8f9e91ad03
These patches were generated from: https://github.com/raspberrypi/linux/commits/rpi-6.12.y With the following command: git format-patch -N v6.12.27..HEAD (HEAD -> 8d3206ee456a5ecdf9ddbfd8e5e231e4f0cd716e) Exceptions: - (def)configs patches - github workflows patches - applied & reverted patches - readme patches - wireless patches Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
48 lines
2.1 KiB
Diff
48 lines
2.1 KiB
Diff
From 00ebe5d1d6be8beb8119a39a440c97f59782c131 Mon Sep 17 00:00:00 2001
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From: Jonathan Bell <jonathan@raspberrypi.com>
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Date: Tue, 7 Jan 2025 12:02:55 +0000
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Subject: [PATCH] PCI: brcmstb: don't use ASPM state defines for register bits
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In commit b478e162f227 ("PCI/ASPM: Consolidate link state defines")
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PCIE_LINK_STATE_L1 and PCIE_LINK_STATE_L0s grew some bits for more
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granular control of ASPM.
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This broke the aspm-no-l0s override, instead disabling link ASPM
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completely if this DT property was specified.
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Specify the field bits in the driver.
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Fixes: caab002d5069 ("PCI: brcmstb: Disable L0s component of ASPM if requested")
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Fixes: 0693b4207fd7 ("PCI: brcmstb: Split post-link up initialization to brcm_pcie_start_link()")
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Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
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---
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drivers/pci/controller/pcie-brcmstb.c | 10 +++++++---
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1 file changed, 7 insertions(+), 3 deletions(-)
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--- a/drivers/pci/controller/pcie-brcmstb.c
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+++ b/drivers/pci/controller/pcie-brcmstb.c
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@@ -47,6 +47,9 @@
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#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc
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#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00
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+#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_L0S 0x1
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+#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_L1 0x2
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+#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_MAX_LINK_SPEED_MASK 0xf
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#define PCIE_RC_CFG_PRIV1_ROOT_CAP 0x4f8
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#define PCIE_RC_CFG_PRIV1_ROOT_CAP_L1SS_MODE_MASK 0xf8
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@@ -1205,10 +1208,11 @@ static int brcm_pcie_setup(struct brcm_p
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pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB;
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- /* Don't advertise L0s capability if 'aspm-no-l0s' */
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- aspm_support = PCIE_LINK_STATE_L1;
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+ /* Always advertise L1 capability */
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+ aspm_support = PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_L1;
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+ /* Advertise L0s capability unless 'aspm-no-l0s' is set */
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if (!of_property_read_bool(pcie->np, "aspm-no-l0s"))
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- aspm_support |= PCIE_LINK_STATE_L0S;
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+ aspm_support |= PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_L0S;
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tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
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u32p_replace_bits(&tmp, aspm_support,
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PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK);
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