8f9e91ad03
These patches were generated from: https://github.com/raspberrypi/linux/commits/rpi-6.12.y With the following command: git format-patch -N v6.12.27..HEAD (HEAD -> 8d3206ee456a5ecdf9ddbfd8e5e231e4f0cd716e) Exceptions: - (def)configs patches - github workflows patches - applied & reverted patches - readme patches - wireless patches Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
72 lines
2.5 KiB
Diff
72 lines
2.5 KiB
Diff
From 23913d7d60576512c818408b0e4bc612d02af1c4 Mon Sep 17 00:00:00 2001
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From: Jim Quinlan <james.quinlan@broadcom.com>
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Date: Fri, 14 Feb 2025 12:39:34 -0500
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Subject: [PATCH] PCI: brcmstb: Use same constant table for config space access
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The constants EXT_CFG_DATA and EXT_CFG_INDEX vary by SOC. One of the
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map_bus methods used these constants, the other used different constants.
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Fortunately there was no problem because the SoCs that used the latter
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map_bus method all had the same register constants.
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Remove the redundant constants and adjust the code to use them. In
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addition, update EXT_CFG_DATA to use the 4k-page based config space access
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system, which is what the second map_bus method was already using.
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Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
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Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
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---
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drivers/pci/controller/pcie-brcmstb.c | 14 ++++++--------
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1 file changed, 6 insertions(+), 8 deletions(-)
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--- a/drivers/pci/controller/pcie-brcmstb.c
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+++ b/drivers/pci/controller/pcie-brcmstb.c
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@@ -150,9 +150,6 @@
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#define MSI_INT_MASK_SET 0x10
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#define MSI_INT_MASK_CLR 0x14
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-#define PCIE_EXT_CFG_DATA 0x8000
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-#define PCIE_EXT_CFG_INDEX 0x9000
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-
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#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
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#define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0
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@@ -727,8 +724,8 @@ static void __iomem *brcm_pcie_map_bus(s
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/* For devices, write to the config space index register */
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idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0);
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- writel(idx, pcie->base + PCIE_EXT_CFG_INDEX);
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- return base + PCIE_EXT_CFG_DATA + PCIE_ECAM_REG(where);
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+ writel(idx, base + IDX_ADDR(pcie));
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+ return base + DATA_ADDR(pcie) + PCIE_ECAM_REG(where);
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}
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static void __iomem *brcm7425_pcie_map_bus(struct pci_bus *bus,
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@@ -1711,7 +1708,7 @@ static void brcm_pcie_remove(struct plat
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static const int pcie_offsets[] = {
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[RGR1_SW_INIT_1] = 0x9210,
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[EXT_CFG_INDEX] = 0x9000,
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- [EXT_CFG_DATA] = 0x9004,
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+ [EXT_CFG_DATA] = 0x8000,
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[PCIE_HARD_DEBUG] = 0x4204,
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[PCIE_INTR2_CPU_BASE] = 0x4300,
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};
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@@ -1719,7 +1716,7 @@ static const int pcie_offsets[] = {
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static const int pcie_offsets_bcm7278[] = {
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[RGR1_SW_INIT_1] = 0xc010,
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[EXT_CFG_INDEX] = 0x9000,
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- [EXT_CFG_DATA] = 0x9004,
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+ [EXT_CFG_DATA] = 0x8000,
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[PCIE_HARD_DEBUG] = 0x4204,
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[PCIE_INTR2_CPU_BASE] = 0x4300,
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};
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@@ -1733,8 +1730,9 @@ static const int pcie_offsets_bcm7425[]
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};
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static const int pcie_offsets_bcm7712[] = {
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+ [RGR1_SW_INIT_1] = 0x9210,
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[EXT_CFG_INDEX] = 0x9000,
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- [EXT_CFG_DATA] = 0x9004,
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+ [EXT_CFG_DATA] = 0x8000,
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[PCIE_HARD_DEBUG] = 0x4304,
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[PCIE_INTR2_CPU_BASE] = 0x4400,
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};
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