8f9e91ad03
These patches were generated from: https://github.com/raspberrypi/linux/commits/rpi-6.12.y With the following command: git format-patch -N v6.12.27..HEAD (HEAD -> 8d3206ee456a5ecdf9ddbfd8e5e231e4f0cd716e) Exceptions: - (def)configs patches - github workflows patches - applied & reverted patches - readme patches - wireless patches Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
90 lines
3.2 KiB
Diff
90 lines
3.2 KiB
Diff
From 4eb0d6f33a7fcc5d5e366ccba09673c7dcfc5e49 Mon Sep 17 00:00:00 2001
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From: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Date: Thu, 13 Feb 2025 11:27:00 +0000
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Subject: [PATCH] drm/vc4: PV1 can be driven via any HVS channel, so adapt to
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allow it
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It was noted that if PV1 was in use to drive DSI1, then the
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writeback connector could not be used as HVS channel 2 was
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already in use.
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The HVS allows PV1 (HVS output 2) to be driven by any HVS
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channel via the DSP3_MUX setting, but that was hardcoded to be
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either 2 (for PV1) or disabled for TXP.
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Expand the available channels field for PV1, and configure
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DSP3_MUX accordingly.
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Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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---
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drivers/gpu/drm/vc4/vc4_crtc.c | 2 +-
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drivers/gpu/drm/vc4/vc4_kms.c | 29 +++++++++++++++--------------
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2 files changed, 16 insertions(+), 15 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_crtc.c
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+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
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@@ -1223,7 +1223,7 @@ const struct vc4_pv_data bcm2835_pv1_dat
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.base = {
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.name = "pixelvalve-1",
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.debugfs_name = "crtc1_regs",
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- .hvs_available_channels = BIT(2),
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+ .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
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.hvs_output = 2,
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},
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.fifo_depth = 64,
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--- a/drivers/gpu/drm/vc4/vc4_kms.c
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+++ b/drivers/gpu/drm/vc4/vc4_kms.c
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@@ -224,12 +224,11 @@ static void vc4_hvs_pv_muxing_commit(str
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struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
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struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
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u32 dispctrl;
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- u32 dsp3_mux_pri;
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if (!crtc_state->active)
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continue;
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- if (vc4_state->assigned_channel != 2)
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+ if (vc4_crtc->data->hvs_output != 2)
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continue;
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/*
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@@ -237,26 +236,28 @@ static void vc4_hvs_pv_muxing_commit(str
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* FIFO X'.
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* SCALER_DISPCTRL_DSP3 = 3 means 'disable DSP 3'.
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*
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- * DSP3 is connected to FIFO2 unless the transposer is
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- * enabled. In this case, FIFO 2 is directly accessed by the
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- * TXP IP, and we need to disable the FIFO2 -> pixelvalve1
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- * route.
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+ * It is more likely that we want the TXP than 3 displays, so
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+ * handle the mapping of DSP3 to any available FIFO.
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*
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* TXP can also run with a lower panic level than a live display,
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* as it doesn't have the same real-time constraint.
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*/
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+ dispctrl = HVS_READ(SCALER_DISPCTRL) &
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+ ~SCALER_DISPCTRL_PANIC2_MASK;
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+
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if (vc4_crtc->feeds_txp) {
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- dsp3_mux_pri = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX);
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- dsp3_mux_pri |= VC4_SET_FIELD(0, SCALER_DISPCTRL_PANIC2);
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+ dispctrl |= VC4_SET_FIELD(0, SCALER_DISPCTRL_PANIC2);
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+ drm_WARN_ON(&vc4->base,
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+ VC4_GET_FIELD(HVS_READ(SCALER_DISPCTRL),
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+ SCALER_DISPCTRL_DSP3_MUX) == 2);
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} else {
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- dsp3_mux_pri = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
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- dsp3_mux_pri |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC2);
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+ dispctrl &= ~SCALER_DISPCTRL_DSP3_MUX_MASK;
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+ dispctrl |= VC4_SET_FIELD(vc4_state->assigned_channel,
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+ SCALER_DISPCTRL_DSP3_MUX);
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+ dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC2);
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}
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- dispctrl = HVS_READ(SCALER_DISPCTRL) &
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- ~(SCALER_DISPCTRL_DSP3_MUX_MASK |
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- SCALER_DISPCTRL_PANIC2_MASK);
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- HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux_pri);
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+ HVS_WRITE(SCALER_DISPCTRL, dispctrl);
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}
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}
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