8f9e91ad03
These patches were generated from: https://github.com/raspberrypi/linux/commits/rpi-6.12.y With the following command: git format-patch -N v6.12.27..HEAD (HEAD -> 8d3206ee456a5ecdf9ddbfd8e5e231e4f0cd716e) Exceptions: - (def)configs patches - github workflows patches - applied & reverted patches - readme patches - wireless patches Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
110 lines
3.7 KiB
Diff
110 lines
3.7 KiB
Diff
From 709ff25f55abbcdd75ba89fce824f929dac3a761 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Ma=C3=ADra=20Canal?= <mcanal@igalia.com>
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Date: Mon, 23 Sep 2024 10:55:12 -0300
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Subject: [PATCH] drm/v3d: Support Big/Super Pages when writing out PTEs
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Commit e4c17720262f394f6320a2b6e17a128bfdabb37c upstream
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The V3D MMU also supports 64KB and 1MB pages, called big and super pages,
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respectively. In order to set a 64KB page or 1MB page in the MMU, we need
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to make sure that page table entries for all 4KB pages within a big/super
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page must be correctly configured.
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In order to create a big/super page, we need a contiguous memory region.
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That's why we use a separate mountpoint with THP enabled. In order to
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place the page table entries in the MMU, we iterate over the 16 4KB pages
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(for big pages) or 256 4KB pages (for super pages) and insert the PTE.
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Signed-off-by: Maíra Canal <mcanal@igalia.com>
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Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
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Link: https://patchwork.freedesktop.org/patch/msgid/20240923141348.2422499-9-mcanal@igalia.com
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---
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drivers/gpu/drm/v3d/v3d_drv.h | 1 +
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drivers/gpu/drm/v3d/v3d_mmu.c | 54 ++++++++++++++++++++++++++---------
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2 files changed, 42 insertions(+), 13 deletions(-)
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--- a/drivers/gpu/drm/v3d/v3d_drv.h
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+++ b/drivers/gpu/drm/v3d/v3d_drv.h
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@@ -20,6 +20,7 @@ struct platform_device;
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struct reset_control;
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#define V3D_MMU_PAGE_SHIFT 12
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+#define V3D_PAGE_FACTOR (PAGE_SIZE >> V3D_MMU_PAGE_SHIFT)
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#define V3D_MAX_QUEUES (V3D_CPU + 1)
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--- a/drivers/gpu/drm/v3d/v3d_mmu.c
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+++ b/drivers/gpu/drm/v3d/v3d_mmu.c
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@@ -25,9 +25,16 @@
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* superpage bit set.
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*/
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#define V3D_PTE_SUPERPAGE BIT(31)
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+#define V3D_PTE_BIGPAGE BIT(30)
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#define V3D_PTE_WRITEABLE BIT(29)
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#define V3D_PTE_VALID BIT(28)
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+static bool v3d_mmu_is_aligned(u32 page, u32 page_address, size_t alignment)
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+{
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+ return IS_ALIGNED(page, alignment >> V3D_MMU_PAGE_SHIFT) &&
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+ IS_ALIGNED(page_address, alignment >> V3D_MMU_PAGE_SHIFT);
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+}
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+
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int v3d_mmu_flush_all(struct v3d_dev *v3d)
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{
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int ret;
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@@ -78,19 +85,40 @@ void v3d_mmu_insert_ptes(struct v3d_bo *
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struct drm_gem_shmem_object *shmem_obj = &bo->base;
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struct v3d_dev *v3d = to_v3d_dev(shmem_obj->base.dev);
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u32 page = bo->node.start;
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- u32 page_prot = V3D_PTE_WRITEABLE | V3D_PTE_VALID;
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- struct sg_dma_page_iter dma_iter;
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+ struct scatterlist *sgl;
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+ unsigned int count;
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+
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+ for_each_sgtable_dma_sg(shmem_obj->sgt, sgl, count) {
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+ dma_addr_t dma_addr = sg_dma_address(sgl);
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+ u32 pfn = dma_addr >> V3D_MMU_PAGE_SHIFT;
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+ unsigned int len = sg_dma_len(sgl);
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+
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+ while (len > 0) {
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+ u32 page_prot = V3D_PTE_WRITEABLE | V3D_PTE_VALID;
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+ u32 page_address = page_prot | pfn;
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+ unsigned int i, page_size;
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+
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+ BUG_ON(pfn + V3D_PAGE_FACTOR >= BIT(24));
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+
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+ if (len >= SZ_1M &&
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+ v3d_mmu_is_aligned(page, page_address, SZ_1M)) {
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+ page_size = SZ_1M;
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+ page_address |= V3D_PTE_SUPERPAGE;
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+ } else if (len >= SZ_64K &&
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+ v3d_mmu_is_aligned(page, page_address, SZ_64K)) {
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+ page_size = SZ_64K;
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+ page_address |= V3D_PTE_BIGPAGE;
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+ } else {
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+ page_size = SZ_4K;
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+ }
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+
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+ for (i = 0; i < page_size >> V3D_MMU_PAGE_SHIFT; i++) {
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+ v3d->pt[page++] = page_address + i;
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+ pfn++;
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+ }
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- for_each_sgtable_dma_page(shmem_obj->sgt, &dma_iter, 0) {
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- dma_addr_t dma_addr = sg_page_iter_dma_address(&dma_iter);
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- u32 page_address = dma_addr >> V3D_MMU_PAGE_SHIFT;
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- u32 pte = page_prot | page_address;
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- u32 i;
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-
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- BUG_ON(page_address + (PAGE_SIZE >> V3D_MMU_PAGE_SHIFT) >=
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- BIT(24));
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- for (i = 0; i < PAGE_SIZE >> V3D_MMU_PAGE_SHIFT; i++)
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- v3d->pt[page++] = pte + i;
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+ len -= page_size;
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+ }
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}
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WARN_ON_ONCE(page - bo->node.start !=
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