332645a610
- Backport upstream Winbond W25N04KV Flash support.
- Backport upstream GigaDevice series Flash support.
- Backport pending Airoha AN8855 switch TPID value fix.
- Backport Mediatek UART baudrate accuracy compensation support.
- Pull mtk patchset from MTK SDK mtksoc-20250711 branch:
Remove mt7622_rfb changes. The MTK SDK already dropped them.
Replace Airoha ethernet PHY driver with new version.
Split downstream snfi changes into independent patches.
Add new Marvell CUX3410 PHY driver.
Add new MediaTek built-in 2.5Gbps PHY driver.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
94 lines
4.6 KiB
Diff
94 lines
4.6 KiB
Diff
From 56d3fcf9efe23f8334741d914f33c9351016d231 Mon Sep 17 00:00:00 2001
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From: Weijie Gao <weijie.gao@mediatek.com>
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Date: Wed, 27 Jul 2022 16:32:17 +0800
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Subject: [PATCH 18/30] mtd: spi-nor: add more flash ids
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Add more spi-nor flash ids
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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---
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drivers/mtd/spi/spi-nor-core.c | 1 +
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drivers/mtd/spi/spi-nor-ids.c | 27 ++++++++++++++++++++++++++-
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2 files changed, 27 insertions(+), 1 deletion(-)
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--- a/drivers/mtd/spi/spi-nor-core.c
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+++ b/drivers/mtd/spi/spi-nor-core.c
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@@ -758,6 +758,7 @@ static int set_4byte(struct spi_nor *nor
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case SNOR_MFR_ISSI:
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case SNOR_MFR_MACRONIX:
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case SNOR_MFR_WINBOND:
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+ case SNOR_MFR_EON:
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if (need_wren)
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write_enable(nor);
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--- a/drivers/mtd/spi/spi-nor-ids.c
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+++ b/drivers/mtd/spi/spi-nor-ids.c
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@@ -83,7 +83,10 @@ const struct flash_info spi_nor_ids[] =
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{ INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, 0) },
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{ INFO("en25q64", 0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
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{ INFO("en25q128b", 0x1c3018, 0, 64 * 1024, 256, 0) },
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- { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, 0) },
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+ { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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+ { INFO("en25qx128a", 0x1c7118, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
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+ { INFO("en25qh256", 0x1c7019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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+ { INFO("en25qx256a", 0x1c7119, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
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{ INFO("en25s64", 0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
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#endif
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#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
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@@ -149,6 +152,11 @@ const struct flash_info spi_nor_ids[] =
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{INFO("gd55x02g", 0xc8481C, 0, 64 * 1024, 4096, SECT_4K |
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SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
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{
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+ INFO("gd25q256", 0xc84019, 0, 64 * 1024, 512,
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+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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+ },
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+ {
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INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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@@ -257,6 +265,7 @@ const struct flash_info spi_nor_ids[] =
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{ INFO("mx25u3235f", 0xc22536, 0, 4 * 1024, 1024, SECT_4K) },
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{ INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) },
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{ INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, SECT_4K) },
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+ { INFO("mx25l12833f", 0xc22018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ INFO("mx25u12835f", 0xc22538, 0, 64 * 1024, 256, SECT_4K) },
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{ INFO("mx25u51245g", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K |
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
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@@ -265,6 +274,7 @@ const struct flash_info spi_nor_ids[] =
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{ INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
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{ INFO("mx25v8035f", 0xc22314, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ INFO("mx25r1635f", 0xc22815, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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+ { INFO("mx25l25645g", 0xc22019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ INFO("mx25l25655e", 0xc22619, 0, 64 * 1024, 512, 0) },
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{ INFO("mx66l51235l", 0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
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{ INFO("mx66u51235f", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
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@@ -525,6 +535,16 @@ const struct flash_info spi_nor_ids[] =
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SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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},
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{
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+ INFO("w25q256jv", 0xef7019, 0, 64 * 1024, 512,
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+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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+ },
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+ {
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+ INFO("w25q512jv", 0xef7020, 0, 64 * 1024, 1024,
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+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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+ },
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+ {
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INFO("w25q128jw", 0xef8018, 0, 64 * 1024, 256,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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@@ -588,6 +608,11 @@ const struct flash_info spi_nor_ids[] =
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SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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},
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{ INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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+ {
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+ INFO("w25q512", 0xef4020, 0, 64 * 1024, 1024,
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+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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+ },
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{ INFO("w25m512jw", 0xef6119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ INFO("w25m512jv", 0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ INFO("w25h02jv", 0xef9022, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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