332645a610
- Backport upstream Winbond W25N04KV Flash support.
- Backport upstream GigaDevice series Flash support.
- Backport pending Airoha AN8855 switch TPID value fix.
- Backport Mediatek UART baudrate accuracy compensation support.
- Pull mtk patchset from MTK SDK mtksoc-20250711 branch:
Remove mt7622_rfb changes. The MTK SDK already dropped them.
Replace Airoha ethernet PHY driver with new version.
Split downstream snfi changes into independent patches.
Add new Marvell CUX3410 PHY driver.
Add new MediaTek built-in 2.5Gbps PHY driver.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
198 lines
4.5 KiB
Diff
198 lines
4.5 KiB
Diff
From 1c5d96f544cfe2140834cc79dc1335b0e6fc5ce5 Mon Sep 17 00:00:00 2001
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From: Weijie Gao <weijie.gao@mediatek.com>
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Date: Mon, 25 Jul 2022 10:53:03 +0800
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Subject: [PATCH 09/30] mtd: mtk-snand: add NMBM support for SPL
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Add NMBM support for mtk-snand SPL loader
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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---
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drivers/mtd/mtk-snand/Makefile | 2 +-
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drivers/mtd/mtk-snand/mtk-snand-spl.c | 133 +++++++++++++++++++++++++-
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2 files changed, 133 insertions(+), 2 deletions(-)
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--- a/drivers/mtd/mtk-snand/Makefile
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+++ b/drivers/mtd/mtk-snand/Makefile
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@@ -8,7 +8,7 @@
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obj-y += mtk-snand.o mtk-snand-ecc.o mtk-snand-ids.o mtk-snand-os.o
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obj-$(CONFIG_MTK_SPI_NAND_MTD) += mtk-snand-mtd.o
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-ifdef CONFIG_SPL_BUILD
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+ifdef CONFIG_XPL_BUILD
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obj-$(CONFIG_SPL_MTK_SPI_NAND) += mtk-snand-spl.o
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endif
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--- a/drivers/mtd/mtk-snand/mtk-snand-spl.c
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+++ b/drivers/mtd/mtk-snand/mtk-snand-spl.c
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@@ -5,7 +5,6 @@
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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-#include <common.h>
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#include <dm.h>
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#include <dm/uclass.h>
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#include <malloc.h>
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@@ -13,12 +12,134 @@
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#include <mtd.h>
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#include <watchdog.h>
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+#include <nmbm/nmbm.h>
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+
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#include "mtk-snand.h"
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static struct mtk_snand *snf;
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static struct mtk_snand_chip_info cinfo;
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static u32 oobavail;
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+#ifdef CONFIG_ENABLE_NAND_NMBM
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+static struct nmbm_instance *ni;
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+
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+static int nmbm_lower_read_page(void *arg, uint64_t addr, void *buf, void *oob,
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+ enum nmbm_oob_mode mode)
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+{
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+ int ret;
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+ bool raw = mode == NMBM_MODE_RAW ? true : false;
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+
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+ if (mode == NMBM_MODE_AUTO_OOB) {
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+ ret = mtk_snand_read_page_auto_oob(snf, addr, buf, oob,
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+ oobavail, NULL, false);
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+ } else {
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+ ret = mtk_snand_read_page(snf, addr, buf, oob, raw);
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+ }
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+
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+ if (ret == -EBADMSG)
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+ return 1;
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+ else if (ret >= 0)
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+ return 0;
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+
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+ return ret;
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+}
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+
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+static int nmbm_lower_write_page(void *arg, uint64_t addr, const void *buf,
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+ const void *oob, enum nmbm_oob_mode mode)
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+{
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+ bool raw = mode == NMBM_MODE_RAW ? true : false;
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+
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+ if (mode == NMBM_MODE_AUTO_OOB) {
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+ return mtk_snand_write_page_auto_oob(snf, addr, buf, oob,
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+ oobavail, NULL, false);
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+ }
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+
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+ return mtk_snand_write_page(snf, addr, buf, oob, raw);
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+}
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+
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+static int nmbm_lower_erase_block(void *arg, uint64_t addr)
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+{
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+ return mtk_snand_erase_block(snf, addr);
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+}
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+
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+static int nmbm_lower_is_bad_block(void *arg, uint64_t addr)
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+{
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+ return mtk_snand_block_isbad(snf, addr);
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+}
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+
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+static int nmbm_lower_mark_bad_block(void *arg, uint64_t addr)
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+{
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+ return mtk_snand_block_markbad(snf, addr);
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+}
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+
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+static void nmbm_lower_log(void *arg, enum nmbm_log_category level,
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+ const char *fmt, va_list ap)
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+{
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+ vprintf(fmt, ap);
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+}
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+
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+static int nmbm_init(void)
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+{
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+ struct nmbm_lower_device nld;
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+ size_t ni_size;
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+ int ret;
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+
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+ memset(&nld, 0, sizeof(nld));
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+
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+ nld.flags = NMBM_F_CREATE;
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+ nld.max_ratio = CONFIG_NMBM_MAX_RATIO;
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+ nld.max_reserved_blocks = CONFIG_NMBM_MAX_BLOCKS;
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+
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+ nld.size = cinfo.chipsize;
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+ nld.erasesize = cinfo.blocksize;
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+ nld.writesize = cinfo.pagesize;
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+ nld.oobsize = cinfo.sparesize;
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+ nld.oobavail = oobavail;
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+
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+ nld.read_page = nmbm_lower_read_page;
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+ nld.write_page = nmbm_lower_write_page;
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+ nld.erase_block = nmbm_lower_erase_block;
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+ nld.is_bad_block = nmbm_lower_is_bad_block;
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+ nld.mark_bad_block = nmbm_lower_mark_bad_block;
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+
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+ nld.logprint = nmbm_lower_log;
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+
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+ ni_size = nmbm_calc_structure_size(&nld);
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+ ni = malloc(ni_size);
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+ if (!ni) {
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+ printf("Failed to allocate memory (0x%u) for NMBM instance\n",
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+ ni_size);
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+ return -ENOMEM;
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+ }
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+
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+ memset(ni, 0, ni_size);
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+
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+ printf("Initializing NMBM ...\n");
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+
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+ ret = nmbm_attach(&nld, ni);
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+ if (ret) {
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+ ni = NULL;
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+ return ret;
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+ }
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+
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+ return 0;
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+}
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+
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+int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
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+{
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+ size_t retlen;
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+
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+ if (!ni)
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+ return -ENODEV;
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+
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+ nmbm_read_range(ni, offs, size, dst, NMBM_MODE_PLACE_OOB, &retlen);
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+ if (retlen != size)
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+ return -EIO;
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+
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+ return 0;
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+}
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+
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+#else
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static u8 *page_cache;
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int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
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@@ -60,6 +181,7 @@ int nand_spl_load_image(uint32_t offs, u
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return ret;
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}
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+#endif
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void nand_init(void)
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{
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@@ -105,11 +227,20 @@ void nand_init(void)
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printf("SPI-NAND: %s (%uMB)\n", cinfo.model,
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(u32)(cinfo.chipsize >> 20));
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+#ifdef CONFIG_ENABLE_NAND_NMBM
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+ nmbm_init();
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+#else
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page_cache = malloc(cinfo.pagesize + cinfo.sparesize);
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if (!page_cache) {
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mtk_snand_cleanup(snf);
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printf("mtk-snand-spl: failed to allocate page cache\n");
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}
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+#endif
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+}
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+
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+unsigned int nand_page_size(void)
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+{
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+ return cinfo.pagesize;
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}
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void nand_deselect(void)
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