difos/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-g10.dts
Christian Marangi 8eab5b2526
ipq806x: enable and setup multi-CPU port for qca8k switch
Enable and setup multi-cpu for qca8k switch for ipq806x based devices.

Rework each DTS to enable the secondary CPU port on QCA8K switch and
apply the required values originally set by the OEM in the old swconfig
node.

In original firmware the first CPU port was always assigned to the WAN
port and the secondary CPU port was assigned to the rest of the LAN
port. Follow this original implementation using an init.d script.

To setup the CPU port ip tools is required. Add additional default
package ip-tiny to correctly setup the CPU port.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2023-09-30 13:51:20 +02:00

378 lines
5.9 KiB
Text

// SPDX-License-Identifier: GPL-2.0
#include "qcom-ipq8064-v2.0-smb208.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
compatible = "asrock,g10", "qcom,ipq8064";
model = "ASRock G10";
aliases {
ethernet0 = &gmac1;
ethernet1 = &gmac0;
led-boot = &led_status_blue;
led-failsafe = &led_status_amber;
led-running = &led_status_blue;
led-upgrade = &led_status_amber;
};
chosen {
bootargs-override = "console=ttyMSM0,115200n8";
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
/*
* this is a bit misleading. Because there are about seven
* multicolor LEDs connected all wired together in parallel.
*/
status_yellow {
label = "yellow:status";
gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
};
led_status_amber: status_amber {
label = "amber:status";
gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
};
led_status_blue: status_blue {
label = "blue:status";
gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
};
/*
* LED is declared in vendors boardfile but it's not
* working and the manual doesn't mention anything
* about the LED being white.
status_white {
label = "white:status";
gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
};
*/
};
i2c-gpio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "i2c-gpio";
gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>, /* sda */
<&qcom_pinmux 54 GPIO_ACTIVE_HIGH>; /* scl */
i2c-gpio,delay-us = <5>;
i2c-gpio,scl-output-only;
mcu@50 {
reg = <0x50>;
compatible = "sonix,sn8f25e21";
};
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
ir-remote {
label = "ir-remote";
gpios = <&qcom_pinmux 15 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
debounce-interval = <60>;
wakeup-source;
};
reset {
label = "reset";
gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
debounce-interval = <60>;
wakeup-source;
};
wps5g {
label = "wps5g";
gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
debounce-interval = <60>;
wakeup-source;
};
wps2g {
label = "wps2g";
gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
debounce-interval = <60>;
wakeup-source;
};
};
};
&adm_dma {
status = "okay";
};
&gmac1 {
status = "okay";
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
phy-mode = "rgmii";
qcom,id = <1>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gmac2 {
status = "okay";
phy-mode = "sgmii";
qcom,id = <2>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gsbi4_serial {
pinctrl-0 = <&uart0_pins>;
pinctrl-names = "default";
};
&mdio0 {
status = "okay";
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
switch@10 {
compatible = "qca,qca8337";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "cpu";
ethernet = <&gmac1>;
phy-mode = "rgmii";
tx-internal-delay-ps = <1000>;
rx-internal-delay-ps = <1000>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@1 {
reg = <1>;
label = "wan";
phy-mode = "internal";
phy-handle = <&phy_port1>;
};
port@2 {
reg = <2>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&phy_port2>;
};
port@3 {
reg = <3>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&phy_port3>;
};
port@4 {
reg = <4>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&phy_port4>;
};
port@5 {
reg = <5>;
label = "lan4";
phy-mode = "internal";
phy-handle = <&phy_port5>;
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac2>;
phy-mode = "sgmii";
qca,sgmii-enable-pll;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy_port1: phy@0 {
reg = <0>;
};
phy_port2: phy@1 {
reg = <1>;
};
phy_port3: phy@2 {
reg = <2>;
};
phy_port4: phy@3 {
reg = <3>;
};
phy_port5: phy@4 {
reg = <4>;
};
};
};
};
&nand {
status = "okay";
nand@0 {
reg = <0>;
compatible = "qcom,nandcs";
nand-ecc-strength = <4>;
nand-bus-width = <8>;
nand-ecc-step-size = <512>;
nand-is-boot-medium;
qcom,boot-partitions = <0x0 0x1200000>;
partitions {
compatible = "qcom,smem-part";
};
};
};
&pcie0 {
status = "okay";
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi5g: wifi@1,0 {
reg = <0x00010000 0 0 0 0>;
compatible = "qcom,ath10k";
qcom,ath10k-calibration-variant = "ASRock-G10";
};
};
};
&pcie1 {
status = "okay";
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi2g: wifi@1,0 {
reg = <0x00010000 0 0 0 0>;
compatible = "qcom,ath10k";
qcom,ath10k-calibration-variant = "ASRock-G10";
};
};
};
&qcom_pinmux {
led_pins: led_pins {
mux {
pins = "gpio7", "gpio8", "gpio9", "gpio26";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
button_pins: button_pins {
mux {
pins = "gpio15", "gpio16", "gpio64", "gpio65";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
uart0_pins: uart0_pins {
mux {
pins = "gpio10", "gpio11";
function = "gsbi4";
drive-strength = <10>;
bias-disable;
};
};
};
&rpm {
pinctrl-0 = <&i2c4_pins>;
pinctrl-names = "default";
};
&hs_phy_0 {
status = "okay";
};
&ss_phy_0 {
status = "okay";
};
&usb3_0 {
status = "okay";
};
&hs_phy_1 {
status = "okay";
};
&ss_phy_1 {
status = "okay";
};
&usb3_1 {
status = "okay";
};
&tcsr {
qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
};
/delete-node/ &pcie2_pins;
/delete-node/ &pcie2;