From patchwork Sun May 11 14:19:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 14084124 From: Frank Wunderlich To: Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Subject: [PATCH v1 07/14] arm64: dts: mediatek: mt7988: add phy calibration efuse subnodes Date: Sun, 11 May 2025 16:19:23 +0200 Message-ID: <20250511141942.10284-8-linux@fw-web.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250511141942.10284-1-linux@fw-web.de> References: <20250511141942.10284-1-linux@fw-web.de> MIME-Version: 1.0 X-Mail-ID: b7327c0d-db13-43b6-8ec5-709b71d19c3b X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Landen Chao , =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , netdev@vger.kernel.org, Sean Wang , Daniel Golle , linux-kernel@vger.kernel.org, DENG Qingfang , linux-mediatek@lists.infradead.org, Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, Felix Fietkau Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: Frank Wunderlich MT7988 contains buildin mt753x switch which needs calibration data from efuse. Signed-off-by: Daniel Golle Signed-off-by: Frank Wunderlich --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -702,6 +702,22 @@ lvts_calibration: calib@918 { reg = <0x918 0x28>; }; + + phy_calibration_p0: calib@940 { + reg = <0x940 0x10>; + }; + + phy_calibration_p1: calib@954 { + reg = <0x954 0x10>; + }; + + phy_calibration_p2: calib@968 { + reg = <0x968 0x10>; + }; + + phy_calibration_p3: calib@97c { + reg = <0x97c 0x10>; + }; }; clock-controller@15000000 {