From 9d79fae257c72b072f52e90e835e98d5cf8befca Mon Sep 17 00:00:00 2001 From: Adam Wilson Date: Mon, 28 Apr 2025 14:06:21 +0100 Subject: [PATCH] Add RS485 mode support for UART2, UART3, UART4, and UART5. --- arch/arm/boot/dts/overlays/README | 52 ++++++++++++++++++++ arch/arm/boot/dts/overlays/uart2-overlay.dts | 12 +++++ arch/arm/boot/dts/overlays/uart3-overlay.dts | 12 +++++ arch/arm/boot/dts/overlays/uart4-overlay.dts | 12 +++++ arch/arm/boot/dts/overlays/uart5-overlay.dts | 12 +++++ 5 files changed, 100 insertions(+) --- a/arch/arm/boot/dts/overlays/README +++ b/arch/arm/boot/dts/overlays/README @@ -5190,6 +5190,19 @@ Name: uart2 Info: Enable uart 2 on GPIOs 0-3. BCM2711 only. Load: dtoverlay=uart2, Params: ctsrts Enable CTS/RTS on GPIOs 2-3 (default off) + rs485 Enable RS485 mode for using the RTS line to + drive the OE pin of an RS485 transceiver (i.e. + MAX3078E); also enables the UARTx ctsrts + parameter, as RTS is required (default off). + rs485_invert_rts When RS485 mode is enabled, inverts the RTS + line from active-high (default) to active-low + (default off). + rs485_rts_on_delay When RS485 mode is enabled, sets the delay (in + milliseconds) between data transmission starting + and the RTS line being asserted (default 0). + rs485_rts_off_delay When RS485 mode is enabled, sets the delay (in + milliseconds) between data transmission ending + and the RTS line being deasserted (default 0). Name: uart2-pi5 @@ -5202,6 +5215,19 @@ Name: uart3 Info: Enable uart 3 on GPIOs 4-7. BCM2711 only. Load: dtoverlay=uart3, Params: ctsrts Enable CTS/RTS on GPIOs 6-7 (default off) + rs485 Enable RS485 mode for using the RTS line to + drive the OE pin of an RS485 transceiver (i.e. + MAX3078E); also enables the UARTx ctsrts + parameter, as RTS is required (default off). + rs485_invert_rts When RS485 mode is enabled, inverts the RTS + line from active-high (default) to active-low + (default off). + rs485_rts_on_delay When RS485 mode is enabled, sets the delay (in + milliseconds) between data transmission starting + and the RTS line being asserted (default 0). + rs485_rts_off_delay When RS485 mode is enabled, sets the delay (in + milliseconds) between data transmission ending + and the RTS line being deasserted (default 0). Name: uart3-pi5 @@ -5214,6 +5240,19 @@ Name: uart4 Info: Enable uart 4 on GPIOs 8-11. BCM2711 only. Load: dtoverlay=uart4, Params: ctsrts Enable CTS/RTS on GPIOs 10-11 (default off) + rs485 Enable RS485 mode for using the RTS line to + drive the OE pin of an RS485 transceiver (i.e. + MAX3078E); also enables the UARTx ctsrts + parameter, as RTS is required (default off). + rs485_invert_rts When RS485 mode is enabled, inverts the RTS + line from active-high (default) to active-low + (default off). + rs485_rts_on_delay When RS485 mode is enabled, sets the delay (in + milliseconds) between data transmission starting + and the RTS line being asserted (default 0). + rs485_rts_off_delay When RS485 mode is enabled, sets the delay (in + milliseconds) between data transmission ending + and the RTS line being deasserted (default 0). Name: uart4-pi5 @@ -5226,6 +5265,19 @@ Name: uart5 Info: Enable uart 5 on GPIOs 12-15. BCM2711 only. Load: dtoverlay=uart5, Params: ctsrts Enable CTS/RTS on GPIOs 14-15 (default off) + rs485 Enable RS485 mode for using the RTS line to + drive the OE pin of an RS485 transceiver (i.e. + MAX3078E); also enables the UARTx ctsrts + parameter, as RTS is required (default off). + rs485_invert_rts When RS485 mode is enabled, inverts the RTS + line from active-high (default) to active-low + (default off). + rs485_rts_on_delay When RS485 mode is enabled, sets the delay (in + milliseconds) between data transmission starting + and the RTS line being asserted (default 0). + rs485_rts_off_delay When RS485 mode is enabled, sets the delay (in + milliseconds) between data transmission ending + and the RTS line being deasserted (default 0). Name: udrc --- a/arch/arm/boot/dts/overlays/uart2-overlay.dts +++ b/arch/arm/boot/dts/overlays/uart2-overlay.dts @@ -19,7 +19,19 @@ }; }; + rs485: fragment@2 { + target = <&uart2>; + __dormant__ { + linux,rs485-enabled-at-boot-time; + rs485-rts-delay = <0 0>; + }; + }; + __overrides__ { ctsrts = <0>,"=1"; + rs485 = <0>,"=1=2"; + rs485_invert_rts = <&rs485>,"rs485-rts-active-low"; + rs485_rts_on_delay = <&rs485>, "rs485-rts-delay:0"; + rs485_rts_off_delay = <&rs485>, "rs485-rts-delay:4"; }; }; --- a/arch/arm/boot/dts/overlays/uart3-overlay.dts +++ b/arch/arm/boot/dts/overlays/uart3-overlay.dts @@ -19,7 +19,19 @@ }; }; + rs485: fragment@2 { + target = <&uart3>; + __dormant__ { + linux,rs485-enabled-at-boot-time; + rs485-rts-delay = <0 0>; + }; + }; + __overrides__ { ctsrts = <0>,"=1"; + rs485 = <0>,"=1=2"; + rs485_invert_rts = <&rs485>,"rs485-rts-active-low"; + rs485_rts_on_delay = <&rs485>, "rs485-rts-delay:0"; + rs485_rts_off_delay = <&rs485>, "rs485-rts-delay:4"; }; }; --- a/arch/arm/boot/dts/overlays/uart4-overlay.dts +++ b/arch/arm/boot/dts/overlays/uart4-overlay.dts @@ -19,7 +19,19 @@ }; }; + rs485: fragment@2 { + target = <&uart4>; + __dormant__ { + linux,rs485-enabled-at-boot-time; + rs485-rts-delay = <0 0>; + }; + }; + __overrides__ { ctsrts = <0>,"=1"; + rs485 = <0>,"=1=2"; + rs485_invert_rts = <&rs485>,"rs485-rts-active-low"; + rs485_rts_on_delay = <&rs485>, "rs485-rts-delay:0"; + rs485_rts_off_delay = <&rs485>, "rs485-rts-delay:4"; }; }; --- a/arch/arm/boot/dts/overlays/uart5-overlay.dts +++ b/arch/arm/boot/dts/overlays/uart5-overlay.dts @@ -19,7 +19,19 @@ }; }; + rs485: fragment@2 { + target = <&uart5>; + __dormant__ { + linux,rs485-enabled-at-boot-time; + rs485-rts-delay = <0 0>; + }; + }; + __overrides__ { ctsrts = <0>,"=1"; + rs485 = <0>,"=1=2"; + rs485_invert_rts = <&rs485>,"rs485-rts-active-low"; + rs485_rts_on_delay = <&rs485>, "rs485-rts-delay:0"; + rs485_rts_off_delay = <&rs485>, "rs485-rts-delay:4"; }; };