From e11c3ae9e077de3fe3d507ae12abb6569be51be4 Mon Sep 17 00:00:00 2001 From: Jonathan Bell Date: Mon, 3 Mar 2025 15:01:28 +0000 Subject: [PATCH] PCI: brcmstb: add NO_SSC quirk for BCM2712 The PHY MDIO register map is different on BCM2712, and as the PHY input clock is 54MHz not 100MHz, enabling refclk SSC is both broken and unfixable. Mask out attempts to enable SSC with a controller quirk. Signed-off-by: Jonathan Bell --- drivers/pci/controller/pcie-brcmstb.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -259,6 +259,12 @@ struct inbound_win { */ #define CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN BIT(0) +/* + * MDIO register map differences and required changes to the defaults mean that refclk + * spread-spectrum clocking isn't supportable. + */ +#define CFG_QUIRK_NO_SSC BIT(1) + struct pcie_cfg_data { const int *offsets; const enum pcie_soc_base soc_base; @@ -1811,7 +1817,7 @@ static const struct pcie_cfg_data bcm271 .perst_set = brcm_pcie_perst_set_7278, .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, .post_setup = brcm_pcie_post_setup_bcm2712, - .quirks = CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN, + .quirks = CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN | CFG_QUIRK_NO_SSC, .num_inbound_wins = 10, }; @@ -1928,7 +1934,8 @@ static int brcm_pcie_probe(struct platfo ret = of_pci_get_max_link_speed(np); pcie->gen = (ret < 0) ? 0 : ret; - pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc"); + pcie->ssc = !(pcie->cfg->quirks & CFG_QUIRK_NO_SSC) && + of_property_read_bool(np, "brcm,enable-ssc"); pcie->rescal = devm_reset_control_get_optional_shared(&pdev->dev, "rescal"); if (IS_ERR(pcie->rescal))