From 198ae80fecb40a9a99c6d301277c794f5e07548b Mon Sep 17 00:00:00 2001 From: Nick Hollinghurst Date: Tue, 11 Feb 2025 13:47:27 +0000 Subject: [PATCH] clk: rp1: Allow audio out to use PLL_AUDIO_SEC; workaround rounding error Connect PLL_AUDIO_SEC to CLK_AUDIO_OUT, which had been commented out to avoid interference with I2S: we expect them never to be enabled at the same time. Work around a rounding error that occurs when the desired rate is exactly the max but not exactly achievable by the PLL. Signed-off-by: Nick Hollinghurst --- drivers/clk/clk-rp1.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) --- a/drivers/clk/clk-rp1.c +++ b/drivers/clk/clk-rp1.c @@ -1326,9 +1326,11 @@ static void rp1_clock_choose_div_and_pra /* * Prevent overclocks - if all parent choices result in * a downstream clock in excess of the maximum, then the - * call to set the clock will fail. + * call to set the clock will fail. But due to round-to- + * nearest in the PLL core (which has 24 fractional bits), + * it's expedient to tolerate a tiny error (1Hz/33MHz). */ - if (tmp > clock->data->max_freq) + if (tmp > clock->data->max_freq + (clock->data->max_freq >> 25)) *calc_rate = 0; else *calc_rate = tmp; @@ -2006,7 +2008,7 @@ static const struct rp1_clk_desc clk_des [RP1_CLK_AUDIO_OUT] = REGISTER_CLK( .name = "clk_audio_out", .parents = {"", //"pll_audio", - "", //"pll_audio_sec", + "pll_audio_sec", "pll_video_sec", "xosc", "clksrc_gp0",