From 1b67413815a83c3839bffcb89689d8e5216299da Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Wed, 31 Jul 2024 10:55:19 +0100 Subject: [PATCH] spi: dw: Clamp the minimum clock speed The DW SPI interface has a 16-bit clock divider, where the bottom bit of the divisor must be 0. Limit how low the clock speed can go to prevent the clock divider from being truncated, as that could lead to a much higher clock rate than requested. Signed-off-by: Phil Elwell --- drivers/spi/spi-dw-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -399,7 +399,7 @@ void dw_spi_update_config(struct dw_spi dw_writel(dws, DW_SPI_CTRLR1, cfg->ndf ? cfg->ndf - 1 : 0); /* Note DW APB SSI clock divider doesn't support odd numbers */ - clk_div = (DIV_ROUND_UP(dws->max_freq, cfg->freq) + 1) & 0xfffe; + clk_div = min(DIV_ROUND_UP(dws->max_freq, cfg->freq) + 1, 0xfffe) & 0xfffe; speed_hz = dws->max_freq / clk_div; if (dws->current_freq != speed_hz) {