The original PCS driver did not use the .pcs_validate() in
phylink_pcs_ops. The patches for 1000/2500base-x and 10g modes were
taken from this old driver, and thus did not bother with
.pcs_validate(). Thus, even though these modes are supported, phylink
would not enable them.
To fix these, list these modes in .pcs_validate(). Also list them in
ipq_pcs_clk_rate_get(). While the latter does not appear to change
behavior, it does change the clock rates listed under
/sys/kernel/debug/clk
Co-developed-by: Mantas Pucka <mantas@8devices.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/18435
Signed-off-by: Robert Marko <robimarko@gmail.com>
The PCS driver in the 6.12 patchset is the v5 submission (see link
below). It solves a number of issues and crashes with teh pcs driver
from the 6.6 patchset. However, this new driver is missing support for
"10gbase-r", "10g-qxgmii", and 1000/2500base-x modes.
Port these modes to the 6.12 patchset. "2500base-x" in particular seems
to be needed to establish a 2.5G link on phy-mode="usxgmii";
Link: https://lore.kernel.org/lkml/20250207-ipq_pcs_6-14_rc1-v5-0-be2ebec32921@quicinc.com/
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/18796
Signed-off-by: Robert Marko <robimarko@gmail.com>
