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qualcommax: ipq50xx: spi-qpic-snand: default to 4-bit ECC

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There are NAND IC-s that define 1-bit ECC as the minimal strength,
however that is unsupported by QPIC-SNAND as it only supports 4 or 8 bit
ECC.

Since most of these chips also support 4-bit ECC just fine, instead of
erroring out if 1-bit ECC is requested lets instead default to 4-bit ECC.

Fixes: 01b72ce61e ("qualcommax: ipq50xx: remove ECC user config from board files")
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/18795
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Robert Marko 2025-05-15 23:15:28 +02:00
parent 91e9a1d221
commit fb90296c32
2 changed files with 92 additions and 0 deletions
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46
target/linux/qualcommax/patches-6.12/0401-spi-spi-qpic-snand-default-to-4-bit-ECC.patch Normal file
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@ -0,0 +1,46 @@
From 2e1ab53e8fcf708db51f560f7846802d406ee57d Mon Sep 17 00:00:00 2001
From: George Moussalem <george.moussalem@outlook.com>
Date: Thu, 15 May 2025 22:47:43 +0200
Subject: [PATCH] spi: spi-qpic-snand: default to 4-bit ECC
There are NAND IC-s that define 1-bit ECC as the minimal strength,
however that is unsupported by QPIC-SNAND as it only supports 4 or 8 bit
ECC.
Since most of these chips also support 4-bit ECC just fine, instead of
erroring out if 1-bit ECC is requested lets instead default to 4-bit ECC.
Fixes: 01b72ce61e8f ("qualcommax: ipq50xx: remove ECC user config from board files")
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
drivers/spi/spi-qpic-snand.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
--- a/drivers/spi/spi-qpic-snand.c
+++ b/drivers/spi/spi-qpic-snand.c
@@ -296,6 +296,24 @@ static int qcom_spi_ecc_init_ctx_pipelin
ecc_cfg->spare_bytes = 2;
break;
+ case 1:
+ case 2:
+ /*
+ * Many chips have set a minimum ECC strength requirement
+ * lower than 4-bits but also support higher strength, so
+ * check if ecc_cfg was set by chip reqs and try 4-bits.
+ */
+ if (reqs->strength) {
+ dev_warn(snandc->dev,
+ "ECC strength requirement of %u-bit(s) is unsupported, trying 4-bits\n",
+ reqs->strength);
+ ecc_cfg->ecc_mode = ECC_MODE_4BIT;
+ ecc_cfg->ecc_bytes_hw = 7;
+ ecc_cfg->spare_bytes = 4;
+ break;
+ } else
+ fallthrough;
+
default:
dev_err(snandc->dev,
"only 4 or 8 bits ECC strength is supported\n");

46
target/linux/qualcommax/patches-6.6/0401-spi-spi-qpic-snand-default-to-4-bit-ECC.patch Normal file
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@ -0,0 +1,46 @@
From 2e1ab53e8fcf708db51f560f7846802d406ee57d Mon Sep 17 00:00:00 2001
From: George Moussalem <george.moussalem@outlook.com>
Date: Thu, 15 May 2025 22:47:43 +0200
Subject: [PATCH] spi: spi-qpic-snand: default to 4-bit ECC
There are NAND IC-s that define 1-bit ECC as the minimal strength,
however that is unsupported by QPIC-SNAND as it only supports 4 or 8 bit
ECC.
Since most of these chips also support 4-bit ECC just fine, instead of
erroring out if 1-bit ECC is requested lets instead default to 4-bit ECC.
Fixes: 01b72ce61e8f ("qualcommax: ipq50xx: remove ECC user config from board files")
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
drivers/spi/spi-qpic-snand.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
--- a/drivers/spi/spi-qpic-snand.c
+++ b/drivers/spi/spi-qpic-snand.c
@@ -296,6 +296,24 @@ static int qcom_spi_ecc_init_ctx_pipelin
ecc_cfg->spare_bytes = 2;
break;
+ case 1:
+ case 2:
+ /*
+ * Many chips have set a minimum ECC strength requirement
+ * lower than 4-bits but also support higher strength, so
+ * check if ecc_cfg was set by chip reqs and try 4-bits.
+ */
+ if (reqs->strength) {
+ dev_warn(snandc->dev,
+ "ECC strength requirement of %u-bit(s) is unsupported, trying 4-bits\n",
+ reqs->strength);
+ ecc_cfg->ecc_mode = ECC_MODE_4BIT;
+ ecc_cfg->ecc_bytes_hw = 7;
+ ecc_cfg->spare_bytes = 4;
+ break;
+ } else
+ fallthrough;
+
default:
dev_err(snandc->dev,
"only 4 or 8 bits ECC strength is supported\n");