From f9206d1111361506379375dc3f72a3d432569c83 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sat, 17 May 2025 13:59:59 +0100 Subject: [PATCH] kernel/mediatek: 6.12: replace downstream files by patches Replace downstream files by patches, either backports of those which have already applied or pending patches tracked on patchwork. This is done to make future maintainance more easy. Signed-off-by: Daniel Golle --- .../arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 822 --------- .../mt7988a-bananapi-bpi-r4-emmc.dtso | 63 - .../mediatek/mt7988a-bananapi-bpi-r4-poe.dts | 26 - .../mediatek/mt7988a-bananapi-bpi-r4-rtc.dtso | 19 - .../mediatek/mt7988a-bananapi-bpi-r4-sd.dtso | 61 - .../mt7988a-bananapi-bpi-r4-wifi-mt7996a.dtso | 112 -- .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 41 - .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 598 ------ .../boot/dts/mediatek/mt7988a-rfb-emmc.dtso | 33 - .../dts/mediatek/mt7988a-rfb-eth1-aqr.dtso | 42 - .../mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso | 30 - .../dts/mediatek/mt7988a-rfb-eth1-mxl.dtso | 39 - .../dts/mediatek/mt7988a-rfb-eth1-sfp.dtso | 47 - .../dts/mediatek/mt7988a-rfb-eth2-aqr.dtso | 42 - .../dts/mediatek/mt7988a-rfb-eth2-mxl.dtso | 39 - .../dts/mediatek/mt7988a-rfb-eth2-sfp.dtso | 47 - .../boot/dts/mediatek/mt7988a-rfb-sd.dtso | 31 - .../dts/mediatek/mt7988a-rfb-snfi-nand.dtso | 71 - .../mt7988a-rfb-spim-nand-factory.dtso | 87 - .../dts/mediatek/mt7988a-rfb-spim-nand.dtso | 77 - .../dts/mediatek/mt7988a-rfb-spim-nor.dtso | 61 - .../arm64/boot/dts/mediatek/mt7988a-rfb.dts | 352 ---- .../arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 1392 -------------- .../drivers/pinctrl/mediatek/pinctrl-mt7988.c | 1548 ---------------- ...tek-add-support-for-MTK_PULL_PD_TYPE.patch | 151 ++ ...l-mediatek-add-MT7988-pinctrl-driver.patch | 1610 +++++++++++++++++ ...ediatek-Drop-mtk_pinconf_bias_set_pd.patch | 41 + ...mediatek-mt7988-add-UART-controllers.patch | 71 + ...-dts-mediatek-mt7988-add-efuse-block.patch | 35 + ...-mediatek-mt7988-Add-pinctrl-support.patch | 85 + ...-mediatek-mt7988-Add-reserved-memory.patch | 37 + ...-dts-mediatek-mt7988-Add-mmc-support.patch | 52 + ...64-dts-mediatek-mt7988-Add-lvts-node.patch | 62 + ...dts-mediatek-mt7988-Add-thermal-zone.patch | 39 + ...atek-mt7988-Add-mcu-sys-node-for-cpu.patch | 31 + ...ek-mt7988-Add-CPU-OPP-table-for-cloc.patch | 84 + ...ek-mt7988-Disable-usb-controllers-by.patch | 34 + ...mediatek-mt7988-Add-t-phy-for-ssusb1.patch | 59 + ...4-dts-mediatek-mt7988-Add-pcie-nodes.patch | 176 ++ ...ek-mt7988a-bpi-r4-Add-pinctrl-subnod.patch | 211 +++ ...iatek-mt7988a-bpi-r4-Enable-watchdog.patch | 25 + ...ek-mt7988a-bpi-r4-Add-fixed-regulato.patch | 48 + ...ek-mt7988a-bpi-r4-Add-thermal-config.patch | 54 + ...ek-mt7988a-bpi-r4-Enable-serial0-deb.patch | 41 + ...ek-mt7988a-bpi-r4-Add-default-UART-s.patch | 29 + ...ek-mt7988a-bpi-r4-Enable-I2C-control.patch | 72 + ...ek-mt7988a-bpi-r4-Add-PCA9545-I2C-Mu.patch | 74 + ...ek-mt7988a-bpi-r4-Enable-t-phy-for-s.patch | 41 + ...ek-mt7988a-bpi-r4-Enable-ssusb1-on-b.patch | 41 + ...s-mediatek-mt7988a-bpi-r4-Enable-pwm.patch | 40 + ...-mediatek-mt7988a-bpi-r4-Enable-pcie.patch | 83 + ...ek-mt7988a-bpi-r4-Add-MediaTek-MT668.patch | 96 + ...ek-mt7988a-bpi-r4-Add-proc-supply-fo.patch | 80 + ...sphy-support-type-switch-by-pericfg.patch} | 20 +- ...13-mmc-mtk-sd-add-support-for-mt7988.patch | 28 + .../117-complete-mt7981b-dtsi.patch | 702 +++++++ ...ek-mt7988a-bpi-r4-allow-hw-variants-.patch | 876 +++++++++ ...k-mt7988a-Add-xsphy-for-ssusb0-pcie2.patch | 74 + ...mediatek-mt7988a-bpi-r4-enable-xsphy.patch | 35 + ...-built-in-ethernet-phy-firmware-node.patch | 27 + ...-mediatek-mt7988-add-spi-controllers.patch | 112 ++ ...move-uart0-and-spi1-pins-to-soc-dtsi.patch | 133 ++ ...m64-dts-mediatek-mt7988-add-cci-node.patch | 128 ++ ...8-add-phy-calibration-efuse-subnodes.patch | 85 + ...atek-mt7988-add-basic-ethernet-nodes.patch | 213 +++ ...-dts-mediatek-mt7988-add-switch-node.patch | 228 +++ ...7988a-bpi-r4-Add-fan-and-coolingmaps.patch | 98 + ...k-mt7988a-bpi-r4-configure-spi-nodes.patch | 99 + ...7988a-bpi-r4-add-proc-supply-for-cci.patch | 68 + ...pi-r4-add-sfp-cages-and-link-to-gmac.patch | 138 ++ ...pi-r4-configure-switch-phys-and-leds.patch | 113 ++ ...988a-add-serial1-and-serial2-aliases.patch | 33 + ...ek-add-MT7988A-reference-board-devic.patch | 1430 +++++++++++++++ ...dts-mediatek-mt7988a-complete-bpi-r4.patch | 487 +++++ 74 files changed, 8620 insertions(+), 5689 deletions(-) delete mode 100644 target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981b.dtsi delete mode 100644 target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso delete mode 100644 target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-poe.dts delete mode 100644 target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-rtc.dtso delete mode 100644 target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso delete mode 100644 target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-wifi-mt7996a.dtso delete mode 100644 target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts delete mode 100644 target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi delete mode 100644 target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso delete mode 100644 target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso delete mode 100644 target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso delete mode 100644 target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso delete mode 100644 target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso delete mode 100644 target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso delete mode 100644 target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso delete mode 100644 target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso delete mode 100644 target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso delete mode 100644 target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso delete mode 100644 target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand-factory.dtso delete mode 100644 target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso delete mode 100644 target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nor.dtso delete mode 100644 target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts delete mode 100644 target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a.dtsi delete mode 100644 target/linux/mediatek/files-6.12/drivers/pinctrl/mediatek/pinctrl-mt7988.c create mode 100644 target/linux/mediatek/patches-6.12/010-v6.14-pinctrl-mediatek-add-support-for-MTK_PULL_PD_TYPE.patch create mode 100644 target/linux/mediatek/patches-6.12/011-v6.14-pinctrl-mediatek-add-MT7988-pinctrl-driver.patch create mode 100644 target/linux/mediatek/patches-6.12/012-v6.14-pinctrl-mediatek-Drop-mtk_pinconf_bias_set_pd.patch create mode 100644 target/linux/mediatek/patches-6.12/020-v6.13-arm64-dts-mediatek-mt7988-add-UART-controllers.patch create mode 100644 target/linux/mediatek/patches-6.12/021-v6.13-arm64-dts-mediatek-mt7988-add-efuse-block.patch create mode 100644 target/linux/mediatek/patches-6.12/022-v6.14-arm64-dts-mediatek-mt7988-Add-pinctrl-support.patch create mode 100644 target/linux/mediatek/patches-6.12/023-v6.14-arm64-dts-mediatek-mt7988-Add-reserved-memory.patch create mode 100644 target/linux/mediatek/patches-6.12/024-v6.14-arm64-dts-mediatek-mt7988-Add-mmc-support.patch create mode 100644 target/linux/mediatek/patches-6.12/025-v6.14-arm64-dts-mediatek-mt7988-Add-lvts-node.patch create mode 100644 target/linux/mediatek/patches-6.12/026-v6.14-arm64-dts-mediatek-mt7988-Add-thermal-zone.patch create mode 100644 target/linux/mediatek/patches-6.12/027-v6.14-arm64-dts-mediatek-mt7988-Add-mcu-sys-node-for-cpu.patch create mode 100644 target/linux/mediatek/patches-6.12/028-v6.14-arm64-dts-mediatek-mt7988-Add-CPU-OPP-table-for-cloc.patch create mode 100644 target/linux/mediatek/patches-6.12/029-v6.14-arm64-dts-mediatek-mt7988-Disable-usb-controllers-by.patch create mode 100644 target/linux/mediatek/patches-6.12/030-v6.14-arm64-dts-mediatek-mt7988-Add-t-phy-for-ssusb1.patch create mode 100644 target/linux/mediatek/patches-6.12/031-v6.14-arm64-dts-mediatek-mt7988-Add-pcie-nodes.patch create mode 100644 target/linux/mediatek/patches-6.12/032-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-pinctrl-subnod.patch create mode 100644 target/linux/mediatek/patches-6.12/033-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-watchdog.patch create mode 100644 target/linux/mediatek/patches-6.12/034-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fixed-regulato.patch create mode 100644 target/linux/mediatek/patches-6.12/035-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-thermal-config.patch create mode 100644 target/linux/mediatek/patches-6.12/036-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-serial0-deb.patch create mode 100644 target/linux/mediatek/patches-6.12/037-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-default-UART-s.patch create mode 100644 target/linux/mediatek/patches-6.12/038-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-I2C-control.patch create mode 100644 target/linux/mediatek/patches-6.12/039-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-PCA9545-I2C-Mu.patch create mode 100644 target/linux/mediatek/patches-6.12/040-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-t-phy-for-s.patch create mode 100644 target/linux/mediatek/patches-6.12/041-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-ssusb1-on-b.patch create mode 100644 target/linux/mediatek/patches-6.12/042-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-pwm.patch create mode 100644 target/linux/mediatek/patches-6.12/043-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-pcie.patch create mode 100644 target/linux/mediatek/patches-6.12/044-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-MediaTek-MT668.patch create mode 100644 target/linux/mediatek/patches-6.12/045-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-proc-supply-fo.patch rename target/linux/mediatek/patches-6.12/{615-phy-phy-mtk-xsphy-support-type-switch-by-pericfg.patch => 050-v6.16-phy-mediatek-xsphy-support-type-switch-by-pericfg.patch} (87%) create mode 100644 target/linux/mediatek/patches-6.12/060-v6.13-mmc-mtk-sd-add-support-for-mt7988.patch create mode 100644 target/linux/mediatek/patches-6.12/117-complete-mt7981b-dtsi.patch create mode 100644 target/linux/mediatek/patches-6.12/170-arm64-dts-mediatek-mt7988a-bpi-r4-allow-hw-variants-.patch create mode 100644 target/linux/mediatek/patches-6.12/171-arm64-dts-mediatek-mt7988a-Add-xsphy-for-ssusb0-pcie2.patch create mode 100644 target/linux/mediatek/patches-6.12/172-arm64-dts-mediatek-mt7988a-bpi-r4-enable-xsphy.patch create mode 100644 target/linux/mediatek/patches-6.12/173-dts-mt7988a-Add-built-in-ethernet-phy-firmware-node.patch create mode 100644 target/linux/mediatek/patches-6.12/174-arm64-dts-mediatek-mt7988-add-spi-controllers.patch create mode 100644 target/linux/mediatek/patches-6.12/175-arm64-dts-mediatek-mt7988-move-uart0-and-spi1-pins-to-soc-dtsi.patch create mode 100644 target/linux/mediatek/patches-6.12/176-arm64-dts-mediatek-mt7988-add-cci-node.patch create mode 100644 target/linux/mediatek/patches-6.12/177-arm64-dts-mediatek-mt7988-add-phy-calibration-efuse-subnodes.patch create mode 100644 target/linux/mediatek/patches-6.12/178-arm64-dts-mediatek-mt7988-add-basic-ethernet-nodes.patch create mode 100644 target/linux/mediatek/patches-6.12/179-arm64-dts-mediatek-mt7988-add-switch-node.patch create mode 100644 target/linux/mediatek/patches-6.12/180-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fan-and-coolingmaps.patch create mode 100644 target/linux/mediatek/patches-6.12/181-arm64-dts-mediatek-mt7988a-bpi-r4-configure-spi-nodes.patch create mode 100644 target/linux/mediatek/patches-6.12/182-arm64-dts-mediatek-mt7988a-bpi-r4-add-proc-supply-for-cci.patch create mode 100644 target/linux/mediatek/patches-6.12/183-arm64-dts-mediatek-mt7988a-bpi-r4-add-sfp-cages-and-link-to-gmac.patch create mode 100644 target/linux/mediatek/patches-6.12/184-arm64-dts-mediatek-mt7988a-bpi-r4-configure-switch-phys-and-leds.patch create mode 100644 target/linux/mediatek/patches-6.12/187-arm64-dts-mt7988a-add-serial1-and-serial2-aliases.patch create mode 100644 target/linux/mediatek/patches-6.12/188-arm64-dts-mediatek-add-MT7988A-reference-board-devic.patch create mode 100644 target/linux/mediatek/patches-6.12/189-arm64-dts-mediatek-mt7988a-complete-bpi-r4.patch diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981b.dtsi deleted file mode 100644 index 012c6e4e5b3..00000000000 --- a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ /dev/null @@ -1,822 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (c) 2020 MediaTek Inc. - * Author: Sam.Shih - * Author: Jianhui Zhao - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "mediatek,mt7981"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a53"; - reg = <0x0>; - device_type = "cpu"; - enable-method = "psci"; - }; - - cpu@1 { - compatible = "arm,cortex-a53"; - reg = <0x1>; - device_type = "cpu"; - enable-method = "psci"; - }; - }; - - ice: ice_debug { - compatible = "mediatek,mt7981-ice_debug", "mediatek,mt2701-ice_debug"; - clocks = <&infracfg CLK_INFRA_DBG_CK>; - clock-names = "ice_dbg"; - }; - - clk40m: oscillator-40m { - compatible = "fixed-clock"; - clock-frequency = <40000000>; - clock-output-names = "clkxtal"; - #clock-cells = <0>; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - /* cooling level (0, 1, 2, 3, 4, 5, 6, 7) : (0%/25%/37.5%/50%/62.5%/75%/87.5%/100% duty) */ - cooling-levels = <0 63 95 127 159 191 223 255>; - #cooling-cells = <2>; - status = "disabled"; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reserved-memory { - ranges; - #address-cells = <2>; - #size-cells = <2>; - - /* 64 KiB reserved for ramoops/pstore */ - ramoops@42ff0000 { - compatible = "ramoops"; - reg = <0 0x42ff0000 0 0x10000>; - record-size = <0x1000>; - }; - - /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@43000000 { - reg = <0 0x43000000 0 0x30000>; - no-map; - }; - - wmcpu_emi: wmcpu-reserved@47c80000 { - reg = <0 0x47c80000 0 0x100000>; - no-map; - }; - - wo_emi0: wo-emi@47d80000 { - reg = <0 0x47d80000 0 0x40000>; - no-map; - }; - - wo_data: wo-data@47dc0000 { - reg = <0 0x47dc0000 0 0x240000>; - no-map; - }; - }; - - soc { - compatible = "simple-bus"; - ranges; - #address-cells = <2>; - #size-cells = <2>; - - gic: interrupt-controller@c000000 { - compatible = "arm,gic-v3"; - reg = <0 0x0c000000 0 0x40000>, /* GICD */ - <0 0x0c080000 0 0x200000>; /* GICR */ - interrupt-parent = <&gic>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - }; - - consys: consys@10000000 { - compatible = "mediatek,mt7981-consys"; - reg = <0 0x10000000 0 0x8600000>; - memory-region = <&wmcpu_emi>; - }; - - infracfg: clock-controller@10001000 { - compatible = "mediatek,mt7981-infracfg", "syscon"; - reg = <0 0x10001000 0 0x1000>; - #clock-cells = <1>; - }; - - wed_pcie: wed_pcie@10003000 { - compatible = "mediatek,wed_pcie"; - reg = <0 0x10003000 0 0x10>; - }; - - topckgen: clock-controller@1001b000 { - compatible = "mediatek,mt7981-topckgen", "syscon"; - reg = <0 0x1001b000 0 0x1000>; - #clock-cells = <1>; - }; - - watchdog: watchdog@1001c000 { - compatible = "mediatek,mt7986-wdt", - "mediatek,mt6589-wdt"; - reg = <0 0x1001c000 0 0x1000>; - interrupts = ; - #reset-cells = <1>; - status = "disabled"; - }; - - apmixedsys: clock-controller@1001e000 { - compatible = "mediatek,mt7981-apmixedsys", "syscon"; - reg = <0 0x1001e000 0 0x1000>; - #clock-cells = <1>; - }; - - pwm: pwm@10048000 { - compatible = "mediatek,mt7981-pwm"; - reg = <0 0x10048000 0 0x1000>; - clocks = <&infracfg CLK_INFRA_PWM_STA>, - <&infracfg CLK_INFRA_PWM_HCK>, - <&infracfg CLK_INFRA_PWM1_CK>, - <&infracfg CLK_INFRA_PWM2_CK>, - <&infracfg CLK_INFRA_PWM3_CK>; - clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; - #pwm-cells = <2>; - }; - - sgmiisys0: syscon@10060000 { - compatible = "mediatek,mt7981-sgmiisys_0", "syscon"; - reg = <0 0x10060000 0 0x1000>; - mediatek,pnswap; - #clock-cells = <1>; - }; - - sgmiisys1: syscon@10070000 { - compatible = "mediatek,mt7981-sgmiisys_1", "syscon"; - reg = <0 0x10070000 0 0x1000>; - #clock-cells = <1>; - }; - - crypto: crypto@10320000 { - compatible = "inside-secure,safexcel-eip97"; - reg = <0 0x10320000 0 0x40000>; - interrupts = , - , - , - ; - interrupt-names = "ring0", "ring1", "ring2", "ring3"; - clocks = <&topckgen CLK_TOP_EIP97B>; - clock-names = "top_eip97_ck"; - assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt6577-uart"; - reg = <0 0x11002000 0 0x400>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_UART0_SEL>, - <&infracfg CLK_INFRA_UART0_CK>; - clock-names = "baud", "bus"; - assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_UART0_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>, - <&topckgen CLK_TOP_UART_SEL>; - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt6577-uart"; - reg = <0 0x11003000 0 0x400>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_UART1_SEL>, - <&infracfg CLK_INFRA_UART1_CK>; - clock-names = "baud", "bus"; - assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_UART1_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>, - <&topckgen CLK_TOP_UART_SEL>; - status = "disabled"; - }; - - uart2: serial@11004000 { - compatible = "mediatek,mt6577-uart"; - reg = <0 0x11004000 0 0x400>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_UART2_SEL>, - <&infracfg CLK_INFRA_UART2_CK>; - clock-names = "baud", "bus"; - assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_UART2_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>, - <&topckgen CLK_TOP_UART_SEL>; - status = "disabled"; - }; - - snand: snfi@11005000 { - compatible = "mediatek,mt7986-snand"; - reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>; - reg-names = "nfi", "ecc"; - interrupts = ; - clocks = <&infracfg CLK_INFRA_SPINFI1_CK>, - <&infracfg CLK_INFRA_NFI1_CK>, - <&infracfg CLK_INFRA_NFI_HCK_CK>; - clock-names = "pad_clk", "nfi_clk", "nfi_hclk"; - assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>, - <&topckgen CLK_TOP_NFI1X_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>, - <&topckgen CLK_TOP_CB_M_D8>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c0: i2c@11007000 { - compatible = "mediatek,mt7981-i2c"; - reg = <0 0x11007000 0 0x1000>, - <0 0x10217080 0 0x80>; - interrupts = ; - clock-div = <1>; - clocks = <&infracfg CLK_INFRA_I2C0_CK>, - <&infracfg CLK_INFRA_AP_DMA_CK>, - <&infracfg CLK_INFRA_I2C_MCK_CK>, - <&infracfg CLK_INFRA_I2C_PCK_CK>; - clock-names = "main", "dma", "arb", "pmic"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@11009000 { - compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; - reg = <0 0x11009000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_CB_M_D2>, - <&topckgen CLK_TOP_SPI_SEL>, - <&infracfg CLK_INFRA_SPI2_CK>, - <&infracfg CLK_INFRA_SPI2_HCK_CK>; - clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@1100a000 { - compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; - reg = <0 0x1100a000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_CB_M_D2>, - <&topckgen CLK_TOP_SPI_SEL>, - <&infracfg CLK_INFRA_SPI0_CK>, - <&infracfg CLK_INFRA_SPI0_HCK_CK>; - clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@1100b000 { - compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; - reg = <0 0x1100b000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_CB_M_D2>, - <&topckgen CLK_TOP_SPIM_MST_SEL>, - <&infracfg CLK_INFRA_SPI1_CK>, - <&infracfg CLK_INFRA_SPI1_HCK_CK>; - clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - thermal: thermal@1100c800 { - compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal"; - reg = <0 0x1100c800 0 0x800>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_THERM_CK>, - <&infracfg CLK_INFRA_ADC_26M_CK>; - clock-names = "therm", "auxadc"; - nvmem-cells = <&thermal_calibration>; - nvmem-cell-names = "calibration-data"; - #thermal-sensor-cells = <1>; - mediatek,auxadc = <&auxadc>; - mediatek,apmixedsys = <&apmixedsys>; - }; - - auxadc: adc@1100d000 { - compatible = "mediatek,mt7981-auxadc", - "mediatek,mt7986-auxadc", - "mediatek,mt7622-auxadc"; - reg = <0 0x1100d000 0 0x1000>; - clocks = <&infracfg CLK_INFRA_ADC_26M_CK>, - <&infracfg CLK_INFRA_ADC_FRC_CK>; - clock-names = "main", "32k"; - #io-channel-cells = <1>; - }; - - xhci: usb@11200000 { - compatible = "mediatek,mt7986-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x11200000 0 0x2e00>, - <0 0x11203e00 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>, - <&infracfg CLK_INFRA_IUSB_CK>, - <&infracfg CLK_INFRA_IUSB_133_CK>, - <&infracfg CLK_INFRA_IUSB_66M_CK>, - <&topckgen CLK_TOP_U2U3_XHCI_SEL>; - clock-names = "sys_ck", - "ref_ck", - "mcu_ck", - "dma_ck", - "xhci_ck"; - phys = <&u2port0 PHY_TYPE_USB2>, - <&u3port0 PHY_TYPE_USB3>; - vusb33-supply = <®_3p3v>; - status = "disabled"; - }; - - afe: audio-controller@11210000 { - compatible = "mediatek,mt79xx-audio"; - reg = <0 0x11210000 0 0x9000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>, - <&infracfg CLK_INFRA_AUD_26M_CK>, - <&infracfg CLK_INFRA_AUD_L_CK>, - <&infracfg CLK_INFRA_AUD_AUD_CK>, - <&infracfg CLK_INFRA_AUD_EG2_CK>, - <&topckgen CLK_TOP_AUD_SEL>; - clock-names = "aud_bus_ck", - "aud_26m_ck", - "aud_l_ck", - "aud_aud_ck", - "aud_eg2_ck", - "aud_sel"; - assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>, - <&topckgen CLK_TOP_A1SYS_SEL>, - <&topckgen CLK_TOP_AUD_L_SEL>, - <&topckgen CLK_TOP_A_TUNER_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>, - <&topckgen CLK_TOP_APLL2_D4>, - <&topckgen CLK_TOP_CB_APLL2_196M>, - <&topckgen CLK_TOP_APLL2_D4>; - status = "disabled"; - }; - - mmc0: mmc@11230000 { - compatible = "mediatek,mt7986-mmc", "mediatek,mt7981-mmc"; - reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_MSDC_CK>, - <&infracfg CLK_INFRA_MSDC_HCK_CK>, - <&infracfg CLK_INFRA_MSDC_66M_CK>, - <&infracfg CLK_INFRA_MSDC_133M_CK>; - assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>, - <&topckgen CLK_TOP_EMMC_400M_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>, - <&topckgen CLK_TOP_CB_NET2_D2>; - clock-names = "source", "hclk", "axi_cg", "ahb_cg"; - status = "disabled"; - }; - - pcie: pcie@11280000 { - compatible = "mediatek,mt7981-pcie", - "mediatek,mt8192-pcie"; - reg = <0 0x11280000 0 0x4000>; - reg-names = "pcie-mac"; - ranges = <0x82000000 0 0x20000000 - 0x0 0x20000000 0 0x10000000>; - device_type = "pci"; - interrupts = ; - bus-range = <0x00 0xff>; - clocks = <&infracfg CLK_INFRA_IPCIE_CK>, - <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, - <&infracfg CLK_INFRA_IPCIER_CK>, - <&infracfg CLK_INFRA_IPCIEB_CK>; - phys = <&u3port0 PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc 0>, - <0 0 0 2 &pcie_intc 1>, - <0 0 0 3 &pcie_intc 2>, - <0 0 0 4 &pcie_intc 3>; - #interrupt-cells = <1>; - #address-cells = <3>; - #size-cells = <2>; - status = "disabled"; - - pcie_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <0>; - }; - }; - - pio: pinctrl@11d00000 { - compatible = "mediatek,mt7981-pinctrl"; - reg = <0 0x11d00000 0 0x1000>, - <0 0x11c00000 0 0x1000>, - <0 0x11c10000 0 0x1000>, - <0 0x11d20000 0 0x1000>, - <0 0x11e00000 0 0x1000>, - <0 0x11e20000 0 0x1000>, - <0 0x11f00000 0 0x1000>, - <0 0x11f10000 0 0x1000>, - <0 0x1000b000 0 0x1000>; - reg-names = "gpio", "iocfg_rt", "iocfg_rm", - "iocfg_rb", "iocfg_lb", "iocfg_bl", - "iocfg_tm", "iocfg_tl", "eint"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pio 0 0 56>; - interrupt-controller; - interrupts = ; - interrupt-parent = <&gic>; - #interrupt-cells = <2>; - - mdio_pins: mdc-mdio-pins { - mux { - function = "eth"; - groups = "smi_mdc_mdio"; - }; - }; - - uart0_pins: uart0-pins { - mux { - function = "uart"; - groups = "uart0"; - }; - }; - - wifi_dbdc_pins: wifi-dbdc-pins { - mux { - function = "eth"; - groups = "wf0_mode1"; - }; - - conf { - pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4", - "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6", - "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10", - "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ", - "WF_CBA_RESETB", "WF_DIG_RESETB"; - drive-strength = <4>; - }; - }; - - gbe_led0_pins: gbe-led0-pins { - mux { - function = "led"; - groups = "gbe_led0"; - }; - }; - - gbe_led1_pins: gbe-led1-pins { - mux { - function = "led"; - groups = "gbe_led1"; - }; - }; - }; - - topmisc: topmisc@11d10000 { - compatible = "mediatek,mt7981-topmisc", "syscon"; - reg = <0 0x11d10000 0 0x10000>; - #clock-cells = <1>; - }; - - usb_phy: usb-phy@11e10000 { - compatible = "mediatek,mt7981", - "mediatek,generic-tphy-v2"; - ranges = <0 0 0x11e10000 0x1700>; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - - u2port0: usb-phy@0 { - reg = <0x0 0x700>; - clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>; - clock-names = "ref"; - #phy-cells = <1>; - }; - - u3port0: usb-phy@700 { - reg = <0x700 0x900>; - clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>; - clock-names = "ref"; - #phy-cells = <1>; - mediatek,syscon-type = <&topmisc 0x218 0>; - status = "okay"; - }; - }; - - efuse: efuse@11f20000 { - compatible = "mediatek,mt7981-efuse", - "mediatek,efuse"; - reg = <0 0x11f20000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - status = "okay"; - - thermal_calibration: thermal-calib@274 { - reg = <0x274 0xc>; - }; - - phy_calibration: phy-calib@8dc { - reg = <0x8dc 0x10>; - }; - - comb_rx_imp_p0: usb3-rx-imp@8c8 { - reg = <0x8c8 1>; - bits = <0 5>; - }; - - comb_tx_imp_p0: usb3-tx-imp@8c8 { - reg = <0x8c8 2>; - bits = <5 5>; - }; - - comb_intr_p0: usb3-intr@8c9 { - reg = <0x8c9 1>; - bits = <2 6>; - }; - }; - - ethsys: clock-controller@15000000 { - compatible = "mediatek,mt7981-ethsys", - "syscon"; - reg = <0 0x15000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - }; - - wed: wed@15010000 { - compatible = "mediatek,mt7981-wed", - "mediatek,mt7986-wed", - "syscon"; - reg = <0 0x15010000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - memory-region = <&wo_emi0>, <&wo_data>; - memory-region-names = "wo-emi", "wo-data"; - mediatek,wo-ccif = <&wo_ccif0>; - mediatek,wo-ilm = <&wo_ilm0>; - mediatek,wo-dlm = <&wo_dlm0>; - mediatek,wo-cpuboot = <&wo_cpuboot>; - }; - - eth: ethernet@15100000 { - compatible = "mediatek,mt7981-eth"; - reg = <0 0x15100000 0 0x80000>; - interrupts = , - , - , - ; - clocks = <ðsys CLK_ETH_FE_EN>, - <ðsys CLK_ETH_GP2_EN>, - <ðsys CLK_ETH_GP1_EN>, - <ðsys CLK_ETH_WOCPU0_EN>, - <&sgmiisys0 CLK_SGM0_TX_EN>, - <&sgmiisys0 CLK_SGM0_RX_EN>, - <&sgmiisys0 CLK_SGM0_CK0_EN>, - <&sgmiisys0 CLK_SGM0_CDR_CK0_EN>, - <&sgmiisys1 CLK_SGM1_TX_EN>, - <&sgmiisys1 CLK_SGM1_RX_EN>, - <&sgmiisys1 CLK_SGM1_CK1_EN>, - <&sgmiisys1 CLK_SGM1_CDR_CK1_EN>, - <&topckgen CLK_TOP_SGM_REG>, - <&topckgen CLK_TOP_NETSYS_SEL>, - <&topckgen CLK_TOP_NETSYS_500M_SEL>; - clock-names = "fe", "gp2", "gp1", "wocpu0", - "sgmii_tx250m", "sgmii_rx250m", - "sgmii_cdr_ref", "sgmii_cdr_fb", - "sgmii2_tx250m", "sgmii2_rx250m", - "sgmii2_cdr_ref", "sgmii2_cdr_fb", - "sgmii_ck", "netsys0", "netsys1"; - assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, - <&topckgen CLK_TOP_SGM_325M_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>, - <&topckgen CLK_TOP_CB_SGM_325M>; - mediatek,ethsys = <ðsys>; - mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; - mediatek,infracfg = <&topmisc>; - mediatek,wed = <&wed>; - #reset-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - mdio_bus: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - int_gbe_phy: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - phy-mode = "gmii"; - phy-is-integrated; - nvmem-cells = <&phy_calibration>; - nvmem-cell-names = "phy-cal-data"; - - leds { - #address-cells = <1>; - #size-cells = <0>; - - int_gbe_phy_led0: int-gbe-phy-led0@0 { - reg = <0>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - - int_gbe_phy_led1: int-gbe-phy-led1@1 { - reg = <1>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - }; - }; - }; - }; - - wdma: wdma@15104800 { - compatible = "mediatek,wed-wdma"; - reg = <0 0x15104800 0 0x400>, - <0 0x15104c00 0 0x400>; - }; - - wo_cpuboot: syscon@15194000 { - compatible = "mediatek,mt7986-wo-cpuboot", "syscon"; - reg = <0 0x15194000 0 0x1000>; - }; - - ap2woccif: ap2woccif@151a5000 { - compatible = "mediatek,ap2woccif"; - reg = <0 0x151a5000 0 0x1000>, - <0 0x151ad000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = , - ; - }; - - wo_ccif0: syscon@151a5000 { - compatible = "mediatek,mt7986-wo-ccif", "syscon"; - reg = <0 0x151a5000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - }; - - wo_ilm0: syscon@151e0000 { - compatible = "mediatek,mt7986-wo-ilm", "syscon"; - reg = <0 0x151e0000 0 0x8000>; - }; - - wo_dlm0: syscon@151e8000 { - compatible = "mediatek,mt7986-wo-dlm", "syscon"; - reg = <0 0x151e8000 0 0x2000>; - }; - - wifi: wifi@18000000 { - compatible = "mediatek,mt7981-wmac"; - reg = <0 0x18000000 0 0x1000000>, - <0 0x10003000 0 0x1000>, - <0 0x11d10000 0 0x1000>; - resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; - reset-names = "consys"; - pinctrl-0 = <&wifi_dbdc_pins>; - pinctrl-names = "dbdc"; - clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>, - <&topckgen CLK_TOP_AP2CNN_HOST_SEL>; - clock-names = "mcu", "ap2conn"; - interrupts = , - , - , - ; - memory-region = <&wmcpu_emi>; - status = "disabled"; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <1000>; - thermal-sensors = <&thermal 0>; - - trips { - cpu_trip_active_highest: active-highest { - temperature = <70000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_active_high: active-high { - temperature = <60000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_active_med: active-med { - temperature = <50000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_active_low: active-low { - temperature = <45000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_active_lowest: active-lowest { - temperature = <40000>; - hysteresis = <2000>; - type = "active"; - }; - }; - - cooling-maps { - cpu-active-highest { - /* active: set fan to cooling level 7 */ - cooling-device = <&fan 7 7>; - trip = <&cpu_trip_active_highest>; - }; - - cpu-active-high { - /* active: set fan to cooling level 5 */ - cooling-device = <&fan 5 5>; - trip = <&cpu_trip_active_high>; - }; - - cpu-active-med { - /* active: set fan to cooling level 3 */ - cooling-device = <&fan 3 3>; - trip = <&cpu_trip_active_med>; - }; - - cpu-active-low { - /* active: set fan to cooling level 2 */ - cooling-device = <&fan 2 2>; - trip = <&cpu_trip_active_low>; - }; - - cpu-active-lowest { - /* active: set fan to cooling level 1 */ - cooling-device = <&fan 1 1>; - trip = <&cpu_trip_active_lowest>; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - clock-frequency = <13000000>; - interrupts = , - , - , - ; - - }; - - trng { - compatible = "mediatek,mt7981-rng"; - }; -}; diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso deleted file mode 100644 index 12c94e4da8d..00000000000 --- a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2021 MediaTek Inc. - * Author: Frank Wunderlich - */ - -/dts-v1/; -/plugin/; - -/ { - compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; - - fragment@0 { - target-path = "/soc/mmc@11230000"; - __overlay__ { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_emmc_51>; - pinctrl-1 = <&mmc0_pins_emmc_51>; - bus-width = <8>; - max-frequency = <200000000>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - hs400-ds-delay = <0x12814>; - vqmmc-supply = <®_1p8v>; - vmmc-supply = <®_3p3v>; - non-removable; - no-sd; - no-sdio; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - card@0 { - compatible = "mmc-card"; - reg = <0>; - - block { - compatible = "block-device"; - partitions { - block-partition-env { - partname = "ubootenv"; - - nvmem-layout { - compatible = "u-boot,env"; - }; - }; - emmc_rootfs: block-partition-production { - partname = "production"; - }; - }; - }; - }; - }; - }; - - fragment@2 { - target-path = "/chosen"; - __overlay__ { - rootdisk-emmc = <&emmc_rootfs>; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-poe.dts b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-poe.dts deleted file mode 100644 index 910f60d11b2..00000000000 --- a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-poe.dts +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -#include "mt7988a-bananapi-bpi-r4.dtsi" - -/ { - model = "Bananapi BPI-R4 2.5GE PoE"; - compatible = "bananapi,bpi-r4-poe", - "mediatek,mt7988a"; -}; - -&gmac1 { - phy-mode = "internal"; - phy-connection-type = "internal"; - phy = <&int_2p5g_phy>; - status = "okay"; - openwrt,netdev-name = "lan4"; -}; - -&int_2p5g_phy { - pinctrl-names = "i2p5gbe-led"; - pinctrl-0 = <&i2p5gbe_led0_pins>; -}; diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-rtc.dtso b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-rtc.dtso deleted file mode 100644 index 39910b8cfee..00000000000 --- a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-rtc.dtso +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2023 - * Author: Daniel Golle - */ - -/dts-v1/; -/plugin/; - -/ { - compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; - - fragment@0 { - target = <&pcf8563>; - __overlay__ { - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso deleted file mode 100644 index 52075ab34ad..00000000000 --- a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso +++ /dev/null @@ -1,61 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2023 MediaTek Inc. - * Author: Frank Wunderlich - */ - -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; - - fragment@1 { - target-path = "/soc/mmc@11230000"; - __overlay__ { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_sdcard>; - pinctrl-1 = <&mmc0_pins_sdcard>; - cd-gpios = <&pio 12 GPIO_ACTIVE_LOW>; - bus-width = <4>; - max-frequency = <52000000>; - cap-sd-highspeed; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; - no-mmc; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - card@0 { - compatible = "mmc-card"; - reg = <0>; - - block { - compatible = "block-device"; - partitions { - block-partition-env { - partname = "ubootenv"; - - nvmem-layout { - compatible = "u-boot,env"; - }; - }; - sd_rootfs: block-partition-production { - partname = "production"; - }; - }; - }; - }; - }; - }; - - fragment@2 { - target-path = "/chosen"; - __overlay__ { - rootdisk-sd = <&sd_rootfs>; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-wifi-mt7996a.dtso b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-wifi-mt7996a.dtso deleted file mode 100644 index d2338adefb4..00000000000 --- a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-wifi-mt7996a.dtso +++ /dev/null @@ -1,112 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; - - fragment@0 { - target-path = "/"; - __overlay__ { - wifi_12v: regulator-wifi-12v { - compatible = "regulator-fixed"; - regulator-name = "wifi"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - gpios = <&pio 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - }; - }; - - fragment@1 { - target = <&i2c_wifi>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - - // 5G WIFI MAC Address EEPROM - wifi_eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - address-bits = <8>; - page-size = <8>; - size = <256>; - - nvmem-layout { - compatible = "fixed-layout"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_5g: macaddr@0 { - reg = <0x0 0x6>; - }; - }; - }; - - // 6G WIFI MAC Address EEPROM - wifi_eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - address-bits = <8>; - page-size = <8>; - size = <256>; - - nvmem-layout { - compatible = "fixed-layout"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_6g: macaddr@0 { - reg = <0x0 0x6>; - }; - }; - }; - }; - }; - - fragment@2 { - target = <&pcie0>; - __overlay__ { - #address-cells = <3>; - #size-cells = <2>; - - pcie@0,0 { - #address-cells = <3>; - #size-cells = <2>; - reg = <0x0000 0 0 0 0>; - - wifi@0,0 { - compatible = "mediatek,mt76"; - reg = <0x0000 0 0 0 0>; - nvmem-cell-names = "mac-address"; - nvmem-cells = <&macaddr_5g>; - }; - }; - }; - }; - - fragment@3 { - target = <&pcie1>; - __overlay__ { - #address-cells = <3>; - #size-cells = <2>; - - pcie@0,0 { - #address-cells = <3>; - #size-cells = <2>; - reg = <0x0000 0 0 0 0>; - - wifi@0,0 { - compatible = "mediatek,mt76"; - reg = <0x0000 0 0 0 0>; - nvmem-cell-names = "mac-address"; - nvmem-cells = <&macaddr_6g>; - }; - }; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts deleted file mode 100644 index 0f8b6e3d03f..00000000000 --- a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -#include "mt7988a-bananapi-bpi-r4.dtsi" - -/ { - model = "Bananapi BPI-R4"; - compatible = "bananapi,bpi-r4", - "mediatek,mt7988a"; - - /* SFP2 cage (LAN) */ - sfp2: sfp2 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp2>; - los-gpios = <&pio 2 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&pio 83 GPIO_ACTIVE_LOW>; - tx-disable-gpios = <&pio 0 GPIO_ACTIVE_HIGH>; - tx-fault-gpios = <&pio 1 GPIO_ACTIVE_HIGH>; - rate-select0-gpios = <&pio 3 GPIO_ACTIVE_LOW>; - maximum-power-milliwatt = <3000>; - }; -}; - -&gmac1 { - sfp = <&sfp2>; - managed = "in-band-status"; - phy-mode = "usxgmii"; - status = "okay"; - openwrt,netdev-name = "sfp-lan"; -}; - -&pca9545 { - i2c_sfp2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; -}; diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi deleted file mode 100644 index a1ff582961a..00000000000 --- a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi +++ /dev/null @@ -1,598 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -#include "mt7988a.dtsi" -#include -#include -#include -#include - -/ { - model = "Bananapi BPI-R4"; - compatible = "bananapi,bpi-r4", - "mediatek,mt7988a"; - - aliases { - ethernet0 = &gmac0; - ethernet1 = &gmac1; - led-boot = &led_green; - led-failsafe = &led_green; - led-running = &led_green; - led-upgrade = &led_green; - serial0 = &serial0; - }; - - chosen { - stdout-path = &serial0; - bootargs = "console=ttyS0,115200n1 loglevel=8 pci=pcie_bus_perf ubi.block=0,fit root=/dev/fit0 rootwait"; - rootdisk-spim-nand = <&ubi_rootfs>; - }; - - memory { - reg = <0x00 0x40000000 0x00 0x10000000>; - }; - - /* SFP1 cage (WAN) */ - sfp1: sfp1 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp1>; - los-gpios = <&pio 54 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>; - tx-disable-gpios = <&pio 70 GPIO_ACTIVE_HIGH>; - tx-fault-gpios = <&pio 69 GPIO_ACTIVE_HIGH>; - rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>; - maximum-power-milliwatt = <3000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - wps { - label = "WPS"; - linux,code = ; - gpios = <&pio 14 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - led_green: led-green { - function = LED_FUNCTION_STATUS; - color = ; - gpios = <&pio 79 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - led_blue: led-blue { - function = LED_FUNCTION_WPS; - color = ; - gpios = <&pio 63 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -ð { - status = "okay"; -}; - -&gmac0 { - status = "okay"; -}; - -&gmac2 { - sfp = <&sfp1>; - managed = "in-band-status"; - phy-mode = "usxgmii"; - status = "okay"; - openwrt,netdev-name = "sfp-wan"; -}; - -&switch { - status = "okay"; -}; - -&gsw_phy0 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe0_led0_pins>; -}; - -&gsw_port0 { - label = "wan"; -}; - -&gsw_phy0_led0 { - status = "okay"; - function = LED_FUNCTION_WAN; - color = ; -}; - -&gsw_phy1 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe1_led0_pins>; -}; - -&gsw_port1 { - label = "lan1"; -}; - -&gsw_phy1_led0 { - status = "okay"; - function = LED_FUNCTION_LAN; - color = ; -}; - -&gsw_phy2 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe2_led0_pins>; -}; - -&gsw_port2 { - label = "lan2"; -}; - -&gsw_phy2_led0 { - status = "okay"; - function = LED_FUNCTION_LAN; - color = ; -}; - -&gsw_phy3 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe3_led0_pins>; -}; - -&gsw_port3 { - label = "lan3"; -}; - -&gsw_phy3_led0 { - status = "okay"; - function = LED_FUNCTION_LAN; - color = ; -}; - -&cpu0 { - proc-supply = <&rt5190_buck3>; -}; - -&cpu1 { - proc-supply = <&rt5190_buck3>; -}; - -&cpu2 { - proc-supply = <&rt5190_buck3>; -}; - -&cpu3 { - proc-supply = <&rt5190_buck3>; -}; - -&cci { - proc-supply = <&rt5190_buck3>; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - - rt5190a_64: rt5190a@64 { - compatible = "richtek,rt5190a"; - reg = <0x64>; - vin2-supply = <&rt5190_buck1>; - vin3-supply = <&rt5190_buck1>; - vin4-supply = <&rt5190_buck1>; - - regulators { - rt5190_buck1: buck1 { - regulator-name = "rt5190a-buck1"; - regulator-min-microvolt = <5090000>; - regulator-max-microvolt = <5090000>; - regulator-allowed-modes = - ; - regulator-boot-on; - regulator-always-on; - }; - buck2 { - regulator-name = "vcore"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - rt5190_buck3: buck3 { - regulator-name = "vproc"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - }; - buck4 { - regulator-name = "rt5190a-buck4"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-allowed-modes = - ; - regulator-boot-on; - regulator-always-on; - }; - ldo { - regulator-name = "rt5190a-ldo"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_1_pins>; - status = "okay"; - - pca9545: i2c-switch@70 { - reg = <0x70>; - compatible = "nxp,pca9545"; - reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>; - #address-cells = <1>; - #size-cells = <0>; - - i2c_rtc: i2c@0 { //eeprom,rtc,ngff - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - address-bits = <8>; - page-size = <8>; - size = <256>; - }; - - eeprom@57 { - compatible = "atmel,24c02"; - reg = <0x57>; - address-bits = <8>; - page-size = <8>; - size = <256>; - }; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - status = "disabled"; - }; - }; - - i2c_sfp1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - i2c_wifi: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; -}; - -/* mPCIe SIM2 */ -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_pins>; - status = "okay"; -}; - -/* mPCIe SIM3 */ -&pcie1 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie1_pins>; - status = "okay"; -}; - -/* M.2 key-B SIM1 */ -&pcie2 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_pins>; - status = "okay"; -}; - -/* M.2 key-M SSD */ -&pcie3 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie3_pins>; - status = "okay"; -}; - -&pio { - mdio0_pins: mdio0-pins { - mux { - function = "eth"; - groups = "mdc_mdio0"; - }; - - conf { - groups = "mdc_mdio0"; - drive-strength = ; - }; - }; - - i2c0_pins: i2c0-pins-g0 { - mux { - function = "i2c"; - groups = "i2c0_1"; - }; - }; - - i2c2_1_pins: i2c2-pins-g1 { - mux { - function = "i2c"; - groups = "i2c2_1"; - }; - }; - - gbe0_led0_pins: gbe0-led0-pins { - mux { - function = "led"; - groups = "gbe0_led0"; - }; - }; - - gbe1_led0_pins: gbe1-led0-pins { - mux { - function = "led"; - groups = "gbe1_led0"; - }; - }; - - gbe2_led0_pins: gbe2-led0-pins { - mux { - function = "led"; - groups = "gbe2_led0"; - }; - }; - - gbe3_led0_pins: gbe3-led0-pins { - mux { - function = "led"; - groups = "gbe3_led0"; - }; - }; - - i2p5gbe_led0_pins: 2p5gbe-led0-pins { - mux { - function = "led"; - groups = "2p5gbe_led0"; - }; - }; - - mmc0_pins_emmc_51: mmc0-pins-emmc-51 { - mux { - function = "flash"; - groups = "emmc_51"; - }; - }; - - mmc0_pins_sdcard: mmc0-pins-sdcard { - mux { - function = "flash"; - groups = "sdcard"; - }; - }; - - pwm0_pins: pwm0-pins { - mux { - groups = "pwm0"; - function = "pwm"; - }; - }; - - uart0_pins: uart0-pins { - mux { - function = "uart"; - groups = "uart0"; - }; - }; - - uart1_2_lite_pins: uart1-2-lite-pins { - mux { - function = "uart"; - groups = "uart1_2_lite"; - }; - }; - - uart2_3_pins: uart2-3-pins { - mux { - function = "uart"; - groups = "uart2_3"; - }; - }; - - spi0_flash_pins: spi0-flash-pins { - mux { - function = "spi"; - groups = "spi0", "spi0_wp_hold"; - }; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins>; - pwms = <&pwm 0 50000>; - /* cooling level (0, 1, 2, 3) : (0% duty, 30% duty, 50% duty, 100% duty) */ - cooling-levels = <0 80 128 255>; - #cooling-cells = <2>; - #thermal-sensor-cells = <1>; - - status = "okay"; - }; -}; - -&pwm { - status = "okay"; -}; - -&cpu_thermal { - trips { - cpu_trip_hot: hot { - temperature = <120000>; - hysteresis = <2000>; - type = "hot"; - }; - - cpu_trip_active_high: active-high { - temperature = <115000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_active_med: active-med { - temperature = <85000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_active_low: active-low { - temperature = <40000>; - hysteresis = <2000>; - type = "active"; - }; - }; - - cooling-maps { - cpu-active-high { - /* active: set fan to cooling level 2 */ - cooling-device = <&fan 3 3>; - trip = <&cpu_trip_active_high>; - }; - - cpu-active-low { - /* active: set fan to cooling level 1 */ - cooling-device = <&fan 2 2>; - trip = <&cpu_trip_active_med>; - }; - - cpu-passive { - /* passive: set fan to cooling level 0 */ - cooling-device = <&fan 1 1>; - trip = <&cpu_trip_active_low>; - }; - }; -}; - -&ssusb1 { - status = "okay"; -}; - -&tphy { - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_flash_pins>; - status = "okay"; - - spi_nand: spi_nand@0 { - compatible = "spi-nand"; - reg = <0>; - spi-max-frequency = <52000000>; - spi-tx-buswidth = <4>; - spi-rx-buswidth = <4>; - }; -}; - -&spi_nand { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bl2"; - reg = <0x0 0x200000>; - read-only; - }; - - partition@200000 { - label = "ubi"; - reg = <0x200000 0x7e00000>; - compatible = "linux,ubi"; - - volumes { - ubi-volume-ubootenv { - volname = "ubootenv"; - nvmem-layout { - compatible = "u-boot,env-redundant-bool"; - }; - }; - - ubi-volume-ubootenv2 { - volname = "ubootenv2"; - nvmem-layout { - compatible = "u-boot,env-redundant-bool"; - }; - }; - - ubi_rootfs: ubi-volume-fit { - volname = "fit"; - }; - }; - }; - }; -}; - -&serial0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&serial1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_2_lite_pins>; -}; - -&serial2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_3_pins>; -}; - -&watchdog { - status = "okay"; -}; - -&xsphy { - status = "okay"; -}; diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso deleted file mode 100644 index 3f8ac2ae382..00000000000 --- a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2021 MediaTek Inc. - * Author: Frank Wunderlich - */ - -/dts-v1/; -/plugin/; - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&mmc0>; - __overlay__ { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_emmc_51>; - pinctrl-1 = <&mmc0_pins_emmc_51>; - bus-width = <8>; - max-frequency = <200000000>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - hs400-ds-delay = <0x12814>; - vqmmc-supply = <®_1p8v>; - vmmc-supply = <®_3p3v>; - non-removable; - no-sd; - no-sdio; - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso deleted file mode 100644 index c471b9ed91d..00000000000 --- a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&mdio_bus>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - - /* external Aquantia AQR113C */ - phy0: ethernet-phy@0 { - reg = <0>; - compatible = "ethernet-phy-ieee802.3-c45"; - firmware-name = "AQR-G4_v5.7.0-AQR_EVB_Generic_X3410_StdCfg_MDISwap_USX_ID46316_VER2140.cld"; - reset-gpios = <&pio 72 GPIO_ACTIVE_LOW>; - reset-assert-us = <100000>; - reset-deassert-us = <221000>; - }; - }; - }; - - fragment@1 { - target = <&gmac1>; - __overlay__ { - phy-mode = "usxgmii"; - phy-connection-type = "usxgmii"; - phy = <&phy0>; - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso deleted file mode 100644 index 86ab7566dc2..00000000000 --- a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&gmac1>; - __overlay__ { - phy-mode = "internal"; - phy-connection-type = "internal"; - phy = <&int_2p5g_phy>; - status = "okay"; - }; - }; - - fragment@1 { - target = <&int_2p5g_phy>; - __overlay__ { - pinctrl-names = "i2p5gbe-led"; - pinctrl-0 = <&i2p5gbe_led0_pins>; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso deleted file mode 100644 index 34a23bbd7eb..00000000000 --- a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&mdio_bus>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - - /* external Maxlinear GPY211C */ - phy13: ethernet-phy@13 { - reg = <13>; - compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "2500base-x"; - }; - }; - }; - - fragment@1 { - target = <&gmac1>; - __overlay__ { - phy-mode = "2500base-x"; - phy-connection-type = "2500base-x"; - phy = <&phy13>; - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso deleted file mode 100644 index ba40a119cbd..00000000000 --- a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&i2c2>; - __overlay__ { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_0_pins>; - status = "okay"; - }; - }; - - fragment@1 { - target-path = "/"; - __overlay__ { - sfp_esp1: sfp@1 { - compatible = "sff,sfp"; - i2c-bus = <&i2c2>; - mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>; - los-gpios = <&pio 81 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&pio 36 GPIO_ACTIVE_HIGH>; - maximum-power-milliwatt = <3000>; - }; - }; - }; - - fragment@2 { - target = <&gmac1>; - __overlay__ { - phy-mode = "10gbase-r"; - managed = "in-band-status"; - sfp = <&sfp_esp1>; - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso deleted file mode 100644 index 1490f055b59..00000000000 --- a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&mdio_bus>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - - /* external Aquantia AQR113C */ - phy8: ethernet-phy@8 { - reg = <8>; - compatible = "ethernet-phy-ieee802.3-c45"; - firmware-name = "AQR-G4_v5.7.0-AQR_EVB_Generic_X3410_StdCfg_MDISwap_USX_ID46316_VER2140.cld"; - reset-gpios = <&pio 71 GPIO_ACTIVE_LOW>; - reset-assert-us = <100000>; - reset-deassert-us = <221000>; - }; - }; - }; - - fragment@1 { - target = <&gmac2>; - __overlay__ { - phy-mode = "usxgmii"; - phy-connection-type = "usxgmii"; - phy = <&phy8>; - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso deleted file mode 100644 index 19e0b2799fc..00000000000 --- a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&mdio_bus>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - - /* external Maxlinear GPY211C */ - phy5: ethernet-phy@5 { - reg = <5>; - compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "2500base-x"; - }; - }; - }; - - fragment@1 { - target = <&gmac2>; - __overlay__ { - phy-mode = "2500base-x"; - phy-connection-type = "2500base-x"; - phy = <&phy5>; - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso deleted file mode 100644 index b9aabd2726e..00000000000 --- a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&i2c1>; - __overlay__ { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_sfp_pins>; - status = "okay"; - }; - }; - - fragment@1 { - target-path = "/"; - __overlay__ { - sfp_esp0: sfp@0 { - compatible = "sff,sfp"; - i2c-bus = <&i2c1>; - mod-def0-gpios = <&pio 35 GPIO_ACTIVE_LOW>; - los-gpios = <&pio 33 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&pio 29 GPIO_ACTIVE_HIGH>; - maximum-power-milliwatt = <3000>; - }; - }; - }; - - fragment@2 { - target = <&gmac2>; - __overlay__ { - phy-mode = "10gbase-r"; - managed = "in-band-status"; - sfp = <&sfp_esp0>; - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso deleted file mode 100644 index 04472cc12dc..00000000000 --- a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2023 MediaTek Inc. - * Author: Frank Wunderlich - */ - -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@1 { - target-path = <&mmc0>; - __overlay__ { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_sdcard>; - pinctrl-1 = <&mmc0_pins_sdcard>; - cd-gpios = <&pio 69 GPIO_ACTIVE_LOW>; - bus-width = <4>; - max-frequency = <52000000>; - cap-sd-highspeed; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; - no-mmc; - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso deleted file mode 100644 index 428f9c2e92c..00000000000 --- a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&snand>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - flash@0 { - compatible = "spi-nand"; - reg = <0>; - spi-max-frequency = <52000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - mediatek,nmbm; - mediatek,bmt-max-ratio = <1>; - mediatek,bmt-max-reserved-blocks = <64>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "BL2"; - reg = <0x00000 0x0100000>; - read-only; - }; - - partition@100000 { - label = "u-boot-env"; - reg = <0x0100000 0x0080000>; - }; - - partition@180000 { - label = "Factory"; - reg = <0x180000 0x0400000>; - }; - - partition@580000 { - label = "FIP"; - reg = <0x580000 0x0200000>; - }; - - partition@780000 { - label = "ubi"; - reg = <0x780000 0x7080000>; - }; - }; - }; - }; - }; - - fragment@1 { - target = <&bch>; - __overlay__ { - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand-factory.dtso b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand-factory.dtso deleted file mode 100644 index a94d1659d58..00000000000 --- a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand-factory.dtso +++ /dev/null @@ -1,87 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) - -/dts-v1/; -/plugin/; - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&ubi_part>; - - __overlay__ { - volumes { - ubi_factory: ubi-volume-factory { - volname = "factory"; - - nvmem-layout { - compatible = "fixed-layout"; - #address-cells = <1>; - #size-cells = <1>; - - eeprom_wmac: eeprom@0 { - reg = <0x0 0x1e00>; - }; - - gmac2_mac: eeprom@fffee { - reg = <0xfffee 0x6>; - }; - - gmac1_mac: eeprom@ffff4 { - reg = <0xffff4 0x6>; - }; - - gmac0_mac: eeprom@ffffa { - reg = <0xffffa 0x6>; - }; - }; - }; - }; - }; - }; - - fragment@1 { - target = <&pcie0>; - __overlay__ { - #address-cells = <3>; - #size-cells = <2>; - - pcie@0,0 { - #address-cells = <3>; - #size-cells = <2>; - reg = <0x0000 0 0 0 0>; - - wifi@0,0 { - compatible = "mediatek,mt76"; - reg = <0x0000 0 0 0 0>; - nvmem-cell-names = "eeprom"; - nvmem-cells = <&eeprom_wmac>; - }; - }; - }; - }; - - fragment@2 { - target = <&gmac0>; - __overlay__ { - nvmem-cell-names = "mac-address"; - nvmem-cells = <&gmac0_mac>; - }; - }; - - fragment@3 { - target = <&gmac1>; - __overlay__ { - nvmem-cell-names = "mac-address"; - nvmem-cells = <&gmac1_mac>; - }; - }; - - fragment@4 { - target = <&gmac2>; - __overlay__ { - nvmem-cell-names = "mac-address"; - nvmem-cells = <&gmac2_mac>; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso deleted file mode 100644 index ba083b63176..00000000000 --- a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso +++ /dev/null @@ -1,77 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&spi0>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_flash_pins>; - status = "okay"; - - flash@0 { - compatible = "spi-nand"; - reg = <0>; - spi-max-frequency = <52000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "BL2"; - reg = <0x00000 0x0200000>; - read-only; - }; - - ubi_part: partition@200000 { - label = "ubi"; - reg = <0x0200000 0x7e00000>; - compatible = "linux,ubi"; - - volumes { - ubi-volume-ubootenv { - volname = "ubootenv"; - nvmem-layout { - compatible = "u-boot,env-redundant-bool"; - }; - }; - - ubi-volume-ubootenv2 { - volname = "ubootenv2"; - nvmem-layout { - compatible = "u-boot,env-redundant-bool"; - }; - }; - - ubi_root: ubi-volume-fit { - volname = "fit"; - }; - - }; - }; - }; - }; - }; - }; - - fragment@1 { - target-path = "/chosen"; - __overlay__ { - rootdisk-spim-nand = <&ubi_root>; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nor.dtso b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nor.dtso deleted file mode 100644 index 702502b52e4..00000000000 --- a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nor.dtso +++ /dev/null @@ -1,61 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&spi2>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_flash_pins>; - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-cal-enable; - spi-cal-mode = "read-data"; - spi-cal-datalen = <7>; - spi-cal-data = /bits/ 8 < - 0x53 0x46 0x5F 0x42 0x4F 0x4F 0x54>; /* SF_BOOT */ - spi-cal-addrlen = <1>; - spi-cal-addr = /bits/ 32 <0x0>; - reg = <0>; - spi-max-frequency = <52000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - - partition@0 { - label = "BL2"; - reg = <0x00000 0x0040000>; - }; - partition@40000 { - label = "u-boot-env"; - reg = <0x40000 0x0010000>; - }; - partition@50000 { - label = "Factory"; - reg = <0x50000 0x0200000>; - }; - partition@250000 { - label = "FIP"; - reg = <0x250000 0x0080000>; - }; - partition@2D0000 { - label = "firmware"; - reg = <0x2D0000 0x1D30000>; - }; - }; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts deleted file mode 100644 index a2a45f801c4..00000000000 --- a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts +++ /dev/null @@ -1,352 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -#include "mt7988a.dtsi" -#include -#include -#include - -/ { - model = "MediaTek MT7988A Reference Board"; - compatible = "mediatek,mt7988a-rfb", - "mediatek,mt7988a"; - - chosen { - bootargs = "console=ttyS0,115200n1 loglevel=8 \ - earlycon=uart8250,mmio32,0x11000000 \ - pci=pcie_bus_perf"; - }; - - memory { - reg = <0 0x40000000 0 0x40000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&pio { - mdio0_pins: mdio0-pins { - mux { - function = "eth"; - groups = "mdc_mdio0"; - }; - - conf { - groups = "mdc_mdio0"; - drive-strength = ; - }; - }; - - gbe0_led0_pins: gbe0-led0-pins { - mux { - function = "led"; - groups = "gbe0_led0"; - }; - }; - - gbe1_led0_pins: gbe1-led0-pins { - mux { - function = "led"; - groups = "gbe1_led0"; - }; - }; - - gbe2_led0_pins: gbe2-led0-pins { - mux { - function = "led"; - groups = "gbe2_led0"; - }; - }; - - gbe3_led0_pins: gbe3-led0-pins { - mux { - function = "led"; - groups = "gbe3_led0"; - }; - }; - - i2c1_sfp_pins: i2c1-sfp-pins-g0 { - mux { - function = "i2c"; - groups = "i2c1_sfp"; - }; - }; - - i2c2_0_pins: i2c2-pins-g0 { - mux { - function = "i2c"; - groups = "i2c2_0"; - }; - }; - - i2c0_pins: i2c0-pins-g0 { - mux { - function = "i2c"; - groups = "i2c0_1"; - }; - }; - - i2c1_pins: i2c1-pins-g0 { - mux { - function = "i2c"; - groups = "i2c1_0"; - }; - }; - - i2p5gbe_led0_pins: 2p5gbe-led0-pins { - mux { - function = "led"; - groups = "2p5gbe_led0"; - }; - }; - - mmc0_pins_emmc_51: mmc0-pins-emmc-51 { - mux { - function = "flash"; - groups = "emmc_51"; - }; - }; - - mmc0_pins_sdcard: mmc0-pins-sdcard { - mux { - function = "flash"; - groups = "sdcard"; - }; - }; - - uart0_pins: uart0-pins { - mux { - function = "uart"; - groups = "uart0"; - }; - }; - - spi0_flash_pins: spi0-flash-pins { - mux { - function = "spi"; - groups = "spi0", "spi0_wp_hold"; - }; - }; - - spi1_pins: spi1-pins { - mux { - function = "spi"; - groups = "spi1"; - }; - }; -}; - -ð { - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; -}; - -&gmac0 { - status = "okay"; -}; - -&cpu0 { - proc-supply = <&rt5190_buck3>; -}; - -&cpu1 { - proc-supply = <&rt5190_buck3>; -}; - -&cpu2 { - proc-supply = <&rt5190_buck3>; -}; - -&cpu3 { - proc-supply = <&rt5190_buck3>; -}; - -&cci { - proc-supply = <&rt5190_buck3>; -}; - -ð { - status = "okay"; -}; - -&switch { - status = "okay"; -}; - -&gsw_phy0 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe0_led0_pins>; -}; - -&gsw_port0 { - label = "lan0"; -}; - -&gsw_phy0_led0 { - status = "okay"; - function = LED_FUNCTION_LAN; - color = ; -}; - -&gsw_phy1 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe1_led0_pins>; -}; - -&gsw_port1 { - label = "lan1"; -}; - -&gsw_phy1_led0 { - status = "okay"; - function = LED_FUNCTION_LAN; - color = ; -}; - -&gsw_phy2 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe2_led0_pins>; -}; - -&gsw_port2 { - label = "lan2"; -}; - -&gsw_phy2_led0 { - status = "okay"; - function = LED_FUNCTION_LAN; - color = ; -}; - -&gsw_phy3 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe3_led0_pins>; -}; - -&gsw_port3 { - label = "lan3"; -}; - -&gsw_phy3_led0 { - status = "okay"; - function = LED_FUNCTION_LAN; - color = ; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - - rt5190a_64: rt5190a@64 { - compatible = "richtek,rt5190a"; - reg = <0x64>; - /*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/ - vin2-supply = <&rt5190_buck1>; - vin3-supply = <&rt5190_buck1>; - vin4-supply = <&rt5190_buck1>; - - regulators { - rt5190_buck1: buck1 { - regulator-name = "rt5190a-buck1"; - regulator-min-microvolt = <5090000>; - regulator-max-microvolt = <5090000>; - regulator-allowed-modes = - ; - regulator-boot-on; - regulator-always-on; - }; - buck2 { - regulator-name = "vcore"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - rt5190_buck3: buck3 { - regulator-name = "vproc"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - }; - buck4 { - regulator-name = "rt5190a-buck4"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-allowed-modes = - ; - regulator-boot-on; - regulator-always-on; - }; - ldo { - regulator-name = "rt5190a-ldo"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&pcie2 { - status = "disabled"; -}; - -&pcie3 { - status = "okay"; -}; - -&ssusb0 { - status = "okay"; -}; - -&ssusb1 { - status = "okay"; -}; - -&tphy { - status = "okay"; -}; - -&serial0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&watchdog { - status = "okay"; -}; - -&xsphy { - status = "okay"; -}; diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a.dtsi deleted file mode 100644 index 6d8953c873f..00000000000 --- a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ /dev/null @@ -1,1392 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2023 MediaTek Inc. - * Author: Sam.Shih - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/* TOPRGU resets */ -#define MT7988_TOPRGU_SGMII0_GRST 1 -#define MT7988_TOPRGU_SGMII1_GRST 2 -#define MT7988_TOPRGU_XFI0_GRST 12 -#define MT7988_TOPRGU_XFI1_GRST 13 -#define MT7988_TOPRGU_XFI_PEXTP0_GRST 14 -#define MT7988_TOPRGU_XFI_PEXTP1_GRST 15 -#define MT7988_TOPRGU_XFI_PLL_GRST 16 - -/ { - compatible = "mediatek,mt7988a"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cci: cci { - compatible = "mediatek,mt7988-cci", - "mediatek,mt8183-cci"; - clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>, - <&topckgen CLK_TOP_XTAL>; - clock-names = "cci", "intermediate"; - operating-points-v2 = <&cci_opp>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a73"; - reg = <0x0>; - device_type = "cpu"; - enable-method = "psci"; - clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; - mediatek,cci = <&cci>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a73"; - reg = <0x1>; - device_type = "cpu"; - enable-method = "psci"; - clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; - mediatek,cci = <&cci>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a73"; - reg = <0x2>; - device_type = "cpu"; - enable-method = "psci"; - clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; - mediatek,cci = <&cci>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a73"; - reg = <0x3>; - device_type = "cpu"; - enable-method = "psci"; - clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; - mediatek,cci = <&cci>; - }; - - cluster0_opp: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp00 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <850000>; - }; - - opp01 { - opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <850000>; - }; - - opp02 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <850000>; - }; - - opp03 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <900000>; - }; - }; - }; - - cci_opp: opp_table_cci { - compatible = "operating-points-v2"; - opp-shared; - - opp00 { - opp-hz = /bits/ 64 <480000000>; - opp-microvolt = <850000>; - }; - - opp01 { - opp-hz = /bits/ 64 <660000000>; - opp-microvolt = <850000>; - }; - - opp02 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <850000>; - }; - - opp03 { - opp-hz = /bits/ 64 <1080000000>; - opp-microvolt = <900000>; - }; - }; - - clk40m: oscillator@0 { - compatible = "fixed-clock"; - clock-frequency = <40000000>; - #clock-cells = <0>; - clock-output-names = "clkxtal"; - }; - - pmu { - compatible = "arm,cortex-a73-pmu"; - interrupt-parent = <&gic>; - interrupts = ; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - reserved-memory { - ranges; - #address-cells = <2>; - #size-cells = <2>; - - /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */ - secmon_reserved: secmon@43000000 { - reg = <0 0x43000000 0 0x50000>; - no-map; - }; - - wmcpu_emi: wmcpu-reserved@47cc0000 { - reg = <0 0x47cc0000 0 0x00100000>; - no-map; - }; - - wo_emi0: wo-emi@4f600000 { - reg = <0 0x4f600000 0 0x40000>; - no-map; - }; - - wo_emi1: wo-emi@4f640000 { - reg = <0 0x4f640000 0 0x40000>; - no-map; - }; - - wo_emi2: wo-emi@4f680000 { - reg = <0 0x4f680000 0 0x40000>; - no-map; - }; - - wo_data: wo-data@4f700000 { - reg = <0 0x4f700000 0 0x800000>; - no-map; - shared = <1>; - }; - }; - - soc { - compatible = "simple-bus"; - ranges; - #address-cells = <2>; - #size-cells = <2>; - - gic: interrupt-controller@c000000 { - compatible = "arm,gic-v3"; - reg = <0 0x0c000000 0 0x40000>, /* GICD */ - <0 0x0c080000 0 0x200000>, /* GICR */ - <0 0x0c400000 0 0x2000>, /* GICC */ - <0 0x0c410000 0 0x1000>, /* GICH */ - <0 0x0c420000 0 0x2000>; /* GICV */ - interrupt-parent = <&gic>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - }; - - phyfw: phy-firmware@f000000 { - compatible = "mediatek,2p5gphy-fw"; - reg = <0 0x0f100000 0 0x20000>, - <0 0x0f0f0018 0 0x20>; - }; - - infracfg: infracfg@10001000 { - compatible = "mediatek,mt7988-infracfg", "syscon"; - reg = <0 0x10001000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - topckgen: topckgen@1001b000 { - compatible = "mediatek,mt7988-topckgen", "syscon"; - reg = <0 0x1001b000 0 0x1000>; - #clock-cells = <1>; - }; - - watchdog: watchdog@1001c000 { - compatible = "mediatek,mt7988-wdt", - "mediatek,mt6589-wdt", - "syscon"; - reg = <0 0x1001c000 0 0x1000>; - interrupts = ; - #reset-cells = <1>; - }; - - apmixedsys: apmixedsys@1001e000 { - compatible = "mediatek,mt7988-apmixedsys"; - reg = <0 0x1001e000 0 0x1000>; - #clock-cells = <1>; - }; - - pio: pinctrl@1001f000 { - compatible = "mediatek,mt7988-pinctrl", "syscon"; - reg = <0 0x1001f000 0 0x1000>, - <0 0x11c10000 0 0x1000>, - <0 0x11d00000 0 0x1000>, - <0 0x11d20000 0 0x1000>, - <0 0x11e00000 0 0x1000>, - <0 0x11f00000 0 0x1000>, - <0 0x1000b000 0 0x1000>; - reg-names = "gpio_base", "iocfg_tr_base", - "iocfg_br_base", "iocfg_rb_base", - "iocfg_lb_base", "iocfg_tl_base", "eint"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pio 0 0 84>; - interrupt-controller; - interrupts = ; - interrupt-parent = <&gic>; - #interrupt-cells = <2>; - - pcie0_pins: pcie0-pins { - mux { - function = "pcie"; - groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", - "pcie_wake_n0_0"; - }; - }; - - pcie1_pins: pcie1-pins { - mux { - function = "pcie"; - groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", - "pcie_wake_n1_0"; - }; - }; - - pcie2_pins: pcie2-pins { - mux { - function = "pcie"; - groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", - "pcie_wake_n2_0"; - }; - }; - - pcie3_pins: pcie3-pins { - mux { - function = "pcie"; - groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", - "pcie_wake_n3_0"; - }; - }; - - snfi_pins: snfi-pins { - mux { - function = "flash"; - groups = "snfi"; - }; - }; - }; - - pwm: pwm@10048000 { - compatible = "mediatek,mt7988-pwm"; - reg = <0 0x10048000 0 0x1000>; - #pwm-cells = <2>; - clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>, - <&infracfg CLK_INFRA_66M_PWM_HCK>, - <&infracfg CLK_INFRA_66M_PWM_CK1>, - <&infracfg CLK_INFRA_66M_PWM_CK2>, - <&infracfg CLK_INFRA_66M_PWM_CK3>, - <&infracfg CLK_INFRA_66M_PWM_CK4>, - <&infracfg CLK_INFRA_66M_PWM_CK5>, - <&infracfg CLK_INFRA_66M_PWM_CK6>, - <&infracfg CLK_INFRA_66M_PWM_CK7>, - <&infracfg CLK_INFRA_66M_PWM_CK8>; - clock-names = "top", "main", "pwm1", "pwm2", "pwm3", - "pwm4","pwm5","pwm6","pwm7","pwm8"; - status = "disabled"; - }; - - sgmiisys0: syscon@10060000 { - compatible = "mediatek,mt7988-sgmiisys", - "mediatek,mt7988-sgmiisys0", - "syscon", - "simple-mfd"; - reg = <0 0x10060000 0 0x1000>; - resets = <&watchdog MT7988_TOPRGU_SGMII0_GRST>; - #clock-cells = <1>; - - sgmiipcs0: pcs { - compatible = "mediatek,mt7988-sgmii"; - clocks = <&topckgen CLK_TOP_SGM_0_SEL>, - <&sgmiisys0 CLK_SGM0_TX_EN>, - <&sgmiisys0 CLK_SGM0_RX_EN>; - clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx"; - }; - }; - - sgmiisys1: syscon@10070000 { - compatible = "mediatek,mt7988-sgmiisys", - "mediatek,mt7988-sgmiisys1", - "syscon", - "simple-mfd"; - reg = <0 0x10070000 0 0x1000>; - resets = <&watchdog MT7988_TOPRGU_SGMII1_GRST>; - #clock-cells = <1>; - - sgmiipcs1: pcs { - compatible = "mediatek,mt7988-sgmii"; - clocks = <&topckgen CLK_TOP_SGM_1_SEL>, - <&sgmiisys1 CLK_SGM1_TX_EN>, - <&sgmiisys1 CLK_SGM1_RX_EN>; - clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx"; - }; - }; - - usxgmiisys0: pcs@10080000 { - compatible = "mediatek,mt7988-usxgmiisys"; - reg = <0 0x10080000 0 0x1000>; - resets = <&watchdog MT7988_TOPRGU_XFI0_GRST>; - clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>; - }; - - usxgmiisys1: pcs@10081000 { - compatible = "mediatek,mt7988-usxgmiisys"; - reg = <0 0x10081000 0 0x1000>; - resets = <&watchdog MT7988_TOPRGU_XFI1_GRST>; - clocks = <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>; - }; - - mcusys: mcusys@100e0000 { - compatible = "mediatek,mt7988-mcusys", "syscon"; - reg = <0 0x100e0000 0 0x1000>; - #clock-cells = <1>; - }; - - serial0: serial@11000000 { - compatible = "mediatek,mt7986-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11000000 0 0x100>; - interrupts = ; - /* - * 8250-mtk driver don't control "baud" clock since commit - * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks - * still need to be passed to the driver to prevent probe fail - */ - clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_52M_UART0_CK>; - clock-names = "baud", "bus"; - assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_MUX_UART0_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, - <&topckgen CLK_TOP_UART_SEL>; - status = "disabled"; - }; - - serial1: serial@11000100 { - compatible = "mediatek,mt7986-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11000100 0 0x100>; - interrupts = ; - /* - * 8250-mtk driver don't control "baud" clock since commit - * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks - * still need to be passed to the driver to prevent probe fail - */ - clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_52M_UART1_CK>; - clock-names = "baud", "bus"; - assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_MUX_UART1_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, - <&topckgen CLK_TOP_UART_SEL>; - status = "disabled"; - }; - - serial2: serial@11000200 { - compatible = "mediatek,mt7986-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11000200 0 0x100>; - interrupts = ; - /* - * 8250-mtk driver don't control "baud" clock since commit - * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks - * still need to be passed to the driver to prevent probe fail - */ - clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_52M_UART2_CK>; - clock-names = "baud", "bus"; - assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_MUX_UART2_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, - <&topckgen CLK_TOP_UART_SEL>; - status = "disabled"; - }; - - snand: spi@11001000 { - compatible = "mediatek,mt7986-snand"; - reg = <0 0x11001000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_SPINFI>, - <&infracfg CLK_INFRA_NFI>; - clock-names = "pad_clk", "nfi_clk"; - assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>, - <&topckgen CLK_TOP_NFI1X_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>, - <&topckgen CLK_TOP_MPLL_D8>; - nand-ecc-engine = <&bch>; - mediatek,quad-spi; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&snfi_pins>; - status = "disabled"; - }; - - bch: ecc@11002000 { - compatible = "mediatek,mt7686-ecc"; - reg = <0 0x11002000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_NFI1X_SEL>; - clock-names = "nfiecc_clk"; - status = "disabled"; - }; - - i2c0: i2c@11003000 { - compatible = "mediatek,mt7988-i2c", - "mediatek,mt7981-i2c"; - reg = <0 0x11003000 0 0x1000>, - <0 0x10217080 0 0x80>; - interrupts = ; - clock-div = <1>; - clocks = <&infracfg CLK_INFRA_I2C_BCK>, - <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; - clock-names = "main", "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@11004000 { - compatible = "mediatek,mt7988-i2c", - "mediatek,mt7981-i2c"; - reg = <0 0x11004000 0 0x1000>, - <0 0x10217100 0 0x80>; - interrupts = ; - clock-div = <1>; - clocks = <&infracfg CLK_INFRA_I2C_BCK>, - <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; - clock-names = "main", "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@11005000 { - compatible = "mediatek,mt7988-i2c", - "mediatek,mt7981-i2c"; - reg = <0 0x11005000 0 0x1000>, - <0 0x10217180 0 0x80>; - interrupts = ; - clock-div = <1>; - clocks = <&infracfg CLK_INFRA_I2C_BCK>, - <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; - clock-names = "main", "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@11007000 { - compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm"; - reg = <0 0x11007000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_MPLL_D2>, - <&topckgen CLK_TOP_SPI_SEL>, - <&infracfg CLK_INFRA_104M_SPI0>, - <&infracfg CLK_INFRA_66M_SPI0_HCK>; - clock-names = "parent-clk", "sel-clk", "spi-clk", - "hclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@11008000 { - compatible = "mediatek,ipm-spi-single", "mediatek,spi-ipm"; - reg = <0 0x11008000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_MPLL_D2>, - <&topckgen CLK_TOP_SPIM_MST_SEL>, - <&infracfg CLK_INFRA_104M_SPI1>, - <&infracfg CLK_INFRA_66M_SPI1_HCK>; - clock-names = "parent-clk", "sel-clk", "spi-clk", - "hclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@11009000 { - compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm"; - reg = <0 0x11009000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_MPLL_D2>, - <&topckgen CLK_TOP_SPI_SEL>, - <&infracfg CLK_INFRA_104M_SPI2_BCK>, - <&infracfg CLK_INFRA_66M_SPI2_HCK>; - clock-names = "parent-clk", "sel-clk", "spi-clk", - "hclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - lvts: lvts@1100a000 { - compatible = "mediatek,mt7988-lvts-ap"; - reg = <0 0x1100a000 0 0x1000>; - clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>; - clock-names = "lvts_clk"; - interrupts = ; - resets = <&infracfg MT7988_INFRA_RST1_THERM_CTRL_SWRST>; - nvmem-cells = <&lvts_calibration>; - nvmem-cell-names = "lvts-calib-data-1"; - #thermal-sensor-cells = <1>; - }; - - ssusb0: usb@11190000 { - compatible = "mediatek,mt7988-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x11190000 0 0x2e00>, - <0 0x11193e00 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - phys = <&xphyu2port0 PHY_TYPE_USB2>, - <&xphyu3port0 PHY_TYPE_USB3>; - clocks = <&infracfg CLK_INFRA_USB_SYS>, - <&infracfg CLK_INFRA_USB_XHCI>, - <&infracfg CLK_INFRA_USB_REF>, - <&infracfg CLK_INFRA_66M_USB_HCK>, - <&infracfg CLK_INFRA_133M_USB_HCK>; - clock-names = "sys_ck", - "xhci_ck", - "ref_ck", - "mcu_ck", - "dma_ck"; - #address-cells = <2>; - #size-cells = <2>; - mediatek,p0_speed_fixup; - status = "disabled"; - }; - - ssusb1: usb@11200000 { - compatible = "mediatek,mt7988-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x11200000 0 0x2e00>, - <0 0x11203e00 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - phys = <&tphyu2port0 PHY_TYPE_USB2>, - <&tphyu3port0 PHY_TYPE_USB3>; - clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>, - <&infracfg CLK_INFRA_USB_XHCI_CK_P1>, - <&infracfg CLK_INFRA_USB_CK_P1>, - <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>, - <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>; - clock-names = "sys_ck", - "xhci_ck", - "ref_ck", - "mcu_ck", - "dma_ck"; - #address-cells = <2>; - #size-cells = <2>; - status = "disabled"; - }; - - afe: audio-controller@11210000 { - compatible = "mediatek,mt79xx-audio"; - reg = <0 0x11210000 0 0x9000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>, - <&infracfg CLK_INFRA_AUD_26M>, - <&infracfg CLK_INFRA_AUD_L>, - <&infracfg CLK_INFRA_AUD_AUD>, - <&infracfg CLK_INFRA_AUD_EG2>, - <&topckgen CLK_TOP_AUD_SEL>, - <&topckgen CLK_TOP_AUD_I2S_M>; - clock-names = "aud_bus_ck", - "aud_26m_ck", - "aud_l_ck", - "aud_aud_ck", - "aud_eg2_ck", - "aud_sel", - "aud_i2s_m"; - assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>, - <&topckgen CLK_TOP_A1SYS_SEL>, - <&topckgen CLK_TOP_AUD_L_SEL>, - <&topckgen CLK_TOP_A_TUNER_SEL>; - assigned-clock-parents = <&apmixedsys CLK_APMIXED_APLL2>, - <&topckgen CLK_TOP_APLL2_D4>, - <&apmixedsys CLK_APMIXED_APLL2>, - <&topckgen CLK_TOP_APLL2_D4>; - status = "disabled"; - }; - - mmc0: mmc@11230000 { - compatible = "mediatek,mt7986-mmc", - "mediatek,mt7981-mmc"; - reg = <0 0x11230000 0 0x1000>, - <0 0x11D60000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_MSDC400>, - <&infracfg CLK_INFRA_MSDC2_HCK>, - <&infracfg CLK_INFRA_66M_MSDC_0_HCK>, - <&infracfg CLK_INFRA_133M_MSDC_0_HCK>; - assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>, - <&topckgen CLK_TOP_EMMC_400M_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>, - <&apmixedsys CLK_APMIXED_MSDCPLL>; - clock-names = "source", - "hclk", - "axi_cg", - "ahb_cg"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pcie2: pcie@11280000 { - compatible = "mediatek,mt7988-pcie", - "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; - reg = <0 0x11280000 0 0x2000>; - reg-names = "pcie-mac"; - ranges = <0x81000000 0x00 0x20000000 0x00 - 0x20000000 0x00 0x00200000>, - <0x82000000 0x00 0x20200000 0x00 - 0x20200000 0x00 0x07e00000>; - device_type = "pci"; - linux,pci-domain = <3>; - interrupts = ; - bus-range = <0x00 0xff>; - clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>, - <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>, - <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>, - <&infracfg CLK_INFRA_133M_PCIE_CK_P2>, - <&topckgen CLK_TOP_PEXTP_P2_SEL>; - clock-names = "pl_250m", "tl_26m", "peri_26m", - "top_133m", "pextp_clk"; - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_pins>; - phys = <&xphyu3port0 PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &pcie_intc2 0>, - <0 0 0 2 &pcie_intc2 1>, - <0 0 0 3 &pcie_intc2 2>, - <0 0 0 4 &pcie_intc2 3>; - #address-cells = <3>; - #size-cells = <2>; - status = "disabled"; - - pcie_intc2: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; - - pcie3: pcie@11290000 { - compatible = "mediatek,mt7988-pcie", - "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; - reg = <0 0x11290000 0 0x2000>; - reg-names = "pcie-mac"; - ranges = <0x81000000 0x00 0x28000000 0x00 - 0x28000000 0x00 0x00200000>, - <0x82000000 0x00 0x28200000 0x00 - 0x28200000 0x00 0x07e00000>; - device_type = "pci"; - linux,pci-domain = <2>; - interrupts = ; - bus-range = <0x00 0xff>; - clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>, - <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>, - <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>, - <&infracfg CLK_INFRA_133M_PCIE_CK_P3>, - <&topckgen CLK_TOP_PEXTP_P3_SEL>; - clock-names = "pl_250m", "tl_26m", "peri_26m", - "top_133m", "pextp_clk"; - pinctrl-names = "default"; - pinctrl-0 = <&pcie3_pins>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &pcie_intc3 0>, - <0 0 0 2 &pcie_intc3 1>, - <0 0 0 3 &pcie_intc3 2>, - <0 0 0 4 &pcie_intc3 3>; - #address-cells = <3>; - #size-cells = <2>; - status = "disabled"; - - pcie_intc3: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; - - pcie0: pcie@11300000 { - compatible = "mediatek,mt7988-pcie", - "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; - reg = <0 0x11300000 0 0x2000>; - reg-names = "pcie-mac"; - ranges = <0x81000000 0x00 0x30000000 0x00 - 0x30000000 0x00 0x00200000>, - <0x82000000 0x00 0x30200000 0x00 - 0x30200000 0x00 0x07e00000>; - device_type = "pci"; - linux,pci-domain = <0>; - interrupts = ; - bus-range = <0x00 0xff>; - clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>, - <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>, - <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>, - <&infracfg CLK_INFRA_133M_PCIE_CK_P0>, - <&topckgen CLK_TOP_PEXTP_P0_SEL>; - clock-names = "pl_250m", "tl_26m", "peri_26m", - "top_133m", "pextp_clk"; - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_pins>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &pcie_intc0 0>, - <0 0 0 2 &pcie_intc0 1>, - <0 0 0 3 &pcie_intc0 2>, - <0 0 0 4 &pcie_intc0 3>; - #address-cells = <3>; - #size-cells = <2>; - status = "disabled"; - - pcie_intc0: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; - - pcie1: pcie@11310000 { - compatible = "mediatek,mt7988-pcie", - "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; - reg = <0 0x11310000 0 0x2000>; - reg-names = "pcie-mac"; - ranges = <0x81000000 0x00 0x38000000 0x00 - 0x38000000 0x00 0x00200000>, - <0x82000000 0x00 0x38200000 0x00 - 0x38200000 0x00 0x07e00000>; - device_type = "pci"; - linux,pci-domain = <1>; - interrupts = ; - bus-range = <0x00 0xff>; - clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>, - <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>, - <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>, - <&infracfg CLK_INFRA_133M_PCIE_CK_P1>, - <&topckgen CLK_TOP_PEXTP_P1_SEL>; - clock-names = "pl_250m", "tl_26m", "peri_26m", - "top_133m", "pextp_clk"; - pinctrl-names = "default"; - pinctrl-0 = <&pcie1_pins>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &pcie_intc1 0>, - <0 0 0 2 &pcie_intc1 1>, - <0 0 0 3 &pcie_intc1 2>, - <0 0 0 4 &pcie_intc1 3>; - #address-cells = <3>; - #size-cells = <2>; - status = "disabled"; - - pcie_intc1: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; - - tphy: tphy@11c50000 { - compatible = "mediatek,mt7988", - "mediatek,generic-tphy-v2"; - ranges; - #address-cells = <2>; - #size-cells = <2>; - status = "disabled"; - - tphyu2port0: usb-phy@11c50000 { - reg = <0 0x11c50000 0 0x700>; - clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>; - clock-names = "ref"; - #phy-cells = <1>; - }; - - tphyu3port0: usb-phy@11c50700 { - reg = <0 0x11c50700 0 0x900>; - clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>; - clock-names = "ref"; - #phy-cells = <1>; - mediatek,usb3-pll-ssc-delta; - mediatek,usb3-pll-ssc-delta1; - }; - }; - - topmisc: topmisc@11d10000 { - compatible = "mediatek,mt7988-topmisc", "syscon", - "mediatek,mt7988-power-controller"; - reg = <0 0x11d10000 0 0x10000>; - #clock-cells = <1>; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - - xsphy: xphy@11e10000 { - compatible = "mediatek,mt7988", - "mediatek,xsphy"; - ranges; - #address-cells = <2>; - #size-cells = <2>; - status = "disabled"; - - xphyu2port0: usb-phy@11e10000 { - reg = <0 0x11e10000 0 0x400>; - clocks = <&infracfg CLK_INFRA_USB_UTMI>; - clock-names = "ref"; - #phy-cells = <1>; - }; - - xphyu3port0: usb-phy@11e13000 { - reg = <0 0x11e13400 0 0x500>; - clocks = <&infracfg CLK_INFRA_USB_PIPE>; - clock-names = "ref"; - #phy-cells = <1>; - mediatek,syscon-type = <&topmisc 0x218 0>; - }; - }; - - xfi_tphy0: phy@11f20000 { - compatible = "mediatek,mt7988-xfi-tphy"; - reg = <0 0x11f20000 0 0x10000>; - resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP0_GRST>; - clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>; - clock-names = "xfipll", "topxtal"; - mediatek,usxgmii-performance-errata; - #phy-cells = <0>; - }; - - xfi_tphy1: phy@11f30000 { - compatible = "mediatek,mt7988-xfi-tphy"; - reg = <0 0x11f30000 0 0x10000>; - resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP1_GRST>; - clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>; - clock-names = "xfipll", "topxtal"; - #phy-cells = <0>; - }; - - xfi_pll: clock-controller@11f40000 { - compatible = "mediatek,mt7988-xfi-pll"; - reg = <0 0x11f40000 0 0x1000>; - resets = <&watchdog MT7988_TOPRGU_XFI_PLL_GRST>; - #clock-cells = <1>; - }; - - efuse: efuse@11f50000 { - compatible = "mediatek,efuse"; - reg = <0 0x11f50000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - lvts_calibration: calib@918 { - reg = <0x918 0x28>; - }; - - phy_calibration_p0: calib@940 { - reg = <0x940 0x10>; - }; - - phy_calibration_p1: calib@954 { - reg = <0x954 0x10>; - }; - - phy_calibration_p2: calib@968 { - reg = <0x968 0x10>; - }; - - phy_calibration_p3: calib@97c { - reg = <0x97c 0x10>; - }; - - cpufreq_calibration: calib@278 { - reg = <0x278 0x1>; - }; - }; - - ethsys: syscon@15000000 { - compatible = "mediatek,mt7988-ethsys", "syscon"; - reg = <0 0x15000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - }; - - wed0: wed@15010000 { - compatible = "mediatek,mt7988-wed", - "syscon"; - reg = <0 0x15010000 0 0x2000>; - interrupt-parent = <&gic>; - interrupts = ; - memory-region = <&wo_emi0>, <&wo_data>; - memory-region-names = "wo-emi", "wo-data"; - mediatek,wo-ccif = <&wo_ccif0>; - mediatek,wo-ilm = <&wo_ilm0>; - mediatek,wo-dlm = <&wo_dlm0>; - mediatek,wo-cpuboot = <&wo_cpuboot0>; - }; - - wed1: wed@15012000 { - compatible = "mediatek,mt7988-wed", - "syscon"; - reg = <0 0x15012000 0 0x2000>; - interrupt-parent = <&gic>; - interrupts = ; - memory-region = <&wo_emi1>, <&wo_data>; - memory-region-names = "wo-emi", "wo-data"; - mediatek,wo-ccif = <&wo_ccif1>; - mediatek,wo-ilm = <&wo_ilm1>; - mediatek,wo-dlm = <&wo_dlm1>; - mediatek,wo-cpuboot = <&wo_cpuboot1>; - }; - - wed2: wed@15014000 { - compatible = "mediatek,mt7988-wed", - "syscon"; - reg = <0 0x15014000 0 0x2000>; - interrupt-parent = <&gic>; - interrupts = ; - memory-region = <&wo_emi2>, <&wo_data>; - memory-region-names = "wo-emi", "wo-data"; - mediatek,wo-ccif = <&wo_ccif2>; - mediatek,wo-ilm = <&wo_ilm2>; - mediatek,wo-dlm = <&wo_dlm2>; - mediatek,wo-cpuboot = <&wo_cpuboot2>; - }; - - switch: switch@15020000 { - compatible = "mediatek,mt7988-switch"; - reg = <0 0x15020000 0 0x8000>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - resets = <ðwarp MT7988_ETHWARP_RST_SWITCH>; - #address-cells = <1>; - #size-cells = <1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - gsw_port0: port@0 { - reg = <0>; - phy-mode = "internal"; - phy-handle = <&gsw_phy0>; - }; - - gsw_port1: port@1 { - reg = <1>; - phy-mode = "internal"; - phy-handle = <&gsw_phy1>; - }; - - gsw_port2: port@2 { - reg = <2>; - phy-mode = "internal"; - phy-handle = <&gsw_phy2>; - }; - - gsw_port3: port@3 { - reg = <3>; - phy-mode = "internal"; - phy-handle = <&gsw_phy3>; - }; - - port@6 { - reg = <6>; - ethernet = <&gmac0>; - phy-mode = "internal"; - - fixed-link { - speed = <10000>; - full-duplex; - pause; - }; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - mediatek,pio = <&pio>; - - gsw_phy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - interrupts = <0>; - phy-mode = "internal"; - nvmem-cells = <&phy_calibration_p0>; - nvmem-cell-names = "phy-cal-data"; - - leds { - #address-cells = <1>; - #size-cells = <0>; - - gsw_phy0_led0: gsw-phy0-led0@0 { - reg = <0>; - status = "disabled"; - }; - - gsw_phy0_led1: gsw-phy0-led1@1 { - reg = <1>; - status = "disabled"; - }; - }; - }; - - gsw_phy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - interrupts = <1>; - phy-mode = "internal"; - nvmem-cells = <&phy_calibration_p1>; - nvmem-cell-names = "phy-cal-data"; - - leds { - #address-cells = <1>; - #size-cells = <0>; - - gsw_phy1_led0: gsw-phy1-led0@0 { - reg = <0>; - status = "disabled"; - }; - - gsw_phy1_led1: gsw-phy1-led1@1 { - reg = <1>; - status = "disabled"; - }; - }; - }; - - gsw_phy2: ethernet-phy@2 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <2>; - interrupts = <2>; - phy-mode = "internal"; - nvmem-cells = <&phy_calibration_p2>; - nvmem-cell-names = "phy-cal-data"; - - leds { - #address-cells = <1>; - #size-cells = <0>; - - gsw_phy2_led0: gsw-phy2-led0@0 { - reg = <0>; - status = "disabled"; - }; - - gsw_phy2_led1: gsw-phy2-led1@1 { - reg = <1>; - status = "disabled"; - }; - }; - }; - - gsw_phy3: ethernet-phy@3 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <3>; - interrupts = <3>; - phy-mode = "internal"; - nvmem-cells = <&phy_calibration_p3>; - nvmem-cell-names = "phy-cal-data"; - - leds { - #address-cells = <1>; - #size-cells = <0>; - - gsw_phy3_led0: gsw-phy3-led0@0 { - reg = <0>; - status = "disabled"; - }; - - gsw_phy3_led1: gsw-phy3-led1@1 { - reg = <1>; - status = "disabled"; - }; - }; - }; - }; - }; - - ethwarp: clock-controller@15031000 { - compatible = "mediatek,mt7988-ethwarp"; - reg = <0 0x15031000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - eth: ethernet@15100000 { - compatible = "mediatek,mt7988-eth"; - reg = <0 0x15100000 0 0x80000>, - <0 0x15400000 0 0x380000>; - interrupts = , - , - , - ; - clocks = <ðsys CLK_ETHDMA_XGP1_EN>, - <ðsys CLK_ETHDMA_XGP2_EN>, - <ðsys CLK_ETHDMA_XGP3_EN>, - <ðsys CLK_ETHDMA_FE_EN>, - <ðsys CLK_ETHDMA_GP2_EN>, - <ðsys CLK_ETHDMA_GP1_EN>, - <ðsys CLK_ETHDMA_GP3_EN>, - <ðsys CLK_ETHDMA_ESW_EN>, - <ðsys CLK_ETHDMA_CRYPT0_EN>, - <ðwarp CLK_ETHWARP_WOCPU2_EN>, - <ðwarp CLK_ETHWARP_WOCPU1_EN>, - <ðwarp CLK_ETHWARP_WOCPU0_EN>, - <&topckgen CLK_TOP_ETH_GMII_SEL>, - <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>, - <&topckgen CLK_TOP_ETH_SYS_200M_SEL>, - <&topckgen CLK_TOP_ETH_SYS_SEL>, - <&topckgen CLK_TOP_ETH_XGMII_SEL>, - <&topckgen CLK_TOP_ETH_MII_SEL>, - <&topckgen CLK_TOP_NETSYS_SEL>, - <&topckgen CLK_TOP_NETSYS_500M_SEL>, - <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>, - <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>, - <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>, - <&topckgen CLK_TOP_NETSYS_WARP_SEL>; - clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1", - "gp3", "esw", "crypto", - "ethwarp_wocpu2", "ethwarp_wocpu1", - "ethwarp_wocpu0", "top_eth_gmii_sel", - "top_eth_refck_50m_sel", "top_eth_sys_200m_sel", - "top_eth_sys_sel", "top_eth_xgmii_sel", - "top_eth_mii_sel", "top_netsys_sel", - "top_netsys_500m_sel", "top_netsys_pao_2x_sel", - "top_netsys_sync_250m_sel", - "top_netsys_ppefb_250m_sel", - "top_netsys_warp_sel"; - assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, - <&topckgen CLK_TOP_NETSYS_GSW_SEL>, - <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>, - <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>, - <&topckgen CLK_TOP_SGM_0_SEL>, - <&topckgen CLK_TOP_SGM_1_SEL>; - assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, - <&topckgen CLK_TOP_NET1PLL_D4>, - <&topckgen CLK_TOP_NET1PLL_D8_D4>, - <&topckgen CLK_TOP_NET1PLL_D8_D4>, - <&apmixedsys CLK_APMIXED_SGMPLL>, - <&apmixedsys CLK_APMIXED_SGMPLL>; - mediatek,ethsys = <ðsys>; - mediatek,infracfg = <&topmisc>; - mediatek,wed = <&wed0>, <&wed1>, <&wed2>; - #address-cells = <1>; - #size-cells = <0>; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "internal"; - status = "disabled"; - - fixed-link { - speed = <10000>; - full-duplex; - pause; - }; - }; - - gmac1: mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - status = "disabled"; - pcs-handle = <&sgmiipcs1>, <&usxgmiisys1>; - phys = <&xfi_tphy1>; - }; - - gmac2: mac@2 { - compatible = "mediatek,eth-mac"; - reg = <2>; - status = "disabled"; - pcs-handle = <&sgmiipcs0>, <&usxgmiisys0>; - phys = <&xfi_tphy0>; - }; - - mdio_bus: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - /* internal 2.5G PHY */ - int_2p5g_phy: ethernet-phy@15 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <15>; - phy-mode = "internal"; - - leds { - #address-cells = <1>; - #size-cells = <0>; - - i2p5gbe_led0: i2p5gbe-led0@0 { - reg = <0>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - - i2p5gbe_led1: i2p5gbe-led1@1 { - reg = <1>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - }; - }; - }; - }; - - wo_ccif0: syscon@151a5000 { - compatible = "mediatek,mt7988-wo-ccif", "syscon"; - reg = <0 0x151a5000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - }; - - wo_ccif1: syscon@152a5000 { - compatible = "mediatek,mt7988-wo-ccif", "syscon"; - reg = <0 0x152a5000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - }; - - wo_ccif2: syscon@153a5000 { - compatible = "mediatek,mt7988-wo-ccif", "syscon"; - reg = <0 0x153a5000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - }; - - wo_ilm0: syscon@151e0000 { - compatible = "mediatek,mt7988-wo-ilm", "syscon"; - reg = <0 0x151e0000 0 0x8000>; - }; - - wo_ilm1: syscon@152e0000 { - compatible = "mediatek,mt7988-wo-ilm", "syscon"; - reg = <0 0x152e0000 0 0x8000>; - }; - - wo_ilm2: syscon@153e0000 { - compatible = "mediatek,mt7988-wo-ilm", "syscon"; - reg = <0 0x153e0000 0 0x8000>; - }; - - wo_dlm0: syscon@151e8000 { - compatible = "mediatek,mt7988-wo-dlm", "syscon"; - reg = <0 0x151e8000 0 0x2000>; - }; - - wo_dlm1: syscon@152e8000 { - compatible = "mediatek,mt7988-wo-dlm", "syscon"; - reg = <0 0x152e8000 0 0x2000>; - }; - - wo_dlm2: syscon@153e8000 { - compatible = "mediatek,mt7988-wo-dlm", "syscon"; - reg = <0 0x153e8000 0 0x2000>; - }; - - wo_cpuboot0: syscon@15194000 { - compatible = "mediatek,mt7988-wo-cpuboot", "syscon"; - reg = <0 0x15194000 0 0x1000>; - }; - - wo_cpuboot1: syscon@15294000 { - compatible = "mediatek,mt7988-wo-cpuboot", "syscon"; - reg = <0 0x15294000 0 0x1000>; - }; - - wo_cpuboot2: syscon@15394000 { - compatible = "mediatek,mt7988-wo-cpuboot", "syscon"; - reg = <0 0x15394000 0 0x1000>; - }; - - crypto: crypto@15600000 { - compatible = "inside-secure,safexcel-eip197b"; - reg = <0 0x15600000 0 0x180000>; - interrupts = , - , - , - ; - interrupt-names = "ring0", "ring1", "ring2", "ring3"; - status = "okay"; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <1000>; - thermal-sensors = <&lvts 0>; - - trips { - cpu_trip_crit: crit { - temperature = <125000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; -}; diff --git a/target/linux/mediatek/files-6.12/drivers/pinctrl/mediatek/pinctrl-mt7988.c b/target/linux/mediatek/files-6.12/drivers/pinctrl/mediatek/pinctrl-mt7988.c deleted file mode 100644 index 648bd03acbc..00000000000 --- a/target/linux/mediatek/files-6.12/drivers/pinctrl/mediatek/pinctrl-mt7988.c +++ /dev/null @@ -1,1548 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * The MT7988 driver based on Linux generic pinctrl binding. - * - * Copyright (C) 2020 MediaTek Inc. - * Author: Sam Shih - */ - -#include "pinctrl-moore.h" - -enum MT7988_PINCTRL_REG_PAGE { - GPIO_BASE, - IOCFG_TR_BASE, - IOCFG_BR_BASE, - IOCFG_RB_BASE, - IOCFG_LB_BASE, - IOCFG_TL_BASE, -}; - -#define MT7988_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4) - -#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ - _x_bits) \ - PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ - _x_bits, 32, 0) - -#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ - _x_bits) \ - PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ - _x_bits, 32, 1) - -static const struct mtk_pin_field_calc mt7988_pin_mode_range[] = { - PIN_FIELD(0, 83, 0x300, 0x10, 0, 4), -}; - -static const struct mtk_pin_field_calc mt7988_pin_dir_range[] = { - PIN_FIELD(0, 83, 0x0, 0x10, 0, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_di_range[] = { - PIN_FIELD(0, 83, 0x200, 0x10, 0, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_do_range[] = { - PIN_FIELD(0, 83, 0x100, 0x10, 0, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = { - PIN_FIELD_BASE(0, 0, 5, 0x30, 0x10, 13, 1), - PIN_FIELD_BASE(1, 1, 5, 0x30, 0x10, 14, 1), - PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 11, 1), - PIN_FIELD_BASE(3, 3, 5, 0x30, 0x10, 12, 1), - PIN_FIELD_BASE(4, 4, 5, 0x30, 0x10, 0, 1), - PIN_FIELD_BASE(5, 5, 5, 0x30, 0x10, 9, 1), - PIN_FIELD_BASE(6, 6, 5, 0x30, 0x10, 10, 1), - - PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 8, 1), - PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 6, 1), - PIN_FIELD_BASE(9, 9, 4, 0x30, 0x10, 5, 1), - PIN_FIELD_BASE(10, 10, 4, 0x30, 0x10, 3, 1), - - PIN_FIELD_BASE(11, 11, 1, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(12, 12, 1, 0x40, 0x10, 21, 1), - PIN_FIELD_BASE(13, 13, 1, 0x40, 0x10, 1, 1), - PIN_FIELD_BASE(14, 14, 1, 0x40, 0x10, 2, 1), - - PIN_FIELD_BASE(15, 15, 5, 0x30, 0x10, 7, 1), - PIN_FIELD_BASE(16, 16, 5, 0x30, 0x10, 8, 1), - PIN_FIELD_BASE(17, 17, 5, 0x30, 0x10, 3, 1), - PIN_FIELD_BASE(18, 18, 5, 0x30, 0x10, 4, 1), - - PIN_FIELD_BASE(19, 19, 4, 0x30, 0x10, 7, 1), - PIN_FIELD_BASE(20, 20, 4, 0x30, 0x10, 4, 1), - - PIN_FIELD_BASE(21, 21, 3, 0x50, 0x10, 17, 1), - PIN_FIELD_BASE(22, 22, 3, 0x50, 0x10, 23, 1), - PIN_FIELD_BASE(23, 23, 3, 0x50, 0x10, 20, 1), - PIN_FIELD_BASE(24, 24, 3, 0x50, 0x10, 19, 1), - PIN_FIELD_BASE(25, 25, 3, 0x50, 0x10, 21, 1), - PIN_FIELD_BASE(26, 26, 3, 0x50, 0x10, 22, 1), - PIN_FIELD_BASE(27, 27, 3, 0x50, 0x10, 18, 1), - PIN_FIELD_BASE(28, 28, 3, 0x50, 0x10, 25, 1), - PIN_FIELD_BASE(29, 29, 3, 0x50, 0x10, 26, 1), - PIN_FIELD_BASE(30, 30, 3, 0x50, 0x10, 27, 1), - PIN_FIELD_BASE(31, 31, 3, 0x50, 0x10, 24, 1), - PIN_FIELD_BASE(32, 32, 3, 0x50, 0x10, 28, 1), - PIN_FIELD_BASE(33, 33, 3, 0x60, 0x10, 0, 1), - PIN_FIELD_BASE(34, 34, 3, 0x50, 0x10, 31, 1), - PIN_FIELD_BASE(35, 35, 3, 0x50, 0x10, 29, 1), - PIN_FIELD_BASE(36, 36, 3, 0x50, 0x10, 30, 1), - PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 1, 1), - PIN_FIELD_BASE(38, 38, 3, 0x50, 0x10, 11, 1), - PIN_FIELD_BASE(39, 39, 3, 0x50, 0x10, 10, 1), - PIN_FIELD_BASE(40, 40, 3, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(41, 41, 3, 0x50, 0x10, 1, 1), - PIN_FIELD_BASE(42, 42, 3, 0x50, 0x10, 9, 1), - PIN_FIELD_BASE(43, 43, 3, 0x50, 0x10, 8, 1), - PIN_FIELD_BASE(44, 44, 3, 0x50, 0x10, 7, 1), - PIN_FIELD_BASE(45, 45, 3, 0x50, 0x10, 6, 1), - PIN_FIELD_BASE(46, 46, 3, 0x50, 0x10, 5, 1), - PIN_FIELD_BASE(47, 47, 3, 0x50, 0x10, 4, 1), - PIN_FIELD_BASE(48, 48, 3, 0x50, 0x10, 3, 1), - PIN_FIELD_BASE(49, 49, 3, 0x50, 0x10, 2, 1), - PIN_FIELD_BASE(50, 50, 3, 0x50, 0x10, 15, 1), - PIN_FIELD_BASE(51, 51, 3, 0x50, 0x10, 12, 1), - PIN_FIELD_BASE(52, 52, 3, 0x50, 0x10, 13, 1), - PIN_FIELD_BASE(53, 53, 3, 0x50, 0x10, 14, 1), - PIN_FIELD_BASE(54, 54, 3, 0x50, 0x10, 16, 1), - - PIN_FIELD_BASE(55, 55, 1, 0x40, 0x10, 14, 1), - PIN_FIELD_BASE(56, 56, 1, 0x40, 0x10, 15, 1), - PIN_FIELD_BASE(57, 57, 1, 0x40, 0x10, 13, 1), - PIN_FIELD_BASE(58, 58, 1, 0x40, 0x10, 4, 1), - PIN_FIELD_BASE(59, 59, 1, 0x40, 0x10, 5, 1), - PIN_FIELD_BASE(60, 60, 1, 0x40, 0x10, 6, 1), - PIN_FIELD_BASE(61, 61, 1, 0x40, 0x10, 3, 1), - PIN_FIELD_BASE(62, 62, 1, 0x40, 0x10, 7, 1), - PIN_FIELD_BASE(63, 63, 1, 0x40, 0x10, 20, 1), - PIN_FIELD_BASE(64, 64, 1, 0x40, 0x10, 8, 1), - PIN_FIELD_BASE(65, 65, 1, 0x40, 0x10, 9, 1), - PIN_FIELD_BASE(66, 66, 1, 0x40, 0x10, 10, 1), - PIN_FIELD_BASE(67, 67, 1, 0x40, 0x10, 11, 1), - PIN_FIELD_BASE(68, 68, 1, 0x40, 0x10, 12, 1), - - PIN_FIELD_BASE(69, 69, 5, 0x30, 0x10, 1, 1), - PIN_FIELD_BASE(70, 70, 5, 0x30, 0x10, 2, 1), - PIN_FIELD_BASE(71, 71, 5, 0x30, 0x10, 5, 1), - PIN_FIELD_BASE(72, 72, 5, 0x30, 0x10, 6, 1), - - PIN_FIELD_BASE(73, 73, 4, 0x30, 0x10, 10, 1), - PIN_FIELD_BASE(74, 74, 4, 0x30, 0x10, 1, 1), - PIN_FIELD_BASE(75, 75, 4, 0x30, 0x10, 11, 1), - PIN_FIELD_BASE(76, 76, 4, 0x30, 0x10, 9, 1), - PIN_FIELD_BASE(77, 77, 4, 0x30, 0x10, 2, 1), - PIN_FIELD_BASE(78, 78, 4, 0x30, 0x10, 0, 1), - PIN_FIELD_BASE(79, 79, 4, 0x30, 0x10, 12, 1), - - PIN_FIELD_BASE(80, 80, 1, 0x40, 0x10, 18, 1), - PIN_FIELD_BASE(81, 81, 1, 0x40, 0x10, 19, 1), - PIN_FIELD_BASE(82, 82, 1, 0x40, 0x10, 16, 1), - PIN_FIELD_BASE(83, 83, 1, 0x40, 0x10, 17, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = { - PIN_FIELD_BASE(0, 0, 5, 0xc0, 0x10, 13, 1), - PIN_FIELD_BASE(1, 1, 5, 0xc0, 0x10, 14, 1), - PIN_FIELD_BASE(2, 2, 5, 0xc0, 0x10, 11, 1), - PIN_FIELD_BASE(3, 3, 5, 0xc0, 0x10, 12, 1), - PIN_FIELD_BASE(4, 4, 5, 0xc0, 0x10, 0, 1), - PIN_FIELD_BASE(5, 5, 5, 0xc0, 0x10, 9, 1), - PIN_FIELD_BASE(6, 6, 5, 0xc0, 0x10, 10, 1), - - PIN_FIELD_BASE(7, 7, 4, 0xb0, 0x10, 8, 1), - PIN_FIELD_BASE(8, 8, 4, 0xb0, 0x10, 6, 1), - PIN_FIELD_BASE(9, 9, 4, 0xb0, 0x10, 5, 1), - PIN_FIELD_BASE(10, 10, 4, 0xb0, 0x10, 3, 1), - - PIN_FIELD_BASE(11, 11, 1, 0xe0, 0x10, 0, 1), - PIN_FIELD_BASE(12, 12, 1, 0xe0, 0x10, 21, 1), - PIN_FIELD_BASE(13, 13, 1, 0xe0, 0x10, 1, 1), - PIN_FIELD_BASE(14, 14, 1, 0xe0, 0x10, 2, 1), - - PIN_FIELD_BASE(15, 15, 5, 0xc0, 0x10, 7, 1), - PIN_FIELD_BASE(16, 16, 5, 0xc0, 0x10, 8, 1), - PIN_FIELD_BASE(17, 17, 5, 0xc0, 0x10, 3, 1), - PIN_FIELD_BASE(18, 18, 5, 0xc0, 0x10, 4, 1), - - PIN_FIELD_BASE(19, 19, 4, 0xb0, 0x10, 7, 1), - PIN_FIELD_BASE(20, 20, 4, 0xb0, 0x10, 4, 1), - - PIN_FIELD_BASE(21, 21, 3, 0x140, 0x10, 17, 1), - PIN_FIELD_BASE(22, 22, 3, 0x140, 0x10, 23, 1), - PIN_FIELD_BASE(23, 23, 3, 0x140, 0x10, 20, 1), - PIN_FIELD_BASE(24, 24, 3, 0x140, 0x10, 19, 1), - PIN_FIELD_BASE(25, 25, 3, 0x140, 0x10, 21, 1), - PIN_FIELD_BASE(26, 26, 3, 0x140, 0x10, 22, 1), - PIN_FIELD_BASE(27, 27, 3, 0x140, 0x10, 18, 1), - PIN_FIELD_BASE(28, 28, 3, 0x140, 0x10, 25, 1), - PIN_FIELD_BASE(29, 29, 3, 0x140, 0x10, 26, 1), - PIN_FIELD_BASE(30, 30, 3, 0x140, 0x10, 27, 1), - PIN_FIELD_BASE(31, 31, 3, 0x140, 0x10, 24, 1), - PIN_FIELD_BASE(32, 32, 3, 0x140, 0x10, 28, 1), - PIN_FIELD_BASE(33, 33, 3, 0x150, 0x10, 0, 1), - PIN_FIELD_BASE(34, 34, 3, 0x140, 0x10, 31, 1), - PIN_FIELD_BASE(35, 35, 3, 0x140, 0x10, 29, 1), - PIN_FIELD_BASE(36, 36, 3, 0x140, 0x10, 30, 1), - PIN_FIELD_BASE(37, 37, 3, 0x150, 0x10, 1, 1), - PIN_FIELD_BASE(38, 38, 3, 0x140, 0x10, 11, 1), - PIN_FIELD_BASE(39, 39, 3, 0x140, 0x10, 10, 1), - PIN_FIELD_BASE(40, 40, 3, 0x140, 0x10, 0, 1), - PIN_FIELD_BASE(41, 41, 3, 0x140, 0x10, 1, 1), - PIN_FIELD_BASE(42, 42, 3, 0x140, 0x10, 9, 1), - PIN_FIELD_BASE(43, 43, 3, 0x140, 0x10, 8, 1), - PIN_FIELD_BASE(44, 44, 3, 0x140, 0x10, 7, 1), - PIN_FIELD_BASE(45, 45, 3, 0x140, 0x10, 6, 1), - PIN_FIELD_BASE(46, 46, 3, 0x140, 0x10, 5, 1), - PIN_FIELD_BASE(47, 47, 3, 0x140, 0x10, 4, 1), - PIN_FIELD_BASE(48, 48, 3, 0x140, 0x10, 3, 1), - PIN_FIELD_BASE(49, 49, 3, 0x140, 0x10, 2, 1), - PIN_FIELD_BASE(50, 50, 3, 0x140, 0x10, 15, 1), - PIN_FIELD_BASE(51, 51, 3, 0x140, 0x10, 12, 1), - PIN_FIELD_BASE(52, 52, 3, 0x140, 0x10, 13, 1), - PIN_FIELD_BASE(53, 53, 3, 0x140, 0x10, 14, 1), - PIN_FIELD_BASE(54, 54, 3, 0x140, 0x10, 16, 1), - - PIN_FIELD_BASE(55, 55, 1, 0xe0, 0x10, 14, 1), - PIN_FIELD_BASE(56, 56, 1, 0xe0, 0x10, 15, 1), - PIN_FIELD_BASE(57, 57, 1, 0xe0, 0x10, 13, 1), - PIN_FIELD_BASE(58, 58, 1, 0xe0, 0x10, 4, 1), - PIN_FIELD_BASE(59, 59, 1, 0xe0, 0x10, 5, 1), - PIN_FIELD_BASE(60, 60, 1, 0xe0, 0x10, 6, 1), - PIN_FIELD_BASE(61, 61, 1, 0xe0, 0x10, 3, 1), - PIN_FIELD_BASE(62, 62, 1, 0xe0, 0x10, 7, 1), - PIN_FIELD_BASE(63, 63, 1, 0xe0, 0x10, 20, 1), - PIN_FIELD_BASE(64, 64, 1, 0xe0, 0x10, 8, 1), - PIN_FIELD_BASE(65, 65, 1, 0xe0, 0x10, 9, 1), - PIN_FIELD_BASE(66, 66, 1, 0xe0, 0x10, 10, 1), - PIN_FIELD_BASE(67, 67, 1, 0xe0, 0x10, 11, 1), - PIN_FIELD_BASE(68, 68, 1, 0xe0, 0x10, 12, 1), - - PIN_FIELD_BASE(69, 69, 5, 0xc0, 0x10, 1, 1), - PIN_FIELD_BASE(70, 70, 5, 0xc0, 0x10, 2, 1), - PIN_FIELD_BASE(71, 71, 5, 0xc0, 0x10, 5, 1), - PIN_FIELD_BASE(72, 72, 5, 0xc0, 0x10, 6, 1), - - PIN_FIELD_BASE(73, 73, 4, 0xb0, 0x10, 10, 1), - PIN_FIELD_BASE(74, 74, 4, 0xb0, 0x10, 1, 1), - PIN_FIELD_BASE(75, 75, 4, 0xb0, 0x10, 11, 1), - PIN_FIELD_BASE(76, 76, 4, 0xb0, 0x10, 9, 1), - PIN_FIELD_BASE(77, 77, 4, 0xb0, 0x10, 2, 1), - PIN_FIELD_BASE(78, 78, 4, 0xb0, 0x10, 0, 1), - PIN_FIELD_BASE(79, 79, 4, 0xb0, 0x10, 12, 1), - - PIN_FIELD_BASE(80, 80, 1, 0xe0, 0x10, 18, 1), - PIN_FIELD_BASE(81, 81, 1, 0xe0, 0x10, 19, 1), - PIN_FIELD_BASE(82, 82, 1, 0xe0, 0x10, 16, 1), - PIN_FIELD_BASE(83, 83, 1, 0xe0, 0x10, 17, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = { - PIN_FIELD_BASE(7, 7, 4, 0x60, 0x10, 5, 1), - PIN_FIELD_BASE(8, 8, 4, 0x60, 0x10, 4, 1), - PIN_FIELD_BASE(9, 9, 4, 0x60, 0x10, 3, 1), - PIN_FIELD_BASE(10, 10, 4, 0x60, 0x10, 2, 1), - - PIN_FIELD_BASE(13, 13, 1, 0x70, 0x10, 0, 1), - PIN_FIELD_BASE(14, 14, 1, 0x70, 0x10, 1, 1), - PIN_FIELD_BASE(63, 63, 1, 0x70, 0x10, 2, 1), - - PIN_FIELD_BASE(75, 75, 4, 0x60, 0x10, 7, 1), - PIN_FIELD_BASE(76, 76, 4, 0x60, 0x10, 6, 1), - PIN_FIELD_BASE(77, 77, 4, 0x60, 0x10, 1, 1), - PIN_FIELD_BASE(78, 78, 4, 0x60, 0x10, 0, 1), - PIN_FIELD_BASE(79, 79, 4, 0x60, 0x10, 8, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = { - PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 5, 1), - PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1), - PIN_FIELD_BASE(9, 9, 4, 0x40, 0x10, 3, 1), - PIN_FIELD_BASE(10, 10, 4, 0x40, 0x10, 2, 1), - - PIN_FIELD_BASE(13, 13, 1, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(14, 14, 1, 0x50, 0x10, 1, 1), - - PIN_FIELD_BASE(15, 15, 5, 0x40, 0x10, 4, 1), - PIN_FIELD_BASE(16, 16, 5, 0x40, 0x10, 5, 1), - PIN_FIELD_BASE(17, 17, 5, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(18, 18, 5, 0x40, 0x10, 1, 1), - - PIN_FIELD_BASE(63, 63, 1, 0x50, 0x10, 2, 1), - PIN_FIELD_BASE(71, 71, 5, 0x40, 0x10, 2, 1), - PIN_FIELD_BASE(72, 72, 5, 0x40, 0x10, 3, 1), - - PIN_FIELD_BASE(75, 75, 4, 0x40, 0x10, 7, 1), - PIN_FIELD_BASE(76, 76, 4, 0x40, 0x10, 6, 1), - PIN_FIELD_BASE(77, 77, 4, 0x40, 0x10, 1, 1), - PIN_FIELD_BASE(78, 78, 4, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(79, 79, 4, 0x40, 0x10, 8, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = { - PIN_FIELD_BASE(0, 0, 5, 0x00, 0x10, 21, 3), - PIN_FIELD_BASE(1, 1, 5, 0x00, 0x10, 24, 3), - PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 15, 3), - PIN_FIELD_BASE(3, 3, 5, 0x00, 0x10, 18, 3), - PIN_FIELD_BASE(4, 4, 5, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(5, 5, 5, 0x00, 0x10, 9, 3), - PIN_FIELD_BASE(6, 6, 5, 0x00, 0x10, 12, 3), - - PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 24, 3), - PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 28, 3), - PIN_FIELD_BASE(9, 9, 4, 0x00, 0x10, 15, 3), - PIN_FIELD_BASE(10, 10, 4, 0x00, 0x10, 9, 3), - - PIN_FIELD_BASE(11, 11, 1, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(12, 12, 1, 0x20, 0x10, 3, 3), - PIN_FIELD_BASE(13, 13, 1, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(14, 14, 1, 0x00, 0x10, 6, 3), - - PIN_FIELD_BASE(19, 19, 4, 0x00, 0x10, 21, 3), - PIN_FIELD_BASE(20, 20, 4, 0x00, 0x10, 12, 3), - - PIN_FIELD_BASE(21, 21, 3, 0x10, 0x10, 21, 3), - PIN_FIELD_BASE(22, 22, 3, 0x20, 0x10, 9, 3), - PIN_FIELD_BASE(23, 23, 3, 0x20, 0x10, 0, 3), - PIN_FIELD_BASE(24, 24, 3, 0x10, 0x10, 27, 3), - PIN_FIELD_BASE(25, 25, 3, 0x20, 0x10, 3, 3), - PIN_FIELD_BASE(26, 26, 3, 0x20, 0x10, 6, 3), - PIN_FIELD_BASE(27, 27, 3, 0x10, 0x10, 24, 3), - PIN_FIELD_BASE(28, 28, 3, 0x20, 0x10, 15, 3), - PIN_FIELD_BASE(29, 29, 3, 0x20, 0x10, 18, 3), - PIN_FIELD_BASE(30, 30, 3, 0x20, 0x10, 21, 3), - PIN_FIELD_BASE(31, 31, 3, 0x20, 0x10, 12, 3), - PIN_FIELD_BASE(32, 32, 3, 0x20, 0x10, 24, 3), - PIN_FIELD_BASE(33, 33, 3, 0x30, 0x10, 6, 3), - PIN_FIELD_BASE(34, 34, 3, 0x30, 0x10, 3, 3), - PIN_FIELD_BASE(35, 35, 3, 0x20, 0x10, 27, 3), - PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 0, 3), - PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 9, 3), - PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 3, 3), - PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 0, 3), - PIN_FIELD_BASE(40, 40, 3, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(41, 41, 3, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(42, 42, 3, 0x00, 0x10, 27, 3), - PIN_FIELD_BASE(43, 43, 3, 0x00, 0x10, 24, 3), - PIN_FIELD_BASE(44, 44, 3, 0x00, 0x10, 21, 3), - PIN_FIELD_BASE(45, 45, 3, 0x00, 0x10, 18, 3), - PIN_FIELD_BASE(46, 46, 3, 0x00, 0x10, 15, 3), - PIN_FIELD_BASE(47, 47, 3, 0x00, 0x10, 12, 3), - PIN_FIELD_BASE(48, 48, 3, 0x00, 0x10, 9, 3), - PIN_FIELD_BASE(49, 49, 3, 0x00, 0x10, 6, 3), - PIN_FIELD_BASE(50, 50, 3, 0x10, 0x10, 15, 3), - PIN_FIELD_BASE(51, 51, 3, 0x10, 0x10, 6, 3), - PIN_FIELD_BASE(52, 52, 3, 0x10, 0x10, 9, 3), - PIN_FIELD_BASE(53, 53, 3, 0x10, 0x10, 12, 3), - PIN_FIELD_BASE(54, 54, 3, 0x10, 0x10, 18, 3), - - PIN_FIELD_BASE(55, 55, 1, 0x10, 0x10, 12, 3), - PIN_FIELD_BASE(56, 56, 1, 0x10, 0x10, 15, 3), - PIN_FIELD_BASE(57, 57, 1, 0x10, 0x10, 9, 3), - PIN_FIELD_BASE(58, 58, 1, 0x00, 0x10, 12, 3), - PIN_FIELD_BASE(59, 59, 1, 0x00, 0x10, 15, 3), - PIN_FIELD_BASE(60, 60, 1, 0x00, 0x10, 18, 3), - PIN_FIELD_BASE(61, 61, 1, 0x00, 0x10, 9, 3), - PIN_FIELD_BASE(62, 62, 1, 0x00, 0x10, 21, 3), - PIN_FIELD_BASE(63, 63, 1, 0x20, 0x10, 0, 3), - PIN_FIELD_BASE(64, 64, 1, 0x00, 0x10, 24, 3), - PIN_FIELD_BASE(65, 65, 1, 0x00, 0x10, 27, 3), - PIN_FIELD_BASE(66, 66, 1, 0x10, 0x10, 0, 3), - PIN_FIELD_BASE(67, 67, 1, 0x10, 0x10, 3, 3), - PIN_FIELD_BASE(68, 68, 1, 0x10, 0x10, 6, 3), - - PIN_FIELD_BASE(69, 69, 5, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(70, 70, 5, 0x00, 0x10, 6, 3), - - PIN_FIELD_BASE(73, 73, 4, 0x10, 0x10, 0, 3), - PIN_FIELD_BASE(74, 74, 4, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(75, 75, 4, 0x10, 0x10, 3, 3), - PIN_FIELD_BASE(76, 76, 4, 0x00, 0x10, 27, 3), - PIN_FIELD_BASE(77, 77, 4, 0x00, 0x10, 6, 3), - PIN_FIELD_BASE(78, 78, 4, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(79, 79, 4, 0x10, 0x10, 6, 3), - - PIN_FIELD_BASE(80, 80, 1, 0x10, 0x10, 24, 3), - PIN_FIELD_BASE(81, 81, 1, 0x10, 0x10, 27, 3), - PIN_FIELD_BASE(82, 82, 1, 0x10, 0x10, 18, 3), - PIN_FIELD_BASE(83, 83, 1, 0x10, 0x10, 21, 3), -}; - -static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = { - PIN_FIELD_BASE(0, 0, 5, 0x50, 0x10, 7, 1), - PIN_FIELD_BASE(1, 1, 5, 0x50, 0x10, 8, 1), - PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 5, 1), - PIN_FIELD_BASE(3, 3, 5, 0x50, 0x10, 6, 1), - PIN_FIELD_BASE(4, 4, 5, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(5, 5, 5, 0x50, 0x10, 3, 1), - PIN_FIELD_BASE(6, 6, 5, 0x50, 0x10, 4, 1), - - PIN_FIELD_BASE(11, 11, 1, 0x60, 0x10, 0, 1), - PIN_FIELD_BASE(12, 12, 1, 0x60, 0x10, 18, 1), - - PIN_FIELD_BASE(19, 19, 4, 0x50, 0x10, 2, 1), - PIN_FIELD_BASE(20, 20, 4, 0x50, 0x10, 1, 1), - - PIN_FIELD_BASE(21, 21, 3, 0x70, 0x10, 17, 1), - PIN_FIELD_BASE(22, 22, 3, 0x70, 0x10, 23, 1), - PIN_FIELD_BASE(23, 23, 3, 0x70, 0x10, 20, 1), - PIN_FIELD_BASE(24, 24, 3, 0x70, 0x10, 19, 1), - PIN_FIELD_BASE(25, 25, 3, 0x70, 0x10, 21, 1), - PIN_FIELD_BASE(26, 26, 3, 0x70, 0x10, 22, 1), - PIN_FIELD_BASE(27, 27, 3, 0x70, 0x10, 18, 1), - PIN_FIELD_BASE(28, 28, 3, 0x70, 0x10, 25, 1), - PIN_FIELD_BASE(29, 29, 3, 0x70, 0x10, 26, 1), - PIN_FIELD_BASE(30, 30, 3, 0x70, 0x10, 27, 1), - PIN_FIELD_BASE(31, 31, 3, 0x70, 0x10, 24, 1), - PIN_FIELD_BASE(32, 32, 3, 0x70, 0x10, 28, 1), - PIN_FIELD_BASE(33, 33, 3, 0x80, 0x10, 0, 1), - PIN_FIELD_BASE(34, 34, 3, 0x70, 0x10, 31, 1), - PIN_FIELD_BASE(35, 35, 3, 0x70, 0x10, 29, 1), - PIN_FIELD_BASE(36, 36, 3, 0x70, 0x10, 30, 1), - PIN_FIELD_BASE(37, 37, 3, 0x80, 0x10, 1, 1), - PIN_FIELD_BASE(38, 38, 3, 0x70, 0x10, 11, 1), - PIN_FIELD_BASE(39, 39, 3, 0x70, 0x10, 10, 1), - PIN_FIELD_BASE(40, 40, 3, 0x70, 0x10, 0, 1), - PIN_FIELD_BASE(41, 41, 3, 0x70, 0x10, 1, 1), - PIN_FIELD_BASE(42, 42, 3, 0x70, 0x10, 9, 1), - PIN_FIELD_BASE(43, 43, 3, 0x70, 0x10, 8, 1), - PIN_FIELD_BASE(44, 44, 3, 0x70, 0x10, 7, 1), - PIN_FIELD_BASE(45, 45, 3, 0x70, 0x10, 6, 1), - PIN_FIELD_BASE(46, 46, 3, 0x70, 0x10, 5, 1), - PIN_FIELD_BASE(47, 47, 3, 0x70, 0x10, 4, 1), - PIN_FIELD_BASE(48, 48, 3, 0x70, 0x10, 3, 1), - PIN_FIELD_BASE(49, 49, 3, 0x70, 0x10, 2, 1), - PIN_FIELD_BASE(50, 50, 3, 0x70, 0x10, 15, 1), - PIN_FIELD_BASE(51, 51, 3, 0x70, 0x10, 12, 1), - PIN_FIELD_BASE(52, 52, 3, 0x70, 0x10, 13, 1), - PIN_FIELD_BASE(53, 53, 3, 0x70, 0x10, 14, 1), - PIN_FIELD_BASE(54, 54, 3, 0x70, 0x10, 16, 1), - - PIN_FIELD_BASE(55, 55, 1, 0x60, 0x10, 12, 1), - PIN_FIELD_BASE(56, 56, 1, 0x60, 0x10, 13, 1), - PIN_FIELD_BASE(57, 57, 1, 0x60, 0x10, 11, 1), - PIN_FIELD_BASE(58, 58, 1, 0x60, 0x10, 2, 1), - PIN_FIELD_BASE(59, 59, 1, 0x60, 0x10, 3, 1), - PIN_FIELD_BASE(60, 60, 1, 0x60, 0x10, 4, 1), - PIN_FIELD_BASE(61, 61, 1, 0x60, 0x10, 1, 1), - PIN_FIELD_BASE(62, 62, 1, 0x60, 0x10, 5, 1), - PIN_FIELD_BASE(64, 64, 1, 0x60, 0x10, 6, 1), - PIN_FIELD_BASE(65, 65, 1, 0x60, 0x10, 7, 1), - PIN_FIELD_BASE(66, 66, 1, 0x60, 0x10, 8, 1), - PIN_FIELD_BASE(67, 67, 1, 0x60, 0x10, 9, 1), - PIN_FIELD_BASE(68, 68, 1, 0x60, 0x10, 10, 1), - - PIN_FIELD_BASE(69, 69, 5, 0x50, 0x10, 1, 1), - PIN_FIELD_BASE(70, 70, 5, 0x50, 0x10, 2, 1), - - PIN_FIELD_BASE(73, 73, 4, 0x50, 0x10, 3, 1), - PIN_FIELD_BASE(74, 74, 4, 0x50, 0x10, 0, 1), - - PIN_FIELD_BASE(80, 80, 1, 0x60, 0x10, 16, 1), - PIN_FIELD_BASE(81, 81, 1, 0x60, 0x10, 17, 1), - PIN_FIELD_BASE(82, 82, 1, 0x60, 0x10, 14, 1), - PIN_FIELD_BASE(83, 83, 1, 0x60, 0x10, 15, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = { - PIN_FIELD_BASE(0, 0, 5, 0x60, 0x10, 7, 1), - PIN_FIELD_BASE(1, 1, 5, 0x60, 0x10, 8, 1), - PIN_FIELD_BASE(2, 2, 5, 0x60, 0x10, 5, 1), - PIN_FIELD_BASE(3, 3, 5, 0x60, 0x10, 6, 1), - PIN_FIELD_BASE(4, 4, 5, 0x60, 0x10, 0, 1), - PIN_FIELD_BASE(5, 5, 5, 0x60, 0x10, 3, 1), - PIN_FIELD_BASE(6, 6, 5, 0x60, 0x10, 4, 1), - - PIN_FIELD_BASE(11, 11, 1, 0x80, 0x10, 0, 1), - PIN_FIELD_BASE(12, 12, 1, 0x80, 0x10, 18, 1), - - PIN_FIELD_BASE(19, 19, 4, 0x70, 0x10, 2, 1), - PIN_FIELD_BASE(20, 20, 4, 0x70, 0x10, 1, 1), - - PIN_FIELD_BASE(21, 21, 3, 0x90, 0x10, 17, 1), - PIN_FIELD_BASE(22, 22, 3, 0x90, 0x10, 23, 1), - PIN_FIELD_BASE(23, 23, 3, 0x90, 0x10, 20, 1), - PIN_FIELD_BASE(24, 24, 3, 0x90, 0x10, 19, 1), - PIN_FIELD_BASE(25, 25, 3, 0x90, 0x10, 21, 1), - PIN_FIELD_BASE(26, 26, 3, 0x90, 0x10, 22, 1), - PIN_FIELD_BASE(27, 27, 3, 0x90, 0x10, 18, 1), - PIN_FIELD_BASE(28, 28, 3, 0x90, 0x10, 25, 1), - PIN_FIELD_BASE(29, 29, 3, 0x90, 0x10, 26, 1), - PIN_FIELD_BASE(30, 30, 3, 0x90, 0x10, 27, 1), - PIN_FIELD_BASE(31, 31, 3, 0x90, 0x10, 24, 1), - PIN_FIELD_BASE(32, 32, 3, 0x90, 0x10, 28, 1), - PIN_FIELD_BASE(33, 33, 3, 0xa0, 0x10, 0, 1), - PIN_FIELD_BASE(34, 34, 3, 0x90, 0x10, 31, 1), - PIN_FIELD_BASE(35, 35, 3, 0x90, 0x10, 29, 1), - PIN_FIELD_BASE(36, 36, 3, 0x90, 0x10, 30, 1), - PIN_FIELD_BASE(37, 37, 3, 0xa0, 0x10, 1, 1), - PIN_FIELD_BASE(38, 38, 3, 0x90, 0x10, 11, 1), - PIN_FIELD_BASE(39, 39, 3, 0x90, 0x10, 10, 1), - PIN_FIELD_BASE(40, 40, 3, 0x90, 0x10, 0, 1), - PIN_FIELD_BASE(41, 41, 3, 0x90, 0x10, 1, 1), - PIN_FIELD_BASE(42, 42, 3, 0x90, 0x10, 9, 1), - PIN_FIELD_BASE(43, 43, 3, 0x90, 0x10, 8, 1), - PIN_FIELD_BASE(44, 44, 3, 0x90, 0x10, 7, 1), - PIN_FIELD_BASE(45, 45, 3, 0x90, 0x10, 6, 1), - PIN_FIELD_BASE(46, 46, 3, 0x90, 0x10, 5, 1), - PIN_FIELD_BASE(47, 47, 3, 0x90, 0x10, 4, 1), - PIN_FIELD_BASE(48, 48, 3, 0x90, 0x10, 3, 1), - PIN_FIELD_BASE(49, 49, 3, 0x90, 0x10, 2, 1), - PIN_FIELD_BASE(50, 50, 3, 0x90, 0x10, 15, 1), - PIN_FIELD_BASE(51, 51, 3, 0x90, 0x10, 12, 1), - PIN_FIELD_BASE(52, 52, 3, 0x90, 0x10, 13, 1), - PIN_FIELD_BASE(53, 53, 3, 0x90, 0x10, 14, 1), - PIN_FIELD_BASE(54, 54, 3, 0x90, 0x10, 16, 1), - - PIN_FIELD_BASE(55, 55, 1, 0x80, 0x10, 12, 1), - PIN_FIELD_BASE(56, 56, 1, 0x80, 0x10, 13, 1), - PIN_FIELD_BASE(57, 57, 1, 0x80, 0x10, 11, 1), - PIN_FIELD_BASE(58, 58, 1, 0x80, 0x10, 2, 1), - PIN_FIELD_BASE(59, 59, 1, 0x80, 0x10, 3, 1), - PIN_FIELD_BASE(60, 60, 1, 0x80, 0x10, 4, 1), - PIN_FIELD_BASE(61, 61, 1, 0x80, 0x10, 1, 1), - PIN_FIELD_BASE(62, 62, 1, 0x80, 0x10, 5, 1), - PIN_FIELD_BASE(64, 64, 1, 0x80, 0x10, 6, 1), - PIN_FIELD_BASE(65, 65, 1, 0x80, 0x10, 7, 1), - PIN_FIELD_BASE(66, 66, 1, 0x80, 0x10, 8, 1), - PIN_FIELD_BASE(67, 67, 1, 0x80, 0x10, 9, 1), - PIN_FIELD_BASE(68, 68, 1, 0x80, 0x10, 10, 1), - - PIN_FIELD_BASE(69, 69, 5, 0x60, 0x10, 1, 1), - PIN_FIELD_BASE(70, 70, 5, 0x60, 0x10, 2, 1), - - PIN_FIELD_BASE(73, 73, 4, 0x70, 0x10, 3, 1), - PIN_FIELD_BASE(74, 74, 4, 0x70, 0x10, 0, 1), - - PIN_FIELD_BASE(80, 80, 1, 0x80, 0x10, 16, 1), - PIN_FIELD_BASE(81, 81, 1, 0x80, 0x10, 17, 1), - PIN_FIELD_BASE(82, 82, 1, 0x80, 0x10, 14, 1), - PIN_FIELD_BASE(83, 83, 1, 0x80, 0x10, 15, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = { - PIN_FIELD_BASE(0, 0, 5, 0x70, 0x10, 7, 1), - PIN_FIELD_BASE(1, 1, 5, 0x70, 0x10, 8, 1), - PIN_FIELD_BASE(2, 2, 5, 0x70, 0x10, 5, 1), - PIN_FIELD_BASE(3, 3, 5, 0x70, 0x10, 6, 1), - PIN_FIELD_BASE(4, 4, 5, 0x70, 0x10, 0, 1), - PIN_FIELD_BASE(5, 5, 5, 0x70, 0x10, 3, 1), - PIN_FIELD_BASE(6, 6, 5, 0x70, 0x10, 4, 1), - - PIN_FIELD_BASE(11, 11, 1, 0x90, 0x10, 0, 1), - PIN_FIELD_BASE(12, 12, 1, 0x90, 0x10, 18, 1), - - PIN_FIELD_BASE(19, 19, 4, 0x80, 0x10, 2, 1), - PIN_FIELD_BASE(20, 20, 4, 0x80, 0x10, 1, 1), - - PIN_FIELD_BASE(21, 21, 3, 0xb0, 0x10, 17, 1), - PIN_FIELD_BASE(22, 22, 3, 0xb0, 0x10, 23, 1), - PIN_FIELD_BASE(23, 23, 3, 0xb0, 0x10, 20, 1), - PIN_FIELD_BASE(24, 24, 3, 0xb0, 0x10, 19, 1), - PIN_FIELD_BASE(25, 25, 3, 0xb0, 0x10, 21, 1), - PIN_FIELD_BASE(26, 26, 3, 0xb0, 0x10, 22, 1), - PIN_FIELD_BASE(27, 27, 3, 0xb0, 0x10, 18, 1), - PIN_FIELD_BASE(28, 28, 3, 0xb0, 0x10, 25, 1), - PIN_FIELD_BASE(29, 29, 3, 0xb0, 0x10, 26, 1), - PIN_FIELD_BASE(30, 30, 3, 0xb0, 0x10, 27, 1), - PIN_FIELD_BASE(31, 31, 3, 0xb0, 0x10, 24, 1), - PIN_FIELD_BASE(32, 32, 3, 0xb0, 0x10, 28, 1), - PIN_FIELD_BASE(33, 33, 3, 0xc0, 0x10, 0, 1), - PIN_FIELD_BASE(34, 34, 3, 0xb0, 0x10, 31, 1), - PIN_FIELD_BASE(35, 35, 3, 0xb0, 0x10, 29, 1), - PIN_FIELD_BASE(36, 36, 3, 0xb0, 0x10, 30, 1), - PIN_FIELD_BASE(37, 37, 3, 0xc0, 0x10, 1, 1), - PIN_FIELD_BASE(38, 38, 3, 0xb0, 0x10, 11, 1), - PIN_FIELD_BASE(39, 39, 3, 0xb0, 0x10, 10, 1), - PIN_FIELD_BASE(40, 40, 3, 0xb0, 0x10, 0, 1), - PIN_FIELD_BASE(41, 41, 3, 0xb0, 0x10, 1, 1), - PIN_FIELD_BASE(42, 42, 3, 0xb0, 0x10, 9, 1), - PIN_FIELD_BASE(43, 43, 3, 0xb0, 0x10, 8, 1), - PIN_FIELD_BASE(44, 44, 3, 0xb0, 0x10, 7, 1), - PIN_FIELD_BASE(45, 45, 3, 0xb0, 0x10, 6, 1), - PIN_FIELD_BASE(46, 46, 3, 0xb0, 0x10, 5, 1), - PIN_FIELD_BASE(47, 47, 3, 0xb0, 0x10, 4, 1), - PIN_FIELD_BASE(48, 48, 3, 0xb0, 0x10, 3, 1), - PIN_FIELD_BASE(49, 49, 3, 0xb0, 0x10, 2, 1), - PIN_FIELD_BASE(50, 50, 3, 0xb0, 0x10, 15, 1), - PIN_FIELD_BASE(51, 51, 3, 0xb0, 0x10, 12, 1), - PIN_FIELD_BASE(52, 52, 3, 0xb0, 0x10, 13, 1), - PIN_FIELD_BASE(53, 53, 3, 0xb0, 0x10, 14, 1), - PIN_FIELD_BASE(54, 54, 3, 0xb0, 0x10, 16, 1), - - PIN_FIELD_BASE(55, 55, 1, 0x90, 0x10, 12, 1), - PIN_FIELD_BASE(56, 56, 1, 0x90, 0x10, 13, 1), - PIN_FIELD_BASE(57, 57, 1, 0x90, 0x10, 11, 1), - PIN_FIELD_BASE(58, 58, 1, 0x90, 0x10, 2, 1), - PIN_FIELD_BASE(59, 59, 1, 0x90, 0x10, 3, 1), - PIN_FIELD_BASE(60, 60, 1, 0x90, 0x10, 4, 1), - PIN_FIELD_BASE(61, 61, 1, 0x90, 0x10, 1, 1), - PIN_FIELD_BASE(62, 62, 1, 0x90, 0x10, 5, 1), - PIN_FIELD_BASE(64, 64, 1, 0x90, 0x10, 6, 1), - PIN_FIELD_BASE(65, 65, 1, 0x90, 0x10, 7, 1), - PIN_FIELD_BASE(66, 66, 1, 0x90, 0x10, 8, 1), - PIN_FIELD_BASE(67, 67, 1, 0x90, 0x10, 9, 1), - PIN_FIELD_BASE(68, 68, 1, 0x90, 0x10, 10, 1), - - PIN_FIELD_BASE(69, 69, 5, 0x70, 0x10, 1, 1), - PIN_FIELD_BASE(70, 70, 5, 0x70, 0x10, 2, 1), - - PIN_FIELD_BASE(73, 73, 4, 0x80, 0x10, 3, 1), - PIN_FIELD_BASE(74, 74, 4, 0x80, 0x10, 0, 1), - - PIN_FIELD_BASE(80, 80, 1, 0x90, 0x10, 16, 1), - PIN_FIELD_BASE(81, 81, 1, 0x90, 0x10, 17, 1), - PIN_FIELD_BASE(82, 82, 1, 0x90, 0x10, 14, 1), - PIN_FIELD_BASE(83, 83, 1, 0x90, 0x10, 15, 1), -}; - -static const unsigned int mt7988_pull_type[] = { - MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/ - MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/ - MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/ - MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PU_PD_TYPE, /*7*/ - MTK_PULL_PU_PD_TYPE, /*8*/ MTK_PULL_PU_PD_TYPE, /*9*/ - MTK_PULL_PU_PD_TYPE, /*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/ - MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PU_PD_TYPE, /*13*/ - MTK_PULL_PU_PD_TYPE, /*14*/ MTK_PULL_PD_TYPE, /*15*/ - MTK_PULL_PD_TYPE, /*16*/ MTK_PULL_PD_TYPE, /*17*/ - MTK_PULL_PD_TYPE, /*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/ - MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/ - MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/ - MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/ - MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/ - MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/ - MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/ - MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/ - MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/ - MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/ - MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/ - MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/ - MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/ - MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/ - MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/ - MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/ - MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/ - MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/ - MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/ - MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/ - MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/ - MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/ - MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PU_PD_TYPE, /*63*/ - MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/ - MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/ - MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PUPD_R1R0_TYPE,/*69*/ - MTK_PULL_PUPD_R1R0_TYPE,/*70*/ MTK_PULL_PD_TYPE, /*71*/ - MTK_PULL_PD_TYPE, /*72*/ MTK_PULL_PUPD_R1R0_TYPE,/*73*/ - MTK_PULL_PUPD_R1R0_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE, /*75*/ - MTK_PULL_PU_PD_TYPE, /*76*/ MTK_PULL_PU_PD_TYPE, /*77*/ - MTK_PULL_PU_PD_TYPE, /*78*/ MTK_PULL_PU_PD_TYPE, /*79*/ - MTK_PULL_PUPD_R1R0_TYPE,/*80*/ MTK_PULL_PUPD_R1R0_TYPE,/*81*/ - MTK_PULL_PUPD_R1R0_TYPE,/*82*/ MTK_PULL_PUPD_R1R0_TYPE,/*83*/ -}; - -static const struct mtk_pin_reg_calc mt7988_reg_cals[] = { - [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7988_pin_mode_range), - [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7988_pin_dir_range), - [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7988_pin_di_range), - [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7988_pin_do_range), - [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7988_pin_smt_range), - [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7988_pin_ies_range), - [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7988_pin_pu_range), - [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7988_pin_pd_range), - [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7988_pin_drv_range), - [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7988_pin_pupd_range), - [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7988_pin_r0_range), - [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7988_pin_r1_range), -}; - -static const struct mtk_pin_desc mt7988_pins[] = { - MT7988_PIN(0, "UART2_RXD"), - MT7988_PIN(1, "UART2_TXD"), - MT7988_PIN(2, "UART2_CTS"), - MT7988_PIN(3, "UART2_RTS"), - MT7988_PIN(4, "GPIO_A"), - MT7988_PIN(5, "SMI_0_MDC"), - MT7988_PIN(6, "SMI_0_MDIO"), - MT7988_PIN(7, "PCIE30_2L_0_WAKE_N"), - MT7988_PIN(8, "PCIE30_2L_0_CLKREQ_N"), - MT7988_PIN(9, "PCIE30_1L_1_WAKE_N"), - MT7988_PIN(10, "PCIE30_1L_1_CLKREQ_N"), - MT7988_PIN(11, "GPIO_P"), - MT7988_PIN(12, "WATCHDOG"), - MT7988_PIN(13, "GPIO_RESET"), - MT7988_PIN(14, "GPIO_WPS"), - MT7988_PIN(15, "PMIC_I2C_SCL"), - MT7988_PIN(16, "PMIC_I2C_SDA"), - MT7988_PIN(17, "I2C_1_SCL"), - MT7988_PIN(18, "I2C_1_SDA"), - MT7988_PIN(19, "PCIE30_2L_0_PRESET_N"), - MT7988_PIN(20, "PCIE30_1L_1_PRESET_N"), - MT7988_PIN(21, "PWMD1"), - MT7988_PIN(22, "SPI0_WP"), - MT7988_PIN(23, "SPI0_HOLD"), - MT7988_PIN(24, "SPI0_CSB"), - MT7988_PIN(25, "SPI0_MISO"), - MT7988_PIN(26, "SPI0_MOSI"), - MT7988_PIN(27, "SPI0_CLK"), - MT7988_PIN(28, "SPI1_CSB"), - MT7988_PIN(29, "SPI1_MISO"), - MT7988_PIN(30, "SPI1_MOSI"), - MT7988_PIN(31, "SPI1_CLK"), - MT7988_PIN(32, "SPI2_CLK"), - MT7988_PIN(33, "SPI2_MOSI"), - MT7988_PIN(34, "SPI2_MISO"), - MT7988_PIN(35, "SPI2_CSB"), - MT7988_PIN(36, "SPI2_HOLD"), - MT7988_PIN(37, "SPI2_WP"), - MT7988_PIN(38, "EMMC_RSTB"), - MT7988_PIN(39, "EMMC_DSL"), - MT7988_PIN(40, "EMMC_CK"), - MT7988_PIN(41, "EMMC_CMD"), - MT7988_PIN(42, "EMMC_DATA_7"), - MT7988_PIN(43, "EMMC_DATA_6"), - MT7988_PIN(44, "EMMC_DATA_5"), - MT7988_PIN(45, "EMMC_DATA_4"), - MT7988_PIN(46, "EMMC_DATA_3"), - MT7988_PIN(47, "EMMC_DATA_2"), - MT7988_PIN(48, "EMMC_DATA_1"), - MT7988_PIN(49, "EMMC_DATA_0"), - MT7988_PIN(50, "PCM_FS_I2S_LRCK"), - MT7988_PIN(51, "PCM_CLK_I2S_BCLK"), - MT7988_PIN(52, "PCM_DRX_I2S_DIN"), - MT7988_PIN(53, "PCM_DTX_I2S_DOUT"), - MT7988_PIN(54, "PCM_MCK_I2S_MCLK"), - MT7988_PIN(55, "UART0_RXD"), - MT7988_PIN(56, "UART0_TXD"), - MT7988_PIN(57, "PWMD0"), - MT7988_PIN(58, "JTAG_JTDI"), - MT7988_PIN(59, "JTAG_JTDO"), - MT7988_PIN(60, "JTAG_JTMS"), - MT7988_PIN(61, "JTAG_JTCLK"), - MT7988_PIN(62, "JTAG_JTRST_N"), - MT7988_PIN(63, "USB_DRV_VBUS_P1"), - MT7988_PIN(64, "LED_A"), - MT7988_PIN(65, "LED_B"), - MT7988_PIN(66, "LED_C"), - MT7988_PIN(67, "LED_D"), - MT7988_PIN(68, "LED_E"), - MT7988_PIN(69, "GPIO_B"), - MT7988_PIN(70, "GPIO_C"), - MT7988_PIN(71, "I2C_2_SCL"), - MT7988_PIN(72, "I2C_2_SDA"), - MT7988_PIN(73, "PCIE30_2L_1_PRESET_N"), - MT7988_PIN(74, "PCIE30_1L_0_PRESET_N"), - MT7988_PIN(75, "PCIE30_2L_1_WAKE_N"), - MT7988_PIN(76, "PCIE30_2L_1_CLKREQ_N"), - MT7988_PIN(77, "PCIE30_1L_0_WAKE_N"), - MT7988_PIN(78, "PCIE30_1L_0_CLKREQ_N"), - MT7988_PIN(79, "USB_DRV_VBUS_P0"), - MT7988_PIN(80, "UART1_RXD"), - MT7988_PIN(81, "UART1_TXD"), - MT7988_PIN(82, "UART1_CTS"), - MT7988_PIN(83, "UART1_RTS"), -}; - -/* jtag */ -static int mt7988_tops_jtag0_0_pins[] = { 0, 1, 2, 3, 4 }; -static int mt7988_tops_jtag0_0_funcs[] = { 2, 2, 2, 2, 2 }; - -static int mt7988_wo0_jtag_pins[] = { 50, 51, 52, 53, 54 }; -static int mt7988_wo0_jtag_funcs[] = { 3, 3, 3, 3, 3 }; - -static int mt7988_wo1_jtag_pins[] = { 50, 51, 52, 53, 54 }; -static int mt7988_wo1_jtag_funcs[] = { 4, 4, 4, 4, 4 }; - -static int mt7988_wo2_jtag_pins[] = { 50, 51, 52, 53, 54 }; -static int mt7988_wo2_jtag_funcs[] = { 5, 5, 5, 5, 5 }; - -static int mt7988_jtag_pins[] = { 58, 59, 60, 61, 62 }; -static int mt7988_jtag_funcs[] = { 1, 1, 1, 1, 1 }; - -static int mt7988_tops_jtag0_1_pins[] = { 58, 59, 60, 61, 62 }; -static int mt7988_tops_jtag0_1_funcs[] = { 4, 4, 4, 4, 4 }; - -/* int_usxgmii */ -static int mt7988_int_usxgmii_pins[] = { 2, 3 }; -static int mt7988_int_usxgmii_funcs[] = { 3, 3 }; - -/* pwm */ -static int mt7988_pwm0_pins[] = { 57 }; -static int mt7988_pwm0_funcs[] = { 1 }; - -static int mt7988_pwm1_pins[] = { 21 }; -static int mt7988_pwm1_funcs[] = { 1 }; - -static int mt7988_pwm2_pins[] = { 80 }; -static int mt7988_pwm2_funcs[] = { 2 }; - -static int mt7988_pwm2_0_pins[] = { 58 }; -static int mt7988_pwm2_0_funcs[] = { 5 }; - -static int mt7988_pwm3_pins[] = { 81 }; -static int mt7988_pwm3_funcs[] = { 2 }; - -static int mt7988_pwm3_0_pins[] = { 59 }; -static int mt7988_pwm3_0_funcs[] = { 5 }; - -static int mt7988_pwm4_pins[] = { 82 }; -static int mt7988_pwm4_funcs[] = { 2 }; - -static int mt7988_pwm4_0_pins[] = { 60 }; -static int mt7988_pwm4_0_funcs[] = { 5 }; - -static int mt7988_pwm5_pins[] = { 83 }; -static int mt7988_pwm5_funcs[] = { 2 }; - -static int mt7988_pwm5_0_pins[] = { 61 }; -static int mt7988_pwm5_0_funcs[] = { 5 }; - -static int mt7988_pwm6_pins[] = { 69 }; -static int mt7988_pwm6_funcs[] = { 3 }; - -static int mt7988_pwm6_0_pins[] = { 62 }; -static int mt7988_pwm6_0_funcs[] = { 5 }; - -static int mt7988_pwm7_pins[] = { 70 }; -static int mt7988_pwm7_funcs[] = { 3 }; - -static int mt7988_pwm7_0_pins[] = { 4 }; -static int mt7988_pwm7_0_funcs[] = { 3 }; - -/* dfd */ -static int mt7988_dfd_pins[] = { 0, 1, 2, 3, 4 }; -static int mt7988_dfd_funcs[] = { 4, 4, 4, 4, 4 }; - -/* i2c */ -static int mt7988_xfi_phy0_i2c0_pins[] = { 0, 1 }; -static int mt7988_xfi_phy0_i2c0_funcs[] = { 5, 5 }; - -static int mt7988_xfi_phy1_i2c0_pins[] = { 0, 1 }; -static int mt7988_xfi_phy1_i2c0_funcs[] = { 6, 6 }; - -static int mt7988_xfi_phy_pll_i2c0_pins[] = { 3, 4 }; -static int mt7988_xfi_phy_pll_i2c0_funcs[] = { 5, 5 }; - -static int mt7988_xfi_phy_pll_i2c1_pins[] = { 3, 4 }; -static int mt7988_xfi_phy_pll_i2c1_funcs[] = { 6, 6 }; - -static int mt7988_i2c0_0_pins[] = { 5, 6 }; -static int mt7988_i2c0_0_funcs[] = { 2, 2 }; - -static int mt7988_i2c1_sfp_pins[] = { 5, 6 }; -static int mt7988_i2c1_sfp_funcs[] = { 4, 4 }; - -static int mt7988_xfi_pextp_phy0_i2c_pins[] = { 5, 6 }; -static int mt7988_xfi_pextp_phy0_i2c_funcs[] = { 5, 5 }; - -static int mt7988_xfi_pextp_phy1_i2c_pins[] = { 5, 6 }; -static int mt7988_xfi_pextp_phy1_i2c_funcs[] = { 6, 6 }; - -static int mt7988_i2c0_1_pins[] = { 15, 16 }; -static int mt7988_i2c0_1_funcs[] = { 1, 1 }; - -static int mt7988_u30_phy_i2c0_pins[] = { 15, 16 }; -static int mt7988_u30_phy_i2c0_funcs[] = { 2, 2 }; - -static int mt7988_u32_phy_i2c0_pins[] = { 15, 16 }; -static int mt7988_u32_phy_i2c0_funcs[] = { 3, 3 }; - -static int mt7988_xfi_phy0_i2c1_pins[] = { 15, 16 }; -static int mt7988_xfi_phy0_i2c1_funcs[] = { 5, 5 }; - -static int mt7988_xfi_phy1_i2c1_pins[] = { 15, 16 }; -static int mt7988_xfi_phy1_i2c1_funcs[] = { 6, 6 }; - -static int mt7988_xfi_phy_pll_i2c2_pins[] = { 15, 16 }; -static int mt7988_xfi_phy_pll_i2c2_funcs[] = { 7, 7 }; - -static int mt7988_i2c1_0_pins[] = { 17, 18 }; -static int mt7988_i2c1_0_funcs[] = { 1, 1 }; - -static int mt7988_u30_phy_i2c1_pins[] = { 17, 18 }; -static int mt7988_u30_phy_i2c1_funcs[] = { 2, 2 }; - -static int mt7988_u32_phy_i2c1_pins[] = { 17, 18 }; -static int mt7988_u32_phy_i2c1_funcs[] = { 3, 3 }; - -static int mt7988_xfi_phy_pll_i2c3_pins[] = { 17, 18 }; -static int mt7988_xfi_phy_pll_i2c3_funcs[] = { 4, 4 }; - -static int mt7988_sgmii0_i2c_pins[] = { 17, 18 }; -static int mt7988_sgmii0_i2c_funcs[] = { 5, 5 }; - -static int mt7988_sgmii1_i2c_pins[] = { 17, 18 }; -static int mt7988_sgmii1_i2c_funcs[] = { 6, 6 }; - -static int mt7988_i2c1_2_pins[] = { 69, 70 }; -static int mt7988_i2c1_2_funcs[] = { 2, 2 }; - -static int mt7988_i2c2_0_pins[] = { 69, 70 }; -static int mt7988_i2c2_0_funcs[] = { 4, 4 }; - -static int mt7988_i2c2_1_pins[] = { 71, 72 }; -static int mt7988_i2c2_1_funcs[] = { 1, 1 }; - -/* eth */ -static int mt7988_mdc_mdio0_pins[] = { 5, 6 }; -static int mt7988_mdc_mdio0_funcs[] = { 1, 1 }; - -static int mt7988_2p5g_ext_mdio_pins[] = { 28, 29 }; -static int mt7988_2p5g_ext_mdio_funcs[] = { 6, 6 }; - -static int mt7988_gbe_ext_mdio_pins[] = { 30, 31 }; -static int mt7988_gbe_ext_mdio_funcs[] = { 6, 6 }; - -static int mt7988_mdc_mdio1_pins[] = { 69, 70 }; -static int mt7988_mdc_mdio1_funcs[] = { 1, 1 }; - -/* pcie */ -static int mt7988_pcie_wake_n0_0_pins[] = { 7 }; -static int mt7988_pcie_wake_n0_0_funcs[] = { 1 }; - -static int mt7988_pcie_clk_req_n0_0_pins[] = { 8 }; -static int mt7988_pcie_clk_req_n0_0_funcs[] = { 1 }; - -static int mt7988_pcie_wake_n3_0_pins[] = { 9 }; -static int mt7988_pcie_wake_n3_0_funcs[] = { 1 }; - -static int mt7988_pcie_clk_req_n3_pins[] = { 10 }; -static int mt7988_pcie_clk_req_n3_funcs[] = { 1 }; - -static int mt7988_pcie_clk_req_n0_1_pins[] = { 10 }; -static int mt7988_pcie_clk_req_n0_1_funcs[] = { 2 }; - -static int mt7988_pcie_p0_phy_i2c_pins[] = { 7, 8 }; -static int mt7988_pcie_p0_phy_i2c_funcs[] = { 3, 3 }; - -static int mt7988_pcie_p1_phy_i2c_pins[] = { 7, 8 }; -static int mt7988_pcie_p1_phy_i2c_funcs[] = { 4, 4 }; - -static int mt7988_pcie_p3_phy_i2c_pins[] = { 9, 10 }; -static int mt7988_pcie_p3_phy_i2c_funcs[] = { 4, 4 }; - -static int mt7988_pcie_p2_phy_i2c_pins[] = { 7, 8 }; -static int mt7988_pcie_p2_phy_i2c_funcs[] = { 5, 5 }; - -static int mt7988_ckm_phy_i2c_pins[] = { 9, 10 }; -static int mt7988_ckm_phy_i2c_funcs[] = { 5, 5 }; - -static int mt7988_pcie_wake_n0_1_pins[] = { 13 }; -static int mt7988_pcie_wake_n0_1_funcs[] = { 2 }; - -static int mt7988_pcie_wake_n3_1_pins[] = { 14 }; -static int mt7988_pcie_wake_n3_1_funcs[] = { 2 }; - -static int mt7988_pcie_2l_0_pereset_pins[] = { 19 }; -static int mt7988_pcie_2l_0_pereset_funcs[] = { 1 }; - -static int mt7988_pcie_1l_1_pereset_pins[] = { 20 }; -static int mt7988_pcie_1l_1_pereset_funcs[] = { 1 }; - -static int mt7988_pcie_clk_req_n2_1_pins[] = { 63 }; -static int mt7988_pcie_clk_req_n2_1_funcs[] = { 2 }; - -static int mt7988_pcie_2l_1_pereset_pins[] = { 73 }; -static int mt7988_pcie_2l_1_pereset_funcs[] = { 1 }; - -static int mt7988_pcie_1l_0_pereset_pins[] = { 74 }; -static int mt7988_pcie_1l_0_pereset_funcs[] = { 1 }; - -static int mt7988_pcie_wake_n1_0_pins[] = { 75 }; -static int mt7988_pcie_wake_n1_0_funcs[] = { 1 }; - -static int mt7988_pcie_clk_req_n1_pins[] = { 76 }; -static int mt7988_pcie_clk_req_n1_funcs[] = { 1 }; - -static int mt7988_pcie_wake_n2_0_pins[] = { 77 }; -static int mt7988_pcie_wake_n2_0_funcs[] = { 1 }; - -static int mt7988_pcie_clk_req_n2_0_pins[] = { 78 }; -static int mt7988_pcie_clk_req_n2_0_funcs[] = { 1 }; - -static int mt7988_pcie_wake_n2_1_pins[] = { 79 }; -static int mt7988_pcie_wake_n2_1_funcs[] = { 2 }; - -/* pmic */ -static int mt7988_pmic_pins[] = { 11 }; -static int mt7988_pmic_funcs[] = { 1 }; - -/* watchdog */ -static int mt7988_watchdog_pins[] = { 12 }; -static int mt7988_watchdog_funcs[] = { 1 }; - -/* spi */ -static int mt7988_spi0_wp_hold_pins[] = { 22, 23 }; -static int mt7988_spi0_wp_hold_funcs[] = { 1, 1 }; - -static int mt7988_spi0_pins[] = { 24, 25, 26, 27 }; -static int mt7988_spi0_funcs[] = { 1, 1, 1, 1 }; - -static int mt7988_spi1_pins[] = { 28, 29, 30, 31 }; -static int mt7988_spi1_funcs[] = { 1, 1, 1, 1 }; - -static int mt7988_spi2_pins[] = { 32, 33, 34, 35 }; -static int mt7988_spi2_funcs[] = { 1, 1, 1, 1 }; - -static int mt7988_spi2_wp_hold_pins[] = { 36, 37 }; -static int mt7988_spi2_wp_hold_funcs[] = { 1, 1 }; - -/* flash */ -static int mt7988_snfi_pins[] = { 22, 23, 24, 25, 26, 27 }; -static int mt7988_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 }; - -static int mt7988_emmc_45_pins[] = { - 21, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37 -}; -static int mt7988_emmc_45_funcs[] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 }; - -static int mt7988_sdcard_pins[] = { 32, 33, 34, 35, 36, 37 }; -static int mt7988_sdcard_funcs[] = { 5, 5, 5, 5, 5, 5 }; - -static int mt7988_emmc_51_pins[] = { 38, 39, 40, 41, 42, 43, - 44, 45, 46, 47, 48, 49 }; -static int mt7988_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; - -/* uart */ -static int mt7988_uart2_pins[] = { 0, 1, 2, 3 }; -static int mt7988_uart2_funcs[] = { 1, 1, 1, 1 }; - -static int mt7988_tops_uart0_0_pins[] = { 22, 23 }; -static int mt7988_tops_uart0_0_funcs[] = { 3, 3 }; - -static int mt7988_uart2_0_pins[] = { 28, 29, 30, 31 }; -static int mt7988_uart2_0_funcs[] = { 2, 2, 2, 2 }; - -static int mt7988_uart1_0_pins[] = { 32, 33, 34, 35 }; -static int mt7988_uart1_0_funcs[] = { 2, 2, 2, 2 }; - -static int mt7988_uart2_1_pins[] = { 32, 33, 34, 35 }; -static int mt7988_uart2_1_funcs[] = { 3, 3, 3, 3 }; - -static int mt7988_net_wo0_uart_txd_0_pins[] = { 28 }; -static int mt7988_net_wo0_uart_txd_0_funcs[] = { 3 }; - -static int mt7988_net_wo1_uart_txd_0_pins[] = { 29 }; -static int mt7988_net_wo1_uart_txd_0_funcs[] = { 3 }; - -static int mt7988_net_wo2_uart_txd_0_pins[] = { 30 }; -static int mt7988_net_wo2_uart_txd_0_funcs[] = { 3 }; - -static int mt7988_tops_uart1_0_pins[] = { 28, 29 }; -static int mt7988_tops_uart1_0_funcs[] = { 4, 4 }; - -static int mt7988_tops_uart0_1_pins[] = { 30, 31 }; -static int mt7988_tops_uart0_1_funcs[] = { 4, 4 }; - -static int mt7988_tops_uart1_1_pins[] = { 36, 37 }; -static int mt7988_tops_uart1_1_funcs[] = { 3, 3 }; - -static int mt7988_uart0_pins[] = { 55, 56 }; -static int mt7988_uart0_funcs[] = { 1, 1 }; - -static int mt7988_tops_uart0_2_pins[] = { 55, 56 }; -static int mt7988_tops_uart0_2_funcs[] = { 2, 2 }; - -static int mt7988_uart2_2_pins[] = { 50, 51, 52, 53 }; -static int mt7988_uart2_2_funcs[] = { 2, 2, 2, 2 }; - -static int mt7988_uart1_1_pins[] = { 58, 59, 60, 61 }; -static int mt7988_uart1_1_funcs[] = { 2, 2, 2, 2 }; - -static int mt7988_uart2_3_pins[] = { 58, 59, 60, 61 }; -static int mt7988_uart2_3_funcs[] = { 3, 3, 3, 3 }; - -static int mt7988_uart1_2_pins[] = { 80, 81, 82, 83 }; -static int mt7988_uart1_2_funcs[] = { 1, 1, 1, 1 }; - -static int mt7988_uart1_2_lite_pins[] = { 80, 81 }; -static int mt7988_uart1_2_lite_funcs[] = { 1, 1 }; - -static int mt7988_tops_uart1_2_pins[] = { 80, 81 }; -static int mt7988_tops_uart1_2_funcs[] = { 4, 4, }; - -static int mt7988_net_wo0_uart_txd_1_pins[] = { 80 }; -static int mt7988_net_wo0_uart_txd_1_funcs[] = { 3 }; - -static int mt7988_net_wo1_uart_txd_1_pins[] = { 81 }; -static int mt7988_net_wo1_uart_txd_1_funcs[] = { 3 }; - -static int mt7988_net_wo2_uart_txd_1_pins[] = { 82 }; -static int mt7988_net_wo2_uart_txd_1_funcs[] = { 3 }; - -/* udi */ -static int mt7988_udi_pins[] = { 32, 33, 34, 35, 36 }; -static int mt7988_udi_funcs[] = { 4, 4, 4, 4, 4 }; - -/* i2s */ -static int mt7988_i2s_pins[] = { 50, 51, 52, 53, 54 }; -static int mt7988_i2s_funcs[] = { 1, 1, 1, 1, 1 }; - -/* pcm */ -static int mt7988_pcm_pins[] = { 50, 51, 52, 53 }; -static int mt7988_pcm_funcs[] = { 1, 1, 1, 1 }; - -/* led */ -static int mt7988_gbe0_led1_pins[] = { 58 }; -static int mt7988_gbe0_led1_funcs[] = { 6 }; -static int mt7988_gbe1_led1_pins[] = { 59 }; -static int mt7988_gbe1_led1_funcs[] = { 6 }; -static int mt7988_gbe2_led1_pins[] = { 60 }; -static int mt7988_gbe2_led1_funcs[] = { 6 }; -static int mt7988_gbe3_led1_pins[] = { 61 }; -static int mt7988_gbe3_led1_funcs[] = { 6 }; - -static int mt7988_2p5gbe_led1_pins[] = { 62 }; -static int mt7988_2p5gbe_led1_funcs[] = { 6 }; - -static int mt7988_gbe0_led0_pins[] = { 64 }; -static int mt7988_gbe0_led0_funcs[] = { 1 }; -static int mt7988_gbe1_led0_pins[] = { 65 }; -static int mt7988_gbe1_led0_funcs[] = { 1 }; -static int mt7988_gbe2_led0_pins[] = { 66 }; -static int mt7988_gbe2_led0_funcs[] = { 1 }; -static int mt7988_gbe3_led0_pins[] = { 67 }; -static int mt7988_gbe3_led0_funcs[] = { 1 }; - -static int mt7988_2p5gbe_led0_pins[] = { 68 }; -static int mt7988_2p5gbe_led0_funcs[] = { 1 }; - -/* usb */ -static int mt7988_drv_vbus_p1_pins[] = { 63 }; -static int mt7988_drv_vbus_p1_funcs[] = { 1 }; - -static int mt7988_drv_vbus_pins[] = { 79 }; -static int mt7988_drv_vbus_funcs[] = { 1 }; - -static const struct group_desc mt7988_groups[] = { - /* @GPIO(0,1,2,3): uart2 */ - PINCTRL_PIN_GROUP("uart2", mt7988_uart2), - /* @GPIO(0,1,2,3,4): tops_jtag0_0 */ - PINCTRL_PIN_GROUP("tops_jtag0_0", mt7988_tops_jtag0_0), - /* @GPIO(2,3): int_usxgmii */ - PINCTRL_PIN_GROUP("int_usxgmii", mt7988_int_usxgmii), - /* @GPIO(0,1,2,3,4): dfd */ - PINCTRL_PIN_GROUP("dfd", mt7988_dfd), - /* @GPIO(0,1): xfi_phy0_i2c0 */ - PINCTRL_PIN_GROUP("xfi_phy0_i2c0", mt7988_xfi_phy0_i2c0), - /* @GPIO(0,1): xfi_phy1_i2c0 */ - PINCTRL_PIN_GROUP("xfi_phy1_i2c0", mt7988_xfi_phy1_i2c0), - /* @GPIO(3,4): xfi_phy_pll_i2c0 */ - PINCTRL_PIN_GROUP("xfi_phy_pll_i2c0", mt7988_xfi_phy_pll_i2c0), - /* @GPIO(3,4): xfi_phy_pll_i2c1 */ - PINCTRL_PIN_GROUP("xfi_phy_pll_i2c1", mt7988_xfi_phy_pll_i2c1), - /* @GPIO(4): pwm7 */ - PINCTRL_PIN_GROUP("pwm7_0", mt7988_pwm7_0), - /* @GPIO(5,6) i2c0_0 */ - PINCTRL_PIN_GROUP("i2c0_0", mt7988_i2c0_0), - /* @GPIO(5,6) i2c1_sfp */ - PINCTRL_PIN_GROUP("i2c1_sfp", mt7988_i2c1_sfp), - /* @GPIO(5,6) xfi_pextp_phy0_i2c */ - PINCTRL_PIN_GROUP("xfi_pextp_phy0_i2c", mt7988_xfi_pextp_phy0_i2c), - /* @GPIO(5,6) xfi_pextp_phy1_i2c */ - PINCTRL_PIN_GROUP("xfi_pextp_phy1_i2c", mt7988_xfi_pextp_phy1_i2c), - /* @GPIO(5,6) mdc_mdio0 */ - PINCTRL_PIN_GROUP("mdc_mdio0", mt7988_mdc_mdio0), - /* @GPIO(7): pcie_wake_n0_0 */ - PINCTRL_PIN_GROUP("pcie_wake_n0_0", mt7988_pcie_wake_n0_0), - /* @GPIO(8): pcie_clk_req_n0_0 */ - PINCTRL_PIN_GROUP("pcie_clk_req_n0_0", mt7988_pcie_clk_req_n0_0), - /* @GPIO(9): pcie_wake_n3_0 */ - PINCTRL_PIN_GROUP("pcie_wake_n3_0", mt7988_pcie_wake_n3_0), - /* @GPIO(10): pcie_clk_req_n3 */ - PINCTRL_PIN_GROUP("pcie_clk_req_n3", mt7988_pcie_clk_req_n3), - /* @GPIO(10): pcie_clk_req_n0_1 */ - PINCTRL_PIN_GROUP("pcie_clk_req_n0_1", mt7988_pcie_clk_req_n0_1), - /* @GPIO(7,8) pcie_p0_phy_i2c */ - PINCTRL_PIN_GROUP("pcie_p0_phy_i2c", mt7988_pcie_p0_phy_i2c), - /* @GPIO(7,8) pcie_p1_phy_i2c */ - PINCTRL_PIN_GROUP("pcie_p1_phy_i2c", mt7988_pcie_p1_phy_i2c), - /* @GPIO(7,8) pcie_p2_phy_i2c */ - PINCTRL_PIN_GROUP("pcie_p2_phy_i2c", mt7988_pcie_p2_phy_i2c), - /* @GPIO(9,10) pcie_p3_phy_i2c */ - PINCTRL_PIN_GROUP("pcie_p3_phy_i2c", mt7988_pcie_p3_phy_i2c), - /* @GPIO(9,10) ckm_phy_i2c */ - PINCTRL_PIN_GROUP("ckm_phy_i2c", mt7988_ckm_phy_i2c), - /* @GPIO(11): pmic */ - PINCTRL_PIN_GROUP("pcie_pmic", mt7988_pmic), - /* @GPIO(12): watchdog */ - PINCTRL_PIN_GROUP("watchdog", mt7988_watchdog), - /* @GPIO(13): pcie_wake_n0_1 */ - PINCTRL_PIN_GROUP("pcie_wake_n0_1", mt7988_pcie_wake_n0_1), - /* @GPIO(14): pcie_wake_n3_1 */ - PINCTRL_PIN_GROUP("pcie_wake_n3_1", mt7988_pcie_wake_n3_1), - /* @GPIO(15,16) i2c0_1 */ - PINCTRL_PIN_GROUP("i2c0_1", mt7988_i2c0_1), - /* @GPIO(15,16) u30_phy_i2c0 */ - PINCTRL_PIN_GROUP("u30_phy_i2c0", mt7988_u30_phy_i2c0), - /* @GPIO(15,16) u32_phy_i2c0 */ - PINCTRL_PIN_GROUP("u32_phy_i2c0", mt7988_u32_phy_i2c0), - /* @GPIO(15,16) xfi_phy0_i2c1 */ - PINCTRL_PIN_GROUP("xfi_phy0_i2c1", mt7988_xfi_phy0_i2c1), - /* @GPIO(15,16) xfi_phy1_i2c1 */ - PINCTRL_PIN_GROUP("xfi_phy1_i2c1", mt7988_xfi_phy1_i2c1), - /* @GPIO(15,16) xfi_phy_pll_i2c2 */ - PINCTRL_PIN_GROUP("xfi_phy_pll_i2c2", mt7988_xfi_phy_pll_i2c2), - /* @GPIO(17,18) i2c1_0 */ - PINCTRL_PIN_GROUP("i2c1_0", mt7988_i2c1_0), - /* @GPIO(17,18) u30_phy_i2c1 */ - PINCTRL_PIN_GROUP("u30_phy_i2c1", mt7988_u30_phy_i2c1), - /* @GPIO(17,18) u32_phy_i2c1 */ - PINCTRL_PIN_GROUP("u32_phy_i2c1", mt7988_u32_phy_i2c1), - /* @GPIO(17,18) xfi_phy_pll_i2c3 */ - PINCTRL_PIN_GROUP("xfi_phy_pll_i2c3", mt7988_xfi_phy_pll_i2c3), - /* @GPIO(17,18) sgmii0_i2c */ - PINCTRL_PIN_GROUP("sgmii0_i2c", mt7988_sgmii0_i2c), - /* @GPIO(17,18) sgmii1_i2c */ - PINCTRL_PIN_GROUP("sgmii1_i2c", mt7988_sgmii1_i2c), - /* @GPIO(19): pcie_2l_0_pereset */ - PINCTRL_PIN_GROUP("pcie_2l_0_pereset", mt7988_pcie_2l_0_pereset), - /* @GPIO(20): pcie_1l_1_pereset */ - PINCTRL_PIN_GROUP("pcie_1l_1_pereset", mt7988_pcie_1l_1_pereset), - /* @GPIO(21): pwm1 */ - PINCTRL_PIN_GROUP("pwm1", mt7988_pwm1), - /* @GPIO(22,23) spi0_wp_hold */ - PINCTRL_PIN_GROUP("spi0_wp_hold", mt7988_spi0_wp_hold), - /* @GPIO(24,25,26,27) spi0 */ - PINCTRL_PIN_GROUP("spi0", mt7988_spi0), - /* @GPIO(28,29,30,31) spi1 */ - PINCTRL_PIN_GROUP("spi1", mt7988_spi1), - /* @GPIO(32,33,34,35) spi2 */ - PINCTRL_PIN_GROUP("spi2", mt7988_spi2), - /* @GPIO(36,37) spi2_wp_hold */ - PINCTRL_PIN_GROUP("spi2_wp_hold", mt7988_spi2_wp_hold), - /* @GPIO(22,23,24,25,26,27) snfi */ - PINCTRL_PIN_GROUP("snfi", mt7988_snfi), - /* @GPIO(22,23) tops_uart0_0 */ - PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart0_0), - /* @GPIO(28,29,30,31) uart2_0 */ - PINCTRL_PIN_GROUP("uart2_0", mt7988_uart2_0), - /* @GPIO(32,33,34,35) uart1_0 */ - PINCTRL_PIN_GROUP("uart1_0", mt7988_uart1_0), - /* @GPIO(32,33,34,35) uart2_1 */ - PINCTRL_PIN_GROUP("uart2_1", mt7988_uart2_1), - /* @GPIO(28) net_wo0_uart_txd_0 */ - PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0), - /* @GPIO(29) net_wo1_uart_txd_0 */ - PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0), - /* @GPIO(30) net_wo2_uart_txd_0 */ - PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0), - /* @GPIO(28,29) tops_uart1_0 */ - PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart1_0), - /* @GPIO(30,31) tops_uart0_1 */ - PINCTRL_PIN_GROUP("tops_uart0_1", mt7988_tops_uart0_1), - /* @GPIO(36,37) tops_uart1_1 */ - PINCTRL_PIN_GROUP("tops_uart1_1", mt7988_tops_uart1_1), - /* @GPIO(32,33,34,35,36) udi */ - PINCTRL_PIN_GROUP("udi", mt7988_udi), - /* @GPIO(21,28,29,30,31,32,33,34,35,36,37) emmc_45 */ - PINCTRL_PIN_GROUP("emmc_45", mt7988_emmc_45), - /* @GPIO(32,33,34,35,36,37) sdcard */ - PINCTRL_PIN_GROUP("sdcard", mt7988_sdcard), - /* @GPIO(38,39,40,41,42,43,44,45,46,47,48,49) emmc_51 */ - PINCTRL_PIN_GROUP("emmc_51", mt7988_emmc_51), - /* @GPIO(28,29) 2p5g_ext_mdio */ - PINCTRL_PIN_GROUP("2p5g_ext_mdio", mt7988_2p5g_ext_mdio), - /* @GPIO(30,31) gbe_ext_mdio */ - PINCTRL_PIN_GROUP("gbe_ext_mdio", mt7988_gbe_ext_mdio), - /* @GPIO(50,51,52,53,54) i2s */ - PINCTRL_PIN_GROUP("i2s", mt7988_i2s), - /* @GPIO(50,51,52,53) pcm */ - PINCTRL_PIN_GROUP("pcm", mt7988_pcm), - /* @GPIO(55,56) uart0 */ - PINCTRL_PIN_GROUP("uart0", mt7988_uart0), - /* @GPIO(55,56) tops_uart0_2 */ - PINCTRL_PIN_GROUP("tops_uart0_2", mt7988_tops_uart0_2), - /* @GPIO(50,51,52,53) uart2_2 */ - PINCTRL_PIN_GROUP("uart2_2", mt7988_uart2_2), - /* @GPIO(50,51,52,53,54) wo0_jtag */ - PINCTRL_PIN_GROUP("wo0_jtag", mt7988_wo0_jtag), - /* @GPIO(50,51,52,53,54) wo1-wo1_jtag */ - PINCTRL_PIN_GROUP("wo1_jtag", mt7988_wo1_jtag), - /* @GPIO(50,51,52,53,54) wo2_jtag */ - PINCTRL_PIN_GROUP("wo2_jtag", mt7988_wo2_jtag), - /* @GPIO(57) pwm0 */ - PINCTRL_PIN_GROUP("pwm0", mt7988_pwm0), - /* @GPIO(58) pwm2_0 */ - PINCTRL_PIN_GROUP("pwm2_0", mt7988_pwm2_0), - /* @GPIO(59) pwm3_0 */ - PINCTRL_PIN_GROUP("pwm3_0", mt7988_pwm3_0), - /* @GPIO(60) pwm4_0 */ - PINCTRL_PIN_GROUP("pwm4_0", mt7988_pwm4_0), - /* @GPIO(61) pwm5_0 */ - PINCTRL_PIN_GROUP("pwm5_0", mt7988_pwm5_0), - /* @GPIO(58,59,60,61,62) jtag */ - PINCTRL_PIN_GROUP("jtag", mt7988_jtag), - /* @GPIO(58,59,60,61,62) tops_jtag0_1 */ - PINCTRL_PIN_GROUP("tops_jtag0_1", mt7988_tops_jtag0_1), - /* @GPIO(58,59,60,61) uart2_3 */ - PINCTRL_PIN_GROUP("uart2_3", mt7988_uart2_3), - /* @GPIO(58,59,60,61) uart1_1 */ - PINCTRL_PIN_GROUP("uart1_1", mt7988_uart1_1), - /* @GPIO(58,59,60,61) gbe_led1 */ - PINCTRL_PIN_GROUP("gbe0_led1", mt7988_gbe0_led1), - PINCTRL_PIN_GROUP("gbe1_led1", mt7988_gbe1_led1), - PINCTRL_PIN_GROUP("gbe2_led1", mt7988_gbe2_led1), - PINCTRL_PIN_GROUP("gbe3_led1", mt7988_gbe3_led1), - /* @GPIO(62) pwm6_0 */ - PINCTRL_PIN_GROUP("pwm6_0", mt7988_pwm6_0), - /* @GPIO(62) 2p5gbe_led1 */ - PINCTRL_PIN_GROUP("2p5gbe_led1", mt7988_2p5gbe_led1), - /* @GPIO(64,65,66,67) gbe_led0 */ - PINCTRL_PIN_GROUP("gbe0_led0", mt7988_gbe0_led0), - PINCTRL_PIN_GROUP("gbe1_led0", mt7988_gbe1_led0), - PINCTRL_PIN_GROUP("gbe2_led0", mt7988_gbe2_led0), - PINCTRL_PIN_GROUP("gbe3_led0", mt7988_gbe3_led0), - /* @GPIO(68) 2p5gbe_led0 */ - PINCTRL_PIN_GROUP("2p5gbe_led0", mt7988_2p5gbe_led0), - /* @GPIO(63) drv_vbus_p1 */ - PINCTRL_PIN_GROUP("drv_vbus_p1", mt7988_drv_vbus_p1), - /* @GPIO(63) pcie_clk_req_n2_1 */ - PINCTRL_PIN_GROUP("pcie_clk_req_n2_1", mt7988_pcie_clk_req_n2_1), - /* @GPIO(69, 70) mdc_mdio1 */ - PINCTRL_PIN_GROUP("mdc_mdio1", mt7988_mdc_mdio1), - /* @GPIO(69, 70) i2c1_2 */ - PINCTRL_PIN_GROUP("i2c1_2", mt7988_i2c1_2), - /* @GPIO(69) pwm6 */ - PINCTRL_PIN_GROUP("pwm6", mt7988_pwm6), - /* @GPIO(70) pwm7 */ - PINCTRL_PIN_GROUP("pwm7", mt7988_pwm7), - /* @GPIO(69,70) i2c2_0 */ - PINCTRL_PIN_GROUP("i2c2_0", mt7988_i2c2_0), - /* @GPIO(71,72) i2c2_1 */ - PINCTRL_PIN_GROUP("i2c2_1", mt7988_i2c2_1), - /* @GPIO(73) pcie_2l_1_pereset */ - PINCTRL_PIN_GROUP("pcie_2l_1_pereset", mt7988_pcie_2l_1_pereset), - /* @GPIO(74) pcie_1l_0_pereset */ - PINCTRL_PIN_GROUP("pcie_1l_0_pereset", mt7988_pcie_1l_0_pereset), - /* @GPIO(75) pcie_wake_n1_0 */ - PINCTRL_PIN_GROUP("pcie_wake_n1_0", mt7988_pcie_wake_n1_0), - /* @GPIO(76) pcie_clk_req_n1 */ - PINCTRL_PIN_GROUP("pcie_clk_req_n1", mt7988_pcie_clk_req_n1), - /* @GPIO(77) pcie_wake_n2_0 */ - PINCTRL_PIN_GROUP("pcie_wake_n2_0", mt7988_pcie_wake_n2_0), - /* @GPIO(78) pcie_clk_req_n2_0 */ - PINCTRL_PIN_GROUP("pcie_clk_req_n2_0", mt7988_pcie_clk_req_n2_0), - /* @GPIO(79) drv_vbus */ - PINCTRL_PIN_GROUP("drv_vbus", mt7988_drv_vbus), - /* @GPIO(79) pcie_wake_n2_1 */ - PINCTRL_PIN_GROUP("pcie_wake_n2_1", mt7988_pcie_wake_n2_1), - /* @GPIO(80,81,82,83) uart1_2 */ - PINCTRL_PIN_GROUP("uart1_2", mt7988_uart1_2), - /* @GPIO(80,81) uart1_2_lite */ - PINCTRL_PIN_GROUP("uart1_2_lite", mt7988_uart1_2_lite), - /* @GPIO(80) pwm2 */ - PINCTRL_PIN_GROUP("pwm2", mt7988_pwm2), - /* @GPIO(81) pwm3 */ - PINCTRL_PIN_GROUP("pwm3", mt7988_pwm3), - /* @GPIO(82) pwm4 */ - PINCTRL_PIN_GROUP("pwm4", mt7988_pwm4), - /* @GPIO(83) pwm5 */ - PINCTRL_PIN_GROUP("pwm5", mt7988_pwm5), - /* @GPIO(80) net_wo0_uart_txd_0 */ - PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0), - /* @GPIO(81) net_wo1_uart_txd_0 */ - PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0), - /* @GPIO(82) net_wo2_uart_txd_0 */ - PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0), - /* @GPIO(80,81) tops_uart1_2 */ - PINCTRL_PIN_GROUP("tops_uart1_2", mt7988_tops_uart1_2), - /* @GPIO(80) net_wo0_uart_txd_1 */ - PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7988_net_wo0_uart_txd_1), - /* @GPIO(81) net_wo1_uart_txd_1 */ - PINCTRL_PIN_GROUP("net_wo1_uart_txd_1", mt7988_net_wo1_uart_txd_1), - /* @GPIO(82) net_wo2_uart_txd_1 */ - PINCTRL_PIN_GROUP("net_wo2_uart_txd_1", mt7988_net_wo2_uart_txd_1), -}; - -/* Joint those groups owning the same capability in user point of view which - * allows that people tend to use through the device tree. - */ -static const char * const mt7988_jtag_groups[] = { - "tops_jtag0_0", "wo0_jtag", "wo1_jtag", - "wo2_jtag", "jtag", "tops_jtag0_1", -}; -static const char * const mt7988_int_usxgmii_groups[] = { - "int_usxgmii", -}; -static const char * const mt7988_pwm_groups[] = { - "pwm0", "pwm1", "pwm2", "pwm2_0", "pwm3", "pwm3_0", "pwm4", "pwm4_0", - "pwm5", "pwm5_0", "pwm6", "pwm6_0", "pwm7", "pwm7_0", -}; -static const char * const mt7988_dfd_groups[] = { - "dfd", -}; -static const char * const mt7988_i2c_groups[] = { - "xfi_phy0_i2c0", - "xfi_phy1_i2c0", - "xfi_phy_pll_i2c0", - "xfi_phy_pll_i2c1", - "i2c0_0", - "i2c1_sfp", - "xfi_pextp_phy0_i2c", - "xfi_pextp_phy1_i2c", - "i2c0_1", - "u30_phy_i2c0", - "u32_phy_i2c0", - "xfi_phy0_i2c1", - "xfi_phy1_i2c1", - "xfi_phy_pll_i2c2", - "i2c1_0", - "u30_phy_i2c1", - "u32_phy_i2c1", - "xfi_phy_pll_i2c3", - "sgmii0_i2c", - "sgmii1_i2c", - "i2c1_2", - "i2c2_0", - "i2c2_1", -}; -static const char * const mt7988_ethernet_groups[] = { - "mdc_mdio0", - "2p5g_ext_mdio", - "gbe_ext_mdio", - "mdc_mdio1", -}; -static const char * const mt7988_pcie_groups[] = { - "pcie_wake_n0_0", "pcie_clk_req_n0_0", "pcie_wake_n3_0", - "pcie_clk_req_n3", "pcie_p0_phy_i2c", "pcie_p1_phy_i2c", - "pcie_p3_phy_i2c", "pcie_p2_phy_i2c", "ckm_phy_i2c", - "pcie_wake_n0_1", "pcie_wake_n3_1", "pcie_2l_0_pereset", - "pcie_1l_1_pereset", "pcie_clk_req_n2_1", "pcie_2l_1_pereset", - "pcie_1l_0_pereset", "pcie_wake_n1_0", "pcie_clk_req_n1", - "pcie_wake_n2_0", "pcie_clk_req_n2_0", "pcie_wake_n2_1", - "pcie_clk_req_n0_1" -}; -static const char * const mt7988_pmic_groups[] = { - "pmic", -}; -static const char * const mt7988_wdt_groups[] = { - "watchdog", -}; -static const char * const mt7988_spi_groups[] = { - "spi0", "spi0_wp_hold", "spi1", "spi2", "spi2_wp_hold", -}; -static const char * const mt7988_flash_groups[] = { "emmc_45", "sdcard", "snfi", - "emmc_51" }; -static const char * const mt7988_uart_groups[] = { - "uart2", - "tops_uart0_0", - "uart2_0", - "uart1_0", - "uart2_1", - "net_wo0_uart_txd_0", - "net_wo1_uart_txd_0", - "net_wo2_uart_txd_0", - "tops_uart1_0", - "ops_uart0_1", - "ops_uart1_1", - "uart0", - "tops_uart0_2", - "uart1_1", - "uart2_3", - "uart1_2", - "uart1_2_lite", - "tops_uart1_2", - "net_wo0_uart_txd_1", - "net_wo1_uart_txd_1", - "net_wo2_uart_txd_1", -}; -static const char * const mt7988_udi_groups[] = { - "udi", -}; -static const char * const mt7988_audio_groups[] = { - "i2s", "pcm", -}; -static const char * const mt7988_led_groups[] = { - "gbe0_led1", "gbe1_led1", "gbe2_led1", "gbe3_led1", "2p5gbe_led1", - "gbe0_led0", "gbe1_led0", "gbe2_led0", "gbe3_led0", "2p5gbe_led0", - "wf5g_led0", "wf5g_led1", -}; -static const char * const mt7988_usb_groups[] = { - "drv_vbus", - "drv_vbus_p1", -}; - -static const struct function_desc mt7988_functions[] = { - { "audio", mt7988_audio_groups, ARRAY_SIZE(mt7988_audio_groups) }, - { "jtag", mt7988_jtag_groups, ARRAY_SIZE(mt7988_jtag_groups) }, - { "int_usxgmii", mt7988_int_usxgmii_groups, - ARRAY_SIZE(mt7988_int_usxgmii_groups) }, - { "pwm", mt7988_pwm_groups, ARRAY_SIZE(mt7988_pwm_groups) }, - { "dfd", mt7988_dfd_groups, ARRAY_SIZE(mt7988_dfd_groups) }, - { "i2c", mt7988_i2c_groups, ARRAY_SIZE(mt7988_i2c_groups) }, - { "eth", mt7988_ethernet_groups, ARRAY_SIZE(mt7988_ethernet_groups) }, - { "pcie", mt7988_pcie_groups, ARRAY_SIZE(mt7988_pcie_groups) }, - { "pmic", mt7988_pmic_groups, ARRAY_SIZE(mt7988_pmic_groups) }, - { "watchdog", mt7988_wdt_groups, ARRAY_SIZE(mt7988_wdt_groups) }, - { "spi", mt7988_spi_groups, ARRAY_SIZE(mt7988_spi_groups) }, - { "flash", mt7988_flash_groups, ARRAY_SIZE(mt7988_flash_groups) }, - { "uart", mt7988_uart_groups, ARRAY_SIZE(mt7988_uart_groups) }, - { "udi", mt7988_udi_groups, ARRAY_SIZE(mt7988_udi_groups) }, - { "usb", mt7988_usb_groups, ARRAY_SIZE(mt7988_usb_groups) }, - { "led", mt7988_led_groups, ARRAY_SIZE(mt7988_led_groups) }, -}; - -static const struct mtk_eint_hw mt7988_eint_hw = { - .port_mask = 7, - .ports = 7, - .ap_num = ARRAY_SIZE(mt7988_pins), - .db_cnt = 16, -}; - -static const char * const mt7988_pinctrl_register_base_names[] = { - "gpio_base", "iocfg_tr_base", "iocfg_br_base", - "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base", -}; - -static struct mtk_pin_soc mt7988_data = { - .reg_cal = mt7988_reg_cals, - .pins = mt7988_pins, - .npins = ARRAY_SIZE(mt7988_pins), - .grps = mt7988_groups, - .ngrps = ARRAY_SIZE(mt7988_groups), - .funcs = mt7988_functions, - .nfuncs = ARRAY_SIZE(mt7988_functions), - .eint_hw = &mt7988_eint_hw, - .gpio_m = 0, - .ies_present = false, - .base_names = mt7988_pinctrl_register_base_names, - .nbase_names = ARRAY_SIZE(mt7988_pinctrl_register_base_names), - .bias_disable_set = mtk_pinconf_bias_disable_set, - .bias_disable_get = mtk_pinconf_bias_disable_get, - .bias_set = mtk_pinconf_bias_set, - .bias_get = mtk_pinconf_bias_get, - .pull_type = mt7988_pull_type, - .bias_set_combo = mtk_pinconf_bias_set_combo, - .bias_get_combo = mtk_pinconf_bias_get_combo, - .drive_set = mtk_pinconf_drive_set_rev1, - .drive_get = mtk_pinconf_drive_get_rev1, - .adv_pull_get = mtk_pinconf_adv_pull_get, - .adv_pull_set = mtk_pinconf_adv_pull_set, -}; - -static const struct of_device_id mt7988_pinctrl_of_match[] = { - { - .compatible = "mediatek,mt7988-pinctrl", - }, - {} -}; - -static int mt7988_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_moore_pinctrl_probe(pdev, &mt7988_data); -} - -static struct platform_driver mt7988_pinctrl_driver = { - .driver = { - .name = "mt7988-pinctrl", - .of_match_table = mt7988_pinctrl_of_match, - }, - .probe = mt7988_pinctrl_probe, -}; - -static int __init mt7988_pinctrl_init(void) -{ - return platform_driver_register(&mt7988_pinctrl_driver); -} -arch_initcall(mt7988_pinctrl_init); diff --git a/target/linux/mediatek/patches-6.12/010-v6.14-pinctrl-mediatek-add-support-for-MTK_PULL_PD_TYPE.patch b/target/linux/mediatek/patches-6.12/010-v6.14-pinctrl-mediatek-add-support-for-MTK_PULL_PD_TYPE.patch new file mode 100644 index 00000000000..2dcdbcffe4a --- /dev/null +++ b/target/linux/mediatek/patches-6.12/010-v6.14-pinctrl-mediatek-add-support-for-MTK_PULL_PD_TYPE.patch @@ -0,0 +1,151 @@ +From 1673d720b7e2862a5ff1994922558b7427f8a56b Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Tue, 17 Dec 2024 09:54:26 +0100 +Subject: [PATCH 1/2] pinctrl: mediatek: add support for MTK_PULL_PD_TYPE + +The MediaTek MT7988 SoC got some pins which only got configurable +pull-down but unlike previous designs there is no pull-up option. +Add new type MTK_PULL_PD_TYPE to support configuring such pins. + +Signed-off-by: Daniel Golle +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/20241217085435.9586-2-linux@fw-web.de +Signed-off-by: Linus Walleij +--- + .../pinctrl/mediatek/pinctrl-mtk-common-v2.c | 73 ++++++++++++++++--- + .../pinctrl/mediatek/pinctrl-mtk-common-v2.h | 1 + + 2 files changed, 63 insertions(+), 11 deletions(-) + +--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c +@@ -573,7 +573,7 @@ EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_r + */ + static int mtk_pinconf_bias_set_pu_pd(struct mtk_pinctrl *hw, + const struct mtk_pin_desc *desc, +- u32 pullup, u32 arg) ++ u32 pullup, u32 arg, bool pd_only) + { + int err, pu, pd; + +@@ -587,18 +587,34 @@ static int mtk_pinconf_bias_set_pu_pd(st + pu = 0; + pd = 1; + } else { +- err = -EINVAL; +- goto out; ++ return -EINVAL; + } + +- err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, pu); +- if (err) +- goto out; ++ if (!pd_only) { ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, pu); ++ if (err) ++ return err; ++ } + +- err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd); ++ return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd); ++} ++ ++static int mtk_pinconf_bias_set_pd(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, ++ u32 pullup, u32 arg) ++{ ++ int err, pd; ++ ++ if (arg != MTK_DISABLE && arg != MTK_ENABLE) ++ return -EINVAL; ++ ++ if (arg == MTK_DISABLE || pullup) ++ pd = 0; ++ else if (!pullup) ++ pd = 1; ++ ++ return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd); + +-out: +- return err; + } + + static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw, +@@ -737,7 +753,7 @@ static int mtk_pinconf_bias_set_pu_pd_rs + return err; + } + +- return mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, enable); ++ return mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, enable, false); + } + + int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw, +@@ -758,8 +774,14 @@ int mtk_pinconf_bias_set_combo(struct mt + return 0; + } + ++ if (try_all_type & MTK_PULL_PD_TYPE) { ++ err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg, true); ++ if (!err) ++ return err; ++ } ++ + if (try_all_type & MTK_PULL_PU_PD_TYPE) { +- err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg); ++ err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg, false); + if (!err) + return 0; + } +@@ -878,6 +900,29 @@ out: + return err; + } + ++static int mtk_pinconf_bias_get_pd(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, ++ u32 *pullup, u32 *enable) ++{ ++ int err, pd; ++ ++ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd); ++ if (err) ++ goto out; ++ ++ if (pd == 0) { ++ *pullup = 0; ++ *enable = MTK_DISABLE; ++ } else if (pd == 1) { ++ *pullup = 0; ++ *enable = MTK_ENABLE; ++ } else ++ err = -EINVAL; ++ ++out: ++ return err; ++} ++ + static int mtk_pinconf_bias_get_pullsel_pullen(struct mtk_pinctrl *hw, + const struct mtk_pin_desc *desc, + u32 *pullup, u32 *enable) +@@ -947,6 +992,12 @@ int mtk_pinconf_bias_get_combo(struct mt + return 0; + } + ++ if (try_all_type & MTK_PULL_PD_TYPE) { ++ err = mtk_pinconf_bias_get_pd(hw, desc, pullup, enable); ++ if (!err) ++ return err; ++ } ++ + if (try_all_type & MTK_PULL_PU_PD_TYPE) { + err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable); + if (!err) +--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h ++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h +@@ -24,6 +24,7 @@ + * turned on/off itself. But it can't be selected pull up/down + */ + #define MTK_PULL_RSEL_TYPE BIT(3) ++#define MTK_PULL_PD_TYPE BIT(4) + /* MTK_PULL_PU_PD_RSEL_TYPE is a type which is controlled by + * MTK_PULL_PU_PD_TYPE and MTK_PULL_RSEL_TYPE. + */ diff --git a/target/linux/mediatek/patches-6.12/011-v6.14-pinctrl-mediatek-add-MT7988-pinctrl-driver.patch b/target/linux/mediatek/patches-6.12/011-v6.14-pinctrl-mediatek-add-MT7988-pinctrl-driver.patch new file mode 100644 index 00000000000..d94a0ba60b9 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/011-v6.14-pinctrl-mediatek-add-MT7988-pinctrl-driver.patch @@ -0,0 +1,1610 @@ +From 08bec851118226cc8c4397692542b855de2e0d73 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Tue, 17 Dec 2024 09:54:27 +0100 +Subject: [PATCH 2/2] pinctrl: mediatek: add MT7988 pinctrl driver +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add pinctrl driver for the MediaTek MT7988 SoC. + +Signed-off-by: Sam Shih +Signed-off-by: Daniel Golle +[correctly initialise for the function_desc structure] +Signed-off-by: Arınç ÃœNAL +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/20241217085435.9586-3-linux@fw-web.de +Signed-off-by: Linus Walleij +--- + drivers/pinctrl/mediatek/Kconfig | 7 + + drivers/pinctrl/mediatek/Makefile | 1 + + drivers/pinctrl/mediatek/pinctrl-mt7988.c | 1556 +++++++++++++++++++++ + 3 files changed, 1564 insertions(+) + create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7988.c + +--- a/drivers/pinctrl/mediatek/Kconfig ++++ b/drivers/pinctrl/mediatek/Kconfig +@@ -187,6 +187,13 @@ config PINCTRL_MT7986 + default ARM64 && ARCH_MEDIATEK + select PINCTRL_MTK_MOORE + ++config PINCTRL_MT7988 ++ bool "Mediatek MT7988 pin control" ++ depends on OF ++ depends on ARM64 || COMPILE_TEST ++ default ARM64 && ARCH_MEDIATEK ++ select PINCTRL_MTK_MOORE ++ + config PINCTRL_MT8167 + bool "MediaTek MT8167 pin control" + depends on OF +--- a/drivers/pinctrl/mediatek/Makefile ++++ b/drivers/pinctrl/mediatek/Makefile +@@ -27,6 +27,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl + obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o + obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o + obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o ++obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o + obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o + obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o + obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o +--- /dev/null ++++ b/drivers/pinctrl/mediatek/pinctrl-mt7988.c +@@ -0,0 +1,1556 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * The MT7988 driver based on Linux generic pinctrl binding. ++ * ++ * Copyright (C) 2020 MediaTek Inc. ++ * Author: Sam Shih ++ */ ++ ++#include "pinctrl-moore.h" ++ ++enum mt7988_pinctrl_reg_page { ++ GPIO_BASE, ++ IOCFG_TR_BASE, ++ IOCFG_BR_BASE, ++ IOCFG_RB_BASE, ++ IOCFG_LB_BASE, ++ IOCFG_TL_BASE, ++}; ++ ++#define MT7988_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4) ++ ++#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ ++ _x_bits) \ ++ PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ ++ _x_bits, 32, 0) ++ ++#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ ++ _x_bits) \ ++ PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ ++ _x_bits, 32, 1) ++ ++static const struct mtk_pin_field_calc mt7988_pin_mode_range[] = { ++ PIN_FIELD(0, 83, 0x300, 0x10, 0, 4), ++}; ++ ++static const struct mtk_pin_field_calc mt7988_pin_dir_range[] = { ++ PIN_FIELD(0, 83, 0x0, 0x10, 0, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7988_pin_di_range[] = { ++ PIN_FIELD(0, 83, 0x200, 0x10, 0, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7988_pin_do_range[] = { ++ PIN_FIELD(0, 83, 0x100, 0x10, 0, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = { ++ PIN_FIELD_BASE(0, 0, 5, 0x30, 0x10, 13, 1), ++ PIN_FIELD_BASE(1, 1, 5, 0x30, 0x10, 14, 1), ++ PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 11, 1), ++ PIN_FIELD_BASE(3, 3, 5, 0x30, 0x10, 12, 1), ++ PIN_FIELD_BASE(4, 4, 5, 0x30, 0x10, 0, 1), ++ PIN_FIELD_BASE(5, 5, 5, 0x30, 0x10, 9, 1), ++ PIN_FIELD_BASE(6, 6, 5, 0x30, 0x10, 10, 1), ++ ++ PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 8, 1), ++ PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 6, 1), ++ PIN_FIELD_BASE(9, 9, 4, 0x30, 0x10, 5, 1), ++ PIN_FIELD_BASE(10, 10, 4, 0x30, 0x10, 3, 1), ++ ++ PIN_FIELD_BASE(11, 11, 1, 0x40, 0x10, 0, 1), ++ PIN_FIELD_BASE(12, 12, 1, 0x40, 0x10, 21, 1), ++ PIN_FIELD_BASE(13, 13, 1, 0x40, 0x10, 1, 1), ++ PIN_FIELD_BASE(14, 14, 1, 0x40, 0x10, 2, 1), ++ ++ PIN_FIELD_BASE(15, 15, 5, 0x30, 0x10, 7, 1), ++ PIN_FIELD_BASE(16, 16, 5, 0x30, 0x10, 8, 1), ++ PIN_FIELD_BASE(17, 17, 5, 0x30, 0x10, 3, 1), ++ PIN_FIELD_BASE(18, 18, 5, 0x30, 0x10, 4, 1), ++ ++ PIN_FIELD_BASE(19, 19, 4, 0x30, 0x10, 7, 1), ++ PIN_FIELD_BASE(20, 20, 4, 0x30, 0x10, 4, 1), ++ ++ PIN_FIELD_BASE(21, 21, 3, 0x50, 0x10, 17, 1), ++ PIN_FIELD_BASE(22, 22, 3, 0x50, 0x10, 23, 1), ++ PIN_FIELD_BASE(23, 23, 3, 0x50, 0x10, 20, 1), ++ PIN_FIELD_BASE(24, 24, 3, 0x50, 0x10, 19, 1), ++ PIN_FIELD_BASE(25, 25, 3, 0x50, 0x10, 21, 1), ++ PIN_FIELD_BASE(26, 26, 3, 0x50, 0x10, 22, 1), ++ PIN_FIELD_BASE(27, 27, 3, 0x50, 0x10, 18, 1), ++ PIN_FIELD_BASE(28, 28, 3, 0x50, 0x10, 25, 1), ++ PIN_FIELD_BASE(29, 29, 3, 0x50, 0x10, 26, 1), ++ PIN_FIELD_BASE(30, 30, 3, 0x50, 0x10, 27, 1), ++ PIN_FIELD_BASE(31, 31, 3, 0x50, 0x10, 24, 1), ++ PIN_FIELD_BASE(32, 32, 3, 0x50, 0x10, 28, 1), ++ PIN_FIELD_BASE(33, 33, 3, 0x60, 0x10, 0, 1), ++ PIN_FIELD_BASE(34, 34, 3, 0x50, 0x10, 31, 1), ++ PIN_FIELD_BASE(35, 35, 3, 0x50, 0x10, 29, 1), ++ PIN_FIELD_BASE(36, 36, 3, 0x50, 0x10, 30, 1), ++ PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 1, 1), ++ PIN_FIELD_BASE(38, 38, 3, 0x50, 0x10, 11, 1), ++ PIN_FIELD_BASE(39, 39, 3, 0x50, 0x10, 10, 1), ++ PIN_FIELD_BASE(40, 40, 3, 0x50, 0x10, 0, 1), ++ PIN_FIELD_BASE(41, 41, 3, 0x50, 0x10, 1, 1), ++ PIN_FIELD_BASE(42, 42, 3, 0x50, 0x10, 9, 1), ++ PIN_FIELD_BASE(43, 43, 3, 0x50, 0x10, 8, 1), ++ PIN_FIELD_BASE(44, 44, 3, 0x50, 0x10, 7, 1), ++ PIN_FIELD_BASE(45, 45, 3, 0x50, 0x10, 6, 1), ++ PIN_FIELD_BASE(46, 46, 3, 0x50, 0x10, 5, 1), ++ PIN_FIELD_BASE(47, 47, 3, 0x50, 0x10, 4, 1), ++ PIN_FIELD_BASE(48, 48, 3, 0x50, 0x10, 3, 1), ++ PIN_FIELD_BASE(49, 49, 3, 0x50, 0x10, 2, 1), ++ PIN_FIELD_BASE(50, 50, 3, 0x50, 0x10, 15, 1), ++ PIN_FIELD_BASE(51, 51, 3, 0x50, 0x10, 12, 1), ++ PIN_FIELD_BASE(52, 52, 3, 0x50, 0x10, 13, 1), ++ PIN_FIELD_BASE(53, 53, 3, 0x50, 0x10, 14, 1), ++ PIN_FIELD_BASE(54, 54, 3, 0x50, 0x10, 16, 1), ++ ++ PIN_FIELD_BASE(55, 55, 1, 0x40, 0x10, 14, 1), ++ PIN_FIELD_BASE(56, 56, 1, 0x40, 0x10, 15, 1), ++ PIN_FIELD_BASE(57, 57, 1, 0x40, 0x10, 13, 1), ++ PIN_FIELD_BASE(58, 58, 1, 0x40, 0x10, 4, 1), ++ PIN_FIELD_BASE(59, 59, 1, 0x40, 0x10, 5, 1), ++ PIN_FIELD_BASE(60, 60, 1, 0x40, 0x10, 6, 1), ++ PIN_FIELD_BASE(61, 61, 1, 0x40, 0x10, 3, 1), ++ PIN_FIELD_BASE(62, 62, 1, 0x40, 0x10, 7, 1), ++ PIN_FIELD_BASE(63, 63, 1, 0x40, 0x10, 20, 1), ++ PIN_FIELD_BASE(64, 64, 1, 0x40, 0x10, 8, 1), ++ PIN_FIELD_BASE(65, 65, 1, 0x40, 0x10, 9, 1), ++ PIN_FIELD_BASE(66, 66, 1, 0x40, 0x10, 10, 1), ++ PIN_FIELD_BASE(67, 67, 1, 0x40, 0x10, 11, 1), ++ PIN_FIELD_BASE(68, 68, 1, 0x40, 0x10, 12, 1), ++ ++ PIN_FIELD_BASE(69, 69, 5, 0x30, 0x10, 1, 1), ++ PIN_FIELD_BASE(70, 70, 5, 0x30, 0x10, 2, 1), ++ PIN_FIELD_BASE(71, 71, 5, 0x30, 0x10, 5, 1), ++ PIN_FIELD_BASE(72, 72, 5, 0x30, 0x10, 6, 1), ++ ++ PIN_FIELD_BASE(73, 73, 4, 0x30, 0x10, 10, 1), ++ PIN_FIELD_BASE(74, 74, 4, 0x30, 0x10, 1, 1), ++ PIN_FIELD_BASE(75, 75, 4, 0x30, 0x10, 11, 1), ++ PIN_FIELD_BASE(76, 76, 4, 0x30, 0x10, 9, 1), ++ PIN_FIELD_BASE(77, 77, 4, 0x30, 0x10, 2, 1), ++ PIN_FIELD_BASE(78, 78, 4, 0x30, 0x10, 0, 1), ++ PIN_FIELD_BASE(79, 79, 4, 0x30, 0x10, 12, 1), ++ ++ PIN_FIELD_BASE(80, 80, 1, 0x40, 0x10, 18, 1), ++ PIN_FIELD_BASE(81, 81, 1, 0x40, 0x10, 19, 1), ++ PIN_FIELD_BASE(82, 82, 1, 0x40, 0x10, 16, 1), ++ PIN_FIELD_BASE(83, 83, 1, 0x40, 0x10, 17, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = { ++ PIN_FIELD_BASE(0, 0, 5, 0xc0, 0x10, 13, 1), ++ PIN_FIELD_BASE(1, 1, 5, 0xc0, 0x10, 14, 1), ++ PIN_FIELD_BASE(2, 2, 5, 0xc0, 0x10, 11, 1), ++ PIN_FIELD_BASE(3, 3, 5, 0xc0, 0x10, 12, 1), ++ PIN_FIELD_BASE(4, 4, 5, 0xc0, 0x10, 0, 1), ++ PIN_FIELD_BASE(5, 5, 5, 0xc0, 0x10, 9, 1), ++ PIN_FIELD_BASE(6, 6, 5, 0xc0, 0x10, 10, 1), ++ ++ PIN_FIELD_BASE(7, 7, 4, 0xb0, 0x10, 8, 1), ++ PIN_FIELD_BASE(8, 8, 4, 0xb0, 0x10, 6, 1), ++ PIN_FIELD_BASE(9, 9, 4, 0xb0, 0x10, 5, 1), ++ PIN_FIELD_BASE(10, 10, 4, 0xb0, 0x10, 3, 1), ++ ++ PIN_FIELD_BASE(11, 11, 1, 0xe0, 0x10, 0, 1), ++ PIN_FIELD_BASE(12, 12, 1, 0xe0, 0x10, 21, 1), ++ PIN_FIELD_BASE(13, 13, 1, 0xe0, 0x10, 1, 1), ++ PIN_FIELD_BASE(14, 14, 1, 0xe0, 0x10, 2, 1), ++ ++ PIN_FIELD_BASE(15, 15, 5, 0xc0, 0x10, 7, 1), ++ PIN_FIELD_BASE(16, 16, 5, 0xc0, 0x10, 8, 1), ++ PIN_FIELD_BASE(17, 17, 5, 0xc0, 0x10, 3, 1), ++ PIN_FIELD_BASE(18, 18, 5, 0xc0, 0x10, 4, 1), ++ ++ PIN_FIELD_BASE(19, 19, 4, 0xb0, 0x10, 7, 1), ++ PIN_FIELD_BASE(20, 20, 4, 0xb0, 0x10, 4, 1), ++ ++ PIN_FIELD_BASE(21, 21, 3, 0x140, 0x10, 17, 1), ++ PIN_FIELD_BASE(22, 22, 3, 0x140, 0x10, 23, 1), ++ PIN_FIELD_BASE(23, 23, 3, 0x140, 0x10, 20, 1), ++ PIN_FIELD_BASE(24, 24, 3, 0x140, 0x10, 19, 1), ++ PIN_FIELD_BASE(25, 25, 3, 0x140, 0x10, 21, 1), ++ PIN_FIELD_BASE(26, 26, 3, 0x140, 0x10, 22, 1), ++ PIN_FIELD_BASE(27, 27, 3, 0x140, 0x10, 18, 1), ++ PIN_FIELD_BASE(28, 28, 3, 0x140, 0x10, 25, 1), ++ PIN_FIELD_BASE(29, 29, 3, 0x140, 0x10, 26, 1), ++ PIN_FIELD_BASE(30, 30, 3, 0x140, 0x10, 27, 1), ++ PIN_FIELD_BASE(31, 31, 3, 0x140, 0x10, 24, 1), ++ PIN_FIELD_BASE(32, 32, 3, 0x140, 0x10, 28, 1), ++ PIN_FIELD_BASE(33, 33, 3, 0x150, 0x10, 0, 1), ++ PIN_FIELD_BASE(34, 34, 3, 0x140, 0x10, 31, 1), ++ PIN_FIELD_BASE(35, 35, 3, 0x140, 0x10, 29, 1), ++ PIN_FIELD_BASE(36, 36, 3, 0x140, 0x10, 30, 1), ++ PIN_FIELD_BASE(37, 37, 3, 0x150, 0x10, 1, 1), ++ PIN_FIELD_BASE(38, 38, 3, 0x140, 0x10, 11, 1), ++ PIN_FIELD_BASE(39, 39, 3, 0x140, 0x10, 10, 1), ++ PIN_FIELD_BASE(40, 40, 3, 0x140, 0x10, 0, 1), ++ PIN_FIELD_BASE(41, 41, 3, 0x140, 0x10, 1, 1), ++ PIN_FIELD_BASE(42, 42, 3, 0x140, 0x10, 9, 1), ++ PIN_FIELD_BASE(43, 43, 3, 0x140, 0x10, 8, 1), ++ PIN_FIELD_BASE(44, 44, 3, 0x140, 0x10, 7, 1), ++ PIN_FIELD_BASE(45, 45, 3, 0x140, 0x10, 6, 1), ++ PIN_FIELD_BASE(46, 46, 3, 0x140, 0x10, 5, 1), ++ PIN_FIELD_BASE(47, 47, 3, 0x140, 0x10, 4, 1), ++ PIN_FIELD_BASE(48, 48, 3, 0x140, 0x10, 3, 1), ++ PIN_FIELD_BASE(49, 49, 3, 0x140, 0x10, 2, 1), ++ PIN_FIELD_BASE(50, 50, 3, 0x140, 0x10, 15, 1), ++ PIN_FIELD_BASE(51, 51, 3, 0x140, 0x10, 12, 1), ++ PIN_FIELD_BASE(52, 52, 3, 0x140, 0x10, 13, 1), ++ PIN_FIELD_BASE(53, 53, 3, 0x140, 0x10, 14, 1), ++ PIN_FIELD_BASE(54, 54, 3, 0x140, 0x10, 16, 1), ++ ++ PIN_FIELD_BASE(55, 55, 1, 0xe0, 0x10, 14, 1), ++ PIN_FIELD_BASE(56, 56, 1, 0xe0, 0x10, 15, 1), ++ PIN_FIELD_BASE(57, 57, 1, 0xe0, 0x10, 13, 1), ++ PIN_FIELD_BASE(58, 58, 1, 0xe0, 0x10, 4, 1), ++ PIN_FIELD_BASE(59, 59, 1, 0xe0, 0x10, 5, 1), ++ PIN_FIELD_BASE(60, 60, 1, 0xe0, 0x10, 6, 1), ++ PIN_FIELD_BASE(61, 61, 1, 0xe0, 0x10, 3, 1), ++ PIN_FIELD_BASE(62, 62, 1, 0xe0, 0x10, 7, 1), ++ PIN_FIELD_BASE(63, 63, 1, 0xe0, 0x10, 20, 1), ++ PIN_FIELD_BASE(64, 64, 1, 0xe0, 0x10, 8, 1), ++ PIN_FIELD_BASE(65, 65, 1, 0xe0, 0x10, 9, 1), ++ PIN_FIELD_BASE(66, 66, 1, 0xe0, 0x10, 10, 1), ++ PIN_FIELD_BASE(67, 67, 1, 0xe0, 0x10, 11, 1), ++ PIN_FIELD_BASE(68, 68, 1, 0xe0, 0x10, 12, 1), ++ ++ PIN_FIELD_BASE(69, 69, 5, 0xc0, 0x10, 1, 1), ++ PIN_FIELD_BASE(70, 70, 5, 0xc0, 0x10, 2, 1), ++ PIN_FIELD_BASE(71, 71, 5, 0xc0, 0x10, 5, 1), ++ PIN_FIELD_BASE(72, 72, 5, 0xc0, 0x10, 6, 1), ++ ++ PIN_FIELD_BASE(73, 73, 4, 0xb0, 0x10, 10, 1), ++ PIN_FIELD_BASE(74, 74, 4, 0xb0, 0x10, 1, 1), ++ PIN_FIELD_BASE(75, 75, 4, 0xb0, 0x10, 11, 1), ++ PIN_FIELD_BASE(76, 76, 4, 0xb0, 0x10, 9, 1), ++ PIN_FIELD_BASE(77, 77, 4, 0xb0, 0x10, 2, 1), ++ PIN_FIELD_BASE(78, 78, 4, 0xb0, 0x10, 0, 1), ++ PIN_FIELD_BASE(79, 79, 4, 0xb0, 0x10, 12, 1), ++ ++ PIN_FIELD_BASE(80, 80, 1, 0xe0, 0x10, 18, 1), ++ PIN_FIELD_BASE(81, 81, 1, 0xe0, 0x10, 19, 1), ++ PIN_FIELD_BASE(82, 82, 1, 0xe0, 0x10, 16, 1), ++ PIN_FIELD_BASE(83, 83, 1, 0xe0, 0x10, 17, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = { ++ PIN_FIELD_BASE(7, 7, 4, 0x60, 0x10, 5, 1), ++ PIN_FIELD_BASE(8, 8, 4, 0x60, 0x10, 4, 1), ++ PIN_FIELD_BASE(9, 9, 4, 0x60, 0x10, 3, 1), ++ PIN_FIELD_BASE(10, 10, 4, 0x60, 0x10, 2, 1), ++ ++ PIN_FIELD_BASE(13, 13, 1, 0x70, 0x10, 0, 1), ++ PIN_FIELD_BASE(14, 14, 1, 0x70, 0x10, 1, 1), ++ PIN_FIELD_BASE(63, 63, 1, 0x70, 0x10, 2, 1), ++ ++ PIN_FIELD_BASE(75, 75, 4, 0x60, 0x10, 7, 1), ++ PIN_FIELD_BASE(76, 76, 4, 0x60, 0x10, 6, 1), ++ PIN_FIELD_BASE(77, 77, 4, 0x60, 0x10, 1, 1), ++ PIN_FIELD_BASE(78, 78, 4, 0x60, 0x10, 0, 1), ++ PIN_FIELD_BASE(79, 79, 4, 0x60, 0x10, 8, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = { ++ PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 5, 1), ++ PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1), ++ PIN_FIELD_BASE(9, 9, 4, 0x40, 0x10, 3, 1), ++ PIN_FIELD_BASE(10, 10, 4, 0x40, 0x10, 2, 1), ++ ++ PIN_FIELD_BASE(13, 13, 1, 0x50, 0x10, 0, 1), ++ PIN_FIELD_BASE(14, 14, 1, 0x50, 0x10, 1, 1), ++ ++ PIN_FIELD_BASE(15, 15, 5, 0x40, 0x10, 4, 1), ++ PIN_FIELD_BASE(16, 16, 5, 0x40, 0x10, 5, 1), ++ PIN_FIELD_BASE(17, 17, 5, 0x40, 0x10, 0, 1), ++ PIN_FIELD_BASE(18, 18, 5, 0x40, 0x10, 1, 1), ++ ++ PIN_FIELD_BASE(63, 63, 1, 0x50, 0x10, 2, 1), ++ PIN_FIELD_BASE(71, 71, 5, 0x40, 0x10, 2, 1), ++ PIN_FIELD_BASE(72, 72, 5, 0x40, 0x10, 3, 1), ++ ++ PIN_FIELD_BASE(75, 75, 4, 0x40, 0x10, 7, 1), ++ PIN_FIELD_BASE(76, 76, 4, 0x40, 0x10, 6, 1), ++ PIN_FIELD_BASE(77, 77, 4, 0x40, 0x10, 1, 1), ++ PIN_FIELD_BASE(78, 78, 4, 0x40, 0x10, 0, 1), ++ PIN_FIELD_BASE(79, 79, 4, 0x40, 0x10, 8, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = { ++ PIN_FIELD_BASE(0, 0, 5, 0x00, 0x10, 21, 3), ++ PIN_FIELD_BASE(1, 1, 5, 0x00, 0x10, 24, 3), ++ PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 15, 3), ++ PIN_FIELD_BASE(3, 3, 5, 0x00, 0x10, 18, 3), ++ PIN_FIELD_BASE(4, 4, 5, 0x00, 0x10, 0, 3), ++ PIN_FIELD_BASE(5, 5, 5, 0x00, 0x10, 9, 3), ++ PIN_FIELD_BASE(6, 6, 5, 0x00, 0x10, 12, 3), ++ ++ PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 24, 3), ++ PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 28, 3), ++ PIN_FIELD_BASE(9, 9, 4, 0x00, 0x10, 15, 3), ++ PIN_FIELD_BASE(10, 10, 4, 0x00, 0x10, 9, 3), ++ ++ PIN_FIELD_BASE(11, 11, 1, 0x00, 0x10, 0, 3), ++ PIN_FIELD_BASE(12, 12, 1, 0x20, 0x10, 3, 3), ++ PIN_FIELD_BASE(13, 13, 1, 0x00, 0x10, 3, 3), ++ PIN_FIELD_BASE(14, 14, 1, 0x00, 0x10, 6, 3), ++ ++ PIN_FIELD_BASE(19, 19, 4, 0x00, 0x10, 21, 3), ++ PIN_FIELD_BASE(20, 20, 4, 0x00, 0x10, 12, 3), ++ ++ PIN_FIELD_BASE(21, 21, 3, 0x10, 0x10, 21, 3), ++ PIN_FIELD_BASE(22, 22, 3, 0x20, 0x10, 9, 3), ++ PIN_FIELD_BASE(23, 23, 3, 0x20, 0x10, 0, 3), ++ PIN_FIELD_BASE(24, 24, 3, 0x10, 0x10, 27, 3), ++ PIN_FIELD_BASE(25, 25, 3, 0x20, 0x10, 3, 3), ++ PIN_FIELD_BASE(26, 26, 3, 0x20, 0x10, 6, 3), ++ PIN_FIELD_BASE(27, 27, 3, 0x10, 0x10, 24, 3), ++ PIN_FIELD_BASE(28, 28, 3, 0x20, 0x10, 15, 3), ++ PIN_FIELD_BASE(29, 29, 3, 0x20, 0x10, 18, 3), ++ PIN_FIELD_BASE(30, 30, 3, 0x20, 0x10, 21, 3), ++ PIN_FIELD_BASE(31, 31, 3, 0x20, 0x10, 12, 3), ++ PIN_FIELD_BASE(32, 32, 3, 0x20, 0x10, 24, 3), ++ PIN_FIELD_BASE(33, 33, 3, 0x30, 0x10, 6, 3), ++ PIN_FIELD_BASE(34, 34, 3, 0x30, 0x10, 3, 3), ++ PIN_FIELD_BASE(35, 35, 3, 0x20, 0x10, 27, 3), ++ PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 0, 3), ++ PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 9, 3), ++ PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 3, 3), ++ PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 0, 3), ++ PIN_FIELD_BASE(40, 40, 3, 0x00, 0x10, 0, 3), ++ PIN_FIELD_BASE(41, 41, 3, 0x00, 0x10, 3, 3), ++ PIN_FIELD_BASE(42, 42, 3, 0x00, 0x10, 27, 3), ++ PIN_FIELD_BASE(43, 43, 3, 0x00, 0x10, 24, 3), ++ PIN_FIELD_BASE(44, 44, 3, 0x00, 0x10, 21, 3), ++ PIN_FIELD_BASE(45, 45, 3, 0x00, 0x10, 18, 3), ++ PIN_FIELD_BASE(46, 46, 3, 0x00, 0x10, 15, 3), ++ PIN_FIELD_BASE(47, 47, 3, 0x00, 0x10, 12, 3), ++ PIN_FIELD_BASE(48, 48, 3, 0x00, 0x10, 9, 3), ++ PIN_FIELD_BASE(49, 49, 3, 0x00, 0x10, 6, 3), ++ PIN_FIELD_BASE(50, 50, 3, 0x10, 0x10, 15, 3), ++ PIN_FIELD_BASE(51, 51, 3, 0x10, 0x10, 6, 3), ++ PIN_FIELD_BASE(52, 52, 3, 0x10, 0x10, 9, 3), ++ PIN_FIELD_BASE(53, 53, 3, 0x10, 0x10, 12, 3), ++ PIN_FIELD_BASE(54, 54, 3, 0x10, 0x10, 18, 3), ++ ++ PIN_FIELD_BASE(55, 55, 1, 0x10, 0x10, 12, 3), ++ PIN_FIELD_BASE(56, 56, 1, 0x10, 0x10, 15, 3), ++ PIN_FIELD_BASE(57, 57, 1, 0x10, 0x10, 9, 3), ++ PIN_FIELD_BASE(58, 58, 1, 0x00, 0x10, 12, 3), ++ PIN_FIELD_BASE(59, 59, 1, 0x00, 0x10, 15, 3), ++ PIN_FIELD_BASE(60, 60, 1, 0x00, 0x10, 18, 3), ++ PIN_FIELD_BASE(61, 61, 1, 0x00, 0x10, 9, 3), ++ PIN_FIELD_BASE(62, 62, 1, 0x00, 0x10, 21, 3), ++ PIN_FIELD_BASE(63, 63, 1, 0x20, 0x10, 0, 3), ++ PIN_FIELD_BASE(64, 64, 1, 0x00, 0x10, 24, 3), ++ PIN_FIELD_BASE(65, 65, 1, 0x00, 0x10, 27, 3), ++ PIN_FIELD_BASE(66, 66, 1, 0x10, 0x10, 0, 3), ++ PIN_FIELD_BASE(67, 67, 1, 0x10, 0x10, 3, 3), ++ PIN_FIELD_BASE(68, 68, 1, 0x10, 0x10, 6, 3), ++ ++ PIN_FIELD_BASE(69, 69, 5, 0x00, 0x10, 3, 3), ++ PIN_FIELD_BASE(70, 70, 5, 0x00, 0x10, 6, 3), ++ ++ PIN_FIELD_BASE(73, 73, 4, 0x10, 0x10, 0, 3), ++ PIN_FIELD_BASE(74, 74, 4, 0x00, 0x10, 3, 3), ++ PIN_FIELD_BASE(75, 75, 4, 0x10, 0x10, 3, 3), ++ PIN_FIELD_BASE(76, 76, 4, 0x00, 0x10, 27, 3), ++ PIN_FIELD_BASE(77, 77, 4, 0x00, 0x10, 6, 3), ++ PIN_FIELD_BASE(78, 78, 4, 0x00, 0x10, 0, 3), ++ PIN_FIELD_BASE(79, 79, 4, 0x10, 0x10, 6, 3), ++ ++ PIN_FIELD_BASE(80, 80, 1, 0x10, 0x10, 24, 3), ++ PIN_FIELD_BASE(81, 81, 1, 0x10, 0x10, 27, 3), ++ PIN_FIELD_BASE(82, 82, 1, 0x10, 0x10, 18, 3), ++ PIN_FIELD_BASE(83, 83, 1, 0x10, 0x10, 21, 3), ++}; ++ ++static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = { ++ PIN_FIELD_BASE(0, 0, 5, 0x50, 0x10, 7, 1), ++ PIN_FIELD_BASE(1, 1, 5, 0x50, 0x10, 8, 1), ++ PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 5, 1), ++ PIN_FIELD_BASE(3, 3, 5, 0x50, 0x10, 6, 1), ++ PIN_FIELD_BASE(4, 4, 5, 0x50, 0x10, 0, 1), ++ PIN_FIELD_BASE(5, 5, 5, 0x50, 0x10, 3, 1), ++ PIN_FIELD_BASE(6, 6, 5, 0x50, 0x10, 4, 1), ++ ++ PIN_FIELD_BASE(11, 11, 1, 0x60, 0x10, 0, 1), ++ PIN_FIELD_BASE(12, 12, 1, 0x60, 0x10, 18, 1), ++ ++ PIN_FIELD_BASE(19, 19, 4, 0x50, 0x10, 2, 1), ++ PIN_FIELD_BASE(20, 20, 4, 0x50, 0x10, 1, 1), ++ ++ PIN_FIELD_BASE(21, 21, 3, 0x70, 0x10, 17, 1), ++ PIN_FIELD_BASE(22, 22, 3, 0x70, 0x10, 23, 1), ++ PIN_FIELD_BASE(23, 23, 3, 0x70, 0x10, 20, 1), ++ PIN_FIELD_BASE(24, 24, 3, 0x70, 0x10, 19, 1), ++ PIN_FIELD_BASE(25, 25, 3, 0x70, 0x10, 21, 1), ++ PIN_FIELD_BASE(26, 26, 3, 0x70, 0x10, 22, 1), ++ PIN_FIELD_BASE(27, 27, 3, 0x70, 0x10, 18, 1), ++ PIN_FIELD_BASE(28, 28, 3, 0x70, 0x10, 25, 1), ++ PIN_FIELD_BASE(29, 29, 3, 0x70, 0x10, 26, 1), ++ PIN_FIELD_BASE(30, 30, 3, 0x70, 0x10, 27, 1), ++ PIN_FIELD_BASE(31, 31, 3, 0x70, 0x10, 24, 1), ++ PIN_FIELD_BASE(32, 32, 3, 0x70, 0x10, 28, 1), ++ PIN_FIELD_BASE(33, 33, 3, 0x80, 0x10, 0, 1), ++ PIN_FIELD_BASE(34, 34, 3, 0x70, 0x10, 31, 1), ++ PIN_FIELD_BASE(35, 35, 3, 0x70, 0x10, 29, 1), ++ PIN_FIELD_BASE(36, 36, 3, 0x70, 0x10, 30, 1), ++ PIN_FIELD_BASE(37, 37, 3, 0x80, 0x10, 1, 1), ++ PIN_FIELD_BASE(38, 38, 3, 0x70, 0x10, 11, 1), ++ PIN_FIELD_BASE(39, 39, 3, 0x70, 0x10, 10, 1), ++ PIN_FIELD_BASE(40, 40, 3, 0x70, 0x10, 0, 1), ++ PIN_FIELD_BASE(41, 41, 3, 0x70, 0x10, 1, 1), ++ PIN_FIELD_BASE(42, 42, 3, 0x70, 0x10, 9, 1), ++ PIN_FIELD_BASE(43, 43, 3, 0x70, 0x10, 8, 1), ++ PIN_FIELD_BASE(44, 44, 3, 0x70, 0x10, 7, 1), ++ PIN_FIELD_BASE(45, 45, 3, 0x70, 0x10, 6, 1), ++ PIN_FIELD_BASE(46, 46, 3, 0x70, 0x10, 5, 1), ++ PIN_FIELD_BASE(47, 47, 3, 0x70, 0x10, 4, 1), ++ PIN_FIELD_BASE(48, 48, 3, 0x70, 0x10, 3, 1), ++ PIN_FIELD_BASE(49, 49, 3, 0x70, 0x10, 2, 1), ++ PIN_FIELD_BASE(50, 50, 3, 0x70, 0x10, 15, 1), ++ PIN_FIELD_BASE(51, 51, 3, 0x70, 0x10, 12, 1), ++ PIN_FIELD_BASE(52, 52, 3, 0x70, 0x10, 13, 1), ++ PIN_FIELD_BASE(53, 53, 3, 0x70, 0x10, 14, 1), ++ PIN_FIELD_BASE(54, 54, 3, 0x70, 0x10, 16, 1), ++ ++ PIN_FIELD_BASE(55, 55, 1, 0x60, 0x10, 12, 1), ++ PIN_FIELD_BASE(56, 56, 1, 0x60, 0x10, 13, 1), ++ PIN_FIELD_BASE(57, 57, 1, 0x60, 0x10, 11, 1), ++ PIN_FIELD_BASE(58, 58, 1, 0x60, 0x10, 2, 1), ++ PIN_FIELD_BASE(59, 59, 1, 0x60, 0x10, 3, 1), ++ PIN_FIELD_BASE(60, 60, 1, 0x60, 0x10, 4, 1), ++ PIN_FIELD_BASE(61, 61, 1, 0x60, 0x10, 1, 1), ++ PIN_FIELD_BASE(62, 62, 1, 0x60, 0x10, 5, 1), ++ PIN_FIELD_BASE(64, 64, 1, 0x60, 0x10, 6, 1), ++ PIN_FIELD_BASE(65, 65, 1, 0x60, 0x10, 7, 1), ++ PIN_FIELD_BASE(66, 66, 1, 0x60, 0x10, 8, 1), ++ PIN_FIELD_BASE(67, 67, 1, 0x60, 0x10, 9, 1), ++ PIN_FIELD_BASE(68, 68, 1, 0x60, 0x10, 10, 1), ++ ++ PIN_FIELD_BASE(69, 69, 5, 0x50, 0x10, 1, 1), ++ PIN_FIELD_BASE(70, 70, 5, 0x50, 0x10, 2, 1), ++ ++ PIN_FIELD_BASE(73, 73, 4, 0x50, 0x10, 3, 1), ++ PIN_FIELD_BASE(74, 74, 4, 0x50, 0x10, 0, 1), ++ ++ PIN_FIELD_BASE(80, 80, 1, 0x60, 0x10, 16, 1), ++ PIN_FIELD_BASE(81, 81, 1, 0x60, 0x10, 17, 1), ++ PIN_FIELD_BASE(82, 82, 1, 0x60, 0x10, 14, 1), ++ PIN_FIELD_BASE(83, 83, 1, 0x60, 0x10, 15, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = { ++ PIN_FIELD_BASE(0, 0, 5, 0x60, 0x10, 7, 1), ++ PIN_FIELD_BASE(1, 1, 5, 0x60, 0x10, 8, 1), ++ PIN_FIELD_BASE(2, 2, 5, 0x60, 0x10, 5, 1), ++ PIN_FIELD_BASE(3, 3, 5, 0x60, 0x10, 6, 1), ++ PIN_FIELD_BASE(4, 4, 5, 0x60, 0x10, 0, 1), ++ PIN_FIELD_BASE(5, 5, 5, 0x60, 0x10, 3, 1), ++ PIN_FIELD_BASE(6, 6, 5, 0x60, 0x10, 4, 1), ++ ++ PIN_FIELD_BASE(11, 11, 1, 0x80, 0x10, 0, 1), ++ PIN_FIELD_BASE(12, 12, 1, 0x80, 0x10, 18, 1), ++ ++ PIN_FIELD_BASE(19, 19, 4, 0x70, 0x10, 2, 1), ++ PIN_FIELD_BASE(20, 20, 4, 0x70, 0x10, 1, 1), ++ ++ PIN_FIELD_BASE(21, 21, 3, 0x90, 0x10, 17, 1), ++ PIN_FIELD_BASE(22, 22, 3, 0x90, 0x10, 23, 1), ++ PIN_FIELD_BASE(23, 23, 3, 0x90, 0x10, 20, 1), ++ PIN_FIELD_BASE(24, 24, 3, 0x90, 0x10, 19, 1), ++ PIN_FIELD_BASE(25, 25, 3, 0x90, 0x10, 21, 1), ++ PIN_FIELD_BASE(26, 26, 3, 0x90, 0x10, 22, 1), ++ PIN_FIELD_BASE(27, 27, 3, 0x90, 0x10, 18, 1), ++ PIN_FIELD_BASE(28, 28, 3, 0x90, 0x10, 25, 1), ++ PIN_FIELD_BASE(29, 29, 3, 0x90, 0x10, 26, 1), ++ PIN_FIELD_BASE(30, 30, 3, 0x90, 0x10, 27, 1), ++ PIN_FIELD_BASE(31, 31, 3, 0x90, 0x10, 24, 1), ++ PIN_FIELD_BASE(32, 32, 3, 0x90, 0x10, 28, 1), ++ PIN_FIELD_BASE(33, 33, 3, 0xa0, 0x10, 0, 1), ++ PIN_FIELD_BASE(34, 34, 3, 0x90, 0x10, 31, 1), ++ PIN_FIELD_BASE(35, 35, 3, 0x90, 0x10, 29, 1), ++ PIN_FIELD_BASE(36, 36, 3, 0x90, 0x10, 30, 1), ++ PIN_FIELD_BASE(37, 37, 3, 0xa0, 0x10, 1, 1), ++ PIN_FIELD_BASE(38, 38, 3, 0x90, 0x10, 11, 1), ++ PIN_FIELD_BASE(39, 39, 3, 0x90, 0x10, 10, 1), ++ PIN_FIELD_BASE(40, 40, 3, 0x90, 0x10, 0, 1), ++ PIN_FIELD_BASE(41, 41, 3, 0x90, 0x10, 1, 1), ++ PIN_FIELD_BASE(42, 42, 3, 0x90, 0x10, 9, 1), ++ PIN_FIELD_BASE(43, 43, 3, 0x90, 0x10, 8, 1), ++ PIN_FIELD_BASE(44, 44, 3, 0x90, 0x10, 7, 1), ++ PIN_FIELD_BASE(45, 45, 3, 0x90, 0x10, 6, 1), ++ PIN_FIELD_BASE(46, 46, 3, 0x90, 0x10, 5, 1), ++ PIN_FIELD_BASE(47, 47, 3, 0x90, 0x10, 4, 1), ++ PIN_FIELD_BASE(48, 48, 3, 0x90, 0x10, 3, 1), ++ PIN_FIELD_BASE(49, 49, 3, 0x90, 0x10, 2, 1), ++ PIN_FIELD_BASE(50, 50, 3, 0x90, 0x10, 15, 1), ++ PIN_FIELD_BASE(51, 51, 3, 0x90, 0x10, 12, 1), ++ PIN_FIELD_BASE(52, 52, 3, 0x90, 0x10, 13, 1), ++ PIN_FIELD_BASE(53, 53, 3, 0x90, 0x10, 14, 1), ++ PIN_FIELD_BASE(54, 54, 3, 0x90, 0x10, 16, 1), ++ ++ PIN_FIELD_BASE(55, 55, 1, 0x80, 0x10, 12, 1), ++ PIN_FIELD_BASE(56, 56, 1, 0x80, 0x10, 13, 1), ++ PIN_FIELD_BASE(57, 57, 1, 0x80, 0x10, 11, 1), ++ PIN_FIELD_BASE(58, 58, 1, 0x80, 0x10, 2, 1), ++ PIN_FIELD_BASE(59, 59, 1, 0x80, 0x10, 3, 1), ++ PIN_FIELD_BASE(60, 60, 1, 0x80, 0x10, 4, 1), ++ PIN_FIELD_BASE(61, 61, 1, 0x80, 0x10, 1, 1), ++ PIN_FIELD_BASE(62, 62, 1, 0x80, 0x10, 5, 1), ++ PIN_FIELD_BASE(64, 64, 1, 0x80, 0x10, 6, 1), ++ PIN_FIELD_BASE(65, 65, 1, 0x80, 0x10, 7, 1), ++ PIN_FIELD_BASE(66, 66, 1, 0x80, 0x10, 8, 1), ++ PIN_FIELD_BASE(67, 67, 1, 0x80, 0x10, 9, 1), ++ PIN_FIELD_BASE(68, 68, 1, 0x80, 0x10, 10, 1), ++ ++ PIN_FIELD_BASE(69, 69, 5, 0x60, 0x10, 1, 1), ++ PIN_FIELD_BASE(70, 70, 5, 0x60, 0x10, 2, 1), ++ ++ PIN_FIELD_BASE(73, 73, 4, 0x70, 0x10, 3, 1), ++ PIN_FIELD_BASE(74, 74, 4, 0x70, 0x10, 0, 1), ++ ++ PIN_FIELD_BASE(80, 80, 1, 0x80, 0x10, 16, 1), ++ PIN_FIELD_BASE(81, 81, 1, 0x80, 0x10, 17, 1), ++ PIN_FIELD_BASE(82, 82, 1, 0x80, 0x10, 14, 1), ++ PIN_FIELD_BASE(83, 83, 1, 0x80, 0x10, 15, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = { ++ PIN_FIELD_BASE(0, 0, 5, 0x70, 0x10, 7, 1), ++ PIN_FIELD_BASE(1, 1, 5, 0x70, 0x10, 8, 1), ++ PIN_FIELD_BASE(2, 2, 5, 0x70, 0x10, 5, 1), ++ PIN_FIELD_BASE(3, 3, 5, 0x70, 0x10, 6, 1), ++ PIN_FIELD_BASE(4, 4, 5, 0x70, 0x10, 0, 1), ++ PIN_FIELD_BASE(5, 5, 5, 0x70, 0x10, 3, 1), ++ PIN_FIELD_BASE(6, 6, 5, 0x70, 0x10, 4, 1), ++ ++ PIN_FIELD_BASE(11, 11, 1, 0x90, 0x10, 0, 1), ++ PIN_FIELD_BASE(12, 12, 1, 0x90, 0x10, 18, 1), ++ ++ PIN_FIELD_BASE(19, 19, 4, 0x80, 0x10, 2, 1), ++ PIN_FIELD_BASE(20, 20, 4, 0x80, 0x10, 1, 1), ++ ++ PIN_FIELD_BASE(21, 21, 3, 0xb0, 0x10, 17, 1), ++ PIN_FIELD_BASE(22, 22, 3, 0xb0, 0x10, 23, 1), ++ PIN_FIELD_BASE(23, 23, 3, 0xb0, 0x10, 20, 1), ++ PIN_FIELD_BASE(24, 24, 3, 0xb0, 0x10, 19, 1), ++ PIN_FIELD_BASE(25, 25, 3, 0xb0, 0x10, 21, 1), ++ PIN_FIELD_BASE(26, 26, 3, 0xb0, 0x10, 22, 1), ++ PIN_FIELD_BASE(27, 27, 3, 0xb0, 0x10, 18, 1), ++ PIN_FIELD_BASE(28, 28, 3, 0xb0, 0x10, 25, 1), ++ PIN_FIELD_BASE(29, 29, 3, 0xb0, 0x10, 26, 1), ++ PIN_FIELD_BASE(30, 30, 3, 0xb0, 0x10, 27, 1), ++ PIN_FIELD_BASE(31, 31, 3, 0xb0, 0x10, 24, 1), ++ PIN_FIELD_BASE(32, 32, 3, 0xb0, 0x10, 28, 1), ++ PIN_FIELD_BASE(33, 33, 3, 0xc0, 0x10, 0, 1), ++ PIN_FIELD_BASE(34, 34, 3, 0xb0, 0x10, 31, 1), ++ PIN_FIELD_BASE(35, 35, 3, 0xb0, 0x10, 29, 1), ++ PIN_FIELD_BASE(36, 36, 3, 0xb0, 0x10, 30, 1), ++ PIN_FIELD_BASE(37, 37, 3, 0xc0, 0x10, 1, 1), ++ PIN_FIELD_BASE(38, 38, 3, 0xb0, 0x10, 11, 1), ++ PIN_FIELD_BASE(39, 39, 3, 0xb0, 0x10, 10, 1), ++ PIN_FIELD_BASE(40, 40, 3, 0xb0, 0x10, 0, 1), ++ PIN_FIELD_BASE(41, 41, 3, 0xb0, 0x10, 1, 1), ++ PIN_FIELD_BASE(42, 42, 3, 0xb0, 0x10, 9, 1), ++ PIN_FIELD_BASE(43, 43, 3, 0xb0, 0x10, 8, 1), ++ PIN_FIELD_BASE(44, 44, 3, 0xb0, 0x10, 7, 1), ++ PIN_FIELD_BASE(45, 45, 3, 0xb0, 0x10, 6, 1), ++ PIN_FIELD_BASE(46, 46, 3, 0xb0, 0x10, 5, 1), ++ PIN_FIELD_BASE(47, 47, 3, 0xb0, 0x10, 4, 1), ++ PIN_FIELD_BASE(48, 48, 3, 0xb0, 0x10, 3, 1), ++ PIN_FIELD_BASE(49, 49, 3, 0xb0, 0x10, 2, 1), ++ PIN_FIELD_BASE(50, 50, 3, 0xb0, 0x10, 15, 1), ++ PIN_FIELD_BASE(51, 51, 3, 0xb0, 0x10, 12, 1), ++ PIN_FIELD_BASE(52, 52, 3, 0xb0, 0x10, 13, 1), ++ PIN_FIELD_BASE(53, 53, 3, 0xb0, 0x10, 14, 1), ++ PIN_FIELD_BASE(54, 54, 3, 0xb0, 0x10, 16, 1), ++ ++ PIN_FIELD_BASE(55, 55, 1, 0x90, 0x10, 12, 1), ++ PIN_FIELD_BASE(56, 56, 1, 0x90, 0x10, 13, 1), ++ PIN_FIELD_BASE(57, 57, 1, 0x90, 0x10, 11, 1), ++ PIN_FIELD_BASE(58, 58, 1, 0x90, 0x10, 2, 1), ++ PIN_FIELD_BASE(59, 59, 1, 0x90, 0x10, 3, 1), ++ PIN_FIELD_BASE(60, 60, 1, 0x90, 0x10, 4, 1), ++ PIN_FIELD_BASE(61, 61, 1, 0x90, 0x10, 1, 1), ++ PIN_FIELD_BASE(62, 62, 1, 0x90, 0x10, 5, 1), ++ PIN_FIELD_BASE(64, 64, 1, 0x90, 0x10, 6, 1), ++ PIN_FIELD_BASE(65, 65, 1, 0x90, 0x10, 7, 1), ++ PIN_FIELD_BASE(66, 66, 1, 0x90, 0x10, 8, 1), ++ PIN_FIELD_BASE(67, 67, 1, 0x90, 0x10, 9, 1), ++ PIN_FIELD_BASE(68, 68, 1, 0x90, 0x10, 10, 1), ++ ++ PIN_FIELD_BASE(69, 69, 5, 0x70, 0x10, 1, 1), ++ PIN_FIELD_BASE(70, 70, 5, 0x70, 0x10, 2, 1), ++ ++ PIN_FIELD_BASE(73, 73, 4, 0x80, 0x10, 3, 1), ++ PIN_FIELD_BASE(74, 74, 4, 0x80, 0x10, 0, 1), ++ ++ PIN_FIELD_BASE(80, 80, 1, 0x90, 0x10, 16, 1), ++ PIN_FIELD_BASE(81, 81, 1, 0x90, 0x10, 17, 1), ++ PIN_FIELD_BASE(82, 82, 1, 0x90, 0x10, 14, 1), ++ PIN_FIELD_BASE(83, 83, 1, 0x90, 0x10, 15, 1), ++}; ++ ++static const unsigned int mt7988_pull_type[] = { ++ MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PU_PD_TYPE, /*7*/ ++ MTK_PULL_PU_PD_TYPE, /*8*/ MTK_PULL_PU_PD_TYPE, /*9*/ ++ MTK_PULL_PU_PD_TYPE, /*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PU_PD_TYPE, /*13*/ ++ MTK_PULL_PU_PD_TYPE, /*14*/ MTK_PULL_PD_TYPE, /*15*/ ++ MTK_PULL_PD_TYPE, /*16*/ MTK_PULL_PD_TYPE, /*17*/ ++ MTK_PULL_PD_TYPE, /*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PU_PD_TYPE, /*63*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PUPD_R1R0_TYPE,/*69*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*70*/ MTK_PULL_PD_TYPE, /*71*/ ++ MTK_PULL_PD_TYPE, /*72*/ MTK_PULL_PUPD_R1R0_TYPE,/*73*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE, /*75*/ ++ MTK_PULL_PU_PD_TYPE, /*76*/ MTK_PULL_PU_PD_TYPE, /*77*/ ++ MTK_PULL_PU_PD_TYPE, /*78*/ MTK_PULL_PU_PD_TYPE, /*79*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*80*/ MTK_PULL_PUPD_R1R0_TYPE,/*81*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*82*/ MTK_PULL_PUPD_R1R0_TYPE,/*83*/ ++}; ++ ++static const struct mtk_pin_reg_calc mt7988_reg_cals[] = { ++ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7988_pin_mode_range), ++ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7988_pin_dir_range), ++ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7988_pin_di_range), ++ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7988_pin_do_range), ++ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7988_pin_smt_range), ++ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7988_pin_ies_range), ++ [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7988_pin_pu_range), ++ [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7988_pin_pd_range), ++ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7988_pin_drv_range), ++ [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7988_pin_pupd_range), ++ [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7988_pin_r0_range), ++ [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7988_pin_r1_range), ++}; ++ ++static const struct mtk_pin_desc mt7988_pins[] = { ++ MT7988_PIN(0, "UART2_RXD"), ++ MT7988_PIN(1, "UART2_TXD"), ++ MT7988_PIN(2, "UART2_CTS"), ++ MT7988_PIN(3, "UART2_RTS"), ++ MT7988_PIN(4, "GPIO_A"), ++ MT7988_PIN(5, "SMI_0_MDC"), ++ MT7988_PIN(6, "SMI_0_MDIO"), ++ MT7988_PIN(7, "PCIE30_2L_0_WAKE_N"), ++ MT7988_PIN(8, "PCIE30_2L_0_CLKREQ_N"), ++ MT7988_PIN(9, "PCIE30_1L_1_WAKE_N"), ++ MT7988_PIN(10, "PCIE30_1L_1_CLKREQ_N"), ++ MT7988_PIN(11, "GPIO_P"), ++ MT7988_PIN(12, "WATCHDOG"), ++ MT7988_PIN(13, "GPIO_RESET"), ++ MT7988_PIN(14, "GPIO_WPS"), ++ MT7988_PIN(15, "PMIC_I2C_SCL"), ++ MT7988_PIN(16, "PMIC_I2C_SDA"), ++ MT7988_PIN(17, "I2C_1_SCL"), ++ MT7988_PIN(18, "I2C_1_SDA"), ++ MT7988_PIN(19, "PCIE30_2L_0_PRESET_N"), ++ MT7988_PIN(20, "PCIE30_1L_1_PRESET_N"), ++ MT7988_PIN(21, "PWMD1"), ++ MT7988_PIN(22, "SPI0_WP"), ++ MT7988_PIN(23, "SPI0_HOLD"), ++ MT7988_PIN(24, "SPI0_CSB"), ++ MT7988_PIN(25, "SPI0_MISO"), ++ MT7988_PIN(26, "SPI0_MOSI"), ++ MT7988_PIN(27, "SPI0_CLK"), ++ MT7988_PIN(28, "SPI1_CSB"), ++ MT7988_PIN(29, "SPI1_MISO"), ++ MT7988_PIN(30, "SPI1_MOSI"), ++ MT7988_PIN(31, "SPI1_CLK"), ++ MT7988_PIN(32, "SPI2_CLK"), ++ MT7988_PIN(33, "SPI2_MOSI"), ++ MT7988_PIN(34, "SPI2_MISO"), ++ MT7988_PIN(35, "SPI2_CSB"), ++ MT7988_PIN(36, "SPI2_HOLD"), ++ MT7988_PIN(37, "SPI2_WP"), ++ MT7988_PIN(38, "EMMC_RSTB"), ++ MT7988_PIN(39, "EMMC_DSL"), ++ MT7988_PIN(40, "EMMC_CK"), ++ MT7988_PIN(41, "EMMC_CMD"), ++ MT7988_PIN(42, "EMMC_DATA_7"), ++ MT7988_PIN(43, "EMMC_DATA_6"), ++ MT7988_PIN(44, "EMMC_DATA_5"), ++ MT7988_PIN(45, "EMMC_DATA_4"), ++ MT7988_PIN(46, "EMMC_DATA_3"), ++ MT7988_PIN(47, "EMMC_DATA_2"), ++ MT7988_PIN(48, "EMMC_DATA_1"), ++ MT7988_PIN(49, "EMMC_DATA_0"), ++ MT7988_PIN(50, "PCM_FS_I2S_LRCK"), ++ MT7988_PIN(51, "PCM_CLK_I2S_BCLK"), ++ MT7988_PIN(52, "PCM_DRX_I2S_DIN"), ++ MT7988_PIN(53, "PCM_DTX_I2S_DOUT"), ++ MT7988_PIN(54, "PCM_MCK_I2S_MCLK"), ++ MT7988_PIN(55, "UART0_RXD"), ++ MT7988_PIN(56, "UART0_TXD"), ++ MT7988_PIN(57, "PWMD0"), ++ MT7988_PIN(58, "JTAG_JTDI"), ++ MT7988_PIN(59, "JTAG_JTDO"), ++ MT7988_PIN(60, "JTAG_JTMS"), ++ MT7988_PIN(61, "JTAG_JTCLK"), ++ MT7988_PIN(62, "JTAG_JTRST_N"), ++ MT7988_PIN(63, "USB_DRV_VBUS_P1"), ++ MT7988_PIN(64, "LED_A"), ++ MT7988_PIN(65, "LED_B"), ++ MT7988_PIN(66, "LED_C"), ++ MT7988_PIN(67, "LED_D"), ++ MT7988_PIN(68, "LED_E"), ++ MT7988_PIN(69, "GPIO_B"), ++ MT7988_PIN(70, "GPIO_C"), ++ MT7988_PIN(71, "I2C_2_SCL"), ++ MT7988_PIN(72, "I2C_2_SDA"), ++ MT7988_PIN(73, "PCIE30_2L_1_PRESET_N"), ++ MT7988_PIN(74, "PCIE30_1L_0_PRESET_N"), ++ MT7988_PIN(75, "PCIE30_2L_1_WAKE_N"), ++ MT7988_PIN(76, "PCIE30_2L_1_CLKREQ_N"), ++ MT7988_PIN(77, "PCIE30_1L_0_WAKE_N"), ++ MT7988_PIN(78, "PCIE30_1L_0_CLKREQ_N"), ++ MT7988_PIN(79, "USB_DRV_VBUS_P0"), ++ MT7988_PIN(80, "UART1_RXD"), ++ MT7988_PIN(81, "UART1_TXD"), ++ MT7988_PIN(82, "UART1_CTS"), ++ MT7988_PIN(83, "UART1_RTS"), ++}; ++ ++/* jtag */ ++static const int mt7988_tops_jtag0_0_pins[] = { 0, 1, 2, 3, 4 }; ++static int mt7988_tops_jtag0_0_funcs[] = { 2, 2, 2, 2, 2 }; ++ ++static const int mt7988_wo0_jtag_pins[] = { 50, 51, 52, 53, 54 }; ++static int mt7988_wo0_jtag_funcs[] = { 3, 3, 3, 3, 3 }; ++ ++static const int mt7988_wo1_jtag_pins[] = { 50, 51, 52, 53, 54 }; ++static int mt7988_wo1_jtag_funcs[] = { 4, 4, 4, 4, 4 }; ++ ++static const int mt7988_wo2_jtag_pins[] = { 50, 51, 52, 53, 54 }; ++static int mt7988_wo2_jtag_funcs[] = { 5, 5, 5, 5, 5 }; ++ ++static const int mt7988_jtag_pins[] = { 58, 59, 60, 61, 62 }; ++static int mt7988_jtag_funcs[] = { 1, 1, 1, 1, 1 }; ++ ++static const int mt7988_tops_jtag0_1_pins[] = { 58, 59, 60, 61, 62 }; ++static int mt7988_tops_jtag0_1_funcs[] = { 4, 4, 4, 4, 4 }; ++ ++/* int_usxgmii */ ++static const int mt7988_int_usxgmii_pins[] = { 2, 3 }; ++static int mt7988_int_usxgmii_funcs[] = { 3, 3 }; ++ ++/* pwm */ ++static const int mt7988_pwm0_pins[] = { 57 }; ++static int mt7988_pwm0_funcs[] = { 1 }; ++ ++static const int mt7988_pwm1_pins[] = { 21 }; ++static int mt7988_pwm1_funcs[] = { 1 }; ++ ++static const int mt7988_pwm2_pins[] = { 80 }; ++static int mt7988_pwm2_funcs[] = { 2 }; ++ ++static const int mt7988_pwm2_0_pins[] = { 58 }; ++static int mt7988_pwm2_0_funcs[] = { 5 }; ++ ++static const int mt7988_pwm3_pins[] = { 81 }; ++static int mt7988_pwm3_funcs[] = { 2 }; ++ ++static const int mt7988_pwm3_0_pins[] = { 59 }; ++static int mt7988_pwm3_0_funcs[] = { 5 }; ++ ++static const int mt7988_pwm4_pins[] = { 82 }; ++static int mt7988_pwm4_funcs[] = { 2 }; ++ ++static const int mt7988_pwm4_0_pins[] = { 60 }; ++static int mt7988_pwm4_0_funcs[] = { 5 }; ++ ++static const int mt7988_pwm5_pins[] = { 83 }; ++static int mt7988_pwm5_funcs[] = { 2 }; ++ ++static const int mt7988_pwm5_0_pins[] = { 61 }; ++static int mt7988_pwm5_0_funcs[] = { 5 }; ++ ++static const int mt7988_pwm6_pins[] = { 69 }; ++static int mt7988_pwm6_funcs[] = { 3 }; ++ ++static const int mt7988_pwm6_0_pins[] = { 62 }; ++static int mt7988_pwm6_0_funcs[] = { 5 }; ++ ++static const int mt7988_pwm7_pins[] = { 70 }; ++static int mt7988_pwm7_funcs[] = { 3 }; ++ ++static const int mt7988_pwm7_0_pins[] = { 4 }; ++static int mt7988_pwm7_0_funcs[] = { 3 }; ++ ++/* dfd */ ++static const int mt7988_dfd_pins[] = { 0, 1, 2, 3, 4 }; ++static int mt7988_dfd_funcs[] = { 4, 4, 4, 4, 4 }; ++ ++/* i2c */ ++static const int mt7988_xfi_phy0_i2c0_pins[] = { 0, 1 }; ++static int mt7988_xfi_phy0_i2c0_funcs[] = { 5, 5 }; ++ ++static const int mt7988_xfi_phy1_i2c0_pins[] = { 0, 1 }; ++static int mt7988_xfi_phy1_i2c0_funcs[] = { 6, 6 }; ++ ++static const int mt7988_xfi_phy_pll_i2c0_pins[] = { 3, 4 }; ++static int mt7988_xfi_phy_pll_i2c0_funcs[] = { 5, 5 }; ++ ++static const int mt7988_xfi_phy_pll_i2c1_pins[] = { 3, 4 }; ++static int mt7988_xfi_phy_pll_i2c1_funcs[] = { 6, 6 }; ++ ++static const int mt7988_i2c0_0_pins[] = { 5, 6 }; ++static int mt7988_i2c0_0_funcs[] = { 2, 2 }; ++ ++static const int mt7988_i2c1_sfp_pins[] = { 5, 6 }; ++static int mt7988_i2c1_sfp_funcs[] = { 4, 4 }; ++ ++static const int mt7988_xfi_pextp_phy0_i2c_pins[] = { 5, 6 }; ++static int mt7988_xfi_pextp_phy0_i2c_funcs[] = { 5, 5 }; ++ ++static const int mt7988_xfi_pextp_phy1_i2c_pins[] = { 5, 6 }; ++static int mt7988_xfi_pextp_phy1_i2c_funcs[] = { 6, 6 }; ++ ++static const int mt7988_i2c0_1_pins[] = { 15, 16 }; ++static int mt7988_i2c0_1_funcs[] = { 1, 1 }; ++ ++static const int mt7988_u30_phy_i2c0_pins[] = { 15, 16 }; ++static int mt7988_u30_phy_i2c0_funcs[] = { 2, 2 }; ++ ++static const int mt7988_u32_phy_i2c0_pins[] = { 15, 16 }; ++static int mt7988_u32_phy_i2c0_funcs[] = { 3, 3 }; ++ ++static const int mt7988_xfi_phy0_i2c1_pins[] = { 15, 16 }; ++static int mt7988_xfi_phy0_i2c1_funcs[] = { 5, 5 }; ++ ++static const int mt7988_xfi_phy1_i2c1_pins[] = { 15, 16 }; ++static int mt7988_xfi_phy1_i2c1_funcs[] = { 6, 6 }; ++ ++static const int mt7988_xfi_phy_pll_i2c2_pins[] = { 15, 16 }; ++static int mt7988_xfi_phy_pll_i2c2_funcs[] = { 7, 7 }; ++ ++static const int mt7988_i2c1_0_pins[] = { 17, 18 }; ++static int mt7988_i2c1_0_funcs[] = { 1, 1 }; ++ ++static const int mt7988_u30_phy_i2c1_pins[] = { 17, 18 }; ++static int mt7988_u30_phy_i2c1_funcs[] = { 2, 2 }; ++ ++static const int mt7988_u32_phy_i2c1_pins[] = { 17, 18 }; ++static int mt7988_u32_phy_i2c1_funcs[] = { 3, 3 }; ++ ++static const int mt7988_xfi_phy_pll_i2c3_pins[] = { 17, 18 }; ++static int mt7988_xfi_phy_pll_i2c3_funcs[] = { 4, 4 }; ++ ++static const int mt7988_sgmii0_i2c_pins[] = { 17, 18 }; ++static int mt7988_sgmii0_i2c_funcs[] = { 5, 5 }; ++ ++static const int mt7988_sgmii1_i2c_pins[] = { 17, 18 }; ++static int mt7988_sgmii1_i2c_funcs[] = { 6, 6 }; ++ ++static const int mt7988_i2c1_2_pins[] = { 69, 70 }; ++static int mt7988_i2c1_2_funcs[] = { 2, 2 }; ++ ++static const int mt7988_i2c2_0_pins[] = { 69, 70 }; ++static int mt7988_i2c2_0_funcs[] = { 4, 4 }; ++ ++static const int mt7988_i2c2_1_pins[] = { 71, 72 }; ++static int mt7988_i2c2_1_funcs[] = { 1, 1 }; ++ ++/* eth */ ++static const int mt7988_mdc_mdio0_pins[] = { 5, 6 }; ++static int mt7988_mdc_mdio0_funcs[] = { 1, 1 }; ++ ++static const int mt7988_2p5g_ext_mdio_pins[] = { 28, 29 }; ++static int mt7988_2p5g_ext_mdio_funcs[] = { 6, 6 }; ++ ++static const int mt7988_gbe_ext_mdio_pins[] = { 30, 31 }; ++static int mt7988_gbe_ext_mdio_funcs[] = { 6, 6 }; ++ ++static const int mt7988_mdc_mdio1_pins[] = { 69, 70 }; ++static int mt7988_mdc_mdio1_funcs[] = { 1, 1 }; ++ ++/* pcie */ ++static const int mt7988_pcie_wake_n0_0_pins[] = { 7 }; ++static int mt7988_pcie_wake_n0_0_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_clk_req_n0_0_pins[] = { 8 }; ++static int mt7988_pcie_clk_req_n0_0_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_wake_n3_0_pins[] = { 9 }; ++static int mt7988_pcie_wake_n3_0_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_clk_req_n3_pins[] = { 10 }; ++static int mt7988_pcie_clk_req_n3_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_clk_req_n0_1_pins[] = { 10 }; ++static int mt7988_pcie_clk_req_n0_1_funcs[] = { 2 }; ++ ++static const int mt7988_pcie_p0_phy_i2c_pins[] = { 7, 8 }; ++static int mt7988_pcie_p0_phy_i2c_funcs[] = { 3, 3 }; ++ ++static const int mt7988_pcie_p1_phy_i2c_pins[] = { 7, 8 }; ++static int mt7988_pcie_p1_phy_i2c_funcs[] = { 4, 4 }; ++ ++static const int mt7988_pcie_p3_phy_i2c_pins[] = { 9, 10 }; ++static int mt7988_pcie_p3_phy_i2c_funcs[] = { 4, 4 }; ++ ++static const int mt7988_pcie_p2_phy_i2c_pins[] = { 7, 8 }; ++static int mt7988_pcie_p2_phy_i2c_funcs[] = { 5, 5 }; ++ ++static const int mt7988_ckm_phy_i2c_pins[] = { 9, 10 }; ++static int mt7988_ckm_phy_i2c_funcs[] = { 5, 5 }; ++ ++static const int mt7988_pcie_wake_n0_1_pins[] = { 13 }; ++static int mt7988_pcie_wake_n0_1_funcs[] = { 2 }; ++ ++static const int mt7988_pcie_wake_n3_1_pins[] = { 14 }; ++static int mt7988_pcie_wake_n3_1_funcs[] = { 2 }; ++ ++static const int mt7988_pcie_2l_0_pereset_pins[] = { 19 }; ++static int mt7988_pcie_2l_0_pereset_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_1l_1_pereset_pins[] = { 20 }; ++static int mt7988_pcie_1l_1_pereset_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_clk_req_n2_1_pins[] = { 63 }; ++static int mt7988_pcie_clk_req_n2_1_funcs[] = { 2 }; ++ ++static const int mt7988_pcie_2l_1_pereset_pins[] = { 73 }; ++static int mt7988_pcie_2l_1_pereset_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_1l_0_pereset_pins[] = { 74 }; ++static int mt7988_pcie_1l_0_pereset_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_wake_n1_0_pins[] = { 75 }; ++static int mt7988_pcie_wake_n1_0_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_clk_req_n1_pins[] = { 76 }; ++static int mt7988_pcie_clk_req_n1_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_wake_n2_0_pins[] = { 77 }; ++static int mt7988_pcie_wake_n2_0_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_clk_req_n2_0_pins[] = { 78 }; ++static int mt7988_pcie_clk_req_n2_0_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_wake_n2_1_pins[] = { 79 }; ++static int mt7988_pcie_wake_n2_1_funcs[] = { 2 }; ++ ++/* pmic */ ++static const int mt7988_pmic_pins[] = { 11 }; ++static int mt7988_pmic_funcs[] = { 1 }; ++ ++/* watchdog */ ++static const int mt7988_watchdog_pins[] = { 12 }; ++static int mt7988_watchdog_funcs[] = { 1 }; ++ ++/* spi */ ++static const int mt7988_spi0_wp_hold_pins[] = { 22, 23 }; ++static int mt7988_spi0_wp_hold_funcs[] = { 1, 1 }; ++ ++static const int mt7988_spi0_pins[] = { 24, 25, 26, 27 }; ++static int mt7988_spi0_funcs[] = { 1, 1, 1, 1 }; ++ ++static const int mt7988_spi1_pins[] = { 28, 29, 30, 31 }; ++static int mt7988_spi1_funcs[] = { 1, 1, 1, 1 }; ++ ++static const int mt7988_spi2_pins[] = { 32, 33, 34, 35 }; ++static int mt7988_spi2_funcs[] = { 1, 1, 1, 1 }; ++ ++static const int mt7988_spi2_wp_hold_pins[] = { 36, 37 }; ++static int mt7988_spi2_wp_hold_funcs[] = { 1, 1 }; ++ ++/* flash */ ++static const int mt7988_snfi_pins[] = { 22, 23, 24, 25, 26, 27 }; ++static int mt7988_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 }; ++ ++static const int mt7988_emmc_45_pins[] = { ++ 21, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37 ++}; ++static int mt7988_emmc_45_funcs[] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 }; ++ ++static const int mt7988_sdcard_pins[] = { 32, 33, 34, 35, 36, 37 }; ++static int mt7988_sdcard_funcs[] = { 5, 5, 5, 5, 5, 5 }; ++ ++static const int mt7988_emmc_51_pins[] = { 38, 39, 40, 41, 42, 43, ++ 44, 45, 46, 47, 48, 49 }; ++static int mt7988_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; ++ ++/* uart */ ++static const int mt7988_uart2_pins[] = { 0, 1, 2, 3 }; ++static int mt7988_uart2_funcs[] = { 1, 1, 1, 1 }; ++ ++static const int mt7988_tops_uart0_0_pins[] = { 22, 23 }; ++static int mt7988_tops_uart0_0_funcs[] = { 3, 3 }; ++ ++static const int mt7988_uart2_0_pins[] = { 28, 29, 30, 31 }; ++static int mt7988_uart2_0_funcs[] = { 2, 2, 2, 2 }; ++ ++static const int mt7988_uart1_0_pins[] = { 32, 33, 34, 35 }; ++static int mt7988_uart1_0_funcs[] = { 2, 2, 2, 2 }; ++ ++static const int mt7988_uart2_1_pins[] = { 32, 33, 34, 35 }; ++static int mt7988_uart2_1_funcs[] = { 3, 3, 3, 3 }; ++ ++static const int mt7988_net_wo0_uart_txd_0_pins[] = { 28 }; ++static int mt7988_net_wo0_uart_txd_0_funcs[] = { 3 }; ++ ++static const int mt7988_net_wo1_uart_txd_0_pins[] = { 29 }; ++static int mt7988_net_wo1_uart_txd_0_funcs[] = { 3 }; ++ ++static const int mt7988_net_wo2_uart_txd_0_pins[] = { 30 }; ++static int mt7988_net_wo2_uart_txd_0_funcs[] = { 3 }; ++ ++static const int mt7988_tops_uart1_0_pins[] = { 28, 29 }; ++static int mt7988_tops_uart1_0_funcs[] = { 4, 4 }; ++ ++static const int mt7988_tops_uart0_1_pins[] = { 30, 31 }; ++static int mt7988_tops_uart0_1_funcs[] = { 4, 4 }; ++ ++static const int mt7988_tops_uart1_1_pins[] = { 36, 37 }; ++static int mt7988_tops_uart1_1_funcs[] = { 3, 3 }; ++ ++static const int mt7988_uart0_pins[] = { 55, 56 }; ++static int mt7988_uart0_funcs[] = { 1, 1 }; ++ ++static const int mt7988_tops_uart0_2_pins[] = { 55, 56 }; ++static int mt7988_tops_uart0_2_funcs[] = { 2, 2 }; ++ ++static const int mt7988_uart2_2_pins[] = { 50, 51, 52, 53 }; ++static int mt7988_uart2_2_funcs[] = { 2, 2, 2, 2 }; ++ ++static const int mt7988_uart1_1_pins[] = { 58, 59, 60, 61 }; ++static int mt7988_uart1_1_funcs[] = { 2, 2, 2, 2 }; ++ ++static const int mt7988_uart2_3_pins[] = { 58, 59, 60, 61 }; ++static int mt7988_uart2_3_funcs[] = { 3, 3, 3, 3 }; ++ ++static const int mt7988_uart1_2_pins[] = { 80, 81, 82, 83 }; ++static int mt7988_uart1_2_funcs[] = { 1, 1, 1, 1 }; ++ ++static const int mt7988_uart1_2_lite_pins[] = { 80, 81 }; ++static int mt7988_uart1_2_lite_funcs[] = { 1, 1 }; ++ ++static const int mt7988_tops_uart1_2_pins[] = { 80, 81 }; ++static int mt7988_tops_uart1_2_funcs[] = { 4, 4, }; ++ ++static const int mt7988_net_wo0_uart_txd_1_pins[] = { 80 }; ++static int mt7988_net_wo0_uart_txd_1_funcs[] = { 3 }; ++ ++static const int mt7988_net_wo1_uart_txd_1_pins[] = { 81 }; ++static int mt7988_net_wo1_uart_txd_1_funcs[] = { 3 }; ++ ++static const int mt7988_net_wo2_uart_txd_1_pins[] = { 82 }; ++static int mt7988_net_wo2_uart_txd_1_funcs[] = { 3 }; ++ ++/* udi */ ++static const int mt7988_udi_pins[] = { 32, 33, 34, 35, 36 }; ++static int mt7988_udi_funcs[] = { 4, 4, 4, 4, 4 }; ++ ++/* i2s */ ++static const int mt7988_i2s_pins[] = { 50, 51, 52, 53, 54 }; ++static int mt7988_i2s_funcs[] = { 1, 1, 1, 1, 1 }; ++ ++/* pcm */ ++static const int mt7988_pcm_pins[] = { 50, 51, 52, 53 }; ++static int mt7988_pcm_funcs[] = { 1, 1, 1, 1 }; ++ ++/* led */ ++static const int mt7988_gbe0_led1_pins[] = { 58 }; ++static int mt7988_gbe0_led1_funcs[] = { 6 }; ++static const int mt7988_gbe1_led1_pins[] = { 59 }; ++static int mt7988_gbe1_led1_funcs[] = { 6 }; ++static const int mt7988_gbe2_led1_pins[] = { 60 }; ++static int mt7988_gbe2_led1_funcs[] = { 6 }; ++static const int mt7988_gbe3_led1_pins[] = { 61 }; ++static int mt7988_gbe3_led1_funcs[] = { 6 }; ++ ++static const int mt7988_2p5gbe_led1_pins[] = { 62 }; ++static int mt7988_2p5gbe_led1_funcs[] = { 6 }; ++ ++static const int mt7988_gbe0_led0_pins[] = { 64 }; ++static int mt7988_gbe0_led0_funcs[] = { 1 }; ++static const int mt7988_gbe1_led0_pins[] = { 65 }; ++static int mt7988_gbe1_led0_funcs[] = { 1 }; ++static const int mt7988_gbe2_led0_pins[] = { 66 }; ++static int mt7988_gbe2_led0_funcs[] = { 1 }; ++static const int mt7988_gbe3_led0_pins[] = { 67 }; ++static int mt7988_gbe3_led0_funcs[] = { 1 }; ++ ++static const int mt7988_2p5gbe_led0_pins[] = { 68 }; ++static int mt7988_2p5gbe_led0_funcs[] = { 1 }; ++ ++/* usb */ ++static const int mt7988_drv_vbus_p1_pins[] = { 63 }; ++static int mt7988_drv_vbus_p1_funcs[] = { 1 }; ++ ++static const int mt7988_drv_vbus_pins[] = { 79 }; ++static int mt7988_drv_vbus_funcs[] = { 1 }; ++ ++static const struct group_desc mt7988_groups[] = { ++ /* @GPIO(0,1,2,3): uart2 */ ++ PINCTRL_PIN_GROUP("uart2", mt7988_uart2), ++ /* @GPIO(0,1,2,3,4): tops_jtag0_0 */ ++ PINCTRL_PIN_GROUP("tops_jtag0_0", mt7988_tops_jtag0_0), ++ /* @GPIO(2,3): int_usxgmii */ ++ PINCTRL_PIN_GROUP("int_usxgmii", mt7988_int_usxgmii), ++ /* @GPIO(0,1,2,3,4): dfd */ ++ PINCTRL_PIN_GROUP("dfd", mt7988_dfd), ++ /* @GPIO(0,1): xfi_phy0_i2c0 */ ++ PINCTRL_PIN_GROUP("xfi_phy0_i2c0", mt7988_xfi_phy0_i2c0), ++ /* @GPIO(0,1): xfi_phy1_i2c0 */ ++ PINCTRL_PIN_GROUP("xfi_phy1_i2c0", mt7988_xfi_phy1_i2c0), ++ /* @GPIO(3,4): xfi_phy_pll_i2c0 */ ++ PINCTRL_PIN_GROUP("xfi_phy_pll_i2c0", mt7988_xfi_phy_pll_i2c0), ++ /* @GPIO(3,4): xfi_phy_pll_i2c1 */ ++ PINCTRL_PIN_GROUP("xfi_phy_pll_i2c1", mt7988_xfi_phy_pll_i2c1), ++ /* @GPIO(4): pwm7 */ ++ PINCTRL_PIN_GROUP("pwm7_0", mt7988_pwm7_0), ++ /* @GPIO(5,6) i2c0_0 */ ++ PINCTRL_PIN_GROUP("i2c0_0", mt7988_i2c0_0), ++ /* @GPIO(5,6) i2c1_sfp */ ++ PINCTRL_PIN_GROUP("i2c1_sfp", mt7988_i2c1_sfp), ++ /* @GPIO(5,6) xfi_pextp_phy0_i2c */ ++ PINCTRL_PIN_GROUP("xfi_pextp_phy0_i2c", mt7988_xfi_pextp_phy0_i2c), ++ /* @GPIO(5,6) xfi_pextp_phy1_i2c */ ++ PINCTRL_PIN_GROUP("xfi_pextp_phy1_i2c", mt7988_xfi_pextp_phy1_i2c), ++ /* @GPIO(5,6) mdc_mdio0 */ ++ PINCTRL_PIN_GROUP("mdc_mdio0", mt7988_mdc_mdio0), ++ /* @GPIO(7): pcie_wake_n0_0 */ ++ PINCTRL_PIN_GROUP("pcie_wake_n0_0", mt7988_pcie_wake_n0_0), ++ /* @GPIO(8): pcie_clk_req_n0_0 */ ++ PINCTRL_PIN_GROUP("pcie_clk_req_n0_0", mt7988_pcie_clk_req_n0_0), ++ /* @GPIO(9): pcie_wake_n3_0 */ ++ PINCTRL_PIN_GROUP("pcie_wake_n3_0", mt7988_pcie_wake_n3_0), ++ /* @GPIO(10): pcie_clk_req_n3 */ ++ PINCTRL_PIN_GROUP("pcie_clk_req_n3", mt7988_pcie_clk_req_n3), ++ /* @GPIO(10): pcie_clk_req_n0_1 */ ++ PINCTRL_PIN_GROUP("pcie_clk_req_n0_1", mt7988_pcie_clk_req_n0_1), ++ /* @GPIO(7,8) pcie_p0_phy_i2c */ ++ PINCTRL_PIN_GROUP("pcie_p0_phy_i2c", mt7988_pcie_p0_phy_i2c), ++ /* @GPIO(7,8) pcie_p1_phy_i2c */ ++ PINCTRL_PIN_GROUP("pcie_p1_phy_i2c", mt7988_pcie_p1_phy_i2c), ++ /* @GPIO(7,8) pcie_p2_phy_i2c */ ++ PINCTRL_PIN_GROUP("pcie_p2_phy_i2c", mt7988_pcie_p2_phy_i2c), ++ /* @GPIO(9,10) pcie_p3_phy_i2c */ ++ PINCTRL_PIN_GROUP("pcie_p3_phy_i2c", mt7988_pcie_p3_phy_i2c), ++ /* @GPIO(9,10) ckm_phy_i2c */ ++ PINCTRL_PIN_GROUP("ckm_phy_i2c", mt7988_ckm_phy_i2c), ++ /* @GPIO(11): pmic */ ++ PINCTRL_PIN_GROUP("pcie_pmic", mt7988_pmic), ++ /* @GPIO(12): watchdog */ ++ PINCTRL_PIN_GROUP("watchdog", mt7988_watchdog), ++ /* @GPIO(13): pcie_wake_n0_1 */ ++ PINCTRL_PIN_GROUP("pcie_wake_n0_1", mt7988_pcie_wake_n0_1), ++ /* @GPIO(14): pcie_wake_n3_1 */ ++ PINCTRL_PIN_GROUP("pcie_wake_n3_1", mt7988_pcie_wake_n3_1), ++ /* @GPIO(15,16) i2c0_1 */ ++ PINCTRL_PIN_GROUP("i2c0_1", mt7988_i2c0_1), ++ /* @GPIO(15,16) u30_phy_i2c0 */ ++ PINCTRL_PIN_GROUP("u30_phy_i2c0", mt7988_u30_phy_i2c0), ++ /* @GPIO(15,16) u32_phy_i2c0 */ ++ PINCTRL_PIN_GROUP("u32_phy_i2c0", mt7988_u32_phy_i2c0), ++ /* @GPIO(15,16) xfi_phy0_i2c1 */ ++ PINCTRL_PIN_GROUP("xfi_phy0_i2c1", mt7988_xfi_phy0_i2c1), ++ /* @GPIO(15,16) xfi_phy1_i2c1 */ ++ PINCTRL_PIN_GROUP("xfi_phy1_i2c1", mt7988_xfi_phy1_i2c1), ++ /* @GPIO(15,16) xfi_phy_pll_i2c2 */ ++ PINCTRL_PIN_GROUP("xfi_phy_pll_i2c2", mt7988_xfi_phy_pll_i2c2), ++ /* @GPIO(17,18) i2c1_0 */ ++ PINCTRL_PIN_GROUP("i2c1_0", mt7988_i2c1_0), ++ /* @GPIO(17,18) u30_phy_i2c1 */ ++ PINCTRL_PIN_GROUP("u30_phy_i2c1", mt7988_u30_phy_i2c1), ++ /* @GPIO(17,18) u32_phy_i2c1 */ ++ PINCTRL_PIN_GROUP("u32_phy_i2c1", mt7988_u32_phy_i2c1), ++ /* @GPIO(17,18) xfi_phy_pll_i2c3 */ ++ PINCTRL_PIN_GROUP("xfi_phy_pll_i2c3", mt7988_xfi_phy_pll_i2c3), ++ /* @GPIO(17,18) sgmii0_i2c */ ++ PINCTRL_PIN_GROUP("sgmii0_i2c", mt7988_sgmii0_i2c), ++ /* @GPIO(17,18) sgmii1_i2c */ ++ PINCTRL_PIN_GROUP("sgmii1_i2c", mt7988_sgmii1_i2c), ++ /* @GPIO(19): pcie_2l_0_pereset */ ++ PINCTRL_PIN_GROUP("pcie_2l_0_pereset", mt7988_pcie_2l_0_pereset), ++ /* @GPIO(20): pcie_1l_1_pereset */ ++ PINCTRL_PIN_GROUP("pcie_1l_1_pereset", mt7988_pcie_1l_1_pereset), ++ /* @GPIO(21): pwm1 */ ++ PINCTRL_PIN_GROUP("pwm1", mt7988_pwm1), ++ /* @GPIO(22,23) spi0_wp_hold */ ++ PINCTRL_PIN_GROUP("spi0_wp_hold", mt7988_spi0_wp_hold), ++ /* @GPIO(24,25,26,27) spi0 */ ++ PINCTRL_PIN_GROUP("spi0", mt7988_spi0), ++ /* @GPIO(28,29,30,31) spi1 */ ++ PINCTRL_PIN_GROUP("spi1", mt7988_spi1), ++ /* @GPIO(32,33,34,35) spi2 */ ++ PINCTRL_PIN_GROUP("spi2", mt7988_spi2), ++ /* @GPIO(36,37) spi2_wp_hold */ ++ PINCTRL_PIN_GROUP("spi2_wp_hold", mt7988_spi2_wp_hold), ++ /* @GPIO(22,23,24,25,26,27) snfi */ ++ PINCTRL_PIN_GROUP("snfi", mt7988_snfi), ++ /* @GPIO(22,23) tops_uart0_0 */ ++ PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart0_0), ++ /* @GPIO(28,29,30,31) uart2_0 */ ++ PINCTRL_PIN_GROUP("uart2_0", mt7988_uart2_0), ++ /* @GPIO(32,33,34,35) uart1_0 */ ++ PINCTRL_PIN_GROUP("uart1_0", mt7988_uart1_0), ++ /* @GPIO(32,33,34,35) uart2_1 */ ++ PINCTRL_PIN_GROUP("uart2_1", mt7988_uart2_1), ++ /* @GPIO(28) net_wo0_uart_txd_0 */ ++ PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0), ++ /* @GPIO(29) net_wo1_uart_txd_0 */ ++ PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0), ++ /* @GPIO(30) net_wo2_uart_txd_0 */ ++ PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0), ++ /* @GPIO(28,29) tops_uart1_0 */ ++ PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart1_0), ++ /* @GPIO(30,31) tops_uart0_1 */ ++ PINCTRL_PIN_GROUP("tops_uart0_1", mt7988_tops_uart0_1), ++ /* @GPIO(36,37) tops_uart1_1 */ ++ PINCTRL_PIN_GROUP("tops_uart1_1", mt7988_tops_uart1_1), ++ /* @GPIO(32,33,34,35,36) udi */ ++ PINCTRL_PIN_GROUP("udi", mt7988_udi), ++ /* @GPIO(21,28,29,30,31,32,33,34,35,36,37) emmc_45 */ ++ PINCTRL_PIN_GROUP("emmc_45", mt7988_emmc_45), ++ /* @GPIO(32,33,34,35,36,37) sdcard */ ++ PINCTRL_PIN_GROUP("sdcard", mt7988_sdcard), ++ /* @GPIO(38,39,40,41,42,43,44,45,46,47,48,49) emmc_51 */ ++ PINCTRL_PIN_GROUP("emmc_51", mt7988_emmc_51), ++ /* @GPIO(28,29) 2p5g_ext_mdio */ ++ PINCTRL_PIN_GROUP("2p5g_ext_mdio", mt7988_2p5g_ext_mdio), ++ /* @GPIO(30,31) gbe_ext_mdio */ ++ PINCTRL_PIN_GROUP("gbe_ext_mdio", mt7988_gbe_ext_mdio), ++ /* @GPIO(50,51,52,53,54) i2s */ ++ PINCTRL_PIN_GROUP("i2s", mt7988_i2s), ++ /* @GPIO(50,51,52,53) pcm */ ++ PINCTRL_PIN_GROUP("pcm", mt7988_pcm), ++ /* @GPIO(55,56) uart0 */ ++ PINCTRL_PIN_GROUP("uart0", mt7988_uart0), ++ /* @GPIO(55,56) tops_uart0_2 */ ++ PINCTRL_PIN_GROUP("tops_uart0_2", mt7988_tops_uart0_2), ++ /* @GPIO(50,51,52,53) uart2_2 */ ++ PINCTRL_PIN_GROUP("uart2_2", mt7988_uart2_2), ++ /* @GPIO(50,51,52,53,54) wo0_jtag */ ++ PINCTRL_PIN_GROUP("wo0_jtag", mt7988_wo0_jtag), ++ /* @GPIO(50,51,52,53,54) wo1-wo1_jtag */ ++ PINCTRL_PIN_GROUP("wo1_jtag", mt7988_wo1_jtag), ++ /* @GPIO(50,51,52,53,54) wo2_jtag */ ++ PINCTRL_PIN_GROUP("wo2_jtag", mt7988_wo2_jtag), ++ /* @GPIO(57) pwm0 */ ++ PINCTRL_PIN_GROUP("pwm0", mt7988_pwm0), ++ /* @GPIO(58) pwm2_0 */ ++ PINCTRL_PIN_GROUP("pwm2_0", mt7988_pwm2_0), ++ /* @GPIO(59) pwm3_0 */ ++ PINCTRL_PIN_GROUP("pwm3_0", mt7988_pwm3_0), ++ /* @GPIO(60) pwm4_0 */ ++ PINCTRL_PIN_GROUP("pwm4_0", mt7988_pwm4_0), ++ /* @GPIO(61) pwm5_0 */ ++ PINCTRL_PIN_GROUP("pwm5_0", mt7988_pwm5_0), ++ /* @GPIO(58,59,60,61,62) jtag */ ++ PINCTRL_PIN_GROUP("jtag", mt7988_jtag), ++ /* @GPIO(58,59,60,61,62) tops_jtag0_1 */ ++ PINCTRL_PIN_GROUP("tops_jtag0_1", mt7988_tops_jtag0_1), ++ /* @GPIO(58,59,60,61) uart2_3 */ ++ PINCTRL_PIN_GROUP("uart2_3", mt7988_uart2_3), ++ /* @GPIO(58,59,60,61) uart1_1 */ ++ PINCTRL_PIN_GROUP("uart1_1", mt7988_uart1_1), ++ /* @GPIO(58,59,60,61) gbe_led1 */ ++ PINCTRL_PIN_GROUP("gbe0_led1", mt7988_gbe0_led1), ++ PINCTRL_PIN_GROUP("gbe1_led1", mt7988_gbe1_led1), ++ PINCTRL_PIN_GROUP("gbe2_led1", mt7988_gbe2_led1), ++ PINCTRL_PIN_GROUP("gbe3_led1", mt7988_gbe3_led1), ++ /* @GPIO(62) pwm6_0 */ ++ PINCTRL_PIN_GROUP("pwm6_0", mt7988_pwm6_0), ++ /* @GPIO(62) 2p5gbe_led1 */ ++ PINCTRL_PIN_GROUP("2p5gbe_led1", mt7988_2p5gbe_led1), ++ /* @GPIO(64,65,66,67) gbe_led0 */ ++ PINCTRL_PIN_GROUP("gbe0_led0", mt7988_gbe0_led0), ++ PINCTRL_PIN_GROUP("gbe1_led0", mt7988_gbe1_led0), ++ PINCTRL_PIN_GROUP("gbe2_led0", mt7988_gbe2_led0), ++ PINCTRL_PIN_GROUP("gbe3_led0", mt7988_gbe3_led0), ++ /* @GPIO(68) 2p5gbe_led0 */ ++ PINCTRL_PIN_GROUP("2p5gbe_led0", mt7988_2p5gbe_led0), ++ /* @GPIO(63) drv_vbus_p1 */ ++ PINCTRL_PIN_GROUP("drv_vbus_p1", mt7988_drv_vbus_p1), ++ /* @GPIO(63) pcie_clk_req_n2_1 */ ++ PINCTRL_PIN_GROUP("pcie_clk_req_n2_1", mt7988_pcie_clk_req_n2_1), ++ /* @GPIO(69, 70) mdc_mdio1 */ ++ PINCTRL_PIN_GROUP("mdc_mdio1", mt7988_mdc_mdio1), ++ /* @GPIO(69, 70) i2c1_2 */ ++ PINCTRL_PIN_GROUP("i2c1_2", mt7988_i2c1_2), ++ /* @GPIO(69) pwm6 */ ++ PINCTRL_PIN_GROUP("pwm6", mt7988_pwm6), ++ /* @GPIO(70) pwm7 */ ++ PINCTRL_PIN_GROUP("pwm7", mt7988_pwm7), ++ /* @GPIO(69,70) i2c2_0 */ ++ PINCTRL_PIN_GROUP("i2c2_0", mt7988_i2c2_0), ++ /* @GPIO(71,72) i2c2_1 */ ++ PINCTRL_PIN_GROUP("i2c2_1", mt7988_i2c2_1), ++ /* @GPIO(73) pcie_2l_1_pereset */ ++ PINCTRL_PIN_GROUP("pcie_2l_1_pereset", mt7988_pcie_2l_1_pereset), ++ /* @GPIO(74) pcie_1l_0_pereset */ ++ PINCTRL_PIN_GROUP("pcie_1l_0_pereset", mt7988_pcie_1l_0_pereset), ++ /* @GPIO(75) pcie_wake_n1_0 */ ++ PINCTRL_PIN_GROUP("pcie_wake_n1_0", mt7988_pcie_wake_n1_0), ++ /* @GPIO(76) pcie_clk_req_n1 */ ++ PINCTRL_PIN_GROUP("pcie_clk_req_n1", mt7988_pcie_clk_req_n1), ++ /* @GPIO(77) pcie_wake_n2_0 */ ++ PINCTRL_PIN_GROUP("pcie_wake_n2_0", mt7988_pcie_wake_n2_0), ++ /* @GPIO(78) pcie_clk_req_n2_0 */ ++ PINCTRL_PIN_GROUP("pcie_clk_req_n2_0", mt7988_pcie_clk_req_n2_0), ++ /* @GPIO(79) drv_vbus */ ++ PINCTRL_PIN_GROUP("drv_vbus", mt7988_drv_vbus), ++ /* @GPIO(79) pcie_wake_n2_1 */ ++ PINCTRL_PIN_GROUP("pcie_wake_n2_1", mt7988_pcie_wake_n2_1), ++ /* @GPIO(80,81,82,83) uart1_2 */ ++ PINCTRL_PIN_GROUP("uart1_2", mt7988_uart1_2), ++ /* @GPIO(80,81) uart1_2_lite */ ++ PINCTRL_PIN_GROUP("uart1_2_lite", mt7988_uart1_2_lite), ++ /* @GPIO(80) pwm2 */ ++ PINCTRL_PIN_GROUP("pwm2", mt7988_pwm2), ++ /* @GPIO(81) pwm3 */ ++ PINCTRL_PIN_GROUP("pwm3", mt7988_pwm3), ++ /* @GPIO(82) pwm4 */ ++ PINCTRL_PIN_GROUP("pwm4", mt7988_pwm4), ++ /* @GPIO(83) pwm5 */ ++ PINCTRL_PIN_GROUP("pwm5", mt7988_pwm5), ++ /* @GPIO(80) net_wo0_uart_txd_0 */ ++ PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0), ++ /* @GPIO(81) net_wo1_uart_txd_0 */ ++ PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0), ++ /* @GPIO(82) net_wo2_uart_txd_0 */ ++ PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0), ++ /* @GPIO(80,81) tops_uart1_2 */ ++ PINCTRL_PIN_GROUP("tops_uart1_2", mt7988_tops_uart1_2), ++ /* @GPIO(80) net_wo0_uart_txd_1 */ ++ PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7988_net_wo0_uart_txd_1), ++ /* @GPIO(81) net_wo1_uart_txd_1 */ ++ PINCTRL_PIN_GROUP("net_wo1_uart_txd_1", mt7988_net_wo1_uart_txd_1), ++ /* @GPIO(82) net_wo2_uart_txd_1 */ ++ PINCTRL_PIN_GROUP("net_wo2_uart_txd_1", mt7988_net_wo2_uart_txd_1), ++}; ++ ++/* Joint those groups owning the same capability in user point of view which ++ * allows that people tend to use through the device tree. ++ */ ++static const char * const mt7988_jtag_groups[] = { ++ "tops_jtag0_0", "wo0_jtag", "wo1_jtag", ++ "wo2_jtag", "jtag", "tops_jtag0_1", ++}; ++static const char * const mt7988_int_usxgmii_groups[] = { ++ "int_usxgmii", ++}; ++static const char * const mt7988_pwm_groups[] = { ++ "pwm0", "pwm1", "pwm2", "pwm2_0", "pwm3", "pwm3_0", "pwm4", "pwm4_0", ++ "pwm5", "pwm5_0", "pwm6", "pwm6_0", "pwm7", "pwm7_0", ++ ++}; ++static const char * const mt7988_dfd_groups[] = { ++ "dfd", ++}; ++static const char * const mt7988_i2c_groups[] = { ++ "xfi_phy0_i2c0", ++ "xfi_phy1_i2c0", ++ "xfi_phy_pll_i2c0", ++ "xfi_phy_pll_i2c1", ++ "i2c0_0", ++ "i2c1_sfp", ++ "xfi_pextp_phy0_i2c", ++ "xfi_pextp_phy1_i2c", ++ "i2c0_1", ++ "u30_phy_i2c0", ++ "u32_phy_i2c0", ++ "xfi_phy0_i2c1", ++ "xfi_phy1_i2c1", ++ "xfi_phy_pll_i2c2", ++ "i2c1_0", ++ "u30_phy_i2c1", ++ "u32_phy_i2c1", ++ "xfi_phy_pll_i2c3", ++ "sgmii0_i2c", ++ "sgmii1_i2c", ++ "i2c1_2", ++ "i2c2_0", ++ "i2c2_1", ++}; ++static const char * const mt7988_ethernet_groups[] = { ++ "mdc_mdio0", ++ "2p5g_ext_mdio", ++ "gbe_ext_mdio", ++ "mdc_mdio1", ++}; ++static const char * const mt7988_pcie_groups[] = { ++ "pcie_wake_n0_0", "pcie_clk_req_n0_0", "pcie_wake_n3_0", ++ "pcie_clk_req_n3", "pcie_p0_phy_i2c", "pcie_p1_phy_i2c", ++ "pcie_p3_phy_i2c", "pcie_p2_phy_i2c", "ckm_phy_i2c", ++ "pcie_wake_n0_1", "pcie_wake_n3_1", "pcie_2l_0_pereset", ++ "pcie_1l_1_pereset", "pcie_clk_req_n2_1", "pcie_2l_1_pereset", ++ "pcie_1l_0_pereset", "pcie_wake_n1_0", "pcie_clk_req_n1", ++ "pcie_wake_n2_0", "pcie_clk_req_n2_0", "pcie_wake_n2_1", ++ "pcie_clk_req_n0_1" ++}; ++static const char * const mt7988_pmic_groups[] = { ++ "pmic", ++}; ++static const char * const mt7988_wdt_groups[] = { ++ "watchdog", ++}; ++static const char * const mt7988_spi_groups[] = { ++ "spi0", "spi0_wp_hold", "spi1", "spi2", "spi2_wp_hold", ++}; ++static const char * const mt7988_flash_groups[] = { "emmc_45", "sdcard", "snfi", ++ "emmc_51" }; ++static const char * const mt7988_uart_groups[] = { ++ "uart2", ++ "tops_uart0_0", ++ "uart2_0", ++ "uart1_0", ++ "uart2_1", ++ "net_wo0_uart_txd_0", ++ "net_wo1_uart_txd_0", ++ "net_wo2_uart_txd_0", ++ "tops_uart1_0", ++ "ops_uart0_1", ++ "ops_uart1_1", ++ "uart0", ++ "tops_uart0_2", ++ "uart1_1", ++ "uart2_3", ++ "uart1_2", ++ "uart1_2_lite", ++ "tops_uart1_2", ++ "net_wo0_uart_txd_1", ++ "net_wo1_uart_txd_1", ++ "net_wo2_uart_txd_1", ++}; ++static const char * const mt7988_udi_groups[] = { ++ "udi", ++}; ++static const char * const mt7988_audio_groups[] = { ++ "i2s", "pcm", ++}; ++static const char * const mt7988_led_groups[] = { ++ "gbe0_led1", "gbe1_led1", "gbe2_led1", "gbe3_led1", "2p5gbe_led1", ++ "gbe0_led0", "gbe1_led0", "gbe2_led0", "gbe3_led0", "2p5gbe_led0", ++ "wf5g_led0", "wf5g_led1", ++}; ++static const char * const mt7988_usb_groups[] = { ++ "drv_vbus", ++ "drv_vbus_p1", ++}; ++ ++static const struct function_desc mt7988_functions[] = { ++ { { "audio", mt7988_audio_groups, ARRAY_SIZE(mt7988_audio_groups) }, ++ NULL }, ++ { { "jtag", mt7988_jtag_groups, ARRAY_SIZE(mt7988_jtag_groups) }, ++ NULL }, ++ { { "int_usxgmii", mt7988_int_usxgmii_groups, ++ ARRAY_SIZE(mt7988_int_usxgmii_groups) }, ++ NULL }, ++ { { "pwm", mt7988_pwm_groups, ARRAY_SIZE(mt7988_pwm_groups) }, NULL }, ++ { { "dfd", mt7988_dfd_groups, ARRAY_SIZE(mt7988_dfd_groups) }, NULL }, ++ { { "i2c", mt7988_i2c_groups, ARRAY_SIZE(mt7988_i2c_groups) }, NULL }, ++ { { "eth", mt7988_ethernet_groups, ARRAY_SIZE(mt7988_ethernet_groups) }, ++ NULL }, ++ { { "pcie", mt7988_pcie_groups, ARRAY_SIZE(mt7988_pcie_groups) }, ++ NULL }, ++ { { "pmic", mt7988_pmic_groups, ARRAY_SIZE(mt7988_pmic_groups) }, ++ NULL }, ++ { { "watchdog", mt7988_wdt_groups, ARRAY_SIZE(mt7988_wdt_groups) }, ++ NULL }, ++ { { "spi", mt7988_spi_groups, ARRAY_SIZE(mt7988_spi_groups) }, NULL }, ++ { { "flash", mt7988_flash_groups, ARRAY_SIZE(mt7988_flash_groups) }, ++ NULL }, ++ { { "uart", mt7988_uart_groups, ARRAY_SIZE(mt7988_uart_groups) }, ++ NULL }, ++ { { "udi", mt7988_udi_groups, ARRAY_SIZE(mt7988_udi_groups) }, NULL }, ++ { { "usb", mt7988_usb_groups, ARRAY_SIZE(mt7988_usb_groups) }, NULL }, ++ { { "led", mt7988_led_groups, ARRAY_SIZE(mt7988_led_groups) }, NULL }, ++}; ++ ++static const struct mtk_eint_hw mt7988_eint_hw = { ++ .port_mask = 7, ++ .ports = 7, ++ .ap_num = ARRAY_SIZE(mt7988_pins), ++ .db_cnt = 16, ++}; ++ ++static const char * const mt7988_pinctrl_register_base_names[] = { ++ "gpio", "iocfg_tr", "iocfg_br", ++ "iocfg_rb", "iocfg_lb", "iocfg_tl", ++}; ++ ++static const struct mtk_pin_soc mt7988_data = { ++ .reg_cal = mt7988_reg_cals, ++ .pins = mt7988_pins, ++ .npins = ARRAY_SIZE(mt7988_pins), ++ .grps = mt7988_groups, ++ .ngrps = ARRAY_SIZE(mt7988_groups), ++ .funcs = mt7988_functions, ++ .nfuncs = ARRAY_SIZE(mt7988_functions), ++ .eint_hw = &mt7988_eint_hw, ++ .gpio_m = 0, ++ .ies_present = false, ++ .base_names = mt7988_pinctrl_register_base_names, ++ .nbase_names = ARRAY_SIZE(mt7988_pinctrl_register_base_names), ++ .bias_disable_set = mtk_pinconf_bias_disable_set, ++ .bias_disable_get = mtk_pinconf_bias_disable_get, ++ .bias_set = mtk_pinconf_bias_set, ++ .bias_get = mtk_pinconf_bias_get, ++ .pull_type = mt7988_pull_type, ++ .bias_set_combo = mtk_pinconf_bias_set_combo, ++ .bias_get_combo = mtk_pinconf_bias_get_combo, ++ .drive_set = mtk_pinconf_drive_set_rev1, ++ .drive_get = mtk_pinconf_drive_get_rev1, ++ .adv_pull_get = mtk_pinconf_adv_pull_get, ++ .adv_pull_set = mtk_pinconf_adv_pull_set, ++}; ++ ++static const struct of_device_id mt7988_pinctrl_of_match[] = { ++ { .compatible = "mediatek,mt7988-pinctrl" }, ++ {} ++}; ++ ++static int mt7988_pinctrl_probe(struct platform_device *pdev) ++{ ++ return mtk_moore_pinctrl_probe(pdev, &mt7988_data); ++} ++ ++static struct platform_driver mt7988_pinctrl_driver = { ++ .driver = { ++ .name = "mt7988-pinctrl", ++ .of_match_table = mt7988_pinctrl_of_match, ++ }, ++ .probe = mt7988_pinctrl_probe, ++}; ++ ++static int __init mt7988_pinctrl_init(void) ++{ ++ return platform_driver_register(&mt7988_pinctrl_driver); ++} ++arch_initcall(mt7988_pinctrl_init); diff --git a/target/linux/mediatek/patches-6.12/012-v6.14-pinctrl-mediatek-Drop-mtk_pinconf_bias_set_pd.patch b/target/linux/mediatek/patches-6.12/012-v6.14-pinctrl-mediatek-Drop-mtk_pinconf_bias_set_pd.patch new file mode 100644 index 00000000000..e615e393450 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/012-v6.14-pinctrl-mediatek-Drop-mtk_pinconf_bias_set_pd.patch @@ -0,0 +1,41 @@ +From 0e18b099672160698dfbd7c3c82e03e011c907e6 Mon Sep 17 00:00:00 2001 +From: Linus Walleij +Date: Wed, 8 Jan 2025 22:52:44 +0100 +Subject: [PATCH] pinctrl: mediatek: Drop mtk_pinconf_bias_set_pd() + +This function is unused and causing compile errors, delete it. + +Reported-by: Stephen Rothwell +Link: https://lore.kernel.org/linux-next/20250106164630.4447cd0d@canb.auug.org.au/ +Signed-off-by: Linus Walleij +--- + .../pinctrl/mediatek/pinctrl-mtk-common-v2.c | 18 ------------------ + 1 file changed, 18 deletions(-) + +--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c +@@ -599,24 +599,6 @@ static int mtk_pinconf_bias_set_pu_pd(st + return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd); + } + +-static int mtk_pinconf_bias_set_pd(struct mtk_pinctrl *hw, +- const struct mtk_pin_desc *desc, +- u32 pullup, u32 arg) +-{ +- int err, pd; +- +- if (arg != MTK_DISABLE && arg != MTK_ENABLE) +- return -EINVAL; +- +- if (arg == MTK_DISABLE || pullup) +- pd = 0; +- else if (!pullup) +- pd = 1; +- +- return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd); +- +-} +- + static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw, + const struct mtk_pin_desc *desc, + u32 pullup, u32 arg) diff --git a/target/linux/mediatek/patches-6.12/020-v6.13-arm64-dts-mediatek-mt7988-add-UART-controllers.patch b/target/linux/mediatek/patches-6.12/020-v6.13-arm64-dts-mediatek-mt7988-add-UART-controllers.patch new file mode 100644 index 00000000000..2c0afbe01c0 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/020-v6.13-arm64-dts-mediatek-mt7988-add-UART-controllers.patch @@ -0,0 +1,71 @@ +From 52e2ca3be4b6d451fef0a2cd337157dd021b830f Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Wed, 5 Jun 2024 10:54:33 +0200 +Subject: [PATCH 01/32] arm64: dts: mediatek: mt7988: add UART controllers +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +MT7988 has three on-SoC UART controllers that support M16C450 and +M16550A modes. + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20240605085433.26513-2-zajec5@gmail.com +Signed-off-by: Matthias Brugger +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 35 ++++++++++++++++++++++- + 1 file changed, 34 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -86,7 +86,7 @@ + #clock-cells = <1>; + }; + +- clock-controller@1001b000 { ++ topckgen: clock-controller@1001b000 { + compatible = "mediatek,mt7988-topckgen", "syscon"; + reg = <0 0x1001b000 0 0x1000>; + #clock-cells = <1>; +@@ -124,6 +124,39 @@ + status = "disabled"; + }; + ++ serial@11000000 { ++ compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; ++ reg = <0 0x11000000 0 0x100>; ++ interrupts = ; ++ interrupt-names = "uart", "wakeup"; ++ clocks = <&topckgen CLK_TOP_UART_SEL>, ++ <&infracfg CLK_INFRA_52M_UART0_CK>; ++ clock-names = "baud", "bus"; ++ status = "disabled"; ++ }; ++ ++ serial@11000100 { ++ compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; ++ reg = <0 0x11000100 0 0x100>; ++ interrupts = ; ++ interrupt-names = "uart", "wakeup"; ++ clocks = <&topckgen CLK_TOP_UART_SEL>, ++ <&infracfg CLK_INFRA_52M_UART1_CK>; ++ clock-names = "baud", "bus"; ++ status = "disabled"; ++ }; ++ ++ serial@11000200 { ++ compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; ++ reg = <0 0x11000200 0 0x100>; ++ interrupts = ; ++ interrupt-names = "uart", "wakeup"; ++ clocks = <&topckgen CLK_TOP_UART_SEL>, ++ <&infracfg CLK_INFRA_52M_UART2_CK>; ++ clock-names = "baud", "bus"; ++ status = "disabled"; ++ }; ++ + i2c@11003000 { + compatible = "mediatek,mt7981-i2c"; + reg = <0 0x11003000 0 0x1000>, diff --git a/target/linux/mediatek/patches-6.12/021-v6.13-arm64-dts-mediatek-mt7988-add-efuse-block.patch b/target/linux/mediatek/patches-6.12/021-v6.13-arm64-dts-mediatek-mt7988-add-efuse-block.patch new file mode 100644 index 00000000000..bf4e7a3b63f --- /dev/null +++ b/target/linux/mediatek/patches-6.12/021-v6.13-arm64-dts-mediatek-mt7988-add-efuse-block.patch @@ -0,0 +1,35 @@ +From 390529e00d5586eb6d7f4c33c23dee7f43ac14e7 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Thu, 13 Jun 2024 21:59:33 +0200 +Subject: [PATCH 02/32] arm64: dts: mediatek: mt7988: add efuse block +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +MT7988 (AKA MediaTek Filogic 880) uses efuse for storing calibration +data. + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +Link: https://lore.kernel.org/r/20240613195933.31089-2-zajec5@gmail.com +Signed-off-by: Matthias Brugger +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -234,6 +234,13 @@ + #clock-cells = <1>; + }; + ++ efuse@11f50000 { ++ compatible = "mediatek,mt7988-efuse", "mediatek,efuse"; ++ reg = <0 0x11f50000 0 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ }; ++ + clock-controller@15000000 { + compatible = "mediatek,mt7988-ethsys", "syscon"; + reg = <0 0x15000000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.12/022-v6.14-arm64-dts-mediatek-mt7988-Add-pinctrl-support.patch b/target/linux/mediatek/patches-6.12/022-v6.14-arm64-dts-mediatek-mt7988-Add-pinctrl-support.patch new file mode 100644 index 00000000000..90ec3186ebd --- /dev/null +++ b/target/linux/mediatek/patches-6.12/022-v6.14-arm64-dts-mediatek-mt7988-Add-pinctrl-support.patch @@ -0,0 +1,85 @@ +From a01cc71a8c55e7fc12cb37109953ad9c58a12d4f Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 09:54:29 +0100 +Subject: [PATCH 03/32] arm64: dts: mediatek: mt7988: Add pinctrl support + +Add mt7988a pinctrl node. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217085435.9586-5-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 54 +++++++++++++++++++++++ + 1 file changed, 54 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -3,6 +3,7 @@ + #include + #include + #include ++#include + + / { + compatible = "mediatek,mt7988a"; +@@ -105,6 +106,59 @@ + #clock-cells = <1>; + }; + ++ pio: pinctrl@1001f000 { ++ compatible = "mediatek,mt7988-pinctrl"; ++ reg = <0 0x1001f000 0 0x1000>, ++ <0 0x11c10000 0 0x1000>, ++ <0 0x11d00000 0 0x1000>, ++ <0 0x11d20000 0 0x1000>, ++ <0 0x11e00000 0 0x1000>, ++ <0 0x11f00000 0 0x1000>, ++ <0 0x1000b000 0 0x1000>; ++ reg-names = "gpio", "iocfg_tr", ++ "iocfg_br", "iocfg_rb", ++ "iocfg_lb", "iocfg_tl", "eint"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-ranges = <&pio 0 0 84>; ++ interrupt-controller; ++ interrupts = ; ++ interrupt-parent = <&gic>; ++ #interrupt-cells = <2>; ++ ++ pcie0_pins: pcie0-pins { ++ mux { ++ function = "pcie"; ++ groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", ++ "pcie_wake_n0_0"; ++ }; ++ }; ++ ++ pcie1_pins: pcie1-pins { ++ mux { ++ function = "pcie"; ++ groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", ++ "pcie_wake_n1_0"; ++ }; ++ }; ++ ++ pcie2_pins: pcie2-pins { ++ mux { ++ function = "pcie"; ++ groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", ++ "pcie_wake_n2_0"; ++ }; ++ }; ++ ++ pcie3_pins: pcie3-pins { ++ mux { ++ function = "pcie"; ++ groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", ++ "pcie_wake_n3_0"; ++ }; ++ }; ++ }; ++ + pwm@10048000 { + compatible = "mediatek,mt7988-pwm"; + reg = <0 0x10048000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.12/023-v6.14-arm64-dts-mediatek-mt7988-Add-reserved-memory.patch b/target/linux/mediatek/patches-6.12/023-v6.14-arm64-dts-mediatek-mt7988-Add-reserved-memory.patch new file mode 100644 index 00000000000..043530c994c --- /dev/null +++ b/target/linux/mediatek/patches-6.12/023-v6.14-arm64-dts-mediatek-mt7988-Add-reserved-memory.patch @@ -0,0 +1,37 @@ +From b3bb498ff23f5bcaa95614e0f8c9176690af8acb Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:15 +0100 +Subject: [PATCH 04/32] arm64: dts: mediatek: mt7988: Add reserved memory + +Add memory range handled by ATF to not be touched by linux kernel. +ATF is SoC specific and not board-specific so add it to mt7988.dtsi. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-2-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -62,6 +62,18 @@ + method = "smc"; + }; + ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */ ++ secmon@43000000 { ++ reg = <0 0x43000000 0 0x50000>; ++ no-map; ++ }; ++ }; ++ + soc { + compatible = "simple-bus"; + ranges; diff --git a/target/linux/mediatek/patches-6.12/024-v6.14-arm64-dts-mediatek-mt7988-Add-mmc-support.patch b/target/linux/mediatek/patches-6.12/024-v6.14-arm64-dts-mediatek-mt7988-Add-mmc-support.patch new file mode 100644 index 00000000000..a52f443d836 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/024-v6.14-arm64-dts-mediatek-mt7988-Add-mmc-support.patch @@ -0,0 +1,52 @@ +From de6ba1a3ef621762394e841888de3e0ed127e20a Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:16 +0100 +Subject: [PATCH 05/32] arm64: dts: mediatek: mt7988: Add mmc support + +Add devicetree node for MMC controller. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-3-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 21 ++++++++++++++++++++- + 1 file changed, 20 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -112,7 +112,7 @@ + #reset-cells = <1>; + }; + +- clock-controller@1001e000 { ++ apmixedsys: clock-controller@1001e000 { + compatible = "mediatek,mt7988-apmixedsys"; + reg = <0 0x1001e000 0 0x1000>; + #clock-cells = <1>; +@@ -293,6 +293,25 @@ + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; + }; + ++ mmc0: mmc@11230000 { ++ compatible = "mediatek,mt7988-mmc"; ++ reg = <0 0x11230000 0 0x1000>, ++ <0 0x11D60000 0 0x1000>; ++ interrupts = ; ++ clocks = <&infracfg CLK_INFRA_MSDC400>, ++ <&infracfg CLK_INFRA_MSDC2_HCK>, ++ <&infracfg CLK_INFRA_66M_MSDC_0_HCK>, ++ <&infracfg CLK_INFRA_133M_MSDC_0_HCK>; ++ assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>, ++ <&topckgen CLK_TOP_EMMC_400M_SEL>; ++ assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>, ++ <&apmixedsys CLK_APMIXED_MSDCPLL>; ++ clock-names = "source", "hclk", "axi_cg", "ahb_cg"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + clock-controller@11f40000 { + compatible = "mediatek,mt7988-xfi-pll"; + reg = <0 0x11f40000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.12/025-v6.14-arm64-dts-mediatek-mt7988-Add-lvts-node.patch b/target/linux/mediatek/patches-6.12/025-v6.14-arm64-dts-mediatek-mt7988-Add-lvts-node.patch new file mode 100644 index 00000000000..b878d20f2e0 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/025-v6.14-arm64-dts-mediatek-mt7988-Add-lvts-node.patch @@ -0,0 +1,62 @@ +From f07e0e093c42736df56f4830179c19f48f8b0725 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:17 +0100 +Subject: [PATCH 06/32] arm64: dts: mediatek: mt7988: Add lvts node + +Add Low Voltage Thermal Sensor (LVTS) node for mt7988 SoC. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-4-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -4,6 +4,7 @@ + #include + #include + #include ++#include + + / { + compatible = "mediatek,mt7988a"; +@@ -97,6 +98,7 @@ + compatible = "mediatek,mt7988-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; ++ #reset-cells = <1>; + }; + + topckgen: clock-controller@1001b000 { +@@ -265,6 +267,17 @@ + status = "disabled"; + }; + ++ lvts: lvts@1100a000 { ++ compatible = "mediatek,mt7988-lvts-ap"; ++ #thermal-sensor-cells = <1>; ++ reg = <0 0x1100a000 0 0x1000>; ++ clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>; ++ interrupts = ; ++ resets = <&infracfg MT7988_INFRA_RST1_THERM_CTRL_SWRST>; ++ nvmem-cells = <&lvts_calibration>; ++ nvmem-cell-names = "lvts-calib-data-1"; ++ }; ++ + usb@11190000 { + compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11190000 0 0x2e00>, +@@ -324,6 +337,10 @@ + reg = <0 0x11f50000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; ++ ++ lvts_calibration: calib@918 { ++ reg = <0x918 0x28>; ++ }; + }; + + clock-controller@15000000 { diff --git a/target/linux/mediatek/patches-6.12/026-v6.14-arm64-dts-mediatek-mt7988-Add-thermal-zone.patch b/target/linux/mediatek/patches-6.12/026-v6.14-arm64-dts-mediatek-mt7988-Add-thermal-zone.patch new file mode 100644 index 00000000000..e0ff078164d --- /dev/null +++ b/target/linux/mediatek/patches-6.12/026-v6.14-arm64-dts-mediatek-mt7988-Add-thermal-zone.patch @@ -0,0 +1,39 @@ +From 122ed9fc41b948d79ac357f95f5438a4bd6786b8 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:18 +0100 +Subject: [PATCH 07/32] arm64: dts: mediatek: mt7988: Add thermal-zone + +Add basic thermal-zone node. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-5-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -358,6 +358,21 @@ + }; + }; + ++ thermal-zones { ++ cpu_thermal: cpu-thermal { ++ polling-delay-passive = <1000>; ++ polling-delay = <1000>; ++ thermal-sensors = <&lvts 0>; ++ trips { ++ cpu_trip_crit: crit { ++ temperature = <125000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ }; ++ + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; diff --git a/target/linux/mediatek/patches-6.12/027-v6.14-arm64-dts-mediatek-mt7988-Add-mcu-sys-node-for-cpu.patch b/target/linux/mediatek/patches-6.12/027-v6.14-arm64-dts-mediatek-mt7988-Add-mcu-sys-node-for-cpu.patch new file mode 100644 index 00000000000..551dca3c091 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/027-v6.14-arm64-dts-mediatek-mt7988-Add-mcu-sys-node-for-cpu.patch @@ -0,0 +1,31 @@ +From 7fa08d530548ed57752703e9f011eeeb809ef9b0 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:20 +0100 +Subject: [PATCH 08/32] arm64: dts: mediatek: mt7988: Add mcu-sys node for cpu + +In preparation for adding support for CPU DVFS and clock tables for it, +add the MCUSYS clock controller node. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-7-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -192,6 +192,12 @@ + status = "disabled"; + }; + ++ mcusys: mcusys@100e0000 { ++ compatible = "mediatek,mt7988-mcusys", "syscon"; ++ reg = <0 0x100e0000 0 0x1000>; ++ #clock-cells = <1>; ++ }; ++ + serial@11000000 { + compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; + reg = <0 0x11000000 0 0x100>; diff --git a/target/linux/mediatek/patches-6.12/028-v6.14-arm64-dts-mediatek-mt7988-Add-CPU-OPP-table-for-cloc.patch b/target/linux/mediatek/patches-6.12/028-v6.14-arm64-dts-mediatek-mt7988-Add-CPU-OPP-table-for-cloc.patch new file mode 100644 index 00000000000..e2bec750e4e --- /dev/null +++ b/target/linux/mediatek/patches-6.12/028-v6.14-arm64-dts-mediatek-mt7988-Add-CPU-OPP-table-for-cloc.patch @@ -0,0 +1,84 @@ +From b10331c8faa1208c61fb98d9b65da2828e239113 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:21 +0100 +Subject: [PATCH 09/32] arm64: dts: mediatek: mt7988: Add CPU OPP table for + clock scaling + +Add operating points defining frequency/voltages of cpu cores. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-8-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 38 +++++++++++++++++++++++ + 1 file changed, 38 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -21,6 +21,10 @@ + reg = <0x0>; + device_type = "cpu"; + enable-method = "psci"; ++ clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, ++ <&topckgen CLK_TOP_XTAL>; ++ clock-names = "cpu", "intermediate"; ++ operating-points-v2 = <&cluster0_opp>; + }; + + cpu@1 { +@@ -28,6 +32,10 @@ + reg = <0x1>; + device_type = "cpu"; + enable-method = "psci"; ++ clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, ++ <&topckgen CLK_TOP_XTAL>; ++ clock-names = "cpu", "intermediate"; ++ operating-points-v2 = <&cluster0_opp>; + }; + + cpu@2 { +@@ -35,6 +43,10 @@ + reg = <0x2>; + device_type = "cpu"; + enable-method = "psci"; ++ clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, ++ <&topckgen CLK_TOP_XTAL>; ++ clock-names = "cpu", "intermediate"; ++ operating-points-v2 = <&cluster0_opp>; + }; + + cpu@3 { +@@ -42,6 +54,32 @@ + reg = <0x3>; + device_type = "cpu"; + enable-method = "psci"; ++ clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, ++ <&topckgen CLK_TOP_XTAL>; ++ clock-names = "cpu", "intermediate"; ++ operating-points-v2 = <&cluster0_opp>; ++ }; ++ ++ cluster0_opp: opp-table-0 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-800000000 { ++ opp-hz = /bits/ 64 <800000000>; ++ opp-microvolt = <850000>; ++ }; ++ opp-1100000000 { ++ opp-hz = /bits/ 64 <1100000000>; ++ opp-microvolt = <850000>; ++ }; ++ opp-1500000000 { ++ opp-hz = /bits/ 64 <1500000000>; ++ opp-microvolt = <850000>; ++ }; ++ opp-1800000000 { ++ opp-hz = /bits/ 64 <1800000000>; ++ opp-microvolt = <900000>; ++ }; + }; + }; + diff --git a/target/linux/mediatek/patches-6.12/029-v6.14-arm64-dts-mediatek-mt7988-Disable-usb-controllers-by.patch b/target/linux/mediatek/patches-6.12/029-v6.14-arm64-dts-mediatek-mt7988-Disable-usb-controllers-by.patch new file mode 100644 index 00000000000..f65d23bc0a1 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/029-v6.14-arm64-dts-mediatek-mt7988-Disable-usb-controllers-by.patch @@ -0,0 +1,34 @@ +From 39bb12c26f556046e55f3638e2e4184bfbfd0564 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:22 +0100 +Subject: [PATCH 10/32] arm64: dts: mediatek: mt7988: Disable usb controllers + by default + +The controllers should be enabled at board level if used. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-9-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -334,6 +334,7 @@ + <&infracfg CLK_INFRA_133M_USB_HCK>, + <&infracfg CLK_INFRA_USB_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; ++ status = "disabled"; + }; + + usb@11200000 { +@@ -348,6 +349,7 @@ + <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>, + <&infracfg CLK_INFRA_USB_XHCI_CK_P1>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; ++ status = "disabled"; + }; + + mmc0: mmc@11230000 { diff --git a/target/linux/mediatek/patches-6.12/030-v6.14-arm64-dts-mediatek-mt7988-Add-t-phy-for-ssusb1.patch b/target/linux/mediatek/patches-6.12/030-v6.14-arm64-dts-mediatek-mt7988-Add-t-phy-for-ssusb1.patch new file mode 100644 index 00000000000..c53db06c39d --- /dev/null +++ b/target/linux/mediatek/patches-6.12/030-v6.14-arm64-dts-mediatek-mt7988-Add-t-phy-for-ssusb1.patch @@ -0,0 +1,59 @@ +From 46d056b6c2376d3ef866f9ab5212879c97588892 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:23 +0100 +Subject: [PATCH 11/32] arm64: dts: mediatek: mt7988: Add t-phy for ssusb1 + +USB controller needs phys for working properly. +On mt7988 ssusb0 uses a xs-phy, ssusb uses t-phy. +For now add the t-phy for ssusb1. We can reuse the mt7986 compatible +here. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-10-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 25 +++++++++++++++++++++++ + 1 file changed, 25 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -349,6 +349,8 @@ + <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>, + <&infracfg CLK_INFRA_USB_XHCI_CK_P1>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; ++ phys = <&tphyu2port0 PHY_TYPE_USB2>, ++ <&tphyu3port0 PHY_TYPE_USB3>; + status = "disabled"; + }; + +@@ -371,6 +373,29 @@ + status = "disabled"; + }; + ++ t-phy@11c50000 { ++ compatible = "mediatek,mt7986-tphy", ++ "mediatek,generic-tphy-v2"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ status = "disabled"; ++ ++ tphyu2port0: usb-phy@11c50000 { ++ reg = <0 0x11c50000 0 0x700>; ++ clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>; ++ clock-names = "ref"; ++ #phy-cells = <1>; ++ }; ++ ++ tphyu3port0: usb-phy@11c50700 { ++ reg = <0 0x11c50700 0 0x900>; ++ clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>; ++ clock-names = "ref"; ++ #phy-cells = <1>; ++ }; ++ }; ++ + clock-controller@11f40000 { + compatible = "mediatek,mt7988-xfi-pll"; + reg = <0 0x11f40000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.12/031-v6.14-arm64-dts-mediatek-mt7988-Add-pcie-nodes.patch b/target/linux/mediatek/patches-6.12/031-v6.14-arm64-dts-mediatek-mt7988-Add-pcie-nodes.patch new file mode 100644 index 00000000000..fe27e5223cb --- /dev/null +++ b/target/linux/mediatek/patches-6.12/031-v6.14-arm64-dts-mediatek-mt7988-Add-pcie-nodes.patch @@ -0,0 +1,176 @@ +From aac2eb27ee500ca2828fe0fd1895ec6f9ef83787 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:24 +0100 +Subject: [PATCH 12/32] arm64: dts: mediatek: mt7988: Add pcie nodes + +Add pcie controllers for mt7988. Reuse mt7986 compatible. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-11-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 152 ++++++++++++++++++++++ + 1 file changed, 152 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -373,6 +373,158 @@ + status = "disabled"; + }; + ++ pcie@11280000 { ++ compatible = "mediatek,mt7986-pcie", ++ "mediatek,mt8192-pcie"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ reg = <0 0x11280000 0 0x2000>; ++ reg-names = "pcie-mac"; ++ linux,pci-domain = <3>; ++ interrupts = ; ++ bus-range = <0x00 0xff>; ++ ranges = <0x81000000 0x00 0x20000000 0x00 ++ 0x20000000 0x00 0x00200000>, ++ <0x82000000 0x00 0x20200000 0x00 ++ 0x20200000 0x00 0x07e00000>; ++ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>, ++ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>, ++ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>, ++ <&infracfg CLK_INFRA_133M_PCIE_CK_P2>; ++ clock-names = "pl_250m", "tl_26m", "peri_26m", ++ "top_133m"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_pins>; ++ status = "disabled"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &pcie_intc2 0>, ++ <0 0 0 2 &pcie_intc2 1>, ++ <0 0 0 3 &pcie_intc2 2>, ++ <0 0 0 4 &pcie_intc2 3>; ++ pcie_intc2: interrupt-controller { ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ ++ pcie@11290000 { ++ compatible = "mediatek,mt7986-pcie", ++ "mediatek,mt8192-pcie"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ reg = <0 0x11290000 0 0x2000>; ++ reg-names = "pcie-mac"; ++ linux,pci-domain = <2>; ++ interrupts = ; ++ bus-range = <0x00 0xff>; ++ ranges = <0x81000000 0x00 0x28000000 0x00 ++ 0x28000000 0x00 0x00200000>, ++ <0x82000000 0x00 0x28200000 0x00 ++ 0x28200000 0x00 0x07e00000>; ++ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>, ++ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>, ++ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>, ++ <&infracfg CLK_INFRA_133M_PCIE_CK_P3>; ++ clock-names = "pl_250m", "tl_26m", "peri_26m", ++ "top_133m"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie3_pins>; ++ status = "disabled"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &pcie_intc3 0>, ++ <0 0 0 2 &pcie_intc3 1>, ++ <0 0 0 3 &pcie_intc3 2>, ++ <0 0 0 4 &pcie_intc3 3>; ++ pcie_intc3: interrupt-controller { ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ ++ pcie@11300000 { ++ compatible = "mediatek,mt7986-pcie", ++ "mediatek,mt8192-pcie"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ reg = <0 0x11300000 0 0x2000>; ++ reg-names = "pcie-mac"; ++ linux,pci-domain = <0>; ++ interrupts = ; ++ bus-range = <0x00 0xff>; ++ ranges = <0x81000000 0x00 0x30000000 0x00 ++ 0x30000000 0x00 0x00200000>, ++ <0x82000000 0x00 0x30200000 0x00 ++ 0x30200000 0x00 0x07e00000>; ++ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>, ++ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>, ++ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>, ++ <&infracfg CLK_INFRA_133M_PCIE_CK_P0>; ++ clock-names = "pl_250m", "tl_26m", "peri_26m", ++ "top_133m"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie0_pins>; ++ status = "disabled"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &pcie_intc0 0>, ++ <0 0 0 2 &pcie_intc0 1>, ++ <0 0 0 3 &pcie_intc0 2>, ++ <0 0 0 4 &pcie_intc0 3>; ++ pcie_intc0: interrupt-controller { ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ ++ pcie@11310000 { ++ compatible = "mediatek,mt7986-pcie", ++ "mediatek,mt8192-pcie"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ reg = <0 0x11310000 0 0x2000>; ++ reg-names = "pcie-mac"; ++ linux,pci-domain = <1>; ++ interrupts = ; ++ bus-range = <0x00 0xff>; ++ ranges = <0x81000000 0x00 0x38000000 0x00 ++ 0x38000000 0x00 0x00200000>, ++ <0x82000000 0x00 0x38200000 0x00 ++ 0x38200000 0x00 0x07e00000>; ++ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>, ++ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>, ++ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>, ++ <&infracfg CLK_INFRA_133M_PCIE_CK_P1>; ++ clock-names = "pl_250m", "tl_26m", "peri_26m", ++ "top_133m"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie1_pins>; ++ status = "disabled"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &pcie_intc1 0>, ++ <0 0 0 2 &pcie_intc1 1>, ++ <0 0 0 3 &pcie_intc1 2>, ++ <0 0 0 4 &pcie_intc1 3>; ++ pcie_intc1: interrupt-controller { ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ + t-phy@11c50000 { + compatible = "mediatek,mt7986-tphy", + "mediatek,generic-tphy-v2"; diff --git a/target/linux/mediatek/patches-6.12/032-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-pinctrl-subnod.patch b/target/linux/mediatek/patches-6.12/032-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-pinctrl-subnod.patch new file mode 100644 index 00000000000..6f0080e6ec8 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/032-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-pinctrl-subnod.patch @@ -0,0 +1,211 @@ +From 6b116c43782a153bcde18bd54d3220d81b476859 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 09:54:30 +0100 +Subject: [PATCH 13/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add pinctrl + subnodes for bpi-r4 + +Add board specific pinctrl configurations on Bananapi R4. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217085435.9586-6-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 189 ++++++++++++++++++ + 1 file changed, 189 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +@@ -9,3 +9,192 @@ + model = "Banana Pi BPI-R4"; + chassis-type = "embedded"; + }; ++ ++&pio { ++ mdio0_pins: mdio0-pins { ++ mux { ++ function = "eth"; ++ groups = "mdc_mdio0"; ++ }; ++ ++ conf { ++ pins = "SMI_0_MDC", "SMI_0_MDIO"; ++ drive-strength = <8>; ++ }; ++ }; ++ ++ i2c0_pins: i2c0-g0-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c0_1"; ++ }; ++ }; ++ ++ i2c1_pins: i2c1-g0-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c1_0"; ++ }; ++ }; ++ ++ i2c1_sfp_pins: i2c1-sfp-g0-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c1_sfp"; ++ }; ++ }; ++ ++ i2c2_0_pins: i2c2-g0-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c2_0"; ++ }; ++ }; ++ ++ i2c2_1_pins: i2c2-g1-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c2_1"; ++ }; ++ }; ++ ++ gbe0_led0_pins: gbe0-led0-pins { ++ mux { ++ function = "led"; ++ groups = "gbe0_led0"; ++ }; ++ }; ++ ++ gbe1_led0_pins: gbe1-led0-pins { ++ mux { ++ function = "led"; ++ groups = "gbe1_led0"; ++ }; ++ }; ++ ++ gbe2_led0_pins: gbe2-led0-pins { ++ mux { ++ function = "led"; ++ groups = "gbe2_led0"; ++ }; ++ }; ++ ++ gbe3_led0_pins: gbe3-led0-pins { ++ mux { ++ function = "led"; ++ groups = "gbe3_led0"; ++ }; ++ }; ++ ++ gbe0_led1_pins: gbe0-led1-pins { ++ mux { ++ function = "led"; ++ groups = "gbe0_led1"; ++ }; ++ }; ++ ++ gbe1_led1_pins: gbe1-led1-pins { ++ mux { ++ function = "led"; ++ groups = "gbe1_led1"; ++ }; ++ }; ++ ++ gbe2_led1_pins: gbe2-led1-pins { ++ mux { ++ function = "led"; ++ groups = "gbe2_led1"; ++ }; ++ }; ++ ++ gbe3_led1_pins: gbe3-led1-pins { ++ mux { ++ function = "led"; ++ groups = "gbe3_led1"; ++ }; ++ }; ++ ++ i2p5gbe_led0_pins: 2p5gbe-led0-pins { ++ mux { ++ function = "led"; ++ groups = "2p5gbe_led0"; ++ }; ++ }; ++ ++ i2p5gbe_led1_pins: 2p5gbe-led1-pins { ++ mux { ++ function = "led"; ++ groups = "2p5gbe_led1"; ++ }; ++ }; ++ ++ mmc0_pins_emmc_45: mmc0-emmc-45-pins { ++ mux { ++ function = "flash"; ++ groups = "emmc_45"; ++ }; ++ }; ++ ++ mmc0_pins_emmc_51: mmc0-emmc-51-pins { ++ mux { ++ function = "flash"; ++ groups = "emmc_51"; ++ }; ++ }; ++ ++ mmc0_pins_sdcard: mmc0-sdcard-pins { ++ mux { ++ function = "flash"; ++ groups = "sdcard"; ++ }; ++ }; ++ ++ uart0_pins: uart0-pins { ++ mux { ++ function = "uart"; ++ groups = "uart0"; ++ }; ++ }; ++ ++ snfi_pins: snfi-pins { ++ mux { ++ function = "flash"; ++ groups = "snfi"; ++ }; ++ }; ++ ++ spi0_pins: spi0-pins { ++ mux { ++ function = "spi"; ++ groups = "spi0"; ++ }; ++ }; ++ ++ spi0_flash_pins: spi0-flash-pins { ++ mux { ++ function = "spi"; ++ groups = "spi0", "spi0_wp_hold"; ++ }; ++ }; ++ ++ spi1_pins: spi1-pins { ++ mux { ++ function = "spi"; ++ groups = "spi1"; ++ }; ++ }; ++ ++ spi2_pins: spi2-pins { ++ mux { ++ function = "spi"; ++ groups = "spi2"; ++ }; ++ }; ++ ++ spi2_flash_pins: spi2-flash-pins { ++ mux { ++ function = "spi"; ++ groups = "spi2", "spi2_wp_hold"; ++ }; ++ }; ++}; diff --git a/target/linux/mediatek/patches-6.12/033-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-watchdog.patch b/target/linux/mediatek/patches-6.12/033-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-watchdog.patch new file mode 100644 index 00000000000..2ce47ed12a0 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/033-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-watchdog.patch @@ -0,0 +1,25 @@ +From 6b6f2f1ee88b8b5763f4112babbc9fc45a94999a Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:25 +0100 +Subject: [PATCH 14/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable watchdog + +Enable the watchdog on Bananapi R4 board. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-12-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +@@ -198,3 +198,7 @@ + }; + }; + }; ++ ++&watchdog { ++ status = "okay"; ++}; diff --git a/target/linux/mediatek/patches-6.12/034-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fixed-regulato.patch b/target/linux/mediatek/patches-6.12/034-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fixed-regulato.patch new file mode 100644 index 00000000000..fb383d041b8 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/034-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fixed-regulato.patch @@ -0,0 +1,48 @@ +From 72b0a6f181c5ca417405e594c80d724baee54813 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:26 +0100 +Subject: [PATCH 15/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add fixed + regulators for 1v8 and 3v3 + +Add regulator nodes used for mmc to Bananapi R4 board. +This board has 1 MMC controller used for SDMMC and eMMC where only one can +be used at one time, selected by hardware switches. SD uses 3v3 for both +supplies and emmc uses both regulators. +So defining both regulators in board dts and referencing them in the dt +overlay. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-13-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +@@ -8,6 +8,24 @@ + compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; + model = "Banana Pi BPI-R4"; + chassis-type = "embedded"; ++ ++ reg_1p8v: regulator-1p8v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-1.8V"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ reg_3p3v: regulator-3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-3.3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; + }; + + &pio { diff --git a/target/linux/mediatek/patches-6.12/035-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-thermal-config.patch b/target/linux/mediatek/patches-6.12/035-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-thermal-config.patch new file mode 100644 index 00000000000..3273e7444c3 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/035-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-thermal-config.patch @@ -0,0 +1,54 @@ +From 67511ea667d3c4da827588fd460772562d7b054e Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:28 +0100 +Subject: [PATCH 16/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add thermal + configuration + +Add additional thermal trips to Bananapi R4 board. +SoC only contains the critical trip. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-15-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 28 +++++++++++++++++++ + 1 file changed, 28 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +@@ -28,6 +28,34 @@ + }; + }; + ++&cpu_thermal { ++ trips { ++ cpu_trip_hot: hot { ++ temperature = <120000>; ++ hysteresis = <2000>; ++ type = "hot"; ++ }; ++ ++ cpu_trip_active_high: active-high { ++ temperature = <115000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ ++ cpu_trip_active_med: active-med { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ ++ cpu_trip_active_low: active-low { ++ temperature = <40000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ }; ++}; ++ + &pio { + mdio0_pins: mdio0-pins { + mux { diff --git a/target/linux/mediatek/patches-6.12/036-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-serial0-deb.patch b/target/linux/mediatek/patches-6.12/036-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-serial0-deb.patch new file mode 100644 index 00000000000..c1d872d1db0 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/036-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-serial0-deb.patch @@ -0,0 +1,41 @@ +From a9df5ed2333b01546b4f906e2f6fd21dd5b146aa Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:29 +0100 +Subject: [PATCH 17/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable serial0 + debug uart + +Enable the debug uart on Bananapi R4 board. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-16-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++ + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 +- + 2 files changed, 5 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +@@ -245,6 +245,10 @@ + }; + }; + ++&serial0 { ++ status = "okay"; ++}; ++ + &watchdog { + status = "okay"; + }; +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -236,7 +236,7 @@ + #clock-cells = <1>; + }; + +- serial@11000000 { ++ serial0: serial@11000000 { + compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; + reg = <0 0x11000000 0 0x100>; + interrupts = ; diff --git a/target/linux/mediatek/patches-6.12/037-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-default-UART-s.patch b/target/linux/mediatek/patches-6.12/037-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-default-UART-s.patch new file mode 100644 index 00000000000..d75b3e57ad9 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/037-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-default-UART-s.patch @@ -0,0 +1,29 @@ +From 3dfb0dcb194e3f32ed931747131be08bfc429522 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:30 +0100 +Subject: [PATCH 18/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add default UART + stdout + +Add chosen node on Bananapi R4 board with stdout and default bootargs. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-17-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +@@ -9,6 +9,10 @@ + model = "Banana Pi BPI-R4"; + chassis-type = "embedded"; + ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; diff --git a/target/linux/mediatek/patches-6.12/038-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-I2C-control.patch b/target/linux/mediatek/patches-6.12/038-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-I2C-control.patch new file mode 100644 index 00000000000..4f48edd4121 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/038-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-I2C-control.patch @@ -0,0 +1,72 @@ +From 90d4eb65db14a3f2e776d2a8b1dc832e70198328 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:31 +0100 +Subject: [PATCH 19/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable I2C + controllers + +Enable the I2C0, I2C2 controllers found on the BananaPi R4 board. +Both controllers are not accessible from user and having fixed spare +devices. I2C0 have a pmic connected, I2C2 is used with I2C-multiplexer +for e.g. SFP cages. +The missing I2C1 is connected to GPIO header which can have either GPIO +mode or I2C mode. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-18-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + .../boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 12 ++++++++++++ + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 6 +++--- + 2 files changed, 15 insertions(+), 3 deletions(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +@@ -60,6 +60,18 @@ + }; + }; + ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++ status = "okay"; ++}; ++ ++&i2c2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_1_pins>; ++ status = "okay"; ++}; ++ + &pio { + mdio0_pins: mdio0-pins { + mux { +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -269,7 +269,7 @@ + status = "disabled"; + }; + +- i2c@11003000 { ++ i2c0: i2c@11003000 { + compatible = "mediatek,mt7981-i2c"; + reg = <0 0x11003000 0 0x1000>, + <0 0x10217080 0 0x80>; +@@ -283,7 +283,7 @@ + status = "disabled"; + }; + +- i2c@11004000 { ++ i2c1: i2c@11004000 { + compatible = "mediatek,mt7981-i2c"; + reg = <0 0x11004000 0 0x1000>, + <0 0x10217100 0 0x80>; +@@ -297,7 +297,7 @@ + status = "disabled"; + }; + +- i2c@11005000 { ++ i2c2: i2c@11005000 { + compatible = "mediatek,mt7981-i2c"; + reg = <0 0x11005000 0 0x1000>, + <0 0x10217180 0 0x80>; diff --git a/target/linux/mediatek/patches-6.12/039-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-PCA9545-I2C-Mu.patch b/target/linux/mediatek/patches-6.12/039-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-PCA9545-I2C-Mu.patch new file mode 100644 index 00000000000..117479b7893 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/039-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-PCA9545-I2C-Mu.patch @@ -0,0 +1,74 @@ +From dde7d741329616025e4cfa350eb3935b495ae140 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:32 +0100 +Subject: [PATCH 20/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add PCA9545 I2C + Mux + +Bananapi R4 uses an i2c multiplexer for SFP slots, rtc and eeprom. +Add its node to the right i2c controller. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-19-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 41 +++++++++++++++++++ + 1 file changed, 41 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +@@ -2,6 +2,8 @@ + + /dts-v1/; + ++#include ++ + #include "mt7988a.dtsi" + + / { +@@ -70,6 +72,45 @@ + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_1_pins>; + status = "okay"; ++ ++ pca9545: i2c-mux@70 { ++ compatible = "nxp,pca9545"; ++ reg = <0x70>; ++ reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ ++ pcf8563: rtc@51 { ++ compatible = "nxp,pcf8563"; ++ reg = <0x51>; ++ #clock-cells = <0>; ++ }; ++ ++ eeprom@57 { ++ compatible = "atmel,24c02"; ++ reg = <0x57>; ++ size = <256>; ++ }; ++ ++ }; ++ ++ i2c_sfp1: i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ }; ++ ++ i2c_sfp2: i2c@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ }; ++ }; + }; + + &pio { diff --git a/target/linux/mediatek/patches-6.12/040-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-t-phy-for-s.patch b/target/linux/mediatek/patches-6.12/040-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-t-phy-for-s.patch new file mode 100644 index 00000000000..e16b30ef303 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/040-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-t-phy-for-s.patch @@ -0,0 +1,41 @@ +From dfe00be85da20d9823d39775c92139c569a7960d Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:33 +0100 +Subject: [PATCH 21/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable t-phy for + ssusb1 + +Bananapi R4 uses t-phy for usb. Enable its node at board level. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-20-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++ + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 +- + 2 files changed, 5 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +@@ -306,6 +306,10 @@ + status = "okay"; + }; + ++&tphy { ++ status = "okay"; ++}; ++ + &watchdog { + status = "okay"; + }; +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -525,7 +525,7 @@ + }; + }; + +- t-phy@11c50000 { ++ tphy: t-phy@11c50000 { + compatible = "mediatek,mt7986-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <2>; diff --git a/target/linux/mediatek/patches-6.12/041-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-ssusb1-on-b.patch b/target/linux/mediatek/patches-6.12/041-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-ssusb1-on-b.patch new file mode 100644 index 00000000000..d1892c6cc15 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/041-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-ssusb1-on-b.patch @@ -0,0 +1,41 @@ +From 2b03ef47273db52e0c0010e963c3626e6842204f Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:34 +0100 +Subject: [PATCH 22/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable ssusb1 on + bpi-r4 + +Enable usb on Bananapi R4 board. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-21-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++ + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 +- + 2 files changed, 5 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +@@ -306,6 +306,10 @@ + status = "okay"; + }; + ++&ssusb1 { ++ status = "okay"; ++}; ++ + &tphy { + status = "okay"; + }; +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -337,7 +337,7 @@ + status = "disabled"; + }; + +- usb@11200000 { ++ ssusb1: usb@11200000 { + compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x2e00>, + <0 0x11203e00 0 0x0100>; diff --git a/target/linux/mediatek/patches-6.12/042-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-pwm.patch b/target/linux/mediatek/patches-6.12/042-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-pwm.patch new file mode 100644 index 00000000000..4e24607e5db --- /dev/null +++ b/target/linux/mediatek/patches-6.12/042-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-pwm.patch @@ -0,0 +1,40 @@ +From b074487a4180aeee440b61fc00a865fc2a4bd32a Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:35 +0100 +Subject: [PATCH 23/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable pwm + +Enable pwm on Bananapi R4 board. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-22-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++ + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 +- + 2 files changed, 5 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +@@ -302,6 +302,10 @@ + }; + }; + ++&pwm { ++ status = "okay"; ++}; ++ + &serial0 { + status = "okay"; + }; +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -211,7 +211,7 @@ + }; + }; + +- pwm@10048000 { ++ pwm: pwm@10048000 { + compatible = "mediatek,mt7988-pwm"; + reg = <0 0x10048000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>, diff --git a/target/linux/mediatek/patches-6.12/043-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-pcie.patch b/target/linux/mediatek/patches-6.12/043-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-pcie.patch new file mode 100644 index 00000000000..a25d2356307 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/043-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-pcie.patch @@ -0,0 +1,83 @@ +From 72bc814e8609e8be59dff8bc6e0e185b5005ace8 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:36 +0100 +Subject: [PATCH 24/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable pcie + +Enable the pci controllers on BPI-R4. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-23-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 20 +++++++++++++++++++ + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 8 ++++---- + 2 files changed, 24 insertions(+), 4 deletions(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +@@ -113,6 +113,26 @@ + }; + }; + ++/* mPCIe SIM2 */ ++&pcie0 { ++ status = "okay"; ++}; ++ ++/* mPCIe SIM3 */ ++&pcie1 { ++ status = "okay"; ++}; ++ ++/* M.2 key-B SIM1 */ ++&pcie2 { ++ status = "okay"; ++}; ++ ++/* M.2 key-M SSD */ ++&pcie3 { ++ status = "okay"; ++}; ++ + &pio { + mdio0_pins: mdio0-pins { + mux { +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -373,7 +373,7 @@ + status = "disabled"; + }; + +- pcie@11280000 { ++ pcie2: pcie@11280000 { + compatible = "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; +@@ -411,7 +411,7 @@ + }; + }; + +- pcie@11290000 { ++ pcie3: pcie@11290000 { + compatible = "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; +@@ -449,7 +449,7 @@ + }; + }; + +- pcie@11300000 { ++ pcie0: pcie@11300000 { + compatible = "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; +@@ -487,7 +487,7 @@ + }; + }; + +- pcie@11310000 { ++ pcie1: pcie@11310000 { + compatible = "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; diff --git a/target/linux/mediatek/patches-6.12/044-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-MediaTek-MT668.patch b/target/linux/mediatek/patches-6.12/044-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-MediaTek-MT668.patch new file mode 100644 index 00000000000..26a5990b609 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/044-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-MediaTek-MT668.patch @@ -0,0 +1,96 @@ +From 84087157052afba2f61cea7c99ccabfe9681b643 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Fri, 20 Dec 2024 17:38:35 +0100 +Subject: [PATCH 25/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add MediaTek + MT6682A/RT5190A PMIC + +Bananapi R4 Board contains a MT6682A pmic which is compatible to rt5190a. +Add its node to the i2 controller. + +The BananaPi R4 board has a MediaTek MT6682A PMIC, a rebrand of the +Richtek RT5190A chip, connected to the I2C0 bus. + +Add the relevant node and, while at it, also configure the regulators +from this PMIC that are used on this board. + +Only Buck2/Buck3 voltage can be controlled by software. + +BUCK4 input is 5V from BUCK1 output, and the resistor (mapped to RP30/RP31 +on BPI-R4) configures BUCK4 output to 1.8V. +LDO input is 3.3V from 3.3VD, and the resistor (mapped to RP38/RP40 on +BPI-R4) configures LDO output to 1.8V. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241220163838.114786-2-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 50 +++++++++++++++++++ + 1 file changed, 50 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +@@ -3,6 +3,7 @@ + /dts-v1/; + + #include ++#include + + #include "mt7988a.dtsi" + +@@ -66,6 +67,55 @@ + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; ++ ++ rt5190a_64: rt5190a@64 { ++ compatible = "richtek,rt5190a"; ++ reg = <0x64>; ++ vin2-supply = <&rt5190_buck1>; ++ vin3-supply = <&rt5190_buck1>; ++ vin4-supply = <&rt5190_buck1>; ++ ++ regulators { ++ rt5190_buck1: buck1 { ++ regulator-name = "rt5190a-buck1"; ++ regulator-min-microvolt = <5090000>; ++ regulator-max-microvolt = <5090000>; ++ regulator-allowed-modes = ++ , ; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ buck2 { ++ regulator-name = "vcore"; ++ regulator-min-microvolt = <600000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ rt5190_buck3: buck3 { ++ regulator-name = "vproc"; ++ regulator-min-microvolt = <600000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-boot-on; ++ }; ++ buck4 { ++ regulator-name = "rt5190a-buck4"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-allowed-modes = ++ , ; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ldo { ++ regulator-name = "rt5190a-ldo"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ }; ++ }; + }; + + &i2c2 { diff --git a/target/linux/mediatek/patches-6.12/045-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-proc-supply-fo.patch b/target/linux/mediatek/patches-6.12/045-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-proc-supply-fo.patch new file mode 100644 index 00000000000..c605e90e5d5 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/045-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-proc-supply-fo.patch @@ -0,0 +1,80 @@ +From c0a17ddd90c2094dfe4610b0d965db8a3b987e32 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Fri, 20 Dec 2024 17:38:36 +0100 +Subject: [PATCH 26/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add proc-supply + for cpus + +Add proc-supply property to cpus on Bananapi R4 board. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241220163838.114786-3-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 16 ++++++++++++++++ + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 8 ++++---- + 2 files changed, 20 insertions(+), 4 deletions(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +@@ -35,6 +35,22 @@ + }; + }; + ++&cpu0 { ++ proc-supply = <&rt5190_buck3>; ++}; ++ ++&cpu1 { ++ proc-supply = <&rt5190_buck3>; ++}; ++ ++&cpu2 { ++ proc-supply = <&rt5190_buck3>; ++}; ++ ++&cpu3 { ++ proc-supply = <&rt5190_buck3>; ++}; ++ + &cpu_thermal { + trips { + cpu_trip_hot: hot { +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -16,7 +16,7 @@ + #address-cells = <1>; + #size-cells = <0>; + +- cpu@0 { ++ cpu0: cpu@0 { + compatible = "arm,cortex-a73"; + reg = <0x0>; + device_type = "cpu"; +@@ -27,7 +27,7 @@ + operating-points-v2 = <&cluster0_opp>; + }; + +- cpu@1 { ++ cpu1: cpu@1 { + compatible = "arm,cortex-a73"; + reg = <0x1>; + device_type = "cpu"; +@@ -38,7 +38,7 @@ + operating-points-v2 = <&cluster0_opp>; + }; + +- cpu@2 { ++ cpu2: cpu@2 { + compatible = "arm,cortex-a73"; + reg = <0x2>; + device_type = "cpu"; +@@ -49,7 +49,7 @@ + operating-points-v2 = <&cluster0_opp>; + }; + +- cpu@3 { ++ cpu3: cpu@3 { + compatible = "arm,cortex-a73"; + reg = <0x3>; + device_type = "cpu"; diff --git a/target/linux/mediatek/patches-6.12/615-phy-phy-mtk-xsphy-support-type-switch-by-pericfg.patch b/target/linux/mediatek/patches-6.12/050-v6.16-phy-mediatek-xsphy-support-type-switch-by-pericfg.patch similarity index 87% rename from target/linux/mediatek/patches-6.12/615-phy-phy-mtk-xsphy-support-type-switch-by-pericfg.patch rename to target/linux/mediatek/patches-6.12/050-v6.16-phy-mediatek-xsphy-support-type-switch-by-pericfg.patch index a597f70caa5..a543ecbaa3f 100644 --- a/target/linux/mediatek/patches-6.12/615-phy-phy-mtk-xsphy-support-type-switch-by-pericfg.patch +++ b/target/linux/mediatek/patches-6.12/050-v6.16-phy-mediatek-xsphy-support-type-switch-by-pericfg.patch @@ -1,6 +1,6 @@ -From 50cefacc6c001eea1d9b1c78ba27304566f304f1 Mon Sep 17 00:00:00 2001 +From b7ae3528a588a4006ff9c9cc581efa317df1c1ed Mon Sep 17 00:00:00 2001 From: Daniel Golle -Date: Fri, 2 Jun 2023 13:06:26 +0800 +Date: Tue, 22 Apr 2025 15:24:29 +0200 Subject: [PATCH] phy: mediatek: xsphy: support type switch by pericfg Patch from Sam Shih found in MediaTek SDK @@ -10,9 +10,11 @@ Get syscon and use it to set the PHY type. Extend support to PCIe and SGMII mode in addition to USB2 and USB3. Signed-off-by: Daniel Golle +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno --- - drivers/phy/mediatek/phy-mtk-xsphy.c | 81 +++++++++++++++++++++++++++- - 1 file changed, 80 insertions(+), 1 deletion(-) + drivers/phy/mediatek/phy-mtk-xsphy.c | 85 +++++++++++++++++++++++++++- + 1 file changed, 84 insertions(+), 1 deletion(-) --- a/drivers/phy/mediatek/phy-mtk-xsphy.c +++ b/drivers/phy/mediatek/phy-mtk-xsphy.c @@ -75,7 +77,7 @@ Signed-off-by: Daniel Golle + int ret; + + /* type switch function is optional */ -+ if (!of_property_read_bool(dn, "mediatek,syscon-type")) ++ if (!of_property_present(dn, "mediatek,syscon-type")) + return 0; + + ret = of_parse_phandle_with_fixed_args(dn, "mediatek,syscon-type", @@ -154,14 +156,14 @@ Signed-off-by: Daniel Golle return inst->phy; } -@@ -515,6 +594,10 @@ static int mtk_xsphy_probe(struct platfo - retval = PTR_ERR(inst->ref_clk); - goto put_child; +@@ -510,6 +589,10 @@ static int mtk_xsphy_probe(struct platfo + dev_err(dev, "failed to get ref_clk(id-%d)\n", port); + return PTR_ERR(inst->ref_clk); } + + retval = phy_type_syscon_get(inst, child_np); + if (retval) -+ goto put_child; ++ return retval; } provider = devm_of_phy_provider_register(dev, mtk_phy_xlate); diff --git a/target/linux/mediatek/patches-6.12/060-v6.13-mmc-mtk-sd-add-support-for-mt7988.patch b/target/linux/mediatek/patches-6.12/060-v6.13-mmc-mtk-sd-add-support-for-mt7988.patch new file mode 100644 index 00000000000..126ae5f2a34 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/060-v6.13-mmc-mtk-sd-add-support-for-mt7988.patch @@ -0,0 +1,28 @@ +From de6840095f8ed542308279c4f24fa42ba27c2dd3 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Sat, 12 Oct 2024 16:38:23 +0200 +Subject: [PATCH] mmc: mtk-sd: add support for mt7988 + +Add support for mmc on MT7988 SoC. + +We can use mt7986 platform data in driver, but mt7988 needs different +clocks so for binding we need own compatible. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Message-ID: <20241012143826.7690-3-linux@fw-web.de> +Signed-off-by: Ulf Hansson +--- + drivers/mmc/host/mtk-sd.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/mmc/host/mtk-sd.c ++++ b/drivers/mmc/host/mtk-sd.c +@@ -631,6 +631,7 @@ static const struct of_device_id msdc_of + { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, + { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, + { .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat}, ++ { .compatible = "mediatek,mt7988-mmc", .data = &mt7986_compat}, + { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, + { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, + { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, diff --git a/target/linux/mediatek/patches-6.12/117-complete-mt7981b-dtsi.patch b/target/linux/mediatek/patches-6.12/117-complete-mt7981b-dtsi.patch new file mode 100644 index 00000000000..45b9691bc55 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/117-complete-mt7981b-dtsi.patch @@ -0,0 +1,702 @@ +From 3986156b3ba97a9c280f4dfe0efbccf52e1fc488 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Wed, 28 Dec 2022 23:44:42 +0000 +Subject: [PATCH] complete mt7981 dts + +working: + * Ethernet (fully working incl. ppe) + * UART + * SPI-NAND flash + * thermal sensors (SoC and mxl-gpy) + * random number generator via SMC + * USB 1.1, 2.0 and 3.0 + * WiFi with MT7976C 2.4G+5G DBDC incl. WED offloading + * PWM + +--- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +@@ -1,7 +1,14 @@ + // SPDX-License-Identifier: GPL-2.0-only OR MIT + + #include ++#include ++#include + #include ++#include ++#include ++#include ++#include ++#include + #include + + / { +@@ -41,6 +48,57 @@ + method = "smc"; + }; + ++ fan: pwm-fan { ++ compatible = "pwm-fan"; ++ /* cooling level (0, 1, 2, 3) : (0% duty, 50% duty, 75% duty, 100% duty) */ ++ cooling-levels = <0 128 192 255>; ++ #cooling-cells = <2>; ++ status = "disabled"; ++ }; ++ ++ reg_3p3v: regulator-3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-3.3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ /* 64 KiB reserved for ramoops/pstore */ ++ ramoops@42ff0000 { ++ compatible = "ramoops"; ++ reg = <0 0x42ff0000 0 0x10000>; ++ record-size = <0x1000>; ++ }; ++ ++ /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ ++ secmon_reserved: secmon@43000000 { ++ reg = <0 0x43000000 0 0x30000>; ++ no-map; ++ }; ++ ++ wmcpu_emi: wmcpu-reserved@47c80000 { ++ reg = <0 0x47c80000 0 0x100000>; ++ no-map; ++ }; ++ ++ wo_emi0: wo-emi@47d80000 { ++ reg = <0 0x47d80000 0 0x40000>; ++ no-map; ++ }; ++ ++ wo_data: wo-data@47dc0000 { ++ reg = <0 0x47dc0000 0 0x240000>; ++ no-map; ++ }; ++ }; ++ + soc { + compatible = "simple-bus"; + ranges; +@@ -76,13 +134,13 @@ + #reset-cells = <1>; + }; + +- clock-controller@1001e000 { +- compatible = "mediatek,mt7981-apmixedsys"; ++ apmixedsys: clock-controller@1001e000 { ++ compatible = "mediatek,mt7981-apmixedsys", "syscon"; + reg = <0 0x1001e000 0 0x1000>; + #clock-cells = <1>; + }; + +- pwm@10048000 { ++ pwm: pwm@10048000 { + compatible = "mediatek,mt7981-pwm"; + reg = <0 0x10048000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_PWM_STA>, +@@ -94,7 +152,21 @@ + #pwm-cells = <2>; + }; + +- serial@11002000 { ++ crypto: crypto@10320000 { ++ compatible = "inside-secure,safexcel-eip97"; ++ reg = <0 0x10320000 0 0x40000>; ++ interrupts = , ++ , ++ , ++ ; ++ interrupt-names = "ring0", "ring1", "ring2", "ring3"; ++ clocks = <&topckgen CLK_TOP_EIP97B>; ++ clock-names = "top_eip97_ck"; ++ assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>; ++ assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>; ++ }; ++ ++ uart0: serial@11002000 { + compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x100>; + interrupts = ; +@@ -105,7 +177,7 @@ + status = "disabled"; + }; + +- serial@11003000 { ++ uart1: serial@11003000 { + compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x100>; + interrupts = ; +@@ -116,7 +188,7 @@ + status = "disabled"; + }; + +- serial@11004000 { ++ uart2: serial@11004000 { + compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x100>; + interrupts = ; +@@ -127,11 +199,12 @@ + status = "disabled"; + }; + +- i2c@11007000 { ++ i2c0: i2c@11007000 { + compatible = "mediatek,mt7981-i2c"; + reg = <0 0x11007000 0 0x1000>, + <0 0x10217080 0 0x80>; + interrupts = ; ++ clock-div = <1>; + clocks = <&infracfg CLK_INFRA_I2C0_CK>, + <&infracfg CLK_INFRA_AP_DMA_CK>, + <&infracfg CLK_INFRA_I2C_MCK_CK>, +@@ -142,7 +215,32 @@ + status = "disabled"; + }; + +- spi@11009000 { ++ thermal: thermal@1100c800 { ++ #thermal-sensor-cells = <1>; ++ compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal"; ++ reg = <0 0x1100c800 0 0x800>; ++ interrupts = ; ++ clocks = <&infracfg CLK_INFRA_THERM_CK>, ++ <&infracfg CLK_INFRA_ADC_26M_CK>; ++ clock-names = "therm", "auxadc"; ++ mediatek,auxadc = <&auxadc>; ++ mediatek,apmixedsys = <&apmixedsys>; ++ nvmem-cells = <&thermal_calibration>; ++ nvmem-cell-names = "calibration-data"; ++ }; ++ ++ auxadc: adc@1100d000 { ++ compatible = "mediatek,mt7981-auxadc", ++ "mediatek,mt7986-auxadc", ++ "mediatek,mt7622-auxadc"; ++ reg = <0 0x1100d000 0 0x1000>; ++ clocks = <&infracfg CLK_INFRA_ADC_26M_CK>, ++ <&infracfg CLK_INFRA_ADC_FRC_CK>; ++ clock-names = "main", "32k"; ++ #io-channel-cells = <1>; ++ }; ++ ++ spi2: spi@11009000 { + compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm"; + reg = <0 0x11009000 0 0x1000>; + interrupts = ; +@@ -156,7 +254,7 @@ + status = "disabled"; + }; + +- spi@1100a000 { ++ spi0: spi@1100a000 { + compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm"; + reg = <0 0x1100a000 0 0x1000>; + interrupts = ; +@@ -170,7 +268,7 @@ + status = "disabled"; + }; + +- spi@1100b000 { ++ spi1: spi@1100b000 { + compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm"; + reg = <0 0x1100b000 0 0x1000>; + interrupts = ; +@@ -184,6 +282,41 @@ + status = "disabled"; + }; + ++ pcie: pcie@11280000 { ++ compatible = "mediatek,mt7981-pcie", ++ "mediatek,mt8192-pcie"; ++ device_type = "pci"; ++ reg = <0 0x11280000 0 0x4000>; ++ reg-names = "pcie-mac"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ interrupts = ; ++ bus-range = <0x00 0xff>; ++ ranges = <0x82000000 0 0x20000000 ++ 0x0 0x20000000 0 0x10000000>; ++ status = "disabled"; ++ ++ clocks = <&infracfg CLK_INFRA_IPCIE_CK>, ++ <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, ++ <&infracfg CLK_INFRA_IPCIER_CK>, ++ <&infracfg CLK_INFRA_IPCIEB_CK>; ++ ++ phys = <&u3port0 PHY_TYPE_PCIE>; ++ phy-names = "pcie-phy"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie_intc 0>, ++ <0 0 0 2 &pcie_intc 1>, ++ <0 0 0 3 &pcie_intc 2>, ++ <0 0 0 4 &pcie_intc 3>; ++ pcie_intc: interrupt-controller { ++ interrupt-controller; ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ + pio: pinctrl@11d00000 { + compatible = "mediatek,mt7981-pinctrl"; + reg = <0 0x11d00000 0 0x1000>, +@@ -204,6 +337,49 @@ + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; ++ ++ mdio_pins: mdc-mdio-pins { ++ mux { ++ function = "eth"; ++ groups = "smi_mdc_mdio"; ++ }; ++ }; ++ ++ uart0_pins: uart0-pins { ++ mux { ++ function = "uart"; ++ groups = "uart0"; ++ }; ++ }; ++ ++ wifi_dbdc_pins: wifi-dbdc-pins { ++ mux { ++ function = "eth"; ++ groups = "wf0_mode1"; ++ }; ++ conf { ++ pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4", ++ "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6", ++ "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10", ++ "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ", ++ "WF_CBA_RESETB", "WF_DIG_RESETB"; ++ drive-strength = <4>; ++ }; ++ }; ++ ++ gbe_led0_pins: gbe-led0-pins { ++ mux { ++ function = "led"; ++ groups = "gbe_led0"; ++ }; ++ }; ++ ++ gbe_led1_pins: gbe-led1-pins { ++ mux { ++ function = "led"; ++ groups = "gbe_led1"; ++ }; ++ }; + }; + + efuse@11f20000 { +@@ -211,17 +387,316 @@ + reg = <0 0x11f20000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; ++ ++ thermal_calibration: thermal-calib@274 { ++ reg = <0x274 0xc>; ++ }; ++ ++ phy_calibration: phy-calib@8dc { ++ reg = <0x8dc 0x10>; ++ }; ++ ++ comb_rx_imp_p0: usb3-rx-imp@8c8 { ++ reg = <0x8c8 1>; ++ bits = <0 5>; ++ }; ++ ++ comb_tx_imp_p0: usb3-tx-imp@8c8 { ++ reg = <0x8c8 2>; ++ bits = <5 5>; ++ }; ++ ++ comb_intr_p0: usb3-intr@8c9 { ++ reg = <0x8c9 1>; ++ bits = <2 6>; ++ }; + }; + +- clock-controller@15000000 { ++ ethsys: clock-controller@15000000 { + compatible = "mediatek,mt7981-ethsys", "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + +- wifi@18000000 { ++ wed: wed@15010000 { ++ compatible = "mediatek,mt7981-wed", ++ "mediatek,mt7986-wed", ++ "syscon"; ++ reg = <0 0x15010000 0 0x1000>; ++ interrupt-parent = <&gic>; ++ interrupts = ; ++ memory-region = <&wo_emi0>, <&wo_data>; ++ memory-region-names = "wo-emi", "wo-data"; ++ mediatek,wo-ccif = <&wo_ccif0>; ++ mediatek,wo-ilm = <&wo_ilm0>; ++ mediatek,wo-dlm = <&wo_dlm0>; ++ mediatek,wo-cpuboot = <&wo_cpuboot>; ++ }; ++ ++ eth: ethernet@15100000 { ++ compatible = "mediatek,mt7981-eth"; ++ reg = <0 0x15100000 0 0x80000>; ++ interrupts = , ++ , ++ , ++ ; ++ clocks = <ðsys CLK_ETH_FE_EN>, ++ <ðsys CLK_ETH_GP2_EN>, ++ <ðsys CLK_ETH_GP1_EN>, ++ <ðsys CLK_ETH_WOCPU0_EN>, ++ <&sgmiisys0 CLK_SGM0_TX_EN>, ++ <&sgmiisys0 CLK_SGM0_RX_EN>, ++ <&sgmiisys0 CLK_SGM0_CK0_EN>, ++ <&sgmiisys0 CLK_SGM0_CDR_CK0_EN>, ++ <&sgmiisys1 CLK_SGM1_TX_EN>, ++ <&sgmiisys1 CLK_SGM1_RX_EN>, ++ <&sgmiisys1 CLK_SGM1_CK1_EN>, ++ <&sgmiisys1 CLK_SGM1_CDR_CK1_EN>, ++ <&topckgen CLK_TOP_SGM_REG>, ++ <&topckgen CLK_TOP_NETSYS_SEL>, ++ <&topckgen CLK_TOP_NETSYS_500M_SEL>; ++ clock-names = "fe", "gp2", "gp1", "wocpu0", ++ "sgmii_tx250m", "sgmii_rx250m", ++ "sgmii_cdr_ref", "sgmii_cdr_fb", ++ "sgmii2_tx250m", "sgmii2_rx250m", ++ "sgmii2_cdr_ref", "sgmii2_cdr_fb", ++ "sgmii_ck", "netsys0", "netsys1"; ++ assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, ++ <&topckgen CLK_TOP_SGM_325M_SEL>; ++ assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>, ++ <&topckgen CLK_TOP_CB_SGM_325M>; ++ mediatek,ethsys = <ðsys>; ++ mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; ++ mediatek,infracfg = <&topmisc>; ++ mediatek,wed = <&wed>; ++ status = "disabled"; ++ ++ mdio_bus: mdio-bus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ int_gbe_phy: ethernet-phy@0 { ++ reg = <0>; ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ phy-mode = "gmii"; ++ phy-is-integrated; ++ nvmem-cells = <&phy_calibration>; ++ nvmem-cell-names = "phy-cal-data"; ++ ++ leds { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ int_gbe_phy_led0: int-gbe-phy-led0@0 { ++ reg = <0>; ++ function = LED_FUNCTION_LAN; ++ pinctrl-0 = <&gbe_led0_pins>; ++ pinctrl-names = "default"; ++ status = "disabled"; ++ }; ++ ++ int_gbe_phy_led1: int-gbe-phy-led1@1 { ++ reg = <1>; ++ function = LED_FUNCTION_LAN; ++ pinctrl-0 = <&gbe_led1_pins>; ++ pinctrl-names = "default"; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ }; ++ }; ++ ++ wdma: wdma@15104800 { ++ compatible = "mediatek,wed-wdma"; ++ reg = <0 0x15104800 0 0x400>, ++ <0 0x15104c00 0 0x400>; ++ }; ++ ++ ap2woccif: ap2woccif@151a5000 { ++ compatible = "mediatek,ap2woccif"; ++ reg = <0 0x151a5000 0 0x1000>, ++ <0 0x151ad000 0 0x1000>; ++ interrupt-parent = <&gic>; ++ interrupts = , ++ ; ++ }; ++ ++ wo_dlm0: syscon@151e8000 { ++ compatible = "mediatek,mt7986-wo-dlm", "syscon"; ++ reg = <0 0x151e8000 0 0x2000>; ++ }; ++ ++ wo_ilm0: syscon@151e0000 { ++ compatible = "mediatek,mt7986-wo-ilm", "syscon"; ++ reg = <0 0x151e0000 0 0x8000>; ++ }; ++ ++ wo_cpuboot: syscon@15194000 { ++ compatible = "mediatek,mt7986-wo-cpuboot", "syscon"; ++ reg = <0 0x15194000 0 0x1000>; ++ }; ++ ++ wo_ccif0: syscon@151a5000 { ++ compatible = "mediatek,mt7986-wo-ccif", "syscon"; ++ reg = <0 0x151a5000 0 0x1000>; ++ interrupt-parent = <&gic>; ++ interrupts = ; ++ }; ++ ++ sgmiisys0: syscon@10060000 { ++ compatible = "mediatek,mt7981-sgmiisys_0", "mediatek,mt7986-sgmiisys_0", "syscon"; ++ reg = <0 0x10060000 0 0x1000>; ++ mediatek,pnswap; ++ #clock-cells = <1>; ++ }; ++ ++ sgmiisys1: syscon@10070000 { ++ compatible = "mediatek,mt7981-sgmiisys_1", "mediatek,mt7986-sgmiisys_1", "syscon"; ++ reg = <0 0x10070000 0 0x1000>; ++ #clock-cells = <1>; ++ }; ++ ++ topmisc: topmisc@11d10000 { ++ compatible = "mediatek,mt7981-topmisc", "syscon"; ++ reg = <0 0x11d10000 0 0x10000>; ++ #clock-cells = <1>; ++ }; ++ ++ snand: snfi@11005000 { ++ compatible = "mediatek,mt7986-snand"; ++ reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>; ++ reg-names = "nfi", "ecc"; ++ interrupts = ; ++ clocks = <&infracfg CLK_INFRA_SPINFI1_CK>, ++ <&infracfg CLK_INFRA_NFI1_CK>, ++ <&infracfg CLK_INFRA_NFI_HCK_CK>; ++ clock-names = "pad_clk", "nfi_clk", "nfi_hclk"; ++ assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>, ++ <&topckgen CLK_TOP_NFI1X_SEL>; ++ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>, ++ <&topckgen CLK_TOP_CB_M_D8>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ mmc0: mmc@11230000 { ++ compatible = "mediatek,mt7986-mmc", ++ "mediatek,mt7981-mmc"; ++ reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>; ++ interrupts = ; ++ clocks = <&infracfg CLK_INFRA_MSDC_CK>, ++ <&infracfg CLK_INFRA_MSDC_HCK_CK>, ++ <&infracfg CLK_INFRA_MSDC_66M_CK>, ++ <&infracfg CLK_INFRA_MSDC_133M_CK>; ++ assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>, ++ <&topckgen CLK_TOP_EMMC_400M_SEL>; ++ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>, ++ <&topckgen CLK_TOP_CB_NET2_D2>; ++ clock-names = "source", "hclk", "axi_cg", "ahb_cg"; ++ status = "disabled"; ++ }; ++ ++ wed_pcie: wed_pcie@10003000 { ++ compatible = "mediatek,wed_pcie"; ++ reg = <0 0x10003000 0 0x10>; ++ }; ++ ++ consys: consys@10000000 { ++ compatible = "mediatek,mt7981-consys"; ++ reg = <0 0x10000000 0 0x8600000>; ++ memory-region = <&wmcpu_emi>; ++ }; ++ ++ xhci: usb@11200000 { ++ compatible = "mediatek,mt7986-xhci", ++ "mediatek,mtk-xhci"; ++ reg = <0 0x11200000 0 0x2e00>, ++ <0 0x11203e00 0 0x0100>; ++ reg-names = "mac", "ippc"; ++ interrupts = ; ++ clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>, ++ <&infracfg CLK_INFRA_IUSB_CK>, ++ <&infracfg CLK_INFRA_IUSB_133_CK>, ++ <&infracfg CLK_INFRA_IUSB_66M_CK>, ++ <&topckgen CLK_TOP_U2U3_XHCI_SEL>; ++ clock-names = "sys_ck", ++ "ref_ck", ++ "mcu_ck", ++ "dma_ck", ++ "xhci_ck"; ++ phys = <&u2port0 PHY_TYPE_USB2>, ++ <&u3port0 PHY_TYPE_USB3>; ++ vusb33-supply = <®_3p3v>; ++ status = "disabled"; ++ }; ++ ++ usb_phy: usb-phy@11e10000 { ++ compatible = "mediatek,mt7981", ++ "mediatek,generic-tphy-v2"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0 0x11e10000 0x1700>; ++ status = "disabled"; ++ ++ u2port0: usb-phy@0 { ++ reg = <0x0 0x700>; ++ clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>; ++ clock-names = "ref"; ++ #phy-cells = <1>; ++ }; ++ ++ u3port0: usb-phy@700 { ++ reg = <0x700 0x900>; ++ clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>; ++ clock-names = "ref"; ++ #phy-cells = <1>; ++ mediatek,syscon-type = <&topmisc 0x218 0>; ++ status = "okay"; ++ }; ++ }; ++ ++ ++ afe: audio-controller@11210000 { ++ compatible = "mediatek,mt79xx-audio"; ++ reg = <0 0x11210000 0 0x9000>; ++ interrupts = ; ++ clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>, ++ <&infracfg CLK_INFRA_AUD_26M_CK>, ++ <&infracfg CLK_INFRA_AUD_L_CK>, ++ <&infracfg CLK_INFRA_AUD_AUD_CK>, ++ <&infracfg CLK_INFRA_AUD_EG2_CK>, ++ <&topckgen CLK_TOP_AUD_SEL>; ++ clock-names = "aud_bus_ck", ++ "aud_26m_ck", ++ "aud_l_ck", ++ "aud_aud_ck", ++ "aud_eg2_ck", ++ "aud_sel"; ++ assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>, ++ <&topckgen CLK_TOP_A1SYS_SEL>, ++ <&topckgen CLK_TOP_AUD_L_SEL>, ++ <&topckgen CLK_TOP_A_TUNER_SEL>; ++ assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>, ++ <&topckgen CLK_TOP_APLL2_D4>, ++ <&topckgen CLK_TOP_CB_APLL2_196M>, ++ <&topckgen CLK_TOP_APLL2_D4>; ++ status = "disabled"; ++ }; ++ ++ ice: ice_debug { ++ compatible = "mediatek,mt7981-ice_debug", ++ "mediatek,mt2701-ice_debug"; ++ clocks = <&infracfg CLK_INFRA_DBG_CK>; ++ clock-names = "ice_dbg"; ++ }; ++ ++ wifi: wifi@18000000 { + compatible = "mediatek,mt7981-wmac"; ++ pinctrl-0 = <&wifi_dbdc_pins>; ++ pinctrl-names = "dbdc"; + reg = <0 0x18000000 0 0x1000000>, + <0 0x10003000 0 0x1000>, + <0 0x11d10000 0 0x1000>; +@@ -234,6 +709,67 @@ + clock-names = "mcu", "ap2conn"; + resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; + reset-names = "consys"; ++ memory-region = <&wmcpu_emi>; ++ status = "disabled"; ++ }; ++ }; ++ ++ thermal-zones { ++ cpu_thermal: cpu-thermal { ++ polling-delay-passive = <1000>; ++ polling-delay = <1000>; ++ thermal-sensors = <&thermal 0>; ++ trips { ++ cpu_trip_crit: crit { ++ temperature = <125000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ ++ cpu_trip_hot: hot { ++ temperature = <120000>; ++ hysteresis = <2000>; ++ type = "hot"; ++ }; ++ ++ cpu_trip_active_high: active-high { ++ temperature = <115000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ ++ cpu_trip_active_med: active-med { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ ++ cpu_trip_active_low: active-low { ++ temperature = <60000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ }; ++ ++ cooling-maps { ++ cpu-active-high { ++ /* active: set fan to cooling level 3 */ ++ cooling-device = <&fan 3 3>; ++ trip = <&cpu_trip_active_high>; ++ }; ++ ++ cpu-active-med { ++ /* active: set fan to cooling level 2 */ ++ cooling-device = <&fan 2 2>; ++ trip = <&cpu_trip_active_med>; ++ }; ++ ++ cpu-active-low { ++ /* passive: set fan to cooling level 1 */ ++ cooling-device = <&fan 1 1>; ++ trip = <&cpu_trip_active_low>; ++ }; ++ }; + }; + }; + +@@ -245,4 +781,8 @@ + , + ; + }; ++ ++ trng { ++ compatible = "mediatek,mt7981-rng"; ++ }; + }; diff --git a/target/linux/mediatek/patches-6.12/170-arm64-dts-mediatek-mt7988a-bpi-r4-allow-hw-variants-.patch b/target/linux/mediatek/patches-6.12/170-arm64-dts-mediatek-mt7988a-bpi-r4-allow-hw-variants-.patch new file mode 100644 index 00000000000..6216f59cfd3 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/170-arm64-dts-mediatek-mt7988a-bpi-r4-allow-hw-variants-.patch @@ -0,0 +1,876 @@ +From df3c7a5128f88e658bd4519154d5e896519e740a Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 22 Apr 2025 15:24:25 +0200 +Subject: [PATCH 27/32] arm64: dts: mediatek: mt7988a-bpi-r4: allow hw variants + of bpi-r4 + +Sinovoip has released other variants of Bananapi-R4 board. +The known changes affecting only the LAN SFP+ slot which is replaced +by a 2.5G phy with optional PoE. + +Just move the common parts to a new dtsi and keep differences (only +i2c for lan-sfp) in dts. + +Signed-off-by: Frank Wunderlich +Acked-by: Krzysztof Kozlowski +Reviewed-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/Makefile | 6 + + .../mediatek/mt7988a-bananapi-bpi-r4-2g5.dts | 11 + + .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 400 +----------------- + .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 399 +++++++++++++++++ + 4 files changed, 421 insertions(+), 395 deletions(-) + create mode 100644 arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts + create mode 100644 arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi + +--- a/arch/arm64/boot/dts/mediatek/Makefile ++++ b/arch/arm64/boot/dts/mediatek/Makefile +@@ -21,6 +21,9 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-b + dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb + dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb + dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4.dtb ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-2g5.dtb ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-emmc.dtbo ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-sd.dtbo + dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb + dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb + dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb +@@ -90,3 +93,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pu + # Device tree overlays support + DTC_FLAGS_mt7986a-bananapi-bpi-r3 := -@ + DTC_FLAGS_mt7986a-bananapi-bpi-r3-mini := -@ ++DTC_FLAGS_mt7988a-bananapi-bpi-r4 := -@ ++DTC_FLAGS_mt7988a-bananapi-bpi-r4-2g5 := -@ ++DTC_FLAGS_mt8395-radxa-nio-12l := -@ +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts +@@ -0,0 +1,11 @@ ++// SPDX-License-Identifier: GPL-2.0-only OR MIT ++ ++/dts-v1/; ++ ++#include "mt7988a-bananapi-bpi-r4.dtsi" ++ ++/ { ++ compatible = "bananapi,bpi-r4-2g5", "bananapi,bpi-r4", "mediatek,mt7988a"; ++ model = "Banana Pi BPI-R4 (1x SFP+, 1x 2.5GbE)"; ++ chassis-type = "embedded"; ++}; +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +@@ -2,408 +2,18 @@ + + /dts-v1/; + +-#include +-#include +- +-#include "mt7988a.dtsi" ++#include "mt7988a-bananapi-bpi-r4.dtsi" + + / { + compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; +- model = "Banana Pi BPI-R4"; ++ model = "Banana Pi BPI-R4 (2x SFP+)"; + chassis-type = "embedded"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- reg_1p8v: regulator-1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; + }; + +-&cpu0 { +- proc-supply = <&rt5190_buck3>; +-}; +- +-&cpu1 { +- proc-supply = <&rt5190_buck3>; +-}; +- +-&cpu2 { +- proc-supply = <&rt5190_buck3>; +-}; +- +-&cpu3 { +- proc-supply = <&rt5190_buck3>; +-}; +- +-&cpu_thermal { +- trips { +- cpu_trip_hot: hot { +- temperature = <120000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- cpu_trip_active_high: active-high { +- temperature = <115000>; +- hysteresis = <2000>; +- type = "active"; +- }; +- +- cpu_trip_active_med: active-med { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "active"; +- }; +- +- cpu_trip_active_low: active-low { +- temperature = <40000>; +- hysteresis = <2000>; +- type = "active"; +- }; +- }; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- status = "okay"; +- +- rt5190a_64: rt5190a@64 { +- compatible = "richtek,rt5190a"; +- reg = <0x64>; +- vin2-supply = <&rt5190_buck1>; +- vin3-supply = <&rt5190_buck1>; +- vin4-supply = <&rt5190_buck1>; +- +- regulators { +- rt5190_buck1: buck1 { +- regulator-name = "rt5190a-buck1"; +- regulator-min-microvolt = <5090000>; +- regulator-max-microvolt = <5090000>; +- regulator-allowed-modes = +- , ; +- regulator-boot-on; +- regulator-always-on; +- }; +- buck2 { +- regulator-name = "vcore"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1400000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- rt5190_buck3: buck3 { +- regulator-name = "vproc"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1400000>; +- regulator-boot-on; +- }; +- buck4 { +- regulator-name = "rt5190a-buck4"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-allowed-modes = +- , ; +- regulator-boot-on; +- regulator-always-on; +- }; +- ldo { +- regulator-name = "rt5190a-ldo"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_1_pins>; +- status = "okay"; +- +- pca9545: i2c-mux@70 { +- compatible = "nxp,pca9545"; +- reg = <0x70>; +- reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>; ++&pca9545 { ++ i2c_sfp2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; +- +- i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- pcf8563: rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- #clock-cells = <0>; +- }; +- +- eeprom@57 { +- compatible = "atmel,24c02"; +- reg = <0x57>; +- size = <256>; +- }; +- +- }; +- +- i2c_sfp1: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- i2c_sfp2: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- }; +-}; +- +-/* mPCIe SIM2 */ +-&pcie0 { +- status = "okay"; +-}; +- +-/* mPCIe SIM3 */ +-&pcie1 { +- status = "okay"; +-}; +- +-/* M.2 key-B SIM1 */ +-&pcie2 { +- status = "okay"; +-}; +- +-/* M.2 key-M SSD */ +-&pcie3 { +- status = "okay"; +-}; +- +-&pio { +- mdio0_pins: mdio0-pins { +- mux { +- function = "eth"; +- groups = "mdc_mdio0"; +- }; +- +- conf { +- pins = "SMI_0_MDC", "SMI_0_MDIO"; +- drive-strength = <8>; +- }; +- }; +- +- i2c0_pins: i2c0-g0-pins { +- mux { +- function = "i2c"; +- groups = "i2c0_1"; +- }; +- }; +- +- i2c1_pins: i2c1-g0-pins { +- mux { +- function = "i2c"; +- groups = "i2c1_0"; +- }; +- }; +- +- i2c1_sfp_pins: i2c1-sfp-g0-pins { +- mux { +- function = "i2c"; +- groups = "i2c1_sfp"; +- }; +- }; +- +- i2c2_0_pins: i2c2-g0-pins { +- mux { +- function = "i2c"; +- groups = "i2c2_0"; +- }; ++ reg = <2>; + }; +- +- i2c2_1_pins: i2c2-g1-pins { +- mux { +- function = "i2c"; +- groups = "i2c2_1"; +- }; +- }; +- +- gbe0_led0_pins: gbe0-led0-pins { +- mux { +- function = "led"; +- groups = "gbe0_led0"; +- }; +- }; +- +- gbe1_led0_pins: gbe1-led0-pins { +- mux { +- function = "led"; +- groups = "gbe1_led0"; +- }; +- }; +- +- gbe2_led0_pins: gbe2-led0-pins { +- mux { +- function = "led"; +- groups = "gbe2_led0"; +- }; +- }; +- +- gbe3_led0_pins: gbe3-led0-pins { +- mux { +- function = "led"; +- groups = "gbe3_led0"; +- }; +- }; +- +- gbe0_led1_pins: gbe0-led1-pins { +- mux { +- function = "led"; +- groups = "gbe0_led1"; +- }; +- }; +- +- gbe1_led1_pins: gbe1-led1-pins { +- mux { +- function = "led"; +- groups = "gbe1_led1"; +- }; +- }; +- +- gbe2_led1_pins: gbe2-led1-pins { +- mux { +- function = "led"; +- groups = "gbe2_led1"; +- }; +- }; +- +- gbe3_led1_pins: gbe3-led1-pins { +- mux { +- function = "led"; +- groups = "gbe3_led1"; +- }; +- }; +- +- i2p5gbe_led0_pins: 2p5gbe-led0-pins { +- mux { +- function = "led"; +- groups = "2p5gbe_led0"; +- }; +- }; +- +- i2p5gbe_led1_pins: 2p5gbe-led1-pins { +- mux { +- function = "led"; +- groups = "2p5gbe_led1"; +- }; +- }; +- +- mmc0_pins_emmc_45: mmc0-emmc-45-pins { +- mux { +- function = "flash"; +- groups = "emmc_45"; +- }; +- }; +- +- mmc0_pins_emmc_51: mmc0-emmc-51-pins { +- mux { +- function = "flash"; +- groups = "emmc_51"; +- }; +- }; +- +- mmc0_pins_sdcard: mmc0-sdcard-pins { +- mux { +- function = "flash"; +- groups = "sdcard"; +- }; +- }; +- +- uart0_pins: uart0-pins { +- mux { +- function = "uart"; +- groups = "uart0"; +- }; +- }; +- +- snfi_pins: snfi-pins { +- mux { +- function = "flash"; +- groups = "snfi"; +- }; +- }; +- +- spi0_pins: spi0-pins { +- mux { +- function = "spi"; +- groups = "spi0"; +- }; +- }; +- +- spi0_flash_pins: spi0-flash-pins { +- mux { +- function = "spi"; +- groups = "spi0", "spi0_wp_hold"; +- }; +- }; +- +- spi1_pins: spi1-pins { +- mux { +- function = "spi"; +- groups = "spi1"; +- }; +- }; +- +- spi2_pins: spi2-pins { +- mux { +- function = "spi"; +- groups = "spi2"; +- }; +- }; +- +- spi2_flash_pins: spi2-flash-pins { +- mux { +- function = "spi"; +- groups = "spi2", "spi2_wp_hold"; +- }; +- }; +-}; +- +-&pwm { +- status = "okay"; +-}; +- +-&serial0 { +- status = "okay"; +-}; +- +-&ssusb1 { +- status = "okay"; +-}; +- +-&tphy { +- status = "okay"; +-}; +- +-&watchdog { +- status = "okay"; + }; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi +@@ -0,0 +1,399 @@ ++// SPDX-License-Identifier: GPL-2.0-only OR MIT ++ ++/dts-v1/; ++ ++#include ++#include ++ ++#include "mt7988a.dtsi" ++ ++/ { ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ reg_1p8v: regulator-1p8v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-1.8V"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ reg_3p3v: regulator-3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-3.3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++}; ++ ++&cpu0 { ++ proc-supply = <&rt5190_buck3>; ++}; ++ ++&cpu1 { ++ proc-supply = <&rt5190_buck3>; ++}; ++ ++&cpu2 { ++ proc-supply = <&rt5190_buck3>; ++}; ++ ++&cpu3 { ++ proc-supply = <&rt5190_buck3>; ++}; ++ ++&cpu_thermal { ++ trips { ++ cpu_trip_hot: hot { ++ temperature = <120000>; ++ hysteresis = <2000>; ++ type = "hot"; ++ }; ++ ++ cpu_trip_active_high: active-high { ++ temperature = <115000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ ++ cpu_trip_active_med: active-med { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ ++ cpu_trip_active_low: active-low { ++ temperature = <40000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ }; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++ status = "okay"; ++ ++ rt5190a_64: rt5190a@64 { ++ compatible = "richtek,rt5190a"; ++ reg = <0x64>; ++ vin2-supply = <&rt5190_buck1>; ++ vin3-supply = <&rt5190_buck1>; ++ vin4-supply = <&rt5190_buck1>; ++ ++ regulators { ++ rt5190_buck1: buck1 { ++ regulator-name = "rt5190a-buck1"; ++ regulator-min-microvolt = <5090000>; ++ regulator-max-microvolt = <5090000>; ++ regulator-allowed-modes = ++ , ; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ buck2 { ++ regulator-name = "vcore"; ++ regulator-min-microvolt = <600000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ rt5190_buck3: buck3 { ++ regulator-name = "vproc"; ++ regulator-min-microvolt = <600000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-boot-on; ++ }; ++ buck4 { ++ regulator-name = "rt5190a-buck4"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-allowed-modes = ++ , ; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ldo { ++ regulator-name = "rt5190a-ldo"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ }; ++ }; ++}; ++ ++&i2c2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_1_pins>; ++ status = "okay"; ++ ++ pca9545: i2c-mux@70 { ++ compatible = "nxp,pca9545"; ++ reg = <0x70>; ++ reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ ++ pcf8563: rtc@51 { ++ compatible = "nxp,pcf8563"; ++ reg = <0x51>; ++ #clock-cells = <0>; ++ }; ++ ++ eeprom@57 { ++ compatible = "atmel,24c02"; ++ reg = <0x57>; ++ size = <256>; ++ }; ++ ++ }; ++ ++ i2c_sfp1: i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ }; ++ }; ++}; ++ ++/* mPCIe SIM2 */ ++&pcie0 { ++ status = "okay"; ++}; ++ ++/* mPCIe SIM3 */ ++&pcie1 { ++ status = "okay"; ++}; ++ ++/* M.2 key-B SIM1 */ ++&pcie2 { ++ status = "okay"; ++}; ++ ++/* M.2 key-M SSD */ ++&pcie3 { ++ status = "okay"; ++}; ++ ++&pio { ++ mdio0_pins: mdio0-pins { ++ mux { ++ function = "eth"; ++ groups = "mdc_mdio0"; ++ }; ++ ++ conf { ++ pins = "SMI_0_MDC", "SMI_0_MDIO"; ++ drive-strength = <8>; ++ }; ++ }; ++ ++ i2c0_pins: i2c0-g0-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c0_1"; ++ }; ++ }; ++ ++ i2c1_pins: i2c1-g0-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c1_0"; ++ }; ++ }; ++ ++ i2c1_sfp_pins: i2c1-sfp-g0-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c1_sfp"; ++ }; ++ }; ++ ++ i2c2_0_pins: i2c2-g0-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c2_0"; ++ }; ++ }; ++ ++ i2c2_1_pins: i2c2-g1-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c2_1"; ++ }; ++ }; ++ ++ gbe0_led0_pins: gbe0-led0-pins { ++ mux { ++ function = "led"; ++ groups = "gbe0_led0"; ++ }; ++ }; ++ ++ gbe1_led0_pins: gbe1-led0-pins { ++ mux { ++ function = "led"; ++ groups = "gbe1_led0"; ++ }; ++ }; ++ ++ gbe2_led0_pins: gbe2-led0-pins { ++ mux { ++ function = "led"; ++ groups = "gbe2_led0"; ++ }; ++ }; ++ ++ gbe3_led0_pins: gbe3-led0-pins { ++ mux { ++ function = "led"; ++ groups = "gbe3_led0"; ++ }; ++ }; ++ ++ gbe0_led1_pins: gbe0-led1-pins { ++ mux { ++ function = "led"; ++ groups = "gbe0_led1"; ++ }; ++ }; ++ ++ gbe1_led1_pins: gbe1-led1-pins { ++ mux { ++ function = "led"; ++ groups = "gbe1_led1"; ++ }; ++ }; ++ ++ gbe2_led1_pins: gbe2-led1-pins { ++ mux { ++ function = "led"; ++ groups = "gbe2_led1"; ++ }; ++ }; ++ ++ gbe3_led1_pins: gbe3-led1-pins { ++ mux { ++ function = "led"; ++ groups = "gbe3_led1"; ++ }; ++ }; ++ ++ i2p5gbe_led0_pins: 2p5gbe-led0-pins { ++ mux { ++ function = "led"; ++ groups = "2p5gbe_led0"; ++ }; ++ }; ++ ++ i2p5gbe_led1_pins: 2p5gbe-led1-pins { ++ mux { ++ function = "led"; ++ groups = "2p5gbe_led1"; ++ }; ++ }; ++ ++ mmc0_pins_emmc_45: mmc0-emmc-45-pins { ++ mux { ++ function = "flash"; ++ groups = "emmc_45"; ++ }; ++ }; ++ ++ mmc0_pins_emmc_51: mmc0-emmc-51-pins { ++ mux { ++ function = "flash"; ++ groups = "emmc_51"; ++ }; ++ }; ++ ++ mmc0_pins_sdcard: mmc0-sdcard-pins { ++ mux { ++ function = "flash"; ++ groups = "sdcard"; ++ }; ++ }; ++ ++ uart0_pins: uart0-pins { ++ mux { ++ function = "uart"; ++ groups = "uart0"; ++ }; ++ }; ++ ++ snfi_pins: snfi-pins { ++ mux { ++ function = "flash"; ++ groups = "snfi"; ++ }; ++ }; ++ ++ spi0_pins: spi0-pins { ++ mux { ++ function = "spi"; ++ groups = "spi0"; ++ }; ++ }; ++ ++ spi0_flash_pins: spi0-flash-pins { ++ mux { ++ function = "spi"; ++ groups = "spi0", "spi0_wp_hold"; ++ }; ++ }; ++ ++ spi1_pins: spi1-pins { ++ mux { ++ function = "spi"; ++ groups = "spi1"; ++ }; ++ }; ++ ++ spi2_pins: spi2-pins { ++ mux { ++ function = "spi"; ++ groups = "spi2"; ++ }; ++ }; ++ ++ spi2_flash_pins: spi2-flash-pins { ++ mux { ++ function = "spi"; ++ groups = "spi2", "spi2_wp_hold"; ++ }; ++ }; ++}; ++ ++&pwm { ++ status = "okay"; ++}; ++ ++&serial0 { ++ status = "okay"; ++}; ++ ++&ssusb1 { ++ status = "okay"; ++}; ++ ++&tphy { ++ status = "okay"; ++}; ++ ++&watchdog { ++ status = "okay"; ++}; diff --git a/target/linux/mediatek/patches-6.12/171-arm64-dts-mediatek-mt7988a-Add-xsphy-for-ssusb0-pcie2.patch b/target/linux/mediatek/patches-6.12/171-arm64-dts-mediatek-mt7988a-Add-xsphy-for-ssusb0-pcie2.patch new file mode 100644 index 00000000000..fac060ef16c --- /dev/null +++ b/target/linux/mediatek/patches-6.12/171-arm64-dts-mediatek-mt7988a-Add-xsphy-for-ssusb0-pcie2.patch @@ -0,0 +1,74 @@ +From 1861c63ba7bb7f8a5145d4ceabcf346f274da61f Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 22 Apr 2025 15:24:30 +0200 +Subject: [PATCH 28/32] arm64: dts: mediatek: mt7988: Add xsphy for + ssusb0/pcie2 + +First usb and third pcie controller on mt7988 need a xs-phy to work +properly. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 36 +++++++++++++++++++++++ + 1 file changed, 36 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -334,6 +334,8 @@ + <&infracfg CLK_INFRA_133M_USB_HCK>, + <&infracfg CLK_INFRA_USB_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; ++ phys = <&xphyu2port0 PHY_TYPE_USB2>, ++ <&xphyu3port0 PHY_TYPE_USB3>; + status = "disabled"; + }; + +@@ -398,6 +400,9 @@ + pinctrl-0 = <&pcie2_pins>; + status = "disabled"; + ++ phys = <&xphyu3port0 PHY_TYPE_PCIE>; ++ phy-names = "pcie-phy"; ++ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc2 0>, +@@ -548,6 +553,37 @@ + }; + }; + ++ ++ topmisc: system-controller@11d10084 { ++ compatible = "mediatek,mt7988-topmisc", ++ "syscon"; ++ reg = <0 0x11d10084 0 0xff80>; ++ }; ++ ++ xs-phy@11e10000 { ++ compatible = "mediatek,mt7988-xsphy", ++ "mediatek,xsphy"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ status = "disabled"; ++ ++ xphyu2port0: usb-phy@11e10000 { ++ reg = <0 0x11e10000 0 0x400>; ++ clocks = <&infracfg CLK_INFRA_USB_UTMI>; ++ clock-names = "ref"; ++ #phy-cells = <1>; ++ }; ++ ++ xphyu3port0: usb-phy@11e13000 { ++ reg = <0 0x11e13400 0 0x500>; ++ clocks = <&infracfg CLK_INFRA_USB_PIPE>; ++ clock-names = "ref"; ++ #phy-cells = <1>; ++ mediatek,syscon-type = <&topmisc 0x194 0>; ++ }; ++ }; ++ + clock-controller@11f40000 { + compatible = "mediatek,mt7988-xfi-pll"; + reg = <0 0x11f40000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.12/172-arm64-dts-mediatek-mt7988a-bpi-r4-enable-xsphy.patch b/target/linux/mediatek/patches-6.12/172-arm64-dts-mediatek-mt7988a-bpi-r4-enable-xsphy.patch new file mode 100644 index 00000000000..da26a93eb70 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/172-arm64-dts-mediatek-mt7988a-bpi-r4-enable-xsphy.patch @@ -0,0 +1,35 @@ +From d326d21a44fbc48663840316c35524002029fbb1 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 22 Apr 2025 15:24:31 +0200 +Subject: [PATCH 29/32] arm64: dts: mediatek: mt7988a-bpi-r4: enable xsphy + +Enable XS-Phy on Bananapi R4 for pcie2. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 4 ++++ + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 +- + 2 files changed, 5 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi +@@ -397,3 +397,7 @@ + &watchdog { + status = "okay"; + }; ++ ++&xsphy { ++ status = "okay"; ++}; +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -560,7 +560,7 @@ + reg = <0 0x11d10084 0 0xff80>; + }; + +- xs-phy@11e10000 { ++ xsphy: xs-phy@11e10000 { + compatible = "mediatek,mt7988-xsphy", + "mediatek,xsphy"; + #address-cells = <2>; diff --git a/target/linux/mediatek/patches-6.12/173-dts-mt7988a-Add-built-in-ethernet-phy-firmware-node.patch b/target/linux/mediatek/patches-6.12/173-dts-mt7988a-Add-built-in-ethernet-phy-firmware-node.patch new file mode 100644 index 00000000000..698f821314e --- /dev/null +++ b/target/linux/mediatek/patches-6.12/173-dts-mt7988a-Add-built-in-ethernet-phy-firmware-node.patch @@ -0,0 +1,27 @@ +From 6cf55d4520eb4ef3ed2cc3726a765a89b0071d8b Mon Sep 17 00:00:00 2001 +From: Sky Huang +Date: Wed, 19 Feb 2025 16:39:09 +0800 +Subject: [PATCH 30/32] dts: mt7988a: Add built-in ethernet phy firmware node + +Add built-in ethernet phy firmware node in mt7988a.dtsi. + +Signed-off-by: Sky Huang +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -322,6 +322,12 @@ + nvmem-cell-names = "lvts-calib-data-1"; + }; + ++ phyfw: phy-firmware@f000000 { ++ compatible = "mediatek,2p5gphy-fw"; ++ reg = <0 0x0f100000 0 0x20000>, ++ <0 0x0f0f0018 0 0x20>; ++ }; ++ + usb@11190000 { + compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11190000 0 0x2e00>, diff --git a/target/linux/mediatek/patches-6.12/174-arm64-dts-mediatek-mt7988-add-spi-controllers.patch b/target/linux/mediatek/patches-6.12/174-arm64-dts-mediatek-mt7988-add-spi-controllers.patch new file mode 100644 index 00000000000..a0557ab966f --- /dev/null +++ b/target/linux/mediatek/patches-6.12/174-arm64-dts-mediatek-mt7988-add-spi-controllers.patch @@ -0,0 +1,112 @@ +From patchwork Sun May 11 14:19:20 2025 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Frank Wunderlich +X-Patchwork-Id: 14084127 +From: Frank Wunderlich +To: Andrew Lunn , + Vladimir Oltean , + "David S. Miller" , + Eric Dumazet , + Jakub Kicinski , + Paolo Abeni , + Rob Herring , + Krzysztof Kozlowski , + Conor Dooley , + Matthias Brugger , + AngeloGioacchino Del Regno +Subject: [PATCH v1 04/14] arm64: dts: mediatek: mt7988: add spi controllers +Date: Sun, 11 May 2025 16:19:20 +0200 +Message-ID: <20250511141942.10284-5-linux@fw-web.de> +X-Mailer: git-send-email 2.43.0 +In-Reply-To: <20250511141942.10284-1-linux@fw-web.de> +References: <20250511141942.10284-1-linux@fw-web.de> +MIME-Version: 1.0 +X-Mail-ID: 5110cbfc-28b8-49e4-b9da-560d0bd630a5 +X-BeenThere: linux-mediatek@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Cc: devicetree@vger.kernel.org, Landen Chao , + =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , + netdev@vger.kernel.org, Sean Wang , + Daniel Golle , linux-kernel@vger.kernel.org, + DENG Qingfang , linux-mediatek@lists.infradead.org, + Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, + Felix Fietkau +Sender: "Linux-mediatek" +Errors-To: + linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org + +From: Frank Wunderlich + +Add SPI controllers for mt7988. + +Signed-off-by: Daniel Golle +Signed-off-by: Frank Wunderlich +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 45 +++++++++++++++++++++++ + 1 file changed, 45 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -311,6 +311,51 @@ + status = "disabled"; + }; + ++ spi0: spi@11007000 { ++ compatible = "mediatek,mt7988-spi-quad", "mediatek,spi-ipm"; ++ reg = <0 0x11007000 0 0x100>; ++ interrupts = ; ++ clocks = <&topckgen CLK_TOP_MPLL_D2>, ++ <&topckgen CLK_TOP_SPI_SEL>, ++ <&infracfg CLK_INFRA_104M_SPI0>, ++ <&infracfg CLK_INFRA_66M_SPI0_HCK>; ++ clock-names = "parent-clk", "sel-clk", "spi-clk", ++ "hclk"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spi1: spi@11008000 { ++ compatible = "mediatek,mt7988-spi-single", "mediatek,spi-ipm"; ++ reg = <0 0x11008000 0 0x100>; ++ interrupts = ; ++ clocks = <&topckgen CLK_TOP_MPLL_D2>, ++ <&topckgen CLK_TOP_SPIM_MST_SEL>, ++ <&infracfg CLK_INFRA_104M_SPI1>, ++ <&infracfg CLK_INFRA_66M_SPI1_HCK>; ++ clock-names = "parent-clk", "sel-clk", "spi-clk", ++ "hclk"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spi2: spi@11009000 { ++ compatible = "mediatek,mt7988-spi-quad", "mediatek,spi-ipm"; ++ reg = <0 0x11009000 0 0x100>; ++ interrupts = ; ++ clocks = <&topckgen CLK_TOP_MPLL_D2>, ++ <&topckgen CLK_TOP_SPI_SEL>, ++ <&infracfg CLK_INFRA_104M_SPI2_BCK>, ++ <&infracfg CLK_INFRA_66M_SPI2_HCK>; ++ clock-names = "parent-clk", "sel-clk", "spi-clk", ++ "hclk"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + lvts: lvts@1100a000 { + compatible = "mediatek,mt7988-lvts-ap"; + #thermal-sensor-cells = <1>; diff --git a/target/linux/mediatek/patches-6.12/175-arm64-dts-mediatek-mt7988-move-uart0-and-spi1-pins-to-soc-dtsi.patch b/target/linux/mediatek/patches-6.12/175-arm64-dts-mediatek-mt7988-move-uart0-and-spi1-pins-to-soc-dtsi.patch new file mode 100644 index 00000000000..7dbc1e4286a --- /dev/null +++ b/target/linux/mediatek/patches-6.12/175-arm64-dts-mediatek-mt7988-move-uart0-and-spi1-pins-to-soc-dtsi.patch @@ -0,0 +1,133 @@ +From patchwork Sun May 11 14:19:21 2025 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Frank Wunderlich +X-Patchwork-Id: 14084155 +From: Frank Wunderlich +To: Andrew Lunn , + Vladimir Oltean , + "David S. Miller" , + Eric Dumazet , + Jakub Kicinski , + Paolo Abeni , + Rob Herring , + Krzysztof Kozlowski , + Conor Dooley , + Matthias Brugger , + AngeloGioacchino Del Regno +Subject: [PATCH v1 05/14] arm64: dts: mediatek: mt7988: move uart0 and spi1 + pins to soc dtsi +Date: Sun, 11 May 2025 16:19:21 +0200 +Message-ID: <20250511141942.10284-6-linux@fw-web.de> +X-Mailer: git-send-email 2.43.0 +In-Reply-To: <20250511141942.10284-1-linux@fw-web.de> +References: <20250511141942.10284-1-linux@fw-web.de> +MIME-Version: 1.0 +X-Mail-ID: 730e5bd4-362e-4c00-a35e-0ec77e8f4691 +X-BeenThere: linux-mediatek@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Cc: devicetree@vger.kernel.org, Landen Chao , + =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , + netdev@vger.kernel.org, Sean Wang , + Daniel Golle , linux-kernel@vger.kernel.org, + DENG Qingfang , linux-mediatek@lists.infradead.org, + Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, + Felix Fietkau +Sender: "Linux-mediatek" +Errors-To: + linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org + +From: Frank Wunderlich + +In order to use uart0 or spi1 there is only 1 possible pin definition +so move them to soc dtsi to reuse them in other boards and avoiding +conflict if defined twice. + +Suggested-by: Daniel Golle +Signed-off-by: Frank Wunderlich +--- + .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 14 -------------- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 18 ++++++++++++++++++ + 2 files changed, 18 insertions(+), 14 deletions(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi +@@ -328,13 +328,6 @@ + }; + }; + +- uart0_pins: uart0-pins { +- mux { +- function = "uart"; +- groups = "uart0"; +- }; +- }; +- + snfi_pins: snfi-pins { + mux { + function = "flash"; +@@ -356,13 +349,6 @@ + }; + }; + +- spi1_pins: spi1-pins { +- mux { +- function = "spi"; +- groups = "spi1"; +- }; +- }; +- + spi2_pins: spi2-pins { + mux { + function = "spi"; +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -209,6 +209,20 @@ + "pcie_wake_n3_0"; + }; + }; ++ ++ spi1_pins: spi1-pins { ++ mux { ++ function = "spi"; ++ groups = "spi1"; ++ }; ++ }; ++ ++ uart0_pins: uart0-pins { ++ mux { ++ function = "uart"; ++ groups = "uart0"; ++ }; ++ }; + }; + + pwm: pwm@10048000 { +@@ -244,6 +258,8 @@ + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_52M_UART0_CK>; + clock-names = "baud", "bus"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins>; + status = "disabled"; + }; + +@@ -338,6 +354,8 @@ + "hclk"; + #address-cells = <1>; + #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins>; + status = "disabled"; + }; + diff --git a/target/linux/mediatek/patches-6.12/176-arm64-dts-mediatek-mt7988-add-cci-node.patch b/target/linux/mediatek/patches-6.12/176-arm64-dts-mediatek-mt7988-add-cci-node.patch new file mode 100644 index 00000000000..915c45caebf --- /dev/null +++ b/target/linux/mediatek/patches-6.12/176-arm64-dts-mediatek-mt7988-add-cci-node.patch @@ -0,0 +1,128 @@ +From patchwork Sun May 11 14:19:22 2025 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Frank Wunderlich +X-Patchwork-Id: 14084106 +From: Frank Wunderlich +To: Andrew Lunn , + Vladimir Oltean , + "David S. Miller" , + Eric Dumazet , + Jakub Kicinski , + Paolo Abeni , + Rob Herring , + Krzysztof Kozlowski , + Conor Dooley , + Matthias Brugger , + AngeloGioacchino Del Regno +Subject: [PATCH v1 06/14] arm64: dts: mediatek: mt7988: add cci node +Date: Sun, 11 May 2025 16:19:22 +0200 +Message-ID: <20250511141942.10284-7-linux@fw-web.de> +X-Mailer: git-send-email 2.43.0 +In-Reply-To: <20250511141942.10284-1-linux@fw-web.de> +References: <20250511141942.10284-1-linux@fw-web.de> +MIME-Version: 1.0 +X-Mail-ID: beeb7784-23fa-410f-9e58-cc51116d869e +X-BeenThere: linux-mediatek@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Cc: devicetree@vger.kernel.org, Landen Chao , + =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , + netdev@vger.kernel.org, Sean Wang , + Daniel Golle , linux-kernel@vger.kernel.org, + DENG Qingfang , linux-mediatek@lists.infradead.org, + Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, + Felix Fietkau +Sender: "Linux-mediatek" +Errors-To: + linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org + +From: Frank Wunderlich + +Add cci devicetree node for cpu frequency scaling. + +Signed-off-by: Daniel Golle +Signed-off-by: Frank Wunderlich +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 33 +++++++++++++++++++++++ + 1 file changed, 33 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -12,6 +12,35 @@ + #address-cells = <2>; + #size-cells = <2>; + ++ cci: cci { ++ compatible = "mediatek,mt8183-cci"; ++ clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>, ++ <&topckgen CLK_TOP_XTAL>; ++ clock-names = "cci", "intermediate"; ++ operating-points-v2 = <&cci_opp>; ++ }; ++ ++ cci_opp: opp-table-cci { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ opp-480000000 { ++ opp-hz = /bits/ 64 <480000000>; ++ opp-microvolt = <850000>; ++ }; ++ opp-660000000 { ++ opp-hz = /bits/ 64 <660000000>; ++ opp-microvolt = <850000>; ++ }; ++ opp-900000000 { ++ opp-hz = /bits/ 64 <900000000>; ++ opp-microvolt = <850000>; ++ }; ++ opp-1080000000 { ++ opp-hz = /bits/ 64 <1080000000>; ++ opp-microvolt = <900000>; ++ }; ++ }; ++ + cpus { + #address-cells = <1>; + #size-cells = <0>; +@@ -25,6 +54,7 @@ + <&topckgen CLK_TOP_XTAL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; ++ mediatek,cci = <&cci>; + }; + + cpu1: cpu@1 { +@@ -36,6 +66,7 @@ + <&topckgen CLK_TOP_XTAL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; ++ mediatek,cci = <&cci>; + }; + + cpu2: cpu@2 { +@@ -47,6 +78,7 @@ + <&topckgen CLK_TOP_XTAL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; ++ mediatek,cci = <&cci>; + }; + + cpu3: cpu@3 { +@@ -58,6 +90,7 @@ + <&topckgen CLK_TOP_XTAL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; ++ mediatek,cci = <&cci>; + }; + + cluster0_opp: opp-table-0 { diff --git a/target/linux/mediatek/patches-6.12/177-arm64-dts-mediatek-mt7988-add-phy-calibration-efuse-subnodes.patch b/target/linux/mediatek/patches-6.12/177-arm64-dts-mediatek-mt7988-add-phy-calibration-efuse-subnodes.patch new file mode 100644 index 00000000000..dc6df8ee576 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/177-arm64-dts-mediatek-mt7988-add-phy-calibration-efuse-subnodes.patch @@ -0,0 +1,85 @@ +From patchwork Sun May 11 14:19:23 2025 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Frank Wunderlich +X-Patchwork-Id: 14084124 +From: Frank Wunderlich +To: Andrew Lunn , + Vladimir Oltean , + "David S. Miller" , + Eric Dumazet , + Jakub Kicinski , + Paolo Abeni , + Rob Herring , + Krzysztof Kozlowski , + Conor Dooley , + Matthias Brugger , + AngeloGioacchino Del Regno +Subject: [PATCH v1 07/14] arm64: dts: mediatek: mt7988: add phy calibration + efuse subnodes +Date: Sun, 11 May 2025 16:19:23 +0200 +Message-ID: <20250511141942.10284-8-linux@fw-web.de> +X-Mailer: git-send-email 2.43.0 +In-Reply-To: <20250511141942.10284-1-linux@fw-web.de> +References: <20250511141942.10284-1-linux@fw-web.de> +MIME-Version: 1.0 +X-Mail-ID: b7327c0d-db13-43b6-8ec5-709b71d19c3b +X-BeenThere: linux-mediatek@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Cc: devicetree@vger.kernel.org, Landen Chao , + =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , + netdev@vger.kernel.org, Sean Wang , + Daniel Golle , linux-kernel@vger.kernel.org, + DENG Qingfang , linux-mediatek@lists.infradead.org, + Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, + Felix Fietkau +Sender: "Linux-mediatek" +Errors-To: + linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org + +From: Frank Wunderlich + +MT7988 contains buildin mt753x switch which needs calibration data from +efuse. + +Signed-off-by: Daniel Golle +Signed-off-by: Frank Wunderlich +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -702,6 +702,22 @@ + lvts_calibration: calib@918 { + reg = <0x918 0x28>; + }; ++ ++ phy_calibration_p0: calib@940 { ++ reg = <0x940 0x10>; ++ }; ++ ++ phy_calibration_p1: calib@954 { ++ reg = <0x954 0x10>; ++ }; ++ ++ phy_calibration_p2: calib@968 { ++ reg = <0x968 0x10>; ++ }; ++ ++ phy_calibration_p3: calib@97c { ++ reg = <0x97c 0x10>; ++ }; + }; + + clock-controller@15000000 { diff --git a/target/linux/mediatek/patches-6.12/178-arm64-dts-mediatek-mt7988-add-basic-ethernet-nodes.patch b/target/linux/mediatek/patches-6.12/178-arm64-dts-mediatek-mt7988-add-basic-ethernet-nodes.patch new file mode 100644 index 00000000000..15c8ad7ea0b --- /dev/null +++ b/target/linux/mediatek/patches-6.12/178-arm64-dts-mediatek-mt7988-add-basic-ethernet-nodes.patch @@ -0,0 +1,213 @@ +From patchwork Sun May 11 14:19:24 2025 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Frank Wunderlich +X-Patchwork-Id: 14084161 +From: Frank Wunderlich +To: Andrew Lunn , + Vladimir Oltean , + "David S. Miller" , + Eric Dumazet , + Jakub Kicinski , + Paolo Abeni , + Rob Herring , + Krzysztof Kozlowski , + Conor Dooley , + Matthias Brugger , + AngeloGioacchino Del Regno +Subject: [PATCH v1 08/14] arm64: dts: mediatek: mt7988: add basic + ethernet-nodes +Date: Sun, 11 May 2025 16:19:24 +0200 +Message-ID: <20250511141942.10284-9-linux@fw-web.de> +X-Mailer: git-send-email 2.43.0 +In-Reply-To: <20250511141942.10284-1-linux@fw-web.de> +References: <20250511141942.10284-1-linux@fw-web.de> +MIME-Version: 1.0 +X-Mail-ID: 5c8e73b6-e2d6-4898-90c0-375604707c20 +X-BeenThere: linux-mediatek@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Cc: devicetree@vger.kernel.org, Landen Chao , + =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , + netdev@vger.kernel.org, Sean Wang , + Daniel Golle , linux-kernel@vger.kernel.org, + DENG Qingfang , linux-mediatek@lists.infradead.org, + Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, + Felix Fietkau +Sender: "Linux-mediatek" +Errors-To: + linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org + +From: Frank Wunderlich + +Add basic ethernet related nodes. + +Mac1+2 needs pcs (sgmii+usxgmii) to work correctly which will be linked +later when driver is merged. + +Signed-off-by: Daniel Golle +Signed-off-by: Frank Wunderlich +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 124 +++++++++++++++++++++- + 1 file changed, 121 insertions(+), 3 deletions(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -686,7 +686,28 @@ + }; + }; + +- clock-controller@11f40000 { ++ xfi_tphy0: phy@11f20000 { ++ compatible = "mediatek,mt7988-xfi-tphy"; ++ reg = <0 0x11f20000 0 0x10000>; ++ resets = <&watchdog 14>; ++ clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, ++ <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>; ++ clock-names = "xfipll", "topxtal"; ++ mediatek,usxgmii-performance-errata; ++ #phy-cells = <0>; ++ }; ++ ++ xfi_tphy1: phy@11f30000 { ++ compatible = "mediatek,mt7988-xfi-tphy"; ++ reg = <0 0x11f30000 0 0x10000>; ++ resets = <&watchdog 15>; ++ clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, ++ <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>; ++ clock-names = "xfipll", "topxtal"; ++ #phy-cells = <0>; ++ }; ++ ++ xfi_pll: clock-controller@11f40000 { + compatible = "mediatek,mt7988-xfi-pll"; + reg = <0 0x11f40000 0 0x1000>; + resets = <&watchdog 16>; +@@ -720,19 +741,116 @@ + }; + }; + +- clock-controller@15000000 { ++ ethsys: clock-controller@15000000 { + compatible = "mediatek,mt7988-ethsys", "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + +- clock-controller@15031000 { ++ ethwarp: clock-controller@15031000 { + compatible = "mediatek,mt7988-ethwarp"; + reg = <0 0x15031000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; ++ ++ eth: ethernet@15100000 { ++ compatible = "mediatek,mt7988-eth"; ++ reg = <0 0x15100000 0 0x80000>, ++ <0 0x15400000 0 0x200000>; ++ interrupts = , ++ , ++ , ++ ; ++ clocks = <ðsys CLK_ETHDMA_CRYPT0_EN>, ++ <ðsys CLK_ETHDMA_FE_EN>, ++ <ðsys CLK_ETHDMA_GP2_EN>, ++ <ðsys CLK_ETHDMA_GP1_EN>, ++ <ðsys CLK_ETHDMA_GP3_EN>, ++ <ðwarp CLK_ETHWARP_WOCPU2_EN>, ++ <ðwarp CLK_ETHWARP_WOCPU1_EN>, ++ <ðwarp CLK_ETHWARP_WOCPU0_EN>, ++ <ðsys CLK_ETHDMA_ESW_EN>, ++ <&topckgen CLK_TOP_ETH_GMII_SEL>, ++ <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>, ++ <&topckgen CLK_TOP_ETH_SYS_200M_SEL>, ++ <&topckgen CLK_TOP_ETH_SYS_SEL>, ++ <&topckgen CLK_TOP_ETH_XGMII_SEL>, ++ <&topckgen CLK_TOP_ETH_MII_SEL>, ++ <&topckgen CLK_TOP_NETSYS_SEL>, ++ <&topckgen CLK_TOP_NETSYS_500M_SEL>, ++ <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>, ++ <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>, ++ <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>, ++ <&topckgen CLK_TOP_NETSYS_WARP_SEL>, ++ <ðsys CLK_ETHDMA_XGP1_EN>, ++ <ðsys CLK_ETHDMA_XGP2_EN>, ++ <ðsys CLK_ETHDMA_XGP3_EN>; ++ clock-names = "crypto", "fe", "gp2", "gp1", ++ "gp3", ++ "ethwarp_wocpu2", "ethwarp_wocpu1", ++ "ethwarp_wocpu0", "esw", "top_eth_gmii_sel", ++ "top_eth_refck_50m_sel", "top_eth_sys_200m_sel", ++ "top_eth_sys_sel", "top_eth_xgmii_sel", ++ "top_eth_mii_sel", "top_netsys_sel", ++ "top_netsys_500m_sel", "top_netsys_pao_2x_sel", ++ "top_netsys_sync_250m_sel", ++ "top_netsys_ppefb_250m_sel", ++ "top_netsys_warp_sel","xgp1", "xgp2", "xgp3"; ++ assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, ++ <&topckgen CLK_TOP_NETSYS_GSW_SEL>, ++ <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>, ++ <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>, ++ <&topckgen CLK_TOP_SGM_0_SEL>, ++ <&topckgen CLK_TOP_SGM_1_SEL>; ++ assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, ++ <&topckgen CLK_TOP_NET1PLL_D4>, ++ <&topckgen CLK_TOP_NET1PLL_D8_D4>, ++ <&topckgen CLK_TOP_NET1PLL_D8_D4>, ++ <&apmixedsys CLK_APMIXED_SGMPLL>, ++ <&apmixedsys CLK_APMIXED_SGMPLL>; ++ mediatek,ethsys = <ðsys>; ++ mediatek,infracfg = <&topmisc>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ gmac0: mac@0 { ++ compatible = "mediatek,eth-mac"; ++ reg = <0>; ++ phy-mode = "internal"; ++ ++ fixed-link { ++ speed = <10000>; ++ full-duplex; ++ pause; ++ }; ++ }; ++ ++ gmac1: mac@1 { ++ compatible = "mediatek,eth-mac"; ++ reg = <1>; ++ status = "disabled"; ++ }; ++ ++ gmac2: mac@2 { ++ compatible = "mediatek,eth-mac"; ++ reg = <2>; ++ status = "disabled"; ++ }; ++ ++ mdio_bus: mdio-bus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ /* internal 2.5G PHY */ ++ int_2p5g_phy: ethernet-phy@f { ++ reg = <15>; ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ phy-mode = "internal"; ++ }; ++ }; ++ }; + }; + + thermal-zones { diff --git a/target/linux/mediatek/patches-6.12/179-arm64-dts-mediatek-mt7988-add-switch-node.patch b/target/linux/mediatek/patches-6.12/179-arm64-dts-mediatek-mt7988-add-switch-node.patch new file mode 100644 index 00000000000..de43734c268 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/179-arm64-dts-mediatek-mt7988-add-switch-node.patch @@ -0,0 +1,228 @@ +From patchwork Sun May 11 14:19:25 2025 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Frank Wunderlich +X-Patchwork-Id: 14084123 +From: Frank Wunderlich +To: Andrew Lunn , + Vladimir Oltean , + "David S. Miller" , + Eric Dumazet , + Jakub Kicinski , + Paolo Abeni , + Rob Herring , + Krzysztof Kozlowski , + Conor Dooley , + Matthias Brugger , + AngeloGioacchino Del Regno +Subject: [PATCH v1 09/14] arm64: dts: mediatek: mt7988: add switch node +Date: Sun, 11 May 2025 16:19:25 +0200 +Message-ID: <20250511141942.10284-10-linux@fw-web.de> +X-Mailer: git-send-email 2.43.0 +In-Reply-To: <20250511141942.10284-1-linux@fw-web.de> +References: <20250511141942.10284-1-linux@fw-web.de> +MIME-Version: 1.0 +X-Mail-ID: a24ecea1-b7fd-4cb4-a93d-b29036e2e6ac +X-BeenThere: linux-mediatek@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Cc: devicetree@vger.kernel.org, Landen Chao , + =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , + netdev@vger.kernel.org, Sean Wang , + Daniel Golle , linux-kernel@vger.kernel.org, + DENG Qingfang , linux-mediatek@lists.infradead.org, + Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, + Felix Fietkau +Sender: "Linux-mediatek" +Errors-To: + linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org + +From: Frank Wunderlich + +Add mt7988 builtin mt753x switch nodes. + +Signed-off-by: Daniel Golle +Signed-off-by: Frank Wunderlich +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 166 ++++++++++++++++++++++ + 1 file changed, 166 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -5,6 +5,7 @@ + #include + #include + #include ++#include + + / { + compatible = "mediatek,mt7988a"; +@@ -748,6 +749,159 @@ + #reset-cells = <1>; + }; + ++ switch: switch@15020000 { ++ compatible = "mediatek,mt7988-switch"; ++ reg = <0 0x15020000 0 0x8000>; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ interrupt-parent = <&gic>; ++ interrupts = ; ++ resets = <ðwarp MT7988_ETHWARP_RST_SWITCH>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ gsw_port0: port@0 { ++ reg = <0>; ++ phy-mode = "internal"; ++ phy-handle = <&gsw_phy0>; ++ }; ++ ++ gsw_port1: port@1 { ++ reg = <1>; ++ phy-mode = "internal"; ++ phy-handle = <&gsw_phy1>; ++ }; ++ ++ gsw_port2: port@2 { ++ reg = <2>; ++ phy-mode = "internal"; ++ phy-handle = <&gsw_phy2>; ++ }; ++ ++ gsw_port3: port@3 { ++ reg = <3>; ++ phy-mode = "internal"; ++ phy-handle = <&gsw_phy3>; ++ }; ++ ++ port@6 { ++ reg = <6>; ++ ethernet = <&gmac0>; ++ phy-mode = "internal"; ++ ++ fixed-link { ++ speed = <10000>; ++ full-duplex; ++ pause; ++ }; ++ }; ++ }; ++ ++ mdio { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ mediatek,pio = <&pio>; ++ ++ gsw_phy0: ethernet-phy@0 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <0>; ++ interrupts = <0>; ++ phy-mode = "internal"; ++ nvmem-cells = <&phy_calibration_p0>; ++ nvmem-cell-names = "phy-cal-data"; ++ ++ leds { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ gsw_phy0_led0: led@0 { ++ reg = <0>; ++ status = "disabled"; ++ }; ++ ++ gsw_phy0_led1: led@1 { ++ reg = <1>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ gsw_phy1: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ interrupts = <1>; ++ phy-mode = "internal"; ++ nvmem-cells = <&phy_calibration_p1>; ++ nvmem-cell-names = "phy-cal-data"; ++ ++ leds { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ gsw_phy1_led0: led@0 { ++ reg = <0>; ++ status = "disabled"; ++ }; ++ ++ gsw_phy1_led1: led@1 { ++ reg = <1>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ gsw_phy2: ethernet-phy@2 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <2>; ++ interrupts = <2>; ++ phy-mode = "internal"; ++ nvmem-cells = <&phy_calibration_p2>; ++ nvmem-cell-names = "phy-cal-data"; ++ ++ leds { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ gsw_phy2_led0: led@0 { ++ reg = <0>; ++ status = "disabled"; ++ }; ++ ++ gsw_phy2_led1: led@1 { ++ reg = <1>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ gsw_phy3: ethernet-phy@3 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <3>; ++ interrupts = <3>; ++ phy-mode = "internal"; ++ nvmem-cells = <&phy_calibration_p3>; ++ nvmem-cell-names = "phy-cal-data"; ++ ++ leds { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ gsw_phy3_led0: led@0 { ++ reg = <0>; ++ status = "disabled"; ++ }; ++ ++ gsw_phy3_led1: led@1 { ++ reg = <1>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ }; ++ }; ++ + ethwarp: clock-controller@15031000 { + compatible = "mediatek,mt7988-ethwarp"; + reg = <0 0x15031000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.12/180-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fan-and-coolingmaps.patch b/target/linux/mediatek/patches-6.12/180-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fan-and-coolingmaps.patch new file mode 100644 index 00000000000..4e3d4ae8c0e --- /dev/null +++ b/target/linux/mediatek/patches-6.12/180-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fan-and-coolingmaps.patch @@ -0,0 +1,98 @@ +From patchwork Sun May 11 14:26:50 2025 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Frank Wunderlich +X-Patchwork-Id: 14084133 +From: Frank Wunderlich +To: Andrew Lunn , + Vladimir Oltean , + "David S. Miller" , + Eric Dumazet , + Jakub Kicinski , + Paolo Abeni , + Rob Herring , + Krzysztof Kozlowski , + Conor Dooley , + Matthias Brugger , + AngeloGioacchino Del Regno +Subject: [PATCH v1 10/14] arm64: dts: mediatek: mt7988a-bpi-r4: Add fan and + coolingmaps +Date: Sun, 11 May 2025 16:26:50 +0200 +Message-ID: <20250511142655.11007-1-frank-w@public-files.de> +X-Mailer: git-send-email 2.43.0 +MIME-Version: 1.0 +X-BeenThere: linux-mediatek@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Cc: devicetree@vger.kernel.org, Landen Chao , + =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , + netdev@vger.kernel.org, Sean Wang , + Daniel Golle , linux-kernel@vger.kernel.org, + DENG Qingfang , linux-mediatek@lists.infradead.org, + Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, + Felix Fietkau +Sender: "Linux-mediatek" +Errors-To: + linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org + +Add Fan and cooling maps for Bananpi-R4 board. + +Signed-off-by: Frank Wunderlich +--- + .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 29 +++++++++++++++++++ + 1 file changed, 29 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi +@@ -12,6 +12,15 @@ + stdout-path = "serial0:115200n8"; + }; + ++ fan: pwm-fan { ++ compatible = "pwm-fan"; ++ /* cooling level (0, 1, 2, 3) : (0% duty, 30% duty, 50% duty, 100% duty) */ ++ cooling-levels = <0 80 128 255>; ++ #cooling-cells = <2>; ++ pwms = <&pwm 0 50000>; ++ status = "okay"; ++ }; ++ + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; +@@ -73,6 +82,26 @@ + type = "active"; + }; + }; ++ ++ cooling-maps { ++ map-cpu-active-high { ++ /* active: set fan to cooling level 2 */ ++ cooling-device = <&fan 3 3>; ++ trip = <&cpu_trip_active_high>; ++ }; ++ ++ map-cpu-active-med { ++ /* active: set fan to cooling level 1 */ ++ cooling-device = <&fan 2 2>; ++ trip = <&cpu_trip_active_med>; ++ }; ++ ++ map-cpu-active-low { ++ /* active: set fan to cooling level 0 */ ++ cooling-device = <&fan 1 1>; ++ trip = <&cpu_trip_active_low>; ++ }; ++ }; + }; + + &i2c0 { diff --git a/target/linux/mediatek/patches-6.12/181-arm64-dts-mediatek-mt7988a-bpi-r4-configure-spi-nodes.patch b/target/linux/mediatek/patches-6.12/181-arm64-dts-mediatek-mt7988a-bpi-r4-configure-spi-nodes.patch new file mode 100644 index 00000000000..c5c5e83e92b --- /dev/null +++ b/target/linux/mediatek/patches-6.12/181-arm64-dts-mediatek-mt7988a-bpi-r4-configure-spi-nodes.patch @@ -0,0 +1,99 @@ +From patchwork Sun May 11 14:26:51 2025 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Frank Wunderlich +X-Patchwork-Id: 14084136 +Received: from frank-u24 ([194.15.84.99]) by mail.gmx.net (mrgmx104 + [212.227.17.168]) with ESMTPSA (Nemesis) id 1MD9XF-1u5YvB0cIj-00FOt5; Sun, 11 + May 2025 16:27:04 +0200 +From: Frank Wunderlich +To: Andrew Lunn , + Vladimir Oltean , + "David S. Miller" , + Eric Dumazet , + Jakub Kicinski , + Paolo Abeni , + Rob Herring , + Krzysztof Kozlowski , + Conor Dooley , + Matthias Brugger , + AngeloGioacchino Del Regno +Subject: [PATCH v1 11/14] arm64: dts: mediatek: mt7988a-bpi-r4: configure + spi-nodes +Date: Sun, 11 May 2025 16:26:51 +0200 +Message-ID: <20250511142655.11007-2-frank-w@public-files.de> +X-Mailer: git-send-email 2.43.0 +In-Reply-To: <20250511142655.11007-1-frank-w@public-files.de> +References: <20250511142655.11007-1-frank-w@public-files.de> +MIME-Version: 1.0 +X-BeenThere: linux-mediatek@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Cc: devicetree@vger.kernel.org, Landen Chao , + =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , + netdev@vger.kernel.org, Sean Wang , + Daniel Golle , linux-kernel@vger.kernel.org, + DENG Qingfang , linux-mediatek@lists.infradead.org, + Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, + Felix Fietkau +Sender: "Linux-mediatek" +Errors-To: + linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org + +Configure and enable SPI nodes on Bananapi R4 board. + +Signed-off-by: Frank Wunderlich +--- + .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 32 +++++++++++++++++++ + 1 file changed, 32 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi +@@ -401,6 +401,38 @@ + status = "okay"; + }; + ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_flash_pins>; ++ status = "okay"; ++ ++ spi_nand: flash@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <52000000>; ++ spi-tx-bus-width = <4>; ++ spi-rx-bus-width = <4>; ++ }; ++}; ++ ++&spi1 { ++ status = "okay"; ++}; ++ ++&spi_nand { ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "bl2"; ++ reg = <0x0 0x200000>; ++ read-only; ++ }; ++ }; ++}; ++ + &ssusb1 { + status = "okay"; + }; diff --git a/target/linux/mediatek/patches-6.12/182-arm64-dts-mediatek-mt7988a-bpi-r4-add-proc-supply-for-cci.patch b/target/linux/mediatek/patches-6.12/182-arm64-dts-mediatek-mt7988a-bpi-r4-add-proc-supply-for-cci.patch new file mode 100644 index 00000000000..f692a6f1c4e --- /dev/null +++ b/target/linux/mediatek/patches-6.12/182-arm64-dts-mediatek-mt7988a-bpi-r4-add-proc-supply-for-cci.patch @@ -0,0 +1,68 @@ +From patchwork Sun May 11 14:26:52 2025 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Frank Wunderlich +X-Patchwork-Id: 14084137 +From: Frank Wunderlich +To: Andrew Lunn , + Vladimir Oltean , + "David S. Miller" , + Eric Dumazet , + Jakub Kicinski , + Paolo Abeni , + Rob Herring , + Krzysztof Kozlowski , + Conor Dooley , + Matthias Brugger , + AngeloGioacchino Del Regno +Subject: [PATCH v1 12/14] arm64: dts: mediatek: mt7988a-bpi-r4: add + proc-supply for cci +Date: Sun, 11 May 2025 16:26:52 +0200 +Message-ID: <20250511142655.11007-3-frank-w@public-files.de> +X-Mailer: git-send-email 2.43.0 +In-Reply-To: <20250511142655.11007-1-frank-w@public-files.de> +References: <20250511142655.11007-1-frank-w@public-files.de> +MIME-Version: 1.0 +X-BeenThere: linux-mediatek@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Cc: devicetree@vger.kernel.org, Landen Chao , + =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , + netdev@vger.kernel.org, Sean Wang , + Daniel Golle , linux-kernel@vger.kernel.org, + DENG Qingfang , linux-mediatek@lists.infradead.org, + Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, + Felix Fietkau +Sender: "Linux-mediatek" +Errors-To: + linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org + +CCI requires proc-supply. Add it on board level. + +Signed-off-by: Frank Wunderlich +--- + arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi +@@ -40,6 +40,10 @@ + }; + }; + ++&cci { ++ proc-supply = <&rt5190_buck3>; ++}; ++ + &cpu0 { + proc-supply = <&rt5190_buck3>; + }; diff --git a/target/linux/mediatek/patches-6.12/183-arm64-dts-mediatek-mt7988a-bpi-r4-add-sfp-cages-and-link-to-gmac.patch b/target/linux/mediatek/patches-6.12/183-arm64-dts-mediatek-mt7988a-bpi-r4-add-sfp-cages-and-link-to-gmac.patch new file mode 100644 index 00000000000..9861dc0f5b1 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/183-arm64-dts-mediatek-mt7988a-bpi-r4-add-sfp-cages-and-link-to-gmac.patch @@ -0,0 +1,138 @@ +From patchwork Sun May 11 14:26:53 2025 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Frank Wunderlich +X-Patchwork-Id: 14084128 +From: Frank Wunderlich +To: Andrew Lunn , + Vladimir Oltean , + "David S. Miller" , + Eric Dumazet , + Jakub Kicinski , + Paolo Abeni , + Rob Herring , + Krzysztof Kozlowski , + Conor Dooley , + Matthias Brugger , + AngeloGioacchino Del Regno +Subject: [PATCH v1 13/14] arm64: dts: mediatek: mt7988a-bpi-r4: add sfp cages + and link to gmac +Date: Sun, 11 May 2025 16:26:53 +0200 +Message-ID: <20250511142655.11007-4-frank-w@public-files.de> +X-Mailer: git-send-email 2.43.0 +In-Reply-To: <20250511142655.11007-1-frank-w@public-files.de> +References: <20250511142655.11007-1-frank-w@public-files.de> +MIME-Version: 1.0 +X-BeenThere: linux-mediatek@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Cc: devicetree@vger.kernel.org, Landen Chao , + =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , + netdev@vger.kernel.org, Sean Wang , + Daniel Golle , linux-kernel@vger.kernel.org, + DENG Qingfang , linux-mediatek@lists.infradead.org, + Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, + Felix Fietkau +Sender: "Linux-mediatek" +Errors-To: + linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org + +Add SFP cages to Bananapi-R4 board. The 2.5g phy variant only contains the +wan-SFP, so add this to common dtsi and the lan-sfp only to the dual-SFP +variant. + +Signed-off-by: Daniel Golle +Signed-off-by: Frank Wunderlich +--- + .../mediatek/mt7988a-bananapi-bpi-r4-2g5.dts | 11 +++++++++++ + .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 18 ++++++++++++++++++ + .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 18 ++++++++++++++++++ + 3 files changed, 47 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts +@@ -9,3 +9,14 @@ + model = "Banana Pi BPI-R4 (1x SFP+, 1x 2.5GbE)"; + chassis-type = "embedded"; + }; ++ ++&gmac1 { ++ phy-mode = "internal"; ++ phy-connection-type = "internal"; ++ phy = <&int_2p5g_phy>; ++}; ++ ++&int_2p5g_phy { ++ pinctrl-names = "i2p5gbe-led"; ++ pinctrl-0 = <&i2p5gbe_led0_pins>; ++}; +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +@@ -8,6 +8,24 @@ + compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; + model = "Banana Pi BPI-R4 (2x SFP+)"; + chassis-type = "embedded"; ++ ++ /* SFP2 cage (LAN) */ ++ sfp2: sfp2 { ++ compatible = "sff,sfp"; ++ i2c-bus = <&i2c_sfp2>; ++ los-gpios = <&pio 2 GPIO_ACTIVE_HIGH>; ++ mod-def0-gpios = <&pio 83 GPIO_ACTIVE_LOW>; ++ tx-disable-gpios = <&pio 0 GPIO_ACTIVE_HIGH>; ++ tx-fault-gpios = <&pio 1 GPIO_ACTIVE_HIGH>; ++ rate-select0-gpios = <&pio 3 GPIO_ACTIVE_LOW>; ++ maximum-power-milliwatt = <3000>; ++ }; ++}; ++ ++&gmac1 { ++ sfp = <&sfp2>; ++ managed = "in-band-status"; ++ phy-mode = "usxgmii"; + }; + + &pca9545 { +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi +@@ -38,6 +38,18 @@ + regulator-boot-on; + regulator-always-on; + }; ++ ++ /* SFP1 cage (WAN) */ ++ sfp1: sfp1 { ++ compatible = "sff,sfp"; ++ i2c-bus = <&i2c_sfp1>; ++ los-gpios = <&pio 54 GPIO_ACTIVE_HIGH>; ++ mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>; ++ tx-disable-gpios = <&pio 70 GPIO_ACTIVE_HIGH>; ++ tx-fault-gpios = <&pio 69 GPIO_ACTIVE_HIGH>; ++ rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>; ++ maximum-power-milliwatt = <3000>; ++ }; + }; + + &cci { +@@ -108,6 +120,12 @@ + }; + }; + ++&gmac2 { ++ sfp = <&sfp1>; ++ managed = "in-band-status"; ++ phy-mode = "usxgmii"; ++}; ++ + &i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; diff --git a/target/linux/mediatek/patches-6.12/184-arm64-dts-mediatek-mt7988a-bpi-r4-configure-switch-phys-and-leds.patch b/target/linux/mediatek/patches-6.12/184-arm64-dts-mediatek-mt7988a-bpi-r4-configure-switch-phys-and-leds.patch new file mode 100644 index 00000000000..0bdc6c9a15d --- /dev/null +++ b/target/linux/mediatek/patches-6.12/184-arm64-dts-mediatek-mt7988a-bpi-r4-configure-switch-phys-and-leds.patch @@ -0,0 +1,113 @@ +From patchwork Sun May 11 14:26:54 2025 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Frank Wunderlich +X-Patchwork-Id: 14084132 +From: Frank Wunderlich +To: Andrew Lunn , + Vladimir Oltean , + "David S. Miller" , + Eric Dumazet , + Jakub Kicinski , + Paolo Abeni , + Rob Herring , + Krzysztof Kozlowski , + Conor Dooley , + Matthias Brugger , + AngeloGioacchino Del Regno +Subject: [PATCH v1 14/14] arm64: dts: mediatek: mt7988a-bpi-r4: configure + switch phys and leds +Date: Sun, 11 May 2025 16:26:54 +0200 +Message-ID: <20250511142655.11007-5-frank-w@public-files.de> +X-Mailer: git-send-email 2.43.0 +In-Reply-To: <20250511142655.11007-1-frank-w@public-files.de> +References: <20250511142655.11007-1-frank-w@public-files.de> +MIME-Version: 1.0 +X-BeenThere: linux-mediatek@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Cc: devicetree@vger.kernel.org, Landen Chao , + =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , + netdev@vger.kernel.org, Sean Wang , + Daniel Golle , linux-kernel@vger.kernel.org, + DENG Qingfang , linux-mediatek@lists.infradead.org, + Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, + Felix Fietkau +Sender: "Linux-mediatek" +Errors-To: + linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org + +Assign pinctrl to switch phys and leds. + +Signed-off-by: Daniel Golle +Signed-off-by: Frank Wunderlich +--- + .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 40 +++++++++++++++++++ + 1 file changed, 40 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi +@@ -126,6 +126,54 @@ + phy-mode = "usxgmii"; + }; + ++&gsw_phy0 { ++ pinctrl-names = "gbe-led"; ++ label = "wan"; ++ pinctrl-0 = <&gbe0_led0_pins>; ++}; ++ ++&gsw_phy0_led0 { ++ status = "okay"; ++ function = LED_FUNCTION_WAN; ++ color = ; ++}; ++ ++&gsw_phy1 { ++ pinctrl-names = "gbe-led"; ++ label = "lan1"; ++ pinctrl-0 = <&gbe1_led0_pins>; ++}; ++ ++&gsw_phy1_led0 { ++ status = "okay"; ++ function = LED_FUNCTION_LAN; ++ color = ; ++}; ++ ++&gsw_phy2 { ++ pinctrl-names = "gbe-led"; ++ label = "lan2"; ++ pinctrl-0 = <&gbe2_led0_pins>; ++}; ++ ++&gsw_phy2_led0 { ++ status = "okay"; ++ function = LED_FUNCTION_LAN; ++ color = ; ++}; ++ ++&gsw_phy3 { ++ pinctrl-names = "gbe-led"; ++ label = "lan3"; ++ pinctrl-0 = <&gbe3_led0_pins>; ++}; ++ ++&gsw_phy3_led0 { ++ status = "okay"; ++ function = LED_FUNCTION_LAN; ++ color = ; ++}; ++ + &i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; diff --git a/target/linux/mediatek/patches-6.12/187-arm64-dts-mt7988a-add-serial1-and-serial2-aliases.patch b/target/linux/mediatek/patches-6.12/187-arm64-dts-mt7988a-add-serial1-and-serial2-aliases.patch new file mode 100644 index 00000000000..efa2121812a --- /dev/null +++ b/target/linux/mediatek/patches-6.12/187-arm64-dts-mt7988a-add-serial1-and-serial2-aliases.patch @@ -0,0 +1,33 @@ +From 109a9c8409f85d777f8ffa3fe145498a1fec0f1e Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Thu, 8 May 2025 04:03:58 +0100 +Subject: [PATCH] arm64: dts: mt7988a: add serial1 and serial2 aliases + +Add aliases serial1 and serial2, so boards can make use of the +auxilary UARTs of the MediaTek MT7988 SoC. + +Signed-off-by: Daniel Golle +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -297,7 +297,7 @@ + status = "disabled"; + }; + +- serial@11000100 { ++ serial1: serial@11000100 { + compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; + reg = <0 0x11000100 0 0x100>; + interrupts = ; +@@ -308,7 +308,7 @@ + status = "disabled"; + }; + +- serial@11000200 { ++ serial2: serial@11000200 { + compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; + reg = <0 0x11000200 0 0x100>; + interrupts = ; diff --git a/target/linux/mediatek/patches-6.12/188-arm64-dts-mediatek-add-MT7988A-reference-board-devic.patch b/target/linux/mediatek/patches-6.12/188-arm64-dts-mediatek-add-MT7988A-reference-board-devic.patch new file mode 100644 index 00000000000..7641c367111 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/188-arm64-dts-mediatek-add-MT7988A-reference-board-devic.patch @@ -0,0 +1,1430 @@ +From bb72bb160130c35fa4b7dedd0f881085f0af1313 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Wed, 22 Feb 2023 19:15:49 +0000 +Subject: [PATCH 31/32] dts: arm64: mediatek: add MT7988A reference board + device tree + +Complete device tree include for the MediaTek MT7988A SoC and make use +of it by adding the device tree of the MediaTek MT7988A Reference Board +as well as overlays for various options regarding the connected +network interfaces and storage devices present. + +Available options for GMAC1 (eth0): + * internal 4-port 1GE switch + +Available options for GMAC2 (eth1): + * internal 2.5G PHY + * external MaxLinear 2.5G PHY + * external Aquantia AQR113C PHY + * SFP+ cage + +Available options for GMAC3 (eth2): + * external MaxLinear 2.5G PHY + * external Aquantia AQR113C PHY + * SFP+ cage + +Available storage options: + * eMMC + * SNFI (ECC-less SPI-NAND with BCH done in SoC) + * SPI-NAND (with ECC done by the flash die) + * SPI-NOR + * SD card + +Signed-off-by: Sam Shih +Signed-off-by: Daniel Golle +--- a/arch/arm64/boot/dts/mediatek/Makefile ++++ b/arch/arm64/boot/dts/mediatek/Makefile +@@ -24,6 +24,19 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-b + dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-2g5.dtb + dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-emmc.dtbo + dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-sd.dtbo ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb.dtb ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-emmc.dtbo ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-eth1-aqr.dtbo ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-eth1-i2p5g-phy.dtbo ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-eth1-mxl.dtbo ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-eth1-sfp.dtbo ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-eth2-aqr.dtbo ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-eth2-mxl.dtbo ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-eth2-sfp.dtbo ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-sd.dtbo ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-snfi-nand.dtbo ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-spim-nand.dtbo ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-spim-nor.dtbo + dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb + dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb + dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso +@@ -0,0 +1,33 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2021 MediaTek Inc. ++ * Author: Frank Wunderlich ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; ++ ++ fragment@0 { ++ target = <&mmc0>; ++ __overlay__ { ++ pinctrl-names = "default", "state_uhs"; ++ pinctrl-0 = <&mmc0_pins_emmc_51>; ++ pinctrl-1 = <&mmc0_pins_emmc_51>; ++ bus-width = <8>; ++ max-frequency = <200000000>; ++ cap-mmc-highspeed; ++ mmc-hs200-1_8v; ++ mmc-hs400-1_8v; ++ hs400-ds-delay = <0x12814>; ++ vqmmc-supply = <®_1p8v>; ++ vmmc-supply = <®_3p3v>; ++ non-removable; ++ no-sd; ++ no-sdio; ++ status = "okay"; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso +@@ -0,0 +1,41 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2022 MediaTek Inc. ++ * Author: Sam.Shih ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++#include ++ ++/ { ++ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; ++ ++ fragment@0 { ++ target = <&mdio_bus>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ /* external Aquantia AQR113C */ ++ phy0: ethernet-phy@0 { ++ reg = <0>; ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ reset-gpios = <&pio 72 GPIO_ACTIVE_LOW>; ++ reset-assert-us = <100000>; ++ reset-deassert-us = <221000>; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gmac1>; ++ __overlay__ { ++ phy-mode = "usxgmii"; ++ phy-connection-type = "usxgmii"; ++ phy = <&phy0>; ++ status = "okay"; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso +@@ -0,0 +1,30 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2022 MediaTek Inc. ++ * Author: Sam.Shih ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; ++ ++ fragment@0 { ++ target = <&gmac1>; ++ __overlay__ { ++ phy-mode = "internal"; ++ phy-connection-type = "internal"; ++ phy = <&int_2p5g_phy>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&int_2p5g_phy>; ++ __overlay__ { ++ pinctrl-names = "i2p5gbe-led"; ++ pinctrl-0 = <&i2p5gbe_led0_pins>; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso +@@ -0,0 +1,39 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2022 MediaTek Inc. ++ * Author: Sam.Shih ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++#include ++ ++/ { ++ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; ++ ++ fragment@0 { ++ target = <&mdio_bus>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ /* external Maxlinear GPY211C */ ++ phy13: ethernet-phy@13 { ++ reg = <13>; ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ phy-mode = "2500base-x"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gmac1>; ++ __overlay__ { ++ phy-mode = "2500base-x"; ++ phy-connection-type = "2500base-x"; ++ phy = <&phy13>; ++ status = "okay"; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso +@@ -0,0 +1,47 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2022 MediaTek Inc. ++ * Author: Sam.Shih ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++#include ++ ++/ { ++ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; ++ ++ fragment@0 { ++ target = <&i2c2>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ sfp_esp1: sfp@1 { ++ compatible = "sff,sfp"; ++ i2c-bus = <&i2c2>; ++ mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>; ++ los-gpios = <&pio 81 GPIO_ACTIVE_HIGH>; ++ tx-disable-gpios = <&pio 36 GPIO_ACTIVE_HIGH>; ++ maximum-power-milliwatt = <3000>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&gmac1>; ++ __overlay__ { ++ phy-mode = "10gbase-r"; ++ managed = "in-band-status"; ++ sfp = <&sfp_esp1>; ++ status = "okay"; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso +@@ -0,0 +1,41 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2022 MediaTek Inc. ++ * Author: Sam.Shih ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++#include ++ ++/ { ++ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; ++ ++ fragment@0 { ++ target = <&mdio_bus>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ /* external Aquantia AQR113C */ ++ phy8: ethernet-phy@8 { ++ reg = <8>; ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ reset-gpios = <&pio 71 GPIO_ACTIVE_LOW>; ++ reset-assert-us = <100000>; ++ reset-deassert-us = <221000>; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gmac2>; ++ __overlay__ { ++ phy-mode = "usxgmii"; ++ phy-connection-type = "usxgmii"; ++ phy = <&phy8>; ++ status = "okay"; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso +@@ -0,0 +1,39 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2022 MediaTek Inc. ++ * Author: Sam.Shih ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++#include ++ ++/ { ++ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; ++ ++ fragment@0 { ++ target = <&mdio_bus>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ /* external Maxlinear GPY211C */ ++ phy5: ethernet-phy@5 { ++ reg = <5>; ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ phy-mode = "2500base-x"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gmac2>; ++ __overlay__ { ++ phy-mode = "2500base-x"; ++ phy-connection-type = "2500base-x"; ++ phy = <&phy5>; ++ status = "okay"; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso +@@ -0,0 +1,47 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2022 MediaTek Inc. ++ * Author: Sam.Shih ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++#include ++ ++/ { ++ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; ++ ++ fragment@0 { ++ target = <&i2c1>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ sfp_esp0: sfp@0 { ++ compatible = "sff,sfp"; ++ i2c-bus = <&i2c1>; ++ mod-def0-gpios = <&pio 35 GPIO_ACTIVE_LOW>; ++ los-gpios = <&pio 33 GPIO_ACTIVE_HIGH>; ++ tx-disable-gpios = <&pio 29 GPIO_ACTIVE_HIGH>; ++ maximum-power-milliwatt = <3000>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&gmac2>; ++ __overlay__ { ++ phy-mode = "10gbase-r"; ++ managed = "in-band-status"; ++ sfp = <&sfp_esp0>; ++ status = "okay"; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso +@@ -0,0 +1,31 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2023 MediaTek Inc. ++ * Author: Frank Wunderlich ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++#include ++ ++/ { ++ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; ++ ++ fragment@1 { ++ target-path = <&mmc0>; ++ __overlay__ { ++ pinctrl-names = "default", "state_uhs"; ++ pinctrl-0 = <&mmc0_pins_sdcard>; ++ pinctrl-1 = <&mmc0_pins_sdcard>; ++ cd-gpios = <&pio 69 GPIO_ACTIVE_LOW>; ++ bus-width = <4>; ++ max-frequency = <52000000>; ++ cap-sd-highspeed; ++ vmmc-supply = <®_3p3v>; ++ vqmmc-supply = <®_3p3v>; ++ no-mmc; ++ status = "okay"; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso +@@ -0,0 +1,70 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2022 MediaTek Inc. ++ * Author: Sam.Shih ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; ++ ++ fragment@0 { ++ target = <&snand>; ++ __overlay__ { ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ flash@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <52000000>; ++ spi-tx-bus-width = <4>; ++ spi-rx-bus-width = <4>; ++ mediatek,nmbm; ++ mediatek,bmt-max-ratio = <1>; ++ mediatek,bmt-max-reserved-blocks = <64>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "BL2"; ++ reg = <0x00000 0x0100000>; ++ read-only; ++ }; ++ ++ partition@100000 { ++ label = "u-boot-env"; ++ reg = <0x0100000 0x0080000>; ++ }; ++ ++ partition@180000 { ++ label = "Factory"; ++ reg = <0x180000 0x0400000>; ++ }; ++ ++ partition@580000 { ++ label = "FIP"; ++ reg = <0x580000 0x0200000>; ++ }; ++ ++ partition@780000 { ++ label = "ubi"; ++ reg = <0x780000 0x7080000>; ++ }; ++ }; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&bch>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand-factory.dtso +@@ -0,0 +1,87 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; ++ ++ fragment@0 { ++ target = <&ubi_part>; ++ ++ __overlay__ { ++ volumes { ++ ubi_factory: ubi-volume-factory { ++ volname = "factory"; ++ ++ nvmem-layout { ++ compatible = "fixed-layout"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ eeprom_wmac: eeprom@0 { ++ reg = <0x0 0x1e00>; ++ }; ++ ++ gmac2_mac: eeprom@fffee { ++ reg = <0xfffee 0x6>; ++ }; ++ ++ gmac1_mac: eeprom@ffff4 { ++ reg = <0xffff4 0x6>; ++ }; ++ ++ gmac0_mac: eeprom@ffffa { ++ reg = <0xffffa 0x6>; ++ }; ++ }; ++ }; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pcie0>; ++ __overlay__ { ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ pcie@0,0 { ++ reg = <0x0000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ wifi@0,0 { ++ compatible = "mediatek,mt76"; ++ reg = <0x0000 0 0 0 0>; ++ nvmem-cell-names = "eeprom"; ++ nvmem-cells = <&eeprom_wmac>; ++ }; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&gmac0>; ++ __overlay__ { ++ nvmem-cell-names = "mac-address"; ++ nvmem-cells = <&gmac0_mac>; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&gmac1>; ++ __overlay__ { ++ nvmem-cell-names = "mac-address"; ++ nvmem-cells = <&gmac1_mac>; ++ }; ++ }; ++ ++ fragment@4 { ++ target = <&gmac2>; ++ __overlay__ { ++ nvmem-cell-names = "mac-address"; ++ nvmem-cells = <&gmac2_mac>; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso +@@ -0,0 +1,66 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2022 MediaTek Inc. ++ * Author: Sam.Shih ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; ++ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_flash_pins>; ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ flash@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <52000000>; ++ spi-tx-bus-width = <4>; ++ spi-rx-bus-width = <4>; ++ mediatek,nmbm; ++ mediatek,bmt-max-ratio = <1>; ++ mediatek,bmt-max-reserved-blocks = <64>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "BL2"; ++ reg = <0x00000 0x0100000>; ++ read-only; ++ }; ++ ++ partition@100000 { ++ label = "u-boot-env"; ++ reg = <0x0100000 0x0080000>; ++ }; ++ ++ partition@180000 { ++ label = "Factory"; ++ reg = <0x180000 0x0400000>; ++ }; ++ ++ partition@580000 { ++ label = "FIP"; ++ reg = <0x580000 0x0200000>; ++ }; ++ ++ partition@780000 { ++ label = "ubi"; ++ reg = <0x780000 0x7080000>; ++ }; ++ }; ++ }; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nor.dtso +@@ -0,0 +1,61 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2022 MediaTek Inc. ++ * Author: Sam.Shih ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; ++ ++ fragment@0 { ++ target = <&spi2>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi2_flash_pins>; ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ flash@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "jedec,spi-nor"; ++ spi-cal-enable; ++ spi-cal-mode = "read-data"; ++ spi-cal-datalen = <7>; ++ spi-cal-data = /bits/ 8 < ++ 0x53 0x46 0x5F 0x42 0x4F 0x4F 0x54>; /* SF_BOOT */ ++ spi-cal-addrlen = <1>; ++ spi-cal-addr = /bits/ 32 <0x0>; ++ reg = <0>; ++ spi-max-frequency = <52000000>; ++ spi-tx-bus-width = <4>; ++ spi-rx-bus-width = <4>; ++ ++ partition@0 { ++ label = "BL2"; ++ reg = <0x0 0x40000>; ++ }; ++ partition@40000 { ++ label = "u-boot-env"; ++ reg = <0x40000 0x10000>; ++ }; ++ partition@50000 { ++ label = "Factory"; ++ reg = <0x50000 0x200000>; ++ }; ++ partition@250000 { ++ label = "FIP"; ++ reg = <0x250000 0x80000>; ++ }; ++ partition@2D0000 { ++ label = "firmware"; ++ reg = <0x2d0000 0x1d30000>; ++ }; ++ }; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts +@@ -0,0 +1,470 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2022 MediaTek Inc. ++ * Author: Sam.Shih ++ */ ++ ++/dts-v1/; ++#include ++#include ++#include ++ ++#include "mt7988a.dtsi" ++ ++/ { ++ model = "MediaTek MT7988A Reference Board"; ++ compatible = "mediatek,mt7988a-rfb", ++ "mediatek,mt7988"; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n1 loglevel=8 \ ++ earlycon=uart8250,mmio32,0x11000000 \ ++ pci=pcie_bus_perf"; ++ }; ++ ++ memory { ++ reg = <0 0x40000000 0 0x40000000>; ++ }; ++ ++ reg_1p8v: regulator-1p8v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-1.8V"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ reg_3p3v: regulator-3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-3.3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++}; ++ ++ð { ++ pinctrl-0 = <&mdio0_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&gmac0 { ++ status = "okay"; ++}; ++ ++&cpu0 { ++ proc-supply = <&rt5190_buck3>; ++}; ++ ++&cpu1 { ++ proc-supply = <&rt5190_buck3>; ++}; ++ ++&cpu2 { ++ proc-supply = <&rt5190_buck3>; ++}; ++ ++&cpu3 { ++ proc-supply = <&rt5190_buck3>; ++}; ++ ++&cci { ++ proc-supply = <&rt5190_buck3>; ++}; ++ ++ð { ++ status = "okay"; ++}; ++ ++&switch { ++ status = "okay"; ++}; ++ ++&gsw_phy0 { ++ pinctrl-names = "gbe-led"; ++ pinctrl-0 = <&gbe0_led0_pins>; ++}; ++ ++&gsw_phy0_led0 { ++ status = "okay"; ++ function = LED_FUNCTION_LAN; ++ color = ; ++}; ++ ++&gsw_port0 { ++ label = "lan0"; ++}; ++ ++&gsw_phy1 { ++ pinctrl-names = "gbe-led"; ++ pinctrl-0 = <&gbe1_led0_pins>; ++}; ++ ++&gsw_phy1_led0 { ++ status = "okay"; ++ function = LED_FUNCTION_LAN; ++ color = ; ++}; ++ ++&gsw_port1 { ++ label = "lan1"; ++}; ++ ++&gsw_phy2 { ++ pinctrl-names = "gbe-led"; ++ pinctrl-0 = <&gbe2_led0_pins>; ++}; ++ ++&gsw_phy2_led0 { ++ status = "okay"; ++ function = LED_FUNCTION_LAN; ++ color = ; ++}; ++ ++&gsw_port2 { ++ label = "lan2"; ++}; ++ ++&gsw_phy3 { ++ pinctrl-names = "gbe-led"; ++ pinctrl-0 = <&gbe3_led0_pins>; ++}; ++ ++&gsw_phy3_led0 { ++ status = "okay"; ++ function = LED_FUNCTION_LAN; ++ color = ; ++}; ++ ++&gsw_port3 { ++ label = "lan3"; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++ status = "okay"; ++ ++ rt5190a_64: rt5190a@64 { ++ compatible = "richtek,rt5190a"; ++ reg = <0x64>; ++ /*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/ ++ vin2-supply = <&rt5190_buck1>; ++ vin3-supply = <&rt5190_buck1>; ++ vin4-supply = <&rt5190_buck1>; ++ ++ regulators { ++ rt5190_buck1: buck1 { ++ regulator-name = "rt5190a-buck1"; ++ regulator-min-microvolt = <5090000>; ++ regulator-max-microvolt = <5090000>; ++ regulator-allowed-modes = ++ ; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ buck2 { ++ regulator-name = "vcore"; ++ regulator-min-microvolt = <600000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ rt5190_buck3: buck3 { ++ regulator-name = "vproc"; ++ regulator-min-microvolt = <600000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-boot-on; ++ }; ++ buck4 { ++ regulator-name = "rt5190a-buck4"; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <850000>; ++ regulator-allowed-modes = ++ ; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ldo { ++ regulator-name = "rt5190a-ldo"; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ }; ++ }; ++}; ++ ++&pcie0 { ++ status = "okay"; ++}; ++ ++&pcie1 { ++ status = "okay"; ++}; ++ ++&pcie2 { ++ status = "disabled"; ++}; ++ ++&pcie3 { ++ status = "okay"; ++}; ++ ++&pio { ++ mdio0_pins: mdio0-pins { ++ mux { ++ function = "eth"; ++ groups = "mdc_mdio0"; ++ }; ++ ++ conf { ++ groups = "mdc_mdio0"; ++ drive-strength = ; ++ }; ++ }; ++ ++ gbe0_led0_pins: gbe0-led0-pins { ++ mux { ++ function = "led"; ++ groups = "gbe0_led0"; ++ }; ++ }; ++ ++ gbe1_led0_pins: gbe1-led0-pins { ++ mux { ++ function = "led"; ++ groups = "gbe1_led0"; ++ }; ++ }; ++ ++ gbe2_led0_pins: gbe2-led0-pins { ++ mux { ++ function = "led"; ++ groups = "gbe2_led0"; ++ }; ++ }; ++ ++ gbe3_led0_pins: gbe3-led0-pins { ++ mux { ++ function = "led"; ++ groups = "gbe3_led0"; ++ }; ++ }; ++ ++ gbe0_led1_pins: gbe0-led1-pins { ++ mux { ++ function = "led"; ++ groups = "gbe0_led1"; ++ }; ++ }; ++ ++ gbe1_led1_pins: gbe1-led1-pins { ++ mux { ++ function = "led"; ++ groups = "gbe1_led1"; ++ }; ++ }; ++ ++ gbe2_led1_pins: gbe2-led1-pins { ++ mux { ++ function = "led"; ++ groups = "gbe2_led1"; ++ }; ++ }; ++ ++ gbe3_led1_pins: gbe3-led1-pins { ++ mux { ++ function = "led"; ++ groups = "gbe3_led1"; ++ }; ++ }; ++ ++ i2c0_pins: i2c0-g0-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c0_1"; ++ }; ++ }; ++ ++ i2c1_pins: i2c1-g0-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c1_0"; ++ }; ++ }; ++ ++ i2c1_sfp_pins: i2c1-sfp-g0-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c1_sfp"; ++ }; ++ }; ++ ++ i2c2_0_pins: i2c2-g0-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c2_0"; ++ }; ++ }; ++ ++ i2c2_1_pins: i2c2-g1-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c2_1"; ++ }; ++ }; ++ ++ i2p5gbe_led0_pins: 2p5gbe-led0-pins { ++ mux { ++ function = "led"; ++ groups = "2p5gbe_led0"; ++ }; ++ }; ++ ++ i2p5gbe_led1_pins: 2p5gbe-led1-pins { ++ mux { ++ function = "led"; ++ groups = "2p5gbe_led1"; ++ }; ++ }; ++ ++ mmc0_pins_emmc_51: mmc0-emmc-51-pins { ++ mux { ++ function = "flash"; ++ groups = "emmc_51"; ++ }; ++ }; ++ ++ mmc0_pins_sdcard: mmc0-sdcard-pins { ++ mux { ++ function = "flash"; ++ groups = "sdcard"; ++ }; ++ }; ++ ++ spi0_pins: spi0-pins { ++ mux { ++ function = "spi"; ++ groups = "spi0"; ++ }; ++ }; ++ ++ spi0_flash_pins: spi0-flash-pins { ++ mux { ++ function = "spi"; ++ groups = "spi0", "spi0_wp_hold"; ++ }; ++ }; ++ ++ spi2_pins: spi2-pins { ++ mux { ++ function = "spi"; ++ groups = "spi2"; ++ }; ++ }; ++ ++ spi2_flash_pins: spi2-flash-pins { ++ mux { ++ function = "spi"; ++ groups = "spi2", "spi2_wp_hold"; ++ }; ++ }; ++ ++ uart0_pins: uart0-pins { ++ mux { ++ function = "uart"; ++ groups = "uart0"; ++ }; ++ }; ++ ++ uart1_0_pins: uart1-0-pins { ++ mux { ++ function = "uart"; ++ groups = "uart1_0"; ++ }; ++ }; ++ ++ uart1_1_pins: uart1-1-pins { ++ mux { ++ function = "uart"; ++ groups = "uart1_1"; ++ }; ++ }; ++ ++ uart1_2_pins: uart1-2-pins { ++ mux { ++ function = "uart"; ++ groups = "uart1_2"; ++ }; ++ }; ++ ++ uart1_2_lite_pins: uart1-2-lite-pins { ++ mux { ++ function = "uart"; ++ groups = "uart1_2_lite"; ++ }; ++ }; ++ ++ uart2_pins: uart2-pins { ++ mux { ++ function = "uart"; ++ groups = "uart2"; ++ }; ++ }; ++ ++ uart2_0_pins: uart2-0-pins { ++ mux { ++ function = "uart"; ++ groups = "uart2_0"; ++ }; ++ }; ++ ++ uart2_1_pins: uart2-1-pins { ++ mux { ++ function = "uart"; ++ groups = "uart2_1"; ++ }; ++ }; ++ ++ uart2_2_pins: uart2-2-pins { ++ mux { ++ function = "uart"; ++ groups = "uart2_2"; ++ }; ++ }; ++ ++ uart2_3_pins: uart2-3-pins { ++ mux { ++ function = "uart"; ++ groups = "uart2_3"; ++ }; ++ }; ++}; ++ ++&ssusb0 { ++ status = "okay"; ++}; ++ ++&ssusb1 { ++ status = "okay"; ++}; ++ ++&tphy { ++ status = "okay"; ++}; ++ ++&serial0 { ++ status = "okay"; ++}; ++ ++&watchdog { ++ status = "okay"; ++}; ++ ++&xsphy { ++ status = "okay"; ++}; +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -193,7 +193,7 @@ + }; + + pio: pinctrl@1001f000 { +- compatible = "mediatek,mt7988-pinctrl"; ++ compatible = "mediatek,mt7988-pinctrl", "syscon"; + reg = <0 0x1001f000 0 0x1000>, + <0 0x11c10000 0 0x1000>, + <0 0x11d00000 0 0x1000>, +@@ -212,6 +212,13 @@ + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + ++ snfi_pins: snfi-pins { ++ mux { ++ function = "flash"; ++ groups = "snfi"; ++ }; ++ }; ++ + pcie0_pins: pcie0-pins { + mux { + function = "pcie"; +@@ -278,6 +285,60 @@ + status = "disabled"; + }; + ++ sgmiisys0: syscon@10060000 { ++ compatible = "mediatek,mt7988-sgmiisys", ++ "mediatek,mt7988-sgmiisys0", ++ "syscon", ++ "simple-mfd"; ++ reg = <0 0x10060000 0 0x1000>; ++ resets = <&watchdog 1>; ++ #clock-cells = <1>; ++ ++ sgmiipcs0: pcs { ++ compatible = "mediatek,mt7988-sgmii"; ++ clocks = <&topckgen CLK_TOP_SGM_0_SEL>, ++ <&sgmiisys0 CLK_SGM0_TX_EN>, ++ <&sgmiisys0 CLK_SGM0_RX_EN>; ++ clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx"; ++ #pcs-cells = <0>; ++ }; ++ }; ++ ++ sgmiisys1: syscon@10070000 { ++ compatible = "mediatek,mt7988-sgmiisys", ++ "mediatek,mt7988-sgmiisys1", ++ "syscon", ++ "simple-mfd"; ++ reg = <0 0x10070000 0 0x1000>; ++ resets = <&watchdog 2>; ++ #clock-cells = <1>; ++ ++ sgmiipcs1: pcs { ++ compatible = "mediatek,mt7988-sgmii"; ++ clocks = <&topckgen CLK_TOP_SGM_1_SEL>, ++ <&sgmiisys1 CLK_SGM1_TX_EN>, ++ <&sgmiisys1 CLK_SGM1_RX_EN>; ++ clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx"; ++ #pcs-cells = <0>; ++ }; ++ }; ++ ++ usxgmiisys0: pcs@10080000 { ++ compatible = "mediatek,mt7988-usxgmiisys"; ++ reg = <0 0x10080000 0 0x1000>; ++ resets = <&watchdog 12>; ++ clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>; ++ #pcs-cells = <0>; ++ }; ++ ++ usxgmiisys1: pcs@10081000 { ++ compatible = "mediatek,mt7988-usxgmiisys"; ++ reg = <0 0x10081000 0 0x1000>; ++ resets = <&watchdog 13>; ++ clocks = <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>; ++ #pcs-cells = <0>; ++ }; ++ + mcusys: mcusys@100e0000 { + compatible = "mediatek,mt7988-mcusys", "syscon"; + reg = <0 0x100e0000 0 0x1000>; +@@ -319,6 +380,32 @@ + status = "disabled"; + }; + ++ snand: spi@11001000 { ++ compatible = "mediatek,mt7986-snand"; ++ reg = <0 0x11001000 0 0x1000>; ++ interrupts = ; ++ clocks = <&infracfg CLK_INFRA_SPINFI>, ++ <&infracfg CLK_INFRA_NFI>, ++ <&infracfg CLK_INFRA_66M_NFI_HCK>; ++ clock-names = "pad_clk", "nfi_clk", "nfi_hclk"; ++ nand-ecc-engine = <&bch>; ++ mediatek,quad-spi; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&snfi_pins>; ++ status = "disabled"; ++ }; ++ ++ bch: ecc@11002000 { ++ compatible = "mediatek,mt7686-ecc"; ++ reg = <0 0x11002000 0 0x1000>; ++ interrupts = ; ++ clocks = <&infracfg CLK_INFRA_NFI>; ++ clock-names = "nfiecc_clk"; ++ status = "disabled"; ++ }; ++ + i2c0: i2c@11003000 { + compatible = "mediatek,mt7981-i2c"; + reg = <0 0x11003000 0 0x1000>, +@@ -425,7 +512,7 @@ + <0 0x0f0f0018 0 0x20>; + }; + +- usb@11190000 { ++ ssusb0: usb@11190000 { + compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11190000 0 0x2e00>, + <0 0x11193e00 0 0x0100>; +@@ -459,6 +546,35 @@ + status = "disabled"; + }; + ++ afe: audio-controller@11210000 { ++ compatible = "mediatek,mt79xx-audio"; ++ reg = <0 0x11210000 0 0x9000>; ++ interrupts = ; ++ clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>, ++ <&infracfg CLK_INFRA_AUD_26M>, ++ <&infracfg CLK_INFRA_AUD_L>, ++ <&infracfg CLK_INFRA_AUD_AUD>, ++ <&infracfg CLK_INFRA_AUD_EG2>, ++ <&topckgen CLK_TOP_AUD_SEL>, ++ <&topckgen CLK_TOP_AUD_I2S_M>; ++ clock-names = "aud_bus_ck", ++ "aud_26m_ck", ++ "aud_l_ck", ++ "aud_aud_ck", ++ "aud_eg2_ck", ++ "aud_sel", ++ "aud_i2s_m"; ++ assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>, ++ <&topckgen CLK_TOP_A1SYS_SEL>, ++ <&topckgen CLK_TOP_AUD_L_SEL>, ++ <&topckgen CLK_TOP_A_TUNER_SEL>; ++ assigned-clock-parents = <&apmixedsys CLK_APMIXED_APLL2>, ++ <&topckgen CLK_TOP_APLL2_D4>, ++ <&apmixedsys CLK_APMIXED_APLL2>, ++ <&topckgen CLK_TOP_APLL2_D4>; ++ status = "disabled"; ++ }; ++ + mmc0: mmc@11230000 { + compatible = "mediatek,mt7988-mmc"; + reg = <0 0x11230000 0 0x1000>, +@@ -721,6 +837,10 @@ + #address-cells = <1>; + #size-cells = <1>; + ++ cpufreq_calibration: calib@278 { ++ reg = <0x278 0x1>; ++ }; ++ + lvts_calibration: calib@918 { + reg = <0x918 0x28>; + }; +@@ -984,12 +1104,16 @@ + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; ++ pcs-handle = <&sgmiipcs1>, <&usxgmiisys1>; ++ phys = <&xfi_tphy1>; + status = "disabled"; + }; + + gmac2: mac@2 { + compatible = "mediatek,eth-mac"; + reg = <2>; ++ pcs-handle = <&sgmiipcs0>, <&usxgmiisys0>; ++ phys = <&xfi_tphy0>; + status = "disabled"; + }; + +@@ -1002,9 +1126,37 @@ + reg = <15>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "internal"; ++ ++ leds { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ i2p5gbe_led0: i2p5gbe-led0@0 { ++ reg = <0>; ++ function = LED_FUNCTION_LAN; ++ status = "disabled"; ++ }; ++ ++ i2p5gbe_led1: i2p5gbe-led1@1 { ++ reg = <1>; ++ function = LED_FUNCTION_LAN; ++ status = "disabled"; ++ }; ++ }; + }; + }; + }; ++ ++ crypto: crypto@15600000 { ++ compatible = "inside-secure,safexcel-eip197b"; ++ reg = <0 0x15600000 0 0x180000>; ++ interrupts = , ++ , ++ , ++ ; ++ interrupt-names = "ring0", "ring1", "ring2", "ring3"; ++ status = "okay"; ++ }; + }; + + thermal-zones { diff --git a/target/linux/mediatek/patches-6.12/189-arm64-dts-mediatek-mt7988a-complete-bpi-r4.patch b/target/linux/mediatek/patches-6.12/189-arm64-dts-mediatek-mt7988a-complete-bpi-r4.patch new file mode 100644 index 00000000000..a2643ea0a30 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/189-arm64-dts-mediatek-mt7988a-complete-bpi-r4.patch @@ -0,0 +1,487 @@ +From f7fb27b62f0ef45f94f4ec33c608bfad1c7691b3 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Wed, 26 Jul 2023 14:56:28 +0100 +Subject: [PATCH 32/32] WIP: add BPi-R4 + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts +@@ -20,3 +20,16 @@ + pinctrl-names = "i2p5gbe-led"; + pinctrl-0 = <&i2p5gbe_led0_pins>; + }; ++ ++&gmac1 { ++ phy-mode = "internal"; ++ phy-connection-type = "internal"; ++ phy = <&int_2p5g_phy>; ++ openwrt,netdev-name = "lan4"; ++ status = "okay"; ++}; ++ ++&int_2p5g_phy { ++ pinctrl-names = "i2p5gbe-led"; ++ pinctrl-0 = <&i2p5gbe_led0_pins>; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso +@@ -0,0 +1,56 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2021 MediaTek Inc. ++ * Author: Frank Wunderlich ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; ++}; ++ ++&{/soc/mmc@11230000} { ++ pinctrl-names = "default", "state_uhs"; ++ pinctrl-0 = <&mmc0_pins_emmc_51>; ++ pinctrl-1 = <&mmc0_pins_emmc_51>; ++ bus-width = <8>; ++ max-frequency = <200000000>; ++ cap-mmc-highspeed; ++ mmc-hs200-1_8v; ++ mmc-hs400-1_8v; ++ hs400-ds-delay = <0x12814>; ++ vqmmc-supply = <®_1p8v>; ++ vmmc-supply = <®_3p3v>; ++ non-removable; ++ no-sd; ++ no-sdio; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ card@0 { ++ compatible = "mmc-card"; ++ reg = <0>; ++ ++ partitions { ++ compatible = "gpt-partitions"; ++ ++ block-partition-env { ++ partname = "ubootenv"; ++ nvmem-layout { ++ compatible = "u-boot,env-layout"; ++ }; ++ }; ++ ++ emmc_rootfs: block-partition-production { ++ partname = "production"; ++ }; ++ }; ++ }; ++}; ++ ++&{/chosen} { ++ rootdisk-emmc = <&emmc_rootfs>; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-rtc.dtso +@@ -0,0 +1,19 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2023 ++ * Author: Daniel Golle ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; ++ ++ fragment@0 { ++ target = <&pcf8563>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso +@@ -0,0 +1,54 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2023 MediaTek Inc. ++ * Author: Frank Wunderlich ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++#include ++ ++/ { ++ compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; ++}; ++ ++&{/soc/mmc@11230000} { ++ pinctrl-names = "default", "state_uhs"; ++ pinctrl-0 = <&mmc0_pins_sdcard>; ++ pinctrl-1 = <&mmc0_pins_sdcard>; ++ cd-gpios = <&pio 12 GPIO_ACTIVE_LOW>; ++ bus-width = <4>; ++ max-frequency = <52000000>; ++ cap-sd-highspeed; ++ vmmc-supply = <®_3p3v>; ++ vqmmc-supply = <®_3p3v>; ++ no-mmc; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ card@0 { ++ compatible = "mmc-card"; ++ reg = <0>; ++ ++ partitions { ++ compatible = "gpt-partitions"; ++ ++ block-partition-env { ++ partname = "ubootenv"; ++ nvmem-layout { ++ compatible = "u-boot,env-layout"; ++ }; ++ }; ++ ++ sd_rootfs: block-partition-production { ++ partname = "production"; ++ }; ++ }; ++ }; ++}; ++ ++&{/chosen} { ++ rootdisk-sd = <&sd_rootfs>; ++}; +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +@@ -35,3 +35,11 @@ + reg = <2>; + }; + }; ++ ++&gmac1 { ++ sfp = <&sfp2>; ++ managed = "in-band-status"; ++ phy-mode = "usxgmii"; ++ openwrt,netdev-name = "sfp-lan"; ++ status = "okay"; ++}; +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi +@@ -3,6 +3,8 @@ + /dts-v1/; + + #include ++#include ++#include + #include + + #include "mt7988a.dtsi" +@@ -10,6 +12,8 @@ + / { + chosen { + stdout-path = "serial0:115200n8"; ++ bootargs = "console=ttyS0,115200n1 loglevel=8 pci=pcie_bus_perf ubi.block=0,fit root=/dev/fit0"; ++ rootdisk-spim-nand = <&ubi_rootfs>; + }; + + fan: pwm-fan { +@@ -50,6 +54,141 @@ + rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>; + maximum-power-milliwatt = <3000>; + }; ++ ++ aliases { ++ ethernet0 = &gmac0; ++ ethernet1 = &gmac1; ++ ethernet2 = &gmac2; ++ serial0 = &serial0; ++ led-boot = &led_green; ++ led-failsafe = &led_green; ++ led-running = &led_green; ++ led-upgrade = &led_green; ++ }; ++ ++ memory { ++ reg = <0x00 0x40000000 0x00 0x10000000>; ++ }; ++ ++ /* SFP1 cage (WAN) */ ++ sfp1: sfp1 { ++ compatible = "sff,sfp"; ++ i2c-bus = <&i2c_sfp1>; ++ los-gpios = <&pio 54 GPIO_ACTIVE_HIGH>; ++ mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>; ++ tx-disable-gpios = <&pio 70 GPIO_ACTIVE_HIGH>; ++ tx-fault-gpios = <&pio 69 GPIO_ACTIVE_HIGH>; ++ rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>; ++ maximum-power-milliwatt = <3000>; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ ++ wps { ++ label = "WPS"; ++ linux,code = ; ++ gpios = <&pio 14 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ gpio-leds { ++ compatible = "gpio-leds"; ++ ++ led_green: led-green { ++ function = LED_FUNCTION_STATUS; ++ color = ; ++ gpios = <&pio 79 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; ++ }; ++ ++ led_blue: led-blue { ++ function = LED_FUNCTION_WPS; ++ color = ; ++ gpios = <&pio 63 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ }; ++ }; ++}; ++ ++ð { ++ status = "okay"; ++}; ++ ++&gmac0 { ++ status = "okay"; ++}; ++ ++&gmac2 { ++ sfp = <&sfp1>; ++ managed = "in-band-status"; ++ phy-mode = "usxgmii"; ++ openwrt,netdev-name = "sfp-wan"; ++ status = "okay"; ++}; ++ ++&switch { ++ status = "okay"; ++}; ++ ++&gsw_phy0 { ++ pinctrl-names = "gbe-led"; ++ pinctrl-0 = <&gbe0_led0_pins>; ++}; ++ ++&gsw_port0 { ++ label = "wan"; ++}; ++ ++&gsw_phy0_led0 { ++ status = "okay"; ++ function = LED_FUNCTION_WAN; ++ color = ; ++}; ++ ++&gsw_phy1 { ++ pinctrl-names = "gbe-led"; ++ pinctrl-0 = <&gbe1_led0_pins>; ++}; ++ ++&gsw_port1 { ++ label = "lan1"; ++}; ++ ++&gsw_phy1_led0 { ++ status = "okay"; ++ function = LED_FUNCTION_LAN; ++ color = ; ++}; ++ ++&gsw_phy2 { ++ pinctrl-names = "gbe-led"; ++ pinctrl-0 = <&gbe2_led0_pins>; ++}; ++ ++&gsw_port2 { ++ label = "lan2"; ++}; ++ ++&gsw_phy2_led0 { ++ status = "okay"; ++ function = LED_FUNCTION_LAN; ++ color = ; ++}; ++ ++&gsw_phy3 { ++ pinctrl-names = "gbe-led"; ++ pinctrl-0 = <&gbe3_led0_pins>; ++}; ++ ++&gsw_port3 { ++ label = "lan3"; ++}; ++ ++&gsw_phy3_led0 { ++ status = "okay"; ++ function = LED_FUNCTION_LAN; ++ color = ; + }; + + &cci { +@@ -174,6 +313,10 @@ + color = ; + }; + ++&cci { ++ proc-supply = <&rt5190_buck3>; ++}; ++ + &i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; +@@ -265,6 +408,14 @@ + #size-cells = <0>; + reg = <1>; + }; ++ ++ i2c_wifi: i2c@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <3>; ++ ++ status = "disabled"; ++ }; + }; + }; + +@@ -364,34 +515,6 @@ + }; + }; + +- gbe0_led1_pins: gbe0-led1-pins { +- mux { +- function = "led"; +- groups = "gbe0_led1"; +- }; +- }; +- +- gbe1_led1_pins: gbe1-led1-pins { +- mux { +- function = "led"; +- groups = "gbe1_led1"; +- }; +- }; +- +- gbe2_led1_pins: gbe2-led1-pins { +- mux { +- function = "led"; +- groups = "gbe2_led1"; +- }; +- }; +- +- gbe3_led1_pins: gbe3-led1-pins { +- mux { +- function = "led"; +- groups = "gbe3_led1"; +- }; +- }; +- + i2p5gbe_led0_pins: 2p5gbe-led0-pins { + mux { + function = "led"; +@@ -399,13 +522,6 @@ + }; + }; + +- i2p5gbe_led1_pins: 2p5gbe-led1-pins { +- mux { +- function = "led"; +- groups = "2p5gbe_led1"; +- }; +- }; +- + mmc0_pins_emmc_45: mmc0-emmc-45-pins { + mux { + function = "flash"; +@@ -427,40 +543,12 @@ + }; + }; + +- snfi_pins: snfi-pins { +- mux { +- function = "flash"; +- groups = "snfi"; +- }; +- }; +- +- spi0_pins: spi0-pins { +- mux { +- function = "spi"; +- groups = "spi0"; +- }; +- }; +- + spi0_flash_pins: spi0-flash-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; +- +- spi2_pins: spi2-pins { +- mux { +- function = "spi"; +- groups = "spi2"; +- }; +- }; +- +- spi2_flash_pins: spi2-flash-pins { +- mux { +- function = "spi"; +- groups = "spi2", "spi2_wp_hold"; +- }; +- }; + }; + + &pwm { +@@ -500,6 +588,32 @@ + reg = <0x0 0x200000>; + read-only; + }; ++ ++ partition@200000 { ++ label = "ubi"; ++ reg = <0x200000 0x7e00000>; ++ compatible = "linux,ubi"; ++ ++ volumes { ++ ubi-volume-ubootenv { ++ volname = "ubootenv"; ++ nvmem-layout { ++ compatible = "u-boot,env-redundant-bool-layout"; ++ }; ++ }; ++ ++ ubi-volume-ubootenv2 { ++ volname = "ubootenv2"; ++ nvmem-layout { ++ compatible = "u-boot,env-redundant-bool-layout"; ++ }; ++ }; ++ ++ ubi_rootfs: ubi-volume-fit { ++ volname = "fit"; ++ }; ++ }; ++ }; + }; + }; +