diff --git a/target/linux/qualcommax/patches-6.12/0055-v6.16-mtd-spinand-esmt-fix-id-code-for-F50D1G41LB.patch b/target/linux/qualcommax/patches-6.12/0055-v6.16-mtd-spinand-esmt-fix-id-code-for-F50D1G41LB.patch
new file mode 100644
index 00000000000..379b77f117e
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.12/0055-v6.16-mtd-spinand-esmt-fix-id-code-for-F50D1G41LB.patch
@@ -0,0 +1,35 @@
+From dd26402642a0899fde59ea6b0852fad3d799b4cc Mon Sep 17 00:00:00 2001
+From: George Moussalem <george.moussalem@outlook.com>
+Date: Thu, 15 May 2025 21:46:05 +0400
+Subject: mtd: spinand: esmt: fix id code for F50D1G41LB
+
+Upon detecting the ID for the ESMT F50D1G41LB chip, the fifth byte
+returned is always 0x00 instead of the expected JEDEC continuation code
+of 0x7f. This causes detection to fail:
+
+[    0.304399] spi-nand spi0.0: unknown raw ID c8117f7f00
+[    0.508943] spi-nand: probe of spi0.0 failed with error -524
+
+So let's revert back to the 4 byte ID code for this chip
+specifically.
+
+Fixes: 4bd14b2fd8a8 ("mtd: spinand: esmt: Extend IDs to 5 bytes")
+Signed-off-by: George Moussalem <george.moussalem@outlook.com>
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
+---
+ drivers/mtd/nand/spi/esmt.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+(limited to 'drivers/mtd/nand/spi/esmt.c')
+
+--- a/drivers/mtd/nand/spi/esmt.c
++++ b/drivers/mtd/nand/spi/esmt.c
+@@ -115,7 +115,7 @@ static const struct spinand_info esmt_c8
+ 		     SPINAND_ECCINFO(&f50l1g41lb_ooblayout, NULL)),
+ 	SPINAND_INFO("F50D1G41LB",
+ 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x11, 0x7f,
+-				0x7f, 0x7f),
++				0x7f),
+ 		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+ 		     NAND_ECCREQ(1, 512),
+ 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,