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generic: 6.1: replace ipq40xx MDIO patch with upstream version

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Replace ipq40xx MDIO patch with upstream version now that the driver
part got merged upstream.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
This commit is contained in:
Christian Marangi 2024-02-03 21:26:32 +01:00
parent 7e0a7bf21d
commit f0cdbfd7cc
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2 changed files with 6 additions and 47 deletions
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11
target/linux/generic/pending-6.1/713-02-net-mdio-ipq4019-add-support-for-clock-frequency-pro.patch → target/linux/generic/backport-6.1/720-v6.9-net-mdio-ipq4019-add-support-for-clock-frequency-pro.patch
View file

@ -1,8 +1,7 @@
From eacf1d2505dfecd3599d558cdade1a2da47fe06d Mon Sep 17 00:00:00 2001 From bdce82e960d1205d118662f575cec39379984e34 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com> From: Christian Marangi <ansuelsmth@gmail.com>
Date: Wed, 24 Jan 2024 18:52:33 +0100 Date: Wed, 31 Jan 2024 03:26:04 +0100
Subject: [PATCH 2/3] net: mdio: ipq4019: add support for clock-frequency Subject: [PATCH] net: mdio: ipq4019: add support for clock-frequency property
property
The IPQ4019 MDIO internally divide the clock feed by AHB based on the The IPQ4019 MDIO internally divide the clock feed by AHB based on the
MDIO_MODE reg. On reset or power up, the default value for the MDIO_MODE reg. On reset or power up, the default value for the
@ -44,6 +43,8 @@ Documentation of some BITs is skipped as they are marked as reserved and
their usage is not clear (RES 11:9 GENPHY 16:13 RES1 19:17) their usage is not clear (RES 11:9 GENPHY 16:13 RES1 19:17)
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
--- ---
drivers/net/mdio/mdio-ipq4019.c | 109 ++++++++++++++++++++++++++++++-- drivers/net/mdio/mdio-ipq4019.c | 109 ++++++++++++++++++++++++++++++--
1 file changed, 103 insertions(+), 6 deletions(-) 1 file changed, 103 insertions(+), 6 deletions(-)
@ -167,7 +168,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+ +
+ /* div is not set to the default value of /256 + /* div is not set to the default value of /256
+ * Probably someone changed that (bootloader, other drivers) + * Probably someone changed that (bootloader, other drivers)
+ * Keep this and doesn't overwrite it. + * Keep this and don't overwrite it.
+ */ + */
+ if (div != MDIO_MODE_DIV_256) { + if (div != MDIO_MODE_DIV_256) {
+ priv->mdc_rate = DIV_ROUND_UP(ahb_rate, div + 1); + priv->mdc_rate = DIV_ROUND_UP(ahb_rate, div + 1);

42
target/linux/generic/pending-6.1/713-01-dt-bindings-net-ipq4019-mdio-document-now-supported-.patch
View file

@ -1,42 +0,0 @@
From 85e2038891989e41bc62f6a4625fd5865da8a1a2 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Wed, 24 Jan 2024 19:17:02 +0100
Subject: [PATCH 1/3] dt-bindings: net: ipq4019-mdio: document now supported
clock-frequency
Document support for clock-frequency and add details on why this
property is needed and what values are supported.
From internal documentation, while other values are supported, the
correct function of the MDIO bus is not assured hence add only the
suggested supported values to the property enum.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
.../bindings/net/qcom,ipq4019-mdio.yaml | 15 +++++++++++++++
1 file changed, 15 insertions(+)
--- a/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml
+++ b/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml
@@ -38,6 +38,21 @@ properties:
MDIO clock source frequency fixed to 100MHZ, this clock should be specified
by the platform IPQ807x, IPQ60xx and IPQ50xx.
+ clock-frequency:
+ description:
+ The MDIO bus clock that must be output by the MDIO bus hardware, if
+ absent, the default hardware values are used.
+
+ MDC rate is feed by an external clock (fixed 100MHz) and is divider
+ internally. The default divider is /256 resulting in the default rate
+ applied of 390KHz.
+
+ To follow 802.3 standard that instruct up to 2.5MHz by default, if
+ this property is not declared and the divider is set to /256, by
+ default 1.5625Mhz is select.
+ enum: [ 390625, 781250, 1562500, 3125000, 6250000, 12500000 ]
+ default: 1562500
+
required:
- compatible
- reg