rockchip: Restore kernel files for v6.6
This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. For the original discussion see: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> Link: https://github.com/openwrt/openwrt/pull/18683 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Tianling Shen
Hauke Mehrtens
parent
23b5f3a90a
commit
eb974c3b3e
147 changed files with 33090 additions and 0 deletions
727
target/linux/rockchip/armv8/config-6.6
Normal file
727
target/linux/rockchip/armv8/config-6.6
Normal file
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@ -0,0 +1,727 @@
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CONFIG_64BIT=y
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CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
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CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
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CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y
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CONFIG_ARCH_DMA_ADDR_T_64BIT=y
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CONFIG_ARCH_FORCE_MAX_ORDER=10
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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CONFIG_ARCH_KEEP_MEMBLOCK=y
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CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
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CONFIG_ARCH_MMAP_RND_BITS=18
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CONFIG_ARCH_MMAP_RND_BITS_MAX=33
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CONFIG_ARCH_MMAP_RND_BITS_MIN=18
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CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
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CONFIG_ARCH_PROC_KCORE_TEXT=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_ARCH_SELECTS_KEXEC_FILE=y
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CONFIG_ARCH_SPARSEMEM_ENABLE=y
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CONFIG_ARCH_STACKWALK=y
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CONFIG_ARCH_SUSPEND_POSSIBLE=y
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CONFIG_ARCH_WANTS_NO_INSTR=y
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CONFIG_ARCH_WANTS_THP_SWAP=y
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CONFIG_ARC_EMAC_CORE=y
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CONFIG_ARM64=y
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CONFIG_ARM64_4K_PAGES=y
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CONFIG_ARM64_ERRATUM_1024718=y
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CONFIG_ARM64_ERRATUM_1165522=y
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CONFIG_ARM64_ERRATUM_1286807=y
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CONFIG_ARM64_ERRATUM_1319367=y
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CONFIG_ARM64_ERRATUM_1463225=y
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CONFIG_ARM64_ERRATUM_1530923=y
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CONFIG_ARM64_ERRATUM_2051678=y
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CONFIG_ARM64_ERRATUM_2054223=y
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CONFIG_ARM64_ERRATUM_2067961=y
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CONFIG_ARM64_ERRATUM_2077057=y
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CONFIG_ARM64_ERRATUM_2441007=y
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CONFIG_ARM64_ERRATUM_2441009=y
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CONFIG_ARM64_ERRATUM_2658417=y
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CONFIG_ARM64_ERRATUM_3117295=y
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CONFIG_ARM64_ERRATUM_819472=y
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CONFIG_ARM64_ERRATUM_824069=y
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CONFIG_ARM64_ERRATUM_826319=y
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CONFIG_ARM64_ERRATUM_827319=y
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CONFIG_ARM64_ERRATUM_832075=y
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CONFIG_ARM64_ERRATUM_843419=y
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CONFIG_ARM64_ERRATUM_858921=y
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CONFIG_ARM64_HW_AFDBM=y
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CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
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CONFIG_ARM64_PAGE_SHIFT=12
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CONFIG_ARM64_PA_BITS=48
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CONFIG_ARM64_PA_BITS_48=y
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CONFIG_ARM64_PTR_AUTH=y
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CONFIG_ARM64_PTR_AUTH_KERNEL=y
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CONFIG_ARM64_RAS_EXTN=y
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CONFIG_ARM64_SVE=y
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CONFIG_ARM64_TAGGED_ADDR_ABI=y
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CONFIG_ARM64_VA_BITS=48
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# CONFIG_ARM64_VA_BITS_39 is not set
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CONFIG_ARM64_VA_BITS_48=y
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CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
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CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
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CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
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CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD=y
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CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
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CONFIG_ARM_AMBA=y
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CONFIG_ARM_ARCH_TIMER=y
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CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
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CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
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CONFIG_ARM_GIC=y
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CONFIG_ARM_GIC_V2M=y
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CONFIG_ARM_GIC_V3=y
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CONFIG_ARM_GIC_V3_ITS=y
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CONFIG_ARM_GIC_V3_ITS_PCI=y
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CONFIG_ARM_MHU=y
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CONFIG_ARM_MHU_V2=y
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CONFIG_ARM_PSCI_CPUIDLE=y
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CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
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CONFIG_ARM_PSCI_FW=y
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# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set
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CONFIG_ARM_SCMI_CPUFREQ=y
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# CONFIG_ARM_SCMI_DEBUG_COUNTERS is not set
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CONFIG_ARM_SCMI_HAVE_SHMEM=y
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CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
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CONFIG_ARM_SCMI_POWER_CONTROL=y
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CONFIG_ARM_SCMI_POWER_DOMAIN=y
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CONFIG_ARM_SCMI_PROTOCOL=y
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# CONFIG_ARM_SCMI_RAW_MODE_SUPPORT is not set
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CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
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CONFIG_ARM_SCMI_TRANSPORT_SMC=y
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CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE=y
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CONFIG_ARM_SCPI_CPUFREQ=y
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CONFIG_ARM_SCPI_POWER_DOMAIN=y
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CONFIG_ARM_SCPI_PROTOCOL=y
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CONFIG_ARM_SMMU=y
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CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
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# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
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CONFIG_ARM_SMMU_V3=y
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# CONFIG_ARM_SMMU_V3_SVA is not set
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CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
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CONFIG_BACKLIGHT_CLASS_DEVICE=y
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CONFIG_BACKLIGHT_GPIO=y
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CONFIG_BACKLIGHT_PWM=y
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CONFIG_BLK_DEV_BSG=y
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CONFIG_BLK_DEV_BSGLIB=y
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CONFIG_BLK_DEV_BSG_COMMON=y
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# CONFIG_BLK_DEV_INITRD is not set
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CONFIG_BLK_DEV_INTEGRITY=y
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CONFIG_BLK_DEV_INTEGRITY_T10=y
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CONFIG_BLK_DEV_LOOP=y
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CONFIG_BLK_DEV_NVME=y
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CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y
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CONFIG_BLK_DEV_SD=y
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CONFIG_BLK_MQ_PCI=y
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CONFIG_BLK_PM=y
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CONFIG_BRCMSTB_GISB_ARB=y
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CONFIG_BSD_PROCESS_ACCT=y
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CONFIG_BSD_PROCESS_ACCT_V3=y
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CONFIG_BUFFER_HEAD=y
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CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y
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CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
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CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
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CONFIG_CHARGER_GPIO=y
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# CONFIG_CHARGER_RK817 is not set
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CONFIG_CLKSRC_MMIO=y
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CONFIG_CLK_PX30=y
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CONFIG_CLK_RK3308=y
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CONFIG_CLK_RK3328=y
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CONFIG_CLK_RK3368=y
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CONFIG_CLK_RK3399=y
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CONFIG_CLK_RK3568=y
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CONFIG_CLK_RK3588=y
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CONFIG_CLONE_BACKWARDS=y
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CONFIG_CMA=y
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CONFIG_CMA_ALIGNMENT=8
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CONFIG_CMA_AREAS=7
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# CONFIG_CMA_DEBUG is not set
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# CONFIG_CMA_DEBUGFS is not set
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CONFIG_CMA_SIZE_MBYTES=16
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# CONFIG_CMA_SIZE_SEL_MAX is not set
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CONFIG_CMA_SIZE_SEL_MBYTES=y
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# CONFIG_CMA_SIZE_SEL_MIN is not set
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# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
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# CONFIG_CMA_SYSFS is not set
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CONFIG_COMMON_CLK=y
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CONFIG_COMMON_CLK_RK808=y
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CONFIG_COMMON_CLK_ROCKCHIP=y
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CONFIG_COMMON_CLK_SCMI=y
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CONFIG_COMMON_CLK_SCPI=y
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CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
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CONFIG_COMPAT_32BIT_TIME=y
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CONFIG_CONFIGFS_FS=y
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CONFIG_CONSOLE_TRANSLATIONS=y
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CONFIG_CONTEXT_TRACKING=y
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CONFIG_CONTEXT_TRACKING_IDLE=y
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CONFIG_CONTIG_ALLOC=y
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CONFIG_CPUFREQ_DT=y
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CONFIG_CPUFREQ_DT_PLATDEV=y
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CONFIG_CPU_FREQ=y
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# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
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CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
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CONFIG_CPU_FREQ_GOV_ATTR_SET=y
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# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
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# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
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CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
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CONFIG_CPU_FREQ_GOV_POWERSAVE=y
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CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
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# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
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CONFIG_CPU_FREQ_STAT=y
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CONFIG_CPU_IDLE=y
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CONFIG_CPU_IDLE_GOV_MENU=y
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CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
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CONFIG_CPU_ISOLATION=y
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CONFIG_CPU_LITTLE_ENDIAN=y
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CONFIG_CPU_MITIGATIONS=y
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CONFIG_CPU_PM=y
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CONFIG_CPU_RMAP=y
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CONFIG_CPU_THERMAL=y
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CONFIG_CRASH_CORE=y
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CONFIG_CRASH_DUMP=y
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CONFIG_CRC16=y
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CONFIG_CRC64=y
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CONFIG_CRC64_ROCKSOFT=y
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CONFIG_CRC_T10DIF=y
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CONFIG_CROSS_MEMORY_ATTACH=y
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CONFIG_CRYPTO_AES_ARM64=y
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CONFIG_CRYPTO_AES_ARM64_CE=y
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CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
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CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
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CONFIG_CRYPTO_CRC32=y
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CONFIG_CRYPTO_CRC32C=y
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CONFIG_CRYPTO_CRC64_ROCKSOFT=y
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CONFIG_CRYPTO_CRCT10DIF=y
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CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
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CONFIG_CRYPTO_CRYPTD=y
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# CONFIG_CRYPTO_DEV_ROCKCHIP is not set
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CONFIG_CRYPTO_GHASH_ARM64_CE=y
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CONFIG_CRYPTO_HW=y
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CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
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CONFIG_CRYPTO_LIB_GF128MUL=y
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CONFIG_CRYPTO_LIB_SHA1=y
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CONFIG_CRYPTO_LIB_SHA256=y
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CONFIG_CRYPTO_LIB_UTILS=y
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CONFIG_CRYPTO_POLYVAL=y
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CONFIG_CRYPTO_POLYVAL_ARM64_CE=y
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CONFIG_CRYPTO_SHA256=y
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CONFIG_CRYPTO_SM3=y
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CONFIG_CRYPTO_SM3_NEON=y
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CONFIG_CRYPTO_SM4=y
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CONFIG_CRYPTO_SM4_ARM64_CE_BLK=y
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CONFIG_CRYPTO_SM4_ARM64_NEON_BLK=y
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CONFIG_DCACHE_WORD_ACCESS=y
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CONFIG_DEBUG_BUGVERBOSE=y
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CONFIG_DEBUG_INFO=y
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# CONFIG_DEVFREQ_GOV_PASSIVE is not set
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CONFIG_DEVFREQ_GOV_PERFORMANCE=y
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CONFIG_DEVFREQ_GOV_POWERSAVE=y
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CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
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CONFIG_DEVFREQ_GOV_USERSPACE=y
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# CONFIG_DEVFREQ_THERMAL is not set
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CONFIG_DEVMEM=y
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# CONFIG_DEVPORT is not set
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CONFIG_DMADEVICES=y
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CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y
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CONFIG_DMA_CMA=y
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CONFIG_DMA_DIRECT_REMAP=y
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CONFIG_DMA_ENGINE=y
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CONFIG_DMA_OF=y
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CONFIG_DMA_OPS=y
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CONFIG_DMA_SHARED_BUFFER=y
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CONFIG_DNOTIFY=y
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CONFIG_DTC=y
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CONFIG_DT_IDLE_GENPD=y
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CONFIG_DT_IDLE_STATES=y
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CONFIG_DUMMY_CONSOLE=y
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CONFIG_DWMAC_DWC_QOS_ETH=y
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CONFIG_DWMAC_GENERIC=y
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CONFIG_DWMAC_ROCKCHIP=y
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CONFIG_DW_WATCHDOG=y
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CONFIG_EDAC_SUPPORT=y
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CONFIG_EEPROM_AT24=y
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CONFIG_EMAC_ROCKCHIP=y
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CONFIG_ENERGY_MODEL=y
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CONFIG_EXCLUSIVE_SYSTEM_RAM=y
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CONFIG_EXT4_FS=y
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CONFIG_EXTCON=y
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CONFIG_F2FS_FS=y
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CONFIG_FANOTIFY=y
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CONFIG_FHANDLE=y
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CONFIG_FIXED_PHY=y
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CONFIG_FIX_EARLYCON_MEM=y
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CONFIG_FRAME_POINTER=y
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CONFIG_FS_IOMAP=y
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CONFIG_FS_MBCACHE=y
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CONFIG_FUNCTION_ALIGNMENT=4
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CONFIG_FUNCTION_ALIGNMENT_4B=y
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CONFIG_FWNODE_MDIO=y
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CONFIG_FW_LOADER_PAGED_BUF=y
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CONFIG_FW_LOADER_SYSFS=y
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CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y
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CONFIG_GENERIC_ALLOCATOR=y
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CONFIG_GENERIC_ARCH_TOPOLOGY=y
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CONFIG_GENERIC_BUG=y
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CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
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CONFIG_GENERIC_CLOCKEVENTS=y
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CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
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CONFIG_GENERIC_CPU_AUTOPROBE=y
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CONFIG_GENERIC_CPU_VULNERABILITIES=y
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CONFIG_GENERIC_CSUM=y
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CONFIG_GENERIC_EARLY_IOREMAP=y
|
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CONFIG_GENERIC_GETTIMEOFDAY=y
|
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CONFIG_GENERIC_IDLE_POLL_SETUP=y
|
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CONFIG_GENERIC_IOREMAP=y
|
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CONFIG_GENERIC_IRQ_CHIP=y
|
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CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
|
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CONFIG_GENERIC_IRQ_MIGRATION=y
|
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CONFIG_GENERIC_IRQ_SHOW=y
|
||||
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
|
||||
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
|
||||
CONFIG_GENERIC_MSI_IRQ=y
|
||||
CONFIG_GENERIC_PCI_IOMAP=y
|
||||
CONFIG_GENERIC_PHY=y
|
||||
CONFIG_GENERIC_PINCONF=y
|
||||
CONFIG_GENERIC_SCHED_CLOCK=y
|
||||
CONFIG_GENERIC_SMP_IDLE_THREAD=y
|
||||
CONFIG_GENERIC_STRNCPY_FROM_USER=y
|
||||
CONFIG_GENERIC_STRNLEN_USER=y
|
||||
CONFIG_GENERIC_TIME_VSYSCALL=y
|
||||
CONFIG_GPIOLIB_IRQCHIP=y
|
||||
CONFIG_GPIO_CDEV=y
|
||||
CONFIG_GPIO_DWAPB=y
|
||||
CONFIG_GPIO_GENERIC=y
|
||||
CONFIG_GPIO_GENERIC_PLATFORM=y
|
||||
CONFIG_GPIO_ROCKCHIP=y
|
||||
CONFIG_GPIO_SYSCON=y
|
||||
CONFIG_GRO_CELLS=y
|
||||
CONFIG_HARDIRQS_SW_RESEND=y
|
||||
CONFIG_HAS_DMA=y
|
||||
CONFIG_HAS_IOMEM=y
|
||||
CONFIG_HAS_IOPORT=y
|
||||
CONFIG_HAS_IOPORT_MAP=y
|
||||
CONFIG_HOTPLUG_CORE_SYNC=y
|
||||
CONFIG_HOTPLUG_CORE_SYNC_DEAD=y
|
||||
CONFIG_HOTPLUG_CPU=y
|
||||
CONFIG_HOTPLUG_PCI=y
|
||||
# CONFIG_HOTPLUG_PCI_CPCI is not set
|
||||
# CONFIG_HOTPLUG_PCI_PCIE is not set
|
||||
# CONFIG_HOTPLUG_PCI_SHPC is not set
|
||||
CONFIG_HUGETLBFS=y
|
||||
CONFIG_HUGETLB_PAGE=y
|
||||
CONFIG_HWMON=y
|
||||
CONFIG_HWSPINLOCK=y
|
||||
CONFIG_HW_CONSOLE=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_HW_RANDOM_ROCKCHIP=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_BOARDINFO=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_COMPAT=y
|
||||
CONFIG_I2C_HELPER_AUTO=y
|
||||
CONFIG_I2C_RK3X=y
|
||||
CONFIG_IIO=y
|
||||
# CONFIG_IIO_SCMI is not set
|
||||
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
|
||||
CONFIG_INDIRECT_PIO=y
|
||||
CONFIG_INPUT=y
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
CONFIG_INPUT_FF_MEMLESS=y
|
||||
CONFIG_INPUT_KEYBOARD=y
|
||||
CONFIG_INPUT_LEDS=y
|
||||
CONFIG_INPUT_MATRIXKMAP=y
|
||||
CONFIG_INPUT_RK805_PWRKEY=y
|
||||
# CONFIG_IOMMUFD is not set
|
||||
CONFIG_IOMMU_API=y
|
||||
# CONFIG_IOMMU_DEBUGFS is not set
|
||||
# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
|
||||
# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set
|
||||
CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y
|
||||
CONFIG_IOMMU_DMA=y
|
||||
CONFIG_IOMMU_IOVA=y
|
||||
CONFIG_IOMMU_IO_PGTABLE=y
|
||||
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
|
||||
# CONFIG_IOMMU_IO_PGTABLE_DART is not set
|
||||
CONFIG_IOMMU_IO_PGTABLE_LPAE=y
|
||||
# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
|
||||
CONFIG_IOMMU_SUPPORT=y
|
||||
# CONFIG_IO_STRICT_DEVMEM is not set
|
||||
CONFIG_IRQCHIP=y
|
||||
CONFIG_IRQ_DOMAIN=y
|
||||
CONFIG_IRQ_DOMAIN_HIERARCHY=y
|
||||
CONFIG_IRQ_FORCED_THREADING=y
|
||||
CONFIG_IRQ_MSI_IOMMU=y
|
||||
CONFIG_IRQ_TIME_ACCOUNTING=y
|
||||
CONFIG_IRQ_WORK=y
|
||||
CONFIG_JBD2=y
|
||||
CONFIG_JFFS2_ZLIB=y
|
||||
CONFIG_JUMP_LABEL=y
|
||||
CONFIG_KALLSYMS=y
|
||||
CONFIG_KCMP=y
|
||||
CONFIG_KEXEC_CORE=y
|
||||
CONFIG_KEXEC_FILE=y
|
||||
CONFIG_KSM=y
|
||||
# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
|
||||
CONFIG_LEDS_GPIO=y
|
||||
CONFIG_LEDS_PWM=y
|
||||
CONFIG_LEDS_SYSCON=y
|
||||
CONFIG_LEDS_TRIGGER_CPU=y
|
||||
CONFIG_LEDS_TRIGGER_PANIC=y
|
||||
CONFIG_LIBCRC32C=y
|
||||
CONFIG_LIBFDT=y
|
||||
CONFIG_LOCALVERSION_AUTO=y
|
||||
CONFIG_LOCK_DEBUGGING_SUPPORT=y
|
||||
CONFIG_LOCK_SPIN_ON_OWNER=y
|
||||
CONFIG_LOG_BUF_SHIFT=19
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_MAGIC_SYSRQ_SERIAL=y
|
||||
CONFIG_MAILBOX=y
|
||||
# CONFIG_MAILBOX_TEST is not set
|
||||
CONFIG_MDIO_BUS=y
|
||||
CONFIG_MDIO_BUS_MUX=y
|
||||
CONFIG_MDIO_BUS_MUX_GPIO=y
|
||||
CONFIG_MDIO_BUS_MUX_MMIOREG=y
|
||||
CONFIG_MDIO_DEVICE=y
|
||||
CONFIG_MDIO_DEVRES=y
|
||||
CONFIG_MEDIATEK_GE_PHY=y
|
||||
# CONFIG_MEDIATEK_GE_SOC_PHY is not set
|
||||
CONFIG_MEMORY_ISOLATION=y
|
||||
CONFIG_MFD_CORE=y
|
||||
# CONFIG_MFD_KHADAS_MCU is not set
|
||||
CONFIG_MFD_RK8XX=y
|
||||
CONFIG_MFD_RK8XX_I2C=y
|
||||
CONFIG_MFD_RK8XX_SPI=y
|
||||
CONFIG_MFD_SYSCON=y
|
||||
CONFIG_MIGRATION=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_BLOCK=y
|
||||
CONFIG_MMC_BLOCK_MINORS=32
|
||||
CONFIG_MMC_CQHCI=y
|
||||
CONFIG_MMC_DW=y
|
||||
# CONFIG_MMC_DW_BLUEFIELD is not set
|
||||
# CONFIG_MMC_DW_EXYNOS is not set
|
||||
# CONFIG_MMC_DW_HI3798CV200 is not set
|
||||
# CONFIG_MMC_DW_K3 is not set
|
||||
# CONFIG_MMC_DW_PCI is not set
|
||||
CONFIG_MMC_DW_PLTFM=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_OF_ARASAN=y
|
||||
CONFIG_MMC_SDHCI_OF_DWCMSHC=y
|
||||
# CONFIG_MMC_SDHCI_PCI is not set
|
||||
CONFIG_MMC_SDHCI_PLTFM=y
|
||||
CONFIG_MMU_LAZY_TLB_REFCOUNT=y
|
||||
CONFIG_MODULES_USE_ELF_RELA=y
|
||||
CONFIG_MOTORCOMM_PHY=y
|
||||
CONFIG_MQ_IOSCHED_DEADLINE=y
|
||||
# CONFIG_MTD_CFI is not set
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
|
||||
CONFIG_MTD_SPI_NOR=y
|
||||
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
|
||||
CONFIG_MTD_SPLIT_FIRMWARE=y
|
||||
CONFIG_MUTEX_SPIN_ON_OWNER=y
|
||||
CONFIG_NEED_DMA_MAP_STATE=y
|
||||
CONFIG_NEED_SG_DMA_FLAGS=y
|
||||
CONFIG_NEED_SG_DMA_LENGTH=y
|
||||
CONFIG_NET_DEVLINK=y
|
||||
CONFIG_NET_DSA=y
|
||||
CONFIG_NET_DSA_MT7530=y
|
||||
CONFIG_NET_DSA_MT7530_MDIO=y
|
||||
CONFIG_NET_DSA_MT7530_MMIO=y
|
||||
CONFIG_NET_DSA_TAG_MTK=y
|
||||
CONFIG_NET_EGRESS=y
|
||||
CONFIG_NET_FLOW_LIMIT=y
|
||||
CONFIG_NET_INGRESS=y
|
||||
CONFIG_NET_PTP_CLASSIFY=y
|
||||
CONFIG_NET_SELFTESTS=y
|
||||
CONFIG_NET_XGRESS=y
|
||||
CONFIG_NLS=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_NOP_USB_XCEIV=y
|
||||
CONFIG_NO_HZ_COMMON=y
|
||||
CONFIG_NO_HZ_IDLE=y
|
||||
CONFIG_NR_CPUS=256
|
||||
CONFIG_NVMEM=y
|
||||
CONFIG_NVMEM_LAYOUTS=y
|
||||
CONFIG_NVMEM_ROCKCHIP_EFUSE=y
|
||||
CONFIG_NVMEM_ROCKCHIP_OTP=y
|
||||
CONFIG_NVMEM_SYSFS=y
|
||||
CONFIG_NVME_CORE=y
|
||||
# CONFIG_NVME_HWMON is not set
|
||||
# CONFIG_NVME_MULTIPATH is not set
|
||||
CONFIG_OF=y
|
||||
CONFIG_OF_ADDRESS=y
|
||||
CONFIG_OF_DYNAMIC=y
|
||||
CONFIG_OF_EARLY_FLATTREE=y
|
||||
CONFIG_OF_FLATTREE=y
|
||||
CONFIG_OF_GPIO=y
|
||||
CONFIG_OF_IOMMU=y
|
||||
CONFIG_OF_IRQ=y
|
||||
CONFIG_OF_KOBJ=y
|
||||
CONFIG_OF_MDIO=y
|
||||
CONFIG_OF_OVERLAY=y
|
||||
CONFIG_OF_RESOLVE=y
|
||||
# CONFIG_OVERLAY_FS_XINO_AUTO is not set
|
||||
CONFIG_PADATA=y
|
||||
CONFIG_PAGE_POOL=y
|
||||
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
|
||||
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
|
||||
# CONFIG_PANIC_ON_OOPS is not set
|
||||
CONFIG_PANIC_ON_OOPS_VALUE=0
|
||||
CONFIG_PANIC_TIMEOUT=0
|
||||
# CONFIG_PARTITION_ADVANCED is not set
|
||||
CONFIG_PARTITION_PERCPU=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCIEAER=y
|
||||
CONFIG_PCIEASPM=y
|
||||
CONFIG_PCIEASPM_DEFAULT=y
|
||||
# CONFIG_PCIEASPM_PERFORMANCE is not set
|
||||
# CONFIG_PCIEASPM_POWERSAVE is not set
|
||||
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
|
||||
CONFIG_PCIEPORTBUS=y
|
||||
CONFIG_PCIE_DW=y
|
||||
CONFIG_PCIE_DW_HOST=y
|
||||
CONFIG_PCIE_PME=y
|
||||
CONFIG_PCIE_ROCKCHIP=y
|
||||
CONFIG_PCIE_ROCKCHIP_DW_HOST=y
|
||||
CONFIG_PCIE_ROCKCHIP_HOST=y
|
||||
CONFIG_PCI_DOMAINS=y
|
||||
CONFIG_PCI_DOMAINS_GENERIC=y
|
||||
CONFIG_PCI_MSI=y
|
||||
CONFIG_PCI_STUB=y
|
||||
CONFIG_PCS_MTK_LYNXI=y
|
||||
CONFIG_PCS_XPCS=y
|
||||
CONFIG_PER_VMA_LOCK=y
|
||||
CONFIG_PGTABLE_LEVELS=4
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHYLIB_LEDS=y
|
||||
CONFIG_PHYLINK=y
|
||||
CONFIG_PHYS_ADDR_T_64BIT=y
|
||||
CONFIG_PHY_ROCKCHIP_DP=y
|
||||
# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set
|
||||
CONFIG_PHY_ROCKCHIP_EMMC=y
|
||||
# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set
|
||||
# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
|
||||
# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
|
||||
CONFIG_PHY_ROCKCHIP_PCIE=y
|
||||
CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
|
||||
CONFIG_PHY_ROCKCHIP_TYPEC=y
|
||||
CONFIG_PHY_ROCKCHIP_USB=y
|
||||
CONFIG_PHY_ROCKCHIP_USBDP=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_RK805=y
|
||||
CONFIG_PINCTRL_ROCKCHIP=y
|
||||
# CONFIG_PINCTRL_SINGLE is not set
|
||||
CONFIG_PL330_DMA=y
|
||||
CONFIG_PLATFORM_MHU=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_PM_CLK=y
|
||||
CONFIG_PM_DEVFREQ=y
|
||||
# CONFIG_PM_DEVFREQ_EVENT is not set
|
||||
CONFIG_PM_GENERIC_DOMAINS=y
|
||||
CONFIG_PM_GENERIC_DOMAINS_OF=y
|
||||
CONFIG_PM_OPP=y
|
||||
CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
|
||||
CONFIG_POWER_RESET=y
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
CONFIG_POWER_SUPPLY_HWMON=y
|
||||
CONFIG_PPS=y
|
||||
CONFIG_PREEMPT_NONE_BUILD=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_PROC_PAGE_MONITOR=y
|
||||
CONFIG_PROC_VMCORE=y
|
||||
CONFIG_PTP_1588_CLOCK=y
|
||||
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
|
||||
CONFIG_PWM=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_PWM_SYSFS=y
|
||||
# CONFIG_QFMT_V2 is not set
|
||||
CONFIG_QUEUED_RWLOCKS=y
|
||||
CONFIG_QUEUED_SPINLOCKS=y
|
||||
CONFIG_QUOTA=y
|
||||
CONFIG_QUOTACTL=y
|
||||
CONFIG_RAID_ATTRS=y
|
||||
CONFIG_RANDSTRUCT_NONE=y
|
||||
CONFIG_RAS=y
|
||||
CONFIG_RATIONAL=y
|
||||
# CONFIG_RAVE_SP_CORE is not set
|
||||
CONFIG_RCU_TRACE=y
|
||||
CONFIG_REALTEK_PHY=y
|
||||
CONFIG_REALTEK_PHY_HWMON=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_REGMAP_I2C=y
|
||||
CONFIG_REGMAP_IRQ=y
|
||||
CONFIG_REGMAP_MMIO=y
|
||||
CONFIG_REGMAP_SPI=y
|
||||
CONFIG_REGULATOR=y
|
||||
CONFIG_REGULATOR_ARM_SCMI=y
|
||||
CONFIG_REGULATOR_FAN53555=y
|
||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
CONFIG_REGULATOR_GPIO=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_REGULATOR_RK808=y
|
||||
CONFIG_RELOCATABLE=y
|
||||
CONFIG_RESET_CONTROLLER=y
|
||||
CONFIG_RESET_SCMI=y
|
||||
CONFIG_RFS_ACCEL=y
|
||||
CONFIG_ROCKCHIP_ERRATUM_3568002=y
|
||||
CONFIG_ROCKCHIP_ERRATUM_3588001=y
|
||||
CONFIG_ROCKCHIP_GRF=y
|
||||
CONFIG_ROCKCHIP_IODOMAIN=y
|
||||
CONFIG_ROCKCHIP_IOMMU=y
|
||||
CONFIG_ROCKCHIP_MBOX=y
|
||||
CONFIG_ROCKCHIP_PHY=y
|
||||
CONFIG_ROCKCHIP_PM_DOMAINS=y
|
||||
# CONFIG_ROCKCHIP_SARADC is not set
|
||||
CONFIG_ROCKCHIP_THERMAL=y
|
||||
CONFIG_ROCKCHIP_TIMER=y
|
||||
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
|
||||
CONFIG_RPS=y
|
||||
CONFIG_RSEQ=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_HYM8563=y
|
||||
CONFIG_RTC_DRV_RK808=y
|
||||
CONFIG_RTC_I2C_AND_SPI=y
|
||||
CONFIG_RTC_NVMEM=y
|
||||
# CONFIG_RUNTIME_TESTING_MENU is not set
|
||||
CONFIG_RWSEM_SPIN_ON_OWNER=y
|
||||
CONFIG_SCHED_MC=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_SCSI_COMMON=y
|
||||
# CONFIG_SCSI_LOWLEVEL is not set
|
||||
# CONFIG_SCSI_PROC_FS is not set
|
||||
CONFIG_SCSI_SAS_ATTRS=y
|
||||
CONFIG_SCSI_SAS_HOST_SMP=y
|
||||
CONFIG_SCSI_SAS_LIBSAS=y
|
||||
# CONFIG_SECURITY_DMESG_RESTRICT is not set
|
||||
CONFIG_SENSORS_ARM_SCMI=y
|
||||
CONFIG_SENSORS_ARM_SCPI=y
|
||||
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
|
||||
CONFIG_SERIAL_8250_DW=y
|
||||
CONFIG_SERIAL_8250_DWLIB=y
|
||||
CONFIG_SERIAL_8250_EXAR=y
|
||||
CONFIG_SERIAL_8250_EXTENDED=y
|
||||
CONFIG_SERIAL_8250_FSL=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=4
|
||||
CONFIG_SERIAL_8250_PCI=y
|
||||
CONFIG_SERIAL_8250_PCILIB=y
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
|
||||
CONFIG_SERIAL_8250_SHARE_IRQ=y
|
||||
CONFIG_SERIAL_AMBA_PL011=y
|
||||
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
|
||||
CONFIG_SERIAL_DEV_BUS=y
|
||||
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
|
||||
CONFIG_SERIAL_MCTRL_GPIO=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
CONFIG_SERIO=y
|
||||
CONFIG_SERIO_AMBAKMI=y
|
||||
CONFIG_SERIO_LIBPS2=y
|
||||
CONFIG_SG_POOL=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SOCK_RX_QUEUE_MAPPING=y
|
||||
CONFIG_SOFTIRQ_ON_OWN_STACK=y
|
||||
CONFIG_SPARSEMEM=y
|
||||
CONFIG_SPARSEMEM_EXTREME=y
|
||||
CONFIG_SPARSEMEM_VMEMMAP=y
|
||||
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_BITBANG=y
|
||||
CONFIG_SPI_DYNAMIC=y
|
||||
CONFIG_SPI_MASTER=y
|
||||
CONFIG_SPI_MEM=y
|
||||
CONFIG_SPI_ROCKCHIP=y
|
||||
CONFIG_SPI_ROCKCHIP_SFC=y
|
||||
CONFIG_SPI_SPIDEV=y
|
||||
CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
|
||||
# CONFIG_SQUASHFS_EMBEDDED is not set
|
||||
CONFIG_SQUASHFS_FILE_CACHE=y
|
||||
# CONFIG_SQUASHFS_FILE_DIRECT is not set
|
||||
CONFIG_SRAM=y
|
||||
CONFIG_STACKPROTECTOR=y
|
||||
CONFIG_STACKPROTECTOR_PER_TASK=y
|
||||
CONFIG_STACKPROTECTOR_STRONG=y
|
||||
CONFIG_STACKTRACE=y
|
||||
CONFIG_STMMAC_ETH=y
|
||||
CONFIG_STMMAC_PLATFORM=y
|
||||
CONFIG_STRICT_DEVMEM=y
|
||||
# CONFIG_STRIP_ASM_SYMS is not set
|
||||
# CONFIG_SWAP is not set
|
||||
CONFIG_SWIOTLB=y
|
||||
CONFIG_SWPHY=y
|
||||
CONFIG_SYNC_FILE=y
|
||||
CONFIG_SYSCTL_EXCEPTION_TRACE=y
|
||||
CONFIG_SYSFS_SYSCALL=y
|
||||
# CONFIG_TEXTSEARCH is not set
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
|
||||
CONFIG_THERMAL_EMULATION=y
|
||||
CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
|
||||
CONFIG_THERMAL_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_HWMON=y
|
||||
CONFIG_THERMAL_OF=y
|
||||
CONFIG_THREAD_INFO_IN_TASK=y
|
||||
CONFIG_TICK_CPU_ACCOUNTING=y
|
||||
CONFIG_TIMER_OF=y
|
||||
CONFIG_TIMER_PROBE=y
|
||||
CONFIG_TRACE_CLOCK=y
|
||||
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
|
||||
CONFIG_TRANSPARENT_HUGEPAGE=y
|
||||
CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
|
||||
# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
|
||||
CONFIG_TRANS_TABLE=y
|
||||
CONFIG_TREE_RCU=y
|
||||
CONFIG_TREE_SRCU=y
|
||||
CONFIG_TYPEC=y
|
||||
# CONFIG_TYPEC_ANX7411 is not set
|
||||
CONFIG_TYPEC_FUSB302=y
|
||||
# CONFIG_TYPEC_HD3SS3220 is not set
|
||||
# CONFIG_TYPEC_MUX_FSA4480 is not set
|
||||
# CONFIG_TYPEC_MUX_GPIO_SBU is not set
|
||||
# CONFIG_TYPEC_MUX_NB7VPQ904M is not set
|
||||
# CONFIG_TYPEC_MUX_PI3USB30532 is not set
|
||||
# CONFIG_TYPEC_RT1719 is not set
|
||||
# CONFIG_TYPEC_STUSB160X is not set
|
||||
# CONFIG_TYPEC_TCPCI is not set
|
||||
CONFIG_TYPEC_TCPM=y
|
||||
# CONFIG_TYPEC_TPS6598X is not set
|
||||
# CONFIG_TYPEC_WUSB3801 is not set
|
||||
# CONFIG_UCLAMP_TASK is not set
|
||||
# CONFIG_UEVENT_HELPER is not set
|
||||
CONFIG_UNMAP_KERNEL_AT_EL0=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_COMMON=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_HOST=y
|
||||
CONFIG_USB_DWC3_OF_SIMPLE=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD_PLATFORM=y
|
||||
# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_HCD_PLATFORM=y
|
||||
CONFIG_USB_PHY=y
|
||||
CONFIG_USB_ROLE_SWITCH=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_SUPPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_ULPI_BUS=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_PLATFORM=y
|
||||
# CONFIG_VIRTIO_MENU is not set
|
||||
CONFIG_VMAP_STACK=y
|
||||
CONFIG_VM_EVENT_COUNTERS=y
|
||||
CONFIG_VT=y
|
||||
CONFIG_VT_CONSOLE=y
|
||||
CONFIG_VT_HW_CONSOLE_BINDING=y
|
||||
CONFIG_WATCHDOG_CORE=y
|
||||
CONFIG_XARRAY_MULTI=y
|
||||
CONFIG_XPS=y
|
||||
CONFIG_XXHASH=y
|
||||
CONFIG_XZ_DEC_ARM=y
|
||||
CONFIG_XZ_DEC_ARMTHUMB=y
|
||||
CONFIG_XZ_DEC_BCJ=y
|
||||
CONFIG_ZLIB_DEFLATE=y
|
||||
CONFIG_ZLIB_INFLATE=y
|
||||
CONFIG_ZONE_DMA32=y
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
From 36d9b3ae708e865cdab95692db5a24c5d975383d Mon Sep 17 00:00:00 2001
|
||||
From: Dragan Simic <dsimic@manjaro.org>
|
||||
Date: Tue, 12 Dec 2023 09:01:39 +0100
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add ethernet0 alias to the dts for
|
||||
RK3566 boards
|
||||
|
||||
Add ethernet0 alias to the board dts files for a few supported RK3566 boards
|
||||
that had it missing. Also, remove the ethernet0 alias from one RK3566 SoM
|
||||
dtsi file, which doesn't enable the GMAC, and add the ethernet0 alias back to
|
||||
the dependent board dts files, which actually enable the GMAC.
|
||||
|
||||
Signed-off-by: Dragan Simic <dsimic@manjaro.org>
|
||||
Link: https://lore.kernel.org/r/d2a272e0ae0fff0adfab8bb0238243b11d348799.1702368023.git.dsimic@manjaro.org
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 1 +
|
||||
1 files changed, 1 insertions(+), 0 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
|
||||
@@ -14,6 +14,7 @@
|
||||
compatible = "radxa,cm3-io", "radxa,cm3", "rockchip,rk3566";
|
||||
|
||||
aliases {
|
||||
+ ethernet0 = &gmac1;
|
||||
mmc1 = &sdmmc0;
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
From 437644753208092f642b7669c69da606aa07dfb4 Mon Sep 17 00:00:00 2001
|
||||
From: Tim Lunn <tim@feathertop.org>
|
||||
Date: Wed, 14 Feb 2024 15:07:30 +1100
|
||||
Subject: [PATCH] arm64: dts: rockchip: adjust vendor on Banana Pi R2 Pro board
|
||||
|
||||
Adjust compatible string to match the board vendor of Sinovoip
|
||||
|
||||
Signed-off-by: Tim Lunn <tim@feathertop.org>
|
||||
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
|
||||
Acked-by: Conor Dooley <conor.dooley@microchip.com>
|
||||
Link: https://lore.kernel.org/r/20240214040731.3069111-4-tim@feathertop.org
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
|
||||
@@ -13,7 +13,7 @@
|
||||
|
||||
/ {
|
||||
model = "Bananapi-R2 Pro (RK3568) DDR4 Board";
|
||||
- compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568";
|
||||
+ compatible = "sinovoip,rk3568-bpi-r2pro", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac0;
|
||||
|
|
@ -0,0 +1,127 @@
|
|||
From 8612169a05c5e979af033868b7a9b177e0f9fcdf Mon Sep 17 00:00:00 2001
|
||||
From: Dragan Simic <dsimic@manjaro.org>
|
||||
Date: Sat, 9 Mar 2024 05:25:06 +0100
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add cache information to the SoC dtsi
|
||||
for RK356x
|
||||
|
||||
Add missing cache information to the Rockchip RK356x SoC dtsi, to allow
|
||||
the userspace, which includes lscpu(1) that uses the virtual files provided
|
||||
by the kernel under the /sys/devices/system/cpu directory, to display the
|
||||
proper RK3566 and RK3568 cache information.
|
||||
|
||||
Adding the cache information to the RK356x SoC dtsi also makes the following
|
||||
warning message in the kernel log go away:
|
||||
|
||||
cacheinfo: Unable to detect cache hierarchy for CPU 0
|
||||
|
||||
The cache parameters for the RK356x dtsi were obtained and partially derived
|
||||
by hand from the cache size and layout specifications found in the following
|
||||
datasheets and technical reference manuals:
|
||||
|
||||
- Rockchip RK3566 datasheet, version 1.1
|
||||
- Rockchip RK3568 datasheet, version 1.3
|
||||
- ARM Cortex-A55 revision r1p0 TRM, version 0100-00
|
||||
- ARM DynamIQ Shared Unit revision r4p0 TRM, version 0400-02
|
||||
|
||||
For future reference, here's a rather detailed summary of the documentation,
|
||||
which applies to both Rockchip RK3566 and RK3568 SoCs:
|
||||
|
||||
- All caches employ the 64-byte cache line length
|
||||
- Each Cortex-A55 core has 32 KB of L1 4-way, set-associative instruction
|
||||
cache and 32 KB of L1 4-way, set-associative data cache
|
||||
- There are no L2 caches, which are per-core and private in Cortex-A55,
|
||||
because it belongs to the ARM DynamIQ IP core lineup
|
||||
- The entire SoC has 512 KB of unified L3 16-way, set-associative cache,
|
||||
which is shared among all four Cortex-A55 CPU cores
|
||||
- Cortex-A55 cores can be configured without private per-core L2 caches,
|
||||
in which case the shared L3 cache appears to them as an L2 cache; this
|
||||
is the case for the RK356x SoCs, so let's use "cache-level = <2>" to
|
||||
prevent the "huh, no L2 caches, but an L3 cache?" confusion among the
|
||||
users viewing the data presented to the userspace; another option could
|
||||
be to have additional 0 KB L2 caches defined, which may be technically
|
||||
correct, but would probably be even more confusing
|
||||
|
||||
Helped-by: Anand Moon <linux.amoon@gmail.com>
|
||||
Tested-By: Diederik de Haas <didi.debian@cknow.org>
|
||||
Reviewed-by: Anand Moon <linux.amoon@gmail.com>
|
||||
Signed-off-by: Dragan Simic <dsimic@manjaro.org>
|
||||
Link: https://lore.kernel.org/r/2dee6dad8460b0c5f3b5da53cf55f735840efef1.1709957777.git.dsimic@manjaro.org
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 41 ++++++++++++++++++++++++
|
||||
1 file changed, 41 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -57,6 +57,13 @@
|
||||
#cooling-cells = <2>;
|
||||
enable-method = "psci";
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
+ i-cache-size = <0x8000>;
|
||||
+ i-cache-line-size = <64>;
|
||||
+ i-cache-sets = <128>;
|
||||
+ d-cache-size = <0x8000>;
|
||||
+ d-cache-line-size = <64>;
|
||||
+ d-cache-sets = <128>;
|
||||
+ next-level-cache = <&l3_cache>;
|
||||
};
|
||||
|
||||
cpu1: cpu@100 {
|
||||
@@ -66,6 +73,13 @@
|
||||
#cooling-cells = <2>;
|
||||
enable-method = "psci";
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
+ i-cache-size = <0x8000>;
|
||||
+ i-cache-line-size = <64>;
|
||||
+ i-cache-sets = <128>;
|
||||
+ d-cache-size = <0x8000>;
|
||||
+ d-cache-line-size = <64>;
|
||||
+ d-cache-sets = <128>;
|
||||
+ next-level-cache = <&l3_cache>;
|
||||
};
|
||||
|
||||
cpu2: cpu@200 {
|
||||
@@ -75,6 +89,13 @@
|
||||
#cooling-cells = <2>;
|
||||
enable-method = "psci";
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
+ i-cache-size = <0x8000>;
|
||||
+ i-cache-line-size = <64>;
|
||||
+ i-cache-sets = <128>;
|
||||
+ d-cache-size = <0x8000>;
|
||||
+ d-cache-line-size = <64>;
|
||||
+ d-cache-sets = <128>;
|
||||
+ next-level-cache = <&l3_cache>;
|
||||
};
|
||||
|
||||
cpu3: cpu@300 {
|
||||
@@ -84,9 +105,29 @@
|
||||
#cooling-cells = <2>;
|
||||
enable-method = "psci";
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
+ i-cache-size = <0x8000>;
|
||||
+ i-cache-line-size = <64>;
|
||||
+ i-cache-sets = <128>;
|
||||
+ d-cache-size = <0x8000>;
|
||||
+ d-cache-line-size = <64>;
|
||||
+ d-cache-sets = <128>;
|
||||
+ next-level-cache = <&l3_cache>;
|
||||
};
|
||||
};
|
||||
|
||||
+ /*
|
||||
+ * There are no private per-core L2 caches, but only the
|
||||
+ * L3 cache that appears to the CPU cores as L2 caches
|
||||
+ */
|
||||
+ l3_cache: l3-cache {
|
||||
+ compatible = "cache";
|
||||
+ cache-level = <2>;
|
||||
+ cache-unified;
|
||||
+ cache-size = <0x80000>;
|
||||
+ cache-line-size = <64>;
|
||||
+ cache-sets = <512>;
|
||||
+ };
|
||||
+
|
||||
cpu0_opp_table: opp-table-0 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
From 0536fa6e6fa3e48f4ca11855b586c277be524fbe Mon Sep 17 00:00:00 2001
|
||||
From: David Wu <david.wu@rock-chips.com>
|
||||
Date: Tue, 21 May 2024 21:10:13 +0000
|
||||
Subject: [PATCH] soc: rockchip: io-domain: Add RK3308 IO voltage domains
|
||||
|
||||
Add IO voltage domains support for the RK3308 SoC.
|
||||
|
||||
Signed-off-by: David Wu <david.wu@rock-chips.com>
|
||||
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
Link: https://lore.kernel.org/r/20240521211029.1236094-11-jonas@kwiboo.se
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
drivers/soc/rockchip/io-domain.c | 40 ++++++++++++++++++++++++++++++++
|
||||
1 file changed, 40 insertions(+)
|
||||
|
||||
--- a/drivers/soc/rockchip/io-domain.c
|
||||
+++ b/drivers/soc/rockchip/io-domain.c
|
||||
@@ -39,6 +39,10 @@
|
||||
#define RK3288_SOC_CON2_FLASH0 BIT(7)
|
||||
#define RK3288_SOC_FLASH_SUPPLY_NUM 2
|
||||
|
||||
+#define RK3308_SOC_CON0 0x300
|
||||
+#define RK3308_SOC_CON0_VCCIO3 BIT(8)
|
||||
+#define RK3308_SOC_VCCIO3_SUPPLY_NUM 3
|
||||
+
|
||||
#define RK3328_SOC_CON4 0x410
|
||||
#define RK3328_SOC_CON4_VCCIO2 BIT(7)
|
||||
#define RK3328_SOC_VCCIO2_SUPPLY_NUM 1
|
||||
@@ -229,6 +233,25 @@ static void rk3288_iodomain_init(struct
|
||||
dev_warn(iod->dev, "couldn't update flash0 ctrl\n");
|
||||
}
|
||||
|
||||
+static void rk3308_iodomain_init(struct rockchip_iodomain *iod)
|
||||
+{
|
||||
+ int ret;
|
||||
+ u32 val;
|
||||
+
|
||||
+ /* if no vccio3 supply we should leave things alone */
|
||||
+ if (!iod->supplies[RK3308_SOC_VCCIO3_SUPPLY_NUM].reg)
|
||||
+ return;
|
||||
+
|
||||
+ /*
|
||||
+ * set vccio3 iodomain to also use this framework
|
||||
+ * instead of a special gpio.
|
||||
+ */
|
||||
+ val = RK3308_SOC_CON0_VCCIO3 | (RK3308_SOC_CON0_VCCIO3 << 16);
|
||||
+ ret = regmap_write(iod->grf, RK3308_SOC_CON0, val);
|
||||
+ if (ret < 0)
|
||||
+ dev_warn(iod->dev, "couldn't update vccio3 vsel ctrl\n");
|
||||
+}
|
||||
+
|
||||
static void rk3328_iodomain_init(struct rockchip_iodomain *iod)
|
||||
{
|
||||
int ret;
|
||||
@@ -376,6 +399,19 @@ static const struct rockchip_iodomain_so
|
||||
.init = rk3288_iodomain_init,
|
||||
};
|
||||
|
||||
+static const struct rockchip_iodomain_soc_data soc_data_rk3308 = {
|
||||
+ .grf_offset = 0x300,
|
||||
+ .supply_names = {
|
||||
+ "vccio0",
|
||||
+ "vccio1",
|
||||
+ "vccio2",
|
||||
+ "vccio3",
|
||||
+ "vccio4",
|
||||
+ "vccio5",
|
||||
+ },
|
||||
+ .init = rk3308_iodomain_init,
|
||||
+};
|
||||
+
|
||||
static const struct rockchip_iodomain_soc_data soc_data_rk3328 = {
|
||||
.grf_offset = 0x410,
|
||||
.supply_names = {
|
||||
@@ -529,6 +565,10 @@ static const struct of_device_id rockchi
|
||||
.data = &soc_data_rk3288
|
||||
},
|
||||
{
|
||||
+ .compatible = "rockchip,rk3308-io-voltage-domain",
|
||||
+ .data = &soc_data_rk3308
|
||||
+ },
|
||||
+ {
|
||||
.compatible = "rockchip,rk3328-io-voltage-domain",
|
||||
.data = &soc_data_rk3328
|
||||
},
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
From d1829ba469d5743734e37d59fece73e3668ab084 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Tue, 21 May 2024 21:10:14 +0000
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add rk3308 IO voltage domains
|
||||
|
||||
Add a disabled RK3308 IO voltage domains node to SoC DT.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
Link: https://lore.kernel.org/r/20240521211029.1236094-12-jonas@kwiboo.se
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3308.dtsi | 5 +++++
|
||||
1 file changed, 5 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
|
||||
@@ -168,6 +168,11 @@
|
||||
compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd";
|
||||
reg = <0x0 0xff000000 0x0 0x08000>;
|
||||
|
||||
+ io_domains: io-domains {
|
||||
+ compatible = "rockchip,rk3308-io-voltage-domain";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
reboot-mode {
|
||||
compatible = "syscon-reboot-mode";
|
||||
offset = <0x500>;
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
From c45de75d7a9ab44a15dedc7a121d6371d6891301 Mon Sep 17 00:00:00 2001
|
||||
From: Trevor Woerner <twoerner@gmail.com>
|
||||
Date: Mon, 20 Nov 2023 11:22:32 -0500
|
||||
Subject: [PATCH] arm64: dts: rockchip: add gpio-line-names to rk3308-rock-pi-s
|
||||
|
||||
Add names to the pins of the general-purpose expansion header as given in the
|
||||
Radxa GPIO page[1] following the conventions in the kernel documentation[2] to
|
||||
make it easier for users to correlate the pins with functions when using
|
||||
utilities such as gpioinfo.
|
||||
|
||||
[1] https://wiki.radxa.com/RockpiS/hardware/gpio
|
||||
[2] Documentation/devicetree/bindings/gpio/gpio.txt
|
||||
|
||||
Signed-off-by: Trevor Woerner <twoerner@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20231120162232.27653-1-twoerner@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
.../boot/dts/rockchip/rk3308-rock-pi-s.dts | 58 +++++++++++++++++++
|
||||
1 file changed, 58 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
|
||||
@@ -315,3 +315,61 @@
|
||||
&wdt {
|
||||
status = "okay";
|
||||
};
|
||||
+
|
||||
+&gpio0 {
|
||||
+ gpio-line-names =
|
||||
+ /* GPIO0_A0 - A7 */
|
||||
+ "", "", "", "", "", "", "", "",
|
||||
+ /* GPIO0_B0 - B7 */
|
||||
+ "", "", "", "header1-pin3 [GPIO0_B3]", "header1-pin5 [GPIO0_B4]",
|
||||
+ "", "", "header1-pin11 [GPIO0_B7]",
|
||||
+ /* GPIO0_C0 - C7 */
|
||||
+ "header1-pin13 [GPIO0_C0]", "header1-pin15 [GPIO0_C1]", "", "", "",
|
||||
+ "", "", "",
|
||||
+ /* GPIO0_D0 - D8 */
|
||||
+ "", "", "", "", "", "", "", "";
|
||||
+};
|
||||
+
|
||||
+&gpio1 {
|
||||
+ gpio-line-names =
|
||||
+ /* GPIO1_A0 - A7 */
|
||||
+ "", "", "", "", "", "", "", "",
|
||||
+ /* GPIO1_B0 - B7 */
|
||||
+ "", "", "", "", "", "", "", "",
|
||||
+ /* GPIO1_C0 - C7 */
|
||||
+ "", "", "", "", "", "", "header1-pin21 [GPIO1_C6]",
|
||||
+ "header1-pin19 [GPIO1_C7]",
|
||||
+ /* GPIO1_D0 - D8 */
|
||||
+ "header1-pin23 [GPIO1_D0]", "header1-pin24 [GPIO1_D1]", "", "", "",
|
||||
+ "", "", "";
|
||||
+};
|
||||
+
|
||||
+&gpio2 {
|
||||
+ gpio-line-names =
|
||||
+ /* GPIO2_A0 - A7 */
|
||||
+ "header1-pin10 [GPIO2_A0]", "header1-pin8 [GPIO2_A1]", "", "",
|
||||
+ "header1-pin7 [GPIO2_A4]", "header1-pin12 [GPIO2_A5]",
|
||||
+ "header2-pin46 [GPIO2_A6]", "header1-pin22 [GPIO1_A7]",
|
||||
+ /* GPIO2_B0 - B7 */
|
||||
+ "header2-pin45 [GPIO2_B0]", "header1-pin18 [GPIO2_B1]",
|
||||
+ "header1-pin16 [GPIO2_B2]", "header2-pin44 [GPIO2_B3]",
|
||||
+ "header2-pin43 [GPIO2_B4]", "header2-pin28 [GPIO2_B5]",
|
||||
+ "header2-pin30 [GPIO2_B6]", "header2-pin32 [GPIO2_B7]",
|
||||
+ /* GPIO2_C0 - C7 */
|
||||
+ "header2-pin34 [GPIO2_C0]", "", "", "", "", "", "", "",
|
||||
+ /* GPIO2_D0 - D8 */
|
||||
+ "", "", "", "", "", "", "", "";
|
||||
+};
|
||||
+
|
||||
+&gpio3 {
|
||||
+ gpio-line-names =
|
||||
+ /* GPIO3_A0 - A7 */
|
||||
+ "", "", "", "", "", "", "", "",
|
||||
+ /* GPIO3_B0 - B7 */
|
||||
+ "", "", "header2-pin42 [GPIO3_B2]", "header2-pin41 [GPIO3_B3]",
|
||||
+ "header2-pin40 [GPIO3_B4]", "header2-pin39 [GPIO3_B5]", "", "",
|
||||
+ /* GPIO3_C0 - C7 */
|
||||
+ "", "", "", "", "", "", "", "",
|
||||
+ /* GPIO3_D0 - D8 */
|
||||
+ "", "", "", "", "", "", "", "";
|
||||
+};
|
||||
|
|
@ -0,0 +1,152 @@
|
|||
From 085021cc825ed90a6ddc4406f608fb8a85745f81 Mon Sep 17 00:00:00 2001
|
||||
From: Trevor Woerner <twoerner@gmail.com>
|
||||
Date: Tue, 19 Dec 2023 12:38:13 -0500
|
||||
Subject: [PATCH] arm64: dts: rockchip: rk3308-rock-pi-s gpio-line-names
|
||||
cleanup
|
||||
|
||||
Perform the following cleanups on a previous patch:
|
||||
- indent lines after "gpio-line-names"
|
||||
- fix D0-D8 -> D0-D7
|
||||
- sort phandle references
|
||||
|
||||
Fixes: c45de75d7a9a ("arm64: dts: rockchip: add gpio-line-names to rk3308-rock-pi-s")
|
||||
Signed-off-by: Trevor Woerner <twoerner@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20231219173814.1569-1-twoerner@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
.../boot/dts/rockchip/rk3308-rock-pi-s.dts | 120 +++++++++---------
|
||||
1 file changed, 62 insertions(+), 58 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
|
||||
@@ -166,6 +166,68 @@
|
||||
};
|
||||
};
|
||||
|
||||
+&gpio0 {
|
||||
+ gpio-line-names =
|
||||
+ /* GPIO0_A0 - A7 */
|
||||
+ "", "", "", "", "", "", "", "",
|
||||
+ /* GPIO0_B0 - B7 */
|
||||
+ "", "", "", "header1-pin3 [GPIO0_B3]",
|
||||
+ "header1-pin5 [GPIO0_B4]", "", "",
|
||||
+ "header1-pin11 [GPIO0_B7]",
|
||||
+ /* GPIO0_C0 - C7 */
|
||||
+ "header1-pin13 [GPIO0_C0]",
|
||||
+ "header1-pin15 [GPIO0_C1]", "", "", "",
|
||||
+ "", "", "",
|
||||
+ /* GPIO0_D0 - D7 */
|
||||
+ "", "", "", "", "", "", "", "";
|
||||
+};
|
||||
+
|
||||
+&gpio1 {
|
||||
+ gpio-line-names =
|
||||
+ /* GPIO1_A0 - A7 */
|
||||
+ "", "", "", "", "", "", "", "",
|
||||
+ /* GPIO1_B0 - B7 */
|
||||
+ "", "", "", "", "", "", "", "",
|
||||
+ /* GPIO1_C0 - C7 */
|
||||
+ "", "", "", "", "", "", "header1-pin21 [GPIO1_C6]",
|
||||
+ "header1-pin19 [GPIO1_C7]",
|
||||
+ /* GPIO1_D0 - D7 */
|
||||
+ "header1-pin23 [GPIO1_D0]", "header1-pin24 [GPIO1_D1]",
|
||||
+ "", "", "", "", "", "";
|
||||
+};
|
||||
+
|
||||
+&gpio2 {
|
||||
+ gpio-line-names =
|
||||
+ /* GPIO2_A0 - A7 */
|
||||
+ "header1-pin10 [GPIO2_A0]", "header1-pin8 [GPIO2_A1]",
|
||||
+ "", "",
|
||||
+ "header1-pin7 [GPIO2_A4]", "header1-pin12 [GPIO2_A5]",
|
||||
+ "header2-pin46 [GPIO2_A6]", "header1-pin22 [GPIO1_A7]",
|
||||
+ /* GPIO2_B0 - B7 */
|
||||
+ "header2-pin45 [GPIO2_B0]", "header1-pin18 [GPIO2_B1]",
|
||||
+ "header1-pin16 [GPIO2_B2]", "header2-pin44 [GPIO2_B3]",
|
||||
+ "header2-pin43 [GPIO2_B4]", "header2-pin28 [GPIO2_B5]",
|
||||
+ "header2-pin30 [GPIO2_B6]", "header2-pin32 [GPIO2_B7]",
|
||||
+ /* GPIO2_C0 - C7 */
|
||||
+ "header2-pin34 [GPIO2_C0]", "", "", "", "", "", "", "",
|
||||
+ /* GPIO2_D0 - D7 */
|
||||
+ "", "", "", "", "", "", "", "";
|
||||
+};
|
||||
+
|
||||
+&gpio3 {
|
||||
+ gpio-line-names =
|
||||
+ /* GPIO3_A0 - A7 */
|
||||
+ "", "", "", "", "", "", "", "",
|
||||
+ /* GPIO3_B0 - B7 */
|
||||
+ "", "", "header2-pin42 [GPIO3_B2]",
|
||||
+ "header2-pin41 [GPIO3_B3]", "header2-pin40 [GPIO3_B4]",
|
||||
+ "header2-pin39 [GPIO3_B5]", "", "",
|
||||
+ /* GPIO3_C0 - C7 */
|
||||
+ "", "", "", "", "", "", "", "",
|
||||
+ /* GPIO3_D0 - D7 */
|
||||
+ "", "", "", "", "", "", "", "";
|
||||
+};
|
||||
+
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -315,61 +377,3 @@
|
||||
&wdt {
|
||||
status = "okay";
|
||||
};
|
||||
-
|
||||
-&gpio0 {
|
||||
- gpio-line-names =
|
||||
- /* GPIO0_A0 - A7 */
|
||||
- "", "", "", "", "", "", "", "",
|
||||
- /* GPIO0_B0 - B7 */
|
||||
- "", "", "", "header1-pin3 [GPIO0_B3]", "header1-pin5 [GPIO0_B4]",
|
||||
- "", "", "header1-pin11 [GPIO0_B7]",
|
||||
- /* GPIO0_C0 - C7 */
|
||||
- "header1-pin13 [GPIO0_C0]", "header1-pin15 [GPIO0_C1]", "", "", "",
|
||||
- "", "", "",
|
||||
- /* GPIO0_D0 - D8 */
|
||||
- "", "", "", "", "", "", "", "";
|
||||
-};
|
||||
-
|
||||
-&gpio1 {
|
||||
- gpio-line-names =
|
||||
- /* GPIO1_A0 - A7 */
|
||||
- "", "", "", "", "", "", "", "",
|
||||
- /* GPIO1_B0 - B7 */
|
||||
- "", "", "", "", "", "", "", "",
|
||||
- /* GPIO1_C0 - C7 */
|
||||
- "", "", "", "", "", "", "header1-pin21 [GPIO1_C6]",
|
||||
- "header1-pin19 [GPIO1_C7]",
|
||||
- /* GPIO1_D0 - D8 */
|
||||
- "header1-pin23 [GPIO1_D0]", "header1-pin24 [GPIO1_D1]", "", "", "",
|
||||
- "", "", "";
|
||||
-};
|
||||
-
|
||||
-&gpio2 {
|
||||
- gpio-line-names =
|
||||
- /* GPIO2_A0 - A7 */
|
||||
- "header1-pin10 [GPIO2_A0]", "header1-pin8 [GPIO2_A1]", "", "",
|
||||
- "header1-pin7 [GPIO2_A4]", "header1-pin12 [GPIO2_A5]",
|
||||
- "header2-pin46 [GPIO2_A6]", "header1-pin22 [GPIO1_A7]",
|
||||
- /* GPIO2_B0 - B7 */
|
||||
- "header2-pin45 [GPIO2_B0]", "header1-pin18 [GPIO2_B1]",
|
||||
- "header1-pin16 [GPIO2_B2]", "header2-pin44 [GPIO2_B3]",
|
||||
- "header2-pin43 [GPIO2_B4]", "header2-pin28 [GPIO2_B5]",
|
||||
- "header2-pin30 [GPIO2_B6]", "header2-pin32 [GPIO2_B7]",
|
||||
- /* GPIO2_C0 - C7 */
|
||||
- "header2-pin34 [GPIO2_C0]", "", "", "", "", "", "", "",
|
||||
- /* GPIO2_D0 - D8 */
|
||||
- "", "", "", "", "", "", "", "";
|
||||
-};
|
||||
-
|
||||
-&gpio3 {
|
||||
- gpio-line-names =
|
||||
- /* GPIO3_A0 - A7 */
|
||||
- "", "", "", "", "", "", "", "",
|
||||
- /* GPIO3_B0 - B7 */
|
||||
- "", "", "header2-pin42 [GPIO3_B2]", "header2-pin41 [GPIO3_B3]",
|
||||
- "header2-pin40 [GPIO3_B4]", "header2-pin39 [GPIO3_B5]", "", "",
|
||||
- /* GPIO3_C0 - C7 */
|
||||
- "", "", "", "", "", "", "", "",
|
||||
- /* GPIO3_D0 - D8 */
|
||||
- "", "", "", "", "", "", "", "";
|
||||
-};
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
From 100b3bdee6035192f6d4a1847970fe004bb505fb Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Tue, 21 May 2024 21:10:15 +0000
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add io-domains to rk3308-rock-pi-s
|
||||
|
||||
The VCCIO4 io-domain used for WiFi/BT is using 1v8 IO signal voltage.
|
||||
|
||||
Add io-domains node with the VCCIO supplies connected on the board.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
Link: https://lore.kernel.org/r/20240521211029.1236094-13-jonas@kwiboo.se
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts | 10 ++++++++++
|
||||
1 file changed, 10 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
|
||||
@@ -232,6 +232,16 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&io_domains {
|
||||
+ vccio0-supply = <&vcc_io>;
|
||||
+ vccio1-supply = <&vcc_io>;
|
||||
+ vccio2-supply = <&vcc_io>;
|
||||
+ vccio3-supply = <&vcc_io>;
|
||||
+ vccio4-supply = <&vcc_1v8>;
|
||||
+ vccio5-supply = <&vcc_io>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&pinctrl {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rtc_32k>;
|
||||
|
|
@ -0,0 +1,769 @@
|
|||
From ee219017ddb50be14c60d3cbe3e51ac0b2008d40 Mon Sep 17 00:00:00 2001
|
||||
From: Chukun Pan <amadeus@jmu.edu.cn>
|
||||
Date: Sun, 28 Apr 2024 20:36:18 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add Radxa ROCK 3C
|
||||
|
||||
The Radxa ROCK 3C is a development board with the
|
||||
Rockchip RK3566 SoC. It has the following features:
|
||||
|
||||
- 1/2/4GB LPDDR4
|
||||
- 1x HDMI Type A
|
||||
- 1x PCIE 2.0 slot
|
||||
- 1x FAN connector
|
||||
- 3.5mm jack with mic
|
||||
- 1GbE RTL8211F Ethernet
|
||||
- 1x USB 3.0, 3x USB 2.0
|
||||
- 40-pin expansion header
|
||||
- MicroSD card/eMMC socket
|
||||
- 16MB SPI NOR (gd25lq128d)
|
||||
- AP6256 or AIC8800 WiFi/BT
|
||||
|
||||
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
|
||||
Link: https://lore.kernel.org/r/20240428123618.72170-3-amadeus@jmu.edu.cn
|
||||
[dropped rk809-sound and not specified pmic sound properties]
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/Makefile | 1 +
|
||||
.../boot/dts/rockchip/rk3566-rock-3c.dts | 726 ++++++++++++++++++
|
||||
2 files changed, 727 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -82,6 +82,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-qu
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-cm3-io.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rock-3c.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-blade.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-model-a.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts
|
||||
@@ -0,0 +1,726 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+#include <dt-bindings/leds/common.h>
|
||||
+#include <dt-bindings/pinctrl/rockchip.h>
|
||||
+#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
+#include "rk3566.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Radxa ROCK 3C";
|
||||
+ compatible = "radxa,rock-3c", "rockchip,rk3566";
|
||||
+
|
||||
+ aliases {
|
||||
+ ethernet0 = &gmac1;
|
||||
+ mmc0 = &sdhci;
|
||||
+ mmc1 = &sdmmc0;
|
||||
+ mmc2 = &sdmmc1;
|
||||
+ };
|
||||
+
|
||||
+ chosen: chosen {
|
||||
+ stdout-path = "serial2:1500000n8";
|
||||
+ };
|
||||
+
|
||||
+ gmac1_clkin: external-gmac1-clock {
|
||||
+ compatible = "fixed-clock";
|
||||
+ clock-frequency = <125000000>;
|
||||
+ clock-output-names = "gmac1_clkin";
|
||||
+ #clock-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ hdmi-con {
|
||||
+ compatible = "hdmi-connector";
|
||||
+ type = "a";
|
||||
+
|
||||
+ port {
|
||||
+ hdmi_con_in: endpoint {
|
||||
+ remote-endpoint = <&hdmi_out_con>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+
|
||||
+ led-0 {
|
||||
+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
+ function = LED_FUNCTION_HEARTBEAT;
|
||||
+ color = <LED_COLOR_ID_BLUE>;
|
||||
+ linux,default-trigger = "heartbeat";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&user_led2>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ sdio_pwrseq: sdio-pwrseq {
|
||||
+ compatible = "mmc-pwrseq-simple";
|
||||
+ clocks = <&rk809 1>;
|
||||
+ clock-names = "ext_clock";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&wifi_reg_on_h>;
|
||||
+ post-power-on-delay-ms = <100>;
|
||||
+ power-off-delay-us = <5000000>;
|
||||
+ reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v_dcin: vcc5v-dcin-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc5v_dcin";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_pcie: vcc3v3-pcie-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pcie_pwr_en>;
|
||||
+ regulator-name = "vcc3v3_pcie";
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ vin-supply = <&vcc3v3_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_sys: vcc3v3-sys-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc3v3_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_sys: vcc5v0-sys-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc5v0_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&vcc5v_dcin>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_usb30_host: vcc5v0-usb30-host-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc5v0_usb30_host_en>;
|
||||
+ regulator-name = "vcc5v0_usb30_host";
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc5v0_usb_otg_en>;
|
||||
+ regulator-name = "vcc5v0_usb_otg";
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc_cam: vcc-cam-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc_cam_en>;
|
||||
+ regulator-name = "vcc_cam";
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ vin-supply = <&vcc3v3_sys>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_mipi: vcc-mipi-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc_mipi_en>;
|
||||
+ regulator-name = "vcc_mipi";
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ vin-supply = <&vcc3v3_sys>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&combphy1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&combphy2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&cpu0 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu1 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu2 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu3 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&gmac1 {
|
||||
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
|
||||
+ clock_in_out = "input";
|
||||
+ phy-handle = <&rgmii_phy1>;
|
||||
+ phy-mode = "rgmii-id";
|
||||
+ phy-supply = <&vcc_3v3>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&gmac1m1_miim
|
||||
+ &gmac1m1_tx_bus2
|
||||
+ &gmac1m1_rx_bus2
|
||||
+ &gmac1m1_rgmii_clk
|
||||
+ &gmac1m1_rgmii_bus
|
||||
+ &gmac1m1_clkinout>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&gpu {
|
||||
+ mali-supply = <&vdd_gpu>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&hdmi {
|
||||
+ avdd-0v9-supply = <&vdda0v9_image>;
|
||||
+ avdd-1v8-supply = <&vcca1v8_image>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&hdmi_in {
|
||||
+ hdmi_in_vp0: endpoint {
|
||||
+ remote-endpoint = <&vp0_out_hdmi>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&hdmi_out {
|
||||
+ hdmi_out_con: endpoint {
|
||||
+ remote-endpoint = <&hdmi_con_in>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&hdmi_sound {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2c0 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ vdd_cpu: regulator@1c {
|
||||
+ compatible = "tcs,tcs4525";
|
||||
+ reg = <0x1c>;
|
||||
+ fcs,suspend-voltage-selector = <1>;
|
||||
+ regulator-name = "vdd_cpu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <800000>;
|
||||
+ regulator-max-microvolt = <1150000>;
|
||||
+ regulator-ramp-delay = <2300>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rk809: pmic@20 {
|
||||
+ compatible = "rockchip,rk809";
|
||||
+ reg = <0x20>;
|
||||
+ interrupt-parent = <&gpio0>;
|
||||
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>;
|
||||
+ system-power-controller;
|
||||
+ vcc1-supply = <&vcc3v3_sys>;
|
||||
+ vcc2-supply = <&vcc3v3_sys>;
|
||||
+ vcc3-supply = <&vcc3v3_sys>;
|
||||
+ vcc4-supply = <&vcc3v3_sys>;
|
||||
+ vcc5-supply = <&vcc3v3_sys>;
|
||||
+ vcc6-supply = <&vcc3v3_sys>;
|
||||
+ vcc7-supply = <&vcc3v3_sys>;
|
||||
+ vcc8-supply = <&vcc3v3_sys>;
|
||||
+ vcc9-supply = <&vcc3v3_sys>;
|
||||
+ wakeup-source;
|
||||
+ #clock-cells = <1>;
|
||||
+
|
||||
+ regulators {
|
||||
+ vdd_logic: DCDC_REG1 {
|
||||
+ regulator-name = "vdd_logic";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ regulator-suspend-microvolt = <900000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_gpu: DCDC_REG2 {
|
||||
+ regulator-name = "vdd_gpu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ regulator-suspend-microvolt = <900000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_ddr: DCDC_REG3 {
|
||||
+ regulator-name = "vcc_ddr";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_npu: DCDC_REG4 {
|
||||
+ regulator-name = "vdd_npu";
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_1v8: DCDC_REG5 {
|
||||
+ regulator-name = "vcc_1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda0v9_image: LDO_REG1 {
|
||||
+ regulator-name = "vdda0v9_image";
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda_0v9: LDO_REG2 {
|
||||
+ regulator-name = "vdda_0v9";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda0v9_pmu: LDO_REG3 {
|
||||
+ regulator-name = "vdda0v9_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <900000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vccio_acodec: LDO_REG4 {
|
||||
+ regulator-name = "vccio_acodec";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vccio_sd: LDO_REG5 {
|
||||
+ regulator-name = "vccio_sd";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_pmu: LDO_REG6 {
|
||||
+ regulator-name = "vcc3v3_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3300000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca_1v8: LDO_REG7 {
|
||||
+ regulator-name = "vcca_1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_pmu: LDO_REG8 {
|
||||
+ regulator-name = "vcca1v8_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_image: LDO_REG9 {
|
||||
+ regulator-name = "vcca1v8_image";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_3v3: SWITCH_REG1 {
|
||||
+ regulator-name = "vcc_3v3";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_sd: SWITCH_REG2 {
|
||||
+ regulator-name = "vcc3v3_sd";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ eeprom: eeprom@50 {
|
||||
+ compatible = "belling,bl24c16a", "atmel,24c16";
|
||||
+ reg = <0x50>;
|
||||
+ pagesize = <16>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2s0_8ch {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2s1_8ch {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>;
|
||||
+ rockchip,trcm-sync-tx-only;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&mdio1 {
|
||||
+ rgmii_phy1: ethernet-phy@1 {
|
||||
+ compatible = "ethernet-phy-ieee802.3-c22";
|
||||
+ reg = <0x1>;
|
||||
+ reset-assert-us = <20000>;
|
||||
+ reset-deassert-us = <100000>;
|
||||
+ reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pcie2x1 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pcie_reset_h>;
|
||||
+ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
|
||||
+ vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ bluetooth {
|
||||
+ bt_reg_on_h: bt-reg-on-h {
|
||||
+ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ bt_wake_host_h: bt-wake-host-h {
|
||||
+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ bt_host_wake_h: bt-host-wake-h {
|
||||
+ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cam {
|
||||
+ vcc_cam_en: vcc_cam_en {
|
||||
+ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ display {
|
||||
+ vcc_mipi_en: vcc_mipi_en {
|
||||
+ rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ user_led2: user-led2 {
|
||||
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pcie {
|
||||
+ pcie_pwr_en: pcie-pwr-en {
|
||||
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ pcie_reset_h: pcie-reset-h {
|
||||
+ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pmic {
|
||||
+ pmic_int_l: pmic-int-l {
|
||||
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ usb {
|
||||
+ vcc5v0_usb30_host_en: vcc5v0-usb30-host-en {
|
||||
+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
|
||||
+ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ wifi {
|
||||
+ wifi_host_wake_h: wifi-host-wake-h {
|
||||
+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ wifi_reg_on_h: wifi-reg-on-h {
|
||||
+ rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pmu_io_domains {
|
||||
+ pmuio1-supply = <&vcc3v3_pmu>;
|
||||
+ pmuio2-supply = <&vcca1v8_pmu>;
|
||||
+ vccio1-supply = <&vccio_acodec>;
|
||||
+ vccio2-supply = <&vcc_1v8>;
|
||||
+ vccio3-supply = <&vccio_sd>;
|
||||
+ vccio4-supply = <&vcca1v8_pmu>;
|
||||
+ vccio5-supply = <&vcc_3v3>;
|
||||
+ vccio6-supply = <&vcc_3v3>;
|
||||
+ vccio7-supply = <&vcc_3v3>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&saradc {
|
||||
+ vref-supply = <&vcca_1v8>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdhci {
|
||||
+ bus-width = <8>;
|
||||
+ max-frequency = <200000000>;
|
||||
+ mmc-hs200-1_8v;
|
||||
+ non-removable;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
+ vmmc-supply = <&vcc_3v3>;
|
||||
+ vqmmc-supply = <&vcc_1v8>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdmmc0 {
|
||||
+ bus-width = <4>;
|
||||
+ cap-sd-highspeed;
|
||||
+ disable-wp;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
+ sd-uhs-sdr50;
|
||||
+ vmmc-supply = <&vcc3v3_sys>;
|
||||
+ vqmmc-supply = <&vccio_sd>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdmmc1 {
|
||||
+ bus-width = <4>;
|
||||
+ cap-sd-highspeed;
|
||||
+ cap-sdio-irq;
|
||||
+ keep-power-in-suspend;
|
||||
+ mmc-pwrseq = <&sdio_pwrseq>;
|
||||
+ non-removable;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>;
|
||||
+ sd-uhs-sdr104;
|
||||
+ vmmc-supply = <&vcc3v3_sys>;
|
||||
+ vqmmc-supply = <&vcca1v8_pmu>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sfc {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ status = "okay";
|
||||
+
|
||||
+ flash@0 {
|
||||
+ compatible = "jedec,spi-nor";
|
||||
+ reg = <0x0>;
|
||||
+ spi-max-frequency = <120000000>;
|
||||
+ spi-rx-bus-width = <4>;
|
||||
+ spi-tx-bus-width = <1>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&tsadc {
|
||||
+ rockchip,hw-tshut-mode = <1>;
|
||||
+ rockchip,hw-tshut-polarity = <0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart1 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&uart1m0_ctsn &uart1m0_rtsn &uart1m0_xfer>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_xhci {
|
||||
+ dr_mode = "host";
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_xhci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy0_host {
|
||||
+ phy-supply = <&vcc5v0_usb30_host>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy0_otg {
|
||||
+ phy-supply = <&vcc5v0_usb_otg>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy1_host {
|
||||
+ phy-supply = <&vcc5v0_usb30_host>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy1_otg {
|
||||
+ phy-supply = <&vcc5v0_usb30_host>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vop {
|
||||
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vop_mmu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vp0 {
|
||||
+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
+ remote-endpoint = <&hdmi_in_vp0>;
|
||||
+ };
|
||||
+};
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
From 06f6dd4d607766a527e37529f2f3f90dd1464293 Mon Sep 17 00:00:00 2001
|
||||
From: FUKAUMI Naoki <naoki@radxa.com>
|
||||
Date: Sun, 23 Jun 2024 11:33:29 +0900
|
||||
Subject: [PATCH] arm64: dts: rockchip: change spi-max-frequency for Radxa ROCK
|
||||
3C
|
||||
|
||||
SPI NOR flash chip may vary, so use safe(lowest) spi-max-frequency.
|
||||
|
||||
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
|
||||
Link: https://lore.kernel.org/r/20240623023329.1044-3-naoki@radxa.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts
|
||||
@@ -633,7 +633,7 @@
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
- spi-max-frequency = <120000000>;
|
||||
+ spi-max-frequency = <104000000>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-tx-bus-width = <1>;
|
||||
};
|
||||
|
|
@ -0,0 +1,657 @@
|
|||
From 1a5c8d307c83c808a32686ed51afb4bac2092d39 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Tue, 21 May 2024 20:28:05 +0000
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add Radxa ZERO 3W/3E
|
||||
|
||||
The Radxa ZERO 3W/3E is an ultra-small, high-performance single board
|
||||
computer based on the Rockchip RK3566, with a compact form factor and
|
||||
rich interfaces.
|
||||
|
||||
The ZERO 3W and ZERO 3E are basically the same size and model, but
|
||||
differ only in storage and network interfaces.
|
||||
|
||||
- eMMC (3W)
|
||||
- SD-card (both)
|
||||
- Ethernet (3E)
|
||||
- WiFi/BT (3W)
|
||||
|
||||
Add initial support for eMMC, SD-card, Ethernet, HDMI and USB.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
Link: https://lore.kernel.org/r/20240521202810.1225636-3-jonas@kwiboo.se
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/Makefile | 2 +
|
||||
.../dts/rockchip/rk3566-radxa-zero-3.dtsi | 463 ++++++++++++++++++
|
||||
.../dts/rockchip/rk3566-radxa-zero-3e.dts | 51 ++
|
||||
.../dts/rockchip/rk3566-radxa-zero-3w.dts | 91 ++++
|
||||
4 files changed, 607 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -81,6 +81,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pi
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-cm3-io.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-zero-3e.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-zero-3w.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rock-3c.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-blade.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi
|
||||
@@ -0,0 +1,463 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+#include <dt-bindings/leds/common.h>
|
||||
+#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
+#include "rk3566.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ aliases {
|
||||
+ mmc0 = &sdmmc0;
|
||||
+ };
|
||||
+
|
||||
+ chosen {
|
||||
+ stdout-path = "serial2:1500000n8";
|
||||
+ };
|
||||
+
|
||||
+ hdmi-con {
|
||||
+ compatible = "hdmi-connector";
|
||||
+ type = "d";
|
||||
+
|
||||
+ port {
|
||||
+ hdmi_con_in: endpoint {
|
||||
+ remote-endpoint = <&hdmi_out_con>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&user_led2>;
|
||||
+
|
||||
+ led-green {
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ default-state = "on";
|
||||
+ function = LED_FUNCTION_HEARTBEAT;
|
||||
+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
+ linux,default-trigger = "heartbeat";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_1v8: regulator-1v8-vcc {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc_1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ vin-supply = <&vcc_1v8_p>;
|
||||
+ };
|
||||
+
|
||||
+ vcca_1v8: regulator-1v8-vcca {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcca_1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ vin-supply = <&vcc_1v8_p>;
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_image: regulator-1v8-vcca-image {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcca1v8_image";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ vin-supply = <&vcc_1v8_p>;
|
||||
+ };
|
||||
+
|
||||
+ vcc_3v3: regulator-3v3-vcc {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc_3v3";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ vin-supply = <&vcc3v3_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc_sys: regulator-5v0-vcc-sys {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&combphy1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&cpu0 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu1 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu2 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu3 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&gpu {
|
||||
+ mali-supply = <&vdd_gpu_npu>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&hdmi {
|
||||
+ avdd-0v9-supply = <&vdda_0v9>;
|
||||
+ avdd-1v8-supply = <&vcca1v8_image>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&hdmi_in {
|
||||
+ hdmi_in_vp0: endpoint {
|
||||
+ remote-endpoint = <&vp0_out_hdmi>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&hdmi_out {
|
||||
+ hdmi_out_con: endpoint {
|
||||
+ remote-endpoint = <&hdmi_con_in>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&hdmi_sound {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2c0 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ rk817: pmic@20 {
|
||||
+ compatible = "rockchip,rk817";
|
||||
+ reg = <0x20>;
|
||||
+ #clock-cells = <1>;
|
||||
+ clock-output-names = "rk817-clkout1", "rk817-clkout2";
|
||||
+ interrupt-parent = <&gpio0>;
|
||||
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pmic_int_l>;
|
||||
+ system-power-controller;
|
||||
+ wakeup-source;
|
||||
+
|
||||
+ vcc1-supply = <&vcc_sys>;
|
||||
+ vcc2-supply = <&vcc_sys>;
|
||||
+ vcc3-supply = <&vcc_sys>;
|
||||
+ vcc4-supply = <&vcc_sys>;
|
||||
+ vcc5-supply = <&vcc_sys>;
|
||||
+ vcc6-supply = <&vcc_sys>;
|
||||
+ vcc7-supply = <&vcc_sys>;
|
||||
+ vcc8-supply = <&vcc_sys>;
|
||||
+ vcc9-supply = <&vcc5v_midu>;
|
||||
+
|
||||
+ regulators {
|
||||
+ vdd_logic: DCDC_REG1 {
|
||||
+ regulator-name = "vdd_logic";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ regulator-suspend-microvolt = <900000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_gpu_npu: DCDC_REG2 {
|
||||
+ regulator-name = "vdd_gpu_npu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_ddr: DCDC_REG3 {
|
||||
+ regulator-name = "vcc_ddr";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_sys: DCDC_REG4 {
|
||||
+ regulator-name = "vcc3v3_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3300000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_pmu: LDO_REG1 {
|
||||
+ regulator-name = "vcca1v8_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda_0v9: LDO_REG2 {
|
||||
+ regulator-name = "vdda_0v9";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda0v9_pmu: LDO_REG3 {
|
||||
+ regulator-name = "vdda0v9_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <900000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vccio_acodec: LDO_REG4 {
|
||||
+ regulator-name = "vccio_acodec";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vccio_sd: LDO_REG5 {
|
||||
+ regulator-name = "vccio_sd";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_pmu: LDO_REG6 {
|
||||
+ regulator-name = "vcc3v3_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3300000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_1v8_p: LDO_REG7 {
|
||||
+ regulator-name = "vcc_1v8_p";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc1v8_dvp: LDO_REG8 {
|
||||
+ regulator-name = "vcc1v8_dvp";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc2v8_dvp: LDO_REG9 {
|
||||
+ regulator-name = "vcc2v8_dvp";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <2800000>;
|
||||
+ regulator-max-microvolt = <2800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc5v_midu: BOOST {
|
||||
+ regulator-name = "vcc5v_midu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vbus: OTG_SWITCH {
|
||||
+ regulator-name = "vbus";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_cpu: regulator@40 {
|
||||
+ compatible = "rockchip,rk8600";
|
||||
+ reg = <0x40>;
|
||||
+ fcs,suspend-voltage-selector = <1>;
|
||||
+ regulator-name = "vdd_cpu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <712500>;
|
||||
+ regulator-max-microvolt = <1390000>;
|
||||
+ regulator-ramp-delay = <2300>;
|
||||
+ vin-supply = <&vcc_sys>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2s0_8ch {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ leds {
|
||||
+ user_led2: user-led2 {
|
||||
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pmic {
|
||||
+ pmic_int_l: pmic-int-l {
|
||||
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pmu_io_domains {
|
||||
+ pmuio1-supply = <&vcc3v3_pmu>;
|
||||
+ pmuio2-supply = <&vcca1v8_pmu>;
|
||||
+ vccio1-supply = <&vccio_acodec>;
|
||||
+ vccio2-supply = <&vcc_1v8>;
|
||||
+ vccio3-supply = <&vccio_sd>;
|
||||
+ vccio4-supply = <&vcc_1v8>;
|
||||
+ vccio5-supply = <&vcc_3v3>;
|
||||
+ vccio6-supply = <&vcc_3v3>;
|
||||
+ vccio7-supply = <&vcc_3v3>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&saradc {
|
||||
+ vref-supply = <&vcca_1v8>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdmmc0 {
|
||||
+ bus-width = <4>;
|
||||
+ cap-sd-highspeed;
|
||||
+ disable-wp;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
+ vmmc-supply = <&vcc3v3_sys>;
|
||||
+ vqmmc-supply = <&vccio_sd>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tsadc {
|
||||
+ rockchip,hw-tshut-mode = <1>;
|
||||
+ rockchip,hw-tshut-polarity = <0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_xhci {
|
||||
+ dr_mode = "peripheral";
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_xhci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy0_host {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy0_otg {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vop {
|
||||
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vop_mmu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vp0 {
|
||||
+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
+ remote-endpoint = <&hdmi_in_vp0>;
|
||||
+ };
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts
|
||||
@@ -0,0 +1,51 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+#include "rk3566-radxa-zero-3.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Radxa ZERO 3E";
|
||||
+ compatible = "radxa,zero-3e", "rockchip,rk3566";
|
||||
+
|
||||
+ aliases {
|
||||
+ ethernet0 = &gmac1;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&gmac1 {
|
||||
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
|
||||
+ clock_in_out = "input";
|
||||
+ phy-handle = <&rgmii_phy1>;
|
||||
+ phy-mode = "rgmii-id";
|
||||
+ phy-supply = <&vcc_3v3>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&gmac1m1_miim
|
||||
+ &gmac1m1_tx_bus2
|
||||
+ &gmac1m1_rx_bus2
|
||||
+ &gmac1m1_rgmii_clk
|
||||
+ &gmac1m1_rgmii_bus
|
||||
+ &gmac1m1_clkinout>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&mdio1 {
|
||||
+ rgmii_phy1: ethernet-phy@1 {
|
||||
+ compatible = "ethernet-phy-ieee802.3-c22";
|
||||
+ reg = <1>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&gmac1_rstn>;
|
||||
+ reset-assert-us = <20000>;
|
||||
+ reset-deassert-us = <50000>;
|
||||
+ reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ gmac1 {
|
||||
+ gmac1_rstn: gmac1-rstn {
|
||||
+ rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts
|
||||
@@ -0,0 +1,91 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+#include "rk3566-radxa-zero-3.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Radxa ZERO 3W";
|
||||
+ compatible = "radxa,zero-3w", "rockchip,rk3566";
|
||||
+
|
||||
+ aliases {
|
||||
+ mmc1 = &sdhci;
|
||||
+ mmc2 = &sdmmc1;
|
||||
+ };
|
||||
+
|
||||
+ sdio_pwrseq: sdio-pwrseq {
|
||||
+ compatible = "mmc-pwrseq-simple";
|
||||
+ clocks = <&rk817 1>;
|
||||
+ clock-names = "ext_clock";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&wifi_reg_on_h>;
|
||||
+ post-power-on-delay-ms = <100>;
|
||||
+ power-off-delay-us = <5000000>;
|
||||
+ reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ bluetooth {
|
||||
+ bt_reg_on_h: bt-reg-on-h {
|
||||
+ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ bt_wake_host_h: bt-wake-host-h {
|
||||
+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ host_wake_bt_h: host-wake-bt-h {
|
||||
+ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ wifi {
|
||||
+ wifi_reg_on_h: wifi-reg-on-h {
|
||||
+ rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ wifi_wake_host_h: wifi-wake-host-h {
|
||||
+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&sdhci {
|
||||
+ bus-width = <8>;
|
||||
+ cap-mmc-highspeed;
|
||||
+ max-frequency = <200000000>;
|
||||
+ mmc-hs200-1_8v;
|
||||
+ no-sd;
|
||||
+ no-sdio;
|
||||
+ non-removable;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
+ vmmc-supply = <&vcc_3v3>;
|
||||
+ vqmmc-supply = <&vcc_1v8>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdmmc1 {
|
||||
+ bus-width = <4>;
|
||||
+ cap-sd-highspeed;
|
||||
+ cap-sdio-irq;
|
||||
+ keep-power-in-suspend;
|
||||
+ mmc-pwrseq = <&sdio_pwrseq>;
|
||||
+ no-mmc;
|
||||
+ no-sd;
|
||||
+ non-removable;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>;
|
||||
+ sd-uhs-sdr104;
|
||||
+ vmmc-supply = <&vcc_3v3>;
|
||||
+ vqmmc-supply = <&vcc_1v8>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart1 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
|
||||
+ uart-has-rtscts;
|
||||
+ status = "okay";
|
||||
+};
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
From 060c1950037e4c54ca4d8186a8f46269e35db901 Mon Sep 17 00:00:00 2001
|
||||
From: FUKAUMI Naoki <naoki@radxa.com>
|
||||
Date: Fri, 21 Jun 2024 07:44:35 +0900
|
||||
Subject: [PATCH] arm64: dts: rockchip: fix mmc aliases for Radxa ZERO 3E/3W
|
||||
|
||||
align with other Radxa products.
|
||||
|
||||
- mmc0 is eMMC
|
||||
- mmc1 is microSD
|
||||
|
||||
for ZERO 3E, there is no eMMC, but aliases should start at 0, so mmc0
|
||||
is microSD as exception.
|
||||
|
||||
Fixes: 1a5c8d307c83 ("arm64: dts: rockchip: Add Radxa ZERO 3W/3E")
|
||||
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
|
||||
|
||||
Changes in v3:
|
||||
- fix syntax error in rk3566-radxa-zero-3e.dts
|
||||
Changes in v2:
|
||||
- microSD is mmc0 instead of mmc1 for ZERO 3E
|
||||
|
||||
Link: https://lore.kernel.org/r/20240620224435.2752-1-naoki@radxa.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi | 4 ----
|
||||
arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts | 1 +
|
||||
arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts | 3 ++-
|
||||
3 files changed, 3 insertions(+), 5 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi
|
||||
@@ -6,10 +6,6 @@
|
||||
#include "rk3566.dtsi"
|
||||
|
||||
/ {
|
||||
- aliases {
|
||||
- mmc0 = &sdmmc0;
|
||||
- };
|
||||
-
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts
|
||||
@@ -10,6 +10,7 @@
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac1;
|
||||
+ mmc0 = &sdmmc0;
|
||||
};
|
||||
};
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts
|
||||
@@ -9,7 +9,8 @@
|
||||
compatible = "radxa,zero-3w", "rockchip,rk3566";
|
||||
|
||||
aliases {
|
||||
- mmc1 = &sdhci;
|
||||
+ mmc0 = &sdhci;
|
||||
+ mmc1 = &sdmmc0;
|
||||
mmc2 = &sdmmc1;
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,101 @@
|
|||
From f7c742cbe664ebdedc075945e75443683d1175f7 Mon Sep 17 00:00:00 2001
|
||||
From: Trevor Woerner <twoerner@gmail.com>
|
||||
Date: Wed, 19 Jun 2024 21:32:49 -0400
|
||||
Subject: [PATCH] arm64: dts: rockchip: add gpio-line-names to radxa-zero-3
|
||||
|
||||
Add names to the pins of the general-purpose expansion header as given
|
||||
in the Radxa documentation[1] following the conventions in the kernel[2]
|
||||
to make it easier for users to correlate pins with functions when using
|
||||
utilities such as 'gpioinfo'.
|
||||
|
||||
[1] https://docs.radxa.com/en/zero/zero3/hardware-design/hardware-interface
|
||||
[2] https://www.kernel.org/doc/Documentation/devicetree/bindings/gpio/gpio.txt
|
||||
|
||||
Signed-off-by: Trevor Woerner <twoerner@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20240620013301.33653-1-twoerner@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
.../dts/rockchip/rk3566-radxa-zero-3.dtsi | 72 +++++++++++++++++++
|
||||
1 file changed, 72 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi
|
||||
@@ -105,6 +105,78 @@
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
+&gpio0 {
|
||||
+ gpio-line-names =
|
||||
+ /* GPIO0_A0 - A7 */
|
||||
+ "", "", "", "", "", "", "", "",
|
||||
+ /* GPIO0_B0 - B7 */
|
||||
+ "", "", "", "", "", "", "", "",
|
||||
+ /* GPIO0_C0 - C7 */
|
||||
+ "", "", "", "", "", "", "", "",
|
||||
+ /* GPIO0_D0 - D7 */
|
||||
+ "pin-10 [GPIO0_D0]", "pin-08 [GPIO0_D1]", "",
|
||||
+ "", "", "", "", "";
|
||||
+};
|
||||
+
|
||||
+&gpio1 {
|
||||
+ gpio-line-names =
|
||||
+ /* GPIO1_A0 - A7 */
|
||||
+ "pin-03 [GPIO1_A0]", "pin-05 [GPIO1_A1]", "",
|
||||
+ "", "pin-37 [GPIO1_A4]", "",
|
||||
+ "", "",
|
||||
+ /* GPIO1_B0 - B7 */
|
||||
+ "", "", "", "", "", "", "", "",
|
||||
+ /* GPIO1_C0 - C7 */
|
||||
+ "", "", "", "", "", "", "", "",
|
||||
+ /* GPIO1_D0 - D7 */
|
||||
+ "", "", "", "", "", "", "", "";
|
||||
+};
|
||||
+
|
||||
+&gpio2 {
|
||||
+ gpio-line-names =
|
||||
+ /* GPIO2_A0 - A7 */
|
||||
+ "", "", "", "", "", "", "", "",
|
||||
+ /* GPIO2_B0 - B7 */
|
||||
+ "", "", "", "", "", "", "", "",
|
||||
+ /* GPIO2_C0 - C7 */
|
||||
+ "", "", "", "", "", "", "", "",
|
||||
+ /* GPIO2_D0 - D7 */
|
||||
+ "", "", "", "", "", "", "", "";
|
||||
+};
|
||||
+
|
||||
+&gpio3 {
|
||||
+ gpio-line-names =
|
||||
+ /* GPIO3_A0 - A7 */
|
||||
+ "", "pin-11 [GPIO3_A1]", "pin-13 [GPIO3_A2]",
|
||||
+ "pin-12 [GPIO3_A3]", "pin-35 [GPIO3_A4]", "pin-40 [GPIO3_A5]",
|
||||
+ "pin-38 [GPIO3_A6]", "pin-36 [GPIO3_A7]",
|
||||
+ /* GPIO3_B0 - B7 */
|
||||
+ "pin-15 [GPIO3_B0]", "pin-16 [GPIO3_B1]", "pin-18 [GPIO3_B2]",
|
||||
+ "pin-29 [GPIO3_B3]", "pin-31 [GPIO3_B4]", "",
|
||||
+ "", "",
|
||||
+ /* GPIO3_C0 - C7 */
|
||||
+ "", "pin-22 [GPIO3_C1]", "pin-32 [GPIO3_C2]",
|
||||
+ "pin-33 [GPIO3_C3]", "pin-07 [GPIO3_C4]", "",
|
||||
+ "", "",
|
||||
+ /* GPIO3_D0 - D7 */
|
||||
+ "", "", "", "", "", "", "", "";
|
||||
+};
|
||||
+
|
||||
+&gpio4 {
|
||||
+ gpio-line-names =
|
||||
+ /* GPIO4_A0 - A7 */
|
||||
+ "", "", "", "", "", "", "", "",
|
||||
+ /* GPIO4_B0 - B7 */
|
||||
+ "", "", "pin-27 [GPIO4_B2]",
|
||||
+ "pin-28 [GPIO4_B3]", "", "", "", "",
|
||||
+ /* GPIO4_C0 - C7 */
|
||||
+ "", "", "pin-23 [GPIO4_C2]",
|
||||
+ "pin-19 [GPIO4_C3]", "", "pin-21 [GPIO4_C5]",
|
||||
+ "pin-24 [GPIO4_C6]", "",
|
||||
+ /* GPIO4_D0 - D7 */
|
||||
+ "", "", "", "", "", "", "", "";
|
||||
+};
|
||||
+
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu_npu>;
|
||||
status = "okay";
|
||||
|
|
@ -0,0 +1,815 @@
|
|||
From 846ef7748fa9124c8eea76e2d5e833fa69b3ef7c Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Thu, 27 Jun 2024 21:17:31 +0000
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add Radxa ROCK 3B
|
||||
|
||||
The Radxa ROCK 3B is a single-board computer based on the Pico-ITX form
|
||||
factor (100mm x 75mm). Two versions of the ROCK 3B exists, a community
|
||||
version based on the RK3568 SoC and an industrial version based on the
|
||||
RK3568J SoC.
|
||||
|
||||
Add initial support for eMMC, SD-card, Ethernet, HDMI, PCIe and USB.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
Link: https://lore.kernel.org/r/20240627211737.1985549-3-jonas@kwiboo.se
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/Makefile | 1 +
|
||||
.../boot/dts/rockchip/rk3568-rock-3b.dts | 781 ++++++++++++++++++
|
||||
2 files changed, 782 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -101,6 +101,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-od
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3b.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-io.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
|
||||
@@ -0,0 +1,781 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+#include <dt-bindings/leds/common.h>
|
||||
+#include <dt-bindings/pinctrl/rockchip.h>
|
||||
+#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
+#include "rk3568.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Radxa ROCK 3B";
|
||||
+ compatible = "radxa,rock-3b", "rockchip,rk3568";
|
||||
+
|
||||
+ aliases {
|
||||
+ ethernet0 = &gmac0;
|
||||
+ ethernet1 = &gmac1;
|
||||
+ mmc0 = &sdhci;
|
||||
+ mmc1 = &sdmmc0;
|
||||
+ mmc2 = &sdmmc2;
|
||||
+ };
|
||||
+
|
||||
+ chosen {
|
||||
+ stdout-path = "serial2:1500000n8";
|
||||
+ };
|
||||
+
|
||||
+ hdmi-con {
|
||||
+ compatible = "hdmi-connector";
|
||||
+ type = "a";
|
||||
+
|
||||
+ port {
|
||||
+ hdmi_con_in: endpoint {
|
||||
+ remote-endpoint = <&hdmi_out_con>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ ir-receiver {
|
||||
+ compatible = "gpio-ir-receiver";
|
||||
+ gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pwm3_ir>;
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&led>;
|
||||
+
|
||||
+ led-0 {
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ default-state = "on";
|
||||
+ function = LED_FUNCTION_HEARTBEAT;
|
||||
+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
+ linux,default-trigger = "heartbeat";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ /* pi6c pcie clock generator */
|
||||
+ vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pcie_pwren_h>;
|
||||
+ regulator-name = "vcc3v3_pi6c_03";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ startup-delay-us = <10000>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_sys: regulator-3v3-vcc-sys {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc3v3_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_sys2: regulator-3v3-vcc-sys2 {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc3v3_sys2";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_sys: regulator-5v0-vcc-sys {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc5v0_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_usb_host: regulator-5v0-vcc-usb-host {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&usb_host_pwren_h>;
|
||||
+ regulator-name = "vcc5v0_usb_host";
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_usb_otg: regulator-5v0-vcc-usb-otg {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&usb_otg_pwren_h>;
|
||||
+ regulator-name = "vcc5v0_usb_otg";
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ };
|
||||
+
|
||||
+ sdio_pwrseq: sdio-pwrseq {
|
||||
+ compatible = "mmc-pwrseq-simple";
|
||||
+ clocks = <&rk809 1>;
|
||||
+ clock-names = "ext_clock";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&wifi_reg_on_h>;
|
||||
+ post-power-on-delay-ms = <100>;
|
||||
+ power-off-delay-us = <5000000>;
|
||||
+ reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+
|
||||
+ sound {
|
||||
+ compatible = "simple-audio-card";
|
||||
+ simple-audio-card,format = "i2s";
|
||||
+ simple-audio-card,name = "Analog RK809";
|
||||
+ simple-audio-card,mclk-fs = <256>;
|
||||
+
|
||||
+ simple-audio-card,cpu {
|
||||
+ sound-dai = <&i2s1_8ch>;
|
||||
+ };
|
||||
+
|
||||
+ simple-audio-card,codec {
|
||||
+ sound-dai = <&rk809>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&combphy0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&combphy1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&combphy2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&cpu0 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu1 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu2 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu3 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&gmac0 {
|
||||
+ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
|
||||
+ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
|
||||
+ clock_in_out = "input";
|
||||
+ phy-handle = <&rgmii_phy0>;
|
||||
+ phy-mode = "rgmii-id";
|
||||
+ phy-supply = <&vcc_3v3>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&gmac0_miim
|
||||
+ &gmac0_tx_bus2
|
||||
+ &gmac0_rx_bus2
|
||||
+ &gmac0_rgmii_clk
|
||||
+ &gmac0_rgmii_bus
|
||||
+ &gmac0_clkinout>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&gmac1 {
|
||||
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
|
||||
+ clock_in_out = "input";
|
||||
+ phy-handle = <&rgmii_phy1>;
|
||||
+ phy-mode = "rgmii-id";
|
||||
+ phy-supply = <&vcc_3v3>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&gmac1m1_miim
|
||||
+ &gmac1m1_tx_bus2
|
||||
+ &gmac1m1_rx_bus2
|
||||
+ &gmac1m1_rgmii_clk
|
||||
+ &gmac1m1_rgmii_bus
|
||||
+ &gmac1m1_clkinout>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&gpu {
|
||||
+ mali-supply = <&vdd_gpu>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&hdmi {
|
||||
+ avdd-0v9-supply = <&vdda0v9_image>;
|
||||
+ avdd-1v8-supply = <&vcca1v8_image>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&hdmi_in {
|
||||
+ hdmi_in_vp0: endpoint {
|
||||
+ remote-endpoint = <&vp0_out_hdmi>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&hdmi_out {
|
||||
+ hdmi_out_con: endpoint {
|
||||
+ remote-endpoint = <&hdmi_con_in>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&hdmi_sound {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2c0 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ vdd_cpu: regulator@1c {
|
||||
+ compatible = "tcs,tcs4525";
|
||||
+ reg = <0x1c>;
|
||||
+ fcs,suspend-voltage-selector = <1>;
|
||||
+ regulator-name = "vdd_cpu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <800000>;
|
||||
+ regulator-max-microvolt = <1150000>;
|
||||
+ regulator-ramp-delay = <2300>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rk809: pmic@20 {
|
||||
+ compatible = "rockchip,rk809";
|
||||
+ reg = <0x20>;
|
||||
+ assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
|
||||
+ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
|
||||
+ #clock-cells = <1>;
|
||||
+ clocks = <&cru I2S1_MCLKOUT_TX>;
|
||||
+ clock-names = "mclk";
|
||||
+ clock-output-names = "rk809-clkout1", "rk809-clkout2";
|
||||
+ interrupt-parent = <&gpio0>;
|
||||
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>;
|
||||
+ #sound-dai-cells = <0>;
|
||||
+ system-power-controller;
|
||||
+ wakeup-source;
|
||||
+
|
||||
+ vcc1-supply = <&vcc3v3_sys>;
|
||||
+ vcc2-supply = <&vcc3v3_sys>;
|
||||
+ vcc3-supply = <&vcc3v3_sys>;
|
||||
+ vcc4-supply = <&vcc3v3_sys>;
|
||||
+ vcc5-supply = <&vcc3v3_sys>;
|
||||
+ vcc6-supply = <&vcc3v3_sys>;
|
||||
+ vcc7-supply = <&vcc3v3_sys>;
|
||||
+ vcc8-supply = <&vcc3v3_sys>;
|
||||
+ vcc9-supply = <&vcc3v3_sys>;
|
||||
+
|
||||
+ regulators {
|
||||
+ vdd_logic: DCDC_REG1 {
|
||||
+ regulator-name = "vdd_logic";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_gpu: DCDC_REG2 {
|
||||
+ regulator-name = "vdd_gpu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_ddr: DCDC_REG3 {
|
||||
+ regulator-name = "vcc_ddr";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_npu: DCDC_REG4 {
|
||||
+ regulator-name = "vdd_npu";
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_1v8: DCDC_REG5 {
|
||||
+ regulator-name = "vcc_1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda0v9_image: LDO_REG1 {
|
||||
+ regulator-name = "vdda0v9_image";
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda_0v9: LDO_REG2 {
|
||||
+ regulator-name = "vdda_0v9";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda0v9_pmu: LDO_REG3 {
|
||||
+ regulator-name = "vdda0v9_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <900000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vccio_acodec: LDO_REG4 {
|
||||
+ regulator-name = "vccio_acodec";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vccio_sd: LDO_REG5 {
|
||||
+ regulator-name = "vccio_sd";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_pmu: LDO_REG6 {
|
||||
+ regulator-name = "vcc3v3_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3300000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca_1v8: LDO_REG7 {
|
||||
+ regulator-name = "vcca_1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_pmu: LDO_REG8 {
|
||||
+ regulator-name = "vcca1v8_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_image: LDO_REG9 {
|
||||
+ regulator-name = "vcca1v8_image";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_3v3: SWITCH_REG1 {
|
||||
+ regulator-name = "vcc_3v3";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_sd: SWITCH_REG2 {
|
||||
+ regulator-name = "vcc3v3_sd";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2c5 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ hym8563: rtc@51 {
|
||||
+ compatible = "haoyu,hym8563";
|
||||
+ reg = <0x51>;
|
||||
+ interrupt-parent = <&gpio0>;
|
||||
+ interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ #clock-cells = <0>;
|
||||
+ clock-output-names = "rtcic_32kout";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&rtcic_int_l>;
|
||||
+ wakeup-source;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2s0_8ch {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2s1_8ch {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&i2s1m0_sclktx
|
||||
+ &i2s1m0_lrcktx
|
||||
+ &i2s1m0_sdi0
|
||||
+ &i2s1m0_sdo0>;
|
||||
+ rockchip,trcm-sync-tx-only;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&mdio0 {
|
||||
+ rgmii_phy0: ethernet-phy@1 {
|
||||
+ compatible = "ethernet-phy-ieee802.3-c22";
|
||||
+ reg = <1>;
|
||||
+ reset-assert-us = <20000>;
|
||||
+ reset-deassert-us = <50000>;
|
||||
+ reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&mdio1 {
|
||||
+ rgmii_phy1: ethernet-phy@1 {
|
||||
+ compatible = "ethernet-phy-ieee802.3-c22";
|
||||
+ reg = <1>;
|
||||
+ reset-assert-us = <20000>;
|
||||
+ reset-deassert-us = <50000>;
|
||||
+ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pcie2x1 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pcie20m1_pins>;
|
||||
+ reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
|
||||
+ vpcie3v3-supply = <&vcc3v3_sys2>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pcie30phy {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pcie3x2 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pcie30x2m1_pins>;
|
||||
+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ bluetooth {
|
||||
+ bt_reg_on_h: bt-reg-on-h {
|
||||
+ rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ bt_wake_host_h: bt-wake-host-h {
|
||||
+ rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ host_wake_bt_h: host-wake-bt-h {
|
||||
+ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ ir-receiver {
|
||||
+ pwm3_ir: pwm3-ir {
|
||||
+ rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ led: led {
|
||||
+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pcie {
|
||||
+ pcie_pwren_h: pcie-pwren-h {
|
||||
+ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pcie20 {
|
||||
+ pcie20m1_pins: pcie20m1-pins {
|
||||
+ rockchip,pins =
|
||||
+ <2 RK_PD0 4 &pcfg_pull_none>,
|
||||
+ <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>,
|
||||
+ <2 RK_PD1 4 &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pcie30x2 {
|
||||
+ pcie30x2m1_pins: pcie30x2m1-pins {
|
||||
+ rockchip,pins =
|
||||
+ <2 RK_PD4 4 &pcfg_pull_none>,
|
||||
+ <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>,
|
||||
+ <2 RK_PD5 4 &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pmic {
|
||||
+ pmic_int_l: pmic-int-l {
|
||||
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rtc {
|
||||
+ rtcic_int_l: rtcic-int-l {
|
||||
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ usb {
|
||||
+ usb_host_pwren_h: usb-host-pwren-h {
|
||||
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ usb_otg_pwren_h: usb-otg-pwren-h {
|
||||
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ wifi {
|
||||
+ wifi_reg_on_h: wifi-reg-on-h {
|
||||
+ rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ wifi_wake_host_h: wifi-wake-host-h {
|
||||
+ rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pmu_io_domains {
|
||||
+ pmuio1-supply = <&vcc3v3_pmu>;
|
||||
+ pmuio2-supply = <&vcc3v3_pmu>;
|
||||
+ vccio1-supply = <&vccio_acodec>;
|
||||
+ vccio2-supply = <&vcc_1v8>;
|
||||
+ vccio3-supply = <&vccio_sd>;
|
||||
+ vccio4-supply = <&vcc_1v8>;
|
||||
+ vccio5-supply = <&vcc_3v3>;
|
||||
+ vccio6-supply = <&vcc_1v8>;
|
||||
+ vccio7-supply = <&vcc_3v3>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&saradc {
|
||||
+ vref-supply = <&vcca_1v8>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdhci {
|
||||
+ bus-width = <8>;
|
||||
+ cap-mmc-highspeed;
|
||||
+ max-frequency = <200000000>;
|
||||
+ mmc-hs200-1_8v;
|
||||
+ non-removable;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
+ vmmc-supply = <&vcc_3v3>;
|
||||
+ vqmmc-supply = <&vcc_1v8>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdmmc0 {
|
||||
+ bus-width = <4>;
|
||||
+ cap-sd-highspeed;
|
||||
+ disable-wp;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
+ vmmc-supply = <&vcc3v3_sd>;
|
||||
+ vqmmc-supply = <&vccio_sd>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdmmc2 {
|
||||
+ bus-width = <4>;
|
||||
+ cap-sd-highspeed;
|
||||
+ cap-sdio-irq;
|
||||
+ keep-power-in-suspend;
|
||||
+ mmc-pwrseq = <&sdio_pwrseq>;
|
||||
+ non-removable;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_clk &sdmmc2m0_cmd>;
|
||||
+ sd-uhs-sdr104;
|
||||
+ vmmc-supply = <&vcc3v3_sys2>;
|
||||
+ vqmmc-supply = <&vcc_1v8>;
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&sfc {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ status = "okay";
|
||||
+
|
||||
+ flash@0 {
|
||||
+ compatible = "jedec,spi-nor";
|
||||
+ reg = <0>;
|
||||
+ spi-max-frequency = <104000000>;
|
||||
+ spi-rx-bus-width = <4>;
|
||||
+ spi-tx-bus-width = <1>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&tsadc {
|
||||
+ rockchip,hw-tshut-mode = <1>;
|
||||
+ rockchip,hw-tshut-polarity = <0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart8 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn &uart8m0_rtsn>;
|
||||
+ uart-has-rtscts;
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_xhci {
|
||||
+ extcon = <&usb2phy0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_xhci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy0_host {
|
||||
+ phy-supply = <&vcc5v0_usb_host>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy0_otg {
|
||||
+ phy-supply = <&vcc5v0_usb_otg>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy1_otg {
|
||||
+ phy-supply = <&vcc5v0_usb_host>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vop {
|
||||
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vop_mmu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vp0 {
|
||||
+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
+ remote-endpoint = <&hdmi_in_vp0>;
|
||||
+ };
|
||||
+};
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
From 626a479873b6a680b3227c4852bde4a1f2c17fdf Mon Sep 17 00:00:00 2001
|
||||
From: Chukun Pan <amadeus@jmu.edu.cn>
|
||||
Date: Fri, 19 Apr 2024 18:30:19 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: correct the model name for Radxa ROCK
|
||||
3A
|
||||
|
||||
According to https://radxa.com/products/rock3/3a,
|
||||
the name of this board should be "Radxa ROCK 3A".
|
||||
|
||||
Suggested-by: FUKAUMI Naoki <naoki@radxa.com>
|
||||
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
|
||||
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
|
||||
Link: https://lore.kernel.org/r/20240419103019.992586-3-amadeus@jmu.edu.cn
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
|
||||
@@ -8,7 +8,7 @@
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
- model = "Radxa ROCK3 Model A";
|
||||
+ model = "Radxa ROCK 3A";
|
||||
compatible = "radxa,rock3a", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
|
|
@ -0,0 +1,291 @@
|
|||
From dcf4fef6631c302f9bdd188979fe3172e47a29c7 Mon Sep 17 00:00:00 2001
|
||||
From: Aurelien Jarno <aurelien@aurel32.net>
|
||||
Date: Tue, 30 Jul 2024 17:11:04 +0100
|
||||
Subject: [PATCH] hwrng: rockchip - add hwrng driver for Rockchip RK3568 SoC
|
||||
|
||||
Rockchip SoCs used to have a random number generator as part of their
|
||||
crypto device, and support for it has to be added to the corresponding
|
||||
driver. However newer Rockchip SoCs like the RK3568 have an independent
|
||||
True Random Number Generator device. This patch adds a driver for it,
|
||||
greatly inspired from the downstream driver.
|
||||
|
||||
The TRNG device does not seem to have a signal conditionner and the FIPS
|
||||
140-2 test returns a lot of failures. They can be reduced by increasing
|
||||
RK_RNG_SAMPLE_CNT, in a tradeoff between quality and speed. This value
|
||||
has been adjusted to get ~90% of successes and the quality value has
|
||||
been set accordingly.
|
||||
|
||||
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
|
||||
[daniel@makrotpia.org: code style fixes]
|
||||
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
||||
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
|
||||
---
|
||||
MAINTAINERS | 1 +
|
||||
drivers/char/hw_random/Kconfig | 14 ++
|
||||
drivers/char/hw_random/Makefile | 1 +
|
||||
drivers/char/hw_random/rockchip-rng.c | 227 ++++++++++++++++++++++++++
|
||||
4 files changed, 243 insertions(+)
|
||||
create mode 100644 drivers/char/hw_random/rockchip-rng.c
|
||||
|
||||
--- a/drivers/char/hw_random/Kconfig
|
||||
+++ b/drivers/char/hw_random/Kconfig
|
||||
@@ -573,6 +573,20 @@ config HW_RANDOM_JH7110
|
||||
To compile this driver as a module, choose M here.
|
||||
The module will be called jh7110-trng.
|
||||
|
||||
+config HW_RANDOM_ROCKCHIP
|
||||
+ tristate "Rockchip True Random Number Generator"
|
||||
+ depends on HW_RANDOM && (ARCH_ROCKCHIP || COMPILE_TEST)
|
||||
+ depends on HAS_IOMEM
|
||||
+ default HW_RANDOM
|
||||
+ help
|
||||
+ This driver provides kernel-side support for the True Random Number
|
||||
+ Generator hardware found on some Rockchip SoC like RK3566 or RK3568.
|
||||
+
|
||||
+ To compile this driver as a module, choose M here: the
|
||||
+ module will be called rockchip-rng.
|
||||
+
|
||||
+ If unsure, say Y.
|
||||
+
|
||||
endif # HW_RANDOM
|
||||
|
||||
config UML_RANDOM
|
||||
--- a/drivers/char/hw_random/Makefile
|
||||
+++ b/drivers/char/hw_random/Makefile
|
||||
@@ -48,4 +48,5 @@ obj-$(CONFIG_HW_RANDOM_XIPHERA) += xiphe
|
||||
obj-$(CONFIG_HW_RANDOM_ARM_SMCCC_TRNG) += arm_smccc_trng.o
|
||||
obj-$(CONFIG_HW_RANDOM_CN10K) += cn10k-rng.o
|
||||
obj-$(CONFIG_HW_RANDOM_POLARFIRE_SOC) += mpfs-rng.o
|
||||
+obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o
|
||||
obj-$(CONFIG_HW_RANDOM_JH7110) += jh7110-trng.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/char/hw_random/rockchip-rng.c
|
||||
@@ -0,0 +1,227 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0
|
||||
+/*
|
||||
+ * rockchip-rng.c True Random Number Generator driver for Rockchip RK3568 SoC
|
||||
+ *
|
||||
+ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd.
|
||||
+ * Copyright (c) 2022, Aurelien Jarno
|
||||
+ * Authors:
|
||||
+ * Lin Jinhan <troy.lin@rock-chips.com>
|
||||
+ * Aurelien Jarno <aurelien@aurel32.net>
|
||||
+ */
|
||||
+#include <linux/clk.h>
|
||||
+#include <linux/hw_random.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/iopoll.h>
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/of.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/pm_runtime.h>
|
||||
+#include <linux/reset.h>
|
||||
+#include <linux/slab.h>
|
||||
+
|
||||
+#define RK_RNG_AUTOSUSPEND_DELAY 100
|
||||
+#define RK_RNG_MAX_BYTE 32
|
||||
+#define RK_RNG_POLL_PERIOD_US 100
|
||||
+#define RK_RNG_POLL_TIMEOUT_US 10000
|
||||
+
|
||||
+/*
|
||||
+ * TRNG collects osc ring output bit every RK_RNG_SAMPLE_CNT time. The value is
|
||||
+ * a tradeoff between speed and quality and has been adjusted to get a quality
|
||||
+ * of ~900 (~87.5% of FIPS 140-2 successes).
|
||||
+ */
|
||||
+#define RK_RNG_SAMPLE_CNT 1000
|
||||
+
|
||||
+/* TRNG registers from RK3568 TRM-Part2, section 5.4.1 */
|
||||
+#define TRNG_RST_CTL 0x0004
|
||||
+#define TRNG_RNG_CTL 0x0400
|
||||
+#define TRNG_RNG_CTL_LEN_64_BIT (0x00 << 4)
|
||||
+#define TRNG_RNG_CTL_LEN_128_BIT (0x01 << 4)
|
||||
+#define TRNG_RNG_CTL_LEN_192_BIT (0x02 << 4)
|
||||
+#define TRNG_RNG_CTL_LEN_256_BIT (0x03 << 4)
|
||||
+#define TRNG_RNG_CTL_OSC_RING_SPEED_0 (0x00 << 2)
|
||||
+#define TRNG_RNG_CTL_OSC_RING_SPEED_1 (0x01 << 2)
|
||||
+#define TRNG_RNG_CTL_OSC_RING_SPEED_2 (0x02 << 2)
|
||||
+#define TRNG_RNG_CTL_OSC_RING_SPEED_3 (0x03 << 2)
|
||||
+#define TRNG_RNG_CTL_MASK GENMASK(15, 0)
|
||||
+#define TRNG_RNG_CTL_ENABLE BIT(1)
|
||||
+#define TRNG_RNG_CTL_START BIT(0)
|
||||
+#define TRNG_RNG_SAMPLE_CNT 0x0404
|
||||
+#define TRNG_RNG_DOUT 0x0410
|
||||
+
|
||||
+struct rk_rng {
|
||||
+ struct hwrng rng;
|
||||
+ void __iomem *base;
|
||||
+ struct reset_control *rst;
|
||||
+ int clk_num;
|
||||
+ struct clk_bulk_data *clk_bulks;
|
||||
+};
|
||||
+
|
||||
+/* The mask in the upper 16 bits determines the bits that are updated */
|
||||
+static void rk_rng_write_ctl(struct rk_rng *rng, u32 val, u32 mask)
|
||||
+{
|
||||
+ writel((mask << 16) | val, rng->base + TRNG_RNG_CTL);
|
||||
+}
|
||||
+
|
||||
+static int rk_rng_init(struct hwrng *rng)
|
||||
+{
|
||||
+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
|
||||
+ int ret;
|
||||
+
|
||||
+ /* start clocks */
|
||||
+ ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks);
|
||||
+ if (ret < 0) {
|
||||
+ dev_err((struct device *) rk_rng->rng.priv,
|
||||
+ "Failed to enable clks %d\n", ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ /* set the sample period */
|
||||
+ writel(RK_RNG_SAMPLE_CNT, rk_rng->base + TRNG_RNG_SAMPLE_CNT);
|
||||
+
|
||||
+ /* set osc ring speed and enable it */
|
||||
+ rk_rng_write_ctl(rk_rng, TRNG_RNG_CTL_LEN_256_BIT |
|
||||
+ TRNG_RNG_CTL_OSC_RING_SPEED_0 |
|
||||
+ TRNG_RNG_CTL_ENABLE,
|
||||
+ TRNG_RNG_CTL_MASK);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static void rk_rng_cleanup(struct hwrng *rng)
|
||||
+{
|
||||
+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
|
||||
+
|
||||
+ /* stop TRNG */
|
||||
+ rk_rng_write_ctl(rk_rng, 0, TRNG_RNG_CTL_MASK);
|
||||
+
|
||||
+ /* stop clocks */
|
||||
+ clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);
|
||||
+}
|
||||
+
|
||||
+static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
|
||||
+{
|
||||
+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
|
||||
+ size_t to_read = min_t(size_t, max, RK_RNG_MAX_BYTE);
|
||||
+ u32 reg;
|
||||
+ int ret = 0;
|
||||
+
|
||||
+ ret = pm_runtime_resume_and_get((struct device *) rk_rng->rng.priv);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+
|
||||
+ /* Start collecting random data */
|
||||
+ rk_rng_write_ctl(rk_rng, TRNG_RNG_CTL_START, TRNG_RNG_CTL_START);
|
||||
+
|
||||
+ ret = readl_poll_timeout(rk_rng->base + TRNG_RNG_CTL, reg,
|
||||
+ !(reg & TRNG_RNG_CTL_START),
|
||||
+ RK_RNG_POLL_PERIOD_US,
|
||||
+ RK_RNG_POLL_TIMEOUT_US);
|
||||
+ if (ret < 0)
|
||||
+ goto out;
|
||||
+
|
||||
+ /* Read random data stored in the registers */
|
||||
+ memcpy_fromio(buf, rk_rng->base + TRNG_RNG_DOUT, to_read);
|
||||
+out:
|
||||
+ pm_runtime_mark_last_busy((struct device *) rk_rng->rng.priv);
|
||||
+ pm_runtime_put_sync_autosuspend((struct device *) rk_rng->rng.priv);
|
||||
+
|
||||
+ return (ret < 0) ? ret : to_read;
|
||||
+}
|
||||
+
|
||||
+static int rk_rng_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct device *dev = &pdev->dev;
|
||||
+ struct rk_rng *rk_rng;
|
||||
+ int ret;
|
||||
+
|
||||
+ rk_rng = devm_kzalloc(dev, sizeof(*rk_rng), GFP_KERNEL);
|
||||
+ if (!rk_rng)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ rk_rng->base = devm_platform_ioremap_resource(pdev, 0);
|
||||
+ if (IS_ERR(rk_rng->base))
|
||||
+ return PTR_ERR(rk_rng->base);
|
||||
+
|
||||
+ rk_rng->clk_num = devm_clk_bulk_get_all(dev, &rk_rng->clk_bulks);
|
||||
+ if (rk_rng->clk_num < 0)
|
||||
+ return dev_err_probe(dev, rk_rng->clk_num,
|
||||
+ "Failed to get clks property\n");
|
||||
+
|
||||
+ rk_rng->rst = devm_reset_control_array_get_exclusive(&pdev->dev);
|
||||
+ if (IS_ERR(rk_rng->rst))
|
||||
+ return dev_err_probe(dev, PTR_ERR(rk_rng->rst),
|
||||
+ "Failed to get reset property\n");
|
||||
+
|
||||
+ reset_control_assert(rk_rng->rst);
|
||||
+ udelay(2);
|
||||
+ reset_control_deassert(rk_rng->rst);
|
||||
+
|
||||
+ platform_set_drvdata(pdev, rk_rng);
|
||||
+
|
||||
+ rk_rng->rng.name = dev_driver_string(dev);
|
||||
+ if (!IS_ENABLED(CONFIG_PM)) {
|
||||
+ rk_rng->rng.init = rk_rng_init;
|
||||
+ rk_rng->rng.cleanup = rk_rng_cleanup;
|
||||
+ }
|
||||
+ rk_rng->rng.read = rk_rng_read;
|
||||
+ rk_rng->rng.priv = (unsigned long) dev;
|
||||
+ rk_rng->rng.quality = 900;
|
||||
+
|
||||
+ pm_runtime_set_autosuspend_delay(dev, RK_RNG_AUTOSUSPEND_DELAY);
|
||||
+ pm_runtime_use_autosuspend(dev);
|
||||
+ devm_pm_runtime_enable(dev);
|
||||
+
|
||||
+ ret = devm_hwrng_register(dev, &rk_rng->rng);
|
||||
+ if (ret)
|
||||
+ return dev_err_probe(&pdev->dev, ret, "Failed to register Rockchip hwrng\n");
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int __maybe_unused rk_rng_runtime_suspend(struct device *dev)
|
||||
+{
|
||||
+ struct rk_rng *rk_rng = dev_get_drvdata(dev);
|
||||
+
|
||||
+ rk_rng_cleanup(&rk_rng->rng);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int __maybe_unused rk_rng_runtime_resume(struct device *dev)
|
||||
+{
|
||||
+ struct rk_rng *rk_rng = dev_get_drvdata(dev);
|
||||
+
|
||||
+ return rk_rng_init(&rk_rng->rng);
|
||||
+}
|
||||
+
|
||||
+static const struct dev_pm_ops rk_rng_pm_ops = {
|
||||
+ SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend,
|
||||
+ rk_rng_runtime_resume, NULL)
|
||||
+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
||||
+ pm_runtime_force_resume)
|
||||
+};
|
||||
+
|
||||
+static const struct of_device_id rk_rng_dt_match[] = {
|
||||
+ { .compatible = "rockchip,rk3568-rng", },
|
||||
+ { /* sentinel */ },
|
||||
+};
|
||||
+
|
||||
+MODULE_DEVICE_TABLE(of, rk_rng_dt_match);
|
||||
+
|
||||
+static struct platform_driver rk_rng_driver = {
|
||||
+ .driver = {
|
||||
+ .name = "rockchip-rng",
|
||||
+ .pm = &rk_rng_pm_ops,
|
||||
+ .of_match_table = rk_rng_dt_match,
|
||||
+ },
|
||||
+ .probe = rk_rng_probe,
|
||||
+};
|
||||
+
|
||||
+module_platform_driver(rk_rng_driver);
|
||||
+
|
||||
+MODULE_DESCRIPTION("Rockchip RK3568 True Random Number Generator driver");
|
||||
+MODULE_AUTHOR("Lin Jinhan <troy.lin@rock-chips.com>");
|
||||
+MODULE_AUTHOR("Aurelien Jarno <aurelien@aurel32.net>");
|
||||
+MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
|
||||
+MODULE_LICENSE("GPL");
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
From afeccc4084963aaa932931b734c8def55613c483 Mon Sep 17 00:00:00 2001
|
||||
From: Aurelien Jarno <aurelien@aurel32.net>
|
||||
Date: Tue, 30 Jul 2024 17:11:44 +0100
|
||||
Subject: [PATCH] arm64: dts: rockchip: add DT entry for RNG to RK356x
|
||||
|
||||
Include the just added Rockchip RNG driver for RK356x SoCs and
|
||||
enable it on RK3568.
|
||||
|
||||
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
|
||||
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
||||
Link: https://lore.kernel.org/r/d2beb15377dc8b580ca5557b1a4a6f50b74055aa.1722355365.git.daniel@makrotopia.org
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 4 ++++
|
||||
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 10 ++++++++++
|
||||
2 files changed, 14 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
@@ -257,6 +257,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
+&rng {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&usb_host0_xhci {
|
||||
phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
|
||||
phy-names = "usb2-phy", "usb3-phy";
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -1106,6 +1106,16 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ rng: rng@fe388000 {
|
||||
+ compatible = "rockchip,rk3568-rng";
|
||||
+ reg = <0x0 0xfe388000 0x0 0x4000>;
|
||||
+ clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
|
||||
+ clock-names = "core", "ahb";
|
||||
+ resets = <&cru SRST_TRNG_NS>;
|
||||
+ reset-names = "reset";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
i2s0_8ch: i2s@fe400000 {
|
||||
compatible = "rockchip,rk3568-i2s-tdm";
|
||||
reg = <0x0 0xfe400000 0x0 0x1000>;
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
From ec532f3591ce6e6ed5ec6c35773a66aae118e1f0 Mon Sep 17 00:00:00 2001
|
||||
From: Heiko Stuebner <heiko@sntech.de>
|
||||
Date: Thu, 15 Aug 2024 18:25:19 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: drop obsolete reset-names from rk356x
|
||||
rng node
|
||||
|
||||
The reset-names property is not part of the binding, so drop it.
|
||||
It is also not used by the driver, so that property was likely
|
||||
a leftover from some vendor-kernel node.
|
||||
|
||||
Fixes: afeccc408496 ("arm64: dts: rockchip: add DT entry for RNG to RK356x")
|
||||
Reported-by: Rob Herring <robh@kernel.org>
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Link: https://lore.kernel.org/r/20240815162519.751193-1-heiko@sntech.de
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 1 -
|
||||
1 file changed, 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -1112,7 +1112,6 @@
|
||||
clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
|
||||
clock-names = "core", "ahb";
|
||||
resets = <&cru SRST_TRNG_NS>;
|
||||
- reset-names = "reset";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
From 8b9c12757f919157752646faf3821abf2b7d2a64 Mon Sep 17 00:00:00 2001
|
||||
From: Chukun Pan <amadeus@jmu.edu.cn>
|
||||
Date: Fri, 22 Nov 2024 15:30:05 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: add reset-names for combphy on rk3568
|
||||
|
||||
The reset-names of combphy are missing, add it.
|
||||
|
||||
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
|
||||
Fixes: fd3ac6e80497 ("dt-bindings: phy: rockchip: rk3588 has two reset lines")
|
||||
Link: https://lore.kernel.org/r/20241122073006.99309-1-amadeus@jmu.edu.cn
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 1 +
|
||||
arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 2 ++
|
||||
2 files changed, 3 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
@@ -223,6 +223,7 @@
|
||||
assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
|
||||
assigned-clock-rates = <100000000>;
|
||||
resets = <&cru SRST_PIPEPHY0>;
|
||||
+ reset-names = "phy";
|
||||
rockchip,pipe-grf = <&pipegrf>;
|
||||
rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
|
||||
#phy-cells = <1>;
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -1756,6 +1756,7 @@
|
||||
assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
|
||||
assigned-clock-rates = <100000000>;
|
||||
resets = <&cru SRST_PIPEPHY1>;
|
||||
+ reset-names = "phy";
|
||||
rockchip,pipe-grf = <&pipegrf>;
|
||||
rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
|
||||
#phy-cells = <1>;
|
||||
@@ -1772,6 +1773,7 @@
|
||||
assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
|
||||
assigned-clock-rates = <100000000>;
|
||||
resets = <&cru SRST_PIPEPHY2>;
|
||||
+ reset-names = "phy";
|
||||
rockchip,pipe-grf = <&pipegrf>;
|
||||
rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
|
||||
#phy-cells = <1>;
|
||||
|
|
@ -0,0 +1,337 @@
|
|||
From b08e2f42e86b5848add254da45b56fc672e2bced Mon Sep 17 00:00:00 2001
|
||||
From: Steven Price <steven.price@arm.com>
|
||||
Date: Wed, 2 Oct 2024 15:16:29 +0100
|
||||
Subject: [PATCH] irqchip/gic-v3-its: Share ITS tables with a non-trusted
|
||||
hypervisor
|
||||
|
||||
Within a realm guest the ITS is emulated by the host. This means the
|
||||
allocations must have been made available to the host by a call to
|
||||
set_memory_decrypted(). Introduce an allocation function which performs
|
||||
this extra call.
|
||||
|
||||
For the ITT use a custom genpool-based allocator that calls
|
||||
set_memory_decrypted() for each page allocated, but then suballocates the
|
||||
size needed for each ITT. Note that there is no mechanism implemented to
|
||||
return pages from the genpool, but it is unlikely that the peak number of
|
||||
devices will be much larger than the normal level - so this isn't expected
|
||||
to be an issue.
|
||||
|
||||
Co-developed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
|
||||
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
|
||||
Signed-off-by: Steven Price <steven.price@arm.com>
|
||||
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
|
||||
Tested-by: Will Deacon <will@kernel.org>
|
||||
Reviewed-by: Marc Zyngier <maz@kernel.org>
|
||||
Link: https://lore.kernel.org/all/20241002141630.433502-2-steven.price@arm.com
|
||||
---
|
||||
drivers/irqchip/irq-gic-v3-its.c | 138 +++++++++++++++++++++++++------
|
||||
1 file changed, 115 insertions(+), 23 deletions(-)
|
||||
|
||||
--- a/drivers/irqchip/irq-gic-v3-its.c
|
||||
+++ b/drivers/irqchip/irq-gic-v3-its.c
|
||||
@@ -12,12 +12,14 @@
|
||||
#include <linux/crash_dump.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/efi.h>
|
||||
+#include <linux/genalloc.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/iommu.h>
|
||||
#include <linux/iopoll.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/log2.h>
|
||||
+#include <linux/mem_encrypt.h>
|
||||
#include <linux/memblock.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/msi.h>
|
||||
@@ -27,6 +29,7 @@
|
||||
#include <linux/of_pci.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/percpu.h>
|
||||
+#include <linux/set_memory.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
|
||||
@@ -163,6 +166,7 @@ struct its_device {
|
||||
struct its_node *its;
|
||||
struct event_lpi_map event_map;
|
||||
void *itt;
|
||||
+ u32 itt_sz;
|
||||
u32 nr_ites;
|
||||
u32 device_id;
|
||||
bool shared;
|
||||
@@ -198,6 +202,87 @@ static DEFINE_IDA(its_vpeid_ida);
|
||||
#define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
|
||||
#define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K)
|
||||
|
||||
+static struct page *its_alloc_pages_node(int node, gfp_t gfp,
|
||||
+ unsigned int order)
|
||||
+{
|
||||
+ struct page *page;
|
||||
+ int ret = 0;
|
||||
+
|
||||
+ page = alloc_pages_node(node, gfp, order);
|
||||
+
|
||||
+ if (!page)
|
||||
+ return NULL;
|
||||
+
|
||||
+ ret = set_memory_decrypted((unsigned long)page_address(page),
|
||||
+ 1 << order);
|
||||
+ /*
|
||||
+ * If set_memory_decrypted() fails then we don't know what state the
|
||||
+ * page is in, so we can't free it. Instead we leak it.
|
||||
+ * set_memory_decrypted() will already have WARNed.
|
||||
+ */
|
||||
+ if (ret)
|
||||
+ return NULL;
|
||||
+
|
||||
+ return page;
|
||||
+}
|
||||
+
|
||||
+static struct page *its_alloc_pages(gfp_t gfp, unsigned int order)
|
||||
+{
|
||||
+ return its_alloc_pages_node(NUMA_NO_NODE, gfp, order);
|
||||
+}
|
||||
+
|
||||
+static void its_free_pages(void *addr, unsigned int order)
|
||||
+{
|
||||
+ /*
|
||||
+ * If the memory cannot be encrypted again then we must leak the pages.
|
||||
+ * set_memory_encrypted() will already have WARNed.
|
||||
+ */
|
||||
+ if (set_memory_encrypted((unsigned long)addr, 1 << order))
|
||||
+ return;
|
||||
+ free_pages((unsigned long)addr, order);
|
||||
+}
|
||||
+
|
||||
+static struct gen_pool *itt_pool;
|
||||
+
|
||||
+static void *itt_alloc_pool(int node, int size)
|
||||
+{
|
||||
+ unsigned long addr;
|
||||
+ struct page *page;
|
||||
+
|
||||
+ if (size >= PAGE_SIZE) {
|
||||
+ page = its_alloc_pages_node(node, GFP_KERNEL | __GFP_ZERO, get_order(size));
|
||||
+
|
||||
+ return page ? page_address(page) : NULL;
|
||||
+ }
|
||||
+
|
||||
+ do {
|
||||
+ addr = gen_pool_alloc(itt_pool, size);
|
||||
+ if (addr)
|
||||
+ break;
|
||||
+
|
||||
+ page = its_alloc_pages_node(node, GFP_KERNEL | __GFP_ZERO, 1);
|
||||
+ if (!page)
|
||||
+ break;
|
||||
+
|
||||
+ gen_pool_add(itt_pool, (unsigned long)page_address(page), PAGE_SIZE, node);
|
||||
+ } while (!addr);
|
||||
+
|
||||
+ return (void *)addr;
|
||||
+}
|
||||
+
|
||||
+static void itt_free_pool(void *addr, int size)
|
||||
+{
|
||||
+ if (!addr)
|
||||
+ return;
|
||||
+
|
||||
+ if (size >= PAGE_SIZE) {
|
||||
+ its_free_pages(addr, get_order(size));
|
||||
+ return;
|
||||
+ }
|
||||
+
|
||||
+ gen_pool_free(itt_pool, (unsigned long)addr, size);
|
||||
+}
|
||||
+
|
||||
/*
|
||||
* Skip ITSs that have no vLPIs mapped, unless we're on GICv4.1, as we
|
||||
* always have vSGIs mapped.
|
||||
@@ -2192,7 +2277,8 @@ static struct page *its_allocate_prop_ta
|
||||
{
|
||||
struct page *prop_page;
|
||||
|
||||
- prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
|
||||
+ prop_page = its_alloc_pages(gfp_flags,
|
||||
+ get_order(LPI_PROPBASE_SZ));
|
||||
if (!prop_page)
|
||||
return NULL;
|
||||
|
||||
@@ -2203,8 +2289,7 @@ static struct page *its_allocate_prop_ta
|
||||
|
||||
static void its_free_prop_table(struct page *prop_page)
|
||||
{
|
||||
- free_pages((unsigned long)page_address(prop_page),
|
||||
- get_order(LPI_PROPBASE_SZ));
|
||||
+ its_free_pages(page_address(prop_page), get_order(LPI_PROPBASE_SZ));
|
||||
}
|
||||
|
||||
static bool gic_check_reserved_range(phys_addr_t addr, unsigned long size)
|
||||
@@ -2326,7 +2411,7 @@ static int its_setup_baser(struct its_no
|
||||
order = get_order(GITS_BASER_PAGES_MAX * psz);
|
||||
}
|
||||
|
||||
- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
|
||||
+ page = its_alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
|
||||
if (!page)
|
||||
return -ENOMEM;
|
||||
|
||||
@@ -2339,7 +2424,7 @@ static int its_setup_baser(struct its_no
|
||||
/* 52bit PA is supported only when PageSize=64K */
|
||||
if (psz != SZ_64K) {
|
||||
pr_err("ITS: no 52bit PA support when psz=%d\n", psz);
|
||||
- free_pages((unsigned long)base, order);
|
||||
+ its_free_pages(base, order);
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
@@ -2395,7 +2480,7 @@ retry_baser:
|
||||
pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n",
|
||||
&its->phys_base, its_base_type_string[type],
|
||||
val, tmp);
|
||||
- free_pages((unsigned long)base, order);
|
||||
+ its_free_pages(base, order);
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
@@ -2534,8 +2619,7 @@ static void its_free_tables(struct its_n
|
||||
|
||||
for (i = 0; i < GITS_BASER_NR_REGS; i++) {
|
||||
if (its->tables[i].base) {
|
||||
- free_pages((unsigned long)its->tables[i].base,
|
||||
- its->tables[i].order);
|
||||
+ its_free_pages(its->tables[i].base, its->tables[i].order);
|
||||
its->tables[i].base = NULL;
|
||||
}
|
||||
}
|
||||
@@ -2801,7 +2885,7 @@ static bool allocate_vpe_l2_table(int cp
|
||||
|
||||
/* Allocate memory for 2nd level table */
|
||||
if (!table[idx]) {
|
||||
- page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(psz));
|
||||
+ page = its_alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(psz));
|
||||
if (!page)
|
||||
return false;
|
||||
|
||||
@@ -2920,7 +3004,7 @@ static int allocate_vpe_l1_table(void)
|
||||
|
||||
pr_debug("np = %d, npg = %lld, psz = %d, epp = %d, esz = %d\n",
|
||||
np, npg, psz, epp, esz);
|
||||
- page = alloc_pages(GFP_ATOMIC | __GFP_ZERO, get_order(np * PAGE_SIZE));
|
||||
+ page = its_alloc_pages(GFP_ATOMIC | __GFP_ZERO, get_order(np * PAGE_SIZE));
|
||||
if (!page)
|
||||
return -ENOMEM;
|
||||
|
||||
@@ -2966,8 +3050,7 @@ static struct page *its_allocate_pending
|
||||
{
|
||||
struct page *pend_page;
|
||||
|
||||
- pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
|
||||
- get_order(LPI_PENDBASE_SZ));
|
||||
+ pend_page = its_alloc_pages(gfp_flags | __GFP_ZERO, get_order(LPI_PENDBASE_SZ));
|
||||
if (!pend_page)
|
||||
return NULL;
|
||||
|
||||
@@ -2979,7 +3062,7 @@ static struct page *its_allocate_pending
|
||||
|
||||
static void its_free_pending_table(struct page *pt)
|
||||
{
|
||||
- free_pages((unsigned long)page_address(pt), get_order(LPI_PENDBASE_SZ));
|
||||
+ its_free_pages(page_address(pt), get_order(LPI_PENDBASE_SZ));
|
||||
}
|
||||
|
||||
/*
|
||||
@@ -3314,8 +3397,8 @@ static bool its_alloc_table_entry(struct
|
||||
|
||||
/* Allocate memory for 2nd level table */
|
||||
if (!table[idx]) {
|
||||
- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
|
||||
- get_order(baser->psz));
|
||||
+ page = its_alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
|
||||
+ get_order(baser->psz));
|
||||
if (!page)
|
||||
return false;
|
||||
|
||||
@@ -3410,7 +3493,6 @@ static struct its_device *its_create_dev
|
||||
if (WARN_ON(!is_power_of_2(nvecs)))
|
||||
nvecs = roundup_pow_of_two(nvecs);
|
||||
|
||||
- dev = kzalloc(sizeof(*dev), GFP_KERNEL);
|
||||
/*
|
||||
* Even if the device wants a single LPI, the ITT must be
|
||||
* sized as a power of two (and you need at least one bit...).
|
||||
@@ -3418,7 +3500,11 @@ static struct its_device *its_create_dev
|
||||
nr_ites = max(2, nvecs);
|
||||
sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1);
|
||||
sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
|
||||
- itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node);
|
||||
+
|
||||
+ itt = itt_alloc_pool(its->numa_node, sz);
|
||||
+
|
||||
+ dev = kzalloc(sizeof(*dev), GFP_KERNEL);
|
||||
+
|
||||
if (alloc_lpis) {
|
||||
lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
|
||||
if (lpi_map)
|
||||
@@ -3430,9 +3516,9 @@ static struct its_device *its_create_dev
|
||||
lpi_base = 0;
|
||||
}
|
||||
|
||||
- if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) {
|
||||
+ if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) {
|
||||
kfree(dev);
|
||||
- kfree(itt);
|
||||
+ itt_free_pool(itt, sz);
|
||||
bitmap_free(lpi_map);
|
||||
kfree(col_map);
|
||||
return NULL;
|
||||
@@ -3442,6 +3528,7 @@ static struct its_device *its_create_dev
|
||||
|
||||
dev->its = its;
|
||||
dev->itt = itt;
|
||||
+ dev->itt_sz = sz;
|
||||
dev->nr_ites = nr_ites;
|
||||
dev->event_map.lpi_map = lpi_map;
|
||||
dev->event_map.col_map = col_map;
|
||||
@@ -3469,7 +3556,7 @@ static void its_free_device(struct its_d
|
||||
list_del(&its_dev->entry);
|
||||
raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
|
||||
kfree(its_dev->event_map.col_map);
|
||||
- kfree(its_dev->itt);
|
||||
+ itt_free_pool(its_dev->itt, its_dev->itt_sz);
|
||||
kfree(its_dev);
|
||||
}
|
||||
|
||||
@@ -5112,8 +5199,9 @@ static int __init its_probe_one(struct i
|
||||
}
|
||||
}
|
||||
|
||||
- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
|
||||
- get_order(ITS_CMD_QUEUE_SZ));
|
||||
+ page = its_alloc_pages_node(its->numa_node,
|
||||
+ GFP_KERNEL | __GFP_ZERO,
|
||||
+ get_order(ITS_CMD_QUEUE_SZ));
|
||||
if (!page) {
|
||||
err = -ENOMEM;
|
||||
goto out_unmap_sgir;
|
||||
@@ -5177,7 +5265,7 @@ static int __init its_probe_one(struct i
|
||||
out_free_tables:
|
||||
its_free_tables(its);
|
||||
out_free_cmd:
|
||||
- free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ));
|
||||
+ its_free_pages(its->cmd_base, get_order(ITS_CMD_QUEUE_SZ));
|
||||
out_unmap_sgir:
|
||||
if (its->sgir_base)
|
||||
iounmap(its->sgir_base);
|
||||
@@ -5659,6 +5747,10 @@ int __init its_init(struct fwnode_handle
|
||||
bool has_v4_1 = false;
|
||||
int err;
|
||||
|
||||
+ itt_pool = gen_pool_create(get_order(ITS_ITT_ALIGN), -1);
|
||||
+ if (!itt_pool)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
gic_rdists = rdists;
|
||||
|
||||
its_parent = parent_domain;
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
From bc88d44bd7e45b992cf8c2c2ffbc7bb3e24db4a7 Mon Sep 17 00:00:00 2001
|
||||
From: Steven Price <steven.price@arm.com>
|
||||
Date: Mon, 21 Oct 2024 11:41:05 +0100
|
||||
Subject: [PATCH] irqchip/gic-v3-its: Fix over allocation in
|
||||
itt_alloc_pool()
|
||||
|
||||
itt_alloc_pool() calls its_alloc_pages_node() to allocate an individual
|
||||
page to add to the pool (for allocations <PAGE_SIZE). However the final
|
||||
argument of its_alloc_pages_node() is the page order not the number of
|
||||
pages. Currently it allocates two pages and leaks the second page.
|
||||
Fix it by passing 0 instead (1 << 0 = 1 page).
|
||||
|
||||
Fixes: b08e2f42e86b ("irqchip/gic-v3-its: Share ITS tables with a non-trusted hypervisor")
|
||||
Reported-by: Shanker Donthineni <sdonthineni@nvidia.com>
|
||||
Signed-off-by: Steven Price <steven.price@arm.com>
|
||||
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
|
||||
Link: https://lore.kernel.org/all/1f6e19c4-1fb9-43ab-a8a2-a465c9cff84b@arm.com
|
||||
Closes: https://lore.kernel.org/r/ed65312a-245c-4fa5-91ad-5d620cab7c6b%40nvidia.com
|
||||
---
|
||||
drivers/irqchip/irq-gic-v3-its.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/irqchip/irq-gic-v3-its.c
|
||||
+++ b/drivers/irqchip/irq-gic-v3-its.c
|
||||
@@ -260,7 +260,7 @@ static void *itt_alloc_pool(int node, in
|
||||
if (addr)
|
||||
break;
|
||||
|
||||
- page = its_alloc_pages_node(node, GFP_KERNEL | __GFP_ZERO, 1);
|
||||
+ page = its_alloc_pages_node(node, GFP_KERNEL | __GFP_ZERO, 0);
|
||||
if (!page)
|
||||
break;
|
||||
|
||||
|
|
@ -0,0 +1,105 @@
|
|||
From 2d81e1bb625238d40a686ed909ff3e1abab7556a Mon Sep 17 00:00:00 2001
|
||||
From: Dmitry Osipenko <dmitry.osipenko@collabora.com>
|
||||
Date: Mon, 17 Feb 2025 01:16:32 +0300
|
||||
Subject: [PATCH] irqchip/gic-v3: Add Rockchip 3568002 erratum workaround
|
||||
|
||||
Rockchip RK3566/RK3568 GIC600 integration has DDR addressing
|
||||
limited to the first 32bit of physical address space. Rockchip
|
||||
assigned Erratum ID #3568002 for this issue. Add driver quirk for
|
||||
this Rockchip GIC Erratum.
|
||||
|
||||
Note, that the 0x0201743b GIC600 ID is not Rockchip-specific and is
|
||||
common for many ARM GICv3 implementations. Hence, there is an extra
|
||||
of_machine_is_compatible() check.
|
||||
|
||||
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
|
||||
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
|
||||
Acked-by: Marc Zyngier <maz@kernel.org>
|
||||
Link: https://lore.kernel.org/all/20250216221634.364158-2-dmitry.osipenko@collabora.com
|
||||
---
|
||||
Documentation/arch/arm64/silicon-errata.rst | 2 ++
|
||||
arch/arm64/Kconfig | 9 ++++++++
|
||||
drivers/irqchip/irq-gic-v3-its.c | 23 ++++++++++++++++++++-
|
||||
3 files changed, 33 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/Documentation/arch/arm64/silicon-errata.rst
|
||||
+++ b/Documentation/arch/arm64/silicon-errata.rst
|
||||
@@ -270,6 +270,8 @@ stable kernels.
|
||||
+----------------+-----------------+-----------------+-----------------------------+
|
||||
| Rockchip | RK3588 | #3588001 | ROCKCHIP_ERRATUM_3588001 |
|
||||
+----------------+-----------------+-----------------+-----------------------------+
|
||||
+| Rockchip | RK3568 | #3568002 | ROCKCHIP_ERRATUM_3568002 |
|
||||
++----------------+-----------------+-----------------+-----------------------------+
|
||||
|
||||
+----------------+-----------------+-----------------+-----------------------------+
|
||||
| Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 |
|
||||
--- a/arch/arm64/Kconfig
|
||||
+++ b/arch/arm64/Kconfig
|
||||
@@ -1267,6 +1267,15 @@ config NVIDIA_CARMEL_CNP_ERRATUM
|
||||
|
||||
If unsure, say Y.
|
||||
|
||||
+config ROCKCHIP_ERRATUM_3568002
|
||||
+ bool "Rockchip 3568002: GIC600 can not access physical addresses higher than 4GB"
|
||||
+ default y
|
||||
+ help
|
||||
+ The Rockchip RK3566 and RK3568 GIC600 SoC integrations have AXI
|
||||
+ addressing limited to the first 32bit of physical address space.
|
||||
+
|
||||
+ If unsure, say Y.
|
||||
+
|
||||
config ROCKCHIP_ERRATUM_3588001
|
||||
bool "Rockchip 3588001: GIC600 can not support shareability attributes"
|
||||
default y
|
||||
--- a/drivers/irqchip/irq-gic-v3-its.c
|
||||
+++ b/drivers/irqchip/irq-gic-v3-its.c
|
||||
@@ -202,13 +202,15 @@ static DEFINE_IDA(its_vpeid_ida);
|
||||
#define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
|
||||
#define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K)
|
||||
|
||||
+static gfp_t gfp_flags_quirk;
|
||||
+
|
||||
static struct page *its_alloc_pages_node(int node, gfp_t gfp,
|
||||
unsigned int order)
|
||||
{
|
||||
struct page *page;
|
||||
int ret = 0;
|
||||
|
||||
- page = alloc_pages_node(node, gfp, order);
|
||||
+ page = alloc_pages_node(node, gfp | gfp_flags_quirk, order);
|
||||
|
||||
if (!page)
|
||||
return NULL;
|
||||
@@ -4851,6 +4853,17 @@ static bool its_set_non_coherent(void *d
|
||||
return true;
|
||||
}
|
||||
|
||||
+static bool __maybe_unused its_enable_rk3568002(void *data)
|
||||
+{
|
||||
+ if (!of_machine_is_compatible("rockchip,rk3566") &&
|
||||
+ !of_machine_is_compatible("rockchip,rk3568"))
|
||||
+ return false;
|
||||
+
|
||||
+ gfp_flags_quirk |= GFP_DMA32;
|
||||
+
|
||||
+ return true;
|
||||
+}
|
||||
+
|
||||
static const struct gic_quirk its_quirks[] = {
|
||||
#ifdef CONFIG_CAVIUM_ERRATUM_22375
|
||||
{
|
||||
@@ -4910,6 +4923,14 @@ static const struct gic_quirk its_quirks
|
||||
.property = "dma-noncoherent",
|
||||
.init = its_set_non_coherent,
|
||||
},
|
||||
+#ifdef CONFIG_ROCKCHIP_ERRATUM_3568002
|
||||
+ {
|
||||
+ .desc = "ITS: Rockchip erratum RK3568002",
|
||||
+ .iidr = 0x0201743b,
|
||||
+ .mask = 0xffffffff,
|
||||
+ .init = its_enable_rk3568002,
|
||||
+ },
|
||||
+#endif
|
||||
{
|
||||
}
|
||||
};
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
From f15be3d4a0a55db2b50f319c378a2d16ceb21f86 Mon Sep 17 00:00:00 2001
|
||||
From: Dmitry Osipenko <dmitry.osipenko@collabora.com>
|
||||
Date: Mon, 17 Feb 2025 01:16:33 +0300
|
||||
Subject: [PATCH] arm64: dts: rockchip: rk356x: Add MSI controller node
|
||||
|
||||
Rockchip 356x SoC's GIC has two hardware integration issues that
|
||||
affect MSI functionality of the GIC. Previously, both these GIC
|
||||
issues were worked around by using MBI for MSI instead of ITS
|
||||
because kernel GIC driver didn't have necessary quirks.
|
||||
|
||||
First issue is about RK356x GIC not supporting programmable
|
||||
shareability, while reporting it as supported in a GIC's feature
|
||||
register. Rockchip assigned Erratum ID #3568001 for this issue. This
|
||||
patch adds dma-noncoherent property to the GIC node, denoting that a SW
|
||||
workaround is required for mitigating the issue.
|
||||
|
||||
Second issue is about GIC AXI master interface addressing limited to
|
||||
the first 4GB of physical address space. Rockchip assigned Erratum
|
||||
ID #3568002 for this issue.
|
||||
|
||||
Now that kernel supports quirks for both of the erratums, add
|
||||
MSI controller node to RK356x device-tree.
|
||||
|
||||
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
|
||||
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
|
||||
Link: https://lore.kernel.org/all/20250216221634.364158-3-dmitry.osipenko@collabora.com
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 12 ++++++++++++
|
||||
1 file changed, 12 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -364,6 +364,18 @@
|
||||
mbi-alias = <0x0 0xfd410000>;
|
||||
mbi-ranges = <296 24>;
|
||||
msi-controller;
|
||||
+ ranges;
|
||||
+ #address-cells = <2>;
|
||||
+ #size-cells = <2>;
|
||||
+ dma-noncoherent;
|
||||
+
|
||||
+ its: msi-controller@fd440000 {
|
||||
+ compatible = "arm,gic-v3-its";
|
||||
+ reg = <0x0 0xfd440000 0 0x20000>;
|
||||
+ dma-noncoherent;
|
||||
+ msi-controller;
|
||||
+ #msi-cells = <1>;
|
||||
+ };
|
||||
};
|
||||
|
||||
usb_host0_ehci: usb@fd800000 {
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
From b956c9de91757c9478e24fc9f6a57fd46f0a49f0 Mon Sep 17 00:00:00 2001
|
||||
From: Dmitry Osipenko <dmitry.osipenko@collabora.com>
|
||||
Date: Mon, 17 Feb 2025 01:16:34 +0300
|
||||
Subject: [PATCH] arm64: dts: rockchip: rk356x: Move PCIe MSI to use GIC
|
||||
ITS instead of MBI
|
||||
|
||||
Rockchip 356x device-tree now supports GIC ITS. Move PCIe controller's
|
||||
MSI to use ITS instead of MBI. This removes extra CPU overhead of handling
|
||||
PCIe MBIs by letting GIC's ITS to serve the PCIe MSIs.
|
||||
|
||||
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
|
||||
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
|
||||
Link: https://lore.kernel.org/all/20250216221634.364158-4-dmitry.osipenko@collabora.com
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -1043,7 +1043,7 @@
|
||||
num-ib-windows = <6>;
|
||||
num-ob-windows = <2>;
|
||||
max-link-speed = <2>;
|
||||
- msi-map = <0x0 &gic 0x0 0x1000>;
|
||||
+ msi-map = <0x0 &its 0x0 0x1000>;
|
||||
num-lanes = <1>;
|
||||
phys = <&combphy2 PHY_TYPE_PCIE>;
|
||||
phy-names = "pcie-phy";
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
From fbea35a661ed100cee2f3bab8015fb0155508106 Mon Sep 17 00:00:00 2001
|
||||
From: Chukun Pan <amadeus@jmu.edu.cn>
|
||||
Date: Sat, 8 Mar 2025 17:30:08 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: Move rk3568 PCIe3 MSI to use GIC ITS
|
||||
|
||||
Following commit b956c9de9175 ("arm64: dts: rockchip: rk356x: Move
|
||||
PCIe MSI to use GIC ITS instead of MBI"), change the PCIe3 controller's
|
||||
MSI on rk3568 to use ITS, so that all MSI-X can work properly.
|
||||
|
||||
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
|
||||
Link: https://lore.kernel.org/r/20250308093008.568437-2-amadeus@jmu.edu.cn
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 8 ++++----
|
||||
1 file changed, 4 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
@@ -64,7 +64,7 @@
|
||||
compatible = "rockchip,rk3568-pcie";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
- bus-range = <0x0 0xf>;
|
||||
+ bus-range = <0x10 0x1f>;
|
||||
clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
|
||||
<&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
|
||||
<&cru CLK_PCIE30X1_AUX_NDFT>;
|
||||
@@ -87,7 +87,7 @@
|
||||
num-ib-windows = <6>;
|
||||
num-ob-windows = <2>;
|
||||
max-link-speed = <3>;
|
||||
- msi-map = <0x0 &gic 0x1000 0x1000>;
|
||||
+ msi-map = <0x1000 &its 0x1000 0x1000>;
|
||||
num-lanes = <1>;
|
||||
phys = <&pcie30phy>;
|
||||
phy-names = "pcie-phy";
|
||||
@@ -117,7 +117,7 @@
|
||||
compatible = "rockchip,rk3568-pcie";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
- bus-range = <0x0 0xf>;
|
||||
+ bus-range = <0x20 0x2f>;
|
||||
clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
|
||||
<&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
|
||||
<&cru CLK_PCIE30X2_AUX_NDFT>;
|
||||
@@ -140,7 +140,7 @@
|
||||
num-ib-windows = <6>;
|
||||
num-ob-windows = <2>;
|
||||
max-link-speed = <3>;
|
||||
- msi-map = <0x0 &gic 0x2000 0x1000>;
|
||||
+ msi-map = <0x2000 &its 0x2000 0x1000>;
|
||||
num-lanes = <2>;
|
||||
phys = <&pcie30phy>;
|
||||
phy-names = "pcie-phy";
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
From 2dc66a5ab2c6fb532fbb16107ee7efcb0effbfa5 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Fri, 26 Jan 2024 19:18:22 +0100
|
||||
Subject: [PATCH] clk: rockchip: rk3588: fix CLK_NR_CLKS usage
|
||||
|
||||
CLK_NR_CLKS is not part of the DT bindings and needs to be removed
|
||||
from it, just like it recently happened for other platforms. This
|
||||
takes care of it by introducing a new function identifying the
|
||||
maximum used clock ID at runtime.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20240126182919.48402-2-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
drivers/clk/rockchip/clk-rk3588.c | 5 ++++-
|
||||
drivers/clk/rockchip/clk.c | 17 +++++++++++++++++
|
||||
drivers/clk/rockchip/clk.h | 2 ++
|
||||
3 files changed, 23 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/clk/rockchip/clk-rk3588.c
|
||||
+++ b/drivers/clk/rockchip/clk-rk3588.c
|
||||
@@ -2458,15 +2458,18 @@ static struct rockchip_clk_branch rk3588
|
||||
static void __init rk3588_clk_init(struct device_node *np)
|
||||
{
|
||||
struct rockchip_clk_provider *ctx;
|
||||
+ unsigned long clk_nr_clks;
|
||||
void __iomem *reg_base;
|
||||
|
||||
+ clk_nr_clks = rockchip_clk_find_max_clk_id(rk3588_clk_branches,
|
||||
+ ARRAY_SIZE(rk3588_clk_branches)) + 1;
|
||||
reg_base = of_iomap(np, 0);
|
||||
if (!reg_base) {
|
||||
pr_err("%s: could not map cru region\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
- ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
|
||||
+ ctx = rockchip_clk_init(np, reg_base, clk_nr_clks);
|
||||
if (IS_ERR(ctx)) {
|
||||
pr_err("%s: rockchip clk init failed\n", __func__);
|
||||
iounmap(reg_base);
|
||||
--- a/drivers/clk/rockchip/clk.c
|
||||
+++ b/drivers/clk/rockchip/clk.c
|
||||
@@ -429,6 +429,23 @@ void rockchip_clk_register_plls(struct r
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(rockchip_clk_register_plls);
|
||||
|
||||
+unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list,
|
||||
+ unsigned int nr_clk)
|
||||
+{
|
||||
+ unsigned long max = 0;
|
||||
+ unsigned int idx;
|
||||
+
|
||||
+ for (idx = 0; idx < nr_clk; idx++, list++) {
|
||||
+ if (list->id > max)
|
||||
+ max = list->id;
|
||||
+ if (list->child && list->child->id > max)
|
||||
+ max = list->id;
|
||||
+ }
|
||||
+
|
||||
+ return max;
|
||||
+}
|
||||
+EXPORT_SYMBOL_GPL(rockchip_clk_find_max_clk_id);
|
||||
+
|
||||
void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
|
||||
struct rockchip_clk_branch *list,
|
||||
unsigned int nr_clk)
|
||||
--- a/drivers/clk/rockchip/clk.h
|
||||
+++ b/drivers/clk/rockchip/clk.h
|
||||
@@ -973,6 +973,8 @@ struct rockchip_clk_provider *rockchip_c
|
||||
void __iomem *base, unsigned long nr_clks);
|
||||
void rockchip_clk_of_add_provider(struct device_node *np,
|
||||
struct rockchip_clk_provider *ctx);
|
||||
+unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list,
|
||||
+ unsigned int nr_clk);
|
||||
void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
|
||||
struct rockchip_clk_branch *list,
|
||||
unsigned int nr_clk);
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
From 11a29dc2e41ead2be78cfa9d532edf924b461acc Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Fri, 26 Jan 2024 19:18:23 +0100
|
||||
Subject: [PATCH] dt-bindings: clock: rk3588: drop CLK_NR_CLKS
|
||||
|
||||
CLK_NR_CLKS should not be part of the binding. Let's drop it, since
|
||||
the kernel code no longer uses it either.
|
||||
|
||||
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20240126182919.48402-3-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
include/dt-bindings/clock/rockchip,rk3588-cru.h | 2 --
|
||||
1 file changed, 2 deletions(-)
|
||||
|
||||
--- a/include/dt-bindings/clock/rockchip,rk3588-cru.h
|
||||
+++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h
|
||||
@@ -734,8 +734,6 @@
|
||||
#define PCLK_AV1_PRE 719
|
||||
#define HCLK_SDIO_PRE 720
|
||||
|
||||
-#define CLK_NR_CLKS (HCLK_SDIO_PRE + 1)
|
||||
-
|
||||
/* scmi-clocks indices */
|
||||
|
||||
#define SCMI_CLK_CPUL 0
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
From c81798cf9dd2f324934585b2b52a0398caefb88e Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Fri, 26 Jan 2024 19:18:24 +0100
|
||||
Subject: [PATCH] dt-bindings: clock: rk3588: add missing PCLK_VO1GRF
|
||||
|
||||
Add PCLK_VO1GRF to complement PCLK_VO0GRF. This will be needed
|
||||
for HDMI support.
|
||||
|
||||
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20240126182919.48402-4-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
include/dt-bindings/clock/rockchip,rk3588-cru.h | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/include/dt-bindings/clock/rockchip,rk3588-cru.h
|
||||
+++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h
|
||||
@@ -733,6 +733,7 @@
|
||||
#define ACLK_AV1_PRE 718
|
||||
#define PCLK_AV1_PRE 719
|
||||
#define HCLK_SDIO_PRE 720
|
||||
+#define PCLK_VO1GRF 721
|
||||
|
||||
/* scmi-clocks indices */
|
||||
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
From 326be62eaf2e89767b7b9223f88eaf3c041b98d2 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Fri, 26 Jan 2024 19:18:25 +0100
|
||||
Subject: [PATCH] clk: rockchip: rk3588: fix pclk_vo0grf and pclk_vo1grf
|
||||
|
||||
Currently pclk_vo1grf is not exposed, but it should be referenced
|
||||
from the vo1_grf syscon, which needs it enabled. That syscon is
|
||||
required for HDMI RX and TX functionality among other things.
|
||||
|
||||
Apart from that pclk_vo0grf and pclk_vo1grf are both linked gates
|
||||
and need the VO's hclk enabled in addition to their parent clock.
|
||||
|
||||
No Fixes tag has been added, since the logic requiring these clocks
|
||||
is not yet upstream anyways.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20240126182919.48402-5-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
drivers/clk/rockchip/clk-rk3588.c | 10 ++++------
|
||||
1 file changed, 4 insertions(+), 6 deletions(-)
|
||||
|
||||
--- a/drivers/clk/rockchip/clk-rk3588.c
|
||||
+++ b/drivers/clk/rockchip/clk-rk3588.c
|
||||
@@ -1851,8 +1851,6 @@ static struct rockchip_clk_branch rk3588
|
||||
RK3588_CLKGATE_CON(56), 0, GFLAGS),
|
||||
GATE(PCLK_TRNG0, "pclk_trng0", "pclk_vo0_root", 0,
|
||||
RK3588_CLKGATE_CON(56), 1, GFLAGS),
|
||||
- GATE(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", CLK_IGNORE_UNUSED,
|
||||
- RK3588_CLKGATE_CON(55), 10, GFLAGS),
|
||||
COMPOSITE(CLK_I2S4_8CH_TX_SRC, "clk_i2s4_8ch_tx_src", gpll_aupll_p, 0,
|
||||
RK3588_CLKSEL_CON(118), 5, 1, MFLAGS, 0, 5, DFLAGS,
|
||||
RK3588_CLKGATE_CON(56), 11, GFLAGS),
|
||||
@@ -1998,8 +1996,6 @@ static struct rockchip_clk_branch rk3588
|
||||
RK3588_CLKGATE_CON(60), 9, GFLAGS),
|
||||
GATE(PCLK_TRNG1, "pclk_trng1", "pclk_vo1_root", 0,
|
||||
RK3588_CLKGATE_CON(60), 10, GFLAGS),
|
||||
- GATE(0, "pclk_vo1grf", "pclk_vo1_root", CLK_IGNORE_UNUSED,
|
||||
- RK3588_CLKGATE_CON(59), 12, GFLAGS),
|
||||
GATE(PCLK_S_EDP0, "pclk_s_edp0", "pclk_vo1_s_root", 0,
|
||||
RK3588_CLKGATE_CON(59), 14, GFLAGS),
|
||||
GATE(PCLK_S_EDP1, "pclk_s_edp1", "pclk_vo1_s_root", 0,
|
||||
@@ -2447,12 +2443,14 @@ static struct rockchip_clk_branch rk3588
|
||||
GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 4, GFLAGS),
|
||||
GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 5, GFLAGS),
|
||||
GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", "aclk_vop_low_root", 0, RK3588_CLKGATE_CON(55), 9, GFLAGS),
|
||||
- GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", 0, RK3588_CLKGATE_CON(55), 5, GFLAGS),
|
||||
+ GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(55), 5, GFLAGS),
|
||||
GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 6, GFLAGS),
|
||||
- GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 9, GFLAGS),
|
||||
+ GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(59), 9, GFLAGS),
|
||||
GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 1, GFLAGS),
|
||||
GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 4, GFLAGS),
|
||||
GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", "hclk_nvm", 0, RK3588_CLKGATE_CON(75), 1, GFLAGS),
|
||||
+ GATE_LINK(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", "hclk_vo0", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(55), 10, GFLAGS),
|
||||
+ GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", "hclk_vo1", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS),
|
||||
};
|
||||
|
||||
static void __init rk3588_clk_init(struct device_node *np)
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
From 2a6e4710672242281347103b64e01693aa823a29 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Fri, 26 Jan 2024 19:18:26 +0100
|
||||
Subject: [PATCH] clk: rockchip: rk3588: fix indent
|
||||
|
||||
pclk_mailbox2 is the only RK3588 clock indented with one tab instead of
|
||||
two tabs. Let's fix this.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20240126182919.48402-6-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
drivers/clk/rockchip/clk-rk3588.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/clk/rockchip/clk-rk3588.c
|
||||
+++ b/drivers/clk/rockchip/clk-rk3588.c
|
||||
@@ -1004,7 +1004,7 @@ static struct rockchip_clk_branch rk3588
|
||||
GATE(PCLK_MAILBOX1, "pclk_mailbox1", "pclk_top_root", 0,
|
||||
RK3588_CLKGATE_CON(16), 12, GFLAGS),
|
||||
GATE(PCLK_MAILBOX2, "pclk_mailbox2", "pclk_top_root", 0,
|
||||
- RK3588_CLKGATE_CON(16), 13, GFLAGS),
|
||||
+ RK3588_CLKGATE_CON(16), 13, GFLAGS),
|
||||
GATE(PCLK_PMU2, "pclk_pmu2", "pclk_top_root", CLK_IS_CRITICAL,
|
||||
RK3588_CLKGATE_CON(19), 3, GFLAGS),
|
||||
GATE(PCLK_PMUCM0_INTMUX, "pclk_pmucm0_intmux", "pclk_top_root", CLK_IS_CRITICAL,
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
From dae3e57000fb2d6f491e3ee2956f5918326d6b72 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Fri, 26 Jan 2024 19:18:27 +0100
|
||||
Subject: [PATCH] clk: rockchip: rk3588: use linked clock ID for GATE_LINK
|
||||
|
||||
In preparation for properly supporting GATE_LINK switch the unused
|
||||
linked clock argument from the clock's name to its ID. This allows
|
||||
easy and fast lookup of the 'struct clk'.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20240126182919.48402-7-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
drivers/clk/rockchip/clk-rk3588.c | 46 +++++++++++++++----------------
|
||||
1 file changed, 23 insertions(+), 23 deletions(-)
|
||||
|
||||
--- a/drivers/clk/rockchip/clk-rk3588.c
|
||||
+++ b/drivers/clk/rockchip/clk-rk3588.c
|
||||
@@ -29,7 +29,7 @@
|
||||
* power, but avoids leaking implementation details into DT or hanging the
|
||||
* system.
|
||||
*/
|
||||
-#define GATE_LINK(_id, cname, pname, linkname, f, o, b, gf) \
|
||||
+#define GATE_LINK(_id, cname, pname, linkedclk, f, o, b, gf) \
|
||||
GATE(_id, cname, pname, f, o, b, gf)
|
||||
#define RK3588_LINKED_CLK CLK_IS_CRITICAL
|
||||
|
||||
@@ -2429,28 +2429,28 @@ static struct rockchip_clk_branch rk3588
|
||||
GATE(ACLK_AV1, "aclk_av1", "aclk_av1_pre", 0,
|
||||
RK3588_CLKGATE_CON(68), 2, GFLAGS),
|
||||
|
||||
- GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", "aclk_vi_root", 0, RK3588_CLKGATE_CON(26), 6, GFLAGS),
|
||||
- GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", "hclk_vi_root", 0, RK3588_CLKGATE_CON(26), 8, GFLAGS),
|
||||
- GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", "aclk_nvm_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS),
|
||||
- GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 2, GFLAGS),
|
||||
- GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 3, GFLAGS),
|
||||
- GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 7, GFLAGS),
|
||||
- GATE_LINK(ACLK_VDPU_LOW_PRE, "aclk_vdpu_low_pre", "aclk_vdpu_low_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 5, GFLAGS),
|
||||
- GATE_LINK(ACLK_RKVENC1_PRE, "aclk_rkvenc1_pre", "aclk_rkvenc1_root", "aclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 3, GFLAGS),
|
||||
- GATE_LINK(HCLK_RKVENC1_PRE, "hclk_rkvenc1_pre", "hclk_rkvenc1_root", "hclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 2, GFLAGS),
|
||||
- GATE_LINK(HCLK_RKVDEC0_PRE, "hclk_rkvdec0_pre", "hclk_rkvdec0_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 5, GFLAGS),
|
||||
- GATE_LINK(ACLK_RKVDEC0_PRE, "aclk_rkvdec0_pre", "aclk_rkvdec0_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 6, GFLAGS),
|
||||
- GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 4, GFLAGS),
|
||||
- GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 5, GFLAGS),
|
||||
- GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", "aclk_vop_low_root", 0, RK3588_CLKGATE_CON(55), 9, GFLAGS),
|
||||
- GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(55), 5, GFLAGS),
|
||||
- GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 6, GFLAGS),
|
||||
- GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(59), 9, GFLAGS),
|
||||
- GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 1, GFLAGS),
|
||||
- GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 4, GFLAGS),
|
||||
- GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", "hclk_nvm", 0, RK3588_CLKGATE_CON(75), 1, GFLAGS),
|
||||
- GATE_LINK(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", "hclk_vo0", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(55), 10, GFLAGS),
|
||||
- GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", "hclk_vo1", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS),
|
||||
+ GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", ACLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 6, GFLAGS),
|
||||
+ GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", HCLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 8, GFLAGS),
|
||||
+ GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", ACLK_NVM_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS),
|
||||
+ GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 2, GFLAGS),
|
||||
+ GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", HCLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 3, GFLAGS),
|
||||
+ GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(44), 7, GFLAGS),
|
||||
+ GATE_LINK(ACLK_VDPU_LOW_PRE, "aclk_vdpu_low_pre", "aclk_vdpu_low_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(44), 5, GFLAGS),
|
||||
+ GATE_LINK(ACLK_RKVENC1_PRE, "aclk_rkvenc1_pre", "aclk_rkvenc1_root", ACLK_RKVENC0, 0, RK3588_CLKGATE_CON(48), 3, GFLAGS),
|
||||
+ GATE_LINK(HCLK_RKVENC1_PRE, "hclk_rkvenc1_pre", "hclk_rkvenc1_root", HCLK_RKVENC0, 0, RK3588_CLKGATE_CON(48), 2, GFLAGS),
|
||||
+ GATE_LINK(HCLK_RKVDEC0_PRE, "hclk_rkvdec0_pre", "hclk_rkvdec0_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(40), 5, GFLAGS),
|
||||
+ GATE_LINK(ACLK_RKVDEC0_PRE, "aclk_rkvdec0_pre", "aclk_rkvdec0_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(40), 6, GFLAGS),
|
||||
+ GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 4, GFLAGS),
|
||||
+ GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 5, GFLAGS),
|
||||
+ GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", ACLK_VOP_LOW_ROOT, 0, RK3588_CLKGATE_CON(55), 9, GFLAGS),
|
||||
+ GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", HCLK_VOP_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(55), 5, GFLAGS),
|
||||
+ GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(59), 6, GFLAGS),
|
||||
+ GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", HCLK_VO1USB_TOP_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(59), 9, GFLAGS),
|
||||
+ GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 1, GFLAGS),
|
||||
+ GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 4, GFLAGS),
|
||||
+ GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", HCLK_NVM, 0, RK3588_CLKGATE_CON(75), 1, GFLAGS),
|
||||
+ GATE_LINK(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", HCLK_VO0, CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(55), 10, GFLAGS),
|
||||
+ GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", HCLK_VO1, CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS),
|
||||
};
|
||||
|
||||
static void __init rk3588_clk_init(struct device_node *np)
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
From ca151fd56b5736a7adbdba5675b9d87d70f20b23 Mon Sep 17 00:00:00 2001
|
||||
From: Shreeya Patel <shreeya.patel@collabora.com>
|
||||
Date: Thu, 28 Mar 2024 04:20:52 +0530
|
||||
Subject: [PATCH] dt-bindings: reset: Define reset id used for HDMI Receiver
|
||||
|
||||
Add reset id used for HDMI Receiver in RK3588 SoCs
|
||||
|
||||
Acked-by: Rob Herring <robh@kernel.org>
|
||||
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20240327225057.672304-2-shreeya.patel@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
include/dt-bindings/reset/rockchip,rk3588-cru.h | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
--- a/include/dt-bindings/reset/rockchip,rk3588-cru.h
|
||||
+++ b/include/dt-bindings/reset/rockchip,rk3588-cru.h
|
||||
@@ -751,4 +751,6 @@
|
||||
#define SRST_P_TRNG_CHK 658
|
||||
#define SRST_TRNG_S 659
|
||||
|
||||
+#define SRST_A_HDMIRX_BIU 660
|
||||
+
|
||||
#endif
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
From 7af67019cd78d028ef377df689ac103d51905518 Mon Sep 17 00:00:00 2001
|
||||
From: Shreeya Patel <shreeya.patel@collabora.com>
|
||||
Date: Thu, 28 Mar 2024 04:20:53 +0530
|
||||
Subject: [PATCH] clk: rockchip: rk3588: Add reset line for HDMI Receiver
|
||||
|
||||
Export hdmirx_biu reset line required by the Synopsys
|
||||
DesignWare HDMIRX Controller.
|
||||
|
||||
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20240327225057.672304-3-shreeya.patel@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
drivers/clk/rockchip/rst-rk3588.c | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/drivers/clk/rockchip/rst-rk3588.c
|
||||
+++ b/drivers/clk/rockchip/rst-rk3588.c
|
||||
@@ -577,6 +577,7 @@ static const int rk3588_register_offset[
|
||||
|
||||
/* SOFTRST_CON59 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_HDCP1_BIU, 59, 6),
|
||||
+ RK3588_CRU_RESET_OFFSET(SRST_A_HDMIRX_BIU, 59, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_VO1_BIU, 59, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_BIU, 59, 9),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_S_BIU, 59, 10),
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
From e781bffc296766b55dbd048890d558655031e8d1 Mon Sep 17 00:00:00 2001
|
||||
From: Elaine Zhang <zhangqing@rock-chips.com>
|
||||
Date: Wed, 28 Aug 2024 15:42:52 +0000
|
||||
Subject: [PATCH] clk: rockchip: Add new pll type pll_rk3588_ddr
|
||||
|
||||
That PLL type is similar to the other rk3588 pll types but the actual
|
||||
rate is twice the configured rate.
|
||||
Therefore, the returned calculated rate must be multiplied by two.
|
||||
|
||||
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
||||
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
|
||||
Acked-by: Dragan Simic <dsimic@manjaro.org>
|
||||
Link: https://lore.kernel.org/r/0102019199a76ec4-9d5846d4-d76a-4e69-a241-c88c2983d607-000000@eu-west-1.amazonses.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
drivers/clk/rockchip/clk-pll.c | 6 +++++-
|
||||
drivers/clk/rockchip/clk.h | 1 +
|
||||
2 files changed, 6 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/clk/rockchip/clk-pll.c
|
||||
+++ b/drivers/clk/rockchip/clk-pll.c
|
||||
@@ -914,7 +914,10 @@ static unsigned long rockchip_rk3588_pll
|
||||
}
|
||||
rate64 = rate64 >> cur.s;
|
||||
|
||||
- return (unsigned long)rate64;
|
||||
+ if (pll->type == pll_rk3588_ddr)
|
||||
+ return (unsigned long)rate64 * 2;
|
||||
+ else
|
||||
+ return (unsigned long)rate64;
|
||||
}
|
||||
|
||||
static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll,
|
||||
@@ -1167,6 +1170,7 @@ struct clk *rockchip_clk_register_pll(st
|
||||
break;
|
||||
case pll_rk3588:
|
||||
case pll_rk3588_core:
|
||||
+ case pll_rk3588_ddr:
|
||||
if (!pll->rate_table)
|
||||
init.ops = &rockchip_rk3588_pll_clk_norate_ops;
|
||||
else
|
||||
--- a/drivers/clk/rockchip/clk.h
|
||||
+++ b/drivers/clk/rockchip/clk.h
|
||||
@@ -287,6 +287,7 @@ enum rockchip_pll_type {
|
||||
pll_rk3399,
|
||||
pll_rk3588,
|
||||
pll_rk3588_core,
|
||||
+ pll_rk3588_ddr,
|
||||
};
|
||||
|
||||
#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
From 2e7b3daa8cb1ebd17e6a7f417ef5e6553203035c Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Mon, 25 Mar 2024 20:33:32 +0100
|
||||
Subject: [PATCH] clk: rockchip: rk3588: drop unused code
|
||||
|
||||
All clocks are registered early using CLK_OF_DECLARE(), which marks
|
||||
the DT node as processed. For the processed DT node the probe routine
|
||||
is never called. Thus this whole code is never executed. This could
|
||||
be "fixed" by using CLK_OF_DECLARE_DRIVER, which avoids marking the
|
||||
DT node as processed. But then the probe routine would re-register
|
||||
all the clocks by calling rk3588_clk_init() again.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20240325193609.237182-2-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
drivers/clk/rockchip/clk-rk3588.c | 40 -------------------------------
|
||||
1 file changed, 40 deletions(-)
|
||||
|
||||
--- a/drivers/clk/rockchip/clk-rk3588.c
|
||||
+++ b/drivers/clk/rockchip/clk-rk3588.c
|
||||
@@ -2502,43 +2502,3 @@ static void __init rk3588_clk_init(struc
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(rk3588_cru, "rockchip,rk3588-cru", rk3588_clk_init);
|
||||
-
|
||||
-struct clk_rk3588_inits {
|
||||
- void (*inits)(struct device_node *np);
|
||||
-};
|
||||
-
|
||||
-static const struct clk_rk3588_inits clk_3588_cru_init = {
|
||||
- .inits = rk3588_clk_init,
|
||||
-};
|
||||
-
|
||||
-static const struct of_device_id clk_rk3588_match_table[] = {
|
||||
- {
|
||||
- .compatible = "rockchip,rk3588-cru",
|
||||
- .data = &clk_3588_cru_init,
|
||||
- },
|
||||
- { }
|
||||
-};
|
||||
-
|
||||
-static int __init clk_rk3588_probe(struct platform_device *pdev)
|
||||
-{
|
||||
- const struct clk_rk3588_inits *init_data;
|
||||
- struct device *dev = &pdev->dev;
|
||||
-
|
||||
- init_data = device_get_match_data(dev);
|
||||
- if (!init_data)
|
||||
- return -EINVAL;
|
||||
-
|
||||
- if (init_data->inits)
|
||||
- init_data->inits(dev->of_node);
|
||||
-
|
||||
- return 0;
|
||||
-}
|
||||
-
|
||||
-static struct platform_driver clk_rk3588_driver = {
|
||||
- .driver = {
|
||||
- .name = "clk-rk3588",
|
||||
- .of_match_table = clk_rk3588_match_table,
|
||||
- .suppress_bind_attrs = true,
|
||||
- },
|
||||
-};
|
||||
-builtin_platform_driver_probe(clk_rk3588_driver, clk_rk3588_probe);
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
From ad1081a0da2744141d12e94ff816ac91feb871ca Mon Sep 17 00:00:00 2001
|
||||
From: Yao Zi <ziyao@disroot.org>
|
||||
Date: Thu, 12 Sep 2024 13:32:05 +0000
|
||||
Subject: [PATCH] clk: rockchip: fix finding of maximum clock ID
|
||||
|
||||
If an ID of a branch's child is greater than current maximum, we should
|
||||
set new maximum to the child's ID, instead of its parent's.
|
||||
|
||||
Fixes: 2dc66a5ab2c6 ("clk: rockchip: rk3588: fix CLK_NR_CLKS usage")
|
||||
Signed-off-by: Yao Zi <ziyao@disroot.org>
|
||||
Link: https://lore.kernel.org/r/20240912133204.29089-2-ziyao@disroot.org
|
||||
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
||||
---
|
||||
drivers/clk/rockchip/clk.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/clk/rockchip/clk.c
|
||||
+++ b/drivers/clk/rockchip/clk.c
|
||||
@@ -439,7 +439,7 @@ unsigned long rockchip_clk_find_max_clk_
|
||||
if (list->id > max)
|
||||
max = list->id;
|
||||
if (list->child && list->child->id > max)
|
||||
- max = list->id;
|
||||
+ max = list->child->id;
|
||||
}
|
||||
|
||||
return max;
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
From 2a46cd97f401a669d71b3d36b78bd6653f8424ee Mon Sep 17 00:00:00 2001
|
||||
From: Ondrej Jirman <megi@xff.cz>
|
||||
Date: Thu, 19 Oct 2023 18:57:25 +0200
|
||||
Subject: [PATCH] mfd: rk8xx: Add support for standard system-power-controller
|
||||
property
|
||||
|
||||
DT property rockchip,system-power-controller is now deprecated.
|
||||
|
||||
Signed-off-by: Ondrej Jirman <megi@xff.cz>
|
||||
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20231019165732.3818789-4-megi@xff.cz
|
||||
Signed-off-by: Lee Jones <lee@kernel.org>
|
||||
---
|
||||
drivers/mfd/rk8xx-core.c | 3 ++-
|
||||
1 file changed, 2 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/mfd/rk8xx-core.c
|
||||
+++ b/drivers/mfd/rk8xx-core.c
|
||||
@@ -677,7 +677,8 @@ int rk8xx_probe(struct device *dev, int
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "failed to add MFD devices\n");
|
||||
|
||||
- if (device_property_read_bool(dev, "rockchip,system-power-controller")) {
|
||||
+ if (device_property_read_bool(dev, "rockchip,system-power-controller") ||
|
||||
+ device_property_read_bool(dev, "system-power-controller")) {
|
||||
ret = devm_register_sys_off_handler(dev,
|
||||
SYS_OFF_MODE_POWER_OFF_PREPARE, SYS_OFF_PRIO_HIGH,
|
||||
&rk808_power_off, rk808);
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
From b0227e7081404448a0059b8698fdffd2dec280d2 Mon Sep 17 00:00:00 2001
|
||||
From: Ondrej Jirman <megi@xff.cz>
|
||||
Date: Thu, 19 Oct 2023 18:57:26 +0200
|
||||
Subject: [PATCH] mfd: rk8xx: Add support for RK806 power off
|
||||
|
||||
Use DEV_OFF bit to power off the RK806 PMIC, when system-power-controller
|
||||
is used in DTS.
|
||||
|
||||
Signed-off-by: Ondrej Jirman <megi@xff.cz>
|
||||
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20231019165732.3818789-5-megi@xff.cz
|
||||
Signed-off-by: Lee Jones <lee@kernel.org>
|
||||
---
|
||||
drivers/mfd/rk8xx-core.c | 4 ++++
|
||||
1 file changed, 4 insertions(+)
|
||||
|
||||
--- a/drivers/mfd/rk8xx-core.c
|
||||
+++ b/drivers/mfd/rk8xx-core.c
|
||||
@@ -517,6 +517,10 @@ static int rk808_power_off(struct sys_of
|
||||
reg = RK805_DEV_CTRL_REG;
|
||||
bit = DEV_OFF;
|
||||
break;
|
||||
+ case RK806_ID:
|
||||
+ reg = RK806_SYS_CFG3;
|
||||
+ bit = DEV_OFF;
|
||||
+ break;
|
||||
case RK808_ID:
|
||||
reg = RK808_DEVCTRL_REG,
|
||||
bit = DEV_OFF_RST;
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,35 @@
|
|||
From c9342d1a351ee1249fa98d936f756299a83d5684 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Tue, 16 Apr 2024 16:51:23 +0200
|
||||
Subject: [PATCH] phy: rockchip: usbdp: fix uninitialized variable
|
||||
|
||||
The ret variable may not be initialized in rk_udphy_usb3_phy_init(), if
|
||||
the PHY is not using USB3 mode.
|
||||
|
||||
Since the DisplayPort part is handled separately and the PHY does not
|
||||
support USB2 (which is routed to another PHY on Rockchip RK3588), the
|
||||
right exit code for this case is 0. Thus let's initialize the variable
|
||||
accordingly.
|
||||
|
||||
Fixes: 2f70bbddeb457 ("phy: rockchip: add usbdp combo phy driver")
|
||||
Reported-by: kernel test robot <lkp@intel.com>
|
||||
Closes: https://lore.kernel.org/oe-kbuild-all/202404141048.qFAYDctQ-lkp@intel.com/
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Reviewed-by: Muhammad Usama Anjum <usama.anjum@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20240416145233.94687-1-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-usbdp.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
|
||||
@@ -1285,7 +1285,7 @@ static const struct phy_ops rk_udphy_dp_
|
||||
static int rk_udphy_usb3_phy_init(struct phy *phy)
|
||||
{
|
||||
struct rk_udphy *udphy = phy_get_drvdata(phy);
|
||||
- int ret;
|
||||
+ int ret = 0;
|
||||
|
||||
mutex_lock(&udphy->mutex);
|
||||
/* DP only or high-speed, disable U3 port */
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
From 9c79b779643e56d4253bd3ba6998c58c819943af Mon Sep 17 00:00:00 2001
|
||||
From: Arnd Bergmann <arnd@arndb.de>
|
||||
Date: Mon, 15 Apr 2024 19:42:25 +0200
|
||||
Subject: [PATCH] phy: rockchip: fix CONFIG_TYPEC dependency
|
||||
|
||||
The newly added driver causes a warning about missing dependencies
|
||||
by selecting CONFIG_TYPEC unconditionally:
|
||||
|
||||
WARNING: unmet direct dependencies detected for TYPEC
|
||||
Depends on [n]: USB_SUPPORT [=n]
|
||||
Selected by [y]:
|
||||
- PHY_ROCKCHIP_USBDP [=y] && ARCH_ROCKCHIP [=y] && OF [=y]
|
||||
|
||||
WARNING: unmet direct dependencies detected for USB_COMMON
|
||||
Depends on [n]: USB_SUPPORT [=n]
|
||||
Selected by [y]:
|
||||
- EXTCON_RTK_TYPE_C [=y] && EXTCON [=y] && (ARCH_REALTEK [=y] || COMPILE_TEST [=y]) && TYPEC [=y]
|
||||
|
||||
Since that is a user-visible option, it should not really be selected
|
||||
in the first place. Replace the 'select' with a 'depends on' as
|
||||
we have for similar drivers.
|
||||
|
||||
Fixes: 2f70bbddeb45 ("phy: rockchip: add usbdp combo phy driver")
|
||||
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
||||
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Link: https://lore.kernel.org/r/20240415174241.77982-1-arnd@kernel.org
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/Kconfig | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/phy/rockchip/Kconfig
|
||||
+++ b/drivers/phy/rockchip/Kconfig
|
||||
@@ -111,8 +111,8 @@ config PHY_ROCKCHIP_USB
|
||||
config PHY_ROCKCHIP_USBDP
|
||||
tristate "Rockchip USBDP COMBO PHY Driver"
|
||||
depends on ARCH_ROCKCHIP && OF
|
||||
+ depends on TYPEC
|
||||
select GENERIC_PHY
|
||||
- select TYPEC
|
||||
help
|
||||
Enable this to support the Rockchip USB3.0/DP combo PHY with
|
||||
Samsung IP block. This is required for USB3 support on RK3588.
|
||||
|
|
@ -0,0 +1,79 @@
|
|||
From 9b6bfad9070a95d19973be17177e5d9220cbbf1f Mon Sep 17 00:00:00 2001
|
||||
From: Rick Wertenbroek <rick.wertenbroek@gmail.com>
|
||||
Date: Thu, 7 Mar 2024 10:53:18 +0100
|
||||
Subject: [PATCH] phy: rockchip: Fix typo in function names
|
||||
|
||||
Several functions had "rochchip" instead of "rockchip" in their name.
|
||||
Replace "rochchip" by "rockchip".
|
||||
|
||||
Signed-off-By: Rick Wertenbroek <rick.wertenbroek@gmail.com>
|
||||
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Link: https://lore.kernel.org/r/20240307095318.3651498-1-rick.wertenbroek@gmail.com
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 4 ++--
|
||||
drivers/phy/rockchip/phy-rockchip-snps-pcie3.c | 12 ++++++------
|
||||
2 files changed, 8 insertions(+), 8 deletions(-)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
|
||||
@@ -248,7 +248,7 @@ static int rockchip_combphy_exit(struct
|
||||
return 0;
|
||||
}
|
||||
|
||||
-static const struct phy_ops rochchip_combphy_ops = {
|
||||
+static const struct phy_ops rockchip_combphy_ops = {
|
||||
.init = rockchip_combphy_init,
|
||||
.exit = rockchip_combphy_exit,
|
||||
.owner = THIS_MODULE,
|
||||
@@ -367,7 +367,7 @@ static int rockchip_combphy_probe(struct
|
||||
return ret;
|
||||
}
|
||||
|
||||
- priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops);
|
||||
+ priv->phy = devm_phy_create(dev, NULL, &rockchip_combphy_ops);
|
||||
if (IS_ERR(priv->phy)) {
|
||||
dev_err(dev, "failed to create combphy\n");
|
||||
return PTR_ERR(priv->phy);
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
|
||||
@@ -182,7 +182,7 @@ static const struct rockchip_p3phy_ops r
|
||||
.phy_init = rockchip_p3phy_rk3588_init,
|
||||
};
|
||||
|
||||
-static int rochchip_p3phy_init(struct phy *phy)
|
||||
+static int rockchip_p3phy_init(struct phy *phy)
|
||||
{
|
||||
struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
|
||||
int ret;
|
||||
@@ -205,7 +205,7 @@ static int rochchip_p3phy_init(struct ph
|
||||
return ret;
|
||||
}
|
||||
|
||||
-static int rochchip_p3phy_exit(struct phy *phy)
|
||||
+static int rockchip_p3phy_exit(struct phy *phy)
|
||||
{
|
||||
struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
|
||||
|
||||
@@ -214,9 +214,9 @@ static int rochchip_p3phy_exit(struct ph
|
||||
return 0;
|
||||
}
|
||||
|
||||
-static const struct phy_ops rochchip_p3phy_ops = {
|
||||
- .init = rochchip_p3phy_init,
|
||||
- .exit = rochchip_p3phy_exit,
|
||||
+static const struct phy_ops rockchip_p3phy_ops = {
|
||||
+ .init = rockchip_p3phy_init,
|
||||
+ .exit = rockchip_p3phy_exit,
|
||||
.set_mode = rockchip_p3phy_set_mode,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
@@ -275,7 +275,7 @@ static int rockchip_p3phy_probe(struct p
|
||||
return priv->num_lanes;
|
||||
}
|
||||
|
||||
- priv->phy = devm_phy_create(dev, NULL, &rochchip_p3phy_ops);
|
||||
+ priv->phy = devm_phy_create(dev, NULL, &rockchip_p3phy_ops);
|
||||
if (IS_ERR(priv->phy)) {
|
||||
dev_err(dev, "failed to create combphy\n");
|
||||
return PTR_ERR(priv->phy);
|
||||
|
|
@ -0,0 +1,106 @@
|
|||
From a1fe1eca0d8be69ccc1f3d615e5a529df1c82e66 Mon Sep 17 00:00:00 2001
|
||||
From: Niklas Cassel <cassel@kernel.org>
|
||||
Date: Fri, 12 Apr 2024 14:58:16 +0200
|
||||
Subject: [PATCH] phy: rockchip-snps-pcie3: add support for
|
||||
rockchip,rx-common-refclk-mode
|
||||
|
||||
>From the RK3588 Technical Reference Manual, Part1,
|
||||
section 6.19 PCIe3PHY_GRF Register Description:
|
||||
"rxX_cmn_refclk_mode"
|
||||
RX common reference clock mode for lane X. This mode should be enabled
|
||||
only when the far-end and near-end devices are running with a common
|
||||
reference clock.
|
||||
|
||||
The hardware reset value for this field is 0x1 (enabled).
|
||||
Note that this register field is only available on RK3588, not on RK3568.
|
||||
|
||||
The link training either fails or is highly unstable (link state will jump
|
||||
continuously between L0 and recovery) when this mode is enabled while
|
||||
using an endpoint running in Separate Reference Clock with No SSC (SRNS)
|
||||
mode or Separate Reference Clock with SSC (SRIS) mode.
|
||||
(Which is usually the case when using a real SoC as endpoint, e.g. the
|
||||
RK3588 PCIe controller can run in both Root Complex and Endpoint mode.)
|
||||
|
||||
Add support for the device tree property rockchip,rx-common-refclk-mode,
|
||||
such that the PCIe PHY can be used in configurations where the Root
|
||||
Complex and Endpoint are not using a common reference clock.
|
||||
|
||||
Signed-off-by: Niklas Cassel <cassel@kernel.org>
|
||||
Link: https://lore.kernel.org/r/20240412125818.17052-3-cassel@kernel.org
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
.../phy/rockchip/phy-rockchip-snps-pcie3.c | 37 +++++++++++++++++++
|
||||
1 file changed, 37 insertions(+)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
|
||||
@@ -35,11 +35,17 @@
|
||||
#define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0
|
||||
#define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904
|
||||
#define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04
|
||||
+#define RK3588_PCIE3PHY_GRF_PHY0_LN0_CON1 0x1004
|
||||
+#define RK3588_PCIE3PHY_GRF_PHY0_LN1_CON1 0x1104
|
||||
+#define RK3588_PCIE3PHY_GRF_PHY1_LN0_CON1 0x2004
|
||||
+#define RK3588_PCIE3PHY_GRF_PHY1_LN1_CON1 0x2104
|
||||
#define RK3588_SRAM_INIT_DONE(reg) (reg & BIT(0))
|
||||
|
||||
#define RK3588_BIFURCATION_LANE_0_1 BIT(0)
|
||||
#define RK3588_BIFURCATION_LANE_2_3 BIT(1)
|
||||
#define RK3588_LANE_AGGREGATION BIT(2)
|
||||
+#define RK3588_RX_CMN_REFCLK_MODE_EN ((BIT(7) << 16) | BIT(7))
|
||||
+#define RK3588_RX_CMN_REFCLK_MODE_DIS (BIT(7) << 16)
|
||||
#define RK3588_PCIE1LN_SEL_EN (GENMASK(1, 0) << 16)
|
||||
#define RK3588_PCIE30_PHY_MODE_EN (GENMASK(2, 0) << 16)
|
||||
|
||||
@@ -60,6 +66,7 @@ struct rockchip_p3phy_priv {
|
||||
int num_clks;
|
||||
int num_lanes;
|
||||
u32 lanes[4];
|
||||
+ u32 rx_cmn_refclk_mode[4];
|
||||
};
|
||||
|
||||
struct rockchip_p3phy_ops {
|
||||
@@ -137,6 +144,19 @@ static int rockchip_p3phy_rk3588_init(st
|
||||
u8 mode = RK3588_LANE_AGGREGATION; /* default */
|
||||
int ret;
|
||||
|
||||
+ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY0_LN0_CON1,
|
||||
+ priv->rx_cmn_refclk_mode[0] ? RK3588_RX_CMN_REFCLK_MODE_EN :
|
||||
+ RK3588_RX_CMN_REFCLK_MODE_DIS);
|
||||
+ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY0_LN1_CON1,
|
||||
+ priv->rx_cmn_refclk_mode[1] ? RK3588_RX_CMN_REFCLK_MODE_EN :
|
||||
+ RK3588_RX_CMN_REFCLK_MODE_DIS);
|
||||
+ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY1_LN0_CON1,
|
||||
+ priv->rx_cmn_refclk_mode[2] ? RK3588_RX_CMN_REFCLK_MODE_EN :
|
||||
+ RK3588_RX_CMN_REFCLK_MODE_DIS);
|
||||
+ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY1_LN1_CON1,
|
||||
+ priv->rx_cmn_refclk_mode[3] ? RK3588_RX_CMN_REFCLK_MODE_EN :
|
||||
+ RK3588_RX_CMN_REFCLK_MODE_DIS);
|
||||
+
|
||||
/* Deassert PCIe PMA output clamp mode */
|
||||
regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, BIT(8) | BIT(24));
|
||||
|
||||
@@ -275,6 +295,23 @@ static int rockchip_p3phy_probe(struct p
|
||||
return priv->num_lanes;
|
||||
}
|
||||
|
||||
+ ret = of_property_read_variable_u32_array(dev->of_node,
|
||||
+ "rockchip,rx-common-refclk-mode",
|
||||
+ priv->rx_cmn_refclk_mode, 1,
|
||||
+ ARRAY_SIZE(priv->rx_cmn_refclk_mode));
|
||||
+ /*
|
||||
+ * if no rockchip,rx-common-refclk-mode, assume enabled for all lanes in
|
||||
+ * order to be DT backwards compatible. (Since HW reset val is enabled.)
|
||||
+ */
|
||||
+ if (ret == -EINVAL) {
|
||||
+ for (int i = 0; i < ARRAY_SIZE(priv->rx_cmn_refclk_mode); i++)
|
||||
+ priv->rx_cmn_refclk_mode[i] = 1;
|
||||
+ } else if (ret < 0) {
|
||||
+ dev_err(dev, "failed to read rockchip,rx-common-refclk-mode property %d\n",
|
||||
+ ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
priv->phy = devm_phy_create(dev, NULL, &rockchip_p3phy_ops);
|
||||
if (IS_ERR(priv->phy)) {
|
||||
dev_err(dev, "failed to create combphy\n");
|
||||
|
|
@ -0,0 +1,91 @@
|
|||
From 97789b93b792fc97ad4476b79e0f38ffa8e7e0ee Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Fri, 20 Oct 2023 16:11:41 +0200
|
||||
Subject: [PATCH] usb: dwc3: add optional PHY interface clocks
|
||||
|
||||
On Rockchip RK3588 one of the DWC3 cores is integrated weirdly and
|
||||
requires two extra clocks to be enabled. Without these extra clocks
|
||||
hot-plugging USB devices is broken.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
|
||||
Link: https://lore.kernel.org/r/20231020150022.48725-3-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
||||
---
|
||||
drivers/usb/dwc3/core.c | 28 ++++++++++++++++++++++++++++
|
||||
drivers/usb/dwc3/core.h | 4 ++++
|
||||
2 files changed, 32 insertions(+)
|
||||
|
||||
--- a/drivers/usb/dwc3/core.c
|
||||
+++ b/drivers/usb/dwc3/core.c
|
||||
@@ -860,8 +860,20 @@ static int dwc3_clk_enable(struct dwc3 *
|
||||
if (ret)
|
||||
goto disable_ref_clk;
|
||||
|
||||
+ ret = clk_prepare_enable(dwc->utmi_clk);
|
||||
+ if (ret)
|
||||
+ goto disable_susp_clk;
|
||||
+
|
||||
+ ret = clk_prepare_enable(dwc->pipe_clk);
|
||||
+ if (ret)
|
||||
+ goto disable_utmi_clk;
|
||||
+
|
||||
return 0;
|
||||
|
||||
+disable_utmi_clk:
|
||||
+ clk_disable_unprepare(dwc->utmi_clk);
|
||||
+disable_susp_clk:
|
||||
+ clk_disable_unprepare(dwc->susp_clk);
|
||||
disable_ref_clk:
|
||||
clk_disable_unprepare(dwc->ref_clk);
|
||||
disable_bus_clk:
|
||||
@@ -871,6 +883,8 @@ disable_bus_clk:
|
||||
|
||||
static void dwc3_clk_disable(struct dwc3 *dwc)
|
||||
{
|
||||
+ clk_disable_unprepare(dwc->pipe_clk);
|
||||
+ clk_disable_unprepare(dwc->utmi_clk);
|
||||
clk_disable_unprepare(dwc->susp_clk);
|
||||
clk_disable_unprepare(dwc->ref_clk);
|
||||
clk_disable_unprepare(dwc->bus_clk);
|
||||
@@ -1886,6 +1900,20 @@ static int dwc3_get_clocks(struct dwc3 *
|
||||
}
|
||||
}
|
||||
|
||||
+ /* specific to Rockchip RK3588 */
|
||||
+ dwc->utmi_clk = devm_clk_get_optional(dev, "utmi");
|
||||
+ if (IS_ERR(dwc->utmi_clk)) {
|
||||
+ return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk),
|
||||
+ "could not get utmi clock\n");
|
||||
+ }
|
||||
+
|
||||
+ /* specific to Rockchip RK3588 */
|
||||
+ dwc->pipe_clk = devm_clk_get_optional(dev, "pipe");
|
||||
+ if (IS_ERR(dwc->pipe_clk)) {
|
||||
+ return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk),
|
||||
+ "could not get pipe clock\n");
|
||||
+ }
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
--- a/drivers/usb/dwc3/core.h
|
||||
+++ b/drivers/usb/dwc3/core.h
|
||||
@@ -1003,6 +1003,8 @@ struct dwc3_scratchpad_array {
|
||||
* @bus_clk: clock for accessing the registers
|
||||
* @ref_clk: reference clock
|
||||
* @susp_clk: clock used when the SS phy is in low power (S3) state
|
||||
+ * @utmi_clk: clock used for USB2 PHY communication
|
||||
+ * @pipe_clk: clock used for USB3 PHY communication
|
||||
* @reset: reset control
|
||||
* @regs: base address for our registers
|
||||
* @regs_size: address space size
|
||||
@@ -1175,6 +1177,8 @@ struct dwc3 {
|
||||
struct clk *bus_clk;
|
||||
struct clk *ref_clk;
|
||||
struct clk *susp_clk;
|
||||
+ struct clk *utmi_clk;
|
||||
+ struct clk *pipe_clk;
|
||||
|
||||
struct reset_control *reset;
|
||||
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
From 3eaf2abd11aa7f3b2fb04d60c64b2c756fe030eb Mon Sep 17 00:00:00 2001
|
||||
From: Muhammed Efe Cetin <efectn@6tel.net>
|
||||
Date: Mon, 9 Oct 2023 22:27:26 +0300
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add sfc node to rk3588s
|
||||
|
||||
Add SFC (SPI Flash) to RK3588S SOC.
|
||||
|
||||
Reviewed-by: Dhruva Gole <d-gole@ti.com>
|
||||
Signed-off-by: Muhammed Efe Cetin <efectn@6tel.net>
|
||||
Link: https://lore.kernel.org/r/d36a64edfaede92ce2e158b0d9dc4f5998e019e3.1696878787.git.efectn@6tel.net
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 11 +++++++++++
|
||||
1 file changed, 11 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
@@ -1425,6 +1425,17 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ sfc: spi@fe2b0000 {
|
||||
+ compatible = "rockchip,sfc";
|
||||
+ reg = <0x0 0xfe2b0000 0x0 0x4000>;
|
||||
+ interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
|
||||
+ clock-names = "clk_sfc", "hclk_sfc";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
sdmmc: mmc@fe2c0000 {
|
||||
compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
|
||||
reg = <0x0 0xfe2c0000 0x0 0x4000>;
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
From bf012368bb0ab69167d49715789fac34dfcd457e Mon Sep 17 00:00:00 2001
|
||||
From: Ondrej Jirman <megi@xff.cz>
|
||||
Date: Sun, 8 Oct 2023 15:04:59 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add I2S2 M0 pin definitions to rk3588s
|
||||
|
||||
This is used on Orange Pi 5 Plus.
|
||||
|
||||
Signed-off-by: Ondrej Jirman <megi@xff.cz>
|
||||
Link: https://lore.kernel.org/r/20231008130515.1155664-2-megi@xff.cz
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
.../boot/dts/rockchip/rk3588s-pinctrl.dtsi | 35 +++++++++++++++++++
|
||||
1 file changed, 35 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi
|
||||
@@ -1350,6 +1350,41 @@
|
||||
|
||||
i2s2 {
|
||||
/omit-if-no-ref/
|
||||
+ i2s2m0_lrck: i2s2m0-lrck {
|
||||
+ rockchip,pins =
|
||||
+ /* i2s2m0_lrck */
|
||||
+ <2 RK_PC0 2 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ i2s2m0_mclk: i2s2m0-mclk {
|
||||
+ rockchip,pins =
|
||||
+ /* i2s2m0_mclk */
|
||||
+ <2 RK_PB6 2 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ i2s2m0_sclk: i2s2m0-sclk {
|
||||
+ rockchip,pins =
|
||||
+ /* i2s2m0_sclk */
|
||||
+ <2 RK_PB7 2 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ i2s2m0_sdi: i2s2m0-sdi {
|
||||
+ rockchip,pins =
|
||||
+ /* i2s2m0_sdi */
|
||||
+ <2 RK_PC3 2 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ i2s2m0_sdo: i2s2m0-sdo {
|
||||
+ rockchip,pins =
|
||||
+ /* i2s2m0_sdo */
|
||||
+ <4 RK_PC3 2 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
i2s2m1_lrck: i2s2m1-lrck {
|
||||
rockchip,pins =
|
||||
/* i2s2m1_lrck */
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
From 3d77a3e51b0faed820a8db985dce5af1cc4eae32 Mon Sep 17 00:00:00 2001
|
||||
From: Ondrej Jirman <megi@xff.cz>
|
||||
Date: Sun, 8 Oct 2023 15:05:00 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add UART9 M0 pin definitions to rk3588s
|
||||
|
||||
This is used on Orange Pi 5 Plus.
|
||||
|
||||
Signed-off-by: Ondrej Jirman <megi@xff.cz>
|
||||
Link: https://lore.kernel.org/r/20231008130515.1155664-3-megi@xff.cz
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi | 9 +++++++++
|
||||
1 file changed, 9 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi
|
||||
@@ -3343,6 +3343,15 @@
|
||||
|
||||
uart9 {
|
||||
/omit-if-no-ref/
|
||||
+ uart9m0_xfer: uart9m0-xfer {
|
||||
+ rockchip,pins =
|
||||
+ /* uart9_rx_m0 */
|
||||
+ <2 RK_PC4 10 &pcfg_pull_up>,
|
||||
+ /* uart9_tx_m0 */
|
||||
+ <2 RK_PC2 10 &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
uart9m1_xfer: uart9m1-xfer {
|
||||
rockchip,pins =
|
||||
/* uart9_rx_m1 */
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
From dd6dc0c4c1265129c229e26917bf4de1d97ff91f Mon Sep 17 00:00:00 2001
|
||||
From: Benjamin Gaignard <benjamin.gaignard@collabora.com>
|
||||
Date: Fri, 6 Oct 2023 08:53:34 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add AV1 decoder node to rk3588s
|
||||
|
||||
Add node for AV1 video decoder.
|
||||
|
||||
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
|
||||
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20231006065334.8117-1-benjamin.gaignard@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 13 +++++++++++++
|
||||
1 file changed, 13 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
@@ -2314,6 +2314,19 @@
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
+
|
||||
+ av1d: video-codec@fdc70000 {
|
||||
+ compatible = "rockchip,rk3588-av1-vpu";
|
||||
+ reg = <0x0 0xfdc70000 0x0 0x800>;
|
||||
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
+ interrupt-names = "vdpu";
|
||||
+ assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
|
||||
+ assigned-clock-rates = <400000000>, <400000000>;
|
||||
+ clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
|
||||
+ clock-names = "aclk", "hclk";
|
||||
+ power-domains = <&power RK3588_PD_AV1>;
|
||||
+ resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>;
|
||||
+ };
|
||||
};
|
||||
|
||||
#include "rk3588s-pinctrl.dtsi"
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
From 5a6976b1040a2f99ab84eddbfa7cd072ac5d10fc Mon Sep 17 00:00:00 2001
|
||||
From: Sascha Hauer <s.hauer@pengutronix.de>
|
||||
Date: Wed, 18 Oct 2023 08:17:14 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add DFI to rk3588s
|
||||
|
||||
The DFI unit can be used to measure DRAM utilization using perf. Add the
|
||||
node to the device tree. The DFI needs a rockchip,pmu phandle to the pmu
|
||||
containing registers for SDRAM configuration details. This is added in
|
||||
this patch as well.
|
||||
|
||||
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
||||
Link: https://lore.kernel.org/r/20231018061714.3553817-27-s.hauer@pengutronix.de
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 16 ++++++++++++++++
|
||||
1 file changed, 16 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
@@ -443,6 +443,11 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ pmu1grf: syscon@fd58a000 {
|
||||
+ compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
|
||||
+ reg = <0x0 0xfd58a000 0x0 0x10000>;
|
||||
+ };
|
||||
+
|
||||
sys_grf: syscon@fd58c000 {
|
||||
compatible = "rockchip,rk3588-sys-grf", "syscon";
|
||||
reg = <0x0 0xfd58c000 0x0 0x1000>;
|
||||
@@ -1330,6 +1335,17 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ dfi: dfi@fe060000 {
|
||||
+ reg = <0x00 0xfe060000 0x00 0x10000>;
|
||||
+ compatible = "rockchip,rk3588-dfi";
|
||||
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
+ <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
+ interrupt-names = "ch0", "ch1", "ch2", "ch3";
|
||||
+ rockchip,pmu = <&pmu1grf>;
|
||||
+ };
|
||||
+
|
||||
gmac1: ethernet@fe1c0000 {
|
||||
compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
|
||||
reg = <0x0 0xfe1c0000 0x0 0x10000>;
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
From bbd3778da16b3d448832b843f80bcde1aff26290 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Fri, 20 Oct 2023 16:11:42 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: rk3588s: Add USB3 host controller
|
||||
|
||||
RK3588 has three USB3 controllers. This adds the host-only controller,
|
||||
which is using the naneng-combphy shared with PCIe and SATA.
|
||||
|
||||
The other two are dual-role and using a different PHY that is not yet
|
||||
supported upstream.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20231020150022.48725-4-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 21 +++++++++++++++++++++
|
||||
1 file changed, 21 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
@@ -443,6 +443,27 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ usb_host2_xhci: usb@fcd00000 {
|
||||
+ compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
|
||||
+ reg = <0x0 0xfcd00000 0x0 0x400000>;
|
||||
+ interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
+ clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
|
||||
+ <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>,
|
||||
+ <&cru CLK_PIPEPHY2_PIPE_U3_G>;
|
||||
+ clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe";
|
||||
+ dr_mode = "host";
|
||||
+ phys = <&combphy2_psu PHY_TYPE_USB3>;
|
||||
+ phy-names = "usb3-phy";
|
||||
+ phy_type = "utmi_wide";
|
||||
+ resets = <&cru SRST_A_USB3OTG2>;
|
||||
+ snps,dis_enblslpm_quirk;
|
||||
+ snps,dis-u2-freeclk-exists-quirk;
|
||||
+ snps,dis-del-phy-power-chg-quirk;
|
||||
+ snps,dis-tx-ipgap-linecheck-quirk;
|
||||
+ snps,dis_rxdet_inp3_quirk;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
pmu1grf: syscon@fd58a000 {
|
||||
compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
|
||||
reg = <0x0 0xfd58a000 0x0 0x10000>;
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
From 815f986f33eeb06652d59d8a4d405d4fdb4e59a8 Mon Sep 17 00:00:00 2001
|
||||
From: Heiko Stuebner <heiko.stuebner@cherry.de>
|
||||
Date: Fri, 1 Dec 2023 14:48:59 +0100
|
||||
Subject: [PATCH] arm64: dts: rockchip: drop interrupt-names property from
|
||||
rk3588s dfi
|
||||
|
||||
The dfi binding does not specify interrupt names, with the interrupts
|
||||
just specifying channels 0-x. So drop the unspecified property.
|
||||
|
||||
Fixes: 5a6976b1040a ("arm64: dts: rockchip: Add DFI to rk3588s")
|
||||
Reported-by: Jagan Teki <jagan@edgeble.ai>
|
||||
Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
|
||||
Link: https://lore.kernel.org/r/20231201134859.322491-1-heiko@sntech.de
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 1 -
|
||||
1 file changed, 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
@@ -1363,7 +1363,6 @@
|
||||
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
- interrupt-names = "ch0", "ch1", "ch2", "ch3";
|
||||
rockchip,pmu = <&pmu1grf>;
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,139 @@
|
|||
From 9918d10d16665527e59fdb87c5acac70cc1cfe8f Mon Sep 17 00:00:00 2001
|
||||
From: Heiko Stuebner <heiko.stuebner@cherry.de>
|
||||
Date: Tue, 5 Dec 2023 17:48:39 +0100
|
||||
Subject: [PATCH] arm64: dts: rockchip: move rk3588 serial aliases to soc dtsi
|
||||
|
||||
The serial ports on rk3588 are named uart0 - uart9. Board schematics
|
||||
also use these exact numbers and we want those names to also reflect
|
||||
in the OS devices because everything else would just cause confusion.
|
||||
|
||||
To prevent each board repeating their list of serial aliases, move them
|
||||
to the soc dtsi, as all previous Rockchip soc do already.
|
||||
|
||||
Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
|
||||
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
|
||||
Link: https://lore.kernel.org/r/20231205164842.556684-2-heiko@sntech.de
|
||||
---
|
||||
.../boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts | 4 ----
|
||||
.../boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts | 4 ----
|
||||
arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 1 -
|
||||
arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 1 -
|
||||
.../boot/dts/rockchip/rk3588-orangepi-5-plus.dts | 1 -
|
||||
arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts | 1 -
|
||||
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 1 -
|
||||
arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 2 --
|
||||
.../boot/dts/rockchip/rk3588s-indiedroid-nova.dts | 1 -
|
||||
.../boot/dts/rockchip/rk3588s-khadas-edge2.dts | 1 -
|
||||
arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts | 1 -
|
||||
arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 1 -
|
||||
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 13 +++++++++++++
|
||||
13 files changed, 13 insertions(+), 19 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts
|
||||
@@ -12,10 +12,6 @@
|
||||
compatible = "edgeble,neural-compute-module-6a-io",
|
||||
"edgeble,neural-compute-module-6a", "rockchip,rk3588";
|
||||
|
||||
- aliases {
|
||||
- serial2 = &uart2;
|
||||
- };
|
||||
-
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts
|
||||
@@ -12,10 +12,6 @@
|
||||
compatible = "edgeble,neural-compute-module-6b-io",
|
||||
"edgeble,neural-compute-module-6b", "rockchip,rk3588";
|
||||
|
||||
- aliases {
|
||||
- serial2 = &uart2;
|
||||
- };
|
||||
-
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
|
||||
@@ -16,7 +16,6 @@
|
||||
|
||||
aliases {
|
||||
mmc0 = &sdhci;
|
||||
- serial2 = &uart2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
|
||||
@@ -19,7 +19,6 @@
|
||||
aliases {
|
||||
mmc0 = &sdhci;
|
||||
mmc1 = &sdmmc;
|
||||
- serial2 = &uart2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
@@ -12,7 +12,6 @@
|
||||
aliases {
|
||||
mmc0 = &sdhci;
|
||||
mmc1 = &sdmmc;
|
||||
- serial2 = &uart2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts
|
||||
@@ -15,7 +15,6 @@
|
||||
mmc0 = &sdhci;
|
||||
mmc1 = &sdmmc;
|
||||
mmc2 = &sdio;
|
||||
- serial2 = &uart2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
|
||||
@@ -12,7 +12,6 @@
|
||||
|
||||
aliases {
|
||||
mmc0 = &sdhci;
|
||||
- serial2 = &uart2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
|
||||
@@ -14,7 +14,6 @@
|
||||
aliases {
|
||||
mmc0 = &sdhci;
|
||||
mmc1 = &sdmmc;
|
||||
- serial2 = &uart2;
|
||||
};
|
||||
|
||||
analog-sound {
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
@@ -18,6 +18,19 @@
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
+ aliases {
|
||||
+ serial0 = &uart0;
|
||||
+ serial1 = &uart1;
|
||||
+ serial2 = &uart2;
|
||||
+ serial3 = &uart3;
|
||||
+ serial4 = &uart4;
|
||||
+ serial5 = &uart5;
|
||||
+ serial6 = &uart6;
|
||||
+ serial7 = &uart7;
|
||||
+ serial8 = &uart8;
|
||||
+ serial9 = &uart9;
|
||||
+ };
|
||||
+
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
From 328e901b7b03d292c1520ffb38e9164feef4f1ea Mon Sep 17 00:00:00 2001
|
||||
From: Heiko Stuebner <heiko.stuebner@cherry.de>
|
||||
Date: Tue, 5 Dec 2023 17:48:40 +0100
|
||||
Subject: [PATCH] arm64: dts: rockchip: add rk3588 i2c aliases to soc dtsi
|
||||
|
||||
The i2c controllers on rk3588 are named i2c0 - i2c8. Board schematics
|
||||
also use these exact numbers and we want those names to also reflect
|
||||
in the OS devices because everything else would just cause confusion.
|
||||
Userspace i2c access is a thing afterall.
|
||||
|
||||
To prevent each board repeating their list of i2c aliases, define them
|
||||
in the soc dtsi, as all previous Rockchip soc do already.
|
||||
|
||||
Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
|
||||
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
|
||||
Link: https://lore.kernel.org/r/20231205164842.556684-3-heiko@sntech.de
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 9 +++++++++
|
||||
1 file changed, 9 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
@@ -19,6 +19,15 @@
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
+ i2c0 = &i2c0;
|
||||
+ i2c1 = &i2c1;
|
||||
+ i2c2 = &i2c2;
|
||||
+ i2c3 = &i2c3;
|
||||
+ i2c4 = &i2c4;
|
||||
+ i2c5 = &i2c5;
|
||||
+ i2c6 = &i2c6;
|
||||
+ i2c7 = &i2c7;
|
||||
+ i2c8 = &i2c8;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
From a024abedbca99a20aeb96f5beec9ded13c85dcb3 Mon Sep 17 00:00:00 2001
|
||||
From: Heiko Stuebner <heiko.stuebner@cherry.de>
|
||||
Date: Tue, 5 Dec 2023 17:48:41 +0100
|
||||
Subject: [PATCH] arm64: dts: rockchip: add rk3588 gpio aliases to soc dtsi
|
||||
|
||||
The gpio controllers on rk3588 are named gpio0 - gpio4. Board schematics
|
||||
also use these exact numbers and we want those names to also reflect
|
||||
in the OS devices because everything else would just cause confusion.
|
||||
Userspace gpio access is a thing afterall.
|
||||
|
||||
To prevent each board repeating their list of gpio aliases, define them
|
||||
in the soc dtsi, as previous Rockchip soc like the rk356x do already.
|
||||
|
||||
Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
|
||||
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
|
||||
Link: https://lore.kernel.org/r/20231205164842.556684-4-heiko@sntech.de
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 5 +++++
|
||||
1 file changed, 5 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
@@ -19,6 +19,11 @@
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
+ gpio0 = &gpio0;
|
||||
+ gpio1 = &gpio1;
|
||||
+ gpio2 = &gpio2;
|
||||
+ gpio3 = &gpio3;
|
||||
+ gpio4 = &gpio4;
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
From a86e88043de929da76f7f6cf0990ba92aed8391a Mon Sep 17 00:00:00 2001
|
||||
From: Heiko Stuebner <heiko.stuebner@cherry.de>
|
||||
Date: Tue, 5 Dec 2023 17:48:42 +0100
|
||||
Subject: [PATCH] arm64: dts: rockchip: add rk3588 spi aliases to soc dtsi
|
||||
|
||||
The spi controllers on rk3588 are named spi0 - spi4. Board schematics
|
||||
also use these exact numbers and we want those names to also reflect
|
||||
in the OS devices because everything else would just cause confusion.
|
||||
Userspace spi access is a thing afterall.
|
||||
|
||||
To prevent each board repeating their list of spi aliases, define them
|
||||
in the soc dtsi, as previous Rockchip soc like the rk356x do already.
|
||||
|
||||
Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
|
||||
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
|
||||
Link: https://lore.kernel.org/r/20231205164842.556684-5-heiko@sntech.de
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 5 +++++
|
||||
1 file changed, 5 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
@@ -43,6 +43,11 @@
|
||||
serial7 = &uart7;
|
||||
serial8 = &uart8;
|
||||
serial9 = &uart9;
|
||||
+ spi0 = &spi0;
|
||||
+ spi1 = &spi1;
|
||||
+ spi2 = &spi2;
|
||||
+ spi3 = &spi3;
|
||||
+ spi4 = &spi4;
|
||||
};
|
||||
|
||||
cpus {
|
||||
|
|
@ -0,0 +1,120 @@
|
|||
From d895dbef3f3a31ab50491bb48552e798cf555987 Mon Sep 17 00:00:00 2001
|
||||
From: Andy Yan <andy.yan@rock-chips.com>
|
||||
Date: Mon, 11 Dec 2023 20:00:04 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add vop on rk3588
|
||||
|
||||
Add vop dt node for rk3588.
|
||||
|
||||
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
|
||||
Link: https://lore.kernel.org/r/20231211120004.1785616-1-andyshrk@163.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 83 +++++++++++++++++++++++
|
||||
1 file changed, 83 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
@@ -394,6 +394,11 @@
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
+ display_subsystem: display-subsystem {
|
||||
+ compatible = "rockchip,display-subsystem";
|
||||
+ ports = <&vop_out>;
|
||||
+ };
|
||||
+
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
@@ -506,6 +511,16 @@
|
||||
reg = <0x0 0xfd58c000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
+ vop_grf: syscon@fd5a4000 {
|
||||
+ compatible = "rockchip,rk3588-vop-grf", "syscon";
|
||||
+ reg = <0x0 0xfd5a4000 0x0 0x2000>;
|
||||
+ };
|
||||
+
|
||||
+ vo1_grf: syscon@fd5a8000 {
|
||||
+ compatible = "rockchip,rk3588-vo-grf", "syscon";
|
||||
+ reg = <0x0 0xfd5a8000 0x0 0x100>;
|
||||
+ };
|
||||
+
|
||||
php_grf: syscon@fd5b0000 {
|
||||
compatible = "rockchip,rk3588-php-grf", "syscon";
|
||||
reg = <0x0 0xfd5b0000 0x0 0x1000>;
|
||||
@@ -625,6 +640,74 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ vop: vop@fdd90000 {
|
||||
+ compatible = "rockchip,rk3588-vop";
|
||||
+ reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;
|
||||
+ reg-names = "vop", "gamma-lut";
|
||||
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
+ clocks = <&cru ACLK_VOP>,
|
||||
+ <&cru HCLK_VOP>,
|
||||
+ <&cru DCLK_VOP0>,
|
||||
+ <&cru DCLK_VOP1>,
|
||||
+ <&cru DCLK_VOP2>,
|
||||
+ <&cru DCLK_VOP3>,
|
||||
+ <&cru PCLK_VOP_ROOT>;
|
||||
+ clock-names = "aclk",
|
||||
+ "hclk",
|
||||
+ "dclk_vp0",
|
||||
+ "dclk_vp1",
|
||||
+ "dclk_vp2",
|
||||
+ "dclk_vp3",
|
||||
+ "pclk_vop";
|
||||
+ iommus = <&vop_mmu>;
|
||||
+ power-domains = <&power RK3588_PD_VOP>;
|
||||
+ rockchip,grf = <&sys_grf>;
|
||||
+ rockchip,vop-grf = <&vop_grf>;
|
||||
+ rockchip,vo1-grf = <&vo1_grf>;
|
||||
+ rockchip,pmu = <&pmu>;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ vop_out: ports {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ vp0: port@0 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ reg = <0>;
|
||||
+ };
|
||||
+
|
||||
+ vp1: port@1 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ reg = <1>;
|
||||
+ };
|
||||
+
|
||||
+ vp2: port@2 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ reg = <2>;
|
||||
+ };
|
||||
+
|
||||
+ vp3: port@3 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ reg = <3>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vop_mmu: iommu@fdd97e00 {
|
||||
+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
|
||||
+ reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>;
|
||||
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
|
||||
+ clock-names = "aclk", "iface";
|
||||
+ #iommu-cells = <0>;
|
||||
+ power-domains = <&power RK3588_PD_VOP>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
uart0: serial@fd890000 {
|
||||
compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
||||
reg = <0x0 0xfd890000 0x0 0x100>;
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
From 11d28971aaaf5de6f50790fb21f1113fee21d320 Mon Sep 17 00:00:00 2001
|
||||
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Date: Mon, 19 Feb 2024 22:46:25 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add HDMI0 PHY to rk3588
|
||||
|
||||
Add DT nodes for HDMI0 PHY and related syscon found on RK3588 SoC.
|
||||
|
||||
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20240219204626.284399-1-cristian.ciocaltea@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 21 +++++++++++++++++++++
|
||||
1 file changed, 21 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
@@ -586,6 +586,11 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ hdptxphy0_grf: syscon@fd5e0000 {
|
||||
+ compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
|
||||
+ reg = <0x0 0xfd5e0000 0x0 0x100>;
|
||||
+ };
|
||||
+
|
||||
ioc: syscon@fd5f0000 {
|
||||
compatible = "rockchip,rk3588-ioc", "syscon";
|
||||
reg = <0x0 0xfd5f0000 0x0 0x10000>;
|
||||
@@ -2358,6 +2363,22 @@
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
+ hdptxphy_hdmi0: phy@fed60000 {
|
||||
+ compatible = "rockchip,rk3588-hdptx-phy";
|
||||
+ reg = <0x0 0xfed60000 0x0 0x2000>;
|
||||
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
|
||||
+ clock-names = "ref", "apb";
|
||||
+ #phy-cells = <0>;
|
||||
+ resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
|
||||
+ <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
|
||||
+ <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>,
|
||||
+ <&cru SRST_HDPTX0_LCPLL>;
|
||||
+ reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
|
||||
+ "lcpll";
|
||||
+ rockchip,grf = <&hdptxphy0_grf>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
combphy0_ps: phy@fee00000 {
|
||||
compatible = "rockchip,rk3588-naneng-combphy";
|
||||
reg = <0x0 0xfee00000 0x0 0x100>;
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
From 2047366b9eff8fada2a118588b0478de6e92d02c Mon Sep 17 00:00:00 2001
|
||||
From: Heiko Stuebner <heiko@sntech.de>
|
||||
Date: Tue, 27 Feb 2024 22:05:21 +0100
|
||||
Subject: [PATCH] arm64: dts: rockchip: add clock to vo1-grf syscon on rk3588
|
||||
|
||||
The VO*-general-register-files need a clock, so add the correct one.
|
||||
|
||||
Cc: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Link: https://lore.kernel.org/r/20240227210521.724754-1-heiko@sntech.de
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
@@ -519,6 +519,7 @@
|
||||
vo1_grf: syscon@fd5a8000 {
|
||||
compatible = "rockchip,rk3588-vo-grf", "syscon";
|
||||
reg = <0x0 0xfd5a8000 0x0 0x100>;
|
||||
+ clocks = <&cru PCLK_VO1GRF>;
|
||||
};
|
||||
|
||||
php_grf: syscon@fd5b0000 {
|
||||
|
|
@ -0,0 +1,81 @@
|
|||
From 6fca4edb93d335f29f81e484936f38a5eed6a9b1 Mon Sep 17 00:00:00 2001
|
||||
From: Boris Brezillon <boris.brezillon@collabora.com>
|
||||
Date: Tue, 26 Mar 2024 17:52:06 +0100
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add rk3588 GPU node
|
||||
|
||||
Add Mali GPU Node to the RK3588 SoC DT including GPU clock
|
||||
operating points
|
||||
|
||||
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20240326165232.73585-3-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 56 +++++++++++++++++++++++
|
||||
1 file changed, 56 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
@@ -501,6 +501,62 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ gpu: gpu@fb000000 {
|
||||
+ compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
|
||||
+ reg = <0x0 0xfb000000 0x0 0x200000>;
|
||||
+ #cooling-cells = <2>;
|
||||
+ assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
|
||||
+ assigned-clock-rates = <200000000>;
|
||||
+ clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
|
||||
+ <&cru CLK_GPU_STACKS>;
|
||||
+ clock-names = "core", "coregroup", "stacks";
|
||||
+ dynamic-power-coefficient = <2982>;
|
||||
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
+ interrupt-names = "job", "mmu", "gpu";
|
||||
+ operating-points-v2 = <&gpu_opp_table>;
|
||||
+ power-domains = <&power RK3588_PD_GPU>;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ gpu_opp_table: opp-table {
|
||||
+ compatible = "operating-points-v2";
|
||||
+
|
||||
+ opp-300000000 {
|
||||
+ opp-hz = /bits/ 64 <300000000>;
|
||||
+ opp-microvolt = <675000 675000 850000>;
|
||||
+ };
|
||||
+ opp-400000000 {
|
||||
+ opp-hz = /bits/ 64 <400000000>;
|
||||
+ opp-microvolt = <675000 675000 850000>;
|
||||
+ };
|
||||
+ opp-500000000 {
|
||||
+ opp-hz = /bits/ 64 <500000000>;
|
||||
+ opp-microvolt = <675000 675000 850000>;
|
||||
+ };
|
||||
+ opp-600000000 {
|
||||
+ opp-hz = /bits/ 64 <600000000>;
|
||||
+ opp-microvolt = <675000 675000 850000>;
|
||||
+ };
|
||||
+ opp-700000000 {
|
||||
+ opp-hz = /bits/ 64 <700000000>;
|
||||
+ opp-microvolt = <700000 700000 850000>;
|
||||
+ };
|
||||
+ opp-800000000 {
|
||||
+ opp-hz = /bits/ 64 <800000000>;
|
||||
+ opp-microvolt = <750000 750000 850000>;
|
||||
+ };
|
||||
+ opp-900000000 {
|
||||
+ opp-hz = /bits/ 64 <900000000>;
|
||||
+ opp-microvolt = <800000 800000 850000>;
|
||||
+ };
|
||||
+ opp-1000000000 {
|
||||
+ opp-hz = /bits/ 64 <1000000000>;
|
||||
+ opp-microvolt = <850000 850000 850000>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
pmu1grf: syscon@fd58a000 {
|
||||
compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
|
||||
reg = <0x0 0xfd58a000 0x0 0x10000>;
|
||||
|
|
@ -0,0 +1,384 @@
|
|||
From cbb97fe18e299ece1c0074924c630de6a19b320f Mon Sep 17 00:00:00 2001
|
||||
From: Diederik de Haas <didi.debian@cknow.org>
|
||||
Date: Sat, 6 Apr 2024 19:28:04 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: Fix ordering of nodes on rk3588s
|
||||
|
||||
Fix the ordering of the main nodes by sorting them alphabetically and
|
||||
then the ones with a memory address sequentially by that address.
|
||||
|
||||
Signed-off-by: Diederik de Haas <didi.debian@cknow.org>
|
||||
Link: https://lore.kernel.org/r/20240406172821.34173-1-didi.debian@cknow.org
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 304 +++++++++++-----------
|
||||
1 file changed, 152 insertions(+), 152 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
@@ -347,6 +347,11 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ display_subsystem: display-subsystem {
|
||||
+ compatible = "rockchip,display-subsystem";
|
||||
+ ports = <&vop_out>;
|
||||
+ };
|
||||
+
|
||||
firmware {
|
||||
optee: optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
@@ -394,11 +399,6 @@
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
- display_subsystem: display-subsystem {
|
||||
- compatible = "rockchip,display-subsystem";
|
||||
- ports = <&vop_out>;
|
||||
- };
|
||||
-
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
@@ -436,6 +436,62 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ gpu: gpu@fb000000 {
|
||||
+ compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
|
||||
+ reg = <0x0 0xfb000000 0x0 0x200000>;
|
||||
+ #cooling-cells = <2>;
|
||||
+ assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
|
||||
+ assigned-clock-rates = <200000000>;
|
||||
+ clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
|
||||
+ <&cru CLK_GPU_STACKS>;
|
||||
+ clock-names = "core", "coregroup", "stacks";
|
||||
+ dynamic-power-coefficient = <2982>;
|
||||
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
+ interrupt-names = "job", "mmu", "gpu";
|
||||
+ operating-points-v2 = <&gpu_opp_table>;
|
||||
+ power-domains = <&power RK3588_PD_GPU>;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ gpu_opp_table: opp-table {
|
||||
+ compatible = "operating-points-v2";
|
||||
+
|
||||
+ opp-300000000 {
|
||||
+ opp-hz = /bits/ 64 <300000000>;
|
||||
+ opp-microvolt = <675000 675000 850000>;
|
||||
+ };
|
||||
+ opp-400000000 {
|
||||
+ opp-hz = /bits/ 64 <400000000>;
|
||||
+ opp-microvolt = <675000 675000 850000>;
|
||||
+ };
|
||||
+ opp-500000000 {
|
||||
+ opp-hz = /bits/ 64 <500000000>;
|
||||
+ opp-microvolt = <675000 675000 850000>;
|
||||
+ };
|
||||
+ opp-600000000 {
|
||||
+ opp-hz = /bits/ 64 <600000000>;
|
||||
+ opp-microvolt = <675000 675000 850000>;
|
||||
+ };
|
||||
+ opp-700000000 {
|
||||
+ opp-hz = /bits/ 64 <700000000>;
|
||||
+ opp-microvolt = <700000 700000 850000>;
|
||||
+ };
|
||||
+ opp-800000000 {
|
||||
+ opp-hz = /bits/ 64 <800000000>;
|
||||
+ opp-microvolt = <750000 750000 850000>;
|
||||
+ };
|
||||
+ opp-900000000 {
|
||||
+ opp-hz = /bits/ 64 <900000000>;
|
||||
+ opp-microvolt = <800000 800000 850000>;
|
||||
+ };
|
||||
+ opp-1000000000 {
|
||||
+ opp-hz = /bits/ 64 <1000000000>;
|
||||
+ opp-microvolt = <850000 850000 850000>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
usb_host0_ehci: usb@fc800000 {
|
||||
compatible = "rockchip,rk3588-ehci", "generic-ehci";
|
||||
reg = <0x0 0xfc800000 0x0 0x40000>;
|
||||
@@ -501,62 +557,6 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
- gpu: gpu@fb000000 {
|
||||
- compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
|
||||
- reg = <0x0 0xfb000000 0x0 0x200000>;
|
||||
- #cooling-cells = <2>;
|
||||
- assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
|
||||
- assigned-clock-rates = <200000000>;
|
||||
- clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
|
||||
- <&cru CLK_GPU_STACKS>;
|
||||
- clock-names = "core", "coregroup", "stacks";
|
||||
- dynamic-power-coefficient = <2982>;
|
||||
- interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
- <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
- <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
- interrupt-names = "job", "mmu", "gpu";
|
||||
- operating-points-v2 = <&gpu_opp_table>;
|
||||
- power-domains = <&power RK3588_PD_GPU>;
|
||||
- status = "disabled";
|
||||
-
|
||||
- gpu_opp_table: opp-table {
|
||||
- compatible = "operating-points-v2";
|
||||
-
|
||||
- opp-300000000 {
|
||||
- opp-hz = /bits/ 64 <300000000>;
|
||||
- opp-microvolt = <675000 675000 850000>;
|
||||
- };
|
||||
- opp-400000000 {
|
||||
- opp-hz = /bits/ 64 <400000000>;
|
||||
- opp-microvolt = <675000 675000 850000>;
|
||||
- };
|
||||
- opp-500000000 {
|
||||
- opp-hz = /bits/ 64 <500000000>;
|
||||
- opp-microvolt = <675000 675000 850000>;
|
||||
- };
|
||||
- opp-600000000 {
|
||||
- opp-hz = /bits/ 64 <600000000>;
|
||||
- opp-microvolt = <675000 675000 850000>;
|
||||
- };
|
||||
- opp-700000000 {
|
||||
- opp-hz = /bits/ 64 <700000000>;
|
||||
- opp-microvolt = <700000 700000 850000>;
|
||||
- };
|
||||
- opp-800000000 {
|
||||
- opp-hz = /bits/ 64 <800000000>;
|
||||
- opp-microvolt = <750000 750000 850000>;
|
||||
- };
|
||||
- opp-900000000 {
|
||||
- opp-hz = /bits/ 64 <900000000>;
|
||||
- opp-microvolt = <800000 800000 850000>;
|
||||
- };
|
||||
- opp-1000000000 {
|
||||
- opp-hz = /bits/ 64 <1000000000>;
|
||||
- opp-microvolt = <850000 850000 850000>;
|
||||
- };
|
||||
- };
|
||||
- };
|
||||
-
|
||||
pmu1grf: syscon@fd58a000 {
|
||||
compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
|
||||
reg = <0x0 0xfd58a000 0x0 0x10000>;
|
||||
@@ -702,74 +702,6 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
- vop: vop@fdd90000 {
|
||||
- compatible = "rockchip,rk3588-vop";
|
||||
- reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;
|
||||
- reg-names = "vop", "gamma-lut";
|
||||
- interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
- clocks = <&cru ACLK_VOP>,
|
||||
- <&cru HCLK_VOP>,
|
||||
- <&cru DCLK_VOP0>,
|
||||
- <&cru DCLK_VOP1>,
|
||||
- <&cru DCLK_VOP2>,
|
||||
- <&cru DCLK_VOP3>,
|
||||
- <&cru PCLK_VOP_ROOT>;
|
||||
- clock-names = "aclk",
|
||||
- "hclk",
|
||||
- "dclk_vp0",
|
||||
- "dclk_vp1",
|
||||
- "dclk_vp2",
|
||||
- "dclk_vp3",
|
||||
- "pclk_vop";
|
||||
- iommus = <&vop_mmu>;
|
||||
- power-domains = <&power RK3588_PD_VOP>;
|
||||
- rockchip,grf = <&sys_grf>;
|
||||
- rockchip,vop-grf = <&vop_grf>;
|
||||
- rockchip,vo1-grf = <&vo1_grf>;
|
||||
- rockchip,pmu = <&pmu>;
|
||||
- status = "disabled";
|
||||
-
|
||||
- vop_out: ports {
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <0>;
|
||||
-
|
||||
- vp0: port@0 {
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <0>;
|
||||
- reg = <0>;
|
||||
- };
|
||||
-
|
||||
- vp1: port@1 {
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <0>;
|
||||
- reg = <1>;
|
||||
- };
|
||||
-
|
||||
- vp2: port@2 {
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <0>;
|
||||
- reg = <2>;
|
||||
- };
|
||||
-
|
||||
- vp3: port@3 {
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <0>;
|
||||
- reg = <3>;
|
||||
- };
|
||||
- };
|
||||
- };
|
||||
-
|
||||
- vop_mmu: iommu@fdd97e00 {
|
||||
- compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
|
||||
- reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>;
|
||||
- interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
- clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
|
||||
- clock-names = "aclk", "iface";
|
||||
- #iommu-cells = <0>;
|
||||
- power-domains = <&power RK3588_PD_VOP>;
|
||||
- status = "disabled";
|
||||
- };
|
||||
-
|
||||
uart0: serial@fd890000 {
|
||||
compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
||||
reg = <0x0 0xfd890000 0x0 0x100>;
|
||||
@@ -1140,6 +1072,87 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ av1d: video-codec@fdc70000 {
|
||||
+ compatible = "rockchip,rk3588-av1-vpu";
|
||||
+ reg = <0x0 0xfdc70000 0x0 0x800>;
|
||||
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
+ interrupt-names = "vdpu";
|
||||
+ assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
|
||||
+ assigned-clock-rates = <400000000>, <400000000>;
|
||||
+ clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
|
||||
+ clock-names = "aclk", "hclk";
|
||||
+ power-domains = <&power RK3588_PD_AV1>;
|
||||
+ resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>;
|
||||
+ };
|
||||
+
|
||||
+ vop: vop@fdd90000 {
|
||||
+ compatible = "rockchip,rk3588-vop";
|
||||
+ reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;
|
||||
+ reg-names = "vop", "gamma-lut";
|
||||
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
+ clocks = <&cru ACLK_VOP>,
|
||||
+ <&cru HCLK_VOP>,
|
||||
+ <&cru DCLK_VOP0>,
|
||||
+ <&cru DCLK_VOP1>,
|
||||
+ <&cru DCLK_VOP2>,
|
||||
+ <&cru DCLK_VOP3>,
|
||||
+ <&cru PCLK_VOP_ROOT>;
|
||||
+ clock-names = "aclk",
|
||||
+ "hclk",
|
||||
+ "dclk_vp0",
|
||||
+ "dclk_vp1",
|
||||
+ "dclk_vp2",
|
||||
+ "dclk_vp3",
|
||||
+ "pclk_vop";
|
||||
+ iommus = <&vop_mmu>;
|
||||
+ power-domains = <&power RK3588_PD_VOP>;
|
||||
+ rockchip,grf = <&sys_grf>;
|
||||
+ rockchip,vop-grf = <&vop_grf>;
|
||||
+ rockchip,vo1-grf = <&vo1_grf>;
|
||||
+ rockchip,pmu = <&pmu>;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ vop_out: ports {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ vp0: port@0 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ reg = <0>;
|
||||
+ };
|
||||
+
|
||||
+ vp1: port@1 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ reg = <1>;
|
||||
+ };
|
||||
+
|
||||
+ vp2: port@2 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ reg = <2>;
|
||||
+ };
|
||||
+
|
||||
+ vp3: port@3 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ reg = <3>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vop_mmu: iommu@fdd97e00 {
|
||||
+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
|
||||
+ reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>;
|
||||
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
|
||||
+ clock-names = "aclk", "iface";
|
||||
+ #iommu-cells = <0>;
|
||||
+ power-domains = <&power RK3588_PD_VOP>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
i2s4_8ch: i2s@fddc0000 {
|
||||
compatible = "rockchip,rk3588-i2s-tdm";
|
||||
reg = <0x0 0xfddc0000 0x0 0x1000>;
|
||||
@@ -1431,6 +1444,16 @@
|
||||
reg = <0x0 0xfdf82200 0x0 0x20>;
|
||||
};
|
||||
|
||||
+ dfi: dfi@fe060000 {
|
||||
+ reg = <0x00 0xfe060000 0x00 0x10000>;
|
||||
+ compatible = "rockchip,rk3588-dfi";
|
||||
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
+ <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
+ rockchip,pmu = <&pmu1grf>;
|
||||
+ };
|
||||
+
|
||||
pcie2x1l1: pcie@fe180000 {
|
||||
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
|
||||
bus-range = <0x30 0x3f>;
|
||||
@@ -1533,16 +1556,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
- dfi: dfi@fe060000 {
|
||||
- reg = <0x00 0xfe060000 0x00 0x10000>;
|
||||
- compatible = "rockchip,rk3588-dfi";
|
||||
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
- <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
- <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
- rockchip,pmu = <&pmu1grf>;
|
||||
- };
|
||||
-
|
||||
gmac1: ethernet@fe1c0000 {
|
||||
compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
|
||||
reg = <0x0 0xfe1c0000 0x0 0x10000>;
|
||||
@@ -2543,19 +2556,6 @@
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
-
|
||||
- av1d: video-codec@fdc70000 {
|
||||
- compatible = "rockchip,rk3588-av1-vpu";
|
||||
- reg = <0x0 0xfdc70000 0x0 0x800>;
|
||||
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
- interrupt-names = "vdpu";
|
||||
- assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
|
||||
- assigned-clock-rates = <400000000>, <400000000>;
|
||||
- clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
|
||||
- clock-names = "aclk", "hclk";
|
||||
- power-domains = <&power RK3588_PD_AV1>;
|
||||
- resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>;
|
||||
- };
|
||||
};
|
||||
|
||||
#include "rk3588s-pinctrl.dtsi"
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
From 4e07a95f7402de092cd71b2cb96c69f85c98f251 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Tue, 9 Apr 2024 00:50:31 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: fix usb2phy nodename for rk3588
|
||||
|
||||
usb2-phy should be named usb2phy according to the DT binding,
|
||||
so let's fix it up accordingly.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20240408225109.128953-5-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 4 ++--
|
||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
@@ -599,7 +599,7 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
- u2phy2: usb2-phy@8000 {
|
||||
+ u2phy2: usb2phy@8000 {
|
||||
compatible = "rockchip,rk3588-usb2phy";
|
||||
reg = <0x8000 0x10>;
|
||||
interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
@@ -624,7 +624,7 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
- u2phy3: usb2-phy@c000 {
|
||||
+ u2phy3: usb2phy@c000 {
|
||||
compatible = "rockchip,rk3588-usb2phy";
|
||||
reg = <0xc000 0x10>;
|
||||
interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
From abe68e0ca71dddce0e5419e35507cb464d61870d Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Tue, 9 Apr 2024 00:50:32 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: reorder usb2phy properties for rk3588
|
||||
|
||||
Reorder common DT properties alphabetically for usb2phy, according
|
||||
to latest DT style rules.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20240408225109.128953-6-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 16 ++++++++--------
|
||||
1 file changed, 8 insertions(+), 8 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
@@ -602,13 +602,13 @@
|
||||
u2phy2: usb2phy@8000 {
|
||||
compatible = "rockchip,rk3588-usb2phy";
|
||||
reg = <0x8000 0x10>;
|
||||
- interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
- resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
|
||||
- reset-names = "phy", "apb";
|
||||
+ #clock-cells = <0>;
|
||||
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
|
||||
clock-names = "phyclk";
|
||||
clock-output-names = "usb480m_phy2";
|
||||
- #clock-cells = <0>;
|
||||
+ interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
+ resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
|
||||
+ reset-names = "phy", "apb";
|
||||
status = "disabled";
|
||||
|
||||
u2phy2_host: host-port {
|
||||
@@ -627,13 +627,13 @@
|
||||
u2phy3: usb2phy@c000 {
|
||||
compatible = "rockchip,rk3588-usb2phy";
|
||||
reg = <0xc000 0x10>;
|
||||
- interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
- resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
|
||||
- reset-names = "phy", "apb";
|
||||
+ #clock-cells = <0>;
|
||||
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
|
||||
clock-names = "phyclk";
|
||||
clock-output-names = "usb480m_phy3";
|
||||
- #clock-cells = <0>;
|
||||
+ interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
+ resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
|
||||
+ reset-names = "phy", "apb";
|
||||
status = "disabled";
|
||||
|
||||
u2phy3_host: host-port {
|
||||
|
|
@ -0,0 +1,175 @@
|
|||
From e18e5e8188f2671abf63abe7db5f21555705130f Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Tue, 9 Apr 2024 00:50:33 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: add USBDP phys on rk3588
|
||||
|
||||
Add both USB3-DisplayPort PHYs to RK3588 SoC DT.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20240408225109.128953-7-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588.dtsi | 52 +++++++++++++++++++
|
||||
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 63 +++++++++++++++++++++++
|
||||
2 files changed, 115 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
|
||||
@@ -17,6 +17,36 @@
|
||||
reg = <0x0 0xfd5c0000 0x0 0x100>;
|
||||
};
|
||||
|
||||
+ usbdpphy1_grf: syscon@fd5cc000 {
|
||||
+ compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
|
||||
+ reg = <0x0 0xfd5cc000 0x0 0x4000>;
|
||||
+ };
|
||||
+
|
||||
+ usb2phy1_grf: syscon@fd5d4000 {
|
||||
+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
|
||||
+ reg = <0x0 0xfd5d4000 0x0 0x4000>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ u2phy1: usb2phy@4000 {
|
||||
+ compatible = "rockchip,rk3588-usb2phy";
|
||||
+ reg = <0x4000 0x10>;
|
||||
+ #clock-cells = <0>;
|
||||
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
|
||||
+ clock-names = "phyclk";
|
||||
+ clock-output-names = "usb480m_phy1";
|
||||
+ interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
+ resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
|
||||
+ reset-names = "phy", "apb";
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ u2phy1_otg: otg-port {
|
||||
+ #phy-cells = <0>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
i2s8_8ch: i2s@fddc8000 {
|
||||
compatible = "rockchip,rk3588-i2s-tdm";
|
||||
reg = <0x0 0xfddc8000 0x0 0x1000>;
|
||||
@@ -310,6 +340,28 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ usbdp_phy1: phy@fed90000 {
|
||||
+ compatible = "rockchip,rk3588-usbdp-phy";
|
||||
+ reg = <0x0 0xfed90000 0x0 0x10000>;
|
||||
+ #phy-cells = <1>;
|
||||
+ clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
|
||||
+ <&cru CLK_USBDP_PHY1_IMMORTAL>,
|
||||
+ <&cru PCLK_USBDPPHY1>,
|
||||
+ <&u2phy1>;
|
||||
+ clock-names = "refclk", "immortal", "pclk", "utmi";
|
||||
+ resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
|
||||
+ <&cru SRST_USBDP_COMBO_PHY1_CMN>,
|
||||
+ <&cru SRST_USBDP_COMBO_PHY1_LANE>,
|
||||
+ <&cru SRST_USBDP_COMBO_PHY1_PCS>,
|
||||
+ <&cru SRST_P_USBDPPHY1>;
|
||||
+ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
|
||||
+ rockchip,u2phy-grf = <&usb2phy1_grf>;
|
||||
+ rockchip,usb-grf = <&usb_grf>;
|
||||
+ rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
|
||||
+ rockchip,vo-grf = <&vo0_grf>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
combphy1_ps: phy@fee10000 {
|
||||
compatible = "rockchip,rk3588-naneng-combphy";
|
||||
reg = <0x0 0xfee10000 0x0 0x100>;
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
@@ -572,12 +572,23 @@
|
||||
reg = <0x0 0xfd5a4000 0x0 0x2000>;
|
||||
};
|
||||
|
||||
+ vo0_grf: syscon@fd5a6000 {
|
||||
+ compatible = "rockchip,rk3588-vo-grf", "syscon";
|
||||
+ reg = <0x0 0xfd5a6000 0x0 0x2000>;
|
||||
+ clocks = <&cru PCLK_VO0GRF>;
|
||||
+ };
|
||||
+
|
||||
vo1_grf: syscon@fd5a8000 {
|
||||
compatible = "rockchip,rk3588-vo-grf", "syscon";
|
||||
reg = <0x0 0xfd5a8000 0x0 0x100>;
|
||||
clocks = <&cru PCLK_VO1GRF>;
|
||||
};
|
||||
|
||||
+ usb_grf: syscon@fd5ac000 {
|
||||
+ compatible = "rockchip,rk3588-usb-grf", "syscon";
|
||||
+ reg = <0x0 0xfd5ac000 0x0 0x4000>;
|
||||
+ };
|
||||
+
|
||||
php_grf: syscon@fd5b0000 {
|
||||
compatible = "rockchip,rk3588-php-grf", "syscon";
|
||||
reg = <0x0 0xfd5b0000 0x0 0x1000>;
|
||||
@@ -593,6 +604,36 @@
|
||||
reg = <0x0 0xfd5c4000 0x0 0x100>;
|
||||
};
|
||||
|
||||
+ usbdpphy0_grf: syscon@fd5c8000 {
|
||||
+ compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
|
||||
+ reg = <0x0 0xfd5c8000 0x0 0x4000>;
|
||||
+ };
|
||||
+
|
||||
+ usb2phy0_grf: syscon@fd5d0000 {
|
||||
+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
|
||||
+ reg = <0x0 0xfd5d0000 0x0 0x4000>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ u2phy0: usb2phy@0 {
|
||||
+ compatible = "rockchip,rk3588-usb2phy";
|
||||
+ reg = <0x0 0x10>;
|
||||
+ #clock-cells = <0>;
|
||||
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
|
||||
+ clock-names = "phyclk";
|
||||
+ clock-output-names = "usb480m_phy0";
|
||||
+ interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
+ resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
|
||||
+ reset-names = "phy", "apb";
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ u2phy0_otg: otg-port {
|
||||
+ #phy-cells = <0>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
usb2phy2_grf: syscon@fd5d8000 {
|
||||
compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
|
||||
reg = <0x0 0xfd5d8000 0x0 0x4000>;
|
||||
@@ -2449,6 +2490,28 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ usbdp_phy0: phy@fed80000 {
|
||||
+ compatible = "rockchip,rk3588-usbdp-phy";
|
||||
+ reg = <0x0 0xfed80000 0x0 0x10000>;
|
||||
+ #phy-cells = <1>;
|
||||
+ clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
|
||||
+ <&cru CLK_USBDP_PHY0_IMMORTAL>,
|
||||
+ <&cru PCLK_USBDPPHY0>,
|
||||
+ <&u2phy0>;
|
||||
+ clock-names = "refclk", "immortal", "pclk", "utmi";
|
||||
+ resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
|
||||
+ <&cru SRST_USBDP_COMBO_PHY0_CMN>,
|
||||
+ <&cru SRST_USBDP_COMBO_PHY0_LANE>,
|
||||
+ <&cru SRST_USBDP_COMBO_PHY0_PCS>,
|
||||
+ <&cru SRST_P_USBDPPHY0>;
|
||||
+ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
|
||||
+ rockchip,u2phy-grf = <&usb2phy0_grf>;
|
||||
+ rockchip,usb-grf = <&usb_grf>;
|
||||
+ rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
|
||||
+ rockchip,vo-grf = <&vo0_grf>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
combphy0_ps: phy@fee00000 {
|
||||
compatible = "rockchip,rk3588-naneng-combphy";
|
||||
reg = <0x0 0xfee00000 0x0 0x100>;
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
From 33f393a2a990e16f56931ca708295f31d2b44415 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Tue, 9 Apr 2024 00:50:34 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: add USB3 DRD controllers on rk3588
|
||||
|
||||
Add both USB3 dual-role controllers to the RK3588 devicetree.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20240408225109.128953-8-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588.dtsi | 20 ++++++++++++++++++++
|
||||
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 22 ++++++++++++++++++++++
|
||||
2 files changed, 42 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
|
||||
@@ -7,6 +7,26 @@
|
||||
#include "rk3588-pinctrl.dtsi"
|
||||
|
||||
/ {
|
||||
+ usb_host1_xhci: usb@fc400000 {
|
||||
+ compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
|
||||
+ reg = <0x0 0xfc400000 0x0 0x400000>;
|
||||
+ interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
+ clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
|
||||
+ <&cru ACLK_USB3OTG1>;
|
||||
+ clock-names = "ref_clk", "suspend_clk", "bus_clk";
|
||||
+ dr_mode = "otg";
|
||||
+ phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>;
|
||||
+ phy-names = "usb2-phy", "usb3-phy";
|
||||
+ phy_type = "utmi_wide";
|
||||
+ power-domains = <&power RK3588_PD_USB>;
|
||||
+ resets = <&cru SRST_A_USB3OTG1>;
|
||||
+ snps,dis_enblslpm_quirk;
|
||||
+ snps,dis-u2-freeclk-exists-quirk;
|
||||
+ snps,dis-del-phy-power-chg-quirk;
|
||||
+ snps,dis-tx-ipgap-linecheck-quirk;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
pcie30_phy_grf: syscon@fd5b8000 {
|
||||
compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
|
||||
reg = <0x0 0xfd5b8000 0x0 0x10000>;
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
@@ -492,6 +492,28 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ usb_host0_xhci: usb@fc000000 {
|
||||
+ compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
|
||||
+ reg = <0x0 0xfc000000 0x0 0x400000>;
|
||||
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
+ clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
|
||||
+ <&cru ACLK_USB3OTG0>;
|
||||
+ clock-names = "ref_clk", "suspend_clk", "bus_clk";
|
||||
+ dr_mode = "otg";
|
||||
+ phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>;
|
||||
+ phy-names = "usb2-phy", "usb3-phy";
|
||||
+ phy_type = "utmi_wide";
|
||||
+ power-domains = <&power RK3588_PD_USB>;
|
||||
+ resets = <&cru SRST_A_USB3OTG0>;
|
||||
+ snps,dis_enblslpm_quirk;
|
||||
+ snps,dis-u1-entry-quirk;
|
||||
+ snps,dis-u2-entry-quirk;
|
||||
+ snps,dis-u2-freeclk-exists-quirk;
|
||||
+ snps,dis-del-phy-power-chg-quirk;
|
||||
+ snps,dis-tx-ipgap-linecheck-quirk;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
usb_host0_ehci: usb@fc800000 {
|
||||
compatible = "rockchip,rk3588-ehci", "generic-ehci";
|
||||
reg = <0x0 0xfc800000 0x0 0x40000>;
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
From cd81d3a0695cc54ad6ac0ef4bbb67a7c8f55d592 Mon Sep 17 00:00:00 2001
|
||||
From: Niklas Cassel <cassel@kernel.org>
|
||||
Date: Thu, 2 May 2024 16:02:32 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: add rk3588 pcie and php IOMMUs
|
||||
|
||||
The mmu600_pcie is connected with the five PCIe controllers.
|
||||
The mmu600_php is connected with the USB3 controller, the GMAC
|
||||
controllers, and the SATA controllers.
|
||||
|
||||
See 8.2 Block Diagram, in rk3588 TRM (Technical Reference Manual).
|
||||
|
||||
The IOMMUs are disabled by default, as further patches are needed to
|
||||
program the SID/SSIDs in to the IOMMUs.
|
||||
|
||||
iommu: Default domain type: Translated
|
||||
iommu: DMA domain TLB invalidation policy: strict mode
|
||||
arm-smmu-v3 fc900000.iommu: ias 48-bit, oas 48-bit (features 0x001c1eaf)
|
||||
arm-smmu-v3 fc900000.iommu: allocated 65536 entries for cmdq
|
||||
arm-smmu-v3 fc900000.iommu: allocated 32768 entries for evtq
|
||||
arm-smmu-v3 fc900000.iommu: msi_domain absent - falling back to wired irqs
|
||||
|
||||
Additionally, the IOMMU correctly triggers an IOMMU fault when
|
||||
a PCIe device performs a write (since the device hasn't been
|
||||
assigned a SID/SSID):
|
||||
arm-smmu-v3 fc900000.iommu: event 0x02 received:
|
||||
arm-smmu-v3 fc900000.iommu: 0x0000010000000002
|
||||
arm-smmu-v3 fc900000.iommu: 0x0000000000000000
|
||||
arm-smmu-v3 fc900000.iommu: 0x0000000000000000
|
||||
arm-smmu-v3 fc900000.iommu: 0x0000000000000000
|
||||
|
||||
While this doesn't provide much value as is, having the devices as
|
||||
disabled in the device tree will allow developers to see that the rk3588
|
||||
actually has IOMMUs on the SoC.
|
||||
|
||||
Signed-off-by: Niklas Cassel <cassel@kernel.org>
|
||||
Link: https://lore.kernel.org/r/20240502140231.477049-2-cassel@kernel.org
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 24 +++++++++++++++++++++++
|
||||
1 file changed, 24 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
@@ -579,6 +579,30 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ mmu600_pcie: iommu@fc900000 {
|
||||
+ compatible = "arm,smmu-v3";
|
||||
+ reg = <0x0 0xfc900000 0x0 0x200000>;
|
||||
+ interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
+ <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
+ <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
+ interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
|
||||
+ #iommu-cells = <1>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ mmu600_php: iommu@fcb00000 {
|
||||
+ compatible = "arm,smmu-v3";
|
||||
+ reg = <0x0 0xfcb00000 0x0 0x200000>;
|
||||
+ interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
+ <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
+ <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
+ <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
+ interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
|
||||
+ #iommu-cells = <1>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
pmu1grf: syscon@fd58a000 {
|
||||
compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
|
||||
reg = <0x0 0xfd58a000 0x0 0x10000>;
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,193 @@
|
|||
From 510cd9e688453166b2bff3999ed21cac97385bb5 Mon Sep 17 00:00:00 2001
|
||||
From: Alexey Charkov <alchark@gmail.com>
|
||||
Date: Mon, 17 Jun 2024 22:28:51 +0400
|
||||
Subject: [PATCH] arm64: dts: rockchip: add thermal zones information on RK3588
|
||||
|
||||
This includes the necessary device tree data to allow thermal
|
||||
monitoring on RK3588(s) using the on-chip TSADC device, along with
|
||||
trip points for automatic thermal management.
|
||||
|
||||
Each of the CPU clusters (one for the little cores and two for
|
||||
the big cores) get a passive cooling trip point at 85C, which
|
||||
will trigger DVFS throttling of the respective cluster upon
|
||||
reaching a high temperature condition.
|
||||
|
||||
All zones also have a critical trip point at 115C, which will
|
||||
trigger a reset.
|
||||
|
||||
Signed-off-by: Alexey Charkov <alchark@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-1-c1f5f3267f1e@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 153 ++++++++++++++++++
|
||||
1 file changed, 153 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
@@ -10,6 +10,7 @@
|
||||
#include <dt-bindings/reset/rockchip,rk3588-cru.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
#include <dt-bindings/ata/ahci.h>
|
||||
+#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
/ {
|
||||
compatible = "rockchip,rk3588";
|
||||
@@ -2368,6 +2369,158 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ thermal_zones: thermal-zones {
|
||||
+ /* sensor near the center of the SoC */
|
||||
+ package_thermal: package-thermal {
|
||||
+ polling-delay-passive = <0>;
|
||||
+ polling-delay = <0>;
|
||||
+ thermal-sensors = <&tsadc 0>;
|
||||
+
|
||||
+ trips {
|
||||
+ package_crit: package-crit {
|
||||
+ temperature = <115000>;
|
||||
+ hysteresis = <0>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ /* sensor between A76 cores 0 and 1 */
|
||||
+ bigcore0_thermal: bigcore0-thermal {
|
||||
+ polling-delay-passive = <100>;
|
||||
+ polling-delay = <0>;
|
||||
+ thermal-sensors = <&tsadc 1>;
|
||||
+
|
||||
+ trips {
|
||||
+ bigcore0_alert: bigcore0-alert {
|
||||
+ temperature = <85000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "passive";
|
||||
+ };
|
||||
+
|
||||
+ bigcore0_crit: bigcore0-crit {
|
||||
+ temperature = <115000>;
|
||||
+ hysteresis = <0>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cooling-maps {
|
||||
+ map0 {
|
||||
+ trip = <&bigcore0_alert>;
|
||||
+ cooling-device =
|
||||
+ <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
+ <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ /* sensor between A76 cores 2 and 3 */
|
||||
+ bigcore2_thermal: bigcore2-thermal {
|
||||
+ polling-delay-passive = <100>;
|
||||
+ polling-delay = <0>;
|
||||
+ thermal-sensors = <&tsadc 2>;
|
||||
+
|
||||
+ trips {
|
||||
+ bigcore2_alert: bigcore2-alert {
|
||||
+ temperature = <85000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "passive";
|
||||
+ };
|
||||
+
|
||||
+ bigcore2_crit: bigcore2-crit {
|
||||
+ temperature = <115000>;
|
||||
+ hysteresis = <0>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cooling-maps {
|
||||
+ map0 {
|
||||
+ trip = <&bigcore2_alert>;
|
||||
+ cooling-device =
|
||||
+ <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
+ <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ /* sensor between the four A55 cores */
|
||||
+ little_core_thermal: littlecore-thermal {
|
||||
+ polling-delay-passive = <100>;
|
||||
+ polling-delay = <0>;
|
||||
+ thermal-sensors = <&tsadc 3>;
|
||||
+
|
||||
+ trips {
|
||||
+ littlecore_alert: littlecore-alert {
|
||||
+ temperature = <85000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "passive";
|
||||
+ };
|
||||
+
|
||||
+ littlecore_crit: littlecore-crit {
|
||||
+ temperature = <115000>;
|
||||
+ hysteresis = <0>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cooling-maps {
|
||||
+ map0 {
|
||||
+ trip = <&littlecore_alert>;
|
||||
+ cooling-device =
|
||||
+ <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
+ <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
+ <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
+ <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ /* sensor near the PD_CENTER power domain */
|
||||
+ center_thermal: center-thermal {
|
||||
+ polling-delay-passive = <0>;
|
||||
+ polling-delay = <0>;
|
||||
+ thermal-sensors = <&tsadc 4>;
|
||||
+
|
||||
+ trips {
|
||||
+ center_crit: center-crit {
|
||||
+ temperature = <115000>;
|
||||
+ hysteresis = <0>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gpu_thermal: gpu-thermal {
|
||||
+ polling-delay-passive = <0>;
|
||||
+ polling-delay = <0>;
|
||||
+ thermal-sensors = <&tsadc 5>;
|
||||
+
|
||||
+ trips {
|
||||
+ gpu_crit: gpu-crit {
|
||||
+ temperature = <115000>;
|
||||
+ hysteresis = <0>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ npu_thermal: npu-thermal {
|
||||
+ polling-delay-passive = <0>;
|
||||
+ polling-delay = <0>;
|
||||
+ thermal-sensors = <&tsadc 6>;
|
||||
+
|
||||
+ trips {
|
||||
+ npu_crit: npu-crit {
|
||||
+ temperature = <115000>;
|
||||
+ hysteresis = <0>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
tsadc: tsadc@fec00000 {
|
||||
compatible = "rockchip,rk3588-tsadc";
|
||||
reg = <0x0 0xfec00000 0x0 0x400>;
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
From b78f87940a79321a444083aca46ac3e8e53d1a90 Mon Sep 17 00:00:00 2001
|
||||
From: Alexey Charkov <alchark@gmail.com>
|
||||
Date: Mon, 17 Jun 2024 22:28:53 +0400
|
||||
Subject: [PATCH] arm64: dts: rockchip: add passive GPU cooling on RK3588
|
||||
|
||||
As the GPU support on RK3588 has been merged upstream, along with OPP
|
||||
values, add a corresponding cooling map for passive cooling using the GPU.
|
||||
|
||||
Signed-off-by: Alexey Charkov <alchark@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-3-c1f5f3267f1e@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 16 +++++++++++++++-
|
||||
1 file changed, 15 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
@@ -2493,17 +2493,31 @@
|
||||
};
|
||||
|
||||
gpu_thermal: gpu-thermal {
|
||||
- polling-delay-passive = <0>;
|
||||
+ polling-delay-passive = <100>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&tsadc 5>;
|
||||
|
||||
trips {
|
||||
+ gpu_alert: gpu-alert {
|
||||
+ temperature = <85000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "passive";
|
||||
+ };
|
||||
+
|
||||
gpu_crit: gpu-crit {
|
||||
temperature = <115000>;
|
||||
hysteresis = <0>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
+
|
||||
+ cooling-maps {
|
||||
+ map0 {
|
||||
+ trip = <&gpu_alert>;
|
||||
+ cooling-device =
|
||||
+ <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
npu_thermal: npu-thermal {
|
||||
|
|
@ -0,0 +1,205 @@
|
|||
From 276856db91b46eaa7a4c19226c096a9dc899a3e9 Mon Sep 17 00:00:00 2001
|
||||
From: Alexey Charkov <alchark@gmail.com>
|
||||
Date: Mon, 17 Jun 2024 22:28:56 +0400
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add OPP data for CPU cores on RK3588
|
||||
|
||||
By default the CPUs on RK3588 start up in a conservative performance
|
||||
mode. Add frequency and voltage mappings to the device tree to enable
|
||||
dynamic scaling via cpufreq.
|
||||
|
||||
OPP values are adapted from Radxa's downstream kernel for Rock 5B [1],
|
||||
stripping them down to the minimum frequency and voltage combinations
|
||||
as expected by the generic upstream cpufreq-dt driver, and also dropping
|
||||
those OPPs that don't differ in voltage but only in frequency (keeping
|
||||
the top frequency OPP in each case).
|
||||
|
||||
Note that this patch ignores voltage scaling for the CPU memory
|
||||
interface which the downstream kernel does through a custom cpufreq
|
||||
driver, and which is why the downstream version has two sets of voltage
|
||||
values for each OPP (the second one being meant for the memory
|
||||
interface supply regulator). This is done instead via regulator
|
||||
coupling between CPU and memory interface supplies on affected boards.
|
||||
|
||||
This has been tested on Rock 5B with u-boot 2023.11 compiled from
|
||||
Collabora's integration tree [2] with binary bl31 and appears to be
|
||||
stable both under active cooling and passive cooling (with throttling)
|
||||
|
||||
[1] https://github.com/radxa/kernel/blob/stable-5.10-rock5/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
[2] https://gitlab.collabora.com/hardware-enablement/rockchip-3588/u-boot
|
||||
|
||||
Signed-off-by: Alexey Charkov <alchark@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-6-c1f5f3267f1e@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi | 149 +++++++++++++++++++
|
||||
arch/arm64/boot/dts/rockchip/rk3588.dtsi | 1 +
|
||||
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 1 +
|
||||
3 files changed, 151 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi
|
||||
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi
|
||||
@@ -0,0 +1,149 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+/ {
|
||||
+ cluster0_opp_table: opp-table-cluster0 {
|
||||
+ compatible = "operating-points-v2";
|
||||
+ opp-shared;
|
||||
+
|
||||
+ opp-1008000000 {
|
||||
+ opp-hz = /bits/ 64 <1008000000>;
|
||||
+ opp-microvolt = <675000 675000 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1200000000 {
|
||||
+ opp-hz = /bits/ 64 <1200000000>;
|
||||
+ opp-microvolt = <712500 712500 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1416000000 {
|
||||
+ opp-hz = /bits/ 64 <1416000000>;
|
||||
+ opp-microvolt = <762500 762500 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ opp-suspend;
|
||||
+ };
|
||||
+ opp-1608000000 {
|
||||
+ opp-hz = /bits/ 64 <1608000000>;
|
||||
+ opp-microvolt = <850000 850000 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1800000000 {
|
||||
+ opp-hz = /bits/ 64 <1800000000>;
|
||||
+ opp-microvolt = <950000 950000 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cluster1_opp_table: opp-table-cluster1 {
|
||||
+ compatible = "operating-points-v2";
|
||||
+ opp-shared;
|
||||
+
|
||||
+ opp-1200000000 {
|
||||
+ opp-hz = /bits/ 64 <1200000000>;
|
||||
+ opp-microvolt = <675000 675000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1416000000 {
|
||||
+ opp-hz = /bits/ 64 <1416000000>;
|
||||
+ opp-microvolt = <725000 725000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1608000000 {
|
||||
+ opp-hz = /bits/ 64 <1608000000>;
|
||||
+ opp-microvolt = <762500 762500 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1800000000 {
|
||||
+ opp-hz = /bits/ 64 <1800000000>;
|
||||
+ opp-microvolt = <850000 850000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-2016000000 {
|
||||
+ opp-hz = /bits/ 64 <2016000000>;
|
||||
+ opp-microvolt = <925000 925000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-2208000000 {
|
||||
+ opp-hz = /bits/ 64 <2208000000>;
|
||||
+ opp-microvolt = <987500 987500 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-2400000000 {
|
||||
+ opp-hz = /bits/ 64 <2400000000>;
|
||||
+ opp-microvolt = <1000000 1000000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cluster2_opp_table: opp-table-cluster2 {
|
||||
+ compatible = "operating-points-v2";
|
||||
+ opp-shared;
|
||||
+
|
||||
+ opp-1200000000 {
|
||||
+ opp-hz = /bits/ 64 <1200000000>;
|
||||
+ opp-microvolt = <675000 675000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1416000000 {
|
||||
+ opp-hz = /bits/ 64 <1416000000>;
|
||||
+ opp-microvolt = <725000 725000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1608000000 {
|
||||
+ opp-hz = /bits/ 64 <1608000000>;
|
||||
+ opp-microvolt = <762500 762500 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1800000000 {
|
||||
+ opp-hz = /bits/ 64 <1800000000>;
|
||||
+ opp-microvolt = <850000 850000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-2016000000 {
|
||||
+ opp-hz = /bits/ 64 <2016000000>;
|
||||
+ opp-microvolt = <925000 925000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-2208000000 {
|
||||
+ opp-hz = /bits/ 64 <2208000000>;
|
||||
+ opp-microvolt = <987500 987500 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-2400000000 {
|
||||
+ opp-hz = /bits/ 64 <2400000000>;
|
||||
+ opp-microvolt = <1000000 1000000 1000000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cpu_b0 {
|
||||
+ operating-points-v2 = <&cluster1_opp_table>;
|
||||
+};
|
||||
+
|
||||
+&cpu_b1 {
|
||||
+ operating-points-v2 = <&cluster1_opp_table>;
|
||||
+};
|
||||
+
|
||||
+&cpu_b2 {
|
||||
+ operating-points-v2 = <&cluster2_opp_table>;
|
||||
+};
|
||||
+
|
||||
+&cpu_b3 {
|
||||
+ operating-points-v2 = <&cluster2_opp_table>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l0 {
|
||||
+ operating-points-v2 = <&cluster0_opp_table>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l1 {
|
||||
+ operating-points-v2 = <&cluster0_opp_table>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l2 {
|
||||
+ operating-points-v2 = <&cluster0_opp_table>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l3 {
|
||||
+ operating-points-v2 = <&cluster0_opp_table>;
|
||||
+};
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
|
||||
@@ -5,3 +5,4 @@
|
||||
*/
|
||||
|
||||
#include "rk3588-extra.dtsi"
|
||||
+#include "rk3588-opp.dtsi"
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
@@ -5,3 +5,4 @@
|
||||
*/
|
||||
|
||||
#include "rk3588-base.dtsi"
|
||||
+#include "rk3588-opp.dtsi"
|
||||
|
|
@ -0,0 +1,140 @@
|
|||
From 667885a6865832eb0678c7e02e47a3392f177ecb Mon Sep 17 00:00:00 2001
|
||||
From: Alexey Charkov <alchark@gmail.com>
|
||||
Date: Mon, 17 Jun 2024 22:28:57 +0400
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add OPP data for CPU cores on RK3588j
|
||||
|
||||
RK3588j is the 'industrial' variant of RK3588, and it uses a different
|
||||
set of OPPs both in terms of allowed frequencies and in terms of
|
||||
applicable voltages at each frequency setpoint.
|
||||
|
||||
Add the OPPs that apply to RK3588j (and apparently RK3588m too) to
|
||||
enable dynamic CPU frequency scaling.
|
||||
|
||||
OPP values are derived from Rockchip downstream sources [1] by taking
|
||||
only those OPPs which have the highest frequency for a given voltage
|
||||
level and dropping the rest (if they are included, the kernel complains
|
||||
at boot time about them being inefficient)
|
||||
|
||||
[1] https://github.com/rockchip-linux/kernel/blob/604cec4004abe5a96c734f2fab7b74809d2d742f/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
|
||||
Signed-off-by: Alexey Charkov <alchark@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-7-c1f5f3267f1e@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588j.dtsi | 108 ++++++++++++++++++++++
|
||||
1 file changed, 108 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi
|
||||
@@ -5,3 +5,111 @@
|
||||
*/
|
||||
|
||||
#include "rk3588-extra.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ cluster0_opp_table: opp-table-cluster0 {
|
||||
+ compatible = "operating-points-v2";
|
||||
+ opp-shared;
|
||||
+
|
||||
+ opp-1416000000 {
|
||||
+ opp-hz = /bits/ 64 <1416000000>;
|
||||
+ opp-microvolt = <750000 750000 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ opp-suspend;
|
||||
+ };
|
||||
+ opp-1608000000 {
|
||||
+ opp-hz = /bits/ 64 <1608000000>;
|
||||
+ opp-microvolt = <887500 887500 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1704000000 {
|
||||
+ opp-hz = /bits/ 64 <1704000000>;
|
||||
+ opp-microvolt = <937500 937500 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cluster1_opp_table: opp-table-cluster1 {
|
||||
+ compatible = "operating-points-v2";
|
||||
+ opp-shared;
|
||||
+
|
||||
+ opp-1416000000 {
|
||||
+ opp-hz = /bits/ 64 <1416000000>;
|
||||
+ opp-microvolt = <750000 750000 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1608000000 {
|
||||
+ opp-hz = /bits/ 64 <1608000000>;
|
||||
+ opp-microvolt = <787500 787500 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1800000000 {
|
||||
+ opp-hz = /bits/ 64 <1800000000>;
|
||||
+ opp-microvolt = <875000 875000 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-2016000000 {
|
||||
+ opp-hz = /bits/ 64 <2016000000>;
|
||||
+ opp-microvolt = <950000 950000 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cluster2_opp_table: opp-table-cluster2 {
|
||||
+ compatible = "operating-points-v2";
|
||||
+ opp-shared;
|
||||
+
|
||||
+ opp-1416000000 {
|
||||
+ opp-hz = /bits/ 64 <1416000000>;
|
||||
+ opp-microvolt = <750000 750000 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1608000000 {
|
||||
+ opp-hz = /bits/ 64 <1608000000>;
|
||||
+ opp-microvolt = <787500 787500 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1800000000 {
|
||||
+ opp-hz = /bits/ 64 <1800000000>;
|
||||
+ opp-microvolt = <875000 875000 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-2016000000 {
|
||||
+ opp-hz = /bits/ 64 <2016000000>;
|
||||
+ opp-microvolt = <950000 950000 950000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cpu_b0 {
|
||||
+ operating-points-v2 = <&cluster1_opp_table>;
|
||||
+};
|
||||
+
|
||||
+&cpu_b1 {
|
||||
+ operating-points-v2 = <&cluster1_opp_table>;
|
||||
+};
|
||||
+
|
||||
+&cpu_b2 {
|
||||
+ operating-points-v2 = <&cluster2_opp_table>;
|
||||
+};
|
||||
+
|
||||
+&cpu_b3 {
|
||||
+ operating-points-v2 = <&cluster2_opp_table>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l0 {
|
||||
+ operating-points-v2 = <&cluster0_opp_table>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l1 {
|
||||
+ operating-points-v2 = <&cluster0_opp_table>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l2 {
|
||||
+ operating-points-v2 = <&cluster0_opp_table>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l3 {
|
||||
+ operating-points-v2 = <&cluster0_opp_table>;
|
||||
+};
|
||||
|
|
@ -0,0 +1,177 @@
|
|||
From a7b2070505a2a09ea65fa0c8c480c97f62d1978d Mon Sep 17 00:00:00 2001
|
||||
From: Alexey Charkov <alchark@gmail.com>
|
||||
Date: Mon, 17 Jun 2024 22:28:58 +0400
|
||||
Subject: [PATCH] arm64: dts: rockchip: Split GPU OPPs of RK3588 and RK3588j
|
||||
|
||||
RK3588j uses a different set of OPPs for its GPU, both in terms of
|
||||
allowed frequencies and in terms of voltages.
|
||||
|
||||
Move the GPU OPPs table into per-variant .dtsi files to accommodate
|
||||
for this difference.
|
||||
|
||||
The table for RK3588j is adapted from Rockchip downstream sources [1],
|
||||
while RK3588 one is moved verbatim into the per-variant .dtsi file.
|
||||
The values provided for RK3588 in the downstream sources match those
|
||||
in the original commit.
|
||||
|
||||
[1] https://github.com/rockchip-linux/kernel/blob/604cec4004abe5a96c734f2fab7b74809d2d742f/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
||||
|
||||
Fixes: 6fca4edb93d3 ("arm64: dts: rockchip: Add rk3588 GPU node")
|
||||
Signed-off-by: Alexey Charkov <alchark@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-8-c1f5f3267f1e@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 38 -----------------
|
||||
arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi | 41 +++++++++++++++++++
|
||||
arch/arm64/boot/dts/rockchip/rk3588j.dtsi | 33 +++++++++++++++
|
||||
3 files changed, 74 insertions(+), 38 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
@@ -451,46 +451,8 @@
|
||||
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "job", "mmu", "gpu";
|
||||
- operating-points-v2 = <&gpu_opp_table>;
|
||||
power-domains = <&power RK3588_PD_GPU>;
|
||||
status = "disabled";
|
||||
-
|
||||
- gpu_opp_table: opp-table {
|
||||
- compatible = "operating-points-v2";
|
||||
-
|
||||
- opp-300000000 {
|
||||
- opp-hz = /bits/ 64 <300000000>;
|
||||
- opp-microvolt = <675000 675000 850000>;
|
||||
- };
|
||||
- opp-400000000 {
|
||||
- opp-hz = /bits/ 64 <400000000>;
|
||||
- opp-microvolt = <675000 675000 850000>;
|
||||
- };
|
||||
- opp-500000000 {
|
||||
- opp-hz = /bits/ 64 <500000000>;
|
||||
- opp-microvolt = <675000 675000 850000>;
|
||||
- };
|
||||
- opp-600000000 {
|
||||
- opp-hz = /bits/ 64 <600000000>;
|
||||
- opp-microvolt = <675000 675000 850000>;
|
||||
- };
|
||||
- opp-700000000 {
|
||||
- opp-hz = /bits/ 64 <700000000>;
|
||||
- opp-microvolt = <700000 700000 850000>;
|
||||
- };
|
||||
- opp-800000000 {
|
||||
- opp-hz = /bits/ 64 <800000000>;
|
||||
- opp-microvolt = <750000 750000 850000>;
|
||||
- };
|
||||
- opp-900000000 {
|
||||
- opp-hz = /bits/ 64 <900000000>;
|
||||
- opp-microvolt = <800000 800000 850000>;
|
||||
- };
|
||||
- opp-1000000000 {
|
||||
- opp-hz = /bits/ 64 <1000000000>;
|
||||
- opp-microvolt = <850000 850000 850000>;
|
||||
- };
|
||||
- };
|
||||
};
|
||||
|
||||
usb_host0_xhci: usb@fc000000 {
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi
|
||||
@@ -114,6 +114,43 @@
|
||||
clock-latency-ns = <40000>;
|
||||
};
|
||||
};
|
||||
+
|
||||
+ gpu_opp_table: opp-table {
|
||||
+ compatible = "operating-points-v2";
|
||||
+
|
||||
+ opp-300000000 {
|
||||
+ opp-hz = /bits/ 64 <300000000>;
|
||||
+ opp-microvolt = <675000 675000 850000>;
|
||||
+ };
|
||||
+ opp-400000000 {
|
||||
+ opp-hz = /bits/ 64 <400000000>;
|
||||
+ opp-microvolt = <675000 675000 850000>;
|
||||
+ };
|
||||
+ opp-500000000 {
|
||||
+ opp-hz = /bits/ 64 <500000000>;
|
||||
+ opp-microvolt = <675000 675000 850000>;
|
||||
+ };
|
||||
+ opp-600000000 {
|
||||
+ opp-hz = /bits/ 64 <600000000>;
|
||||
+ opp-microvolt = <675000 675000 850000>;
|
||||
+ };
|
||||
+ opp-700000000 {
|
||||
+ opp-hz = /bits/ 64 <700000000>;
|
||||
+ opp-microvolt = <700000 700000 850000>;
|
||||
+ };
|
||||
+ opp-800000000 {
|
||||
+ opp-hz = /bits/ 64 <800000000>;
|
||||
+ opp-microvolt = <750000 750000 850000>;
|
||||
+ };
|
||||
+ opp-900000000 {
|
||||
+ opp-hz = /bits/ 64 <900000000>;
|
||||
+ opp-microvolt = <800000 800000 850000>;
|
||||
+ };
|
||||
+ opp-1000000000 {
|
||||
+ opp-hz = /bits/ 64 <1000000000>;
|
||||
+ opp-microvolt = <850000 850000 850000>;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
&cpu_b0 {
|
||||
@@ -147,3 +184,7 @@
|
||||
&cpu_l3 {
|
||||
operating-points-v2 = <&cluster0_opp_table>;
|
||||
};
|
||||
+
|
||||
+&gpu {
|
||||
+ operating-points-v2 = <&gpu_opp_table>;
|
||||
+};
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi
|
||||
@@ -80,6 +80,35 @@
|
||||
clock-latency-ns = <40000>;
|
||||
};
|
||||
};
|
||||
+
|
||||
+ gpu_opp_table: opp-table {
|
||||
+ compatible = "operating-points-v2";
|
||||
+
|
||||
+ opp-300000000 {
|
||||
+ opp-hz = /bits/ 64 <300000000>;
|
||||
+ opp-microvolt = <750000 750000 850000>;
|
||||
+ };
|
||||
+ opp-400000000 {
|
||||
+ opp-hz = /bits/ 64 <400000000>;
|
||||
+ opp-microvolt = <750000 750000 850000>;
|
||||
+ };
|
||||
+ opp-500000000 {
|
||||
+ opp-hz = /bits/ 64 <500000000>;
|
||||
+ opp-microvolt = <750000 750000 850000>;
|
||||
+ };
|
||||
+ opp-600000000 {
|
||||
+ opp-hz = /bits/ 64 <600000000>;
|
||||
+ opp-microvolt = <750000 750000 850000>;
|
||||
+ };
|
||||
+ opp-700000000 {
|
||||
+ opp-hz = /bits/ 64 <700000000>;
|
||||
+ opp-microvolt = <750000 750000 850000>;
|
||||
+ };
|
||||
+ opp-850000000 {
|
||||
+ opp-hz = /bits/ 64 <800000000>;
|
||||
+ opp-microvolt = <787500 787500 850000>;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
&cpu_b0 {
|
||||
@@ -113,3 +142,7 @@
|
||||
&cpu_l3 {
|
||||
operating-points-v2 = <&cluster0_opp_table>;
|
||||
};
|
||||
+
|
||||
+&gpu {
|
||||
+ operating-points-v2 = <&gpu_opp_table>;
|
||||
+};
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
From 0773a4a199aabb60afe50f5a19a6772abf4ad0bf Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Mon, 6 Nov 2023 16:54:32 +0100
|
||||
Subject: [PATCH] arm64: dts: rockchip: add USB3 host to rock-5a
|
||||
|
||||
Enable USB3 host controller for the Radxa ROCK 5 Model A. This adds
|
||||
USB3 for the lower USB3 port (the one closer to the PCB).
|
||||
|
||||
The upper USB3 port uses the RK3588 USB TypeC host controller, which
|
||||
use a different PHY without upstream support.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20231106155934.80838-2-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 8 ++++++++
|
||||
1 file changed, 8 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
|
||||
@@ -113,6 +113,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
+&combphy2_psu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&cpu_b0 {
|
||||
cpu-supply = <&vdd_cpu_big0_s0>;
|
||||
};
|
||||
@@ -734,3 +738,7 @@
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
+
|
||||
+&usb_host2_xhci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
From af7ec140ddc1815bc462109792d95bcad05cfbc4 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Tue, 9 Apr 2024 00:50:36 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: add upper USB3 port to rock-5a
|
||||
|
||||
Enable full support (XHCI, EHCI, OHCI) for the upper USB3 port from
|
||||
Radxa Rock 5 Model A. The lower one is already supported.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20240408225109.128953-10-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
.../boot/dts/rockchip/rk3588s-rock-5a.dts | 18 ++++++++++++++++++
|
||||
1 file changed, 18 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
|
||||
@@ -698,6 +698,14 @@
|
||||
};
|
||||
};
|
||||
|
||||
+&u2phy0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy0_otg {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&u2phy2 {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -721,6 +729,11 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&usbdp_phy0 {
|
||||
+ status = "okay";
|
||||
+ rockchip,dp-lane-mux = <2 3>;
|
||||
+};
|
||||
+
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
@@ -731,6 +744,11 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&usb_host0_xhci {
|
||||
+ dr_mode = "host";
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
From 00224650dd45e166ea6eb1593f5f064583963ccf Mon Sep 17 00:00:00 2001
|
||||
From: FUKAUMI Naoki <naoki@radxa.com>
|
||||
Date: Sun, 23 Jun 2024 11:33:28 +0900
|
||||
Subject: [PATCH] arm64: dts: rockchip: add (but disabled) SFC node for Radxa
|
||||
ROCK 5A
|
||||
|
||||
This commit adds SFC node for Radxa ROCK 5A.
|
||||
|
||||
since sdhci and sfc on RK3588s share pins(i.e. exclusive), it cannot
|
||||
be enabled both nodes at the same time. so status = "okay" is omitted
|
||||
here.
|
||||
|
||||
you may be able to enable sfc (and disable sdhci) by fdt overlay.
|
||||
|
||||
SPI NOR flash chip may vary, so use safe(lowest) spi-max-frequency.
|
||||
|
||||
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
|
||||
Link: https://lore.kernel.org/r/20240623023329.1044-2-naoki@radxa.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 13 +++++++++++++
|
||||
1 file changed, 13 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
|
||||
@@ -376,6 +376,19 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&sfc {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&fspim0_pins>;
|
||||
+
|
||||
+ flash@0 {
|
||||
+ compatible = "jedec,spi-nor";
|
||||
+ reg = <0>;
|
||||
+ spi-max-frequency = <104000000>;
|
||||
+ spi-rx-bus-width = <4>;
|
||||
+ spi-tx-bus-width = <1>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
&spi2 {
|
||||
status = "okay";
|
||||
assigned-clocks = <&cru CLK_SPI2>;
|
||||
|
|
@ -0,0 +1,110 @@
|
|||
From b728d4c51f0ce9207daf502f3a85073785c46319 Mon Sep 17 00:00:00 2001
|
||||
From: FUKAUMI Naoki <naoki@radxa.com>
|
||||
Date: Mon, 26 Aug 2024 17:04:56 +0900
|
||||
Subject: [PATCH] arm64: dts: rockchip: enable PCIe on M.2 E key for Radxa ROCK
|
||||
5A
|
||||
|
||||
Enable pcie2x1l2 and related combphy/regulator routed to M.2 E key
|
||||
connector on Radxa ROCK 5A.
|
||||
|
||||
Tested with Radxa Wireless Module A8:
|
||||
|
||||
$ lspci
|
||||
0004:40:00.0 PCI bridge: Rockchip Electronics Co., Ltd RK3588 (rev 01)
|
||||
0004:41:00.0 Network controller: Realtek Semiconductor Co., Ltd. RTL8852BE PCIe 802.11ax Wireless Network Controller
|
||||
|
||||
$ ip l
|
||||
1: lo: <LOOPBACK,UP,LOWER_UP> mtu 65536 qdisc noqueue state UNKNOWN mode DEFAULT group default qlen 1000
|
||||
link/loopback 00:00:00:00:00:00 brd 00:00:00:00:00:00
|
||||
2: end0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
|
||||
link/ether c2:58:fc:70:55:86 brd ff:ff:ff:ff:ff:ff
|
||||
3: wlP4p65s0: <BROADCAST,MULTICAST> mtu 1500 qdisc noop state DOWN mode DEFAULT group default qlen 1000
|
||||
link/ether 2c:05:47:65:5b:ed brd ff:ff:ff:ff:ff:ff
|
||||
|
||||
$ lsusb
|
||||
Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
|
||||
Bus 001 Device 002: ID 1a40:0101 Terminus Technology Inc. Hub
|
||||
Bus 001 Device 003: ID 0bda:b85b Realtek Semiconductor Corp. Bluetooth Radio
|
||||
Bus 002 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub
|
||||
Bus 003 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub
|
||||
Bus 004 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
|
||||
Bus 005 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
|
||||
Bus 006 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
|
||||
Bus 006 Device 002: ID 0789:0336 Logitec Corp. LMD USB Device
|
||||
Bus 007 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
|
||||
Bus 008 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
|
||||
|
||||
$ hciconfig
|
||||
hci0: Type: Primary Bus: USB
|
||||
BD Address: 2C:05:47:65:5B:EE ACL MTU: 1021:6 SCO MTU: 255:12
|
||||
UP RUNNING
|
||||
RX bytes:2698 acl:0 sco:0 events:329 errors:0
|
||||
TX bytes:69393 acl:0 sco:0 commands:329 errors:0
|
||||
|
||||
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
|
||||
Link: https://lore.kernel.org/r/20240826080456.525-1-naoki@radxa.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
.../boot/dts/rockchip/rk3588s-rock-5a.dts | 30 +++++++++++++++++++
|
||||
1 file changed, 30 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
|
||||
@@ -64,6 +64,18 @@
|
||||
regulator-max-microvolt = <12000000>;
|
||||
};
|
||||
|
||||
+ vcc3v3_wf: vcc3v3-wf-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc3v3_wf";
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-0 = <&pow_en>;
|
||||
+ pinctrl-names = "default";
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ };
|
||||
+
|
||||
vcc5v0_host: vcc5v0-host-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_host";
|
||||
@@ -113,6 +125,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
+&combphy0_ps {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&combphy2_psu {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -292,6 +308,14 @@
|
||||
};
|
||||
};
|
||||
|
||||
+&pcie2x1l2 {
|
||||
+ pinctrl-0 = <&pcie20x1m0_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
|
||||
+ vpcie3v3-supply = <&vcc3v3_wf>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&pinctrl {
|
||||
leds {
|
||||
io_led: io-led {
|
||||
@@ -299,6 +323,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ pcie {
|
||||
+ pow_en: pow-en {
|
||||
+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
power {
|
||||
vcc_5v0_en: vcc-5v0-en {
|
||||
rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
From 42145b7a823530f57983fb6e6897f40c0be278d5 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Mon, 18 Sep 2023 16:14:49 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: add PCIe network controller to rock-5b
|
||||
|
||||
Enable the RTL8125 network controller, which is connected via
|
||||
PCIe.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20230918141451.131247-2-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
.../boot/dts/rockchip/rk3588-rock-5b.dts | 27 +++++++++++++++++++
|
||||
1 file changed, 27 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
@@ -43,6 +43,15 @@
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
+ vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc3v3_pcie2x1l2";
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ startup-delay-us = <5000>;
|
||||
+ vin-supply = <&vcc_3v3_s3>;
|
||||
+ };
|
||||
+
|
||||
vcc5v0_host: vcc5v0-host-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_host";
|
||||
@@ -77,6 +86,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
+&combphy0_ps {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&cpu_b0 {
|
||||
cpu-supply = <&vdd_cpu_big0_s0>;
|
||||
};
|
||||
@@ -203,6 +216,14 @@
|
||||
};
|
||||
};
|
||||
|
||||
+&pcie2x1l2 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pcie2_2_rst>;
|
||||
+ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
|
||||
+ vpcie3v3-supply = <&vcc3v3_pcie2x1l2>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&pinctrl {
|
||||
hym8563 {
|
||||
hym8563_int: hym8563-int {
|
||||
@@ -216,6 +237,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ pcie2 {
|
||||
+ pcie2_2_rst: pcie2-2-rst {
|
||||
+ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
usb {
|
||||
vcc5v0_host_en: vcc5v0-host-en {
|
||||
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
From 199cbd5f195adbc0e70ad218cdba82f45750f11b Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Mon, 18 Sep 2023 16:14:50 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: add PCIe for M.2 M-key to rock-5b
|
||||
|
||||
The Radxa Rock 5B has PCIe 3x4 routed to its M.2 M-key connector
|
||||
on the board's back.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20230918141451.131247-3-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
.../boot/dts/rockchip/rk3588-rock-5b.dts | 35 +++++++++++++++++++
|
||||
1 file changed, 35 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
@@ -52,6 +52,19 @@
|
||||
vin-supply = <&vcc_3v3_s3>;
|
||||
};
|
||||
|
||||
+ vcc3v3_pcie30: vcc3v3-pcie30-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pcie3_vcc3v3_en>;
|
||||
+ regulator-name = "vcc3v3_pcie30";
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ startup-delay-us = <5000>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ };
|
||||
+
|
||||
vcc5v0_host: vcc5v0-host-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_host";
|
||||
@@ -224,6 +237,18 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&pcie30phy {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pcie3x4 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pcie3_rst>;
|
||||
+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
+ vpcie3v3-supply = <&vcc3v3_pcie30>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&pinctrl {
|
||||
hym8563 {
|
||||
hym8563_int: hym8563-int {
|
||||
@@ -243,6 +268,16 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ pcie3 {
|
||||
+ pcie3_rst: pcie3-rst {
|
||||
+ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ pcie3_vcc3v3_en: pcie3-vcc3v3-en {
|
||||
+ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
usb {
|
||||
vcc5v0_host_en: vcc5v0-host-en {
|
||||
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
|
|
@ -0,0 +1,80 @@
|
|||
From da447ec387800bdf2df1fb1d8c1522991d025952 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Mon, 18 Sep 2023 16:14:51 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: add PCIe for M.2 E-Key to rock-5b
|
||||
|
||||
Enable PCIe2_0 controller and its voltage supply, which is routed
|
||||
to the M.2 E-Key on the upper side of the Radxa Rock 5B.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20230918141451.131247-4-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
.../boot/dts/rockchip/rk3588-rock-5b.dts | 35 +++++++++++++++++++
|
||||
1 file changed, 35 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
@@ -43,6 +43,21 @@
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
+ vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pcie2_0_vcc3v3_en>;
|
||||
+ regulator-name = "vcc3v3_pcie2x1l0";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ startup-delay-us = <50000>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ };
|
||||
+
|
||||
vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_pcie2x1l2";
|
||||
@@ -103,6 +118,10 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&combphy1_ps {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&cpu_b0 {
|
||||
cpu-supply = <&vdd_cpu_big0_s0>;
|
||||
};
|
||||
@@ -229,6 +248,14 @@
|
||||
};
|
||||
};
|
||||
|
||||
+&pcie2x1l0 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pcie2_0_rst>;
|
||||
+ reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
+ vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&pcie2x1l2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie2_2_rst>;
|
||||
@@ -263,6 +290,14 @@
|
||||
};
|
||||
|
||||
pcie2 {
|
||||
+ pcie2_0_rst: pcie2-0-rst {
|
||||
+ rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ pcie2_0_vcc3v3_en: pcie2-0-vcc-en {
|
||||
+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
pcie2_2_rst: pcie2-2-rst {
|
||||
rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
|
@ -0,0 +1,93 @@
|
|||
From 1c9a53ff7ece056eb995332f0d9523ca43fdcb5a Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Tam=C3=A1s=20Sz=C5=B1cs?= <tszucs@protonmail.ch>
|
||||
Date: Sun, 24 Sep 2023 20:37:45 +0000
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add sdio node to rock-5b
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
Enable SDIO on Radxa ROCK 5 Model B M.2 Key E. Add sdio node and alias as mmc2.
|
||||
Add regulator for the 3.3 V rail bringing it up during boot. Make sure EKEY_EN
|
||||
is muxed as GPIO.
|
||||
|
||||
Signed-off-by: Tamás Szűcs <tszucs@protonmail.ch>
|
||||
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20230924203740.65744-1-tszucs@protonmail.ch
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
.../boot/dts/rockchip/rk3588-rock-5b.dts | 43 +++++++++++++++++++
|
||||
1 file changed, 43 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
@@ -12,6 +12,7 @@
|
||||
aliases {
|
||||
mmc0 = &sdhci;
|
||||
mmc1 = &sdmmc;
|
||||
+ mmc2 = &sdio;
|
||||
};
|
||||
|
||||
chosen {
|
||||
@@ -112,6 +113,21 @@
|
||||
regulator-max-microvolt = <1100000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
+
|
||||
+ vcc3v3_wf: vcc3v3-wf-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc3v3_wf";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ enable-active-high;
|
||||
+ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc3v3_wf_en>;
|
||||
+ startup-delay-us = <50000>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ };
|
||||
};
|
||||
|
||||
&combphy0_ps {
|
||||
@@ -318,6 +334,12 @@
|
||||
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
+
|
||||
+ m2e {
|
||||
+ vcc3v3_wf_en: vcc3v3-wf-en {
|
||||
+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
@@ -354,6 +376,27 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&sdio {
|
||||
+ max-frequency = <200000000>;
|
||||
+ no-sd;
|
||||
+ no-mmc;
|
||||
+ non-removable;
|
||||
+ bus-width = <4>;
|
||||
+ cap-sdio-irq;
|
||||
+ disable-wp;
|
||||
+ keep-power-in-suspend;
|
||||
+ wakeup-source;
|
||||
+ sd-uhs-sdr12;
|
||||
+ sd-uhs-sdr25;
|
||||
+ sd-uhs-sdr50;
|
||||
+ sd-uhs-sdr104;
|
||||
+ vmmc-supply = <&vcc3v3_wf>;
|
||||
+ vqmmc-supply = <&vcc_1v8_s3>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sdiom0_pins>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&spi2 {
|
||||
status = "okay";
|
||||
assigned-clocks = <&cru CLK_SPI2>;
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
From 0002c377e862140ad65b67b8b9dbf086d4578f95 Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Tam=C3=A1s=20Sz=C5=B1cs?= <tszucs@protonmail.ch>
|
||||
Date: Wed, 11 Oct 2023 18:18:05 +0000
|
||||
Subject: [PATCH] arm64: dts: rockchip: Remove duplicate regulator vcc3v3_wf
|
||||
from rock-5b
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
Regulator for VCC3V3_WF has been added as vcc3v3_pcie2x1l0 first. Clean this up.
|
||||
|
||||
Fixes: 1c9a53ff7ece ("arm64: dts: rockchip: Add sdio node to rock-5b")
|
||||
Signed-off-by: Tamás Szűcs <tszucs@protonmail.ch>
|
||||
Link: https://lore.kernel.org/r/20231011181757.58047-1-tszucs@protonmail.ch
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
.../boot/dts/rockchip/rk3588-rock-5b.dts | 23 +------------------
|
||||
1 file changed, 1 insertion(+), 22 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
@@ -113,21 +113,6 @@
|
||||
regulator-max-microvolt = <1100000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
-
|
||||
- vcc3v3_wf: vcc3v3-wf-regulator {
|
||||
- compatible = "regulator-fixed";
|
||||
- regulator-name = "vcc3v3_wf";
|
||||
- regulator-always-on;
|
||||
- regulator-boot-on;
|
||||
- regulator-min-microvolt = <3300000>;
|
||||
- regulator-max-microvolt = <3300000>;
|
||||
- enable-active-high;
|
||||
- gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
|
||||
- pinctrl-names = "default";
|
||||
- pinctrl-0 = <&vcc3v3_wf_en>;
|
||||
- startup-delay-us = <50000>;
|
||||
- vin-supply = <&vcc5v0_sys>;
|
||||
- };
|
||||
};
|
||||
|
||||
&combphy0_ps {
|
||||
@@ -334,12 +319,6 @@
|
||||
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
-
|
||||
- m2e {
|
||||
- vcc3v3_wf_en: vcc3v3-wf-en {
|
||||
- rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
- };
|
||||
- };
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
@@ -390,7 +369,7 @@
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
- vmmc-supply = <&vcc3v3_wf>;
|
||||
+ vmmc-supply = <&vcc3v3_pcie2x1l0>;
|
||||
vqmmc-supply = <&vcc_1v8_s3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdiom0_pins>;
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
From a6169ab369236f15c79b45037074a2567d30b037 Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Tam=C3=A1s=20Sz=C5=B1cs?= <szucst@iit.uni-miskolc.hu>
|
||||
Date: Fri, 13 Oct 2023 23:51:53 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: Enable UART6 on rock-5b
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
Enable UART lines on Radxa ROCK 5 Model B M.2 Key E.
|
||||
|
||||
Signed-off-by: Tamás Szűcs <szucst@iit.uni-miskolc.hu>
|
||||
Link: https://lore.kernel.org/r/20231013215208.81345-1-szucst@iit.uni-miskolc.hu
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 6 ++++++
|
||||
1 file changed, 6 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
@@ -376,6 +376,12 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&uart6 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&spi2 {
|
||||
status = "okay";
|
||||
assigned-clocks = <&cru CLK_SPI2>;
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
From 7952cbbda301f7d297c6ac761f9dfafb90205358 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Thu, 5 Oct 2023 15:40:37 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: add status LED to rock-5b
|
||||
|
||||
Describe the Rock 5B status LED in its device tree.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20231005134037.33231-1-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
.../boot/dts/rockchip/rk3588-rock-5b.dts | 20 +++++++++++++++++++
|
||||
1 file changed, 20 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
@@ -3,6 +3,7 @@
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
+#include <dt-bindings/leds/common.h>
|
||||
#include "rk3588.dtsi"
|
||||
|
||||
/ {
|
||||
@@ -36,6 +37,19 @@
|
||||
pinctrl-0 = <&hp_detect>;
|
||||
};
|
||||
|
||||
+ leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&led_rgb_b>;
|
||||
+
|
||||
+ led_rgb_b {
|
||||
+ function = LED_FUNCTION_STATUS;
|
||||
+ color = <LED_COLOR_ID_BLUE>;
|
||||
+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
+ linux,default-trigger = "heartbeat";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
fan: pwm-fan {
|
||||
compatible = "pwm-fan";
|
||||
cooling-levels = <0 95 145 195 255>;
|
||||
@@ -284,6 +298,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ leds {
|
||||
+ led_rgb_b: led-rgb-b {
|
||||
+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
sound {
|
||||
hp_detect: hp-detect {
|
||||
rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
From f97d78b9f6cff4c680206a8c8b03f726f0dc2c8b Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Mon, 6 Nov 2023 16:54:31 +0100
|
||||
Subject: [PATCH] arm64: dts: rockchip: add USB3 host to rock-5b
|
||||
|
||||
Enable USB3 host controller for the Radxa ROCK 5 Model B. This adds
|
||||
USB3 for the upper USB3 port (the one further away from the PCB).
|
||||
|
||||
The lower USB3 and the USB-C ports use the RK3588 USB TypeC host
|
||||
controller, which use a different PHY without upstream support.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20231106155934.80838-1-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 8 ++++++++
|
||||
1 file changed, 8 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
@@ -137,6 +137,10 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&combphy2_psu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&cpu_b0 {
|
||||
cpu-supply = <&vdd_cpu_big0_s0>;
|
||||
};
|
||||
@@ -764,3 +768,7 @@
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
+
|
||||
+&usb_host2_xhci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
From 7738f551173540b3daa63a91b384b167eacd24fd Mon Sep 17 00:00:00 2001
|
||||
From: John Clark <inindev@gmail.com>
|
||||
Date: Mon, 25 Dec 2023 22:28:19 +0000
|
||||
Subject: [PATCH] arm64: dts: rockchip: support poweroff on the rock-5b
|
||||
|
||||
Allow the rock-5b to poweroff its pmic. When issuing a "shutdown -h now"
|
||||
on the rock-5b it reboots instead. Defining 'system-power-controller'
|
||||
allows the rk806 to power down.
|
||||
|
||||
Commit c699fbfdfd54 ("arm64: dts: rockchip: Support poweroff on
|
||||
NanoPC-T6") similarly resolves this issue for the nanopc-t6.
|
||||
|
||||
Signed-off-by: John Clark <inindev@gmail.com>
|
||||
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20231225222859.17153-1-inindev@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
@@ -426,6 +426,8 @@
|
||||
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
|
||||
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
|
||||
|
||||
+ system-power-controller;
|
||||
+
|
||||
vcc1-supply = <&vcc5v0_sys>;
|
||||
vcc2-supply = <&vcc5v0_sys>;
|
||||
vcc3-supply = <&vcc5v0_sys>;
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
From aed6514c4e3aee843385ded4c5ee0921b51c30fa Mon Sep 17 00:00:00 2001
|
||||
From: John Clark <inindev@gmail.com>
|
||||
Date: Mon, 25 Dec 2023 22:28:20 +0000
|
||||
Subject: [PATCH] arm64: dts: rockchip: correct gpio_pwrctrl1 typo on rock-5b
|
||||
|
||||
Both rk806_dvs1_null and rk806_dvs2_null duplicate gpio_pwrctrl2 and
|
||||
gpio_pwrctrl1 is not set. This patch sets gpio_pwrctrl1.
|
||||
|
||||
Signed-off-by: John Clark <inindev@gmail.com>
|
||||
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20231225222859.17153-2-inindev@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
@@ -448,7 +448,7 @@
|
||||
#gpio-cells = <2>;
|
||||
|
||||
rk806_dvs1_null: dvs1-null-pins {
|
||||
- pins = "gpio_pwrctrl2";
|
||||
+ pins = "gpio_pwrctrl1";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
From 82d40b141a4c7ab6608a84a5ce0c58b747cb7163 Mon Sep 17 00:00:00 2001
|
||||
From: Alexey Charkov <alchark@gmail.com>
|
||||
Date: Sun, 7 Jan 2024 00:26:45 +0400
|
||||
Subject: [PATCH] arm64: dts: rockchip: add rfkill node for M.2 Key E WiFi on rock-5b
|
||||
|
||||
By default the GPIO pin that connects to the WiFi enable signal
|
||||
inside the M.2 Key E slot is driven low, resulting in impossibility
|
||||
to connect to any network. Add a DT node to expose it as an RFKILL
|
||||
device, which lets the WiFi driver or userspace toggle it as
|
||||
required.
|
||||
|
||||
Signed-off-by: Alexey Charkov <alchark@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20240106202650.22310-1-alchark@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 7 +++++++
|
||||
1 file changed, 7 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
@@ -58,6 +58,13 @@
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
+ rfkill {
|
||||
+ compatible = "rfkill-gpio";
|
||||
+ label = "rfkill-pcie-wlan";
|
||||
+ radio-type = "wlan";
|
||||
+ shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+
|
||||
vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
From 038347286941148b6fd0cc2c40afcd540315aa6f Mon Sep 17 00:00:00 2001
|
||||
From: Boris Brezillon <boris.brezillon@collabora.com>
|
||||
Date: Tue, 26 Mar 2024 17:52:07 +0100
|
||||
Subject: [PATCH] arm64: dts: rockchip: Enable GPU on rk3588-rock5b
|
||||
|
||||
Enable the Mali GPU in the Rock 5B.
|
||||
|
||||
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20240326165232.73585-4-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 5 +++++
|
||||
1 file changed, 5 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
@@ -180,6 +180,11 @@
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
};
|
||||
|
||||
+&gpu {
|
||||
+ mali-supply = <&vdd_gpu_s0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0m2_xfer>;
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
From 45e831033f7a00a14f64afa1e34c476a9ff0f9f0 Mon Sep 17 00:00:00 2001
|
||||
From: Dragan Simic <dsimic@manjaro.org>
|
||||
Date: Thu, 18 Apr 2024 18:26:20 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: Correct the model names for Radxa ROCK
|
||||
5 boards
|
||||
|
||||
Correct the descriptions of a few Radxa boards, according to the up-to-date
|
||||
documentation from Radxa and the detailed explanation from Naoki. [1] To sum
|
||||
it up, the short naming, as specified by Radxa, is preferred.
|
||||
|
||||
[1] https://lore.kernel.org/linux-rockchip/B26C732A4DCEA9B3+282b8775-601b-4d4a-a513-4924b7940076@radxa.com/
|
||||
|
||||
Suggested-by: FUKAUMI Naoki <naoki@radxa.com>
|
||||
Signed-off-by: Dragan Simic <dsimic@manjaro.org>
|
||||
Link: https://lore.kernel.org/r/6931289a252dc2d6c7bfd2388835c5e98ba0d8c9.1713457260.git.dsimic@manjaro.org
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 2 +-
|
||||
arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 2 +-
|
||||
2 files changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
@@ -7,7 +7,7 @@
|
||||
#include "rk3588.dtsi"
|
||||
|
||||
/ {
|
||||
- model = "Radxa ROCK 5 Model B";
|
||||
+ model = "Radxa ROCK 5B";
|
||||
compatible = "radxa,rock-5b", "rockchip,rk3588";
|
||||
|
||||
aliases {
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
|
||||
@@ -8,7 +8,7 @@
|
||||
#include "rk3588s.dtsi"
|
||||
|
||||
/ {
|
||||
- model = "Radxa ROCK 5 Model A";
|
||||
+ model = "Radxa ROCK 5A";
|
||||
compatible = "radxa,rock-5a", "rockchip,rk3588s";
|
||||
|
||||
aliases {
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
From 494532921aacb496529d544fedfdb3a7b43dfef0 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Tue, 9 Apr 2024 00:50:37 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: add lower USB3 port to rock-5b
|
||||
|
||||
Enable full support (XHCI, EHCI, OHCI) for the lower USB3 port from
|
||||
Radxa Rock 5 Model B. The upper one is already supported.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20240408225109.128953-11-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 17 +++++++++++++++++
|
||||
1 file changed, 17 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
@@ -748,6 +748,14 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&u2phy1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy1_otg {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&u2phy2 {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -767,6 +775,10 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&usbdp_phy1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -783,6 +795,11 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&usb_host1_xhci {
|
||||
+ dr_mode = "host";
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&usb_host2_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,67 @@
|
|||
From 4a152231b050590af771fa3cc8462ed08b691a24 Mon Sep 17 00:00:00 2001
|
||||
From: Alexey Charkov <alchark@gmail.com>
|
||||
Date: Mon, 17 Jun 2024 22:28:54 +0400
|
||||
Subject: [PATCH] arm64: dts: rockchip: enable automatic fan control on Rock 5B
|
||||
|
||||
This links the PWM fan on Radxa Rock 5B as an active cooling device
|
||||
managed automatically by the thermal subsystem, with a target SoC
|
||||
temperature of 65C and a minimum-spin interval from 55C to 65C to
|
||||
ensure airflow when the system gets warm
|
||||
|
||||
Helped-by: Dragan Simic <dsimic@manjaro.org>
|
||||
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
|
||||
Signed-off-by: Alexey Charkov <alchark@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-4-c1f5f3267f1e@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
.../boot/dts/rockchip/rk3588-rock-5b.dts | 32 ++++++++++++++++++-
|
||||
1 file changed, 31 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
@@ -52,7 +52,7 @@
|
||||
|
||||
fan: pwm-fan {
|
||||
compatible = "pwm-fan";
|
||||
- cooling-levels = <0 95 145 195 255>;
|
||||
+ cooling-levels = <0 120 150 180 210 240 255>;
|
||||
fan-supply = <&vcc5v0_sys>;
|
||||
pwms = <&pwm1 0 50000 0>;
|
||||
#cooling-cells = <2>;
|
||||
@@ -278,6 +278,36 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
+
|
||||
+&package_thermal {
|
||||
+ polling-delay = <1000>;
|
||||
+
|
||||
+ trips {
|
||||
+ package_fan0: package-fan0 {
|
||||
+ temperature = <55000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "active";
|
||||
+ };
|
||||
+
|
||||
+ package_fan1: package-fan1 {
|
||||
+ temperature = <65000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "active";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cooling-maps {
|
||||
+ map1 {
|
||||
+ trip = <&package_fan0>;
|
||||
+ cooling-device = <&fan THERMAL_NO_LIMIT 1>;
|
||||
+ };
|
||||
+
|
||||
+ map2 {
|
||||
+ trip = <&package_fan1>;
|
||||
+ cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
|
||||
&pcie2x1l0 {
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
From 9204a7ecca96403ee3d61c14cb9eb87ec89b0fcd Mon Sep 17 00:00:00 2001
|
||||
From: FUKAUMI Naoki <naoki@radxa.com>
|
||||
Date: Sun, 23 Jun 2024 11:33:27 +0900
|
||||
Subject: [PATCH] arm64: dts: rockchip: add SFC support for Radxa ROCK 5B
|
||||
|
||||
This commit adds support for SPI NOR flash on Radxa ROCK 5B.
|
||||
|
||||
SPI NOR flash chip may vary, so use safe(lowest) spi-max-frequency.
|
||||
|
||||
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
|
||||
Link: https://lore.kernel.org/r/20240623023329.1044-1-naoki@radxa.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 14 ++++++++++++++
|
||||
1 file changed, 14 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
||||
@@ -442,6 +442,20 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&sfc {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&fspim2_pins>;
|
||||
+ status = "okay";
|
||||
+
|
||||
+ flash@0 {
|
||||
+ compatible = "jedec,spi-nor";
|
||||
+ reg = <0>;
|
||||
+ spi-max-frequency = <104000000>;
|
||||
+ spi-rx-bus-width = <4>;
|
||||
+ spi-tx-bus-width = <1>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
&uart6 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>;
|
||||
|
|
@ -0,0 +1,792 @@
|
|||
From f1b11f43b3e983b26d8010fc43ba6c2b979826f2 Mon Sep 17 00:00:00 2001
|
||||
From: Muhammed Efe Cetin <efectn@protonmail.com>
|
||||
Date: Sat, 30 Dec 2023 14:18:00 +0300
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add support for NanoPi R6S
|
||||
|
||||
Add basic NanoPi R6S support that comes with USB2, PCIe, SD card, eMMC
|
||||
support.
|
||||
|
||||
Signed-off-by: Muhammed Efe Cetin <efectn@protonmail.com>
|
||||
Link: https://lore.kernel.org/r/6db3b653efc6f0a2dca8e96fdd0503906db72fb6.1703934548.git.efectn@protonmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/Makefile | 1 +
|
||||
.../boot/dts/rockchip/rk3588s-nanopi-r6s.dts | 764 ++++++++++++++++++
|
||||
2 files changed, 765 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -109,4 +109,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-na
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-indiedroid-nova.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts
|
||||
@@ -0,0 +1,764 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+#include <dt-bindings/pinctrl/rockchip.h>
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+#include <dt-bindings/input/input.h>
|
||||
+#include "rk3588s.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "FriendlyElec NanoPi R6S";
|
||||
+ compatible = "friendlyarm,nanopi-r6s", "rockchip,rk3588s";
|
||||
+
|
||||
+ aliases {
|
||||
+ ethernet0 = &gmac1;
|
||||
+ mmc0 = &sdmmc;
|
||||
+ mmc1 = &sdhci;
|
||||
+ };
|
||||
+
|
||||
+ chosen {
|
||||
+ stdout-path = "serial2:1500000n8";
|
||||
+ };
|
||||
+
|
||||
+ adc-keys {
|
||||
+ compatible = "adc-keys";
|
||||
+ io-channels = <&saradc 0>;
|
||||
+ io-channel-names = "buttons";
|
||||
+ keyup-threshold-microvolt = <1800000>;
|
||||
+ poll-interval = <100>;
|
||||
+
|
||||
+ button-maskrom {
|
||||
+ label = "Maskrom";
|
||||
+ linux,code = <KEY_VENDOR>;
|
||||
+ press-threshold-microvolt = <1800>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gpio-keys {
|
||||
+ compatible = "gpio-keys";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&key1_pin>;
|
||||
+
|
||||
+ button-user {
|
||||
+ label = "User";
|
||||
+ linux,code = <BTN_1>;
|
||||
+ gpios = <&gpio1 RK_PC0 GPIO_ACTIVE_LOW>;
|
||||
+ debounce-interval = <50>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+
|
||||
+ sys_led: led-0 {
|
||||
+ label = "sys_led";
|
||||
+ gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
|
||||
+ linux,default-trigger = "heartbeat";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sys_led_pin>;
|
||||
+ };
|
||||
+
|
||||
+ wan_led: led-1 {
|
||||
+ label = "wan_led";
|
||||
+ gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&wan_led_pin>;
|
||||
+ };
|
||||
+
|
||||
+ lan1_led: led-2 {
|
||||
+ label = "lan1_led";
|
||||
+ gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&lan1_led_pin>;
|
||||
+ };
|
||||
+
|
||||
+ lan2_led: led-3 {
|
||||
+ label = "lan2_led";
|
||||
+ gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&lan2_led_pin>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_sys: vcc5v0-sys-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc5v0_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ };
|
||||
+
|
||||
+ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc_1v1_nldo_s3";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1100000>;
|
||||
+ regulator-max-microvolt = <1100000>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc_3v3_s0: vcc-3v3-s0-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ regulator-name = "vcc_3v3_s0";
|
||||
+ vin-supply = <&vcc_3v3_s3>;
|
||||
+ };
|
||||
+
|
||||
+ vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sd_s0_pwr>;
|
||||
+ regulator-name = "vcc_3v3_sd_s0";
|
||||
+ regulator-boot-on;
|
||||
+ regulator-max-microvolt = <3000000>;
|
||||
+ regulator-min-microvolt = <3000000>;
|
||||
+ vin-supply = <&vcc_3v3_s3>;
|
||||
+ };
|
||||
+
|
||||
+ vcc_3v3_pcie20: vcc3v3-pcie20-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc_3v3_pcie20";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ vin-supply = <&vcc_3v3_s3>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_usb: vcc5v0-usb-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc5v0_usb";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_usb_otg0: vcc5v0-usb-otg0-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&typec5v_pwren>;
|
||||
+ regulator-name = "vcc5v0_usb_otg0";
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&vcc5v0_usb>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_host_20: vcc5v0-host-20-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc5v0_host20_en>;
|
||||
+ regulator-name = "vcc5v0_host_20";
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&vcc5v0_usb>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&combphy0_ps {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&combphy2_psu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&cpu_b0 {
|
||||
+ cpu-supply = <&vdd_cpu_big0_s0>;
|
||||
+};
|
||||
+
|
||||
+&cpu_b1 {
|
||||
+ cpu-supply = <&vdd_cpu_big0_s0>;
|
||||
+};
|
||||
+
|
||||
+&cpu_b2 {
|
||||
+ cpu-supply = <&vdd_cpu_big1_s0>;
|
||||
+};
|
||||
+
|
||||
+&cpu_b3 {
|
||||
+ cpu-supply = <&vdd_cpu_big1_s0>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l0 {
|
||||
+ cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l1 {
|
||||
+ cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l2 {
|
||||
+ cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l3 {
|
||||
+ cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
+};
|
||||
+
|
||||
+&gmac1 {
|
||||
+ clock_in_out = "output";
|
||||
+ phy-handle = <&rgmii_phy1>;
|
||||
+ phy-mode = "rgmii-rxid";
|
||||
+ pinctrl-0 = <&gmac1_miim
|
||||
+ &gmac1_tx_bus2
|
||||
+ &gmac1_rx_bus2
|
||||
+ &gmac1_rgmii_clk
|
||||
+ &gmac1_rgmii_bus>;
|
||||
+ pinctrl-names = "default";
|
||||
+ tx_delay = <0x42>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2c0 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&i2c0m2_xfer>;
|
||||
+ status = "okay";
|
||||
+
|
||||
+ vdd_cpu_big0_s0: regulator@42 {
|
||||
+ compatible = "rockchip,rk8602";
|
||||
+ reg = <0x42>;
|
||||
+ fcs,suspend-voltage-selector = <1>;
|
||||
+ regulator-name = "vdd_cpu_big0_s0";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <550000>;
|
||||
+ regulator-max-microvolt = <1050000>;
|
||||
+ regulator-ramp-delay = <2300>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_cpu_big1_s0: regulator@43 {
|
||||
+ compatible = "rockchip,rk8603", "rockchip,rk8602";
|
||||
+ reg = <0x43>;
|
||||
+ fcs,suspend-voltage-selector = <1>;
|
||||
+ regulator-name = "vdd_cpu_big1_s0";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <550000>;
|
||||
+ regulator-max-microvolt = <1050000>;
|
||||
+ regulator-ramp-delay = <2300>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2c2 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ vdd_npu_s0: regulator@42 {
|
||||
+ compatible = "rockchip,rk8602";
|
||||
+ reg = <0x42>;
|
||||
+ fcs,suspend-voltage-selector = <1>;
|
||||
+ regulator-name = "vdd_npu_s0";
|
||||
+ regulator-min-microvolt = <550000>;
|
||||
+ regulator-max-microvolt = <950000>;
|
||||
+ regulator-ramp-delay = <2300>;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-always-on;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2c6 {
|
||||
+ clock-frequency = <200000>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&i2c6m0_xfer>;
|
||||
+ status = "okay";
|
||||
+
|
||||
+ hym8563: rtc@51 {
|
||||
+ compatible = "haoyu,hym8563";
|
||||
+ reg = <0x51>;
|
||||
+ #clock-cells = <0>;
|
||||
+ clock-output-names = "hym8563";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&rtc_int>;
|
||||
+ interrupt-parent = <&gpio0>;
|
||||
+ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ wakeup-source;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&mdio1 {
|
||||
+ rgmii_phy1: ethernet-phy@1 {
|
||||
+ compatible = "ethernet-phy-id001c.c916";
|
||||
+ reg = <0x1>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&rtl8211f_rst>;
|
||||
+ reset-assert-us = <20000>;
|
||||
+ reset-deassert-us = <100000>;
|
||||
+ reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pcie2x1l1 {
|
||||
+ reset-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
|
||||
+ vpcie3v3-supply = <&vcc_3v3_pcie20>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pcie2x1l2 {
|
||||
+ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
|
||||
+ vpcie3v3-supply = <&vcc_3v3_pcie20>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ gpio-key {
|
||||
+ key1_pin: key1-pin {
|
||||
+ rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gpio-leds {
|
||||
+ sys_led_pin: sys-led-pin {
|
||||
+ rockchip,pins =
|
||||
+ <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ wan_led_pin: wan-led-pin {
|
||||
+ rockchip,pins =
|
||||
+ <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ lan1_led_pin: lan1-led-pin {
|
||||
+ rockchip,pins =
|
||||
+ <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ lan2_led_pin: lan2-led-pin {
|
||||
+ rockchip,pins =
|
||||
+ <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ hym8563 {
|
||||
+ rtc_int: rtc-int {
|
||||
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ sdmmc {
|
||||
+ sd_s0_pwr: sd-s0-pwr {
|
||||
+ rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ usb {
|
||||
+ typec5v_pwren: typec5v-pwren {
|
||||
+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_host20_en: vcc5v0-host20-en {
|
||||
+ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rtl8211f {
|
||||
+ rtl8211f_rst: rtl8211f-rst {
|
||||
+ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&saradc {
|
||||
+ vref-supply = <&avcc_1v8_s0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdhci {
|
||||
+ bus-width = <8>;
|
||||
+ no-sdio;
|
||||
+ no-sd;
|
||||
+ non-removable;
|
||||
+ mmc-hs200-1_8v;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdmmc {
|
||||
+ bus-width = <4>;
|
||||
+ cap-sd-highspeed;
|
||||
+ disable-wp;
|
||||
+ max-frequency = <150000000>;
|
||||
+ no-mmc;
|
||||
+ no-sdio;
|
||||
+ sd-uhs-sdr104;
|
||||
+ vmmc-supply = <&vcc_3v3_sd_s0>;
|
||||
+ vqmmc-supply = <&vccio_sd_s0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&spi2 {
|
||||
+ status = "okay";
|
||||
+ assigned-clocks = <&cru CLK_SPI2>;
|
||||
+ assigned-clock-rates = <200000000>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
|
||||
+ num-cs = <1>;
|
||||
+
|
||||
+ pmic@0 {
|
||||
+ compatible = "rockchip,rk806";
|
||||
+ spi-max-frequency = <1000000>;
|
||||
+ reg = <0x0>;
|
||||
+
|
||||
+ interrupt-parent = <&gpio0>;
|
||||
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
|
||||
+
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
|
||||
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
|
||||
+
|
||||
+ system-power-controller;
|
||||
+
|
||||
+ vcc1-supply = <&vcc5v0_sys>;
|
||||
+ vcc2-supply = <&vcc5v0_sys>;
|
||||
+ vcc3-supply = <&vcc5v0_sys>;
|
||||
+ vcc4-supply = <&vcc5v0_sys>;
|
||||
+ vcc5-supply = <&vcc5v0_sys>;
|
||||
+ vcc6-supply = <&vcc5v0_sys>;
|
||||
+ vcc7-supply = <&vcc5v0_sys>;
|
||||
+ vcc8-supply = <&vcc5v0_sys>;
|
||||
+ vcc9-supply = <&vcc5v0_sys>;
|
||||
+ vcc10-supply = <&vcc5v0_sys>;
|
||||
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
|
||||
+ vcc12-supply = <&vcc5v0_sys>;
|
||||
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
|
||||
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
|
||||
+ vcca-supply = <&vcc5v0_sys>;
|
||||
+
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+
|
||||
+ rk806_dvs1_null: dvs1-null-pins {
|
||||
+ pins = "gpio_pwrctrl1";
|
||||
+ function = "pin_fun0";
|
||||
+ };
|
||||
+
|
||||
+ rk806_dvs2_null: dvs2-null-pins {
|
||||
+ pins = "gpio_pwrctrl2";
|
||||
+ function = "pin_fun0";
|
||||
+ };
|
||||
+
|
||||
+ rk806_dvs3_null: dvs3-null-pins {
|
||||
+ pins = "gpio_pwrctrl3";
|
||||
+ function = "pin_fun0";
|
||||
+ };
|
||||
+
|
||||
+ regulators {
|
||||
+ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <550000>;
|
||||
+ regulator-max-microvolt = <950000>;
|
||||
+ regulator-ramp-delay = <12500>;
|
||||
+ regulator-name = "vdd_gpu_s0";
|
||||
+ regulator-enable-ramp-delay = <400>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <550000>;
|
||||
+ regulator-max-microvolt = <950000>;
|
||||
+ regulator-ramp-delay = <12500>;
|
||||
+ regulator-name = "vdd_cpu_lit_s0";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_log_s0: dcdc-reg3 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <675000>;
|
||||
+ regulator-max-microvolt = <750000>;
|
||||
+ regulator-ramp-delay = <12500>;
|
||||
+ regulator-name = "vdd_log_s0";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ regulator-suspend-microvolt = <750000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <550000>;
|
||||
+ regulator-max-microvolt = <950000>;
|
||||
+ regulator-ramp-delay = <12500>;
|
||||
+ regulator-name = "vdd_vdenc_s0";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_ddr_s0: dcdc-reg5 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <675000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+ regulator-ramp-delay = <12500>;
|
||||
+ regulator-name = "vdd_ddr_s0";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ regulator-suspend-microvolt = <850000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd2_ddr_s3: dcdc-reg6 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-name = "vdd2_ddr_s3";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_2v0_pldo_s3: dcdc-reg7 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <2000000>;
|
||||
+ regulator-max-microvolt = <2000000>;
|
||||
+ regulator-ramp-delay = <12500>;
|
||||
+ regulator-name = "vdd_2v0_pldo_s3";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <2000000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_3v3_s3: dcdc-reg8 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ regulator-name = "vcc_3v3_s3";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3300000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vddq_ddr_s0: dcdc-reg9 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-name = "vddq_ddr_s0";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_1v8_s3: dcdc-reg10 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ regulator-name = "vcc_1v8_s3";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ avcc_1v8_s0: pldo-reg1 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ regulator-name = "avcc_1v8_s0";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_1v8_s0: pldo-reg2 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ regulator-name = "vcc_1v8_s0";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ avdd_1v2_s0: pldo-reg3 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1200000>;
|
||||
+ regulator-max-microvolt = <1200000>;
|
||||
+ regulator-name = "avdd_1v2_s0";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ avcc_3v3_s0: pldo-reg4 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ regulator-ramp-delay = <12500>;
|
||||
+ regulator-name = "avcc_3v3_s0";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vccio_sd_s0: pldo-reg5 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ regulator-ramp-delay = <12500>;
|
||||
+ regulator-name = "vccio_sd_s0";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pldo6_s3: pldo-reg6 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ regulator-name = "pldo6_s3";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_0v75_s3: nldo-reg1 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <750000>;
|
||||
+ regulator-max-microvolt = <750000>;
|
||||
+ regulator-name = "vdd_0v75_s3";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <750000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ avdd_ddr_pll_s0: nldo-reg2 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <850000>;
|
||||
+ regulator-max-microvolt = <850000>;
|
||||
+ regulator-name = "avdd_ddr_pll_s0";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ regulator-suspend-microvolt = <850000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ avdd_0v75_s0: nldo-reg3 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <750000>;
|
||||
+ regulator-max-microvolt = <750000>;
|
||||
+ regulator-name = "avdd_0v75_s0";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ avdd_0v85_s0: nldo-reg4 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <850000>;
|
||||
+ regulator-max-microvolt = <850000>;
|
||||
+ regulator-name = "avdd_0v85_s0";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_0v75_s0: nldo-reg5 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <750000>;
|
||||
+ regulator-max-microvolt = <750000>;
|
||||
+ regulator-name = "vdd_0v75_s0";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&tsadc {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy2_host {
|
||||
+ phy-supply = <&vcc5v0_host_20>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ pinctrl-0 = <&uart2m0_xfer>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
From d5f1d7437451dbd86a91747793ecd7842e0ce88f Mon Sep 17 00:00:00 2001
|
||||
From: Muhammed Efe Cetin <efectn@protonmail.com>
|
||||
Date: Sat, 30 Dec 2023 14:18:01 +0300
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add support for NanoPi R6C
|
||||
|
||||
NanoPi R6C is mostly same as R6S variant. It has M2 port instead of a
|
||||
NIC port and different led labeling.
|
||||
|
||||
Signed-off-by: Muhammed Efe Cetin <efectn@protonmail.com>
|
||||
Link: https://lore.kernel.org/r/0f9ee0baa6c9de4d54dd6d13957ca15a63ec934f.1703934548.git.efectn@protonmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/Makefile | 1 +
|
||||
.../arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts | 14 ++++++++++++++
|
||||
2 files changed, 15 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -110,4 +110,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ro
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-indiedroid-nova.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts
|
||||
@@ -0,0 +1,14 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+#include "rk3588s-nanopi-r6s.dts"
|
||||
+
|
||||
+/ {
|
||||
+ model = "FriendlyElec NanoPi R6C";
|
||||
+ compatible = "friendlyarm,nanopi-r6c", "rockchip,rk3588s";
|
||||
+};
|
||||
+
|
||||
+&lan2_led {
|
||||
+ label = "user_led";
|
||||
+};
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
From c699fbfdfd54630fc51b96da577f02e7b772eb37 Mon Sep 17 00:00:00 2001
|
||||
From: Hugh Cole-Baker <sigmaris@gmail.com>
|
||||
Date: Sat, 16 Dec 2023 21:21:34 +0000
|
||||
Subject: [PATCH] arm64: dts: rockchip: Support poweroff on NanoPC-T6
|
||||
|
||||
The RK806 on the NanoPC-T6 can be used to power on/off the whole board.
|
||||
Mark it as the system power controller.
|
||||
|
||||
Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20231216212134.23314-1-sigmaris@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
|
||||
@@ -569,6 +569,8 @@
|
||||
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
|
||||
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
|
||||
|
||||
+ system-power-controller;
|
||||
+
|
||||
vcc1-supply = <&vcc4v0_sys>;
|
||||
vcc2-supply = <&vcc4v0_sys>;
|
||||
vcc3-supply = <&vcc4v0_sys>;
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
From 9e1faff1cbc877903d019a7943d37ddc5042704d Mon Sep 17 00:00:00 2001
|
||||
From: John Clark <inindev@gmail.com>
|
||||
Date: Thu, 28 Dec 2023 17:29:35 +0000
|
||||
Subject: [PATCH] arm64: dts: rockchip: nanopc-t6 sdmmc beautification
|
||||
|
||||
drop max-frequency = <200000000> as it is already defined in rk3588s.dtsi
|
||||
order no-sdio & no-mmc properties while we are here
|
||||
|
||||
Signed-off-by: John Clark <inindev@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20231228173011.2863-1-inindev@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 5 ++---
|
||||
1 file changed, 2 insertions(+), 3 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
|
||||
@@ -536,13 +536,12 @@
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
- max-frequency = <200000000>;
|
||||
- no-sdio;
|
||||
- no-mmc;
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
disable-wp;
|
||||
+ no-mmc;
|
||||
+ no-sdio;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc_3v3_s3>;
|
||||
vqmmc-supply = <&vccio_sd_s0>;
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
From 24559788384916041a0bbf54c32e2a16b612d247 Mon Sep 17 00:00:00 2001
|
||||
From: John Clark <inindev@gmail.com>
|
||||
Date: Mon, 25 Dec 2023 22:32:16 +0000
|
||||
Subject: [PATCH] arm64: dts: rockchip: correct gpio_pwrctrl1 typo on nanopc-t6
|
||||
|
||||
Both rk806_dvs1_null and rk806_dvs2_null duplicate gpio_pwrctrl2 and
|
||||
gpio_pwrctrl1 is not set. This patch sets gpio_pwrctrl1.
|
||||
|
||||
Signed-off-by: John Clark <inindev@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20231225223226.17690-1-inindev@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
|
||||
@@ -590,7 +590,7 @@
|
||||
#gpio-cells = <2>;
|
||||
|
||||
rk806_dvs1_null: dvs1-null-pins {
|
||||
- pins = "gpio_pwrctrl2";
|
||||
+ pins = "gpio_pwrctrl1";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
From d235e65adf00f6db09331874c5a987b7fe18023b Mon Sep 17 00:00:00 2001
|
||||
From: Hugh Cole-Baker <sigmaris@gmail.com>
|
||||
Date: Tue, 9 Jan 2024 20:27:28 +0000
|
||||
Subject: [PATCH] arm64: dts: rockchip: enable NanoPC-T6 MiniPCIe power
|
||||
|
||||
The NanoPC-T6 has a Mini PCIe slot intended to be used for a 4G or LTE
|
||||
modem. This slot has no PCIe functionality, only USB 2.0 pins are wired
|
||||
to the SoC, and USIM pins are wired to a SIM card slot on the board.
|
||||
Define the 3.3v supply for the slot so it can be used.
|
||||
|
||||
Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20240109202729.54292-1-sigmaris@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 17 +++++++++++++++++
|
||||
1 file changed, 17 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
|
||||
@@ -159,6 +159,18 @@
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
+
|
||||
+ vdd_4g_3v3: vdd-4g-3v3-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pin_4g_lte_pwren>;
|
||||
+ regulator-name = "vdd_4g_3v3";
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ };
|
||||
};
|
||||
|
||||
&combphy0_ps {
|
||||
@@ -504,6 +516,10 @@
|
||||
};
|
||||
|
||||
usb {
|
||||
+ pin_4g_lte_pwren: 4g-lte-pwren {
|
||||
+ rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
typec5v_pwren: typec5v-pwren {
|
||||
rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
@@ -884,6 +900,7 @@
|
||||
};
|
||||
|
||||
&u2phy2_host {
|
||||
+ phy-supply = <&vdd_4g_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
From d8bb6c2311b6b2aad11b937f96db1d6c3393246a Mon Sep 17 00:00:00 2001
|
||||
From: John Clark <inindev@gmail.com>
|
||||
Date: Sat, 30 Dec 2023 11:50:53 -0500
|
||||
Subject: [PATCH] arm64: dts: rockchip: add sdmmc card detect to the nanopc-t6
|
||||
|
||||
The nanopc-t6 has an sdmmc card detect connected to gpio0_a4 which is
|
||||
active low.
|
||||
|
||||
Signed-off-by: John Clark <inindev@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20231230165053.3781-1-inindev@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
|
||||
@@ -555,6 +555,7 @@
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
no-mmc;
|
||||
no-sdio;
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
From 6cb02674a061e4ef4f437ab60c91038d4c0d85ef Mon Sep 17 00:00:00 2001
|
||||
From: John Clark <inindev@gmail.com>
|
||||
Date: Tue, 2 Jan 2024 02:40:53 +0000
|
||||
Subject: [PATCH] arm64: dts: rockchip: fix nanopc-t6 sdmmc regulator
|
||||
|
||||
sdmmc on the nanopc-t6 is powered by vcc3v3_sd_s0, not vcc_3v3_s3
|
||||
add the vcc3v3_sd_s0 regulator, and control it with gpio4_a5
|
||||
|
||||
Signed-off-by: John Clark <inindev@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20240102024054.1030313-1-inindev@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 13 ++++++++++++-
|
||||
1 file changed, 12 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
|
||||
@@ -160,6 +160,17 @@
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
+ vcc3v3_sd_s0: vcc3v3-sd-s0-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-low;
|
||||
+ gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_LOW>;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-name = "vcc3v3_sd_s0";
|
||||
+ vin-supply = <&vcc_3v3_s3>;
|
||||
+ };
|
||||
+
|
||||
vdd_4g_3v3: vdd-4g-3v3-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
@@ -560,7 +571,7 @@
|
||||
no-mmc;
|
||||
no-sdio;
|
||||
sd-uhs-sdr104;
|
||||
- vmmc-supply = <&vcc_3v3_s3>;
|
||||
+ vmmc-supply = <&vcc3v3_sd_s0>;
|
||||
vqmmc-supply = <&vccio_sd_s0>;
|
||||
status = "okay";
|
||||
};
|
||||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue