diff --git a/.gitignore b/.gitignore index a80cdbbea31..84cfc997705 100644 --- a/.gitignore +++ b/.gitignore @@ -14,6 +14,7 @@ /feeds /feeds.conf /files +/target/linux/feeds /overlay /package/feeds /package/openwrt-packages diff --git a/include/download.mk b/include/download.mk index 9ab0b6c08fc..e261b140354 100644 --- a/include/download.mk +++ b/include/download.mk @@ -209,6 +209,7 @@ define DownloadMethod/github_archive --subdir="$(SUBDIR)" \ --source="$(FILE)" \ --hash="$(MIRROR_HASH)" \ + --submodules $(SUBMODULES) \ || ( $(call DownloadMethod/rawgit) ); \ ) endef @@ -222,7 +223,7 @@ define DownloadMethod/rawgit [ \! -d $(SUBDIR) ] && \ git clone $(OPTS) $(URL) $(SUBDIR) && \ (cd $(SUBDIR) && git checkout $(VERSION) && \ - git submodule update --init --recursive) && \ + $(if $(filter skip,$(SUBMODULES)),true,git submodule update --init --recursive -- $(SUBMODULES))) && \ echo "Packing checkout..." && \ export TAR_TIMESTAMP=`cd $(SUBDIR) && git log -1 --format='@%ct'` && \ rm -rf $(SUBDIR)/.git && \ @@ -301,6 +302,7 @@ define Download/Defaults MIRROR_MD5SUM:=x VERSION:= OPTS:= + SUBMODULES:= endef define Download/default @@ -309,6 +311,7 @@ define Download/default URL_FILE:=$(PKG_SOURCE_URL_FILE) SUBDIR:=$(PKG_SOURCE_SUBDIR) PROTO:=$(PKG_SOURCE_PROTO) + SUBMODULES:=$(PKG_SOURCE_SUBMODULES) $(if $(PKG_SOURCE_MIRROR),MIRROR:=$(filter 1,$(PKG_MIRROR))) $(if $(PKG_MIRROR_MD5SUM),MIRROR_MD5SUM:=$(PKG_MIRROR_MD5SUM)) $(if $(PKG_MIRROR_HASH),MIRROR_HASH:=$(PKG_MIRROR_HASH)) diff --git a/include/kernel-6.1 b/include/kernel-6.1 index f844ef1c295..d1628fbb80c 100644 --- a/include/kernel-6.1 +++ b/include/kernel-6.1 @@ -1,2 +1,2 @@ -LINUX_VERSION-6.1 = .38 -LINUX_KERNEL_HASH-6.1.38 = f9a4f91b609f7d332a5f2be01ab86336fa00149fae6bdc19f16fa19f78802d43 \ No newline at end of file +LINUX_VERSION-6.1 = .41 +LINUX_KERNEL_HASH-6.1.41 = 312809a78eea052a08a6580f47b2ed8dd28e5633461d6731febaf3cb1e570bb7 \ No newline at end of file diff --git a/package/boot/arm-trusted-firmware-mediatek/Makefile b/package/boot/arm-trusted-firmware-mediatek/Makefile index 2098d0835f8..0d1ad8e98a2 100644 --- a/package/boot/arm-trusted-firmware-mediatek/Makefile +++ b/package/boot/arm-trusted-firmware-mediatek/Makefile @@ -1,6 +1,6 @@ # # Copyright (C) 2017 Hauke Mehrtens -# Copyright (C) 2021 Daniel Golle +# Copyright (C) 2021-2023 Daniel Golle # # This is free software, licensed under the GNU General Public License v2. # See /LICENSE for more information. @@ -13,9 +13,9 @@ PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=https://github.com/mtk-openwrt/arm-trusted-firmware.git -PKG_SOURCE_DATE:=2022-08-31 -PKG_SOURCE_VERSION:=7539348480af57c6d0db95aba6381f3ee7483779 -PKG_MIRROR_HASH:=125090124d77753acc379b3b124100978c1ecb3da37c4983ba9644b433b7eb08 +PKG_SOURCE_DATE:=2023-07-24 +PKG_SOURCE_VERSION:=00ac6db375b76e57e1f5e9e9bffa033e907c3581 +PKG_MIRROR_HASH:=35e84b2160a7ddc083439e469d7366bb4e6098fc43b5616e68f001364eb05835 PKG_MAINTAINER:=Daniel Golle @@ -31,6 +31,7 @@ define Trusted-Firmware-A/Default DDR_TYPE:= NAND_TYPE:= BOARD_QFN:= + DRAM_USE_COMB:= endef define Trusted-Firmware-A/mt7622-nor-1ddr @@ -214,6 +215,126 @@ define Trusted-Firmware-A/mt7986-spim-nand-ddr3 DDR_TYPE:=ddr3 endef +define Trusted-Firmware-A/mt7988-nor-ddr3 + NAME:=MediaTek MT7988 (SPI-NOR, DDR3) + BOOT_DEVICE:=nor + BUILD_SUBTARGET:=filogic + PLAT:=mt7988 + DDR_TYPE:=ddr3 +endef + +define Trusted-Firmware-A/mt7988-emmc-ddr3 + NAME:=MediaTek MT7988 (eMMC, DDR3) + BOOT_DEVICE:=emmc + BUILD_SUBTARGET:=filogic + PLAT:=mt7988 + DDR_TYPE:=ddr3 +endef + +define Trusted-Firmware-A/mt7988-sdmmc-ddr3 + NAME:=MediaTek MT7988 (SD card, DDR3) + BOOT_DEVICE:=sdmmc + BUILD_SUBTARGET:=filogic + PLAT:=mt7988 + DDR_TYPE:=ddr3 +endef + +define Trusted-Firmware-A/mt7988-snand-ddr3 + NAME:=MediaTek MT7988 (SPI-NAND via SNFI, DDR3) + BOOT_DEVICE:=snand + BUILD_SUBTARGET:=filogic + PLAT:=mt7988 + DDR_TYPE:=ddr3 +endef + +define Trusted-Firmware-A/mt7988-spim-nand-ddr3 + NAME:=MediaTek MT7988 (SPI-NAND via SPIM, DDR3) + BOOT_DEVICE:=spim-nand + BUILD_SUBTARGET:=filogic + PLAT:=mt7988 + DDR_TYPE:=ddr3 +endef + +define Trusted-Firmware-A/mt7988-nor-ddr4 + NAME:=MediaTek MT7988 (SPI-NOR, DDR4) + BOOT_DEVICE:=nor + BUILD_SUBTARGET:=filogic + PLAT:=mt7988 + DDR_TYPE:=ddr4 +endef + +define Trusted-Firmware-A/mt7988-emmc-ddr4 + NAME:=MediaTek MT7988 (eMMC, DDR4) + BOOT_DEVICE:=emmc + BUILD_SUBTARGET:=filogic + PLAT:=mt7988 + DDR_TYPE:=ddr4 +endef + +define Trusted-Firmware-A/mt7988-sdmmc-ddr4 + NAME:=MediaTek MT7988 (SD card, DDR4) + BOOT_DEVICE:=sdmmc + BUILD_SUBTARGET:=filogic + PLAT:=mt7988 + DDR_TYPE:=ddr4 +endef + +define Trusted-Firmware-A/mt7988-snand-ddr4 + NAME:=MediaTek MT7988 (SPI-NAND via SNFI, DDR4) + BOOT_DEVICE:=snand + BUILD_SUBTARGET:=filogic + PLAT:=mt7988 + DDR_TYPE:=ddr4 +endef + +define Trusted-Firmware-A/mt7988-spim-nand-ddr4 + NAME:=MediaTek MT7988 (SPI-NAND via SPIM, DDR4) + BOOT_DEVICE:=spim-nand + BUILD_SUBTARGET:=filogic + PLAT:=mt7988 + DDR_TYPE:=ddr4 +endef + +define Trusted-Firmware-A/mt7988-nor-comb + NAME:=MediaTek MT7988 (SPI-NOR) + BOOT_DEVICE:=nor + BUILD_SUBTARGET:=filogic + PLAT:=mt7988 + DRAM_USE_COMB:=1 +endef + +define Trusted-Firmware-A/mt7988-emmc-comb + NAME:=MediaTek MT7988 (eMMC) + BOOT_DEVICE:=emmc + BUILD_SUBTARGET:=filogic + PLAT:=mt7988 + DRAM_USE_COMB:=1 +endef + +define Trusted-Firmware-A/mt7988-sdmmc-comb + NAME:=MediaTek MT7988 (SD card) + BOOT_DEVICE:=sdmmc + BUILD_SUBTARGET:=filogic + PLAT:=mt7988 + DRAM_USE_COMB:=1 +endef + +define Trusted-Firmware-A/mt7988-snand-comb + NAME:=MediaTek MT7988 (SPI-NAND via SNFI) + BOOT_DEVICE:=snand + BUILD_SUBTARGET:=filogic + PLAT:=mt7988 + DRAM_USE_COMB:=1 +endef + +define Trusted-Firmware-A/mt7988-spim-nand-comb + NAME:=MediaTek MT7988 (SPI-NAND via SPIM) + BOOT_DEVICE:=spim-nand + BUILD_SUBTARGET:=filogic + PLAT:=mt7988 + DRAM_USE_COMB:=1 +endef + TFA_TARGETS:= \ mt7622-nor-1ddr \ mt7622-nor-2ddr \ @@ -237,7 +358,22 @@ TFA_TARGETS:= \ mt7986-nor-ddr4 \ mt7986-sdmmc-ddr4 \ mt7986-snand-ddr4 \ - mt7986-spim-nand-ddr4 + mt7986-spim-nand-ddr4 \ + mt7988-emmc-ddr3 \ + mt7988-nor-ddr3 \ + mt7988-sdmmc-ddr3 \ + mt7988-snand-ddr3 \ + mt7988-spim-nand-ddr3 \ + mt7988-emmc-ddr4 \ + mt7988-nor-ddr4 \ + mt7988-sdmmc-ddr4 \ + mt7988-snand-ddr4 \ + mt7988-spim-nand-ddr4 \ + mt7988-emmc-comb \ + mt7988-nor-comb \ + mt7988-sdmmc-comb \ + mt7988-snand-comb \ + mt7988-spim-nand-comb TFA_MAKE_FLAGS += \ BOOT_DEVICE=$(BOOT_DEVICE) \ @@ -247,6 +383,7 @@ TFA_MAKE_FLAGS += \ $(if $(NAND_TYPE),NAND_TYPE=$(NAND_TYPE)) \ HAVE_DRAM_OBJ_FILE=yes \ $(if $(DDR3_FLYBY),DDR3_FLYBY=1) \ + $(if $(DRAM_USE_COMB),DRAM_USE_COMB=1) \ all define Package/trusted-firmware-a/install diff --git a/package/boot/arm-trusted-firmware-tools/Makefile b/package/boot/arm-trusted-firmware-tools/Makefile index 81c8a99cbc2..209e945a0b0 100644 --- a/package/boot/arm-trusted-firmware-tools/Makefile +++ b/package/boot/arm-trusted-firmware-tools/Makefile @@ -8,9 +8,9 @@ include $(TOPDIR)/rules.mk PKG_NAME:=arm-trusted-firmware-tools -PKG_VERSION:=2.7 +PKG_VERSION:=2.9 PKG_RELEASE:=1 -PKG_HASH:=53422dc649153838e03820330ba17cb10afe3e330ecde0db11e4d5f1361a33e6 +PKG_HASH:=76a66a1de0c01aeb83dfc7b72b51173fe62c6e51d6fca17cc562393117bed08b PKG_MAINTAINER:=Daniel Golle PKG_HOST_ONLY:=1 diff --git a/package/boot/uboot-envtools/files/mediatek_filogic b/package/boot/uboot-envtools/files/mediatek_filogic index 77c9d964db3..4fb1af82183 100644 --- a/package/boot/uboot-envtools/files/mediatek_filogic +++ b/package/boot/uboot-envtools/files/mediatek_filogic @@ -47,6 +47,8 @@ mercusys,mr90x-v1) netgear,wax220) ubootenv_add_uci_config "/dev/mtd5" "0x0" "0x20000" "0x20000" ;; +xiaomi,mi-router-wr30u-112m-nmbm|\ +xiaomi,mi-router-wr30u-stock|\ xiaomi,redmi-router-ax6000-stock) ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x10000" "0x20000" ubootenv_add_uci_sys_config "/dev/mtd2" "0x0" "0x10000" "0x20000" @@ -56,6 +58,7 @@ qihoo,360t7|\ tplink,tl-xdr4288|\ tplink,tl-xdr6086|\ tplink,tl-xdr6088|\ +xiaomi,mi-router-wr30u-ubootmod|\ xiaomi,redmi-router-ax6000-ubootmod) . /lib/upgrade/nand.sh local envubi=$(nand_find_ubi ubi) diff --git a/package/boot/uboot-mediatek/Makefile b/package/boot/uboot-mediatek/Makefile index 33fd7e086e8..a5401860c2b 100644 --- a/package/boot/uboot-mediatek/Makefile +++ b/package/boot/uboot-mediatek/Makefile @@ -1,8 +1,8 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk -PKG_VERSION:=2023.04 -PKG_HASH:=e31cac91545ff41b71cec5d8c22afd695645cd6e2a442ccdacacd60534069341 +PKG_VERSION:=2023.07.02 +PKG_HASH:=6b6a48581c14abb0f95bd87c1af4d740922406d7b801002a9f94727fdde021d5 PKG_BUILD_DEPENDS:=!(TARGET_ramips||TARGET_mediatek_mt7623):arm-trusted-firmware-tools/host include $(INCLUDE_DIR)/u-boot.mk @@ -200,6 +200,18 @@ define U-Boot/mt7981_qihoo_360t7 DEPENDS:=+trusted-firmware-a-mt7981-spim-nand-ddr3 endef +define U-Boot/mt7981_xiaomi_mi-router-wr30u + NAME:=Xiaomi Router WR30U + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=xiaomi_mi-router-wr30u-ubootmod + UBOOT_CONFIG:=mt7981_xiaomi_mi-router-wr30u + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=spim-nand + BL2_SOC:=mt7981 + BL2_DDRTYPE:=ddr3 + DEPENDS:=+trusted-firmware-a-mt7981-spim-nand-ddr3 +endef + define U-Boot/mt7986_rfb NAME:=MT7986 Reference Board BUILD_SUBTARGET:=filogic @@ -309,6 +321,66 @@ define U-Boot/mt7986_xiaomi_redmi-router-ax6000 DEPENDS:=+trusted-firmware-a-mt7986-spim-nand-ddr4 endef +define U-Boot/mt7988_rfb-spim-nand + NAME:=MT7988 Reference Board + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=mediatek_mt7988a-rfb-nand + UBOOT_CONFIG:=mt7988_rfb + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=spim-nand + BL2_SOC:=mt7988 + BL2_DDRTYPE:=ddr4 + DEPENDS:=+trusted-firmware-a-mt7988-spim-nand-ddr4 +endef + +define U-Boot/mt7988_rfb-snand + NAME:=MT7988 Reference Board + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=mediatek_mt7988a-rfb-nand + UBOOT_CONFIG:=mt7988_rfb + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=snand + BL2_SOC:=mt7988 + BL2_DDRTYPE:=ddr4 + DEPENDS:=+trusted-firmware-a-mt7988-snand-ddr4 +endef + +define U-Boot/mt7988_rfb-nor + NAME:=MT7988 Reference Board + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=mediatek_mt7988a-rfb-nand + UBOOT_CONFIG:=mt7988_rfb + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=nor + BL2_SOC:=mt7988 + BL2_DDRTYPE:=ddr4 + DEPENDS:=+trusted-firmware-a-mt7988-nor-ddr4 +endef + +define U-Boot/mt7988_rfb-emmc + NAME:=MT7988 Reference Board + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=mediatek_mt7988a-rfb-nand + UBOOT_CONFIG:=mt7988_rfb + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=emmc + BL2_SOC:=mt7988 + BL2_DDRTYPE:=ddr4 + DEPENDS:=+trusted-firmware-a-mt7988-emmc-ddr4 +endef + +define U-Boot/mt7988_rfb-sd + NAME:=MT7988 Reference Board + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=mediatek_mt7988a-rfb-nand + UBOOT_CONFIG:=mt7988_sd_rfb + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=sdmmc + BL2_SOC:=mt7988 + BL2_DDRTYPE:=ddr4 + DEPENDS:=+trusted-firmware-a-mt7988-sdmmc-ddr4 +endef + UBOOT_TARGETS := \ mt7620_mt7530_rfb \ mt7620_rfb \ @@ -327,6 +399,7 @@ UBOOT_TARGETS := \ mt7629_rfb \ mt7981_h3c_magic-nx30-pro \ mt7981_qihoo_360t7 \ + mt7981_xiaomi_mi-router-wr30u \ mt7986_bananapi_bpi-r3-emmc \ mt7986_bananapi_bpi-r3-sdmmc \ mt7986_bananapi_bpi-r3-snand \ @@ -335,7 +408,12 @@ UBOOT_TARGETS := \ mt7986_tplink_tl-xdr6086 \ mt7986_tplink_tl-xdr6088 \ mt7986_xiaomi_redmi-router-ax6000 \ - mt7986_rfb + mt7986_rfb \ + mt7988_rfb-spim-nand \ + mt7988_rfb-snand \ + mt7988_rfb-nor \ + mt7988_rfb-emmc \ + mt7988_rfb-sd ifdef CONFIG_TARGET_mediatek UBOOT_MAKE_FLAGS += $(UBOOT_IMAGE:.fip=.bin) diff --git a/package/boot/uboot-mediatek/patches/000-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch b/package/boot/uboot-mediatek/patches/000-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch index cd9004844c0..60eda91124b 100644 --- a/package/boot/uboot-mediatek/patches/000-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch +++ b/package/boot/uboot-mediatek/patches/000-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch @@ -21,7 +21,7 @@ Signed-off-by: Weijie Gao CONFIG_SYS_PROMPT="MT7622> " CONFIG_DEBUG_UART_BASE=0x11002000 CONFIG_DEBUG_UART_CLOCK=25000000 -@@ -24,6 +26,9 @@ CONFIG_CMD_SF_TEST=y +@@ -25,6 +27,9 @@ CONFIG_CMD_SF_TEST=y CONFIG_CMD_PING=y CONFIG_CMD_SMC=y CONFIG_ENV_OVERWRITE=y diff --git a/package/boot/uboot-mediatek/patches/001-pinctrl-mediatek-set-R1-R0-in-case-pullen-pullsel-su.patch b/package/boot/uboot-mediatek/patches/001-pinctrl-mediatek-set-R1-R0-in-case-pullen-pullsel-su.patch deleted file mode 100644 index 988c78cdfb8..00000000000 --- a/package/boot/uboot-mediatek/patches/001-pinctrl-mediatek-set-R1-R0-in-case-pullen-pullsel-su.patch +++ /dev/null @@ -1,88 +0,0 @@ -From patchwork Wed Apr 12 20:36:43 2023 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Daniel Golle -X-Patchwork-Id: 1768270 -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@legolas.ozlabs.org -Date: Wed, 12 Apr 2023 21:36:43 +0100 -From: Daniel Golle -To: u-boot@lists.denx.de, Sam Shih , - GSS_MTK_Uboot_upstream , - Chunfeng Yun , - Weijie Gao , Ryder Lee , - Frank Wunderlich -Cc: Steven Liu =?utf-8?b?KOWKieS6uuixqik=?= , - John Crispin -Subject: [PATCH] pinctrl: mediatek: set R1/R0 in case pullen/pullsel succeeded -Message-ID: -MIME-Version: 1.0 -Content-Disposition: inline -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -Sender: "U-Boot" - -Commit dafe0fbfb0f3 ("pinctrl: mediatek: rewrite mtk_pinconf_set and -related functions") changed the logic deciding to set R0 and R1 -registers for V1 devices. - -Before: - /* Also set PUPD/R0/R1 if the pin has them */ - err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PUPD, !pullup); - if (err != -EINVAL) { - mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R0, r0); - mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R1, r1); - } - -After: - /* try pupd_r1_r0 if pullen_pullsel return error */ - err = mtk_pinconf_bias_set_pullen_pullsel(dev, pin, disable, pullup, - val); - if (err) - return mtk_pinconf_bias_set_pupd_r1_r0(dev, pin, disable, - pullup, val); - -Tracing mtk_pinconf_bias_set_pullen_pullsel shows that the function -always either returns 0 in case of success or -EINVAL in case any error -has occurred. Hence the logic responsible of the decision to program R0 -and R1 has been inverted. - -This leads to problems on BananaPi R2 (MT7623N) when booting from -SDMMC, it turns out accessing eMMC no longer works since -U-Boot 2022.07: - -MT7623> mmc dev 0 -Card did not respond to voltage select! : -110 - -The problem wasn't detected for a long time as both eMMC and SDMMC work -fine if they are used to boot from, and hence R0 and R1 were already -setup by the bootrom and/or preloader. - -Fix the logic to restore the originally intended and correct behavior -and also change the descriptive comment accordingly. - -Fixes: dafe0fbfb0f3 ("pinctrl: mediatek: rewrite mtk_pinconf_set and related functions") -Signed-off-by: Daniel Golle ---- - drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c -@@ -349,10 +349,10 @@ int mtk_pinconf_bias_set_v1(struct udevi - { - int err; - -- /* try pupd_r1_r0 if pullen_pullsel return error */ -+ /* set pupd_r1_r0 if pullen_pullsel succeeded */ - err = mtk_pinconf_bias_set_pullen_pullsel(dev, pin, disable, pullup, - val); -- if (err) -+ if (!err) - return mtk_pinconf_bias_set_pupd_r1_r0(dev, pin, disable, - pullup, val); - diff --git a/package/boot/uboot-mediatek/patches/100-02-drivers-mtd-add-support-for-MediaTek-SPI-NAND-flash-.patch b/package/boot/uboot-mediatek/patches/100-02-drivers-mtd-add-support-for-MediaTek-SPI-NAND-flash-.patch index a6c59d1f666..311c0513440 100644 --- a/package/boot/uboot-mediatek/patches/100-02-drivers-mtd-add-support-for-MediaTek-SPI-NAND-flash-.patch +++ b/package/boot/uboot-mediatek/patches/100-02-drivers-mtd-add-support-for-MediaTek-SPI-NAND-flash-.patch @@ -49,7 +49,7 @@ Signed-off-by: Weijie Gao config SYS_NAND_MAX_OOBFREE --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile -@@ -38,3 +38,5 @@ obj-$(CONFIG_$(SPL_TPL_)SPI_FLASH_SUPPOR +@@ -39,3 +39,5 @@ obj-$(CONFIG_$(SPL_TPL_)SPI_FLASH_SUPPOR obj-$(CONFIG_SPL_UBI) += ubispl/ endif diff --git a/package/boot/uboot-mediatek/patches/100-06-mtd-add-core-facility-code-of-NMBM.patch b/package/boot/uboot-mediatek/patches/100-06-mtd-add-core-facility-code-of-NMBM.patch index bf04f5b6e49..23634e64253 100644 --- a/package/boot/uboot-mediatek/patches/100-06-mtd-add-core-facility-code-of-NMBM.patch +++ b/package/boot/uboot-mediatek/patches/100-06-mtd-add-core-facility-code-of-NMBM.patch @@ -31,16 +31,16 @@ Signed-off-by: Weijie Gao --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig -@@ -272,4 +272,6 @@ source "drivers/mtd/spi/Kconfig" +@@ -274,4 +274,6 @@ source "drivers/mtd/ubi/Kconfig" - source "drivers/mtd/ubi/Kconfig" + source "drivers/mtd/nvmxip/Kconfig" +source "drivers/mtd/nmbm/Kconfig" + endmenu --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile -@@ -40,3 +40,4 @@ obj-$(CONFIG_SPL_UBI) += ubispl/ +@@ -41,3 +41,4 @@ obj-$(CONFIG_SPL_UBI) += ubispl/ endif obj-$(CONFIG_MTK_SPI_NAND) += mtk-snand/ diff --git a/package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch b/package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch index 1d8139e6726..93fc32cf9ec 100644 --- a/package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch +++ b/package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch @@ -34,7 +34,7 @@ Signed-off-by: Weijie Gao #if defined(CONFIG_CMD_ONENAND) /* go init the NAND */ static int initr_onenand(void) -@@ -703,6 +717,9 @@ static init_fnc_t init_sequence_r[] = { +@@ -696,6 +710,9 @@ static init_fnc_t init_sequence_r[] = { #ifdef CONFIG_CMD_ONENAND initr_onenand, #endif diff --git a/package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch b/package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch index 6b319384d51..35d8f115f60 100644 --- a/package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch +++ b/package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch @@ -15,7 +15,7 @@ Signed-off-by: Weijie Gao --- a/cmd/Kconfig +++ b/cmd/Kconfig -@@ -1352,6 +1352,12 @@ config CMD_NAND_TORTURE +@@ -1353,6 +1353,12 @@ config CMD_NAND_TORTURE endif # CMD_NAND @@ -30,7 +30,7 @@ Signed-off-by: Weijie Gao depends on NVME --- a/cmd/Makefile +++ b/cmd/Makefile -@@ -123,6 +123,7 @@ obj-y += legacy-mtd-utils.o +@@ -125,6 +125,7 @@ obj-y += legacy-mtd-utils.o endif obj-$(CONFIG_CMD_MUX) += mux.o obj-$(CONFIG_CMD_NAND) += nand.o diff --git a/package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch b/package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch index 31f26be0536..f3831e07f7d 100644 --- a/package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch +++ b/package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch @@ -26,7 +26,7 @@ Signed-off-by: Weijie Gao --- a/cmd/Kconfig +++ b/cmd/Kconfig -@@ -1352,6 +1352,14 @@ config CMD_NAND_TORTURE +@@ -1353,6 +1353,14 @@ config CMD_NAND_TORTURE endif # CMD_NAND @@ -43,7 +43,7 @@ Signed-off-by: Weijie Gao bool "nmbm" --- a/cmd/Makefile +++ b/cmd/Makefile -@@ -123,6 +123,7 @@ obj-y += legacy-mtd-utils.o +@@ -125,6 +125,7 @@ obj-y += legacy-mtd-utils.o endif obj-$(CONFIG_CMD_MUX) += mux.o obj-$(CONFIG_CMD_NAND) += nand.o diff --git a/package/boot/uboot-mediatek/patches/100-14-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch b/package/boot/uboot-mediatek/patches/100-14-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch index 3d79731dd14..d9a645d20ef 100644 --- a/package/boot/uboot-mediatek/patches/100-14-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch +++ b/package/boot/uboot-mediatek/patches/100-14-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch @@ -13,7 +13,7 @@ Signed-off-by: Weijie Gao --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c -@@ -2818,6 +2818,100 @@ static int spi_nor_init_params(struct sp +@@ -2848,6 +2848,100 @@ static int spi_nor_init_params(struct sp return 0; } @@ -114,7 +114,7 @@ Signed-off-by: Weijie Gao static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size) { size_t i; -@@ -3930,6 +4024,7 @@ int spi_nor_scan(struct spi_nor *nor) +@@ -4045,6 +4139,7 @@ int spi_nor_scan(struct spi_nor *nor) nor->write = spi_nor_write_data; nor->read_reg = spi_nor_read_reg; nor->write_reg = spi_nor_write_reg; diff --git a/package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch b/package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch index 797d925e173..93a940b943f 100644 --- a/package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch +++ b/package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch @@ -23,7 +23,7 @@ Signed-off-by: Weijie Gao +++ b/arch/arm/dts/mt7629-rfb-u-boot.dtsi @@ -40,3 +40,11 @@ &snfi { - u-boot,dm-pre-reloc; + bootph-all; }; + +&pinctrl { diff --git a/package/boot/uboot-mediatek/patches/100-19-board-mt7622-use-new-spi-nand-driver.patch b/package/boot/uboot-mediatek/patches/100-19-board-mt7622-use-new-spi-nand-driver.patch index 03555d4a4b7..6202ddf3b01 100644 --- a/package/boot/uboot-mediatek/patches/100-19-board-mt7622-use-new-spi-nand-driver.patch +++ b/package/boot/uboot-mediatek/patches/100-19-board-mt7622-use-new-spi-nand-driver.patch @@ -55,7 +55,7 @@ Signed-off-by: Weijie Gao reg = <0x11014000 0x1000>; --- a/configs/mt7622_rfb_defconfig +++ b/configs/mt7622_rfb_defconfig -@@ -21,6 +21,7 @@ CONFIG_SYS_MAXARGS=8 +@@ -22,6 +22,7 @@ CONFIG_SYS_MAXARGS=8 CONFIG_SYS_PBSIZE=1049 CONFIG_CMD_BOOTMENU=y CONFIG_CMD_MMC=y @@ -63,7 +63,7 @@ Signed-off-by: Weijie Gao CONFIG_CMD_PCI=y CONFIG_CMD_SF_TEST=y CONFIG_CMD_PING=y -@@ -40,6 +41,10 @@ CONFIG_SYSCON=y +@@ -41,6 +42,10 @@ CONFIG_SYSCON=y CONFIG_CLK=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_MMC_MTK=y diff --git a/package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch b/package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch index cf2019fcba6..cb3f1ff2af5 100644 --- a/package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch +++ b/package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch @@ -18,14 +18,14 @@ Signed-off-by: Weijie Gao --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -1288,6 +1288,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ +@@ -1308,6 +1308,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7623n-bananapi-bpi-r2.dtb \ mt7629-rfb.dtb \ mt7981-rfb.dtb \ + mt7981-snfi-nand-rfb.dtb \ mt7981-emmc-rfb.dtb \ mt7981-sd-rfb.dtb \ - mt7986a-rfb.dtb \ + mt7986a-bpi-r3-sd.dtb \ --- /dev/null +++ b/arch/arm/dts/mt7981-snfi-nand-rfb.dts @@ -0,0 +1,132 @@ diff --git a/package/boot/uboot-mediatek/patches/100-21-mtd-spi-nor-add-more-flash-ids.patch b/package/boot/uboot-mediatek/patches/100-21-mtd-spi-nor-add-more-flash-ids.patch index 08334248218..bd68677eb06 100644 --- a/package/boot/uboot-mediatek/patches/100-21-mtd-spi-nor-add-more-flash-ids.patch +++ b/package/boot/uboot-mediatek/patches/100-21-mtd-spi-nor-add-more-flash-ids.patch @@ -13,7 +13,7 @@ Signed-off-by: Weijie Gao --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c -@@ -672,6 +672,7 @@ static int set_4byte(struct spi_nor *nor +@@ -673,6 +673,7 @@ static int set_4byte(struct spi_nor *nor case SNOR_MFR_ISSI: case SNOR_MFR_MACRONIX: case SNOR_MFR_WINBOND: diff --git a/package/boot/uboot-mediatek/patches/100-22-mtd-spi-nand-backport-from-upstream-kernel.patch b/package/boot/uboot-mediatek/patches/100-22-mtd-spi-nand-backport-from-upstream-kernel.patch index 1c83479d0db..358461a2b70 100644 --- a/package/boot/uboot-mediatek/patches/100-22-mtd-spi-nand-backport-from-upstream-kernel.patch +++ b/package/boot/uboot-mediatek/patches/100-22-mtd-spi-nand-backport-from-upstream-kernel.patch @@ -207,8 +207,8 @@ Signed-off-by: Weijie Gao - ret = spinand_manufacturer_detect(spinand); + ret = spinand_id_detect(spinand); if (ret) { - dev_err(spinand->slave->dev, "unknown raw ID %*phN\n", - SPINAND_MAX_ID_LEN, spinand->id.data); + dev_err(spinand->slave->dev, "unknown raw ID %02x %02x %02x %02x\n", + spinand->id.data[0], spinand->id.data[1], --- a/drivers/mtd/nand/spi/gigadevice.c +++ b/drivers/mtd/nand/spi/gigadevice.c @@ -22,8 +22,13 @@ diff --git a/package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch b/package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch index 1709680ebbc..0c68f429c6b 100644 --- a/package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch +++ b/package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch @@ -15,7 +15,7 @@ Signed-off-by: Weijie Gao --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig -@@ -823,6 +823,14 @@ config MMC_MTK +@@ -820,6 +820,14 @@ config MMC_MTK This is needed if support for any SD/SDIO/MMC devices is required. If unsure, say N. @@ -32,7 +32,7 @@ Signed-off-by: Weijie Gao config FSL_SDHC_V2_3 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile -@@ -84,3 +84,7 @@ obj-$(CONFIG_RENESAS_SDHI) += tmio-comm +@@ -83,3 +83,7 @@ obj-$(CONFIG_RENESAS_SDHI) += tmio-comm obj-$(CONFIG_MMC_BCM2835) += bcm2835_sdhost.o obj-$(CONFIG_MMC_MTK) += mtk-sd.o obj-$(CONFIG_MMC_SDHCI_F_SDH30) += f_sdh30.o diff --git a/package/boot/uboot-mediatek/patches/101-01-arm-mediatek-retrieve-ram_base-from-dts-node-for-arm.patch b/package/boot/uboot-mediatek/patches/101-01-arm-mediatek-retrieve-ram_base-from-dts-node-for-arm.patch new file mode 100644 index 00000000000..645b7801c8b --- /dev/null +++ b/package/boot/uboot-mediatek/patches/101-01-arm-mediatek-retrieve-ram_base-from-dts-node-for-arm.patch @@ -0,0 +1,297 @@ +From 63336ec7fd7d480ac58a91f3b20d08bf1b3a13ad Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 19 Jul 2023 17:15:41 +0800 +Subject: [PATCH 01/29] arm: mediatek: retrieve ram_base from dts node for + armv8 platform + +Now we use fdtdec_setup_mem_size_base() to get DRAM base from fdt ram node +and update gd->ram_base. CFG_SYS_SDRAM_BASE is unused and will be removed. + +Also, since mt7622 always passes fdt to linux kernel, there's no need to +assign value to gd->bd->bi_boot_params. + +Signed-off-by: Weijie Gao +--- + arch/arm/dts/mt7981-emmc-rfb.dts | 5 +++++ + arch/arm/dts/mt7981-rfb.dts | 5 +++++ + arch/arm/dts/mt7981-sd-rfb.dts | 5 +++++ + arch/arm/dts/mt7986a-bpi-r3-sd.dts | 5 +++++ + arch/arm/dts/mt7986a-rfb.dts | 5 +++++ + arch/arm/dts/mt7986a-sd-rfb.dts | 5 +++++ + arch/arm/dts/mt7986b-rfb.dts | 5 +++++ + arch/arm/dts/mt7986b-sd-rfb.dts | 5 +++++ + arch/arm/mach-mediatek/mt7622/init.c | 13 +++++++++---- + arch/arm/mach-mediatek/mt7981/init.c | 11 +++++++++-- + arch/arm/mach-mediatek/mt7986/init.c | 11 +++++++++-- + board/mediatek/mt7622/mt7622_rfb.c | 1 - + include/configs/mt7622.h | 10 ---------- + include/configs/mt7981.h | 9 --------- + include/configs/mt7986.h | 9 --------- + 15 files changed, 67 insertions(+), 37 deletions(-) + +--- a/arch/arm/dts/mt7981-emmc-rfb.dts ++++ b/arch/arm/dts/mt7981-emmc-rfb.dts +@@ -18,6 +18,11 @@ + tick-timer = &timer0; + }; + ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0x40000000 0x10000000>; ++ }; ++ + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; +--- a/arch/arm/dts/mt7981-rfb.dts ++++ b/arch/arm/dts/mt7981-rfb.dts +@@ -17,6 +17,11 @@ + stdout-path = &uart0; + tick-timer = &timer0; + }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0x40000000 0x10000000>; ++ }; + }; + + &uart0 { +--- a/arch/arm/dts/mt7981-sd-rfb.dts ++++ b/arch/arm/dts/mt7981-sd-rfb.dts +@@ -18,6 +18,11 @@ + tick-timer = &timer0; + }; + ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0x40000000 0x10000000>; ++ }; ++ + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; +--- a/arch/arm/dts/mt7986a-bpi-r3-sd.dts ++++ b/arch/arm/dts/mt7986a-bpi-r3-sd.dts +@@ -19,6 +19,11 @@ + tick-timer = &timer0; + }; + ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0x40000000 0x80000000>; ++ }; ++ + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; +--- a/arch/arm/dts/mt7986a-rfb.dts ++++ b/arch/arm/dts/mt7986a-rfb.dts +@@ -18,6 +18,11 @@ + tick-timer = &timer0; + }; + ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0x40000000 0x10000000>; ++ }; ++ + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; +--- a/arch/arm/dts/mt7986a-sd-rfb.dts ++++ b/arch/arm/dts/mt7986a-sd-rfb.dts +@@ -19,6 +19,11 @@ + tick-timer = &timer0; + }; + ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0x40000000 0x10000000>; ++ }; ++ + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; +--- a/arch/arm/dts/mt7986b-rfb.dts ++++ b/arch/arm/dts/mt7986b-rfb.dts +@@ -18,6 +18,11 @@ + tick-timer = &timer0; + }; + ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0x40000000 0x10000000>; ++ }; ++ + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; +--- a/arch/arm/dts/mt7986b-sd-rfb.dts ++++ b/arch/arm/dts/mt7986b-sd-rfb.dts +@@ -19,6 +19,11 @@ + tick-timer = &timer0; + }; + ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0x40000000 0x10000000>; ++ }; ++ + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; +--- a/arch/arm/mach-mediatek/mt7622/init.c ++++ b/arch/arm/mach-mediatek/mt7622/init.c +@@ -4,11 +4,14 @@ + * Author: Sam Shih + */ + +-#include + #include + #include + #include +-#include ++#include ++#include ++#include ++ ++DECLARE_GLOBAL_DATA_PTR; + + int print_cpuinfo(void) + { +@@ -20,11 +23,13 @@ int dram_init(void) + { + int ret; + +- ret = fdtdec_setup_memory_banksize(); ++ ret = fdtdec_setup_mem_size_base(); + if (ret) + return ret; +- return fdtdec_setup_mem_size_base(); + ++ gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_2G); ++ ++ return 0; + } + + void reset_cpu(void) +--- a/arch/arm/mach-mediatek/mt7981/init.c ++++ b/arch/arm/mach-mediatek/mt7981/init.c +@@ -4,18 +4,25 @@ + * Author: Sam Shih + */ + +-#include ++#include + #include + #include + #include + #include ++#include + #include + + DECLARE_GLOBAL_DATA_PTR; + + int dram_init(void) + { +- gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G); ++ int ret; ++ ++ ret = fdtdec_setup_mem_size_base(); ++ if (ret) ++ return ret; ++ ++ gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_1G); + + return 0; + } +--- a/arch/arm/mach-mediatek/mt7986/init.c ++++ b/arch/arm/mach-mediatek/mt7986/init.c +@@ -4,18 +4,25 @@ + * Author: Sam Shih + */ + +-#include ++#include + #include + #include + #include + #include ++#include + #include + + DECLARE_GLOBAL_DATA_PTR; + + int dram_init(void) + { +- gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G); ++ int ret; ++ ++ ret = fdtdec_setup_mem_size_base(); ++ if (ret) ++ return ret; ++ ++ gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_2G); + + return 0; + } +--- a/board/mediatek/mt7622/mt7622_rfb.c ++++ b/board/mediatek/mt7622/mt7622_rfb.c +@@ -19,7 +19,6 @@ DECLARE_GLOBAL_DATA_PTR; + + int board_init(void) + { +- gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; + return 0; + } + +--- a/include/configs/mt7622.h ++++ b/include/configs/mt7622.h +@@ -9,14 +9,4 @@ + #ifndef __MT7622_H + #define __MT7622_H + +-/* Uboot definition */ +-#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +- +-/* SPL -> Uboot */ +-#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE +-/* DRAM */ +-#define CFG_SYS_SDRAM_BASE 0x40000000 +- +-/* Ethernet */ +- + #endif +--- a/include/configs/mt7981.h ++++ b/include/configs/mt7981.h +@@ -9,13 +9,4 @@ + #ifndef __MT7981_H + #define __MT7981_H + +-/* Uboot definition */ +-#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +- +-/* SPL -> Uboot */ +-#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE +- +-/* DRAM */ +-#define CFG_SYS_SDRAM_BASE 0x40000000 +- + #endif +--- a/include/configs/mt7986.h ++++ b/include/configs/mt7986.h +@@ -9,13 +9,4 @@ + #ifndef __MT7986_H + #define __MT7986_H + +-/* Uboot definition */ +-#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +- +-/* SPL -> Uboot */ +-#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE +- +-/* DRAM */ +-#define CFG_SYS_SDRAM_BASE 0x40000000 +- + #endif diff --git a/package/boot/uboot-mediatek/patches/101-02-board-mediatek-update-config-headers.patch b/package/boot/uboot-mediatek/patches/101-02-board-mediatek-update-config-headers.patch new file mode 100644 index 00000000000..b64ee15171f --- /dev/null +++ b/package/boot/uboot-mediatek/patches/101-02-board-mediatek-update-config-headers.patch @@ -0,0 +1,129 @@ +From df3a0091b249ea82198ea019d145d05a7cf49c0d Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 19 Jul 2023 17:15:47 +0800 +Subject: [PATCH 02/29] board: mediatek: update config headers + +Remove unused information from include/configs/mtxxxx.h + +Signed-off-by: Weijie Gao +--- + include/configs/mt7620.h | 3 +-- + include/configs/mt7621.h | 6 ++---- + include/configs/mt7623.h | 8 -------- + include/configs/mt7628.h | 5 ++--- + include/configs/mt7629.h | 13 +------------ + 5 files changed, 6 insertions(+), 29 deletions(-) + +--- a/include/configs/mt7620.h ++++ b/include/configs/mt7620.h +@@ -10,10 +10,9 @@ + + #define CFG_SYS_SDRAM_BASE 0x80000000 + +-#define CFG_SYS_INIT_SP_OFFSET 0x400000 ++#define CFG_SYS_INIT_SP_OFFSET 0x400000 + + /* SPL */ +- + #define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE + + /* Dummy value */ +--- a/include/configs/mt7621.h ++++ b/include/configs/mt7621.h +@@ -12,13 +12,11 @@ + + #define CFG_MAX_MEM_MAPPED 0x1c000000 + +-#define CFG_SYS_INIT_SP_OFFSET 0x800000 ++#define CFG_SYS_INIT_SP_OFFSET 0x800000 + + /* MMC */ + #define MMC_SUPPORTS_TUNING + +-/* NAND */ +- + /* Serial SPL */ + #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) + #define CFG_SYS_NS16550_CLK 50000000 +@@ -26,7 +24,7 @@ + #endif + + /* Serial common */ +-#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ ++#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ + 230400, 460800, 921600 } + + /* Dummy value */ +--- a/include/configs/mt7623.h ++++ b/include/configs/mt7623.h +@@ -11,12 +11,6 @@ + + #include + +-/* Miscellaneous configurable options */ +- +-/* Environment */ +- +-/* Preloader -> Uboot */ +- + /* MMC */ + #define MMC_SUPPORTS_TUNING + +@@ -32,8 +26,6 @@ + "fdt_addr_r=" FDT_HIGH "\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" + +-/* Ethernet */ +- + #ifdef CONFIG_DISTRO_DEFAULTS + + #define BOOT_TARGET_DEVICES(func) \ +--- a/include/configs/mt7628.h ++++ b/include/configs/mt7628.h +@@ -10,7 +10,7 @@ + + #define CFG_SYS_SDRAM_BASE 0x80000000 + +-#define CFG_SYS_INIT_SP_OFFSET 0x80000 ++#define CFG_SYS_INIT_SP_OFFSET 0x80000 + + /* Serial SPL */ + #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) +@@ -19,11 +19,10 @@ + #endif + + /* Serial common */ +-#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ ++#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ + 230400, 460800, 921600 } + + /* SPL */ +- + #define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE + + /* Dummy value */ +--- a/include/configs/mt7629.h ++++ b/include/configs/mt7629.h +@@ -9,21 +9,10 @@ + #ifndef __MT7629_H + #define __MT7629_H + +-#include +- +-/* Miscellaneous configurable options */ +- +-/* Environment */ +- ++/* SPL */ + #define CFG_SYS_UBOOT_BASE (0x30000000 + CONFIG_SPL_PAD_TO) + +-/* SPL -> Uboot */ +- +-/* UBoot -> Kernel */ +- + /* DRAM */ + #define CFG_SYS_SDRAM_BASE 0x40000000 + +-/* Ethernet */ +- + #endif diff --git a/package/boot/uboot-mediatek/patches/101-03-spi-mtk_spim-get-spi-clk-rate-only-once.patch b/package/boot/uboot-mediatek/patches/101-03-spi-mtk_spim-get-spi-clk-rate-only-once.patch new file mode 100644 index 00000000000..323bb249332 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/101-03-spi-mtk_spim-get-spi-clk-rate-only-once.patch @@ -0,0 +1,84 @@ +From 0d6d8a408f80358dd47984320ea9c65e555ac4c9 Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 19 Jul 2023 17:15:54 +0800 +Subject: [PATCH 03/29] spi: mtk_spim: get spi clk rate only once + +We don't really need to switch clk rate during operating SPIM controller. +Get clk rate only once at driver probing. + +Signed-off-by: SkyLake.Huang +Signed-off-by: Weijie Gao +Reviewed-by: Jagan Teki +--- + drivers/spi/mtk_spim.c | 21 +++++++++++++-------- + 1 file changed, 13 insertions(+), 8 deletions(-) + +--- a/drivers/spi/mtk_spim.c ++++ b/drivers/spi/mtk_spim.c +@@ -137,6 +137,8 @@ struct mtk_spim_capability { + * @state: Controller state + * @sel_clk: Pad clock + * @spi_clk: Core clock ++ * @pll_clk_rate: Controller's PLL source clock rate, which is different ++ * from SPI bus clock rate + * @xfer_len: Current length of data for transfer + * @hw_cap: Controller capabilities + * @tick_dly: Used to postpone SPI sampling time +@@ -149,6 +151,7 @@ struct mtk_spim_priv { + void __iomem *base; + u32 state; + struct clk sel_clk, spi_clk; ++ u32 pll_clk_rate; + u32 xfer_len; + struct mtk_spim_capability hw_cap; + u32 tick_dly; +@@ -253,11 +256,10 @@ static int mtk_spim_hw_init(struct spi_s + static void mtk_spim_prepare_transfer(struct mtk_spim_priv *priv, + u32 speed_hz) + { +- u32 spi_clk_hz, div, sck_time, cs_time, reg_val; ++ u32 div, sck_time, cs_time, reg_val; + +- spi_clk_hz = clk_get_rate(&priv->spi_clk); +- if (speed_hz <= spi_clk_hz / 4) +- div = DIV_ROUND_UP(spi_clk_hz, speed_hz); ++ if (speed_hz <= priv->pll_clk_rate / 4) ++ div = DIV_ROUND_UP(priv->pll_clk_rate, speed_hz); + else + div = 4; + +@@ -404,7 +406,7 @@ static int mtk_spim_transfer_wait(struct + { + struct udevice *bus = dev_get_parent(slave->dev); + struct mtk_spim_priv *priv = dev_get_priv(bus); +- u32 sck_l, sck_h, spi_bus_clk, clk_count, reg; ++ u32 sck_l, sck_h, clk_count, reg; + ulong us = 1; + int ret = 0; + +@@ -413,12 +415,11 @@ static int mtk_spim_transfer_wait(struct + else + clk_count = op->data.nbytes; + +- spi_bus_clk = clk_get_rate(&priv->spi_clk); + sck_l = readl(priv->base + SPI_CFG2_REG) >> SPI_CFG2_SCK_LOW_OFFSET; + sck_h = readl(priv->base + SPI_CFG2_REG) & SPI_CFG2_SCK_HIGH_MASK; +- do_div(spi_bus_clk, sck_l + sck_h + 2); ++ do_div(priv->pll_clk_rate, sck_l + sck_h + 2); + +- us = CLK_TO_US(spi_bus_clk, clk_count * 8); ++ us = CLK_TO_US(priv->pll_clk_rate, clk_count * 8); + us += 1000 * 1000; /* 1s tolerance */ + + if (us > UINT_MAX) +@@ -662,6 +663,10 @@ static int mtk_spim_probe(struct udevice + clk_enable(&priv->sel_clk); + clk_enable(&priv->spi_clk); + ++ priv->pll_clk_rate = clk_get_rate(&priv->spi_clk); ++ if (priv->pll_clk_rate == 0) ++ return -EINVAL; ++ + return 0; + } + diff --git a/package/boot/uboot-mediatek/patches/101-04-spi-mtk_spim-clear-IRQ-enable-bits.patch b/package/boot/uboot-mediatek/patches/101-04-spi-mtk_spim-clear-IRQ-enable-bits.patch new file mode 100644 index 00000000000..e8577f63bf1 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/101-04-spi-mtk_spim-clear-IRQ-enable-bits.patch @@ -0,0 +1,35 @@ +From a7b630f02bb12f71f23866aee6f9a1a07497d475 Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 19 Jul 2023 17:16:02 +0800 +Subject: [PATCH 04/29] spi: mtk_spim: clear IRQ enable bits + +In u-boot we don't use IRQ. Instead, we poll busy bit in SPI_STATUS. + +However these IRQ enable bits may be set in previous boot stage (BootROM). + +If we leave these bits not cleared, although u-boot has disabled IRQ and +nothing will happen, the linux kernel may encounter panic during +initializing the spim driver due to IRQ event happens before IRQ handler +is properly setup. + +This patch clear IRQ bits to prevent this from happening. + +Signed-off-by: SkyLake.Huang +Signed-off-by: Weijie Gao +Reviewed-by: Jagan Teki +--- + drivers/spi/mtk_spim.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/spi/mtk_spim.c ++++ b/drivers/spi/mtk_spim.c +@@ -242,6 +242,9 @@ static int mtk_spim_hw_init(struct spi_s + reg_val &= ~SPI_CMD_SAMPLE_SEL; + } + ++ /* Disable interrupt enable for pause mode & normal mode */ ++ reg_val &= ~(SPI_CMD_PAUSE_IE | SPI_CMD_FINISH_IE); ++ + /* disable dma mode */ + reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA); + diff --git a/package/boot/uboot-mediatek/patches/101-05-serial-mtk-initial-priv-data-before-using.patch b/package/boot/uboot-mediatek/patches/101-05-serial-mtk-initial-priv-data-before-using.patch new file mode 100644 index 00000000000..6f805765c1f --- /dev/null +++ b/package/boot/uboot-mediatek/patches/101-05-serial-mtk-initial-priv-data-before-using.patch @@ -0,0 +1,25 @@ +From 73060da8b54e74c51ef6c1fd31c4fac6ad6b8d0e Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 19 Jul 2023 17:16:07 +0800 +Subject: [PATCH 05/29] serial: mtk: initial priv data before using + +This patch ensures driver private data being fully initialized in +_debug_uart_init which is not covered by .priv_auto ops. + +Signed-off-by: Sam Shih +Signed-off-by: Weijie Gao +Reviewed-by: Stefan Roese +--- + drivers/serial/serial_mtk.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/serial/serial_mtk.c ++++ b/drivers/serial/serial_mtk.c +@@ -439,6 +439,7 @@ static inline void _debug_uart_init(void + { + struct mtk_serial_priv priv; + ++ memset(&priv, 0, sizeof(struct mtk_serial_priv)); + priv.regs = (void *) CONFIG_VAL(DEBUG_UART_BASE); + priv.fixed_clk_rate = CONFIG_DEBUG_UART_CLOCK; + diff --git a/package/boot/uboot-mediatek/patches/101-06-reset-mediatek-check-malloc-return-valaue-before-use.patch b/package/boot/uboot-mediatek/patches/101-06-reset-mediatek-check-malloc-return-valaue-before-use.patch new file mode 100644 index 00000000000..b319f5e27eb --- /dev/null +++ b/package/boot/uboot-mediatek/patches/101-06-reset-mediatek-check-malloc-return-valaue-before-use.patch @@ -0,0 +1,26 @@ +From 06e6d224f7d564a34407eba21b51797da7f22628 Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 19 Jul 2023 17:16:11 +0800 +Subject: [PATCH 06/29] reset: mediatek: check malloc return valaue before use + +This patch add missing return value check for allocating the driver's +private data. -ENOMEM will be returned if malloc() fails. + +Signed-off-by: Sam Shih +Signed-off-by: Weijie Gao +--- + drivers/reset/reset-mediatek.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/reset/reset-mediatek.c ++++ b/drivers/reset/reset-mediatek.c +@@ -79,6 +79,9 @@ int mediatek_reset_bind(struct udevice * + return ret; + + priv = malloc(sizeof(struct mediatek_reset_priv)); ++ if (!priv) ++ return -ENOMEM; ++ + priv->regofs = regofs; + priv->nr_resets = num_regs * 32; + dev_set_priv(rst_dev, priv); diff --git a/package/boot/uboot-mediatek/patches/101-07-i2c-mediatek-fix-I2C-usability-for-MT7981.patch b/package/boot/uboot-mediatek/patches/101-07-i2c-mediatek-fix-I2C-usability-for-MT7981.patch new file mode 100644 index 00000000000..dd00104c391 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/101-07-i2c-mediatek-fix-I2C-usability-for-MT7981.patch @@ -0,0 +1,125 @@ +From 77898faf6ce56eb08109cdb853f074bad5acee55 Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 19 Jul 2023 17:16:15 +0800 +Subject: [PATCH 07/29] i2c: mediatek: fix I2C usability for MT7981 + +MT7981 actually uses MediaTek I2C controller v3 instead of v1. +This patch adds support for I2C controller v3 fix fixes the I2C usability +for MT7981. + +Signed-off-by: Sam Shih +Signed-off-by: Weijie Gao +--- + drivers/i2c/mtk_i2c.c | 45 +++++++++++++++++++++++++++++++++++++++++-- + 1 file changed, 43 insertions(+), 2 deletions(-) + +--- a/drivers/i2c/mtk_i2c.c ++++ b/drivers/i2c/mtk_i2c.c +@@ -183,9 +183,36 @@ static const uint mt_i2c_regs_v2[] = { + [REG_DCM_EN] = 0xf88, + }; + ++static const uint mt_i2c_regs_v3[] = { ++ [REG_PORT] = 0x0, ++ [REG_INTR_MASK] = 0x8, ++ [REG_INTR_STAT] = 0xc, ++ [REG_CONTROL] = 0x10, ++ [REG_TRANSFER_LEN] = 0x14, ++ [REG_TRANSAC_LEN] = 0x18, ++ [REG_DELAY_LEN] = 0x1c, ++ [REG_TIMING] = 0x20, ++ [REG_START] = 0x24, ++ [REG_EXT_CONF] = 0x28, ++ [REG_LTIMING] = 0x2c, ++ [REG_HS] = 0x30, ++ [REG_IO_CONFIG] = 0x34, ++ [REG_FIFO_ADDR_CLR] = 0x38, ++ [REG_TRANSFER_LEN_AUX] = 0x44, ++ [REG_CLOCK_DIV] = 0x48, ++ [REG_SOFTRESET] = 0x50, ++ [REG_SLAVE_ADDR] = 0x94, ++ [REG_DEBUGSTAT] = 0xe4, ++ [REG_DEBUGCTRL] = 0xe8, ++ [REG_FIFO_STAT] = 0xf4, ++ [REG_FIFO_THRESH] = 0xf8, ++ [REG_DCM_EN] = 0xf88, ++}; ++ + struct mtk_i2c_soc_data { + const uint *regs; + uint dma_sync: 1; ++ uint ltiming_adjust: 1; + }; + + struct mtk_i2c_priv { +@@ -401,6 +428,10 @@ static int mtk_i2c_set_speed(struct udev + (sample_cnt << HS_SAMPLE_OFFSET) | + (step_cnt << HS_STEP_OFFSET); + i2c_writel(priv, REG_HS, high_speed_reg); ++ if (priv->soc_data->ltiming_adjust) { ++ timing_reg = (sample_cnt << 12) | (step_cnt << 9); ++ i2c_writel(priv, REG_LTIMING, timing_reg); ++ } + } else { + ret = mtk_i2c_calculate_speed(clk_src, priv->speed, + &step_cnt, &sample_cnt); +@@ -412,7 +443,12 @@ static int mtk_i2c_set_speed(struct udev + high_speed_reg = I2C_TIME_CLR_VALUE; + i2c_writel(priv, REG_TIMING, timing_reg); + i2c_writel(priv, REG_HS, high_speed_reg); ++ if (priv->soc_data->ltiming_adjust) { ++ timing_reg = (sample_cnt << 6) | step_cnt; ++ i2c_writel(priv, REG_LTIMING, timing_reg); ++ } + } ++ + exit: + if (mtk_i2c_clk_disable(priv)) + return log_msg_ret("set_speed disable clk", -1); +@@ -725,7 +761,6 @@ static int mtk_i2c_probe(struct udevice + return log_msg_ret("probe enable clk", -1); + + mtk_i2c_init_hw(priv); +- + if (mtk_i2c_clk_disable(priv)) + return log_msg_ret("probe disable clk", -1); + +@@ -750,31 +785,37 @@ static int mtk_i2c_deblock(struct udevic + static const struct mtk_i2c_soc_data mt76xx_soc_data = { + .regs = mt_i2c_regs_v1, + .dma_sync = 0, ++ .ltiming_adjust = 0, + }; + + static const struct mtk_i2c_soc_data mt7981_soc_data = { +- .regs = mt_i2c_regs_v1, ++ .regs = mt_i2c_regs_v3, + .dma_sync = 1, ++ .ltiming_adjust = 1, + }; + + static const struct mtk_i2c_soc_data mt7986_soc_data = { + .regs = mt_i2c_regs_v1, + .dma_sync = 1, ++ .ltiming_adjust = 0, + }; + + static const struct mtk_i2c_soc_data mt8183_soc_data = { + .regs = mt_i2c_regs_v2, + .dma_sync = 1, ++ .ltiming_adjust = 0, + }; + + static const struct mtk_i2c_soc_data mt8518_soc_data = { + .regs = mt_i2c_regs_v1, + .dma_sync = 0, ++ .ltiming_adjust = 0, + }; + + static const struct mtk_i2c_soc_data mt8512_soc_data = { + .regs = mt_i2c_regs_v1, + .dma_sync = 1, ++ .ltiming_adjust = 0, + }; + + static const struct dm_i2c_ops mtk_i2c_ops = { diff --git a/package/boot/uboot-mediatek/patches/101-08-arm-dts-enable-i2c-support-for-MediaTek-MT7981.patch b/package/boot/uboot-mediatek/patches/101-08-arm-dts-enable-i2c-support-for-MediaTek-MT7981.patch new file mode 100644 index 00000000000..77c4023493a --- /dev/null +++ b/package/boot/uboot-mediatek/patches/101-08-arm-dts-enable-i2c-support-for-MediaTek-MT7981.patch @@ -0,0 +1,36 @@ +From e9467f40d4327cfcb80944a0f12ae195b0d7cd40 Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 19 Jul 2023 17:16:19 +0800 +Subject: [PATCH 08/29] arm: dts: enable i2c support for MediaTek MT7981 + +This patch enables i2c support for MediaTek MT7981 + +Signed-off-by: Sam Shih +Signed-off-by: Weijie Gao +--- + arch/arm/dts/mt7981.dtsi | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +--- a/arch/arm/dts/mt7981.dtsi ++++ b/arch/arm/dts/mt7981.dtsi +@@ -181,6 +181,20 @@ + status = "disabled"; + }; + ++ i2c0: i2c@11007000 { ++ compatible = "mediatek,mt7981-i2c"; ++ reg = <0x11007000 0x1000>, ++ <0x10217080 0x80>; ++ interrupts = ; ++ clock-div = <1>; ++ clocks = <&infracfg_ao CK_INFRA_I2CO_CK>, ++ <&infracfg_ao CK_INFRA_AP_DMA_CK>; ++ clock-names = "main", "dma"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + uart0: serial@11002000 { + compatible = "mediatek,hsuart"; + reg = <0x11002000 0x400>; diff --git a/package/boot/uboot-mediatek/patches/101-09-pwm-mtk-add-support-for-MediaTek-MT7988-SoC.patch b/package/boot/uboot-mediatek/patches/101-09-pwm-mtk-add-support-for-MediaTek-MT7988-SoC.patch new file mode 100644 index 00000000000..6ef62811cb1 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/101-09-pwm-mtk-add-support-for-MediaTek-MT7988-SoC.patch @@ -0,0 +1,34 @@ +From 646dab4a8e853b2d0789fa2ff64e7c48f5396cfa Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 19 Jul 2023 17:16:24 +0800 +Subject: [PATCH 09/29] pwm: mtk: add support for MediaTek MT7988 SoC + +This patch adds PWM support for MediaTek MT7988 SoC. + +Signed-off-by: Weijie Gao +--- + drivers/pwm/pwm-mtk.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/drivers/pwm/pwm-mtk.c ++++ b/drivers/pwm/pwm-mtk.c +@@ -205,12 +205,19 @@ static const struct mtk_pwm_soc mt7986_d + .reg_ver = PWM_REG_V1, + }; + ++static const struct mtk_pwm_soc mt7988_data = { ++ .num_pwms = 8, ++ .pwm45_fixup = false, ++ .reg_ver = PWM_REG_V2, ++}; ++ + static const struct udevice_id mtk_pwm_ids[] = { + { .compatible = "mediatek,mt7622-pwm", .data = (ulong)&mt7622_data }, + { .compatible = "mediatek,mt7623-pwm", .data = (ulong)&mt7623_data }, + { .compatible = "mediatek,mt7629-pwm", .data = (ulong)&mt7629_data }, + { .compatible = "mediatek,mt7981-pwm", .data = (ulong)&mt7981_data }, + { .compatible = "mediatek,mt7986-pwm", .data = (ulong)&mt7986_data }, ++ { .compatible = "mediatek,mt7988-pwm", .data = (ulong)&mt7988_data }, + { } + }; + diff --git a/package/boot/uboot-mediatek/patches/101-10-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch b/package/boot/uboot-mediatek/patches/101-10-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch new file mode 100644 index 00000000000..12eda828fa9 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/101-10-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch @@ -0,0 +1,1505 @@ +From 94306126baa215c39e9fd5328550586dedf00230 Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 19 Jul 2023 17:16:28 +0800 +Subject: [PATCH 10/29] clk: mediatek: add clock driver support for MediaTek + MT7988 SoC + +This patch adds clock driver support for MediaTek MT7988 SoC + +Signed-off-by: Weijie Gao +--- + drivers/clk/mediatek/Makefile | 1 + + drivers/clk/mediatek/clk-mt7988.c | 1123 ++++++++++++++++++++++++ + include/dt-bindings/clock/mt7988-clk.h | 349 ++++++++ + 3 files changed, 1473 insertions(+) + create mode 100644 drivers/clk/mediatek/clk-mt7988.c + create mode 100644 include/dt-bindings/clock/mt7988-clk.h + +--- a/drivers/clk/mediatek/Makefile ++++ b/drivers/clk/mediatek/Makefile +@@ -9,6 +9,7 @@ obj-$(CONFIG_TARGET_MT7622) += clk-mt762 + obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o + obj-$(CONFIG_TARGET_MT7986) += clk-mt7986.o + obj-$(CONFIG_TARGET_MT7981) += clk-mt7981.o ++obj-$(CONFIG_TARGET_MT7988) += clk-mt7988.o + obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o + obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o + obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o +--- /dev/null ++++ b/drivers/clk/mediatek/clk-mt7988.c +@@ -0,0 +1,1123 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * MediaTek clock driver for MT7988 SoC ++ * ++ * Copyright (C) 2022 MediaTek Inc. ++ * Author: Sam Shih ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "clk-mtk.h" ++ ++#define MT7988_CLK_PDN 0x250 ++#define MT7988_CLK_PDN_EN_WRITE BIT(31) ++ ++#define MT7988_ETHDMA_RST_CTRL_OFS 0x34 ++#define MT7988_ETHWARP_RST_CTRL_OFS 0x8 ++ ++#define XTAL_FACTOR(_id, _name, _parent, _mult, _div) \ ++ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) ++ ++#define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ ++ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) ++ ++#define TOP_FACTOR(_id, _name, _parent, _mult, _div) \ ++ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) ++ ++#define INFRA_FACTOR(_id, _name, _parent, _mult, _div) \ ++ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_INFRASYS) ++ ++/* FIXED PLLS */ ++static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = { ++ FIXED_CLK(CK_APMIXED_NETSYSPLL, CLK_XTAL, 850000000), ++ FIXED_CLK(CK_APMIXED_MPLL, CLK_XTAL, 416000000), ++ FIXED_CLK(CK_APMIXED_MMPLL, CLK_XTAL, 720000000), ++ FIXED_CLK(CK_APMIXED_APLL2, CLK_XTAL, 196608000), ++ FIXED_CLK(CK_APMIXED_NET1PLL, CLK_XTAL, 2500000000), ++ FIXED_CLK(CK_APMIXED_NET2PLL, CLK_XTAL, 800000000), ++ FIXED_CLK(CK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000), ++ FIXED_CLK(CK_APMIXED_SGMPLL, CLK_XTAL, 325000000), ++ FIXED_CLK(CK_APMIXED_ARM_B, CLK_XTAL, 1500000000), ++ FIXED_CLK(CK_APMIXED_CCIPLL2_B, CLK_XTAL, 960000000), ++ FIXED_CLK(CK_APMIXED_USXGMIIPLL, CLK_XTAL, 644533000), ++ FIXED_CLK(CK_APMIXED_MSDCPLL, CLK_XTAL, 400000000), ++}; ++ ++/* TOPCKGEN FIXED DIV */ ++static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = { ++ XTAL_FACTOR(CK_TOP_CB_CKSQ_40M, "cb_cksq_40m", CLK_XTAL, 1, 1), ++ PLL_FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", CK_APMIXED_MPLL, 1, 1), ++ PLL_FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", CK_APMIXED_MPLL, 1, 2), ++ PLL_FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", CK_APMIXED_MPLL, 1, 2), ++ PLL_FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", CK_APMIXED_MPLL, 1, 4), ++ PLL_FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", CK_APMIXED_MPLL, 1, 8), ++ PLL_FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", CK_APMIXED_MPLL, 1, 16), ++ PLL_FACTOR(CK_TOP_CB_MM_720M, "cb_mm_720m", CK_APMIXED_MMPLL, 1, 1), ++ PLL_FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", CK_APMIXED_MMPLL, 1, 2), ++ PLL_FACTOR(CK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", CK_APMIXED_MMPLL, 1, 15), ++ PLL_FACTOR(CK_TOP_CB_MM_D4, "cb_mm_d4", CK_APMIXED_MMPLL, 1, 4), ++ PLL_FACTOR(CK_TOP_MM_D6_D2, "mm_d6_d2", CK_APMIXED_MMPLL, 1, 12), ++ PLL_FACTOR(CK_TOP_CB_MM_D8, "cb_mm_d8", CK_APMIXED_MMPLL, 1, 8), ++ PLL_FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", CK_APMIXED_APLL2, 1, ++ 1), ++ PLL_FACTOR(CK_TOP_CB_APLL2_D4, "cb_apll2_d4", CK_APMIXED_APLL2, 1, 4), ++ PLL_FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", CK_APMIXED_NET1PLL, 1, 4), ++ PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5), ++ PLL_FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", CK_APMIXED_NET1PLL, 1, 10), ++ PLL_FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", CK_APMIXED_NET1PLL, 1, 20), ++ PLL_FACTOR(CK_TOP_CB_NET1_D8, "cb_net1_d8", CK_APMIXED_NET1PLL, 1, 8), ++ PLL_FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", CK_APMIXED_NET1PLL, 1, 16), ++ PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32), ++ PLL_FACTOR(CK_TOP_NET1_D8_D8, "net1_d8_d8", CK_APMIXED_NET1PLL, 1, 64), ++ PLL_FACTOR(CK_TOP_NET1_D8_D16, "net1_d8_d16", CK_APMIXED_NET1PLL, 1, ++ 128), ++ PLL_FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", CK_APMIXED_NET2PLL, 1, ++ 1), ++ PLL_FACTOR(CK_TOP_CB_NET2_D2, "cb_net2_d2", CK_APMIXED_NET2PLL, 1, 2), ++ PLL_FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", CK_APMIXED_NET2PLL, 1, 4), ++ PLL_FACTOR(CK_TOP_NET2_D4_D4, "net2_d4_d4", CK_APMIXED_NET2PLL, 1, 16), ++ PLL_FACTOR(CK_TOP_NET2_D4_D8, "net2_d4_d8", CK_APMIXED_NET2PLL, 1, 32), ++ PLL_FACTOR(CK_TOP_CB_NET2_D6, "cb_net2_d6", CK_APMIXED_NET2PLL, 1, 6), ++ PLL_FACTOR(CK_TOP_CB_NET2_D8, "cb_net2_d8", CK_APMIXED_NET2PLL, 1, 8), ++ PLL_FACTOR(CK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", ++ CK_APMIXED_WEDMCUPLL, 1, 1), ++ PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1), ++ PLL_FACTOR(CK_TOP_CB_NETSYS_850M, "cb_netsys_850m", ++ CK_APMIXED_NETSYSPLL, 1, 1), ++ PLL_FACTOR(CK_TOP_CB_MSDC_400M, "cb_msdc_400m", CK_APMIXED_MSDCPLL, 1, ++ 1), ++ TOP_FACTOR(CK_TOP_CKSQ_40M_D2, "cksq_40m_d2", CK_TOP_CB_CKSQ_40M, 1, 2), ++ TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_CB_CKSQ_40M, 1, ++ 1250), ++ TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_CB_CKSQ_40M, 1, ++ 1220), ++ TOP_FACTOR(CK_TOP_INFRA_F32K, "csw_infra_f32k", CK_TOP_CB_RTC_32P7K, 1, ++ 1), ++ XTAL_FACTOR(CK_TOP_CKSQ_SRC, "cksq_src", CLK_XTAL, 1, 1), ++ TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1), ++ TOP_FACTOR(CK_TOP_NETSYS_GSW, "netsys_gsw", CK_TOP_NETSYS_GSW_SEL, 1, ++ 1), ++ TOP_FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", ++ CK_TOP_NETSYS_MCU_SEL, 1, 1), ++ TOP_FACTOR(CK_TOP_EIP197, "eip197", CK_TOP_EIP197_SEL, 1, 1), ++ TOP_FACTOR(CK_TOP_EMMC_250M, "emmc_250m", CK_TOP_EMMC_250M_SEL, 1, 1), ++ TOP_FACTOR(CK_TOP_EMMC_400M, "emmc_400m", CK_TOP_EMMC_400M_SEL, 1, 1), ++ TOP_FACTOR(CK_TOP_SPI, "spi", CK_TOP_SPI_SEL, 1, 1), ++ TOP_FACTOR(CK_TOP_SPIM_MST, "spim_mst", CK_TOP_SPIM_MST_SEL, 1, 1), ++ TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1), ++ TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1), ++ TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1), ++ TOP_FACTOR(CK_TOP_USB_SYS, "usb_sys", CK_TOP_USB_SYS_SEL, 1, 1), ++ TOP_FACTOR(CK_TOP_USB_SYS_P1, "usb_sys_p1", CK_TOP_USB_SYS_P1_SEL, 1, ++ 1), ++ TOP_FACTOR(CK_TOP_USB_XHCI, "usb_xhci", CK_TOP_USB_XHCI_SEL, 1, 1), ++ TOP_FACTOR(CK_TOP_USB_XHCI_P1, "usb_xhci_p1", CK_TOP_USB_XHCI_P1_SEL, 1, ++ 1), ++ TOP_FACTOR(CK_TOP_USB_FRMCNT, "usb_frmcnt", CK_TOP_USB_FRMCNT_SEL, 1, ++ 1), ++ TOP_FACTOR(CK_TOP_USB_FRMCNT_P1, "usb_frmcnt_p1", ++ CK_TOP_USB_FRMCNT_P1_SEL, 1, 1), ++ TOP_FACTOR(CK_TOP_AUD, "aud", CK_TOP_AUD_SEL, 1, 1), ++ TOP_FACTOR(CK_TOP_A1SYS, "a1sys", CK_TOP_A1SYS_SEL, 1, 1), ++ TOP_FACTOR(CK_TOP_AUD_L, "aud_l", CK_TOP_AUD_L_SEL, 1, 1), ++ TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 1, 1), ++ TOP_FACTOR(CK_TOP_SYSAXI, "sysaxi", CK_TOP_SYSAXI_SEL, 1, 1), ++ TOP_FACTOR(CK_TOP_INFRA_F26M, "csw_infra_f26m", CK_TOP_INFRA_F26M_SEL, ++ 1, 1), ++ TOP_FACTOR(CK_TOP_USB_REF, "usb_ref", CK_TOP_CKSQ_SRC, 1, 1), ++ TOP_FACTOR(CK_TOP_USB_CK_P1, "usb_ck_p1", CK_TOP_CKSQ_SRC, 1, 1), ++}; ++ ++/* TOPCKGEN MUX PARENTS */ ++static const int netsys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_D2, ++ CK_TOP_CB_MM_D2 }; ++ ++static const int netsys_500m_parents[] = { CK_TOP_CB_CKSQ_40M, ++ CK_TOP_CB_NET1_D5, ++ CK_TOP_NET1_D5_D2 }; ++ ++static const int netsys_2x_parents[] = { CK_TOP_CB_CKSQ_40M, ++ CK_TOP_CB_NET2_800M, ++ CK_TOP_CB_MM_720M }; ++ ++static const int netsys_gsw_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D4, ++ CK_TOP_CB_NET1_D5 }; ++ ++static const int eth_gmii_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4 }; ++ ++static const int netsys_mcu_parents[] = { ++ CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_800M, CK_TOP_CB_MM_720M, ++ CK_TOP_CB_NET1_D4, CK_TOP_CB_NET1_D5, CK_TOP_CB_M_416M ++}; ++ ++static const int eip197_parents[] = { ++ CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NETSYS_850M, CK_TOP_CB_NET2_800M, ++ CK_TOP_CB_MM_720M, CK_TOP_CB_NET1_D4, CK_TOP_CB_NET1_D5 ++}; ++ ++static const int axi_infra_parents[] = { CK_TOP_CB_CKSQ_40M, ++ CK_TOP_NET1_D8_D2 }; ++ ++static const int uart_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D8, ++ CK_TOP_M_D8_D2 }; ++ ++static const int emmc_250m_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D2, ++ CK_TOP_CB_MM_D4 }; ++ ++static const int emmc_400m_parents[] = { ++ CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MSDC_400M, CK_TOP_CB_MM_D2, ++ CK_TOP_CB_M_D2, CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2 ++}; ++ ++static const int spi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2, ++ CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2, ++ CK_TOP_CB_NET2_D6, CK_TOP_NET1_D5_D4, ++ CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 }; ++ ++static const int nfi1x_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D4, ++ CK_TOP_NET1_D8_D2, CK_TOP_CB_NET2_D6, ++ CK_TOP_CB_M_D4, CK_TOP_CB_MM_D8, ++ CK_TOP_NET1_D8_D4, CK_TOP_CB_M_D8 }; ++ ++static const int spinfi_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_CB_CKSQ_40M, ++ CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4, ++ CK_TOP_CB_MM_D8, CK_TOP_NET1_D8_D4, ++ CK_TOP_MM_D6_D2, CK_TOP_CB_M_D8 }; ++ ++static const int pwm_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2, ++ CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4, ++ CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K }; ++ ++static const int i2c_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4, ++ CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 }; ++ ++static const int pcie_mbist_250m_parents[] = { CK_TOP_CB_CKSQ_40M, ++ CK_TOP_NET1_D5_D2 }; ++ ++static const int pextp_tl_ck_parents[] = { CK_TOP_CB_CKSQ_40M, ++ CK_TOP_CB_NET2_D6, CK_TOP_CB_MM_D8, ++ CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K }; ++ ++static const int usb_frmcnt_parents[] = { CK_TOP_CB_CKSQ_40M, ++ CK_TOP_CB_MM_D3_D5 }; ++ ++static const int aud_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M }; ++ ++static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_D4 }; ++ ++static const int aud_l_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M, ++ CK_TOP_M_D8_D2 }; ++ ++static const int sspxtp_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_M_D8_D2 }; ++ ++static const int usxgmii_sbus_0_parents[] = { CK_TOP_CB_CKSQ_40M, ++ CK_TOP_NET1_D8_D4 }; ++ ++static const int sgm_0_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_SGM_325M }; ++ ++static const int sysapb_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D3_D2 }; ++ ++static const int eth_refck_50m_parents[] = { CK_TOP_CB_CKSQ_40M, ++ CK_TOP_NET2_D4_D4 }; ++ ++static const int eth_sys_200m_parents[] = { CK_TOP_CB_CKSQ_40M, ++ CK_TOP_CB_NET2_D4 }; ++ ++static const int eth_xgmii_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_NET1_D8_D8, ++ CK_TOP_NET1_D8_D16 }; ++ ++static const int bus_tops_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D5, ++ CK_TOP_CB_NET2_D2 }; ++ ++static const int npu_tops_parents[] = { CK_TOP_CB_CKSQ_40M, ++ CK_TOP_CB_NET2_800M }; ++ ++static const int dramc_md32_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2, ++ CK_TOP_CB_WEDMCU_208M }; ++ ++static const int da_xtp_glb_p0_parents[] = { CK_TOP_CB_CKSQ_40M, ++ CK_TOP_CB_NET2_D8 }; ++ ++static const int mcusys_backup_625m_parents[] = { CK_TOP_CB_CKSQ_40M, ++ CK_TOP_CB_NET1_D4 }; ++ ++static const int macsec_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_SGM_325M, ++ CK_TOP_CB_NET1_D8 }; ++ ++static const int netsys_tops_400m_parents[] = { CK_TOP_CB_CKSQ_40M, ++ CK_TOP_CB_NET2_D2 }; ++ ++static const int eth_mii_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_NET2_D4_D8 }; ++ ++#define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ ++ _shift, _width, _gate, _upd_ofs, _upd) \ ++ { \ ++ .id = _id, .mux_reg = _mux_ofs, .mux_set_reg = _mux_set_ofs, \ ++ .mux_clr_reg = _mux_clr_ofs, .upd_reg = _upd_ofs, \ ++ .upd_shift = _upd, .mux_shift = _shift, \ ++ .mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs, \ ++ .gate_shift = _gate, .parent = _parents, \ ++ .num_parents = ARRAY_SIZE(_parents), \ ++ .flags = CLK_MUX_SETCLR_UPD, \ ++ } ++ ++/* TOPCKGEN MUX_GATE */ ++static const struct mtk_composite topckgen_mtk_muxes[] = { ++ TOP_MUX(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x0, 0x4, 0x8, ++ 0, 2, 7, 0x1c0, 0), ++ TOP_MUX(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents, ++ 0x0, 0x4, 0x8, 8, 2, 15, 0x1c0, 1), ++ TOP_MUX(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x0, ++ 0x4, 0x8, 16, 2, 23, 0x1c0, 2), ++ TOP_MUX(CK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents, ++ 0x0, 0x4, 0x8, 24, 2, 31, 0x1c0, 3), ++ TOP_MUX(CK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x10, ++ 0x14, 0x18, 0, 1, 7, 0x1c0, 4), ++ TOP_MUX(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents, ++ 0x10, 0x14, 0x18, 8, 3, 15, 0x1c0, 5), ++ TOP_MUX(CK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel", ++ netsys_mcu_parents, 0x10, 0x14, 0x18, 16, 3, 23, 0x1c0, 6), ++ TOP_MUX(CK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, 0x10, 0x14, ++ 0x18, 24, 3, 31, 0x1c0, 7), ++ TOP_MUX(CK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, 0x20, ++ 0x24, 0x28, 0, 1, 7, 0x1c0, 8), ++ TOP_MUX(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x20, 0x24, 0x28, 8, ++ 2, 15, 0x1c0, 9), ++ TOP_MUX(CK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x20, ++ 0x24, 0x28, 16, 2, 23, 0x1c0, 10), ++ TOP_MUX(CK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x20, ++ 0x24, 0x28, 24, 3, 31, 0x1c0, 11), ++ TOP_MUX(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x30, 0x34, 0x38, 0, 3, ++ 7, 0x1c0, 12), ++ TOP_MUX(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x30, 0x34, ++ 0x38, 8, 3, 15, 0x1c0, 13), ++ TOP_MUX(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x30, 0x34, 0x38, ++ 16, 3, 23, 0x1c0, 14), ++ TOP_MUX(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x30, 0x34, ++ 0x38, 24, 3, 31, 0x1c0, 15), ++ TOP_MUX(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x40, 0x44, 0x48, 0, 3, ++ 7, 0x1c0, 16), ++ TOP_MUX(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x40, 0x44, 0x48, 8, 2, ++ 15, 0x1c0, 17), ++ TOP_MUX(CK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel", ++ pcie_mbist_250m_parents, 0x40, 0x44, 0x48, 16, 1, 23, 0x1c0, ++ 18), ++ TOP_MUX(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents, ++ 0x40, 0x44, 0x48, 24, 3, 31, 0x1c0, 19), ++ TOP_MUX(CK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_ck_p1_sel", ++ pextp_tl_ck_parents, 0x50, 0x54, 0x58, 0, 3, 7, 0x1c0, 20), ++ TOP_MUX(CK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_ck_p2_sel", ++ pextp_tl_ck_parents, 0x50, 0x54, 0x58, 8, 3, 15, 0x1c0, 21), ++ TOP_MUX(CK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_ck_p3_sel", ++ pextp_tl_ck_parents, 0x50, 0x54, 0x58, 16, 3, 23, 0x1c0, 22), ++ TOP_MUX(CK_TOP_USB_SYS_SEL, "usb_sys_sel", eth_gmii_parents, 0x50, 0x54, ++ 0x58, 24, 1, 31, 0x1c0, 23), ++ TOP_MUX(CK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, 0x60, ++ 0x64, 0x68, 0, 1, 7, 0x1c0, 24), ++ TOP_MUX(CK_TOP_USB_XHCI_SEL, "usb_xhci_sel", eth_gmii_parents, 0x60, ++ 0x64, 0x68, 8, 1, 15, 0x1c0, 25), ++ TOP_MUX(CK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents, ++ 0x60, 0x64, 0x68, 16, 1, 23, 0x1c0, 26), ++ TOP_MUX(CK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents, ++ 0x60, 0x64, 0x68, 24, 1, 31, 0x1c0, 27), ++ TOP_MUX(CK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel", ++ usb_frmcnt_parents, 0x70, 0x74, 0x78, 0, 1, 7, 0x1c0, 28), ++ TOP_MUX(CK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x70, 0x74, 0x78, 8, 1, ++ 15, 0x1c0, 29), ++ TOP_MUX(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x70, 0x74, 0x78, ++ 16, 1, 23, 0x1c0, 30), ++ TOP_MUX(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x70, 0x74, 0x78, ++ 24, 2, 31, 0x1c4, 0), ++ TOP_MUX(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, 0x80, 0x84, ++ 0x88, 0, 1, 7, 0x1c4, 1), ++ TOP_MUX(CK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, 0x80, 0x84, ++ 0x88, 8, 1, 15, 0x1c4, 2), ++ TOP_MUX(CK_TOP_USB_PHY_SEL, "usb_phy_sel", sspxtp_parents, 0x80, 0x84, ++ 0x88, 16, 1, 23, 0x1c4, 3), ++ TOP_MUX(CK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel", ++ usxgmii_sbus_0_parents, 0x80, 0x84, 0x88, 24, 1, 31, 0x1c4, 4), ++ TOP_MUX(CK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel", ++ usxgmii_sbus_0_parents, 0x90, 0x94, 0x98, 0, 1, 7, 0x1c4, 5), ++ TOP_MUX(CK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, 0x90, 0x94, 0x98, ++ 8, 1, 15, 0x1c4, 6), ++ TOP_MUX(CK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", usxgmii_sbus_0_parents, ++ 0x90, 0x94, 0x98, 16, 1, 23, 0x1c4, 7), ++ TOP_MUX(CK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, 0x90, 0x94, 0x98, ++ 24, 1, 31, 0x1c4, 8), ++ TOP_MUX(CK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", usxgmii_sbus_0_parents, ++ 0xa0, 0xa4, 0xa8, 0, 1, 7, 0x1c4, 9), ++ TOP_MUX(CK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", sspxtp_parents, ++ 0xa0, 0xa4, 0xa8, 8, 1, 15, 0x1c4, 10), ++ TOP_MUX(CK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", sspxtp_parents, ++ 0xa0, 0xa4, 0xa8, 16, 1, 23, 0x1c4, 11), ++ TOP_MUX(CK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, 0xa0, 0xa4, ++ 0xa8, 24, 1, 31, 0x1c4, 12), ++ TOP_MUX(CK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0xb0, 0xb4, ++ 0xb8, 0, 1, 7, 0x1c4, 13), ++ TOP_MUX(CK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel", ++ eth_refck_50m_parents, 0xb0, 0xb4, 0xb8, 8, 1, 15, 0x1c4, 14), ++ TOP_MUX(CK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel", ++ eth_sys_200m_parents, 0xb0, 0xb4, 0xb8, 16, 1, 23, 0x1c4, 15), ++ TOP_MUX(CK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents, ++ 0xb0, 0xb4, 0xb8, 24, 1, 31, 0x1c4, 16), ++ TOP_MUX(CK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, 0xc0, ++ 0xc4, 0xc8, 0, 2, 7, 0x1c4, 17), ++ TOP_MUX(CK_TOP_BUS_TOPS_SEL, "bus_tops_sel", bus_tops_parents, 0xc0, ++ 0xc4, 0xc8, 8, 2, 15, 0x1c4, 18), ++ TOP_MUX(CK_TOP_NPU_TOPS_SEL, "npu_tops_sel", npu_tops_parents, 0xc0, ++ 0xc4, 0xc8, 16, 1, 23, 0x1c4, 19), ++ TOP_MUX(CK_TOP_DRAMC_SEL, "dramc_sel", sspxtp_parents, 0xc0, 0xc4, 0xc8, ++ 24, 1, 31, 0x1c4, 20), ++ TOP_MUX(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents, ++ 0xd0, 0xd4, 0xd8, 0, 2, 7, 0x1c4, 21), ++ TOP_MUX(CK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents, ++ 0xd0, 0xd4, 0xd8, 8, 1, 15, 0x1c4, 22), ++ TOP_MUX(CK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", sspxtp_parents, 0xd0, 0xd4, ++ 0xd8, 16, 1, 23, 0x1c4, 23), ++ TOP_MUX(CK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", sspxtp_parents, 0xd0, 0xd4, ++ 0xd8, 24, 1, 31, 0x1c4, 24), ++ TOP_MUX(CK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", sspxtp_parents, 0xe0, 0xe4, ++ 0xe8, 0, 1, 7, 0x1c4, 25), ++ TOP_MUX(CK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", sspxtp_parents, 0xe0, 0xe4, ++ 0xe8, 8, 1, 15, 0x1c4, 26), ++ TOP_MUX(CK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel", ++ da_xtp_glb_p0_parents, 0xe0, 0xe4, 0xe8, 16, 1, 23, 0x1c4, 27), ++ TOP_MUX(CK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel", ++ da_xtp_glb_p0_parents, 0xe0, 0xe4, 0xe8, 24, 1, 31, 0x1c4, 28), ++ TOP_MUX(CK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel", ++ da_xtp_glb_p0_parents, 0xf0, 0xf4, 0xf8, 0, 1, 7, 0x1c4, 29), ++ TOP_MUX(CK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel", ++ da_xtp_glb_p0_parents, 0xf0, 0xf4, 0xf8, 8, 1, 15, 0x1c4, 30), ++ TOP_MUX(CK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0xf0, 0xf4, 0xf8, 16, ++ 1, 23, 0x1c8, 0), ++ TOP_MUX(CK_TOP_DA_SELM_XTAL_SEL, "da_selm_xtal_sel", sspxtp_parents, ++ 0xf0, 0xf4, 0xf8, 24, 1, 31, 0x1c8, 1), ++ TOP_MUX(CK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, 0x100, 0x104, ++ 0x108, 0, 1, 7, 0x1c8, 2), ++ TOP_MUX(CK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", sspxtp_parents, ++ 0x100, 0x104, 0x108, 8, 1, 15, 0x1c8, 3), ++ TOP_MUX(CK_TOP_MCUSYS_BACKUP_625M_SEL, "mcusys_backup_625m_sel", ++ mcusys_backup_625m_parents, 0x100, 0x104, 0x108, 16, 1, 23, ++ 0x1c8, 4), ++ TOP_MUX(CK_TOP_NETSYS_SYNC_250M_SEL, "netsys_sync_250m_sel", ++ pcie_mbist_250m_parents, 0x100, 0x104, 0x108, 24, 1, 31, 0x1c8, ++ 5), ++ TOP_MUX(CK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, 0x110, 0x114, ++ 0x118, 0, 2, 7, 0x1c8, 6), ++ TOP_MUX(CK_TOP_NETSYS_TOPS_400M_SEL, "netsys_tops_400m_sel", ++ netsys_tops_400m_parents, 0x110, 0x114, 0x118, 8, 1, 15, 0x1c8, ++ 7), ++ TOP_MUX(CK_TOP_NETSYS_PPEFB_250M_SEL, "netsys_ppefb_250m_sel", ++ pcie_mbist_250m_parents, 0x110, 0x114, 0x118, 16, 1, 23, 0x1c8, ++ 8), ++ TOP_MUX(CK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", netsys_parents, ++ 0x110, 0x114, 0x118, 24, 2, 31, 0x1c8, 9), ++ TOP_MUX(CK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, 0x120, ++ 0x124, 0x128, 0, 1, 7, 0x1c8, 10), ++ TOP_MUX(CK_TOP_CK_NPU_SEL_CM_TOPS_SEL, "ck_npu_sel_cm_tops_sel", ++ netsys_2x_parents, 0x120, 0x124, 0x128, 8, 2, 15, 0x1c8, 11), ++}; ++ ++/* INFRA FIXED DIV */ ++static const struct mtk_fixed_factor infracfg_mtk_fixed_factor[] = { ++ TOP_FACTOR(CK_INFRA_CK_F26M, "infra_ck_f26m", CK_TOP_INFRA_F26M_SEL, 1, ++ 1), ++ TOP_FACTOR(CK_INFRA_PWM_O, "infra_pwm_o", CK_TOP_PWM_SEL, 1, 1), ++ TOP_FACTOR(CK_INFRA_PCIE_OCC_P0, "infra_pcie_ck_occ_p0", ++ CK_TOP_PEXTP_TL_SEL, 1, 1), ++ TOP_FACTOR(CK_INFRA_PCIE_OCC_P1, "infra_pcie_ck_occ_p1", ++ CK_TOP_PEXTP_TL_P1_SEL, 1, 1), ++ TOP_FACTOR(CK_INFRA_PCIE_OCC_P2, "infra_pcie_ck_occ_p2", ++ CK_TOP_PEXTP_TL_P2_SEL, 1, 1), ++ TOP_FACTOR(CK_INFRA_PCIE_OCC_P3, "infra_pcie_ck_occ_p3", ++ CK_TOP_PEXTP_TL_P3_SEL, 1, 1), ++ TOP_FACTOR(CK_INFRA_133M_HCK, "infra_133m_hck", CK_TOP_SYSAXI, 1, 1), ++ INFRA_FACTOR(CK_INFRA_133M_PHCK, "infra_133m_phck", CK_INFRA_133M_HCK, ++ 1, 1), ++ INFRA_FACTOR(CK_INFRA_66M_PHCK, "infra_66m_phck", CK_INFRA_133M_HCK, 1, ++ 1), ++ TOP_FACTOR(CK_INFRA_FAUD_L_O, "infra_faud_l_o", CK_TOP_AUD_L, 1, 1), ++ TOP_FACTOR(CK_INFRA_FAUD_AUD_O, "infra_faud_aud_o", CK_TOP_A1SYS, 1, 1), ++ TOP_FACTOR(CK_INFRA_FAUD_EG2_O, "infra_faud_eg2_o", CK_TOP_A_TUNER, 1, ++ 1), ++ TOP_FACTOR(CK_INFRA_I2C_O, "infra_i2c_o", CK_TOP_I2C_BCK, 1, 1), ++ TOP_FACTOR(CK_INFRA_UART_O0, "infra_uart_o0", CK_TOP_UART_SEL, 1, 1), ++ TOP_FACTOR(CK_INFRA_UART_O1, "infra_uart_o1", CK_TOP_UART_SEL, 1, 1), ++ TOP_FACTOR(CK_INFRA_UART_O2, "infra_uart_o2", CK_TOP_UART_SEL, 1, 1), ++ TOP_FACTOR(CK_INFRA_NFI_O, "infra_nfi_o", CK_TOP_NFI1X, 1, 1), ++ TOP_FACTOR(CK_INFRA_SPINFI_O, "infra_spinfi_o", CK_TOP_SPINFI_BCK, 1, ++ 1), ++ TOP_FACTOR(CK_INFRA_SPI0_O, "infra_spi0_o", CK_TOP_SPI, 1, 1), ++ TOP_FACTOR(CK_INFRA_SPI1_O, "infra_spi1_o", CK_TOP_SPIM_MST, 1, 1), ++ INFRA_FACTOR(CK_INFRA_LB_MUX_FRTC, "infra_lb_mux_frtc", CK_INFRA_FRTC, ++ 1, 1), ++ TOP_FACTOR(CK_INFRA_FRTC, "infra_frtc", CK_TOP_CB_RTC_32K, 1, 1), ++ TOP_FACTOR(CK_INFRA_FMSDC400_O, "infra_fmsdc400_o", CK_TOP_EMMC_400M, 1, ++ 1), ++ TOP_FACTOR(CK_INFRA_FMSDC2_HCK_OCC, "infra_fmsdc2_hck_occ", ++ CK_TOP_EMMC_250M, 1, 1), ++ TOP_FACTOR(CK_INFRA_PERI_133M, "infra_peri_133m", CK_TOP_SYSAXI, 1, 1), ++ TOP_FACTOR(CK_INFRA_USB_O, "infra_usb_o", CK_TOP_USB_REF, 1, 1), ++ TOP_FACTOR(CK_INFRA_USB_O_P1, "infra_usb_o_p1", CK_TOP_USB_CK_P1, 1, 1), ++ TOP_FACTOR(CK_INFRA_USB_FRMCNT_O, "infra_usb_frmcnt_o", ++ CK_TOP_USB_FRMCNT, 1, 1), ++ TOP_FACTOR(CK_INFRA_USB_FRMCNT_O_P1, "infra_usb_frmcnt_o_p1", ++ CK_TOP_USB_FRMCNT_P1, 1, 1), ++ TOP_FACTOR(CK_INFRA_USB_XHCI_O, "infra_usb_xhci_o", CK_TOP_USB_XHCI, 1, ++ 1), ++ TOP_FACTOR(CK_INFRA_USB_XHCI_O_P1, "infra_usb_xhci_o_p1", ++ CK_TOP_USB_XHCI_P1, 1, 1), ++ XTAL_FACTOR(CK_INFRA_USB_PIPE_O, "infra_usb_pipe_o", CLK_XTAL, 1, 1), ++ XTAL_FACTOR(CK_INFRA_USB_PIPE_O_P1, "infra_usb_pipe_o_p1", CLK_XTAL, 1, ++ 1), ++ XTAL_FACTOR(CK_INFRA_USB_UTMI_O, "infra_usb_utmi_o", CLK_XTAL, 1, 1), ++ XTAL_FACTOR(CK_INFRA_USB_UTMI_O_P1, "infra_usb_utmi_o_p1", CLK_XTAL, 1, ++ 1), ++ XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P0, "infra_pcie_pipe_ck_occ_p0", ++ CLK_XTAL, 1, 1), ++ XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P1, "infra_pcie_pipe_ck_occ_p1", ++ CLK_XTAL, 1, 1), ++ XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P2, "infra_pcie_pipe_ck_occ_p2", ++ CLK_XTAL, 1, 1), ++ XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P3, "infra_pcie_pipe_ck_occ_p3", ++ CLK_XTAL, 1, 1), ++ TOP_FACTOR(CK_INFRA_F26M_O0, "infra_f26m_o0", CK_TOP_INFRA_F26M, 1, 1), ++ TOP_FACTOR(CK_INFRA_F26M_O1, "infra_f26m_o1", CK_TOP_INFRA_F26M, 1, 1), ++ TOP_FACTOR(CK_INFRA_133M_MCK, "infra_133m_mck", CK_TOP_SYSAXI, 1, 1), ++ TOP_FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", CK_TOP_SYSAXI, 1, 1), ++ TOP_FACTOR(CK_INFRA_PERI_66M_O, "infra_peri_66m_o", CK_TOP_SYSAXI, 1, ++ 1), ++ TOP_FACTOR(CK_INFRA_USB_SYS_O, "infra_usb_sys_o", CK_TOP_USB_SYS, 1, 1), ++ TOP_FACTOR(CK_INFRA_USB_SYS_O_P1, "infra_usb_sys_o_p1", ++ CK_TOP_USB_SYS_P1, 1, 1), ++}; ++ ++/* INFRASYS MUX PARENTS */ ++static const int infra_mux_uart0_parents[] = { CK_INFRA_CK_F26M, ++ CK_INFRA_UART_O0 }; ++ ++static const int infra_mux_uart1_parents[] = { CK_INFRA_CK_F26M, ++ CK_INFRA_UART_O1 }; ++ ++static const int infra_mux_uart2_parents[] = { CK_INFRA_CK_F26M, ++ CK_INFRA_UART_O2 }; ++ ++static const int infra_mux_spi0_parents[] = { CK_INFRA_I2C_O, CK_INFRA_SPI0_O }; ++ ++static const int infra_mux_spi1_parents[] = { CK_INFRA_I2C_O, CK_INFRA_SPI1_O }; ++ ++static const int infra_pwm_bck_parents[] = { CK_TOP_INFRA_F32K, ++ CK_INFRA_CK_F26M, CK_INFRA_66M_MCK, ++ CK_INFRA_PWM_O }; ++ ++static const int infra_pcie_gfmux_tl_ck_o_p0_parents[] = { ++ CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M, ++ CK_INFRA_PCIE_OCC_P0 ++}; ++ ++static const int infra_pcie_gfmux_tl_ck_o_p1_parents[] = { ++ CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M, ++ CK_INFRA_PCIE_OCC_P1 ++}; ++ ++static const int infra_pcie_gfmux_tl_ck_o_p2_parents[] = { ++ CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M, ++ CK_INFRA_PCIE_OCC_P2 ++}; ++ ++static const int infra_pcie_gfmux_tl_ck_o_p3_parents[] = { ++ CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M, ++ CK_INFRA_PCIE_OCC_P3 ++}; ++ ++#define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \ ++ { \ ++ .id = _id, .mux_reg = _reg + 0x8, .mux_set_reg = _reg + 0x0, \ ++ .mux_clr_reg = _reg + 0x4, .mux_shift = _shift, \ ++ .mux_mask = BIT(_width) - 1, .parent = _parents, \ ++ .num_parents = ARRAY_SIZE(_parents), \ ++ .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_INFRASYS, \ ++ } ++ ++/* INFRA MUX */ ++static const struct mtk_composite infracfg_mtk_mux[] = { ++ INFRA_MUX(CK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel", ++ infra_mux_uart0_parents, 0x10, 0, 1), ++ INFRA_MUX(CK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel", ++ infra_mux_uart1_parents, 0x10, 1, 1), ++ INFRA_MUX(CK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel", ++ infra_mux_uart2_parents, 0x10, 2, 1), ++ INFRA_MUX(CK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", ++ infra_mux_spi0_parents, 0x10, 4, 1), ++ INFRA_MUX(CK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", ++ infra_mux_spi1_parents, 0x10, 5, 1), ++ INFRA_MUX(CK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel", ++ infra_mux_spi0_parents, 0x10, 6, 1), ++ INFRA_MUX(CK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents, ++ 0x10, 14, 2), ++ INFRA_MUX(CK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel", ++ infra_pwm_bck_parents, 0x10, 16, 2), ++ INFRA_MUX(CK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel", ++ infra_pwm_bck_parents, 0x10, 18, 2), ++ INFRA_MUX(CK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel", ++ infra_pwm_bck_parents, 0x10, 20, 2), ++ INFRA_MUX(CK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel", ++ infra_pwm_bck_parents, 0x10, 22, 2), ++ INFRA_MUX(CK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel", ++ infra_pwm_bck_parents, 0x10, 24, 2), ++ INFRA_MUX(CK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel", ++ infra_pwm_bck_parents, 0x10, 26, 2), ++ INFRA_MUX(CK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel", ++ infra_pwm_bck_parents, 0x10, 28, 2), ++ INFRA_MUX(CK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel", ++ infra_pwm_bck_parents, 0x10, 30, 2), ++ INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, ++ "infra_pcie_gfmux_tl_o_p0_sel", ++ infra_pcie_gfmux_tl_ck_o_p0_parents, 0x20, 0, 2), ++ INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, ++ "infra_pcie_gfmux_tl_o_p1_sel", ++ infra_pcie_gfmux_tl_ck_o_p1_parents, 0x20, 2, 2), ++ INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, ++ "infra_pcie_gfmux_tl_o_p2_sel", ++ infra_pcie_gfmux_tl_ck_o_p2_parents, 0x20, 4, 2), ++ INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, ++ "infra_pcie_gfmux_tl_o_p3_sel", ++ infra_pcie_gfmux_tl_ck_o_p3_parents, 0x20, 6, 2), ++}; ++ ++static const struct mtk_gate_regs infra_0_cg_regs = { ++ .set_ofs = 0x10, ++ .clr_ofs = 0x14, ++ .sta_ofs = 0x18, ++}; ++ ++static const struct mtk_gate_regs infra_1_cg_regs = { ++ .set_ofs = 0x40, ++ .clr_ofs = 0x44, ++ .sta_ofs = 0x48, ++}; ++ ++static const struct mtk_gate_regs infra_2_cg_regs = { ++ .set_ofs = 0x50, ++ .clr_ofs = 0x54, ++ .sta_ofs = 0x58, ++}; ++ ++static const struct mtk_gate_regs infra_3_cg_regs = { ++ .set_ofs = 0x60, ++ .clr_ofs = 0x64, ++ .sta_ofs = 0x68, ++}; ++ ++#define GATE_INFRA0(_id, _name, _parent, _shift) \ ++ { \ ++ .id = _id, .parent = _parent, .regs = &infra_0_cg_regs, \ ++ .shift = _shift, \ ++ .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \ ++ } ++ ++#define GATE_INFRA1(_id, _name, _parent, _shift) \ ++ { \ ++ .id = _id, .parent = _parent, .regs = &infra_1_cg_regs, \ ++ .shift = _shift, \ ++ .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \ ++ } ++ ++#define GATE_INFRA2(_id, _name, _parent, _shift) \ ++ { \ ++ .id = _id, .parent = _parent, .regs = &infra_2_cg_regs, \ ++ .shift = _shift, \ ++ .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \ ++ } ++ ++#define GATE_INFRA3(_id, _name, _parent, _shift) \ ++ { \ ++ .id = _id, .parent = _parent, .regs = &infra_3_cg_regs, \ ++ .shift = _shift, \ ++ .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \ ++ } ++ ++/* INFRA GATE */ ++static const struct mtk_gate infracfg_mtk_gates[] = { ++ GATE_INFRA1(CK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck", ++ CK_INFRA_66M_MCK, 0), ++ GATE_INFRA1(CK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck", ++ CK_INFRA_66M_MCK, 1), ++ GATE_INFRA1(CK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck", ++ CK_INFRA_PWM_SEL, 2), ++ GATE_INFRA1(CK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1", ++ CK_INFRA_PWM_CK1_SEL, 3), ++ GATE_INFRA1(CK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2", ++ CK_INFRA_PWM_CK2_SEL, 4), ++ GATE_INFRA1(CK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3", ++ CK_INFRA_PWM_CK3_SEL, 5), ++ GATE_INFRA1(CK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4", ++ CK_INFRA_PWM_CK4_SEL, 6), ++ GATE_INFRA1(CK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5", ++ CK_INFRA_PWM_CK5_SEL, 7), ++ GATE_INFRA1(CK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6", ++ CK_INFRA_PWM_CK6_SEL, 8), ++ GATE_INFRA1(CK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7", ++ CK_INFRA_PWM_CK7_SEL, 9), ++ GATE_INFRA1(CK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8", ++ CK_INFRA_PWM_CK8_SEL, 10), ++ GATE_INFRA1(CK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck", ++ CK_INFRA_133M_MCK, 12), ++ GATE_INFRA1(CK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck", ++ CK_INFRA_66M_PHCK, 13), ++ GATE_INFRA1(CK_INFRA_AUD_26M, "infra_f_faud_26m", CK_INFRA_CK_F26M, 14), ++ GATE_INFRA1(CK_INFRA_AUD_L, "infra_f_faud_l", CK_INFRA_FAUD_L_O, 15), ++ GATE_INFRA1(CK_INFRA_AUD_AUD, "infra_f_aud_aud", CK_INFRA_FAUD_AUD_O, ++ 16), ++ GATE_INFRA1(CK_INFRA_AUD_EG2, "infra_f_faud_eg2", CK_INFRA_FAUD_EG2_O, ++ 18), ++ GATE_INFRA1(CK_INFRA_DRAMC_F26M, "infra_dramc_f26m", CK_INFRA_CK_F26M, ++ 19), ++ GATE_INFRA1(CK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm", ++ CK_INFRA_133M_MCK, 20), ++ GATE_INFRA1(CK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck", ++ CK_INFRA_66M_MCK, 21), ++ GATE_INFRA1(CK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck", ++ CK_INFRA_66M_MCK, 29), ++ GATE_INFRA1(CK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m", ++ CK_INFRA_CK_F26M, 30), ++ GATE_INFRA1(CK_INFRA_66M_TRNG, "infra_hf_66m_trng", CK_INFRA_PERI_66M_O, ++ 31), ++ GATE_INFRA2(CK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system", ++ CK_INFRA_CK_F26M, 0), ++ GATE_INFRA2(CK_INFRA_I2C_BCK, "infra_i2c_bck", CK_INFRA_I2C_O, 1), ++ GATE_INFRA2(CK_INFRA_66M_UART0_PCK, "infra_hf_66m_uart0_pck", ++ CK_INFRA_66M_MCK, 3), ++ GATE_INFRA2(CK_INFRA_66M_UART1_PCK, "infra_hf_66m_uart1_pck", ++ CK_INFRA_66M_MCK, 4), ++ GATE_INFRA2(CK_INFRA_66M_UART2_PCK, "infra_hf_66m_uart2_pck", ++ CK_INFRA_66M_MCK, 5), ++ GATE_INFRA2(CK_INFRA_52M_UART0_CK, "infra_f_52m_uart0", ++ CK_INFRA_MUX_UART0_SEL, 3), ++ GATE_INFRA2(CK_INFRA_52M_UART1_CK, "infra_f_52m_uart1", ++ CK_INFRA_MUX_UART1_SEL, 4), ++ GATE_INFRA2(CK_INFRA_52M_UART2_CK, "infra_f_52m_uart2", ++ CK_INFRA_MUX_UART2_SEL, 5), ++ GATE_INFRA2(CK_INFRA_NFI, "infra_f_fnfi", CK_INFRA_NFI_O, 9), ++ GATE_INFRA2(CK_INFRA_SPINFI, "infra_f_fspinfi", CK_INFRA_SPINFI_O, 10), ++ GATE_INFRA2(CK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", ++ CK_INFRA_66M_MCK, 11), ++ GATE_INFRA2(CK_INFRA_104M_SPI0, "infra_hf_104m_spi0", ++ CK_INFRA_MUX_SPI0_SEL, 12), ++ GATE_INFRA2(CK_INFRA_104M_SPI1, "infra_hf_104m_spi1", ++ CK_INFRA_MUX_SPI1_SEL, 13), ++ GATE_INFRA2(CK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck", ++ CK_INFRA_MUX_SPI2_SEL, 14), ++ GATE_INFRA2(CK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", ++ CK_INFRA_66M_MCK, 15), ++ GATE_INFRA2(CK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck", ++ CK_INFRA_66M_MCK, 16), ++ GATE_INFRA2(CK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck", ++ CK_INFRA_66M_MCK, 17), ++ GATE_INFRA2(CK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", ++ CK_INFRA_66M_MCK, 18), ++ GATE_INFRA2(CK_INFRA_RTC, "infra_f_frtc", CK_INFRA_LB_MUX_FRTC, 19), ++ GATE_INFRA2(CK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck", ++ CK_INFRA_F26M_O1, 20), ++ GATE_INFRA2(CK_INFRA_RC_ADC, "infra_f_frc_adc", CK_INFRA_26M_ADC_BCK, ++ 21), ++ GATE_INFRA2(CK_INFRA_MSDC400, "infra_f_fmsdc400", CK_INFRA_FMSDC400_O, ++ 22), ++ GATE_INFRA2(CK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", ++ CK_INFRA_FMSDC2_HCK_OCC, 23), ++ GATE_INFRA2(CK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck", ++ CK_INFRA_PERI_133M, 24), ++ GATE_INFRA2(CK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck", ++ CK_INFRA_66M_PHCK, 25), ++ GATE_INFRA2(CK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck", ++ CK_INFRA_133M_MCK, 26), ++ GATE_INFRA2(CK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", CK_INFRA_NFI_O, ++ 27), ++ GATE_INFRA2(CK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1", ++ CK_INFRA_133M_MCK, 29), ++ GATE_INFRA2(CK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1", ++ CK_INFRA_66M_PHCK, 31), ++ GATE_INFRA3(CK_INFRA_133M_USB_HCK, "infra_133m_usb_hck", ++ CK_INFRA_133M_PHCK, 0), ++ GATE_INFRA3(CK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1", ++ CK_INFRA_133M_PHCK, 1), ++ GATE_INFRA3(CK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", ++ CK_INFRA_66M_PHCK, 2), ++ GATE_INFRA3(CK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1", ++ CK_INFRA_66M_PHCK, 3), ++ GATE_INFRA3(CK_INFRA_USB_SYS, "infra_usb_sys", CK_INFRA_USB_SYS_O, 4), ++ GATE_INFRA3(CK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1", ++ CK_INFRA_USB_SYS_O_P1, 5), ++ GATE_INFRA3(CK_INFRA_USB_REF, "infra_usb_ref", CK_INFRA_USB_O, 6), ++ GATE_INFRA3(CK_INFRA_USB_CK_P1, "infra_usb_ck_p1", CK_INFRA_USB_O_P1, ++ 7), ++ GATE_INFRA3(CK_INFRA_USB_FRMCNT, "infra_usb_frmcnt", ++ CK_INFRA_USB_FRMCNT_O, 8), ++ GATE_INFRA3(CK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1", ++ CK_INFRA_USB_FRMCNT_O_P1, 9), ++ GATE_INFRA3(CK_INFRA_USB_PIPE, "infra_usb_pipe", CK_INFRA_USB_PIPE_O, ++ 10), ++ GATE_INFRA3(CK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", ++ CK_INFRA_USB_PIPE_O_P1, 11), ++ GATE_INFRA3(CK_INFRA_USB_UTMI, "infra_usb_utmi", CK_INFRA_USB_UTMI_O, ++ 12), ++ GATE_INFRA3(CK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1", ++ CK_INFRA_USB_UTMI_O_P1, 13), ++ GATE_INFRA3(CK_INFRA_USB_XHCI, "infra_usb_xhci", CK_INFRA_USB_XHCI_O, ++ 14), ++ GATE_INFRA3(CK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1", ++ CK_INFRA_USB_XHCI_O_P1, 15), ++ GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0", ++ CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, 20), ++ GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1", ++ CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, 21), ++ GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2", ++ CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, 22), ++ GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3", ++ CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, 23), ++ GATE_INFRA3(CK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0", ++ CK_INFRA_PCIE_PIPE_OCC_P0, 24), ++ GATE_INFRA3(CK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1", ++ CK_INFRA_PCIE_PIPE_OCC_P1, 25), ++ GATE_INFRA3(CK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2", ++ CK_INFRA_PCIE_PIPE_OCC_P2, 26), ++ GATE_INFRA3(CK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3", ++ CK_INFRA_PCIE_PIPE_OCC_P3, 27), ++ GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0", ++ CK_INFRA_133M_PHCK, 28), ++ GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1", ++ CK_INFRA_133M_PHCK, 29), ++ GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2", ++ CK_INFRA_133M_PHCK, 30), ++ GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", ++ CK_INFRA_133M_PHCK, 31), ++ GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P0, ++ "infra_pcie_peri_ck_26m_ck_p0", CK_INFRA_F26M_O0, 7), ++ GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P1, ++ "infra_pcie_peri_ck_26m_ck_p1", CK_INFRA_F26M_O0, 8), ++ GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P2, ++ "infra_pcie_peri_ck_26m_ck_p2", CK_INFRA_F26M_O0, 9), ++ GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P3, ++ "infra_pcie_peri_ck_26m_ck_p3", CK_INFRA_F26M_O0, 10), ++}; ++ ++static const struct mtk_clk_tree mt7988_fixed_pll_clk_tree = { ++ .fdivs_offs = ARRAY_SIZE(apmixedsys_mtk_plls), ++ .fclks = apmixedsys_mtk_plls, ++ .xtal_rate = 40 * MHZ, ++}; ++ ++static const struct mtk_clk_tree mt7988_topckgen_clk_tree = { ++ .fdivs_offs = CK_TOP_CB_CKSQ_40M, ++ .muxes_offs = CK_TOP_NETSYS_SEL, ++ .fdivs = topckgen_mtk_fixed_factors, ++ .muxes = topckgen_mtk_muxes, ++ .flags = CLK_BYPASS_XTAL, ++ .xtal_rate = 40 * MHZ, ++}; ++ ++static const struct mtk_clk_tree mt7988_infracfg_clk_tree = { ++ .fdivs_offs = CK_INFRA_CK_F26M, ++ .muxes_offs = CK_INFRA_MUX_UART0_SEL, ++ .fdivs = infracfg_mtk_fixed_factor, ++ .muxes = infracfg_mtk_mux, ++ .flags = CLK_BYPASS_XTAL, ++ .xtal_rate = 40 * MHZ, ++}; ++ ++static const struct udevice_id mt7988_fixed_pll_compat[] = { ++ { .compatible = "mediatek,mt7988-fixed-plls" }, ++ {} ++}; ++ ++static const struct udevice_id mt7988_topckgen_compat[] = { ++ { .compatible = "mediatek,mt7988-topckgen" }, ++ {} ++}; ++ ++static int mt7988_fixed_pll_probe(struct udevice *dev) ++{ ++ return mtk_common_clk_init(dev, &mt7988_fixed_pll_clk_tree); ++} ++ ++static int mt7988_topckgen_probe(struct udevice *dev) ++{ ++ struct mtk_clk_priv *priv = dev_get_priv(dev); ++ ++ priv->base = dev_read_addr_ptr(dev); ++ if (!priv->base) ++ return -ENOENT; ++ ++ writel(MT7988_CLK_PDN_EN_WRITE, priv->base + MT7988_CLK_PDN); ++ return mtk_common_clk_init(dev, &mt7988_topckgen_clk_tree); ++} ++ ++U_BOOT_DRIVER(mtk_clk_apmixedsys) = { ++ .name = "mt7988-clock-fixed-pll", ++ .id = UCLASS_CLK, ++ .of_match = mt7988_fixed_pll_compat, ++ .probe = mt7988_fixed_pll_probe, ++ .priv_auto = sizeof(struct mtk_clk_priv), ++ .ops = &mtk_clk_topckgen_ops, ++ .flags = DM_FLAG_PRE_RELOC, ++}; ++ ++U_BOOT_DRIVER(mtk_clk_topckgen) = { ++ .name = "mt7988-clock-topckgen", ++ .id = UCLASS_CLK, ++ .of_match = mt7988_topckgen_compat, ++ .probe = mt7988_topckgen_probe, ++ .priv_auto = sizeof(struct mtk_clk_priv), ++ .ops = &mtk_clk_topckgen_ops, ++ .flags = DM_FLAG_PRE_RELOC, ++}; ++ ++static const struct udevice_id mt7988_infracfg_compat[] = { ++ { .compatible = "mediatek,mt7988-infracfg" }, ++ {} ++}; ++ ++static const struct udevice_id mt7988_infracfg_ao_cgs_compat[] = { ++ { .compatible = "mediatek,mt7988-infracfg_ao_cgs" }, ++ {} ++}; ++ ++static int mt7988_infracfg_probe(struct udevice *dev) ++{ ++ return mtk_common_clk_init(dev, &mt7988_infracfg_clk_tree); ++} ++ ++static int mt7988_infracfg_ao_cgs_probe(struct udevice *dev) ++{ ++ return mtk_common_clk_gate_init(dev, &mt7988_infracfg_clk_tree, ++ infracfg_mtk_gates); ++} ++ ++U_BOOT_DRIVER(mtk_clk_infracfg) = { ++ .name = "mt7988-clock-infracfg", ++ .id = UCLASS_CLK, ++ .of_match = mt7988_infracfg_compat, ++ .probe = mt7988_infracfg_probe, ++ .priv_auto = sizeof(struct mtk_clk_priv), ++ .ops = &mtk_clk_infrasys_ops, ++ .flags = DM_FLAG_PRE_RELOC, ++}; ++ ++U_BOOT_DRIVER(mtk_clk_infracfg_ao_cgs) = { ++ .name = "mt7988-clock-infracfg_ao_cgs", ++ .id = UCLASS_CLK, ++ .of_match = mt7988_infracfg_ao_cgs_compat, ++ .probe = mt7988_infracfg_ao_cgs_probe, ++ .priv_auto = sizeof(struct mtk_cg_priv), ++ .ops = &mtk_clk_gate_ops, ++ .flags = DM_FLAG_PRE_RELOC, ++}; ++ ++/* ETHDMA */ ++ ++static const struct mtk_gate_regs ethdma_cg_regs = { ++ .set_ofs = 0x30, ++ .clr_ofs = 0x30, ++ .sta_ofs = 0x30, ++}; ++ ++#define GATE_ETHDMA(_id, _name, _parent, _shift) \ ++ { \ ++ .id = _id, .parent = _parent, .regs = ðdma_cg_regs, \ ++ .shift = _shift, \ ++ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ ++ } ++ ++static const struct mtk_gate ethdma_mtk_gate[] = { ++ GATE_ETHDMA(CK_ETHDMA_FE_EN, "ethdma_fe_en", CK_TOP_NETSYS_2X, 6), ++}; ++ ++static int mt7988_ethdma_probe(struct udevice *dev) ++{ ++ return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree, ++ ethdma_mtk_gate); ++} ++ ++static int mt7988_ethdma_bind(struct udevice *dev) ++{ ++ int ret = 0; ++ ++ if (CONFIG_IS_ENABLED(RESET_MEDIATEK)) { ++ ret = mediatek_reset_bind(dev, MT7988_ETHDMA_RST_CTRL_OFS, 1); ++ if (ret) ++ debug("Warning: failed to bind reset controller\n"); ++ } ++ ++ return ret; ++} ++ ++static const struct udevice_id mt7988_ethdma_compat[] = { ++ { ++ .compatible = "mediatek,mt7988-ethdma", ++ }, ++ {} ++}; ++ ++U_BOOT_DRIVER(mtk_clk_ethdma) = { ++ .name = "mt7988-clock-ethdma", ++ .id = UCLASS_CLK, ++ .of_match = mt7988_ethdma_compat, ++ .probe = mt7988_ethdma_probe, ++ .bind = mt7988_ethdma_bind, ++ .priv_auto = sizeof(struct mtk_cg_priv), ++ .ops = &mtk_clk_gate_ops, ++}; ++ ++/* SGMIISYS_0 */ ++ ++static const struct mtk_gate_regs sgmii0_cg_regs = { ++ .set_ofs = 0xE4, ++ .clr_ofs = 0xE4, ++ .sta_ofs = 0xE4, ++}; ++ ++#define GATE_SGMII0(_id, _name, _parent, _shift) \ ++ { \ ++ .id = _id, .parent = _parent, .regs = &sgmii0_cg_regs, \ ++ .shift = _shift, \ ++ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ ++ } ++ ++static const struct mtk_gate sgmiisys_0_mtk_gate[] = { ++ /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */ ++ GATE_SGMII0(CK_SGM0_TX_EN, "sgm0_tx_en", CK_TOP_CB_CKSQ_40M, 2), ++ /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */ ++ GATE_SGMII0(CK_SGM0_RX_EN, "sgm0_rx_en", CK_TOP_CB_CKSQ_40M, 3), ++}; ++ ++static int mt7988_sgmiisys_0_probe(struct udevice *dev) ++{ ++ return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree, ++ sgmiisys_0_mtk_gate); ++} ++ ++static const struct udevice_id mt7988_sgmiisys_0_compat[] = { ++ { ++ .compatible = "mediatek,mt7988-sgmiisys_0", ++ }, ++ {} ++}; ++ ++U_BOOT_DRIVER(mtk_clk_sgmiisys_0) = { ++ .name = "mt7988-clock-sgmiisys_0", ++ .id = UCLASS_CLK, ++ .of_match = mt7988_sgmiisys_0_compat, ++ .probe = mt7988_sgmiisys_0_probe, ++ .priv_auto = sizeof(struct mtk_cg_priv), ++ .ops = &mtk_clk_gate_ops, ++}; ++ ++/* SGMIISYS_1 */ ++ ++static const struct mtk_gate_regs sgmii1_cg_regs = { ++ .set_ofs = 0xE4, ++ .clr_ofs = 0xE4, ++ .sta_ofs = 0xE4, ++}; ++ ++#define GATE_SGMII1(_id, _name, _parent, _shift) \ ++ { \ ++ .id = _id, .parent = _parent, .regs = &sgmii1_cg_regs, \ ++ .shift = _shift, \ ++ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ ++ } ++ ++static const struct mtk_gate sgmiisys_1_mtk_gate[] = { ++ /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */ ++ GATE_SGMII1(CK_SGM1_TX_EN, "sgm1_tx_en", CK_TOP_CB_CKSQ_40M, 2), ++ /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */ ++ GATE_SGMII1(CK_SGM1_RX_EN, "sgm1_rx_en", CK_TOP_CB_CKSQ_40M, 3), ++}; ++ ++static int mt7988_sgmiisys_1_probe(struct udevice *dev) ++{ ++ return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree, ++ sgmiisys_1_mtk_gate); ++} ++ ++static const struct udevice_id mt7988_sgmiisys_1_compat[] = { ++ { ++ .compatible = "mediatek,mt7988-sgmiisys_1", ++ }, ++ {} ++}; ++ ++U_BOOT_DRIVER(mtk_clk_sgmiisys_1) = { ++ .name = "mt7988-clock-sgmiisys_1", ++ .id = UCLASS_CLK, ++ .of_match = mt7988_sgmiisys_1_compat, ++ .probe = mt7988_sgmiisys_1_probe, ++ .priv_auto = sizeof(struct mtk_cg_priv), ++ .ops = &mtk_clk_gate_ops, ++}; ++ ++/* ETHWARP */ ++ ++static const struct mtk_gate_regs ethwarp_cg_regs = { ++ .set_ofs = 0x14, ++ .clr_ofs = 0x14, ++ .sta_ofs = 0x14, ++}; ++ ++#define GATE_ETHWARP(_id, _name, _parent, _shift) \ ++ { \ ++ .id = _id, .parent = _parent, .regs = ðwarp_cg_regs, \ ++ .shift = _shift, \ ++ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ ++ } ++ ++static const struct mtk_gate ethwarp_mtk_gate[] = { ++ GATE_ETHWARP(CK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en", ++ CK_TOP_NETSYS_WED_MCU, 13), ++ GATE_ETHWARP(CK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en", ++ CK_TOP_NETSYS_WED_MCU, 14), ++ GATE_ETHWARP(CK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en", ++ CK_TOP_NETSYS_WED_MCU, 15), ++}; ++ ++static int mt7988_ethwarp_probe(struct udevice *dev) ++{ ++ return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree, ++ ethwarp_mtk_gate); ++} ++ ++static int mt7988_ethwarp_bind(struct udevice *dev) ++{ ++ int ret = 0; ++ ++ if (CONFIG_IS_ENABLED(RESET_MEDIATEK)) { ++ ret = mediatek_reset_bind(dev, MT7988_ETHWARP_RST_CTRL_OFS, 2); ++ if (ret) ++ debug("Warning: failed to bind reset controller\n"); ++ } ++ ++ return ret; ++} ++ ++static const struct udevice_id mt7988_ethwarp_compat[] = { ++ { ++ .compatible = "mediatek,mt7988-ethwarp", ++ }, ++ {} ++}; ++ ++U_BOOT_DRIVER(mtk_clk_ethwarp) = { ++ .name = "mt7988-clock-ethwarp", ++ .id = UCLASS_CLK, ++ .of_match = mt7988_ethwarp_compat, ++ .probe = mt7988_ethwarp_probe, ++ .bind = mt7988_ethwarp_bind, ++ .priv_auto = sizeof(struct mtk_cg_priv), ++ .ops = &mtk_clk_gate_ops, ++}; +--- /dev/null ++++ b/include/dt-bindings/clock/mt7988-clk.h +@@ -0,0 +1,349 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2022 MediaTek Inc. All rights reserved. ++ * ++ * Author: Sam Shih ++ */ ++ ++#ifndef _DT_BINDINGS_CLK_MT7988_H ++#define _DT_BINDINGS_CLK_MT7988_H ++ ++/* INFRACFG */ ++/* mtk_fixed_factor */ ++#define CK_INFRA_CK_F26M 0 ++#define CK_INFRA_PWM_O 1 ++#define CK_INFRA_PCIE_OCC_P0 2 ++#define CK_INFRA_PCIE_OCC_P1 3 ++#define CK_INFRA_PCIE_OCC_P2 4 ++#define CK_INFRA_PCIE_OCC_P3 5 ++#define CK_INFRA_133M_HCK 6 ++#define CK_INFRA_133M_PHCK 7 ++#define CK_INFRA_66M_PHCK 8 ++#define CK_INFRA_FAUD_L_O 9 ++#define CK_INFRA_FAUD_AUD_O 10 ++#define CK_INFRA_FAUD_EG2_O 11 ++#define CK_INFRA_I2C_O 12 ++#define CK_INFRA_UART_O0 13 ++#define CK_INFRA_UART_O1 14 ++#define CK_INFRA_UART_O2 15 ++#define CK_INFRA_NFI_O 16 ++#define CK_INFRA_SPINFI_O 17 ++#define CK_INFRA_SPI0_O 18 ++#define CK_INFRA_SPI1_O 19 ++#define CK_INFRA_LB_MUX_FRTC 20 ++#define CK_INFRA_FRTC 21 ++#define CK_INFRA_FMSDC400_O 22 ++#define CK_INFRA_FMSDC2_HCK_OCC 23 ++#define CK_INFRA_PERI_133M 24 ++#define CK_INFRA_USB_O 25 ++#define CK_INFRA_USB_O_P1 26 ++#define CK_INFRA_USB_FRMCNT_O 27 ++#define CK_INFRA_USB_FRMCNT_O_P1 28 ++#define CK_INFRA_USB_XHCI_O 29 ++#define CK_INFRA_USB_XHCI_O_P1 30 ++#define CK_INFRA_USB_PIPE_O 31 ++#define CK_INFRA_USB_PIPE_O_P1 32 ++#define CK_INFRA_USB_UTMI_O 33 ++#define CK_INFRA_USB_UTMI_O_P1 34 ++#define CK_INFRA_PCIE_PIPE_OCC_P0 35 ++#define CK_INFRA_PCIE_PIPE_OCC_P1 36 ++#define CK_INFRA_PCIE_PIPE_OCC_P2 37 ++#define CK_INFRA_PCIE_PIPE_OCC_P3 38 ++#define CK_INFRA_F26M_O0 39 ++#define CK_INFRA_F26M_O1 40 ++#define CK_INFRA_133M_MCK 41 ++#define CK_INFRA_66M_MCK 42 ++#define CK_INFRA_PERI_66M_O 43 ++#define CK_INFRA_USB_SYS_O 44 ++#define CK_INFRA_USB_SYS_O_P1 45 ++ ++/* INFRACFG_AO */ ++#define GATE_OFFSET 65 ++/* mtk_mux */ ++#define CK_INFRA_MUX_UART0_SEL 46 /* Linux CLK ID (0) */ ++#define CK_INFRA_MUX_UART1_SEL 47 /* Linux CLK ID (1) */ ++#define CK_INFRA_MUX_UART2_SEL 48 /* Linux CLK ID (2) */ ++#define CK_INFRA_MUX_SPI0_SEL 49 /* Linux CLK ID (3) */ ++#define CK_INFRA_MUX_SPI1_SEL 50 /* Linux CLK ID (4) */ ++#define CK_INFRA_MUX_SPI2_SEL 51 /* Linux CLK ID (5) */ ++#define CK_INFRA_PWM_SEL 52 /* Linux CLK ID (6) */ ++#define CK_INFRA_PWM_CK1_SEL 53 /* Linux CLK ID (7) */ ++#define CK_INFRA_PWM_CK2_SEL 54 /* Linux CLK ID (8) */ ++#define CK_INFRA_PWM_CK3_SEL 55 /* Linux CLK ID (9) */ ++#define CK_INFRA_PWM_CK4_SEL 56 /* Linux CLK ID (10) */ ++#define CK_INFRA_PWM_CK5_SEL 57 /* Linux CLK ID (11) */ ++#define CK_INFRA_PWM_CK6_SEL 58 /* Linux CLK ID (12) */ ++#define CK_INFRA_PWM_CK7_SEL 59 /* Linux CLK ID (13) */ ++#define CK_INFRA_PWM_CK8_SEL 60 /* Linux CLK ID (14) */ ++#define CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 61 /* Linux CLK ID (15) */ ++#define CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 62 /* Linux CLK ID (16) */ ++#define CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 63 /* Linux CLK ID (17) */ ++#define CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 64 /* Linux CLK ID (18) */ ++/* mtk_gate */ ++#define CK_INFRA_66M_GPT_BCK (65 - GATE_OFFSET) /* Linux CLK ID (19) */ ++#define CK_INFRA_66M_PWM_HCK (66 - GATE_OFFSET) /* Linux CLK ID (20) */ ++#define CK_INFRA_66M_PWM_BCK (67 - GATE_OFFSET) /* Linux CLK ID (21) */ ++#define CK_INFRA_66M_PWM_CK1 (68 - GATE_OFFSET) /* Linux CLK ID (22) */ ++#define CK_INFRA_66M_PWM_CK2 (69 - GATE_OFFSET) /* Linux CLK ID (23) */ ++#define CK_INFRA_66M_PWM_CK3 (70 - GATE_OFFSET) /* Linux CLK ID (24) */ ++#define CK_INFRA_66M_PWM_CK4 (71 - GATE_OFFSET) /* Linux CLK ID (25) */ ++#define CK_INFRA_66M_PWM_CK5 (72 - GATE_OFFSET) /* Linux CLK ID (26) */ ++#define CK_INFRA_66M_PWM_CK6 (73 - GATE_OFFSET) /* Linux CLK ID (27) */ ++#define CK_INFRA_66M_PWM_CK7 (74 - GATE_OFFSET) /* Linux CLK ID (28) */ ++#define CK_INFRA_66M_PWM_CK8 (75 - GATE_OFFSET) /* Linux CLK ID (29) */ ++#define CK_INFRA_133M_CQDMA_BCK (76 - GATE_OFFSET) /* Linux CLK ID (30) */ ++#define CK_INFRA_66M_AUD_SLV_BCK (77 - GATE_OFFSET) /* Linux CLK ID (31) */ ++#define CK_INFRA_AUD_26M (78 - GATE_OFFSET) /* Linux CLK ID (32) */ ++#define CK_INFRA_AUD_L (79 - GATE_OFFSET) /* Linux CLK ID (33) */ ++#define CK_INFRA_AUD_AUD (80 - GATE_OFFSET) /* Linux CLK ID (34) */ ++#define CK_INFRA_AUD_EG2 (81 - GATE_OFFSET) /* Linux CLK ID (35) */ ++#define CK_INFRA_DRAMC_F26M (82 - GATE_OFFSET) /* Linux CLK ID (36) */ ++#define CK_INFRA_133M_DBG_ACKM (83 - GATE_OFFSET) /* Linux CLK ID (37) */ ++#define CK_INFRA_66M_AP_DMA_BCK (84 - GATE_OFFSET) /* Linux CLK ID (38) */ ++#define CK_INFRA_66M_SEJ_BCK (85 - GATE_OFFSET) /* Linux CLK ID (39) */ ++#define CK_INFRA_PRE_CK_SEJ_F13M (86 - GATE_OFFSET) /* Linux CLK ID (40) */ ++#define CK_INFRA_66M_TRNG (87 - GATE_OFFSET) /* Linux CLK ID (41) */ ++#define CK_INFRA_26M_THERM_SYSTEM (88 - GATE_OFFSET) /* Linux CLK ID (42) */ ++#define CK_INFRA_I2C_BCK (89 - GATE_OFFSET) /* Linux CLK ID (43) */ ++#define CK_INFRA_66M_UART0_PCK (90 - GATE_OFFSET) /* Linux CLK ID (44) */ ++#define CK_INFRA_66M_UART1_PCK (91 - GATE_OFFSET) /* Linux CLK ID (45) */ ++#define CK_INFRA_66M_UART2_PCK (92 - GATE_OFFSET) /* Linux CLK ID (46) */ ++#define CK_INFRA_52M_UART0_CK (93 - GATE_OFFSET) /* Linux CLK ID (47) */ ++#define CK_INFRA_52M_UART1_CK (94 - GATE_OFFSET) /* Linux CLK ID (48) */ ++#define CK_INFRA_52M_UART2_CK (95 - GATE_OFFSET) /* Linux CLK ID (49) */ ++#define CK_INFRA_NFI (96 - GATE_OFFSET) /* Linux CLK ID (50) */ ++#define CK_INFRA_SPINFI (97 - GATE_OFFSET) /* Linux CLK ID (51) */ ++#define CK_INFRA_66M_NFI_HCK (98 - GATE_OFFSET) /* Linux CLK ID (52) */ ++#define CK_INFRA_104M_SPI0 (99 - GATE_OFFSET) /* Linux CLK ID (53) */ ++#define CK_INFRA_104M_SPI1 (100 - GATE_OFFSET) /* Linux CLK ID (54) */ ++#define CK_INFRA_104M_SPI2_BCK (101 - GATE_OFFSET) /* Linux CLK ID (55) */ ++#define CK_INFRA_66M_SPI0_HCK (102 - GATE_OFFSET) /* Linux CLK ID (56) */ ++#define CK_INFRA_66M_SPI1_HCK (103 - GATE_OFFSET) /* Linux CLK ID (57) */ ++#define CK_INFRA_66M_SPI2_HCK (104 - GATE_OFFSET) /* Linux CLK ID (58) */ ++#define CK_INFRA_66M_FLASHIF_AXI (105 - GATE_OFFSET) /* Linux CLK ID (59) */ ++#define CK_INFRA_RTC (106 - GATE_OFFSET) /* Linux CLK ID (60) */ ++#define CK_INFRA_26M_ADC_BCK (107 - GATE_OFFSET) /* Linux CLK ID (61) */ ++#define CK_INFRA_RC_ADC (108 - GATE_OFFSET) /* Linux CLK ID (62) */ ++#define CK_INFRA_MSDC400 (109 - GATE_OFFSET) /* Linux CLK ID (63) */ ++#define CK_INFRA_MSDC2_HCK (110 - GATE_OFFSET) /* Linux CLK ID (64) */ ++#define CK_INFRA_133M_MSDC_0_HCK (111 - GATE_OFFSET) /* Linux CLK ID (65) */ ++#define CK_INFRA_66M_MSDC_0_HCK (112 - GATE_OFFSET) /* Linux CLK ID (66) */ ++#define CK_INFRA_133M_CPUM_BCK (113 - GATE_OFFSET) /* Linux CLK ID (67) */ ++#define CK_INFRA_BIST2FPC (114 - GATE_OFFSET) /* Linux CLK ID (68) */ ++#define CK_INFRA_I2C_X16W_MCK_CK_P1 (115 - GATE_OFFSET) /* Linux CLK ID (69) */ ++#define CK_INFRA_I2C_X16W_PCK_CK_P1 (116 - GATE_OFFSET) /* Linux CLK ID (70) */ ++#define CK_INFRA_133M_USB_HCK (117 - GATE_OFFSET) /* Linux CLK ID (71) */ ++#define CK_INFRA_133M_USB_HCK_CK_P1 (118 - GATE_OFFSET) /* Linux CLK ID (72) */ ++#define CK_INFRA_66M_USB_HCK (119 - GATE_OFFSET) /* Linux CLK ID (73) */ ++#define CK_INFRA_66M_USB_HCK_CK_P1 (120 - GATE_OFFSET) /* Linux CLK ID (74) */ ++#define CK_INFRA_USB_SYS (121 - GATE_OFFSET) /* Linux CLK ID (75) */ ++#define CK_INFRA_USB_SYS_CK_P1 (122 - GATE_OFFSET) /* Linux CLK ID (76) */ ++#define CK_INFRA_USB_REF (123 - GATE_OFFSET) /* Linux CLK ID (77) */ ++#define CK_INFRA_USB_CK_P1 (124 - GATE_OFFSET) /* Linux CLK ID (78) */ ++#define CK_INFRA_USB_FRMCNT (125 - GATE_OFFSET) /* Linux CLK ID (79) */ ++#define CK_INFRA_USB_FRMCNT_CK_P1 (126 - GATE_OFFSET) /* Linux CLK ID (80) */ ++#define CK_INFRA_USB_PIPE (127 - GATE_OFFSET) /* Linux CLK ID (81) */ ++#define CK_INFRA_USB_PIPE_CK_P1 (128 - GATE_OFFSET) /* Linux CLK ID (82) */ ++#define CK_INFRA_USB_UTMI (129 - GATE_OFFSET) /* Linux CLK ID (83) */ ++#define CK_INFRA_USB_UTMI_CK_P1 (130 - GATE_OFFSET) /* Linux CLK ID (84) */ ++#define CK_INFRA_USB_XHCI (131 - GATE_OFFSET) /* Linux CLK ID (85) */ ++#define CK_INFRA_USB_XHCI_CK_P1 (132 - GATE_OFFSET) /* Linux CLK ID (86) */ ++#define CK_INFRA_PCIE_GFMUX_TL_P0 (133 - GATE_OFFSET) /* Linux CLK ID (87) */ ++#define CK_INFRA_PCIE_GFMUX_TL_P1 (134 - GATE_OFFSET) /* Linux CLK ID (88) */ ++#define CK_INFRA_PCIE_GFMUX_TL_P2 (135 - GATE_OFFSET) /* Linux CLK ID (89) */ ++#define CK_INFRA_PCIE_GFMUX_TL_P3 (136 - GATE_OFFSET) /* Linux CLK ID (90) */ ++#define CK_INFRA_PCIE_PIPE_P0 (137 - GATE_OFFSET) /* Linux CLK ID (91) */ ++#define CK_INFRA_PCIE_PIPE_P1 (138 - GATE_OFFSET) /* Linux CLK ID (92) */ ++#define CK_INFRA_PCIE_PIPE_P2 (139 - GATE_OFFSET) /* Linux CLK ID (93) */ ++#define CK_INFRA_PCIE_PIPE_P3 (140 - GATE_OFFSET) /* Linux CLK ID (94) */ ++#define CK_INFRA_133M_PCIE_CK_P0 (141 - GATE_OFFSET) /* Linux CLK ID (95) */ ++#define CK_INFRA_133M_PCIE_CK_P1 (142 - GATE_OFFSET) /* Linux CLK ID (96) */ ++#define CK_INFRA_133M_PCIE_CK_P2 (143 - GATE_OFFSET) /* Linux CLK ID (97) */ ++#define CK_INFRA_133M_PCIE_CK_P3 (144 - GATE_OFFSET) /* Linux CLK ID (98) */ ++#define CK_INFRA_PCIE_PERI_26M_CK_P0 (145 - GATE_OFFSET) /* Linux CLK ID (99) */ ++#define CK_INFRA_PCIE_PERI_26M_CK_P1 \ ++ (146 - GATE_OFFSET) /* Linux CLK ID (100) */ ++#define CK_INFRA_PCIE_PERI_26M_CK_P2 \ ++ (147 - GATE_OFFSET) /* Linux CLK ID (101) */ ++#define CK_INFRA_PCIE_PERI_26M_CK_P3 \ ++ (148 - GATE_OFFSET) /* Linux CLK ID (102) */ ++ ++/* TOPCKGEN */ ++/* mtk_fixed_factor */ ++#define CK_TOP_CB_CKSQ_40M 0 /* Linux CLK ID (74) */ ++#define CK_TOP_CB_M_416M 1 /* Linux CLK ID (75) */ ++#define CK_TOP_CB_M_D2 2 /* Linux CLK ID (76) */ ++#define CK_TOP_M_D3_D2 3 /* Linux CLK ID (77) */ ++#define CK_TOP_CB_M_D4 4 /* Linux CLK ID (78) */ ++#define CK_TOP_CB_M_D8 5 /* Linux CLK ID (79) */ ++#define CK_TOP_M_D8_D2 6 /* Linux CLK ID (80) */ ++#define CK_TOP_CB_MM_720M 7 /* Linux CLK ID (81) */ ++#define CK_TOP_CB_MM_D2 8 /* Linux CLK ID (82) */ ++#define CK_TOP_CB_MM_D3_D5 9 /* Linux CLK ID (83) */ ++#define CK_TOP_CB_MM_D4 10 /* Linux CLK ID (84) */ ++#define CK_TOP_MM_D6_D2 11 /* Linux CLK ID (85) */ ++#define CK_TOP_CB_MM_D8 12 /* Linux CLK ID (86) */ ++#define CK_TOP_CB_APLL2_196M 13 /* Linux CLK ID (87) */ ++#define CK_TOP_CB_APLL2_D4 14 /* Linux CLK ID (88) */ ++#define CK_TOP_CB_NET1_D4 15 /* Linux CLK ID (89) */ ++#define CK_TOP_CB_NET1_D5 16 /* Linux CLK ID (90) */ ++#define CK_TOP_NET1_D5_D2 17 /* Linux CLK ID (91) */ ++#define CK_TOP_NET1_D5_D4 18 /* Linux CLK ID (92) */ ++#define CK_TOP_CB_NET1_D8 19 /* Linux CLK ID (93) */ ++#define CK_TOP_NET1_D8_D2 20 /* Linux CLK ID (94) */ ++#define CK_TOP_NET1_D8_D4 21 /* Linux CLK ID (95) */ ++#define CK_TOP_NET1_D8_D8 22 /* Linux CLK ID (96) */ ++#define CK_TOP_NET1_D8_D16 23 /* Linux CLK ID (97) */ ++#define CK_TOP_CB_NET2_800M 24 /* Linux CLK ID (98) */ ++#define CK_TOP_CB_NET2_D2 25 /* Linux CLK ID (99) */ ++#define CK_TOP_CB_NET2_D4 26 /* Linux CLK ID (100) */ ++#define CK_TOP_NET2_D4_D4 27 /* Linux CLK ID (101) */ ++#define CK_TOP_NET2_D4_D8 28 /* Linux CLK ID (102) */ ++#define CK_TOP_CB_NET2_D6 29 /* Linux CLK ID (103) */ ++#define CK_TOP_CB_NET2_D8 30 /* Linux CLK ID (104) */ ++#define CK_TOP_CB_WEDMCU_208M 31 /* Linux CLK ID (105) */ ++#define CK_TOP_CB_SGM_325M 32 /* Linux CLK ID (106) */ ++#define CK_TOP_CB_NETSYS_850M 33 /* Linux CLK ID (107) */ ++#define CK_TOP_CB_MSDC_400M 34 /* Linux CLK ID (108) */ ++#define CK_TOP_CKSQ_40M_D2 35 /* Linux CLK ID (109) */ ++#define CK_TOP_CB_RTC_32K 36 /* Linux CLK ID (110) */ ++#define CK_TOP_CB_RTC_32P7K 37 /* Linux CLK ID (111) */ ++#define CK_TOP_INFRA_F32K 38 /* Linux CLK ID (112) */ ++#define CK_TOP_CKSQ_SRC 39 /* Linux CLK ID (113) */ ++#define CK_TOP_NETSYS_2X 40 /* Linux CLK ID (114) */ ++#define CK_TOP_NETSYS_GSW 41 /* Linux CLK ID (115) */ ++#define CK_TOP_NETSYS_WED_MCU 42 /* Linux CLK ID (116) */ ++#define CK_TOP_EIP197 43 /* Linux CLK ID (117) */ ++#define CK_TOP_EMMC_250M 44 /* Linux CLK ID (118) */ ++#define CK_TOP_EMMC_400M 45 /* Linux CLK ID (119) */ ++#define CK_TOP_SPI 46 /* Linux CLK ID (120) */ ++#define CK_TOP_SPIM_MST 47 /* Linux CLK ID (121) */ ++#define CK_TOP_NFI1X 48 /* Linux CLK ID (122) */ ++#define CK_TOP_SPINFI_BCK 49 /* Linux CLK ID (123) */ ++#define CK_TOP_I2C_BCK 50 /* Linux CLK ID (124) */ ++#define CK_TOP_USB_SYS 51 /* Linux CLK ID (125) */ ++#define CK_TOP_USB_SYS_P1 52 /* Linux CLK ID (126) */ ++#define CK_TOP_USB_XHCI 53 /* Linux CLK ID (127) */ ++#define CK_TOP_USB_XHCI_P1 54 /* Linux CLK ID (128) */ ++#define CK_TOP_USB_FRMCNT 55 /* Linux CLK ID (129) */ ++#define CK_TOP_USB_FRMCNT_P1 56 /* Linux CLK ID (130) */ ++#define CK_TOP_AUD 57 /* Linux CLK ID (131) */ ++#define CK_TOP_A1SYS 58 /* Linux CLK ID (132) */ ++#define CK_TOP_AUD_L 59 /* Linux CLK ID (133) */ ++#define CK_TOP_A_TUNER 60 /* Linux CLK ID (134) */ ++#define CK_TOP_SYSAXI 61 /* Linux CLK ID (135) */ ++#define CK_TOP_INFRA_F26M 62 /* Linux CLK ID (136) */ ++#define CK_TOP_USB_REF 63 /* Linux CLK ID (137) */ ++#define CK_TOP_USB_CK_P1 64 /* Linux CLK ID (138) */ ++/* mtk_mux */ ++#define CK_TOP_NETSYS_SEL 65 /* Linux CLK ID (0) */ ++#define CK_TOP_NETSYS_500M_SEL 66 /* Linux CLK ID (1) */ ++#define CK_TOP_NETSYS_2X_SEL 67 /* Linux CLK ID (2) */ ++#define CK_TOP_NETSYS_GSW_SEL 68 /* Linux CLK ID (3) */ ++#define CK_TOP_ETH_GMII_SEL 69 /* Linux CLK ID (4) */ ++#define CK_TOP_NETSYS_MCU_SEL 70 /* Linux CLK ID (5) */ ++#define CK_TOP_NETSYS_PAO_2X_SEL 71 /* Linux CLK ID (6) */ ++#define CK_TOP_EIP197_SEL 72 /* Linux CLK ID (7) */ ++#define CK_TOP_AXI_INFRA_SEL 73 /* Linux CLK ID (8) */ ++#define CK_TOP_UART_SEL 74 /* Linux CLK ID (9) */ ++#define CK_TOP_EMMC_250M_SEL 75 /* Linux CLK ID (10) */ ++#define CK_TOP_EMMC_400M_SEL 76 /* Linux CLK ID (11) */ ++#define CK_TOP_SPI_SEL 77 /* Linux CLK ID (12) */ ++#define CK_TOP_SPIM_MST_SEL 78 /* Linux CLK ID (13) */ ++#define CK_TOP_NFI1X_SEL 79 /* Linux CLK ID (14) */ ++#define CK_TOP_SPINFI_SEL 80 /* Linux CLK ID (15) */ ++#define CK_TOP_PWM_SEL 81 /* Linux CLK ID (16) */ ++#define CK_TOP_I2C_SEL 82 /* Linux CLK ID (17) */ ++#define CK_TOP_PCIE_MBIST_250M_SEL 83 /* Linux CLK ID (18) */ ++#define CK_TOP_PEXTP_TL_SEL 84 /* Linux CLK ID (19) */ ++#define CK_TOP_PEXTP_TL_P1_SEL 85 /* Linux CLK ID (20) */ ++#define CK_TOP_PEXTP_TL_P2_SEL 86 /* Linux CLK ID (21) */ ++#define CK_TOP_PEXTP_TL_P3_SEL 87 /* Linux CLK ID (22) */ ++#define CK_TOP_USB_SYS_SEL 88 /* Linux CLK ID (23) */ ++#define CK_TOP_USB_SYS_P1_SEL 89 /* Linux CLK ID (24) */ ++#define CK_TOP_USB_XHCI_SEL 90 /* Linux CLK ID (25) */ ++#define CK_TOP_USB_XHCI_P1_SEL 91 /* Linux CLK ID (26) */ ++#define CK_TOP_USB_FRMCNT_SEL 92 /* Linux CLK ID (27) */ ++#define CK_TOP_USB_FRMCNT_P1_SEL 93 /* Linux CLK ID (28) */ ++#define CK_TOP_AUD_SEL 94 /* Linux CLK ID (29) */ ++#define CK_TOP_A1SYS_SEL 95 /* Linux CLK ID (30) */ ++#define CK_TOP_AUD_L_SEL 96 /* Linux CLK ID (31) */ ++#define CK_TOP_A_TUNER_SEL 97 /* Linux CLK ID (32) */ ++#define CK_TOP_SSPXTP_SEL 98 /* Linux CLK ID (33) */ ++#define CK_TOP_USB_PHY_SEL 99 /* Linux CLK ID (34) */ ++#define CK_TOP_USXGMII_SBUS_0_SEL 100 /* Linux CLK ID (35) */ ++#define CK_TOP_USXGMII_SBUS_1_SEL 101 /* Linux CLK ID (36) */ ++#define CK_TOP_SGM_0_SEL 102 /* Linux CLK ID (37) */ ++#define CK_TOP_SGM_SBUS_0_SEL 103 /* Linux CLK ID (38) */ ++#define CK_TOP_SGM_1_SEL 104 /* Linux CLK ID (39) */ ++#define CK_TOP_SGM_SBUS_1_SEL 105 /* Linux CLK ID (40) */ ++#define CK_TOP_XFI_PHY_0_XTAL_SEL 106 /* Linux CLK ID (41) */ ++#define CK_TOP_XFI_PHY_1_XTAL_SEL 107 /* Linux CLK ID (42) */ ++#define CK_TOP_SYSAXI_SEL 108 /* Linux CLK ID (43) */ ++#define CK_TOP_SYSAPB_SEL 109 /* Linux CLK ID (44) */ ++#define CK_TOP_ETH_REFCK_50M_SEL 110 /* Linux CLK ID (45) */ ++#define CK_TOP_ETH_SYS_200M_SEL 111 /* Linux CLK ID (46) */ ++#define CK_TOP_ETH_SYS_SEL 112 /* Linux CLK ID (47) */ ++#define CK_TOP_ETH_XGMII_SEL 113 /* Linux CLK ID (48) */ ++#define CK_TOP_BUS_TOPS_SEL 114 /* Linux CLK ID (49) */ ++#define CK_TOP_NPU_TOPS_SEL 115 /* Linux CLK ID (50) */ ++#define CK_TOP_DRAMC_SEL 116 /* Linux CLK ID (51) */ ++#define CK_TOP_DRAMC_MD32_SEL 117 /* Linux CLK ID (52) */ ++#define CK_TOP_INFRA_F26M_SEL 118 /* Linux CLK ID (53) */ ++#define CK_TOP_PEXTP_P0_SEL 119 /* Linux CLK ID (54) */ ++#define CK_TOP_PEXTP_P1_SEL 120 /* Linux CLK ID (55) */ ++#define CK_TOP_PEXTP_P2_SEL 121 /* Linux CLK ID (56) */ ++#define CK_TOP_PEXTP_P3_SEL 122 /* Linux CLK ID (57) */ ++#define CK_TOP_DA_XTP_GLB_P0_SEL 123 /* Linux CLK ID (58) */ ++#define CK_TOP_DA_XTP_GLB_P1_SEL 124 /* Linux CLK ID (59) */ ++#define CK_TOP_DA_XTP_GLB_P2_SEL 125 /* Linux CLK ID (60) */ ++#define CK_TOP_DA_XTP_GLB_P3_SEL 126 /* Linux CLK ID (61) */ ++#define CK_TOP_CKM_SEL 127 /* Linux CLK ID (62) */ ++#define CK_TOP_DA_SELM_XTAL_SEL 128 /* Linux CLK ID (63) */ ++#define CK_TOP_PEXTP_SEL 129 /* Linux CLK ID (64) */ ++#define CK_TOP_TOPS_P2_26M_SEL 130 /* Linux CLK ID (65) */ ++#define CK_TOP_MCUSYS_BACKUP_625M_SEL 131 /* Linux CLK ID (66) */ ++#define CK_TOP_NETSYS_SYNC_250M_SEL 132 /* Linux CLK ID (67) */ ++#define CK_TOP_MACSEC_SEL 133 /* Linux CLK ID (68) */ ++#define CK_TOP_NETSYS_TOPS_400M_SEL 134 /* Linux CLK ID (69) */ ++#define CK_TOP_NETSYS_PPEFB_250M_SEL 135 /* Linux CLK ID (70) */ ++#define CK_TOP_NETSYS_WARP_SEL 136 /* Linux CLK ID (71) */ ++#define CK_TOP_ETH_MII_SEL 137 /* Linux CLK ID (72) */ ++#define CK_TOP_CK_NPU_SEL_CM_TOPS_SEL 138 /* Linux CLK ID (73) */ ++ ++/* APMIXEDSYS */ ++/* mtk_pll_data */ ++#define CK_APMIXED_NETSYSPLL 0 ++#define CK_APMIXED_MPLL 1 ++#define CK_APMIXED_MMPLL 2 ++#define CK_APMIXED_APLL2 3 ++#define CK_APMIXED_NET1PLL 4 ++#define CK_APMIXED_NET2PLL 5 ++#define CK_APMIXED_WEDMCUPLL 6 ++#define CK_APMIXED_SGMPLL 7 ++#define CK_APMIXED_ARM_B 8 ++#define CK_APMIXED_CCIPLL2_B 9 ++#define CK_APMIXED_USXGMIIPLL 10 ++#define CK_APMIXED_MSDCPLL 11 ++ ++/* ETHSYS ETH DMA */ ++/* mtk_gate */ ++#define CK_ETHDMA_FE_EN 0 ++ ++/* SGMIISYS_0 */ ++/* mtk_gate */ ++#define CK_SGM0_TX_EN 0 ++#define CK_SGM0_RX_EN 1 ++ ++/* SGMIISYS_1 */ ++/* mtk_gate */ ++#define CK_SGM1_TX_EN 0 ++#define CK_SGM1_RX_EN 1 ++ ++/* ETHWARP */ ++/* mtk_gate */ ++#define CK_ETHWARP_WOCPU2_EN 0 ++#define CK_ETHWARP_WOCPU1_EN 1 ++#define CK_ETHWARP_WOCPU0_EN 2 ++ ++#endif /* _DT_BINDINGS_CLK_MT7988_H */ diff --git a/package/boot/uboot-mediatek/patches/101-11-reset-mediatek-add-reset-definition-for-MediaTek-MT7.patch b/package/boot/uboot-mediatek/patches/101-11-reset-mediatek-add-reset-definition-for-MediaTek-MT7.patch new file mode 100644 index 00000000000..f14c3836387 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/101-11-reset-mediatek-add-reset-definition-for-MediaTek-MT7.patch @@ -0,0 +1,49 @@ +From b4a308dd31a7c6754be230849a5e430052268b9c Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 19 Jul 2023 17:16:33 +0800 +Subject: [PATCH 11/29] reset: mediatek: add reset definition for MediaTek + MT7988 SoC + +This patch adds reset bits for MediaTek MT7988 + +Signed-off-by: Sam Shih +Signed-off-by: Weijie Gao +--- + include/dt-bindings/reset/mt7988-reset.h | 31 ++++++++++++++++++++++++ + 1 file changed, 31 insertions(+) + create mode 100644 include/dt-bindings/reset/mt7988-reset.h + +--- /dev/null ++++ b/include/dt-bindings/reset/mt7988-reset.h +@@ -0,0 +1,31 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2023 MediaTek Inc. ++ */ ++ ++#ifndef _DT_BINDINGS_MTK_RESET_H_ ++#define _DT_BINDINGS_MTK_RESET_H_ ++ ++/* ETHDMA Subsystem resets */ ++#define ETHDMA_FE_RST 6 ++#define ETHDMA_PMTR_RST 8 ++#define ETHDMA_GMAC_RST 23 ++#define ETHDMA_WDMA0_RST 24 ++#define ETHDMA_WDMA1_RST 25 ++#define ETHDMA_WDMA2_RST 26 ++#define ETHDMA_PPE0_RST 29 ++#define ETHDMA_PPE1_RST 30 ++#define ETHDMA_PPE2_RST 31 ++ ++/* ETHWARP Subsystem resets */ ++#define ETHWARP_GSW_RST 9 ++#define ETHWARP_EIP197_RST 10 ++#define ETHWARP_WOCPU0_RST 32 ++#define ETHWARP_WOCPU1_RST 33 ++#define ETHWARP_WOCPU2_RST 34 ++#define ETHWARP_WOX_NET_MUX_RST 35 ++#define ETHWARP_WED0_RST 36 ++#define ETHWARP_WED1_RST 37 ++#define ETHWARP_WED2_RST 38 ++ ++#endif /* _DT_BINDINGS_MTK_RESET_H_ */ diff --git a/package/boot/uboot-mediatek/patches/101-12-pinctrl-mediatek-convert-most-definitions-to-const.patch b/package/boot/uboot-mediatek/patches/101-12-pinctrl-mediatek-convert-most-definitions-to-const.patch new file mode 100644 index 00000000000..4085f115419 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/101-12-pinctrl-mediatek-convert-most-definitions-to-const.patch @@ -0,0 +1,2267 @@ +From 30227fcf55ac95ad6778de2fc3e6d1e00cf82566 Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 19 Jul 2023 17:16:37 +0800 +Subject: [PATCH 12/29] pinctrl: mediatek: convert most definitions to const + +There exists a situation of the mediatek pinctrl driver that may return +wrong pin function value for the pinmux driver: +- All pin function arrays are defined without const +- Some pin function arrays contain all-zero value, e.g.: + static int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, }; +- These arrays will be put into .bss section during compilation +- .bss section has no "a" attribute and does not exist in the final binary + file after objcopy. +- FDT binary blob is appended to the u-boot binary, which occupies the + .bss section. +- During board_f stage, .bss has not been initialized, and contains the + data of FDT, which is not full-zero data. +- pinctrl driver is initialized in board_f stage, and it will get wrong + data if another driver is going to set default pinctrl. + +Since pinmux information and soc data are only meant to be read-only, thus +should be declared as const. This will force all pinctrl data being put +into .rodata section. Since .rodata has "a" attribute, even the all-zero +data will be allocated and filled with correct value in to u-boot binary. + +Signed-off-by: Weijie Gao +--- + drivers/pinctrl/mediatek/pinctrl-mt7622.c | 474 ++++++------- + drivers/pinctrl/mediatek/pinctrl-mt7623.c | 650 +++++++++--------- + drivers/pinctrl/mediatek/pinctrl-mt7629.c | 174 ++--- + drivers/pinctrl/mediatek/pinctrl-mt7981.c | 270 ++++---- + drivers/pinctrl/mediatek/pinctrl-mt7986.c | 145 ++-- + drivers/pinctrl/mediatek/pinctrl-mt8512.c | 24 +- + drivers/pinctrl/mediatek/pinctrl-mt8516.c | 18 +- + drivers/pinctrl/mediatek/pinctrl-mt8518.c | 20 +- + drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 4 +- + drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 8 +- + 10 files changed, 898 insertions(+), 889 deletions(-) + +--- a/drivers/pinctrl/mediatek/pinctrl-mt7622.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c +@@ -233,283 +233,285 @@ static const struct mtk_pin_desc mt7622_ + */ + + /* EMMC */ +-static int mt7622_emmc_pins[] = { 40, 41, 42, 43, 44, 45, 47, 48, 49, 50, }; +-static int mt7622_emmc_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; ++static const int mt7622_emmc_pins[] = { ++ 40, 41, 42, 43, 44, 45, 47, 48, 49, 50, }; ++static const int mt7622_emmc_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; + +-static int mt7622_emmc_rst_pins[] = { 37, }; +-static int mt7622_emmc_rst_funcs[] = { 1, }; ++static const int mt7622_emmc_rst_pins[] = { 37, }; ++static const int mt7622_emmc_rst_funcs[] = { 1, }; + + /* LED for EPHY */ +-static int mt7622_ephy_leds_pins[] = { 86, 91, 92, 93, 94, }; +-static int mt7622_ephy_leds_funcs[] = { 0, 0, 0, 0, 0, }; +-static int mt7622_ephy0_led_pins[] = { 86, }; +-static int mt7622_ephy0_led_funcs[] = { 0, }; +-static int mt7622_ephy1_led_pins[] = { 91, }; +-static int mt7622_ephy1_led_funcs[] = { 2, }; +-static int mt7622_ephy2_led_pins[] = { 92, }; +-static int mt7622_ephy2_led_funcs[] = { 2, }; +-static int mt7622_ephy3_led_pins[] = { 93, }; +-static int mt7622_ephy3_led_funcs[] = { 2, }; +-static int mt7622_ephy4_led_pins[] = { 94, }; +-static int mt7622_ephy4_led_funcs[] = { 2, }; ++static const int mt7622_ephy_leds_pins[] = { 86, 91, 92, 93, 94, }; ++static const int mt7622_ephy_leds_funcs[] = { 0, 0, 0, 0, 0, }; ++static const int mt7622_ephy0_led_pins[] = { 86, }; ++static const int mt7622_ephy0_led_funcs[] = { 0, }; ++static const int mt7622_ephy1_led_pins[] = { 91, }; ++static const int mt7622_ephy1_led_funcs[] = { 2, }; ++static const int mt7622_ephy2_led_pins[] = { 92, }; ++static const int mt7622_ephy2_led_funcs[] = { 2, }; ++static const int mt7622_ephy3_led_pins[] = { 93, }; ++static const int mt7622_ephy3_led_funcs[] = { 2, }; ++static const int mt7622_ephy4_led_pins[] = { 94, }; ++static const int mt7622_ephy4_led_funcs[] = { 2, }; + + /* Embedded Switch */ +-static int mt7622_esw_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, +- 62, 63, 64, 65, 66, 67, 68, 69, 70, }; +-static int mt7622_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +- 0, 0, 0, 0, 0, 0, 0, 0, 0, }; +-static int mt7622_esw_p0_p1_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, }; +-static int mt7622_esw_p0_p1_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; +-static int mt7622_esw_p2_p3_p4_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, 67, +- 68, 69, 70, }; +-static int mt7622_esw_p2_p3_p4_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, +- 0, 0, 0, }; ++static const int mt7622_esw_pins[] = { ++ 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, ++ 69, 70, }; ++static const int mt7622_esw_funcs[] = { ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; ++static const int mt7622_esw_p0_p1_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, }; ++static const int mt7622_esw_p0_p1_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; ++static const int mt7622_esw_p2_p3_p4_pins[] = { ++ 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, }; ++static const int mt7622_esw_p2_p3_p4_funcs[] = { ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; + /* RGMII via ESW */ +-static int mt7622_rgmii_via_esw_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, +- 67, 68, 69, 70, }; +-static int mt7622_rgmii_via_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +- 0, }; ++static const int mt7622_rgmii_via_esw_pins[] = { ++ 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, }; ++static const int mt7622_rgmii_via_esw_funcs[] = { ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; + + /* RGMII via GMAC1 */ +-static int mt7622_rgmii_via_gmac1_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, +- 67, 68, 69, 70, }; +-static int mt7622_rgmii_via_gmac1_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, +- 2, }; ++static const int mt7622_rgmii_via_gmac1_pins[] = { ++ 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, }; ++static const int mt7622_rgmii_via_gmac1_funcs[] = { ++ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; + + /* RGMII via GMAC2 */ +-static int mt7622_rgmii_via_gmac2_pins[] = { 25, 26, 27, 28, 29, 30, 31, 32, +- 33, 34, 35, 36, }; +-static int mt7622_rgmii_via_gmac2_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +- 0, }; ++static const int mt7622_rgmii_via_gmac2_pins[] = { ++ 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, }; ++static const int mt7622_rgmii_via_gmac2_funcs[] = { ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; + + /* I2C */ +-static int mt7622_i2c0_pins[] = { 14, 15, }; +-static int mt7622_i2c0_funcs[] = { 0, 0, }; +-static int mt7622_i2c1_0_pins[] = { 55, 56, }; +-static int mt7622_i2c1_0_funcs[] = { 0, 0, }; +-static int mt7622_i2c1_1_pins[] = { 73, 74, }; +-static int mt7622_i2c1_1_funcs[] = { 3, 3, }; +-static int mt7622_i2c1_2_pins[] = { 87, 88, }; +-static int mt7622_i2c1_2_funcs[] = { 0, 0, }; +-static int mt7622_i2c2_0_pins[] = { 57, 58, }; +-static int mt7622_i2c2_0_funcs[] = { 0, 0, }; +-static int mt7622_i2c2_1_pins[] = { 75, 76, }; +-static int mt7622_i2c2_1_funcs[] = { 3, 3, }; +-static int mt7622_i2c2_2_pins[] = { 89, 90, }; +-static int mt7622_i2c2_2_funcs[] = { 0, 0, }; ++static const int mt7622_i2c0_pins[] = { 14, 15, }; ++static const int mt7622_i2c0_funcs[] = { 0, 0, }; ++static const int mt7622_i2c1_0_pins[] = { 55, 56, }; ++static const int mt7622_i2c1_0_funcs[] = { 0, 0, }; ++static const int mt7622_i2c1_1_pins[] = { 73, 74, }; ++static const int mt7622_i2c1_1_funcs[] = { 3, 3, }; ++static const int mt7622_i2c1_2_pins[] = { 87, 88, }; ++static const int mt7622_i2c1_2_funcs[] = { 0, 0, }; ++static const int mt7622_i2c2_0_pins[] = { 57, 58, }; ++static const int mt7622_i2c2_0_funcs[] = { 0, 0, }; ++static const int mt7622_i2c2_1_pins[] = { 75, 76, }; ++static const int mt7622_i2c2_1_funcs[] = { 3, 3, }; ++static const int mt7622_i2c2_2_pins[] = { 89, 90, }; ++static const int mt7622_i2c2_2_funcs[] = { 0, 0, }; + + /* I2S */ +-static int mt7622_i2s_in_mclk_bclk_ws_pins[] = { 3, 4, 5, }; +-static int mt7622_i2s_in_mclk_bclk_ws_funcs[] = { 3, 3, 0, }; +-static int mt7622_i2s1_in_data_pins[] = { 1, }; +-static int mt7622_i2s1_in_data_funcs[] = { 0, }; +-static int mt7622_i2s2_in_data_pins[] = { 16, }; +-static int mt7622_i2s2_in_data_funcs[] = { 0, }; +-static int mt7622_i2s3_in_data_pins[] = { 17, }; +-static int mt7622_i2s3_in_data_funcs[] = { 0, }; +-static int mt7622_i2s4_in_data_pins[] = { 18, }; +-static int mt7622_i2s4_in_data_funcs[] = { 0, }; +-static int mt7622_i2s_out_mclk_bclk_ws_pins[] = { 3, 4, 5, }; +-static int mt7622_i2s_out_mclk_bclk_ws_funcs[] = { 0, 0, 0, }; +-static int mt7622_i2s1_out_data_pins[] = { 2, }; +-static int mt7622_i2s1_out_data_funcs[] = { 0, }; +-static int mt7622_i2s2_out_data_pins[] = { 19, }; +-static int mt7622_i2s2_out_data_funcs[] = { 0, }; +-static int mt7622_i2s3_out_data_pins[] = { 20, }; +-static int mt7622_i2s3_out_data_funcs[] = { 0, }; +-static int mt7622_i2s4_out_data_pins[] = { 21, }; +-static int mt7622_i2s4_out_data_funcs[] = { 0, }; ++static const int mt7622_i2s_in_mclk_bclk_ws_pins[] = { 3, 4, 5, }; ++static const int mt7622_i2s_in_mclk_bclk_ws_funcs[] = { 3, 3, 0, }; ++static const int mt7622_i2s1_in_data_pins[] = { 1, }; ++static const int mt7622_i2s1_in_data_funcs[] = { 0, }; ++static const int mt7622_i2s2_in_data_pins[] = { 16, }; ++static const int mt7622_i2s2_in_data_funcs[] = { 0, }; ++static const int mt7622_i2s3_in_data_pins[] = { 17, }; ++static const int mt7622_i2s3_in_data_funcs[] = { 0, }; ++static const int mt7622_i2s4_in_data_pins[] = { 18, }; ++static const int mt7622_i2s4_in_data_funcs[] = { 0, }; ++static const int mt7622_i2s_out_mclk_bclk_ws_pins[] = { 3, 4, 5, }; ++static const int mt7622_i2s_out_mclk_bclk_ws_funcs[] = { 0, 0, 0, }; ++static const int mt7622_i2s1_out_data_pins[] = { 2, }; ++static const int mt7622_i2s1_out_data_funcs[] = { 0, }; ++static const int mt7622_i2s2_out_data_pins[] = { 19, }; ++static const int mt7622_i2s2_out_data_funcs[] = { 0, }; ++static const int mt7622_i2s3_out_data_pins[] = { 20, }; ++static const int mt7622_i2s3_out_data_funcs[] = { 0, }; ++static const int mt7622_i2s4_out_data_pins[] = { 21, }; ++static const int mt7622_i2s4_out_data_funcs[] = { 0, }; + + /* IR */ +-static int mt7622_ir_0_tx_pins[] = { 16, }; +-static int mt7622_ir_0_tx_funcs[] = { 4, }; +-static int mt7622_ir_1_tx_pins[] = { 59, }; +-static int mt7622_ir_1_tx_funcs[] = { 5, }; +-static int mt7622_ir_2_tx_pins[] = { 99, }; +-static int mt7622_ir_2_tx_funcs[] = { 3, }; +-static int mt7622_ir_0_rx_pins[] = { 17, }; +-static int mt7622_ir_0_rx_funcs[] = { 4, }; +-static int mt7622_ir_1_rx_pins[] = { 60, }; +-static int mt7622_ir_1_rx_funcs[] = { 5, }; +-static int mt7622_ir_2_rx_pins[] = { 100, }; +-static int mt7622_ir_2_rx_funcs[] = { 3, }; ++static const int mt7622_ir_0_tx_pins[] = { 16, }; ++static const int mt7622_ir_0_tx_funcs[] = { 4, }; ++static const int mt7622_ir_1_tx_pins[] = { 59, }; ++static const int mt7622_ir_1_tx_funcs[] = { 5, }; ++static const int mt7622_ir_2_tx_pins[] = { 99, }; ++static const int mt7622_ir_2_tx_funcs[] = { 3, }; ++static const int mt7622_ir_0_rx_pins[] = { 17, }; ++static const int mt7622_ir_0_rx_funcs[] = { 4, }; ++static const int mt7622_ir_1_rx_pins[] = { 60, }; ++static const int mt7622_ir_1_rx_funcs[] = { 5, }; ++static const int mt7622_ir_2_rx_pins[] = { 100, }; ++static const int mt7622_ir_2_rx_funcs[] = { 3, }; + + /* MDIO */ +-static int mt7622_mdc_mdio_pins[] = { 23, 24, }; +-static int mt7622_mdc_mdio_funcs[] = { 0, 0, }; ++static const int mt7622_mdc_mdio_pins[] = { 23, 24, }; ++static const int mt7622_mdc_mdio_funcs[] = { 0, 0, }; + + /* PCIE */ +-static int mt7622_pcie0_0_waken_pins[] = { 14, }; +-static int mt7622_pcie0_0_waken_funcs[] = { 2, }; +-static int mt7622_pcie0_0_clkreq_pins[] = { 15, }; +-static int mt7622_pcie0_0_clkreq_funcs[] = { 2, }; +-static int mt7622_pcie0_1_waken_pins[] = { 79, }; +-static int mt7622_pcie0_1_waken_funcs[] = { 4, }; +-static int mt7622_pcie0_1_clkreq_pins[] = { 80, }; +-static int mt7622_pcie0_1_clkreq_funcs[] = { 4, }; +-static int mt7622_pcie1_0_waken_pins[] = { 14, }; +-static int mt7622_pcie1_0_waken_funcs[] = { 3, }; +-static int mt7622_pcie1_0_clkreq_pins[] = { 15, }; +-static int mt7622_pcie1_0_clkreq_funcs[] = { 3, }; +- +-static int mt7622_pcie0_pad_perst_pins[] = { 83, }; +-static int mt7622_pcie0_pad_perst_funcs[] = { 0, }; +-static int mt7622_pcie1_pad_perst_pins[] = { 84, }; +-static int mt7622_pcie1_pad_perst_funcs[] = { 0, }; ++static const int mt7622_pcie0_0_waken_pins[] = { 14, }; ++static const int mt7622_pcie0_0_waken_funcs[] = { 2, }; ++static const int mt7622_pcie0_0_clkreq_pins[] = { 15, }; ++static const int mt7622_pcie0_0_clkreq_funcs[] = { 2, }; ++static const int mt7622_pcie0_1_waken_pins[] = { 79, }; ++static const int mt7622_pcie0_1_waken_funcs[] = { 4, }; ++static const int mt7622_pcie0_1_clkreq_pins[] = { 80, }; ++static const int mt7622_pcie0_1_clkreq_funcs[] = { 4, }; ++static const int mt7622_pcie1_0_waken_pins[] = { 14, }; ++static const int mt7622_pcie1_0_waken_funcs[] = { 3, }; ++static const int mt7622_pcie1_0_clkreq_pins[] = { 15, }; ++static const int mt7622_pcie1_0_clkreq_funcs[] = { 3, }; ++ ++static const int mt7622_pcie0_pad_perst_pins[] = { 83, }; ++static const int mt7622_pcie0_pad_perst_funcs[] = { 0, }; ++static const int mt7622_pcie1_pad_perst_pins[] = { 84, }; ++static const int mt7622_pcie1_pad_perst_funcs[] = { 0, }; + + /* PMIC bus */ +-static int mt7622_pmic_bus_pins[] = { 71, 72, }; +-static int mt7622_pmic_bus_funcs[] = { 0, 0, }; ++static const int mt7622_pmic_bus_pins[] = { 71, 72, }; ++static const int mt7622_pmic_bus_funcs[] = { 0, 0, }; + + /* Parallel NAND */ +-static int mt7622_pnand_pins[] = { 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, +- 48, 49, 50, }; +-static int mt7622_pnand_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +- 0, }; ++static const int mt7622_pnand_pins[] = { ++ 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, }; ++static const int mt7622_pnand_funcs[] = { ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; + + /* PWM */ +-static int mt7622_pwm_ch1_0_pins[] = { 51, }; +-static int mt7622_pwm_ch1_0_funcs[] = { 3, }; +-static int mt7622_pwm_ch1_1_pins[] = { 73, }; +-static int mt7622_pwm_ch1_1_funcs[] = { 4, }; +-static int mt7622_pwm_ch1_2_pins[] = { 95, }; +-static int mt7622_pwm_ch1_2_funcs[] = { 0, }; +-static int mt7622_pwm_ch2_0_pins[] = { 52, }; +-static int mt7622_pwm_ch2_0_funcs[] = { 3, }; +-static int mt7622_pwm_ch2_1_pins[] = { 74, }; +-static int mt7622_pwm_ch2_1_funcs[] = { 4, }; +-static int mt7622_pwm_ch2_2_pins[] = { 96, }; +-static int mt7622_pwm_ch2_2_funcs[] = { 0, }; +-static int mt7622_pwm_ch3_0_pins[] = { 53, }; +-static int mt7622_pwm_ch3_0_funcs[] = { 3, }; +-static int mt7622_pwm_ch3_1_pins[] = { 75, }; +-static int mt7622_pwm_ch3_1_funcs[] = { 4, }; +-static int mt7622_pwm_ch3_2_pins[] = { 97, }; +-static int mt7622_pwm_ch3_2_funcs[] = { 0, }; +-static int mt7622_pwm_ch4_0_pins[] = { 54, }; +-static int mt7622_pwm_ch4_0_funcs[] = { 3, }; +-static int mt7622_pwm_ch4_1_pins[] = { 67, }; +-static int mt7622_pwm_ch4_1_funcs[] = { 3, }; +-static int mt7622_pwm_ch4_2_pins[] = { 76, }; +-static int mt7622_pwm_ch4_2_funcs[] = { 4, }; +-static int mt7622_pwm_ch4_3_pins[] = { 98, }; +-static int mt7622_pwm_ch4_3_funcs[] = { 0, }; +-static int mt7622_pwm_ch5_0_pins[] = { 68, }; +-static int mt7622_pwm_ch5_0_funcs[] = { 3, }; +-static int mt7622_pwm_ch5_1_pins[] = { 77, }; +-static int mt7622_pwm_ch5_1_funcs[] = { 4, }; +-static int mt7622_pwm_ch5_2_pins[] = { 99, }; +-static int mt7622_pwm_ch5_2_funcs[] = { 0, }; +-static int mt7622_pwm_ch6_0_pins[] = { 69, }; +-static int mt7622_pwm_ch6_0_funcs[] = { 3, }; +-static int mt7622_pwm_ch6_1_pins[] = { 78, }; +-static int mt7622_pwm_ch6_1_funcs[] = { 4, }; +-static int mt7622_pwm_ch6_2_pins[] = { 81, }; +-static int mt7622_pwm_ch6_2_funcs[] = { 4, }; +-static int mt7622_pwm_ch6_3_pins[] = { 100, }; +-static int mt7622_pwm_ch6_3_funcs[] = { 0, }; +-static int mt7622_pwm_ch7_0_pins[] = { 70, }; +-static int mt7622_pwm_ch7_0_funcs[] = { 3, }; +-static int mt7622_pwm_ch7_1_pins[] = { 82, }; +-static int mt7622_pwm_ch7_1_funcs[] = { 4, }; +-static int mt7622_pwm_ch7_2_pins[] = { 101, }; +-static int mt7622_pwm_ch7_2_funcs[] = { 0, }; ++static const int mt7622_pwm_ch1_0_pins[] = { 51, }; ++static const int mt7622_pwm_ch1_0_funcs[] = { 3, }; ++static const int mt7622_pwm_ch1_1_pins[] = { 73, }; ++static const int mt7622_pwm_ch1_1_funcs[] = { 4, }; ++static const int mt7622_pwm_ch1_2_pins[] = { 95, }; ++static const int mt7622_pwm_ch1_2_funcs[] = { 0, }; ++static const int mt7622_pwm_ch2_0_pins[] = { 52, }; ++static const int mt7622_pwm_ch2_0_funcs[] = { 3, }; ++static const int mt7622_pwm_ch2_1_pins[] = { 74, }; ++static const int mt7622_pwm_ch2_1_funcs[] = { 4, }; ++static const int mt7622_pwm_ch2_2_pins[] = { 96, }; ++static const int mt7622_pwm_ch2_2_funcs[] = { 0, }; ++static const int mt7622_pwm_ch3_0_pins[] = { 53, }; ++static const int mt7622_pwm_ch3_0_funcs[] = { 3, }; ++static const int mt7622_pwm_ch3_1_pins[] = { 75, }; ++static const int mt7622_pwm_ch3_1_funcs[] = { 4, }; ++static const int mt7622_pwm_ch3_2_pins[] = { 97, }; ++static const int mt7622_pwm_ch3_2_funcs[] = { 0, }; ++static const int mt7622_pwm_ch4_0_pins[] = { 54, }; ++static const int mt7622_pwm_ch4_0_funcs[] = { 3, }; ++static const int mt7622_pwm_ch4_1_pins[] = { 67, }; ++static const int mt7622_pwm_ch4_1_funcs[] = { 3, }; ++static const int mt7622_pwm_ch4_2_pins[] = { 76, }; ++static const int mt7622_pwm_ch4_2_funcs[] = { 4, }; ++static const int mt7622_pwm_ch4_3_pins[] = { 98, }; ++static const int mt7622_pwm_ch4_3_funcs[] = { 0, }; ++static const int mt7622_pwm_ch5_0_pins[] = { 68, }; ++static const int mt7622_pwm_ch5_0_funcs[] = { 3, }; ++static const int mt7622_pwm_ch5_1_pins[] = { 77, }; ++static const int mt7622_pwm_ch5_1_funcs[] = { 4, }; ++static const int mt7622_pwm_ch5_2_pins[] = { 99, }; ++static const int mt7622_pwm_ch5_2_funcs[] = { 0, }; ++static const int mt7622_pwm_ch6_0_pins[] = { 69, }; ++static const int mt7622_pwm_ch6_0_funcs[] = { 3, }; ++static const int mt7622_pwm_ch6_1_pins[] = { 78, }; ++static const int mt7622_pwm_ch6_1_funcs[] = { 4, }; ++static const int mt7622_pwm_ch6_2_pins[] = { 81, }; ++static const int mt7622_pwm_ch6_2_funcs[] = { 4, }; ++static const int mt7622_pwm_ch6_3_pins[] = { 100, }; ++static const int mt7622_pwm_ch6_3_funcs[] = { 0, }; ++static const int mt7622_pwm_ch7_0_pins[] = { 70, }; ++static const int mt7622_pwm_ch7_0_funcs[] = { 3, }; ++static const int mt7622_pwm_ch7_1_pins[] = { 82, }; ++static const int mt7622_pwm_ch7_1_funcs[] = { 4, }; ++static const int mt7622_pwm_ch7_2_pins[] = { 101, }; ++static const int mt7622_pwm_ch7_2_funcs[] = { 0, }; + + /* SD */ +-static int mt7622_sd_0_pins[] = { 16, 17, 18, 19, 20, 21, }; +-static int mt7622_sd_0_funcs[] = { 2, 2, 2, 2, 2, 2, }; +-static int mt7622_sd_1_pins[] = { 25, 26, 27, 28, 29, 30, }; +-static int mt7622_sd_1_funcs[] = { 2, 2, 2, 2, 2, 2, }; ++static const int mt7622_sd_0_pins[] = { 16, 17, 18, 19, 20, 21, }; ++static const int mt7622_sd_0_funcs[] = { 2, 2, 2, 2, 2, 2, }; ++static const int mt7622_sd_1_pins[] = { 25, 26, 27, 28, 29, 30, }; ++static const int mt7622_sd_1_funcs[] = { 2, 2, 2, 2, 2, 2, }; + + /* Serial NAND */ +-static int mt7622_snfi_pins[] = { 8, 9, 10, 11, 12, 13, }; +-static int mt7622_snfi_funcs[] = { 2, 2, 2, 2, 2, 2, }; ++static const int mt7622_snfi_pins[] = { 8, 9, 10, 11, 12, 13, }; ++static const int mt7622_snfi_funcs[] = { 2, 2, 2, 2, 2, 2, }; + + /* SPI NOR */ +-static int mt7622_spi_pins[] = { 8, 9, 10, 11, 12, 13 }; +-static int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, }; ++static const int mt7622_spi_pins[] = { 8, 9, 10, 11, 12, 13 }; ++static const int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, }; + + /* SPIC */ +-static int mt7622_spic0_0_pins[] = { 63, 64, 65, 66, }; +-static int mt7622_spic0_0_funcs[] = { 4, 4, 4, 4, }; +-static int mt7622_spic0_1_pins[] = { 79, 80, 81, 82, }; +-static int mt7622_spic0_1_funcs[] = { 3, 3, 3, 3, }; +-static int mt7622_spic1_0_pins[] = { 67, 68, 69, 70, }; +-static int mt7622_spic1_0_funcs[] = { 4, 4, 4, 4, }; +-static int mt7622_spic1_1_pins[] = { 73, 74, 75, 76, }; +-static int mt7622_spic1_1_funcs[] = { 0, 0, 0, 0, }; +-static int mt7622_spic2_0_pins[] = { 10, 11, 12, 13, }; +-static int mt7622_spic2_0_funcs[] = { 0, 0, 0, 0, }; +-static int mt7622_spic2_0_wp_hold_pins[] = { 8, 9, }; +-static int mt7622_spic2_0_wp_hold_funcs[] = { 0, 0, }; ++static const int mt7622_spic0_0_pins[] = { 63, 64, 65, 66, }; ++static const int mt7622_spic0_0_funcs[] = { 4, 4, 4, 4, }; ++static const int mt7622_spic0_1_pins[] = { 79, 80, 81, 82, }; ++static const int mt7622_spic0_1_funcs[] = { 3, 3, 3, 3, }; ++static const int mt7622_spic1_0_pins[] = { 67, 68, 69, 70, }; ++static const int mt7622_spic1_0_funcs[] = { 4, 4, 4, 4, }; ++static const int mt7622_spic1_1_pins[] = { 73, 74, 75, 76, }; ++static const int mt7622_spic1_1_funcs[] = { 0, 0, 0, 0, }; ++static const int mt7622_spic2_0_pins[] = { 10, 11, 12, 13, }; ++static const int mt7622_spic2_0_funcs[] = { 0, 0, 0, 0, }; ++static const int mt7622_spic2_0_wp_hold_pins[] = { 8, 9, }; ++static const int mt7622_spic2_0_wp_hold_funcs[] = { 0, 0, }; + + /* TDM */ +-static int mt7622_tdm_0_out_mclk_bclk_ws_pins[] = { 8, 9, 10, }; +-static int mt7622_tdm_0_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; +-static int mt7622_tdm_0_in_mclk_bclk_ws_pins[] = { 11, 12, 13, }; +-static int mt7622_tdm_0_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; +-static int mt7622_tdm_0_out_data_pins[] = { 20, }; +-static int mt7622_tdm_0_out_data_funcs[] = { 3, }; +-static int mt7622_tdm_0_in_data_pins[] = { 21, }; +-static int mt7622_tdm_0_in_data_funcs[] = { 3, }; +-static int mt7622_tdm_1_out_mclk_bclk_ws_pins[] = { 57, 58, 59, }; +-static int mt7622_tdm_1_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; +-static int mt7622_tdm_1_in_mclk_bclk_ws_pins[] = { 60, 61, 62, }; +-static int mt7622_tdm_1_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; +-static int mt7622_tdm_1_out_data_pins[] = { 55, }; +-static int mt7622_tdm_1_out_data_funcs[] = { 3, }; +-static int mt7622_tdm_1_in_data_pins[] = { 56, }; +-static int mt7622_tdm_1_in_data_funcs[] = { 3, }; ++static const int mt7622_tdm_0_out_mclk_bclk_ws_pins[] = { 8, 9, 10, }; ++static const int mt7622_tdm_0_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; ++static const int mt7622_tdm_0_in_mclk_bclk_ws_pins[] = { 11, 12, 13, }; ++static const int mt7622_tdm_0_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; ++static const int mt7622_tdm_0_out_data_pins[] = { 20, }; ++static const int mt7622_tdm_0_out_data_funcs[] = { 3, }; ++static const int mt7622_tdm_0_in_data_pins[] = { 21, }; ++static const int mt7622_tdm_0_in_data_funcs[] = { 3, }; ++static const int mt7622_tdm_1_out_mclk_bclk_ws_pins[] = { 57, 58, 59, }; ++static const int mt7622_tdm_1_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; ++static const int mt7622_tdm_1_in_mclk_bclk_ws_pins[] = { 60, 61, 62, }; ++static const int mt7622_tdm_1_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; ++static const int mt7622_tdm_1_out_data_pins[] = { 55, }; ++static const int mt7622_tdm_1_out_data_funcs[] = { 3, }; ++static const int mt7622_tdm_1_in_data_pins[] = { 56, }; ++static const int mt7622_tdm_1_in_data_funcs[] = { 3, }; + + /* UART */ +-static int mt7622_uart0_0_tx_rx_pins[] = { 6, 7, }; +-static int mt7622_uart0_0_tx_rx_funcs[] = { 0, 0, }; +-static int mt7622_uart1_0_tx_rx_pins[] = { 55, 56, }; +-static int mt7622_uart1_0_tx_rx_funcs[] = { 2, 2, }; +-static int mt7622_uart1_0_rts_cts_pins[] = { 57, 58, }; +-static int mt7622_uart1_0_rts_cts_funcs[] = { 2, 2, }; +-static int mt7622_uart1_1_tx_rx_pins[] = { 73, 74, }; +-static int mt7622_uart1_1_tx_rx_funcs[] = { 2, 2, }; +-static int mt7622_uart1_1_rts_cts_pins[] = { 75, 76, }; +-static int mt7622_uart1_1_rts_cts_funcs[] = { 2, 2, }; +-static int mt7622_uart2_0_tx_rx_pins[] = { 3, 4, }; +-static int mt7622_uart2_0_tx_rx_funcs[] = { 2, 2, }; +-static int mt7622_uart2_0_rts_cts_pins[] = { 1, 2, }; +-static int mt7622_uart2_0_rts_cts_funcs[] = { 2, 2, }; +-static int mt7622_uart2_1_tx_rx_pins[] = { 51, 52, }; +-static int mt7622_uart2_1_tx_rx_funcs[] = { 0, 0, }; +-static int mt7622_uart2_1_rts_cts_pins[] = { 53, 54, }; +-static int mt7622_uart2_1_rts_cts_funcs[] = { 0, 0, }; +-static int mt7622_uart2_2_tx_rx_pins[] = { 59, 60, }; +-static int mt7622_uart2_2_tx_rx_funcs[] = { 4, 4, }; +-static int mt7622_uart2_2_rts_cts_pins[] = { 61, 62, }; +-static int mt7622_uart2_2_rts_cts_funcs[] = { 4, 4, }; +-static int mt7622_uart2_3_tx_rx_pins[] = { 95, 96, }; +-static int mt7622_uart2_3_tx_rx_funcs[] = { 3, 3, }; +-static int mt7622_uart3_0_tx_rx_pins[] = { 57, 58, }; +-static int mt7622_uart3_0_tx_rx_funcs[] = { 5, 5, }; +-static int mt7622_uart3_1_tx_rx_pins[] = { 81, 82, }; +-static int mt7622_uart3_1_tx_rx_funcs[] = { 0, 0, }; +-static int mt7622_uart3_1_rts_cts_pins[] = { 79, 80, }; +-static int mt7622_uart3_1_rts_cts_funcs[] = { 0, 0, }; +-static int mt7622_uart4_0_tx_rx_pins[] = { 61, 62, }; +-static int mt7622_uart4_0_tx_rx_funcs[] = { 5, 5, }; +-static int mt7622_uart4_1_tx_rx_pins[] = { 91, 92, }; +-static int mt7622_uart4_1_tx_rx_funcs[] = { 0, 0, }; +-static int mt7622_uart4_1_rts_cts_pins[] = { 93, 94 }; +-static int mt7622_uart4_1_rts_cts_funcs[] = { 0, 0, }; +-static int mt7622_uart4_2_tx_rx_pins[] = { 97, 98, }; +-static int mt7622_uart4_2_tx_rx_funcs[] = { 2, 2, }; +-static int mt7622_uart4_2_rts_cts_pins[] = { 95, 96 }; +-static int mt7622_uart4_2_rts_cts_funcs[] = { 2, 2, }; ++static const int mt7622_uart0_0_tx_rx_pins[] = { 6, 7, }; ++static const int mt7622_uart0_0_tx_rx_funcs[] = { 0, 0, }; ++static const int mt7622_uart1_0_tx_rx_pins[] = { 55, 56, }; ++static const int mt7622_uart1_0_tx_rx_funcs[] = { 2, 2, }; ++static const int mt7622_uart1_0_rts_cts_pins[] = { 57, 58, }; ++static const int mt7622_uart1_0_rts_cts_funcs[] = { 2, 2, }; ++static const int mt7622_uart1_1_tx_rx_pins[] = { 73, 74, }; ++static const int mt7622_uart1_1_tx_rx_funcs[] = { 2, 2, }; ++static const int mt7622_uart1_1_rts_cts_pins[] = { 75, 76, }; ++static const int mt7622_uart1_1_rts_cts_funcs[] = { 2, 2, }; ++static const int mt7622_uart2_0_tx_rx_pins[] = { 3, 4, }; ++static const int mt7622_uart2_0_tx_rx_funcs[] = { 2, 2, }; ++static const int mt7622_uart2_0_rts_cts_pins[] = { 1, 2, }; ++static const int mt7622_uart2_0_rts_cts_funcs[] = { 2, 2, }; ++static const int mt7622_uart2_1_tx_rx_pins[] = { 51, 52, }; ++static const int mt7622_uart2_1_tx_rx_funcs[] = { 0, 0, }; ++static const int mt7622_uart2_1_rts_cts_pins[] = { 53, 54, }; ++static const int mt7622_uart2_1_rts_cts_funcs[] = { 0, 0, }; ++static const int mt7622_uart2_2_tx_rx_pins[] = { 59, 60, }; ++static const int mt7622_uart2_2_tx_rx_funcs[] = { 4, 4, }; ++static const int mt7622_uart2_2_rts_cts_pins[] = { 61, 62, }; ++static const int mt7622_uart2_2_rts_cts_funcs[] = { 4, 4, }; ++static const int mt7622_uart2_3_tx_rx_pins[] = { 95, 96, }; ++static const int mt7622_uart2_3_tx_rx_funcs[] = { 3, 3, }; ++static const int mt7622_uart3_0_tx_rx_pins[] = { 57, 58, }; ++static const int mt7622_uart3_0_tx_rx_funcs[] = { 5, 5, }; ++static const int mt7622_uart3_1_tx_rx_pins[] = { 81, 82, }; ++static const int mt7622_uart3_1_tx_rx_funcs[] = { 0, 0, }; ++static const int mt7622_uart3_1_rts_cts_pins[] = { 79, 80, }; ++static const int mt7622_uart3_1_rts_cts_funcs[] = { 0, 0, }; ++static const int mt7622_uart4_0_tx_rx_pins[] = { 61, 62, }; ++static const int mt7622_uart4_0_tx_rx_funcs[] = { 5, 5, }; ++static const int mt7622_uart4_1_tx_rx_pins[] = { 91, 92, }; ++static const int mt7622_uart4_1_tx_rx_funcs[] = { 0, 0, }; ++static const int mt7622_uart4_1_rts_cts_pins[] = { 93, 94 }; ++static const int mt7622_uart4_1_rts_cts_funcs[] = { 0, 0, }; ++static const int mt7622_uart4_2_tx_rx_pins[] = { 97, 98, }; ++static const int mt7622_uart4_2_tx_rx_funcs[] = { 2, 2, }; ++static const int mt7622_uart4_2_rts_cts_pins[] = { 95, 96 }; ++static const int mt7622_uart4_2_rts_cts_funcs[] = { 2, 2, }; + + /* Watchdog */ +-static int mt7622_watchdog_pins[] = { 78, }; +-static int mt7622_watchdog_funcs[] = { 0, }; ++static const int mt7622_watchdog_pins[] = { 78, }; ++static const int mt7622_watchdog_funcs[] = { 0, }; + + /* WLAN LED */ +-static int mt7622_wled_pins[] = { 85, }; +-static int mt7622_wled_funcs[] = { 0, }; ++static const int mt7622_wled_pins[] = { 85, }; ++static const int mt7622_wled_funcs[] = { 0, }; + + static const struct mtk_group_desc mt7622_groups[] = { + PINCTRL_PIN_GROUP("emmc", mt7622_emmc), +@@ -719,7 +721,7 @@ static const struct mtk_function_desc mt + {"watchdog", mt7622_wdt_groups, ARRAY_SIZE(mt7622_wdt_groups)}, + }; + +-static struct mtk_pinctrl_soc mt7622_data = { ++static const struct mtk_pinctrl_soc mt7622_data = { + .name = "mt7622_pinctrl", + .reg_cal = mt7622_reg_cals, + .pins = mt7622_pins, +--- a/drivers/pinctrl/mediatek/pinctrl-mt7623.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c +@@ -692,377 +692,377 @@ static const struct mtk_pin_desc mt7623_ + */ + + /* AUDIO EXT CLK */ +-static int mt7623_aud_ext_clk0_pins[] = { 208, }; +-static int mt7623_aud_ext_clk0_funcs[] = { 1, }; +-static int mt7623_aud_ext_clk1_pins[] = { 209, }; +-static int mt7623_aud_ext_clk1_funcs[] = { 1, }; ++static const int mt7623_aud_ext_clk0_pins[] = { 208, }; ++static const int mt7623_aud_ext_clk0_funcs[] = { 1, }; ++static const int mt7623_aud_ext_clk1_pins[] = { 209, }; ++static const int mt7623_aud_ext_clk1_funcs[] = { 1, }; + + /* DISP PWM */ +-static int mt7623_disp_pwm_0_pins[] = { 72, }; +-static int mt7623_disp_pwm_0_funcs[] = { 5, }; +-static int mt7623_disp_pwm_1_pins[] = { 203, }; +-static int mt7623_disp_pwm_1_funcs[] = { 2, }; +-static int mt7623_disp_pwm_2_pins[] = { 208, }; +-static int mt7623_disp_pwm_2_funcs[] = { 5, }; ++static const int mt7623_disp_pwm_0_pins[] = { 72, }; ++static const int mt7623_disp_pwm_0_funcs[] = { 5, }; ++static const int mt7623_disp_pwm_1_pins[] = { 203, }; ++static const int mt7623_disp_pwm_1_funcs[] = { 2, }; ++static const int mt7623_disp_pwm_2_pins[] = { 208, }; ++static const int mt7623_disp_pwm_2_funcs[] = { 5, }; + + /* ESW */ +-static int mt7623_esw_int_pins[] = { 273, }; +-static int mt7623_esw_int_funcs[] = { 1, }; +-static int mt7623_esw_rst_pins[] = { 277, }; +-static int mt7623_esw_rst_funcs[] = { 1, }; ++static const int mt7623_esw_int_pins[] = { 273, }; ++static const int mt7623_esw_int_funcs[] = { 1, }; ++static const int mt7623_esw_rst_pins[] = { 277, }; ++static const int mt7623_esw_rst_funcs[] = { 1, }; + + /* EPHY */ +-static int mt7623_ephy_pins[] = { 262, 263, 264, 265, 266, 267, 268, +- 269, 270, 271, 272, 274, }; +-static int mt7623_ephy_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; ++static const int mt7623_ephy_pins[] = { 262, 263, 264, 265, 266, 267, 268, ++ 269, 270, 271, 272, 274, }; ++static const int mt7623_ephy_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; + + /* EXT_SDIO */ +-static int mt7623_ext_sdio_pins[] = { 236, 237, 238, 239, 240, 241, }; +-static int mt7623_ext_sdio_funcs[] = { 1, 1, 1, 1, 1, 1, }; ++static const int mt7623_ext_sdio_pins[] = { 236, 237, 238, 239, 240, 241, }; ++static const int mt7623_ext_sdio_funcs[] = { 1, 1, 1, 1, 1, 1, }; + + /* HDMI RX */ +-static int mt7623_hdmi_rx_pins[] = { 247, 248, }; +-static int mt7623_hdmi_rx_funcs[] = { 1, 1 }; +-static int mt7623_hdmi_rx_i2c_pins[] = { 244, 245, }; +-static int mt7623_hdmi_rx_i2c_funcs[] = { 1, 1 }; ++static const int mt7623_hdmi_rx_pins[] = { 247, 248, }; ++static const int mt7623_hdmi_rx_funcs[] = { 1, 1 }; ++static const int mt7623_hdmi_rx_i2c_pins[] = { 244, 245, }; ++static const int mt7623_hdmi_rx_i2c_funcs[] = { 1, 1 }; + + /* HDMI TX */ +-static int mt7623_hdmi_cec_pins[] = { 122, }; +-static int mt7623_hdmi_cec_funcs[] = { 1, }; +-static int mt7623_hdmi_htplg_pins[] = { 123, }; +-static int mt7623_hdmi_htplg_funcs[] = { 1, }; +-static int mt7623_hdmi_i2c_pins[] = { 124, 125, }; +-static int mt7623_hdmi_i2c_funcs[] = { 1, 1 }; ++static const int mt7623_hdmi_cec_pins[] = { 122, }; ++static const int mt7623_hdmi_cec_funcs[] = { 1, }; ++static const int mt7623_hdmi_htplg_pins[] = { 123, }; ++static const int mt7623_hdmi_htplg_funcs[] = { 1, }; ++static const int mt7623_hdmi_i2c_pins[] = { 124, 125, }; ++static const int mt7623_hdmi_i2c_funcs[] = { 1, 1 }; + + /* I2C */ +-static int mt7623_i2c0_pins[] = { 75, 76, }; +-static int mt7623_i2c0_funcs[] = { 1, 1, }; +-static int mt7623_i2c1_0_pins[] = { 57, 58, }; +-static int mt7623_i2c1_0_funcs[] = { 1, 1, }; +-static int mt7623_i2c1_1_pins[] = { 242, 243, }; +-static int mt7623_i2c1_1_funcs[] = { 4, 4, }; +-static int mt7623_i2c1_2_pins[] = { 85, 86, }; +-static int mt7623_i2c1_2_funcs[] = { 3, 3, }; +-static int mt7623_i2c1_3_pins[] = { 105, 106, }; +-static int mt7623_i2c1_3_funcs[] = { 3, 3, }; +-static int mt7623_i2c1_4_pins[] = { 124, 125, }; +-static int mt7623_i2c1_4_funcs[] = { 4, 4, }; +-static int mt7623_i2c2_0_pins[] = { 77, 78, }; +-static int mt7623_i2c2_0_funcs[] = { 1, 1, }; +-static int mt7623_i2c2_1_pins[] = { 89, 90, }; +-static int mt7623_i2c2_1_funcs[] = { 3, 3, }; +-static int mt7623_i2c2_2_pins[] = { 109, 110, }; +-static int mt7623_i2c2_2_funcs[] = { 3, 3, }; +-static int mt7623_i2c2_3_pins[] = { 122, 123, }; +-static int mt7623_i2c2_3_funcs[] = { 4, 4, }; ++static const int mt7623_i2c0_pins[] = { 75, 76, }; ++static const int mt7623_i2c0_funcs[] = { 1, 1, }; ++static const int mt7623_i2c1_0_pins[] = { 57, 58, }; ++static const int mt7623_i2c1_0_funcs[] = { 1, 1, }; ++static const int mt7623_i2c1_1_pins[] = { 242, 243, }; ++static const int mt7623_i2c1_1_funcs[] = { 4, 4, }; ++static const int mt7623_i2c1_2_pins[] = { 85, 86, }; ++static const int mt7623_i2c1_2_funcs[] = { 3, 3, }; ++static const int mt7623_i2c1_3_pins[] = { 105, 106, }; ++static const int mt7623_i2c1_3_funcs[] = { 3, 3, }; ++static const int mt7623_i2c1_4_pins[] = { 124, 125, }; ++static const int mt7623_i2c1_4_funcs[] = { 4, 4, }; ++static const int mt7623_i2c2_0_pins[] = { 77, 78, }; ++static const int mt7623_i2c2_0_funcs[] = { 1, 1, }; ++static const int mt7623_i2c2_1_pins[] = { 89, 90, }; ++static const int mt7623_i2c2_1_funcs[] = { 3, 3, }; ++static const int mt7623_i2c2_2_pins[] = { 109, 110, }; ++static const int mt7623_i2c2_2_funcs[] = { 3, 3, }; ++static const int mt7623_i2c2_3_pins[] = { 122, 123, }; ++static const int mt7623_i2c2_3_funcs[] = { 4, 4, }; + + /* I2S */ +-static int mt7623_i2s0_pins[] = { 49, 72, 73, 74, 126, }; +-static int mt7623_i2s0_funcs[] = { 1, 1, 1, 1, 1, }; +-static int mt7623_i2s1_pins[] = { 33, 34, 35, 36, 37, }; +-static int mt7623_i2s1_funcs[] = { 1, 1, 1, 1, 1, }; +-static int mt7623_i2s2_bclk_lrclk_mclk_pins[] = { 50, 52, 188, }; +-static int mt7623_i2s2_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, }; +-static int mt7623_i2s2_data_in_pins[] = { 51, }; +-static int mt7623_i2s2_data_in_funcs[] = { 1, }; +-static int mt7623_i2s2_data_0_pins[] = { 203, }; +-static int mt7623_i2s2_data_0_funcs[] = { 9, }; +-static int mt7623_i2s2_data_1_pins[] = { 38, }; +-static int mt7623_i2s2_data_1_funcs[] = { 4, }; +-static int mt7623_i2s3_bclk_lrclk_mclk_pins[] = { 191, 192, 193, }; +-static int mt7623_i2s3_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, }; +-static int mt7623_i2s3_data_in_pins[] = { 190, }; +-static int mt7623_i2s3_data_in_funcs[] = { 1, }; +-static int mt7623_i2s3_data_0_pins[] = { 204, }; +-static int mt7623_i2s3_data_0_funcs[] = { 9, }; +-static int mt7623_i2s3_data_1_pins[] = { 2, }; +-static int mt7623_i2s3_data_1_funcs[] = { 0, }; +-static int mt7623_i2s4_pins[] = { 194, 195, 196, 197, 198, }; +-static int mt7623_i2s4_funcs[] = { 1, 1, 1, 1, 1, }; +-static int mt7623_i2s5_pins[] = { 16, 17, 30, 31, 32, }; +-static int mt7623_i2s5_funcs[] = { 1, 1, 1, 1, 1, }; ++static const int mt7623_i2s0_pins[] = { 49, 72, 73, 74, 126, }; ++static const int mt7623_i2s0_funcs[] = { 1, 1, 1, 1, 1, }; ++static const int mt7623_i2s1_pins[] = { 33, 34, 35, 36, 37, }; ++static const int mt7623_i2s1_funcs[] = { 1, 1, 1, 1, 1, }; ++static const int mt7623_i2s2_bclk_lrclk_mclk_pins[] = { 50, 52, 188, }; ++static const int mt7623_i2s2_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, }; ++static const int mt7623_i2s2_data_in_pins[] = { 51, }; ++static const int mt7623_i2s2_data_in_funcs[] = { 1, }; ++static const int mt7623_i2s2_data_0_pins[] = { 203, }; ++static const int mt7623_i2s2_data_0_funcs[] = { 9, }; ++static const int mt7623_i2s2_data_1_pins[] = { 38, }; ++static const int mt7623_i2s2_data_1_funcs[] = { 4, }; ++static const int mt7623_i2s3_bclk_lrclk_mclk_pins[] = { 191, 192, 193, }; ++static const int mt7623_i2s3_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, }; ++static const int mt7623_i2s3_data_in_pins[] = { 190, }; ++static const int mt7623_i2s3_data_in_funcs[] = { 1, }; ++static const int mt7623_i2s3_data_0_pins[] = { 204, }; ++static const int mt7623_i2s3_data_0_funcs[] = { 9, }; ++static const int mt7623_i2s3_data_1_pins[] = { 2, }; ++static const int mt7623_i2s3_data_1_funcs[] = { 0, }; ++static const int mt7623_i2s4_pins[] = { 194, 195, 196, 197, 198, }; ++static const int mt7623_i2s4_funcs[] = { 1, 1, 1, 1, 1, }; ++static const int mt7623_i2s5_pins[] = { 16, 17, 30, 31, 32, }; ++static const int mt7623_i2s5_funcs[] = { 1, 1, 1, 1, 1, }; + + /* IR */ +-static int mt7623_ir_pins[] = { 46, }; +-static int mt7623_ir_funcs[] = { 1, }; ++static const int mt7623_ir_pins[] = { 46, }; ++static const int mt7623_ir_funcs[] = { 1, }; + + /* LCD */ +-static int mt7623_mipi_tx_pins[] = { 91, 92, 93, 94, 95, 96, 97, 98, +- 99, 100, }; +-static int mt7623_mipi_tx_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; +-static int mt7623_dsi_te_pins[] = { 84, }; +-static int mt7623_dsi_te_funcs[] = { 1, }; +-static int mt7623_lcm_rst_pins[] = { 83, }; +-static int mt7623_lcm_rst_funcs[] = { 1, }; ++static const int mt7623_mipi_tx_pins[] = { 91, 92, 93, 94, 95, 96, 97, 98, ++ 99, 100, }; ++static const int mt7623_mipi_tx_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; ++static const int mt7623_dsi_te_pins[] = { 84, }; ++static const int mt7623_dsi_te_funcs[] = { 1, }; ++static const int mt7623_lcm_rst_pins[] = { 83, }; ++static const int mt7623_lcm_rst_funcs[] = { 1, }; + + /* MDC/MDIO */ +-static int mt7623_mdc_mdio_pins[] = { 275, 276, }; +-static int mt7623_mdc_mdio_funcs[] = { 1, 1, }; ++static const int mt7623_mdc_mdio_pins[] = { 275, 276, }; ++static const int mt7623_mdc_mdio_funcs[] = { 1, 1, }; + + /* MSDC */ +-static int mt7623_msdc0_pins[] = { 111, 112, 113, 114, 115, 116, 117, 118, +- 119, 120, 121, }; +-static int mt7623_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; +-static int mt7623_msdc1_pins[] = { 105, 106, 107, 108, 109, 110, }; +-static int mt7623_msdc1_funcs[] = { 1, 1, 1, 1, 1, 1, }; +-static int mt7623_msdc1_ins_pins[] = { 261, }; +-static int mt7623_msdc1_ins_funcs[] = { 1, }; +-static int mt7623_msdc1_wp_0_pins[] = { 29, }; +-static int mt7623_msdc1_wp_0_funcs[] = { 1, }; +-static int mt7623_msdc1_wp_1_pins[] = { 55, }; +-static int mt7623_msdc1_wp_1_funcs[] = { 3, }; +-static int mt7623_msdc1_wp_2_pins[] = { 209, }; +-static int mt7623_msdc1_wp_2_funcs[] = { 2, }; +-static int mt7623_msdc2_pins[] = { 85, 86, 87, 88, 89, 90, }; +-static int mt7623_msdc2_funcs[] = { 1, 1, 1, 1, 1, 1, }; +-static int mt7623_msdc3_pins[] = { 249, 250, 251, 252, 253, 254, 255, 256, +- 257, 258, 259, 260, }; +-static int mt7623_msdc3_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; ++static const int mt7623_msdc0_pins[] = { 111, 112, 113, 114, 115, 116, 117, 118, ++ 119, 120, 121, }; ++static const int mt7623_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; ++static const int mt7623_msdc1_pins[] = { 105, 106, 107, 108, 109, 110, }; ++static const int mt7623_msdc1_funcs[] = { 1, 1, 1, 1, 1, 1, }; ++static const int mt7623_msdc1_ins_pins[] = { 261, }; ++static const int mt7623_msdc1_ins_funcs[] = { 1, }; ++static const int mt7623_msdc1_wp_0_pins[] = { 29, }; ++static const int mt7623_msdc1_wp_0_funcs[] = { 1, }; ++static const int mt7623_msdc1_wp_1_pins[] = { 55, }; ++static const int mt7623_msdc1_wp_1_funcs[] = { 3, }; ++static const int mt7623_msdc1_wp_2_pins[] = { 209, }; ++static const int mt7623_msdc1_wp_2_funcs[] = { 2, }; ++static const int mt7623_msdc2_pins[] = { 85, 86, 87, 88, 89, 90, }; ++static const int mt7623_msdc2_funcs[] = { 1, 1, 1, 1, 1, 1, }; ++static const int mt7623_msdc3_pins[] = { 249, 250, 251, 252, 253, 254, 255, 256, ++ 257, 258, 259, 260, }; ++static const int mt7623_msdc3_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; + + /* NAND */ +-static int mt7623_nandc_pins[] = { 43, 47, 48, 111, 112, 113, 114, 115, +- 116, 117, 118, 119, 120, 121, }; +-static int mt7623_nandc_funcs[] = { 1, 1, 1, 4, 4, 4, 4, 4, 4, 4, 4, 4, +- 4, 4, }; +-static int mt7623_nandc_ceb0_pins[] = { 45, }; +-static int mt7623_nandc_ceb0_funcs[] = { 1, }; +-static int mt7623_nandc_ceb1_pins[] = { 44, }; +-static int mt7623_nandc_ceb1_funcs[] = { 1, }; ++static const int mt7623_nandc_pins[] = { 43, 47, 48, 111, 112, 113, 114, 115, ++ 116, 117, 118, 119, 120, 121, }; ++static const int mt7623_nandc_funcs[] = { 1, 1, 1, 4, 4, 4, 4, 4, 4, 4, 4, 4, ++ 4, 4, }; ++static const int mt7623_nandc_ceb0_pins[] = { 45, }; ++static const int mt7623_nandc_ceb0_funcs[] = { 1, }; ++static const int mt7623_nandc_ceb1_pins[] = { 44, }; ++static const int mt7623_nandc_ceb1_funcs[] = { 1, }; + + /* RTC */ +-static int mt7623_rtc_pins[] = { 10, }; +-static int mt7623_rtc_funcs[] = { 1, }; ++static const int mt7623_rtc_pins[] = { 10, }; ++static const int mt7623_rtc_funcs[] = { 1, }; + + /* OTG */ +-static int mt7623_otg_iddig0_0_pins[] = { 29, }; +-static int mt7623_otg_iddig0_0_funcs[] = { 1, }; +-static int mt7623_otg_iddig0_1_pins[] = { 44, }; +-static int mt7623_otg_iddig0_1_funcs[] = { 2, }; +-static int mt7623_otg_iddig0_2_pins[] = { 236, }; +-static int mt7623_otg_iddig0_2_funcs[] = { 2, }; +-static int mt7623_otg_iddig1_0_pins[] = { 27, }; +-static int mt7623_otg_iddig1_0_funcs[] = { 2, }; +-static int mt7623_otg_iddig1_1_pins[] = { 47, }; +-static int mt7623_otg_iddig1_1_funcs[] = { 2, }; +-static int mt7623_otg_iddig1_2_pins[] = { 238, }; +-static int mt7623_otg_iddig1_2_funcs[] = { 2, }; +-static int mt7623_otg_drv_vbus0_0_pins[] = { 28, }; +-static int mt7623_otg_drv_vbus0_0_funcs[] = { 1, }; +-static int mt7623_otg_drv_vbus0_1_pins[] = { 45, }; +-static int mt7623_otg_drv_vbus0_1_funcs[] = { 2, }; +-static int mt7623_otg_drv_vbus0_2_pins[] = { 237, }; +-static int mt7623_otg_drv_vbus0_2_funcs[] = { 2, }; +-static int mt7623_otg_drv_vbus1_0_pins[] = { 26, }; +-static int mt7623_otg_drv_vbus1_0_funcs[] = { 2, }; +-static int mt7623_otg_drv_vbus1_1_pins[] = { 48, }; +-static int mt7623_otg_drv_vbus1_1_funcs[] = { 2, }; +-static int mt7623_otg_drv_vbus1_2_pins[] = { 239, }; +-static int mt7623_otg_drv_vbus1_2_funcs[] = { 2, }; ++static const int mt7623_otg_iddig0_0_pins[] = { 29, }; ++static const int mt7623_otg_iddig0_0_funcs[] = { 1, }; ++static const int mt7623_otg_iddig0_1_pins[] = { 44, }; ++static const int mt7623_otg_iddig0_1_funcs[] = { 2, }; ++static const int mt7623_otg_iddig0_2_pins[] = { 236, }; ++static const int mt7623_otg_iddig0_2_funcs[] = { 2, }; ++static const int mt7623_otg_iddig1_0_pins[] = { 27, }; ++static const int mt7623_otg_iddig1_0_funcs[] = { 2, }; ++static const int mt7623_otg_iddig1_1_pins[] = { 47, }; ++static const int mt7623_otg_iddig1_1_funcs[] = { 2, }; ++static const int mt7623_otg_iddig1_2_pins[] = { 238, }; ++static const int mt7623_otg_iddig1_2_funcs[] = { 2, }; ++static const int mt7623_otg_drv_vbus0_0_pins[] = { 28, }; ++static const int mt7623_otg_drv_vbus0_0_funcs[] = { 1, }; ++static const int mt7623_otg_drv_vbus0_1_pins[] = { 45, }; ++static const int mt7623_otg_drv_vbus0_1_funcs[] = { 2, }; ++static const int mt7623_otg_drv_vbus0_2_pins[] = { 237, }; ++static const int mt7623_otg_drv_vbus0_2_funcs[] = { 2, }; ++static const int mt7623_otg_drv_vbus1_0_pins[] = { 26, }; ++static const int mt7623_otg_drv_vbus1_0_funcs[] = { 2, }; ++static const int mt7623_otg_drv_vbus1_1_pins[] = { 48, }; ++static const int mt7623_otg_drv_vbus1_1_funcs[] = { 2, }; ++static const int mt7623_otg_drv_vbus1_2_pins[] = { 239, }; ++static const int mt7623_otg_drv_vbus1_2_funcs[] = { 2, }; + + /* PCIE */ +-static int mt7623_pcie0_0_perst_pins[] = { 208, }; +-static int mt7623_pcie0_0_perst_funcs[] = { 3, }; +-static int mt7623_pcie0_1_perst_pins[] = { 22, }; +-static int mt7623_pcie0_1_perst_funcs[] = { 2, }; +-static int mt7623_pcie1_0_perst_pins[] = { 209, }; +-static int mt7623_pcie1_0_perst_funcs[] = { 3, }; +-static int mt7623_pcie1_1_perst_pins[] = { 23, }; +-static int mt7623_pcie1_1_perst_funcs[] = { 2, }; +-static int mt7623_pcie2_0_perst_pins[] = { 24, }; +-static int mt7623_pcie2_0_perst_funcs[] = { 2, }; +-static int mt7623_pcie2_1_perst_pins[] = { 29, }; +-static int mt7623_pcie2_1_perst_funcs[] = { 6, }; +-static int mt7623_pcie0_0_wake_pins[] = { 28, }; +-static int mt7623_pcie0_0_wake_funcs[] = { 6, }; +-static int mt7623_pcie0_1_wake_pins[] = { 251, }; +-static int mt7623_pcie0_1_wake_funcs[] = { 6, }; +-static int mt7623_pcie1_0_wake_pins[] = { 27, }; +-static int mt7623_pcie1_0_wake_funcs[] = { 6, }; +-static int mt7623_pcie1_1_wake_pins[] = { 253, }; +-static int mt7623_pcie1_1_wake_funcs[] = { 6, }; +-static int mt7623_pcie2_0_wake_pins[] = { 26, }; +-static int mt7623_pcie2_0_wake_funcs[] = { 6, }; +-static int mt7623_pcie2_1_wake_pins[] = { 255, }; +-static int mt7623_pcie2_1_wake_funcs[] = { 6, }; +-static int mt7623_pcie0_clkreq_pins[] = { 250, }; +-static int mt7623_pcie0_clkreq_funcs[] = { 6, }; +-static int mt7623_pcie1_clkreq_pins[] = { 252, }; +-static int mt7623_pcie1_clkreq_funcs[] = { 6, }; +-static int mt7623_pcie2_clkreq_pins[] = { 254, }; +-static int mt7623_pcie2_clkreq_funcs[] = { 6, }; ++static const int mt7623_pcie0_0_perst_pins[] = { 208, }; ++static const int mt7623_pcie0_0_perst_funcs[] = { 3, }; ++static const int mt7623_pcie0_1_perst_pins[] = { 22, }; ++static const int mt7623_pcie0_1_perst_funcs[] = { 2, }; ++static const int mt7623_pcie1_0_perst_pins[] = { 209, }; ++static const int mt7623_pcie1_0_perst_funcs[] = { 3, }; ++static const int mt7623_pcie1_1_perst_pins[] = { 23, }; ++static const int mt7623_pcie1_1_perst_funcs[] = { 2, }; ++static const int mt7623_pcie2_0_perst_pins[] = { 24, }; ++static const int mt7623_pcie2_0_perst_funcs[] = { 2, }; ++static const int mt7623_pcie2_1_perst_pins[] = { 29, }; ++static const int mt7623_pcie2_1_perst_funcs[] = { 6, }; ++static const int mt7623_pcie0_0_wake_pins[] = { 28, }; ++static const int mt7623_pcie0_0_wake_funcs[] = { 6, }; ++static const int mt7623_pcie0_1_wake_pins[] = { 251, }; ++static const int mt7623_pcie0_1_wake_funcs[] = { 6, }; ++static const int mt7623_pcie1_0_wake_pins[] = { 27, }; ++static const int mt7623_pcie1_0_wake_funcs[] = { 6, }; ++static const int mt7623_pcie1_1_wake_pins[] = { 253, }; ++static const int mt7623_pcie1_1_wake_funcs[] = { 6, }; ++static const int mt7623_pcie2_0_wake_pins[] = { 26, }; ++static const int mt7623_pcie2_0_wake_funcs[] = { 6, }; ++static const int mt7623_pcie2_1_wake_pins[] = { 255, }; ++static const int mt7623_pcie2_1_wake_funcs[] = { 6, }; ++static const int mt7623_pcie0_clkreq_pins[] = { 250, }; ++static const int mt7623_pcie0_clkreq_funcs[] = { 6, }; ++static const int mt7623_pcie1_clkreq_pins[] = { 252, }; ++static const int mt7623_pcie1_clkreq_funcs[] = { 6, }; ++static const int mt7623_pcie2_clkreq_pins[] = { 254, }; ++static const int mt7623_pcie2_clkreq_funcs[] = { 6, }; + /* the pcie_*_rev are only used for MT7623 */ +-static int mt7623_pcie0_0_rev_perst_pins[] = { 208, }; +-static int mt7623_pcie0_0_rev_perst_funcs[] = { 11, }; +-static int mt7623_pcie0_1_rev_perst_pins[] = { 22, }; +-static int mt7623_pcie0_1_rev_perst_funcs[] = { 10, }; +-static int mt7623_pcie1_0_rev_perst_pins[] = { 209, }; +-static int mt7623_pcie1_0_rev_perst_funcs[] = { 11, }; +-static int mt7623_pcie1_1_rev_perst_pins[] = { 23, }; +-static int mt7623_pcie1_1_rev_perst_funcs[] = { 10, }; +-static int mt7623_pcie2_0_rev_perst_pins[] = { 24, }; +-static int mt7623_pcie2_0_rev_perst_funcs[] = { 11, }; +-static int mt7623_pcie2_1_rev_perst_pins[] = { 29, }; +-static int mt7623_pcie2_1_rev_perst_funcs[] = { 14, }; ++static const int mt7623_pcie0_0_rev_perst_pins[] = { 208, }; ++static const int mt7623_pcie0_0_rev_perst_funcs[] = { 11, }; ++static const int mt7623_pcie0_1_rev_perst_pins[] = { 22, }; ++static const int mt7623_pcie0_1_rev_perst_funcs[] = { 10, }; ++static const int mt7623_pcie1_0_rev_perst_pins[] = { 209, }; ++static const int mt7623_pcie1_0_rev_perst_funcs[] = { 11, }; ++static const int mt7623_pcie1_1_rev_perst_pins[] = { 23, }; ++static const int mt7623_pcie1_1_rev_perst_funcs[] = { 10, }; ++static const int mt7623_pcie2_0_rev_perst_pins[] = { 24, }; ++static const int mt7623_pcie2_0_rev_perst_funcs[] = { 11, }; ++static const int mt7623_pcie2_1_rev_perst_pins[] = { 29, }; ++static const int mt7623_pcie2_1_rev_perst_funcs[] = { 14, }; + + /* PCM */ +-static int mt7623_pcm_clk_0_pins[] = { 18, }; +-static int mt7623_pcm_clk_0_funcs[] = { 1, }; +-static int mt7623_pcm_clk_1_pins[] = { 17, }; +-static int mt7623_pcm_clk_1_funcs[] = { 3, }; +-static int mt7623_pcm_clk_2_pins[] = { 35, }; +-static int mt7623_pcm_clk_2_funcs[] = { 3, }; +-static int mt7623_pcm_clk_3_pins[] = { 50, }; +-static int mt7623_pcm_clk_3_funcs[] = { 3, }; +-static int mt7623_pcm_clk_4_pins[] = { 74, }; +-static int mt7623_pcm_clk_4_funcs[] = { 3, }; +-static int mt7623_pcm_clk_5_pins[] = { 191, }; +-static int mt7623_pcm_clk_5_funcs[] = { 3, }; +-static int mt7623_pcm_clk_6_pins[] = { 196, }; +-static int mt7623_pcm_clk_6_funcs[] = { 3, }; +-static int mt7623_pcm_sync_0_pins[] = { 19, }; +-static int mt7623_pcm_sync_0_funcs[] = { 1, }; +-static int mt7623_pcm_sync_1_pins[] = { 30, }; +-static int mt7623_pcm_sync_1_funcs[] = { 3, }; +-static int mt7623_pcm_sync_2_pins[] = { 36, }; +-static int mt7623_pcm_sync_2_funcs[] = { 3, }; +-static int mt7623_pcm_sync_3_pins[] = { 52, }; +-static int mt7623_pcm_sync_3_funcs[] = { 31, }; +-static int mt7623_pcm_sync_4_pins[] = { 73, }; +-static int mt7623_pcm_sync_4_funcs[] = { 3, }; +-static int mt7623_pcm_sync_5_pins[] = { 192, }; +-static int mt7623_pcm_sync_5_funcs[] = { 3, }; +-static int mt7623_pcm_sync_6_pins[] = { 197, }; +-static int mt7623_pcm_sync_6_funcs[] = { 3, }; +-static int mt7623_pcm_rx_0_pins[] = { 20, }; +-static int mt7623_pcm_rx_0_funcs[] = { 1, }; +-static int mt7623_pcm_rx_1_pins[] = { 16, }; +-static int mt7623_pcm_rx_1_funcs[] = { 3, }; +-static int mt7623_pcm_rx_2_pins[] = { 34, }; +-static int mt7623_pcm_rx_2_funcs[] = { 3, }; +-static int mt7623_pcm_rx_3_pins[] = { 51, }; +-static int mt7623_pcm_rx_3_funcs[] = { 3, }; +-static int mt7623_pcm_rx_4_pins[] = { 72, }; +-static int mt7623_pcm_rx_4_funcs[] = { 3, }; +-static int mt7623_pcm_rx_5_pins[] = { 190, }; +-static int mt7623_pcm_rx_5_funcs[] = { 3, }; +-static int mt7623_pcm_rx_6_pins[] = { 195, }; +-static int mt7623_pcm_rx_6_funcs[] = { 3, }; +-static int mt7623_pcm_tx_0_pins[] = { 21, }; +-static int mt7623_pcm_tx_0_funcs[] = { 1, }; +-static int mt7623_pcm_tx_1_pins[] = { 32, }; +-static int mt7623_pcm_tx_1_funcs[] = { 3, }; +-static int mt7623_pcm_tx_2_pins[] = { 33, }; +-static int mt7623_pcm_tx_2_funcs[] = { 3, }; +-static int mt7623_pcm_tx_3_pins[] = { 38, }; +-static int mt7623_pcm_tx_3_funcs[] = { 3, }; +-static int mt7623_pcm_tx_4_pins[] = { 49, }; +-static int mt7623_pcm_tx_4_funcs[] = { 3, }; +-static int mt7623_pcm_tx_5_pins[] = { 189, }; +-static int mt7623_pcm_tx_5_funcs[] = { 3, }; +-static int mt7623_pcm_tx_6_pins[] = { 194, }; +-static int mt7623_pcm_tx_6_funcs[] = { 3, }; ++static const int mt7623_pcm_clk_0_pins[] = { 18, }; ++static const int mt7623_pcm_clk_0_funcs[] = { 1, }; ++static const int mt7623_pcm_clk_1_pins[] = { 17, }; ++static const int mt7623_pcm_clk_1_funcs[] = { 3, }; ++static const int mt7623_pcm_clk_2_pins[] = { 35, }; ++static const int mt7623_pcm_clk_2_funcs[] = { 3, }; ++static const int mt7623_pcm_clk_3_pins[] = { 50, }; ++static const int mt7623_pcm_clk_3_funcs[] = { 3, }; ++static const int mt7623_pcm_clk_4_pins[] = { 74, }; ++static const int mt7623_pcm_clk_4_funcs[] = { 3, }; ++static const int mt7623_pcm_clk_5_pins[] = { 191, }; ++static const int mt7623_pcm_clk_5_funcs[] = { 3, }; ++static const int mt7623_pcm_clk_6_pins[] = { 196, }; ++static const int mt7623_pcm_clk_6_funcs[] = { 3, }; ++static const int mt7623_pcm_sync_0_pins[] = { 19, }; ++static const int mt7623_pcm_sync_0_funcs[] = { 1, }; ++static const int mt7623_pcm_sync_1_pins[] = { 30, }; ++static const int mt7623_pcm_sync_1_funcs[] = { 3, }; ++static const int mt7623_pcm_sync_2_pins[] = { 36, }; ++static const int mt7623_pcm_sync_2_funcs[] = { 3, }; ++static const int mt7623_pcm_sync_3_pins[] = { 52, }; ++static const int mt7623_pcm_sync_3_funcs[] = { 31, }; ++static const int mt7623_pcm_sync_4_pins[] = { 73, }; ++static const int mt7623_pcm_sync_4_funcs[] = { 3, }; ++static const int mt7623_pcm_sync_5_pins[] = { 192, }; ++static const int mt7623_pcm_sync_5_funcs[] = { 3, }; ++static const int mt7623_pcm_sync_6_pins[] = { 197, }; ++static const int mt7623_pcm_sync_6_funcs[] = { 3, }; ++static const int mt7623_pcm_rx_0_pins[] = { 20, }; ++static const int mt7623_pcm_rx_0_funcs[] = { 1, }; ++static const int mt7623_pcm_rx_1_pins[] = { 16, }; ++static const int mt7623_pcm_rx_1_funcs[] = { 3, }; ++static const int mt7623_pcm_rx_2_pins[] = { 34, }; ++static const int mt7623_pcm_rx_2_funcs[] = { 3, }; ++static const int mt7623_pcm_rx_3_pins[] = { 51, }; ++static const int mt7623_pcm_rx_3_funcs[] = { 3, }; ++static const int mt7623_pcm_rx_4_pins[] = { 72, }; ++static const int mt7623_pcm_rx_4_funcs[] = { 3, }; ++static const int mt7623_pcm_rx_5_pins[] = { 190, }; ++static const int mt7623_pcm_rx_5_funcs[] = { 3, }; ++static const int mt7623_pcm_rx_6_pins[] = { 195, }; ++static const int mt7623_pcm_rx_6_funcs[] = { 3, }; ++static const int mt7623_pcm_tx_0_pins[] = { 21, }; ++static const int mt7623_pcm_tx_0_funcs[] = { 1, }; ++static const int mt7623_pcm_tx_1_pins[] = { 32, }; ++static const int mt7623_pcm_tx_1_funcs[] = { 3, }; ++static const int mt7623_pcm_tx_2_pins[] = { 33, }; ++static const int mt7623_pcm_tx_2_funcs[] = { 3, }; ++static const int mt7623_pcm_tx_3_pins[] = { 38, }; ++static const int mt7623_pcm_tx_3_funcs[] = { 3, }; ++static const int mt7623_pcm_tx_4_pins[] = { 49, }; ++static const int mt7623_pcm_tx_4_funcs[] = { 3, }; ++static const int mt7623_pcm_tx_5_pins[] = { 189, }; ++static const int mt7623_pcm_tx_5_funcs[] = { 3, }; ++static const int mt7623_pcm_tx_6_pins[] = { 194, }; ++static const int mt7623_pcm_tx_6_funcs[] = { 3, }; + + /* PWM */ +-static int mt7623_pwm_ch1_0_pins[] = { 203, }; +-static int mt7623_pwm_ch1_0_funcs[] = { 1, }; +-static int mt7623_pwm_ch1_1_pins[] = { 208, }; +-static int mt7623_pwm_ch1_1_funcs[] = { 2, }; +-static int mt7623_pwm_ch1_2_pins[] = { 72, }; +-static int mt7623_pwm_ch1_2_funcs[] = { 4, }; +-static int mt7623_pwm_ch1_3_pins[] = { 88, }; +-static int mt7623_pwm_ch1_3_funcs[] = { 3, }; +-static int mt7623_pwm_ch1_4_pins[] = { 108, }; +-static int mt7623_pwm_ch1_4_funcs[] = { 3, }; +-static int mt7623_pwm_ch2_0_pins[] = { 204, }; +-static int mt7623_pwm_ch2_0_funcs[] = { 1, }; +-static int mt7623_pwm_ch2_1_pins[] = { 53, }; +-static int mt7623_pwm_ch2_1_funcs[] = { 5, }; +-static int mt7623_pwm_ch2_2_pins[] = { 88, }; +-static int mt7623_pwm_ch2_2_funcs[] = { 6, }; +-static int mt7623_pwm_ch2_3_pins[] = { 108, }; +-static int mt7623_pwm_ch2_3_funcs[] = { 6, }; +-static int mt7623_pwm_ch2_4_pins[] = { 209, }; +-static int mt7623_pwm_ch2_4_funcs[] = { 5, }; +-static int mt7623_pwm_ch3_0_pins[] = { 205, }; +-static int mt7623_pwm_ch3_0_funcs[] = { 1, }; +-static int mt7623_pwm_ch3_1_pins[] = { 55, }; +-static int mt7623_pwm_ch3_1_funcs[] = { 5, }; +-static int mt7623_pwm_ch3_2_pins[] = { 89, }; +-static int mt7623_pwm_ch3_2_funcs[] = { 6, }; +-static int mt7623_pwm_ch3_3_pins[] = { 109, }; +-static int mt7623_pwm_ch3_3_funcs[] = { 6, }; +-static int mt7623_pwm_ch4_0_pins[] = { 206, }; +-static int mt7623_pwm_ch4_0_funcs[] = { 1, }; +-static int mt7623_pwm_ch4_1_pins[] = { 90, }; +-static int mt7623_pwm_ch4_1_funcs[] = { 6, }; +-static int mt7623_pwm_ch4_2_pins[] = { 110, }; +-static int mt7623_pwm_ch4_2_funcs[] = { 6, }; +-static int mt7623_pwm_ch4_3_pins[] = { 124, }; +-static int mt7623_pwm_ch4_3_funcs[] = { 5, }; +-static int mt7623_pwm_ch5_0_pins[] = { 207, }; +-static int mt7623_pwm_ch5_0_funcs[] = { 1, }; +-static int mt7623_pwm_ch5_1_pins[] = { 125, }; +-static int mt7623_pwm_ch5_1_funcs[] = { 5, }; ++static const int mt7623_pwm_ch1_0_pins[] = { 203, }; ++static const int mt7623_pwm_ch1_0_funcs[] = { 1, }; ++static const int mt7623_pwm_ch1_1_pins[] = { 208, }; ++static const int mt7623_pwm_ch1_1_funcs[] = { 2, }; ++static const int mt7623_pwm_ch1_2_pins[] = { 72, }; ++static const int mt7623_pwm_ch1_2_funcs[] = { 4, }; ++static const int mt7623_pwm_ch1_3_pins[] = { 88, }; ++static const int mt7623_pwm_ch1_3_funcs[] = { 3, }; ++static const int mt7623_pwm_ch1_4_pins[] = { 108, }; ++static const int mt7623_pwm_ch1_4_funcs[] = { 3, }; ++static const int mt7623_pwm_ch2_0_pins[] = { 204, }; ++static const int mt7623_pwm_ch2_0_funcs[] = { 1, }; ++static const int mt7623_pwm_ch2_1_pins[] = { 53, }; ++static const int mt7623_pwm_ch2_1_funcs[] = { 5, }; ++static const int mt7623_pwm_ch2_2_pins[] = { 88, }; ++static const int mt7623_pwm_ch2_2_funcs[] = { 6, }; ++static const int mt7623_pwm_ch2_3_pins[] = { 108, }; ++static const int mt7623_pwm_ch2_3_funcs[] = { 6, }; ++static const int mt7623_pwm_ch2_4_pins[] = { 209, }; ++static const int mt7623_pwm_ch2_4_funcs[] = { 5, }; ++static const int mt7623_pwm_ch3_0_pins[] = { 205, }; ++static const int mt7623_pwm_ch3_0_funcs[] = { 1, }; ++static const int mt7623_pwm_ch3_1_pins[] = { 55, }; ++static const int mt7623_pwm_ch3_1_funcs[] = { 5, }; ++static const int mt7623_pwm_ch3_2_pins[] = { 89, }; ++static const int mt7623_pwm_ch3_2_funcs[] = { 6, }; ++static const int mt7623_pwm_ch3_3_pins[] = { 109, }; ++static const int mt7623_pwm_ch3_3_funcs[] = { 6, }; ++static const int mt7623_pwm_ch4_0_pins[] = { 206, }; ++static const int mt7623_pwm_ch4_0_funcs[] = { 1, }; ++static const int mt7623_pwm_ch4_1_pins[] = { 90, }; ++static const int mt7623_pwm_ch4_1_funcs[] = { 6, }; ++static const int mt7623_pwm_ch4_2_pins[] = { 110, }; ++static const int mt7623_pwm_ch4_2_funcs[] = { 6, }; ++static const int mt7623_pwm_ch4_3_pins[] = { 124, }; ++static const int mt7623_pwm_ch4_3_funcs[] = { 5, }; ++static const int mt7623_pwm_ch5_0_pins[] = { 207, }; ++static const int mt7623_pwm_ch5_0_funcs[] = { 1, }; ++static const int mt7623_pwm_ch5_1_pins[] = { 125, }; ++static const int mt7623_pwm_ch5_1_funcs[] = { 5, }; + + /* PWRAP */ +-static int mt7623_pwrap_pins[] = { 0, 1, 2, 3, 4, 5, 6, }; +-static int mt7623_pwrap_funcs[] = { 1, 1, 1, 1, 1, 1, 1, }; ++static const int mt7623_pwrap_pins[] = { 0, 1, 2, 3, 4, 5, 6, }; ++static const int mt7623_pwrap_funcs[] = { 1, 1, 1, 1, 1, 1, 1, }; + + /* SPDIF */ +-static int mt7623_spdif_in0_0_pins[] = { 56, }; +-static int mt7623_spdif_in0_0_funcs[] = { 3, }; +-static int mt7623_spdif_in0_1_pins[] = { 201, }; +-static int mt7623_spdif_in0_1_funcs[] = { 1, }; +-static int mt7623_spdif_in1_0_pins[] = { 54, }; +-static int mt7623_spdif_in1_0_funcs[] = { 3, }; +-static int mt7623_spdif_in1_1_pins[] = { 202, }; +-static int mt7623_spdif_in1_1_funcs[] = { 1, }; +-static int mt7623_spdif_out_pins[] = { 202, }; +-static int mt7623_spdif_out_funcs[] = { 1, }; ++static const int mt7623_spdif_in0_0_pins[] = { 56, }; ++static const int mt7623_spdif_in0_0_funcs[] = { 3, }; ++static const int mt7623_spdif_in0_1_pins[] = { 201, }; ++static const int mt7623_spdif_in0_1_funcs[] = { 1, }; ++static const int mt7623_spdif_in1_0_pins[] = { 54, }; ++static const int mt7623_spdif_in1_0_funcs[] = { 3, }; ++static const int mt7623_spdif_in1_1_pins[] = { 202, }; ++static const int mt7623_spdif_in1_1_funcs[] = { 1, }; ++static const int mt7623_spdif_out_pins[] = { 202, }; ++static const int mt7623_spdif_out_funcs[] = { 1, }; + + /* SPI */ +-static int mt7623_spi0_pins[] = { 53, 54, 55, 56, }; +-static int mt7623_spi0_funcs[] = { 1, 1, 1, 1, }; +-static int mt7623_spi1_pins[] = { 7, 199, 8, 9, }; +-static int mt7623_spi1_funcs[] = { 1, 1, 1, 1, }; +-static int mt7623_spi2_pins[] = { 101, 104, 102, 103, }; +-static int mt7623_spi2_funcs[] = { 1, 1, 1, 1, }; ++static const int mt7623_spi0_pins[] = { 53, 54, 55, 56, }; ++static const int mt7623_spi0_funcs[] = { 1, 1, 1, 1, }; ++static const int mt7623_spi1_pins[] = { 7, 199, 8, 9, }; ++static const int mt7623_spi1_funcs[] = { 1, 1, 1, 1, }; ++static const int mt7623_spi2_pins[] = { 101, 104, 102, 103, }; ++static const int mt7623_spi2_funcs[] = { 1, 1, 1, 1, }; + + /* UART */ +-static int mt7623_uart0_0_txd_rxd_pins[] = { 79, 80, }; +-static int mt7623_uart0_0_txd_rxd_funcs[] = { 1, 1, }; +-static int mt7623_uart0_1_txd_rxd_pins[] = { 87, 88, }; +-static int mt7623_uart0_1_txd_rxd_funcs[] = { 5, 5, }; +-static int mt7623_uart0_2_txd_rxd_pins[] = { 107, 108, }; +-static int mt7623_uart0_2_txd_rxd_funcs[] = { 5, 5, }; +-static int mt7623_uart0_3_txd_rxd_pins[] = { 123, 122, }; +-static int mt7623_uart0_3_txd_rxd_funcs[] = { 5, 5, }; +-static int mt7623_uart0_rts_cts_pins[] = { 22, 23, }; +-static int mt7623_uart0_rts_cts_funcs[] = { 1, 1, }; +-static int mt7623_uart1_0_txd_rxd_pins[] = { 81, 82, }; +-static int mt7623_uart1_0_txd_rxd_funcs[] = { 1, 1, }; +-static int mt7623_uart1_1_txd_rxd_pins[] = { 89, 90, }; +-static int mt7623_uart1_1_txd_rxd_funcs[] = { 5, 5, }; +-static int mt7623_uart1_2_txd_rxd_pins[] = { 109, 110, }; +-static int mt7623_uart1_2_txd_rxd_funcs[] = { 5, 5, }; +-static int mt7623_uart1_rts_cts_pins[] = { 24, 25, }; +-static int mt7623_uart1_rts_cts_funcs[] = { 1, 1, }; +-static int mt7623_uart2_0_txd_rxd_pins[] = { 14, 15, }; +-static int mt7623_uart2_0_txd_rxd_funcs[] = { 1, 1, }; +-static int mt7623_uart2_1_txd_rxd_pins[] = { 200, 201, }; +-static int mt7623_uart2_1_txd_rxd_funcs[] = { 6, 6, }; +-static int mt7623_uart2_rts_cts_pins[] = { 242, 243, }; +-static int mt7623_uart2_rts_cts_funcs[] = { 1, 1, }; +-static int mt7623_uart3_txd_rxd_pins[] = { 242, 243, }; +-static int mt7623_uart3_txd_rxd_funcs[] = { 2, 2, }; +-static int mt7623_uart3_rts_cts_pins[] = { 26, 27, }; +-static int mt7623_uart3_rts_cts_funcs[] = { 1, 1, }; ++static const int mt7623_uart0_0_txd_rxd_pins[] = { 79, 80, }; ++static const int mt7623_uart0_0_txd_rxd_funcs[] = { 1, 1, }; ++static const int mt7623_uart0_1_txd_rxd_pins[] = { 87, 88, }; ++static const int mt7623_uart0_1_txd_rxd_funcs[] = { 5, 5, }; ++static const int mt7623_uart0_2_txd_rxd_pins[] = { 107, 108, }; ++static const int mt7623_uart0_2_txd_rxd_funcs[] = { 5, 5, }; ++static const int mt7623_uart0_3_txd_rxd_pins[] = { 123, 122, }; ++static const int mt7623_uart0_3_txd_rxd_funcs[] = { 5, 5, }; ++static const int mt7623_uart0_rts_cts_pins[] = { 22, 23, }; ++static const int mt7623_uart0_rts_cts_funcs[] = { 1, 1, }; ++static const int mt7623_uart1_0_txd_rxd_pins[] = { 81, 82, }; ++static const int mt7623_uart1_0_txd_rxd_funcs[] = { 1, 1, }; ++static const int mt7623_uart1_1_txd_rxd_pins[] = { 89, 90, }; ++static const int mt7623_uart1_1_txd_rxd_funcs[] = { 5, 5, }; ++static const int mt7623_uart1_2_txd_rxd_pins[] = { 109, 110, }; ++static const int mt7623_uart1_2_txd_rxd_funcs[] = { 5, 5, }; ++static const int mt7623_uart1_rts_cts_pins[] = { 24, 25, }; ++static const int mt7623_uart1_rts_cts_funcs[] = { 1, 1, }; ++static const int mt7623_uart2_0_txd_rxd_pins[] = { 14, 15, }; ++static const int mt7623_uart2_0_txd_rxd_funcs[] = { 1, 1, }; ++static const int mt7623_uart2_1_txd_rxd_pins[] = { 200, 201, }; ++static const int mt7623_uart2_1_txd_rxd_funcs[] = { 6, 6, }; ++static const int mt7623_uart2_rts_cts_pins[] = { 242, 243, }; ++static const int mt7623_uart2_rts_cts_funcs[] = { 1, 1, }; ++static const int mt7623_uart3_txd_rxd_pins[] = { 242, 243, }; ++static const int mt7623_uart3_txd_rxd_funcs[] = { 2, 2, }; ++static const int mt7623_uart3_rts_cts_pins[] = { 26, 27, }; ++static const int mt7623_uart3_rts_cts_funcs[] = { 1, 1, }; + + /* Watchdog */ +-static int mt7623_watchdog_0_pins[] = { 11, }; +-static int mt7623_watchdog_0_funcs[] = { 1, }; +-static int mt7623_watchdog_1_pins[] = { 121, }; +-static int mt7623_watchdog_1_funcs[] = { 5, }; ++static const int mt7623_watchdog_0_pins[] = { 11, }; ++static const int mt7623_watchdog_0_funcs[] = { 1, }; ++static const int mt7623_watchdog_1_pins[] = { 121, }; ++static const int mt7623_watchdog_1_funcs[] = { 5, }; + + static const struct mtk_group_desc mt7623_groups[] = { + PINCTRL_PIN_GROUP("aud_ext_clk0", mt7623_aud_ext_clk0), +@@ -1362,7 +1362,7 @@ static const struct mtk_function_desc mt + {"watchdog", mt7623_wdt_groups, ARRAY_SIZE(mt7623_wdt_groups)}, + }; + +-static struct mtk_pinctrl_soc mt7623_data = { ++static const struct mtk_pinctrl_soc mt7623_data = { + .name = "mt7623_pinctrl", + .reg_cal = mt7623_reg_cals, + .pins = mt7623_pins, +--- a/drivers/pinctrl/mediatek/pinctrl-mt7629.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt7629.c +@@ -180,118 +180,118 @@ static const struct mtk_pin_desc mt7629_ + */ + + /* WF 5G */ +-static int mt7629_wf0_5g_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, }; +-static int mt7629_wf0_5g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; ++static const int mt7629_wf0_5g_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, }; ++static const int mt7629_wf0_5g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; + + /* LED for EPHY */ +-static int mt7629_ephy_leds_pins[] = { 12, 13, 14, 15, 16, 17, 18, }; +-static int mt7629_ephy_leds_funcs[] = { 1, 1, 1, 1, 1, 1, 1, }; +-static int mt7629_ephy_led0_pins[] = { 12, }; +-static int mt7629_ephy_led0_funcs[] = { 1, }; +-static int mt7629_ephy_led1_pins[] = { 13, }; +-static int mt7629_ephy_led1_funcs[] = { 1, }; +-static int mt7629_ephy_led2_pins[] = { 14, }; +-static int mt7629_ephy_led2_funcs[] = { 1, }; +-static int mt7629_ephy_led3_pins[] = { 15, }; +-static int mt7629_ephy_led3_funcs[] = { 1, }; +-static int mt7629_ephy_led4_pins[] = { 16, }; +-static int mt7629_ephy_led4_funcs[] = { 1, }; +-static int mt7629_wf2g_led_pins[] = { 17, }; +-static int mt7629_wf2g_led_funcs[] = { 1, }; +-static int mt7629_wf5g_led_pins[] = { 18, }; +-static int mt7629_wf5g_led_funcs[] = { 1, }; ++static const int mt7629_ephy_leds_pins[] = { 12, 13, 14, 15, 16, 17, 18, }; ++static const int mt7629_ephy_leds_funcs[] = { 1, 1, 1, 1, 1, 1, 1, }; ++static const int mt7629_ephy_led0_pins[] = { 12, }; ++static const int mt7629_ephy_led0_funcs[] = { 1, }; ++static const int mt7629_ephy_led1_pins[] = { 13, }; ++static const int mt7629_ephy_led1_funcs[] = { 1, }; ++static const int mt7629_ephy_led2_pins[] = { 14, }; ++static const int mt7629_ephy_led2_funcs[] = { 1, }; ++static const int mt7629_ephy_led3_pins[] = { 15, }; ++static const int mt7629_ephy_led3_funcs[] = { 1, }; ++static const int mt7629_ephy_led4_pins[] = { 16, }; ++static const int mt7629_ephy_led4_funcs[] = { 1, }; ++static const int mt7629_wf2g_led_pins[] = { 17, }; ++static const int mt7629_wf2g_led_funcs[] = { 1, }; ++static const int mt7629_wf5g_led_pins[] = { 18, }; ++static const int mt7629_wf5g_led_funcs[] = { 1, }; + + /* LED for EPHY used as JTAG */ +-static int mt7629_ephy_leds_jtag_pins[] = { 12, 13, 14, 15, 16, }; +-static int mt7629_ephy_leds_jtag_funcs[] = { 7, 7, 7, 7, 7, }; ++static const int mt7629_ephy_leds_jtag_pins[] = { 12, 13, 14, 15, 16, }; ++static const int mt7629_ephy_leds_jtag_funcs[] = { 7, 7, 7, 7, 7, }; + + /* Watchdog */ +-static int mt7629_watchdog_pins[] = { 11, }; +-static int mt7629_watchdog_funcs[] = { 1, }; ++static const int mt7629_watchdog_pins[] = { 11, }; ++static const int mt7629_watchdog_funcs[] = { 1, }; + + /* LED for GPHY */ +-static int mt7629_gphy_leds_0_pins[] = { 21, 22, 23, }; +-static int mt7629_gphy_leds_0_funcs[] = { 2, 2, 2, }; +-static int mt7629_gphy_led1_0_pins[] = { 21, }; +-static int mt7629_gphy_led1_0_funcs[] = { 2, }; +-static int mt7629_gphy_led2_0_pins[] = { 22, }; +-static int mt7629_gphy_led2_0_funcs[] = { 2, }; +-static int mt7629_gphy_led3_0_pins[] = { 23, }; +-static int mt7629_gphy_led3_0_funcs[] = { 2, }; +-static int mt7629_gphy_leds_1_pins[] = { 57, 58, 59, }; +-static int mt7629_gphy_leds_1_funcs[] = { 1, 1, 1, }; +-static int mt7629_gphy_led1_1_pins[] = { 57, }; +-static int mt7629_gphy_led1_1_funcs[] = { 1, }; +-static int mt7629_gphy_led2_1_pins[] = { 58, }; +-static int mt7629_gphy_led2_1_funcs[] = { 1, }; +-static int mt7629_gphy_led3_1_pins[] = { 59, }; +-static int mt7629_gphy_led3_1_funcs[] = { 1, }; ++static const int mt7629_gphy_leds_0_pins[] = { 21, 22, 23, }; ++static const int mt7629_gphy_leds_0_funcs[] = { 2, 2, 2, }; ++static const int mt7629_gphy_led1_0_pins[] = { 21, }; ++static const int mt7629_gphy_led1_0_funcs[] = { 2, }; ++static const int mt7629_gphy_led2_0_pins[] = { 22, }; ++static const int mt7629_gphy_led2_0_funcs[] = { 2, }; ++static const int mt7629_gphy_led3_0_pins[] = { 23, }; ++static const int mt7629_gphy_led3_0_funcs[] = { 2, }; ++static const int mt7629_gphy_leds_1_pins[] = { 57, 58, 59, }; ++static const int mt7629_gphy_leds_1_funcs[] = { 1, 1, 1, }; ++static const int mt7629_gphy_led1_1_pins[] = { 57, }; ++static const int mt7629_gphy_led1_1_funcs[] = { 1, }; ++static const int mt7629_gphy_led2_1_pins[] = { 58, }; ++static const int mt7629_gphy_led2_1_funcs[] = { 1, }; ++static const int mt7629_gphy_led3_1_pins[] = { 59, }; ++static const int mt7629_gphy_led3_1_funcs[] = { 1, }; + + /* I2C */ +-static int mt7629_i2c_0_pins[] = { 19, 20, }; +-static int mt7629_i2c_0_funcs[] = { 1, 1, }; +-static int mt7629_i2c_1_pins[] = { 53, 54, }; +-static int mt7629_i2c_1_funcs[] = { 1, 1, }; ++static const int mt7629_i2c_0_pins[] = { 19, 20, }; ++static const int mt7629_i2c_0_funcs[] = { 1, 1, }; ++static const int mt7629_i2c_1_pins[] = { 53, 54, }; ++static const int mt7629_i2c_1_funcs[] = { 1, 1, }; + + /* SPI */ +-static int mt7629_spi_0_pins[] = { 21, 22, 23, 24, }; +-static int mt7629_spi_0_funcs[] = { 1, 1, 1, 1, }; +-static int mt7629_spi_1_pins[] = { 62, 63, 64, 65, }; +-static int mt7629_spi_1_funcs[] = { 1, 1, 1, 1, }; +-static int mt7629_spi_wp_pins[] = { 66, }; +-static int mt7629_spi_wp_funcs[] = { 1, }; +-static int mt7629_spi_hold_pins[] = { 67, }; +-static int mt7629_spi_hold_funcs[] = { 1, }; ++static const int mt7629_spi_0_pins[] = { 21, 22, 23, 24, }; ++static const int mt7629_spi_0_funcs[] = { 1, 1, 1, 1, }; ++static const int mt7629_spi_1_pins[] = { 62, 63, 64, 65, }; ++static const int mt7629_spi_1_funcs[] = { 1, 1, 1, 1, }; ++static const int mt7629_spi_wp_pins[] = { 66, }; ++static const int mt7629_spi_wp_funcs[] = { 1, }; ++static const int mt7629_spi_hold_pins[] = { 67, }; ++static const int mt7629_spi_hold_funcs[] = { 1, }; + + /* UART */ +-static int mt7629_uart1_0_txd_rxd_pins[] = { 25, 26, }; +-static int mt7629_uart1_0_txd_rxd_funcs[] = { 1, 1, }; +-static int mt7629_uart1_1_txd_rxd_pins[] = { 53, 54, }; +-static int mt7629_uart1_1_txd_rxd_funcs[] = { 2, 2, }; +-static int mt7629_uart2_0_txd_rxd_pins[] = { 29, 30, }; +-static int mt7629_uart2_0_txd_rxd_funcs[] = { 1, 1, }; +-static int mt7629_uart2_1_txd_rxd_pins[] = { 57, 58, }; +-static int mt7629_uart2_1_txd_rxd_funcs[] = { 2, 2, }; +-static int mt7629_uart1_0_cts_rts_pins[] = { 27, 28, }; +-static int mt7629_uart1_0_cts_rts_funcs[] = { 1, 1, }; +-static int mt7629_uart1_1_cts_rts_pins[] = { 55, 56, }; +-static int mt7629_uart1_1_cts_rts_funcs[] = { 2, 2, }; +-static int mt7629_uart2_0_cts_rts_pins[] = { 31, 32, }; +-static int mt7629_uart2_0_cts_rts_funcs[] = { 1, 1, }; +-static int mt7629_uart2_1_cts_rts_pins[] = { 59, 60, }; +-static int mt7629_uart2_1_cts_rts_funcs[] = { 2, 2, }; +-static int mt7629_uart0_txd_rxd_pins[] = { 68, 69, }; +-static int mt7629_uart0_txd_rxd_funcs[] = { 1, 1, }; ++static const int mt7629_uart1_0_txd_rxd_pins[] = { 25, 26, }; ++static const int mt7629_uart1_0_txd_rxd_funcs[] = { 1, 1, }; ++static const int mt7629_uart1_1_txd_rxd_pins[] = { 53, 54, }; ++static const int mt7629_uart1_1_txd_rxd_funcs[] = { 2, 2, }; ++static const int mt7629_uart2_0_txd_rxd_pins[] = { 29, 30, }; ++static const int mt7629_uart2_0_txd_rxd_funcs[] = { 1, 1, }; ++static const int mt7629_uart2_1_txd_rxd_pins[] = { 57, 58, }; ++static const int mt7629_uart2_1_txd_rxd_funcs[] = { 2, 2, }; ++static const int mt7629_uart1_0_cts_rts_pins[] = { 27, 28, }; ++static const int mt7629_uart1_0_cts_rts_funcs[] = { 1, 1, }; ++static const int mt7629_uart1_1_cts_rts_pins[] = { 55, 56, }; ++static const int mt7629_uart1_1_cts_rts_funcs[] = { 2, 2, }; ++static const int mt7629_uart2_0_cts_rts_pins[] = { 31, 32, }; ++static const int mt7629_uart2_0_cts_rts_funcs[] = { 1, 1, }; ++static const int mt7629_uart2_1_cts_rts_pins[] = { 59, 60, }; ++static const int mt7629_uart2_1_cts_rts_funcs[] = { 2, 2, }; ++static const int mt7629_uart0_txd_rxd_pins[] = { 68, 69, }; ++static const int mt7629_uart0_txd_rxd_funcs[] = { 1, 1, }; + + /* MDC/MDIO */ +-static int mt7629_mdc_mdio_pins[] = { 49, 50, }; +-static int mt7629_mdc_mdio_funcs[] = { 1, 1, }; ++static const int mt7629_mdc_mdio_pins[] = { 49, 50, }; ++static const int mt7629_mdc_mdio_funcs[] = { 1, 1, }; + + /* PCIE */ +-static int mt7629_pcie_pereset_pins[] = { 51, }; +-static int mt7629_pcie_pereset_funcs[] = { 1, }; +-static int mt7629_pcie_wake_pins[] = { 55, }; +-static int mt7629_pcie_wake_funcs[] = { 1, }; +-static int mt7629_pcie_clkreq_pins[] = { 56, }; +-static int mt7629_pcie_clkreq_funcs[] = { 1, }; ++static const int mt7629_pcie_pereset_pins[] = { 51, }; ++static const int mt7629_pcie_pereset_funcs[] = { 1, }; ++static const int mt7629_pcie_wake_pins[] = { 55, }; ++static const int mt7629_pcie_wake_funcs[] = { 1, }; ++static const int mt7629_pcie_clkreq_pins[] = { 56, }; ++static const int mt7629_pcie_clkreq_funcs[] = { 1, }; + + /* PWM */ +-static int mt7629_pwm_0_pins[] = { 52, }; +-static int mt7629_pwm_0_funcs[] = { 1, }; +-static int mt7629_pwm_1_pins[] = { 61, }; +-static int mt7629_pwm_1_funcs[] = { 2, }; ++static const int mt7629_pwm_0_pins[] = { 52, }; ++static const int mt7629_pwm_0_funcs[] = { 1, }; ++static const int mt7629_pwm_1_pins[] = { 61, }; ++static const int mt7629_pwm_1_funcs[] = { 2, }; + + /* WF 2G */ +-static int mt7629_wf0_2g_pins[] = { 70, 71, 72, 73, 74, 75, 76, 77, 78, }; +-static int mt7629_wf0_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, }; ++static const int mt7629_wf0_2g_pins[] = { 70, 71, 72, 73, 74, 75, 76, 77, 78, }; ++static const int mt7629_wf0_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, }; + + /* SNFI */ +-static int mt7629_snfi_pins[] = { 62, 63, 64, 65, 66, 67 }; +-static int mt7629_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 }; ++static const int mt7629_snfi_pins[] = { 62, 63, 64, 65, 66, 67 }; ++static const int mt7629_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 }; + + /* SPI NOR */ +-static int mt7629_snor_pins[] = { 62, 63, 64, 65, 66, 67 }; +-static int mt7629_snor_funcs[] = { 1, 1, 1, 1, 1, 1 }; ++static const int mt7629_snor_pins[] = { 62, 63, 64, 65, 66, 67 }; ++static const int mt7629_snor_funcs[] = { 1, 1, 1, 1, 1, 1 }; + + static const struct mtk_group_desc mt7629_groups[] = { + PINCTRL_PIN_GROUP("wf0_5g", mt7629_wf0_5g), +@@ -385,7 +385,7 @@ static const struct mtk_function_desc mt + {"jtag", mt7629_jtag_groups, ARRAY_SIZE(mt7629_jtag_groups)}, + }; + +-static struct mtk_pinctrl_soc mt7629_data = { ++static const struct mtk_pinctrl_soc mt7629_data = { + .name = "mt7629_pinctrl", + .reg_cal = mt7629_reg_cals, + .pins = mt7629_pins, +--- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c +@@ -570,242 +570,246 @@ static const struct mtk_pin_desc mt7981_ + }; + + /* WA_AICE */ +-static int mt7981_wa_aice1_pins[] = { 0, 1, }; +-static int mt7981_wa_aice1_funcs[] = { 2, 2, }; ++static const int mt7981_wa_aice1_pins[] = { 0, 1, }; ++static const int mt7981_wa_aice1_funcs[] = { 2, 2, }; + +-static int mt7981_wa_aice2_pins[] = { 0, 1, }; +-static int mt7981_wa_aice2_funcs[] = { 3, 3, }; ++static const int mt7981_wa_aice2_pins[] = { 0, 1, }; ++static const int mt7981_wa_aice2_funcs[] = { 3, 3, }; + +-static int mt7981_wa_aice3_pins[] = { 28, 29, }; +-static int mt7981_wa_aice3_funcs[] = { 3, 3, }; ++static const int mt7981_wa_aice3_pins[] = { 28, 29, }; ++static const int mt7981_wa_aice3_funcs[] = { 3, 3, }; + +-static int mt7981_wm_aice1_pins[] = { 9, 10, }; +-static int mt7981_wm_aice1_funcs[] = { 2, 2, }; ++static const int mt7981_wm_aice1_pins[] = { 9, 10, }; ++static const int mt7981_wm_aice1_funcs[] = { 2, 2, }; + +-static int mt7981_wm_aice2_pins[] = { 30, 31, }; +-static int mt7981_wm_aice2_funcs[] = { 5, 5, }; ++static const int mt7981_wm_aice2_pins[] = { 30, 31, }; ++static const int mt7981_wm_aice2_funcs[] = { 5, 5, }; + + /* WM_UART */ +-static int mt7981_wm_uart_0_pins[] = { 0, 1, }; +-static int mt7981_wm_uart_0_funcs[] = { 5, 5, }; ++static const int mt7981_wm_uart_0_pins[] = { 0, 1, }; ++static const int mt7981_wm_uart_0_funcs[] = { 5, 5, }; + +-static int mt7981_wm_uart_1_pins[] = { 20, 21, }; +-static int mt7981_wm_uart_1_funcs[] = { 4, 4, }; ++static const int mt7981_wm_uart_1_pins[] = { 20, 21, }; ++static const int mt7981_wm_uart_1_funcs[] = { 4, 4, }; + +-static int mt7981_wm_uart_2_pins[] = { 30, 31, }; +-static int mt7981_wm_uart_2_funcs[] = { 3, 3, }; ++static const int mt7981_wm_uart_2_pins[] = { 30, 31, }; ++static const int mt7981_wm_uart_2_funcs[] = { 3, 3, }; + + /* DFD */ +-static int mt7981_dfd_pins[] = { 0, 1, 4, 5, }; +-static int mt7981_dfd_funcs[] = { 5, 5, 6, 6, }; ++static const int mt7981_dfd_pins[] = { 0, 1, 4, 5, }; ++static const int mt7981_dfd_funcs[] = { 5, 5, 6, 6, }; + + /* SYS_WATCHDOG */ +-static int mt7981_watchdog_pins[] = { 2, }; +-static int mt7981_watchdog_funcs[] = { 1, }; ++static const int mt7981_watchdog_pins[] = { 2, }; ++static const int mt7981_watchdog_funcs[] = { 1, }; + +-static int mt7981_watchdog1_pins[] = { 13, }; +-static int mt7981_watchdog1_funcs[] = { 5, }; ++static const int mt7981_watchdog1_pins[] = { 13, }; ++static const int mt7981_watchdog1_funcs[] = { 5, }; + + /* PCIE_PERESET_N */ +-static int mt7981_pcie_pereset_pins[] = { 3, }; +-static int mt7981_pcie_pereset_funcs[] = { 1, }; ++static const int mt7981_pcie_pereset_pins[] = { 3, }; ++static const int mt7981_pcie_pereset_funcs[] = { 1, }; + + /* JTAG */ +-static int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, }; +-static int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, }; ++static const int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, }; ++static const int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, }; + + /* WM_JTAG */ +-static int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, }; +-static int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, }; ++static const int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, }; ++static const int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, }; + +-static int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, }; +-static int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; ++static const int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, }; ++static const int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; + + /* WO0_JTAG */ +-static int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, }; +-static int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, }; ++static const int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, }; ++static const int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, }; + +-static int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, }; +-static int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; ++static const int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, }; ++static const int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; + + /* UART2 */ +-static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, }; +-static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, }; ++static const int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, }; ++static const int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, }; + + /* GBE_LED0 */ +-static int mt7981_gbe_led0_pins[] = { 8, }; +-static int mt7981_gbe_led0_funcs[] = { 3, }; ++static const int mt7981_gbe_led0_pins[] = { 8, }; ++static const int mt7981_gbe_led0_funcs[] = { 3, }; + + /* PTA_EXT */ +-static int mt7981_pta_ext_0_pins[] = { 4, 5, 6, }; +-static int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, }; ++static const int mt7981_pta_ext_0_pins[] = { 4, 5, 6, }; ++static const int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, }; + +-static int mt7981_pta_ext_1_pins[] = { 22, 23, 24, }; +-static int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, }; ++static const int mt7981_pta_ext_1_pins[] = { 22, 23, 24, }; ++static const int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, }; + + /* PWM2 */ +-static int mt7981_pwm2_pins[] = { 7, }; +-static int mt7981_pwm2_funcs[] = { 4, }; ++static const int mt7981_pwm2_pins[] = { 7, }; ++static const int mt7981_pwm2_funcs[] = { 4, }; + + /* NET_WO0_UART_TXD */ +-static int mt7981_net_wo0_uart_txd_0_pins[] = { 8, }; +-static int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, }; ++static const int mt7981_net_wo0_uart_txd_0_pins[] = { 8, }; ++static const int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, }; + +-static int mt7981_net_wo0_uart_txd_1_pins[] = { 14, }; +-static int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, }; ++static const int mt7981_net_wo0_uart_txd_1_pins[] = { 14, }; ++static const int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, }; + +-static int mt7981_net_wo0_uart_txd_2_pins[] = { 15, }; +-static int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, }; ++static const int mt7981_net_wo0_uart_txd_2_pins[] = { 15, }; ++static const int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, }; + + /* SPI1 */ +-static int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, }; +-static int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, }; ++static const int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, }; ++static const int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, }; + + /* I2C */ +-static int mt7981_i2c0_0_pins[] = { 6, 7, }; +-static int mt7981_i2c0_0_funcs[] = { 6, 6, }; ++static const int mt7981_i2c0_0_pins[] = { 6, 7, }; ++static const int mt7981_i2c0_0_funcs[] = { 6, 6, }; + +-static int mt7981_i2c0_1_pins[] = { 30, 31, }; +-static int mt7981_i2c0_1_funcs[] = { 4, 4, }; ++static const int mt7981_i2c0_1_pins[] = { 30, 31, }; ++static const int mt7981_i2c0_1_funcs[] = { 4, 4, }; + +-static int mt7981_i2c0_2_pins[] = { 36, 37, }; +-static int mt7981_i2c0_2_funcs[] = { 2, 2, }; ++static const int mt7981_i2c0_2_pins[] = { 36, 37, }; ++static const int mt7981_i2c0_2_funcs[] = { 2, 2, }; + +-static int mt7981_u2_phy_i2c_pins[] = { 30, 31, }; +-static int mt7981_u2_phy_i2c_funcs[] = { 6, 6, }; ++static const int mt7981_u2_phy_i2c_pins[] = { 30, 31, }; ++static const int mt7981_u2_phy_i2c_funcs[] = { 6, 6, }; + +-static int mt7981_u3_phy_i2c_pins[] = { 32, 33, }; +-static int mt7981_u3_phy_i2c_funcs[] = { 3, 3, }; ++static const int mt7981_u3_phy_i2c_pins[] = { 32, 33, }; ++static const int mt7981_u3_phy_i2c_funcs[] = { 3, 3, }; + +-static int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, }; +-static int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, }; ++static const int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, }; ++static const int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, }; + +-static int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, }; +-static int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, }; ++static const int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, }; ++static const int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, }; + + /* DFD_NTRST */ +-static int mt7981_dfd_ntrst_pins[] = { 8, }; +-static int mt7981_dfd_ntrst_funcs[] = { 6, }; ++static const int mt7981_dfd_ntrst_pins[] = { 8, }; ++static const int mt7981_dfd_ntrst_funcs[] = { 6, }; + + /* PWM0 */ +-static int mt7981_pwm0_0_pins[] = { 13, }; +-static int mt7981_pwm0_0_funcs[] = { 2, }; ++static const int mt7981_pwm0_0_pins[] = { 13, }; ++static const int mt7981_pwm0_0_funcs[] = { 2, }; + +-static int mt7981_pwm0_1_pins[] = { 15, }; +-static int mt7981_pwm0_1_funcs[] = { 1, }; ++static const int mt7981_pwm0_1_pins[] = { 15, }; ++static const int mt7981_pwm0_1_funcs[] = { 1, }; + + /* PWM1 */ +-static int mt7981_pwm1_0_pins[] = { 14, }; +-static int mt7981_pwm1_0_funcs[] = { 2, }; ++static const int mt7981_pwm1_0_pins[] = { 14, }; ++static const int mt7981_pwm1_0_funcs[] = { 2, }; + +-static int mt7981_pwm1_1_pins[] = { 15, }; +-static int mt7981_pwm1_1_funcs[] = { 3, }; ++static const int mt7981_pwm1_1_pins[] = { 15, }; ++static const int mt7981_pwm1_1_funcs[] = { 3, }; + + /* GBE_LED1 */ +-static int mt7981_gbe_led1_pins[] = { 13, }; +-static int mt7981_gbe_led1_funcs[] = { 3, }; ++static const int mt7981_gbe_led1_pins[] = { 13, }; ++static const int mt7981_gbe_led1_funcs[] = { 3, }; + + /* PCM */ +-static int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 }; +-static int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, }; ++static const int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 }; ++static const int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, }; + + /* UDI */ +-static int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, }; +-static int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, }; ++static const int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, }; ++static const int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, }; + + /* DRV_VBUS */ +-static int mt7981_drv_vbus_pins[] = { 14, }; +-static int mt7981_drv_vbus_funcs[] = { 1, }; ++static const int mt7981_drv_vbus_pins[] = { 14, }; ++static const int mt7981_drv_vbus_funcs[] = { 1, }; + + /* EMMC */ +-static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, }; +-static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; ++static const int mt7981_emmc_45_pins[] = { ++ 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, }; ++static const int mt7981_emmc_45_funcs[] = { ++ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; + + /* SNFI */ +-static int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, }; +-static int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, }; ++static const int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, }; ++static const int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, }; + + /* SPI0 */ +-static int mt7981_spi0_pins[] = { 16, 17, 18, 19, }; +-static int mt7981_spi0_funcs[] = { 1, 1, 1, 1, }; ++static const int mt7981_spi0_pins[] = { 16, 17, 18, 19, }; ++static const int mt7981_spi0_funcs[] = { 1, 1, 1, 1, }; + + /* SPI0 */ +-static int mt7981_spi0_wp_hold_pins[] = { 20, 21, }; +-static int mt7981_spi0_wp_hold_funcs[] = { 1, 1, }; ++static const int mt7981_spi0_wp_hold_pins[] = { 20, 21, }; ++static const int mt7981_spi0_wp_hold_funcs[] = { 1, 1, }; + + /* SPI1 */ +-static int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, }; +-static int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, }; ++static const int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, }; ++static const int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, }; + + /* SPI2 */ +-static int mt7981_spi2_pins[] = { 26, 27, 28, 29, }; +-static int mt7981_spi2_funcs[] = { 1, 1, 1, 1, }; ++static const int mt7981_spi2_pins[] = { 26, 27, 28, 29, }; ++static const int mt7981_spi2_funcs[] = { 1, 1, 1, 1, }; + + /* SPI2 */ +-static int mt7981_spi2_wp_hold_pins[] = { 30, 31, }; +-static int mt7981_spi2_wp_hold_funcs[] = { 1, 1, }; ++static const int mt7981_spi2_wp_hold_pins[] = { 30, 31, }; ++static const int mt7981_spi2_wp_hold_funcs[] = { 1, 1, }; + + /* UART1 */ +-static int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, }; +-static int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, }; ++static const int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, }; ++static const int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, }; + +-static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, }; +-static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, }; ++static const int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, }; ++static const int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, }; + + /* UART2 */ +-static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, }; +-static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, }; ++static const int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, }; ++static const int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, }; + + /* UART0 */ +-static int mt7981_uart0_pins[] = { 32, 33, }; +-static int mt7981_uart0_funcs[] = { 1, 1, }; ++static const int mt7981_uart0_pins[] = { 32, 33, }; ++static const int mt7981_uart0_funcs[] = { 1, 1, }; + + /* PCIE_CLK_REQ */ +-static int mt7981_pcie_clk_pins[] = { 34, }; +-static int mt7981_pcie_clk_funcs[] = { 2, }; ++static const int mt7981_pcie_clk_pins[] = { 34, }; ++static const int mt7981_pcie_clk_funcs[] = { 2, }; + + /* PCIE_WAKE_N */ +-static int mt7981_pcie_wake_pins[] = { 35, }; +-static int mt7981_pcie_wake_funcs[] = { 2, }; ++static const int mt7981_pcie_wake_pins[] = { 35, }; ++static const int mt7981_pcie_wake_funcs[] = { 2, }; + + /* MDC_MDIO */ +-static int mt7981_smi_mdc_mdio_pins[] = { 36, 37, }; +-static int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, }; ++static const int mt7981_smi_mdc_mdio_pins[] = { 36, 37, }; ++static const int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, }; + +-static int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, }; +-static int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, }; ++static const int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, }; ++static const int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, }; + + /* WF0_MODE1 */ +-static int mt7981_wf0_mode1_pins[] = { 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, +- 50, 51, 52, 53, 54, 55, 56 }; +-static int mt7981_wf0_mode1_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, +- 1, 1, 1, 1 }; ++static const int mt7981_wf0_mode1_pins[] = { ++ 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56 }; ++static const int mt7981_wf0_mode1_funcs[] = { ++ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; + + /* WF0_MODE3 */ +-static int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 }; +-static int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 }; ++static const int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 }; ++static const int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 }; + + /* WF2G_LED */ +-static int mt7981_wf2g_led0_pins[] = { 30, }; +-static int mt7981_wf2g_led0_funcs[] = { 2, }; ++static const int mt7981_wf2g_led0_pins[] = { 30, }; ++static const int mt7981_wf2g_led0_funcs[] = { 2, }; + +-static int mt7981_wf2g_led1_pins[] = { 34, }; +-static int mt7981_wf2g_led1_funcs[] = { 1, }; ++static const int mt7981_wf2g_led1_pins[] = { 34, }; ++static const int mt7981_wf2g_led1_funcs[] = { 1, }; + + /* WF5G_LED */ +-static int mt7981_wf5g_led0_pins[] = { 31, }; +-static int mt7981_wf5g_led0_funcs[] = { 2, }; ++static const int mt7981_wf5g_led0_pins[] = { 31, }; ++static const int mt7981_wf5g_led0_funcs[] = { 2, }; + +-static int mt7981_wf5g_led1_pins[] = { 35, }; +-static int mt7981_wf5g_led1_funcs[] = { 1, }; ++static const int mt7981_wf5g_led1_pins[] = { 35, }; ++static const int mt7981_wf5g_led1_funcs[] = { 1, }; + + /* MT7531_INT */ +-static int mt7981_mt7531_int_pins[] = { 38, }; +-static int mt7981_mt7531_int_funcs[] = { 1, }; ++static const int mt7981_mt7531_int_pins[] = { 38, }; ++static const int mt7981_mt7531_int_funcs[] = { 1, }; + + /* ANT_SEL */ +-static int mt7981_ant_sel_pins[] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 }; +-static int mt7981_ant_sel_funcs[] = { 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 }; ++static const int mt7981_ant_sel_pins[] = { ++ 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 }; ++static const int mt7981_ant_sel_funcs[] = { ++ 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 }; + + static const struct mtk_group_desc mt7981_groups[] = { + /* @GPIO(0,1): WA_AICE(2) */ +@@ -1012,7 +1016,7 @@ static const char *const mt7981_pinctrl_ + "iocfg_lb_base", "iocfg_bl_base", "iocfg_tm_base", "iocfg_tl_base", + }; + +-static struct mtk_pinctrl_soc mt7981_data = { ++static const struct mtk_pinctrl_soc mt7981_data = { + .name = "mt7981_pinctrl", + .reg_cal = mt7981_reg_cals, + .pins = mt7981_pins, +--- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c +@@ -554,114 +554,117 @@ static const struct mtk_io_type_desc mt7 + * The hardware probably has multiple combinations of these pinouts. + */ + +-static int mt7986_watchdog_pins[] = { 0, }; +-static int mt7986_watchdog_funcs[] = { 1, }; ++static const int mt7986_watchdog_pins[] = { 0, }; ++static const int mt7986_watchdog_funcs[] = { 1, }; + +-static int mt7986_wifi_led_pins[] = { 1, 2, }; +-static int mt7986_wifi_led_funcs[] = { 1, 1, }; ++static const int mt7986_wifi_led_pins[] = { 1, 2, }; ++static const int mt7986_wifi_led_funcs[] = { 1, 1, }; + +-static int mt7986_i2c_pins[] = { 3, 4, }; +-static int mt7986_i2c_funcs[] = { 1, 1, }; ++static const int mt7986_i2c_pins[] = { 3, 4, }; ++static const int mt7986_i2c_funcs[] = { 1, 1, }; + +-static int mt7986_uart1_0_pins[] = { 7, 8, 9, 10, }; +-static int mt7986_uart1_0_funcs[] = { 3, 3, 3, 3, }; ++static const int mt7986_uart1_0_pins[] = { 7, 8, 9, 10, }; ++static const int mt7986_uart1_0_funcs[] = { 3, 3, 3, 3, }; + +-static int mt7986_spi1_0_pins[] = { 11, 12, 13, 14, }; +-static int mt7986_spi1_0_funcs[] = { 3, 3, 3, 3, }; ++static const int mt7986_spi1_0_pins[] = { 11, 12, 13, 14, }; ++static const int mt7986_spi1_0_funcs[] = { 3, 3, 3, 3, }; + +-static int mt7986_pwm1_1_pins[] = { 20, }; +-static int mt7986_pwm1_1_funcs[] = { 2, }; ++static const int mt7986_pwm1_1_pins[] = { 20, }; ++static const int mt7986_pwm1_1_funcs[] = { 2, }; + +-static int mt7986_pwm0_pins[] = { 21, }; +-static int mt7986_pwm0_funcs[] = { 1, }; ++static const int mt7986_pwm0_pins[] = { 21, }; ++static const int mt7986_pwm0_funcs[] = { 1, }; + +-static int mt7986_pwm1_0_pins[] = { 22, }; +-static int mt7986_pwm1_0_funcs[] = { 1, }; ++static const int mt7986_pwm1_0_pins[] = { 22, }; ++static const int mt7986_pwm1_0_funcs[] = { 1, }; + +-static int mt7986_emmc_45_pins[] = { ++static const int mt7986_emmc_45_pins[] = { + 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, }; +-static int mt7986_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; ++static const int mt7986_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; + +-static int mt7986_snfi_pins[] = { 23, 24, 25, 26, 27, 28, }; +-static int mt7986_snfi_funcs[] = { 1, 1, 1, 1, 1, 1, }; ++static const int mt7986_snfi_pins[] = { 23, 24, 25, 26, 27, 28, }; ++static const int mt7986_snfi_funcs[] = { 1, 1, 1, 1, 1, 1, }; + +-static int mt7986_spi1_1_pins[] = { 23, 24, 25, 26, }; +-static int mt7986_spi1_1_funcs[] = { 3, 3, 3, 3, }; ++static const int mt7986_spi1_1_pins[] = { 23, 24, 25, 26, }; ++static const int mt7986_spi1_1_funcs[] = { 3, 3, 3, 3, }; + +-static int mt7986_uart1_1_pins[] = { 23, 24, 25, 26, }; +-static int mt7986_uart1_1_funcs[] = { 4, 4, 4, 4, }; ++static const int mt7986_uart1_1_pins[] = { 23, 24, 25, 26, }; ++static const int mt7986_uart1_1_funcs[] = { 4, 4, 4, 4, }; + +-static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, }; +-static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, }; ++static const int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, }; ++static const int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, }; + +-static int mt7986_uart1_2_pins[] = { 29, 30, 31, 32, }; +-static int mt7986_uart1_2_funcs[] = { 3, 3, 3, 3, }; ++static const int mt7986_uart1_2_pins[] = { 29, 30, 31, 32, }; ++static const int mt7986_uart1_2_funcs[] = { 3, 3, 3, 3, }; + +-static int mt7986_uart2_0_pins[] = { 29, 30, 31, 32, }; +-static int mt7986_uart2_0_funcs[] = { 4, 4, 4, 4, }; ++static const int mt7986_uart2_0_pins[] = { 29, 30, 31, 32, }; ++static const int mt7986_uart2_0_funcs[] = { 4, 4, 4, 4, }; + +-static int mt7986_spi0_pins[] = { 33, 34, 35, 36, }; +-static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, }; ++static const int mt7986_spi0_pins[] = { 33, 34, 35, 36, }; ++static const int mt7986_spi0_funcs[] = { 1, 1, 1, 1, }; + +-static int mt7986_spi0_wp_hold_pins[] = { 37, 38, }; +-static int mt7986_spi0_wp_hold_funcs[] = { 1, 1, }; ++static const int mt7986_spi0_wp_hold_pins[] = { 37, 38, }; ++static const int mt7986_spi0_wp_hold_funcs[] = { 1, 1, }; + +-static int mt7986_uart2_1_pins[] = { 33, 34, 35, 36, }; +-static int mt7986_uart2_1_funcs[] = { 3, 3, 3, 3, }; ++static const int mt7986_uart2_1_pins[] = { 33, 34, 35, 36, }; ++static const int mt7986_uart2_1_funcs[] = { 3, 3, 3, 3, }; + +-static int mt7986_uart1_3_rx_tx_pins[] = { 35, 36, }; +-static int mt7986_uart1_3_rx_tx_funcs[] = { 2, 2, }; ++static const int mt7986_uart1_3_rx_tx_pins[] = { 35, 36, }; ++static const int mt7986_uart1_3_rx_tx_funcs[] = { 2, 2, }; + +-static int mt7986_uart1_3_cts_rts_pins[] = { 37, 38, }; +-static int mt7986_uart1_3_cts_rts_funcs[] = { 2, 2, }; ++static const int mt7986_uart1_3_cts_rts_pins[] = { 37, 38, }; ++static const int mt7986_uart1_3_cts_rts_funcs[] = { 2, 2, }; + +-static int mt7986_spi1_3_pins[] = { 33, 34, 35, 36, }; +-static int mt7986_spi1_3_funcs[] = { 4, 4, 4, 4, }; ++static const int mt7986_spi1_3_pins[] = { 33, 34, 35, 36, }; ++static const int mt7986_spi1_3_funcs[] = { 4, 4, 4, 4, }; + +-static int mt7986_uart0_pins[] = { 39, 40, }; +-static int mt7986_uart0_funcs[] = { 1, 1, }; ++static const int mt7986_uart0_pins[] = { 39, 40, }; ++static const int mt7986_uart0_funcs[] = { 1, 1, }; + +-static int mt7986_pcie_reset_pins[] = { 41, }; +-static int mt7986_pcie_reset_funcs[] = { 1, }; ++static const int mt7986_pcie_reset_pins[] = { 41, }; ++static const int mt7986_pcie_reset_funcs[] = { 1, }; + +-static int mt7986_uart1_pins[] = { 42, 43, 44, 45, }; +-static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, }; ++static const int mt7986_uart1_pins[] = { 42, 43, 44, 45, }; ++static const int mt7986_uart1_funcs[] = { 1, 1, 1, 1, }; + +-static int mt7986_uart2_pins[] = { 46, 47, 48, 49, }; +-static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, }; ++static const int mt7986_uart2_pins[] = { 46, 47, 48, 49, }; ++static const int mt7986_uart2_funcs[] = { 1, 1, 1, 1, }; + +-static int mt7986_emmc_51_pins[] = { ++static const int mt7986_emmc_51_pins[] = { + 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, }; +-static int mt7986_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; ++static const int mt7986_emmc_51_funcs[] = { ++ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; + +-static int mt7986_pcm_pins[] = { 62, 63, 64, 65, }; +-static int mt7986_pcm_funcs[] = { 1, 1, 1, 1, }; ++static const int mt7986_pcm_pins[] = { 62, 63, 64, 65, }; ++static const int mt7986_pcm_funcs[] = { 1, 1, 1, 1, }; + +-static int mt7986_i2s_pins[] = { 62, 63, 64, 65, }; +-static int mt7986_i2s_funcs[] = { 1, 1, 1, 1, }; ++static const int mt7986_i2s_pins[] = { 62, 63, 64, 65, }; ++static const int mt7986_i2s_funcs[] = { 1, 1, 1, 1, }; + +-static int mt7986_switch_int_pins[] = { 66, }; +-static int mt7986_switch_int_funcs[] = { 1, }; ++static const int mt7986_switch_int_pins[] = { 66, }; ++static const int mt7986_switch_int_funcs[] = { 1, }; + +-static int mt7986_mdc_mdio_pins[] = { 67, 68, }; +-static int mt7986_mdc_mdio_funcs[] = { 1, 1, }; ++static const int mt7986_mdc_mdio_pins[] = { 67, 68, }; ++static const int mt7986_mdc_mdio_funcs[] = { 1, 1, }; + +-static int mt7986_wf_2g_pins[] = {74, 75, 76, 77, 78, 79, 80, 81, 82, 83, }; +-static int mt7986_wf_2g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; ++static const int mt7986_wf_2g_pins[] = { ++ 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, }; ++static const int mt7986_wf_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; + +-static int mt7986_wf_5g_pins[] = {91, 92, 93, 94, 95, 96, 97, 98, 99, 100, }; +-static int mt7986_wf_5g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; ++static const int mt7986_wf_5g_pins[] = { ++ 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, }; ++static const int mt7986_wf_5g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; + +-static int mt7986_wf_dbdc_pins[] = { ++static const int mt7986_wf_dbdc_pins[] = { + 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, }; +-static int mt7986_wf_dbdc_funcs[] = { ++static const int mt7986_wf_dbdc_funcs[] = { + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; + +-static int mt7986_pcie_clk_pins[] = { 9, }; +-static int mt7986_pcie_clk_funcs[] = { 1, }; ++static const int mt7986_pcie_clk_pins[] = { 9, }; ++static const int mt7986_pcie_clk_funcs[] = { 1, }; + +-static int mt7986_pcie_wake_pins[] = { 10, }; +-static int mt7986_pcie_wake_funcs[] = { 1, }; ++static const int mt7986_pcie_wake_pins[] = { 10, }; ++static const int mt7986_pcie_wake_funcs[] = { 1, }; + + static const struct mtk_group_desc mt7986_groups[] = { + PINCTRL_PIN_GROUP("watchdog", mt7986_watchdog), +@@ -738,7 +741,7 @@ static const struct mtk_function_desc mt + {"wifi", mt7986_wf_groups, ARRAY_SIZE(mt7986_wf_groups)}, + }; + +-static struct mtk_pinctrl_soc mt7986_data = { ++static const struct mtk_pinctrl_soc mt7986_data = { + .name = "mt7986_pinctrl", + .reg_cal = mt7986_reg_cals, + .pins = mt7986_pins, +--- a/drivers/pinctrl/mediatek/pinctrl-mt8512.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt8512.c +@@ -315,12 +315,12 @@ static const struct mtk_pin_desc mt8512_ + */ + + /* UART */ +-static int mt8512_uart0_0_rxd_txd_pins[] = { 52, 53, }; +-static int mt8512_uart0_0_rxd_txd_funcs[] = { 1, 1, }; +-static int mt8512_uart1_0_rxd_txd_pins[] = { 54, 55, }; +-static int mt8512_uart1_0_rxd_txd_funcs[] = { 1, 1, }; +-static int mt8512_uart2_0_rxd_txd_pins[] = { 28, 29, }; +-static int mt8512_uart2_0_rxd_txd_funcs[] = { 1, 1, }; ++static const int mt8512_uart0_0_rxd_txd_pins[] = { 52, 53, }; ++static const int mt8512_uart0_0_rxd_txd_funcs[] = { 1, 1, }; ++static const int mt8512_uart1_0_rxd_txd_pins[] = { 54, 55, }; ++static const int mt8512_uart1_0_rxd_txd_funcs[] = { 1, 1, }; ++static const int mt8512_uart2_0_rxd_txd_pins[] = { 28, 29, }; ++static const int mt8512_uart2_0_rxd_txd_funcs[] = { 1, 1, }; + + /* Joint those groups owning the same capability in user point of view which + * allows that people tend to use through the device tree. +@@ -330,13 +330,13 @@ static const char *const mt8512_uart_gro + "uart2_0_rxd_txd", }; + + /* SNAND */ +-static int mt8512_snfi_pins[] = { 71, 76, 77, 78, 79, 80, }; +-static int mt8512_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, }; ++static const int mt8512_snfi_pins[] = { 71, 76, 77, 78, 79, 80, }; ++static const int mt8512_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, }; + + /* MMC0 */ +-static int mt8512_msdc0_pins[] = { 76, 77, 78, 79, 80, 81, 82, 83, 84, +- 85, 86, }; +-static int mt8512_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; ++static const int mt8512_msdc0_pins[] = { 76, 77, 78, 79, 80, 81, 82, 83, 84, ++ 85, 86, }; ++static const int mt8512_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; + + static const struct mtk_group_desc mt8512_groups[] = { + PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8512_uart0_0_rxd_txd), +@@ -356,7 +356,7 @@ static const struct mtk_function_desc mt + {"snand", mt8512_msdc_groups, ARRAY_SIZE(mt8512_msdc_groups)}, + }; + +-static struct mtk_pinctrl_soc mt8512_data = { ++static const struct mtk_pinctrl_soc mt8512_data = { + .name = "mt8512_pinctrl", + .reg_cal = mt8512_reg_cals, + .pins = mt8512_pins, +--- a/drivers/pinctrl/mediatek/pinctrl-mt8516.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c +@@ -326,12 +326,12 @@ static const struct mtk_pin_desc mt8516_ + */ + + /* UART */ +-static int mt8516_uart0_0_rxd_txd_pins[] = { 62, 63, }; +-static int mt8516_uart0_0_rxd_txd_funcs[] = { 1, 1, }; +-static int mt8516_uart1_0_rxd_txd_pins[] = { 64, 65, }; +-static int mt8516_uart1_0_rxd_txd_funcs[] = { 1, 1, }; +-static int mt8516_uart2_0_rxd_txd_pins[] = { 34, 35, }; +-static int mt8516_uart2_0_rxd_txd_funcs[] = { 1, 1, }; ++static const int mt8516_uart0_0_rxd_txd_pins[] = { 62, 63, }; ++static const int mt8516_uart0_0_rxd_txd_funcs[] = { 1, 1, }; ++static const int mt8516_uart1_0_rxd_txd_pins[] = { 64, 65, }; ++static const int mt8516_uart1_0_rxd_txd_funcs[] = { 1, 1, }; ++static const int mt8516_uart2_0_rxd_txd_pins[] = { 34, 35, }; ++static const int mt8516_uart2_0_rxd_txd_funcs[] = { 1, 1, }; + + /* Joint those groups owning the same capability in user point of view which + * allows that people tend to use through the device tree. +@@ -341,9 +341,9 @@ static const char *const mt8516_uart_gro + "uart2_0_rxd_txd", }; + + /* MMC0 */ +-static int mt8516_msdc0_pins[] = { 110, 111, 112, 113, 114, 115, 116, 117, 118, +- 119, 120, }; +-static int mt8516_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; ++static const int mt8516_msdc0_pins[] = { 110, 111, 112, 113, 114, 115, 116, 117, ++ 118, 119, 120, }; ++static const int mt8516_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; + + static const struct mtk_group_desc mt8516_groups[] = { + PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8516_uart0_0_rxd_txd), +--- a/drivers/pinctrl/mediatek/pinctrl-mt8518.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt8518.c +@@ -346,12 +346,12 @@ static const struct mtk_pin_desc mt8518_ + */ + + /* UART */ +-static int mt8518_uart0_0_rxd_txd_pins[] = { 104, 105, }; +-static int mt8518_uart0_0_rxd_txd_funcs[] = { 1, 1, }; +-static int mt8518_uart1_0_rxd_txd_pins[] = { 52, 53, }; +-static int mt8518_uart1_0_rxd_txd_funcs[] = { 1, 1, }; +-static int mt8518_uart2_0_rxd_txd_pins[] = { 106, 107, }; +-static int mt8518_uart2_0_rxd_txd_funcs[] = { 1, 1, }; ++static const int mt8518_uart0_0_rxd_txd_pins[] = { 104, 105, }; ++static const int mt8518_uart0_0_rxd_txd_funcs[] = { 1, 1, }; ++static const int mt8518_uart1_0_rxd_txd_pins[] = { 52, 53, }; ++static const int mt8518_uart1_0_rxd_txd_funcs[] = { 1, 1, }; ++static const int mt8518_uart2_0_rxd_txd_pins[] = { 106, 107, }; ++static const int mt8518_uart2_0_rxd_txd_funcs[] = { 1, 1, }; + + /* Joint those groups owning the same capability in user point of view which + * allows that people tend to use through the device tree. +@@ -361,9 +361,9 @@ static const char *const mt8518_uart_gro + "uart2_0_rxd_txd", }; + + /* MMC0 */ +-static int mt8518_msdc0_pins[] = { 3, 4, 5, 6, 7, 8, 9, 10, 11, +- 12, 13, }; +-static int mt8518_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; ++static const int mt8518_msdc0_pins[] = { 3, 4, 5, 6, 7, 8, 9, 10, 11, ++ 12, 13, }; ++static const int mt8518_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; + + static const struct mtk_group_desc mt8518_groups[] = { + PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8518_uart0_0_rxd_txd), +@@ -380,7 +380,7 @@ static const struct mtk_function_desc mt + {"msdc", mt8518_msdc_groups, ARRAY_SIZE(mt8518_msdc_groups)}, + }; + +-static struct mtk_pinctrl_soc mt8518_data = { ++static const struct mtk_pinctrl_soc mt8518_data = { + .name = "mt8518_pinctrl", + .reg_cal = mt8518_reg_cals, + .pins = mt8518_pins, +--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +@@ -314,7 +314,7 @@ static int mtk_pinmux_group_set(struct u + int i; + + for (i = 0; i < grp->num_pins; i++) { +- int *pin_modes = grp->data; ++ const int *pin_modes = grp->data; + + mtk_hw_set_value(dev, grp->pins[i], PINCTRL_PIN_REG_MODE, + pin_modes[i]); +@@ -769,7 +769,7 @@ static int mtk_gpiochip_register(struct + #endif + + int mtk_pinctrl_common_probe(struct udevice *dev, +- struct mtk_pinctrl_soc *soc) ++ const struct mtk_pinctrl_soc *soc) + { + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + int ret = 0; +--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h ++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +@@ -174,9 +174,9 @@ struct mtk_pin_desc { + */ + struct mtk_group_desc { + const char *name; +- int *pins; ++ const int *pins; + int num_pins; +- void *data; ++ const void *data; + }; + + /** +@@ -233,7 +233,7 @@ struct mtk_pinctrl_soc { + */ + struct mtk_pinctrl_priv { + void __iomem *base[MAX_BASE_CALC]; +- struct mtk_pinctrl_soc *soc; ++ const struct mtk_pinctrl_soc *soc; + }; + + extern const struct pinctrl_ops mtk_pinctrl_ops; +@@ -242,7 +242,7 @@ extern const struct pinctrl_ops mtk_pinc + void mtk_rmw(struct udevice *dev, u32 reg, u32 mask, u32 set); + void mtk_i_rmw(struct udevice *dev, u8 i, u32 reg, u32 mask, u32 set); + int mtk_pinctrl_common_probe(struct udevice *dev, +- struct mtk_pinctrl_soc *soc); ++ const struct mtk_pinctrl_soc *soc); + + #if CONFIG_IS_ENABLED(PINCONF) + diff --git a/package/boot/uboot-mediatek/patches/101-13-pinctrl-mediatek-fix-the-return-value-in-driving-con.patch b/package/boot/uboot-mediatek/patches/101-13-pinctrl-mediatek-fix-the-return-value-in-driving-con.patch new file mode 100644 index 00000000000..d83a89ab37e --- /dev/null +++ b/package/boot/uboot-mediatek/patches/101-13-pinctrl-mediatek-fix-the-return-value-in-driving-con.patch @@ -0,0 +1,37 @@ +From 783c46d29f8b186bd65f3e83f38ad883e8bcec69 Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 19 Jul 2023 17:16:42 +0800 +Subject: [PATCH 13/29] pinctrl: mediatek: fix the return value in driving + configuration functions + +The original mediatek pinctrl functions for driving configuration +'mtk_pinconf_drive_set_*' do not return -ENOSUPP even if input +parameters are not supported. +This patch fixes the return value in those functions. + +Signed-off-by: Sam Shih +Signed-off-by: Weijie Gao +--- + drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +@@ -513,7 +513,7 @@ int mtk_pinconf_drive_set_v0(struct udev + return err; + } + +- return 0; ++ return err; + } + + int mtk_pinconf_drive_set_v1(struct udevice *dev, u32 pin, u32 arg) +@@ -531,7 +531,7 @@ int mtk_pinconf_drive_set_v1(struct udev + return err; + } + +- return 0; ++ return err; + } + + int mtk_pinconf_drive_set(struct udevice *dev, u32 pin, u32 arg) diff --git a/package/boot/uboot-mediatek/patches/101-14-pinctrl-mediatek-add-pinmux_set-ops-support.patch b/package/boot/uboot-mediatek/patches/101-14-pinctrl-mediatek-add-pinmux_set-ops-support.patch new file mode 100644 index 00000000000..7cb185ff42c --- /dev/null +++ b/package/boot/uboot-mediatek/patches/101-14-pinctrl-mediatek-add-pinmux_set-ops-support.patch @@ -0,0 +1,43 @@ +From 090351b416e57e0f7b5d1a4c87d4ed9ab4f5c89b Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 19 Jul 2023 17:16:46 +0800 +Subject: [PATCH 14/29] pinctrl: mediatek: add pinmux_set ops support + +This patch adds pinmux_set ops for mediatek pinctrl framework + +Signed-off-by: Sam Shih +Signed-off-by: Weijie Gao +--- + drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +@@ -304,6 +304,19 @@ static const char *mtk_get_function_name + return priv->soc->funcs[selector].name; + } + ++static int mtk_pinmux_set(struct udevice *dev, unsigned int pin_selector, ++ unsigned int func_selector) ++{ ++ int err; ++ ++ err = mtk_hw_set_value(dev, pin_selector, PINCTRL_PIN_REG_MODE, ++ func_selector); ++ if (err) ++ return err; ++ ++ return 0; ++} ++ + static int mtk_pinmux_group_set(struct udevice *dev, + unsigned int group_selector, + unsigned int func_selector) +@@ -647,6 +660,7 @@ const struct pinctrl_ops mtk_pinctrl_ops + .get_group_name = mtk_get_group_name, + .get_functions_count = mtk_get_functions_count, + .get_function_name = mtk_get_function_name, ++ .pinmux_set = mtk_pinmux_set, + .pinmux_group_set = mtk_pinmux_group_set, + #if CONFIG_IS_ENABLED(PINCONF) + .pinconf_num_params = ARRAY_SIZE(mtk_conf_params), diff --git a/package/boot/uboot-mediatek/patches/101-15-pinctrl-mediatek-add-pinctrl-driver-for-MT7988-SoC.patch b/package/boot/uboot-mediatek/patches/101-15-pinctrl-mediatek-add-pinctrl-driver-for-MT7988-SoC.patch new file mode 100644 index 00000000000..cfc7c32ba31 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/101-15-pinctrl-mediatek-add-pinctrl-driver-for-MT7988-SoC.patch @@ -0,0 +1,1315 @@ +From 5e821f4ebd9da4ccf3c8871e402996f6a6eb8d1c Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 19 Jul 2023 17:16:50 +0800 +Subject: [PATCH 15/29] pinctrl: mediatek: add pinctrl driver for MT7988 SoC + +This patch adds pinctrl and gpio support for MT7988 SoC + +Signed-off-by: Weijie Gao +--- + drivers/pinctrl/mediatek/Kconfig | 4 + + drivers/pinctrl/mediatek/Makefile | 1 + + drivers/pinctrl/mediatek/pinctrl-mt7988.c | 1274 +++++++++++++++++++++ + 3 files changed, 1279 insertions(+) + create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7988.c + +--- a/drivers/pinctrl/mediatek/Kconfig ++++ b/drivers/pinctrl/mediatek/Kconfig +@@ -24,6 +24,10 @@ config PINCTRL_MT7986 + bool "MT7986 SoC pinctrl driver" + select PINCTRL_MTK + ++config PINCTRL_MT7988 ++ bool "MT7988 SoC pinctrl driver" ++ select PINCTRL_MTK ++ + config PINCTRL_MT8512 + bool "MT8512 SoC pinctrl driver" + select PINCTRL_MTK +--- a/drivers/pinctrl/mediatek/Makefile ++++ b/drivers/pinctrl/mediatek/Makefile +@@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl- + obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o + obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o + obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o ++obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o + obj-$(CONFIG_PINCTRL_MT8512) += pinctrl-mt8512.o + obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o + obj-$(CONFIG_PINCTRL_MT8518) += pinctrl-mt8518.o +--- /dev/null ++++ b/drivers/pinctrl/mediatek/pinctrl-mt7988.c +@@ -0,0 +1,1274 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2022 MediaTek Inc. ++ * Author: Sam Shih ++ */ ++ ++#include ++#include "pinctrl-mtk-common.h" ++ ++enum MT7988_PINCTRL_REG_PAGE { ++ GPIO_BASE, ++ IOCFG_TR_BASE, ++ IOCFG_BR_BASE, ++ IOCFG_RB_BASE, ++ IOCFG_LB_BASE, ++ IOCFG_TL_BASE, ++}; ++ ++#define MT7988_TYPE0_PIN(_number, _name) \ ++ MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP0) ++ ++#define MT7988_TYPE1_PIN(_number, _name) \ ++ MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP1) ++ ++#define MT7988_TYPE2_PIN(_number, _name) \ ++ MTK_TYPED_PIN(_number, _name, DRV_FIXED, IO_TYPE_GRP2) ++ ++#define PIN_FIELD_GPIO(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ ++ PIN_FIELD_BASE_CALC(_s_pin, _e_pin, GPIO_BASE, _s_addr, _x_addrs, \ ++ _s_bit, _x_bits, 32, 0) ++ ++#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ ++ _x_bits) \ ++ PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, \ ++ _s_bit, _x_bits, 32, 0) ++ ++#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ ++ _x_bits) \ ++ PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, \ ++ _s_bit, _x_bits, 32, 1) ++ ++static const struct mtk_pin_field_calc mt7988_pin_mode_range[] = { ++ PIN_FIELD_GPIO(0, 83, 0x300, 0x10, 0, 4), ++}; ++ ++static const struct mtk_pin_field_calc mt7988_pin_dir_range[] = { ++ PIN_FIELD_GPIO(0, 83, 0x0, 0x10, 0, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7988_pin_di_range[] = { ++ PIN_FIELD_GPIO(0, 83, 0x200, 0x10, 0, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7988_pin_do_range[] = { ++ PIN_FIELD_GPIO(0, 83, 0x100, 0x10, 0, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = { ++ PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x30, 0x10, 13, 1), ++ PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x30, 0x10, 14, 1), ++ PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x30, 0x10, 11, 1), ++ PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x30, 0x10, 12, 1), ++ PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x30, 0x10, 0, 1), ++ PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x30, 0x10, 9, 1), ++ PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x30, 0x10, 10, 1), ++ ++ PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x30, 0x10, 8, 1), ++ PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x30, 0x10, 6, 1), ++ PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x30, 0x10, 5, 1), ++ PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x30, 0x10, 3, 1), ++ ++ PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x40, 0x10, 0, 1), ++ PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x40, 0x10, 21, 1), ++ PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x40, 0x10, 1, 1), ++ PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x40, 0x10, 2, 1), ++ ++ PIN_FIELD_BASE(15, 15, IOCFG_TL_BASE, 0x30, 0x10, 7, 1), ++ PIN_FIELD_BASE(16, 16, IOCFG_TL_BASE, 0x30, 0x10, 8, 1), ++ PIN_FIELD_BASE(17, 17, IOCFG_TL_BASE, 0x30, 0x10, 3, 1), ++ PIN_FIELD_BASE(18, 18, IOCFG_TL_BASE, 0x30, 0x10, 4, 1), ++ ++ PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x30, 0x10, 7, 1), ++ PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x30, 0x10, 4, 1), ++ ++ PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x50, 0x10, 17, 1), ++ PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x50, 0x10, 23, 1), ++ PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x50, 0x10, 20, 1), ++ PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x50, 0x10, 19, 1), ++ PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x50, 0x10, 21, 1), ++ PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x50, 0x10, 22, 1), ++ PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x50, 0x10, 18, 1), ++ PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x50, 0x10, 25, 1), ++ PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x50, 0x10, 26, 1), ++ PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x50, 0x10, 27, 1), ++ PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x50, 0x10, 24, 1), ++ PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x50, 0x10, 28, 1), ++ PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x60, 0x10, 0, 1), ++ PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x50, 0x10, 31, 1), ++ PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x50, 0x10, 29, 1), ++ PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x50, 0x10, 30, 1), ++ PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x60, 0x10, 1, 1), ++ PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x50, 0x10, 11, 1), ++ PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x50, 0x10, 10, 1), ++ PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x50, 0x10, 0, 1), ++ PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x50, 0x10, 1, 1), ++ PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x50, 0x10, 9, 1), ++ PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x50, 0x10, 8, 1), ++ PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x50, 0x10, 7, 1), ++ PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x50, 0x10, 6, 1), ++ PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x50, 0x10, 5, 1), ++ PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x50, 0x10, 4, 1), ++ PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x50, 0x10, 3, 1), ++ PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x50, 0x10, 2, 1), ++ PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x50, 0x10, 15, 1), ++ PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x50, 0x10, 12, 1), ++ PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x50, 0x10, 13, 1), ++ PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x50, 0x10, 14, 1), ++ PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x50, 0x10, 16, 1), ++ ++ PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x40, 0x10, 14, 1), ++ PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x40, 0x10, 15, 1), ++ PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x40, 0x10, 13, 1), ++ PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x40, 0x10, 4, 1), ++ PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x40, 0x10, 5, 1), ++ PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x40, 0x10, 6, 1), ++ PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x40, 0x10, 3, 1), ++ PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x40, 0x10, 7, 1), ++ PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x40, 0x10, 20, 1), ++ PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x40, 0x10, 8, 1), ++ PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x40, 0x10, 9, 1), ++ PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x40, 0x10, 10, 1), ++ PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x40, 0x10, 11, 1), ++ PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x40, 0x10, 12, 1), ++ ++ PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x30, 0x10, 1, 1), ++ PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x30, 0x10, 2, 1), ++ PIN_FIELD_BASE(71, 71, IOCFG_TL_BASE, 0x30, 0x10, 5, 1), ++ PIN_FIELD_BASE(72, 72, IOCFG_TL_BASE, 0x30, 0x10, 6, 1), ++ ++ PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x30, 0x10, 10, 1), ++ PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x30, 0x10, 1, 1), ++ PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x30, 0x10, 11, 1), ++ PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x30, 0x10, 9, 1), ++ PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x30, 0x10, 2, 1), ++ PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x30, 0x10, 0, 1), ++ PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x30, 0x10, 12, 1), ++ ++ PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x40, 0x10, 18, 1), ++ PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x40, 0x10, 19, 1), ++ PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x40, 0x10, 16, 1), ++ PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x40, 0x10, 17, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = { ++ PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0xc0, 0x10, 13, 1), ++ PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0xc0, 0x10, 14, 1), ++ PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0xc0, 0x10, 11, 1), ++ PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0xc0, 0x10, 12, 1), ++ PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0xc0, 0x10, 0, 1), ++ PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0xc0, 0x10, 9, 1), ++ PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0xc0, 0x10, 10, 1), ++ ++ PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0xb0, 0x10, 8, 1), ++ PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0xb0, 0x10, 6, 1), ++ PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0xb0, 0x10, 5, 1), ++ PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0xb0, 0x10, 3, 1), ++ ++ PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0xe0, 0x10, 0, 1), ++ PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0xe0, 0x10, 21, 1), ++ PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0xe0, 0x10, 1, 1), ++ PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0xe0, 0x10, 2, 1), ++ ++ PIN_FIELD_BASE(15, 15, IOCFG_TL_BASE, 0xc0, 0x10, 7, 1), ++ PIN_FIELD_BASE(16, 16, IOCFG_TL_BASE, 0xc0, 0x10, 8, 1), ++ PIN_FIELD_BASE(17, 17, IOCFG_TL_BASE, 0xc0, 0x10, 3, 1), ++ PIN_FIELD_BASE(18, 18, IOCFG_TL_BASE, 0xc0, 0x10, 4, 1), ++ ++ PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0xb0, 0x10, 7, 1), ++ PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0xb0, 0x10, 4, 1), ++ ++ PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x140, 0x10, 17, 1), ++ PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x140, 0x10, 23, 1), ++ PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x140, 0x10, 20, 1), ++ PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x140, 0x10, 19, 1), ++ PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x140, 0x10, 21, 1), ++ PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x140, 0x10, 22, 1), ++ PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x140, 0x10, 18, 1), ++ PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x140, 0x10, 25, 1), ++ PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x140, 0x10, 26, 1), ++ PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x140, 0x10, 27, 1), ++ PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x140, 0x10, 24, 1), ++ PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x140, 0x10, 28, 1), ++ PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x150, 0x10, 0, 1), ++ PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x140, 0x10, 31, 1), ++ PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x140, 0x10, 29, 1), ++ PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x140, 0x10, 30, 1), ++ PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x150, 0x10, 1, 1), ++ PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x140, 0x10, 11, 1), ++ PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x140, 0x10, 10, 1), ++ PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x140, 0x10, 0, 1), ++ PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x140, 0x10, 1, 1), ++ PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x140, 0x10, 9, 1), ++ PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x140, 0x10, 8, 1), ++ PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x140, 0x10, 7, 1), ++ PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x140, 0x10, 6, 1), ++ PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x140, 0x10, 5, 1), ++ PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x140, 0x10, 4, 1), ++ PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x140, 0x10, 3, 1), ++ PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x140, 0x10, 2, 1), ++ PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x140, 0x10, 15, 1), ++ PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x140, 0x10, 12, 1), ++ PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x140, 0x10, 13, 1), ++ PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x140, 0x10, 14, 1), ++ PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x140, 0x10, 16, 1), ++ ++ PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0xe0, 0x10, 14, 1), ++ PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0xe0, 0x10, 15, 1), ++ PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0xe0, 0x10, 13, 1), ++ PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0xe0, 0x10, 4, 1), ++ PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0xe0, 0x10, 5, 1), ++ PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0xe0, 0x10, 6, 1), ++ PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0xe0, 0x10, 3, 1), ++ PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0xe0, 0x10, 7, 1), ++ PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0xe0, 0x10, 20, 1), ++ PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0xe0, 0x10, 8, 1), ++ PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0xe0, 0x10, 9, 1), ++ PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0xe0, 0x10, 10, 1), ++ PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0xe0, 0x10, 11, 1), ++ PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0xe0, 0x10, 12, 1), ++ ++ PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0xc0, 0x10, 1, 1), ++ PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0xc0, 0x10, 2, 1), ++ PIN_FIELD_BASE(71, 71, IOCFG_TL_BASE, 0xc0, 0x10, 5, 1), ++ PIN_FIELD_BASE(72, 72, IOCFG_TL_BASE, 0xc0, 0x10, 6, 1), ++ ++ PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0xb0, 0x10, 10, 1), ++ PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0xb0, 0x10, 1, 1), ++ PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0xb0, 0x10, 11, 1), ++ PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0xb0, 0x10, 9, 1), ++ PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0xb0, 0x10, 2, 1), ++ PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0xb0, 0x10, 0, 1), ++ PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0xb0, 0x10, 12, 1), ++ ++ PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0xe0, 0x10, 18, 1), ++ PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0xe0, 0x10, 19, 1), ++ PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0xe0, 0x10, 16, 1), ++ PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0xe0, 0x10, 17, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = { ++ PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x60, 0x10, 5, 1), ++ PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x60, 0x10, 4, 1), ++ PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x60, 0x10, 3, 1), ++ PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x60, 0x10, 2, 1), ++ ++ PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x70, 0x10, 0, 1), ++ PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x70, 0x10, 1, 1), ++ PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x70, 0x10, 2, 1), ++ ++ PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x60, 0x10, 7, 1), ++ PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x60, 0x10, 6, 1), ++ PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x60, 0x10, 1, 1), ++ PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x60, 0x10, 0, 1), ++ PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x60, 0x10, 8, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = { ++ PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x40, 0x10, 5, 1), ++ PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x40, 0x10, 4, 1), ++ PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x40, 0x10, 3, 1), ++ PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x40, 0x10, 2, 1), ++ ++ PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x50, 0x10, 0, 1), ++ PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x50, 0x10, 1, 1), ++ ++ PIN_FIELD_BASE(15, 15, IOCFG_TL_BASE, 0x40, 0x10, 4, 1), ++ PIN_FIELD_BASE(16, 16, IOCFG_TL_BASE, 0x40, 0x10, 5, 1), ++ PIN_FIELD_BASE(17, 17, IOCFG_TL_BASE, 0x40, 0x10, 0, 1), ++ PIN_FIELD_BASE(18, 18, IOCFG_TL_BASE, 0x40, 0x10, 1, 1), ++ ++ PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x50, 0x10, 2, 1), ++ PIN_FIELD_BASE(71, 71, IOCFG_TL_BASE, 0x40, 0x10, 2, 1), ++ PIN_FIELD_BASE(72, 72, IOCFG_TL_BASE, 0x40, 0x10, 3, 1), ++ ++ PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x40, 0x10, 7, 1), ++ PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x40, 0x10, 6, 1), ++ PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x40, 0x10, 1, 1), ++ PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x40, 0x10, 0, 1), ++ PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x40, 0x10, 8, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = { ++ PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x00, 0x10, 21, 3), ++ PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x00, 0x10, 24, 3), ++ PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x00, 0x10, 15, 3), ++ PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x00, 0x10, 18, 3), ++ PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x00, 0x10, 0, 3), ++ PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x00, 0x10, 9, 3), ++ PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x00, 0x10, 12, 3), ++ ++ PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x00, 0x10, 24, 3), ++ PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x00, 0x10, 28, 3), ++ PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x00, 0x10, 15, 3), ++ PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x00, 0x10, 9, 3), ++ ++ PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x00, 0x10, 0, 3), ++ PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x20, 0x10, 3, 3), ++ PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x00, 0x10, 3, 3), ++ PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x00, 0x10, 6, 3), ++ ++ PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x00, 0x10, 21, 3), ++ PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x00, 0x10, 12, 3), ++ ++ PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x10, 0x10, 21, 3), ++ PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x20, 0x10, 9, 3), ++ PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x20, 0x10, 0, 3), ++ PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x10, 0x10, 27, 3), ++ PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x20, 0x10, 3, 3), ++ PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x20, 0x10, 6, 3), ++ PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x10, 0x10, 24, 3), ++ PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x20, 0x10, 15, 3), ++ PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x20, 0x10, 18, 3), ++ PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x20, 0x10, 21, 3), ++ PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x20, 0x10, 12, 3), ++ PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x20, 0x10, 24, 3), ++ PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x30, 0x10, 6, 3), ++ PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x30, 0x10, 3, 3), ++ PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x20, 0x10, 27, 3), ++ PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x30, 0x10, 0, 3), ++ PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x30, 0x10, 9, 3), ++ PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x10, 0x10, 3, 3), ++ PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x10, 0x10, 0, 3), ++ PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x00, 0x10, 0, 3), ++ PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x00, 0x10, 3, 3), ++ PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x00, 0x10, 27, 3), ++ PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x00, 0x10, 24, 3), ++ PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x00, 0x10, 21, 3), ++ PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x00, 0x10, 18, 3), ++ PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x00, 0x10, 15, 3), ++ PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x00, 0x10, 12, 3), ++ PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x00, 0x10, 9, 3), ++ PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x00, 0x10, 6, 3), ++ PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x10, 0x10, 15, 3), ++ PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x10, 0x10, 6, 3), ++ PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x10, 0x10, 9, 3), ++ PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x10, 0x10, 12, 3), ++ PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x10, 0x10, 18, 3), ++ ++ PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x10, 0x10, 12, 3), ++ PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x10, 0x10, 15, 3), ++ PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x10, 0x10, 9, 3), ++ PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x00, 0x10, 12, 3), ++ PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x00, 0x10, 15, 3), ++ PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x00, 0x10, 18, 3), ++ PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x00, 0x10, 9, 3), ++ PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x00, 0x10, 21, 3), ++ PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x20, 0x10, 0, 3), ++ PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x00, 0x10, 24, 3), ++ PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x00, 0x10, 27, 3), ++ PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x10, 0x10, 0, 3), ++ PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x10, 0x10, 3, 3), ++ PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x10, 0x10, 6, 3), ++ ++ PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x00, 0x10, 3, 3), ++ PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x00, 0x10, 6, 3), ++ ++ PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x10, 0x10, 0, 3), ++ PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x00, 0x10, 3, 3), ++ PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x10, 0x10, 3, 3), ++ PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x00, 0x10, 27, 3), ++ PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x00, 0x10, 6, 3), ++ PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x00, 0x10, 0, 3), ++ PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x10, 0x10, 6, 3), ++ ++ PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x10, 0x10, 24, 3), ++ PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x10, 0x10, 27, 3), ++ PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x10, 0x10, 18, 3), ++ PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x10, 0x10, 21, 3), ++}; ++ ++static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = { ++ PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x50, 0x10, 7, 1), ++ PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x50, 0x10, 8, 1), ++ PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x50, 0x10, 5, 1), ++ PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x50, 0x10, 6, 1), ++ PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x50, 0x10, 0, 1), ++ PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x50, 0x10, 3, 1), ++ PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x50, 0x10, 4, 1), ++ ++ PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x60, 0x10, 0, 1), ++ PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x60, 0x10, 18, 1), ++ ++ PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x50, 0x10, 2, 1), ++ PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x50, 0x10, 1, 1), ++ ++ PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x70, 0x10, 17, 1), ++ PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x70, 0x10, 23, 1), ++ PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x70, 0x10, 20, 1), ++ PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x70, 0x10, 19, 1), ++ PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x70, 0x10, 21, 1), ++ PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x70, 0x10, 22, 1), ++ PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x70, 0x10, 18, 1), ++ PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x70, 0x10, 25, 1), ++ PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x70, 0x10, 26, 1), ++ PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x70, 0x10, 27, 1), ++ PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x70, 0x10, 24, 1), ++ PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x70, 0x10, 28, 1), ++ PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x80, 0x10, 0, 1), ++ PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x70, 0x10, 31, 1), ++ PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x70, 0x10, 29, 1), ++ PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x70, 0x10, 30, 1), ++ PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x80, 0x10, 1, 1), ++ PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x70, 0x10, 11, 1), ++ PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x70, 0x10, 10, 1), ++ PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x70, 0x10, 0, 1), ++ PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x70, 0x10, 1, 1), ++ PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x70, 0x10, 9, 1), ++ PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x70, 0x10, 8, 1), ++ PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x70, 0x10, 7, 1), ++ PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x70, 0x10, 6, 1), ++ PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x70, 0x10, 5, 1), ++ PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x70, 0x10, 4, 1), ++ PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x70, 0x10, 3, 1), ++ PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x70, 0x10, 2, 1), ++ PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x70, 0x10, 15, 1), ++ PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x70, 0x10, 12, 1), ++ PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x70, 0x10, 13, 1), ++ PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x70, 0x10, 14, 1), ++ PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x70, 0x10, 16, 1), ++ ++ PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x60, 0x10, 12, 1), ++ PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x60, 0x10, 13, 1), ++ PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x60, 0x10, 11, 1), ++ PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x60, 0x10, 2, 1), ++ PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x60, 0x10, 3, 1), ++ PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x60, 0x10, 4, 1), ++ PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x60, 0x10, 1, 1), ++ PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x60, 0x10, 5, 1), ++ PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x60, 0x10, 6, 1), ++ PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x60, 0x10, 7, 1), ++ PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x60, 0x10, 8, 1), ++ PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x60, 0x10, 9, 1), ++ PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x60, 0x10, 10, 1), ++ ++ PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x50, 0x10, 1, 1), ++ PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x50, 0x10, 2, 1), ++ ++ PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x50, 0x10, 3, 1), ++ PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x50, 0x10, 0, 1), ++ ++ PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x60, 0x10, 16, 1), ++ PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x60, 0x10, 17, 1), ++ PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x60, 0x10, 14, 1), ++ PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x60, 0x10, 15, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = { ++ PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x60, 0x10, 7, 1), ++ PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x60, 0x10, 8, 1), ++ PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x60, 0x10, 5, 1), ++ PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x60, 0x10, 6, 1), ++ PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x60, 0x10, 0, 1), ++ PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x60, 0x10, 3, 1), ++ PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x60, 0x10, 4, 1), ++ ++ PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x80, 0x10, 0, 1), ++ PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x80, 0x10, 18, 1), ++ ++ PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x70, 0x10, 2, 1), ++ PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x70, 0x10, 1, 1), ++ ++ PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x90, 0x10, 17, 1), ++ PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x90, 0x10, 23, 1), ++ PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x90, 0x10, 20, 1), ++ PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x90, 0x10, 19, 1), ++ PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x90, 0x10, 21, 1), ++ PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x90, 0x10, 22, 1), ++ PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x90, 0x10, 18, 1), ++ PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x90, 0x10, 25, 1), ++ PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x90, 0x10, 26, 1), ++ PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x90, 0x10, 27, 1), ++ PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x90, 0x10, 24, 1), ++ PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x90, 0x10, 28, 1), ++ PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0xa0, 0x10, 0, 1), ++ PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x90, 0x10, 31, 1), ++ PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x90, 0x10, 29, 1), ++ PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x90, 0x10, 30, 1), ++ PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0xa0, 0x10, 1, 1), ++ PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x90, 0x10, 11, 1), ++ PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x90, 0x10, 10, 1), ++ PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x90, 0x10, 0, 1), ++ PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x90, 0x10, 1, 1), ++ PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x90, 0x10, 9, 1), ++ PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x90, 0x10, 8, 1), ++ PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x90, 0x10, 7, 1), ++ PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x90, 0x10, 6, 1), ++ PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x90, 0x10, 5, 1), ++ PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x90, 0x10, 4, 1), ++ PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x90, 0x10, 3, 1), ++ PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x90, 0x10, 2, 1), ++ PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x90, 0x10, 15, 1), ++ PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x90, 0x10, 12, 1), ++ PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x90, 0x10, 13, 1), ++ PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x90, 0x10, 14, 1), ++ PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x90, 0x10, 16, 1), ++ ++ PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x80, 0x10, 12, 1), ++ PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x80, 0x10, 13, 1), ++ PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x80, 0x10, 11, 1), ++ PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x80, 0x10, 2, 1), ++ PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x80, 0x10, 3, 1), ++ PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x80, 0x10, 4, 1), ++ PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x80, 0x10, 1, 1), ++ PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x80, 0x10, 5, 1), ++ PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x80, 0x10, 6, 1), ++ PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x80, 0x10, 7, 1), ++ PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x80, 0x10, 8, 1), ++ PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x80, 0x10, 9, 1), ++ PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x80, 0x10, 10, 1), ++ ++ PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x60, 0x10, 1, 1), ++ PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x60, 0x10, 2, 1), ++ ++ PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x70, 0x10, 3, 1), ++ PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x70, 0x10, 0, 1), ++ ++ PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x80, 0x10, 16, 1), ++ PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x80, 0x10, 17, 1), ++ PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x80, 0x10, 14, 1), ++ PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x80, 0x10, 15, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = { ++ PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x70, 0x10, 7, 1), ++ PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x70, 0x10, 8, 1), ++ PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x70, 0x10, 5, 1), ++ PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x70, 0x10, 6, 1), ++ PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x70, 0x10, 0, 1), ++ PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x70, 0x10, 3, 1), ++ PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x70, 0x10, 4, 1), ++ ++ PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x90, 0x10, 0, 1), ++ PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x90, 0x10, 18, 1), ++ ++ PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x80, 0x10, 2, 1), ++ PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x80, 0x10, 1, 1), ++ ++ PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0xb0, 0x10, 17, 1), ++ PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0xb0, 0x10, 23, 1), ++ PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0xb0, 0x10, 20, 1), ++ PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0xb0, 0x10, 19, 1), ++ PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0xb0, 0x10, 21, 1), ++ PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0xb0, 0x10, 22, 1), ++ PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0xb0, 0x10, 18, 1), ++ PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0xb0, 0x10, 25, 1), ++ PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0xb0, 0x10, 26, 1), ++ PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0xb0, 0x10, 27, 1), ++ PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0xb0, 0x10, 24, 1), ++ PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0xb0, 0x10, 28, 1), ++ PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0xc0, 0x10, 0, 1), ++ PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0xb0, 0x10, 31, 1), ++ PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0xb0, 0x10, 29, 1), ++ PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0xb0, 0x10, 30, 1), ++ PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0xc0, 0x10, 1, 1), ++ PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0xb0, 0x10, 11, 1), ++ PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0xb0, 0x10, 10, 1), ++ PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0xb0, 0x10, 0, 1), ++ PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0xb0, 0x10, 1, 1), ++ PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0xb0, 0x10, 9, 1), ++ PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0xb0, 0x10, 8, 1), ++ PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0xb0, 0x10, 7, 1), ++ PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0xb0, 0x10, 6, 1), ++ PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0xb0, 0x10, 5, 1), ++ PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0xb0, 0x10, 4, 1), ++ PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0xb0, 0x10, 3, 1), ++ PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0xb0, 0x10, 2, 1), ++ PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0xb0, 0x10, 15, 1), ++ PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0xb0, 0x10, 12, 1), ++ PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0xb0, 0x10, 13, 1), ++ PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0xb0, 0x10, 14, 1), ++ PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0xb0, 0x10, 16, 1), ++ ++ PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x90, 0x10, 12, 1), ++ PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x90, 0x10, 13, 1), ++ PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x90, 0x10, 11, 1), ++ PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x90, 0x10, 2, 1), ++ PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x90, 0x10, 3, 1), ++ PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x90, 0x10, 4, 1), ++ PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x90, 0x10, 1, 1), ++ PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x90, 0x10, 5, 1), ++ PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x90, 0x10, 6, 1), ++ PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x90, 0x10, 7, 1), ++ PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x90, 0x10, 8, 1), ++ PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x90, 0x10, 9, 1), ++ PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x90, 0x10, 10, 1), ++ ++ PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x70, 0x10, 1, 1), ++ PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x70, 0x10, 2, 1), ++ ++ PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x80, 0x10, 3, 1), ++ PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x80, 0x10, 0, 1), ++ ++ PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x90, 0x10, 16, 1), ++ PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x90, 0x10, 17, 1), ++ PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x90, 0x10, 14, 1), ++ PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x90, 0x10, 15, 1), ++}; ++ ++static const struct mtk_pin_reg_calc mt7988_reg_cals[] = { ++ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7988_pin_mode_range), ++ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7988_pin_dir_range), ++ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7988_pin_di_range), ++ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7988_pin_do_range), ++ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7988_pin_smt_range), ++ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7988_pin_ies_range), ++ [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7988_pin_pu_range), ++ [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7988_pin_pd_range), ++ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7988_pin_drv_range), ++ [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7988_pin_pupd_range), ++ [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7988_pin_r0_range), ++ [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7988_pin_r1_range), ++}; ++ ++static const struct mtk_pin_desc mt7988_pins[] = { ++ MT7988_TYPE0_PIN(0, "UART2_RXD"), ++ MT7988_TYPE0_PIN(1, "UART2_TXD"), ++ MT7988_TYPE0_PIN(2, "UART2_CTS"), ++ MT7988_TYPE0_PIN(3, "UART2_RTS"), ++ MT7988_TYPE0_PIN(4, "GPIO_A"), ++ MT7988_TYPE0_PIN(5, "SMI_0_MDC"), ++ MT7988_TYPE0_PIN(6, "SMI_0_MDIO"), ++ MT7988_TYPE1_PIN(7, "PCIE30_2L_0_WAKE_N"), ++ MT7988_TYPE1_PIN(8, "PCIE30_2L_0_CLKREQ_N"), ++ MT7988_TYPE1_PIN(9, "PCIE30_1L_1_WAKE_N"), ++ MT7988_TYPE1_PIN(10, "PCIE30_1L_1_CLKREQ_N"), ++ MT7988_TYPE0_PIN(11, "GPIO_P"), ++ MT7988_TYPE0_PIN(12, "WATCHDOG"), ++ MT7988_TYPE1_PIN(13, "GPIO_RESET"), ++ MT7988_TYPE1_PIN(14, "GPIO_WPS"), ++ MT7988_TYPE2_PIN(15, "PMIC_I2C_SCL"), ++ MT7988_TYPE2_PIN(16, "PMIC_I2C_SDA"), ++ MT7988_TYPE2_PIN(17, "I2C_1_SCL"), ++ MT7988_TYPE2_PIN(18, "I2C_1_SDA"), ++ MT7988_TYPE0_PIN(19, "PCIE30_2L_0_PRESET_N"), ++ MT7988_TYPE0_PIN(20, "PCIE30_1L_1_PRESET_N"), ++ MT7988_TYPE0_PIN(21, "PWMD1"), ++ MT7988_TYPE0_PIN(22, "SPI0_WP"), ++ MT7988_TYPE0_PIN(23, "SPI0_HOLD"), ++ MT7988_TYPE0_PIN(24, "SPI0_CSB"), ++ MT7988_TYPE0_PIN(25, "SPI0_MISO"), ++ MT7988_TYPE0_PIN(26, "SPI0_MOSI"), ++ MT7988_TYPE0_PIN(27, "SPI0_CLK"), ++ MT7988_TYPE0_PIN(28, "SPI1_CSB"), ++ MT7988_TYPE0_PIN(29, "SPI1_MISO"), ++ MT7988_TYPE0_PIN(30, "SPI1_MOSI"), ++ MT7988_TYPE0_PIN(31, "SPI1_CLK"), ++ MT7988_TYPE0_PIN(32, "SPI2_CLK"), ++ MT7988_TYPE0_PIN(33, "SPI2_MOSI"), ++ MT7988_TYPE0_PIN(34, "SPI2_MISO"), ++ MT7988_TYPE0_PIN(35, "SPI2_CSB"), ++ MT7988_TYPE0_PIN(36, "SPI2_HOLD"), ++ MT7988_TYPE0_PIN(37, "SPI2_WP"), ++ MT7988_TYPE0_PIN(38, "EMMC_RSTB"), ++ MT7988_TYPE0_PIN(39, "EMMC_DSL"), ++ MT7988_TYPE0_PIN(40, "EMMC_CK"), ++ MT7988_TYPE0_PIN(41, "EMMC_CMD"), ++ MT7988_TYPE0_PIN(42, "EMMC_DATA_7"), ++ MT7988_TYPE0_PIN(43, "EMMC_DATA_6"), ++ MT7988_TYPE0_PIN(44, "EMMC_DATA_5"), ++ MT7988_TYPE0_PIN(45, "EMMC_DATA_4"), ++ MT7988_TYPE0_PIN(46, "EMMC_DATA_3"), ++ MT7988_TYPE0_PIN(47, "EMMC_DATA_2"), ++ MT7988_TYPE0_PIN(48, "EMMC_DATA_1"), ++ MT7988_TYPE0_PIN(49, "EMMC_DATA_0"), ++ MT7988_TYPE0_PIN(50, "PCM_FS_I2S_LRCK"), ++ MT7988_TYPE0_PIN(51, "PCM_CLK_I2S_BCLK"), ++ MT7988_TYPE0_PIN(52, "PCM_DRX_I2S_DIN"), ++ MT7988_TYPE0_PIN(53, "PCM_DTX_I2S_DOUT"), ++ MT7988_TYPE0_PIN(54, "PCM_MCK_I2S_MCLK"), ++ MT7988_TYPE0_PIN(55, "UART0_RXD"), ++ MT7988_TYPE0_PIN(56, "UART0_TXD"), ++ MT7988_TYPE0_PIN(57, "PWMD0"), ++ MT7988_TYPE0_PIN(58, "JTAG_JTDI"), ++ MT7988_TYPE0_PIN(59, "JTAG_JTDO"), ++ MT7988_TYPE0_PIN(60, "JTAG_JTMS"), ++ MT7988_TYPE0_PIN(61, "JTAG_JTCLK"), ++ MT7988_TYPE0_PIN(62, "JTAG_JTRST_N"), ++ MT7988_TYPE1_PIN(63, "USB_DRV_VBUS_P1"), ++ MT7988_TYPE0_PIN(64, "LED_A"), ++ MT7988_TYPE0_PIN(65, "LED_B"), ++ MT7988_TYPE0_PIN(66, "LED_C"), ++ MT7988_TYPE0_PIN(67, "LED_D"), ++ MT7988_TYPE0_PIN(68, "LED_E"), ++ MT7988_TYPE0_PIN(69, "GPIO_B"), ++ MT7988_TYPE0_PIN(70, "GPIO_C"), ++ MT7988_TYPE2_PIN(71, "I2C_2_SCL"), ++ MT7988_TYPE2_PIN(72, "I2C_2_SDA"), ++ MT7988_TYPE0_PIN(73, "PCIE30_2L_1_PRESET_N"), ++ MT7988_TYPE0_PIN(74, "PCIE30_1L_0_PRESET_N"), ++ MT7988_TYPE1_PIN(75, "PCIE30_2L_1_WAKE_N"), ++ MT7988_TYPE1_PIN(76, "PCIE30_2L_1_CLKREQ_N"), ++ MT7988_TYPE1_PIN(77, "PCIE30_1L_0_WAKE_N"), ++ MT7988_TYPE1_PIN(78, "PCIE30_1L_0_CLKREQ_N"), ++ MT7988_TYPE1_PIN(79, "USB_DRV_VBUS_P0"), ++ MT7988_TYPE0_PIN(80, "UART1_RXD"), ++ MT7988_TYPE0_PIN(81, "UART1_TXD"), ++ MT7988_TYPE0_PIN(82, "UART1_CTS"), ++ MT7988_TYPE0_PIN(83, "UART1_RTS"), ++}; ++ ++/* jtag */ ++static const int mt7988_tops_jtag0_0_pins[] = { 0, 1, 2, 3, 4 }; ++static const int mt7988_tops_jtag0_0_funcs[] = { 2, 2, 2, 2, 2 }; ++ ++static const int mt7988_wo0_jtag_pins[] = { 50, 51, 52, 53, 54 }; ++static const int mt7988_wo0_jtag_funcs[] = { 3, 3, 3, 3, 3 }; ++ ++static const int mt7988_wo1_jtag_pins[] = { 50, 51, 52, 53, 54 }; ++static const int mt7988_wo1_jtag_funcs[] = { 4, 4, 4, 4, 4 }; ++ ++static const int mt7988_wo2_jtag_pins[] = { 50, 51, 52, 53, 54 }; ++static const int mt7988_wo2_jtag_funcs[] = { 5, 5, 5, 5, 5 }; ++ ++static const int mt7988_jtag_pins[] = { 58, 59, 60, 61, 62 }; ++static const int mt7988_jtag_funcs[] = { 1, 1, 1, 1, 1 }; ++ ++static const int mt7988_tops_jtag0_1_pins[] = { 58, 59, 60, 61, 62 }; ++static const int mt7988_tops_jtag0_1_funcs[] = { 4, 4, 4, 4, 4 }; ++ ++/* int_usxgmii */ ++static const int mt7988_int_usxgmii_pins[] = { 2, 3 }; ++static const int mt7988_int_usxgmii_funcs[] = { 3, 3 }; ++ ++/* pwm */ ++static const int mt7988_pwm0_pins[] = { 57 }; ++static const int mt7988_pwm0_funcs[] = { 1 }; ++ ++static const int mt7988_pwm1_pins[] = { 21 }; ++static const int mt7988_pwm1_funcs[] = { 1 }; ++ ++static const int mt7988_pwm2_pins[] = { 80 }; ++static const int mt7988_pwm2_funcs[] = { 2 }; ++ ++static const int mt7988_pwm3_pins[] = { 81 }; ++static const int mt7988_pwm3_funcs[] = { 2 }; ++ ++static const int mt7988_pwm4_pins[] = { 82 }; ++static const int mt7988_pwm4_funcs[] = { 2 }; ++ ++static const int mt7988_pwm5_pins[] = { 83 }; ++static const int mt7988_pwm5_funcs[] = { 2 }; ++ ++static const int mt7988_pwm6_pins[] = { 69 }; ++static const int mt7988_pwm6_funcs[] = { 3 }; ++ ++static const int mt7988_pwm7_pins[] = { 70 }; ++static const int mt7988_pwm7_funcs[] = { 3 }; ++ ++/* dfd */ ++static const int mt7988_dfd_pins[] = { 0, 1, 2, 3, 4 }; ++static const int mt7988_dfd_funcs[] = { 4, 4, 4, 4, 4 }; ++ ++/* i2c */ ++static const int mt7988_xfi_phy0_i2c0_pins[] = { 0, 1 }; ++static const int mt7988_xfi_phy0_i2c0_funcs[] = { 5, 5 }; ++ ++static const int mt7988_xfi_phy1_i2c0_pins[] = { 0, 1 }; ++static const int mt7988_xfi_phy1_i2c0_funcs[] = { 6, 6 }; ++ ++static const int mt7988_xfi_phy_pll_i2c0_pins[] = { 3, 4 }; ++static const int mt7988_xfi_phy_pll_i2c0_funcs[] = { 5, 5 }; ++ ++static const int mt7988_xfi_phy_pll_i2c1_pins[] = { 3, 4 }; ++static const int mt7988_xfi_phy_pll_i2c1_funcs[] = { 6, 6 }; ++ ++static const int mt7988_i2c0_0_pins[] = { 5, 6 }; ++static const int mt7988_i2c0_0_funcs[] = { 2, 2 }; ++ ++static const int mt7988_i2c1_sfp_pins[] = { 5, 6 }; ++static const int mt7988_i2c1_sfp_funcs[] = { 4, 4 }; ++ ++static const int mt7988_xfi_pextp_phy0_i2c_pins[] = { 5, 6 }; ++static const int mt7988_xfi_pextp_phy0_i2c_funcs[] = { 5, 5 }; ++ ++static const int mt7988_xfi_pextp_phy1_i2c_pins[] = { 5, 6 }; ++static const int mt7988_xfi_pextp_phy1_i2c_funcs[] = { 6, 6 }; ++ ++static const int mt7988_i2c0_1_pins[] = { 15, 16 }; ++static const int mt7988_i2c0_1_funcs[] = { 1, 1 }; ++ ++static const int mt7988_u30_phy_i2c0_pins[] = { 15, 16 }; ++static const int mt7988_u30_phy_i2c0_funcs[] = { 2, 2 }; ++ ++static const int mt7988_u32_phy_i2c0_pins[] = { 15, 16 }; ++static const int mt7988_u32_phy_i2c0_funcs[] = { 3, 3 }; ++ ++static const int mt7988_xfi_phy0_i2c1_pins[] = { 15, 16 }; ++static const int mt7988_xfi_phy0_i2c1_funcs[] = { 5, 5 }; ++ ++static const int mt7988_xfi_phy1_i2c1_pins[] = { 15, 16 }; ++static const int mt7988_xfi_phy1_i2c1_funcs[] = { 6, 6 }; ++ ++static const int mt7988_xfi_phy_pll_i2c2_pins[] = { 15, 16 }; ++static const int mt7988_xfi_phy_pll_i2c2_funcs[] = { 7, 7 }; ++ ++static const int mt7988_i2c1_0_pins[] = { 17, 18 }; ++static const int mt7988_i2c1_0_funcs[] = { 1, 1 }; ++ ++static const int mt7988_u30_phy_i2c1_pins[] = { 17, 18 }; ++static const int mt7988_u30_phy_i2c1_funcs[] = { 2, 2 }; ++ ++static const int mt7988_u32_phy_i2c1_pins[] = { 17, 18 }; ++static const int mt7988_u32_phy_i2c1_funcs[] = { 3, 3 }; ++ ++static const int mt7988_xfi_phy_pll_i2c3_pins[] = { 17, 18 }; ++static const int mt7988_xfi_phy_pll_i2c3_funcs[] = { 4, 4 }; ++ ++static const int mt7988_sgmii0_i2c_pins[] = { 17, 18 }; ++static const int mt7988_sgmii0_i2c_funcs[] = { 5, 5 }; ++ ++static const int mt7988_sgmii1_i2c_pins[] = { 17, 18 }; ++static const int mt7988_sgmii1_i2c_funcs[] = { 6, 6 }; ++ ++static const int mt7988_i2c1_2_pins[] = { 69, 70 }; ++static const int mt7988_i2c1_2_funcs[] = { 2, 2 }; ++ ++static const int mt7988_i2c2_0_pins[] = { 69, 70 }; ++static const int mt7988_i2c2_0_funcs[] = { 4, 4 }; ++ ++static const int mt7988_i2c2_1_pins[] = { 71, 72 }; ++static const int mt7988_i2c2_1_funcs[] = { 1, 1 }; ++ ++/* eth */ ++static const int mt7988_mdc_mdio0_pins[] = { 5, 6 }; ++static const int mt7988_mdc_mdio0_funcs[] = { 1, 1 }; ++ ++static const int mt7988_2p5g_ext_mdio_pins[] = { 28, 29 }; ++static const int mt7988_2p5g_ext_mdio_funcs[] = { 6, 6 }; ++ ++static const int mt7988_gbe_ext_mdio_pins[] = { 30, 31 }; ++static const int mt7988_gbe_ext_mdio_funcs[] = { 6, 6 }; ++ ++static const int mt7988_mdc_mdio1_pins[] = { 69, 70 }; ++static const int mt7988_mdc_mdio1_funcs[] = { 1, 1 }; ++ ++/* pcie */ ++static const int mt7988_pcie_wake_n0_0_pins[] = { 7 }; ++static const int mt7988_pcie_wake_n0_0_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_clk_req_n0_0_pins[] = { 8 }; ++static const int mt7988_pcie_clk_req_n0_0_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_wake_n3_0_pins[] = { 9 }; ++static const int mt7988_pcie_wake_n3_0_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_clk_req_n3_pins[] = { 10 }; ++static const int mt7988_pcie_clk_req_n3_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_clk_req_n0_1_pins[] = { 10 }; ++static const int mt7988_pcie_clk_req_n0_1_funcs[] = { 2 }; ++ ++static const int mt7988_pcie_p0_phy_i2c_pins[] = { 7, 8 }; ++static const int mt7988_pcie_p0_phy_i2c_funcs[] = { 3, 3 }; ++ ++static const int mt7988_pcie_p1_phy_i2c_pins[] = { 7, 8 }; ++static const int mt7988_pcie_p1_phy_i2c_funcs[] = { 4, 4 }; ++ ++static const int mt7988_pcie_p3_phy_i2c_pins[] = { 9, 10 }; ++static const int mt7988_pcie_p3_phy_i2c_funcs[] = { 4, 4 }; ++ ++static const int mt7988_pcie_p2_phy_i2c_pins[] = { 7, 8 }; ++static const int mt7988_pcie_p2_phy_i2c_funcs[] = { 5, 5 }; ++ ++static const int mt7988_ckm_phy_i2c_pins[] = { 9, 10 }; ++static const int mt7988_ckm_phy_i2c_funcs[] = { 5, 5 }; ++ ++static const int mt7988_pcie_wake_n0_1_pins[] = { 13 }; ++static const int mt7988_pcie_wake_n0_1_funcs[] = { 2 }; ++ ++static const int mt7988_pcie_wake_n3_1_pins[] = { 14 }; ++static const int mt7988_pcie_wake_n3_1_funcs[] = { 2 }; ++ ++static const int mt7988_pcie_2l_0_pereset_pins[] = { 19 }; ++static const int mt7988_pcie_2l_0_pereset_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_1l_1_pereset_pins[] = { 20 }; ++static const int mt7988_pcie_1l_1_pereset_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_clk_req_n2_1_pins[] = { 63 }; ++static const int mt7988_pcie_clk_req_n2_1_funcs[] = { 2 }; ++ ++static const int mt7988_pcie_2l_1_pereset_pins[] = { 73 }; ++static const int mt7988_pcie_2l_1_pereset_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_1l_0_pereset_pins[] = { 74 }; ++static const int mt7988_pcie_1l_0_pereset_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_wake_n1_0_pins[] = { 75 }; ++static const int mt7988_pcie_wake_n1_0_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_clk_req_n1_pins[] = { 76 }; ++static const int mt7988_pcie_clk_req_n1_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_wake_n2_0_pins[] = { 77 }; ++static const int mt7988_pcie_wake_n2_0_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_clk_req_n2_0_pins[] = { 78 }; ++static const int mt7988_pcie_clk_req_n2_0_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_wake_n2_1_pins[] = { 79 }; ++static const int mt7988_pcie_wake_n2_1_funcs[] = { 2 }; ++ ++/* pmic */ ++static const int mt7988_pmic_pins[] = { 11 }; ++static const int mt7988_pmic_funcs[] = { 1 }; ++ ++/* watchdog */ ++static const int mt7988_watchdog_pins[] = { 12 }; ++static const int mt7988_watchdog_funcs[] = { 1 }; ++ ++/* spi */ ++static const int mt7988_spi0_wp_hold_pins[] = { 22, 23 }; ++static const int mt7988_spi0_wp_hold_funcs[] = { 1, 1 }; ++ ++static const int mt7988_spi0_pins[] = { 24, 25, 26, 27 }; ++static const int mt7988_spi0_funcs[] = { 1, 1, 1, 1 }; ++ ++static const int mt7988_spi1_pins[] = { 28, 29, 30, 31 }; ++static const int mt7988_spi1_funcs[] = { 1, 1, 1, 1 }; ++ ++static const int mt7988_spi2_pins[] = { 32, 33, 34, 35 }; ++static const int mt7988_spi2_funcs[] = { 1, 1, 1, 1 }; ++ ++static const int mt7988_spi2_wp_hold_pins[] = { 36, 37 }; ++static const int mt7988_spi2_wp_hold_funcs[] = { 1, 1 }; ++ ++/* flash */ ++static const int mt7988_snfi_pins[] = { 22, 23, 24, 25, 26, 27 }; ++static const int mt7988_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 }; ++ ++static const int mt7988_emmc_45_pins[] = { ++ 21, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37 }; ++static const int mt7988_emmc_45_funcs[] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 }; ++ ++static const int mt7988_emmc_51_pins[] = { ++ 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49 }; ++static const int mt7988_emmc_51_funcs[] = { ++ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; ++ ++/* uart */ ++static const int mt7988_uart2_pins[] = { 0, 1, 2, 3 }; ++static const int mt7988_uart2_funcs[] = { 1, 1, 1, 1 }; ++ ++static const int mt7988_tops_uart0_0_pins[] = { 22, 23 }; ++static const int mt7988_tops_uart0_0_funcs[] = { 3, 3 }; ++ ++static const int mt7988_uart2_0_pins[] = { 28, 29, 30, 31 }; ++static const int mt7988_uart2_0_funcs[] = { 2, 2, 2, 2 }; ++ ++static const int mt7988_uart1_0_pins[] = { 32, 33, 34, 35 }; ++static const int mt7988_uart1_0_funcs[] = { 2, 2, 2, 2 }; ++ ++static const int mt7988_uart2_1_pins[] = { 32, 33, 34, 35 }; ++static const int mt7988_uart2_1_funcs[] = { 3, 3, 3, 3 }; ++ ++static const int mt7988_net_wo0_uart_txd_0_pins[] = { 28 }; ++static const int mt7988_net_wo0_uart_txd_0_funcs[] = { 3 }; ++ ++static const int mt7988_net_wo1_uart_txd_0_pins[] = { 29 }; ++static const int mt7988_net_wo1_uart_txd_0_funcs[] = { 3 }; ++ ++static const int mt7988_net_wo2_uart_txd_0_pins[] = { 30 }; ++static const int mt7988_net_wo2_uart_txd_0_funcs[] = { 3 }; ++ ++static const int mt7988_tops_uart1_0_pins[] = { 28, 29 }; ++static const int mt7988_tops_uart1_0_funcs[] = { 4, 4 }; ++ ++static const int mt7988_tops_uart0_1_pins[] = { 30, 31 }; ++static const int mt7988_tops_uart0_1_funcs[] = { 4, 4 }; ++ ++static const int mt7988_tops_uart1_1_pins[] = { 36, 37 }; ++static const int mt7988_tops_uart1_1_funcs[] = { 3, 3 }; ++ ++static const int mt7988_uart0_pins[] = { 55, 56 }; ++static const int mt7988_uart0_funcs[] = { 1, 1 }; ++ ++static const int mt7988_tops_uart0_2_pins[] = { 55, 56 }; ++static const int mt7988_tops_uart0_2_funcs[] = { 2, 2 }; ++ ++static const int mt7988_uart2_2_pins[] = { 50, 51, 52, 53 }; ++static const int mt7988_uart2_2_funcs[] = { 2, 2, 2, 2 }; ++ ++static const int mt7988_uart1_1_pins[] = { 58, 59, 60, 61 }; ++static const int mt7988_uart1_1_funcs[] = { 2, 2, 2, 2 }; ++ ++static const int mt7988_uart2_3_pins[] = { 58, 59, 60, 61 }; ++static const int mt7988_uart2_3_funcs[] = { 3, 3, 3, 3 }; ++ ++static const int mt7988_uart1_2_pins[] = { 80, 81, 82, 83 }; ++static const int mt7988_uart1_2_funcs[] = { 1, 1, 1, 1 }; ++ ++static const int mt7988_tops_uart1_2_pins[] = { 80, 81 }; ++static const int mt7988_tops_uart1_2_funcs[] = { 4, 4, }; ++ ++static const int mt7988_net_wo0_uart_txd_1_pins[] = { 80 }; ++static const int mt7988_net_wo0_uart_txd_1_funcs[] = { 3 }; ++ ++static const int mt7988_net_wo1_uart_txd_1_pins[] = { 81 }; ++static const int mt7988_net_wo1_uart_txd_1_funcs[] = { 3 }; ++ ++static const int mt7988_net_wo2_uart_txd_1_pins[] = { 82 }; ++static const int mt7988_net_wo2_uart_txd_1_funcs[] = { 3 }; ++ ++/* udi */ ++static const int mt7988_udi_pins[] = { 32, 33, 34, 35, 36 }; ++static const int mt7988_udi_funcs[] = { 4, 4, 4, 4, 4 }; ++ ++/* pcm */ ++static const int mt7988_pcm_pins[] = { 50, 51, 52, 53, 54 }; ++static const int mt7988_pcm_funcs[] = { 1, 1, 1, 1, 1 }; ++ ++/* led */ ++static const int mt7988_gbe_led1_pins[] = { 58, 59, 60, 61 }; ++static const int mt7988_gbe_led1_funcs[] = { 6, 6, 6, 6 }; ++ ++static const int mt7988_2p5gbe_led1_pins[] = { 62 }; ++static const int mt7988_2p5gbe_led1_funcs[] = { 6 }; ++ ++static const int mt7988_gbe_led0_pins[] = { 64, 65, 66, 67 }; ++static const int mt7988_gbe_led0_funcs[] = { 1, 1, 1, 1 }; ++ ++static const int mt7988_2p5gbe_led0_pins[] = { 68 }; ++static const int mt7988_2p5gbe_led0_funcs[] = { 1 }; ++ ++/* usb */ ++static const int mt7988_drv_vbus_p1_pins[] = { 63 }; ++static const int mt7988_drv_vbus_p1_funcs[] = { 1 }; ++ ++static const int mt7988_drv_vbus_pins[] = { 79 }; ++static const int mt7988_drv_vbus_funcs[] = { 1 }; ++ ++static const struct mtk_group_desc mt7988_groups[] = { ++ PINCTRL_PIN_GROUP("uart2", mt7988_uart2), ++ PINCTRL_PIN_GROUP("tops_jtag0_0", mt7988_tops_jtag0_0), ++ PINCTRL_PIN_GROUP("int_usxgmii", mt7988_int_usxgmii), ++ PINCTRL_PIN_GROUP("dfd", mt7988_dfd), ++ PINCTRL_PIN_GROUP("xfi_phy0_i2c0", mt7988_xfi_phy0_i2c0), ++ PINCTRL_PIN_GROUP("xfi_phy1_i2c0", mt7988_xfi_phy1_i2c0), ++ PINCTRL_PIN_GROUP("xfi_phy_pll_i2c0", mt7988_xfi_phy_pll_i2c0), ++ PINCTRL_PIN_GROUP("xfi_phy_pll_i2c1", mt7988_xfi_phy_pll_i2c1), ++ PINCTRL_PIN_GROUP("i2c0_0", mt7988_i2c0_0), ++ PINCTRL_PIN_GROUP("i2c1_sfp", mt7988_i2c1_sfp), ++ PINCTRL_PIN_GROUP("xfi_pextp_phy0_i2c", mt7988_xfi_pextp_phy0_i2c), ++ PINCTRL_PIN_GROUP("xfi_pextp_phy1_i2c", mt7988_xfi_pextp_phy1_i2c), ++ PINCTRL_PIN_GROUP("mdc_mdio0", mt7988_mdc_mdio0), ++ PINCTRL_PIN_GROUP("pcie_wake_n0_0", mt7988_pcie_wake_n0_0), ++ PINCTRL_PIN_GROUP("pcie_clk_req_n0_0", mt7988_pcie_clk_req_n0_0), ++ PINCTRL_PIN_GROUP("pcie_wake_n3_0", mt7988_pcie_wake_n3_0), ++ PINCTRL_PIN_GROUP("pcie_clk_req_n3", mt7988_pcie_clk_req_n3), ++ PINCTRL_PIN_GROUP("pcie_clk_req_n0_1", mt7988_pcie_clk_req_n0_1), ++ PINCTRL_PIN_GROUP("pcie_p0_phy_i2c", mt7988_pcie_p0_phy_i2c), ++ PINCTRL_PIN_GROUP("pcie_p1_phy_i2c", mt7988_pcie_p1_phy_i2c), ++ PINCTRL_PIN_GROUP("pcie_p2_phy_i2c", mt7988_pcie_p2_phy_i2c), ++ PINCTRL_PIN_GROUP("pcie_p3_phy_i2c", mt7988_pcie_p3_phy_i2c), ++ PINCTRL_PIN_GROUP("ckm_phy_i2c", mt7988_ckm_phy_i2c), ++ PINCTRL_PIN_GROUP("pcie_pmic", mt7988_pmic), ++ PINCTRL_PIN_GROUP("watchdog", mt7988_watchdog), ++ PINCTRL_PIN_GROUP("pcie_wake_n0_1", mt7988_pcie_wake_n0_1), ++ PINCTRL_PIN_GROUP("pcie_wake_n3_1", mt7988_pcie_wake_n3_1), ++ PINCTRL_PIN_GROUP("i2c0_1", mt7988_i2c0_1), ++ PINCTRL_PIN_GROUP("u30_phy_i2c0", mt7988_u30_phy_i2c0), ++ PINCTRL_PIN_GROUP("u32_phy_i2c0", mt7988_u32_phy_i2c0), ++ PINCTRL_PIN_GROUP("xfi_phy0_i2c1", mt7988_xfi_phy0_i2c1), ++ PINCTRL_PIN_GROUP("xfi_phy1_i2c1", mt7988_xfi_phy1_i2c1), ++ PINCTRL_PIN_GROUP("xfi_phy_pll_i2c2", mt7988_xfi_phy_pll_i2c2), ++ PINCTRL_PIN_GROUP("i2c1_0", mt7988_i2c1_0), ++ PINCTRL_PIN_GROUP("u30_phy_i2c1", mt7988_u30_phy_i2c1), ++ PINCTRL_PIN_GROUP("u32_phy_i2c1", mt7988_u32_phy_i2c1), ++ PINCTRL_PIN_GROUP("xfi_phy_pll_i2c3", mt7988_xfi_phy_pll_i2c3), ++ PINCTRL_PIN_GROUP("sgmii0_i2c", mt7988_sgmii0_i2c), ++ PINCTRL_PIN_GROUP("sgmii1_i2c", mt7988_sgmii1_i2c), ++ PINCTRL_PIN_GROUP("pcie_2l_0_pereset", mt7988_pcie_2l_0_pereset), ++ PINCTRL_PIN_GROUP("pcie_1l_1_pereset", mt7988_pcie_1l_1_pereset), ++ PINCTRL_PIN_GROUP("pwm1", mt7988_pwm1), ++ PINCTRL_PIN_GROUP("spi0_wp_hold", mt7988_spi0_wp_hold), ++ PINCTRL_PIN_GROUP("spi0", mt7988_spi0), ++ PINCTRL_PIN_GROUP("spi1", mt7988_spi1), ++ PINCTRL_PIN_GROUP("spi2", mt7988_spi2), ++ PINCTRL_PIN_GROUP("spi2_wp_hold", mt7988_spi2_wp_hold), ++ PINCTRL_PIN_GROUP("snfi", mt7988_snfi), ++ PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart0_0), ++ PINCTRL_PIN_GROUP("uart2_0", mt7988_uart2_0), ++ PINCTRL_PIN_GROUP("uart1_0", mt7988_uart1_0), ++ PINCTRL_PIN_GROUP("uart2_1", mt7988_uart2_1), ++ PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0), ++ PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0), ++ PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0), ++ PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart1_0), ++ PINCTRL_PIN_GROUP("tops_uart0_1", mt7988_tops_uart0_1), ++ PINCTRL_PIN_GROUP("tops_uart1_1", mt7988_tops_uart1_1), ++ PINCTRL_PIN_GROUP("udi", mt7988_udi), ++ PINCTRL_PIN_GROUP("emmc_45", mt7988_emmc_45), ++ PINCTRL_PIN_GROUP("emmc_51", mt7988_emmc_51), ++ PINCTRL_PIN_GROUP("2p5g_ext_mdio", mt7988_2p5g_ext_mdio), ++ PINCTRL_PIN_GROUP("gbe_ext_mdio", mt7988_gbe_ext_mdio), ++ PINCTRL_PIN_GROUP("pcm", mt7988_pcm), ++ PINCTRL_PIN_GROUP("uart0", mt7988_uart0), ++ PINCTRL_PIN_GROUP("tops_uart0_2", mt7988_tops_uart0_2), ++ PINCTRL_PIN_GROUP("uart2_2", mt7988_uart2_2), ++ PINCTRL_PIN_GROUP("wo0_jtag", mt7988_wo0_jtag), ++ PINCTRL_PIN_GROUP("wo1_jtag", mt7988_wo1_jtag), ++ PINCTRL_PIN_GROUP("wo2_jtag", mt7988_wo2_jtag), ++ PINCTRL_PIN_GROUP("pwm0", mt7988_pwm0), ++ PINCTRL_PIN_GROUP("jtag", mt7988_jtag), ++ PINCTRL_PIN_GROUP("tops_jtag0_1", mt7988_tops_jtag0_1), ++ PINCTRL_PIN_GROUP("uart2_3", mt7988_uart2_3), ++ PINCTRL_PIN_GROUP("uart1_1", mt7988_uart1_1), ++ PINCTRL_PIN_GROUP("gbe_led1", mt7988_gbe_led1), ++ PINCTRL_PIN_GROUP("2p5gbe_led1", mt7988_2p5gbe_led1), ++ PINCTRL_PIN_GROUP("gbe_led0", mt7988_gbe_led0), ++ PINCTRL_PIN_GROUP("2p5gbe_led0", mt7988_2p5gbe_led0), ++ PINCTRL_PIN_GROUP("drv_vbus_p1", mt7988_drv_vbus_p1), ++ PINCTRL_PIN_GROUP("pcie_clk_req_n2_1", mt7988_pcie_clk_req_n2_1), ++ PINCTRL_PIN_GROUP("mdc_mdio1", mt7988_mdc_mdio1), ++ PINCTRL_PIN_GROUP("i2c1_2", mt7988_i2c1_2), ++ PINCTRL_PIN_GROUP("pwm6", mt7988_pwm6), ++ PINCTRL_PIN_GROUP("pwm7", mt7988_pwm7), ++ PINCTRL_PIN_GROUP("i2c2_0", mt7988_i2c2_0), ++ PINCTRL_PIN_GROUP("i2c2_1", mt7988_i2c2_1), ++ PINCTRL_PIN_GROUP("pcie_2l_1_pereset", mt7988_pcie_2l_1_pereset), ++ PINCTRL_PIN_GROUP("pcie_1l_0_pereset", mt7988_pcie_1l_0_pereset), ++ PINCTRL_PIN_GROUP("pcie_wake_n1_0", mt7988_pcie_wake_n1_0), ++ PINCTRL_PIN_GROUP("pcie_clk_req_n1", mt7988_pcie_clk_req_n1), ++ PINCTRL_PIN_GROUP("pcie_wake_n2_0", mt7988_pcie_wake_n2_0), ++ PINCTRL_PIN_GROUP("pcie_clk_req_n2_0", mt7988_pcie_clk_req_n2_0), ++ PINCTRL_PIN_GROUP("drv_vbus", mt7988_drv_vbus), ++ PINCTRL_PIN_GROUP("pcie_wake_n2_1", mt7988_pcie_wake_n2_1), ++ PINCTRL_PIN_GROUP("uart1_2", mt7988_uart1_2), ++ PINCTRL_PIN_GROUP("pwm2", mt7988_pwm2), ++ PINCTRL_PIN_GROUP("pwm3", mt7988_pwm3), ++ PINCTRL_PIN_GROUP("pwm4", mt7988_pwm4), ++ PINCTRL_PIN_GROUP("pwm5", mt7988_pwm5), ++ PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0), ++ PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0), ++ PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0), ++ PINCTRL_PIN_GROUP("tops_uart1_2", mt7988_tops_uart1_2), ++ PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7988_net_wo0_uart_txd_1), ++ PINCTRL_PIN_GROUP("net_wo1_uart_txd_1", mt7988_net_wo1_uart_txd_1), ++ PINCTRL_PIN_GROUP("net_wo2_uart_txd_1", mt7988_net_wo2_uart_txd_1), ++}; ++ ++static const struct mtk_io_type_desc mt7988_io_type_desc[] = { ++ [IO_TYPE_GRP0] = { ++ .name = "18OD33", ++ .bias_set = mtk_pinconf_bias_set_pupd_r1_r0, ++ .drive_set = mtk_pinconf_drive_set_v1, ++ .input_enable = mtk_pinconf_input_enable_v1, ++ }, ++ [IO_TYPE_GRP1] = { ++ .name = "18A01", ++ .bias_set = mtk_pinconf_bias_set_pu_pd, ++ .drive_set = mtk_pinconf_drive_set_v1, ++ .input_enable = mtk_pinconf_input_enable_v1, ++ }, ++ [IO_TYPE_GRP2] = { ++ .name = "I2C", ++ .input_enable = mtk_pinconf_input_enable_v1, ++ }, ++}; ++ ++/* Joint those groups owning the same capability in user point of view which ++ * allows that people tend to use through the device tree. ++ */ ++static const char *const mt7988_jtag_groups[] = { "tops_jtag0_0", "wo0_jtag", ++ "wo1_jtag", "wo2_jtag", "jtag", "tops_jtag0_1", }; ++static const char *const mt7988_int_usxgmii_groups[] = { "int_usxgmii", }; ++static const char *const mt7988_pwm_groups[] = { "pwm0", "pwm1", "pwm2", "pwm3", ++ "pwm4", "pwm5", "pwm6", "pwm7" }; ++static const char *const mt7988_dfd_groups[] = { "dfd", }; ++static const char *const mt7988_i2c_groups[] = { "xfi_phy0_i2c0", ++ "xfi_phy1_i2c0", "xfi_phy_pll_i2c0", "xfi_phy_pll_i2c1", "i2c0_0", ++ "i2c1_sfp", "xfi_pextp_phy0_i2c", "xfi_pextp_phy1_i2c", "i2c0_1", ++ "u30_phy_i2c0", "u32_phy_i2c0", "xfi_phy0_i2c1", "xfi_phy1_i2c1", ++ "xfi_phy_pll_i2c2", "i2c1_0", "u30_phy_i2c1", "u32_phy_i2c1", ++ "xfi_phy_pll_i2c3", "sgmii0_i2c", "sgmii1_i2c", "i2c1_2", "i2c2_0", ++ "i2c2_1", }; ++static const char *const mt7988_ethernet_groups[] = { "mdc_mdio0", ++ "2p5g_ext_mdio", "gbe_ext_mdio", "mdc_mdio1", }; ++static const char *const mt7988_pcie_groups[] = { "pcie_wake_n0_0", ++ "pcie_clk_req_n0_0", "pcie_wake_n3_0", "pcie_clk_req_n3", ++ "pcie_p0_phy_i2c", "pcie_p1_phy_i2c", "pcie_p3_phy_i2", ++ "pcie_p2_phy_i2c", "ckm_phy_i2c", "pcie_wake_n0_1", "pcie_wake_n3_1", ++ "pcie_2l_0_pereset", "pcie_1l_1_pereset", "pcie_clk_req_n2_1", ++ "pcie_2l_1_perese", "pcie_1l_0_pereset", "pcie_wake_n1_0", ++ "cie_clk_req_n1", "pcie_wake_n2_0", "pcie_wake_n2_1", }; ++static const char *const mt7988_pmic_groups[] = { "pmic", }; ++static const char *const mt7988_wdt_groups[] = { "watchdog", }; ++static const char *const mt7988_spi_groups[] = { "spi0", "spi0_wp_hold", ++ "spi1", "spi2", "spi2_wp_hold", }; ++static const char *const mt7988_flash_groups[] = { "emmc_45", "snfi", ++ "emmc_51" }; ++static const char *const mt7988_uart_groups[] = { "uart2", "tops_uart0_0", ++ "uart2_0", "uart1_0", "uart2_1", ++ "net_wo0_uart_txd_0", "net_wo1_uart_txd_0", "net_wo2_uart_txd_0", ++ "tops_uart1_0", "ops_uart0_1", "ops_uart1_1", ++ "uart0", "tops_uart0_2", "uart1_1", ++ "uart2_3", "uart1_2", "tops_uart1_2", ++ "net_wo0_uart_txd_1", "net_wo1_uart_txd_1", "net_wo2_uart_txd_1", }; ++static const char *const mt7988_udi_groups[] = { "udi", }; ++static const char *const mt7988_pcm_groups[] = { "pcm", }; ++static const char *const mt7988_led_groups[] = { "gbe_led1", "2p5gbe_led1", ++ "gbe_led0", "2p5gbe_led0", "wf5g_led0", "wf5g_led1", }; ++static const char *const mt7988_usb_groups[] = { "drv_vbus", "drv_vbus_p1", }; ++ ++static const struct mtk_function_desc mt7988_functions[] = { ++ {"jtag", mt7988_jtag_groups, ARRAY_SIZE(mt7988_jtag_groups)}, ++ {"int_usxgmii", mt7988_int_usxgmii_groups, ++ ARRAY_SIZE(mt7988_int_usxgmii_groups)}, ++ {"pwm", mt7988_pwm_groups, ARRAY_SIZE(mt7988_pwm_groups)}, ++ {"dfd", mt7988_dfd_groups, ARRAY_SIZE(mt7988_dfd_groups)}, ++ {"i2c", mt7988_i2c_groups, ARRAY_SIZE(mt7988_i2c_groups)}, ++ {"eth", mt7988_ethernet_groups, ARRAY_SIZE(mt7988_ethernet_groups)}, ++ {"pcie", mt7988_pcie_groups, ARRAY_SIZE(mt7988_pcie_groups)}, ++ {"pmic", mt7988_pmic_groups, ARRAY_SIZE(mt7988_pmic_groups)}, ++ {"watchdog", mt7988_wdt_groups, ARRAY_SIZE(mt7988_wdt_groups)}, ++ {"spi", mt7988_spi_groups, ARRAY_SIZE(mt7988_spi_groups)}, ++ {"flash", mt7988_flash_groups, ARRAY_SIZE(mt7988_flash_groups)}, ++ {"uart", mt7988_uart_groups, ARRAY_SIZE(mt7988_uart_groups)}, ++ {"udi", mt7988_udi_groups, ARRAY_SIZE(mt7988_udi_groups)}, ++ {"pcm", mt7988_pcm_groups, ARRAY_SIZE(mt7988_pcm_groups)}, ++ {"usb", mt7988_usb_groups, ARRAY_SIZE(mt7988_usb_groups)}, ++ {"led", mt7988_led_groups, ARRAY_SIZE(mt7988_led_groups)}, ++}; ++ ++static const char *const mt7988_pinctrl_register_base_names[] = { ++ "gpio_base", "iocfg_tr_base", "iocfg_br_base", "iocfg_rb_base", ++ "iocfg_lb_base", "iocfg_tl_base", ++}; ++ ++static const struct mtk_pinctrl_soc mt7988_data = { ++ .name = "mt7988_pinctrl", ++ .reg_cal = mt7988_reg_cals, ++ .pins = mt7988_pins, ++ .npins = ARRAY_SIZE(mt7988_pins), ++ .grps = mt7988_groups, ++ .ngrps = ARRAY_SIZE(mt7988_groups), ++ .funcs = mt7988_functions, ++ .nfuncs = ARRAY_SIZE(mt7988_functions), ++ .io_type = mt7988_io_type_desc, ++ .ntype = ARRAY_SIZE(mt7988_io_type_desc), ++ .gpio_mode = 0, ++ .base_names = mt7988_pinctrl_register_base_names, ++ .nbase_names = ARRAY_SIZE(mt7988_pinctrl_register_base_names), ++ .base_calc = 1, ++}; ++ ++static int mtk_pinctrl_mt7988_probe(struct udevice *dev) ++{ ++ return mtk_pinctrl_common_probe(dev, &mt7988_data); ++} ++ ++static const struct udevice_id mt7988_pctrl_match[] = { ++ {.compatible = "mediatek,mt7988-pinctrl"}, ++ { /* sentinel */ } ++}; ++ ++U_BOOT_DRIVER(mt7988_pinctrl) = { ++ .name = "mt7988_pinctrl", ++ .id = UCLASS_PINCTRL, ++ .of_match = mt7988_pctrl_match, ++ .ops = &mtk_pinctrl_ops, ++ .probe = mtk_pinctrl_mt7988_probe, ++ .priv_auto = sizeof(struct mtk_pinctrl_priv), ++}; diff --git a/package/boot/uboot-mediatek/patches/101-16-net-mediatek-connect-switch-to-PSE-only-when-startin.patch b/package/boot/uboot-mediatek/patches/101-16-net-mediatek-connect-switch-to-PSE-only-when-startin.patch new file mode 100644 index 00000000000..e3e6212742b --- /dev/null +++ b/package/boot/uboot-mediatek/patches/101-16-net-mediatek-connect-switch-to-PSE-only-when-startin.patch @@ -0,0 +1,138 @@ +From a0405999ebecf21ed9f76f1dc9420682cd3feba0 Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 19 Jul 2023 17:16:54 +0800 +Subject: [PATCH 16/29] net: mediatek: connect switch to PSE only when starting + eth is requested + +So far the switch is initialized in probe stage and is connected to PSE +unconditionally. This will cause all packets being flooded to PSE and may +cause PSE hang before entering linux. + +This patch changes the connection between switch and PSE: +- Still initialize switch in probe stage, but disconnect it with PSE +- Connect switch with PSE on eth start +- Disconnect on eth stop + +Signed-off-by: Weijie Gao +--- + drivers/net/mtk_eth.c | 44 ++++++++++++++++++++++++++++++++++++++++--- + 1 file changed, 41 insertions(+), 3 deletions(-) + +--- a/drivers/net/mtk_eth.c ++++ b/drivers/net/mtk_eth.c +@@ -123,8 +123,10 @@ struct mtk_eth_priv { + + enum mtk_switch sw; + int (*switch_init)(struct mtk_eth_priv *priv); ++ void (*switch_mac_control)(struct mtk_eth_priv *priv, bool enable); + u32 mt753x_smi_addr; + u32 mt753x_phy_base; ++ u32 mt753x_pmcr; + + struct gpio_desc rst_gpio; + int mcm; +@@ -613,6 +615,16 @@ static int mt7530_pad_clk_setup(struct m + return 0; + } + ++static void mt7530_mac_control(struct mtk_eth_priv *priv, bool enable) ++{ ++ u32 pmcr = FORCE_MODE; ++ ++ if (enable) ++ pmcr = priv->mt753x_pmcr; ++ ++ mt753x_reg_write(priv, PMCR_REG(6), pmcr); ++} ++ + static int mt7530_setup(struct mtk_eth_priv *priv) + { + u16 phy_addr, phy_val; +@@ -663,11 +675,14 @@ static int mt7530_setup(struct mtk_eth_p + FORCE_DPX | FORCE_LINK; + + /* MT7530 Port6: Forced 1000M/FD, FC disabled */ +- mt753x_reg_write(priv, PMCR_REG(6), val); ++ priv->mt753x_pmcr = val; + + /* MT7530 Port5: Forced link down */ + mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE); + ++ /* Keep MAC link down before starting eth */ ++ mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE); ++ + /* MT7530 Port6: Set to RGMII */ + mt753x_reg_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_M, P6_INTF_MODE_RGMII); + +@@ -823,6 +838,17 @@ static void mt7531_phy_setting(struct mt + } + } + ++static void mt7531_mac_control(struct mtk_eth_priv *priv, bool enable) ++{ ++ u32 pmcr = FORCE_MODE_LNK; ++ ++ if (enable) ++ pmcr = priv->mt753x_pmcr; ++ ++ mt753x_reg_write(priv, PMCR_REG(5), pmcr); ++ mt753x_reg_write(priv, PMCR_REG(6), pmcr); ++} ++ + static int mt7531_setup(struct mtk_eth_priv *priv) + { + u16 phy_addr, phy_val; +@@ -882,8 +908,11 @@ static int mt7531_setup(struct mtk_eth_p + (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX | + FORCE_LINK; + +- mt753x_reg_write(priv, PMCR_REG(5), pmcr); +- mt753x_reg_write(priv, PMCR_REG(6), pmcr); ++ priv->mt753x_pmcr = pmcr; ++ ++ /* Keep MAC link down before starting eth */ ++ mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE_LNK); ++ mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK); + + /* Turn on PHYs */ + for (i = 0; i < MT753X_NUM_PHYS; i++) { +@@ -1227,6 +1256,9 @@ static int mtk_eth_start(struct udevice + + mtk_eth_fifo_init(priv); + ++ if (priv->switch_mac_control) ++ priv->switch_mac_control(priv, true); ++ + /* Start PHY */ + if (priv->sw == SW_NONE) { + ret = mtk_phy_start(priv); +@@ -1245,6 +1277,9 @@ static void mtk_eth_stop(struct udevice + { + struct mtk_eth_priv *priv = dev_get_priv(dev); + ++ if (priv->switch_mac_control) ++ priv->switch_mac_control(priv, false); ++ + mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, + TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN, 0); + udelay(500); +@@ -1484,16 +1519,19 @@ static int mtk_eth_of_to_plat(struct ude + /* check for switch first, otherwise phy will be used */ + priv->sw = SW_NONE; + priv->switch_init = NULL; ++ priv->switch_mac_control = NULL; + str = dev_read_string(dev, "mediatek,switch"); + + if (str) { + if (!strcmp(str, "mt7530")) { + priv->sw = SW_MT7530; + priv->switch_init = mt7530_setup; ++ priv->switch_mac_control = mt7530_mac_control; + priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR; + } else if (!strcmp(str, "mt7531")) { + priv->sw = SW_MT7531; + priv->switch_init = mt7531_setup; ++ priv->switch_mac_control = mt7531_mac_control; + priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR; + } else { + printf("error: unsupported switch\n"); diff --git a/package/boot/uboot-mediatek/patches/101-17-net-mediatek-optimize-the-switch-reset-delay-wait-ti.patch b/package/boot/uboot-mediatek/patches/101-17-net-mediatek-optimize-the-switch-reset-delay-wait-ti.patch new file mode 100644 index 00000000000..c8823ac545c --- /dev/null +++ b/package/boot/uboot-mediatek/patches/101-17-net-mediatek-optimize-the-switch-reset-delay-wait-ti.patch @@ -0,0 +1,56 @@ +From d9a52701f6677889cc3332ab7a888f35cd69cc76 Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 19 Jul 2023 17:16:59 +0800 +Subject: [PATCH 17/29] net: mediatek: optimize the switch reset delay wait + time + +Not all switches requires 1 second delay after deasserting reset. +MT7531 requires only maximum 200ms. + +This patch defines dedicated reset wait time for each switch chip, and will +significantly improve the boot time for boards using MT7531. + +Signed-off-by: Weijie Gao +--- + drivers/net/mtk_eth.c | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +--- a/drivers/net/mtk_eth.c ++++ b/drivers/net/mtk_eth.c +@@ -127,6 +127,7 @@ struct mtk_eth_priv { + u32 mt753x_smi_addr; + u32 mt753x_phy_base; + u32 mt753x_pmcr; ++ u32 mt753x_reset_wait_time; + + struct gpio_desc rst_gpio; + int mcm; +@@ -943,12 +944,12 @@ int mt753x_switch_init(struct mtk_eth_pr + reset_assert(&priv->rst_mcm); + udelay(1000); + reset_deassert(&priv->rst_mcm); +- mdelay(1000); ++ mdelay(priv->mt753x_reset_wait_time); + } else if (dm_gpio_is_valid(&priv->rst_gpio)) { + dm_gpio_set_value(&priv->rst_gpio, 0); + udelay(1000); + dm_gpio_set_value(&priv->rst_gpio, 1); +- mdelay(1000); ++ mdelay(priv->mt753x_reset_wait_time); + } + + ret = priv->switch_init(priv); +@@ -1528,11 +1529,13 @@ static int mtk_eth_of_to_plat(struct ude + priv->switch_init = mt7530_setup; + priv->switch_mac_control = mt7530_mac_control; + priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR; ++ priv->mt753x_reset_wait_time = 1000; + } else if (!strcmp(str, "mt7531")) { + priv->sw = SW_MT7531; + priv->switch_init = mt7531_setup; + priv->switch_mac_control = mt7531_mac_control; + priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR; ++ priv->mt753x_reset_wait_time = 200; + } else { + printf("error: unsupported switch\n"); + return -EINVAL; diff --git a/package/boot/uboot-mediatek/patches/101-18-net-mediatek-fix-direct-MDIO-clause-45-access-via-So.patch b/package/boot/uboot-mediatek/patches/101-18-net-mediatek-fix-direct-MDIO-clause-45-access-via-So.patch new file mode 100644 index 00000000000..5214e842c82 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/101-18-net-mediatek-fix-direct-MDIO-clause-45-access-via-So.patch @@ -0,0 +1,34 @@ +From c44f6ac1a31961b0d4faf982ee42167de5ac1672 Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 19 Jul 2023 17:17:03 +0800 +Subject: [PATCH 18/29] net: mediatek: fix direct MDIO clause 45 access via SoC + +The original direct MDIO clause 45 access via SoC is missing the +data output. This patch adds it back to ensure MDIO clause 45 can +work properly for external PHYs. + +Signed-off-by: Weijie Gao +--- + drivers/net/mtk_eth.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/net/mtk_eth.c ++++ b/drivers/net/mtk_eth.c +@@ -198,7 +198,7 @@ static int mtk_mii_rw(struct mtk_eth_pri + (((u32)phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) | + (((u32)reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M); + +- if (cmd == MDIO_CMD_WRITE) ++ if (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR) + val |= data & MDIO_RW_DATA_M; + + mtk_gmac_write(priv, GMAC_PIAC_REG, val | PHY_ACS_ST); +@@ -210,7 +210,7 @@ static int mtk_mii_rw(struct mtk_eth_pri + return ret; + } + +- if (cmd == MDIO_CMD_READ) { ++ if (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) { + val = mtk_gmac_read(priv, GMAC_PIAC_REG); + return val & MDIO_RW_DATA_M; + } diff --git a/package/boot/uboot-mediatek/patches/101-19-net-mediatek-add-missing-static-qualifier.patch b/package/boot/uboot-mediatek/patches/101-19-net-mediatek-add-missing-static-qualifier.patch new file mode 100644 index 00000000000..9350ca04dc2 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/101-19-net-mediatek-add-missing-static-qualifier.patch @@ -0,0 +1,36 @@ +From 9d35558bedfb82860c63cc11d3426afcbd82cb5c Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 19 Jul 2023 17:17:07 +0800 +Subject: [PATCH 19/29] net: mediatek: add missing static qualifier + +mt7531_mmd_ind_read and mt753x_switch_init are defined without static. +Since they're not used outside this file, we should add them back. + +Signed-off-by: Weijie Gao + +fixup to add static qualifier +--- + drivers/net/mtk_eth.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/drivers/net/mtk_eth.c ++++ b/drivers/net/mtk_eth.c +@@ -436,7 +436,8 @@ static int mt7531_mii_ind_write(struct m + MDIO_ST_C22); + } + +-int mt7531_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg) ++static int mt7531_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, ++ u16 reg) + { + u8 phy_addr; + int ret; +@@ -934,7 +935,7 @@ static int mt7531_setup(struct mtk_eth_p + return 0; + } + +-int mt753x_switch_init(struct mtk_eth_priv *priv) ++static int mt753x_switch_init(struct mtk_eth_priv *priv) + { + int ret; + int i; diff --git a/package/boot/uboot-mediatek/patches/101-20-net-mediatek-add-support-for-SGMII-1Gbps-auto-negoti.patch b/package/boot/uboot-mediatek/patches/101-20-net-mediatek-add-support-for-SGMII-1Gbps-auto-negoti.patch new file mode 100644 index 00000000000..45acbc36ac1 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/101-20-net-mediatek-add-support-for-SGMII-1Gbps-auto-negoti.patch @@ -0,0 +1,149 @@ +From 8e59c3cc700a6efb8db574f3c8e18b6181b4a07d Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 19 Jul 2023 17:17:13 +0800 +Subject: [PATCH 20/29] net: mediatek: add support for SGMII 1Gbps + auto-negotiation mode + +Existing SGMII support of mtk-eth is actually a MediaTek-specific +2.5Gbps high-speed SGMII (HSGMII) which does not support +auto-negotiation mode. + +This patch adds SGMII 1Gbps auto-negotiation mode and rename the +existing HSGMII to 2500basex. + +Signed-off-by: Weijie Gao +--- + drivers/net/mtk_eth.c | 46 +++++++++++++++++++++++++++++++++++++------ + drivers/net/mtk_eth.h | 2 ++ + 2 files changed, 42 insertions(+), 6 deletions(-) + +--- a/drivers/net/mtk_eth.c ++++ b/drivers/net/mtk_eth.c +@@ -893,7 +893,7 @@ static int mt7531_setup(struct mtk_eth_p + if (!port5_sgmii) + mt7531_port_rgmii_init(priv, 5); + break; +- case PHY_INTERFACE_MODE_SGMII: ++ case PHY_INTERFACE_MODE_2500BASEX: + mt7531_port_sgmii_init(priv, 6); + if (port5_sgmii) + mt7531_port_sgmii_init(priv, 5); +@@ -986,6 +986,7 @@ static void mtk_phy_link_adjust(struct m + (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) | + MAC_MODE | FORCE_MODE | + MAC_TX_EN | MAC_RX_EN | ++ DEL_RXFIFO_CLR | + BKOFF_EN | BACKPR_EN; + + switch (priv->phydev->speed) { +@@ -996,6 +997,7 @@ static void mtk_phy_link_adjust(struct m + mcr |= (SPEED_100M << FORCE_SPD_S); + break; + case SPEED_1000: ++ case SPEED_2500: + mcr |= (SPEED_1000M << FORCE_SPD_S); + break; + }; +@@ -1048,7 +1050,8 @@ static int mtk_phy_start(struct mtk_eth_ + return 0; + } + +- mtk_phy_link_adjust(priv); ++ if (!priv->force_mode) ++ mtk_phy_link_adjust(priv); + + debug("Speed: %d, %s duplex%s\n", phydev->speed, + (phydev->duplex) ? "full" : "half", +@@ -1076,7 +1079,31 @@ static int mtk_phy_probe(struct udevice + return 0; + } + +-static void mtk_sgmii_init(struct mtk_eth_priv *priv) ++static void mtk_sgmii_an_init(struct mtk_eth_priv *priv) ++{ ++ /* Set SGMII GEN1 speed(1G) */ ++ clrsetbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, ++ SGMSYS_SPEED_2500, 0); ++ ++ /* Enable SGMII AN */ ++ setbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1, ++ SGMII_AN_ENABLE); ++ ++ /* SGMII AN mode setting */ ++ writel(SGMII_AN_MODE, priv->sgmii_base + SGMSYS_SGMII_MODE); ++ ++ /* SGMII PN SWAP setting */ ++ if (priv->pn_swap) { ++ setbits_le32(priv->sgmii_base + SGMSYS_QPHY_WRAP_CTRL, ++ SGMII_PN_SWAP_TX_RX); ++ } ++ ++ /* Release PHYA power down state */ ++ clrsetbits_le32(priv->sgmii_base + SGMSYS_QPHY_PWR_STATE_CTRL, ++ SGMII_PHYA_PWD, 0); ++} ++ ++static void mtk_sgmii_force_init(struct mtk_eth_priv *priv) + { + /* Set SGMII GEN2 speed(2.5G) */ + setbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, +@@ -1111,10 +1138,14 @@ static void mtk_mac_init(struct mtk_eth_ + ge_mode = GE_MODE_RGMII; + break; + case PHY_INTERFACE_MODE_SGMII: ++ case PHY_INTERFACE_MODE_2500BASEX: + ge_mode = GE_MODE_RGMII; + mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, SYSCFG0_SGMII_SEL_M, + SYSCFG0_SGMII_SEL(priv->gmac_id)); +- mtk_sgmii_init(priv); ++ if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) ++ mtk_sgmii_an_init(priv); ++ else ++ mtk_sgmii_force_init(priv); + break; + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_GMII: +@@ -1148,6 +1179,7 @@ static void mtk_mac_init(struct mtk_eth_ + mcr |= SPEED_100M << FORCE_SPD_S; + break; + case SPEED_1000: ++ case SPEED_2500: + mcr |= SPEED_1000M << FORCE_SPD_S; + break; + } +@@ -1490,13 +1522,15 @@ static int mtk_eth_of_to_plat(struct ude + priv->duplex = ofnode_read_bool(subnode, "full-duplex"); + + if (priv->speed != SPEED_10 && priv->speed != SPEED_100 && +- priv->speed != SPEED_1000) { ++ priv->speed != SPEED_1000 && priv->speed != SPEED_2500 && ++ priv->speed != SPEED_10000) { + printf("error: no valid speed set in fixed-link\n"); + return -EINVAL; + } + } + +- if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) { ++ if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII || ++ priv->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { + /* get corresponding sgmii phandle */ + ret = dev_read_phandle_with_args(dev, "mediatek,sgmiisys", + NULL, 0, 0, &args); +--- a/drivers/net/mtk_eth.h ++++ b/drivers/net/mtk_eth.h +@@ -69,6 +69,7 @@ enum mkt_eth_capabilities { + #define SGMII_AN_RESTART BIT(9) + + #define SGMSYS_SGMII_MODE 0x20 ++#define SGMII_AN_MODE 0x31120103 + #define SGMII_FORCE_MODE 0x31120019 + + #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 +@@ -168,6 +169,7 @@ enum mkt_eth_capabilities { + #define FORCE_MODE BIT(15) + #define MAC_TX_EN BIT(14) + #define MAC_RX_EN BIT(13) ++#define DEL_RXFIFO_CLR BIT(12) + #define BKOFF_EN BIT(9) + #define BACKPR_EN BIT(8) + #define FORCE_RX_FC BIT(5) diff --git a/package/boot/uboot-mediatek/patches/101-21-arm-dts-medaitek-convert-gmac-link-mode-to-2500base-.patch b/package/boot/uboot-mediatek/patches/101-21-arm-dts-medaitek-convert-gmac-link-mode-to-2500base-.patch new file mode 100644 index 00000000000..27612fd9e4e --- /dev/null +++ b/package/boot/uboot-mediatek/patches/101-21-arm-dts-medaitek-convert-gmac-link-mode-to-2500base-.patch @@ -0,0 +1,214 @@ +From 64ef7e977767e3b1305fb94a5169d8b7d3b19b6c Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 19 Jul 2023 17:17:18 +0800 +Subject: [PATCH 21/29] arm: dts: mediatek: convert gmac link mode to + 2500base-x + +Now that individual 2.5Gbps SGMII support has been added to +mtk-eth, all boards that use 2.5Gbps link with mt7531 must be +converted to use "2500base-x" instead of "sgmii". + +Signed-off-by: Weijie Gao +[also convert BPi-R3] +Signed-off-by: Daniel Golle +--- + arch/arm/dts/mt7622-bananapi-bpi-r64.dts | 4 ++-- + arch/arm/dts/mt7622-rfb.dts | 4 ++-- + arch/arm/dts/mt7629-rfb.dts | 4 ++-- + arch/arm/dts/mt7981-emmc-rfb.dts | 4 ++-- + arch/arm/dts/mt7981-rfb.dts | 4 ++-- + arch/arm/dts/mt7981-sd-rfb.dts | 4 ++-- + arch/arm/dts/mt7986a-bpi-r3-sd.dts | 4 ++-- + arch/arm/dts/mt7986a-rfb.dts | 4 ++-- + arch/arm/dts/mt7986a-sd-rfb.dts | 4 ++-- + arch/arm/dts/mt7986b-rfb.dts | 4 ++-- + arch/arm/dts/mt7986b-sd-rfb.dts | 4 ++-- + 11 files changed, 22 insertions(+), 22 deletions(-) + +--- a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts ++++ b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts +@@ -224,12 +224,12 @@ + ð { + status = "okay"; + mediatek,gmac-id = <0>; +- phy-mode = "sgmii"; ++ phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; + reset-gpios = <&gpio 54 GPIO_ACTIVE_HIGH>; + + fixed-link { +- speed = <1000>; ++ speed = <2500>; + full-duplex; + }; + }; +--- a/arch/arm/dts/mt7622-rfb.dts ++++ b/arch/arm/dts/mt7622-rfb.dts +@@ -240,12 +240,12 @@ + ð { + status = "okay"; + mediatek,gmac-id = <0>; +- phy-mode = "sgmii"; ++ phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; + reset-gpios = <&gpio 54 GPIO_ACTIVE_HIGH>; + + fixed-link { +- speed = <1000>; ++ speed = <2500>; + full-duplex; + }; + }; +--- a/arch/arm/dts/mt7629-rfb.dts ++++ b/arch/arm/dts/mt7629-rfb.dts +@@ -25,12 +25,12 @@ + ð { + status = "okay"; + mediatek,gmac-id = <0>; +- phy-mode = "sgmii"; ++ phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; + reset-gpios = <&gpio 28 GPIO_ACTIVE_HIGH>; + + fixed-link { +- speed = <1000>; ++ speed = <2500>; + full-duplex; + }; + }; +--- a/arch/arm/dts/mt7981-emmc-rfb.dts ++++ b/arch/arm/dts/mt7981-emmc-rfb.dts +@@ -46,12 +46,12 @@ + ð { + status = "okay"; + mediatek,gmac-id = <0>; +- phy-mode = "sgmii"; ++ phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; + reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; + + fixed-link { +- speed = <1000>; ++ speed = <2500>; + full-duplex; + }; + }; +--- a/arch/arm/dts/mt7981-rfb.dts ++++ b/arch/arm/dts/mt7981-rfb.dts +@@ -37,12 +37,12 @@ + ð { + status = "okay"; + mediatek,gmac-id = <0>; +- phy-mode = "sgmii"; ++ phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; + reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; + + fixed-link { +- speed = <1000>; ++ speed = <2500>; + full-duplex; + }; + }; +--- a/arch/arm/dts/mt7981-sd-rfb.dts ++++ b/arch/arm/dts/mt7981-sd-rfb.dts +@@ -46,12 +46,12 @@ + ð { + status = "okay"; + mediatek,gmac-id = <0>; +- phy-mode = "sgmii"; ++ phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; + reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; + + fixed-link { +- speed = <1000>; ++ speed = <2500>; + full-duplex; + }; + }; +--- a/arch/arm/dts/mt7986a-bpi-r3-sd.dts ++++ b/arch/arm/dts/mt7986a-bpi-r3-sd.dts +@@ -76,12 +76,12 @@ + ð { + status = "okay"; + mediatek,gmac-id = <0>; +- phy-mode = "sgmii"; ++ phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; + reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; + + fixed-link { +- speed = <1000>; ++ speed = <2500>; + full-duplex; + }; + }; +--- a/arch/arm/dts/mt7986a-rfb.dts ++++ b/arch/arm/dts/mt7986a-rfb.dts +@@ -55,12 +55,12 @@ + ð { + status = "okay"; + mediatek,gmac-id = <0>; +- phy-mode = "sgmii"; ++ phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; + reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; + + fixed-link { +- speed = <1000>; ++ speed = <2500>; + full-duplex; + }; + }; +--- a/arch/arm/dts/mt7986a-sd-rfb.dts ++++ b/arch/arm/dts/mt7986a-sd-rfb.dts +@@ -47,12 +47,12 @@ + ð { + status = "okay"; + mediatek,gmac-id = <0>; +- phy-mode = "sgmii"; ++ phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; + reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; + + fixed-link { +- speed = <1000>; ++ speed = <2500>; + full-duplex; + }; + }; +--- a/arch/arm/dts/mt7986b-rfb.dts ++++ b/arch/arm/dts/mt7986b-rfb.dts +@@ -46,12 +46,12 @@ + ð { + status = "okay"; + mediatek,gmac-id = <0>; +- phy-mode = "sgmii"; ++ phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; + reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; + + fixed-link { +- speed = <1000>; ++ speed = <2500>; + full-duplex; + }; + }; +--- a/arch/arm/dts/mt7986b-sd-rfb.dts ++++ b/arch/arm/dts/mt7986b-sd-rfb.dts +@@ -47,12 +47,12 @@ + ð { + status = "okay"; + mediatek,gmac-id = <0>; +- phy-mode = "sgmii"; ++ phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; + reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; + + fixed-link { +- speed = <1000>; ++ speed = <2500>; + full-duplex; + }; + }; diff --git a/package/boot/uboot-mediatek/patches/101-22-net-mediatek-add-support-for-GMAC-USB3-PHY-mux-mode-.patch b/package/boot/uboot-mediatek/patches/101-22-net-mediatek-add-support-for-GMAC-USB3-PHY-mux-mode-.patch new file mode 100644 index 00000000000..c7e49ff304d --- /dev/null +++ b/package/boot/uboot-mediatek/patches/101-22-net-mediatek-add-support-for-GMAC-USB3-PHY-mux-mode-.patch @@ -0,0 +1,138 @@ +From 542d455466bdf32e1bb70230ebcdefd8ed09643b Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 19 Jul 2023 17:17:22 +0800 +Subject: [PATCH 22/29] net: mediatek: add support for GMAC/USB3 PHY mux mode + for MT7981 + +MT7981 has its GMAC2 PHY shared with USB3. To enable GMAC2, mux +register must be set to connect the SGMII phy to GMAC2. + +Signed-off-by: Weijie Gao +--- + drivers/net/mtk_eth.c | 33 ++++++++++++++++++++++++++++++++- + drivers/net/mtk_eth.h | 16 ++++++++++++++++ + 2 files changed, 48 insertions(+), 1 deletion(-) + +--- a/drivers/net/mtk_eth.c ++++ b/drivers/net/mtk_eth.c +@@ -103,6 +103,8 @@ struct mtk_eth_priv { + + struct regmap *ethsys_regmap; + ++ struct regmap *infra_regmap; ++ + struct mii_dev *mdio_bus; + int (*mii_read)(struct mtk_eth_priv *priv, u8 phy, u8 reg); + int (*mii_write)(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 val); +@@ -186,6 +188,17 @@ static void mtk_ethsys_rmw(struct mtk_et + regmap_write(priv->ethsys_regmap, reg, val); + } + ++static void mtk_infra_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, ++ u32 set) ++{ ++ uint val; ++ ++ regmap_read(priv->infra_regmap, reg, &val); ++ val &= ~clr; ++ val |= set; ++ regmap_write(priv->infra_regmap, reg, val); ++} ++ + /* Direct MDIO clause 22/45 access via SoC */ + static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data, + u32 cmd, u32 st) +@@ -1139,6 +1152,11 @@ static void mtk_mac_init(struct mtk_eth_ + break; + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_2500BASEX: ++ if (MTK_HAS_CAPS(priv->soc->caps, MTK_GMAC2_U3_QPHY)) { ++ mtk_infra_rmw(priv, USB_PHY_SWITCH_REG, QPHY_SEL_MASK, ++ SGMII_QPHY_SEL); ++ } ++ + ge_mode = GE_MODE_RGMII; + mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, SYSCFG0_SGMII_SEL_M, + SYSCFG0_SGMII_SEL(priv->gmac_id)); +@@ -1497,6 +1515,19 @@ static int mtk_eth_of_to_plat(struct ude + if (IS_ERR(priv->ethsys_regmap)) + return PTR_ERR(priv->ethsys_regmap); + ++ if (MTK_HAS_CAPS(priv->soc->caps, MTK_INFRA)) { ++ /* get corresponding infracfg phandle */ ++ ret = dev_read_phandle_with_args(dev, "mediatek,infracfg", ++ NULL, 0, 0, &args); ++ ++ if (ret) ++ return ret; ++ ++ priv->infra_regmap = syscon_node_to_regmap(args.node); ++ if (IS_ERR(priv->infra_regmap)) ++ return PTR_ERR(priv->infra_regmap); ++ } ++ + /* Reset controllers */ + ret = reset_get_by_name(dev, "fe", &priv->rst_fe); + if (ret) { +@@ -1614,7 +1645,7 @@ static const struct mtk_soc_data mt7986_ + }; + + static const struct mtk_soc_data mt7981_data = { +- .caps = MT7986_CAPS, ++ .caps = MT7981_CAPS, + .ana_rgc3 = 0x128, + .pdma_base = PDMA_V2_BASE, + .txd_size = sizeof(struct mtk_tx_dma_v2), +--- a/drivers/net/mtk_eth.h ++++ b/drivers/net/mtk_eth.h +@@ -15,27 +15,38 @@ + enum mkt_eth_capabilities { + MTK_TRGMII_BIT, + MTK_TRGMII_MT7621_CLK_BIT, ++ MTK_U3_COPHY_V2_BIT, ++ MTK_INFRA_BIT, + MTK_NETSYS_V2_BIT, + + /* PATH BITS */ + MTK_ETH_PATH_GMAC1_TRGMII_BIT, ++ MTK_ETH_PATH_GMAC2_SGMII_BIT, + }; + + #define MTK_TRGMII BIT(MTK_TRGMII_BIT) + #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) ++#define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT) ++#define MTK_INFRA BIT(MTK_INFRA_BIT) + #define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) + + /* Supported path present on SoCs */ + #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) + ++#define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) ++ + #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) + ++#define MTK_GMAC2_U3_QPHY (MTK_ETH_PATH_GMAC2_SGMII | MTK_U3_COPHY_V2 | MTK_INFRA) ++ + #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) + + #define MT7621_CAPS (MTK_GMAC1_TRGMII | MTK_TRGMII_MT7621_CLK) + + #define MT7623_CAPS (MTK_GMAC1_TRGMII) + ++#define MT7981_CAPS (MTK_GMAC2_U3_QPHY | MTK_NETSYS_V2) ++ + #define MT7986_CAPS (MTK_NETSYS_V2) + + /* Frame Engine Register Bases */ +@@ -56,6 +67,11 @@ enum mkt_eth_capabilities { + #define ETHSYS_CLKCFG0_REG 0x2c + #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) + ++/* Top misc registers */ ++#define USB_PHY_SWITCH_REG 0x218 ++#define QPHY_SEL_MASK 0x3 ++#define SGMII_QPHY_SEL 0x2 ++ + /* SYSCFG0_GE_MODE: GE Modes */ + #define GE_MODE_RGMII 0 + #define GE_MODE_MII 1 diff --git a/package/boot/uboot-mediatek/patches/101-23-arm-dts-mediatek-add-infracfg-registers-to-support-G.patch b/package/boot/uboot-mediatek/patches/101-23-arm-dts-mediatek-add-infracfg-registers-to-support-G.patch new file mode 100644 index 00000000000..63c25304a06 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/101-23-arm-dts-mediatek-add-infracfg-registers-to-support-G.patch @@ -0,0 +1,36 @@ +From 64dab5fc8405005a78bdf1e0035d8b754cdf0c7e Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 19 Jul 2023 17:17:27 +0800 +Subject: [PATCH 23/29] arm: dts: mediatek: add infracfg registers to support + GMAC/USB3 Co-PHY + +This patch adds infracfg to eth node to support enabling GMAC2. + +Signed-off-by: Weijie Gao +--- + arch/arm/dts/mt7981.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/arch/arm/dts/mt7981.dtsi ++++ b/arch/arm/dts/mt7981.dtsi +@@ -266,6 +266,7 @@ + reset-names = "fe"; + mediatek,ethsys = <ðsys>; + mediatek,sgmiisys = <&sgmiisys0>; ++ mediatek,infracfg = <&topmisc>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -284,6 +285,12 @@ + #clock-cells = <1>; + }; + ++ topmisc: topmisc@11d10000 { ++ compatible = "mediatek,mt7981-topmisc", "syscon"; ++ reg = <0x11d10000 0x10000>; ++ #clock-cells = <1>; ++ }; ++ + spi0: spi@1100a000 { + compatible = "mediatek,ipm-spi"; + reg = <0x1100a000 0x100>; diff --git a/package/boot/uboot-mediatek/patches/101-24-net-mediatek-add-USXGMII-support.patch b/package/boot/uboot-mediatek/patches/101-24-net-mediatek-add-USXGMII-support.patch new file mode 100644 index 00000000000..67288c749e4 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/101-24-net-mediatek-add-USXGMII-support.patch @@ -0,0 +1,341 @@ +From d62b483092035bc86d1db83ea4ac29bfa7bba77d Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 19 Jul 2023 17:17:31 +0800 +Subject: [PATCH 24/29] net: mediatek: add USXGMII support + +This patch adds support for USXGMII of SoC. + +Signed-off-by: Weijie Gao +--- + drivers/net/mtk_eth.c | 230 +++++++++++++++++++++++++++++++++++++++++- + drivers/net/mtk_eth.h | 24 +++++ + 2 files changed, 251 insertions(+), 3 deletions(-) + +--- a/drivers/net/mtk_eth.c ++++ b/drivers/net/mtk_eth.c +@@ -105,6 +105,11 @@ struct mtk_eth_priv { + + struct regmap *infra_regmap; + ++ struct regmap *usxgmii_regmap; ++ struct regmap *xfi_pextp_regmap; ++ struct regmap *xfi_pll_regmap; ++ struct regmap *toprgu_regmap; ++ + struct mii_dev *mdio_bus; + int (*mii_read)(struct mtk_eth_priv *priv, u8 phy, u8 reg); + int (*mii_write)(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 val); +@@ -989,6 +994,42 @@ static int mt753x_switch_init(struct mtk + return 0; + } + ++static void mtk_xphy_link_adjust(struct mtk_eth_priv *priv) ++{ ++ u16 lcl_adv = 0, rmt_adv = 0; ++ u8 flowctrl; ++ u32 mcr; ++ ++ mcr = mtk_gmac_read(priv, XGMAC_PORT_MCR(priv->gmac_id)); ++ mcr &= ~(XGMAC_FORCE_TX_FC | XGMAC_FORCE_RX_FC); ++ ++ if (priv->phydev->duplex) { ++ if (priv->phydev->pause) ++ rmt_adv = LPA_PAUSE_CAP; ++ if (priv->phydev->asym_pause) ++ rmt_adv |= LPA_PAUSE_ASYM; ++ ++ if (priv->phydev->advertising & ADVERTISED_Pause) ++ lcl_adv |= ADVERTISE_PAUSE_CAP; ++ if (priv->phydev->advertising & ADVERTISED_Asym_Pause) ++ lcl_adv |= ADVERTISE_PAUSE_ASYM; ++ ++ flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); ++ ++ if (flowctrl & FLOW_CTRL_TX) ++ mcr |= XGMAC_FORCE_TX_FC; ++ if (flowctrl & FLOW_CTRL_RX) ++ mcr |= XGMAC_FORCE_RX_FC; ++ ++ debug("rx pause %s, tx pause %s\n", ++ flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled", ++ flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled"); ++ } ++ ++ mcr &= ~(XGMAC_TRX_DISABLE); ++ mtk_gmac_write(priv, XGMAC_PORT_MCR(priv->gmac_id), mcr); ++} ++ + static void mtk_phy_link_adjust(struct mtk_eth_priv *priv) + { + u16 lcl_adv = 0, rmt_adv = 0; +@@ -1063,8 +1104,12 @@ static int mtk_phy_start(struct mtk_eth_ + return 0; + } + +- if (!priv->force_mode) +- mtk_phy_link_adjust(priv); ++ if (!priv->force_mode) { ++ if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII) ++ mtk_xphy_link_adjust(priv); ++ else ++ mtk_phy_link_adjust(priv); ++ } + + debug("Speed: %d, %s duplex%s\n", phydev->speed, + (phydev->duplex) ? "full" : "half", +@@ -1140,6 +1185,112 @@ static void mtk_sgmii_force_init(struct + SGMII_PHYA_PWD, 0); + } + ++static void mtk_xfi_pll_enable(struct mtk_eth_priv *priv) ++{ ++ u32 val = 0; ++ ++ /* Add software workaround for USXGMII PLL TCL issue */ ++ regmap_write(priv->xfi_pll_regmap, XFI_PLL_ANA_GLB8, ++ RG_XFI_PLL_ANA_SWWA); ++ ++ regmap_read(priv->xfi_pll_regmap, XFI_PLL_DIG_GLB8, &val); ++ val |= RG_XFI_PLL_EN; ++ regmap_write(priv->xfi_pll_regmap, XFI_PLL_DIG_GLB8, val); ++} ++ ++static void mtk_usxgmii_reset(struct mtk_eth_priv *priv) ++{ ++ switch (priv->gmac_id) { ++ case 1: ++ regmap_write(priv->toprgu_regmap, 0xFC, 0x0000A004); ++ regmap_write(priv->toprgu_regmap, 0x18, 0x88F0A004); ++ regmap_write(priv->toprgu_regmap, 0xFC, 0x00000000); ++ regmap_write(priv->toprgu_regmap, 0x18, 0x88F00000); ++ regmap_write(priv->toprgu_regmap, 0x18, 0x00F00000); ++ break; ++ case 2: ++ regmap_write(priv->toprgu_regmap, 0xFC, 0x00005002); ++ regmap_write(priv->toprgu_regmap, 0x18, 0x88F05002); ++ regmap_write(priv->toprgu_regmap, 0xFC, 0x00000000); ++ regmap_write(priv->toprgu_regmap, 0x18, 0x88F00000); ++ regmap_write(priv->toprgu_regmap, 0x18, 0x00F00000); ++ break; ++ } ++ ++ mdelay(10); ++} ++ ++static void mtk_usxgmii_setup_phya_an_10000(struct mtk_eth_priv *priv) ++{ ++ regmap_write(priv->usxgmii_regmap, 0x810, 0x000FFE6D); ++ regmap_write(priv->usxgmii_regmap, 0x818, 0x07B1EC7B); ++ regmap_write(priv->usxgmii_regmap, 0x80C, 0x30000000); ++ ndelay(1020); ++ regmap_write(priv->usxgmii_regmap, 0x80C, 0x10000000); ++ ndelay(1020); ++ regmap_write(priv->usxgmii_regmap, 0x80C, 0x00000000); ++ ++ regmap_write(priv->xfi_pextp_regmap, 0x9024, 0x00C9071C); ++ regmap_write(priv->xfi_pextp_regmap, 0x2020, 0xAA8585AA); ++ regmap_write(priv->xfi_pextp_regmap, 0x2030, 0x0C020707); ++ regmap_write(priv->xfi_pextp_regmap, 0x2034, 0x0E050F0F); ++ regmap_write(priv->xfi_pextp_regmap, 0x2040, 0x00140032); ++ regmap_write(priv->xfi_pextp_regmap, 0x50F0, 0x00C014AA); ++ regmap_write(priv->xfi_pextp_regmap, 0x50E0, 0x3777C12B); ++ regmap_write(priv->xfi_pextp_regmap, 0x506C, 0x005F9CFF); ++ regmap_write(priv->xfi_pextp_regmap, 0x5070, 0x9D9DFAFA); ++ regmap_write(priv->xfi_pextp_regmap, 0x5074, 0x27273F3F); ++ regmap_write(priv->xfi_pextp_regmap, 0x5078, 0xA7883C68); ++ regmap_write(priv->xfi_pextp_regmap, 0x507C, 0x11661166); ++ regmap_write(priv->xfi_pextp_regmap, 0x5080, 0x0E000AAF); ++ regmap_write(priv->xfi_pextp_regmap, 0x5084, 0x08080D0D); ++ regmap_write(priv->xfi_pextp_regmap, 0x5088, 0x02030909); ++ regmap_write(priv->xfi_pextp_regmap, 0x50E4, 0x0C0C0000); ++ regmap_write(priv->xfi_pextp_regmap, 0x50E8, 0x04040000); ++ regmap_write(priv->xfi_pextp_regmap, 0x50EC, 0x0F0F0C06); ++ regmap_write(priv->xfi_pextp_regmap, 0x50A8, 0x506E8C8C); ++ regmap_write(priv->xfi_pextp_regmap, 0x6004, 0x18190000); ++ regmap_write(priv->xfi_pextp_regmap, 0x00F8, 0x01423342); ++ regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F20); ++ regmap_write(priv->xfi_pextp_regmap, 0x0030, 0x00050C00); ++ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x02002800); ++ ndelay(1020); ++ regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000020); ++ regmap_write(priv->xfi_pextp_regmap, 0x3028, 0x00008A01); ++ regmap_write(priv->xfi_pextp_regmap, 0x302C, 0x0000A884); ++ regmap_write(priv->xfi_pextp_regmap, 0x3024, 0x00083002); ++ regmap_write(priv->xfi_pextp_regmap, 0x3010, 0x00022220); ++ regmap_write(priv->xfi_pextp_regmap, 0x5064, 0x0F020A01); ++ regmap_write(priv->xfi_pextp_regmap, 0x50B4, 0x06100600); ++ regmap_write(priv->xfi_pextp_regmap, 0x3048, 0x40704000); ++ regmap_write(priv->xfi_pextp_regmap, 0x3050, 0xA8000000); ++ regmap_write(priv->xfi_pextp_regmap, 0x3054, 0x000000AA); ++ regmap_write(priv->xfi_pextp_regmap, 0x306C, 0x00000F00); ++ regmap_write(priv->xfi_pextp_regmap, 0xA060, 0x00040000); ++ regmap_write(priv->xfi_pextp_regmap, 0x90D0, 0x00000001); ++ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200E800); ++ udelay(150); ++ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C111); ++ ndelay(1020); ++ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C101); ++ udelay(15); ++ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C111); ++ ndelay(1020); ++ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C101); ++ udelay(100); ++ regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000030); ++ regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F00); ++ regmap_write(priv->xfi_pextp_regmap, 0x3040, 0x30000000); ++ udelay(400); ++} ++ ++static void mtk_usxgmii_an_init(struct mtk_eth_priv *priv) ++{ ++ mtk_xfi_pll_enable(priv); ++ mtk_usxgmii_reset(priv); ++ mtk_usxgmii_setup_phya_an_10000(priv); ++} ++ + static void mtk_mac_init(struct mtk_eth_priv *priv) + { + int i, ge_mode = 0; +@@ -1222,6 +1373,36 @@ static void mtk_mac_init(struct mtk_eth_ + } + } + ++static void mtk_xmac_init(struct mtk_eth_priv *priv) ++{ ++ u32 sts; ++ ++ switch (priv->phy_interface) { ++ case PHY_INTERFACE_MODE_USXGMII: ++ mtk_usxgmii_an_init(priv); ++ break; ++ default: ++ break; ++ } ++ ++ /* Set GMAC to the correct mode */ ++ mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, ++ SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id), ++ 0); ++ ++ if (priv->gmac_id == 1) { ++ mtk_infra_rmw(priv, TOPMISC_NETSYS_PCS_MUX, ++ NETSYS_PCS_MUX_MASK, MUX_G2_USXGMII_SEL); ++ } else if (priv->gmac_id == 2) { ++ sts = mtk_gmac_read(priv, XGMAC_STS(priv->gmac_id)); ++ sts |= XGMAC_FORCE_LINK; ++ mtk_gmac_write(priv, XGMAC_STS(priv->gmac_id), sts); ++ } ++ ++ /* Force GMAC link down */ ++ mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), FORCE_MODE); ++} ++ + static void mtk_eth_fifo_init(struct mtk_eth_priv *priv) + { + char *pkt_base = priv->pkt_pool; +@@ -1463,7 +1644,10 @@ static int mtk_eth_probe(struct udevice + ARCH_DMA_MINALIGN); + + /* Set MAC mode */ +- mtk_mac_init(priv); ++ if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII) ++ mtk_xmac_init(priv); ++ else ++ mtk_mac_init(priv); + + /* Probe phy if switch is not specified */ + if (priv->sw == SW_NONE) +@@ -1581,6 +1765,46 @@ static int mtk_eth_of_to_plat(struct ude + } + + priv->pn_swap = ofnode_read_bool(args.node, "pn_swap"); ++ } else if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII) { ++ /* get corresponding usxgmii phandle */ ++ ret = dev_read_phandle_with_args(dev, "mediatek,usxgmiisys", ++ NULL, 0, 0, &args); ++ if (ret) ++ return ret; ++ ++ priv->usxgmii_regmap = syscon_node_to_regmap(args.node); ++ if (IS_ERR(priv->usxgmii_regmap)) ++ return PTR_ERR(priv->usxgmii_regmap); ++ ++ /* get corresponding xfi_pextp phandle */ ++ ret = dev_read_phandle_with_args(dev, "mediatek,xfi_pextp", ++ NULL, 0, 0, &args); ++ if (ret) ++ return ret; ++ ++ priv->xfi_pextp_regmap = syscon_node_to_regmap(args.node); ++ if (IS_ERR(priv->xfi_pextp_regmap)) ++ return PTR_ERR(priv->xfi_pextp_regmap); ++ ++ /* get corresponding xfi_pll phandle */ ++ ret = dev_read_phandle_with_args(dev, "mediatek,xfi_pll", ++ NULL, 0, 0, &args); ++ if (ret) ++ return ret; ++ ++ priv->xfi_pll_regmap = syscon_node_to_regmap(args.node); ++ if (IS_ERR(priv->xfi_pll_regmap)) ++ return PTR_ERR(priv->xfi_pll_regmap); ++ ++ /* get corresponding toprgu phandle */ ++ ret = dev_read_phandle_with_args(dev, "mediatek,toprgu", ++ NULL, 0, 0, &args); ++ if (ret) ++ return ret; ++ ++ priv->toprgu_regmap = syscon_node_to_regmap(args.node); ++ if (IS_ERR(priv->toprgu_regmap)) ++ return PTR_ERR(priv->toprgu_regmap); + } + + /* check for switch first, otherwise phy will be used */ +--- a/drivers/net/mtk_eth.h ++++ b/drivers/net/mtk_eth.h +@@ -68,6 +68,11 @@ enum mkt_eth_capabilities { + #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) + + /* Top misc registers */ ++#define TOPMISC_NETSYS_PCS_MUX 0x84 ++#define NETSYS_PCS_MUX_MASK GENMASK(1, 0) ++#define MUX_G2_USXGMII_SEL BIT(1) ++#define MUX_HSGMII1_G1_SEL BIT(0) ++ + #define USB_PHY_SWITCH_REG 0x218 + #define QPHY_SEL_MASK 0x3 + #define SGMII_QPHY_SEL 0x2 +@@ -98,6 +103,15 @@ enum mkt_eth_capabilities { + #define SGMSYS_GEN2_SPEED_V2 0x128 + #define SGMSYS_SPEED_2500 BIT(2) + ++/* USXGMII subsystem config registers */ ++/* Register to control USXGMII XFI PLL digital */ ++#define XFI_PLL_DIG_GLB8 0x08 ++#define RG_XFI_PLL_EN BIT(31) ++ ++/* Register to control USXGMII XFI PLL analog */ ++#define XFI_PLL_ANA_GLB8 0x108 ++#define RG_XFI_PLL_ANA_SWWA 0x02283248 ++ + /* Frame Engine Registers */ + #define FE_GLO_MISC_REG 0x124 + #define PDMA_VER_V2 BIT(4) +@@ -221,6 +235,16 @@ enum mkt_eth_capabilities { + #define TD_DM_DRVP_S 0 + #define TD_DM_DRVP_M 0x0f + ++/* XGMAC Status Registers */ ++#define XGMAC_STS(x) (((x) == 2) ? 0x001C : 0x000C) ++#define XGMAC_FORCE_LINK BIT(15) ++ ++/* XGMAC Registers */ ++#define XGMAC_PORT_MCR(x) (0x2000 + (((x) - 1) * 0x1000)) ++#define XGMAC_TRX_DISABLE 0xf ++#define XGMAC_FORCE_TX_FC BIT(5) ++#define XGMAC_FORCE_RX_FC BIT(4) ++ + /* MT7530 Registers */ + + #define PCR_REG(p) (0x2004 + (p) * 0x100) diff --git a/package/boot/uboot-mediatek/patches/101-25-net-mediatek-add-support-for-NETSYS-v3.patch b/package/boot/uboot-mediatek/patches/101-25-net-mediatek-add-support-for-NETSYS-v3.patch new file mode 100644 index 00000000000..691b59faed8 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/101-25-net-mediatek-add-support-for-NETSYS-v3.patch @@ -0,0 +1,221 @@ +From 7d201749cc49a58fb5e791d1e099ec3e3489e16d Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 19 Jul 2023 17:17:37 +0800 +Subject: [PATCH 25/29] net: mediatek: add support for NETSYS v3 + +This patch adds support for NETSYS v3 hardware. +Comparing to NETSYS v2, NETSYS v3 has three GMACs. + +Signed-off-by: Weijie Gao +--- + drivers/net/mtk_eth.c | 49 ++++++++++++++++++++++++++++++++----------- + drivers/net/mtk_eth.h | 7 +++++++ + 2 files changed, 44 insertions(+), 12 deletions(-) + +--- a/drivers/net/mtk_eth.c ++++ b/drivers/net/mtk_eth.c +@@ -76,6 +76,7 @@ enum mtk_switch { + * @caps Flags shown the extra capability for the SoC + * @ana_rgc3: The offset for register ANA_RGC3 related to + * sgmiisys syscon ++ * @gdma_count: Number of GDMAs + * @pdma_base: Register base of PDMA block + * @txd_size: Tx DMA descriptor size. + * @rxd_size: Rx DMA descriptor size. +@@ -83,6 +84,7 @@ enum mtk_switch { + struct mtk_soc_data { + u32 caps; + u32 ana_rgc3; ++ u32 gdma_count; + u32 pdma_base; + u32 txd_size; + u32 rxd_size; +@@ -159,7 +161,9 @@ static void mtk_gdma_write(struct mtk_et + { + u32 gdma_base; + +- if (no == 1) ++ if (no == 2) ++ gdma_base = GDMA3_BASE; ++ else if (no == 1) + gdma_base = GDMA2_BASE; + else + gdma_base = GDMA1_BASE; +@@ -1429,7 +1433,10 @@ static void mtk_eth_fifo_init(struct mtk + txd->txd1 = virt_to_phys(pkt_base); + txd->txd2 = PDMA_TXD2_DDONE | PDMA_TXD2_LS0; + +- if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2)) ++ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) ++ txd->txd5 = PDMA_V2_TXD5_FPORT_SET(priv->gmac_id == 2 ? ++ 15 : priv->gmac_id + 1); ++ else if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2)) + txd->txd5 = PDMA_V2_TXD5_FPORT_SET(priv->gmac_id + 1); + else + txd->txd4 = PDMA_V1_TXD4_FPORT_SET(priv->gmac_id + 1); +@@ -1442,7 +1449,8 @@ static void mtk_eth_fifo_init(struct mtk + + rxd->rxd1 = virt_to_phys(pkt_base); + +- if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2)) ++ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || ++ MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) + rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN); + else + rxd->rxd2 = PDMA_V1_RXD2_PLEN0_SET(PKTSIZE_ALIGN); +@@ -1466,7 +1474,7 @@ static void mtk_eth_fifo_init(struct mtk + static int mtk_eth_start(struct udevice *dev) + { + struct mtk_eth_priv *priv = dev_get_priv(dev); +- int ret; ++ int i, ret; + + /* Reset FE */ + reset_assert(&priv->rst_fe); +@@ -1474,16 +1482,24 @@ static int mtk_eth_start(struct udevice + reset_deassert(&priv->rst_fe); + mdelay(10); + +- if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2)) ++ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || ++ MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) + setbits_le32(priv->fe_base + FE_GLO_MISC_REG, PDMA_VER_V2); + + /* Packets forward to PDMA */ + mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, GDMA_FWD_TO_CPU); + +- if (priv->gmac_id == 0) +- mtk_gdma_write(priv, 1, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD); +- else +- mtk_gdma_write(priv, 0, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD); ++ for (i = 0; i < priv->soc->gdma_count; i++) { ++ if (i == priv->gmac_id) ++ continue; ++ ++ mtk_gdma_write(priv, i, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD); ++ } ++ ++ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) { ++ mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG, ++ GDMA_CPU_BRIDGE_EN); ++ } + + udelay(500); + +@@ -1557,7 +1573,8 @@ static int mtk_eth_send(struct udevice * + flush_dcache_range((ulong)pkt_base, (ulong)pkt_base + + roundup(length, ARCH_DMA_MINALIGN)); + +- if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2)) ++ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || ++ MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) + txd->txd2 = PDMA_TXD2_LS0 | PDMA_V2_TXD2_SDL0_SET(length); + else + txd->txd2 = PDMA_TXD2_LS0 | PDMA_V1_TXD2_SDL0_SET(length); +@@ -1583,7 +1600,8 @@ static int mtk_eth_recv(struct udevice * + return -EAGAIN; + } + +- if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2)) ++ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || ++ MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) + length = PDMA_V2_RXD2_PLEN0_GET(rxd->rxd2); + else + length = PDMA_V1_RXD2_PLEN0_GET(rxd->rxd2); +@@ -1606,7 +1624,8 @@ static int mtk_eth_free_pkt(struct udevi + + rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size; + +- if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2)) ++ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || ++ MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) + rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN); + else + rxd->rxd2 = PDMA_V1_RXD2_PLEN0_SET(PKTSIZE_ALIGN); +@@ -1863,6 +1882,7 @@ static int mtk_eth_of_to_plat(struct ude + static const struct mtk_soc_data mt7986_data = { + .caps = MT7986_CAPS, + .ana_rgc3 = 0x128, ++ .gdma_count = 2, + .pdma_base = PDMA_V2_BASE, + .txd_size = sizeof(struct mtk_tx_dma_v2), + .rxd_size = sizeof(struct mtk_rx_dma_v2), +@@ -1871,6 +1891,7 @@ static const struct mtk_soc_data mt7986_ + static const struct mtk_soc_data mt7981_data = { + .caps = MT7981_CAPS, + .ana_rgc3 = 0x128, ++ .gdma_count = 2, + .pdma_base = PDMA_V2_BASE, + .txd_size = sizeof(struct mtk_tx_dma_v2), + .rxd_size = sizeof(struct mtk_rx_dma_v2), +@@ -1878,6 +1899,7 @@ static const struct mtk_soc_data mt7981_ + + static const struct mtk_soc_data mt7629_data = { + .ana_rgc3 = 0x128, ++ .gdma_count = 2, + .pdma_base = PDMA_V1_BASE, + .txd_size = sizeof(struct mtk_tx_dma), + .rxd_size = sizeof(struct mtk_rx_dma), +@@ -1885,6 +1907,7 @@ static const struct mtk_soc_data mt7629_ + + static const struct mtk_soc_data mt7623_data = { + .caps = MT7623_CAPS, ++ .gdma_count = 2, + .pdma_base = PDMA_V1_BASE, + .txd_size = sizeof(struct mtk_tx_dma), + .rxd_size = sizeof(struct mtk_rx_dma), +@@ -1892,6 +1915,7 @@ static const struct mtk_soc_data mt7623_ + + static const struct mtk_soc_data mt7622_data = { + .ana_rgc3 = 0x2028, ++ .gdma_count = 2, + .pdma_base = PDMA_V1_BASE, + .txd_size = sizeof(struct mtk_tx_dma), + .rxd_size = sizeof(struct mtk_rx_dma), +@@ -1899,6 +1923,7 @@ static const struct mtk_soc_data mt7622_ + + static const struct mtk_soc_data mt7621_data = { + .caps = MT7621_CAPS, ++ .gdma_count = 2, + .pdma_base = PDMA_V1_BASE, + .txd_size = sizeof(struct mtk_tx_dma), + .rxd_size = sizeof(struct mtk_rx_dma), +--- a/drivers/net/mtk_eth.h ++++ b/drivers/net/mtk_eth.h +@@ -18,6 +18,7 @@ enum mkt_eth_capabilities { + MTK_U3_COPHY_V2_BIT, + MTK_INFRA_BIT, + MTK_NETSYS_V2_BIT, ++ MTK_NETSYS_V3_BIT, + + /* PATH BITS */ + MTK_ETH_PATH_GMAC1_TRGMII_BIT, +@@ -29,6 +30,7 @@ enum mkt_eth_capabilities { + #define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT) + #define MTK_INFRA BIT(MTK_INFRA_BIT) + #define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) ++#define MTK_NETSYS_V3 BIT(MTK_NETSYS_V3_BIT) + + /* Supported path present on SoCs */ + #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) +@@ -52,8 +54,10 @@ enum mkt_eth_capabilities { + /* Frame Engine Register Bases */ + #define PDMA_V1_BASE 0x0800 + #define PDMA_V2_BASE 0x6000 ++#define PDMA_V3_BASE 0x6800 + #define GDMA1_BASE 0x0500 + #define GDMA2_BASE 0x1500 ++#define GDMA3_BASE 0x0540 + #define GMAC_BASE 0x10000 + + /* Ethernet subsystem registers */ +@@ -153,6 +157,9 @@ enum mkt_eth_capabilities { + #define UN_DP_S 0 + #define UN_DP_M 0x0f + ++#define GDMA_EG_CTRL_REG 0x004 ++#define GDMA_CPU_BRIDGE_EN BIT(31) ++ + #define GDMA_MAC_LSB_REG 0x008 + + #define GDMA_MAC_MSB_REG 0x00c diff --git a/package/boot/uboot-mediatek/patches/101-26-net-mediatek-add-support-for-MediaTek-MT7988-SoC.patch b/package/boot/uboot-mediatek/patches/101-26-net-mediatek-add-support-for-MediaTek-MT7988-SoC.patch new file mode 100644 index 00000000000..29e86490521 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/101-26-net-mediatek-add-support-for-MediaTek-MT7988-SoC.patch @@ -0,0 +1,327 @@ +From 59dba9d87c9caf04a5d797af46699055a53870f4 Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 19 Jul 2023 17:17:41 +0800 +Subject: [PATCH 26/29] net: mediatek: add support for MediaTek MT7988 SoC + +This patch adds support for MediaTek MT7988. + +MT7988 features MediaTek NETSYS v3, including three GMACs, and two +of them supports 10Gbps USXGMII. + +MT7988 embeds a MT7531 switch (not MCM) which supports accessing +internal registers through MMIO instead of MDIO. + +Signed-off-by: Weijie Gao +--- + drivers/net/mtk_eth.c | 158 +++++++++++++++++++++++++++++++++++++++++- + drivers/net/mtk_eth.h | 20 ++++++ + 2 files changed, 177 insertions(+), 1 deletion(-) + +--- a/drivers/net/mtk_eth.c ++++ b/drivers/net/mtk_eth.c +@@ -54,6 +54,16 @@ + (DP_PDMA << MC_DP_S) | \ + (DP_PDMA << UN_DP_S)) + ++#define GDMA_BRIDGE_TO_CPU \ ++ (0xC0000000 | \ ++ GDM_ICS_EN | \ ++ GDM_TCS_EN | \ ++ GDM_UCS_EN | \ ++ (DP_PDMA << MYMAC_DP_S) | \ ++ (DP_PDMA << BC_DP_S) | \ ++ (DP_PDMA << MC_DP_S) | \ ++ (DP_PDMA << UN_DP_S)) ++ + #define GDMA_FWD_DISCARD \ + (0x20000000 | \ + GDM_ICS_EN | \ +@@ -68,7 +78,8 @@ + enum mtk_switch { + SW_NONE, + SW_MT7530, +- SW_MT7531 ++ SW_MT7531, ++ SW_MT7988, + }; + + /* struct mtk_soc_data - This is the structure holding all differences +@@ -102,6 +113,7 @@ struct mtk_eth_priv { + void __iomem *fe_base; + void __iomem *gmac_base; + void __iomem *sgmii_base; ++ void __iomem *gsw_base; + + struct regmap *ethsys_regmap; + +@@ -171,6 +183,11 @@ static void mtk_gdma_write(struct mtk_et + writel(val, priv->fe_base + gdma_base + reg); + } + ++static void mtk_fe_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set) ++{ ++ clrsetbits_le32(priv->fe_base + reg, clr, set); ++} ++ + static u32 mtk_gmac_read(struct mtk_eth_priv *priv, u32 reg) + { + return readl(priv->gmac_base + reg); +@@ -208,6 +225,16 @@ static void mtk_infra_rmw(struct mtk_eth + regmap_write(priv->infra_regmap, reg, val); + } + ++static u32 mtk_gsw_read(struct mtk_eth_priv *priv, u32 reg) ++{ ++ return readl(priv->gsw_base + reg); ++} ++ ++static void mtk_gsw_write(struct mtk_eth_priv *priv, u32 reg, u32 val) ++{ ++ writel(val, priv->gsw_base + reg); ++} ++ + /* Direct MDIO clause 22/45 access via SoC */ + static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data, + u32 cmd, u32 st) +@@ -342,6 +369,11 @@ static int mt753x_reg_read(struct mtk_et + { + int ret, low_word, high_word; + ++ if (priv->sw == SW_MT7988) { ++ *data = mtk_gsw_read(priv, reg); ++ return 0; ++ } ++ + /* Write page address */ + ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6); + if (ret) +@@ -367,6 +399,11 @@ static int mt753x_reg_write(struct mtk_e + { + int ret; + ++ if (priv->sw == SW_MT7988) { ++ mtk_gsw_write(priv, reg, data); ++ return 0; ++ } ++ + /* Write page address */ + ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6); + if (ret) +@@ -537,6 +574,7 @@ static int mtk_mdio_register(struct udev + priv->mmd_write = mtk_mmd_ind_write; + break; + case SW_MT7531: ++ case SW_MT7988: + priv->mii_read = mt7531_mii_ind_read; + priv->mii_write = mt7531_mii_ind_write; + priv->mmd_read = mt7531_mmd_ind_read; +@@ -957,6 +995,103 @@ static int mt7531_setup(struct mtk_eth_p + return 0; + } + ++static void mt7988_phy_setting(struct mtk_eth_priv *priv) ++{ ++ u16 val; ++ u32 i; ++ ++ for (i = 0; i < MT753X_NUM_PHYS; i++) { ++ /* Enable HW auto downshift */ ++ priv->mii_write(priv, i, 0x1f, 0x1); ++ val = priv->mii_read(priv, i, PHY_EXT_REG_14); ++ val |= PHY_EN_DOWN_SHFIT; ++ priv->mii_write(priv, i, PHY_EXT_REG_14, val); ++ ++ /* PHY link down power saving enable */ ++ val = priv->mii_read(priv, i, PHY_EXT_REG_17); ++ val |= PHY_LINKDOWN_POWER_SAVING_EN; ++ priv->mii_write(priv, i, PHY_EXT_REG_17, val); ++ } ++} ++ ++static void mt7988_mac_control(struct mtk_eth_priv *priv, bool enable) ++{ ++ u32 pmcr = FORCE_MODE_LNK; ++ ++ if (enable) ++ pmcr = priv->mt753x_pmcr; ++ ++ mt753x_reg_write(priv, PMCR_REG(6), pmcr); ++} ++ ++static int mt7988_setup(struct mtk_eth_priv *priv) ++{ ++ u16 phy_addr, phy_val; ++ u32 pmcr; ++ int i; ++ ++ priv->gsw_base = regmap_get_range(priv->ethsys_regmap, 0) + GSW_BASE; ++ ++ priv->mt753x_phy_base = (priv->mt753x_smi_addr + 1) & ++ MT753X_SMI_ADDR_MASK; ++ ++ /* Turn off PHYs */ ++ for (i = 0; i < MT753X_NUM_PHYS; i++) { ++ phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i); ++ phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); ++ phy_val |= BMCR_PDOWN; ++ priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); ++ } ++ ++ switch (priv->phy_interface) { ++ case PHY_INTERFACE_MODE_USXGMII: ++ /* Use CPU bridge instead of actual USXGMII path */ ++ ++ /* Set GDM1 no drop */ ++ mtk_fe_rmw(priv, PSE_NO_DROP_CFG_REG, 0, PSE_NO_DROP_GDM1); ++ ++ /* Enable GDM1 to GSW CPU bridge */ ++ mtk_gmac_rmw(priv, GMAC_MAC_MISC_REG, 0, BIT(0)); ++ ++ /* XGMAC force link up */ ++ mtk_gmac_rmw(priv, GMAC_XGMAC_STS_REG, 0, P1_XGMAC_FORCE_LINK); ++ ++ /* Setup GSW CPU bridge IPG */ ++ mtk_gmac_rmw(priv, GMAC_GSW_CFG_REG, GSWTX_IPG_M | GSWRX_IPG_M, ++ (0xB << GSWTX_IPG_S) | (0xB << GSWRX_IPG_S)); ++ break; ++ default: ++ printf("Error: MT7988 GSW does not support %s interface\n", ++ phy_string_for_interface(priv->phy_interface)); ++ break; ++ } ++ ++ pmcr = MT7988_FORCE_MODE | ++ (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | ++ MAC_MODE | MAC_TX_EN | MAC_RX_EN | ++ BKOFF_EN | BACKPR_EN | ++ FORCE_RX_FC | FORCE_TX_FC | ++ (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX | ++ FORCE_LINK; ++ ++ priv->mt753x_pmcr = pmcr; ++ ++ /* Keep MAC link down before starting eth */ ++ mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK); ++ ++ /* Turn on PHYs */ ++ for (i = 0; i < MT753X_NUM_PHYS; i++) { ++ phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i); ++ phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); ++ phy_val &= ~BMCR_PDOWN; ++ priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); ++ } ++ ++ mt7988_phy_setting(priv); ++ ++ return 0; ++} ++ + static int mt753x_switch_init(struct mtk_eth_priv *priv) + { + int ret; +@@ -1497,6 +1632,11 @@ static int mtk_eth_start(struct udevice + } + + if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) { ++ if (priv->sw == SW_MT7988 && priv->gmac_id == 0) { ++ mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, ++ GDMA_BRIDGE_TO_CPU); ++ } ++ + mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG, + GDMA_CPU_BRIDGE_EN); + } +@@ -1845,6 +1985,12 @@ static int mtk_eth_of_to_plat(struct ude + priv->switch_mac_control = mt7531_mac_control; + priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR; + priv->mt753x_reset_wait_time = 200; ++ } else if (!strcmp(str, "mt7988")) { ++ priv->sw = SW_MT7988; ++ priv->switch_init = mt7988_setup; ++ priv->switch_mac_control = mt7988_mac_control; ++ priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR; ++ priv->mt753x_reset_wait_time = 50; + } else { + printf("error: unsupported switch\n"); + return -EINVAL; +@@ -1879,6 +2025,15 @@ static int mtk_eth_of_to_plat(struct ude + return 0; + } + ++static const struct mtk_soc_data mt7988_data = { ++ .caps = MT7988_CAPS, ++ .ana_rgc3 = 0x128, ++ .gdma_count = 3, ++ .pdma_base = PDMA_V3_BASE, ++ .txd_size = sizeof(struct mtk_tx_dma_v2), ++ .rxd_size = sizeof(struct mtk_rx_dma_v2), ++}; ++ + static const struct mtk_soc_data mt7986_data = { + .caps = MT7986_CAPS, + .ana_rgc3 = 0x128, +@@ -1930,6 +2085,7 @@ static const struct mtk_soc_data mt7621_ + }; + + static const struct udevice_id mtk_eth_ids[] = { ++ { .compatible = "mediatek,mt7988-eth", .data = (ulong)&mt7988_data }, + { .compatible = "mediatek,mt7986-eth", .data = (ulong)&mt7986_data }, + { .compatible = "mediatek,mt7981-eth", .data = (ulong)&mt7981_data }, + { .compatible = "mediatek,mt7629-eth", .data = (ulong)&mt7629_data }, +--- a/drivers/net/mtk_eth.h ++++ b/drivers/net/mtk_eth.h +@@ -51,6 +51,8 @@ enum mkt_eth_capabilities { + + #define MT7986_CAPS (MTK_NETSYS_V2) + ++#define MT7988_CAPS (MTK_NETSYS_V3 | MTK_INFRA) ++ + /* Frame Engine Register Bases */ + #define PDMA_V1_BASE 0x0800 + #define PDMA_V2_BASE 0x6000 +@@ -59,6 +61,7 @@ enum mkt_eth_capabilities { + #define GDMA2_BASE 0x1500 + #define GDMA3_BASE 0x0540 + #define GMAC_BASE 0x10000 ++#define GSW_BASE 0x20000 + + /* Ethernet subsystem registers */ + +@@ -117,6 +120,9 @@ enum mkt_eth_capabilities { + #define RG_XFI_PLL_ANA_SWWA 0x02283248 + + /* Frame Engine Registers */ ++#define PSE_NO_DROP_CFG_REG 0x108 ++#define PSE_NO_DROP_GDM1 BIT(1) ++ + #define FE_GLO_MISC_REG 0x124 + #define PDMA_VER_V2 BIT(4) + +@@ -187,6 +193,17 @@ enum mkt_eth_capabilities { + #define MDIO_RW_DATA_S 0 + #define MDIO_RW_DATA_M 0xffff + ++#define GMAC_XGMAC_STS_REG 0x000c ++#define P1_XGMAC_FORCE_LINK BIT(15) ++ ++#define GMAC_MAC_MISC_REG 0x0010 ++ ++#define GMAC_GSW_CFG_REG 0x0080 ++#define GSWTX_IPG_M 0xF0000 ++#define GSWTX_IPG_S 16 ++#define GSWRX_IPG_M 0xF ++#define GSWRX_IPG_S 0 ++ + /* MDIO_CMD: MDIO commands */ + #define MDIO_CMD_ADDR 0 + #define MDIO_CMD_WRITE 1 +@@ -285,6 +302,9 @@ enum mkt_eth_capabilities { + FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \ + FORCE_MODE_DPX | FORCE_MODE_SPD | \ + FORCE_MODE_LNK ++#define MT7988_FORCE_MODE FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \ ++ FORCE_MODE_DPX | FORCE_MODE_SPD | \ ++ FORCE_MODE_LNK + + /* MT7531 SGMII Registers */ + #define MT7531_SGMII_REG_BASE 0x5000 diff --git a/package/boot/uboot-mediatek/patches/101-27-tools-mtk_image-use-uint32_t-for-ghf-header-magic-an.patch b/package/boot/uboot-mediatek/patches/101-27-tools-mtk_image-use-uint32_t-for-ghf-header-magic-an.patch new file mode 100644 index 00000000000..07620f77b31 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/101-27-tools-mtk_image-use-uint32_t-for-ghf-header-magic-an.patch @@ -0,0 +1,55 @@ +From 757b997f1f5a958e6fec3d5aee1ff5cdf5766711 Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 19 Jul 2023 17:17:45 +0800 +Subject: [PATCH 27/29] tools: mtk_image: use uint32_t for ghf header magic and + version + +This patch converts magic and version fields of ghf common header +to one field with the type of uint32_t to make this header flexible +for futher updates. + +Signed-off-by: Weijie Gao +--- + tools/mtk_image.c | 10 ++++++---- + tools/mtk_image.h | 6 +++--- + 2 files changed, 9 insertions(+), 7 deletions(-) + +--- a/tools/mtk_image.c ++++ b/tools/mtk_image.c +@@ -542,11 +542,13 @@ static void put_brom_layout_header(struc + hdr->type = cpu_to_le32(type); + } + +-static void put_ghf_common_header(struct gfh_common_header *gfh, int size, +- int type, int ver) ++static void put_ghf_common_header(struct gfh_common_header *gfh, uint16_t size, ++ uint16_t type, uint8_t ver) + { +- memcpy(gfh->magic, GFH_HEADER_MAGIC, sizeof(gfh->magic)); +- gfh->version = ver; ++ uint32_t magic_version = GFH_HEADER_MAGIC | ++ (uint32_t)ver << GFH_HEADER_VERSION_SHIFT; ++ ++ gfh->magic_version = cpu_to_le32(magic_version); + gfh->size = cpu_to_le16(size); + gfh->type = cpu_to_le16(type); + } +--- a/tools/mtk_image.h ++++ b/tools/mtk_image.h +@@ -63,13 +63,13 @@ struct gen_device_header { + + /* BootROM header definitions */ + struct gfh_common_header { +- uint8_t magic[3]; +- uint8_t version; ++ uint32_t magic_version; + uint16_t size; + uint16_t type; + }; + +-#define GFH_HEADER_MAGIC "MMM" ++#define GFH_HEADER_MAGIC 0x4D4D4D ++#define GFH_HEADER_VERSION_SHIFT 24 + + #define GFH_TYPE_FILE_INFO 0 + #define GFH_TYPE_BL_INFO 1 diff --git a/package/boot/uboot-mediatek/patches/101-28-arm-mediatek-add-support-for-MediaTek-MT7988-SoC.patch b/package/boot/uboot-mediatek/patches/101-28-arm-mediatek-add-support-for-MediaTek-MT7988-SoC.patch new file mode 100644 index 00000000000..f54a028b426 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/101-28-arm-mediatek-add-support-for-MediaTek-MT7988-SoC.patch @@ -0,0 +1,606 @@ +From 884430dadcc2c5d0a2b248795001955a9fa5a1a9 Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 19 Jul 2023 17:17:49 +0800 +Subject: [PATCH 28/29] arm: mediatek: add support for MediaTek MT7988 SoC + +This patch adds basic support for MediaTek MT7988 SoC. +This includes files that will initialize the SoC after boot and +its device tree. + +Signed-off-by: Weijie Gao +--- + arch/arm/dts/mt7988-u-boot.dtsi | 25 ++ + arch/arm/dts/mt7988.dtsi | 391 ++++++++++++++++++ + arch/arm/mach-mediatek/Kconfig | 13 +- + arch/arm/mach-mediatek/Makefile | 1 + + arch/arm/mach-mediatek/mt7988/Makefile | 4 + + arch/arm/mach-mediatek/mt7988/init.c | 63 +++ + arch/arm/mach-mediatek/mt7988/lowlevel_init.S | 30 ++ + 7 files changed, 526 insertions(+), 1 deletion(-) + create mode 100644 arch/arm/dts/mt7988-u-boot.dtsi + create mode 100644 arch/arm/dts/mt7988.dtsi + create mode 100644 arch/arm/mach-mediatek/mt7988/Makefile + create mode 100644 arch/arm/mach-mediatek/mt7988/init.c + create mode 100644 arch/arm/mach-mediatek/mt7988/lowlevel_init.S + +--- /dev/null ++++ b/arch/arm/dts/mt7988-u-boot.dtsi +@@ -0,0 +1,25 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2022 MediaTek Inc. ++ * Author: Sam Shih ++ */ ++ ++&system_clk { ++ bootph-all; ++}; ++ ++&spi_clk { ++ bootph-all; ++}; ++ ++&uart0 { ++ bootph-all; ++}; ++ ++&uart1 { ++ bootph-all; ++}; ++ ++&uart2 { ++ bootph-all; ++}; +--- /dev/null ++++ b/arch/arm/dts/mt7988.dtsi +@@ -0,0 +1,391 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2022 MediaTek Inc. ++ * Author: Sam Shih ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++/ { ++ compatible = "mediatek,mt7988-rfb"; ++ interrupt-parent = <&gic>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu0: cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a73"; ++ reg = <0x0>; ++ mediatek,hwver = <&hwver>; ++ }; ++ ++ cpu1: cpu@1 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a73"; ++ reg = <0x1>; ++ mediatek,hwver = <&hwver>; ++ }; ++ ++ cpu2: cpu@2 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a73"; ++ reg = <0x2>; ++ mediatek,hwver = <&hwver>; ++ }; ++ ++ cpu3: cpu@3 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a73"; ++ reg = <0x3>; ++ mediatek,hwver = <&hwver>; ++ }; ++ }; ++ ++ system_clk: dummy40m { ++ compatible = "fixed-clock"; ++ clock-frequency = <40000000>; ++ #clock-cells = <0>; ++ }; ++ ++ spi_clk: dummy208m { ++ compatible = "fixed-clock"; ++ clock-frequency = <208000000>; ++ #clock-cells = <0>; ++ }; ++ ++ hwver: hwver { ++ compatible = "mediatek,hwver", "syscon"; ++ reg = <0 0x8000000 0 0x1000>; ++ }; ++ ++ timer { ++ compatible = "arm,armv8-timer"; ++ interrupt-parent = <&gic>; ++ clock-frequency = <13000000>; ++ interrupts = , ++ , ++ , ++ ; ++ }; ++ ++ watchdog: watchdog@1001c000 { ++ compatible = "mediatek,mt7622-wdt", ++ "mediatek,mt6589-wdt", ++ "syscon"; ++ reg = <0 0x1001c000 0 0x1000>; ++ interrupts = ; ++ #reset-cells = <1>; ++ }; ++ ++ gic: interrupt-controller@c000000 { ++ compatible = "arm,gic-v3"; ++ #interrupt-cells = <3>; ++ interrupt-parent = <&gic>; ++ interrupt-controller; ++ reg = <0 0x0c000000 0 0x40000>, /* GICD */ ++ <0 0x0c080000 0 0x200000>; /* GICR */ ++ interrupts = ; ++ }; ++ ++ infracfg_ao_cgs: infracfg_ao_cgs@10001000 { ++ compatible = "mediatek,mt7988-infracfg_ao_cgs", "syscon"; ++ reg = <0 0x10001000 0 0x1000>; ++ clock-parent = <&infracfg_ao>; ++ #clock-cells = <1>; ++ }; ++ ++ apmixedsys: apmixedsys@1001e000 { ++ compatible = "mediatek,mt7988-fixed-plls", "syscon"; ++ reg = <0 0x1001e000 0 0x1000>; ++ #clock-cells = <1>; ++ }; ++ ++ topckgen: topckgen@1001b000 { ++ compatible = "mediatek,mt7988-topckgen", "syscon"; ++ reg = <0 0x1001b000 0 0x1000>; ++ clock-parent = <&apmixedsys>; ++ #clock-cells = <1>; ++ }; ++ ++ pinctrl: pinctrl@1001f000 { ++ compatible = "mediatek,mt7988-pinctrl"; ++ reg = <0 0x1001f000 0 0x1000>, ++ <0 0x11c10000 0 0x1000>, ++ <0 0x11d00000 0 0x1000>, ++ <0 0x11d20000 0 0x1000>, ++ <0 0x11e00000 0 0x1000>, ++ <0 0x11f00000 0 0x1000>, ++ <0 0x1000b000 0 0x1000>; ++ reg-names = "gpio_base", "iocfg_tr_base", "iocfg_br_base", ++ "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base", ++ "eint"; ++ gpio: gpio-controller { ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; ++ }; ++ ++ sgmiisys0: syscon@10060000 { ++ compatible = "mediatek,mt7988-sgmiisys_0", "syscon"; ++ reg = <0 0x10060000 0 0x1000>; ++ clock-parent = <&topckgen>; ++ #clock-cells = <1>; ++ }; ++ ++ sgmiisys1: syscon@10070000 { ++ compatible = "mediatek,mt7988-sgmiisys_1", "syscon"; ++ reg = <0 0x10070000 0 0x1000>; ++ clock-parent = <&topckgen>; ++ #clock-cells = <1>; ++ }; ++ ++ usxgmiisys0: syscon@10080000 { ++ compatible = "mediatek,mt7988-usxgmiisys_0", "syscon"; ++ reg = <0 0x10080000 0 0x1000>; ++ clock-parent = <&topckgen>; ++ #clock-cells = <1>; ++ }; ++ ++ usxgmiisys1: syscon@10081000 { ++ compatible = "mediatek,mt7988-usxgmiisys_1", "syscon"; ++ reg = <0 0x10081000 0 0x1000>; ++ clock-parent = <&topckgen>; ++ #clock-cells = <1>; ++ }; ++ ++ xfi_pextp0: syscon@11f20000 { ++ compatible = "mediatek,mt7988-xfi_pextp_0", "syscon"; ++ reg = <0 0x11f20000 0 0x10000>; ++ clock-parent = <&topckgen>; ++ #clock-cells = <1>; ++ }; ++ ++ xfi_pextp1: syscon@11f30000 { ++ compatible = "mediatek,mt7988-xfi_pextp_1", "syscon"; ++ reg = <0 0x11f30000 0 0x10000>; ++ clock-parent = <&topckgen>; ++ #clock-cells = <1>; ++ }; ++ ++ xfi_pll: syscon@11f40000 { ++ compatible = "mediatek,mt7988-xfi_pll", "syscon"; ++ reg = <0 0x11f40000 0 0x1000>; ++ clock-parent = <&topckgen>; ++ #clock-cells = <1>; ++ }; ++ ++ topmisc: topmisc@11d10000 { ++ compatible = "mediatek,mt7988-topmisc", "syscon", ++ "mediatek,mt7988-power-controller"; ++ reg = <0 0x11d10000 0 0x10000>; ++ clock-parent = <&topckgen>; ++ #clock-cells = <1>; ++ }; ++ ++ infracfg_ao: infracfg@10001000 { ++ compatible = "mediatek,mt7988-infracfg", "syscon"; ++ reg = <0 0x10001000 0 0x1000>; ++ clock-parent = <&topckgen>; ++ #clock-cells = <1>; ++ }; ++ ++ uart0: serial@11000000 { ++ compatible = "mediatek,hsuart"; ++ reg = <0 0x11000000 0 0x100>; ++ interrupts = ; ++ clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART0_CK>; ++ assigned-clocks = <&topckgen CK_TOP_UART_SEL>, ++ <&infracfg_ao CK_INFRA_MUX_UART0_SEL>; ++ assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, ++ <&infracfg_ao CK_INFRA_UART_O0>; ++ status = "disabled"; ++ }; ++ ++ uart1: serial@11000100 { ++ compatible = "mediatek,hsuart"; ++ reg = <0 0x11000100 0 0x100>; ++ interrupts = ; ++ clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART1_CK>; ++ assigned-clocks = <&topckgen CK_TOP_UART_SEL>, ++ <&infracfg_ao CK_INFRA_MUX_UART1_SEL>; ++ assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, ++ <&infracfg_ao CK_INFRA_UART_O1>; ++ status = "disabled"; ++ }; ++ ++ uart2: serial@11000200 { ++ compatible = "mediatek,hsuart"; ++ reg = <0 0x11000200 0 0x100>; ++ interrupts = ; ++ clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART2_CK>; ++ assigned-clocks = <&topckgen CK_TOP_UART_SEL>, ++ <&infracfg_ao CK_INFRA_MUX_UART2_SEL>; ++ assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, ++ <&infracfg_ao CK_INFRA_UART_O2>; ++ status = "disabled"; ++ }; ++ ++ i2c0: i2c@11003000 { ++ compatible = "mediatek,mt7988-i2c", ++ "mediatek,mt7981-i2c"; ++ reg = <0 0x11003000 0 0x1000>, ++ <0 0x10217080 0 0x80>; ++ interrupts = ; ++ clock-div = <1>; ++ clocks = <&infracfg_ao CK_INFRA_I2C_BCK>, ++ <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>; ++ clock-names = "main", "dma"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c1: i2c@11004000 { ++ compatible = "mediatek,mt7988-i2c", ++ "mediatek,mt7981-i2c"; ++ reg = <0 0x11004000 0 0x1000>, ++ <0 0x10217100 0 0x80>; ++ interrupts = ; ++ clock-div = <1>; ++ clocks = <&infracfg_ao CK_INFRA_I2C_BCK>, ++ <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>; ++ clock-names = "main", "dma"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c2: i2c@11005000 { ++ compatible = "mediatek,mt7988-i2c", ++ "mediatek,mt7981-i2c"; ++ reg = <0 0x11005000 0 0x1000>, ++ <0 0x10217180 0 0x80>; ++ interrupts = ; ++ clock-div = <1>; ++ clocks = <&infracfg_ao CK_INFRA_I2C_BCK>, ++ <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>; ++ clock-names = "main", "dma"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ pwm: pwm@10048000 { ++ compatible = "mediatek,mt7988-pwm"; ++ reg = <0 0x10048000 0 0x1000>; ++ #pwm-cells = <2>; ++ clocks = <&infracfg_ao CK_INFRA_66M_PWM_BCK>, ++ <&infracfg_ao CK_INFRA_66M_PWM_HCK>, ++ <&infracfg_ao CK_INFRA_66M_PWM_CK1>, ++ <&infracfg_ao CK_INFRA_66M_PWM_CK2>, ++ <&infracfg_ao CK_INFRA_66M_PWM_CK3>, ++ <&infracfg_ao CK_INFRA_66M_PWM_CK4>, ++ <&infracfg_ao CK_INFRA_66M_PWM_CK5>, ++ <&infracfg_ao CK_INFRA_66M_PWM_CK6>, ++ <&infracfg_ao CK_INFRA_66M_PWM_CK7>, ++ <&infracfg_ao CK_INFRA_66M_PWM_CK8>; ++ clock-names = "top", "main", "pwm1", "pwm2", "pwm3", ++ "pwm4","pwm5","pwm6","pwm7","pwm8"; ++ status = "disabled"; ++ }; ++ ++ snand: snand@11001000 { ++ compatible = "mediatek,mt7988-snand", ++ "mediatek,mt7986-snand"; ++ reg = <0 0x11001000 0 0x1000>, ++ <0 0x11002000 0 0x1000>; ++ reg-names = "nfi", "ecc"; ++ interrupts = ; ++ clocks = <&infracfg_ao CK_INFRA_SPINFI>, ++ <&infracfg_ao CK_INFRA_NFI>, ++ <&infracfg_ao CK_INFRA_66M_NFI_HCK>; ++ clock-names = "pad_clk", "nfi_clk", "nfi_hclk"; ++ assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>, ++ <&topckgen CK_TOP_NFI1X_SEL>; ++ assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>, ++ <&topckgen CK_TOP_CB_M_D8>; ++ status = "disabled"; ++ }; ++ ++ spi0: spi@1100a000 { ++ compatible = "mediatek,ipm-spi"; ++ reg = <0 0x11007000 0 0x100>; ++ clocks = <&spi_clk>, ++ <&spi_clk>; ++ clock-names = "sel-clk", "spi-clk"; ++ interrupts = ; ++ status = "disabled"; ++ }; ++ ++ spi1: spi@1100b000 { ++ compatible = "mediatek,ipm-spi"; ++ reg = <0 0x11008000 0 0x100>; ++ interrupts = ; ++ status = "disabled"; ++ }; ++ ++ spi2: spi@11009000 { ++ compatible = "mediatek,ipm-spi"; ++ reg = <0 0x11009000 0 0x100>; ++ clocks = <&spi_clk>, ++ <&spi_clk>; ++ clock-names = "sel-clk", "spi-clk"; ++ interrupts = ; ++ status = "disabled"; ++ }; ++ ++ mmc0: mmc@11230000 { ++ compatible = "mediatek,mt7988-mmc", ++ "mediatek,mt7986-mmc"; ++ reg = <0 0x11230000 0 0x1000>; ++ interrupts = ; ++ clocks = <&infracfg_ao_cgs CK_INFRA_MSDC400>, ++ <&infracfg_ao_cgs CK_INFRA_MSDC2_HCK>, ++ <&infracfg_ao_cgs CK_INFRA_133M_MSDC_0_HCK>, ++ <&infracfg_ao_cgs CK_INFRA_66M_MSDC_0_HCK>; ++ clock-names = "source", "hclk", "source_cg", "axi_cg"; ++ status = "disabled"; ++ }; ++ ++ ethdma: syscon@15000000 { ++ compatible = "mediatek,mt7988-ethdma", "syscon"; ++ reg = <0 0x15000000 0 0x20000>; ++ clock-parent = <&topckgen>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ ethwarp: syscon@15031000 { ++ compatible = "mediatek,mt7988-ethwarp", "syscon"; ++ reg = <0 0x15031000 0 0x1000>; ++ clock-parent = <&topckgen>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ eth: ethernet@15100000 { ++ compatible = "mediatek,mt7988-eth", "syscon"; ++ reg = <0 0x15100000 0 0x20000>; ++ mediatek,ethsys = <ðdma>; ++ mediatek,sgmiisys = <&sgmiisys0>; ++ mediatek,usxgmiisys = <&usxgmiisys0>; ++ mediatek,xfi_pextp = <&xfi_pextp0>; ++ mediatek,xfi_pll = <&xfi_pll>; ++ mediatek,infracfg = <&topmisc>; ++ mediatek,toprgu = <&watchdog>; ++ resets = <ðdma ETHDMA_FE_RST>, <ðwarp ETHWARP_GSW_RST>; ++ reset-names = "fe", "mcm"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ mediatek,mcm; ++ status = "disabled"; ++ }; ++}; +--- a/arch/arm/mach-mediatek/Kconfig ++++ b/arch/arm/mach-mediatek/Kconfig +@@ -58,6 +58,15 @@ config TARGET_MT7986 + including UART, SPI, SPI flash, USB3.0, MMC, NAND, SNFI, PWM, PCIe, + Gigabit Ethernet, I2C, built-in 4x4 Wi-Fi, and PCIe. + ++config TARGET_MT7988 ++ bool "MediaTek MT7988 SoC" ++ select ARM64 ++ select CPU ++ help ++ The MediaTek MT7988 is a ARM64-based SoC with a quad-core Cortex-A73. ++ including UART, SPI, SPI flash, USB3.0, MMC, NAND, SNFI, PWM, PCIe, ++ 10 Gigabit Ethernet , I2C, and PCIe. ++ + config TARGET_MT8183 + bool "MediaTek MT8183 SoC" + select ARM64 +@@ -104,6 +113,7 @@ config SYS_BOARD + default "mt7629" if TARGET_MT7629 + default "mt7981" if TARGET_MT7981 + default "mt7986" if TARGET_MT7986 ++ default "mt7988" if TARGET_MT7988 + default "mt8183" if TARGET_MT8183 + default "mt8512" if TARGET_MT8512 + default "mt8516" if TARGET_MT8516 +@@ -121,6 +131,7 @@ config SYS_CONFIG_NAME + default "mt7629" if TARGET_MT7629 + default "mt7981" if TARGET_MT7981 + default "mt7986" if TARGET_MT7986 ++ default "mt7988" if TARGET_MT7988 + default "mt8183" if TARGET_MT8183 + default "mt8512" if TARGET_MT8512 + default "mt8516" if TARGET_MT8516 +@@ -135,7 +146,7 @@ config MTK_BROM_HEADER_INFO + string + default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7622 + default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 +- default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 ++ default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 || TARGET_MT7988 + default "lk=1" if TARGET_MT7623 + + source "board/mediatek/mt7629/Kconfig" +--- a/arch/arm/mach-mediatek/Makefile ++++ b/arch/arm/mach-mediatek/Makefile +@@ -9,6 +9,7 @@ obj-$(CONFIG_TARGET_MT7623) += mt7623/ + obj-$(CONFIG_TARGET_MT7629) += mt7629/ + obj-$(CONFIG_TARGET_MT7981) += mt7981/ + obj-$(CONFIG_TARGET_MT7986) += mt7986/ ++obj-$(CONFIG_TARGET_MT7988) += mt7988/ + obj-$(CONFIG_TARGET_MT8183) += mt8183/ + obj-$(CONFIG_TARGET_MT8516) += mt8516/ + obj-$(CONFIG_TARGET_MT8518) += mt8518/ +--- /dev/null ++++ b/arch/arm/mach-mediatek/mt7988/Makefile +@@ -0,0 +1,4 @@ ++# SPDX-License-Identifier: GPL-2.0 ++ ++obj-y += init.o ++obj-y += lowlevel_init.o +--- /dev/null ++++ b/arch/arm/mach-mediatek/mt7988/init.c +@@ -0,0 +1,63 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2022 MediaTek Inc. ++ * Author: Sam Shih ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++#define SZ_8G _AC(0x200000000, ULL) ++ ++int dram_init(void) ++{ ++ int ret; ++ ++ ret = fdtdec_setup_mem_size_base(); ++ if (ret) ++ return ret; ++ ++ gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_8G); ++ ++ return 0; ++} ++ ++int dram_init_banksize(void) ++{ ++ gd->bd->bi_dram[0].start = gd->ram_base; ++ gd->bd->bi_dram[0].size = gd->ram_size; ++ ++ return 0; ++} ++ ++void reset_cpu(ulong addr) ++{ ++ psci_system_reset(); ++} ++ ++static struct mm_region mt7988_mem_map[] = { ++ { ++ /* DDR */ ++ .virt = 0x40000000UL, ++ .phys = 0x40000000UL, ++ .size = 0x200000000ULL, ++ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, ++ }, { ++ .virt = 0x00000000UL, ++ .phys = 0x00000000UL, ++ .size = 0x40000000UL, ++ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | ++ PTE_BLOCK_NON_SHARE | ++ PTE_BLOCK_PXN | PTE_BLOCK_UXN ++ }, { ++ 0, ++ } ++}; ++ ++struct mm_region *mem_map = mt7988_mem_map; +--- /dev/null ++++ b/arch/arm/mach-mediatek/mt7988/lowlevel_init.S +@@ -0,0 +1,30 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2020 MediaTek Inc. ++ * Author: Sam Shih ++ */ ++ ++/* ++ * Switch from AArch64 EL2 to AArch32 EL2 ++ * @param inputs: ++ * x0: argument, zero ++ * x1: machine nr ++ * x2: fdt address ++ * x3: input argument ++ * x4: kernel entry point ++ * @param outputs for secure firmware: ++ * x0: function id ++ * x1: kernel entry point ++ * x2: machine nr ++ * x3: fdt address ++*/ ++ ++.global armv8_el2_to_aarch32 ++armv8_el2_to_aarch32: ++ mov x3, x2 ++ mov x2, x1 ++ mov x1, x4 ++ mov x4, #0 ++ ldr x0, =0x82000200 ++ SMC #0 ++ ret diff --git a/package/boot/uboot-mediatek/patches/101-29-board-mediatek-add-MT7988-reference-boards.patch b/package/boot/uboot-mediatek/patches/101-29-board-mediatek-add-MT7988-reference-boards.patch new file mode 100644 index 00000000000..e2a7309e7e1 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/101-29-board-mediatek-add-MT7988-reference-boards.patch @@ -0,0 +1,575 @@ +From fd7d9124ffa6761f27747daeea599e0ab874c1fa Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 19 Jul 2023 17:17:54 +0800 +Subject: [PATCH 29/29] board: mediatek: add MT7988 reference boards + +This patch adds general board files based on MT7988 SoCs. + +MT7988 uses one mmc controller for booting from both SD and eMMC, +and the pins of mmc controller booting from SD are also shared with +one of spi controllers. +So two configs are need for these boot types: + +1. mt7988_rfb_defconfig - SPI-NOR, SPI-NAND and eMMC +2. mt7988_sd_rfb_defconfig - SPI-NAND and SD + +Signed-off-by: Weijie Gao +--- + arch/arm/dts/Makefile | 2 + + arch/arm/dts/mt7988-rfb.dts | 182 +++++++++++++++++++++++++++++ + arch/arm/dts/mt7988-sd-rfb.dts | 134 +++++++++++++++++++++ + board/mediatek/mt7988/MAINTAINERS | 7 ++ + board/mediatek/mt7988/Makefile | 3 + + board/mediatek/mt7988/mt7988_rfb.c | 10 ++ + configs/mt7988_rfb_defconfig | 83 +++++++++++++ + configs/mt7988_sd_rfb_defconfig | 71 +++++++++++ + include/configs/mt7988.h | 14 +++ + 9 files changed, 506 insertions(+) + create mode 100644 arch/arm/dts/mt7988-rfb.dts + create mode 100644 arch/arm/dts/mt7988-sd-rfb.dts + create mode 100644 board/mediatek/mt7988/MAINTAINERS + create mode 100644 board/mediatek/mt7988/Makefile + create mode 100644 board/mediatek/mt7988/mt7988_rfb.c + create mode 100644 configs/mt7988_rfb_defconfig + create mode 100644 configs/mt7988_sd_rfb_defconfig + create mode 100644 include/configs/mt7988.h + +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -1319,6 +1319,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ + mt7986b-sd-rfb.dtb \ + mt7986a-emmc-rfb.dtb \ + mt7986b-emmc-rfb.dtb \ ++ mt7988-rfb.dtb \ ++ mt7988-sd-rfb.dtb \ + mt8183-pumpkin.dtb \ + mt8512-bm1-emmc.dtb \ + mt8516-pumpkin.dtb \ +--- /dev/null ++++ b/arch/arm/dts/mt7988-rfb.dts +@@ -0,0 +1,182 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2022 MediaTek Inc. ++ * Author: Sam Shih ++ */ ++ ++/dts-v1/; ++#include "mt7988.dtsi" ++#include ++ ++/ { ++ model = "mt7988-rfb"; ++ compatible = "mediatek,mt7988-rfb"; ++ ++ chosen { ++ stdout-path = &uart0; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0 0x40000000 0 0x10000000>; ++ }; ++ ++ reg_3p3v: regulator-3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-3.3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ reg_1p8v: regulator-1p8v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-1.8V"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ status = "okay"; ++}; ++ ++ð { ++ status = "okay"; ++ mediatek,gmac-id = <0>; ++ phy-mode = "usxgmii"; ++ mediatek,switch = "mt7988"; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ pause; ++ }; ++}; ++ ++&pinctrl { ++ i2c1_pins: i2c1-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c1_0"; ++ }; ++ }; ++ ++ pwm_pins: pwm-pins { ++ mux { ++ function = "pwm"; ++ groups = "pwm0", "pwm1", "pwm2", "pwm3", "pwm4", ++ "pwm5", "pwm6", "pwm7"; ++ }; ++ }; ++ ++ spi0_pins: spi0-pins { ++ mux { ++ function = "spi"; ++ groups = "spi0", "spi0_wp_hold"; ++ }; ++ }; ++ ++ spi2_pins: spi2-pins { ++ mux { ++ function = "spi"; ++ groups = "spi2", "spi2_wp_hold"; ++ }; ++ }; ++ ++ mmc0_pins_default: mmc0default { ++ mux { ++ function = "flash"; ++ groups = "emmc_51"; ++ }; ++ ++ conf-cmd-dat { ++ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", ++ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", ++ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; ++ input-enable; ++ }; ++ ++ conf-clk { ++ pins = "EMMC_CK"; ++ }; ++ ++ conf-dsl { ++ pins = "EMMC_DSL"; ++ }; ++ ++ conf-rst { ++ pins = "EMMC_RSTB"; ++ }; ++ }; ++}; ++ ++&pwm { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm_pins>; ++ status = "okay"; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ must_tx; ++ enhance_timing; ++ dma_ext; ++ ipm_design; ++ support_quad; ++ tick_dly = <2>; ++ sample_sel = <0>; ++ ++ spi_nand@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <52000000>; ++ }; ++}; ++ ++&spi2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi2_pins>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ must_tx; ++ enhance_timing; ++ dma_ext; ++ ipm_design; ++ support_quad; ++ tick_dly = <2>; ++ sample_sel = <0>; ++ ++ spi_nor@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <52000000>; ++ }; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins_default>; ++ max-frequency = <52000000>; ++ bus-width = <8>; ++ cap-mmc-highspeed; ++ cap-mmc-hw-reset; ++ vmmc-supply = <®_3p3v>; ++ vqmmc-supply = <®_1p8v>; ++ non-removable; ++ status = "okay"; ++}; +--- /dev/null ++++ b/arch/arm/dts/mt7988-sd-rfb.dts +@@ -0,0 +1,134 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2022 MediaTek Inc. ++ * Author: Sam Shih ++ */ ++ ++/dts-v1/; ++#include "mt7988.dtsi" ++#include ++ ++/ { ++ model = "mt7988-rfb"; ++ compatible = "mediatek,mt7988-rfb", "mediatek,mt7988-sd-rfb"; ++ ++ chosen { ++ stdout-path = &uart0; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0 0x40000000 0 0x10000000>; ++ }; ++ ++ reg_3p3v: regulator-3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-3.3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ status = "okay"; ++}; ++ ++ð { ++ status = "okay"; ++ mediatek,gmac-id = <0>; ++ phy-mode = "usxgmii"; ++ mediatek,switch = "mt7988"; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ pause; ++ }; ++}; ++ ++&pinctrl { ++ i2c1_pins: i2c1-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c1_0"; ++ }; ++ }; ++ ++ pwm_pins: pwm-pins { ++ mux { ++ function = "pwm"; ++ groups = "pwm0", "pwm1", "pwm2", "pwm3", "pwm4", ++ "pwm5", "pwm6", "pwm7"; ++ }; ++ }; ++ ++ spi0_pins: spi0-pins { ++ mux { ++ function = "spi"; ++ groups = "spi0", "spi0_wp_hold"; ++ }; ++ }; ++ ++ mmc1_pins_default: mmc1default { ++ mux { ++ function = "flash"; ++ groups = "emmc_45"; ++ }; ++ ++ conf-cmd-dat { ++ pins = "SPI2_CSB", "SPI2_MISO", "SPI2_MOSI", ++ "SPI2_CLK", "SPI2_HOLD"; ++ input-enable; ++ }; ++ ++ conf-clk { ++ pins = "SPI2_WP"; ++ }; ++ }; ++}; ++ ++&pwm { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm_pins>; ++ status = "okay"; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ must_tx; ++ enhance_timing; ++ dma_ext; ++ ipm_design; ++ support_quad; ++ tick_dly = <2>; ++ sample_sel = <0>; ++ ++ spi_nand@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <52000000>; ++ }; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc1_pins_default>; ++ max-frequency = <52000000>; ++ bus-width = <4>; ++ cap-sd-highspeed; ++ vmmc-supply = <®_3p3v>; ++ vqmmc-supply = <®_3p3v>; ++ status = "okay"; ++}; +--- /dev/null ++++ b/board/mediatek/mt7988/MAINTAINERS +@@ -0,0 +1,7 @@ ++MT7988 ++M: Sam Shih ++S: Maintained ++F: board/mediatek/mt7988 ++F: include/configs/mt7988.h ++F: configs/mt7988_rfb_defconfig ++F: configs/mt7988_sd_rfb_defconfig +--- /dev/null ++++ b/board/mediatek/mt7988/Makefile +@@ -0,0 +1,3 @@ ++# SPDX-License-Identifier: GPL-2.0 ++ ++obj-y += mt7988_rfb.o +--- /dev/null ++++ b/board/mediatek/mt7988/mt7988_rfb.c +@@ -0,0 +1,10 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2022 MediaTek Inc. ++ * Author: Sam Shih ++ */ ++ ++int board_init(void) ++{ ++ return 0; ++} +--- /dev/null ++++ b/configs/mt7988_rfb_defconfig +@@ -0,0 +1,83 @@ ++CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="mt7988-rfb" ++CONFIG_SYS_PROMPT="MT7988> " ++CONFIG_TARGET_MT7988=y ++CONFIG_DEBUG_UART_BASE=0x11000000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_DEBUG_UART=y ++# CONFIG_AUTOBOOT is not set ++CONFIG_DEFAULT_FDT_FILE="mt7988-rfb" ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_SYS_CBSIZE=512 ++CONFIG_SYS_PBSIZE=1049 ++# CONFIG_BOOTM_NETBSD is not set ++# CONFIG_BOOTM_PLAN9 is not set ++# CONFIG_BOOTM_RTEMS is not set ++# CONFIG_BOOTM_VXWORKS is not set ++# CONFIG_CMD_ELF is not set ++CONFIG_CMD_CLK=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_SMC=y ++CONFIG_DOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++CONFIG_PARTITION_TYPE_GUID=y ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_NETMASK=y ++CONFIG_NETMASK="255.255.255.0" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.2" ++CONFIG_PROT_TCP=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_SFDP_SUPPORT=y ++CONFIG_SPI_FLASH_EON=y ++CONFIG_SPI_FLASH_GIGADEVICE=y ++CONFIG_SPI_FLASH_ISSI=y ++CONFIG_SPI_FLASH_MACRONIX=y ++CONFIG_SPI_FLASH_SPANSION=y ++CONFIG_SPI_FLASH_STMICRO=y ++CONFIG_SPI_FLASH_WINBOND=y ++CONFIG_SPI_FLASH_XMC=y ++CONFIG_SPI_FLASH_XTX=y ++CONFIG_SPI_FLASH_MTD=y ++CONFIG_PHY_FIXED=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7988=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPIM=y ++CONFIG_LZO=y ++CONFIG_HEXDUMP=y ++# CONFIG_EFI_LOADER is not set +--- /dev/null ++++ b/configs/mt7988_sd_rfb_defconfig +@@ -0,0 +1,71 @@ ++CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="mt7988-sd-rfb" ++CONFIG_SYS_PROMPT="MT7988> " ++CONFIG_TARGET_MT7988=y ++CONFIG_DEBUG_UART_BASE=0x11000000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_DEBUG_UART=y ++# CONFIG_AUTOBOOT is not set ++CONFIG_DEFAULT_FDT_FILE="mt7988-sd-rfb" ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_SYS_CBSIZE=512 ++CONFIG_SYS_PBSIZE=1049 ++# CONFIG_BOOTM_NETBSD is not set ++# CONFIG_BOOTM_PLAN9 is not set ++# CONFIG_BOOTM_RTEMS is not set ++# CONFIG_BOOTM_VXWORKS is not set ++# CONFIG_CMD_ELF is not set ++CONFIG_CMD_CLK=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_SMC=y ++CONFIG_DOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++CONFIG_PARTITION_TYPE_GUID=y ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_NETMASK=y ++CONFIG_NETMASK="255.255.255.0" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.2" ++CONFIG_PROT_TCP=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_PHY_FIXED=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7988=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPIM=y ++CONFIG_LZO=y ++CONFIG_HEXDUMP=y ++# CONFIG_EFI_LOADER is not set +--- /dev/null ++++ b/include/configs/mt7988.h +@@ -0,0 +1,14 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Configuration for MediaTek MT7988 SoC ++ * ++ * Copyright (C) 2022 MediaTek Inc. ++ * Author: Sam Shih ++ */ ++ ++#ifndef __MT7988_H ++#define __MT7988_H ++ ++#define CFG_MAX_MEM_MAPPED 0xC0000000 ++ ++#endif diff --git a/package/boot/uboot-mediatek/patches/103-mt7988-enable-pstore.patch b/package/boot/uboot-mediatek/patches/103-mt7988-enable-pstore.patch new file mode 100644 index 00000000000..a34dcddd71b --- /dev/null +++ b/package/boot/uboot-mediatek/patches/103-mt7988-enable-pstore.patch @@ -0,0 +1,33 @@ +--- a/arch/arm/dts/mt7988.dtsi ++++ b/arch/arm/dts/mt7988.dtsi +@@ -61,6 +61,30 @@ + #clock-cells = <0>; + }; + ++ psci { ++ compatible = "arm,psci-0.2"; ++ method = "smc"; ++ }; ++ ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ /* 64 KiB reserved for ramoops/pstore */ ++ ramoops@42ff0000 { ++ compatible = "ramoops"; ++ reg = <0 0x42ff0000 0 0x10000>; ++ record-size = <0x1000>; ++ }; ++ ++ /* 320 KiB reserved for ARM Trusted Firmware (BL31+BL32) */ ++ secmon_reserved: secmon@43000000 { ++ reg = <0 0x43000000 0 0x50000>; ++ no-map; ++ }; ++ }; ++ + hwver: hwver { + compatible = "mediatek,hwver", "syscon"; + reg = <0 0x8000000 0 0x1000>; diff --git a/package/boot/uboot-mediatek/patches/110-no-kwbimage.patch b/package/boot/uboot-mediatek/patches/110-no-kwbimage.patch index 76921b757e0..2d61d6f4a7e 100644 --- a/package/boot/uboot-mediatek/patches/110-no-kwbimage.patch +++ b/package/boot/uboot-mediatek/patches/110-no-kwbimage.patch @@ -1,6 +1,6 @@ --- a/tools/Makefile +++ b/tools/Makefile -@@ -115,7 +115,6 @@ dumpimage-mkimage-objs := aisimage.o \ +@@ -116,7 +116,6 @@ dumpimage-mkimage-objs := aisimage.o \ imximage.o \ imx8image.o \ imx8mimage.o \ diff --git a/package/boot/uboot-mediatek/patches/120-use-xz-instead-of-lzma.patch b/package/boot/uboot-mediatek/patches/120-use-xz-instead-of-lzma.patch index 7fda30a756b..411f99467b7 100644 --- a/package/boot/uboot-mediatek/patches/120-use-xz-instead-of-lzma.patch +++ b/package/boot/uboot-mediatek/patches/120-use-xz-instead-of-lzma.patch @@ -1,6 +1,6 @@ --- a/Makefile +++ b/Makefile -@@ -1067,7 +1067,7 @@ quiet_cmd_pad_cat = CAT $@ +@@ -1070,7 +1070,7 @@ quiet_cmd_pad_cat = CAT $@ cmd_pad_cat = $(cmd_objcopy) && $(append) || { rm -f $@; false; } quiet_cmd_lzma = LZMA $@ diff --git a/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch b/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch index fcbb6b28a06..574259fb395 100644 --- a/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch +++ b/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch @@ -122,7 +122,7 @@ int arch, int ph_type, int bootstage_id, --- a/include/image.h +++ b/include/image.h -@@ -1046,6 +1046,7 @@ int fit_parse_subimage(const char *spec, +@@ -1047,6 +1047,7 @@ int fit_parse_subimage(const char *spec, ulong *addr, const char **image_name); int fit_get_subimage_count(const void *fit, int images_noffset); diff --git a/package/boot/uboot-mediatek/patches/212-cmd-bootmenu-hack-restore-ansi.patch b/package/boot/uboot-mediatek/patches/212-cmd-bootmenu-hack-restore-ansi.patch deleted file mode 100644 index cdb1477d423..00000000000 --- a/package/boot/uboot-mediatek/patches/212-cmd-bootmenu-hack-restore-ansi.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/common/menu.c -+++ b/common/menu.c -@@ -15,7 +15,7 @@ - - #include "menu.h" - --#define ansi 0 -+#define ansi 1 - - /* - * Internally, each item in a menu is represented by a struct menu_item. diff --git a/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch b/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch index 37956727b26..d91b9904cbd 100644 --- a/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch +++ b/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch @@ -1,6 +1,6 @@ --- a/cmd/Kconfig +++ b/cmd/Kconfig -@@ -601,6 +601,12 @@ config CMD_ENV_EXISTS +@@ -602,6 +602,12 @@ config CMD_ENV_EXISTS Check if a variable is defined in the environment for use in shell scripting. @@ -76,7 +76,7 @@ #if defined(CONFIG_CMD_ENV_CALLBACK) static int print_static_binding(const char *var_name, const char *callback_name, void *priv) -@@ -1231,6 +1285,9 @@ static struct cmd_tbl cmd_env_sub[] = { +@@ -1228,6 +1282,9 @@ static struct cmd_tbl cmd_env_sub[] = { U_BOOT_CMD_MKENT(load, 1, 0, do_env_load, "", ""), #endif U_BOOT_CMD_MKENT(print, CONFIG_SYS_MAXARGS, 1, do_env_print, "", ""), @@ -86,7 +86,7 @@ #if defined(CONFIG_CMD_RUN) U_BOOT_CMD_MKENT(run, CONFIG_SYS_MAXARGS, 1, do_run, "", ""), #endif -@@ -1322,6 +1379,9 @@ static char env_help_text[] = +@@ -1319,6 +1376,9 @@ static char env_help_text[] = #if defined(CONFIG_CMD_NVEDIT_EFI) "env print -e [-guid guid] [-n] [name ...] - print UEFI environment\n" #endif @@ -96,7 +96,7 @@ #if defined(CONFIG_CMD_RUN) "env run var [...] - run commands in an environment variable\n" #endif -@@ -1431,6 +1491,17 @@ U_BOOT_CMD( +@@ -1428,6 +1488,17 @@ U_BOOT_CMD( ); #endif diff --git a/package/boot/uboot-mediatek/patches/280-image-fdt-save-name-of-FIT-configuration-in-chosen-node.patch b/package/boot/uboot-mediatek/patches/280-image-fdt-save-name-of-FIT-configuration-in-chosen-node.patch index 873d80f6f9d..f087bec72a6 100644 --- a/package/boot/uboot-mediatek/patches/280-image-fdt-save-name-of-FIT-configuration-in-chosen-node.patch +++ b/package/boot/uboot-mediatek/patches/280-image-fdt-save-name-of-FIT-configuration-in-chosen-node.patch @@ -16,7 +16,7 @@ Reviewed-by: Tom Rini --- a/boot/image-fdt.c +++ b/boot/image-fdt.c -@@ -636,6 +636,12 @@ int image_setup_libfdt(struct bootm_head +@@ -637,6 +637,12 @@ int image_setup_libfdt(struct bootm_head images->fit_uname_cfg, strlen(images->fit_uname_cfg) + 1, 1); diff --git a/package/boot/uboot-mediatek/patches/300-force-pylibfdt-build.patch b/package/boot/uboot-mediatek/patches/300-force-pylibfdt-build.patch index d34ed6f2ae5..89cdf60f950 100644 --- a/package/boot/uboot-mediatek/patches/300-force-pylibfdt-build.patch +++ b/package/boot/uboot-mediatek/patches/300-force-pylibfdt-build.patch @@ -1,6 +1,6 @@ --- a/Makefile +++ b/Makefile -@@ -2000,26 +2000,7 @@ endif +@@ -2006,26 +2006,7 @@ endif # Check dtc and pylibfdt, if DTC is provided, else build them PHONY += scripts_dtc scripts_dtc: scripts_basic diff --git a/package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch b/package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch index 1862a9344ad..65990156c22 100644 --- a/package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch +++ b/package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch @@ -17,7 +17,7 @@ #include #include -@@ -25,7 +32,22 @@ int board_init(void) +@@ -24,7 +31,22 @@ int board_init(void) int board_late_init(void) { @@ -43,7 +43,7 @@ } --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig -@@ -140,4 +140,11 @@ config MTK_BROM_HEADER_INFO +@@ -151,4 +151,11 @@ config MTK_BROM_HEADER_INFO source "board/mediatek/mt7629/Kconfig" diff --git a/package/boot/uboot-mediatek/patches/305-mt7988-generic-reset-button-ignore-env.patch b/package/boot/uboot-mediatek/patches/305-mt7988-generic-reset-button-ignore-env.patch new file mode 100644 index 00000000000..2bbc5c1005f --- /dev/null +++ b/package/boot/uboot-mediatek/patches/305-mt7988-generic-reset-button-ignore-env.patch @@ -0,0 +1,46 @@ +--- a/board/mediatek/mt7988/mt7988_rfb.c ++++ b/board/mediatek/mt7988/mt7988_rfb.c +@@ -4,7 +4,43 @@ + * Author: Sam Shih + */ + ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifndef CONFIG_RESET_BUTTON_LABEL ++#define CONFIG_RESET_BUTTON_LABEL "reset" ++#endif ++ + int board_init(void) + { + return 0; + } ++ ++int board_late_init(void) ++{ ++ gd->env_valid = 1; //to load environment variable from persistent store ++ struct udevice *dev; ++ ++ gd->env_valid = ENV_VALID; ++ if (!button_get_by_label(CONFIG_RESET_BUTTON_LABEL, &dev)) { ++ puts("reset button found\n"); ++#ifdef CONFIG_RESET_BUTTON_SETTLE_DELAY ++ if (CONFIG_RESET_BUTTON_SETTLE_DELAY > 0) { ++ button_get_state(dev); ++ mdelay(CONFIG_RESET_BUTTON_SETTLE_DELAY); ++ } ++#endif ++ if (button_get_state(dev) == BUTTON_ON) { ++ puts("button pushed, resetting environment\n"); ++ gd->env_valid = ENV_INVALID; ++ } ++ } ++ env_relocate(); ++ return 0; ++} diff --git a/package/boot/uboot-mediatek/patches/403-add-bananapi_bpi-r64-snand.patch b/package/boot/uboot-mediatek/patches/403-add-bananapi_bpi-r64-snand.patch index a414f0a8b5c..c9da03c7254 100644 --- a/package/boot/uboot-mediatek/patches/403-add-bananapi_bpi-r64-snand.patch +++ b/package/boot/uboot-mediatek/patches/403-add-bananapi_bpi-r64-snand.patch @@ -20,14 +20,14 @@ +&snand { + pinctrl-names = "default"; + pinctrl-0 = <&snfi_pins>; ++ quad-spi; status = "okay"; - - spi-flash@0{ - compatible = "jedec,spi-nor"; - reg = <0>; -- u-boot,dm-pre-reloc; +- bootph-all; - }; -+ quad-spi; }; &uart0 { diff --git a/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch b/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch index 3fc2c554bb0..363509efc1b 100644 --- a/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch +++ b/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch @@ -323,12 +323,12 @@ +ð { + status = "okay"; + mediatek,gmac-id = <0>; -+ phy-mode = "sgmii"; ++ phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; + reset-gpios = <&gpio 54 GPIO_ACTIVE_HIGH>; + + fixed-link { -+ speed = <1000>; ++ speed = <2500>; + full-duplex; + }; +}; @@ -344,7 +344,7 @@ +}; --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -1285,6 +1285,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ +@@ -1305,6 +1305,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7622-rfb.dtb \ mt7623a-unielec-u7623-02-emmc.dtb \ mt7622-bananapi-bpi-r64.dtb \ diff --git a/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch b/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch index 1955958b9b0..b495f48d668 100644 --- a/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch +++ b/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch @@ -320,11 +320,11 @@ + pinctrl-0 = <ð_pins>; + + mediatek,gmac-id = <0>; -+ phy-mode = "sgmii"; ++ phy-mode = "2500base-x"; + phy-handle = <&gphy>; + + fixed-link { -+ speed = <1000>; ++ speed = <2500>; + full-duplex; + }; + @@ -341,7 +341,7 @@ +}; --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -1286,6 +1286,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ +@@ -1306,6 +1306,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7623a-unielec-u7623-02-emmc.dtb \ mt7622-bananapi-bpi-r64.dtb \ mt7622-linksys-e8450-ubi.dtb \ @@ -433,7 +433,7 @@ #ifdef CONFIG_MMC static int initr_mmc(void) { -@@ -720,6 +735,9 @@ static init_fnc_t init_sequence_r[] = { +@@ -713,6 +728,9 @@ static init_fnc_t init_sequence_r[] = { #ifdef CONFIG_NMBM_MTD initr_nmbm, #endif diff --git a/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch b/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch index 62d5b84ac3f..c11c42fd8f3 100644 --- a/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch +++ b/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch @@ -1,14 +1,3 @@ ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -1293,6 +1293,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ - mt7981-snfi-nand-rfb.dtb \ - mt7981-emmc-rfb.dtb \ - mt7981-sd-rfb.dtb \ -+ mt7986a-bpi-r3-sd.dtb \ -+ mt7986a-bpi-r3-emmc.dtb \ - mt7986a-rfb.dtb \ - mt7986b-rfb.dtb \ - mt7986a-sd-rfb.dtb \ --- /dev/null +++ b/configs/mt7986a_bpi-r3-emmc_defconfig @@ -0,0 +1,196 @@ @@ -806,317 +795,6 @@ +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.254" --- /dev/null -+++ b/arch/arm/dts/mt7986a-bpi-r3-emmc.dts -@@ -0,0 +1,33 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2021 MediaTek Inc. -+ * Author: Sam Shih -+ */ -+ -+/dts-v1/; -+#include "mt7986a-bpi-r3-sd.dts" -+#include -+/ { -+ reg_1p8v: regulator-1p8v { -+ compatible = "regulator-fixed"; -+ regulator-name = "fixed-1.8V"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+}; -+ -+&mmc0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc0_pins_default>; -+ bus-width = <8>; -+ max-frequency = <200000000>; -+ cap-mmc-highspeed; -+ cap-mmc-hw-reset; -+ vmmc-supply = <®_3p3v>; -+ vqmmc-supply = <®_1p8v>; -+ non-removable; -+ status = "okay"; -+}; -+ ---- /dev/null -+++ b/arch/arm/dts/mt7986a-bpi-r3-sd.dts -@@ -0,0 +1,272 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2021 MediaTek Inc. -+ * Author: Sam Shih -+ */ -+ -+/dts-v1/; -+#include -+#include "mt7986.dtsi" -+#include -+ -+/ { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ model = "BananaPi BPi-R3"; -+ compatible = "mediatek,mt7986", "mediatek,mt7986-sd-rfb"; -+ -+ chosen { -+ stdout-path = &uart0; -+ tick-timer = &timer0; -+ }; -+ -+ reg_3p3v: regulator-3p3v { -+ compatible = "regulator-fixed"; -+ regulator-name = "fixed-3.3V"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ keys { -+ compatible = "gpio-keys"; -+/* -+ factory { -+ label = "reset"; -+ gpios = <&gpio 9 GPIO_ACTIVE_LOW>; -+ }; -+*/ -+ wps { -+ label = "reset"; -+ gpios = <&gpio 10 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ }; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ led_status_green: green { -+ label = "green:status"; -+ gpios = <&gpio 69 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ led_status_blue: blue { -+ label = "blue:status"; -+ gpios = <&gpio 86 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+ -+}; -+ -+&uart0 { -+ mediatek,force-highspeed; -+ status = "okay"; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>; -+ status = "disabled"; -+}; -+ -+ð { -+ status = "okay"; -+ mediatek,gmac-id = <0>; -+ phy-mode = "sgmii"; -+ mediatek,switch = "mt7531"; -+ reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; -+ -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+}; -+ -+&pinctrl { -+ spic_pins: spi1-pins-func-1 { -+ mux { -+ function = "spi"; -+ groups = "spi1_2"; -+ }; -+ }; -+ -+ uart1_pins: spi1-pins-func-3 { -+ mux { -+ function = "uart"; -+ groups = "uart1_2"; -+ }; -+ }; -+ -+ pwm_pins: pwm0-pins-func-1 { -+ mux { -+ function = "pwm"; -+ groups = "pwm0"; -+ }; -+ }; -+ -+ mmc0_pins_default: mmc0default { -+ mux { -+ function = "flash"; -+ groups = "emmc_51"; -+ }; -+ -+ conf-cmd-dat { -+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", -+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", -+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; -+ input-enable; -+ drive-strength = ; -+ bias-pull-up = ; -+ }; -+ -+ conf-clk { -+ pins = "EMMC_CK"; -+ drive-strength = ; -+ bias-pull-down = ; -+ }; -+ -+ conf-dsl { -+ pins = "EMMC_DSL"; -+ bias-pull-down = ; -+ }; -+ -+ conf-rst { -+ pins = "EMMC_RSTB"; -+ drive-strength = ; -+ bias-pull-up = ; -+ }; -+ }; -+ -+ spi_flash_pins: spi0-pins-func-1 { -+ mux { -+ function = "flash"; -+ groups = "spi0", "spi0_wp_hold"; -+ }; -+ -+ conf-pu { -+ pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; -+ drive-strength = ; -+ bias-pull-up = ; -+ }; -+ -+ conf-pd { -+ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; -+ drive-strength = ; -+ bias-pull-down = ; -+ }; -+ }; -+}; -+ -+&pwm { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pwm_pins>; -+ status = "okay"; -+}; -+ -+&spi0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi_flash_pins>; -+ status = "okay"; -+ must_tx; -+ enhance_timing; -+ dma_ext; -+ ipm_design; -+ support_quad; -+ tick_dly = <1>; -+ sample_sel = <0>; -+ -+ spi_nor@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <52000000>; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "bl2"; -+ reg = <0x0 0x40000>; -+ }; -+ -+ partition@40000 { -+ label = "u-boot-env"; -+ reg = <0x40000 0x40000>; -+ }; -+ -+ partition@80000 { -+ label = "reserved"; -+ reg = <0x80000 0x80000>; -+ }; -+ -+ partition@100000 { -+ label = "fip"; -+ reg = <0x100000 0x80000>; -+ }; -+ -+ partition@180000 { -+ label = "recovery"; -+ reg = <0x180000 0xa80000>; -+ }; -+ -+ partition@c00000 { -+ label = "fit"; -+ reg = <0xc00000 0x1400000>; -+ }; -+ }; -+ }; -+ -+ spi_nand@1 { -+ compatible = "spi-nand"; -+ reg = <1>; -+ spi-max-frequency = <52000000>; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "bl2"; -+ reg = <0x0 0x80000>; -+ }; -+ -+ partition@80000 { -+ label = "factory"; -+ reg = <0x80000 0x300000>; -+ }; -+ -+ partition@380000 { -+ label = "fip"; -+ reg = <0x380000 0x200000>; -+ }; -+ -+ partition@580000 { -+ label = "ubi"; -+ reg = <0x580000 0x7a80000>; -+ }; -+ }; -+ }; -+}; -+ -+&watchdog { -+ status = "disabled"; -+}; -+ -+&mmc0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc0_pins_default>; -+ bus-width = <4>; -+ max-frequency = <52000000>; -+ cap-sd-highspeed; -+ r_smpl = <1>; -+ vmmc-supply = <®_3p3v>; -+ vqmmc-supply = <®_3p3v>; -+ status = "okay"; -+}; -+ ---- /dev/null +++ b/bananapi_bpi-r3_sdmmc_env @@ -0,0 +1,80 @@ +ipaddr=192.168.1.1 diff --git a/package/boot/uboot-mediatek/patches/432-add-tplink-xdr608x.patch b/package/boot/uboot-mediatek/patches/432-add-tplink-xdr608x.patch index 4e876fe20fd..b1c25ba7915 100644 --- a/package/boot/uboot-mediatek/patches/432-add-tplink-xdr608x.patch +++ b/package/boot/uboot-mediatek/patches/432-add-tplink-xdr608x.patch @@ -634,12 +634,12 @@ +ð { + status = "okay"; + mediatek,gmac-id = <0>; -+ phy-mode = "sgmii"; ++ phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; + reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; + + fixed-link { -+ speed = <1000>; ++ speed = <2500>; + full-duplex; + }; +}; diff --git a/package/boot/uboot-mediatek/patches/433-add-qihoo_360t7.patch b/package/boot/uboot-mediatek/patches/433-add-qihoo_360t7.patch index 2be7e18c6ec..aaaeaa4f8ae 100644 --- a/package/boot/uboot-mediatek/patches/433-add-qihoo_360t7.patch +++ b/package/boot/uboot-mediatek/patches/433-add-qihoo_360t7.patch @@ -246,12 +246,12 @@ +ð { + status = "okay"; + mediatek,gmac-id = <0>; -+ phy-mode = "sgmii"; ++ phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; + reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; + + fixed-link { -+ speed = <1000>; ++ speed = <2500>; + full-duplex; + }; +}; diff --git a/package/boot/uboot-mediatek/patches/434-add-xiaomi_mi-router-wr30u.patch b/package/boot/uboot-mediatek/patches/434-add-xiaomi_mi-router-wr30u.patch new file mode 100644 index 00000000000..6be64e54216 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/434-add-xiaomi_mi-router-wr30u.patch @@ -0,0 +1,456 @@ +--- /dev/null ++++ b/configs/mt7981_xiaomi_mi-router-wr30u_defconfig +@@ -0,0 +1,175 @@ ++CONFIG_ARM=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TARGET_MT7981=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="mt7981_xiaomi_mi-router-wr30u" ++CONFIG_DEFAULT_ENV_FILE="xiaomi_mi-router-wr30u_env" ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7981_xiaomi_mi-router-wr30u.dtb" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_SYS_PROMPT="MT7981> " ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_PCI=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_CMD_UBIFS=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_NETCONSOLE=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_SCSI=y ++CONFIG_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_SCSI_AHCI=y ++CONFIG_SCSI=y ++CONFIG_CMD_SCSI=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_PHY_FIXED=y ++CONFIG_MTK_AHCI=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PCI=y ++# CONFIG_MMC is not set ++# CONFIG_DM_MMC is not set ++CONFIG_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y ++CONFIG_DM_PCI=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7622=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_SIZE=0x1f000 ++CONFIG_ENV_SIZE_REDUND=0x1f000 ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_PHY_FIXED=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7981=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_HEXDUMP=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTK_SPIM=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_NAND=y ++CONFIG_CMD_NAND_TRIMFFS=y ++CONFIG_LMB_MAX_REGIONS=64 ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +--- /dev/null ++++ b/arch/arm/dts/mt7981_xiaomi_mi-router-wr30u.dts +@@ -0,0 +1,216 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2022 MediaTek Inc. ++ * Author: Sam Shih ++ */ ++ ++/dts-v1/; ++#include "mt7981.dtsi" ++#include ++#include ++ ++/ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "Xiaomi Router WR30U"; ++ compatible = "mediatek,mt7981", "mediatek,mt7981-rfb"; ++ ++ chosen { ++ stdout-path = &uart0; ++ tick-timer = &timer0; ++ }; ++ ++ config { ++ blink_led = "yellow:network"; ++ system_led = "yellow:system"; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ ++ reset { ++ label = "reset"; ++ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ linux,code = ; ++ }; ++ ++ mesh { ++ label = "mesh"; ++ gpios = <&gpio 0 GPIO_ACTIVE_LOW>; ++ linux,code = ; ++ linux,input-type = ; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led_system_blue { ++ label = "blue:system"; ++ gpios = <&gpio 9 GPIO_ACTIVE_LOW>; ++ }; ++ ++ led_system_yellow { ++ label = "yellow:system"; ++ gpios = <&gpio 10 GPIO_ACTIVE_LOW>; ++ }; ++ ++ led_network_blue { ++ label = "blue:network"; ++ gpios = <&gpio 11 GPIO_ACTIVE_LOW>; ++ }; ++ ++ led_network_yellow { ++ label = "yellow:network"; ++ gpios = <&gpio 12 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&uart0 { ++ mediatek,force-highspeed; ++ status = "okay"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++ status = "disabled"; ++}; ++ ++ð { ++ status = "okay"; ++ mediatek,gmac-id = <0>; ++ phy-mode = "sgmii"; ++ mediatek,switch = "mt7531"; ++ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++}; ++ ++&pinctrl { ++ spi_flash_pins: spi0-pins-func-1 { ++ mux { ++ function = "flash"; ++ groups = "spi0", "spi0_wp_hold"; ++ }; ++ ++ conf-pu { ++ pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; ++ drive-strength = ; ++ bias-pull-up = ; ++ }; ++ ++ conf-pd { ++ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; ++ drive-strength = ; ++ bias-pull-down = ; ++ }; ++ }; ++ ++ spic_pins: spi1-pins-func-1 { ++ mux { ++ function = "spi"; ++ groups = "spi1_1"; ++ }; ++ }; ++ ++ uart1_pins: spi1-pins-func-3 { ++ mux { ++ function = "uart"; ++ groups = "uart1_2"; ++ }; ++ }; ++ ++ pwm_pins: pwm0-pins-func-1 { ++ mux { ++ function = "pwm"; ++ groups = "pwm0_1", "pwm1_0"; ++ }; ++ }; ++}; ++ ++&pwm { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm_pins>; ++ status = "okay"; ++}; ++ ++&spi0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi_flash_pins>; ++ status = "okay"; ++ must_tx; ++ enhance_timing; ++ dma_ext; ++ ipm_design; ++ support_quad; ++ tick_dly = <2>; ++ sample_sel = <0>; ++ ++ spi_nand@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <52000000>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "bl2"; ++ reg = <0x00 0x100000>; ++ }; ++ ++ partition@100000 { ++ label = "Nvram"; ++ reg = <0x100000 0x40000>; ++ }; ++ ++ partition@140000 { ++ label = "Bdata"; ++ reg = <0x140000 0x40000>; ++ }; ++ ++ partition@180000 { ++ label = "factory"; ++ reg = <0x180000 0x200000>; ++ }; ++ ++ partition@380000 { ++ label = "fip"; ++ reg = <0x380000 0x200000>; ++ }; ++ ++ partition@580000 { ++ label = "crash"; ++ reg = <0x580000 0x40000>; ++ }; ++ ++ partition@5c0000 { ++ label = "crash_log"; ++ reg = <0x5c0000 0x40000>; ++ }; ++ ++ partition@600000 { ++ label = "ubi"; ++ reg = <0x600000 0x7000000>; ++ }; ++ ++ partition@7600000 { ++ label = "KF"; ++ reg = <0x7600000 0x40000>; ++ }; ++ }; ++ }; ++}; ++ ++&watchdog { ++ status = "disabled"; ++}; +--- /dev/null ++++ b/xiaomi_mi-router-wr30u_env +@@ -0,0 +1,56 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x46000000 ++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0 ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi ++bootconf=config-1 ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-xiaomi_mi-router-wr30u-ubootmod-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-filogic-xiaomi_mi-router-wr30u-ubootmod-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-xiaomi_mi-router-wr30u-ubootmod-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-filogic-xiaomi_mi-router-wr30u-ubootmod-squashfs-sysupgrade.itb ++bootled_pwr=yellow:system ++bootled_rec=yellow:network ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= ( ( ( OpenWrt ) ) ) ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=Load BL31+U-Boot FIP via TFTP then write to NAND.=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=Load BL2 preloader via TFTP then write to NAND.=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_8=Reboot.=reset ++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off ++boot_recovery=led $bootled_rec on ; run ubi_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off ++boot_ubi=run boot_production ; run boot_recovery ; run boot_tftp_forever ++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run mtd_write_fip && run reset_factory ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run mtd_write_bl2 ++part_default=production ++part_recovery=recovery ++reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 ++mtd_write_fip=mtd erase fip && mtd write fip $loadaddr ++mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 0 || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 1 || run ubi_format ++ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset ++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi ++ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs ++ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery ++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize ++_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title $ver" diff --git a/package/boot/uboot-mediatek/patches/435-add-h3c_magic-nx30-pro.patch b/package/boot/uboot-mediatek/patches/435-add-h3c_magic-nx30-pro.patch index e7d1ce764cb..57181c73c0e 100644 --- a/package/boot/uboot-mediatek/patches/435-add-h3c_magic-nx30-pro.patch +++ b/package/boot/uboot-mediatek/patches/435-add-h3c_magic-nx30-pro.patch @@ -246,12 +246,12 @@ +ð { + status = "okay"; + mediatek,gmac-id = <0>; -+ phy-mode = "sgmii"; ++ phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; + reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; + + fixed-link { -+ speed = <1000>; ++ speed = <2500>; + full-duplex; + }; +}; diff --git a/package/boot/uboot-mvebu/Makefile b/package/boot/uboot-mvebu/Makefile index e3f1582f23f..e6120959f64 100644 --- a/package/boot/uboot-mvebu/Makefile +++ b/package/boot/uboot-mvebu/Makefile @@ -8,10 +8,10 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk -PKG_VERSION:=2023.01 +PKG_VERSION:=2023.07.02 PKG_RELEASE:=1 -PKG_HASH:=69423bad380f89a0916636e89e6dcbd2e4512d584308d922d1039d1e4331950f +PKG_HASH:=6b6a48581c14abb0f95bd87c1af4d740922406d7b801002a9f94727fdde021d5 include $(INCLUDE_DIR)/u-boot.mk include $(INCLUDE_DIR)/package.mk diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index 983edcb2409..2d44c218f24 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -74,6 +74,13 @@ define U-Boot/rk3399/Default ATF:=rk3399_bl31.elf endef +define U-Boot/nanopc-t4-rk3399 + $(U-Boot/rk3399/Default) + NAME:=NanoPC T4 + BUILD_DEVICES:= \ + friendlyarm_nanopc-t4 +endef + define U-Boot/nanopi-r4s-rk3399 $(U-Boot/rk3399/Default) NAME:=NanoPi R4S @@ -96,6 +103,7 @@ define U-Boot/rockpro64-rk3399 endef UBOOT_TARGETS := \ + nanopc-t4-rk3399 \ nanopi-r4s-rk3399 \ rock-pi-4-rk3399 \ rockpro64-rk3399 \ diff --git a/package/boot/uboot-rockchip/patches/105-nanopc-t4-fix-memory-unstability.patch b/package/boot/uboot-rockchip/patches/105-nanopc-t4-fix-memory-unstability.patch new file mode 100644 index 00000000000..7d2161ae422 --- /dev/null +++ b/package/boot/uboot-rockchip/patches/105-nanopc-t4-fix-memory-unstability.patch @@ -0,0 +1,24 @@ +From 445502bc21ecf1b5120faee785cea578b810c759 Mon Sep 17 00:00:00 2001 +From: Lu jicong +Date: Wed, 5 Jul 2023 17:13:55 +0800 +Subject: [PATCH] rockchip: rk3399: nanopc-t4: use 1600MHz sdram config + +Current 1866MHz sdram config is too high for NanoPC-T4. +On this frequency, its lpddr3 sdram becomes unstable, +causing memtest failures and random kernel crashes. + +Signed-off-by: Lu jicong +--- + arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi b/arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi +index 17201bcf41..8b6c9059ab 100644 +--- a/arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi ++++ b/arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi +@@ -4,4 +4,4 @@ + */ + + #include "rk3399-nanopi4-u-boot.dtsi" +-#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi" ++#include "rk3399-sdram-lpddr3-4GB-1600.dtsi" diff --git a/package/devel/strace/Makefile b/package/devel/strace/Makefile index 9400608cddf..e572cc0315d 100644 --- a/package/devel/strace/Makefile +++ b/package/devel/strace/Makefile @@ -9,12 +9,12 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk PKG_NAME:=strace -PKG_VERSION:=6.3 +PKG_VERSION:=6.4 PKG_RELEASE:=1 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz PKG_SOURCE_URL:=https://strace.io/files/$(PKG_VERSION) -PKG_HASH:=e17878e301506c1cc301611118ad14efee7f8bcef63b27ace5d290acce7bb731 +PKG_HASH:=27987dbac57fdfd260c6db4dc8328df35c95c6867c8a3d4371d59cdcf4eb9238 PKG_MAINTAINER:=Felix Fietkau PKG_LICENSE:=LGPL-2.1-or-later diff --git a/package/firmware/linux-firmware/broadcom.mk b/package/firmware/linux-firmware/broadcom.mk index 48d986e2183..4f64b423eb8 100644 --- a/package/firmware/linux-firmware/broadcom.mk +++ b/package/firmware/linux-firmware/broadcom.mk @@ -149,6 +149,18 @@ define Package/brcmfmac-nvram-43455-sdio/install endef $(eval $(call BuildPackage,brcmfmac-nvram-43455-sdio)) +Package/brcmfmac-nvram-4356-sdio = $(call Package/firmware-default,Broadcom BCM4356 SDIO NVRAM) +define Package/brcmfmac-nvram-4356-sdio/install + $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/brcm/brcmfmac4356-sdio.AP6356S.txt \ + $(1)/lib/firmware/brcm/ + $(LN) \ + brcmfmac4356-sdio.AP6356S.txt \ + $(1)/lib/firmware/brcm/brcmfmac4356-sdio.friendlyarm,nanopc-t4.txt +endef +$(eval $(call BuildPackage,brcmfmac-nvram-4356-sdio)) + Package/brcmfmac-firmware-usb = $(call Package/firmware-default,Broadcom BCM43xx fullmac USB firmware) define Package/brcmfmac-firmware-usb/install $(INSTALL_DIR) $(1)/lib/firmware/brcm diff --git a/package/kernel/linux/modules/block.mk b/package/kernel/linux/modules/block.mk index bdf84e8ae29..4ee3f78f380 100644 --- a/package/kernel/linux/modules/block.mk +++ b/package/kernel/linux/modules/block.mk @@ -505,7 +505,7 @@ define KernelPackage/nvme FILES:= \ $(LINUX_DIR)/drivers/nvme/host/nvme-core.ko \ $(LINUX_DIR)/drivers/nvme/host/nvme.ko - AUTOLOAD:=$(call AutoLoad,30,nvme-core nvme) + AUTOLOAD:=$(call AutoLoad,30,nvme-core nvme,1) endef define KernelPackage/nvme/description diff --git a/package/kernel/mac80211/broadcom.mk b/package/kernel/mac80211/broadcom.mk index cf80ad2d326..13da62a6f46 100644 --- a/package/kernel/mac80211/broadcom.mk +++ b/package/kernel/mac80211/broadcom.mk @@ -431,6 +431,7 @@ define KernelPackage/brcmfmac/config bool "Enable SDIO bus interface support" default y if TARGET_bcm27xx default y if TARGET_imx_cortexa7 + default y if TARGET_rockchip default y if TARGET_sunxi default n help diff --git a/package/kernel/mac80211/patches/rt2x00/997-wifi-rt2x00-limit-MT7620-TX-power-based-on-eeprom-ca.patch b/package/kernel/mac80211/patches/rt2x00/997-wifi-rt2x00-limit-MT7620-TX-power-based-on-eeprom-ca.patch new file mode 100644 index 00000000000..fd1b3d8bf3b --- /dev/null +++ b/package/kernel/mac80211/patches/rt2x00/997-wifi-rt2x00-limit-MT7620-TX-power-based-on-eeprom-ca.patch @@ -0,0 +1,106 @@ +From: Shiji Yang +Date: Sat, 22 Jul 2023 21:56:30 +0800 +Subject: [PATCH] wifi: rt2x00: limit MT7620 TX power based on eeprom + calibration + +In the vendor driver, the current channel power is queried from +EEPROM_TXPOWER_BG1 and EEPROM_TXPOWER_BG2. And then the mixed value +will be written into the low half-word of the TX_ALC_CFG_0 register. +The high half-word of the TX_ALC_CFG_0 is a fixed value 0x2f2f. + +We can't get the accurate TX power. Based on my tests and the new +MediaTek mt76 driver source code, the real TX power is approximately +equal to channel_power + (max) rate_power. Usually max rate_power is +the gain of the OFDM 6M rate, which can be readed from the offset +EEPROM_TXPOWER_BYRATE +1. + +Based on these eeprom values, this patch adds basic TX power control +for the MT7620 and limits its maximum TX power. This can avoid the +link speed decrease caused by chip overheating. rt2800_config_alc() +function has also been renamed to rt2800_config_alc_rt6352() because +it's only used by RT6352(MT7620). + +Notice: +It's still need some work to sync the max channel power to the user +interface. This part is missing from the rt2x00 driver structure. If +we set the power exceed the calibration value, it won't take effect. + +Signed-off-by: Shiji Yang +--- + .../net/wireless/ralink/rt2x00/rt2800lib.c | 49 +++++++++++++------ + 1 file changed, 34 insertions(+), 15 deletions(-) + +--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c ++++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c +@@ -3891,28 +3891,47 @@ static void rt2800_config_channel_rf7620 + } + } + +-static void rt2800_config_alc(struct rt2x00_dev *rt2x00dev, ++static void rt2800_config_alc_rt6352(struct rt2x00_dev *rt2x00dev, + struct ieee80211_channel *chan, + int power_level) { +- u16 eeprom, target_power, max_power; ++ u16 eeprom, chan_power, rate_power, target_power; ++ u16 tx_power[2]; ++ s8 *power_group[2]; + u32 mac_sys_ctrl; +- u32 reg; ++ u32 cnt, reg; + u8 bbp; + +- /* hardware unit is 0.5dBm, limited to 23.5dBm */ +- power_level *= 2; +- if (power_level > 0x2f) +- power_level = 0x2f; +- +- max_power = chan->max_power * 2; +- if (max_power > 0x2f) +- max_power = 0x2f; ++ /* get per channel power, 2 channels in total, unit is 0.5dBm */ ++ power_level = (power_level - 3) * 2; ++ /* ++ * We can't get the accurate TX power. Based on some tests, the real ++ * TX power is approximately equal to channel_power + (max)rate_power. ++ * Usually max rate_power is the gain of the OFDM 6M rate. The antenna ++ * gain and externel PA gain are not included as we are unable to ++ * obtain these values. ++ */ ++ rate_power = rt2800_eeprom_read_from_array(rt2x00dev, ++ EEPROM_TXPOWER_BYRATE, 1) & 0x3f; ++ power_level -= rate_power; ++ if (power_level < 1) ++ power_level = 1; ++ if (power_level > chan->max_power * 2) ++ power_level = chan->max_power * 2; ++ ++ power_group[0] = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1); ++ power_group[1] = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2); ++ for (cnt = 0; cnt < 2; cnt++) { ++ chan_power = power_group[cnt][rt2x00dev->rf_channel - 1]; ++ if (chan_power >= 0x20 || chan_power == 0) ++ chan_power = 0x10; ++ tx_power[cnt] = power_level < chan_power ? power_level : chan_power; ++ } + + reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_0); +- rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, power_level); +- rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, power_level); +- rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_0, max_power); +- rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_1, max_power); ++ rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, tx_power[0]); ++ rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, tx_power[1]); ++ rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_0, 0x2f); ++ rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_1, 0x2f); + + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); + if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) { +@@ -5321,7 +5340,7 @@ static void rt2800_config_txpower_rt6352 + rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t); + rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg); + +- rt2800_config_alc(rt2x00dev, chan, power_level); ++ rt2800_config_alc_rt6352(rt2x00dev, chan, power_level); + + /* TODO: temperature compensation code! */ + } diff --git a/package/kernel/mac80211/patches/rt2x00/998-wifi-rt2x00-rework-MT7620-PA-LNA-RF-calibration.patch b/package/kernel/mac80211/patches/rt2x00/998-wifi-rt2x00-rework-MT7620-PA-LNA-RF-calibration.patch new file mode 100644 index 00000000000..7fdad639766 --- /dev/null +++ b/package/kernel/mac80211/patches/rt2x00/998-wifi-rt2x00-rework-MT7620-PA-LNA-RF-calibration.patch @@ -0,0 +1,434 @@ +From: Shiji Yang +Date: Tue, 25 Jul 2023 20:05:06 +0800 +Subject: [PATCH] wifi: rt2x00: rework MT7620 PA/LNA RF calibration + +1. Move MT7620 PA/LNA calibration code to dedicated functions. + Calibration stage 1 is executed before configuring channels and + stage 2 is executed after configuring channels. +2. For external PA/LNA devices, restore RF and BBP registers before + R-Calibration. +3. Do Rx DCOC calibration again before RXIQ calibration. +4. Correct MAC_SYS_CTRL register RX mask to 0x08 in R-Calibration + function. For MAC_SYS_CTRL register, Bit[2] controls MAC_TX_EN + and Bit[3] controls MAC_RX_EN (Bit index starts from 0). +5. Move the channel configuration code from rt2800_vco_calibration() + to the rt2800_config_channel(). +6. Use MT7620 SOC specific AGC initial LNA value instead of the + RT5592's value. +7. Adjust the register operation sequence according to the vendor + driver code. This may not be useful, but it can make things + clearer when developers try to review it. + +Signed-off-by: Shiji Yang +--- + .../net/wireless/ralink/rt2x00/rt2800lib.c | 318 +++++++++++------- + drivers/net/wireless/ralink/rt2x00/rt2x00.h | 6 + + 2 files changed, 194 insertions(+), 130 deletions(-) + +--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c ++++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c +@@ -62,6 +62,9 @@ MODULE_PARM_DESC(watchdog, "Enable watch + rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \ + H2M_MAILBOX_CSR_OWNER, (__reg)) + ++static void rt6352_init_palna_stage1(struct rt2x00_dev *rt2x00dev); ++static void rt6352_init_palna_stage2(struct rt2x00_dev *rt2x00dev); ++ + static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev) + { + /* check for rt2872 on SoC */ +@@ -3881,14 +3884,6 @@ static void rt2800_config_channel_rf7620 + rfcsr |= tx_agc_fc; + rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr); + } +- +- if (conf_is_ht40(conf)) { +- rt2800_bbp_glrt_write(rt2x00dev, 141, 0x10); +- rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2f); +- } else { +- rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1a); +- rt2800_bbp_glrt_write(rt2x00dev, 157, 0x40); +- } + } + + static void rt2800_config_alc_rt6352(struct rt2x00_dev *rt2x00dev, +@@ -4151,6 +4146,9 @@ static void rt2800_config_channel(struct + rt2800_txpower_to_dev(rt2x00dev, rf->channel, + info->default_power3); + ++ if (rt2x00_rt(rt2x00dev, RT6352)) ++ rt6352_init_palna_stage1(rt2x00dev); ++ + switch (rt2x00dev->chip.rt) { + case RT3883: + rt3883_bbp_adjust(rt2x00dev, rf); +@@ -4457,89 +4455,65 @@ static void rt2800_config_channel(struct + usleep_range(1000, 1500); + } + +- if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) { ++ if (rt2x00_rt(rt2x00dev, RT5592)) { + reg = 0x10; +- if (!conf_is_ht40(conf)) { +- if (rt2x00_rt(rt2x00dev, RT6352) && +- rt2x00_has_cap_external_lna_bg(rt2x00dev)) { +- reg |= 0x5; +- } else { +- reg |= 0xa; +- } +- } ++ if (!conf_is_ht40(conf)) ++ reg |= 0xa; + rt2800_bbp_write(rt2x00dev, 195, 141); + rt2800_bbp_write(rt2x00dev, 196, reg); + +- /* AGC init. +- * Despite the vendor driver using different values here for +- * RT6352 chip, we use 0x1c for now. This may have to be changed +- * once TSSI got implemented. +- */ + reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2*rt2x00dev->lna_gain; + rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); +- +- if (rt2x00_rt(rt2x00dev, RT5592)) +- rt2800_iq_calibrate(rt2x00dev, rf->channel); ++ ++ rt2800_iq_calibrate(rt2x00dev, rf->channel); + } + + if (rt2x00_rt(rt2x00dev, RT6352)) { +- if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, +- &rt2x00dev->cap_flags)) { +- reg = rt2800_register_read(rt2x00dev, RF_CONTROL3); +- reg |= 0x00000101; +- rt2800_register_write(rt2x00dev, RF_CONTROL3, reg); +- +- reg = rt2800_register_read(rt2x00dev, RF_BYPASS3); +- reg |= 0x00000101; +- rt2800_register_write(rt2x00dev, RF_BYPASS3, reg); +- +- rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0x73); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0x73); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0x73); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0xC8); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xA4); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x05); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xC8); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xA4); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x05); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x27); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0xC8); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xA4); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x05); +- rt2800_rfcsr_write_dccal(rt2x00dev, 05, 0x00); ++ /* BBP for GLRT BW */ ++ if (conf_is_ht40(conf)) { ++ rt2800_bbp_glrt_write(rt2x00dev, 141, 0x10); ++ rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2f); ++ } else { ++ rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1a); ++ rt2800_bbp_glrt_write(rt2x00dev, 157, 0x40); + +- rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, +- 0x36303636); +- rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, +- 0x6C6C6B6C); +- rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, +- 0x6C6C6B6C); ++ if (rt2800_hw_get_chippkg(rt2x00dev) == 1 && ++ rt2x00_has_cap_external_lna_bg(rt2x00dev)) ++ rt2800_bbp_glrt_write(rt2x00dev, 141, 0x15); + } + +- if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { +- reg = rt2800_register_read(rt2x00dev, RF_CONTROL3); +- reg |= 0x00000101; +- rt2800_register_write(rt2x00dev, RF_CONTROL3, reg); +- +- reg = rt2800_register_read(rt2x00dev, RF_BYPASS3); +- reg |= 0x00000101; +- rt2800_register_write(rt2x00dev, RF_BYPASS3, reg); +- +- rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x66); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x20); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x42); +- rt2800_bbp_write(rt2x00dev, 75, 0x68); +- rt2800_bbp_write(rt2x00dev, 76, 0x4C); +- rt2800_bbp_write(rt2x00dev, 79, 0x1C); +- rt2800_bbp_write(rt2x00dev, 80, 0x0C); +- rt2800_bbp_write(rt2x00dev, 82, 0xB6); +- /* bank 0 RF reg 42 and glrt BBP reg 141 will be set in +- * config channel function in dependence of channel and +- * HT20/HT40 so don't touch it +- */ ++ if (rt2x00dev->default_ant.rx_chain_num == 1) { ++ rt2800_bbp_write(rt2x00dev, 91, 0x07); ++ rt2800_bbp_write(rt2x00dev, 95, 0x1A); ++ rt2800_bbp_write(rt2x00dev, 195, 128); ++ rt2800_bbp_write(rt2x00dev, 196, 0xA0); ++ rt2800_bbp_write(rt2x00dev, 195, 170); ++ rt2800_bbp_write(rt2x00dev, 196, 0x12); ++ rt2800_bbp_write(rt2x00dev, 195, 171); ++ rt2800_bbp_write(rt2x00dev, 196, 0x10); ++ } else { ++ rt2800_bbp_write(rt2x00dev, 91, 0x06); ++ rt2800_bbp_write(rt2x00dev, 95, 0x9A); ++ rt2800_bbp_write(rt2x00dev, 195, 128); ++ rt2800_bbp_write(rt2x00dev, 196, 0xE0); ++ rt2800_bbp_write(rt2x00dev, 195, 170); ++ rt2800_bbp_write(rt2x00dev, 196, 0x30); ++ rt2800_bbp_write(rt2x00dev, 195, 171); ++ rt2800_bbp_write(rt2x00dev, 196, 0x30); + } ++ ++ /* AGC init */ ++ reg = rf->channel <= 14 ? 0x04 + 2 * rt2x00dev->lna_gain : 0; ++ rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); ++ ++ /* On 11A, We should delay and wait RF/BBP to be stable ++ * and the appropriate time should be 1000 micro seconds ++ * 2005/06/05 - On 11G, we also need this delay time. ++ * Otherwise it's difficult to pass the WHQL. ++ */ ++ usleep_range(1000, 1500); ++ ++ rt6352_init_palna_stage2(rt2x00dev); + } + + bbp = rt2800_bbp_read(rt2x00dev, 4); +@@ -5649,43 +5623,6 @@ void rt2800_vco_calibration(struct rt2x0 + } + } + rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); +- +- if (rt2x00_rt(rt2x00dev, RT6352)) { +- if (rt2x00dev->default_ant.rx_chain_num == 1) { +- rt2800_bbp_write(rt2x00dev, 91, 0x07); +- rt2800_bbp_write(rt2x00dev, 95, 0x1A); +- rt2800_bbp_write(rt2x00dev, 195, 128); +- rt2800_bbp_write(rt2x00dev, 196, 0xA0); +- rt2800_bbp_write(rt2x00dev, 195, 170); +- rt2800_bbp_write(rt2x00dev, 196, 0x12); +- rt2800_bbp_write(rt2x00dev, 195, 171); +- rt2800_bbp_write(rt2x00dev, 196, 0x10); +- } else { +- rt2800_bbp_write(rt2x00dev, 91, 0x06); +- rt2800_bbp_write(rt2x00dev, 95, 0x9A); +- rt2800_bbp_write(rt2x00dev, 195, 128); +- rt2800_bbp_write(rt2x00dev, 196, 0xE0); +- rt2800_bbp_write(rt2x00dev, 195, 170); +- rt2800_bbp_write(rt2x00dev, 196, 0x30); +- rt2800_bbp_write(rt2x00dev, 195, 171); +- rt2800_bbp_write(rt2x00dev, 196, 0x30); +- } +- +- if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { +- rt2800_bbp_write(rt2x00dev, 75, 0x68); +- rt2800_bbp_write(rt2x00dev, 76, 0x4C); +- rt2800_bbp_write(rt2x00dev, 79, 0x1C); +- rt2800_bbp_write(rt2x00dev, 80, 0x0C); +- rt2800_bbp_write(rt2x00dev, 82, 0xB6); +- } +- +- /* On 11A, We should delay and wait RF/BBP to be stable +- * and the appropriate time should be 1000 micro seconds +- * 2005/06/05 - On 11G, we also need this delay time. +- * Otherwise it's difficult to pass the WHQL. +- */ +- usleep_range(1000, 1500); +- } + } + EXPORT_SYMBOL_GPL(rt2800_vco_calibration); + +@@ -8650,7 +8587,7 @@ static void rt2800_r_calibration(struct + rt2x00_warn(rt2x00dev, "Wait MAC Tx Status to MAX !!!\n"); + + maccfg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); +- maccfg &= (~0x04); ++ maccfg &= (~0x08); + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, maccfg); + + if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX))) +@@ -10688,30 +10625,151 @@ static void rt2800_init_rfcsr_6352(struc + rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00); + rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C); + } ++} + +- rt6352_enable_pa_pin(rt2x00dev, 0); +- rt2800_r_calibration(rt2x00dev); +- rt2800_rf_self_txdc_cal(rt2x00dev); +- rt2800_rxdcoc_calibration(rt2x00dev); +- rt2800_bw_filter_calibration(rt2x00dev, true); +- rt2800_bw_filter_calibration(rt2x00dev, false); +- rt2800_loft_iq_calibration(rt2x00dev); +- rt2800_rxiq_calibration(rt2x00dev); +- rt6352_enable_pa_pin(rt2x00dev, 1); ++static void rt6352_init_ext_palna(struct rt2x00_dev *rt2x00dev) ++{ ++ u32 reg; ++ ++ if (rt2x00_has_cap_external_pa(rt2x00dev)) { ++ reg = rt2800_register_read(rt2x00dev, RF_CONTROL3); ++ reg |= 0x00000101; ++ rt2800_register_write(rt2x00dev, RF_CONTROL3, reg); ++ ++ reg = rt2800_register_read(rt2x00dev, RF_BYPASS3); ++ reg |= 0x00000101; ++ rt2800_register_write(rt2x00dev, RF_BYPASS3, reg); ++ } + +- if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { ++ if (rt2800_hw_get_chippkg(rt2x00dev) == 1 && ++ rt2x00_has_cap_external_lna_bg(rt2x00dev)) { + rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x66); + rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x20); + rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x42); ++ } ++ ++ if (rt2800_hw_get_chippkg(rt2x00dev) == 1 && ++ rt2x00_has_cap_external_pa(rt2x00dev)) { ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0x73); ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0x73); ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0x73); ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27); ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0xC8); ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xA4); ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x05); ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27); ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xC8); ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xA4); ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x05); ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x27); ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0xC8); ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xA4); ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x05); ++ } ++ ++ if (rt2800_hw_get_chippkg(rt2x00dev) == 1 && ++ rt2x00_has_cap_external_pa(rt2x00dev)) { ++ rt2800_rfcsr_write_dccal(rt2x00dev, 05, 0x00); ++ } ++ ++ if (rt2800_hw_get_chippkg(rt2x00dev) == 1 && ++ rt2x00_has_cap_external_lna_bg(rt2x00dev)) { + rt2800_bbp_write(rt2x00dev, 75, 0x68); + rt2800_bbp_write(rt2x00dev, 76, 0x4C); + rt2800_bbp_write(rt2x00dev, 79, 0x1C); + rt2800_bbp_write(rt2x00dev, 80, 0x0C); + rt2800_bbp_write(rt2x00dev, 82, 0xB6); +- /* bank 0 RF reg 42 and glrt BBP reg 141 will be set in config +- * channel function in dependence of channel and HT20/HT40, +- * so don't touch them here. +- */ ++ } ++ ++ if (rt2800_hw_get_chippkg(rt2x00dev) == 1 && ++ rt2x00_has_cap_external_pa(rt2x00dev)) { ++ rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, 0x36303636); ++ rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C6B6C); ++ rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C6B6C); ++ } ++} ++ ++static void rt6352_restore_rf_bbp(struct rt2x00_dev *rt2x00dev) ++{ ++ if (rt2x00_has_cap_external_pa(rt2x00dev)) { ++ rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0); ++ rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0); ++ } ++ ++ if (rt2800_hw_get_chippkg(rt2x00dev) == 1 && ++ rt2x00_has_cap_external_lna_bg(rt2x00dev)) { ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16); ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23); ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02); ++ } ++ ++ if (rt2800_hw_get_chippkg(rt2x00dev) == 1 && ++ rt2x00_has_cap_external_pa(rt2x00dev)) ++ { ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3); ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3); ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5); ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27); ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C); ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC); ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F); ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27); ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66); ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF); ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C); ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20); ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B); ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7); ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09); ++ } ++ ++ if (rt2800_hw_get_chippkg(rt2x00dev) == 1 && ++ rt2x00_has_cap_external_lna_bg(rt2x00dev)) { ++ rt2800_bbp_write(rt2x00dev, 75, 0x60); ++ rt2800_bbp_write(rt2x00dev, 76, 0x44); ++ rt2800_bbp_write(rt2x00dev, 79, 0x1C); ++ rt2800_bbp_write(rt2x00dev, 80, 0x0C); ++ rt2800_bbp_write(rt2x00dev, 82, 0xB6); ++ } ++ ++ if (rt2800_hw_get_chippkg(rt2x00dev) == 1 ++ && rt2x00_has_cap_external_pa(rt2x00dev)) { ++ rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, 0x3630363A); ++ rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C); ++ rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C); ++ } ++} ++ ++/* MT7620 PA/LNA initialization before switching channels */ ++static void rt6352_init_palna_stage1(struct rt2x00_dev *rt2x00dev) ++{ ++ if (rt2x00_has_cap_external_pa(rt2x00dev) || ++ rt2x00_has_cap_external_lna_bg(rt2x00dev)) { ++ rt6352_enable_pa_pin(rt2x00dev, 0); ++ rt6352_restore_rf_bbp(rt2x00dev); ++ } ++ ++ rt2800_r_calibration(rt2x00dev); ++} ++ ++/* MT7620 PA/LNA initialization after switching channels */ ++static void rt6352_init_palna_stage2(struct rt2x00_dev *rt2x00dev) ++{ ++ rt2800_rf_self_txdc_cal(rt2x00dev); ++ rt2800_rxdcoc_calibration(rt2x00dev); ++ rt2800_bw_filter_calibration(rt2x00dev, true); ++ rt2800_bw_filter_calibration(rt2x00dev, false); ++ rt2800_loft_iq_calibration(rt2x00dev); ++ ++ /* missing DPD Calibration for devices using internal PA */ ++ ++ rt2800_rxdcoc_calibration(rt2x00dev); ++ rt2800_rxiq_calibration(rt2x00dev); ++ ++ if(rt2x00_has_cap_external_pa(rt2x00dev) || ++ rt2x00_has_cap_external_lna_bg(rt2x00dev)) { ++ rt6352_enable_pa_pin(rt2x00dev, 1); ++ rt6352_init_ext_palna(rt2x00dev); + } + } + +--- a/drivers/net/wireless/ralink/rt2x00/rt2x00.h ++++ b/drivers/net/wireless/ralink/rt2x00/rt2x00.h +@@ -1277,6 +1277,12 @@ rt2x00_has_cap_external_lna_bg(struct rt + } + + static inline bool ++rt2x00_has_cap_external_pa(struct rt2x00_dev *rt2x00dev) ++{ ++ return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_EXTERNAL_PA_TX0); ++} ++ ++static inline bool + rt2x00_has_cap_double_antenna(struct rt2x00_dev *rt2x00dev) + { + return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_DOUBLE_ANTENNA); diff --git a/package/kernel/mt76/Makefile b/package/kernel/mt76/Makefile index 2ab6d6d6ebe..42d0e6a070f 100644 --- a/package/kernel/mt76/Makefile +++ b/package/kernel/mt76/Makefile @@ -8,9 +8,9 @@ PKG_LICENSE_FILES:= PKG_SOURCE_URL:=https://github.com/openwrt/mt76 PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2023-07-14 -PKG_SOURCE_VERSION:=bb3937d5c3e0b13c0d08747ec0fc9726fb4fd870 -PKG_MIRROR_HASH:=498d9cfdafe06572d0668d49e89f1014715100fa59c4f89b8495cd869c8c9b0b +PKG_SOURCE_DATE:=2023-07-26 +PKG_SOURCE_VERSION:=cd3dfe39276905307cc028ac8edf2c06963cda23 +PKG_MIRROR_HASH:=413d2d0faa81d834ba13cb9e503e1e3a61e3e071014da6b525a123e5da053f90 PKG_MAINTAINER:=Felix Fietkau PKG_USE_NINJA:=0 diff --git a/package/kernel/rtl8812au-ct/patches/005-kernel-6.1.patch b/package/kernel/rtl8812au-ct/patches/005-kernel-6.1.patch new file mode 100644 index 00000000000..98aa6784910 --- /dev/null +++ b/package/kernel/rtl8812au-ct/patches/005-kernel-6.1.patch @@ -0,0 +1,14 @@ +--- a/include/osdep_service_linux.h ++++ b/include/osdep_service_linux.h +@@ -163,7 +163,11 @@ typedef void* _thread_hdl_; + typedef int thread_return; + typedef void* thread_context; + ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5,17,0)) ++#define thread_exit() kthread_complete_and_exit(NULL, 0) ++#else + #define thread_exit() complete_and_exit(NULL, 0) ++#endif + + typedef void timer_hdl_return; + typedef void* timer_hdl_context; diff --git a/package/libs/libnl-tiny/Makefile b/package/libs/libnl-tiny/Makefile index 048c3e79397..4bdd7c1c397 100644 --- a/package/libs/libnl-tiny/Makefile +++ b/package/libs/libnl-tiny/Makefile @@ -12,9 +12,9 @@ PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/libnl-tiny.git -PKG_SOURCE_DATE:=2023-07-01 -PKG_SOURCE_VERSION:=d433990c00e804593f253cc709b8fe901492b530 -PKG_MIRROR_HASH:=fffb2782c7ed2ebabc7d57e5513f52ac53d1828014bc9a8ea131f50eab093086 +PKG_SOURCE_DATE:=2023-07-27 +PKG_SOURCE_VERSION:=bc92a280186f9becc53c0f17e4e43cfbdeec7e7b +PKG_MIRROR_HASH:=57c5ac75fdb4413e98e525bee7de419fc6cce5f23389581dafd9ffe22321224d CMAKE_INSTALL:=1 PKG_LICENSE:=LGPL-2.1 @@ -27,7 +27,7 @@ define Package/libnl-tiny SECTION:=libs CATEGORY:=Libraries TITLE:=netlink socket library - ABI_VERSION:=$(PKG_SOURCE_DATE) + ABI_VERSION:=1 endef define Package/libnl-tiny/description @@ -37,13 +37,13 @@ endef define Build/InstallDev $(INSTALL_DIR) $(1)/usr/lib/pkgconfig $(1)/usr/include/libnl-tiny $(CP) $(PKG_INSTALL_DIR)/usr/include/libnl-tiny/* $(1)/usr/include/libnl-tiny - $(INSTALL_DATA) $(PKG_INSTALL_DIR)/usr/lib/libnl-tiny.so $(1)/usr/lib/ + $(CP) $(PKG_INSTALL_DIR)/usr/lib/libnl-tiny.so* $(1)/usr/lib/ $(INSTALL_DATA) $(PKG_BUILD_DIR)/libnl-tiny.pc $(1)/usr/lib/pkgconfig endef define Package/libnl-tiny/install $(INSTALL_DIR) $(1)/usr/lib - $(INSTALL_DATA) $(PKG_INSTALL_DIR)/usr/lib/libnl-tiny.so $(1)/usr/lib/ + $(CP) $(PKG_INSTALL_DIR)/usr/lib/libnl-tiny.so.* $(1)/usr/lib/ endef $(eval $(call BuildPackage,libnl-tiny)) diff --git a/package/libs/nettle/Makefile b/package/libs/nettle/Makefile index 36410920b99..e8dcb8ba913 100644 --- a/package/libs/nettle/Makefile +++ b/package/libs/nettle/Makefile @@ -8,13 +8,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=nettle -PKG_VERSION:=3.9 +PKG_VERSION:=3.9.1 PKG_RELEASE:=1 PKG_BUILD_FLAGS:=no-mips16 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=@GNU/nettle -PKG_HASH:=0ee7adf5a7201610bb7fe0acbb7c9b3be83be44904dd35ebbcd965cd896bfeaa +PKG_HASH:=ccfeff981b0ca71bbd6fbcb054f407c60ffb644389a5be80d6716d5b550c6ce3 PKG_LICENSE:=GPL-2.0-or-later PKG_LICENSE_FILES:=COPYING diff --git a/package/libs/openssl/Makefile b/package/libs/openssl/Makefile index 0d09114f06e..13e5952b372 100644 --- a/package/libs/openssl/Makefile +++ b/package/libs/openssl/Makefile @@ -9,8 +9,8 @@ include $(TOPDIR)/rules.mk PKG_NAME:=openssl PKG_VERSION:=3.0.9 -PKG_RELEASE:=2 -PKG_BUILD_FLAGS:=no-mips16 gc-sections +PKG_RELEASE:=3 +PKG_BUILD_FLAGS:=no-mips16 gc-sections no-lto PKG_BUILD_PARALLEL:=1 diff --git a/package/network/services/dropbear/files/dropbear.failsafe b/package/network/services/dropbear/files/dropbear.failsafe index a98ede459ad..97bd12d58a1 100755 --- a/package/network/services/dropbear/files/dropbear.failsafe +++ b/package/network/services/dropbear/files/dropbear.failsafe @@ -1,8 +1,9 @@ #!/bin/sh failsafe_dropbear () { - dropbearkey -t rsa -s 1024 -f /tmp/dropbear_failsafe_host_key - dropbear -r /tmp/dropbear_failsafe_host_key <> /dev/null 2>&1 + dropbearkey -t rsa -s 1024 -f /tmp/dropbear_rsa_failsafe_host_key + dropbearkey -t ed25519 -f /tmp/dropbear_ed25519_failsafe_host_key + dropbear -r /tmp/dropbear_rsa_failsafe_host_key -r /tmp/dropbear_ed25519_failsafe_host_key <> /dev/null 2>&1 } boot_hook_add failsafe failsafe_dropbear diff --git a/package/network/utils/ethtool/Makefile b/package/network/utils/ethtool/Makefile index 10fecd4a9c5..024fdf1e63f 100644 --- a/package/network/utils/ethtool/Makefile +++ b/package/network/utils/ethtool/Makefile @@ -8,13 +8,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=ethtool -PKG_VERSION:=6.3 +PKG_VERSION:=6.4 PKG_RELEASE:=1 PKG_MAINTAINER:=Felix Fietkau PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz PKG_SOURCE_URL:=@KERNEL/software/network/ethtool -PKG_HASH:=d9425f0a3df138734001fccc4175fe178c025f938460ac25c4ebc39960168822 +PKG_HASH:=5eaa083e8108e1dd3876b2c803a1942a2763942715b7f6eb916e189adbb44972 PKG_LICENSE:=GPL-2.0 PKG_LICENSE_FILES:=COPYING diff --git a/package/network/utils/iproute2/Makefile b/package/network/utils/iproute2/Makefile index 101ca673244..194edcb35a9 100644 --- a/package/network/utils/iproute2/Makefile +++ b/package/network/utils/iproute2/Makefile @@ -8,12 +8,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=iproute2 -PKG_VERSION:=6.3.0 +PKG_VERSION:=6.4.0 PKG_RELEASE:=1 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz PKG_SOURCE_URL:=@KERNEL/linux/utils/net/iproute2 -PKG_HASH:=dfb2a98db96e7a653cffc6693335a1a466e29a34b6ac528be48f35e1d2766732 +PKG_HASH:=4c51b8decbc7e4da159ffb066f590cfb93dbf9af7ff86b1647ce42b7c179a272 PKG_BUILD_PARALLEL:=1 PKG_BUILD_DEPENDS:=iptables PKG_LICENSE:=GPL-2.0 diff --git a/package/system/procd/Makefile b/package/system/procd/Makefile index 9e829a21591..d0576c12595 100644 --- a/package/system/procd/Makefile +++ b/package/system/procd/Makefile @@ -8,7 +8,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=procd -PKG_RELEASE:=1 +PKG_RELEASE:=2 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/procd.git diff --git a/package/system/procd/files/procd.sh b/package/system/procd/files/procd.sh index 5148b2f03c3..8ee25f4f08b 100644 --- a/package/system/procd/files/procd.sh +++ b/package/system/procd/files/procd.sh @@ -524,7 +524,10 @@ _procd_send_signal() { _procd_status() { local service="$1" local instance="$2" - local data + local data state + local n_running=0 + local n_stopped=0 + local n_total=0 json_init [ -n "$service" ] && json_add_string name "$service" @@ -539,10 +542,29 @@ _procd_status() { fi [ -n "$instance" ] && instance="\"$instance\"" || instance='*' - if [ -z "$(echo "$data" | jsonfilter -e '$['"$instance"']')" ]; then - echo "unknown instance $instance"; return 4 + + for state in $(jsonfilter -s "$data" -e '$['"$instance"'].running'); do + n_total=$((n_total + 1)) + case "$state" in + false) n_stopped=$((n_stopped + 1)) ;; + true) n_running=$((n_running + 1)) ;; + esac + done + + if [ $n_total -gt 0 ]; then + if [ $n_running -gt 0 ] && [ $n_stopped -eq 0 ]; then + echo "running" + return 0 + elif [ $n_running -gt 0 ]; then + echo "running ($n_running/$n_total)" + return 0 + else + echo "not running" + return 5 + fi else - echo "running"; return 0 + echo "unknown instance $instance" + return 4 fi } diff --git a/package/system/urngd/Makefile b/package/system/urngd/Makefile index 8350f7ceb99..e131e1be7eb 100644 --- a/package/system/urngd/Makefile +++ b/package/system/urngd/Makefile @@ -5,9 +5,9 @@ PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/urngd.git -PKG_SOURCE_DATE:=2020-01-21 -PKG_SOURCE_VERSION:=c7f7b6b65b82eda4675b42d8cd28d76ea7aebf1a -PKG_MIRROR_HASH:=2d31025b79fe130c579d6c3f4bf4dc12abc43a7319b20a5cdca24ae363ec70f3 +PKG_SOURCE_DATE:=2023-07-25 +PKG_SOURCE_VERSION:=7aefb47be57df0467d97d539f7fe9e23e607a3b4 +PKG_MIRROR_HASH:=941e4298acc9a0c9b485b9ad706bb11c4d0bc7a66eec22e569b430ab38a9f5fc PKG_LICENSE:=GPL-2.0 BSD-3-Clause PKG_LICENSE_FILES:= diff --git a/package/utils/ugps/Makefile b/package/utils/ugps/Makefile index 5afba4e0b02..322f0d210d5 100644 --- a/package/utils/ugps/Makefile +++ b/package/utils/ugps/Makefile @@ -12,9 +12,9 @@ PKG_RELEASE:=2 PKG_SOURCE_URL=$(PROJECT_GIT)/project/ugps.git PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2021-06-08 -PKG_SOURCE_VERSION:=5e88403fc0d39ae8a270d2c6c6e9c8a4d5232cf3 -PKG_MIRROR_HASH:=a3dfc2cc6def3b634d8b7cda9139926be3d876cf2faa5251c4821987954442a5 +PKG_SOURCE_DATE:=2023-01-27 +PKG_SOURCE_VERSION:=a8171a07193351a9125024d5c759c0ebd6a6895c +PKG_MIRROR_HASH:=9116c9698c15744bb2e36a7cfd0a73f1609b6932f32ca07da57238aea8a2d5cf PKG_MAINTAINER:=John Crispin PKG_LICENSE:=GPL-2.0+ diff --git a/package/utils/ugps/files/ugps.init b/package/utils/ugps/files/ugps.init index 77c36030667..e702b4ca44e 100644 --- a/package/utils/ugps/files/ugps.init +++ b/package/utils/ugps/files/ugps.init @@ -12,6 +12,7 @@ service_triggers() { start_service() { local tty="$(uci get gps.@gps[-1].tty)" + local baudrate="$(uci get gps.@gps[-1].baudrate || echo 0)" local atime="$(uci get gps.@gps[-1].adjust_time)" local disabled="$(uci get gps.@gps[-1].disabled || echo 0)" @@ -29,6 +30,7 @@ start_service() { procd_open_instance procd_set_param command "$PROG" + [ "$baudrate" -eq 0 ] || procd_append_param command "-b ${baudrate}" [ "$atime" -eq 0 ] || procd_append_param command "-a" procd_append_param command "$tty" procd_set_param respawn diff --git a/package/utils/zyxel-bootconfig/files/95_apply_bootconfig b/package/utils/zyxel-bootconfig/files/95_apply_bootconfig index 500b81234a6..c98bc8fbe24 100644 --- a/package/utils/zyxel-bootconfig/files/95_apply_bootconfig +++ b/package/utils/zyxel-bootconfig/files/95_apply_bootconfig @@ -3,6 +3,7 @@ apply_bootconfig() { case $(board_name) in zyxel,nwa50ax|\ + zyxel,nwa50ax-pro|\ zyxel,nwa55axe) mtd_idx=$(find_mtd_index "bootconfig") zyxel-bootconfig "/dev/mtd$mtd_idx" set-image-status 0 valid diff --git a/scripts/dl_github_archive.py b/scripts/dl_github_archive.py index 328d588e781..580b7cba38a 100755 --- a/scripts/dl_github_archive.py +++ b/scripts/dl_github_archive.py @@ -239,6 +239,7 @@ class DownloadGitHubTarball(object): self.version = args.version self.subdir = args.subdir self.source = args.source + self.submodules = args.submodules self.url = args.url self._init_owner_repo() self.xhash = args.hash @@ -249,6 +250,8 @@ class DownloadGitHubTarball(object): def download(self): """Download and repack GitHub archive tarball.""" + if self.submodules and self.submodules != ['skip']: + raise self._error('Fetching submodules is not yet supported') self._init_commit_ts() with Path(TMPDIR_DL, keep=True) as dir_dl: # fetch tarball from GitHub @@ -262,7 +265,7 @@ class DownloadGitHubTarball(object): dir0 = os.path.join(dir_untar.path, tarball_prefix) dir1 = os.path.join(dir_untar.path, self.subdir) # submodules check - if self._has_submodule(dir0): + if self.submodules != ['skip'] and self._has_submodule(dir0): raise self._error('Fetching submodules is not yet supported') # rename subdir os.rename(dir0, dir1) @@ -415,6 +418,7 @@ def main(): parser.add_argument('--version', help='Source code version') parser.add_argument('--source', help='Source tarball filename') parser.add_argument('--hash', help='Source tarball\'s expected sha256sum') + parser.add_argument('--submodules', nargs='*', help='List of submodules, or "skip"') args = parser.parse_args() try: method = DownloadGitHubTarball(args) diff --git a/scripts/mkits-zyxel-fit-filogic.sh b/scripts/mkits-zyxel-fit-filogic.sh new file mode 100755 index 00000000000..319e187f5a9 --- /dev/null +++ b/scripts/mkits-zyxel-fit-filogic.sh @@ -0,0 +1,40 @@ +#!/usr/bin/env bash +# +# Licensed under the terms of the GNU GPL License version 2 or later. +# Author: David Bauer , based on mkits-zyxel-factory.sh. + +usage() { + echo "Usage: `basename $0` output file compat-models" + exit 1 +} + +# We need at least 3 arguments +[ "$#" -lt 3 ] && usage + +# Target output file +OUTPUT="$1"; shift +FILE="$1"; shift +MODELS="$1"; shift + +# Create a default, fully populated DTS file +echo "\ +/dts-v1/; + +/ { + timestamp = <0x684090B4>; + description = \"Zyxel FIT (Flattened Image Tree)\"; + compat-models = [${MODELS}]; + fw_version = \"9.99(###.1)\"; + #address-cells = <1>; + + images { + ubi { + data = /incbin/(\"${FILE}\"); + type = \"firmware\"; + compression = \"none\"; + hash { + algo = \"sha256\"; + }; + }; + }; +};" > ${OUTPUT} diff --git a/target/linux/ath79/dts/ar7161_dlink_dir-825-b1.dts b/target/linux/ath79/dts/ar7161_dlink_dir-825-b1.dts index 0e39be7d0bb..bdb678298d7 100644 --- a/target/linux/ath79/dts/ar7161_dlink_dir-825-b1.dts +++ b/target/linux/ath79/dts/ar7161_dlink_dir-825-b1.dts @@ -139,8 +139,8 @@ ath9k0: wifi@0,11 { compatible = "pci168c,0029"; reg = <0x8800 0 0 0 0>; - nvmem-cells = <&macaddr_lan>, <&cal_art_1000>; - nvmem-cell-names = "mac-address-ascii", "calibration"; + nvmem-cells = <&macaddr_lan 0>, <&cal_art_1000>; + nvmem-cell-names = "mac-address", "calibration"; #gpio-cells = <2>; gpio-controller; }; @@ -148,9 +148,8 @@ ath9k1: wifi@0,12 { compatible = "pci168c,0029"; reg = <0x9000 0 0 0 0>; - nvmem-cells = <&macaddr_wan>, <&cal_art_5000>; - nvmem-cell-names = "mac-address-ascii", "calibration"; - mac-address-increment = <1>; + nvmem-cells = <&macaddr_wan 1>, <&cal_art_5000>; + nvmem-cell-names = "mac-address", "calibration"; #gpio-cells = <2>; gpio-controller; }; @@ -191,23 +190,31 @@ label = "caldata"; reg = <0x660000 0x010000>; read-only; - #address-cells = <1>; - #size-cells = <1>; - cal_art_1000: cal@1000 { - reg = <0x1000 0xeb8>; - }; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - cal_art_5000: cal@5000 { - reg = <0x5000 0xeb8>; - }; + cal_art_1000: cal@1000 { + reg = <0x1000 0xeb8>; + }; - macaddr_lan: macaddr@ffa0 { - reg = <0xffa0 0x11>; - }; + cal_art_5000: cal@5000 { + reg = <0x5000 0xeb8>; + }; - macaddr_wan: macaddr@ffb4 { - reg = <0xffb4 0x11>; + macaddr_lan: macaddr@ffa0 { + compatible = "mac-base"; + reg = <0xffa0 0x11>; + #nvmem-cell-cells = <1>; + }; + + macaddr_wan: macaddr@ffb4 { + compatible = "mac-base"; + reg = <0xffb4 0x11>; + #nvmem-cell-cells = <1>; + }; }; }; @@ -224,8 +231,8 @@ pll-data = <0x11110000 0x00001099 0x00991099>; - nvmem-cells = <&macaddr_lan>; - nvmem-cell-names = "mac-address-ascii"; + nvmem-cells = <&macaddr_lan 0>; + nvmem-cell-names = "mac-address"; fixed-link { speed = <1000>; @@ -238,8 +245,8 @@ pll-data = <0x11110000 0x00001099 0x00991099>; - nvmem-cells = <&macaddr_wan>; - nvmem-cell-names = "mac-address-ascii"; + nvmem-cells = <&macaddr_wan 0>; + nvmem-cell-names = "mac-address"; phy-handle = <&phy4>; }; diff --git a/target/linux/ath79/dts/ar9331_hiwifi_hc6361.dts b/target/linux/ath79/dts/ar9331_hiwifi_hc6361.dts index 05d3f6730e7..fa000ab90c7 100644 --- a/target/linux/ath79/dts/ar9331_hiwifi_hc6361.dts +++ b/target/linux/ath79/dts/ar9331_hiwifi_hc6361.dts @@ -77,9 +77,22 @@ }; bdinfo: partition@10000 { + compatible = "nvmem-cells"; reg = <0x10000 0x10000>; label = "bdinfo"; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_bdinfo_18a: macaddr@18a { + compatible = "mac-base"; + reg = <0x18a 0x11>; + #nvmem-cell-cells = <1>; + }; + }; }; firmware: partition@20000 { @@ -124,33 +137,21 @@ ð0 { status = "okay"; - nvmem-cells = <&macaddr_bdinfo_18a>; - nvmem-cell-names = "mac-address-ascii"; - mac-address-increment = <1>; + nvmem-cells = <&macaddr_bdinfo_18a 1>; + nvmem-cell-names = "mac-address"; }; ð1 { status = "okay"; - nvmem-cells = <&macaddr_bdinfo_18a>; - nvmem-cell-names = "mac-address-ascii"; + nvmem-cells = <&macaddr_bdinfo_18a 0>; + nvmem-cell-names = "mac-address"; }; &wmac { status = "okay"; mtd-cal-data = <&art 0x1000>; - nvmem-cells = <&macaddr_bdinfo_18a>; - nvmem-cell-names = "mac-address-ascii"; - mac-address-increment = <2>; -}; - -&bdinfo { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_bdinfo_18a: macaddr@18a { - reg = <0x18a 0x11>; - }; + nvmem-cells = <&macaddr_bdinfo_18a 2>; + nvmem-cell-names = "mac-address"; }; diff --git a/target/linux/ath79/dts/ar9342_zyxel_nwa11xx.dtsi b/target/linux/ath79/dts/ar9342_zyxel_nwa11xx.dtsi index 7cc1bba3fc4..a05cc2e2637 100644 --- a/target/linux/ath79/dts/ar9342_zyxel_nwa11xx.dtsi +++ b/target/linux/ath79/dts/ar9342_zyxel_nwa11xx.dtsi @@ -93,15 +93,23 @@ read-only; compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - macaddr_mib0_4b: macaddr@4b { - reg = <0x4b 0x11>; - }; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_mib0_66: macaddr@66 { - reg = <0x66 0x11>; + macaddr_mib0_4b: macaddr@4b { + compatible = "mac-base"; + reg = <0x4b 0x11>; + #nvmem-cell-cells = <1>; + }; + + macaddr_mib0_66: macaddr@66 { + compatible = "mac-base"; + reg = <0x66 0x11>; + #nvmem-cell-cells = <1>; + }; }; }; @@ -161,6 +169,6 @@ ieee80211-freq-limit = <2402000 2482000>; - nvmem-cells = <&macaddr_mib0_4b>, <&calibration_ath9k>; - nvmem-cell-names = "mac-address-ascii", "calibration"; + nvmem-cells = <&macaddr_mib0_4b 0>, <&calibration_ath9k>; + nvmem-cell-names = "mac-address", "calibration"; }; diff --git a/target/linux/ath79/dts/ar9344_dlink_dir-8x5.dtsi b/target/linux/ath79/dts/ar9344_dlink_dir-8x5.dtsi index 8e21b0dd9e8..8db1bf5e0c0 100644 --- a/target/linux/ath79/dts/ar9344_dlink_dir-8x5.dtsi +++ b/target/linux/ath79/dts/ar9344_dlink_dir-8x5.dtsi @@ -29,8 +29,8 @@ /* default for ar934x, except for 1000M */ pll-data = <0x06000000 0x00000101 0x00001616>; - nvmem-cells = <&macaddr_lan>; - nvmem-cell-names = "mac-address-ascii"; + nvmem-cells = <&macaddr_lan 0>; + nvmem-cell-names = "mac-address"; phy-mode = "rgmii"; phy-handle = <&phy0>; @@ -58,13 +58,13 @@ ath9k: wifi@0,0 { compatible = "pci168c,0030"; reg = <0x0000 0 0 0 0>; - /* "mac-address-ascii" currently does not work for + /* "mac-address" currently does not work for ath9k pci devices. these below are retained for future improvements. */ - /* nvmem-cells = <&macaddr_wan>, <&cal_art_5000>; - nvmem-cell-names = "mac-address-ascii", "calibration"; - mac-address-increment = <1>; */ - qca,no-eeprom; /* remove this when "mac-address-ascii" works */ + /* nvmem-cells = <&macaddr_wan 1>, <&cal_art_5000>; + nvmem-cell-names = "mac-address", "calibration"; + */ + qca,no-eeprom; /* remove this when "mac-address" works */ gpio-controller; #gpio-cells = <2>; }; @@ -117,15 +117,23 @@ read-only; compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - macaddr_lan: macaddr@4 { - reg = <0x4 0x11>; - }; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_wan: macaddr@18 { - reg = <0x18 0x11>; + macaddr_lan: macaddr@4 { + compatible = "mac-base"; + reg = <0x4 0x11>; + #nvmem-cell-cells = <1>; + }; + + macaddr_wan: macaddr@18 { + compatible = "mac-base"; + reg = <0x18 0x11>; + #nvmem-cell-cells = <1>; + }; }; }; @@ -160,6 +168,6 @@ &wmac { status = "okay"; - nvmem-cells = <&macaddr_lan>, <&cal_art_1000>; - nvmem-cell-names = "mac-address-ascii", "calibration"; + nvmem-cells = <&macaddr_lan 0>, <&cal_art_1000>; + nvmem-cell-names = "mac-address", "calibration"; }; diff --git a/target/linux/ath79/dts/qca9558_dlink_dir-629-a1.dts b/target/linux/ath79/dts/qca9558_dlink_dir-629-a1.dts index 41b0039e930..d012ae4c505 100644 --- a/target/linux/ath79/dts/qca9558_dlink_dir-629-a1.dts +++ b/target/linux/ath79/dts/qca9558_dlink_dir-629-a1.dts @@ -65,8 +65,8 @@ phy-mode = "mii"; - nvmem-cells = <&macaddr_mfcdata_35>; - nvmem-cell-names = "mac-address-ascii"; + nvmem-cells = <&macaddr_mfcdata_35 0>; + nvmem-cell-names = "mac-address"; fixed-link { speed = <100>; @@ -115,15 +115,23 @@ read-only; compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - macaddr_mfcdata_35: macaddr@35 { - reg = <0x35 0x11>; - }; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_mfcdata_51: macaddr@51 { - reg = <0x51 0x11>; + macaddr_mfcdata_35: macaddr@35 { + compatible = "mac-base"; + reg = <0x35 0x11>; + #nvmem-cell-cells = <1>; + }; + + macaddr_mfcdata_51: macaddr@51 { + compatible = "mac-base"; + reg = <0x51 0x11>; + #nvmem-cell-cells = <1>; + }; }; }; @@ -165,6 +173,6 @@ &wmac { status = "okay"; - nvmem-cells = <&cal_art_1000>, <&macaddr_mfcdata_51>; - nvmem-cell-names = "calibration", "mac-address-ascii"; + nvmem-cells = <&cal_art_1000>, <&macaddr_mfcdata_51 0>; + nvmem-cell-names = "calibration", "mac-address"; }; diff --git a/target/linux/ath79/dts/qca9563_dlink_dir-8x9-a1.dtsi b/target/linux/ath79/dts/qca9563_dlink_dir-8x9-a1.dtsi index 3fd9790c4a2..616c29a4c15 100644 --- a/target/linux/ath79/dts/qca9563_dlink_dir-8x9-a1.dtsi +++ b/target/linux/ath79/dts/qca9563_dlink_dir-8x9-a1.dtsi @@ -32,8 +32,8 @@ compatible = "qcom,ath10k"; reg = <0x0000 0 0 0 0>; - nvmem-cells = <&calibration_ath10k>, <&macaddr_devdata_94>; - nvmem-cell-names = "calibration", "mac-address-ascii"; + nvmem-cells = <&calibration_ath10k>, <&macaddr_devdata_94 0>; + nvmem-cell-names = "calibration", "mac-address"; }; }; @@ -68,16 +68,25 @@ read-only; compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - macaddr_devdata_94: macaddr@94 { - reg = <0x94 0x11>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_devdata_94: macaddr@94 { + compatible = "mac-base"; + reg = <0x94 0x11>; + #nvmem-cell-cells = <1>; + }; + + macaddr_devdata_b0: macaddr@b0 { + compatible = "mac-base"; + reg = <0xb0 0x11>; + #nvmem-cell-cells = <1>; + }; }; - macaddr_devdata_b0: macaddr@b0 { - reg = <0xb0 0x11>; - }; }; partition@60000 { @@ -147,6 +156,6 @@ &wmac { status = "okay"; - nvmem-cells = <&calibration_ath9k>, <&macaddr_devdata_b0>; - nvmem-cell-names = "calibration", "mac-address-ascii"; + nvmem-cells = <&calibration_ath9k>, <&macaddr_devdata_b0 0>; + nvmem-cell-names = "calibration", "mac-address"; }; diff --git a/target/linux/bcm27xx/patches-6.1/950-0034-drm-bridge-Introduce-pre_enable_upstream_first-to-al.patch b/target/linux/bcm27xx/patches-6.1/950-0034-drm-bridge-Introduce-pre_enable_upstream_first-to-al.patch deleted file mode 100644 index bab4ed9b907..00000000000 --- a/target/linux/bcm27xx/patches-6.1/950-0034-drm-bridge-Introduce-pre_enable_upstream_first-to-al.patch +++ /dev/null @@ -1,308 +0,0 @@ -From 5365030a003a6cb0c336202256341e4bc9d65d52 Mon Sep 17 00:00:00 2001 -From: Dave Stevenson -Date: Thu, 16 Dec 2021 15:25:35 +0000 -Subject: [PATCH] drm/bridge: Introduce pre_enable_upstream_first to - alter bridge init order - -DSI sink devices typically want the DSI host powered up and configured -before they are powered up. pre_enable is the place this would normally -happen, but they are called in reverse order from panel/connector towards -the encoder, which is the "wrong" order. - -Add a new flag pre_enable_upstream_first that any bridge can set -to swap the order of pre_enable (and post_disable) for that and the -immediately upstream bridge. -Should the immediately upstream bridge also set the -pre_enable_upstream_first flag, the bridge upstream of that will be called -before either of those which requested pre_enable_upstream_first. - -eg: -- Panel -- Bridge 1 -- Bridge 2 pre_enable_upstream_first -- Bridge 3 -- Bridge 4 pre_enable_upstream_first -- Bridge 5 pre_enable_upstream_first -- Bridge 6 -- Encoder -Would result in pre_enable's being called as Panel, Bridge 1, Bridge 3, -Bridge 2, Bridge 6, Bridge 5, Bridge 4, Encoder. - -Signed-off-by: Dave Stevenson ---- - drivers/gpu/drm/drm_bridge.c | 177 +++++++++++++++++++++++++---------- - include/drm/drm_bridge.h | 8 ++ - 2 files changed, 137 insertions(+), 48 deletions(-) - ---- a/drivers/gpu/drm/drm_bridge.c -+++ b/drivers/gpu/drm/drm_bridge.c -@@ -547,20 +547,15 @@ EXPORT_SYMBOL(drm_bridge_chain_disable); - * encoder chain, starting from the first bridge to the last. These are called - * after completing the encoder's prepare op. - * -+ * If a bridge sets @pre_enable_upstream_first, then the @post_disable for that -+ * bridge will be called before the previous one to reverse the @pre_enable -+ * calling direction. -+ * - * Note: the bridge passed should be the one closest to the encoder - */ - void drm_bridge_chain_post_disable(struct drm_bridge *bridge) - { -- struct drm_encoder *encoder; -- -- if (!bridge) -- return; -- -- encoder = bridge->encoder; -- list_for_each_entry_from(bridge, &encoder->bridge_chain, chain_node) { -- if (bridge->funcs->post_disable) -- bridge->funcs->post_disable(bridge); -- } -+ drm_atomic_bridge_chain_post_disable(bridge, NULL); - } - EXPORT_SYMBOL(drm_bridge_chain_post_disable); - -@@ -602,24 +597,14 @@ EXPORT_SYMBOL(drm_bridge_chain_mode_set) - * chain, starting from the last bridge to the first. These are called - * before calling the encoder's commit op. - * -+ * If a bridge sets @pre_enable_upstream_first, then the @pre_enable for the -+ * previous bridge will be called before @pre_enable of this bridge. -+ * - * Note: the bridge passed should be the one closest to the encoder - */ - void drm_bridge_chain_pre_enable(struct drm_bridge *bridge) - { -- struct drm_encoder *encoder; -- struct drm_bridge *iter; -- -- if (!bridge) -- return; -- -- encoder = bridge->encoder; -- list_for_each_entry_reverse(iter, &encoder->bridge_chain, chain_node) { -- if (iter->funcs->pre_enable) -- iter->funcs->pre_enable(iter); -- -- if (iter == bridge) -- break; -- } -+ drm_atomic_bridge_chain_pre_enable(bridge, NULL); - } - EXPORT_SYMBOL(drm_bridge_chain_pre_enable); - -@@ -691,6 +676,25 @@ void drm_atomic_bridge_chain_disable(str - } - EXPORT_SYMBOL(drm_atomic_bridge_chain_disable); - -+static void drm_atomic_bridge_call_post_disable(struct drm_bridge *bridge, -+ struct drm_atomic_state *old_state) -+{ -+ if (old_state && bridge->funcs->atomic_post_disable) { -+ struct drm_bridge_state *old_bridge_state; -+ -+ old_bridge_state = -+ drm_atomic_get_old_bridge_state(old_state, -+ bridge); -+ if (WARN_ON(!old_bridge_state)) -+ return; -+ -+ bridge->funcs->atomic_post_disable(bridge, -+ old_bridge_state); -+ } else if (bridge->funcs->post_disable) { -+ bridge->funcs->post_disable(bridge); -+ } -+} -+ - /** - * drm_atomic_bridge_chain_post_disable - cleans up after disabling all bridges - * in the encoder chain -@@ -701,6 +705,9 @@ EXPORT_SYMBOL(drm_atomic_bridge_chain_di - * &drm_bridge_funcs.post_disable) op for all the bridges in the encoder chain, - * starting from the first bridge to the last. These are called after completing - * &drm_encoder_helper_funcs.atomic_disable -+ * If a bridge sets @pre_enable_upstream_first, then the @post_disable for that -+ * bridge will be called before the previous one to reverse the @pre_enable -+ * calling direction. - * - * Note: the bridge passed should be the one closest to the encoder - */ -@@ -708,30 +715,75 @@ void drm_atomic_bridge_chain_post_disabl - struct drm_atomic_state *old_state) - { - struct drm_encoder *encoder; -+ struct drm_bridge *next, *limit; - - if (!bridge) - return; - - encoder = bridge->encoder; -+ - list_for_each_entry_from(bridge, &encoder->bridge_chain, chain_node) { -- if (bridge->funcs->atomic_post_disable) { -- struct drm_bridge_state *old_bridge_state; -+ limit = NULL; - -- old_bridge_state = -- drm_atomic_get_old_bridge_state(old_state, -- bridge); -- if (WARN_ON(!old_bridge_state)) -- return; -+ if (!list_is_last(&bridge->chain_node, &encoder->bridge_chain)) { -+ next = list_next_entry(bridge, chain_node); - -- bridge->funcs->atomic_post_disable(bridge, -- old_bridge_state); -- } else if (bridge->funcs->post_disable) { -- bridge->funcs->post_disable(bridge); -+ if (next->pre_enable_upstream_first) { -+ /* Downstream bridge had requested that upstream -+ * was enabled first, so disabled last -+ */ -+ limit = next; -+ -+ /* Find the next bridge that has NOT requested -+ * upstream to be enabled first / disabled last -+ */ -+ list_for_each_entry_from(next, &encoder->bridge_chain, -+ chain_node) { -+ if (next->pre_enable_upstream_first) { -+ next = list_prev_entry(next, chain_node); -+ limit = next; -+ break; -+ } -+ } -+ -+ /* Call these bridges in reverse order */ -+ list_for_each_entry_from_reverse(next, &encoder->bridge_chain, -+ chain_node) { -+ if (next == bridge) -+ break; -+ -+ drm_atomic_bridge_call_post_disable(next, -+ old_state); -+ } -+ } - } -+ -+ drm_atomic_bridge_call_post_disable(bridge, old_state); -+ -+ if (limit) -+ bridge = limit; - } - } - EXPORT_SYMBOL(drm_atomic_bridge_chain_post_disable); - -+static void drm_atomic_bridge_call_pre_enable(struct drm_bridge *bridge, -+ struct drm_atomic_state *old_state) -+{ -+ if (old_state && bridge->funcs->atomic_pre_enable) { -+ struct drm_bridge_state *old_bridge_state; -+ -+ old_bridge_state = -+ drm_atomic_get_old_bridge_state(old_state, -+ bridge); -+ if (WARN_ON(!old_bridge_state)) -+ return; -+ -+ bridge->funcs->atomic_pre_enable(bridge, old_bridge_state); -+ } else if (bridge->funcs->pre_enable) { -+ bridge->funcs->pre_enable(bridge); -+ } -+} -+ - /** - * drm_atomic_bridge_chain_pre_enable - prepares for enabling all bridges in - * the encoder chain -@@ -743,33 +795,62 @@ EXPORT_SYMBOL(drm_atomic_bridge_chain_po - * starting from the last bridge to the first. These are called before calling - * &drm_encoder_helper_funcs.atomic_enable - * -+ * If a bridge sets @pre_enable_upstream_first, then the pre_enable for the -+ * upstream bridge will be called before pre_enable of this bridge. -+ * - * Note: the bridge passed should be the one closest to the encoder - */ - void drm_atomic_bridge_chain_pre_enable(struct drm_bridge *bridge, - struct drm_atomic_state *old_state) - { - struct drm_encoder *encoder; -- struct drm_bridge *iter; -+ struct drm_bridge *iter, *next, *limit; - - if (!bridge) - return; - - encoder = bridge->encoder; -- list_for_each_entry_reverse(iter, &encoder->bridge_chain, chain_node) { -- if (iter->funcs->atomic_pre_enable) { -- struct drm_bridge_state *old_bridge_state; - -- old_bridge_state = -- drm_atomic_get_old_bridge_state(old_state, -- iter); -- if (WARN_ON(!old_bridge_state)) -- return; -+ list_for_each_entry_reverse(iter, &encoder->bridge_chain, chain_node) { -+ if (iter->pre_enable_upstream_first) { -+ next = iter; -+ limit = bridge; -+ list_for_each_entry_from_reverse(next, -+ &encoder->bridge_chain, -+ chain_node) { -+ if (next == bridge) -+ break; -+ -+ if (!next->pre_enable_upstream_first) { -+ /* Found first bridge that does NOT -+ * request upstream to be enabled first -+ */ -+ limit = list_prev_entry(next, chain_node); -+ break; -+ } -+ } -+ -+ list_for_each_entry_from(next, &encoder->bridge_chain, chain_node) { -+ /* Call requested upstream bridge pre_enable -+ * in order. -+ */ -+ if (next == iter) -+ /* At the first bridgge to request upstream -+ * bridges called first. -+ */ -+ break; - -- iter->funcs->atomic_pre_enable(iter, old_bridge_state); -- } else if (iter->funcs->pre_enable) { -- iter->funcs->pre_enable(iter); -+ drm_atomic_bridge_call_pre_enable(next, old_state); -+ } - } - -+ drm_atomic_bridge_call_pre_enable(iter, old_state); -+ -+ if (iter->pre_enable_upstream_first) -+ /* Jump all bridges that we have already pre_enabled -+ */ -+ iter = limit; -+ - if (iter == bridge) - break; - } ---- a/include/drm/drm_bridge.h -+++ b/include/drm/drm_bridge.h -@@ -769,6 +769,14 @@ struct drm_bridge { - */ - bool interlace_allowed; - /** -+ * @pre_enable_upstream_first: The bridge requires that the upstream -+ * bridge @pre_enable function is called before its @pre_enable, -+ * and conversely for post_disable. This is most frequently a -+ * requirement for DSI devices which need the host to be initialised -+ * before the peripheral. -+ */ -+ bool pre_enable_upstream_first; -+ /** - * @ddc: Associated I2C adapter for DDC access, if any. - */ - struct i2c_adapter *ddc; diff --git a/target/linux/bcm27xx/patches-6.1/950-0035-drm-panel-Add-prepare_upstream_first-flag-to-drm_pan.patch b/target/linux/bcm27xx/patches-6.1/950-0035-drm-panel-Add-prepare_upstream_first-flag-to-drm_pan.patch index 6ca65ab3f3c..1e54e613016 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0035-drm-panel-Add-prepare_upstream_first-flag-to-drm_pan.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0035-drm-panel-Add-prepare_upstream_first-flag-to-drm_pan.patch @@ -1,32 +1,33 @@ -From 9ac3eedd8cda7d5f2429edc0bdba137c35e07157 Mon Sep 17 00:00:00 2001 +From 5ea6b17027810ffbdb5bea7d0a2b1d312dd1021c Mon Sep 17 00:00:00 2001 From: Dave Stevenson -Date: Wed, 23 Feb 2022 15:36:56 +0000 -Subject: [PATCH] drm/panel: Add prepare_upstream_first flag to - drm_panel +Date: Mon, 5 Dec 2022 17:33:27 +0000 +Subject: [PATCH] drm/panel: Add prepare_prev_first flag to drm_panel -Mapping to the drm_bridge flag pre_enable_upstream_first, -add a new flag prepare_upstream_first to drm_panel to allow +Mapping to the drm_bridge flag pre_enable_prev_first, +add a new flag prepare_prev_first to drm_panel to allow the panel driver to request that the upstream bridge should be pre_enabled before the panel prepare. Signed-off-by: Dave Stevenson +Reviewed-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/20221205173328.1395350-6-dave.stevenson@raspberrypi.com +Signed-off-by: Maxime Ripard --- - drivers/gpu/drm/bridge/panel.c | 3 +++ + drivers/gpu/drm/bridge/panel.c | 2 ++ include/drm/drm_panel.h | 10 ++++++++++ - 2 files changed, 13 insertions(+) + 2 files changed, 12 insertions(+) --- a/drivers/gpu/drm/bridge/panel.c +++ b/drivers/gpu/drm/bridge/panel.c -@@ -258,6 +258,9 @@ struct drm_bridge *drm_panel_bridge_add_ - panel_bridge->bridge.ops = DRM_BRIDGE_OP_MODES; - panel_bridge->bridge.type = connector_type; +@@ -368,6 +368,8 @@ struct drm_bridge *devm_drm_panel_bridge + devres_free(ptr); + } -+ panel_bridge->bridge.pre_enable_upstream_first = -+ panel->prepare_upstream_first; ++ bridge->pre_enable_prev_first = panel->prepare_prev_first; + - drm_bridge_add(&panel_bridge->bridge); - - return &panel_bridge->bridge; + return bridge; + } + EXPORT_SYMBOL(devm_drm_panel_bridge_add_typed); --- a/include/drm/drm_panel.h +++ b/include/drm/drm_panel.h @@ -196,6 +196,16 @@ struct drm_panel { @@ -35,14 +36,14 @@ Signed-off-by: Dave Stevenson struct list_head list; + + /** -+ * @prepare_upstream_first: ++ * @prepare_prev_first: + * -+ * The upstream controller should be prepared first, before the prepare ++ * The previous controller should be prepared first, before the prepare + * for the panel is called. This is largely required for DSI panels + * where the DSI host controller should be initialised to LP-11 before + * the panel is powered up. + */ -+ bool prepare_upstream_first; ++ bool prepare_prev_first; }; void drm_panel_init(struct drm_panel *panel, struct device *dev, diff --git a/target/linux/bcm27xx/patches-6.1/950-0045-drm-atomic-helpers-remove-legacy_cursor_update-hacks.patch b/target/linux/bcm27xx/patches-6.1/950-0045-drm-atomic-helpers-remove-legacy_cursor_update-hacks.patch index 520d6fa7ebc..8bcbb0db27a 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0045-drm-atomic-helpers-remove-legacy_cursor_update-hacks.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0045-drm-atomic-helpers-remove-legacy_cursor_update-hacks.patch @@ -59,7 +59,7 @@ Signed-off-by: Maxime Ripard --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c -@@ -1608,13 +1608,6 @@ drm_atomic_helper_wait_for_vblanks(struc +@@ -1617,13 +1617,6 @@ drm_atomic_helper_wait_for_vblanks(struc int i, ret; unsigned int crtc_mask = 0; @@ -73,7 +73,7 @@ Signed-off-by: Maxime Ripard for_each_oldnew_crtc_in_state(old_state, crtc, old_crtc_state, new_crtc_state, i) { if (!new_crtc_state->active) continue; -@@ -2264,12 +2257,6 @@ int drm_atomic_helper_setup_commit(struc +@@ -2273,12 +2266,6 @@ int drm_atomic_helper_setup_commit(struc complete_all(&commit->flip_done); continue; } @@ -88,7 +88,7 @@ Signed-off-by: Maxime Ripard commit->event = kzalloc(sizeof(*commit->event), --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c -@@ -7766,6 +7766,19 @@ static int intel_atomic_commit(struct dr +@@ -7765,6 +7765,19 @@ static int intel_atomic_commit(struct dr state->base.legacy_cursor_update = false; } diff --git a/target/linux/bcm27xx/patches-6.1/950-0104-pinctrl-bcm2835-Set-base-to-0-give-expected-gpio-num.patch b/target/linux/bcm27xx/patches-6.1/950-0104-pinctrl-bcm2835-Set-base-to-0-give-expected-gpio-num.patch index b9881364863..5ef7bf624b0 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0104-pinctrl-bcm2835-Set-base-to-0-give-expected-gpio-num.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0104-pinctrl-bcm2835-Set-base-to-0-give-expected-gpio-num.patch @@ -20,7 +20,7 @@ Signed-off-by: Phil Elwell --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c -@@ -393,7 +393,7 @@ static const struct gpio_chip bcm2835_gp +@@ -391,7 +391,7 @@ static const struct gpio_chip bcm2835_gp .get = bcm2835_gpio_get, .set = bcm2835_gpio_set, .set_config = gpiochip_generic_config, @@ -29,7 +29,7 @@ Signed-off-by: Phil Elwell .ngpio = BCM2835_NUM_GPIOS, .can_sleep = false, .of_gpio_ranges_fallback = bcm2835_of_gpio_ranges_fallback, -@@ -410,7 +410,7 @@ static const struct gpio_chip bcm2711_gp +@@ -408,7 +408,7 @@ static const struct gpio_chip bcm2711_gp .get = bcm2835_gpio_get, .set = bcm2835_gpio_set, .set_config = gpiochip_generic_config, diff --git a/target/linux/bcm27xx/patches-6.1/950-0106-Add-dwc_otg-driver.patch b/target/linux/bcm27xx/patches-6.1/950-0106-Add-dwc_otg-driver.patch index 6980592085d..a3d861ec2f8 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0106-Add-dwc_otg-driver.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0106-Add-dwc_otg-driver.patch @@ -4574,7 +4574,7 @@ Signed-off-by: Jonathan Bell + usb_gadget_unregister_driver(&fsg_driver); + + /* Let the unbind and cleanup routines know the thread has exited */ -+ complete_and_exit(&fsg->thread_notifier, 0); ++ kthread_complete_and_exit(&fsg->thread_notifier, 0); +} + + diff --git a/target/linux/bcm27xx/patches-6.1/950-0111-MMC-added-alternative-MMC-driver.patch b/target/linux/bcm27xx/patches-6.1/950-0111-MMC-added-alternative-MMC-driver.patch index 0e14805d5b8..ace12078da7 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0111-MMC-added-alternative-MMC-driver.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0111-MMC-added-alternative-MMC-driver.patch @@ -325,7 +325,7 @@ Signed-off-by: Phil Elwell } --- a/drivers/mmc/core/quirks.h +++ b/drivers/mmc/core/quirks.h -@@ -106,6 +106,14 @@ static const struct mmc_fixup __maybe_un +@@ -129,6 +129,14 @@ static const struct mmc_fixup __maybe_un MMC_FIXUP(CID_NAME_ANY, CID_MANFID_SANDISK_SD, 0x5344, add_quirk_sd, MMC_QUIRK_BROKEN_SD_DISCARD), @@ -2007,9 +2007,9 @@ Signed-off-by: Phil Elwell sdhci_dumpregs(host); --- a/include/linux/mmc/card.h +++ b/include/linux/mmc/card.h -@@ -295,6 +295,8 @@ struct mmc_card { - #define MMC_QUIRK_BROKEN_HPI (1<<13) /* Disable broken HPI support */ +@@ -296,6 +296,8 @@ struct mmc_card { #define MMC_QUIRK_BROKEN_SD_DISCARD (1<<14) /* Disable broken SD discard support */ + #define MMC_QUIRK_BROKEN_SD_CACHE (1<<15) /* Disable broken SD cache support */ +#define MMC_QUIRK_ERASE_BROKEN (1<<31) /* Skip erase */ + diff --git a/target/linux/bcm27xx/patches-6.1/950-0190-xhci-Use-more-event-ring-segment-table-entries.patch b/target/linux/bcm27xx/patches-6.1/950-0190-xhci-Use-more-event-ring-segment-table-entries.patch index c624dfb8da9..cf92e9e9005 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0190-xhci-Use-more-event-ring-segment-table-entries.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0190-xhci-Use-more-event-ring-segment-table-entries.patch @@ -22,7 +22,7 @@ Signed-off-by: Jonathan Bell --- a/drivers/usb/host/xhci-mem.c +++ b/drivers/usb/host/xhci-mem.c -@@ -2501,9 +2501,11 @@ int xhci_mem_init(struct xhci_hcd *xhci, +@@ -2522,9 +2522,11 @@ int xhci_mem_init(struct xhci_hcd *xhci, * Event ring setup: Allocate a normal ring, but also setup * the event ring segment table (ERST). Section 4.9.3. */ @@ -36,7 +36,7 @@ Signed-off-by: Jonathan Bell if (!xhci->event_ring) goto fail; if (xhci_check_trb_in_td_math(xhci) < 0) -@@ -2516,7 +2518,7 @@ int xhci_mem_init(struct xhci_hcd *xhci, +@@ -2537,7 +2539,7 @@ int xhci_mem_init(struct xhci_hcd *xhci, /* set ERST count with the number of entries in the segment table */ val = readl(&xhci->ir_set->erst_size); val &= ERST_SIZE_MASK; diff --git a/target/linux/bcm27xx/patches-6.1/950-0218-pinctrl-bcm2835-Remove-gpiochip-on-error.patch b/target/linux/bcm27xx/patches-6.1/950-0218-pinctrl-bcm2835-Remove-gpiochip-on-error.patch index 1c4dd224029..d44742982c0 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0218-pinctrl-bcm2835-Remove-gpiochip-on-error.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0218-pinctrl-bcm2835-Remove-gpiochip-on-error.patch @@ -14,7 +14,7 @@ Signed-off-by: Phil Elwell --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c -@@ -1357,7 +1357,7 @@ static int bcm2835_pinctrl_probe(struct +@@ -1355,7 +1355,7 @@ static int bcm2835_pinctrl_probe(struct girq->default_type = IRQ_TYPE_NONE; girq->handler = handle_level_irq; diff --git a/target/linux/bcm27xx/patches-6.1/950-0328-staging-vchiq_arm-Add-36-bit-address-support.patch b/target/linux/bcm27xx/patches-6.1/950-0328-staging-vchiq_arm-Add-36-bit-address-support.patch index 5ecd2d357d9..a9e9991d1a9 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0328-staging-vchiq_arm-Add-36-bit-address-support.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0328-staging-vchiq_arm-Add-36-bit-address-support.patch @@ -158,14 +158,14 @@ Signed-off-by: Phil Elwell pagelistinfo->scatterlist_mapped = 0; @@ -468,6 +515,7 @@ free_pagelist(struct vchiq_instance *ins - int vchiq_platform_init(struct platform_device *pdev, struct vchiq_state *state) + static int vchiq_platform_init(struct platform_device *pdev, struct vchiq_state *state) { struct device *dev = &pdev->dev; + struct device *dma_dev = NULL; struct vchiq_drvdata *drvdata = platform_get_drvdata(pdev); struct rpi_firmware *fw = drvdata->fw; struct vchiq_slot_zero *vchiq_slot_zero; -@@ -489,6 +537,24 @@ int vchiq_platform_init(struct platform_ +@@ -489,6 +537,24 @@ static int vchiq_platform_init(struct pl g_cache_line_size = drvdata->cache_line_size; g_fragments_size = 2 * g_cache_line_size; @@ -190,7 +190,7 @@ Signed-off-by: Phil Elwell /* Allocate space for the channels in coherent memory */ slot_mem_size = PAGE_ALIGN(TOTAL_SLOTS * VCHIQ_SLOT_SIZE); frag_mem_size = PAGE_ALIGN(g_fragments_size * MAX_FRAGMENTS); -@@ -501,13 +567,14 @@ int vchiq_platform_init(struct platform_ +@@ -501,13 +567,14 @@ static int vchiq_platform_init(struct pl } WARN_ON(((unsigned long)slot_mem & (PAGE_SIZE - 1)) != 0); @@ -206,7 +206,7 @@ Signed-off-by: Phil Elwell vchiq_slot_zero->platform_data[VCHIQ_PLATFORM_FRAGMENTS_COUNT_IDX] = MAX_FRAGMENTS; -@@ -541,7 +608,6 @@ int vchiq_platform_init(struct platform_ +@@ -541,7 +608,6 @@ static int vchiq_platform_init(struct pl } /* Send the base address of the slots to VideoCore */ @@ -214,7 +214,7 @@ Signed-off-by: Phil Elwell err = rpi_firmware_property(fw, RPI_FIRMWARE_VCHIQ_INIT, &channelbase, sizeof(channelbase)); if (err || channelbase) { -@@ -549,6 +615,8 @@ int vchiq_platform_init(struct platform_ +@@ -549,6 +615,8 @@ static int vchiq_platform_init(struct pl return err ? : -ENXIO; } diff --git a/target/linux/bcm27xx/patches-6.1/950-0330-staging-vchiq_arm-Usa-a-DMA-pool-for-small-bulks.patch b/target/linux/bcm27xx/patches-6.1/950-0330-staging-vchiq_arm-Usa-a-DMA-pool-for-small-bulks.patch index b4f99d04ca2..0f0f2474806 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0330-staging-vchiq_arm-Usa-a-DMA-pool-for-small-bulks.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0330-staging-vchiq_arm-Usa-a-DMA-pool-for-small-bulks.patch @@ -102,7 +102,7 @@ Signed-off-by: Oliver Gjoneski pagelistinfo->dma_dir = (type == PAGELIST_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE; pagelistinfo->num_pages = num_pages; -@@ -616,6 +634,13 @@ int vchiq_platform_init(struct platform_ +@@ -616,6 +634,13 @@ static int vchiq_platform_init(struct pl } g_dma_dev = dma_dev ?: dev; diff --git a/target/linux/bcm27xx/patches-6.1/950-0332-drm-panel-simple-Add-a-timing-for-the-Raspberry-Pi-7.patch b/target/linux/bcm27xx/patches-6.1/950-0332-drm-panel-simple-Add-a-timing-for-the-Raspberry-Pi-7.patch index aa7bfe130b9..4ce71a86aa7 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0332-drm-panel-simple-Add-a-timing-for-the-Raspberry-Pi-7.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0332-drm-panel-simple-Add-a-timing-for-the-Raspberry-Pi-7.patch @@ -15,7 +15,7 @@ Signed-off-by: Dave Stevenson --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c -@@ -3188,6 +3188,31 @@ static const struct panel_desc qishenglo +@@ -3190,6 +3190,31 @@ static const struct panel_desc qishenglo .connector_type = DRM_MODE_CONNECTOR_DPI, }; @@ -47,7 +47,7 @@ Signed-off-by: Dave Stevenson static const struct display_timing rocktech_rk070er9427_timing = { .pixelclock = { 26400000, 33300000, 46800000 }, .hactive = { 800, 800, 800 }, -@@ -4219,6 +4244,9 @@ static const struct of_device_id platfor +@@ -4221,6 +4246,9 @@ static const struct of_device_id platfor .compatible = "qishenglong,gopher2b-lcd", .data = &qishenglong_gopher2b_lcd, }, { diff --git a/target/linux/bcm27xx/patches-6.1/950-0359-xhci-quirks-add-link-TRB-quirk-for-VL805.patch b/target/linux/bcm27xx/patches-6.1/950-0359-xhci-quirks-add-link-TRB-quirk-for-VL805.patch index 10a068df53a..b90f9f7d8b8 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0359-xhci-quirks-add-link-TRB-quirk-for-VL805.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0359-xhci-quirks-add-link-TRB-quirk-for-VL805.patch @@ -50,11 +50,11 @@ Signed-off-by: Jonathan Bell addr = xhci_trb_virt_to_dma(new_seg, new_deq); --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h -@@ -1899,6 +1899,7 @@ struct xhci_hcd { - #define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42) - #define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43) +@@ -1901,6 +1901,7 @@ struct xhci_hcd { #define XHCI_RESET_TO_DEFAULT BIT_ULL(44) -+#define XHCI_AVOID_DQ_ON_LINK BIT_ULL(45) + #define XHCI_ZHAOXIN_TRB_FETCH BIT_ULL(45) + #define XHCI_ZHAOXIN_HOST BIT_ULL(46) ++#define XHCI_AVOID_DQ_ON_LINK BIT_ULL(47) unsigned int num_active_eps; unsigned int limit_active_eps; diff --git a/target/linux/bcm27xx/patches-6.1/950-0362-usb-xhci-add-VLI_TRB_CACHE_BUG-quirk.patch b/target/linux/bcm27xx/patches-6.1/950-0362-usb-xhci-add-VLI_TRB_CACHE_BUG-quirk.patch index 22dc08ff98d..df2cc5d79b6 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0362-usb-xhci-add-VLI_TRB_CACHE_BUG-quirk.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0362-usb-xhci-add-VLI_TRB_CACHE_BUG-quirk.patch @@ -63,11 +63,11 @@ Signed-off-by: Jonathan Bell if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h -@@ -1901,6 +1901,7 @@ struct xhci_hcd { - #define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43) - #define XHCI_RESET_TO_DEFAULT BIT_ULL(44) - #define XHCI_AVOID_DQ_ON_LINK BIT_ULL(45) -+#define XHCI_VLI_TRB_CACHE_BUG BIT_ULL(46) +@@ -1903,6 +1903,7 @@ struct xhci_hcd { + #define XHCI_ZHAOXIN_TRB_FETCH BIT_ULL(45) + #define XHCI_ZHAOXIN_HOST BIT_ULL(46) + #define XHCI_AVOID_DQ_ON_LINK BIT_ULL(47) ++#define XHCI_VLI_TRB_CACHE_BUG BIT_ULL(48) unsigned int num_active_eps; unsigned int limit_active_eps; diff --git a/target/linux/bcm27xx/patches-6.1/950-0383-drm-panel-simple-add-Geekworm-MZP280-Panel.patch b/target/linux/bcm27xx/patches-6.1/950-0383-drm-panel-simple-add-Geekworm-MZP280-Panel.patch index dfa2e67b70a..5b7d4cb218d 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0383-drm-panel-simple-add-Geekworm-MZP280-Panel.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0383-drm-panel-simple-add-Geekworm-MZP280-Panel.patch @@ -46,7 +46,7 @@ Acked-by: Maxime Ripard static const struct drm_display_mode giantplus_gpg482739qs5_mode = { .clock = 9000, .hdisplay = 480, -@@ -4103,6 +4129,9 @@ static const struct of_device_id platfor +@@ -4105,6 +4131,9 @@ static const struct of_device_id platfor .compatible = "friendlyarm,hd702e", .data = &friendlyarm_hd702e, }, { diff --git a/target/linux/bcm27xx/patches-6.1/950-0390-usb-xhci-add-a-quirk-for-Superspeed-bulk-OUT-transfe.patch b/target/linux/bcm27xx/patches-6.1/950-0390-usb-xhci-add-a-quirk-for-Superspeed-bulk-OUT-transfe.patch index bad37906307..7ec1e3843e3 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0390-usb-xhci-add-a-quirk-for-Superspeed-bulk-OUT-transfe.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0390-usb-xhci-add-a-quirk-for-Superspeed-bulk-OUT-transfe.patch @@ -86,11 +86,11 @@ Signed-off-by: Jonathan Bell first_trb = false; --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h -@@ -1902,6 +1902,7 @@ struct xhci_hcd { - #define XHCI_RESET_TO_DEFAULT BIT_ULL(44) - #define XHCI_AVOID_DQ_ON_LINK BIT_ULL(45) - #define XHCI_VLI_TRB_CACHE_BUG BIT_ULL(46) -+#define XHCI_VLI_SS_BULK_OUT_BUG BIT_ULL(47) +@@ -1904,6 +1904,7 @@ struct xhci_hcd { + #define XHCI_ZHAOXIN_HOST BIT_ULL(46) + #define XHCI_AVOID_DQ_ON_LINK BIT_ULL(47) + #define XHCI_VLI_TRB_CACHE_BUG BIT_ULL(48) ++#define XHCI_VLI_SS_BULK_OUT_BUG BIT_ULL(49) unsigned int num_active_eps; unsigned int limit_active_eps; diff --git a/target/linux/bcm27xx/patches-6.1/950-0402-pinctrl-bcm2835-Only-return-non-GPIOs-to-inputs.patch b/target/linux/bcm27xx/patches-6.1/950-0402-pinctrl-bcm2835-Only-return-non-GPIOs-to-inputs.patch index 449406193a5..bd199b76e24 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0402-pinctrl-bcm2835-Only-return-non-GPIOs-to-inputs.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0402-pinctrl-bcm2835-Only-return-non-GPIOs-to-inputs.patch @@ -13,7 +13,7 @@ Signed-off-by: Phil Elwell --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c -@@ -928,9 +928,12 @@ static int bcm2835_pmx_free(struct pinct +@@ -926,9 +926,12 @@ static int bcm2835_pmx_free(struct pinct unsigned offset) { struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); @@ -28,7 +28,7 @@ Signed-off-by: Phil Elwell return 0; } -@@ -972,10 +975,7 @@ static void bcm2835_pmx_gpio_disable_fre +@@ -970,10 +973,7 @@ static void bcm2835_pmx_gpio_disable_fre struct pinctrl_gpio_range *range, unsigned offset) { diff --git a/target/linux/bcm27xx/patches-6.1/950-0404-drm-panel-panel-ilitek9881c-Add-prepare_upstream_fir.patch b/target/linux/bcm27xx/patches-6.1/950-0404-drm-panel-panel-ilitek9881c-Add-prepare_upstream_fir.patch index 53373f6b5c8..ce66c7d2eef 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0404-drm-panel-panel-ilitek9881c-Add-prepare_upstream_fir.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0404-drm-panel-panel-ilitek9881c-Add-prepare_upstream_fir.patch @@ -2,12 +2,12 @@ From 942d55434af46aebe8f5508995807253a6b235b3 Mon Sep 17 00:00:00 2001 From: Dave Stevenson Date: Thu, 31 Mar 2022 12:05:04 +0100 Subject: [PATCH] drm/panel: panel-ilitek9881c: Add - prepare_upstream_first flag + prepare_prev_first flag The panel sends MIPI DCS commands during prepare and is expecting the bus to remain in LP-11 state in-between. -Set the prepare_upstream_first flag so that the upstream DSI host +Set the prepare_prev_first flag so that the upstream DSI host is prepared / pre_enabled first, and therefore the bus is in a defined state. @@ -22,7 +22,7 @@ Signed-off-by: Dave Stevenson ctx->dsi = dsi; ctx->desc = of_device_get_match_data(&dsi->dev); -+ ctx->panel.prepare_upstream_first = true; ++ ctx->panel.prepare_prev_first = true; drm_panel_init(&ctx->panel, &dsi->dev, &ili9881c_funcs, DRM_MODE_CONNECTOR_DSI); diff --git a/target/linux/bcm27xx/patches-6.1/950-0439-nvmem-Use-NVMEM_DEVID_AUTO.patch b/target/linux/bcm27xx/patches-6.1/950-0439-nvmem-Use-NVMEM_DEVID_AUTO.patch deleted file mode 100644 index 1758d3e1627..00000000000 --- a/target/linux/bcm27xx/patches-6.1/950-0439-nvmem-Use-NVMEM_DEVID_AUTO.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 10fcafcad54e1d055b6b67881a5b52b95dbd2da3 Mon Sep 17 00:00:00 2001 -From: Phil Elwell -Date: Fri, 7 Oct 2022 10:38:31 +0100 -Subject: [PATCH] nvmem: Use NVMEM_DEVID_AUTO - -It is reasonable to declare multiple nvmem blocks. Unless a unique 'id' -is passed in for each block there may be name clashes. - -Avoid this by using the magic token NVMEM_DEVID_AUTO. - -Fixes: 5a3fa75a4d9cb ("nvmem: Add driver to expose reserved memory as nvmem") - -Signed-off-by: Phil Elwell ---- - drivers/nvmem/rmem.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/nvmem/rmem.c -+++ b/drivers/nvmem/rmem.c -@@ -71,6 +71,7 @@ static int rmem_probe(struct platform_de - config.dev = dev; - config.priv = priv; - config.name = "rmem"; -+ config.id = NVMEM_DEVID_AUTO; - config.size = mem->size; - config.reg_read = rmem_read; - diff --git a/target/linux/bcm27xx/patches-6.1/950-0469-usb-xhci-add-XHCI_VLI_HUB_TT_QUIRK.patch b/target/linux/bcm27xx/patches-6.1/950-0469-usb-xhci-add-XHCI_VLI_HUB_TT_QUIRK.patch index 474698e9130..29f4ce16849 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0469-usb-xhci-add-XHCI_VLI_HUB_TT_QUIRK.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0469-usb-xhci-add-XHCI_VLI_HUB_TT_QUIRK.patch @@ -109,11 +109,11 @@ Signed-off-by: Jonathan Bell return 0; --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h -@@ -1903,6 +1903,7 @@ struct xhci_hcd { - #define XHCI_AVOID_DQ_ON_LINK BIT_ULL(45) - #define XHCI_VLI_TRB_CACHE_BUG BIT_ULL(46) - #define XHCI_VLI_SS_BULK_OUT_BUG BIT_ULL(47) -+#define XHCI_VLI_HUB_TT_QUIRK BIT_ULL(48) +@@ -1905,6 +1905,7 @@ struct xhci_hcd { + #define XHCI_AVOID_DQ_ON_LINK BIT_ULL(47) + #define XHCI_VLI_TRB_CACHE_BUG BIT_ULL(48) + #define XHCI_VLI_SS_BULK_OUT_BUG BIT_ULL(49) ++#define XHCI_VLI_HUB_TT_QUIRK BIT_ULL(50) unsigned int num_active_eps; unsigned int limit_active_eps; diff --git a/target/linux/bcm27xx/patches-6.1/950-0477-drm-atomic-Constify-the-old-new-state-accessors.patch b/target/linux/bcm27xx/patches-6.1/950-0477-drm-atomic-Constify-the-old-new-state-accessors.patch index 983c54fae12..f12a952ec2d 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0477-drm-atomic-Constify-the-old-new-state-accessors.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0477-drm-atomic-Constify-the-old-new-state-accessors.patch @@ -16,7 +16,7 @@ Link: https://patchwork.freedesktop.org/patch/msgid/20221123-rpi-kunit-tests-v1- --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c -@@ -880,7 +880,7 @@ EXPORT_SYMBOL(drm_atomic_get_private_obj +@@ -889,7 +889,7 @@ EXPORT_SYMBOL(drm_atomic_get_private_obj * or NULL if the private_obj is not part of the global atomic state. */ struct drm_private_state * @@ -25,7 +25,7 @@ Link: https://patchwork.freedesktop.org/patch/msgid/20221123-rpi-kunit-tests-v1- struct drm_private_obj *obj) { int i; -@@ -902,7 +902,7 @@ EXPORT_SYMBOL(drm_atomic_get_old_private +@@ -911,7 +911,7 @@ EXPORT_SYMBOL(drm_atomic_get_old_private * or NULL if the private_obj is not part of the global atomic state. */ struct drm_private_state * @@ -34,7 +34,7 @@ Link: https://patchwork.freedesktop.org/patch/msgid/20221123-rpi-kunit-tests-v1- struct drm_private_obj *obj) { int i; -@@ -934,7 +934,7 @@ EXPORT_SYMBOL(drm_atomic_get_new_private +@@ -943,7 +943,7 @@ EXPORT_SYMBOL(drm_atomic_get_new_private * not connected. */ struct drm_connector * @@ -43,7 +43,7 @@ Link: https://patchwork.freedesktop.org/patch/msgid/20221123-rpi-kunit-tests-v1- struct drm_encoder *encoder) { struct drm_connector_state *conn_state; -@@ -968,7 +968,7 @@ EXPORT_SYMBOL(drm_atomic_get_old_connect +@@ -977,7 +977,7 @@ EXPORT_SYMBOL(drm_atomic_get_old_connect * not connected. */ struct drm_connector * @@ -52,7 +52,7 @@ Link: https://patchwork.freedesktop.org/patch/msgid/20221123-rpi-kunit-tests-v1- struct drm_encoder *encoder) { struct drm_connector_state *conn_state; -@@ -1118,7 +1118,7 @@ EXPORT_SYMBOL(drm_atomic_get_bridge_stat +@@ -1127,7 +1127,7 @@ EXPORT_SYMBOL(drm_atomic_get_bridge_stat * the bridge is not part of the global atomic state. */ struct drm_bridge_state * @@ -61,7 +61,7 @@ Link: https://patchwork.freedesktop.org/patch/msgid/20221123-rpi-kunit-tests-v1- struct drm_bridge *bridge) { struct drm_private_state *obj_state; -@@ -1140,7 +1140,7 @@ EXPORT_SYMBOL(drm_atomic_get_old_bridge_ +@@ -1149,7 +1149,7 @@ EXPORT_SYMBOL(drm_atomic_get_old_bridge_ * the bridge is not part of the global atomic state. */ struct drm_bridge_state * diff --git a/target/linux/bcm27xx/patches-6.1/950-0521-drm-panel-simple-Add-Innolux-AT056tN53V1-5.6-VGA.patch b/target/linux/bcm27xx/patches-6.1/950-0521-drm-panel-simple-Add-Innolux-AT056tN53V1-5.6-VGA.patch index 5ce1d8a190d..411c9c7c109 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0521-drm-panel-simple-Add-Innolux-AT056tN53V1-5.6-VGA.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0521-drm-panel-simple-Add-Innolux-AT056tN53V1-5.6-VGA.patch @@ -126,7 +126,7 @@ Signed-off-by: Phil Elwell - MEDIA_BUS_FMT_RGB666_1X24_CPADHI --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c -@@ -2135,6 +2135,38 @@ static const struct panel_desc innolux_a +@@ -2136,6 +2136,38 @@ static const struct panel_desc innolux_a .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, }; @@ -165,7 +165,7 @@ Signed-off-by: Phil Elwell static const struct drm_display_mode innolux_at070tn92_mode = { .clock = 33333, .hdisplay = 800, -@@ -4139,6 +4171,9 @@ static const struct of_device_id platfor +@@ -4141,6 +4173,9 @@ static const struct of_device_id platfor .compatible = "innolux,at043tn24", .data = &innolux_at043tn24, }, { diff --git a/target/linux/bcm27xx/patches-6.1/950-0698-serial-8250-Add-NOMSI-bug-for-bcm2835aux.patch b/target/linux/bcm27xx/patches-6.1/950-0698-serial-8250-Add-NOMSI-bug-for-bcm2835aux.patch index 885806f9761..6f62736b08b 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0698-serial-8250-Add-NOMSI-bug-for-bcm2835aux.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0698-serial-8250-Add-NOMSI-bug-for-bcm2835aux.patch @@ -20,9 +20,9 @@ Signed-off-by: Phil Elwell --- a/drivers/tty/serial/8250/8250.h +++ b/drivers/tty/serial/8250/8250.h -@@ -93,6 +93,7 @@ struct serial8250_config { +@@ -92,6 +92,7 @@ struct serial8250_config { + #define UART_BUG_NOMSR BIT(2) /* UART has buggy MSR status bits (Au1x00) */ #define UART_BUG_THRE BIT(3) /* UART has buggy THRE reassertion */ - #define UART_BUG_PARITY BIT(4) /* UART mishandles parity if FIFO enabled */ #define UART_BUG_TXRACE BIT(5) /* UART Tx fails to set remote DR */ +#define UART_BUG_NOMSI BIT(6) /* UART has no modem status interrupt */ diff --git a/target/linux/bcm27xx/patches-6.1/950-0699-Bluetooth-hci_sync-Add-fallback-bd-address-prop.patch b/target/linux/bcm27xx/patches-6.1/950-0699-Bluetooth-hci_sync-Add-fallback-bd-address-prop.patch index 6fd82ce0112..fd847817297 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0699-Bluetooth-hci_sync-Add-fallback-bd-address-prop.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0699-Bluetooth-hci_sync-Add-fallback-bd-address-prop.patch @@ -31,11 +31,11 @@ Signed-off-by: Phil Elwell @@ -4568,7 +4569,9 @@ static int hci_dev_setup_sync(struct hci if (!ret) { - if (test_bit(HCI_QUIRK_USE_BDADDR_PROPERTY, &hdev->quirks)) { -- if (!bacmp(&hdev->public_addr, BDADDR_ANY)) -+ if (!bacmp(&hdev->public_addr, BDADDR_ANY) && -+ (invalid_bdaddr || -+ !fwnode_property_present(fwnode, "fallback-bd-address"))) - hci_dev_get_bd_addr_from_property(hdev); + if (test_bit(HCI_QUIRK_USE_BDADDR_PROPERTY, &hdev->quirks) && +- !bacmp(&hdev->public_addr, BDADDR_ANY)) ++ !bacmp(&hdev->public_addr, BDADDR_ANY) && ++ (invalid_bdaddr || ++ !fwnode_property_present(fwnode, "fallback-bd-address"))) + hci_dev_get_bd_addr_from_property(hdev); - if (bacmp(&hdev->public_addr, BDADDR_ANY) && + if ((invalid_bdaddr || diff --git a/target/linux/bcm27xx/patches-6.1/950-0704-pinctrl-bcm2835-Workaround-for-edge-IRQ-loss.patch b/target/linux/bcm27xx/patches-6.1/950-0704-pinctrl-bcm2835-Workaround-for-edge-IRQ-loss.patch index 65345f480e7..16028b897ca 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0704-pinctrl-bcm2835-Workaround-for-edge-IRQ-loss.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0704-pinctrl-bcm2835-Workaround-for-edge-IRQ-loss.patch @@ -19,7 +19,7 @@ Signed-off-by: Phil Elwell --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c -@@ -422,15 +422,32 @@ static void bcm2835_gpio_irq_handle_bank +@@ -420,15 +420,32 @@ static void bcm2835_gpio_irq_handle_bank unsigned long events; unsigned offset; unsigned gpio; @@ -52,7 +52,7 @@ Signed-off-by: Phil Elwell } static void bcm2835_gpio_irq_handler(struct irq_desc *desc) -@@ -670,11 +687,7 @@ static int bcm2835_gpio_irq_set_type(str +@@ -668,11 +685,7 @@ static int bcm2835_gpio_irq_set_type(str static void bcm2835_gpio_irq_ack(struct irq_data *data) { diff --git a/target/linux/bcm4908/patches-6.1/040-mtd-parsers-refer-to-ARCH_BCMBCA-instead-of-ARCH_BCM.patch b/target/linux/bcm4908/patches-6.1/040-mtd-parsers-refer-to-ARCH_BCMBCA-instead-of-ARCH_BCM.patch deleted file mode 100644 index ff56aacc7c3..00000000000 --- a/target/linux/bcm4908/patches-6.1/040-mtd-parsers-refer-to-ARCH_BCMBCA-instead-of-ARCH_BCM.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 085679b15b5af65f9610f619afde41da0f966194 Mon Sep 17 00:00:00 2001 -From: Lukas Bulwahn -Date: Wed, 16 Nov 2022 13:49:32 +0100 -Subject: [PATCH] mtd: parsers: refer to ARCH_BCMBCA instead of ARCH_BCM4908 - -Commit dd5c672d7ca9 ("arm64: bcmbca: Merge ARCH_BCM4908 to ARCH_BCMBCA") -removes config ARCH_BCM4908 as config ARCH_BCMBCA has the same intent. - -Probably due to concurrent development, commit 002181f5b150 ("mtd: parsers: -add Broadcom's U-Boot parser") introduces 'Broadcom's U-Boot partition -parser' that depends on ARCH_BCM4908, but this use was not visible during -the config refactoring from the commit above. Hence, these two changes -create a reference to a non-existing config symbol. - -Adjust the MTD_BRCM_U_BOOT definition to refer to ARCH_BCMBCA instead of -ARCH_BCM4908 to remove the reference to the non-existing config symbol -ARCH_BCM4908. - -Signed-off-by: Lukas Bulwahn -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20221116124932.4748-1-lukas.bulwahn@gmail.com ---- - drivers/mtd/parsers/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/mtd/parsers/Kconfig -+++ b/drivers/mtd/parsers/Kconfig -@@ -22,7 +22,7 @@ config MTD_BCM63XX_PARTS - - config MTD_BRCM_U_BOOT - tristate "Broadcom's U-Boot partition parser" -- depends on ARCH_BCM4908 || COMPILE_TEST -+ depends on ARCH_BCMBCA || COMPILE_TEST - help - Broadcom uses a custom way of storing U-Boot environment variables. - They are placed inside U-Boot partition itself at unspecified offset. diff --git a/target/linux/bcm53xx/patches-6.1/130-ARM-dts-BCM53573-Fix-Ethernet-info-for-Luxul-devices.patch b/target/linux/bcm53xx/patches-5.15/037-v6.6-0009-ARM-dts-BCM53573-Fix-Ethernet-info-for-Luxul-devices.patch similarity index 88% rename from target/linux/bcm53xx/patches-6.1/130-ARM-dts-BCM53573-Fix-Ethernet-info-for-Luxul-devices.patch rename to target/linux/bcm53xx/patches-5.15/037-v6.6-0009-ARM-dts-BCM53573-Fix-Ethernet-info-for-Luxul-devices.patch index 381a8c38943..07dd9296b69 100644 --- a/target/linux/bcm53xx/patches-6.1/130-ARM-dts-BCM53573-Fix-Ethernet-info-for-Luxul-devices.patch +++ b/target/linux/bcm53xx/patches-5.15/037-v6.6-0009-ARM-dts-BCM53573-Fix-Ethernet-info-for-Luxul-devices.patch @@ -1,5 +1,6 @@ +From 44ad8207806973f4e4f7d870fff36cc01f494250 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 13 Jul 2023 13:05:44 +0200 +Date: Thu, 13 Jul 2023 13:11:45 +0200 Subject: [PATCH] ARM: dts: BCM53573: Fix Ethernet info for Luxul devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 @@ -27,6 +28,8 @@ to work properly. Fixes: 9fb90ae6cae7 ("ARM: dts: BCM53573: Describe on-SoC BCM53125 rev 4 switch") Signed-off-by: RafaÅ‚ MiÅ‚ecki +Link: https://lore.kernel.org/r/20230713111145.14864-1-zajec5@gmail.com +Signed-off-by: Florian Fainelli --- .../boot/dts/broadcom/bcm47189-luxul-xap-1440.dts | 13 +++++++++++++ .../boot/dts/broadcom/bcm47189-luxul-xap-810.dts | 13 +++++++++++++ diff --git a/target/linux/bcm53xx/patches-5.15/037-v6.6-0010-ARM-dts-bcm5301x-Add-SEAMA-compatibles.patch b/target/linux/bcm53xx/patches-5.15/037-v6.6-0010-ARM-dts-bcm5301x-Add-SEAMA-compatibles.patch new file mode 100644 index 00000000000..f23873e1112 --- /dev/null +++ b/target/linux/bcm53xx/patches-5.15/037-v6.6-0010-ARM-dts-bcm5301x-Add-SEAMA-compatibles.patch @@ -0,0 +1,36 @@ +From 72ec77d74d28be7359ef77971cdee38b60af9e49 Mon Sep 17 00:00:00 2001 +From: Linus Walleij +Date: Thu, 13 Jul 2023 00:16:42 +0200 +Subject: [PATCH] ARM: dts: bcm5301x: Add SEAMA compatibles + +This adds SEAMA compatibles to the firmware partition of these +two D-Link devices. + +Signed-off-by: Linus Walleij +Link: https://lore.kernel.org/r/20230713-seama-partitions-v4-2-69e577453d40@linaro.org +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-885l.dts | 1 + + arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-890l.dts | 1 + + 2 files changed, 2 insertions(+) + +--- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts ++++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts +@@ -33,6 +33,7 @@ + #size-cells = <1>; + + partition@0 { ++ compatible = "seama"; + label = "firmware"; + reg = <0x00000000 0x08000000>; + }; +--- a/arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts ++++ b/arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts +@@ -149,6 +149,7 @@ + * partitions: this device uses SEAMA. + */ + firmware@0 { ++ compatible = "seama"; + label = "firmware"; + reg = <0x00000000 0x08000000>; + }; diff --git a/target/linux/bcm53xx/patches-5.15/037-v6.6-0011-ARM-dts-BCM53573-Fix-Tenda-AC9-switch-CPU-port.patch b/target/linux/bcm53xx/patches-5.15/037-v6.6-0011-ARM-dts-BCM53573-Fix-Tenda-AC9-switch-CPU-port.patch new file mode 100644 index 00000000000..d5cb817e8e2 --- /dev/null +++ b/target/linux/bcm53xx/patches-5.15/037-v6.6-0011-ARM-dts-BCM53573-Fix-Tenda-AC9-switch-CPU-port.patch @@ -0,0 +1,31 @@ +From 7141209db9c335ab261a17933809a3e660ebdc12 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Sun, 23 Jul 2023 21:54:14 +0200 +Subject: [PATCH] ARM: dts: BCM53573: Fix Tenda AC9 switch CPU port +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Primary Ethernet interface is connected to the port 8 (not 5). + +Fixes: 64612828628c ("ARM: dts: BCM53573: Add Tenda AC9 switch ports") +Signed-off-by: RafaÅ‚ MiÅ‚ecki +Link: https://lore.kernel.org/r/20230723195416.7831-1-zajec5@gmail.com +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/broadcom/bcm47189-tenda-ac9.dts | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts ++++ b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts +@@ -135,8 +135,8 @@ + label = "lan4"; + }; + +- port@5 { +- reg = <5>; ++ port@8 { ++ reg = <8>; + label = "cpu"; + ethernet = <&gmac0>; + }; diff --git a/target/linux/bcm53xx/patches-5.15/037-v6.6-0012-ARM-dts-BCM53573-Describe-BCM53125-switch-ports-in-t.patch b/target/linux/bcm53xx/patches-5.15/037-v6.6-0012-ARM-dts-BCM53573-Describe-BCM53125-switch-ports-in-t.patch new file mode 100644 index 00000000000..ab27495078a --- /dev/null +++ b/target/linux/bcm53xx/patches-5.15/037-v6.6-0012-ARM-dts-BCM53573-Describe-BCM53125-switch-ports-in-t.patch @@ -0,0 +1,97 @@ +From 8d6b61ecad2f1c939813c5c4517d53e04672dc48 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Sun, 23 Jul 2023 21:54:15 +0200 +Subject: [PATCH] ARM: dts: BCM53573: Describe BCM53125 switch ports in the + main DTS +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +BCM53125 always has 5 ports with GPHYs (for LAN/WAN ports) and 2 IMP +ports. It seems the best place to describe that in the main .dtsi. +Device specific bits can go to device .dts files. This will help +avoiding some code duplication. + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +Link: https://lore.kernel.org/r/20230723195416.7831-2-zajec5@gmail.com +Signed-off-by: Florian Fainelli +--- + .../boot/dts/broadcom/bcm47189-tenda-ac9.dts | 7 ----- + arch/arm/boot/dts/broadcom/bcm53573.dtsi | 26 ++++++++++++++++++- + 2 files changed, 25 insertions(+), 8 deletions(-) + +--- a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts ++++ b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts +@@ -111,34 +111,27 @@ + + ports { + port@0 { +- reg = <0>; + label = "wan"; + }; + + port@1 { +- reg = <1>; + label = "lan1"; + }; + + port@2 { +- reg = <2>; + label = "lan2"; + }; + + port@3 { +- reg = <3>; + label = "lan3"; + }; + + port@4 { +- reg = <4>; + label = "lan4"; + }; + + port@8 { +- reg = <8>; + label = "cpu"; +- ethernet = <&gmac0>; + }; + }; + }; +--- a/arch/arm/boot/dts/bcm53573.dtsi ++++ b/arch/arm/boot/dts/bcm53573.dtsi +@@ -192,10 +192,34 @@ + + status = "disabled"; + +- /* ports are defined in board DTS */ + ports { + #address-cells = <1>; + #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ }; ++ ++ port@2 { ++ reg = <2>; ++ }; ++ ++ port@3 { ++ reg = <3>; ++ }; ++ ++ port@4 { ++ reg = <4>; ++ }; ++ ++ port@8 { ++ reg = <8>; ++ ethernet = <&gmac0>; ++ }; + }; + }; + }; diff --git a/target/linux/bcm53xx/patches-5.15/037-v6.6-0013-ARM-dts-BCM53573-Add-BCM53125-switch-port-5.patch b/target/linux/bcm53xx/patches-5.15/037-v6.6-0013-ARM-dts-BCM53573-Add-BCM53125-switch-port-5.patch new file mode 100644 index 00000000000..cc9e86ac751 --- /dev/null +++ b/target/linux/bcm53xx/patches-5.15/037-v6.6-0013-ARM-dts-BCM53573-Add-BCM53125-switch-port-5.patch @@ -0,0 +1,36 @@ +From d95b1caeea194962220db1778ce7fe71cdba788b Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Sun, 23 Jul 2023 21:54:16 +0200 +Subject: [PATCH] ARM: dts: BCM53573: Add BCM53125 switch port 5 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +It's connected to the extra Ethernet interface. + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +Link: https://lore.kernel.org/r/20230723195416.7831-3-zajec5@gmail.com +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/broadcom/bcm53573.dtsi | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/arch/arm/boot/dts/bcm53573.dtsi ++++ b/arch/arm/boot/dts/bcm53573.dtsi +@@ -216,6 +216,16 @@ + reg = <4>; + }; + ++ port@5 { ++ reg = <5>; ++ ethernet = <&gmac1>; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++ }; ++ + port@8 { + reg = <8>; + ethernet = <&gmac0>; diff --git a/target/linux/bcm53xx/patches-5.15/037-v6.6-0014-ARM-dts-BCM53573-Add-Ethernet-interfaces-links.patch b/target/linux/bcm53xx/patches-5.15/037-v6.6-0014-ARM-dts-BCM53573-Add-Ethernet-interfaces-links.patch new file mode 100644 index 00000000000..f97d4edd754 --- /dev/null +++ b/target/linux/bcm53xx/patches-5.15/037-v6.6-0014-ARM-dts-BCM53573-Add-Ethernet-interfaces-links.patch @@ -0,0 +1,73 @@ +From e0ae343a2c1b782a346d9b844ea65e1d49c428b2 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Mon, 24 Jul 2023 12:12:27 +0200 +Subject: [PATCH] ARM: dts: BCM53573: Add Ethernet interfaces links +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +BCM53573 has 2 Ethernet interfaces each connected to one of switch ports +in the default design. They both use fixed links. + +An exception are Luxul XAP devices that have switch replaced by a single +PHY. + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +Link: https://lore.kernel.org/r/20230724101227.5420-1-zajec5@gmail.com +Signed-off-by: Florian Fainelli +--- + .../boot/dts/broadcom/bcm47189-luxul-xap-1440.dts | 2 ++ + .../arm/boot/dts/broadcom/bcm47189-luxul-xap-810.dts | 2 ++ + arch/arm/boot/dts/broadcom/bcm53573.dtsi | 12 ++++++++++++ + 3 files changed, 16 insertions(+) + +--- a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts ++++ b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts +@@ -50,6 +50,8 @@ + phy-mode = "rgmii"; + phy-handle = <&bcm54210e>; + ++ /delete-node/ fixed-link; ++ + mdio { + /delete-node/ switch@1e; + +--- a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts ++++ b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts +@@ -86,6 +86,8 @@ + phy-mode = "rgmii"; + phy-handle = <&bcm54210e>; + ++ /delete-node/ fixed-link; ++ + mdio { + /delete-node/ switch@1e; + +--- a/arch/arm/boot/dts/bcm53573.dtsi ++++ b/arch/arm/boot/dts/bcm53573.dtsi +@@ -181,6 +181,12 @@ + + gmac0: ethernet@5000 { + reg = <0x5000 0x1000>; ++ phy-mode = "internal"; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; + + mdio { + #address-cells = <1>; +@@ -237,6 +243,12 @@ + + gmac1: ethernet@b000 { + reg = <0xb000 0x1000>; ++ phy-mode = "internal"; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; + }; + + pmu@12000 { diff --git a/target/linux/bcm53xx/patches-5.15/037-v6.6-0015-ARM-dts-BCM53573-Disable-second-Ethernet-on-Luxul-de.patch b/target/linux/bcm53xx/patches-5.15/037-v6.6-0015-ARM-dts-BCM53573-Disable-second-Ethernet-on-Luxul-de.patch new file mode 100644 index 00000000000..166f602452a --- /dev/null +++ b/target/linux/bcm53xx/patches-5.15/037-v6.6-0015-ARM-dts-BCM53573-Disable-second-Ethernet-on-Luxul-de.patch @@ -0,0 +1,39 @@ +From d8835601e3c306fda78f8736f1aef688e99e892d Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Mon, 24 Jul 2023 12:11:59 +0200 +Subject: [PATCH] ARM: dts: BCM53573: Disable second Ethernet on Luxul devices +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +XAP-810 and XAP-1440 both have a single Ethernet port and BCM54210E PHY. +Their second Ethernet interface is not connected to anything. + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +Link: https://lore.kernel.org/r/20230724101159.5289-1-zajec5@gmail.com +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/broadcom/bcm47189-luxul-xap-1440.dts | 4 ++++ + arch/arm/boot/dts/broadcom/bcm47189-luxul-xap-810.dts | 4 ++++ + 2 files changed, 8 insertions(+) + +--- a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts ++++ b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts +@@ -60,3 +60,7 @@ + }; + }; + }; ++ ++&gmac1 { ++ status = "disabled"; ++}; +--- a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts ++++ b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts +@@ -96,3 +96,7 @@ + }; + }; + }; ++ ++&gmac1 { ++ status = "disabled"; ++}; diff --git a/target/linux/bcm53xx/patches-5.15/321-ARM-dts-BCM5301X-Describe-partition-formats.patch b/target/linux/bcm53xx/patches-5.15/321-ARM-dts-BCM5301X-Describe-partition-formats.patch deleted file mode 100644 index f2861177dd1..00000000000 --- a/target/linux/bcm53xx/patches-5.15/321-ARM-dts-BCM5301X-Describe-partition-formats.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 7166207bd1d8c46d09d640d46afc685df9bb9083 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 22 Nov 2018 09:21:49 +0100 -Subject: [PATCH] ARM: dts: BCM5301X: Describe partition formats -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -It's needed by OpenWrt for custom partitioning. - -Signed-off-by: RafaÅ‚ MiÅ‚ecki ---- - arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts -+++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts -@@ -35,6 +35,7 @@ - partition@0 { - label = "firmware"; - reg = <0x00000000 0x08000000>; -+ compatible = "seama"; - }; - }; - }; diff --git a/target/linux/bcm53xx/patches-6.1/031-v6.5-0001-ARM-dts-BCM5301X-Relicense-Rafa-s-code-to-the-GPL-2..patch b/target/linux/bcm53xx/patches-6.1/031-v6.5-0001-ARM-dts-BCM5301X-Relicense-Rafa-s-code-to-the-GPL-2..patch index 43a9d0aa1b9..4744e6d5b15 100644 --- a/target/linux/bcm53xx/patches-6.1/031-v6.5-0001-ARM-dts-BCM5301X-Relicense-Rafa-s-code-to-the-GPL-2..patch +++ b/target/linux/bcm53xx/patches-6.1/031-v6.5-0001-ARM-dts-BCM5301X-Relicense-Rafa-s-code-to-the-GPL-2..patch @@ -460,7 +460,7 @@ Signed-off-by: Florian Fainelli }; }; -@@ -558,24 +390,4 @@ +@@ -557,24 +389,4 @@ }; }; }; diff --git a/target/linux/bcm53xx/patches-6.1/031-v6.5-0003-ARM-dts-BCM5301X-Drop-clock-names-from-the-SPI-node.patch b/target/linux/bcm53xx/patches-6.1/031-v6.5-0003-ARM-dts-BCM5301X-Drop-clock-names-from-the-SPI-node.patch deleted file mode 100644 index 4065db8366a..00000000000 --- a/target/linux/bcm53xx/patches-6.1/031-v6.5-0003-ARM-dts-BCM5301X-Drop-clock-names-from-the-SPI-node.patch +++ /dev/null @@ -1,32 +0,0 @@ -From d3c8e2c5757153bbfad70019ec1decbca86f3def Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 3 May 2023 14:28:30 +0200 -Subject: [PATCH] ARM: dts: BCM5301X: Drop "clock-names" from the SPI node -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -There is no such property in the SPI controller binding documentation. -Also Linux driver doesn't look for it. - -This fixes: -arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: spi@18029200: Unevaluated properties are not allowed ('clock-names' was unexpected) - From schema: Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.yaml - -Signed-off-by: RafaÅ‚ MiÅ‚ecki -Link: https://lore.kernel.org/r/20230503122830.3200-1-zajec5@gmail.com -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm5301x.dtsi | 1 - - 1 file changed, 1 deletion(-) - ---- a/arch/arm/boot/dts/bcm5301x.dtsi -+++ b/arch/arm/boot/dts/bcm5301x.dtsi -@@ -335,7 +335,6 @@ - "spi_lr_session_done", - "spi_lr_overread"; - clocks = <&iprocmed>; -- clock-names = "iprocmed"; - num-cs = <2>; - #address-cells = <1>; - #size-cells = <0>; diff --git a/target/linux/bcm53xx/patches-6.1/031-v6.5-0015-ARM-dts-BCM5301X-fix-duplex-full-full-duplex.patch b/target/linux/bcm53xx/patches-6.1/031-v6.5-0015-ARM-dts-BCM5301X-fix-duplex-full-full-duplex.patch deleted file mode 100644 index 805dcf54ebb..00000000000 --- a/target/linux/bcm53xx/patches-6.1/031-v6.5-0015-ARM-dts-BCM5301X-fix-duplex-full-full-duplex.patch +++ /dev/null @@ -1,44 +0,0 @@ -From fd274b733bfdde3ca72f0fa2a37f032f3a8c402c Mon Sep 17 00:00:00 2001 -From: Christian Lamparter -Date: Thu, 8 Jun 2023 17:36:29 +0200 -Subject: [PATCH] ARM: dts: BCM5301X: fix duplex-full => full-duplex - -this typo was found by the dtbs_check -| ports:port@5:fixed-link: 'oneOf' conditional failed, -| {'speed': [[1000]], 'duplex-full': True} is not of type 'array' -| 'duplex-full' does not match any of the regexes: 'pinctrl-[0-]..." - -this should have been full-duplex; - -Fixes: 935327a73553 ("ARM: dts: BCM5301X: Add DT for Meraki MR26") -Fixes: ec88a9c344d9 ("ARM: BCM5301X: Add DT for Meraki MR32") -Signed-off-by: Christian Lamparter -Link: https://lore.kernel.org/r/50522f45566951a9eabd22820647924cc6b4a264.1686238550.git.chunkeey@gmail.com -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm53015-meraki-mr26.dts | 2 +- - arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm/boot/dts/bcm53015-meraki-mr26.dts -+++ b/arch/arm/boot/dts/bcm53015-meraki-mr26.dts -@@ -121,7 +121,7 @@ - - fixed-link { - speed = <1000>; -- duplex-full; -+ full-duplex; - }; - }; - }; ---- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts -+++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts -@@ -182,7 +182,7 @@ - - fixed-link { - speed = <1000>; -- duplex-full; -+ full-duplex; - }; - }; - }; diff --git a/target/linux/bcm53xx/patches-5.15/130-ARM-dts-BCM53573-Fix-Ethernet-info-for-Luxul-devices.patch b/target/linux/bcm53xx/patches-6.1/032-v6.6-0009-ARM-dts-BCM53573-Fix-Ethernet-info-for-Luxul-devices.patch similarity index 88% rename from target/linux/bcm53xx/patches-5.15/130-ARM-dts-BCM53573-Fix-Ethernet-info-for-Luxul-devices.patch rename to target/linux/bcm53xx/patches-6.1/032-v6.6-0009-ARM-dts-BCM53573-Fix-Ethernet-info-for-Luxul-devices.patch index 381a8c38943..07dd9296b69 100644 --- a/target/linux/bcm53xx/patches-5.15/130-ARM-dts-BCM53573-Fix-Ethernet-info-for-Luxul-devices.patch +++ b/target/linux/bcm53xx/patches-6.1/032-v6.6-0009-ARM-dts-BCM53573-Fix-Ethernet-info-for-Luxul-devices.patch @@ -1,5 +1,6 @@ +From 44ad8207806973f4e4f7d870fff36cc01f494250 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 13 Jul 2023 13:05:44 +0200 +Date: Thu, 13 Jul 2023 13:11:45 +0200 Subject: [PATCH] ARM: dts: BCM53573: Fix Ethernet info for Luxul devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 @@ -27,6 +28,8 @@ to work properly. Fixes: 9fb90ae6cae7 ("ARM: dts: BCM53573: Describe on-SoC BCM53125 rev 4 switch") Signed-off-by: RafaÅ‚ MiÅ‚ecki +Link: https://lore.kernel.org/r/20230713111145.14864-1-zajec5@gmail.com +Signed-off-by: Florian Fainelli --- .../boot/dts/broadcom/bcm47189-luxul-xap-1440.dts | 13 +++++++++++++ .../boot/dts/broadcom/bcm47189-luxul-xap-810.dts | 13 +++++++++++++ diff --git a/target/linux/bcm53xx/patches-6.1/032-v6.6-0010-ARM-dts-bcm5301x-Add-SEAMA-compatibles.patch b/target/linux/bcm53xx/patches-6.1/032-v6.6-0010-ARM-dts-bcm5301x-Add-SEAMA-compatibles.patch new file mode 100644 index 00000000000..f23873e1112 --- /dev/null +++ b/target/linux/bcm53xx/patches-6.1/032-v6.6-0010-ARM-dts-bcm5301x-Add-SEAMA-compatibles.patch @@ -0,0 +1,36 @@ +From 72ec77d74d28be7359ef77971cdee38b60af9e49 Mon Sep 17 00:00:00 2001 +From: Linus Walleij +Date: Thu, 13 Jul 2023 00:16:42 +0200 +Subject: [PATCH] ARM: dts: bcm5301x: Add SEAMA compatibles + +This adds SEAMA compatibles to the firmware partition of these +two D-Link devices. + +Signed-off-by: Linus Walleij +Link: https://lore.kernel.org/r/20230713-seama-partitions-v4-2-69e577453d40@linaro.org +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-885l.dts | 1 + + arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-890l.dts | 1 + + 2 files changed, 2 insertions(+) + +--- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts ++++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts +@@ -33,6 +33,7 @@ + #size-cells = <1>; + + partition@0 { ++ compatible = "seama"; + label = "firmware"; + reg = <0x00000000 0x08000000>; + }; +--- a/arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts ++++ b/arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts +@@ -149,6 +149,7 @@ + * partitions: this device uses SEAMA. + */ + firmware@0 { ++ compatible = "seama"; + label = "firmware"; + reg = <0x00000000 0x08000000>; + }; diff --git a/target/linux/bcm53xx/patches-6.1/032-v6.6-0011-ARM-dts-BCM53573-Fix-Tenda-AC9-switch-CPU-port.patch b/target/linux/bcm53xx/patches-6.1/032-v6.6-0011-ARM-dts-BCM53573-Fix-Tenda-AC9-switch-CPU-port.patch new file mode 100644 index 00000000000..d5cb817e8e2 --- /dev/null +++ b/target/linux/bcm53xx/patches-6.1/032-v6.6-0011-ARM-dts-BCM53573-Fix-Tenda-AC9-switch-CPU-port.patch @@ -0,0 +1,31 @@ +From 7141209db9c335ab261a17933809a3e660ebdc12 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Sun, 23 Jul 2023 21:54:14 +0200 +Subject: [PATCH] ARM: dts: BCM53573: Fix Tenda AC9 switch CPU port +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Primary Ethernet interface is connected to the port 8 (not 5). + +Fixes: 64612828628c ("ARM: dts: BCM53573: Add Tenda AC9 switch ports") +Signed-off-by: RafaÅ‚ MiÅ‚ecki +Link: https://lore.kernel.org/r/20230723195416.7831-1-zajec5@gmail.com +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/broadcom/bcm47189-tenda-ac9.dts | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts ++++ b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts +@@ -135,8 +135,8 @@ + label = "lan4"; + }; + +- port@5 { +- reg = <5>; ++ port@8 { ++ reg = <8>; + label = "cpu"; + ethernet = <&gmac0>; + }; diff --git a/target/linux/bcm53xx/patches-6.1/032-v6.6-0012-ARM-dts-BCM53573-Describe-BCM53125-switch-ports-in-t.patch b/target/linux/bcm53xx/patches-6.1/032-v6.6-0012-ARM-dts-BCM53573-Describe-BCM53125-switch-ports-in-t.patch new file mode 100644 index 00000000000..ab27495078a --- /dev/null +++ b/target/linux/bcm53xx/patches-6.1/032-v6.6-0012-ARM-dts-BCM53573-Describe-BCM53125-switch-ports-in-t.patch @@ -0,0 +1,97 @@ +From 8d6b61ecad2f1c939813c5c4517d53e04672dc48 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Sun, 23 Jul 2023 21:54:15 +0200 +Subject: [PATCH] ARM: dts: BCM53573: Describe BCM53125 switch ports in the + main DTS +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +BCM53125 always has 5 ports with GPHYs (for LAN/WAN ports) and 2 IMP +ports. It seems the best place to describe that in the main .dtsi. +Device specific bits can go to device .dts files. This will help +avoiding some code duplication. + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +Link: https://lore.kernel.org/r/20230723195416.7831-2-zajec5@gmail.com +Signed-off-by: Florian Fainelli +--- + .../boot/dts/broadcom/bcm47189-tenda-ac9.dts | 7 ----- + arch/arm/boot/dts/broadcom/bcm53573.dtsi | 26 ++++++++++++++++++- + 2 files changed, 25 insertions(+), 8 deletions(-) + +--- a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts ++++ b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts +@@ -111,34 +111,27 @@ + + ports { + port@0 { +- reg = <0>; + label = "wan"; + }; + + port@1 { +- reg = <1>; + label = "lan1"; + }; + + port@2 { +- reg = <2>; + label = "lan2"; + }; + + port@3 { +- reg = <3>; + label = "lan3"; + }; + + port@4 { +- reg = <4>; + label = "lan4"; + }; + + port@8 { +- reg = <8>; + label = "cpu"; +- ethernet = <&gmac0>; + }; + }; + }; +--- a/arch/arm/boot/dts/bcm53573.dtsi ++++ b/arch/arm/boot/dts/bcm53573.dtsi +@@ -192,10 +192,34 @@ + + status = "disabled"; + +- /* ports are defined in board DTS */ + ports { + #address-cells = <1>; + #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ }; ++ ++ port@2 { ++ reg = <2>; ++ }; ++ ++ port@3 { ++ reg = <3>; ++ }; ++ ++ port@4 { ++ reg = <4>; ++ }; ++ ++ port@8 { ++ reg = <8>; ++ ethernet = <&gmac0>; ++ }; + }; + }; + }; diff --git a/target/linux/bcm53xx/patches-6.1/032-v6.6-0013-ARM-dts-BCM53573-Add-BCM53125-switch-port-5.patch b/target/linux/bcm53xx/patches-6.1/032-v6.6-0013-ARM-dts-BCM53573-Add-BCM53125-switch-port-5.patch new file mode 100644 index 00000000000..cc9e86ac751 --- /dev/null +++ b/target/linux/bcm53xx/patches-6.1/032-v6.6-0013-ARM-dts-BCM53573-Add-BCM53125-switch-port-5.patch @@ -0,0 +1,36 @@ +From d95b1caeea194962220db1778ce7fe71cdba788b Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Sun, 23 Jul 2023 21:54:16 +0200 +Subject: [PATCH] ARM: dts: BCM53573: Add BCM53125 switch port 5 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +It's connected to the extra Ethernet interface. + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +Link: https://lore.kernel.org/r/20230723195416.7831-3-zajec5@gmail.com +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/broadcom/bcm53573.dtsi | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/arch/arm/boot/dts/bcm53573.dtsi ++++ b/arch/arm/boot/dts/bcm53573.dtsi +@@ -216,6 +216,16 @@ + reg = <4>; + }; + ++ port@5 { ++ reg = <5>; ++ ethernet = <&gmac1>; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++ }; ++ + port@8 { + reg = <8>; + ethernet = <&gmac0>; diff --git a/target/linux/bcm53xx/patches-6.1/032-v6.6-0014-ARM-dts-BCM53573-Add-Ethernet-interfaces-links.patch b/target/linux/bcm53xx/patches-6.1/032-v6.6-0014-ARM-dts-BCM53573-Add-Ethernet-interfaces-links.patch new file mode 100644 index 00000000000..f97d4edd754 --- /dev/null +++ b/target/linux/bcm53xx/patches-6.1/032-v6.6-0014-ARM-dts-BCM53573-Add-Ethernet-interfaces-links.patch @@ -0,0 +1,73 @@ +From e0ae343a2c1b782a346d9b844ea65e1d49c428b2 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Mon, 24 Jul 2023 12:12:27 +0200 +Subject: [PATCH] ARM: dts: BCM53573: Add Ethernet interfaces links +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +BCM53573 has 2 Ethernet interfaces each connected to one of switch ports +in the default design. They both use fixed links. + +An exception are Luxul XAP devices that have switch replaced by a single +PHY. + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +Link: https://lore.kernel.org/r/20230724101227.5420-1-zajec5@gmail.com +Signed-off-by: Florian Fainelli +--- + .../boot/dts/broadcom/bcm47189-luxul-xap-1440.dts | 2 ++ + .../arm/boot/dts/broadcom/bcm47189-luxul-xap-810.dts | 2 ++ + arch/arm/boot/dts/broadcom/bcm53573.dtsi | 12 ++++++++++++ + 3 files changed, 16 insertions(+) + +--- a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts ++++ b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts +@@ -50,6 +50,8 @@ + phy-mode = "rgmii"; + phy-handle = <&bcm54210e>; + ++ /delete-node/ fixed-link; ++ + mdio { + /delete-node/ switch@1e; + +--- a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts ++++ b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts +@@ -86,6 +86,8 @@ + phy-mode = "rgmii"; + phy-handle = <&bcm54210e>; + ++ /delete-node/ fixed-link; ++ + mdio { + /delete-node/ switch@1e; + +--- a/arch/arm/boot/dts/bcm53573.dtsi ++++ b/arch/arm/boot/dts/bcm53573.dtsi +@@ -181,6 +181,12 @@ + + gmac0: ethernet@5000 { + reg = <0x5000 0x1000>; ++ phy-mode = "internal"; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; + + mdio { + #address-cells = <1>; +@@ -237,6 +243,12 @@ + + gmac1: ethernet@b000 { + reg = <0xb000 0x1000>; ++ phy-mode = "internal"; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; + }; + + pmu@12000 { diff --git a/target/linux/bcm53xx/patches-6.1/032-v6.6-0015-ARM-dts-BCM53573-Disable-second-Ethernet-on-Luxul-de.patch b/target/linux/bcm53xx/patches-6.1/032-v6.6-0015-ARM-dts-BCM53573-Disable-second-Ethernet-on-Luxul-de.patch new file mode 100644 index 00000000000..166f602452a --- /dev/null +++ b/target/linux/bcm53xx/patches-6.1/032-v6.6-0015-ARM-dts-BCM53573-Disable-second-Ethernet-on-Luxul-de.patch @@ -0,0 +1,39 @@ +From d8835601e3c306fda78f8736f1aef688e99e892d Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Mon, 24 Jul 2023 12:11:59 +0200 +Subject: [PATCH] ARM: dts: BCM53573: Disable second Ethernet on Luxul devices +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +XAP-810 and XAP-1440 both have a single Ethernet port and BCM54210E PHY. +Their second Ethernet interface is not connected to anything. + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +Link: https://lore.kernel.org/r/20230724101159.5289-1-zajec5@gmail.com +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/broadcom/bcm47189-luxul-xap-1440.dts | 4 ++++ + arch/arm/boot/dts/broadcom/bcm47189-luxul-xap-810.dts | 4 ++++ + 2 files changed, 8 insertions(+) + +--- a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts ++++ b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts +@@ -60,3 +60,7 @@ + }; + }; + }; ++ ++&gmac1 { ++ status = "disabled"; ++}; +--- a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts ++++ b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts +@@ -96,3 +96,7 @@ + }; + }; + }; ++ ++&gmac1 { ++ status = "disabled"; ++}; diff --git a/target/linux/bcm53xx/patches-6.1/180-usb-xhci-add-support-for-performing-fake-doorbell.patch b/target/linux/bcm53xx/patches-6.1/180-usb-xhci-add-support-for-performing-fake-doorbell.patch index 33066a84d8e..37bf49c98ca 100644 --- a/target/linux/bcm53xx/patches-6.1/180-usb-xhci-add-support-for-performing-fake-doorbell.patch +++ b/target/linux/bcm53xx/patches-6.1/180-usb-xhci-add-support-for-performing-fake-doorbell.patch @@ -107,11 +107,11 @@ it on BCM4708 family. if (xhci->quirks & XHCI_NEC_HOST) --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h -@@ -1899,6 +1899,7 @@ struct xhci_hcd { - #define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42) - #define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43) +@@ -1901,6 +1901,7 @@ struct xhci_hcd { #define XHCI_RESET_TO_DEFAULT BIT_ULL(44) -+#define XHCI_FAKE_DOORBELL BIT_ULL(45) + #define XHCI_ZHAOXIN_TRB_FETCH BIT_ULL(45) + #define XHCI_ZHAOXIN_HOST BIT_ULL(46) ++#define XHCI_FAKE_DOORBELL BIT_ULL(47) unsigned int num_active_eps; unsigned int limit_active_eps; diff --git a/target/linux/bcm53xx/patches-6.1/321-ARM-dts-BCM5301X-Describe-partition-formats.patch b/target/linux/bcm53xx/patches-6.1/321-ARM-dts-BCM5301X-Describe-partition-formats.patch deleted file mode 100644 index f2861177dd1..00000000000 --- a/target/linux/bcm53xx/patches-6.1/321-ARM-dts-BCM5301X-Describe-partition-formats.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 7166207bd1d8c46d09d640d46afc685df9bb9083 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 22 Nov 2018 09:21:49 +0100 -Subject: [PATCH] ARM: dts: BCM5301X: Describe partition formats -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -It's needed by OpenWrt for custom partitioning. - -Signed-off-by: RafaÅ‚ MiÅ‚ecki ---- - arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts -+++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts -@@ -35,6 +35,7 @@ - partition@0 { - label = "firmware"; - reg = <0x00000000 0x08000000>; -+ compatible = "seama"; - }; - }; - }; diff --git a/target/linux/generic/backport-5.15/409-v6.3-mtd-mtdpart-Don-t-create-platform-device-that-ll-nev.patch b/target/linux/generic/backport-5.15/409-v6.3-mtd-mtdpart-Don-t-create-platform-device-that-ll-nev.patch new file mode 100644 index 00000000000..ba14ae01785 --- /dev/null +++ b/target/linux/generic/backport-5.15/409-v6.3-mtd-mtdpart-Don-t-create-platform-device-that-ll-nev.patch @@ -0,0 +1,54 @@ +From fb42378dcc7f247df56f0ecddfdae85487495fbc Mon Sep 17 00:00:00 2001 +From: Saravana Kannan +Date: Mon, 6 Feb 2023 17:42:04 -0800 +Subject: [PATCH] mtd: mtdpart: Don't create platform device that'll never + probe + +These "nvmem-cells" platform devices never get probed because there's no +platform driver for it and it's never used anywhere else. So it's a +waste of memory. These devices also cause fw_devlink to block nvmem +consumers of "nvmem-cells" partition from probing because the supplier +device never probes. + +So stop creating platform devices for nvmem-cells partitions to avoid +wasting memory and to avoid blocking probing of consumers. + +Reported-by: Maxim Kiselev +Fixes: bcdf0315a61a ("mtd: call of_platform_populate() for MTD partitions") +Signed-off-by: Saravana Kannan +Tested-by: Maksim Kiselev +Tested-by: Douglas Anderson +Tested-by: Geert Uytterhoeven +Tested-by: Luca Weiss # qcom/sm7225-fairphone-fp4 +Link: https://lore.kernel.org/r/20230207014207.1678715-13-saravanak@google.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/mtd/mtdpart.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -577,6 +577,7 @@ static int mtd_part_of_parse(struct mtd_ + { + struct mtd_part_parser *parser; + struct device_node *np; ++ struct device_node *child; + struct property *prop; + struct device *dev; + const char *compat; +@@ -594,6 +595,15 @@ static int mtd_part_of_parse(struct mtd_ + else + np = of_get_child_by_name(np, "partitions"); + ++ /* ++ * Don't create devices that are added to a bus but will never get ++ * probed. That'll cause fw_devlink to block probing of consumers of ++ * this partition until the partition device is probed. ++ */ ++ for_each_child_of_node(np, child) ++ if (of_device_is_compatible(child, "nvmem-cells")) ++ of_node_set_flag(child, OF_POPULATED); ++ + of_property_for_each_string(np, "compatible", prop, compat) { + parser = mtd_part_get_compatible_parser(compat); + if (!parser) diff --git a/target/linux/generic/backport-6.1/020-v6.3-10-UPSTREAM-mm-add-vma_has_recency.patch b/target/linux/generic/backport-6.1/020-v6.3-10-UPSTREAM-mm-add-vma_has_recency.patch index 69078629055..8fd5564d007 100644 --- a/target/linux/generic/backport-6.1/020-v6.3-10-UPSTREAM-mm-add-vma_has_recency.patch +++ b/target/linux/generic/backport-6.1/020-v6.3-10-UPSTREAM-mm-add-vma_has_recency.patch @@ -87,7 +87,7 @@ Signed-off-by: T.J. Mercier mark_page_accessed(page); } rss[mm_counter(page)]--; -@@ -5182,8 +5181,8 @@ static inline void mm_account_fault(stru +@@ -5189,8 +5188,8 @@ static inline void mm_account_fault(stru #ifdef CONFIG_LRU_GEN static void lru_gen_enter_fault(struct vm_area_struct *vma) { diff --git a/target/linux/generic/backport-6.1/701-v6.5-net-bgmac-postpone-turning-IRQs-off-to-avoid-SoC-han.patch b/target/linux/generic/backport-6.1/701-v6.5-net-bgmac-postpone-turning-IRQs-off-to-avoid-SoC-han.patch deleted file mode 100644 index 26e9ae3bcd2..00000000000 --- a/target/linux/generic/backport-6.1/701-v6.5-net-bgmac-postpone-turning-IRQs-off-to-avoid-SoC-han.patch +++ /dev/null @@ -1,45 +0,0 @@ -From e7731194fdf085f46d58b1adccfddbd0dfee4873 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 7 Jul 2023 08:53:25 +0200 -Subject: [PATCH] net: bgmac: postpone turning IRQs off to avoid SoC hangs -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Turning IRQs off is done by accessing Ethernet controller registers. -That can't be done until device's clock is enabled. It results in a SoC -hang otherwise. - -This bug remained unnoticed for years as most bootloaders keep all -Ethernet interfaces turned on. It seems to only affect a niche SoC -family BCM47189. It has two Ethernet controllers but CFE bootloader uses -only the first one. - -Fixes: 34322615cbaa ("net: bgmac: Mask interrupts during probe") -Signed-off-by: RafaÅ‚ MiÅ‚ecki -Reviewed-by: Michal Kubiak -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/broadcom/bgmac.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/net/ethernet/broadcom/bgmac.c -+++ b/drivers/net/ethernet/broadcom/bgmac.c -@@ -1492,8 +1492,6 @@ int bgmac_enet_probe(struct bgmac *bgmac - - bgmac->in_init = true; - -- bgmac_chip_intrs_off(bgmac); -- - net_dev->irq = bgmac->irq; - SET_NETDEV_DEV(net_dev, bgmac->dev); - dev_set_drvdata(bgmac->dev, bgmac); -@@ -1511,6 +1509,8 @@ int bgmac_enet_probe(struct bgmac *bgmac - */ - bgmac_clk_enable(bgmac, 0); - -+ bgmac_chip_intrs_off(bgmac); -+ - /* This seems to be fixing IRQ by assigning OOB #6 to the core */ - if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK)) { - if (bgmac->feature_flags & BGMAC_FEAT_IRQ_ID_OOB_6) diff --git a/target/linux/generic/backport-6.1/777-v6.2-05-net-dsa-qca8k-improve-mdio-master-read-write-by-usin.patch b/target/linux/generic/backport-6.1/777-v6.2-05-net-dsa-qca8k-improve-mdio-master-read-write-by-usin.patch index 4cbb66cf35f..ea34901472d 100644 --- a/target/linux/generic/backport-6.1/777-v6.2-05-net-dsa-qca8k-improve-mdio-master-read-write-by-usin.patch +++ b/target/linux/generic/backport-6.1/777-v6.2-05-net-dsa-qca8k-improve-mdio-master-read-write-by-usin.patch @@ -28,7 +28,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/dsa/qca/qca8k-8xxx.c +++ b/drivers/net/dsa/qca/qca8k-8xxx.c -@@ -740,9 +740,9 @@ qca8k_mdio_busy_wait(struct mii_bus *bus +@@ -743,9 +743,9 @@ qca8k_mdio_busy_wait(struct mii_bus *bus qca8k_split_addr(reg, &r1, &r2, &page); @@ -40,7 +40,7 @@ Signed-off-by: David S. Miller /* Check if qca8k_read has failed for a different reason * before returnting -ETIMEDOUT -@@ -784,7 +784,7 @@ qca8k_mdio_write(struct qca8k_priv *priv +@@ -787,7 +787,7 @@ qca8k_mdio_write(struct qca8k_priv *priv exit: /* even if the busy_wait timeouts try to clear the MASTER_EN */ @@ -49,7 +49,7 @@ Signed-off-by: David S. Miller mutex_unlock(&bus->mdio_lock); -@@ -814,18 +814,18 @@ qca8k_mdio_read(struct qca8k_priv *priv, +@@ -817,18 +817,18 @@ qca8k_mdio_read(struct qca8k_priv *priv, if (ret) goto exit; diff --git a/target/linux/generic/backport-6.1/801-v6.4-01-net-dsa-qca8k-move-qca8k_port_to_phy-to-header.patch b/target/linux/generic/backport-6.1/801-v6.4-01-net-dsa-qca8k-move-qca8k_port_to_phy-to-header.patch index e336fb81bab..ba8216f7830 100644 --- a/target/linux/generic/backport-6.1/801-v6.4-01-net-dsa-qca8k-move-qca8k_port_to_phy-to-header.patch +++ b/target/linux/generic/backport-6.1/801-v6.4-01-net-dsa-qca8k-move-qca8k_port_to_phy-to-header.patch @@ -20,7 +20,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/dsa/qca/qca8k-8xxx.c +++ b/drivers/net/dsa/qca/qca8k-8xxx.c -@@ -716,21 +716,6 @@ err_clear_skb: +@@ -719,21 +719,6 @@ err_clear_skb: return ret; } diff --git a/target/linux/generic/backport-6.1/801-v6.4-02-net-dsa-qca8k-add-LEDs-basic-support.patch b/target/linux/generic/backport-6.1/801-v6.4-02-net-dsa-qca8k-add-LEDs-basic-support.patch index 37922580dae..e5cd03f1f30 100644 --- a/target/linux/generic/backport-6.1/801-v6.4-02-net-dsa-qca8k-add-LEDs-basic-support.patch +++ b/target/linux/generic/backport-6.1/801-v6.4-02-net-dsa-qca8k-add-LEDs-basic-support.patch @@ -71,7 +71,7 @@ Signed-off-by: David S. Miller static void qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page) -@@ -1726,6 +1727,10 @@ qca8k_setup(struct dsa_switch *ds) +@@ -1729,6 +1730,10 @@ qca8k_setup(struct dsa_switch *ds) if (ret) return ret; diff --git a/target/linux/generic/backport-6.1/803-v6.5-01-leds-trigger-netdev-Recheck-NETDEV_LED_MODE_LINKUP-o.patch b/target/linux/generic/backport-6.1/803-v6.5-01-leds-trigger-netdev-Recheck-NETDEV_LED_MODE_LINKUP-o.patch deleted file mode 100644 index 3385023168d..00000000000 --- a/target/linux/generic/backport-6.1/803-v6.5-01-leds-trigger-netdev-Recheck-NETDEV_LED_MODE_LINKUP-o.patch +++ /dev/null @@ -1,35 +0,0 @@ -From cee4bd16c3195a701be683f7da9e88c6e11acb73 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Wed, 19 Apr 2023 23:07:39 +0200 -Subject: [PATCH 1/5] leds: trigger: netdev: Recheck NETDEV_LED_MODE_LINKUP on - dev rename - -Dev can be renamed also while up for supported device. We currently -wrongly clear the NETDEV_LED_MODE_LINKUP flag on NETDEV_CHANGENAME -event. - -Fix this by rechecking if the carrier is ok on NETDEV_CHANGENAME and -correctly set the NETDEV_LED_MODE_LINKUP bit. - -Fixes: 5f820ed52371 ("leds: trigger: netdev: fix handling on interface rename") -Cc: stable@vger.kernel.org # v5.5+ -Signed-off-by: Christian Marangi -Reviewed-by: Andrew Lunn -Signed-off-by: Lee Jones -Link: https://lore.kernel.org/r/20230419210743.3594-2-ansuelsmth@gmail.com ---- - drivers/leds/trigger/ledtrig-netdev.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/leds/trigger/ledtrig-netdev.c -+++ b/drivers/leds/trigger/ledtrig-netdev.c -@@ -318,6 +318,9 @@ static int netdev_trig_notify(struct not - clear_bit(NETDEV_LED_MODE_LINKUP, &trigger_data->mode); - switch (evt) { - case NETDEV_CHANGENAME: -+ if (netif_carrier_ok(dev)) -+ set_bit(NETDEV_LED_MODE_LINKUP, &trigger_data->mode); -+ fallthrough; - case NETDEV_REGISTER: - if (trigger_data->net_dev) - dev_put(trigger_data->net_dev); diff --git a/target/linux/generic/hack-6.1/204-module_strip.patch b/target/linux/generic/hack-6.1/204-module_strip.patch index f0949d32fdd..71ee62ece8d 100644 --- a/target/linux/generic/hack-6.1/204-module_strip.patch +++ b/target/linux/generic/hack-6.1/204-module_strip.patch @@ -141,7 +141,7 @@ Signed-off-by: Felix Fietkau --- a/scripts/mod/modpost.c +++ b/scripts/mod/modpost.c -@@ -1817,7 +1817,9 @@ static void read_symbols(const char *mod +@@ -1781,7 +1781,9 @@ static void read_symbols(const char *mod symname = remove_dot(info.strtab + sym->st_name); handle_symbol(mod, &info, sym, symname); @@ -151,7 +151,7 @@ Signed-off-by: Felix Fietkau } for (sym = info.symtab_start; sym < info.symtab_stop; sym++) { -@@ -1980,8 +1982,10 @@ static void add_header(struct buffer *b, +@@ -1944,8 +1946,10 @@ static void add_header(struct buffer *b, buf_printf(b, "BUILD_SALT;\n"); buf_printf(b, "BUILD_LTO_INFO;\n"); buf_printf(b, "\n"); @@ -162,7 +162,7 @@ Signed-off-by: Felix Fietkau buf_printf(b, "\n"); buf_printf(b, "__visible struct module __this_module\n"); buf_printf(b, "__section(\".gnu.linkonce.this_module\") = {\n"); -@@ -1995,8 +1999,10 @@ static void add_header(struct buffer *b, +@@ -1959,8 +1963,10 @@ static void add_header(struct buffer *b, buf_printf(b, "\t.arch = MODULE_ARCH_INIT,\n"); buf_printf(b, "};\n"); @@ -173,7 +173,7 @@ Signed-off-by: Felix Fietkau buf_printf(b, "\n" -@@ -2004,8 +2010,10 @@ static void add_header(struct buffer *b, +@@ -1968,8 +1974,10 @@ static void add_header(struct buffer *b, "MODULE_INFO(retpoline, \"Y\");\n" "#endif\n"); @@ -184,7 +184,7 @@ Signed-off-by: Felix Fietkau if (strstarts(mod->name, "tools/testing")) buf_printf(b, "\nMODULE_INFO(test, \"Y\");\n"); -@@ -2101,11 +2109,13 @@ static void add_depends(struct buffer *b +@@ -2065,11 +2073,13 @@ static void add_depends(struct buffer *b static void add_srcversion(struct buffer *b, struct module *mod) { @@ -198,7 +198,7 @@ Signed-off-by: Felix Fietkau } static void write_buf(struct buffer *b, const char *fname) -@@ -2191,7 +2201,9 @@ static void write_mod_c_file(struct modu +@@ -2155,7 +2165,9 @@ static void write_mod_c_file(struct modu add_exported_symbols(&buf, mod); add_versions(&buf, mod); add_depends(&buf, mod); diff --git a/target/linux/generic/hack-6.1/780-usb-net-MeigLink_modem_support.patch b/target/linux/generic/hack-6.1/780-usb-net-MeigLink_modem_support.patch index 7257f7010bb..64241c4801b 100644 --- a/target/linux/generic/hack-6.1/780-usb-net-MeigLink_modem_support.patch +++ b/target/linux/generic/hack-6.1/780-usb-net-MeigLink_modem_support.patch @@ -29,7 +29,7 @@ Subject: [PATCH] net/usb/qmi_wwan: add MeigLink modem support #define QUECTEL_VENDOR_ID 0x2c7c /* These Quectel products use Quectel's vendor ID */ -@@ -1173,6 +1175,11 @@ static const struct usb_device_id option +@@ -1177,6 +1179,11 @@ static const struct usb_device_id option .driver_info = ZLP }, { USB_DEVICE(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_BG96), .driver_info = RSVD(4) }, diff --git a/target/linux/generic/hack-6.1/902-debloat_proc.patch b/target/linux/generic/hack-6.1/902-debloat_proc.patch index 5722ac97b1e..b035f04ba23 100644 --- a/target/linux/generic/hack-6.1/902-debloat_proc.patch +++ b/target/linux/generic/hack-6.1/902-debloat_proc.patch @@ -330,7 +330,7 @@ Signed-off-by: Felix Fietkau --- a/net/core/sock.c +++ b/net/core/sock.c -@@ -4082,6 +4082,8 @@ static __net_initdata struct pernet_oper +@@ -4093,6 +4093,8 @@ static __net_initdata struct pernet_oper static int __init proto_init(void) { diff --git a/target/linux/generic/pending-5.15/307-mips_highmem_offset.patch b/target/linux/generic/pending-5.15/307-mips_highmem_offset.patch deleted file mode 100644 index 0529b0c5c8a..00000000000 --- a/target/linux/generic/pending-5.15/307-mips_highmem_offset.patch +++ /dev/null @@ -1,19 +0,0 @@ -From: Felix Fietkau -Subject: kernel: adjust mips highmem offset to avoid the need for -mlong-calls on systems with >256M RAM - -Signed-off-by: Felix Fietkau ---- - arch/mips/include/asm/mach-generic/spaces.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/mips/include/asm/mach-generic/spaces.h -+++ b/arch/mips/include/asm/mach-generic/spaces.h -@@ -46,7 +46,7 @@ - * Memory above this physical address will be considered highmem. - */ - #ifndef HIGHMEM_START --#define HIGHMEM_START _AC(0x20000000, UL) -+#define HIGHMEM_START _AC(0x10000000, UL) - #endif - - #endif /* CONFIG_32BIT */ diff --git a/target/linux/generic/pending-6.1/143-jffs2-reduce-stack-usage-in-jffs2_build_xattr_subsys.patch b/target/linux/generic/pending-6.1/143-jffs2-reduce-stack-usage-in-jffs2_build_xattr_subsys.patch deleted file mode 100644 index e5a86dd29fe..00000000000 --- a/target/linux/generic/pending-6.1/143-jffs2-reduce-stack-usage-in-jffs2_build_xattr_subsys.patch +++ /dev/null @@ -1,121 +0,0 @@ -From eee53f6eb7561f516b9c4bac829ce31c48096130 Mon Sep 17 00:00:00 2001 -From: Fabian Frederick -Date: Tue, 9 May 2017 22:30:03 +0200 -Subject: [PATCH] jffs2: reduce stack usage in jffs2_build_xattr_subsystem() - -Use kcalloc() for allocation/flush of 128 pointers table to -reduce stack usage. - -Function now returns -ENOMEM or 0 on success. - -stackusage -Before: -./fs/jffs2/xattr.c:775 jffs2_build_xattr_subsystem 1208 -dynamic,bounded - -After: -./fs/jffs2/xattr.c:775 jffs2_build_xattr_subsystem 192 -dynamic,bounded - -Also update definition when CONFIG_JFFS2_FS_XATTR is not enabled - -Tested with an MTD mount point and some user set/getfattr. - -Many current target on OpenWRT also suffer from a compilation warning -(that become an error with CONFIG_WERROR) with the following output: - -fs/jffs2/xattr.c: In function 'jffs2_build_xattr_subsystem': -fs/jffs2/xattr.c:887:1: error: the frame size of 1088 bytes is larger than 1024 bytes [-Werror=frame-larger-than=] - 887 | } - | ^ - -Using dynamic allocation fix this compilation warning. - -Fixes: c9f700f840bd ("[JFFS2][XATTR] using 'delete marker' for xdatum/xref deletion") -Reported-by: Tim Gardner -Reported-by: kernel test robot -Reported-by: Ron Economos -Reported-by: Nathan Chancellor -Reviewed-by: Nick Desaulniers -Signed-off-by: Fabian Frederick -Signed-off-by: Christian Marangi -Cc: stable@vger.kernel.org ---- - fs/jffs2/build.c | 5 ++++- - fs/jffs2/xattr.c | 13 +++++++++---- - fs/jffs2/xattr.h | 4 ++-- - 3 files changed, 15 insertions(+), 7 deletions(-) - ---- a/fs/jffs2/build.c -+++ b/fs/jffs2/build.c -@@ -211,7 +211,10 @@ static int jffs2_build_filesystem(struct - ic->scan_dents = NULL; - cond_resched(); - } -- jffs2_build_xattr_subsystem(c); -+ ret = jffs2_build_xattr_subsystem(c); -+ if (ret) -+ goto exit; -+ - c->flags &= ~JFFS2_SB_FLAG_BUILDING; - - dbg_fsbuild("FS build complete\n"); ---- a/fs/jffs2/xattr.c -+++ b/fs/jffs2/xattr.c -@@ -772,10 +772,10 @@ void jffs2_clear_xattr_subsystem(struct - } - - #define XREF_TMPHASH_SIZE (128) --void jffs2_build_xattr_subsystem(struct jffs2_sb_info *c) -+int jffs2_build_xattr_subsystem(struct jffs2_sb_info *c) - { - struct jffs2_xattr_ref *ref, *_ref; -- struct jffs2_xattr_ref *xref_tmphash[XREF_TMPHASH_SIZE]; -+ struct jffs2_xattr_ref **xref_tmphash; - struct jffs2_xattr_datum *xd, *_xd; - struct jffs2_inode_cache *ic; - struct jffs2_raw_node_ref *raw; -@@ -784,9 +784,12 @@ void jffs2_build_xattr_subsystem(struct - - BUG_ON(!(c->flags & JFFS2_SB_FLAG_BUILDING)); - -+ xref_tmphash = kcalloc(XREF_TMPHASH_SIZE, -+ sizeof(struct jffs2_xattr_ref *), GFP_KERNEL); -+ if (!xref_tmphash) -+ return -ENOMEM; -+ - /* Phase.1 : Merge same xref */ -- for (i=0; i < XREF_TMPHASH_SIZE; i++) -- xref_tmphash[i] = NULL; - for (ref=c->xref_temp; ref; ref=_ref) { - struct jffs2_xattr_ref *tmp; - -@@ -884,6 +887,8 @@ void jffs2_build_xattr_subsystem(struct - "%u of xref (%u dead, %u orphan) found.\n", - xdatum_count, xdatum_unchecked_count, xdatum_orphan_count, - xref_count, xref_dead_count, xref_orphan_count); -+ kfree(xref_tmphash); -+ return 0; - } - - struct jffs2_xattr_datum *jffs2_setup_xattr_datum(struct jffs2_sb_info *c, ---- a/fs/jffs2/xattr.h -+++ b/fs/jffs2/xattr.h -@@ -71,7 +71,7 @@ static inline int is_xattr_ref_dead(stru - #ifdef CONFIG_JFFS2_FS_XATTR - - extern void jffs2_init_xattr_subsystem(struct jffs2_sb_info *c); --extern void jffs2_build_xattr_subsystem(struct jffs2_sb_info *c); -+extern int jffs2_build_xattr_subsystem(struct jffs2_sb_info *c); - extern void jffs2_clear_xattr_subsystem(struct jffs2_sb_info *c); - - extern struct jffs2_xattr_datum *jffs2_setup_xattr_datum(struct jffs2_sb_info *c, -@@ -103,7 +103,7 @@ extern ssize_t jffs2_listxattr(struct de - #else - - #define jffs2_init_xattr_subsystem(c) --#define jffs2_build_xattr_subsystem(c) -+#define jffs2_build_xattr_subsystem(c) (0) - #define jffs2_clear_xattr_subsystem(c) - - #define jffs2_xattr_do_crccheck_inode(c, ic) diff --git a/target/linux/generic/pending-6.1/160-workqueue-fix-enum-type-for-gcc-13.patch b/target/linux/generic/pending-6.1/160-workqueue-fix-enum-type-for-gcc-13.patch deleted file mode 100644 index 82076121ac3..00000000000 --- a/target/linux/generic/pending-6.1/160-workqueue-fix-enum-type-for-gcc-13.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 525ff9c2965770762b81d679820552a208070d59 Mon Sep 17 00:00:00 2001 -From: Arnd Bergmann -Date: Tue, 17 Jan 2023 17:40:35 +0100 -Subject: workqueue: fix enum type for gcc-13 - -In gcc-13, the WORK_STRUCT_WQ_DATA_MASK constant is a signed 64-bit -type on 32-bit architectures because the enum definition has both -negative numbers and numbers above LONG_MAX in it: - -kernel/workqueue.c: In function 'get_work_pwq': -kernel/workqueue.c:709:24: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast] - 709 | return (void *)(data & WORK_STRUCT_WQ_DATA_MASK); - | ^ -kernel/workqueue.c: In function 'get_work_pool': -kernel/workqueue.c:737:25: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast] - 737 | return ((struct pool_workqueue *) - | ^ -kernel/workqueue.c: In function 'get_work_pool_id': -kernel/workqueue.c:759:25: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast] - 759 | return ((struct pool_workqueue *) - | ^ - -Change the enum definition to ensure all values can fit into -the range of 'unsigned long' on all architectures. - -Signed-off-by: Arnd Bergmann -Tested-by: Thierry Reding -Tested-by: Lai Jiangshan -Signed-off-by: Tejun Heo ---- - include/linux/workqueue.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/include/linux/workqueue.h -+++ b/include/linux/workqueue.h -@@ -83,7 +83,7 @@ enum { - - /* convenience constants */ - WORK_STRUCT_FLAG_MASK = (1UL << WORK_STRUCT_FLAG_BITS) - 1, -- WORK_STRUCT_WQ_DATA_MASK = ~WORK_STRUCT_FLAG_MASK, -+ WORK_STRUCT_WQ_DATA_MASK = (unsigned long)~WORK_STRUCT_FLAG_MASK, - WORK_STRUCT_NO_POOL = (unsigned long)WORK_OFFQ_POOL_NONE << WORK_OFFQ_POOL_SHIFT, - - /* bit mask for work_busy() return values */ diff --git a/target/linux/generic/pending-6.1/307-mips_highmem_offset.patch b/target/linux/generic/pending-6.1/307-mips_highmem_offset.patch deleted file mode 100644 index 0529b0c5c8a..00000000000 --- a/target/linux/generic/pending-6.1/307-mips_highmem_offset.patch +++ /dev/null @@ -1,19 +0,0 @@ -From: Felix Fietkau -Subject: kernel: adjust mips highmem offset to avoid the need for -mlong-calls on systems with >256M RAM - -Signed-off-by: Felix Fietkau ---- - arch/mips/include/asm/mach-generic/spaces.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/mips/include/asm/mach-generic/spaces.h -+++ b/arch/mips/include/asm/mach-generic/spaces.h -@@ -46,7 +46,7 @@ - * Memory above this physical address will be considered highmem. - */ - #ifndef HIGHMEM_START --#define HIGHMEM_START _AC(0x20000000, UL) -+#define HIGHMEM_START _AC(0x10000000, UL) - #endif - - #endif /* CONFIG_32BIT */ diff --git a/target/linux/generic/pending-6.1/710-bridge-add-knob-for-filtering-rx-tx-BPDU-pack.patch b/target/linux/generic/pending-6.1/710-bridge-add-knob-for-filtering-rx-tx-BPDU-pack.patch index 7eb3d8653fa..4c09ed6b50d 100644 --- a/target/linux/generic/pending-6.1/710-bridge-add-knob-for-filtering-rx-tx-BPDU-pack.patch +++ b/target/linux/generic/pending-6.1/710-bridge-add-knob-for-filtering-rx-tx-BPDU-pack.patch @@ -161,7 +161,7 @@ Signed-off-by: Felix Fietkau struct rtnl_link { rtnl_doit_func doit; -@@ -4817,7 +4817,9 @@ int ndo_dflt_bridge_getlink(struct sk_bu +@@ -4823,7 +4823,9 @@ int ndo_dflt_bridge_getlink(struct sk_bu brport_nla_put_flag(skb, flags, mask, IFLA_BRPORT_MCAST_FLOOD, BR_MCAST_FLOOD) || brport_nla_put_flag(skb, flags, mask, diff --git a/target/linux/ipq40xx/base-files/etc/board.d/02_network b/target/linux/ipq40xx/base-files/etc/board.d/02_network index 1a74fb792ce..c297566dd85 100644 --- a/target/linux/ipq40xx/base-files/etc/board.d/02_network +++ b/target/linux/ipq40xx/base-files/etc/board.d/02_network @@ -24,6 +24,7 @@ ipq40xx_setup_interfaces() p2w,r619ac-64m|\ p2w,r619ac-128m|\ pakedge,wr-1|\ + teltonika,rutx50|\ zyxel,nbg6617) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan" ;; diff --git a/target/linux/ipq40xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ipq40xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata index 7f41bdcfcc5..c8cf297e810 100644 --- a/target/linux/ipq40xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata +++ b/target/linux/ipq40xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata @@ -131,7 +131,8 @@ case "$FIRMWARE" in caldata_extract "0:ART" 0x1000 0x2f20 ath10k_patch_mac $(macaddr_add $(get_mac_label) 2) ;; - teltonika,rutx10) + teltonika,rutx10|\ + teltonika,rutx50) caldata_extract "0:ART" 0x1000 0x2f20 ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary "0:CONFIG" 0x0) 2) ;; @@ -227,7 +228,8 @@ case "$FIRMWARE" in caldata_extract "0:ART" 0x5000 0x2f20 ath10k_patch_mac $(macaddr_add $(get_mac_label) 4) ;; - teltonika,rutx10) + teltonika,rutx10|\ + teltonika,rutx50) caldata_extract "0:ART" 0x5000 0x2f20 ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary "0:CONFIG" 0x0) 3) ;; diff --git a/target/linux/ipq40xx/base-files/lib/upgrade/platform.sh b/target/linux/ipq40xx/base-files/lib/upgrade/platform.sh index e6e99b9d212..8807f844e59 100644 --- a/target/linux/ipq40xx/base-files/lib/upgrade/platform.sh +++ b/target/linux/ipq40xx/base-files/lib/upgrade/platform.sh @@ -207,6 +207,7 @@ platform_do_upgrade() { sony_emmc_do_upgrade "$1" ;; teltonika,rutx10 |\ + teltonika,rutx50 |\ zte,mf18a |\ zte,mf286d |\ zte,mf287plus |\ diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-rutx.dtsi b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-rutx.dtsi index 230b62a94ee..df9425b12a8 100644 --- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-rutx.dtsi +++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-rutx.dtsi @@ -44,43 +44,6 @@ linux,code = ; }; }; - - gpio_export { - compatible = "gpio-export"; - #size-cells = <0>; - - gpio_out { - gpio-export,name = "gpio_out"; - gpio-export,output = <0>; - gpio-export,direction_may_change = <0>; - gpios = <&stm32_io 23 GPIO_ACTIVE_HIGH>; - }; - - gpio_in { - gpio-export,name = "gpio_in"; - gpio-export,input = <0>; - gpio-export,direction_may_change = <0>; - gpios = <&stm32_io 24 GPIO_ACTIVE_LOW>; - }; - }; - }; -}; - -&blsp1_i2c3 { - status = "okay"; - pinctrl-0 = <&i2c_0_pins>; - pinctrl-names = "default"; - clock-frequency = <400000>; - - stm32_io: stm32@74 { - compatible = "tlt,stm32v1"; - #gpio-cells = <2>; - #interrupt-cells = <2>; - gpio-controller; - interrupt-controller; - interrupt-parent = <&tlmm>; - interrupts = <5 2>; - reg = <0x74>; }; }; diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-rutx10.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-rutx10.dts index 31d14aa6ae1..8fc976a11b1 100644 --- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-rutx10.dts +++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-rutx10.dts @@ -22,6 +22,43 @@ linux,default-trigger = "phy1tpt"; }; }; + + gpio_export { + compatible = "gpio-export"; + #size-cells = <0>; + + gpio_out { + gpio-export,name = "gpio_out"; + gpio-export,output = <0>; + gpio-export,direction_may_change = <0>; + gpios = <&stm32_io 23 GPIO_ACTIVE_HIGH>; + }; + + gpio_in { + gpio-export,name = "gpio_in"; + gpio-export,input = <0>; + gpio-export,direction_may_change = <0>; + gpios = <&stm32_io 24 GPIO_ACTIVE_LOW>; + }; + }; + }; +}; + +&blsp1_i2c3 { + status = "okay"; + pinctrl-0 = <&i2c_0_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + + stm32_io: stm32@74 { + compatible = "tlt,stm32v1"; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + interrupt-parent = <&tlmm>; + interrupts = <5 2>; + reg = <0x74>; }; }; diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-rutx50.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-rutx50.dts new file mode 100644 index 00000000000..ea2102f7d6a --- /dev/null +++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-rutx50.dts @@ -0,0 +1,181 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcom-ipq4018-rutx.dtsi" + +/ { + model = "Teltonika RUTX50"; + compatible = "teltonika,rutx50"; + + aliases { + led-boot = &led_rssi0; + led-failsafe = &led_rssi0; + led-running = &led_rssi0; + led-upgrade = &led_rssi0; + label-mac-device = &gmac; + }; + + soc { + gpio-export { + compatible = "gpio-export"; + #size-cells = <0>; + + gpio_modem_reset { + gpio-export,name = "modem_reset"; + gpio-export,output = <0>; + gpios = <&shift_io 8 GPIO_ACTIVE_HIGH>; + }; + + gpio_modem_power { + gpio-export,name = "modem_power"; + gpio-export,output = <0>; + gpios = <&shift_io 9 GPIO_ACTIVE_HIGH>; + }; + + gpio_out_1 { + gpio-export,name = "sim-select"; + /* 0 = SIM1 ; 1 = SIM2 */ + gpio-export,output = <0>; + gpios = <&shift_io 10 GPIO_ACTIVE_HIGH>; + }; + + gpio_in_1 { + gpio-export,name = "sim-detect"; + gpio-export,input = <0>; + gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "green:sim1"; + gpios = <&shift_io 14 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + label = "green:sim2"; + gpios = <&shift_io 15 GPIO_ACTIVE_HIGH>; + }; + + led-2 { + label = "green:eth"; + gpios = <&shift_io 6 GPIO_ACTIVE_HIGH>; + }; + + led-3 { + label = "green:wifi"; + gpios = <&shift_io 7 GPIO_ACTIVE_HIGH>; + }; + + led-4 { + label = "green:3g"; + gpios = <&shift_io 5 GPIO_ACTIVE_HIGH>; + }; + + led-5 { + label = "green:4g"; + gpios = <&shift_io 4 GPIO_ACTIVE_HIGH>; + }; + + led-6 { + label = "green:5g"; + gpios = <&shift_io 3 GPIO_ACTIVE_HIGH>; + }; + + led_rssi0: led-7 { + label = "green:rssi0"; + gpios = <&shift_io 0 GPIO_ACTIVE_HIGH>; + }; + + led-8 { + label = "green:rssi1"; + gpios = <&shift_io 1 GPIO_ACTIVE_HIGH>; + }; + + led-9 { + label = "green:rssi2"; + gpios = <&shift_io 2 GPIO_ACTIVE_HIGH>; + }; + + led-10 { + label = "green:wifi2g"; + gpios = <&shift_io 12 GPIO_ACTIVE_HIGH>; + }; + + led-11 { + label = "green:wifi5g"; + gpios = <&shift_io 13 GPIO_ACTIVE_HIGH>; + }; + }; + + spi-gpio { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + gpio-sck = <&tlmm 1 GPIO_ACTIVE_HIGH>; + gpio-mosi = <&tlmm 3 GPIO_ACTIVE_HIGH>; + cs-gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; + + shift_io: shift_io@0 { + compatible = "fairchild,74hc595"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + /* Attn: This is specific to RUTX50 in Teltonika GPL */ + registers-number = <2>; + spi-max-frequency = <10000000>; + }; + }; + }; +}; + +&wifi0 { + status = "okay"; + qcom,ath10k-calibration-variant = "Teltonika-RUTX10"; +}; + +&wifi1 { + status = "okay"; + qcom,ath10k-calibration-variant = "Teltonika-RUTX10"; +}; + +&gmac { + status = "okay"; +}; + +&switch { + status = "okay"; +}; + +&swport1 { + status = "okay"; + + label = "lan1"; +}; + +&swport2 { + status = "okay"; + + label = "lan2"; +}; + +&swport3 { + status = "okay"; + + label = "lan3"; +}; + +&swport4 { + status = "okay"; + + label = "lan4"; +}; + +&swport5 { + status = "okay"; + + label = "wan"; +}; diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-fritzrepeater-3000.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-fritzrepeater-3000.dts index 8d88bc15211..41dec725424 100644 --- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-fritzrepeater-3000.dts +++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-fritzrepeater-3000.dts @@ -121,6 +121,9 @@ status = "okay"; nand@0 { + /delete-property/ nand-ecc-strength; + /delete-property/ nand-ecc-step-size; + partitions { compatible = "fixed-partitions"; #address-cells = <1>; diff --git a/target/linux/ipq40xx/image/generic.mk b/target/linux/ipq40xx/image/generic.mk index f15463ae8ca..a9dd2aa0912 100644 --- a/target/linux/ipq40xx/image/generic.mk +++ b/target/linux/ipq40xx/image/generic.mk @@ -1076,6 +1076,22 @@ endef # Missing DSA Setup #TARGET_DEVICES += teltonika_rutx10 +define Device/teltonika_rutx50 + $(call Device/FitImage) + $(call Device/UbiFit) + DEVICE_VENDOR := Teltonika + DEVICE_MODEL := RUTX50 + SOC := qcom-ipq4018 + DEVICE_DTS_CONFIG := config@5 + KERNEL_INSTALL := 1 + BLOCKSIZE := 128k + PAGESIZE := 2048 + FILESYSTEMS := squashfs + IMAGE/factory.ubi := append-ubi + DEVICE_PACKAGES := ipq-wifi-teltonika_rutx kmod-usb-net-qmi-wwan kmod-usb-serial-option uqmi +endef +TARGET_DEVICES += teltonika_rutx50 + define Device/tel_x1pro $(call Device/FitImage) DEVICE_VENDOR := Telco diff --git a/target/linux/ipq806x/Makefile b/target/linux/ipq806x/Makefile index 81fda2964db..108abce6b30 100644 --- a/target/linux/ipq806x/Makefile +++ b/target/linux/ipq806x/Makefile @@ -10,8 +10,7 @@ CPU_TYPE:=cortex-a15 CPU_SUBTYPE:=neon-vfpv4 SUBTARGETS:=generic chromium -KERNEL_PATCHVER:=5.15 -KERNEL_TESTING_PATCHVER:=6.1 +KERNEL_PATCHVER:=6.1 KERNELNAME:=zImage Image dtbs diff --git a/target/linux/ipq806x/base-files/etc/board.d/02_network b/target/linux/ipq806x/base-files/etc/board.d/02_network index 70812a1013c..bc45298da65 100644 --- a/target/linux/ipq806x/base-files/etc/board.d/02_network +++ b/target/linux/ipq806x/base-files/etc/board.d/02_network @@ -6,101 +6,123 @@ . /lib/functions/uci-defaults.sh . /lib/functions/system.sh +ipq806x_setup_interfaces() +{ + local board="$1" + + case "$board" in + arris,tr4400-v2) + ucidef_set_interfaces_lan_wan "eth1" "eth2" + ucidef_add_switch "switch0" \ + "1:lan" "2:lan" "3:lan" "4:lan" "6u@eth1" "0u@eth0" + ;; + askey,rt4230w-rev6 |\ + asrock,g10 |\ + nec,wg2600hp) + ucidef_add_switch "switch0" \ + "2:lan" "3:lan" "4:lan" "5:lan" "6@eth1" "1:wan" "0@eth0" + ;; + buffalo,wxr-2533dhp |\ + compex,wpq864 |\ + netgear,d7800 |\ + netgear,r7500 |\ + netgear,r7500v2 |\ + qcom,ipq8064-ap148) + ucidef_add_switch "switch0" \ + "1:lan" "2:lan" "3:lan" "4:lan" "6@eth1" "5:wan" "0@eth0" + ;; + edgecore,ecw5410) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ;; + linksys,ea7500-v1) + ucidef_add_switch "switch0" \ + "2:lan:1" "3:lan:2" "4:lan:3" "5:lan:4" "6@eth1" "1:wan" "0@eth0" + ;; + linksys,ea8500) + ucidef_add_switch "switch0" \ + "1:lan" "2:lan" "3:lan" "4:lan" "6@eth1" "5:wan" "0@eth0" + ;; + meraki,mr42) + ucidef_set_interface_lan "eth0" + ;; + meraki,mr52) + ucidef_set_interfaces_lan_wan "eth0" "eth1" + ;; + nec,wg2600hp3) + ucidef_add_switch "switch0" \ + "2:lan" "3:lan" "4:lan" "5:lan" "0@eth1" "1:wan" "6@eth0" + ;; + netgear,r7800 |\ + netgear,xr450 |\ + netgear,xr500 |\ + tplink,c2600 |\ + tplink,vr2600v) + ucidef_add_switch "switch0" \ + "1:lan:4" "2:lan:3" "3:lan:2" "4:lan:1" "6@eth1" "5:wan" "0@eth0" + ;; + qcom,ipq8064-ap161) + ucidef_set_interface_lan "eth1 eth2" + ucidef_add_switch "switch0" \ + "0:lan" "1:lan" "2:lan" "3u@eth1" "6:wan" "4u@eth0" + ;; + qcom,ipq8064-db149) + ucidef_set_interface_lan "eth1 eth2 eth3" + ucidef_add_switch "switch0" \ + "1:lan" "2:lan" "3:lan" "4:lan" "6u@eth1" "5:wan" "0u@eth0" + ;; + tplink,ad7200) + ucidef_add_switch "switch0" \ + "2:lan:1" "3:lan:2" "4:lan:3" "5:lan:4" "6@eth1" "1:wan" "0@eth0" + ;; + asus,onhub |\ + tplink,onhub) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ucidef_add_switch "switch0" \ + "1:lan" "6@eth1" "2:wan" "0@eth0" + ;; + nokia,ac400i |\ + ubnt,unifi-ac-hd) + ucidef_set_interface_lan "eth0 eth1" + ;; + zyxel,nbg6817) + ucidef_add_switch "switch0" \ + "1:lan" "2:lan" "3:lan" "4:lan" "6@eth1" "5:wan" "0@eth0" + ;; + *) + echo "Unsupported hardware. Network interfaces not intialized" + ;; + esac +} + +ipq806x_setup_mac_address() +{ + local board="$1" + + case "$board" in + linksys,ea7500-v1) + hw_mac_addr=$(mtd_get_mac_ascii devinfo hw_mac_addr) + ucidef_set_interface_macaddr "lan" "$hw_mac_addr" + ucidef_set_interface_macaddr "wan" "$hw_mac_addr" + ;; + linksys,ea8500) + hw_mac_addr=$(mtd_get_mac_ascii devinfo hw_mac_addr) + ucidef_set_interface_macaddr "lan" "$hw_mac_addr" + ucidef_set_interface_macaddr "wan" "$hw_mac_addr" + ;; + zyxel,nbg6817) + hw_mac_addr=$(mtd_get_mac_ascii 0:appsblenv ethaddr) + ucidef_set_interface_macaddr "lan" "$(macaddr_add $hw_mac_addr 2)" + ucidef_set_interface_macaddr "wan" "$(macaddr_add $hw_mac_addr 3)" + ;; + esac +} + board_config_update board=$(board_name) -case "$board" in -arris,tr4400-v2) - ucidef_set_interfaces_lan_wan "eth1" "eth2" - ucidef_add_switch "switch0" \ - "1:lan" "2:lan" "3:lan" "4:lan" "6u@eth1" "0u@eth0" - ;; -askey,rt4230w-rev6 |\ -asrock,g10 |\ -nec,wg2600hp) - ucidef_add_switch "switch0" \ - "2:lan" "3:lan" "4:lan" "5:lan" "6@eth1" "1:wan" "0@eth0" - ;; -buffalo,wxr-2533dhp |\ -compex,wpq864 |\ -netgear,d7800 |\ -netgear,r7500 |\ -netgear,r7500v2 |\ -qcom,ipq8064-ap148) - ucidef_add_switch "switch0" \ - "1:lan" "2:lan" "3:lan" "4:lan" "6@eth1" "5:wan" "0@eth0" - ;; -edgecore,ecw5410) - ucidef_set_interfaces_lan_wan "eth1" "eth0" - ;; -linksys,ea7500-v1) - hw_mac_addr=$(mtd_get_mac_ascii devinfo hw_mac_addr) - ucidef_add_switch "switch0" \ - "2:lan:1" "3:lan:2" "4:lan:3" "5:lan:4" "6@eth1" "1:wan" "0@eth0" - ucidef_set_interface_macaddr "lan" "$hw_mac_addr" - ucidef_set_interface_macaddr "wan" "$hw_mac_addr" - ;; -linksys,ea8500) - hw_mac_addr=$(mtd_get_mac_ascii devinfo hw_mac_addr) - ucidef_add_switch "switch0" \ - "1:lan" "2:lan" "3:lan" "4:lan" "6@eth1" "5:wan" "0@eth0" - ucidef_set_interface_macaddr "lan" "$hw_mac_addr" - ucidef_set_interface_macaddr "wan" "$hw_mac_addr" - ;; -meraki,mr42) - ucidef_set_interface_lan "eth0" - ;; -meraki,mr52) - ucidef_set_interfaces_lan_wan "eth0" "eth1" - ;; -nec,wg2600hp3) - ucidef_add_switch "switch0" \ - "2:lan" "3:lan" "4:lan" "5:lan" "0@eth1" "1:wan" "6@eth0" - ;; -netgear,r7800 |\ -netgear,xr450 |\ -netgear,xr500 |\ -tplink,c2600 |\ -tplink,vr2600v) - ucidef_add_switch "switch0" \ - "1:lan:4" "2:lan:3" "3:lan:2" "4:lan:1" "6@eth1" "5:wan" "0@eth0" - ;; -qcom,ipq8064-ap161) - ucidef_set_interface_lan "eth1 eth2" - ucidef_add_switch "switch0" \ - "0:lan" "1:lan" "2:lan" "3u@eth1" "6:wan" "4u@eth0" - ;; -qcom,ipq8064-db149) - ucidef_set_interface_lan "eth1 eth2 eth3" - ucidef_add_switch "switch0" \ - "1:lan" "2:lan" "3:lan" "4:lan" "6u@eth1" "5:wan" "0u@eth0" - ;; -tplink,ad7200) - ucidef_add_switch "switch0" \ - "2:lan:1" "3:lan:2" "4:lan:3" "5:lan:4" "6@eth1" "1:wan" "0@eth0" - ;; -asus,onhub |\ -tplink,onhub) - ucidef_set_interfaces_lan_wan "eth1" "eth0" - ucidef_add_switch "switch0" \ - "1:lan" "6@eth1" "2:wan" "0@eth0" - ;; -nokia,ac400i |\ -ubnt,unifi-ac-hd) - ucidef_set_interface_lan "eth0 eth1" - ;; -zyxel,nbg6817) - hw_mac_addr=$(mtd_get_mac_ascii 0:appsblenv ethaddr) - ucidef_add_switch "switch0" \ - "1:lan" "2:lan" "3:lan" "4:lan" "6@eth1" "5:wan" "0@eth0" - ucidef_set_interface_macaddr "lan" "$(macaddr_add $hw_mac_addr 2)" - ucidef_set_interface_macaddr "wan" "$(macaddr_add $hw_mac_addr 3)" - ;; -*) - echo "Unsupported hardware. Network interfaces not intialized" - ;; -esac +ipq806x_setup_mac_address $board +ipq806x_setup_interfaces $board board_config_flush diff --git a/target/linux/ipq806x/config-5.15 b/target/linux/ipq806x/config-5.15 deleted file mode 100644 index 1f456b2ce9f..00000000000 --- a/target/linux/ipq806x/config-5.15 +++ /dev/null @@ -1,507 +0,0 @@ -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_APQ_GCC_8084 is not set -# CONFIG_APQ_MMCC_8084 is not set -CONFIG_AR8216_PHY=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -# CONFIG_ARCH_IPQ40XX is not set -CONFIG_ARCH_KEEP_MEMBLOCK=y -# CONFIG_ARCH_MDM9615 is not set -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MSM8960=y -CONFIG_ARCH_MSM8974=y -CONFIG_ARCH_MSM8X60=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_QCOM=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM=y -CONFIG_ARM_AMBA=y -CONFIG_ARM_APPENDED_DTB=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_ATAG_DTB_COMPAT=y -# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y -CONFIG_ARM_CPUIDLE=y -CONFIG_ARM_CPU_SUSPEND=y -# CONFIG_ARM_CPU_TOPOLOGY is not set -CONFIG_ARM_CRYPTO=y -CONFIG_ARM_GIC=y -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_IPQ806X_FAB_DEVFREQ=y -CONFIG_ARM_KRAIT_CACHE_DEVFREQ=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -# CONFIG_ARM_QCOM_CPUFREQ_HW is not set -CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y -CONFIG_ARM_QCOM_SPM_CPUIDLE=y -# CONFIG_ARM_SMMU is not set -CONFIG_ARM_THUMB=y -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_AT803X_PHY=y -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BOUNCE=y -# CONFIG_CACHE_L2X0 is not set -CONFIG_CLKSRC_QCOM=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE_OVERRIDE=y -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_QCOM=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPUFREQ_DT=y -CONFIG_CPUFREQ_DT_PLATDEV=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_FREQ=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -# CONFIG_CPU_FREQ_GOV_USERSPACE is not set -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THERMAL=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRC16=y -# CONFIG_CRC32_SARWATE is not set -CONFIG_CRC32_SLICEBY8=y -CONFIG_CRC8=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DEV_QCOM_RNG=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_GPIO=y -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -CONFIG_DEVFREQ_GOV_PASSIVE=y -# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set -# CONFIG_DEVFREQ_GOV_POWERSAVE is not set -# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set -# CONFIG_DEVFREQ_GOV_USERSPACE is not set -# CONFIG_DEVFREQ_THERMAL is not set -CONFIG_DMADEVICES=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_OPS=y -CONFIG_DMA_REMAP=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DTC=y -CONFIG_DT_IDLE_STATES=y -# CONFIG_DWMAC_GENERIC is not set -CONFIG_DWMAC_IPQ806X=y -# CONFIG_DWMAC_QCOM_ETHQOS is not set -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_ETHERNET_PACKET_MANGLE=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_VDSO_32=y -CONFIG_GLOB=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_CDEV=y -CONFIG_GRO_CELLS=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_SMP=y -CONFIG_HIGHMEM=y -# CONFIG_HIGHPTE is not set -CONFIG_HOTPLUG_CPU=y -CONFIG_HWMON=y -CONFIG_HWSPINLOCK=y -CONFIG_HWSPINLOCK_QCOM=y -CONFIG_HW_RANDOM=y -CONFIG_HZ_FIXED=0 -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_HELPER_AUTO=y -# CONFIG_I2C_QCOM_CCI is not set -CONFIG_I2C_QUP=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_IOMMU_DEBUGFS is not set -# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set -# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set -CONFIG_IOMMU_SUPPORT=y -# CONFIG_IPQ_APSS_PLL is not set -# CONFIG_IPQ_GCC_4019 is not set -# CONFIG_IPQ_GCC_6018 is not set -CONFIG_IPQ_GCC_806X=y -# CONFIG_IPQ_GCC_8074 is not set -# CONFIG_IPQ_LCC_806X is not set -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_KMAP_LOCAL=y -CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y -CONFIG_KPSS_XCC=y -CONFIG_KRAITCC=y -CONFIG_KRAIT_CLOCKS=y -CONFIG_KRAIT_L2_ACCESSORS=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MDIO_BITBANG=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MDIO_GPIO=y -CONFIG_MDIO_IPQ8064=y -# CONFIG_MDM_GCC_9615 is not set -# CONFIG_MDM_LCC_9615 is not set -CONFIG_MEMFD_CREATE=y -# CONFIG_MFD_HI6421_SPMI is not set -CONFIG_MFD_QCOM_RPM=y -# CONFIG_MFD_SPMI_PMIC is not set -CONFIG_MFD_SYSCON=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_ARMMMCI=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_MINORS=16 -CONFIG_MMC_CQHCI=y -CONFIG_MMC_QCOM_DML=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_IO_ACCESSORS=y -CONFIG_MMC_SDHCI_MSM=y -# CONFIG_MMC_SDHCI_PCI is not set -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MSM_GCC_8660=y -# CONFIG_MSM_GCC_8916 is not set -# CONFIG_MSM_GCC_8939 is not set -# CONFIG_MSM_GCC_8960 is not set -# CONFIG_MSM_GCC_8974 is not set -# CONFIG_MSM_GCC_8994 is not set -# CONFIG_MSM_GCC_8996 is not set -# CONFIG_MSM_GCC_8998 is not set -# CONFIG_MSM_GPUCC_8998 is not set -# CONFIG_MSM_IOMMU is not set -# CONFIG_MSM_LCC_8960 is not set -# CONFIG_MSM_MMCC_8960 is not set -# CONFIG_MSM_MMCC_8974 is not set -# CONFIG_MSM_MMCC_8996 is not set -# CONFIG_MSM_MMCC_8998 is not set -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_QCOM=y -CONFIG_MTD_QCOMSMEM_PARTS=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_FIT_FW=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEON=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_QCA8K=y -CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT=y -CONFIG_NET_DSA_TAG_QCA=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_PTP_CLASSIFY=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NLS=y -CONFIG_NO_HZ=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=2 -CONFIG_NVMEM=y -CONFIG_NVMEM_QCOM_QFPROM=y -# CONFIG_NVMEM_SPMI_SDAM is not set -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PAGE_POOL=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_DW=y -CONFIG_PCIE_DW_HOST=y -CONFIG_PCIE_QCOM=y -CONFIG_PCI_DEBUG=y -CONFIG_PCI_DISABLE_COMMON_QUIRKS=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PCS_XPCS=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -# CONFIG_PHY_QCOM_APQ8064_SATA is not set -# CONFIG_PHY_QCOM_IPQ4019_USB is not set -CONFIG_PHY_QCOM_IPQ806X_SATA=y -# CONFIG_PHY_QCOM_IPQ806X_USB is not set -# CONFIG_PHY_QCOM_PCIE2 is not set -# CONFIG_PHY_QCOM_QMP is not set -# CONFIG_PHY_QCOM_QUSB2 is not set -# CONFIG_PHY_QCOM_USB_HS_28NM is not set -# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set -# CONFIG_PHY_QCOM_USB_SS is not set -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_APQ8064 is not set -# CONFIG_PINCTRL_APQ8084 is not set -# CONFIG_PINCTRL_IPQ4019 is not set -# CONFIG_PINCTRL_IPQ6018 is not set -CONFIG_PINCTRL_IPQ8064=y -# CONFIG_PINCTRL_IPQ8074 is not set -# CONFIG_PINCTRL_MDM9615 is not set -CONFIG_PINCTRL_MSM=y -# CONFIG_PINCTRL_MSM8226 is not set -# CONFIG_PINCTRL_MSM8660 is not set -# CONFIG_PINCTRL_MSM8916 is not set -# CONFIG_PINCTRL_MSM8960 is not set -# CONFIG_PINCTRL_MSM8976 is not set -# CONFIG_PINCTRL_MSM8994 is not set -# CONFIG_PINCTRL_MSM8996 is not set -# CONFIG_PINCTRL_MSM8998 is not set -# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set -# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set -# CONFIG_PINCTRL_QCS404 is not set -# CONFIG_PINCTRL_SC7180 is not set -# CONFIG_PINCTRL_SDM660 is not set -# CONFIG_PINCTRL_SDM845 is not set -# CONFIG_PINCTRL_SM8150 is not set -# CONFIG_PINCTRL_SM8250 is not set -CONFIG_PM_DEVFREQ=y -# CONFIG_PM_DEVFREQ_EVENT is not set -CONFIG_PM_OPP=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_MSM=y -CONFIG_POWER_SUPPLY=y -CONFIG_PPS=y -CONFIG_PRINTK_TIME=y -CONFIG_PTP_1588_CLOCK=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -# CONFIG_QCOM_A53PLL is not set -CONFIG_QCOM_ADM=y -CONFIG_QCOM_BAM_DMA=y -CONFIG_QCOM_CLK_RPM=y -# CONFIG_QCOM_COMMAND_DB is not set -# CONFIG_QCOM_CPR is not set -# CONFIG_QCOM_EBI2 is not set -# CONFIG_QCOM_GENI_SE is not set -CONFIG_QCOM_GSBI=y -CONFIG_QCOM_HFPLL=y -# CONFIG_QCOM_IOMMU is not set -# CONFIG_QCOM_LLCC is not set -# CONFIG_QCOM_OCMEM is not set -# CONFIG_QCOM_PDC is not set -# CONFIG_QCOM_RMTFS_MEM is not set -CONFIG_QCOM_RPMCC=y -# CONFIG_QCOM_RPMH is not set -CONFIG_QCOM_SCM=y -# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set -CONFIG_QCOM_SMEM=y -# CONFIG_QCOM_SMSM is not set -CONFIG_QCOM_SOCINFO=y -CONFIG_QCOM_TCSR=y -CONFIG_QCOM_TSENS=y -CONFIG_QCOM_WDT=y -# CONFIG_QCS_GCC_404 is not set -# CONFIG_QCS_Q6SSTOP_404 is not set -# CONFIG_QCS_TURING_404 is not set -CONFIG_RAS=y -CONFIG_RATIONAL=y -CONFIG_RCU_CPU_STALL_TIMEOUT=21 -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -# CONFIG_REGULATOR_QCOM_LABIBB is not set -CONFIG_REGULATOR_QCOM_RPM=y -# CONFIG_REGULATOR_QCOM_SPMI is not set -# CONFIG_REGULATOR_QCOM_USB_VBUS is not set -# CONFIG_REGULATOR_VQMMC_IPQ4019 is not set -CONFIG_RESET_CONTROLLER=y -# CONFIG_RESET_QCOM_AOSS is not set -# CONFIG_RESET_QCOM_PDC is not set -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_MC146818_LIB=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -# CONFIG_SC_DISPCC_7180 is not set -# CONFIG_SC_GCC_7180 is not set -# CONFIG_SC_GPUCC_7180 is not set -# CONFIG_SC_LPASS_CORECC_7180 is not set -# CONFIG_SC_MSS_7180 is not set -# CONFIG_SC_VIDEOCC_7180 is not set -# CONFIG_SDM_CAMCC_845 is not set -# CONFIG_SDM_DISPCC_845 is not set -# CONFIG_SDM_GCC_660 is not set -# CONFIG_SDM_GCC_845 is not set -# CONFIG_SDM_GPUCC_845 is not set -# CONFIG_SDM_LPASSCC_845 is not set -# CONFIG_SDM_VIDEOCC_845 is not set -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_MSM=y -CONFIG_SERIAL_MSM_CONSOLE=y -CONFIG_SGL_ALLOC=y -CONFIG_SMP=y -CONFIG_SMP_ON_UP=y -# CONFIG_SM_GCC_8150 is not set -# CONFIG_SM_GCC_8250 is not set -# CONFIG_SM_GPUCC_8150 is not set -# CONFIG_SM_GPUCC_8250 is not set -# CONFIG_SM_VIDEOCC_8150 is not set -# CONFIG_SM_VIDEOCC_8250 is not set -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SOC_BUS=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_QUP=y -CONFIG_SPMI=y -# CONFIG_SPMI_HISI3670 is not set -CONFIG_SPMI_MSM_PMIC_ARB=y -# CONFIG_SPMI_PMIC_CLKDIV is not set -CONFIG_SRCU=y -CONFIG_STMMAC_ETH=y -CONFIG_STMMAC_PLATFORM=y -CONFIG_SWCONFIG=y -CONFIG_SWCONFIG_LEDS=y -CONFIG_SWPHY=y -CONFIG_SWP_EMULATE=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_OF=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -CONFIG_UBIFS_FS_ADVANCED_COMPR=y -# CONFIG_UCLAMP_TASK is not set -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNWINDER_ARM=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_WATCHDOG_CORE=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts deleted file mode 100644 index 162b28d27fb..00000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts +++ /dev/null @@ -1,332 +0,0 @@ -#include "qcom-ipq8065-smb208.dtsi" - -#include - -/ { - model = "ZyXEL NBG6817"; - compatible = "zyxel,nbg6817", "qcom,ipq8065", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - aliases { - mdio-gpio0 = &mdio0; - sdcc1 = &sdcc1; - - led-boot = &power; - led-failsafe = &power; - led-running = &power; - led-upgrade = &power; - }; - - chosen { - bootargs = "rootfstype=squashfs,ext4 rootwait noinitrd fstools_ignore_partname=1"; - append-rootblock = "root=/dev/mmcblk0p"; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wifi { - label = "wifi"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - internet { - label = "white:internet"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; - }; - - power: power { - label = "white:power"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - wifi2g { - label = "amber:wifi2g"; - gpios = <&qcom_pinmux 33 GPIO_ACTIVE_HIGH>; - }; - - /* wifi2g amber from the manual is missing */ - - wifi5g { - label = "amber:wifi5g"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - }; - - /* wifi5g amber from the manual is missing */ - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio53", "gpio54", "gpio65"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio9", "gpio26", "gpio33", "gpio64"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - mdio0_pins: mdio0-pins { - clk { - pins = "gpio1"; - input-disable; - }; - }; - - rgmii2_pins: rgmii2-pins { - tx { - pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32" ; - input-disable; - }; - }; - - spi_pins: spi_pins { - cs { - pins = "gpio20"; - drive-strength = <12>; - }; - }; - - usb0_pwr_en_pins: usb0_pwr_en_pins { - mux { - pins = "gpio16", "gpio17"; - function = "gpio"; - drive-strength = <12>; - }; - - pwr { - pins = "gpio17"; - bias-pull-down; - output-high; - }; - - ovc { - pins = "gpio16"; - bias-pull-up; - }; - }; - - usb1_pwr_en_pins: usb1_pwr_en_pins { - mux { - pins = "gpio14", "gpio15"; - function = "gpio"; - drive-strength = <12>; - }; - - pwr { - pins = "gpio14"; - bias-pull-down; - output-high; - }; - - ovc { - pins = "gpio15"; - bias-pull-up; - }; - }; -}; - -&gsbi5 { - qcom,mode = ; - status = "okay"; - - spi4: spi@1a280000 { - status = "okay"; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - m25p80@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <51200000>; - reg = <0>; - - partitions { - compatible = "qcom,smem-part"; - }; - }; - }; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; - - pinctrl-0 = <&usb0_pwr_en_pins>; - pinctrl-names = "default"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; - - pinctrl-0 = <&usb1_pwr_en_pins>; - pinctrl-names = "default"; -}; - -&pcie0 { - status = "okay"; - reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_pins>; - pinctrl-names = "default"; -}; - -&pcie1 { - status = "okay"; - reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_pins>; - pinctrl-names = "default"; - max-link-speed = <1>; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0xaa545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - 0x00970 0x1e864443 /* QM_PORT0_CTRL0 */ - 0x00974 0x000001c6 /* QM_PORT0_CTRL1 */ - 0x00978 0x19008643 /* QM_PORT1_CTRL0 */ - 0x0097c 0x000001c6 /* QM_PORT1_CTRL1 */ - 0x00980 0x19008643 /* QM_PORT2_CTRL0 */ - 0x00984 0x000001c6 /* QM_PORT2_CTRL1 */ - 0x00988 0x19008643 /* QM_PORT3_CTRL0 */ - 0x0098c 0x000001c6 /* QM_PORT3_CTRL1 */ - 0x00990 0x19008643 /* QM_PORT4_CTRL0 */ - 0x00994 0x000001c6 /* QM_PORT4_CTRL1 */ - 0x00998 0x1e864443 /* QM_PORT5_CTRL0 */ - 0x0099c 0x000001c6 /* QM_PORT5_CTRL1 */ - 0x009a0 0x1e864443 /* QM_PORT6_CTRL0 */ - 0x009a4 0x000001c6 /* QM_PORT6_CTRL1 */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - qca,ar8327-initvals = < - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x0000c 0x80 /* PAD6_MODE */ - >; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <1>; - qcom,phy_mdio_addr = <4>; - qcom,poll_required = <0>; - qcom,rgmii_delay = <1>; - qcom,phy_mii_type = <0>; - qcom,emulation = <0>; - qcom,irq = <255>; - mdiobus = <&mdio0>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - qcom,phy_mdio_addr = <0>; /* none */ - qcom,poll_required = <0>; /* no polling */ - qcom,rgmii_delay = <0>; - qcom,phy_mii_type = <1>; - qcom,emulation = <0>; - qcom,irq = <258>; - mdiobus = <&mdio0>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&amba { - sdcc1: sdcc@12400000 { - status = "okay"; - }; -}; - -&adm_dma { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts deleted file mode 100644 index c55287a4f12..00000000000 --- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts +++ /dev/null @@ -1,510 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "qcom-ipq8062-smb208.dtsi" -#include - -/ { - model = "NEC Platforms Aterm WG2600HP3"; - compatible = "nec,wg2600hp3", "qcom,ipq8062", "qcom,ipq8064"; - - memory { - device_type = "memory"; - reg = <0x42000000 0x1e000000>; - }; - - aliases { - label-mac-device = &gmac2; - - led-boot = &led_power_green; - led-failsafe = &led_power_red; - led-running = &led_power_green; - led-upgrade = &led_power_red; - }; - - keys { - compatible = "gpio-keys"; - - pinctrl-0 = <&buttons_pins>; - pinctrl-names = "default"; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - mode0 { - label = "mode0"; - gpios = <&qcom_pinmux 40 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - debounce-interval = <60>; - wakeup-source; - }; - - mode1 { - label = "mode1"; - gpios = <&qcom_pinmux 41 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - - pinctrl-0 = <&leds_pins>; - pinctrl-names = "default"; - - led_power_green: power_green { - label = "green:power"; - gpios = <&qcom_pinmux 14 GPIO_ACTIVE_HIGH>; - }; - - led_power_red: power_red { - label = "red:power"; - gpios = <&qcom_pinmux 35 GPIO_ACTIVE_HIGH>; - }; - - active_green { - label = "green:active"; - gpios = <&qcom_pinmux 42 GPIO_ACTIVE_HIGH>; - }; - - active_red { - label = "red:active"; - gpios = <&qcom_pinmux 38 GPIO_ACTIVE_HIGH>; - }; - - wlan2g_green { - label = "green:wlan2g"; - gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy1tpt"; - }; - - wlan2g_red { - label = "red:wlan2g"; - gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>; - }; - - wlan5g_green { - label = "green:wlan5g"; - gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy0tpt"; - }; - - wlan5g_red { - label = "red:wlan5g"; - gpios = <&qcom_pinmux 58 GPIO_ACTIVE_HIGH>; - }; - - tv_green { - label = "green:tv"; - gpios = <&qcom_pinmux 46 GPIO_ACTIVE_HIGH>; - }; - - tv_red { - label = "red:tv"; - gpios = <&qcom_pinmux 36 GPIO_ACTIVE_HIGH>; - }; - - converter_green { - label = "green:converter"; - gpios = <&qcom_pinmux 43 GPIO_ACTIVE_HIGH>; - }; - - converter_red { - label = "red:converter"; - gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -/* nand_pins are used for leds_pins, empty the node - * from ipq8064.dtsi - */ -&nand_pins { - /delete-property/ disable; - /delete-property/ pullups; - /delete-property/ hold; -}; - -&qcom_pinmux { - pinctrl-0 = <&akro_pins>; - pinctrl-names = "default"; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - bias-pull-down; - }; - - data { - pins = "gpio18", "gpio19"; - drive-strength = <10>; - }; - - cs { - pins = "gpio20"; - drive-strength = <10>; - }; - - clk { - pins = "gpio21"; - drive-strength = <12>; - }; - }; - - buttons_pins: buttons_pins { - mux { - pins = "gpio22", "gpio24", "gpio40", - "gpio41"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - leds_pins: leds_pins { - mux { - pins = "gpio14", "gpio15", "gpio35", - "gpio36", "gpio38", "gpio42", - "gpio43", "gpio46", "gpio55", - "gpio56", "gpio57", "gpio58"; - function = "gpio"; - bias-pull-down; - }; - - akro2 { - pins = "gpio15", "gpio35", "gpio38", - "gpio42", "gpio43", "gpio46", - "gpio55", "gpio56", "gpio57", - "gpio58"; - drive-strength = <2>; - }; - - akro4 { - pins = "gpio14", "gpio36"; - drive-strength = <4>; - }; - }; - - /* - * Stock firmware has the following settings, so let's do the same. - * I don't sure why these are required. - */ - akro_pins: akro_pinmux { - akro { - pins = "gpio17", "gpio26", "gpio47"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - reset { - pins = "gpio45"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - output-low; - }; - - gmac0_rgmii { - pins = "gpio25"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - }; - }; -}; - -&gsbi5 { - status = "okay"; - qcom,mode = ; - - spi@1a280000 { - status = "okay"; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "SBL1"; - reg = <0x0000000 0x0020000>; - read-only; - }; - - partition@20000 { - label = "MIBIB"; - reg = <0x0020000 0x0020000>; - read-only; - }; - - partition@40000 { - label = "SBL2"; - reg = <0x0040000 0x0040000>; - read-only; - }; - - partition@80000 { - label = "SBL3"; - reg = <0x0080000 0x0080000>; - read-only; - }; - - partition@100000 { - label = "DDRCONFIG"; - reg = <0x0100000 0x0010000>; - read-only; - }; - - partition@110000 { - label = "SSD"; - reg = <0x0110000 0x0010000>; - read-only; - }; - - partition@120000 { - label = "TZ"; - reg = <0x0120000 0x0080000>; - read-only; - }; - - partition@1a0000 { - label = "RPM"; - reg = <0x01a0000 0x0080000>; - read-only; - }; - - partition@220000 { - label = "APPSBL"; - reg = <0x0220000 0x0080000>; - read-only; - }; - - partition@2a0000 { - label = "APPSBLENV"; - reg = <0x02a0000 0x0010000>; - read-only; - }; - - factory: partition@2b0000 { - label = "PRODUCTDATA"; - reg = <0x02b0000 0x0030000>; - read-only; - }; - - partition@2e0000 { - label = "ART"; - reg = <0x02e0000 0x0040000>; - read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - precal_ART_1000: precal@1000 { - reg = <0x1000 0x2f20>; - }; - - precal_ART_5000: precal@5000 { - reg = <0x5000 0x2f20>; - }; - }; - - partition@320000 { - label = "TP"; - reg = <0x0320000 0x0040000>; - read-only; - }; - - partition@360000 { - label = "TINY"; - reg = <0x0360000 0x0500000>; - read-only; - }; - - partition@860000 { - compatible = "denx,uimage"; - label = "firmware"; - reg = <0x0860000 0x17a0000>; - }; - }; - }; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&pcie0 { - status = "okay"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "qcom,ath10k"; - reg = <0x00010000 0 0 0 0>; - - qcom,ath10k-calibration-variant = "NEC-Platforms-WG2600HP3"; - - nvmem-cells = <&macaddr_PRODUCTDATA_12>, <&precal_ART_1000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - }; - }; -}; - -&pcie1 { - status = "okay"; - force_gen1 = <1>; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "qcom,ath10k"; - reg = <0x00010000 0 0 0 0>; - - ieee80211-freq-limit = <2400000 2483000>; - qcom,ath10k-calibration-variant = "NEC-Platforms-WG2600HP3"; - - nvmem-cells = <&macaddr_PRODUCTDATA_c>, <&precal_ART_5000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x04 0x80080080 /* PAD0_MODE */ - 0x0c 0x06000000 /* PAD6_MODE */ - 0x10 0x002613a0 /* PWS_REG */ - 0x50 0xcc36cc36 /* LED_CTRL0 */ - 0x54 0xca36ca36 /* LED_CTRL1 */ - 0x58 0xc936c936 /* LED_CTRL2 */ - 0x5c 0x03ffff00 /* LED_CTRL3 */ - 0x7c 0x0000004e /* PORT0_STATUS */ - 0x94 0x0000004e /* PORT6_STATUS */ - 0xe0 0xc74164de /* SGMII_CTRL */ - 0xe4 0x0006a545 /* MAC_PWR_SEL */ - >; - }; -}; - -&gmac1 { - status = "okay"; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - phy-mode = "rgmii"; - qcom,id = <1>; - mdiobus = <&mdio0>; - nvmem-cells = <&macaddr_factory_0>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - mdiobus = <&mdio0>; - nvmem-cells = <&macaddr_factory_6>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&factory { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_factory_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_factory_6: macaddr@6 { - reg = <0x6 0x6>; - }; - - macaddr_PRODUCTDATA_c: macaddr@c { - reg = <0xc 0x6>; - }; - - macaddr_PRODUCTDATA_12: macaddr@12 { - reg = <0x12 0x6>; - }; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi deleted file mode 100644 index 3494b2bde2f..00000000000 --- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi +++ /dev/null @@ -1,402 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "qcom-ipq8064-v2.0-smb208.dtsi" - -#include - -/ { - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - reserved-memory { - ramoops@42100000 { - compatible = "ramoops"; - reg = <0x42100000 0x40000>; - record-size = <0x4000>; - console-size = <0x4000>; - ftrace-size = <0x4000>; - pmsg-size = <0x4000>; - }; - }; - - aliases { - mdio-gpio0 = &mdio0; - label-mac-device = &gmac2; - }; -}; - -&qcom_pinmux { - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - bias-pull-down; - }; - - data { - pins = "gpio18", "gpio19"; - drive-strength = <10>; - }; - - cs { - pins = "gpio20"; - function = "gpio"; - drive-strength = <10>; - bias-pull-up; - }; - - clk { - pins = "gpio21"; - drive-strength = <12>; - }; - }; - - usb0_pwr_en_pin: usb0_pwr_en_pin { - mux { - pins = "gpio25"; - function = "gpio"; - drive-strength = <10>; - bias-pull-up; - output-high; - }; - }; - - usb1_pwr_en_pin: usb1_pwr_en_pin { - mux { - pins = "gpio23"; - function = "gpio"; - drive-strength = <10>; - bias-pull-up; - output-high; - }; - }; -}; - -&gsbi5 { - qcom,mode = ; - status = "okay"; - - spi@1a280000 { - status = "okay"; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - reg = <0>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "SBL1"; - reg = <0x0 0x20000>; - read-only; - }; - - partition@20000 { - label = "MIBIB"; - reg = <0x20000 0x20000>; - read-only; - }; - - partition@40000 { - label = "SBL2"; - reg = <0x40000 0x20000>; - read-only; - }; - - partition@60000 { - label = "SBL3"; - reg = <0x60000 0x30000>; - read-only; - }; - - partition@90000 { - label = "DDRCONFIG"; - reg = <0x90000 0x10000>; - read-only; - }; - - partition@a0000 { - label = "SSD"; - reg = <0xa0000 0x10000>; - read-only; - }; - - partition@b0000 { - label = "TZ"; - reg = <0xb0000 0x30000>; - read-only; - }; - - partition@e0000 { - label = "RPM"; - reg = <0xe0000 0x20000>; - read-only; - }; - - partition@100000 { - label = "fs-uboot"; - reg = <0x100000 0x70000>; - read-only; - }; - - partition@170000 { - label = "uboot-env"; - reg = <0x170000 0x40000>; - read-only; - }; - - partition@1b0000 { - label = "radio"; - reg = <0x1b0000 0x40000>; - read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - precal_radio_1000: precal@1000 { - reg = <0x1000 0x2f20>; - }; - - precal_radio_5000: precal@5000 { - reg = <0x5000 0x2f20>; - }; - }; - - partition@1f0000 { - label = "os-image"; - reg = <0x1f0000 0x400000>; - }; - - partition@5f0000 { - label = "rootfs"; - reg = <0x5f0000 0x1900000>; - }; - - defaultmac: partition@1ef0000 { - label = "default-mac"; - reg = <0x1ef0000 0x00200>; - read-only; - }; - - partition@1ef0200 { - label = "pin"; - reg = <0x1ef0200 0x00200>; - read-only; - }; - - partition@1ef0400 { - label = "product-info"; - reg = <0x1ef0400 0x0fc00>; - read-only; - }; - - partition@1f00000 { - label = "partition-table"; - reg = <0x1f00000 0x10000>; - read-only; - }; - - partition@1f10000 { - label = "soft-version"; - reg = <0x1f10000 0x10000>; - read-only; - }; - - partition@1f20000 { - label = "support-list"; - reg = <0x1f20000 0x10000>; - read-only; - }; - - partition@1f30000 { - label = "profile"; - reg = <0x1f30000 0x10000>; - read-only; - }; - - partition@1f40000 { - label = "default-config"; - reg = <0x1f40000 0x10000>; - read-only; - }; - - partition@1f50000 { - label = "user-config"; - reg = <0x1f50000 0x40000>; - read-only; - }; - - partition@1f90000 { - label = "qos-db"; - reg = <0x1f90000 0x40000>; - read-only; - }; - - partition@1fd0000 { - label = "usb-config"; - reg = <0x1fd0000 0x10000>; - read-only; - }; - - partition@1fe0000 { - label = "log"; - reg = <0x1fe0000 0x20000>; - read-only; - }; - }; - }; - }; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; - - pinctrl-0 = <&usb0_pwr_en_pin>; - pinctrl-names = "default"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; - - pinctrl-0 = <&usb1_pwr_en_pin>; - pinctrl-names = "default"; -}; - -&pcie0 { - status = "okay"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_defaultmac_8>, <&precal_radio_1000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - mac-address-increment = <(-1)>; - }; - }; -}; - -&pcie1 { - status = "okay"; - max-link-speed = <1>; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_defaultmac_8>, <&precal_radio_5000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <1>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - nvmem-cells = <&macaddr_defaultmac_8>; - nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - - nvmem-cells = <&macaddr_defaultmac_8>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&defaultmac { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_defaultmac_8: macaddr@8 { - reg = <0x8 0x6>; - }; -}; diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ad7200.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ad7200.dts deleted file mode 100644 index 6cb21fc4f3f..00000000000 --- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ad7200.dts +++ /dev/null @@ -1,135 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "qcom-ipq8064-ad7200-c2600.dtsi" - -/ { - model = "TP-Link Talon AD7200"; - compatible = "tplink,ad7200", "qcom,ipq8064"; - - aliases { - led-boot = &led_status; - led-failsafe = &led_status; - led-running = &led_status; - led-upgrade = &led_status; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wifi { - label = "wifi"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - led_enable { - label = "led-enable"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - lan { - label = "blue:lan"; - gpios = <&qcom_pinmux 2 GPIO_ACTIVE_HIGH>; - }; - - usb1 { - label = "blue:usb1"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - wlan5g { - label = "blue:wlan5g"; - gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>; - }; - - usb3 { - label = "blue:usb3"; - gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>; - }; - - wlan2g { - label = "blue:wlan2g"; - gpios = <&qcom_pinmux 17 GPIO_ACTIVE_HIGH>; - }; - - wan_orange { - label = "orange:wan"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; - }; - - wan_blue { - label = "blue:wan"; - gpios = <&qcom_pinmux 33 GPIO_ACTIVE_LOW>; - }; - - wps { - label = "blue:wps"; - gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>; - }; - - wlan60g { - label = "blue:wlan60g"; - gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>; - }; - - led_status: status { - label = "blue:status"; - gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio53", "gpio54", "gpio67"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio2", "gpio8", "gpio15", "gpio16", "gpio17", "gpio26", - "gpio33", "gpio55", "gpio56", "gpio66"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; -}; - -&pcie2 { - status = "okay"; - max-link-speed = <1>; -}; diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ap148.dts deleted file mode 100644 index d3b7c44877e..00000000000 --- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +++ /dev/null @@ -1,134 +0,0 @@ -#include "qcom-ipq8064-v1.0.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. IPQ8064/AP-148"; - compatible = "qcom,ipq8064-ap148", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - }; - - aliases { - mdio-gpio0 = &mdio0; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&flash { - partitions { - compatible = "qcom,smem-part"; - }; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; - max-link-speed = <1>; -}; - -&nand { - status = "okay"; - - nand@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "qcom,smem-part"; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <1>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ap161.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ap161.dts deleted file mode 100644 index 02ddbf31180..00000000000 --- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ap161.dts +++ /dev/null @@ -1,172 +0,0 @@ -#include "qcom-ipq8064-v1.0.dtsi" - -/ { - model = "Qualcomm IPQ8064/AP161"; - compatible = "qcom,ipq8064-ap161", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - }; - - aliases { - mdio-gpio0 = &mdio0; - }; -}; - -&qcom_pinmux { - rgmii2_pins: rgmii2-pins { - mux { - pins = "gpio27", "gpio28", "gpio29", - "gpio30", "gpio31", "gpio32", - "gpio51", "gpio52", "gpio59", - "gpio60", "gpio61", "gpio62", - "gpio2", "gpio66"; - }; - }; -}; - -&flash { - partitions { - compatible = "qcom,smem-part"; - }; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; - max-link-speed = <1>; -}; - -&pcie2 { - status = "okay"; -}; - -&nand { - status = "okay"; - - nand@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "qcom,smem-part"; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x20080 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - qca,phy-rgmii-en; - qca,txclk-delay-en; - qca,rxclk-delay-en; - }; - - phy3: ethernet-phy@3 { - device_type = "ethernet-phy"; - reg = <3>; - }; -}; - -&gmac0 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <0>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - mdiobus = <&mdio0>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <1>; - mdiobus = <&mdio0>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - mdiobus = <&mdio0>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&adm_dma { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-asus-onhub.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-asus-onhub.dts deleted file mode 100644 index 442bcf19a67..00000000000 --- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-asus-onhub.dts +++ /dev/null @@ -1,92 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2014 The ChromiumOS Authors - */ - -#include "qcom-ipq8064-onhub.dtsi" -#include -#include -#include - -/ { - model = "ASUS OnHub"; - compatible = "asus,onhub", "google,arkham", "qcom,ipq8064"; -}; - -&qcom_pinmux { - ap3223_pins: ap3223_pinmux { - pins = "gpio22"; - function = "gpio"; - bias-none; - }; - - i2c7_pins: i2c7_pinmux { - mux { - pins = "gpio8", "gpio9"; - function = "gsbi7"; - }; - data { - pins = "gpio8"; - bias-disable; - }; - clk { - pins = "gpio9"; - bias-disable; - }; - }; -}; - -&gsbi7 { - status = "okay"; - qcom,mode = ; -}; - -&gsbi7_i2c { - status = "okay"; - clock-frequency = <100000>; - pinctrl-0 = <&i2c7_pins>; - pinctrl-names = "default"; - - ap3223@1c { - compatible = "dynaimage,ap3223"; - reg = <0x1c>; - - pinctrl-0 = <&ap3223_pins>; - pinctrl-names = "default"; - - int-gpio = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>; - }; - - led-controller@32 { - compatible = "national,lp5523"; - reg = <0x32>; - clock-mode = /bits/ 8 <1>; - #address-cells = <1>; - #size-cells = <0>; - - led@4 { - reg = <4>; - color = ; - chan-name = "green:status"; - linux,default-trigger = "default-on"; - led-cur = /bits/ 8 <0xfa>; - max-cur = /bits/ 8 <0xff>; - }; - - led@5 { - reg = <5>; - color = ; - chan-name = "blue:status"; - led-cur = /bits/ 8 <0xfa>; - max-cur = /bits/ 8 <0xff>; - }; - - led@8 { - reg = <8>; - color = ; - chan-name = "red:status"; - led-cur = /bits/ 8 <0xfa>; - max-cur = /bits/ 8 <0xff>; - }; - }; -}; diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-c2600.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-c2600.dts deleted file mode 100644 index cef1aba3444..00000000000 --- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-c2600.dts +++ /dev/null @@ -1,119 +0,0 @@ -#include "qcom-ipq8064-ad7200-c2600.dtsi" - -/ { - model = "TP-Link Archer C2600"; - compatible = "tplink,c2600", "qcom,ipq8064"; - - aliases { - led-boot = &power; - led-failsafe = &general; - led-running = &power; - led-upgrade = &general; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wifi { - label = "wifi"; - gpios = <&qcom_pinmux 49 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - ledswitch { - label = "ledswitch"; - gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - lan { - label = "white:lan"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_HIGH>; - }; - - usb4 { - label = "white:usb_4"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - usb2 { - label = "white:usb_2"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - wps { - label = "white:wps"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - wan_amber { - label = "amber:wan"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; - }; - - wan_white { - label = "white:wan"; - gpios = <&qcom_pinmux 33 GPIO_ACTIVE_LOW>; - }; - - power: power { - label = "white:power"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - general: general { - label = "white:general"; - gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio16", "gpio54", "gpio65"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio6", "gpio7", "gpio8", "gpio9", "gpio26", "gpio33", - "gpio53", "gpio66"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; -}; diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-d7800.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-d7800.dts deleted file mode 100644 index b8273c614ae..00000000000 --- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-d7800.dts +++ /dev/null @@ -1,394 +0,0 @@ -#include "qcom-ipq8064-v2.0-smb208.dtsi" - -#include - -/ { - model = "Netgear Nighthawk X4 D7800"; - compatible = "netgear,d7800", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - reserved-memory { - rsvd@5fe00000 { - reg = <0x5fe00000 0x200000>; - reusable; - }; - }; - - aliases { - mdio-gpio0 = &mdio0; - - led-boot = &power_white; - led-failsafe = &power_amber; - led-running = &power_white; - led-upgrade = &power_amber; - }; - - chosen { - bootargs = "rootfstype=squashfs noinitrd"; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wifi { - label = "wifi"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - usb1 { - label = "white:usb1"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - usb2 { - label = "white:usb2"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - power_amber: power_amber { - label = "amber:power"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - wan_white { - label = "white:wan"; - gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; - }; - - wan_amber { - label = "amber:wan"; - gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; - }; - - wps { - label = "white:wps"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; - }; - - esata { - label = "white:esata"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - }; - - power_white: power_white { - label = "white:power"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - wifi { - label = "white:wifi"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio6", "gpio54", "gpio65"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23", - "gpio24","gpio26", "gpio53", "gpio64"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - usb0_pwr_en_pins: usb0_pwr_en_pins { - mux { - pins = "gpio15"; - function = "gpio"; - drive-strength = <12>; - bias-pull-down; - output-high; - }; - }; - - usb1_pwr_en_pins: usb1_pwr_en_pins { - mux { - pins = "gpio16", "gpio68"; - function = "gpio"; - drive-strength = <12>; - bias-pull-down; - output-high; - }; - }; -}; - -&sata_phy { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; - - pinctrl-0 = <&usb0_pwr_en_pins>; - pinctrl-names = "default"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; - - pinctrl-0 = <&usb1_pwr_en_pins>; - pinctrl-names = "default"; -}; - -&pcie0 { - status = "okay"; - reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&pcie0_pins>; - pinctrl-names = "default"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_art_6>, <&precal_art_1000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - mac-address-increment = <(1)>; - }; - }; -}; - -&pcie1 { - status = "okay"; - reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&pcie1_pins>; - pinctrl-names = "default"; - max-link-speed = <1>; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_art_6>, <&precal_art_5000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - mac-address-increment = <(2)>; - }; - }; -}; - -&pcie2 { - status = "okay"; - reset-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&pcie2_pins>; - pinctrl-names = "default"; -}; - -&nand { - status = "okay"; - - nand@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - nand-is-boot-medium; - qcom,boot-partitions = <0x0 0x1180000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - qcadata@0 { - label = "qcadata"; - reg = <0x0000000 0x0c80000>; - read-only; - }; - - APPSBL@c80000 { - label = "APPSBL"; - reg = <0x0c80000 0x0500000>; - read-only; - }; - - APPSBLENV@1180000 { - label = "APPSBLENV"; - reg = <0x1180000 0x0080000>; - read-only; - }; - - art@1200000 { - label = "art"; - reg = <0x1200000 0x0140000>; - read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; - - precal_art_1000: precal@1000 { - reg = <0x1000 0x2f20>; - }; - - precal_art_5000: precal@5000 { - reg = <0x5000 0x2f20>; - }; - }; - - artbak: art@1340000 { - label = "artbak"; - reg = <0x1340000 0x0140000>; - read-only; - }; - - kernel@1480000 { - label = "kernel"; - reg = <0x1480000 0x0400000>; - }; - - ubi@1880000 { - label = "ubi"; - reg = <0x1880000 0x6080000>; - }; - - reserve@7900000 { - label = "reserve"; - reg = <0x7900000 0x0700000>; - read-only; - }; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <1>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - nvmem-cells = <&macaddr_art_6>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - - nvmem-cells = <&macaddr_art_0>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&adm_dma { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-db149.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-db149.dts deleted file mode 100644 index f628df919b4..00000000000 --- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-db149.dts +++ /dev/null @@ -1,179 +0,0 @@ -#include "qcom-ipq8064-v1.0.dtsi" - -/ { - model = "Qualcomm IPQ8064/DB149"; - compatible = "qcom,ipq8064-db149", "qcom,ipq8064"; - - aliases { - serial0 = &gsbi2_serial; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - }; -}; - -&qcom_pinmux { - rgmii0_pins: rgmii0_pins { - mux { - pins = "gpio2", "gpio66"; - drive-strength = <8>; - bias-disable; - }; - }; -}; - -&gsbi2 { - qcom,mode = ; - status = "okay"; - - gsbi2_serial: serial@12490000 { - status = "okay"; - }; -}; - -&gsbi4 { - status = "disabled"; -}; - -&gsbi4_serial { - status = "disabled"; -}; - -&flash { - m25p,fast-read; - - partition@0 { - label = "lowlevel_init"; - reg = <0x0 0x1b0000>; - }; - - partition@1 { - label = "u-boot"; - reg = <0x1b0000 0x80000>; - }; - - partition@2 { - label = "u-boot-env"; - reg = <0x230000 0x40000>; - }; - - partition@3 { - label = "caldata"; - reg = <0x270000 0x40000>; - }; - - partition@4 { - label = "firmware"; - reg = <0x2b0000 0x1d50000>; - }; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&pcie2 { - status = "okay"; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - }; - - phy6: ethernet-phy@6 { - reg = <6>; - }; - - phy7: ethernet-phy@7 { - reg = <7>; - }; -}; - -&gmac0 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <0>; - phy-handle = <&phy4>; - - pinctrl-0 = <&rgmii0_pins>; - pinctrl-names = "default"; -}; - -&gmac1 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <1>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - phy-handle = <&phy6>; -}; - -&gmac3 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <3>; - phy-handle = <&phy7>; -}; diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ea7500-v1.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ea7500-v1.dts deleted file mode 100644 index 9d82d52d273..00000000000 --- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ea7500-v1.dts +++ /dev/null @@ -1,91 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "qcom-ipq8064-eax500.dtsi" - -/ { - model = "Linksys EA7500 V1 WiFi Router"; - compatible = "linksys,ea7500-v1", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0xe000000>; - device_type = "memory"; - }; - - aliases { - led-boot = &led_power; - led-failsafe = &led_power; - led-running = &led_power; - led-upgrade = &led_power; - }; - - chosen { - /* look for root deviceblock nbr in this bootarg */ - find-rootblock = "ubi.mtd="; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - led_power: power { - label = "white:power"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio65", "gpio68"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio6"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; -}; - -&partitions { - partition@5f80000 { - label = "sysdiag"; - reg = <0x5f80000 0x100000>; - }; - - partition@6080000 { - label = "syscfg"; - reg = <0x6080000 0x1f80000>; - }; -}; diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts deleted file mode 100644 index 1c6a4bdacd0..00000000000 --- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts +++ /dev/null @@ -1,128 +0,0 @@ -#include "qcom-ipq8064-eax500.dtsi" - -/ { - model = "Linksys EA8500 WiFi Router"; - compatible = "linksys,ea8500", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - aliases { - mdio-gpio0 = &mdio0; - - led-boot = &led_power; - led-failsafe = &led_power; - led-running = &led_power; - led-upgrade = &led_power; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wifi { - label = "wifi"; - gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - wps { - label = "green:wps"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - }; - - led_power: power { - label = "white:power"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - wifi { - label = "green:wifi"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio65", "gpio67", "gpio68"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio6", "gpio53", "gpio54"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; -}; - -&sata_phy { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&partitions { - partition@5f80000 { - label = "syscfg"; - reg = <0x5f80000 0x2080000>; - }; -}; - -&mdio0 { - phy4: ethernet-phy@4 { - reg = <4>; - }; -}; - -&gmac1 { - qcom,phy_mdio_addr = <4>; - qcom,poll_required = <1>; - qcom,rgmii_delay = <0>; - qcom,emulation = <0>; -}; - -/* LAN */ -&gmac2 { - qcom,phy_mdio_addr = <0>; /* none */ - qcom,poll_required = <0>; /* no polling */ - qcom,rgmii_delay = <0>; - qcom,emulation = <0>; -}; diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi deleted file mode 100644 index 910bd86bc5f..00000000000 --- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi +++ /dev/null @@ -1,232 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "qcom-ipq8064-v2.0-smb208.dtsi" - -#include - -/ { - chosen { - bootargs = "console=ttyMSM0,115200n8"; - /* append to bootargs adding the root deviceblock nbr from bootloader */ - append-rootblock = "ubi.mtd="; - }; -}; - -&qcom_pinmux { - /* eax500 routers reuse the pcie2 reset pin for switch reset pin */ - switch_reset: switch_reset_pins { - mux { - pins = "gpio63"; - function = "gpio"; - drive-strength = <12>; - bias-pull-up; - }; - }; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; - - max-link-speed = <1>; -}; - -&pcie1 { - status = "okay"; -}; - -&nand { - status = "okay"; - - nand@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - nand-is-boot-medium; - qcom,boot-partitions = <0x0 0x0c80000>; - - partitions: partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "SBL1"; - reg = <0x0000000 0x0040000>; - read-only; - }; - - partition@40000 { - label = "MIBIB"; - reg = <0x0040000 0x0140000>; - read-only; - }; - - partition@180000 { - label = "SBL2"; - reg = <0x0180000 0x0140000>; - read-only; - }; - - partition@2c0000 { - label = "SBL3"; - reg = <0x02c0000 0x0280000>; - read-only; - }; - - partition@540000 { - label = "DDRCONFIG"; - reg = <0x0540000 0x0120000>; - read-only; - }; - - partition@660000 { - label = "SSD"; - reg = <0x0660000 0x0120000>; - read-only; - }; - - partition@780000 { - label = "TZ"; - reg = <0x0780000 0x0280000>; - read-only; - }; - - partition@a00000 { - label = "RPM"; - reg = <0x0a00000 0x0280000>; - read-only; - }; - - art: partition@c80000 { - label = "art"; - reg = <0x0c80000 0x0140000>; - read-only; - }; - - partition@dc0000 { - label = "APPSBL"; - reg = <0x0dc0000 0x0100000>; - read-only; - }; - - partition@ec0000 { - label = "u_env"; - reg = <0x0ec0000 0x0040000>; - }; - - partition@f00000 { - label = "s_env"; - reg = <0x0f00000 0x0040000>; - }; - - partition@f40000 { - label = "devinfo"; - reg = <0x0f40000 0x0040000>; - }; - - partition@f80000 { - label = "kernel1"; - reg = <0x0f80000 0x2800000>; /* 4 MB, spill to rootfs */ - }; - - partition@1380000 { - label = "rootfs1"; - reg = <0x1380000 0x2400000>; - }; - - partition@3780000 { - label = "kernel2"; - reg = <0x3780000 0x2800000>; - }; - - partition@3b80000 { - label = "rootfs2"; - reg = <0x3b80000 0x2400000>; - }; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - /* Switch from documentation require at least 10ms for reset */ - reset-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_HIGH>; - reset-post-delay-us = <12000>; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x00010 0x2613a0 /* PWS_REG */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; -}; - -&gmac1 { - status = "okay"; - - phy-mode = "rgmii"; - qcom,id = <1>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - - phy-mode = "sgmii"; - qcom,id = <2>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&adm_dma { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-g10.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-g10.dts deleted file mode 100644 index 63a72b53ae7..00000000000 --- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-g10.dts +++ /dev/null @@ -1,292 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-ipq8064-v2.0-smb208.dtsi" - -#include -#include - -/ { - compatible = "asrock,g10", "qcom,ipq8064"; - model = "ASRock G10"; - - aliases { - ethernet0 = &gmac1; - ethernet1 = &gmac0; - - led-boot = &led_status_blue; - led-failsafe = &led_status_amber; - led-running = &led_status_blue; - led-upgrade = &led_status_amber; - }; - - chosen { - bootargs-override = "console=ttyMSM0,115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - /* - * this is a bit misleading. Because there are about seven - * multicolor LEDs connected all wired together in parallel. - */ - - status_yellow { - label = "yellow:status"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - led_status_amber: status_amber { - label = "amber:status"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - led_status_blue: status_blue { - label = "blue:status"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - /* - * LED is declared in vendors boardfile but it's not - * working and the manual doesn't mention anything - * about the LED being white. - - status_white { - label = "white:status"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - }; - */ - }; - - i2c-gpio { - #address-cells = <1>; - #size-cells = <0>; - - compatible = "i2c-gpio"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>, /* sda */ - <&qcom_pinmux 54 GPIO_ACTIVE_HIGH>; /* scl */ - i2c-gpio,delay-us = <5>; - i2c-gpio,scl-output-only; - - mcu@50 { - reg = <0x50>; - compatible = "sonix,sn8f25e21"; - }; - }; - - keys { - compatible = "gpio-keys"; - - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - ir-remote { - label = "ir-remote"; - gpios = <&qcom_pinmux 15 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps5g { - label = "wps5g"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps2g { - label = "wps2g"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&gmac1 { - status = "okay"; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - phy-mode = "rgmii"; - qcom,id = <1>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - - phy-mode = "sgmii"; - qcom,id = <2>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gsbi4_serial { - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; -}; - -&nand { - status = "okay"; - - nand@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - nand-is-boot-medium; - qcom,boot-partitions = <0x0 0x1200000>; - - partitions { - compatible = "qcom,smem-part"; - }; - }; -}; - -&pcie0 { - status = "okay"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi5g: wifi@1,0 { - reg = <0x00010000 0 0 0 0>; - compatible = "qcom,ath10k"; - qcom,ath10k-calibration-variant = "ASRock-G10"; - }; - }; -}; - -&pcie1 { - status = "okay"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi2g: wifi@1,0 { - reg = <0x00010000 0 0 0 0>; - compatible = "qcom,ath10k"; - qcom,ath10k-calibration-variant = "ASRock-G10"; - }; - }; -}; - -&qcom_pinmux { - led_pins: led_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", "gpio26"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - button_pins: button_pins { - mux { - pins = "gpio15", "gpio16", "gpio64", "gpio65"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - uart0_pins: uart0_pins { - mux { - pins = "gpio10", "gpio11"; - function = "gsbi4"; - drive-strength = <10>; - bias-disable; - }; - }; -}; - -&rpm { - pinctrl-0 = <&i2c4_pins>; - pinctrl-names = "default"; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&tcsr { - qcom,usb-ctrl-select = ; -}; - -/delete-node/ &pcie2_pins; -/delete-node/ &pcie2; diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-onhub.dtsi b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-onhub.dtsi deleted file mode 100644 index 549c4620261..00000000000 --- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-onhub.dtsi +++ /dev/null @@ -1,491 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2014 The ChromiumOS Authors - */ - -#include "qcom-ipq8064-smb208.dtsi" -#include -#include -#include - -/ { - aliases { - ethernet0 = &gmac0; - ethernet1 = &gmac2; - mdio-gpio0 = &mdio; - serial0 = &gsbi4_serial; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - dev { - label = "dev"; - gpios = <&qcom_pinmux 15 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - mdio: mdio { - compatible = "virtual,mdio-gpio"; - #address-cells = <1>; - #size-cells = <0>; - gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>, - <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0xaa545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; - - soc { - rng@1a500000 { - status = "disabled"; - }; - - sound { - compatible = "google,storm-audio"; - qcom,model = "ipq806x-storm"; - cpu = <&lpass>; - codec = <&max98357a>; - }; - - lpass: lpass@28100000 { - status = "okay"; - pinctrl-names = "default", "idle"; - pinctrl-0 = <&mi2s_default>; - pinctrl-1 = <&mi2s_idle>; - }; - - max98357a: max98357a { - compatible = "maxim,max98357a"; - #sound-dai-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmode_pins>; - sdmode-gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&qcom_pinmux { - rgmii0_pins: rgmii0_pins { - mux { - pins = "gpio2", "gpio66"; - drive-strength = <8>; - bias-disable; - }; - }; - mi2s_pins { - mi2s_default: mi2s_default { - dout { - pins = "gpio32"; - function = "mi2s"; - drive-strength = <16>; - bias-disable; - }; - sync { - pins = "gpio27"; - function = "mi2s"; - drive-strength = <16>; - bias-disable; - }; - clk { - pins = "gpio28"; - function = "mi2s"; - drive-strength = <16>; - bias-disable; - }; - }; - mi2s_idle: mi2s_idle { - dout { - pins = "gpio32"; - function = "mi2s"; - drive-strength = <2>; - bias-pull-down; - }; - sync { - pins = "gpio27"; - function = "mi2s"; - drive-strength = <2>; - bias-pull-down; - }; - clk { - pins = "gpio28"; - function = "mi2s"; - drive-strength = <2>; - bias-pull-down; - }; - }; - }; - - mdio_pins: mdio_pins { - mux { - pins = "gpio0", "gpio1"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - }; - rst { - pins = "gpio26"; - output-low; - }; - }; - - sdmode_pins: sdmode_pinmux { - pins = "gpio25"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - }; - - sdcc1_pins: sdcc1_pinmux { - mux { - pins = "gpio38", "gpio39", "gpio40", - "gpio41", "gpio42", "gpio43", - "gpio44", "gpio45", "gpio46", - "gpio47"; - function = "sdc1"; - }; - cmd { - pins = "gpio45"; - drive-strength = <10>; - bias-pull-up; - }; - data { - pins = "gpio38", "gpio39", "gpio40", - "gpio41", "gpio43", "gpio44", - "gpio46", "gpio47"; - drive-strength = <10>; - bias-pull-up; - }; - clk { - pins = "gpio42"; - drive-strength = <16>; - bias-pull-down; - }; - }; - - i2c1_pins: i2c1_pinmux { - pins = "gpio53", "gpio54"; - function = "gsbi1"; - bias-disable; - }; - - rpm_i2c_pinmux: rpm_i2c_pinmux { - mux { - pins = "gpio12", "gpio13"; - function = "gsbi4"; - drive-strength = <12>; - bias-disable; - }; - }; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - bias-pull-down; - /delete-property/ bias-none; - /delete-property/ drive-strength; - }; - data { - pins = "gpio18", "gpio19"; - drive-strength = <10>; - }; - cs { - pins = "gpio20"; - drive-strength = <10>; - bias-pull-up; - }; - clk { - pins = "gpio21"; - drive-strength = <12>; - }; - }; - - fw_pinmux { - wp { - pins = "gpio17"; - output-low; - }; - }; - - button_pins: button_pins { - recovery { - pins = "gpio16"; - function = "gpio"; - bias-none; - }; - developer { - pins = "gpio15"; - function = "gpio"; - bias-none; - }; - }; - - spi6_pins: spi6_pins { - mux { - pins = "gpio55", "gpio56", "gpio58"; - function = "gsbi6"; - bias-pull-down; - }; - data { - pins = "gpio55", "gpio56"; - drive-strength = <10>; - }; - cs { - pins = "gpio57"; - drive-strength = <10>; - bias-pull-up; - output-high; - }; - clk { - pins = "gpio58"; - drive-strength = <12>; - }; - }; -}; - -&gmac0 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <0>; - phy-handle = <&phy1>; - - pinctrl-0 = <&rgmii0_pins>; - pinctrl-names = "default"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - phy-handle = <&phy0>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gsbi1 { - status = "okay"; - qcom,mode = ; -}; - -&gsbi1_i2c { - status = "okay"; - - clock-frequency = <100000>; - - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - - tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - powered-while-suspended; - }; -}; - -&gsbi4 { - status = "okay"; - qcom,mode = ; -}; - -&gsbi4_serial { - status = "okay"; -}; - -&gsbi5 { - status = "okay"; - qcom,mode = ; - - spi4: spi@1a280000 { - status = "okay"; - spi-max-frequency = <50000000>; - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 0>; - - flash: flash@0 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - }; - }; -}; - -&gsbi6 { - status = "okay"; - qcom,mode = ; -}; - -&gsbi6_spi { - status = "okay"; - spi-max-frequency = <25000000>; - - pinctrl-0 = <&spi6_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>; - - dmas = <&adm_dma 8 0xb>, - <&adm_dma 7 0x14>; - dma-names = "rx", "tx"; - - /* - * This "spidev" was included in the manufacturer device tree. I suspect - * it's the (unused) Zigbee radio -- SiliconLabs EM3581 Zigbee? There's - * no driver or binding for this at the moment. - */ - spidev@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <25000000>; - }; -}; - -&pcie0 { - status = "okay"; - - pcie@0 { - reg = <0 0 0 0 0>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - device_type = "pci"; - - ath10k@0,0 { - reg = <0 0 0 0 0>; - device_type = "pci"; - qcom,ath10k-sa-gpio = <2 3 4 0>; - qcom,ath10k-sa-gpio-func = <5 5 5 0>; - }; - }; -}; - -&pcie1 { - status = "okay"; - - pcie@0 { - reg = <0 0 0 0 0>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - device_type = "pci"; - - ath10k@0,0 { - reg = <0 0 0 0 0>; - device_type = "pci"; - qcom,ath10k-sa-gpio = <2 3 4 0>; - qcom,ath10k-sa-gpio-func = <5 5 5 0>; - }; - }; -}; - -&pcie2 { - status = "okay"; - - pcie@0 { - reg = <0 0 0 0 0>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - device_type = "pci"; - - ath10k@0,0 { - reg = <0 0 0 0 0>; - device_type = "pci"; - }; - }; -}; - -&rpm { - pinctrl-0 = <&rpm_i2c_pinmux>; - pinctrl-names = "default"; -}; - -&sdcc1 { - status = "okay"; - pinctrl-0 = <&sdcc1_pins>; - pinctrl-names = "default"; - /delete-property/ mmc-ddr-1_8v; -}; - -&tcsr { - compatible = "qcom,tcsr-ipq8064", "qcom,tcsr", "syscon"; - qcom,usb-ctrl-select = ; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-r7500.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-r7500.dts deleted file mode 100644 index 7bea5b6bceb..00000000000 --- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-r7500.dts +++ /dev/null @@ -1,327 +0,0 @@ -#include "qcom-ipq8064-v1.0.dtsi" - -#include -#include - -/ { - model = "Netgear Nighthawk X4 R7500"; - compatible = "netgear,r7500", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0xe000000>; - device_type = "memory"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - }; - - aliases { - mdio-gpio0 = &mdio0; - - led-boot = &power_white; - led-failsafe = &power_amber; - led-running = &power_white; - led-upgrade = &power_amber; - }; - - chosen { - bootargs = "rootfstype=squashfs noinitrd"; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wifi { - label = "wifi"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - usb1 { - label = "white:usb1"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - usb2 { - label = "white:usb2"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - power_amber: power_amber { - label = "amber:power"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - wan_white { - label = "white:wan"; - gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; - }; - - wan_amber { - label = "amber:wan"; - gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; - }; - - wps { - label = "white:wps"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; - }; - - esata { - label = "white:esata"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - }; - - power_white: power_white { - label = "white:power"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - wifi { - label = "white:wifi"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio6", "gpio54", "gpio65"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23", - "gpio24","gpio26", "gpio53", "gpio64"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; -}; - -&gsbi5 { - status = "disabled"; - - spi@1a280000 { - status = "disabled"; - }; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; - max-link-speed = <1>; -}; - -&nand { - status = "okay"; - - nand@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - nand-is-boot-medium; - qcom,boot-partitions = <0x0 0x1180000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - qcadata@0 { - label = "qcadata"; - reg = <0x0000000 0x0c80000>; - read-only; - }; - - APPSBL@c80000 { - label = "APPSBL"; - reg = <0x0c80000 0x0500000>; - read-only; - }; - - APPSBLENV@1180000 { - label = "APPSBLENV"; - reg = <0x1180000 0x0080000>; - read-only; - }; - - art: art@1200000 { - label = "art"; - reg = <0x1200000 0x0140000>; - read-only; - }; - - kernel@1340000 { - label = "kernel"; - reg = <0x1340000 0x0400000>; - }; - - ubi@1740000 { - label = "ubi"; - reg = <0x1740000 0x1600000>; - }; - - netgear@2d40000 { - label = "netgear"; - reg = <0x2d40000 0x0c00000>; - read-only; - }; - - reserve@3940000 { - label = "reserve"; - reg = <0x3940000 0x46c0000>; - read-only; - }; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <1>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - nvmem-cells = <&macaddr_art_6>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - - nvmem-cells = <&macaddr_art_0>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&tcsr { - qcom,usb-ctrl-select = ; - compatible = "qcom,tcsr"; -}; - -&adm_dma { - status = "okay"; -}; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; -}; diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts deleted file mode 100644 index 6f0ba09c872..00000000000 --- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts +++ /dev/null @@ -1,387 +0,0 @@ -#include "qcom-ipq8064-v2.0-smb208.dtsi" - -#include - -/ { - model = "Netgear Nighthawk X4 R7500v2"; - compatible = "netgear,r7500v2", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - reserved-memory { - rsvd@5fe00000 { - reg = <0x5fe00000 0x200000>; - reusable; - }; - }; - - aliases { - mdio-gpio0 = &mdio0; - - led-boot = &power; - led-failsafe = &power; - led-running = &power; - led-upgrade = &power; - }; - - chosen { - bootargs = "rootfstype=squashfs noinitrd"; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wifi { - label = "wifi"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - usb1 { - label = "amber:usb1"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - usb3 { - label = "amber:usb3"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - status { - label = "amber:status"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - internet { - label = "white:internet"; - gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; - }; - - wan { - label = "white:wan"; - gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; - }; - - wps { - label = "white:wps"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; - }; - - esata { - label = "white:esata"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - }; - - power: power { - label = "white:power"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - wifi { - label = "white:wifi"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio6", "gpio54", "gpio65"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23", - "gpio24","gpio26", "gpio53", "gpio64"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - usb0_pwr_en_pins: usb0_pwr_en_pins { - mux { - pins = "gpio15"; - function = "gpio"; - drive-strength = <12>; - bias-pull-down; - output-high; - }; - }; - - usb1_pwr_en_pins: usb1_pwr_en_pins { - mux { - pins = "gpio16", "gpio68"; - function = "gpio"; - drive-strength = <12>; - bias-pull-down; - output-high; - }; - }; -}; - -&sata_phy { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; - - pinctrl-0 = <&usb0_pwr_en_pins>; - pinctrl-names = "default"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; - - pinctrl-0 = <&usb1_pwr_en_pins>; - pinctrl-names = "default"; -}; - -&pcie0 { - status = "okay"; - reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_pins>; - pinctrl-names = "default"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_art_6>, <&precal_art_1000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - mac-address-increment = <(1)>; - }; - }; -}; - -&pcie1 { - status = "okay"; - reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_pins>; - pinctrl-names = "default"; - max-link-speed = <1>; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_art_6>, <&precal_art_5000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - mac-address-increment = <(2)>; - }; - }; -}; - -&nand { - status = "okay"; - - nand@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - nand-is-boot-medium; - qcom,boot-partitions = <0x0 0x1180000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - qcadata@0 { - label = "qcadata"; - reg = <0x0000000 0x0c80000>; - read-only; - }; - - APPSBL@c80000 { - label = "APPSBL"; - reg = <0x0c80000 0x0500000>; - read-only; - }; - - APPSBLENV@1180000 { - label = "APPSBLENV"; - reg = <0x1180000 0x0080000>; - read-only; - }; - - art@1200000 { - label = "art"; - reg = <0x1200000 0x0140000>; - read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; - - precal_art_1000: precal@1000 { - reg = <0x1000 0x2f20>; - }; - - precal_art_5000: precal@5000 { - reg = <0x5000 0x2f20>; - }; - }; - - artbak: art@1340000 { - label = "artbak"; - reg = <0x1340000 0x0140000>; - read-only; - }; - - kernel@1480000 { - label = "kernel"; - reg = <0x1480000 0x0400000>; - }; - - ubi@1880000 { - label = "ubi"; - reg = <0x1880000 0x6080000>; - }; - - reserve@7900000 { - label = "reserve"; - reg = <0x7900000 0x0700000>; - read-only; - }; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0xaa545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <1>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - nvmem-cells = <&macaddr_art_6>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - - nvmem-cells = <&macaddr_art_0>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-tplink-onhub.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-tplink-onhub.dts deleted file mode 100644 index 6adc6be4aec..00000000000 --- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-tplink-onhub.dts +++ /dev/null @@ -1,209 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2014 The ChromiumOS Authors - */ - -#include "qcom-ipq8064-onhub.dtsi" -#include -#include -#include - -/ { - model = "TP-Link OnHub"; - compatible = "tplink,onhub", "google,whirlwind-sp5", "qcom,ipq8064"; -}; - -&qcom_pinmux { - i2c7_pins: i2c7_pinmux { - mux { - pins = "gpio8", "gpio9"; - function = "gsbi7"; - }; - data { - pins = "gpio8"; - bias-disable; - }; - clk { - pins = "gpio9"; - bias-disable; - }; - }; -}; - -&gsbi7 { - status = "okay"; - qcom,mode = ; -}; - -&gsbi7_i2c { - status = "okay"; - clock-frequency = <100000>; - pinctrl-0 = <&i2c7_pins>; - pinctrl-names = "default"; - - led-controller@32 { - compatible = "national,lp5523"; - reg = <0x32>; - clock-mode = /bits/ 8 <1>; - #address-cells = <1>; - #size-cells = <0>; - - led@0 { - reg = <0>; - color = ; - chan-name = "red:status-0"; - linux,default-trigger = "default-on"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - - led@1 { - reg = <1>; - color = ; - chan-name = "green:status-0"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - - led@2 { - reg = <2>; - color = ; - chan-name = "blue:status-0"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - - led@3 { - reg = <3>; - color = ; - chan-name = "red:status-1"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - - led@4 { - reg = <4>; - color = ; - chan-name = "green:status-1"; - linux,default-trigger = "default-on"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - - led@5 { - reg = <5>; - color = ; - chan-name = "blue:status-1"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - - led@6 { - reg = <6>; - color = ; - chan-name = "red:status-2"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - - led@7 { - reg = <7>; - color = ; - chan-name = "green:status-2"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - - led@8 { - reg = <8>; - color = ; - chan-name = "blue:status-2"; - linux,default-trigger = "default-on"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - }; - - led-controller@33 { - compatible = "national,lp5523"; - reg = <0x33>; - clock-mode = /bits/ 8 <1>; - #address-cells = <1>; - #size-cells = <0>; - - led@0 { - reg = <0>; - color = ; - chan-name = "red:status-3"; - linux,default-trigger = "default-on"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - - led@1 { - reg = <1>; - color = ; - chan-name = "green:status-3"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - - led@2 { - reg = <2>; - color = ; - chan-name = "blue:status-3"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - - led@3 { - reg = <3>; - color = ; - chan-name = "red:status-4"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - - led@4 { - reg = <4>; - color = ; - chan-name = "green:status-4"; - linux,default-trigger = "default-on"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - - led@5 { - reg = <5>; - color = ; - chan-name = "blue:status-4"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - - led@6 { - reg = <6>; - color = ; - chan-name = "red:status-5"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - - led@7 { - reg = <7>; - color = ; - chan-name = "green:status-5"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - - led@8 { - reg = <8>; - color = ; - chan-name = "blue:status-5"; - linux,default-trigger = "default-on"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - }; -}; diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts deleted file mode 100644 index 90927ddb856..00000000000 --- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts +++ /dev/null @@ -1,315 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "qcom-ipq8064-v2.0-smb208.dtsi" - -#include -#include - -/ { - model = "Ubiquiti UniFi AC HD"; - compatible = "ubnt,unifi-ac-hd", "qcom,ipq8064"; - - aliases { - label-mac-device = &gmac2; - led-boot = &led_dome_white; - led-failsafe = &led_dome_white; - led-running = &led_dome_blue; - led-upgrade = &led_dome_blue; - mdio-gpio0 = &mdio0; - ethernet0 = &gmac2; - ethernet1 = &gmac1; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - led_dome_blue: dome_blue { - label = "blue:dome"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - led_dome_white: dome_white { - label = "white:dome"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - }; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio68"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio9", "gpio53"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - output-low; - }; - }; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - drive-strength = <10>; - bias-none; - }; - - cs { - pins = "gpio20"; - drive-strength = <12>; - }; - }; -}; - -&CPU_SPC { - status = "disabled"; -}; - -&gsbi5 { - status = "okay"; - - qcom,mode = ; - - spi@1a280000 { - status = "okay"; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - cs-gpios = <&qcom_pinmux 20 0>; - - flash@0 { - compatible = "mx25u25635f", "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - reg = <0>; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "SBL1"; - reg = <0x0 0x20000>; - read-only; - }; - - partition@20000 { - label = "MIBIB"; - reg = <0x20000 0x10000>; - read-only; - }; - - partition@30000 { - label = "SBL2"; - reg = <0x30000 0x20000>; - read-only; - }; - - partition@50000 { - label = "SBL3"; - reg = <0x50000 0x30000>; - read-only; - }; - - partition@80000 { - label = "DDRCONFIG"; - reg = <0x80000 0x10000>; - read-only; - }; - - partition@90000 { - label = "SSD"; - reg = <0x90000 0x10000>; - read-only; - }; - - partition@a0000 { - label = "TZ"; - reg = <0xa0000 0x30000>; - read-only; - }; - - partition@d0000 { - label = "RPM"; - reg = <0xd0000 0x20000>; - read-only; - }; - - partition@f0000 { - label = "APPSBL"; - reg = <0xf0000 0xc0000>; - read-only; - }; - - partition@1b0000 { - label = "APPSBLENV"; - reg = <0x1b0000 0x10000>; - read-only; - }; - - eeprom: partition@1c0000 { - label = "EEPROM"; - reg = <0x1c0000 0x10000>; - read-only; - }; - - partition@1d0000 { - label = "bootselect"; - reg = <0x1d0000 0x10000>; - }; - - partition@1e0000 { - compatible = "denx,fit"; - label = "firmware"; - reg = <0x1e0000 0xe70000>; - }; - - partition@1050000 { - label = "kernel1"; - reg = <0x1050000 0xe70000>; - read-only; - }; - - partition@1ec0000 { - label = "debug"; - reg = <0x1ec0000 0x100000>; - read-only; - }; - - partition@1fc0000 { - label = "cfg"; - reg = <0x1fc0000 0x40000>; - read-only; - }; - }; - }; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&nand { - status = "okay"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy4: ethernet-phy@4 { - reg = <4>; - }; - - phy5: ethernet-phy@5 { - reg = <5>; - }; -}; - -&gmac1 { - status = "okay"; - - mdiobus = <&mdio0>; - phy-handle = <&phy5>; - phy-mode = "sgmii"; - qcom,id = <1>; - - nvmem-cells = <&macaddr_eeprom_6>; - nvmem-cell-names = "mac-address"; -}; - -&gmac2 { - status = "okay"; - - mdiobus = <&mdio0>; - phy-handle = <&phy4>; - phy-mode = "sgmii"; - qcom,id = <2>; - - nvmem-cells = <&macaddr_eeprom_0>; - nvmem-cell-names = "mac-address"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&tcsr { - status = "okay"; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&eeprom { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_eeprom_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_eeprom_6: macaddr@6 { - reg = <0x6 0x6>; - }; -}; diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts deleted file mode 100644 index b0db8c88635..00000000000 --- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts +++ /dev/null @@ -1,424 +0,0 @@ -#include "qcom-ipq8064-v2.0-smb208.dtsi" - -#include - -/ { - model = "TP-Link Archer VR2600v"; - compatible = "tplink,vr2600v", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - aliases { - mdio-gpio0 = &mdio0; - - led-boot = &power; - led-failsafe = &general; - led-running = &power; - led-upgrade = &general; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wifi { - label = "wifi"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - dect { - label = "dect"; - gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - ledswitch { - label = "ledswitch"; - gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - dsl { - label = "white:dsl"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - usb { - label = "white:usb"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - lan { - label = "white:lan"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - wlan2g { - label = "white:wlan2g"; - gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>; - }; - - wlan5g { - label = "white:wlan5g"; - gpios = <&qcom_pinmux 17 GPIO_ACTIVE_HIGH>; - }; - - power: power { - label = "white:power"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - phone { - label = "white:phone"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - }; - - wan { - label = "white:wan"; - gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>; - }; - - general: general { - label = "white:general"; - gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&qcom_pinmux { - led_pins: led_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", "gpio16", "gpio17", - "gpio26", "gpio53", "gpio56", "gpio66"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - button_pins: button_pins { - mux { - pins = "gpio54", "gpio64", "gpio65", "gpio67", "gpio68"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - bias-pull-down; - }; - - data { - pins = "gpio18", "gpio19"; - drive-strength = <10>; - }; - - cs { - pins = "gpio20"; - drive-strength = <10>; - bias-pull-up; - }; - - clk { - pins = "gpio21"; - drive-strength = <12>; - }; - }; -}; - -&gsbi5 { - qcom,mode = ; - status = "okay"; - - spi4: spi@1a280000 { - status = "okay"; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - reg = <0>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "SBL1"; - reg = <0x0 0x20000>; - read-only; - }; - - partition@20000 { - label = "MIBIB"; - reg = <0x20000 0x20000>; - read-only; - }; - - partition@40000 { - label = "SBL2"; - reg = <0x40000 0x40000>; - read-only; - }; - - partition@80000 { - label = "SBL3"; - reg = <0x80000 0x80000>; - read-only; - }; - - partition@100000 { - label = "DDRCONFIG"; - reg = <0x100000 0x10000>; - read-only; - }; - - partition@110000 { - label = "SSD"; - reg = <0x110000 0x10000>; - read-only; - }; - - partition@120000 { - label = "TZ"; - reg = <0x120000 0x80000>; - read-only; - }; - - partition@1a0000 { - label = "RPM"; - reg = <0x1a0000 0x80000>; - read-only; - }; - - partition@220000 { - label = "APPSBL"; - reg = <0x220000 0x80000>; - read-only; - }; - - partition@2a0000 { - label = "APPSBLENV"; - reg = <0x2a0000 0x40000>; - read-only; - }; - - partition@2e0000 { - label = "OLDART"; - reg = <0x2e0000 0x40000>; - read-only; - }; - - partition@320000 { - label = "firmware"; - reg = <0x320000 0xc60000>; - compatible = "openwrt,uimage"; - openwrt,offset = <512>; /* account for pad-extra 512 */ - }; - - /* hole 0xf80000 - 0xfaf100 */ - - partition@faf100 { - label = "default-mac"; - reg = <0xfaf100 0x00200>; - read-only; - - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_defaultmac_0: macaddr@0 { - reg = <0x0 0x6>; - }; - }; - - partition@fc0000 { - label = "ART"; - reg = <0xfc0000 0x40000>; - read-only; - - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - precal_ART_1000: precal@1000 { - reg = <0x1000 0x2f20>; - }; - - precal_ART_5000: precal@5000 { - reg = <0x5000 0x2f20>; - }; - }; - }; - }; - }; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_defaultmac_0>, <&precal_ART_1000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - mac-address-increment = <(-1)>; - }; - }; -}; - -&pcie1 { - status = "okay"; - max-link-speed = <1>; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_defaultmac_0>, <&precal_ART_5000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <1>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - nvmem-cells = <&macaddr_defaultmac_0>; - nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - - nvmem-cells = <&macaddr_defaultmac_0>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&adm_dma { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts deleted file mode 100644 index 431c9cd9af8..00000000000 --- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts +++ /dev/null @@ -1,463 +0,0 @@ -#include "qcom-ipq8064-v2.0-smb208.dtsi" - -#include - -/ { - model = "NEC Aterm WG2600HP"; - compatible = "nec,wg2600hp", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - aliases { - mdio-gpio0 = &mdio0; - - led-boot = &power_green; - led-failsafe = &power_red; - led-running = &power_green; - led-upgrade = &power_green; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - bridge { - label = "bridge"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - debounce-interval = <60>; - wakeup-source; - }; - - converter { - label = "converter"; - gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - converter_green { - label = "green:converter"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_HIGH>; - }; - - power_red: power_red { - label = "red:power"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - active_green { - label = "green:active"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - active_red { - label = "red:active"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - power_green: power_green { - label = "green:power"; - gpios = <&qcom_pinmux 14 GPIO_ACTIVE_HIGH>; - }; - - converter_red { - label = "red:converter"; - gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>; - }; - - wlan2g_green { - label = "green:wlan2g"; - gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>; - }; - - wlan2g_red { - label = "red:wlan2g"; - gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>; - }; - - wlan5g_green { - label = "green:wlan5g"; - gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>; - }; - - wlan5g_red { - label = "red:wlan5g"; - gpios = <&qcom_pinmux 58 GPIO_ACTIVE_HIGH>; - }; - - tv_green { - label = "green:tv"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; - }; - - tv_red { - label = "red:tv"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&CPU_SPC { - status = "disabled"; -}; - -&adm_dma { - status = "okay"; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x06000000 /* PAD0_MODE */ - 0x0000c 0x00080080 /* PAD6_MODE */ - 0x000e4 0x0006a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x0000004e /* PORT0_STATUS */ - 0x00094 0x0000004e /* PORT6_STATUS */ - >; - }; - - ethernet-phy@4 { - reg = <4>; - }; -}; - -&gmac1 { - status = "okay"; - - phy-mode = "rgmii"; - qcom,id = <1>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - nvmem-cells = <&macaddr_PRODUCTDATA_6>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - - phy-mode = "sgmii"; - qcom,id = <2>; - - nvmem-cells = <&macaddr_PRODUCTDATA_0>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gsbi5 { - status = "okay"; - - qcom,mode = ; - - spi@1a280000 { - status = "okay"; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - flash@0 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - SBL1@0 { - label = "SBL1"; - reg = <0x0 0x20000>; - read-only; - }; - - MIBIB@20000 { - label = "MIBIB"; - reg = <0x20000 0x20000>; - read-only; - }; - - SBL2@40000 { - label = "SBL2"; - reg = <0x40000 0x40000>; - read-only; - }; - - SBL3@80000 { - label = "SBL3"; - reg = <0x80000 0x80000>; - read-only; - }; - - DDRCONFIG@100000 { - label = "DDRCONFIG"; - reg = <0x100000 0x10000>; - read-only; - }; - - SSD@110000 { - label = "SSD"; - reg = <0x110000 0x10000>; - read-only; - }; - - TZ@120000 { - label = "TZ"; - reg = <0x120000 0x80000>; - read-only; - }; - - RPM@1a0000 { - label = "RPM"; - reg = <0x1a0000 0x80000>; - read-only; - }; - - APPSBL@220000 { - label = "APPSBL"; - reg = <0x220000 0x80000>; - read-only; - }; - - APPSBLENV@2a0000 { - label = "APPSBLENV"; - reg = <0x2a0000 0x10000>; - }; - - PRODUCTDATA: PRODUCTDATA@2b0000 { - label = "PRODUCTDATA"; - reg = <0x2b0000 0x30000>; - read-only; - }; - - ART@2e0000 { - label = "ART"; - reg = <0x2e0000 0x40000>; - read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - precal_ART_1000: precal@1000 { - reg = <0x1000 0x2f20>; - }; - - precal_ART_5000: precal@5000 { - reg = <0x5000 0x2f20>; - }; - }; - - TP@320000 { - label = "TP"; - reg = <0x320000 0x40000>; - read-only; - }; - - TINY@360000 { - label = "TINY"; - reg = <0x360000 0x500000>; - read-only; - }; - - firmware@860000 { - compatible = "denx,uimage"; - label = "firmware"; - reg = <0x860000 0x17a0000>; - }; - }; - }; - }; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; - - pinctrl-0 = <&usb_pwr_en_pins>; - pinctrl-names = "default"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_PRODUCTDATA_12>, <&precal_ART_1000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - }; - }; -}; - -&pcie1 { - status = "okay"; - max-link-speed = <1>; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_PRODUCTDATA_c>, <&precal_ART_5000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio16", "gpio54", "gpio24", "gpio25"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio6", "gpio7", "gpio8", "gpio9", "gpio14", - "gpio15", "gpio55", "gpio56", "gpio57", "gpio58", - "gpio64", "gpio65"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - bias-pull-down; - }; - - data { - pins = "gpio18", "gpio19"; - drive-strength = <10>; - }; - - cs { - pins = "gpio20"; - drive-strength = <10>; - bias-pull-up; - }; - - clk { - pins = "gpio21"; - drive-strength = <12>; - }; - }; - - usb_pwr_en_pins: usb_pwr_en_pins { - mux { - pins = "gpio22"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - output-high; - }; - }; -}; - -&PRODUCTDATA { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_PRODUCTDATA_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_PRODUCTDATA_6: macaddr@6 { - reg = <0x6 0x6>; - }; - - macaddr_PRODUCTDATA_c: macaddr@c { - reg = <0xc 0x6>; - }; - - macaddr_PRODUCTDATA_12: macaddr@12 { - reg = <0x12 0x6>; - }; -}; diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts deleted file mode 100644 index 359b4cd470c..00000000000 --- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts +++ /dev/null @@ -1,473 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (C) 2017 Christian Mehlis - * Copyright (C) 2018 Mathias Kresin - * All rights reserved. - */ - -#include "qcom-ipq8064-v1.0.dtsi" - -#include -#include - -/ { - compatible = "compex,wpq864", "qcom,ipq8064"; - model = "Compex WPQ864"; - - aliases { - mdio-gpio0 = &mdio0; - ethernet0 = &gmac1; - ethernet1 = &gmac0; - - led-boot = &led_pass; - led-failsafe = &led_fail; - led-running = &led_pass; - led-upgrade = &led_pass; - }; - - leds { - compatible = "gpio-leds"; - - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - rss4 { - label = "green:rss4"; - gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; - }; - - rss3 { - label = "green:rss3"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - rss2 { - label = "orange:rss2"; - gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>; - }; - - rss1 { - label = "red:rss1"; - gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; - }; - - led_pass: pass { - label = "green:pass"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - }; - - led_fail: fail { - label = "green:fail"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - usb { - label = "green:usb"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - usb-pcie { - label = "green:usb-pcie"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - }; - - keys { - compatible = "gpio-keys"; - - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - beeper { - compatible = "gpio-beeper"; - - pinctrl-0 = <&beeper_pins>; - pinctrl-names = "default"; - - gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>; - }; -}; - -&rpm { - pinctrl-0 = <&rpm_pins>; - pinctrl-names = "default"; -}; - -&nand { - status = "okay"; - - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - mt29f2g08abbeah4@0 { - compatible = "qcom,nandcs"; - - reg = <0>; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - nand-is-boot-medium; - qcom,boot-partitions = <0x0 0x1180000 0x5340000 0x10c0000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "0:SBL1"; - reg = <0x0000000 0x0040000>; - read-only; - }; - - partition@40000 { - label = "0:MIBIB"; - reg = <0x0040000 0x0140000>; - read-only; - }; - - partition@180000 { - label = "0:SBL2"; - reg = <0x0180000 0x0140000>; - read-only; - }; - - partition@2c0000 { - label = "0:SBL3"; - reg = <0x02c0000 0x0280000>; - read-only; - }; - - partition@540000 { - label = "0:DDRCONFIG"; - reg = <0x0540000 0x0120000>; - read-only; - }; - - partition@660000 { - label = "0:SSD"; - reg = <0x0660000 0x0120000>; - read-only; - }; - - partition@780000 { - label = "0:TZ"; - reg = <0x0780000 0x0280000>; - read-only; - }; - - partition@a00000 { - label = "0:RPM"; - reg = <0x0a00000 0x0280000>; - read-only; - }; - - partition@c80000 { - label = "0:APPSBL"; - reg = <0x0c80000 0x0500000>; - read-only; - }; - - partition@1180000 { - label = "0:APPSBLENV"; - reg = <0x1180000 0x0080000>; - }; - - partition@1200000 { - label = "0:ART"; - reg = <0x1200000 0x0140000>; - }; - - partition@1340000 { - label = "ubi"; - reg = <0x1340000 0x4000000>; - }; - - partition@5340000 { - label = "0:BOOTCONFIG"; - reg = <0x5340000 0x0060000>; - }; - - partition@53a0000 { - label = "0:SBL2_1"; - reg = <0x53a0000 0x0140000>; - read-only; - }; - - partition@54e0000 { - label = "0:SBL3_1"; - reg = <0x54e0000 0x0280000>; - read-only; - }; - - partition@5760000 { - label = "0:DDRCONFIG_1"; - reg = <0x5760000 0x0120000>; - read-only; - }; - - partition@5880000 { - label = "0:SSD_1"; - reg = <0x5880000 0x0120000>; - read-only; - }; - - partition@59a0000 { - label = "0:TZ_1"; - reg = <0x59a0000 0x0280000>; - read-only; - }; - - partition@5c20000 { - label = "0:RPM_1"; - reg = <0x5c20000 0x0280000>; - read-only; - }; - - partition@5ea0000 { - label = "0:BOOTCONFIG1"; - reg = <0x5ea0000 0x0060000>; - }; - - partition@5f00000 { - label = "0:APPSBL_1"; - reg = <0x5f00000 0x0500000>; - read-only; - }; - - partition@6400000 { - label = "ubi_1"; - reg = <0x6400000 0x4000000>; - }; - - partition@a400000 { - label = "unused"; - reg = <0xa400000 0x5c00000>; - }; - }; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - ethernet-phy@4 { - reg = <4>; - }; -}; - -&gmac1 { - status = "okay"; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - phy-mode = "rgmii"; - qcom,id = <1>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - - phy-mode = "sgmii"; - qcom,id = <2>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gsbi4_serial { - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; -}; - -&flash { - compatible = "jedec,spi-nor"; -}; - -&sata_phy { - status = "disabled"; -}; - -&sata { - status = "disabled"; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; - - rx_eq = <2>; - tx_deamp_3_5db = <32>; - mpll = <160>; -}; - -&usb3_0 { - status = "okay"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; - - rx_eq = <2>; - tx_deamp_3_5db = <32>; - mpll = <160>; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; - - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - /delete-property/ perst-gpios; -}; - -&pcie1 { - status = "okay"; -}; - -&pcie2 { - status = "okay"; - - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - /delete-property/ perst-gpios; -}; - -&qcom_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinctrl0 { - pcie0_pcie2_perst { - pins = "gpio3"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - output-high; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", "gpio22", - "gpio23", "gpio24", "gpio25", "gpio53"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - button_pins: button_pins { - mux { - pins = "gpio54"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - beeper_pins: beeper_pins { - mux { - pins = "gpio55"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - rpm_pins: rpm_pins { - mux { - pins = "gpio12", "gpio13"; - function = "gsbi4"; - drive-strength = <10>; - bias-disable; - }; - }; - - uart0_pins: uart0_pins { - mux { - pins = "gpio10", "gpio11"; - function = "gsbi4"; - drive-strength = <10>; - bias-disable; - }; - }; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19"; - function = "gsbi5"; - drive-strength = <10>; - bias-pull-down; - }; - - clk { - pins = "gpio21"; - function = "gsbi5"; - drive-strength = <12>; - bias-pull-down; - }; - - cs { - pins = "gpio20"; - function = "gpio"; - drive-strength = <10>; - bias-pull-up; - }; - }; -}; - -&tcsr { - qcom,usb-ctrl-select = ; -}; diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts deleted file mode 100644 index 39fd81fe553..00000000000 --- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts +++ /dev/null @@ -1,539 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -#include "qcom-ipq8064-v2.0-smb208.dtsi" - -#include - -/ { - model = "Buffalo WXR-2533DHP"; - compatible = "buffalo,wxr-2533dhp", "qcom,ipq8064"; - - memory@42000000 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - aliases { - led-boot = &power; - led-failsafe = &diag; - led-running = &power; - led-upgrade = &power; - }; - - chosen { - /* use "ubi_rootfs" volume in "ubi" partition as rootfs */ - bootargs = "ubi.block=0,1 root=/dev/ubiblock0_1 rootfstype=squashfs"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - usb { - label = "green:usb"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "usbport"; - trigger-sources = <&hub_port0 &hub_port1>; - }; - - guestport { - label = "green:guestport"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - diag: diag { - label = "orange:diag"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - internet_orange { - label = "orange:internet"; - gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>; - }; - - internet_white { - label = "white:internet"; - gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; - }; - - wireless_orange { - label = "orange:wireless"; - gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; - }; - - wireless_white { - label = "white:wireless"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; - }; - - router_orange { - label = "orange:router"; - gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>; - }; - - router_white { - label = "white:router"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; - }; - - power: power { - label = "white:power"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - }; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - power { - label = "power"; - gpios = <&qcom_pinmux 58 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - eject { - label = "eject"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - guest { - label = "guest"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - ap { - label = "ap"; - gpios = <&qcom_pinmux 55 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - debounce-interval = <60>; - wakeup-source; - }; - - router { - label = "router"; - gpios = <&qcom_pinmux 56 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - debounce-interval = <60>; - wakeup-source; - }; - - auto { - label = "auto"; - gpios = <&qcom_pinmux 57 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - debounce-interval = <60>; - wakeup-source; - }; - }; -}; - -&nand { - status = "okay"; - - cs@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - ubi@0 { - label = "ubi"; - reg = <0x0000000 0x4000000>; - }; - - rootfs_1@4000000 { - label = "rootfs_1"; - reg = <0x4000000 0x4000000>; - }; - }; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x07600000 /* PAD0_MODE */ - 0x00008 0x01000000 /* PAD5_MODE */ - 0x0000c 0x00000080 /* PAD6_MODE */ - 0x00050 0xcc35cc35 /* LED_CTRL0 */ - 0x00054 0xca35ca35 /* LED_CTRL1 */ - 0x00058 0xc935c935 /* LED_CTRL2 */ - 0x0005c 0x03ffff00 /* LED_CTRL3 */ - 0x000e4 0x0006a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x0000007e /* PORT0_STATUS */ - 0x00094 0x0000007e /* PORT6_STATUS */ - >; - }; - - ethernet-phy@4 { - reg = <4>; - }; -}; - -&gmac1 { - status = "okay"; - - phy-mode = "rgmii"; - qcom,id = <1>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - nvmem-cells = <&macaddr_ART_6>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - - phy-mode = "sgmii"; - qcom,id = <2>; - - nvmem-cells = <&macaddr_ART_0>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gsbi4_serial { - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; -}; - -&gsbi5 { - status = "okay"; - qcom,mode = ; - - spi@1a280000 { - status = "okay"; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - flash@0 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - SBL1@0 { - label = "SBL1"; - reg = <0x0 0x10000>; - read-only; - }; - - MIBIB@10000 { - label = "MIBIB"; - reg = <0x10000 0x20000>; - read-only; - }; - - SBL2@30000 { - label = "SBL2"; - reg = <0x30000 0x30000>; - read-only; - }; - - SBL3@60000 { - label = "SBL3"; - reg = <0x60000 0x30000>; - read-only; - }; - - DDRCONFIG@90000 { - label = "DDRCONFIG"; - reg = <0x90000 0x10000>; - read-only; - }; - - SSD@a0000 { - label = "SSD"; - reg = <0xa0000 0x10000>; - read-only; - }; - - TZ@b0000 { - label = "TZ"; - reg = <0xb0000 0x30000>; - read-only; - }; - - RPM@e0000 { - label = "RPM"; - reg = <0xe0000 0x20000>; - read-only; - }; - - APPSBL@100000 { - label = "APPSBL"; - reg = <0x100000 0x70000>; - read-only; - }; - - APPSBLENV@170000 { - label = "APPSBLENV"; - reg = <0x170000 0x10000>; - read-only; - }; - - ART@180000 { - label = "ART"; - reg = <0x180000 0x40000>; - read-only; - - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_ART_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_ART_6: macaddr@6 { - reg = <0x6 0x6>; - }; - - macaddr_ART_18: macaddr@18 { - reg = <0x18 0x6>; - }; - - macaddr_ART_1e: macaddr@1e { - reg = <0x1e 0x6>; - }; - - precal_ART_1000: precal@1000 { - reg = <0x1000 0x2f20>; - }; - - precal_ART_5000: precal@5000 { - reg = <0x5000 0x2f20>; - }; - }; - - BOOTCONFIG@1c0000 { - label = "BOOTCONFIG"; - reg = <0x1c0000 0x10000>; - read-only; - }; - - APPSBL_1@1d0000 { - label = "APPSBL_1"; - reg = <0x1d0000 0x70000>; - read-only; - }; - }; - }; - }; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; - - pinctrl-0 = <&usb_pwr_en_pins>; - pinctrl-names = "default"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&dwc3_0 { - #address-cells = <1>; - #size-cells = <0>; - - hub_port0: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; -}; - -&dwc3_1 { - #address-cells = <1>; - #size-cells = <0>; - - hub_port1: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; -}; - -&pcie0 { - status = "okay"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_ART_1e>, <&precal_ART_1000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - }; - }; -}; - -&pcie1 { - status = "okay"; - max-link-speed = <1>; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_ART_18>, <&precal_ART_5000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio6", "gpio54", "gpio55", "gpio56", "gpio57", - "gpio58", "gpio64", "gpio65"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", "gpio16", "gpio22", - "gpio23", "gpio24", "gpio25", "gpio26", "gpio53"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - uart0_pins: uart0_pins { - mux { - pins = "gpio10", "gpio11"; - function = "gsbi4"; - drive-strength = <12>; - bias-disable; - }; - }; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - bias-pull-down; - }; - - data { - pins = "gpio18", "gpio19"; - drive-strength = <10>; - }; - - cs{ - pins = "gpio20"; - drive-strength = <10>; - bias-pull-up; - }; - - clk { - pins = "gpio21"; - drive-strength = <12>; - }; - }; - - usb_pwr_en_pins: usb_pwr_en_pins { - mux{ - pins = "gpio68"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - output-high; - }; - }; -}; diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-ac400i.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-ac400i.dts deleted file mode 100644 index 7151f8de525..00000000000 --- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-ac400i.dts +++ /dev/null @@ -1,318 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "qcom-ipq8065-smb208.dtsi" -#include - -/ { - model = "Nokia AC400i"; - compatible = "nokia,ac400i", "qcom,ipq8065", "qcom,ipq8064"; - - aliases { - mdio-gpio0 = &mdio0; - ethernet0 = &gmac0; - ethernet1 = &gmac1; - - led-boot = &pwr_red; - led-failsafe = &pwr_red; - led-running = &pwr_green; - led-upgrade = &pwr_green; - }; - - chosen { - bootargs-override = " console=ttyMSM0,115200n8 ubi.mtd=ubi root=/dev/ubiblock0_2"; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 15 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - 5g_red { - label = "red:5g"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_HIGH>; - }; - - 5g_green { - label = "green:5g"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; - }; - - 2g_red { - label = "red:2g"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - }; - - 2g_green { - label = "green:2g"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_HIGH>; - }; - - eth1_red { - label = "red:eth1"; - gpios = <&qcom_pinmux 68 GPIO_ACTIVE_HIGH>; - }; - - eth1_green { - label = "green:eth1"; - gpios = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>; - }; - - eth2_red { - label = "red:eth2"; - gpios = <&qcom_pinmux 67 GPIO_ACTIVE_HIGH>; - }; - - eth2_green { - label = "green:eth2"; - gpios = <&qcom_pinmux 23 GPIO_ACTIVE_LOW>; - }; - - ctrl_red { - label = "red:ctrl"; - gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>; - }; - - ctrl_green { - label = "green:ctrl"; - gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>; - }; - - pwr_red: pwr_red { - label = "red:pwr"; - gpios = <&qcom_pinmux 2 GPIO_ACTIVE_LOW>; - }; - - pwr_green: pwr_green { - label = "green:pwr"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&qcom_pinmux { - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19"; - function = "gsbi5"; - drive-strength = <10>; - bias-pull-down; - }; - - clk { - pins = "gpio21"; - function = "gsbi5"; - drive-strength = <12>; - bias-pull-down; - }; - - cs { - pins = "gpio20"; - function = "gpio"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio65", "gpio64", - "gpio53", "gpio54", - "gpio68", "gpio22", - "gpio67", "gpio23", - "gpio55", "gpio56", - "gpio2", "gpio26"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - button_pins: button_pins { - mux { - pins = "gpio15"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - -}; - -&gsbi5 { - qcom,mode = ; - status = "okay"; - - spi4: spi@1a280000 { - status = "okay"; - spi-max-frequency = <50000000>; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - m25p80@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - reg = <0>; - - partitions { - compatible = "qcom,smem-part"; - }; - }; - }; -}; - -&usb3_0 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; - - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - /delete-property/ perst-gpios; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "qcom,ath10k"; - status = "okay"; - reg = <0x00010000 0 0 0 0>; - qcom,ath10k-calibration-variant = "Nokia-AC400i"; - }; - }; -}; - -&pcie1 { - status = "okay"; - - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - /delete-property/ perst-gpios; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "qcom,ath10k"; - status = "okay"; - reg = <0x00010000 0 0 0 0>; - qcom,ath10k-calibration-variant = "Nokia-AC400i"; - }; - }; -}; - -&mdio0 { - status = "okay"; - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - -}; - -//POE -&gmac0 { - status = "okay"; - qcom,id = <0>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - mdiobus = <&mdio0>; - phy-handle = <&phy0>; - phy-mode = "rgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -//LAN1 -&gmac1 { - status = "okay"; - qcom,id = <1>; - - mdiobus = <&mdio0>; - phy-handle = <&phy1>; - phy-mode = "rgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&nand { - status = "okay"; - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - nand@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - rootfs@0 { - label = "rootfs"; - reg = <0x0000000 0x4000000>; - }; - - rootfs_1@4000000 { - label = "rootfs_1"; - reg = <0x4000000 0x4000000>; - }; - - cfg@8000000 { - label = "cfg"; - reg = <0x8000000 0x8000000>; - }; - }; - }; -}; - -&adm_dma { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi deleted file mode 100644 index 2328c497ea1..00000000000 --- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi +++ /dev/null @@ -1,466 +0,0 @@ -#include "qcom-ipq8065-smb208.dtsi" - -#include - -/ { - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - reserved-memory { - rsvd@5fe00000 { - reg = <0x5fe00000 0x200000>; - reusable; - }; - - ramoops@42100000 { - compatible = "ramoops"; - reg = <0x42100000 0x40000>; - record-size = <0x4000>; - console-size = <0x4000>; - ftrace-size = <0x4000>; - pmsg-size = <0x4000>; - }; - }; - - aliases { - label-mac-device = &gmac2; - - led-boot = &power_white; - led-failsafe = &power_amber; - led-running = &power_white; - led-upgrade = &power_amber; - - mdio-gpio0 = &mdio0; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wifi { - label = "wifi"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds: leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - power_white: power_white { - label = "white:power"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - power_amber: power_amber { - label = "amber:power"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - wan_white { - label = "white:wan"; - gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; - }; - - wan_amber { - label = "amber:wan"; - gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; - }; - - wifi { - label = "white:wifi"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; - }; - - wps { - label = "white:wps"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio6", "gpio54", "gpio65"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", - "gpio22", "gpio23", "gpio24", - "gpio26", "gpio53", "gpio64"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - mdio0_pins: mdio0-pins { - clk { - pins = "gpio1"; - input-disable; - }; - }; - - rgmii2_pins: rgmii2-pins { - tx { - pins = "gpio27", "gpio28", "gpio29", - "gpio30", "gpio31", "gpio32"; - input-disable; - }; - }; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - bias-pull-down; - }; - - data { - pins = "gpio18", "gpio19"; - drive-strength = <10>; - }; - - cs { - pins = "gpio20"; - drive-strength = <10>; - bias-pull-up; - }; - - clk { - pins = "gpio21"; - drive-strength = <12>; - }; - }; - - spi6_pins: spi6_pins { - mux { - pins = "gpio55", "gpio56", "gpio58"; - function = "gsbi6"; - bias-pull-down; - }; - - mosi { - pins = "gpio55"; - drive-strength = <12>; - }; - - miso { - pins = "gpio56"; - drive-strength = <14>; - }; - - cs { - pins = "gpio57"; - drive-strength = <12>; - bias-pull-up; - }; - - clk { - pins = "gpio58"; - drive-strength = <12>; - }; - - reset { - pins = "gpio33"; - drive-strength = <10>; - bias-pull-down; - output-high; - }; - }; - - usb0_pwr_en_pins: usb0_pwr_en_pins { - mux { - pins = "gpio15"; - function = "gpio"; - drive-strength = <12>; - bias-pull-down; - output-high; - }; - }; - - usb1_pwr_en_pins: usb1_pwr_en_pins { - mux { - pins = "gpio16", "gpio68"; - function = "gpio"; - drive-strength = <12>; - bias-pull-down; - output-high; - }; - }; -}; - -&nand { - status = "okay"; - - nand@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - nand-is-boot-medium; - qcom,boot-partitions = <0x0 0x1180000>; - - partitions: partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "qcadata"; - reg = <0x0000000 0x0c80000>; - read-only; - }; - - partition@c80000 { - label = "APPSBL"; - reg = <0x0c80000 0x0500000>; - read-only; - }; - - partition@1180000 { - label = "APPSBLENV"; - reg = <0x1180000 0x0080000>; - read-only; - }; - - art: partition@1200000 { - label = "art"; - reg = <0x1200000 0x0140000>; - read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; - - precal_art_1000: precal@1000 { - reg = <0x1000 0x2f20>; - }; - - precal_art_5000: precal@5000 { - reg = <0x5000 0x2f20>; - }; - }; - - partition@1340000 { - label = "artbak"; - reg = <0x1340000 0x0140000>; - read-only; - }; - - partition@1480000 { - label = "kernel"; - reg = <0x1480000 0x0400000>; - }; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0xaa545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - 0x00970 0x1e864443 /* QM_PORT0_CTRL0 */ - 0x00974 0x000001c6 /* QM_PORT0_CTRL1 */ - 0x00978 0x19008643 /* QM_PORT1_CTRL0 */ - 0x0097c 0x000001c6 /* QM_PORT1_CTRL1 */ - 0x00980 0x19008643 /* QM_PORT2_CTRL0 */ - 0x00984 0x000001c6 /* QM_PORT2_CTRL1 */ - 0x00988 0x19008643 /* QM_PORT3_CTRL0 */ - 0x0098c 0x000001c6 /* QM_PORT3_CTRL1 */ - 0x00990 0x19008643 /* QM_PORT4_CTRL0 */ - 0x00994 0x000001c6 /* QM_PORT4_CTRL1 */ - 0x00998 0x1e864443 /* QM_PORT5_CTRL0 */ - 0x0099c 0x000001c6 /* QM_PORT5_CTRL1 */ - 0x009a0 0x1e864443 /* QM_PORT6_CTRL0 */ - 0x009a4 0x000001c6 /* QM_PORT6_CTRL1 */ - >; - qca,ar8327-vlans = < - 0x1 0x5e /* VLAN1 Ports 1/2/3/4/6 */ - 0x2 0x21 /* VLAN2 Ports 0/5 */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - qca,ar8327-initvals = < - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x0000c 0x80 /* PAD6_MODE */ - >; - }; -}; - -&gmac1 { - status = "okay"; - - phy-mode = "rgmii"; - qcom,id = <1>; - qcom,phy_mdio_addr = <4>; - qcom,poll_required = <0>; - qcom,rgmii_delay = <1>; - qcom,phy_mii_type = <0>; - qcom,emulation = <0>; - qcom,irq = <255>; - mdiobus = <&mdio0>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - nvmem-cells = <&macaddr_art_6>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - - phy-mode = "sgmii"; - qcom,id = <2>; - qcom,phy_mdio_addr = <0>; /* none */ - qcom,poll_required = <0>; /* no polling */ - qcom,rgmii_delay = <0>; - qcom,phy_mii_type = <1>; - qcom,emulation = <0>; - qcom,irq = <258>; - mdiobus = <&mdio0>; - - nvmem-cells = <&macaddr_art_0>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&sata_phy { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; - - pinctrl-0 = <&usb0_pwr_en_pins>; - pinctrl-names = "default"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; - - pinctrl-0 = <&usb1_pwr_en_pins>; - pinctrl-names = "default"; -}; - -&pcie0 { - status = "okay"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi0: wifi@1,0 { - compatible = "pci168c,0046"; - reg = <0x00010000 0 0 0 0>; - }; - }; -}; - -&pcie1 { - status = "okay"; - - max-link-speed = <1>; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi1: wifi@1,0 { - compatible = "pci168c,0046"; - reg = <0x00010000 0 0 0 0>; - }; - }; -}; diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-r7800.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-r7800.dts deleted file mode 100644 index bf7c963944b..00000000000 --- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-r7800.dts +++ /dev/null @@ -1,48 +0,0 @@ -#include "qcom-ipq8065-nighthawk.dtsi" - -/ { - model = "Netgear Nighthawk X4S R7800"; - compatible = "netgear,r7800", "qcom,ipq8065", "qcom,ipq8064"; -}; - -&leds { - usb1 { - label = "white:usb1"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - usb2 { - label = "white:usb2"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - esata { - label = "white:esata"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - }; -}; - -&partitions { - partition@1880000 { - label = "ubi"; - reg = <0x1880000 0x6080000>; - }; - - partition@7900000 { - label = "reserve"; - reg = <0x7900000 0x0700000>; - read-only; - }; -}; - -&wifi0 { - nvmem-cells = <&macaddr_art_6>, <&precal_art_1000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - mac-address-increment = <(1)>; -}; - -&wifi1 { - nvmem-cells = <&macaddr_art_6>, <&precal_art_5000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - mac-address-increment = <(2)>; -}; diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts deleted file mode 100644 index 8d9601b6324..00000000000 --- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts +++ /dev/null @@ -1,418 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "qcom-ipq8065-smb208.dtsi" -#include - -/ { - model = "Askey RT4230W REV6"; - compatible = "askey,rt4230w-rev6", "qcom,ipq8065", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x3e000000>; - device_type = "memory"; - }; - - aliases { - led-boot = &ledctrl3; - led-failsafe = &ledctrl1; - led-running = &ledctrl2; - led-upgrade = &ledctrl3; - }; - - chosen { - bootargs = "rootfstype=squashfs noinitrd"; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - ledctrl1: ledctrl1 { - label = "ledctrl1"; - gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; - }; - - ledctrl2: ledctrl2 { - label = "ledctrl2"; - gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; - }; - - ledctrl3: ledctrl3 { - label = "ledctrl3"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio54", "gpio68"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio22", "gpio23", "gpio24"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - rgmii2_pins: rgmii2-pins { - mux { - pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", - "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62"; - function = "rgmii2"; - drive-strength = <8>; - bias-disable; - }; - - tx { - pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32"; - input-disable; - }; - }; - - spi_pins: spi_pins { - cs { - pins = "gpio20"; - drive-strength = <12>; - }; - }; -}; - -&gsbi5 { - qcom,mode = ; - status = "okay"; - - spi@1a280000 { - status = "okay"; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - flash@0 { - compatible = "everspin,mr25h256"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <40000000>; - reg = <0>; - }; - }; -}; - -&nand { - status = "okay"; - - nand@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - qcom,boot-partitions = <0x0 0x1180000 0x1340000 0x10c0000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "0:SBL1"; - reg = <0x0000000 0x0040000>; - read-only; - }; - - partition@40000 { - label = "0:MIBIB"; - reg = <0x0040000 0x0140000>; - read-only; - }; - - partition@180000 { - label = "0:SBL2"; - reg = <0x0180000 0x0140000>; - read-only; - }; - - partition@2c0000 { - label = "0:SBL3"; - reg = <0x02c0000 0x0280000>; - read-only; - }; - - partition@540000 { - label = "0:DDRCONFIG"; - reg = <0x0540000 0x0120000>; - read-only; - }; - - partition@660000 { - label = "0:SSD"; - reg = <0x0660000 0x0120000>; - read-only; - }; - - partition@780000 { - label = "0:TZ"; - reg = <0x0780000 0x0280000>; - read-only; - }; - - partition@a00000 { - label = "0:RPM"; - reg = <0x0a00000 0x0280000>; - read-only; - }; - - partition@c80000 { - label = "0:APPSBL"; - reg = <0x0c80000 0x0500000>; - read-only; - }; - - partition@1180000 { - label = "0:APPSBLENV"; - reg = <0x1180000 0x0080000>; - }; - - partition@1200000 { - label = "0:ART"; - reg = <0x1200000 0x0140000>; - read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_ART_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_ART_6: macaddr@6 { - reg = <0x6 0x6>; - }; - - precal_ART_1000: precal@1000 { - reg = <0x1000 0x2f20>; - }; - - precal_ART_5000: precal@5000 { - reg = <0x5000 0x2f20>; - }; - }; - - partition@1340000 { - label = "0:BOOTCONFIG"; - reg = <0x1340000 0x0060000>; - read-only; - }; - - partition@13a0000 { - label = "0:SBL2_1"; - reg = <0x13a0000 0x0140000>; - read-only; - }; - - partition@14e0000 { - label = "0:SBL3_1"; - reg = <0x14e0000 0x0280000>; - read-only; - }; - - partition@1760000 { - label = "0:DDRCONFIG_1"; - reg = <0x1760000 0x0120000>; - read-only; - }; - - partition@1880000 { - label = "0:SSD_1"; - reg = <0x1880000 0x0120000>; - read-only; - }; - - partition@19a0000 { - label = "0:TZ_1"; - reg = <0x19a0000 0x0280000>; - read-only; - }; - - partition@1c20000 { - label = "0:RPM_1"; - reg = <0x1c20000 0x0280000>; - read-only; - }; - - partition@1ea0000 { - label = "0:BOOTCONFIG1"; - reg = <0x1ea0000 0x0060000>; - read-only; - }; - - partition@1f00000 { - label = "0:APPSBL_1"; - reg = <0x1f00000 0x0500000>; - read-only; - }; - - partition@2400000 { - label = "ubi"; - reg = <0x2400000 0x1a000000>; - }; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0x0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0xaa545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - 0x00050 0xcf02cf02 /* LED_CTRL_0 */ - 0x00054 0xc832c832 /* LED_CTRL_1 */ - >; - }; -}; - -&gmac0 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <0>; - - nvmem-cells = <&macaddr_ART_0>; - nvmem-cell-names = "mac-address"; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <1>; - - nvmem-cells = <&macaddr_ART_6>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; - reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&pcie0_pins>; - pinctrl-names = "default"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi0: wifi@1,0 { - compatible = "pci168c,0046"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&precal_ART_1000>; - nvmem-cell-names = "pre-calibration"; - }; - }; -}; - -&pcie1 { - status = "okay"; - reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&pcie1_pins>; - pinctrl-names = "default"; - max-link-speed = <1>; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi1: wifi@1,0 { - compatible = "pci168c,0046"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&precal_ART_5000>; - nvmem-cell-names = "pre-calibration"; - }; - }; -}; diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts deleted file mode 100644 index 7b236af253e..00000000000 --- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts +++ /dev/null @@ -1,432 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "qcom-ipq8065-smb208.dtsi" -#include - -/ { - model = "Arris TR4400 v2"; - compatible = "arris,tr4400-v2", "qcom,ipq8065", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - aliases { - led-boot = &led_status_blue; - led-failsafe = &led_status_red; - led-running = &led_status_blue; - led-upgrade = &led_status_red; - }; - - chosen { - bootargs = "rootfstype=squashfs noinitrd"; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - led_status_red: status_red { - label = "red:status"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - led_status_blue: status_blue { - label = "blue:status"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio6", "gpio54"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio7", "gpio8"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - rgmii2_pins: rgmii2-pins { - tx { - pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32"; - input-disable; - }; - }; - - spi_pins: spi_pins { - cs { - pins = "gpio20"; - drive-strength = <12>; - }; - }; -}; - -&gsbi5 { - qcom,mode = ; - status = "okay"; - - spi@1a280000 { - status = "okay"; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - flash@0 { - compatible = "everspin,mr25h256"; - spi-max-frequency = <40000000>; - reg = <0>; - }; - }; -}; - -&nand { - status = "okay"; - - nand@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - qcom,boot-partitions = <0x0 0x1180000 0x5340000 0x10c0000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "0:SBL1"; - reg = <0x0000000 0x0040000>; - read-only; - }; - partition@40000 { - label = "0:MIBIB"; - reg = <0x0040000 0x0140000>; - read-only; - }; - partition@180000 { - label = "0:SBL2"; - reg = <0x0180000 0x0140000>; - read-only; - }; - partition@2c0000 { - label = "0:SBL3"; - reg = <0x02c0000 0x0280000>; - read-only; - }; - partition@540000 { - label = "0:DDRCONFIG"; - reg = <0x0540000 0x0120000>; - read-only; - }; - partition@660000 { - label = "0:SSD"; - reg = <0x0660000 0x0120000>; - read-only; - }; - partition@780000 { - label = "0:TZ"; - reg = <0x0780000 0x0280000>; - read-only; - }; - partition@a00000 { - label = "0:RPM"; - reg = <0x0a00000 0x0280000>; - read-only; - }; - partition@c80000 { - label = "0:APPSBL"; - reg = <0x0c80000 0x0500000>; - read-only; - }; - partition@1180000 { - label = "0:APPSBLENV"; - reg = <0x1180000 0x0080000>; - }; - partition@1200000 { - label = "0:ART"; - reg = <0x1200000 0x0140000>; - read-only; - - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - precal_ART_1000: precal@1000 { - reg = <0x1000 0x2f20>; - }; - precal_ART_5000: precal@5000 { - reg = <0x5000 0x2f20>; - }; - }; - stock_partition@1340000 { - label = "stock_rootfs"; - reg = <0x1340000 0x4000000>; - }; - partition@5340000 { - label = "0:BOOTCONFIG"; - reg = <0x5340000 0x0060000>; - read-only; - }; - partition@53a0000 { - label = "0:SBL2_1"; - reg = <0x53a0000 0x0140000>; - read-only; - }; - partition@54e0000 { - label = "0:SBL3_1"; - reg = <0x54e0000 0x0280000>; - read-only; - }; - partition@5760000 { - label = "0:DDRCONFIG_1"; - reg = <0x5760000 0x0120000>; - read-only; - }; - partition@5880000 { - label = "0:SSD_1"; - reg = <0x5880000 0x0120000>; - read-only; - }; - partition@59a0000 { - label = "0:TZ_1"; - reg = <0x59a0000 0x0280000>; - read-only; - }; - partition@5c20000 { - label = "0:RPM_1"; - reg = <0x5c20000 0x0280000>; - read-only; - }; - partition@5ea0000 { - label = "0:BOOTCONFIG1"; - reg = <0x5ea0000 0x0060000>; - read-only; - }; - partition@5f00000 { - label = "0:APPSBL_1"; - reg = <0x5f00000 0x0500000>; - read-only; - }; - stock_partition@6400000 { - label = "stock_rootfs_1"; - reg = <0x6400000 0x4000000>; - }; - stock_partition@a400000 { - label = "stock_fw_env"; - reg = <0xa400000 0x0100000>; - }; - stock_partition@a500000 { - label = "stock_config"; - reg = <0xa500000 0x0800000>; - }; - stock_partition@ad00000 { - label = "stock_PKI"; - reg = <0xad00000 0x0200000>; - }; - stock_partition@af00000 { - label = "stock_scfgmgr"; - reg = <0xaf00000 0x0100000>; - }; - - partition@6400000 { - label = "fw_env"; - reg = <0x6400000 0x0100000>; - - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_fw_env_0: macaddr@0 { - reg = <0x00 0x6>; - }; - macaddr_fw_env_6: macaddr@6 { - reg = <0x06 0x6>; - }; - macaddr_fw_env_c: macaddr@c { - reg = <0x0c 0x6>; - }; - macaddr_fw_env_12: macaddr@12 { - reg = <0x12 0x6>; - }; - macaddr_fw_env_18: macaddr@18 { - reg = <0x18 0x6>; - }; - }; - partition@6500000 { - label = "ubi"; - reg = <0x6500000 0x9b00000>; - }; - partition@1340000 { - label = "extra"; - reg = <0x1340000 0x4000000>; - }; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - ethernet-phy@0 { - reg = <0x0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0xaa545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy7: ethernet-phy@7 { - reg = <7>; - }; -}; - -&gmac0 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <0>; - - nvmem-cells = <&macaddr_fw_env_18>; - nvmem-cell-names = "mac-address"; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <1>; - - nvmem-cells = <&macaddr_fw_env_0>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac3 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <3>; - phy-handle = <&phy7>; - - nvmem-cells = <&macaddr_fw_env_6>; - nvmem-cell-names = "mac-address"; -}; - -&adm_dma { - status = "okay"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; - reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&pcie0_pins>; - pinctrl-names = "default"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi0: wifi@1,0 { - compatible = "pci168c,0046"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&precal_ART_1000>, <&macaddr_fw_env_12>; - nvmem-cell-names = "pre-calibration", "mac-address"; - }; - }; -}; - -&pcie1 { - status = "okay"; - reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&pcie1_pins>; - pinctrl-names = "default"; - max-link-speed = <1>; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi1: wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&precal_ART_5000>, <&macaddr_fw_env_c>; - nvmem-cell-names = "pre-calibration", "mac-address"; - }; - }; -}; diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-xr450.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-xr450.dts deleted file mode 100644 index 4353aec7ac0..00000000000 --- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-xr450.dts +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "qcom-ipq8065-nighthawk.dtsi" - -/ { - model = "Netgear Nighthawk XR450"; - compatible = "netgear,xr450", "qcom,ipq8065", "qcom,ipq8064"; - -}; - -&leds { - usb1 { - label = "white:usb1"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - usb2 { - label = "white:usb2"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - }; -}; - -&partitions { - partition@1880000 { - label = "ubi"; - reg = <0x1880000 0xce00000>; - }; - - partition@e680000 { - label = "reserve"; - reg = <0xe680000 0x0780000>; - read-only; - }; -}; - -&wifi0 { - nvmem-cells = <&macaddr_art_c>, <&precal_art_1000>; - nvmem-cell-names = "mac-address", "pre-calibration"; -}; - -&wifi1 { - nvmem-cells = <&macaddr_art_0>, <&precal_art_5000>; - nvmem-cell-names = "mac-address", "pre-calibration"; -}; - -&art { - macaddr_art_c: macaddr@c { - reg = <0xc 0x6>; - }; -}; diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-xr500.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-xr500.dts deleted file mode 100644 index f584735e155..00000000000 --- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-xr500.dts +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "qcom-ipq8065-nighthawk.dtsi" - -/ { - model = "Netgear Nighthawk XR500"; - compatible = "netgear,xr500", "qcom,ipq8065", "qcom,ipq8064"; - -}; - -&leds { - usb1 { - label = "white:usb1"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - usb2 { - label = "white:usb2"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - }; -}; - -&partitions { - partition@1880000 { - label = "ubi"; - reg = <0x1880000 0xce00000>; - }; - - partition@e680000 { - label = "reserve"; - reg = <0xe680000 0x0780000>; - read-only; - }; -}; - -&wifi0 { - nvmem-cells = <&macaddr_art_c>, <&precal_art_1000>; - nvmem-cell-names = "mac-address", "pre-calibration"; -}; - -&wifi1 { - nvmem-cells = <&macaddr_art_0>, <&precal_art_5000>; - nvmem-cell-names = "mac-address", "pre-calibration"; -}; - -&art { - macaddr_art_c: macaddr@c { - reg = <0xc 0x6>; - }; -}; diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi deleted file mode 100644 index a8f43591f90..00000000000 --- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi +++ /dev/null @@ -1,236 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT - -#include "qcom-ipq8064-v2.0-smb208.dtsi" - -/ { - memory { - device_type = "memory"; - linux,usable-memory = <0x41500000 0x1ea00000>; - reg = <0x40000000 0x20000000>; - }; - - cpus { - idle-states { - CPU_SPC: spc { - status = "disabled"; - }; - }; - }; - - chosen { - bootargs-append = " console=ttyMSM0,115200n8 ubi.mtd=ubi ubi.mtd=art"; - }; -}; - -&qcom_pinmux { - mdio0_pins_active: mdio0_pins_active { - mux { - pins = "gpio0", "gpio1"; - function = "mdio"; - drive-strength = <2>; - bias-pull-down; - output-low; - }; - - clk { - pins = "gpio1"; - input-disable; - }; - }; - - phy_active: phy_active { - phy { - pins = "gpio6", "gpio7"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - output-high; - }; - }; - - uart1_pins: uart1_pins { - mux { - pins = "gpio51", "gpio52"; - function = "gsbi1"; - drive-strength = <4>; - bias-disable; - }; - }; -}; - -&gsbi1 { - status = "okay"; - qcom,mode = ; - - serial@12450000 { - status = "okay"; - - pinctrl-0 = <&uart1_pins>; - pinctrl-names = "default"; - }; -}; - -&pcie0 { - status = "okay"; - - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - /delete-property/ perst-gpios; - - bridge@0,0 { - reg = <0x0 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi0: wifi@1,0 { - compatible = "qcom,ath10k"; - status = "okay"; - reg = <0x10000 0 0 0 0>; - }; - }; -}; - -&pcie1 { - status = "okay"; - - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - /delete-property/ perst-gpios; - - bridge@0,0 { - reg = <0x0 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi1: wifi@1,0 { - compatible = "qcom,ath10k"; - status = "okay"; - reg = <0x10000 0 0 0 0>; - }; - }; -}; - -&pcie2 { - status = "okay"; - - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - /delete-property/ perst-gpios; - - bridge@0,0 { - reg = <0x0 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi2: wifi@1,0 { - compatible = "qcom,ath10k"; - status = "okay"; - reg = <0x10000 0 0 0 0>; - }; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&nand { - status = "okay"; - - nand@0 { - compatible = "qcom,nandcs"; - - reg = <0>; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - nand-is-boot-medium; - qcom,boot-partitions = <0x0 0x2140000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "sbl1"; - reg = <0x0 0x40000>; - read-only; - }; - - partition@40000 { - label = "mibib"; - reg = <0x40000 0x140000>; - read-only; - }; - - partition@180000 { - label = "sbl2"; - reg = <0x180000 0x140000>; - read-only; - }; - - partition@2c0000 { - label = "sbl3"; - reg = <0x2c0000 0x280000>; - read-only; - }; - - partition@540000 { - label = "ddrconfig"; - reg = <0x540000 0x120000>; - read-only; - }; - - partition@660000 { - label = "ssd"; - reg = <0x660000 0x120000>; - read-only; - }; - - partition@780000 { - label = "tz"; - reg = <0x780000 0x280000>; - read-only; - }; - - partition@a00000 { - label = "rpm"; - reg = <0xa00000 0x280000>; - read-only; - }; - - partition@1fc0000 { - label = "u-boot"; - reg = <0x1fc0000 0x180000>; - read-only; - }; - - partition@21c0000 { - label = "bootkernel1"; - reg = <0x21c0000 0xa80000>; - }; - - partition@2c40000 { - label = "bootkernel2"; - reg = <0x2c40000 0xa80000>; - }; - - partition@36c0000 { - label = "ubi"; - reg = <0x36c0000 0x46c0000>; - }; - - partition@7d80000 { - label = "art"; - reg = <0x7d80000 0x200000>; - read-only; - }; - }; - }; -}; diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts deleted file mode 100644 index 50c1d37c292..00000000000 --- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts +++ /dev/null @@ -1,329 +0,0 @@ -#include "qcom-ipq8064-v2.0-smb208.dtsi" - -#include -#include - -/ { - model = "Edgecore ECW5410"; - compatible = "edgecore,ecw5410", "qcom,ipq8064"; - - reserved-memory { - nss@40000000 { - reg = <0x40000000 0x1000000>; - no-map; - }; - - smem: smem@41000000 { - reg = <0x41000000 0x200000>; - no-map; - }; - - wifi_dump@44000000 { - reg = <0x44000000 0x600000>; - no-map; - }; - }; - - cpus { - idle-states { - CPU_SPC: spc { - status = "disabled"; - }; - }; - }; - - aliases { - serial1 = &gsbi1_serial; - ethernet0 = &gmac2; - ethernet1 = &gmac3; - - led-boot = &led_power_green; - led-failsafe = &led_power_red; - led-running = &led_power_green; - led-upgrade = &led_power_green; - }; - - chosen { - bootargs-append = " console=ttyMSM0,115200n8 root=/dev/ubiblock0_1"; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - led_power_green: power_green { - label = "green:power"; - gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>; - }; - - wlan2g_green { - label = "green:wlan2g"; - gpios = <&qcom_pinmux 23 GPIO_ACTIVE_LOW>; - }; - - wlan2g_yellow { - label = "yellow:wlan2g"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>; - }; - - wlan5g_green { - label = "green:wlan5g"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; - }; - - led_power_red: power_red { - label = "red:power"; - gpios = <&qcom_pinmux 28 GPIO_ACTIVE_LOW>; - }; - - wlan5g_yellow { - label = "yellow:wlan5g"; - gpios = <&qcom_pinmux 59 GPIO_ACTIVE_LOW>; - }; - }; -}; - - -&qcom_pinmux { - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19"; - function = "gsbi5"; - drive-strength = <10>; - bias-pull-down; - }; - - clk { - pins = "gpio21"; - function = "gsbi5"; - drive-strength = <12>; - bias-pull-down; - }; - - cs { - pins = "gpio20"; - function = "gpio"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio16", "gpio23", "gpio24", "gpio26", - "gpio28", "gpio59"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - button_pins: button_pins { - mux { - pins = "gpio25"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - uart1_pins: uart1_pins { - mux { - pins = "gpio51", "gpio52", "gpio53", "gpio54"; - function = "gsbi1"; - drive-strength = <12>; - bias-none; - }; - }; -}; - -&gsbi1 { - qcom,mode = ; - status = "okay"; - - serial@12450000 { - status = "okay"; - - pinctrl-0 = <&uart1_pins>; - pinctrl-names = "default"; - }; -}; - -&gsbi5 { - qcom,mode = ; - status = "okay"; - - spi4: spi@1a280000 { - status = "okay"; - spi-max-frequency = <50000000>; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - m25p80@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - reg = <0>; - - partitions { - compatible = "qcom,smem-part"; - }; - }; - }; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; - - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - /delete-property/ perst-gpios; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "qcom,ath10k"; - status = "okay"; - reg = <0x00010000 0 0 0 0>; - qcom,ath10k-calibration-variant = "Edgecore-ECW5410-L"; - }; - }; -}; - -&pcie2 { - status = "okay"; - - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - /delete-property/ perst-gpios; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "qcom,ath10k"; - status = "okay"; - reg = <0x00010000 0 0 0 0>; - qcom,ath10k-calibration-variant = "Edgecore-ECW5410-L"; - }; - }; -}; - -&nand { - status = "okay"; - - nand@0 { - compatible = "qcom,nandcs"; - - reg = <0>; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - rootfs1@0 { - label = "rootfs1"; - reg = <0x0000000 0x4000000>; - }; - - rootfs2@4000000 { - label = "rootfs2"; - reg = <0x4000000 0x4000000>; - }; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&gmac2 { - status = "okay"; - - qcom,id = <2>; - mdiobus = <&mdio0>; - - phy-mode = "sgmii"; - phy-handle = <&phy1>; -}; - -&gmac3 { - status = "okay"; - - qcom,id = <3>; - mdiobus = <&mdio0>; - - phy-mode = "sgmii"; - phy-handle = <&phy0>; -}; - -&adm_dma { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8068-mr42.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8068-mr42.dts deleted file mode 100644 index cfbfafb1793..00000000000 --- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8068-mr42.dts +++ /dev/null @@ -1,228 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT - -#include "qcom-ipq8068-cryptid-common.dtsi" - -#include - -/ { - model = "Meraki MR42"; - compatible = "meraki,mr42", "qcom,ipq8064"; - - aliases { - serial1 = &gsbi1_serial; - ethernet0 = &gmac3; - - led-boot = &led_active; - led-failsafe = &led_power; - led-running = &led_active; - led-upgrade = &led_active; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - led_power: power { - label = "orange:power"; - gpios = <&qcom_pinmux 31 GPIO_ACTIVE_HIGH>; - }; - - led_active: active { - label = "white:active"; - gpios = <&qcom_pinmux 32 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&gmac3 { - status = "okay"; - - qcom,id = <3>; - mdiobus = <&mdio0>; - - phy-mode = "sgmii"; - phy-handle = <&phy2>; - - nvmem-cells = <&mac_address>; - nvmem-cell-names = "mac-address"; -}; - -&gsbi2 { - status = "okay"; - qcom,mode = ; -}; - -&gsbi2_i2c { - status = "okay"; - - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - - ina2xx@40 { - compatible = "ina219"; - shunt-resistor = <40000>; - reg = <0x40>; - }; - - eeprom@56 { - compatible = "atmel,24c64"; - pagesize = <32>; - reg = <0x56>; - read-only; - #address-cells = <1>; - #size-cells = <1>; - - mac_address: mac-address@66 { - reg = <0x66 0x6>; - }; - }; -}; - -&gsbi6 { - qcom,mode = ; - status = "okay"; -}; - -&gsbi6_i2c { - status = "okay"; - - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - - tlc591xx@40 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "ti,tlc59108"; - reg = <0x40>; - - red@0 { - label = "red:user"; - reg = <0x0>; - }; - - green@1 { - label = "green:user"; - reg = <0x1>; - }; - - blue@2 { - label = "blue:user"; - reg = <0x2>; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins_active>, <&phy_active>; - pinctrl-names = "default"; - - phy2: ethernet-phy2 { - reg = <2>; - - reset-gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - reset-assert-us = <24000>; - - eee-broken-100tx; - eee-broken-1000t; - }; -}; - -&qcom_pinmux { - i2c0_pins: i2c0_pins { - mux { - pins = "gpio24", "gpio25"; - function = "gsbi2"; - drive-strength = <2>; - bias-pull-up; - input; - }; - }; - - button_pins: button_pins { - mux { - pins = "gpio26"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - i2c1_pins: i2c1_pins { - mux { - pins = "gpio29", "gpio30"; - function = "gsbi6"; - drive-strength = <2>; - bias-pull-up; - input; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio31", "gpio32"; - function = "gpio"; - drive-strength = <12>; - bias-pull-down; - output-low; - }; - }; -}; - -&wifi0 { - nvmem-cells = <&mac_address>; - nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; -}; - -&wifi1 { - nvmem-cells = <&mac_address>; - nvmem-cell-names = "mac-address"; - mac-address-increment = <2>; -}; - -&wifi2 { - nvmem-cells = <&mac_address>; - nvmem-cell-names = "mac-address"; - mac-address-increment = <3>; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8068-mr52.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8068-mr52.dts deleted file mode 100644 index f81e3ef690d..00000000000 --- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8068-mr52.dts +++ /dev/null @@ -1,254 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT - -#include "qcom-ipq8068-cryptid-common.dtsi" - -#include - -/ { - model = "Meraki MR52"; - compatible = "meraki,mr52", "qcom,ipq8064"; - - aliases { - serial1 = &gsbi1_serial; - mdio-gpio0 = &mdio_gpio0; - ethernet0 = &gmac2; - ethernet1 = &gmac3; - - led-boot = &led_active; - led-failsafe = &led_power; - led-running = &led_active; - led-upgrade = &led_active; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - led_power: power { - label = "orange:power"; - gpios = <&qcom_pinmux 19 GPIO_ACTIVE_HIGH>; - }; - - lan2_green { - label = "green:lan2"; - gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; - }; - - lan1_green { - label = "green:lan1"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; - }; - - led_active: active { - label = "white:active"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; - }; - - lan2_orange { - label = "orange:lan2"; - gpios = <&qcom_pinmux 60 GPIO_ACTIVE_HIGH>; - }; - - lan1_orange { - label = "orange:lan1"; - gpios = <&qcom_pinmux 62 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&gmac2 { - status = "okay"; - - qcom,id = <2>; - mdiobus = <&mdio0>; - - phy-mode = "sgmii"; - phy-handle = <&phy0>; - - nvmem-cells = <&mac_address>; - nvmem-cell-names = "mac-address"; -}; - -&gmac3 { - status = "okay"; - - qcom,id = <3>; - mdiobus = <&mdio_gpio0>; - - phy-mode = "sgmii"; - phy-handle = <&phy4>; - - nvmem-cells = <&mac_address>; - nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; -}; - -&gsbi7 { - status = "okay"; - qcom,mode = ; -}; - -&gsbi7_i2c { - status = "okay"; - - pinctrl-0 = <&i2c_pins>; - pinctrl-names = "default"; - - ina2xx@45 { - compatible = "ina219"; - shunt-resistor = <80000>; - reg = <0x45>; - }; - - tlc591xx@49 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "ti,tlc59108"; - reg = <0x49>; - - red@0 { - label = "red:user"; - reg = <0x0>; - }; - - green@1 { - label = "green:user"; - reg = <0x1>; - }; - - blue@2 { - label = "blue:user"; - reg = <0x2>; - }; - }; - - eeprom@52 { - compatible = "atmel,24c64"; - pagesize = <32>; - reg = <0x52>; - read-only; - #address-cells = <1>; - #size-cells = <1>; - - mac_address: mac-address@66 { - reg = <0x66 0x6>; - }; - }; -}; - -&qcom_pinmux { - i2c_pins: i2c_pins { - mux { - pins = "gpio8", "gpio9"; - function = "gsbi7"; - drive-strength = <2>; - bias-pull-up; - input; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio19", "gpio26"; - function = "gpio"; - drive-strength = <12>; - bias-pull-down; - output-low; - }; - }; - - button_pins: button_pins { - mux { - pins = "gpio25"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - input; - }; - }; -}; - -&soc { - mdio_gpio0: mdio { - compatible = "virtual,mdio-gpio"; - #address-cells = <1>; - #size-cells = <0>; - - status = "okay"; - - pinctrl-0 = <&mdio0_pins_active>, <&phy_active>; - pinctrl-names = "default"; - - gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH - &qcom_pinmux 0 GPIO_ACTIVE_HIGH>; - - phy0: ethernet-phy0 { - reg = <0>; - reset-gpios = <&qcom_pinmux 7 GPIO_ACTIVE_LOW>; - reset-assert-us = <24000>; - }; - - phy4: ethernet-phy4 { - reg = <4>; - reset-gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - reset-assert-us = <24000>; - }; - }; -}; - -&wifi0 { - nvmem-cells = <&mac_address>; - nvmem-cell-names = "mac-address"; - mac-address-increment = <4>; -}; - -&wifi1 { - nvmem-cells = <&mac_address>; - nvmem-cell-names = "mac-address"; - mac-address-increment = <3>; -}; - -&wifi2 { - nvmem-cells = <&mac_address>; - nvmem-cell-names = "mac-address"; - mac-address-increment = <2>; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts similarity index 100% rename from target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi similarity index 100% rename from target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ad7200.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ad7200.dts similarity index 100% rename from target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ad7200.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ad7200.dts diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ap148.dts similarity index 100% rename from target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap148.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ap148.dts diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap161.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ap161.dts similarity index 100% rename from target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap161.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ap161.dts diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-asus-onhub.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-asus-onhub.dts similarity index 100% rename from target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-asus-onhub.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-asus-onhub.dts diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-c2600.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-c2600.dts similarity index 100% rename from target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-c2600.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-c2600.dts diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-d7800.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-d7800.dts similarity index 100% rename from target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-d7800.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-d7800.dts diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-db149.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-db149.dts similarity index 100% rename from target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-db149.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-db149.dts diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ea7500-v1.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ea7500-v1.dts similarity index 100% rename from target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ea7500-v1.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ea7500-v1.dts diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts similarity index 100% rename from target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi similarity index 100% rename from target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-g10.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-g10.dts similarity index 100% rename from target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-g10.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-g10.dts diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-onhub.dtsi b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-onhub.dtsi similarity index 100% rename from target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-onhub.dtsi rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-onhub.dtsi diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500.dts similarity index 100% rename from target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500.dts diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts similarity index 100% rename from target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-tplink-onhub.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-tplink-onhub.dts similarity index 100% rename from target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-tplink-onhub.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-tplink-onhub.dts diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts similarity index 100% rename from target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts similarity index 100% rename from target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts similarity index 100% rename from target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts similarity index 100% rename from target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts similarity index 100% rename from target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-ac400i.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-ac400i.dts similarity index 100% rename from target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-ac400i.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-ac400i.dts diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts similarity index 100% rename from target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi similarity index 100% rename from target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-r7800.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-r7800.dts similarity index 100% rename from target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-r7800.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-r7800.dts diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts similarity index 100% rename from target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts similarity index 100% rename from target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-xr450.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-xr450.dts similarity index 100% rename from target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-xr450.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-xr450.dts diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-xr500.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-xr500.dts similarity index 100% rename from target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-xr500.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-xr500.dts diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi similarity index 100% rename from target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts similarity index 100% rename from target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-mr42.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-mr42.dts similarity index 100% rename from target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-mr42.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-mr42.dts diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-mr52.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-mr52.dts similarity index 100% rename from target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-mr52.dts rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-mr52.dts diff --git a/target/linux/ipq806x/patches-5.15/0060-HACK-arch-arm-force-ZRELADDR-on-arch-qcom.patch b/target/linux/ipq806x/patches-5.15/0060-HACK-arch-arm-force-ZRELADDR-on-arch-qcom.patch deleted file mode 100644 index 1860cef8003..00000000000 --- a/target/linux/ipq806x/patches-5.15/0060-HACK-arch-arm-force-ZRELADDR-on-arch-qcom.patch +++ /dev/null @@ -1,62 +0,0 @@ -From fa71139b55e114aa8c3c4823ff8ee7d49ee810d4 Mon Sep 17 00:00:00 2001 -From: Mathieu Olivari -Date: Wed, 29 Apr 2015 15:21:46 -0700 -Subject: [PATCH 60/69] HACK: arch: arm: force ZRELADDR on arch-qcom - -ARCH_QCOM is using the ARCH_MULTIPLATFORM option, as now recommended -on most ARM architectures. This automatically calculate ZRELADDR by -masking PHYS_OFFSET with 0xf8000000. - -However, on IPQ806x, the first ~20MB of RAM is reserved for the hardware -network accelerators, and the bootloader removes this section from the -layout passed from the ATAGS (when used). - -For newer bootloader, when DT is used, this is not a problem, we just -reserve this memory in the device tree. But if the bootloader doesn't -have DT support, then ATAGS have to be used. In this case, the ARM -decompressor will position the kernel in this low mem, which will not be -in the RAM section mapped by the bootloader, which means the kernel will -freeze in the middle of the boot process trying to map the memory. - -As a work around, this patch allows disabling AUTO_ZRELADDR when -ARCH_QCOM is selected. It makes the zImage usage possible on bootloaders -which don't support device-tree, which is the case on certain early -IPQ806x based designs. - -Signed-off-by: Mathieu Olivari ---- - arch/arm/Kconfig | 2 +- - arch/arm/Makefile | 2 ++ - arch/arm/mach-qcom/Makefile.boot | 1 + - 3 files changed, 4 insertions(+), 1 deletion(-) - create mode 100644 arch/arm/mach-qcom/Makefile.boot - ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -317,7 +317,7 @@ config ARCH_MULTIPLATFORM - select ARCH_SELECT_MEMORY_MODEL - select ARM_HAS_SG_CHAIN - select ARM_PATCH_PHYS_VIRT -- select AUTO_ZRELADDR -+ select AUTO_ZRELADDR if !ARCH_QCOM - select TIMER_OF - select COMMON_CLK - select GENERIC_IRQ_MULTI_HANDLER ---- a/arch/arm/Makefile -+++ b/arch/arm/Makefile -@@ -237,9 +237,11 @@ MACHINE := arch/arm/mach-$(word 1,$(mac - else - MACHINE := - endif -+ifeq ($(CONFIG_ARCH_QCOM),) - ifeq ($(CONFIG_ARCH_MULTIPLATFORM),y) - MACHINE := - endif -+endif - - machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y)) - platdirs := $(patsubst %,arch/arm/plat-%/,$(sort $(plat-y))) ---- /dev/null -+++ b/arch/arm/mach-qcom/Makefile.boot -@@ -0,0 +1 @@ -+zreladdr-y+= 0x42208000 diff --git a/target/linux/ipq806x/patches-5.15/0067-generic-Mangle-bootloader-s-kernel-arguments.patch b/target/linux/ipq806x/patches-5.15/0067-generic-Mangle-bootloader-s-kernel-arguments.patch deleted file mode 100644 index df5d4811a88..00000000000 --- a/target/linux/ipq806x/patches-5.15/0067-generic-Mangle-bootloader-s-kernel-arguments.patch +++ /dev/null @@ -1,280 +0,0 @@ -From 71270226b14733a4b1f2cde58ea9265caa50b38d Mon Sep 17 00:00:00 2001 -From: Adrian Panella -Date: Thu, 9 Mar 2017 09:37:17 +0100 -Subject: [PATCH 67/69] generic: Mangle bootloader's kernel arguments - -The command-line arguments provided by the boot loader will be -appended to a new device tree property: bootloader-args. -If there is a property "append-rootblock" in DT under /chosen -and a root= option in bootloaders command line it will be parsed -and added to DT bootargs with the form: XX. -Only command line ATAG will be processed, the rest of the ATAGs -sent by bootloader will be ignored. -This is usefull in dual boot systems, to get the current root partition -without afecting the rest of the system. - -Signed-off-by: Adrian Panella ---- - arch/arm/Kconfig | 11 +++++ - arch/arm/boot/compressed/atags_to_fdt.c | 72 ++++++++++++++++++++++++++++++++- - init/main.c | 16 ++++++++ - 3 files changed, 98 insertions(+), 1 deletion(-) - ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -1727,6 +1727,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN - The command-line arguments provided by the boot loader will be - appended to the the device tree bootargs property. - -+config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE -+ bool "Append rootblock parsing bootloader's kernel arguments" -+ help -+ The command-line arguments provided by the boot loader will be -+ appended to a new device tree property: bootloader-args. -+ If there is a property "append-rootblock" in DT under /chosen -+ and a root= option in bootloaders command line it will be parsed -+ and added to DT bootargs with the form: XX. -+ Only command line ATAG will be processed, the rest of the ATAGs -+ sent by bootloader will be ignored. -+ - endchoice - - config CMDLINE ---- a/arch/arm/boot/compressed/atags_to_fdt.c -+++ b/arch/arm/boot/compressed/atags_to_fdt.c -@@ -5,6 +5,8 @@ - - #if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND) - #define do_extend_cmdline 1 -+#elif defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+#define do_extend_cmdline 1 - #else - #define do_extend_cmdline 0 - #endif -@@ -20,6 +22,7 @@ static int node_offset(void *fdt, const - return offset; - } - -+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE - static int setprop(void *fdt, const char *node_path, const char *property, - void *val_array, int size) - { -@@ -28,6 +31,7 @@ static int setprop(void *fdt, const char - return offset; - return fdt_setprop(fdt, offset, property, val_array, size); - } -+#endif - - static int setprop_string(void *fdt, const char *node_path, - const char *property, const char *string) -@@ -38,6 +42,7 @@ static int setprop_string(void *fdt, con - return fdt_setprop_string(fdt, offset, property, string); - } - -+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE - static int setprop_cell(void *fdt, const char *node_path, - const char *property, uint32_t val) - { -@@ -46,6 +51,7 @@ static int setprop_cell(void *fdt, const - return offset; - return fdt_setprop_cell(fdt, offset, property, val); - } -+#endif - - static const void *getprop(const void *fdt, const char *node_path, - const char *property, int *len) -@@ -58,6 +64,7 @@ static const void *getprop(const void *f - return fdt_getprop(fdt, offset, property, len); - } - -+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE - static uint32_t get_cell_size(const void *fdt) - { - int len; -@@ -68,6 +75,81 @@ static uint32_t get_cell_size(const void - cell_size = fdt32_to_cpu(*size_len); - return cell_size; - } -+#endif -+ -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+/** -+ * taken from arch/x86/boot/string.c -+ * local_strstr - Find the first substring in a %NUL terminated string -+ * @s1: The string to be searched -+ * @s2: The string to search for -+ */ -+static char *local_strstr(const char *s1, const char *s2) -+{ -+ size_t l1, l2; -+ -+ l2 = strlen(s2); -+ if (!l2) -+ return (char *)s1; -+ l1 = strlen(s1); -+ while (l1 >= l2) { -+ l1--; -+ if (!memcmp(s1, s2, l2)) -+ return (char *)s1; -+ s1++; -+ } -+ return NULL; -+} -+ -+static char *append_rootblock(char *dest, const char *str, int len, void *fdt) -+{ -+ char *ptr, *end, *tmp; -+ const char *root="root="; -+ const char *find_rootblock; -+ int i, l; -+ const char *rootblock; -+ -+ find_rootblock = getprop(fdt, "/chosen", "find-rootblock", &l); -+ if (!find_rootblock) -+ find_rootblock = root; -+ -+ //ARM doesn't have __HAVE_ARCH_STRSTR, so it was copied from x86 -+ ptr = local_strstr(str, find_rootblock); -+ -+ if(!ptr) -+ return dest; -+ -+ end = strchr(ptr, ' '); -+ end = end ? (end - 1) : (strchr(ptr, 0) - 1); -+ -+ // Some boards ubi.mtd=XX,ZZZZ, so let's check for '," too. -+ tmp = strchr(ptr, ','); -+ -+ if(tmp) -+ end = end < tmp ? end : tmp - 1; -+ -+ //find partition number (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX | ubi.mtd=XX,ZZZZ ) -+ for( i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++); -+ ptr = end + 1; -+ -+ /* if append-rootblock property is set use it to append to command line */ -+ rootblock = getprop(fdt, "/chosen", "append-rootblock", &l); -+ if(rootblock != NULL) { -+ if(*dest != ' ') { -+ *dest = ' '; -+ dest++; -+ len++; -+ } -+ if (len + l + i <= COMMAND_LINE_SIZE) { -+ memcpy(dest, rootblock, l); -+ dest += l - 1; -+ memcpy(dest, ptr, i); -+ dest += i; -+ } -+ } -+ return dest; -+} -+#endif - - static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline) - { -@@ -88,18 +170,28 @@ static void merge_fdt_bootargs(void *fdt - - /* and append the ATAG_CMDLINE */ - if (fdt_cmdline) { -+ -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+ //save original bootloader args -+ //and append ubi.mtd with root partition number to current cmdline -+ setprop_string(fdt, "/chosen", "bootloader-args", fdt_cmdline); -+ ptr = append_rootblock(ptr, fdt_cmdline, len, fdt); -+ -+#else - len = strlen(fdt_cmdline); - if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) { - *ptr++ = ' '; - memcpy(ptr, fdt_cmdline, len); - ptr += len; - } -+#endif - } - *ptr = '\0'; - - setprop_string(fdt, "/chosen", "bootargs", cmdline); - } - -+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE - static void hex_str(char *out, uint32_t value) - { - uint32_t digit; -@@ -117,6 +209,7 @@ static void hex_str(char *out, uint32_t - } - *out = '\0'; - } -+#endif - - /* - * Convert and fold provided ATAGs into the provided FDT. -@@ -131,9 +224,11 @@ int atags_to_fdt(void *atag_list, void * - struct tag *atag = atag_list; - /* In the case of 64 bits memory size, need to reserve 2 cells for - * address and size for each bank */ -+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE - __be32 mem_reg_property[2 * 2 * NR_BANKS]; -- int memcount = 0; -- int ret, memsize; -+ int memsize, memcount = 0; -+#endif -+ int ret; - - /* make sure we've got an aligned pointer */ - if ((u32)atag_list & 0x3) -@@ -168,7 +263,9 @@ int atags_to_fdt(void *atag_list, void * - else - setprop_string(fdt, "/chosen", "bootargs", - atag->u.cmdline.cmdline); -- } else if (atag->hdr.tag == ATAG_MEM) { -+ } -+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE -+ else if (atag->hdr.tag == ATAG_MEM) { - if (memcount >= sizeof(mem_reg_property)/4) - continue; - if (!atag->u.mem.size) -@@ -212,6 +309,10 @@ int atags_to_fdt(void *atag_list, void * - setprop(fdt, "/memory", "reg", mem_reg_property, - 4 * memcount * memsize); - } -+#else -+ -+ } -+#endif - - return fdt_pack(fdt); - } ---- a/init/main.c -+++ b/init/main.c -@@ -114,6 +114,10 @@ - - #include - -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+#include -+#endif -+ - static int kernel_init(void *); - - extern void init_IRQ(void); -@@ -993,6 +997,18 @@ asmlinkage __visible void __init __no_sa - pr_notice("Kernel command line: %s\n", saved_command_line); - /* parameters may set static keys */ - jump_label_init(); -+ -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+ //Show bootloader's original command line for reference -+ if(of_chosen) { -+ const char *prop = of_get_property(of_chosen, "bootloader-args", NULL); -+ if(prop) -+ pr_notice("Bootloader command line (ignored): %s\n", prop); -+ else -+ pr_notice("Bootloader command line not present\n"); -+ } -+#endif -+ - parse_early_param(); - after_dashes = parse_args("Booting kernel", - static_command_line, __start___param, diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-04-linux-next-clk-qcom-gcc-ipq806x-fix-wrong-naming-for-gcc_pxo_pl.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-04-linux-next-clk-qcom-gcc-ipq806x-fix-wrong-naming-for-gcc_pxo_pl.patch deleted file mode 100644 index f3f3ea30da8..00000000000 --- a/target/linux/ipq806x/patches-5.15/100-v5.18-04-linux-next-clk-qcom-gcc-ipq806x-fix-wrong-naming-for-gcc_pxo_pl.patch +++ /dev/null @@ -1,109 +0,0 @@ -From e95e825333eda345d812b461301dad50021d5487 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 26 Feb 2022 14:52:24 +0100 -Subject: [PATCH 04/14] clk: qcom: gcc-ipq806x: fix wrong naming for - gcc_pxo_pll8_pll0 - -Parent gcc_pxo_pll8_pll0 had the parent definition and parent map -swapped. Fix this naming error. - -Signed-off-by: Ansuel Smith -Reviewed-by: Bjorn Andersson -Reviewed-by: Stephen Boyd -Tested-by: Jonathan McDowell -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220226135235.10051-5-ansuelsmth@gmail.com ---- - drivers/clk/qcom/gcc-ipq806x.c | 20 ++++++++++---------- - 1 file changed, 10 insertions(+), 10 deletions(-) - ---- a/drivers/clk/qcom/gcc-ipq806x.c -+++ b/drivers/clk/qcom/gcc-ipq806x.c -@@ -291,13 +291,13 @@ static const char * const gcc_pxo_pll3[] - "pll3", - }; - --static const struct parent_map gcc_pxo_pll8_pll0[] = { -+static const struct parent_map gcc_pxo_pll8_pll0_map[] = { - { P_PXO, 0 }, - { P_PLL8, 3 }, - { P_PLL0, 2 } - }; - --static const char * const gcc_pxo_pll8_pll0_map[] = { -+static const char * const gcc_pxo_pll8_pll0[] = { - "pxo", - "pll8_vote", - "pll0_vote", -@@ -1993,7 +1993,7 @@ static struct clk_rcg usb30_master_clk_s - }, - .s = { - .src_sel_shift = 0, -- .parent_map = gcc_pxo_pll8_pll0, -+ .parent_map = gcc_pxo_pll8_pll0_map, - }, - .freq_tbl = clk_tbl_usb30_master, - .clkr = { -@@ -2001,7 +2001,7 @@ static struct clk_rcg usb30_master_clk_s - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "usb30_master_ref_src", -- .parent_names = gcc_pxo_pll8_pll0_map, -+ .parent_names = gcc_pxo_pll8_pll0, - .num_parents = 3, - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, -@@ -2063,7 +2063,7 @@ static struct clk_rcg usb30_utmi_clk = { - }, - .s = { - .src_sel_shift = 0, -- .parent_map = gcc_pxo_pll8_pll0, -+ .parent_map = gcc_pxo_pll8_pll0_map, - }, - .freq_tbl = clk_tbl_usb30_utmi, - .clkr = { -@@ -2071,7 +2071,7 @@ static struct clk_rcg usb30_utmi_clk = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "usb30_utmi_clk", -- .parent_names = gcc_pxo_pll8_pll0_map, -+ .parent_names = gcc_pxo_pll8_pll0, - .num_parents = 3, - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, -@@ -2133,7 +2133,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_s - }, - .s = { - .src_sel_shift = 0, -- .parent_map = gcc_pxo_pll8_pll0, -+ .parent_map = gcc_pxo_pll8_pll0_map, - }, - .freq_tbl = clk_tbl_usb, - .clkr = { -@@ -2141,7 +2141,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_s - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "usb_hs1_xcvr_src", -- .parent_names = gcc_pxo_pll8_pll0_map, -+ .parent_names = gcc_pxo_pll8_pll0, - .num_parents = 3, - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, -@@ -2197,7 +2197,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_s - }, - .s = { - .src_sel_shift = 0, -- .parent_map = gcc_pxo_pll8_pll0, -+ .parent_map = gcc_pxo_pll8_pll0_map, - }, - .freq_tbl = clk_tbl_usb, - .clkr = { -@@ -2205,7 +2205,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_s - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "usb_fs1_xcvr_src", -- .parent_names = gcc_pxo_pll8_pll0_map, -+ .parent_names = gcc_pxo_pll8_pll0, - .num_parents = 3, - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-05-linux-next-clk-qcom-gcc-ipq806x-convert-parent_names-to-parent_.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-05-linux-next-clk-qcom-gcc-ipq806x-convert-parent_names-to-parent_.patch deleted file mode 100644 index d99ac9992f3..00000000000 --- a/target/linux/ipq806x/patches-5.15/100-v5.18-05-linux-next-clk-qcom-gcc-ipq806x-convert-parent_names-to-parent_.patch +++ /dev/null @@ -1,921 +0,0 @@ -From cb02866f9a740fb9fb8ff19698a69290da4057e5 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 26 Feb 2022 14:52:25 +0100 -Subject: [PATCH 05/14] clk: qcom: gcc-ipq806x: convert parent_names to - parent_data - -Convert parent_names to parent_data to modernize the driver. -Where possible use parent_hws directly. - -Signed-off-by: Ansuel Smith -Tested-by: Jonathan McDowell -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220226135235.10051-6-ansuelsmth@gmail.com ---- - drivers/clk/qcom/gcc-ipq806x.c | 286 ++++++++++++++++++++------------- - 1 file changed, 173 insertions(+), 113 deletions(-) - ---- a/drivers/clk/qcom/gcc-ipq806x.c -+++ b/drivers/clk/qcom/gcc-ipq806x.c -@@ -25,6 +25,10 @@ - #include "clk-hfpll.h" - #include "reset.h" - -+static const struct clk_parent_data gcc_pxo[] = { -+ { .fw_name = "pxo", .name = "pxo" }, -+}; -+ - static struct clk_pll pll0 = { - .l_reg = 0x30c4, - .m_reg = 0x30c8, -@@ -35,7 +39,7 @@ static struct clk_pll pll0 = { - .status_bit = 16, - .clkr.hw.init = &(struct clk_init_data){ - .name = "pll0", -- .parent_names = (const char *[]){ "pxo" }, -+ .parent_data = gcc_pxo, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -@@ -46,7 +50,9 @@ static struct clk_regmap pll0_vote = { - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "pll0_vote", -- .parent_names = (const char *[]){ "pll0" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &pll0.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_pll_vote_ops, - }, -@@ -62,7 +68,7 @@ static struct clk_pll pll3 = { - .status_bit = 16, - .clkr.hw.init = &(struct clk_init_data){ - .name = "pll3", -- .parent_names = (const char *[]){ "pxo" }, -+ .parent_data = gcc_pxo, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -@@ -89,7 +95,7 @@ static struct clk_pll pll8 = { - .status_bit = 16, - .clkr.hw.init = &(struct clk_init_data){ - .name = "pll8", -- .parent_names = (const char *[]){ "pxo" }, -+ .parent_data = gcc_pxo, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -@@ -100,7 +106,9 @@ static struct clk_regmap pll8_vote = { - .enable_mask = BIT(8), - .hw.init = &(struct clk_init_data){ - .name = "pll8_vote", -- .parent_names = (const char *[]){ "pll8" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &pll8.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_pll_vote_ops, - }, -@@ -123,7 +131,7 @@ static struct hfpll_data hfpll0_data = { - static struct clk_hfpll hfpll0 = { - .d = &hfpll0_data, - .clkr.hw.init = &(struct clk_init_data){ -- .parent_names = (const char *[]){ "pxo" }, -+ .parent_data = gcc_pxo, - .num_parents = 1, - .name = "hfpll0", - .ops = &clk_ops_hfpll, -@@ -149,7 +157,7 @@ static struct hfpll_data hfpll1_data = { - static struct clk_hfpll hfpll1 = { - .d = &hfpll1_data, - .clkr.hw.init = &(struct clk_init_data){ -- .parent_names = (const char *[]){ "pxo" }, -+ .parent_data = gcc_pxo, - .num_parents = 1, - .name = "hfpll1", - .ops = &clk_ops_hfpll, -@@ -175,7 +183,7 @@ static struct hfpll_data hfpll_l2_data = - static struct clk_hfpll hfpll_l2 = { - .d = &hfpll_l2_data, - .clkr.hw.init = &(struct clk_init_data){ -- .parent_names = (const char *[]){ "pxo" }, -+ .parent_data = gcc_pxo, - .num_parents = 1, - .name = "hfpll_l2", - .ops = &clk_ops_hfpll, -@@ -194,7 +202,7 @@ static struct clk_pll pll14 = { - .status_bit = 16, - .clkr.hw.init = &(struct clk_init_data){ - .name = "pll14", -- .parent_names = (const char *[]){ "pxo" }, -+ .parent_data = gcc_pxo, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -@@ -205,7 +213,9 @@ static struct clk_regmap pll14_vote = { - .enable_mask = BIT(14), - .hw.init = &(struct clk_init_data){ - .name = "pll14_vote", -- .parent_names = (const char *[]){ "pll14" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &pll14.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_pll_vote_ops, - }, -@@ -238,7 +248,7 @@ static struct clk_pll pll18 = { - .freq_tbl = pll18_freq_tbl, - .clkr.hw.init = &(struct clk_init_data){ - .name = "pll18", -- .parent_names = (const char *[]){ "pxo" }, -+ .parent_data = gcc_pxo, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -@@ -259,9 +269,9 @@ static const struct parent_map gcc_pxo_p - { P_PLL8, 3 } - }; - --static const char * const gcc_pxo_pll8[] = { -- "pxo", -- "pll8_vote", -+static const struct clk_parent_data gcc_pxo_pll8[] = { -+ { .fw_name = "pxo", .name = "pxo" }, -+ { .hw = &pll8_vote.hw }, - }; - - static const struct parent_map gcc_pxo_pll8_cxo_map[] = { -@@ -270,10 +280,10 @@ static const struct parent_map gcc_pxo_p - { P_CXO, 5 } - }; - --static const char * const gcc_pxo_pll8_cxo[] = { -- "pxo", -- "pll8_vote", -- "cxo", -+static const struct clk_parent_data gcc_pxo_pll8_cxo[] = { -+ { .fw_name = "pxo", .name = "pxo" }, -+ { .hw = &pll8_vote.hw }, -+ { .fw_name = "cxo", .name = "cxo" }, - }; - - static const struct parent_map gcc_pxo_pll3_map[] = { -@@ -286,9 +296,9 @@ static const struct parent_map gcc_pxo_p - { P_PLL3, 6 } - }; - --static const char * const gcc_pxo_pll3[] = { -- "pxo", -- "pll3", -+static const struct clk_parent_data gcc_pxo_pll3[] = { -+ { .fw_name = "pxo", .name = "pxo" }, -+ { .hw = &pll3.clkr.hw }, - }; - - static const struct parent_map gcc_pxo_pll8_pll0_map[] = { -@@ -297,10 +307,10 @@ static const struct parent_map gcc_pxo_p - { P_PLL0, 2 } - }; - --static const char * const gcc_pxo_pll8_pll0[] = { -- "pxo", -- "pll8_vote", -- "pll0_vote", -+static const struct clk_parent_data gcc_pxo_pll8_pll0[] = { -+ { .fw_name = "pxo", .name = "pxo" }, -+ { .hw = &pll8_vote.hw }, -+ { .hw = &pll0_vote.hw }, - }; - - static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = { -@@ -311,12 +321,12 @@ static const struct parent_map gcc_pxo_p - { P_PLL18, 1 } - }; - --static const char * const gcc_pxo_pll8_pll14_pll18_pll0[] = { -- "pxo", -- "pll8_vote", -- "pll0_vote", -- "pll14", -- "pll18", -+static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = { -+ { .fw_name = "pxo", .name = "pxo" }, -+ { .hw = &pll8_vote.hw }, -+ { .hw = &pll0_vote.hw }, -+ { .hw = &pll14.clkr.hw }, -+ { .hw = &pll18.clkr.hw }, - }; - - static struct freq_tbl clk_tbl_gsbi_uart[] = { -@@ -362,7 +372,7 @@ static struct clk_rcg gsbi1_uart_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gsbi1_uart_src", -- .parent_names = gcc_pxo_pll8, -+ .parent_data = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, -@@ -378,8 +388,8 @@ static struct clk_branch gsbi1_uart_clk - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gsbi1_uart_clk", -- .parent_names = (const char *[]){ -- "gsbi1_uart_src", -+ .parent_hws = (const struct clk_hw*[]){ -+ &gsbi1_uart_src.clkr.hw, - }, - .num_parents = 1, - .ops = &clk_branch_ops, -@@ -413,7 +423,7 @@ static struct clk_rcg gsbi2_uart_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gsbi2_uart_src", -- .parent_names = gcc_pxo_pll8, -+ .parent_data = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, -@@ -429,8 +439,8 @@ static struct clk_branch gsbi2_uart_clk - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gsbi2_uart_clk", -- .parent_names = (const char *[]){ -- "gsbi2_uart_src", -+ .parent_hws = (const struct clk_hw*[]){ -+ &gsbi2_uart_src.clkr.hw, - }, - .num_parents = 1, - .ops = &clk_branch_ops, -@@ -464,7 +474,7 @@ static struct clk_rcg gsbi4_uart_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gsbi4_uart_src", -- .parent_names = gcc_pxo_pll8, -+ .parent_data = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, -@@ -480,8 +490,8 @@ static struct clk_branch gsbi4_uart_clk - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gsbi4_uart_clk", -- .parent_names = (const char *[]){ -- "gsbi4_uart_src", -+ .parent_hws = (const struct clk_hw*[]){ -+ &gsbi4_uart_src.clkr.hw, - }, - .num_parents = 1, - .ops = &clk_branch_ops, -@@ -515,7 +525,7 @@ static struct clk_rcg gsbi5_uart_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gsbi5_uart_src", -- .parent_names = gcc_pxo_pll8, -+ .parent_data = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, -@@ -531,8 +541,8 @@ static struct clk_branch gsbi5_uart_clk - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gsbi5_uart_clk", -- .parent_names = (const char *[]){ -- "gsbi5_uart_src", -+ .parent_hws = (const struct clk_hw*[]){ -+ &gsbi5_uart_src.clkr.hw, - }, - .num_parents = 1, - .ops = &clk_branch_ops, -@@ -566,7 +576,7 @@ static struct clk_rcg gsbi6_uart_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gsbi6_uart_src", -- .parent_names = gcc_pxo_pll8, -+ .parent_data = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, -@@ -582,8 +592,8 @@ static struct clk_branch gsbi6_uart_clk - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gsbi6_uart_clk", -- .parent_names = (const char *[]){ -- "gsbi6_uart_src", -+ .parent_hws = (const struct clk_hw*[]){ -+ &gsbi6_uart_src.clkr.hw, - }, - .num_parents = 1, - .ops = &clk_branch_ops, -@@ -617,7 +627,7 @@ static struct clk_rcg gsbi7_uart_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gsbi7_uart_src", -- .parent_names = gcc_pxo_pll8, -+ .parent_data = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, -@@ -633,8 +643,8 @@ static struct clk_branch gsbi7_uart_clk - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gsbi7_uart_clk", -- .parent_names = (const char *[]){ -- "gsbi7_uart_src", -+ .parent_hws = (const struct clk_hw*[]){ -+ &gsbi7_uart_src.clkr.hw, - }, - .num_parents = 1, - .ops = &clk_branch_ops, -@@ -681,7 +691,7 @@ static struct clk_rcg gsbi1_qup_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gsbi1_qup_src", -- .parent_names = gcc_pxo_pll8, -+ .parent_data = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, -@@ -697,7 +707,9 @@ static struct clk_branch gsbi1_qup_clk = - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gsbi1_qup_clk", -- .parent_names = (const char *[]){ "gsbi1_qup_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &gsbi1_qup_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -730,7 +742,7 @@ static struct clk_rcg gsbi2_qup_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gsbi2_qup_src", -- .parent_names = gcc_pxo_pll8, -+ .parent_data = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, -@@ -746,7 +758,9 @@ static struct clk_branch gsbi2_qup_clk = - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gsbi2_qup_clk", -- .parent_names = (const char *[]){ "gsbi2_qup_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &gsbi2_qup_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -779,7 +793,7 @@ static struct clk_rcg gsbi4_qup_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gsbi4_qup_src", -- .parent_names = gcc_pxo_pll8, -+ .parent_data = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, -@@ -795,7 +809,9 @@ static struct clk_branch gsbi4_qup_clk = - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gsbi4_qup_clk", -- .parent_names = (const char *[]){ "gsbi4_qup_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &gsbi4_qup_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -828,7 +844,7 @@ static struct clk_rcg gsbi5_qup_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gsbi5_qup_src", -- .parent_names = gcc_pxo_pll8, -+ .parent_data = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, -@@ -844,7 +860,9 @@ static struct clk_branch gsbi5_qup_clk = - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gsbi5_qup_clk", -- .parent_names = (const char *[]){ "gsbi5_qup_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &gsbi5_qup_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -877,7 +895,7 @@ static struct clk_rcg gsbi6_qup_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gsbi6_qup_src", -- .parent_names = gcc_pxo_pll8, -+ .parent_data = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, -@@ -893,7 +911,9 @@ static struct clk_branch gsbi6_qup_clk = - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gsbi6_qup_clk", -- .parent_names = (const char *[]){ "gsbi6_qup_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &gsbi6_qup_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -926,7 +946,7 @@ static struct clk_rcg gsbi7_qup_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gsbi7_qup_src", -- .parent_names = gcc_pxo_pll8, -+ .parent_data = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, -@@ -942,7 +962,9 @@ static struct clk_branch gsbi7_qup_clk = - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gsbi7_qup_clk", -- .parent_names = (const char *[]){ "gsbi7_qup_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &gsbi7_qup_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -1076,7 +1098,7 @@ static struct clk_rcg gp0_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gp0_src", -- .parent_names = gcc_pxo_pll8_cxo, -+ .parent_data = gcc_pxo_pll8_cxo, - .num_parents = 3, - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, -@@ -1092,7 +1114,9 @@ static struct clk_branch gp0_clk = { - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gp0_clk", -- .parent_names = (const char *[]){ "gp0_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &gp0_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -1125,7 +1149,7 @@ static struct clk_rcg gp1_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gp1_src", -- .parent_names = gcc_pxo_pll8_cxo, -+ .parent_data = gcc_pxo_pll8_cxo, - .num_parents = 3, - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, -@@ -1141,7 +1165,9 @@ static struct clk_branch gp1_clk = { - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gp1_clk", -- .parent_names = (const char *[]){ "gp1_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &gp1_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -1174,7 +1200,7 @@ static struct clk_rcg gp2_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gp2_src", -- .parent_names = gcc_pxo_pll8_cxo, -+ .parent_data = gcc_pxo_pll8_cxo, - .num_parents = 3, - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, -@@ -1190,7 +1216,9 @@ static struct clk_branch gp2_clk = { - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gp2_clk", -- .parent_names = (const char *[]){ "gp2_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &gp2_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -1228,7 +1256,7 @@ static struct clk_rcg prng_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "prng_src", -- .parent_names = gcc_pxo_pll8, -+ .parent_data = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, - }, -@@ -1244,7 +1272,9 @@ static struct clk_branch prng_clk = { - .enable_mask = BIT(10), - .hw.init = &(struct clk_init_data){ - .name = "prng_clk", -- .parent_names = (const char *[]){ "prng_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &prng_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - }, -@@ -1290,7 +1320,7 @@ static struct clk_rcg sdc1_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "sdc1_src", -- .parent_names = gcc_pxo_pll8, -+ .parent_data = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, - }, -@@ -1305,7 +1335,9 @@ static struct clk_branch sdc1_clk = { - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "sdc1_clk", -- .parent_names = (const char *[]){ "sdc1_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &sdc1_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -1338,7 +1370,7 @@ static struct clk_rcg sdc3_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "sdc3_src", -- .parent_names = gcc_pxo_pll8, -+ .parent_data = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, - }, -@@ -1353,7 +1385,9 @@ static struct clk_branch sdc3_clk = { - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "sdc3_clk", -- .parent_names = (const char *[]){ "sdc3_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &sdc3_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -1421,7 +1455,7 @@ static struct clk_rcg tsif_ref_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "tsif_ref_src", -- .parent_names = gcc_pxo_pll8, -+ .parent_data = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, - }, -@@ -1436,7 +1470,9 @@ static struct clk_branch tsif_ref_clk = - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "tsif_ref_clk", -- .parent_names = (const char *[]){ "tsif_ref_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &tsif_ref_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -1583,7 +1619,7 @@ static struct clk_rcg pcie_ref_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "pcie_ref_src", -- .parent_names = gcc_pxo_pll3, -+ .parent_data = gcc_pxo_pll3, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, -@@ -1599,7 +1635,9 @@ static struct clk_branch pcie_ref_src_cl - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "pcie_ref_src_clk", -- .parent_names = (const char *[]){ "pcie_ref_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &pcie_ref_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -1675,7 +1713,7 @@ static struct clk_rcg pcie1_ref_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "pcie1_ref_src", -- .parent_names = gcc_pxo_pll3, -+ .parent_data = gcc_pxo_pll3, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, -@@ -1691,7 +1729,9 @@ static struct clk_branch pcie1_ref_src_c - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "pcie1_ref_src_clk", -- .parent_names = (const char *[]){ "pcie1_ref_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &pcie1_ref_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -1767,7 +1807,7 @@ static struct clk_rcg pcie2_ref_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "pcie2_ref_src", -- .parent_names = gcc_pxo_pll3, -+ .parent_data = gcc_pxo_pll3, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, -@@ -1783,7 +1823,9 @@ static struct clk_branch pcie2_ref_src_c - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "pcie2_ref_src_clk", -- .parent_names = (const char *[]){ "pcie2_ref_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &pcie2_ref_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -1864,7 +1906,7 @@ static struct clk_rcg sata_ref_src = { - .enable_mask = BIT(7), - .hw.init = &(struct clk_init_data){ - .name = "sata_ref_src", -- .parent_names = gcc_pxo_pll3, -+ .parent_data = gcc_pxo_pll3, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, -@@ -1880,7 +1922,9 @@ static struct clk_branch sata_rxoob_clk - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "sata_rxoob_clk", -- .parent_names = (const char *[]){ "sata_ref_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &sata_ref_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -1896,7 +1940,9 @@ static struct clk_branch sata_pmalive_cl - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "sata_pmalive_clk", -- .parent_names = (const char *[]){ "sata_ref_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &sata_ref_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -1912,7 +1958,7 @@ static struct clk_branch sata_phy_ref_cl - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "sata_phy_ref_clk", -- .parent_names = (const char *[]){ "pxo" }, -+ .parent_data = gcc_pxo, - .num_parents = 1, - .ops = &clk_branch_ops, - }, -@@ -2001,7 +2047,7 @@ static struct clk_rcg usb30_master_clk_s - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "usb30_master_ref_src", -- .parent_names = gcc_pxo_pll8_pll0, -+ .parent_data = gcc_pxo_pll8_pll0, - .num_parents = 3, - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, -@@ -2017,7 +2063,9 @@ static struct clk_branch usb30_0_branch_ - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "usb30_0_branch_clk", -- .parent_names = (const char *[]){ "usb30_master_ref_src", }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &usb30_master_clk_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -2033,7 +2081,9 @@ static struct clk_branch usb30_1_branch_ - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "usb30_1_branch_clk", -- .parent_names = (const char *[]){ "usb30_master_ref_src", }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &usb30_master_clk_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -2071,7 +2121,7 @@ static struct clk_rcg usb30_utmi_clk = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "usb30_utmi_clk", -- .parent_names = gcc_pxo_pll8_pll0, -+ .parent_data = gcc_pxo_pll8_pll0, - .num_parents = 3, - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, -@@ -2087,7 +2137,9 @@ static struct clk_branch usb30_0_utmi_cl - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "usb30_0_utmi_clk_ctl", -- .parent_names = (const char *[]){ "usb30_utmi_clk", }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &usb30_utmi_clk.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -2103,7 +2155,9 @@ static struct clk_branch usb30_1_utmi_cl - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "usb30_1_utmi_clk_ctl", -- .parent_names = (const char *[]){ "usb30_utmi_clk", }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &usb30_utmi_clk.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -2141,7 +2195,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_s - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "usb_hs1_xcvr_src", -- .parent_names = gcc_pxo_pll8_pll0, -+ .parent_data = gcc_pxo_pll8_pll0, - .num_parents = 3, - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, -@@ -2157,7 +2211,9 @@ static struct clk_branch usb_hs1_xcvr_cl - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "usb_hs1_xcvr_clk", -- .parent_names = (const char *[]){ "usb_hs1_xcvr_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &usb_hs1_xcvr_clk_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -2205,7 +2261,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_s - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "usb_fs1_xcvr_src", -- .parent_names = gcc_pxo_pll8_pll0, -+ .parent_data = gcc_pxo_pll8_pll0, - .num_parents = 3, - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, -@@ -2221,7 +2277,9 @@ static struct clk_branch usb_fs1_xcvr_cl - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "usb_fs1_xcvr_clk", -- .parent_names = (const char *[]){ "usb_fs1_xcvr_src", }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &usb_fs1_xcvr_clk_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -2237,7 +2295,9 @@ static struct clk_branch usb_fs1_sys_clk - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "usb_fs1_sys_clk", -- .parent_names = (const char *[]){ "usb_fs1_xcvr_src", }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &usb_fs1_xcvr_clk_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -2337,7 +2397,7 @@ static struct clk_dyn_rcg gmac_core1_src - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gmac_core1_src", -- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, -+ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, - .ops = &clk_dyn_rcg_ops, - }, -@@ -2354,8 +2414,8 @@ static struct clk_branch gmac_core1_clk - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "gmac_core1_clk", -- .parent_names = (const char *[]){ -- "gmac_core1_src", -+ .parent_hws = (const struct clk_hw*[]){ -+ &gmac_core1_src.clkr.hw, - }, - .num_parents = 1, - .ops = &clk_branch_ops, -@@ -2409,7 +2469,7 @@ static struct clk_dyn_rcg gmac_core2_src - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gmac_core2_src", -- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, -+ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, - .ops = &clk_dyn_rcg_ops, - }, -@@ -2426,8 +2486,8 @@ static struct clk_branch gmac_core2_clk - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "gmac_core2_clk", -- .parent_names = (const char *[]){ -- "gmac_core2_src", -+ .parent_hws = (const struct clk_hw*[]){ -+ &gmac_core2_src.clkr.hw, - }, - .num_parents = 1, - .ops = &clk_branch_ops, -@@ -2481,7 +2541,7 @@ static struct clk_dyn_rcg gmac_core3_src - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gmac_core3_src", -- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, -+ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, - .ops = &clk_dyn_rcg_ops, - }, -@@ -2498,8 +2558,8 @@ static struct clk_branch gmac_core3_clk - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "gmac_core3_clk", -- .parent_names = (const char *[]){ -- "gmac_core3_src", -+ .parent_hws = (const struct clk_hw*[]){ -+ &gmac_core3_src.clkr.hw, - }, - .num_parents = 1, - .ops = &clk_branch_ops, -@@ -2553,7 +2613,7 @@ static struct clk_dyn_rcg gmac_core4_src - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gmac_core4_src", -- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, -+ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, - .ops = &clk_dyn_rcg_ops, - }, -@@ -2570,8 +2630,8 @@ static struct clk_branch gmac_core4_clk - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "gmac_core4_clk", -- .parent_names = (const char *[]){ -- "gmac_core4_src", -+ .parent_hws = (const struct clk_hw*[]){ -+ &gmac_core4_src.clkr.hw, - }, - .num_parents = 1, - .ops = &clk_branch_ops, -@@ -2613,7 +2673,7 @@ static struct clk_dyn_rcg nss_tcm_src = - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "nss_tcm_src", -- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, -+ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, - .ops = &clk_dyn_rcg_ops, - }, -@@ -2628,8 +2688,8 @@ static struct clk_branch nss_tcm_clk = { - .enable_mask = BIT(6) | BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "nss_tcm_clk", -- .parent_names = (const char *[]){ -- "nss_tcm_src", -+ .parent_hws = (const struct clk_hw*[]){ -+ &nss_tcm_src.clkr.hw, - }, - .num_parents = 1, - .ops = &clk_branch_ops, -@@ -2691,7 +2751,7 @@ static struct clk_dyn_rcg ubi32_core1_sr - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "ubi32_core1_src_clk", -- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, -+ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, - .ops = &clk_dyn_rcg_ops, - .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, -@@ -2744,7 +2804,7 @@ static struct clk_dyn_rcg ubi32_core2_sr - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "ubi32_core2_src_clk", -- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, -+ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, - .ops = &clk_dyn_rcg_ops, - .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-06-linux-next-clk-qcom-gcc-ipq806x-use-ARRAY_SIZE-for-num_parents.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-06-linux-next-clk-qcom-gcc-ipq806x-use-ARRAY_SIZE-for-num_parents.patch deleted file mode 100644 index 6e6cec7db5c..00000000000 --- a/target/linux/ipq806x/patches-5.15/100-v5.18-06-linux-next-clk-qcom-gcc-ipq806x-use-ARRAY_SIZE-for-num_parents.patch +++ /dev/null @@ -1,325 +0,0 @@ -From a6aedd6532131bc81d47bbf63385dfcf2a0e9faa Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 26 Feb 2022 14:52:26 +0100 -Subject: [PATCH 06/14] clk: qcom: gcc-ipq806x: use ARRAY_SIZE for num_parents - -Use ARRAY_SIZE for num_parents instead of hardcoding the value. - -Signed-off-by: Ansuel Smith -Reviewed-by: Bjorn Andersson -Reviewed-by: Stephen Boyd -Tested-by: Jonathan McDowell -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220226135235.10051-7-ansuelsmth@gmail.com ---- - drivers/clk/qcom/gcc-ipq806x.c | 68 +++++++++++++++++----------------- - 1 file changed, 34 insertions(+), 34 deletions(-) - ---- a/drivers/clk/qcom/gcc-ipq806x.c -+++ b/drivers/clk/qcom/gcc-ipq806x.c -@@ -373,7 +373,7 @@ static struct clk_rcg gsbi1_uart_src = { - .hw.init = &(struct clk_init_data){ - .name = "gsbi1_uart_src", - .parent_data = gcc_pxo_pll8, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, - }, -@@ -424,7 +424,7 @@ static struct clk_rcg gsbi2_uart_src = { - .hw.init = &(struct clk_init_data){ - .name = "gsbi2_uart_src", - .parent_data = gcc_pxo_pll8, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, - }, -@@ -475,7 +475,7 @@ static struct clk_rcg gsbi4_uart_src = { - .hw.init = &(struct clk_init_data){ - .name = "gsbi4_uart_src", - .parent_data = gcc_pxo_pll8, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, - }, -@@ -526,7 +526,7 @@ static struct clk_rcg gsbi5_uart_src = { - .hw.init = &(struct clk_init_data){ - .name = "gsbi5_uart_src", - .parent_data = gcc_pxo_pll8, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, - }, -@@ -577,7 +577,7 @@ static struct clk_rcg gsbi6_uart_src = { - .hw.init = &(struct clk_init_data){ - .name = "gsbi6_uart_src", - .parent_data = gcc_pxo_pll8, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, - }, -@@ -628,7 +628,7 @@ static struct clk_rcg gsbi7_uart_src = { - .hw.init = &(struct clk_init_data){ - .name = "gsbi7_uart_src", - .parent_data = gcc_pxo_pll8, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, - }, -@@ -692,7 +692,7 @@ static struct clk_rcg gsbi1_qup_src = { - .hw.init = &(struct clk_init_data){ - .name = "gsbi1_qup_src", - .parent_data = gcc_pxo_pll8, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, - }, -@@ -743,7 +743,7 @@ static struct clk_rcg gsbi2_qup_src = { - .hw.init = &(struct clk_init_data){ - .name = "gsbi2_qup_src", - .parent_data = gcc_pxo_pll8, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, - }, -@@ -794,7 +794,7 @@ static struct clk_rcg gsbi4_qup_src = { - .hw.init = &(struct clk_init_data){ - .name = "gsbi4_qup_src", - .parent_data = gcc_pxo_pll8, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, - }, -@@ -845,7 +845,7 @@ static struct clk_rcg gsbi5_qup_src = { - .hw.init = &(struct clk_init_data){ - .name = "gsbi5_qup_src", - .parent_data = gcc_pxo_pll8, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, - }, -@@ -896,7 +896,7 @@ static struct clk_rcg gsbi6_qup_src = { - .hw.init = &(struct clk_init_data){ - .name = "gsbi6_qup_src", - .parent_data = gcc_pxo_pll8, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, - }, -@@ -947,7 +947,7 @@ static struct clk_rcg gsbi7_qup_src = { - .hw.init = &(struct clk_init_data){ - .name = "gsbi7_qup_src", - .parent_data = gcc_pxo_pll8, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, - }, -@@ -1099,7 +1099,7 @@ static struct clk_rcg gp0_src = { - .hw.init = &(struct clk_init_data){ - .name = "gp0_src", - .parent_data = gcc_pxo_pll8_cxo, -- .num_parents = 3, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, - }, -@@ -1150,7 +1150,7 @@ static struct clk_rcg gp1_src = { - .hw.init = &(struct clk_init_data){ - .name = "gp1_src", - .parent_data = gcc_pxo_pll8_cxo, -- .num_parents = 3, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, - }, -@@ -1201,7 +1201,7 @@ static struct clk_rcg gp2_src = { - .hw.init = &(struct clk_init_data){ - .name = "gp2_src", - .parent_data = gcc_pxo_pll8_cxo, -- .num_parents = 3, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, - }, -@@ -1257,7 +1257,7 @@ static struct clk_rcg prng_src = { - .hw.init = &(struct clk_init_data){ - .name = "prng_src", - .parent_data = gcc_pxo_pll8, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, - }, - }, -@@ -1321,7 +1321,7 @@ static struct clk_rcg sdc1_src = { - .hw.init = &(struct clk_init_data){ - .name = "sdc1_src", - .parent_data = gcc_pxo_pll8, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, - }, - } -@@ -1371,7 +1371,7 @@ static struct clk_rcg sdc3_src = { - .hw.init = &(struct clk_init_data){ - .name = "sdc3_src", - .parent_data = gcc_pxo_pll8, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, - }, - } -@@ -1456,7 +1456,7 @@ static struct clk_rcg tsif_ref_src = { - .hw.init = &(struct clk_init_data){ - .name = "tsif_ref_src", - .parent_data = gcc_pxo_pll8, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, - }, - } -@@ -1620,7 +1620,7 @@ static struct clk_rcg pcie_ref_src = { - .hw.init = &(struct clk_init_data){ - .name = "pcie_ref_src", - .parent_data = gcc_pxo_pll3, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll3), - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, - }, -@@ -1714,7 +1714,7 @@ static struct clk_rcg pcie1_ref_src = { - .hw.init = &(struct clk_init_data){ - .name = "pcie1_ref_src", - .parent_data = gcc_pxo_pll3, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll3), - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, - }, -@@ -1808,7 +1808,7 @@ static struct clk_rcg pcie2_ref_src = { - .hw.init = &(struct clk_init_data){ - .name = "pcie2_ref_src", - .parent_data = gcc_pxo_pll3, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll3), - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, - }, -@@ -1907,7 +1907,7 @@ static struct clk_rcg sata_ref_src = { - .hw.init = &(struct clk_init_data){ - .name = "sata_ref_src", - .parent_data = gcc_pxo_pll3, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll3), - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, - }, -@@ -2048,7 +2048,7 @@ static struct clk_rcg usb30_master_clk_s - .hw.init = &(struct clk_init_data){ - .name = "usb30_master_ref_src", - .parent_data = gcc_pxo_pll8_pll0, -- .num_parents = 3, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, - }, -@@ -2122,7 +2122,7 @@ static struct clk_rcg usb30_utmi_clk = { - .hw.init = &(struct clk_init_data){ - .name = "usb30_utmi_clk", - .parent_data = gcc_pxo_pll8_pll0, -- .num_parents = 3, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, - }, -@@ -2196,7 +2196,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_s - .hw.init = &(struct clk_init_data){ - .name = "usb_hs1_xcvr_src", - .parent_data = gcc_pxo_pll8_pll0, -- .num_parents = 3, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, - }, -@@ -2262,7 +2262,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_s - .hw.init = &(struct clk_init_data){ - .name = "usb_fs1_xcvr_src", - .parent_data = gcc_pxo_pll8_pll0, -- .num_parents = 3, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, - }, -@@ -2398,7 +2398,7 @@ static struct clk_dyn_rcg gmac_core1_src - .hw.init = &(struct clk_init_data){ - .name = "gmac_core1_src", - .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, -- .num_parents = 5, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), - .ops = &clk_dyn_rcg_ops, - }, - }, -@@ -2470,7 +2470,7 @@ static struct clk_dyn_rcg gmac_core2_src - .hw.init = &(struct clk_init_data){ - .name = "gmac_core2_src", - .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, -- .num_parents = 5, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), - .ops = &clk_dyn_rcg_ops, - }, - }, -@@ -2542,7 +2542,7 @@ static struct clk_dyn_rcg gmac_core3_src - .hw.init = &(struct clk_init_data){ - .name = "gmac_core3_src", - .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, -- .num_parents = 5, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), - .ops = &clk_dyn_rcg_ops, - }, - }, -@@ -2614,7 +2614,7 @@ static struct clk_dyn_rcg gmac_core4_src - .hw.init = &(struct clk_init_data){ - .name = "gmac_core4_src", - .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, -- .num_parents = 5, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), - .ops = &clk_dyn_rcg_ops, - }, - }, -@@ -2674,7 +2674,7 @@ static struct clk_dyn_rcg nss_tcm_src = - .hw.init = &(struct clk_init_data){ - .name = "nss_tcm_src", - .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, -- .num_parents = 5, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), - .ops = &clk_dyn_rcg_ops, - }, - }, -@@ -2752,7 +2752,7 @@ static struct clk_dyn_rcg ubi32_core1_sr - .hw.init = &(struct clk_init_data){ - .name = "ubi32_core1_src_clk", - .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, -- .num_parents = 5, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), - .ops = &clk_dyn_rcg_ops, - .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, - }, -@@ -2805,7 +2805,7 @@ static struct clk_dyn_rcg ubi32_core2_sr - .hw.init = &(struct clk_init_data){ - .name = "ubi32_core2_src_clk", - .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, -- .num_parents = 5, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), - .ops = &clk_dyn_rcg_ops, - .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, - }, diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-07-linux-next-clk-qcom-gcc-ipq806x-add-additional-freq-nss-cores.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-07-linux-next-clk-qcom-gcc-ipq806x-add-additional-freq-nss-cores.patch deleted file mode 100644 index b0f09ec34dc..00000000000 --- a/target/linux/ipq806x/patches-5.15/100-v5.18-07-linux-next-clk-qcom-gcc-ipq806x-add-additional-freq-nss-cores.patch +++ /dev/null @@ -1,88 +0,0 @@ -From 512ea2edfe15ffa2cd839b3a31d768145f2edc20 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 26 Feb 2022 14:52:27 +0100 -Subject: [PATCH 07/14] clk: qcom: gcc-ipq806x: add additional freq nss cores - -Ipq8065 SoC (an evolution of ipq8064 SoC) contains nss cores that can be -clocked to 800MHz. Add these missing freq to the gcc driver. -Set the freq_tbl for the ubi32_cores to the correct values based on the -machine compatible. - -Signed-off-by: Ansuel Smith -Reviewed-by: Stephen Boyd -Tested-by: Jonathan McDowell -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220226135235.10051-8-ansuelsmth@gmail.com ---- - drivers/clk/qcom/gcc-ipq806x.c | 24 +++++++++++++++++++++--- - 1 file changed, 21 insertions(+), 3 deletions(-) - ---- a/drivers/clk/qcom/gcc-ipq806x.c -+++ b/drivers/clk/qcom/gcc-ipq806x.c -@@ -232,7 +232,9 @@ static struct clk_regmap pll14_vote = { - - static struct pll_freq_tbl pll18_freq_tbl[] = { - NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625), -+ NSS_PLL_RATE(600000000, 48, 0, 1, 0x01495625), - NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625), -+ NSS_PLL_RATE(800000000, 64, 0, 1, 0x01495625), - }; - - static struct clk_pll pll18 = { -@@ -2698,7 +2700,7 @@ static struct clk_branch nss_tcm_clk = { - }, - }; - --static const struct freq_tbl clk_tbl_nss[] = { -+static const struct freq_tbl clk_tbl_nss_ipq8064[] = { - { 110000000, P_PLL18, 1, 1, 5 }, - { 275000000, P_PLL18, 2, 0, 0 }, - { 550000000, P_PLL18, 1, 0, 0 }, -@@ -2706,6 +2708,14 @@ static const struct freq_tbl clk_tbl_nss - { } - }; - -+static const struct freq_tbl clk_tbl_nss_ipq8065[] = { -+ { 110000000, P_PLL18, 1, 1, 5 }, -+ { 275000000, P_PLL18, 2, 0, 0 }, -+ { 600000000, P_PLL18, 1, 0, 0 }, -+ { 800000000, P_PLL18, 1, 0, 0 }, -+ { } -+}; -+ - static struct clk_dyn_rcg ubi32_core1_src_clk = { - .ns_reg[0] = 0x3d2c, - .ns_reg[1] = 0x3d30, -@@ -2745,7 +2755,7 @@ static struct clk_dyn_rcg ubi32_core1_sr - .pre_div_width = 2, - }, - .mux_sel_bit = 0, -- .freq_tbl = clk_tbl_nss, -+ /* nss freq table is selected based on the SoC compatible */ - .clkr = { - .enable_reg = 0x3d20, - .enable_mask = BIT(1), -@@ -2798,7 +2808,7 @@ static struct clk_dyn_rcg ubi32_core2_sr - .pre_div_width = 2, - }, - .mux_sel_bit = 0, -- .freq_tbl = clk_tbl_nss, -+ /* nss freq table is selected based on the SoC compatible */ - .clkr = { - .enable_reg = 0x3d40, - .enable_mask = BIT(1), -@@ -3131,6 +3141,14 @@ static int gcc_ipq806x_probe(struct plat - if (ret) - return ret; - -+ if (of_machine_is_compatible("qcom,ipq8065")) { -+ ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8065; -+ ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8065; -+ } else { -+ ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8064; -+ ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8064; -+ } -+ - ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc); - if (ret) - return ret; diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-08-linux-next-clk-qcom-gcc-ipq806x-add-unusued-flag-for-critical-c.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-08-linux-next-clk-qcom-gcc-ipq806x-add-unusued-flag-for-critical-c.patch deleted file mode 100644 index 3d55cb421a1..00000000000 --- a/target/linux/ipq806x/patches-5.15/100-v5.18-08-linux-next-clk-qcom-gcc-ipq806x-add-unusued-flag-for-critical-c.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 28aa450d38e521de45be951df052d2c49a17fae2 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 26 Feb 2022 14:52:28 +0100 -Subject: [PATCH 08/14] clk: qcom: gcc-ipq806x: add unusued flag for critical - clock - -Some clocks are used by other devices present on the SoC. For example -the gsbi4_h_clk is used by RPM and is if disabled cause the RPM to -reject any regulator change command. These clock should never be -disabled. - -Signed-off-by: Ansuel Smith -Tested-by: Jonathan McDowell -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220226135235.10051-9-ansuelsmth@gmail.com ---- - drivers/clk/qcom/gcc-ipq806x.c | 9 +++++---- - 1 file changed, 5 insertions(+), 4 deletions(-) - ---- a/drivers/clk/qcom/gcc-ipq806x.c -+++ b/drivers/clk/qcom/gcc-ipq806x.c -@@ -798,7 +798,7 @@ static struct clk_rcg gsbi4_qup_src = { - .parent_data = gcc_pxo_pll8, - .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, -- .flags = CLK_SET_PARENT_GATE, -+ .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED, - }, - }, - }; -@@ -816,7 +816,7 @@ static struct clk_branch gsbi4_qup_clk = - }, - .num_parents = 1, - .ops = &clk_branch_ops, -- .flags = CLK_SET_RATE_PARENT, -+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, - }, - }, - }; -@@ -900,7 +900,7 @@ static struct clk_rcg gsbi6_qup_src = { - .parent_data = gcc_pxo_pll8, - .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, -- .flags = CLK_SET_PARENT_GATE, -+ .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED, - }, - }, - }; -@@ -969,7 +969,7 @@ static struct clk_branch gsbi7_qup_clk = - }, - .num_parents = 1, - .ops = &clk_branch_ops, -- .flags = CLK_SET_RATE_PARENT, -+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, - }, - }, - }; -@@ -1015,6 +1015,7 @@ static struct clk_branch gsbi4_h_clk = { - .hw.init = &(struct clk_init_data){ - .name = "gsbi4_h_clk", - .ops = &clk_branch_ops, -+ .flags = CLK_IGNORE_UNUSED, - }, - }, - }; diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-09-linux-next-clk-qcom-clk-rcg-add-clk_rcg_floor_ops-ops.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-09-linux-next-clk-qcom-clk-rcg-add-clk_rcg_floor_ops-ops.patch deleted file mode 100644 index 22bd040d1bf..00000000000 --- a/target/linux/ipq806x/patches-5.15/100-v5.18-09-linux-next-clk-qcom-clk-rcg-add-clk_rcg_floor_ops-ops.patch +++ /dev/null @@ -1,69 +0,0 @@ -From 33958ad3fc02aeb06a4634e59689a9559d968e1f Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 26 Feb 2022 14:52:29 +0100 -Subject: [PATCH 09/14] clk: qcom: clk-rcg: add clk_rcg_floor_ops ops - -Add clk_rcg_floor_ops for clock that can't provide a stable freq and -require to use a floor freq to provide the requested frequency. - -Signed-off-by: Ansuel Smith -Reviewed-by: Bjorn Andersson -Reviewed-by: Stephen Boyd -Tested-by: Jonathan McDowell -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220226135235.10051-10-ansuelsmth@gmail.com ---- - drivers/clk/qcom/clk-rcg.c | 24 ++++++++++++++++++++++++ - drivers/clk/qcom/clk-rcg.h | 1 + - 2 files changed, 25 insertions(+) - ---- a/drivers/clk/qcom/clk-rcg.c -+++ b/drivers/clk/qcom/clk-rcg.c -@@ -526,6 +526,19 @@ static int clk_rcg_set_rate(struct clk_h - return __clk_rcg_set_rate(rcg, f); - } - -+static int clk_rcg_set_floor_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long parent_rate) -+{ -+ struct clk_rcg *rcg = to_clk_rcg(hw); -+ const struct freq_tbl *f; -+ -+ f = qcom_find_freq_floor(rcg->freq_tbl, rate); -+ if (!f) -+ return -EINVAL; -+ -+ return __clk_rcg_set_rate(rcg, f); -+} -+ - static int clk_rcg_bypass_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) - { -@@ -816,6 +829,17 @@ const struct clk_ops clk_rcg_ops = { - }; - EXPORT_SYMBOL_GPL(clk_rcg_ops); - -+const struct clk_ops clk_rcg_floor_ops = { -+ .enable = clk_enable_regmap, -+ .disable = clk_disable_regmap, -+ .get_parent = clk_rcg_get_parent, -+ .set_parent = clk_rcg_set_parent, -+ .recalc_rate = clk_rcg_recalc_rate, -+ .determine_rate = clk_rcg_determine_rate, -+ .set_rate = clk_rcg_set_floor_rate, -+}; -+EXPORT_SYMBOL_GPL(clk_rcg_floor_ops); -+ - const struct clk_ops clk_rcg_bypass_ops = { - .enable = clk_enable_regmap, - .disable = clk_disable_regmap, ---- a/drivers/clk/qcom/clk-rcg.h -+++ b/drivers/clk/qcom/clk-rcg.h -@@ -86,6 +86,7 @@ struct clk_rcg { - }; - - extern const struct clk_ops clk_rcg_ops; -+extern const struct clk_ops clk_rcg_floor_ops; - extern const struct clk_ops clk_rcg_bypass_ops; - extern const struct clk_ops clk_rcg_bypass2_ops; - extern const struct clk_ops clk_rcg_pixel_ops; diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-10-linux-next-clk-qcom-gcc-ipq806x-add-additional-freq-for-sdc-tab.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-10-linux-next-clk-qcom-gcc-ipq806x-add-additional-freq-for-sdc-tab.patch deleted file mode 100644 index 3bb5e57c87a..00000000000 --- a/target/linux/ipq806x/patches-5.15/100-v5.18-10-linux-next-clk-qcom-gcc-ipq806x-add-additional-freq-for-sdc-tab.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 7e726f34c782b2ca28a29ca9870e34e4319d65bc Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 26 Feb 2022 14:52:30 +0100 -Subject: [PATCH 10/14] clk: qcom: gcc-ipq806x: add additional freq for sdc - table - -Add additional freq supported for the sdc table. The ops are changed to -the floor_ops to handle a freq request of 52kHz where we need to provide -a freq of 51.2kHz instead for stability reason. - -Signed-off-by: Ansuel Smith -Reviewed-by: Stephen Boyd -Tested-by: Jonathan McDowell -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220226135235.10051-11-ansuelsmth@gmail.com ---- - drivers/clk/qcom/gcc-ipq806x.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - ---- a/drivers/clk/qcom/gcc-ipq806x.c -+++ b/drivers/clk/qcom/gcc-ipq806x.c -@@ -1292,6 +1292,7 @@ static const struct freq_tbl clk_tbl_sdc - { 20210000, P_PLL8, 1, 1, 19 }, - { 24000000, P_PLL8, 4, 1, 4 }, - { 48000000, P_PLL8, 4, 1, 2 }, -+ { 51200000, P_PLL8, 1, 2, 15 }, - { 64000000, P_PLL8, 3, 1, 2 }, - { 96000000, P_PLL8, 4, 0, 0 }, - { 192000000, P_PLL8, 2, 0, 0 }, -@@ -1325,7 +1326,7 @@ static struct clk_rcg sdc1_src = { - .name = "sdc1_src", - .parent_data = gcc_pxo_pll8, - .num_parents = ARRAY_SIZE(gcc_pxo_pll8), -- .ops = &clk_rcg_ops, -+ .ops = &clk_rcg_floor_ops, - }, - } - }; diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-11-linux-next-dt-bindings-clock-add-ipq8064-ce5-clk-define.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-11-linux-next-dt-bindings-clock-add-ipq8064-ce5-clk-define.patch deleted file mode 100644 index 858c6f78a52..00000000000 --- a/target/linux/ipq806x/patches-5.15/100-v5.18-11-linux-next-dt-bindings-clock-add-ipq8064-ce5-clk-define.patch +++ /dev/null @@ -1,39 +0,0 @@ -From b565d66403e3df303a058c0d8d00d0fc6aeb2ddc Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 26 Feb 2022 14:52:31 +0100 -Subject: [PATCH 11/14] dt-bindings: clock: add ipq8064 ce5 clk define - -Add ipq8064 ce5 clk define needed for CryptoEngine in gcc driver. -Define CE5_SRC is not used so it's OK to change and we align it to -the QSDK naming. - -Signed-off-by: Ansuel Smith -Acked-by: Rob Herring -Reviewed-by: Stephen Boyd -Tested-by: Jonathan McDowell -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220226135235.10051-12-ansuelsmth@gmail.com ---- - include/dt-bindings/clock/qcom,gcc-ipq806x.h | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - ---- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h -+++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h -@@ -240,7 +240,7 @@ - #define PLL14 232 - #define PLL14_VOTE 233 - #define PLL18 234 --#define CE5_SRC 235 -+#define CE5_A_CLK 235 - #define CE5_H_CLK 236 - #define CE5_CORE_CLK 237 - #define CE3_SLEEP_CLK 238 -@@ -283,5 +283,8 @@ - #define EBI2_AON_CLK 281 - #define NSSTCM_CLK_SRC 282 - #define NSSTCM_CLK 283 -+#define CE5_A_CLK_SRC 285 -+#define CE5_H_CLK_SRC 286 -+#define CE5_CORE_CLK_SRC 287 - - #endif diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-12-linux-next-clk-qcom-gcc-ipq806x-add-CryptoEngine-clocks.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-12-linux-next-clk-qcom-gcc-ipq806x-add-CryptoEngine-clocks.patch deleted file mode 100644 index 3ded707bf0c..00000000000 --- a/target/linux/ipq806x/patches-5.15/100-v5.18-12-linux-next-clk-qcom-gcc-ipq806x-add-CryptoEngine-clocks.patch +++ /dev/null @@ -1,304 +0,0 @@ -From b293510f3961b90dcab59965f57779be93ceda7c Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 26 Feb 2022 14:52:32 +0100 -Subject: [PATCH 12/14] clk: qcom: gcc-ipq806x: add CryptoEngine clocks - -Add missing CryptoEngine clocks and pll11 required clock. - -Signed-off-by: Ansuel Smith -Reviewed-by: Stephen Boyd -Tested-by: Jonathan McDowell -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220226135235.10051-13-ansuelsmth@gmail.com ---- - drivers/clk/qcom/gcc-ipq806x.c | 244 +++++++++++++++++++++++++++++++++ - 1 file changed, 244 insertions(+) - ---- a/drivers/clk/qcom/gcc-ipq806x.c -+++ b/drivers/clk/qcom/gcc-ipq806x.c -@@ -256,6 +256,24 @@ static struct clk_pll pll18 = { - }, - }; - -+static struct clk_pll pll11 = { -+ .l_reg = 0x3184, -+ .m_reg = 0x3188, -+ .n_reg = 0x318c, -+ .config_reg = 0x3194, -+ .mode_reg = 0x3180, -+ .status_reg = 0x3198, -+ .status_bit = 16, -+ .clkr.hw.init = &(struct clk_init_data){ -+ .name = "pll11", -+ .parent_data = &(const struct clk_parent_data){ -+ .fw_name = "pxo", -+ }, -+ .num_parents = 1, -+ .ops = &clk_pll_ops, -+ }, -+}; -+ - enum { - P_PXO, - P_PLL8, -@@ -264,6 +282,7 @@ enum { - P_CXO, - P_PLL14, - P_PLL18, -+ P_PLL11, - }; - - static const struct parent_map gcc_pxo_pll8_map[] = { -@@ -331,6 +350,44 @@ static const struct clk_parent_data gcc_ - { .hw = &pll18.clkr.hw }, - }; - -+static const struct parent_map gcc_pxo_pll8_pll0_pll14_pll18_pll11_map[] = { -+ { P_PXO, 0 }, -+ { P_PLL8, 4 }, -+ { P_PLL0, 2 }, -+ { P_PLL14, 5 }, -+ { P_PLL18, 1 }, -+ { P_PLL11, 3 }, -+}; -+ -+static const struct clk_parent_data gcc_pxo_pll8_pll0_pll14_pll18_pll11[] = { -+ { .fw_name = "pxo" }, -+ { .hw = &pll8_vote.hw }, -+ { .hw = &pll0_vote.hw }, -+ { .hw = &pll14.clkr.hw }, -+ { .hw = &pll18.clkr.hw }, -+ { .hw = &pll11.clkr.hw }, -+ -+}; -+ -+static const struct parent_map gcc_pxo_pll3_pll0_pll14_pll18_pll11_map[] = { -+ { P_PXO, 0 }, -+ { P_PLL3, 6 }, -+ { P_PLL0, 2 }, -+ { P_PLL14, 5 }, -+ { P_PLL18, 1 }, -+ { P_PLL11, 3 }, -+}; -+ -+static const struct clk_parent_data gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = { -+ { .fw_name = "pxo" }, -+ { .hw = &pll3.clkr.hw }, -+ { .hw = &pll0_vote.hw }, -+ { .hw = &pll14.clkr.hw }, -+ { .hw = &pll18.clkr.hw }, -+ { .hw = &pll11.clkr.hw }, -+ -+}; -+ - static struct freq_tbl clk_tbl_gsbi_uart[] = { - { 1843200, P_PLL8, 2, 6, 625 }, - { 3686400, P_PLL8, 2, 12, 625 }, -@@ -2824,6 +2881,186 @@ static struct clk_dyn_rcg ubi32_core2_sr - }, - }; - -+static const struct freq_tbl clk_tbl_ce5_core[] = { -+ { 150000000, P_PLL3, 8, 1, 1 }, -+ { 213200000, P_PLL11, 5, 1, 1 }, -+ { } -+}; -+ -+static struct clk_dyn_rcg ce5_core_src = { -+ .ns_reg[0] = 0x36C4, -+ .ns_reg[1] = 0x36C8, -+ .bank_reg = 0x36C0, -+ .s[0] = { -+ .src_sel_shift = 0, -+ .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map, -+ }, -+ .s[1] = { -+ .src_sel_shift = 0, -+ .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map, -+ }, -+ .p[0] = { -+ .pre_div_shift = 3, -+ .pre_div_width = 4, -+ }, -+ .p[1] = { -+ .pre_div_shift = 3, -+ .pre_div_width = 4, -+ }, -+ .mux_sel_bit = 0, -+ .freq_tbl = clk_tbl_ce5_core, -+ .clkr = { -+ .enable_reg = 0x36C0, -+ .enable_mask = BIT(1), -+ .hw.init = &(struct clk_init_data){ -+ .name = "ce5_core_src", -+ .parent_data = gcc_pxo_pll3_pll0_pll14_pll18_pll11, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll3_pll0_pll14_pll18_pll11), -+ .ops = &clk_dyn_rcg_ops, -+ }, -+ }, -+}; -+ -+static struct clk_branch ce5_core_clk = { -+ .halt_reg = 0x2FDC, -+ .halt_bit = 5, -+ .hwcg_reg = 0x36CC, -+ .hwcg_bit = 6, -+ .clkr = { -+ .enable_reg = 0x36CC, -+ .enable_mask = BIT(4), -+ .hw.init = &(struct clk_init_data){ -+ .name = "ce5_core_clk", -+ .parent_hws = (const struct clk_hw*[]){ -+ &ce5_core_src.clkr.hw, -+ }, -+ .num_parents = 1, -+ .ops = &clk_branch_ops, -+ .flags = CLK_SET_RATE_PARENT, -+ }, -+ }, -+}; -+ -+static const struct freq_tbl clk_tbl_ce5_a_clk[] = { -+ { 160000000, P_PLL0, 5, 1, 1 }, -+ { 213200000, P_PLL11, 5, 1, 1 }, -+ { } -+}; -+ -+static struct clk_dyn_rcg ce5_a_clk_src = { -+ .ns_reg[0] = 0x3d84, -+ .ns_reg[1] = 0x3d88, -+ .bank_reg = 0x3d80, -+ .s[0] = { -+ .src_sel_shift = 0, -+ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, -+ }, -+ .s[1] = { -+ .src_sel_shift = 0, -+ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, -+ }, -+ .p[0] = { -+ .pre_div_shift = 3, -+ .pre_div_width = 4, -+ }, -+ .p[1] = { -+ .pre_div_shift = 3, -+ .pre_div_width = 4, -+ }, -+ .mux_sel_bit = 0, -+ .freq_tbl = clk_tbl_ce5_a_clk, -+ .clkr = { -+ .enable_reg = 0x3d80, -+ .enable_mask = BIT(1), -+ .hw.init = &(struct clk_init_data){ -+ .name = "ce5_a_clk_src", -+ .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11), -+ .ops = &clk_dyn_rcg_ops, -+ }, -+ }, -+}; -+ -+static struct clk_branch ce5_a_clk = { -+ .halt_reg = 0x3c20, -+ .halt_bit = 12, -+ .hwcg_reg = 0x3d8c, -+ .hwcg_bit = 6, -+ .clkr = { -+ .enable_reg = 0x3d8c, -+ .enable_mask = BIT(4), -+ .hw.init = &(struct clk_init_data){ -+ .name = "ce5_a_clk", -+ .parent_hws = (const struct clk_hw*[]){ -+ &ce5_a_clk_src.clkr.hw, -+ }, -+ .num_parents = 1, -+ .ops = &clk_branch_ops, -+ .flags = CLK_SET_RATE_PARENT, -+ }, -+ }, -+}; -+ -+static const struct freq_tbl clk_tbl_ce5_h_clk[] = { -+ { 160000000, P_PLL0, 5, 1, 1 }, -+ { 213200000, P_PLL11, 5, 1, 1 }, -+ { } -+}; -+ -+static struct clk_dyn_rcg ce5_h_clk_src = { -+ .ns_reg[0] = 0x3c64, -+ .ns_reg[1] = 0x3c68, -+ .bank_reg = 0x3c60, -+ .s[0] = { -+ .src_sel_shift = 0, -+ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, -+ }, -+ .s[1] = { -+ .src_sel_shift = 0, -+ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, -+ }, -+ .p[0] = { -+ .pre_div_shift = 3, -+ .pre_div_width = 4, -+ }, -+ .p[1] = { -+ .pre_div_shift = 3, -+ .pre_div_width = 4, -+ }, -+ .mux_sel_bit = 0, -+ .freq_tbl = clk_tbl_ce5_h_clk, -+ .clkr = { -+ .enable_reg = 0x3c60, -+ .enable_mask = BIT(1), -+ .hw.init = &(struct clk_init_data){ -+ .name = "ce5_h_clk_src", -+ .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11), -+ .ops = &clk_dyn_rcg_ops, -+ }, -+ }, -+}; -+ -+static struct clk_branch ce5_h_clk = { -+ .halt_reg = 0x3c20, -+ .halt_bit = 11, -+ .hwcg_reg = 0x3c6c, -+ .hwcg_bit = 6, -+ .clkr = { -+ .enable_reg = 0x3c6c, -+ .enable_mask = BIT(4), -+ .hw.init = &(struct clk_init_data){ -+ .name = "ce5_h_clk", -+ .parent_hws = (const struct clk_hw*[]){ -+ &ce5_h_clk_src.clkr.hw, -+ }, -+ .num_parents = 1, -+ .ops = &clk_branch_ops, -+ .flags = CLK_SET_RATE_PARENT, -+ }, -+ }, -+}; -+ - static struct clk_regmap *gcc_ipq806x_clks[] = { - [PLL0] = &pll0.clkr, - [PLL0_VOTE] = &pll0_vote, -@@ -2831,6 +3068,7 @@ static struct clk_regmap *gcc_ipq806x_cl - [PLL4_VOTE] = &pll4_vote, - [PLL8] = &pll8.clkr, - [PLL8_VOTE] = &pll8_vote, -+ [PLL11] = &pll11.clkr, - [PLL14] = &pll14.clkr, - [PLL14_VOTE] = &pll14_vote, - [PLL18] = &pll18.clkr, -@@ -2945,6 +3183,12 @@ static struct clk_regmap *gcc_ipq806x_cl - [PLL9] = &hfpll0.clkr, - [PLL10] = &hfpll1.clkr, - [PLL12] = &hfpll_l2.clkr, -+ [CE5_A_CLK_SRC] = &ce5_a_clk_src.clkr, -+ [CE5_A_CLK] = &ce5_a_clk.clkr, -+ [CE5_H_CLK_SRC] = &ce5_h_clk_src.clkr, -+ [CE5_H_CLK] = &ce5_h_clk.clkr, -+ [CE5_CORE_CLK_SRC] = &ce5_core_src.clkr, -+ [CE5_CORE_CLK] = &ce5_core_clk.clkr, - }; - - static const struct qcom_reset_map gcc_ipq806x_resets[] = { diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-13-linux-next-dt-bindings-reset-add-ipq8064-ce5-resets.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-13-linux-next-dt-bindings-reset-add-ipq8064-ce5-resets.patch deleted file mode 100644 index 5d05c2b3af3..00000000000 --- a/target/linux/ipq806x/patches-5.15/100-v5.18-13-linux-next-dt-bindings-reset-add-ipq8064-ce5-resets.patch +++ /dev/null @@ -1,29 +0,0 @@ -From f4a7e56f4956f0450b9f671ed93d45ffcc15aa62 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Tue, 18 Jan 2022 01:22:05 +0100 -Subject: [PATCH v6 13/15] dt-bindings: reset: add ipq8064 ce5 resets - -Add ipq8064 ce5 resets needed for CryptoEngine gcc driver. - -Signed-off-by: Ansuel Smith -Reviewed-by: Bjorn Andersson -Acked-by: Philipp Zabel -Acked-by: Rob Herring -Reviewed-by: Stephen Boyd ---- - include/dt-bindings/reset/qcom,gcc-ipq806x.h | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h -+++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h -@@ -163,5 +163,10 @@ - #define NSS_CAL_PRBS_RST_N_RESET 154 - #define NSS_LCKDT_RST_N_RESET 155 - #define NSS_SRDS_N_RESET 156 -+#define CRYPTO_ENG1_RESET 157 -+#define CRYPTO_ENG2_RESET 158 -+#define CRYPTO_ENG3_RESET 159 -+#define CRYPTO_ENG4_RESET 160 -+#define CRYPTO_AHB_RESET 161 - - #endif diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-14-linux-next-clk-qcom-gcc-ipq806x-add-CryptoEngine-resets.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-14-linux-next-clk-qcom-gcc-ipq806x-add-CryptoEngine-resets.patch deleted file mode 100644 index a26f67e36e0..00000000000 --- a/target/linux/ipq806x/patches-5.15/100-v5.18-14-linux-next-clk-qcom-gcc-ipq806x-add-CryptoEngine-resets.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 4f865bdcb44fb18951de94be5c2ec37a891a8d03 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 26 Feb 2022 14:52:34 +0100 -Subject: [PATCH 14/14] clk: qcom: gcc-ipq806x: add CryptoEngine resets - -Add missing CryptoEngine resets. - -Signed-off-by: Ansuel Smith -Reviewed-by: Stephen Boyd -Tested-by: Jonathan McDowell -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220226135235.10051-15-ansuelsmth@gmail.com ---- - drivers/clk/qcom/gcc-ipq806x.c | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/drivers/clk/qcom/gcc-ipq806x.c -+++ b/drivers/clk/qcom/gcc-ipq806x.c -@@ -3320,6 +3320,11 @@ static const struct qcom_reset_map gcc_i - [GMAC_CORE3_RESET] = { 0x3cfc, 0 }, - [GMAC_CORE4_RESET] = { 0x3d1c, 0 }, - [GMAC_AHB_RESET] = { 0x3e24, 0 }, -+ [CRYPTO_ENG1_RESET] = { 0x3e00, 0}, -+ [CRYPTO_ENG2_RESET] = { 0x3e04, 0}, -+ [CRYPTO_ENG3_RESET] = { 0x3e08, 0}, -+ [CRYPTO_ENG4_RESET] = { 0x3e0c, 0}, -+ [CRYPTO_AHB_RESET] = { 0x3e10, 0}, - [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 }, - [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 }, - [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 }, diff --git a/target/linux/ipq806x/patches-5.15/101-v6.0-01-net-ethernet-stmmac-add-missing-sgmii-configure-for-.patch b/target/linux/ipq806x/patches-5.15/101-v6.0-01-net-ethernet-stmmac-add-missing-sgmii-configure-for-.patch deleted file mode 100644 index bd492ca1ecd..00000000000 --- a/target/linux/ipq806x/patches-5.15/101-v6.0-01-net-ethernet-stmmac-add-missing-sgmii-configure-for-.patch +++ /dev/null @@ -1,151 +0,0 @@ -From 9ec092d2feb69045dd289845024301fb91c064ee Mon Sep 17 00:00:00 2001 -From: Christian 'Ansuel' Marangi -Date: Tue, 14 Jun 2022 13:22:27 +0200 -Subject: [PATCH 1/2] net: ethernet: stmmac: add missing sgmii configure for - ipq806x - -The different gmacid require different configuration based on the soc -and on the gmac id. Add these missing configuration taken from the -original driver. - -Signed-off-by: Christian 'Ansuel' Marangi -Link: https://lore.kernel.org/r/20220614112228.1998-1-ansuelsmth@gmail.com -Signed-off-by: Paolo Abeni ---- - drivers/net/ethernet/stmicro/stmmac/Kconfig | 1 + - .../ethernet/stmicro/stmmac/dwmac-ipq806x.c | 93 +++++++++++++++---- - 2 files changed, 78 insertions(+), 16 deletions(-) - ---- a/drivers/net/ethernet/stmicro/stmmac/Kconfig -+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig -@@ -83,6 +83,7 @@ config DWMAC_IPQ806X - default ARCH_QCOM - depends on OF && (ARCH_QCOM || COMPILE_TEST) - select MFD_SYSCON -+ select QCOM_SOCINFO - help - Support for QCA IPQ806X DWMAC Ethernet. - ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c -@@ -27,6 +27,8 @@ - #include - #include - #include -+#include -+#include - - #include "stmmac_platform.h" - -@@ -75,11 +77,20 @@ - #define QSGMII_PHY_RX_SIGNAL_DETECT_EN BIT(2) - #define QSGMII_PHY_TX_DRIVER_EN BIT(3) - #define QSGMII_PHY_QSGMII_EN BIT(7) --#define QSGMII_PHY_PHASE_LOOP_GAIN_OFFSET 12 --#define QSGMII_PHY_RX_DC_BIAS_OFFSET 18 --#define QSGMII_PHY_RX_INPUT_EQU_OFFSET 20 --#define QSGMII_PHY_CDR_PI_SLEW_OFFSET 22 --#define QSGMII_PHY_TX_DRV_AMP_OFFSET 28 -+#define QSGMII_PHY_DEEMPHASIS_LVL_MASK GENMASK(11, 10) -+#define QSGMII_PHY_DEEMPHASIS_LVL(x) FIELD_PREP(QSGMII_PHY_DEEMPHASIS_LVL_MASK, (x)) -+#define QSGMII_PHY_PHASE_LOOP_GAIN_MASK GENMASK(14, 12) -+#define QSGMII_PHY_PHASE_LOOP_GAIN(x) FIELD_PREP(QSGMII_PHY_PHASE_LOOP_GAIN_MASK, (x)) -+#define QSGMII_PHY_RX_DC_BIAS_MASK GENMASK(19, 18) -+#define QSGMII_PHY_RX_DC_BIAS(x) FIELD_PREP(QSGMII_PHY_RX_DC_BIAS_MASK, (x)) -+#define QSGMII_PHY_RX_INPUT_EQU_MASK GENMASK(21, 20) -+#define QSGMII_PHY_RX_INPUT_EQU(x) FIELD_PREP(QSGMII_PHY_RX_INPUT_EQU_MASK, (x)) -+#define QSGMII_PHY_CDR_PI_SLEW_MASK GENMASK(23, 22) -+#define QSGMII_PHY_CDR_PI_SLEW(x) FIELD_PREP(QSGMII_PHY_CDR_PI_SLEW_MASK, (x)) -+#define QSGMII_PHY_TX_SLEW_MASK GENMASK(27, 26) -+#define QSGMII_PHY_TX_SLEW(x) FIELD_PREP(QSGMII_PHY_TX_SLEW_MASK, (x)) -+#define QSGMII_PHY_TX_DRV_AMP_MASK GENMASK(31, 28) -+#define QSGMII_PHY_TX_DRV_AMP(x) FIELD_PREP(QSGMII_PHY_TX_DRV_AMP_MASK, (x)) - - struct ipq806x_gmac { - struct platform_device *pdev; -@@ -242,6 +253,64 @@ static void ipq806x_gmac_fix_mac_speed(v - ipq806x_gmac_set_speed(gmac, speed); - } - -+static const struct soc_device_attribute ipq806x_gmac_soc_v1[] = { -+ { -+ .revision = "1.*", -+ }, -+ { -+ /* sentinel */ -+ } -+}; -+ -+static int -+ipq806x_gmac_configure_qsgmii_params(struct ipq806x_gmac *gmac) -+{ -+ struct platform_device *pdev = gmac->pdev; -+ const struct soc_device_attribute *soc; -+ struct device *dev = &pdev->dev; -+ u32 qsgmii_param; -+ -+ switch (gmac->id) { -+ case 1: -+ soc = soc_device_match(ipq806x_gmac_soc_v1); -+ -+ if (soc) -+ qsgmii_param = QSGMII_PHY_TX_DRV_AMP(0xc) | -+ QSGMII_PHY_TX_SLEW(0x2) | -+ QSGMII_PHY_DEEMPHASIS_LVL(0x2); -+ else -+ qsgmii_param = QSGMII_PHY_TX_DRV_AMP(0xd) | -+ QSGMII_PHY_TX_SLEW(0x0) | -+ QSGMII_PHY_DEEMPHASIS_LVL(0x0); -+ -+ qsgmii_param |= QSGMII_PHY_RX_DC_BIAS(0x2); -+ break; -+ case 2: -+ case 3: -+ qsgmii_param = QSGMII_PHY_RX_DC_BIAS(0x3) | -+ QSGMII_PHY_TX_DRV_AMP(0xc); -+ break; -+ default: /* gmac 0 can't be set in SGMII mode */ -+ dev_err(dev, "gmac id %d can't be in SGMII mode", gmac->id); -+ return -EINVAL; -+ } -+ -+ /* Common params across all gmac id */ -+ qsgmii_param |= QSGMII_PHY_CDR_EN | -+ QSGMII_PHY_RX_FRONT_EN | -+ QSGMII_PHY_RX_SIGNAL_DETECT_EN | -+ QSGMII_PHY_TX_DRIVER_EN | -+ QSGMII_PHY_QSGMII_EN | -+ QSGMII_PHY_PHASE_LOOP_GAIN(0x4) | -+ QSGMII_PHY_RX_INPUT_EQU(0x1) | -+ QSGMII_PHY_CDR_PI_SLEW(0x2); -+ -+ regmap_write(gmac->qsgmii_csr, QSGMII_PHY_SGMII_CTL(gmac->id), -+ qsgmii_param); -+ -+ return 0; -+} -+ - static int ipq806x_gmac_probe(struct platform_device *pdev) - { - struct plat_stmmacenet_data *plat_dat; -@@ -328,17 +397,9 @@ static int ipq806x_gmac_probe(struct pla - regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val); - - if (gmac->phy_mode == PHY_INTERFACE_MODE_SGMII) { -- regmap_write(gmac->qsgmii_csr, QSGMII_PHY_SGMII_CTL(gmac->id), -- QSGMII_PHY_CDR_EN | -- QSGMII_PHY_RX_FRONT_EN | -- QSGMII_PHY_RX_SIGNAL_DETECT_EN | -- QSGMII_PHY_TX_DRIVER_EN | -- QSGMII_PHY_QSGMII_EN | -- 0x4ul << QSGMII_PHY_PHASE_LOOP_GAIN_OFFSET | -- 0x3ul << QSGMII_PHY_RX_DC_BIAS_OFFSET | -- 0x1ul << QSGMII_PHY_RX_INPUT_EQU_OFFSET | -- 0x2ul << QSGMII_PHY_CDR_PI_SLEW_OFFSET | -- 0xCul << QSGMII_PHY_TX_DRV_AMP_OFFSET); -+ err = ipq806x_gmac_configure_qsgmii_params(gmac); -+ if (err) -+ goto err_remove_config_dt; - } - - plat_dat->has_gmac = true; diff --git a/target/linux/ipq806x/patches-5.15/101-v6.0-02-net-ethernet-stmmac-reset-force-speed-bit-for-ipq806.patch b/target/linux/ipq806x/patches-5.15/101-v6.0-02-net-ethernet-stmmac-reset-force-speed-bit-for-ipq806.patch deleted file mode 100644 index d444553452c..00000000000 --- a/target/linux/ipq806x/patches-5.15/101-v6.0-02-net-ethernet-stmmac-reset-force-speed-bit-for-ipq806.patch +++ /dev/null @@ -1,110 +0,0 @@ -From 8bca458990dd8c6d001b2fb52063aa18e8ca7444 Mon Sep 17 00:00:00 2001 -From: Christian 'Ansuel' Marangi -Date: Tue, 14 Jun 2022 13:22:28 +0200 -Subject: [PATCH 2/2] net: ethernet: stmmac: reset force speed bit for ipq806x - -Some bootloader may set the force speed regs even if the actual -interface should use autonegotiation between PCS and PHY. -This cause the complete malfuction of the interface. - -To fix this correctly reset the force speed regs if a fixed-link is not -defined in the DTS. With a fixed-link node correctly configure the -forced speed regs to handle any misconfiguration by the bootloader. - -Reported-by: Mark Mentovai -Co-developed-by: Mark Mentovai -Signed-off-by: Mark Mentovai -Signed-off-by: Christian 'Ansuel' Marangi -Link: https://lore.kernel.org/r/20220614112228.1998-2-ansuelsmth@gmail.com -Signed-off-by: Paolo Abeni ---- - .../ethernet/stmicro/stmmac/dwmac-ipq806x.c | 64 +++++++++++++++++++ - 1 file changed, 64 insertions(+) - ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c -@@ -66,6 +66,17 @@ - #define NSS_COMMON_CLK_DIV_SGMII_100 4 - #define NSS_COMMON_CLK_DIV_SGMII_10 49 - -+#define QSGMII_PCS_ALL_CH_CTL 0x80 -+#define QSGMII_PCS_CH_SPEED_FORCE BIT(1) -+#define QSGMII_PCS_CH_SPEED_10 0x0 -+#define QSGMII_PCS_CH_SPEED_100 BIT(2) -+#define QSGMII_PCS_CH_SPEED_1000 BIT(3) -+#define QSGMII_PCS_CH_SPEED_MASK (QSGMII_PCS_CH_SPEED_FORCE | \ -+ QSGMII_PCS_CH_SPEED_10 | \ -+ QSGMII_PCS_CH_SPEED_100 | \ -+ QSGMII_PCS_CH_SPEED_1000) -+#define QSGMII_PCS_CH_SPEED_SHIFT(x) ((x) * 4) -+ - #define QSGMII_PCS_CAL_LCKDT_CTL 0x120 - #define QSGMII_PCS_CAL_LCKDT_CTL_RST BIT(19) - -@@ -253,6 +264,55 @@ static void ipq806x_gmac_fix_mac_speed(v - ipq806x_gmac_set_speed(gmac, speed); - } - -+static int -+ipq806x_gmac_configure_qsgmii_pcs_speed(struct ipq806x_gmac *gmac) -+{ -+ struct platform_device *pdev = gmac->pdev; -+ struct device *dev = &pdev->dev; -+ struct device_node *dn; -+ int link_speed; -+ int val = 0; -+ int ret; -+ -+ /* Some bootloader may apply wrong configuration and cause -+ * not functioning port. If fixed link is not set, -+ * reset the force speed bit. -+ */ -+ if (!of_phy_is_fixed_link(pdev->dev.of_node)) -+ goto write; -+ -+ dn = of_get_child_by_name(pdev->dev.of_node, "fixed-link"); -+ ret = of_property_read_u32(dn, "speed", &link_speed); -+ of_node_put(dn); -+ if (ret) { -+ dev_err(dev, "found fixed-link node with no speed"); -+ return ret; -+ } -+ -+ val = QSGMII_PCS_CH_SPEED_FORCE; -+ -+ switch (link_speed) { -+ case SPEED_1000: -+ val |= QSGMII_PCS_CH_SPEED_1000; -+ break; -+ case SPEED_100: -+ val |= QSGMII_PCS_CH_SPEED_100; -+ break; -+ case SPEED_10: -+ val |= QSGMII_PCS_CH_SPEED_10; -+ break; -+ } -+ -+write: -+ regmap_update_bits(gmac->qsgmii_csr, QSGMII_PCS_ALL_CH_CTL, -+ QSGMII_PCS_CH_SPEED_MASK << -+ QSGMII_PCS_CH_SPEED_SHIFT(gmac->id), -+ val << -+ QSGMII_PCS_CH_SPEED_SHIFT(gmac->id)); -+ -+ return 0; -+} -+ - static const struct soc_device_attribute ipq806x_gmac_soc_v1[] = { - { - .revision = "1.*", -@@ -400,6 +460,10 @@ static int ipq806x_gmac_probe(struct pla - err = ipq806x_gmac_configure_qsgmii_params(gmac); - if (err) - goto err_remove_config_dt; -+ -+ err = ipq806x_gmac_configure_qsgmii_pcs_speed(gmac); -+ if (err) -+ goto err_remove_config_dt; - } - - plat_dat->has_gmac = true; diff --git a/target/linux/ipq806x/patches-5.15/102-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch b/target/linux/ipq806x/patches-5.15/102-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch deleted file mode 100644 index e0c195f1ab9..00000000000 --- a/target/linux/ipq806x/patches-5.15/102-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 5001f2e1a325b68dbf225bd17f69a4d3d975cca5 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 9 Mar 2017 09:31:44 +0100 -Subject: [PATCH 61/69] mtd: "rootfs" conflicts with OpenWrt auto mounting - -Signed-off-by: John Crispin ---- - drivers/mtd/mtdpart.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/drivers/mtd/mtdpart.c -+++ b/drivers/mtd/mtdpart.c -@@ -51,7 +51,11 @@ static struct mtd_info *allocate_partiti - - /* allocate the partition structure */ - child = kzalloc(sizeof(*child), GFP_KERNEL); -- name = kstrdup(part->name, GFP_KERNEL); -+ /* "rootfs" conflicts with OpenWrt auto mounting */ -+ if (mtd_type_is_nand(parent) && !strcmp(part->name, "rootfs")) -+ name = "ubi"; -+ else -+ name = kstrdup(part->name, GFP_KERNEL); - if (!name || !child) { - printk(KERN_ERR"memory allocation error while creating partitions for \"%s\"\n", - parent->name); diff --git a/target/linux/ipq806x/patches-5.15/103-v5.19-ARM-dts-qcom-add-syscon-and-cxo-pxo-clock-to-gcc-nod.patch b/target/linux/ipq806x/patches-5.15/103-v5.19-ARM-dts-qcom-add-syscon-and-cxo-pxo-clock-to-gcc-nod.patch deleted file mode 100644 index 2ce526b6ca7..00000000000 --- a/target/linux/ipq806x/patches-5.15/103-v5.19-ARM-dts-qcom-add-syscon-and-cxo-pxo-clock-to-gcc-nod.patch +++ /dev/null @@ -1,48 +0,0 @@ -From a5ba119455c77a07e05f2fe0af446c8bf43d1a00 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 26 Feb 2022 14:52:35 +0100 -Subject: [PATCH] ARM: dts: qcom: add syscon and cxo/pxo clock to gcc node for - ipq8064 - -Add syscon compatible required for tsens driver to correctly probe driver -and access the reg. Also add cxo and pxo tag and declare them as gcc clock -now requires them for the ipq8064 gcc driver that has now been modernized. - -Signed-off-by: Ansuel Smith -Reviewed-by: Bjorn Andersson -Reviewed-by: Stephen Boyd -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220226135235.10051-16-ansuelsmth@gmail.com ---- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 +++++--- - 1 file changed, 5 insertions(+), 3 deletions(-) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -298,13 +298,13 @@ - }; - - clocks { -- cxo_board { -+ cxo_board: cxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - -- pxo_board { -+ pxo_board: pxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; -@@ -736,7 +736,9 @@ - }; - - gcc: clock-controller@900000 { -- compatible = "qcom,gcc-ipq8064"; -+ compatible = "qcom,gcc-ipq8064", "syscon"; -+ clocks = <&pxo_board>, <&cxo_board>; -+ clock-names = "pxo", "cxo"; - reg = <0x00900000 0x4000>; - #clock-cells = <1>; - #reset-cells = <1>; diff --git a/target/linux/ipq806x/patches-5.15/103-v6.0-01-ARM-dts-qcom-replace-gcc-PXO-with-pxo_board-fixed-cl.patch b/target/linux/ipq806x/patches-5.15/103-v6.0-01-ARM-dts-qcom-replace-gcc-PXO-with-pxo_board-fixed-cl.patch deleted file mode 100644 index d0bc34c07fa..00000000000 --- a/target/linux/ipq806x/patches-5.15/103-v6.0-01-ARM-dts-qcom-replace-gcc-PXO-with-pxo_board-fixed-cl.patch +++ /dev/null @@ -1,29 +0,0 @@ -From eb9e93937756a05787977875830c0dc482cb57e0 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 30 Apr 2022 07:51:17 +0200 -Subject: [PATCH] ARM: dts: qcom: replace gcc PXO with pxo_board fixed clock - -Replace gcc PXO phandle to pxo_board fixed clock declared in the dts. -gcc driver doesn't provide PXO_SRC as it's a fixed-clock. This cause a -kernel panic if any driver actually try to use it. - -Fixes: 40cf5c884a96 ("ARM: dts: qcom: add L2CC and RPM for IPQ8064") -Signed-off-by: Ansuel Smith -Reviewed-by: Dmitry Baryshkov -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220430055118.1947-2-ansuelsmth@gmail.com ---- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -784,7 +784,7 @@ - l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc", "syscon"; - reg = <0x2011000 0x1000>; -- clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; -+ clocks = <&gcc PLL8_VOTE>, <&pxo_board>; - clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu_l2_aux"; - }; diff --git a/target/linux/ipq806x/patches-5.15/104-v6.0-01-ARM-dts-qcom-ipq8064-add-multiple-missing-pin-defini.patch b/target/linux/ipq806x/patches-5.15/104-v6.0-01-ARM-dts-qcom-ipq8064-add-multiple-missing-pin-defini.patch deleted file mode 100644 index 5dad164e3c2..00000000000 --- a/target/linux/ipq806x/patches-5.15/104-v6.0-01-ARM-dts-qcom-ipq8064-add-multiple-missing-pin-defini.patch +++ /dev/null @@ -1,101 +0,0 @@ -From 4af1defb305798d1a064a5ea0d0c9b30e5eee185 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 7 Jul 2022 03:09:35 +0200 -Subject: [PATCH 1/8] ARM: dts: qcom: ipq8064: add multiple missing pin - definition - -Add missing definition for mdio0 pins used for gpio-bitbang driver,i2c4 -pins and rgmii2 pins for ipq8064. - -Drop i2c4_pins node from ipq8064-ap148 dts as it's now moved to ipq8064 -dtsi. - -Drop mdio0_pins node from ipq8064-rb3011 dts as it's now moved to -ipq8064 dtsi. - -Signed-off-by: Christian Marangi -Tested-by: Jonathan McDowell -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220707010943.20857-2-ansuelsmth@gmail.com ---- - arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 6 ----- - arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 9 ------- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 32 +++++++++++++++++++++++ - 3 files changed, 32 insertions(+), 15 deletions(-) - ---- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts -+++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts -@@ -305,15 +305,6 @@ - }; - }; - -- mdio0_pins: mdio0_pins { -- mux { -- pins = "gpio0", "gpio1"; -- function = "gpio"; -- drive-strength = <8>; -- bias-disable; -- }; -- }; -- - mdio1_pins: mdio1_pins { - mux { - pins = "gpio10", "gpio11"; ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -382,6 +382,13 @@ - }; - }; - -+ i2c4_pins: i2c4-default { -+ pins = "gpio12", "gpio13"; -+ function = "gsbi4"; -+ drive-strength = <12>; -+ bias-disable; -+ }; -+ - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; -@@ -424,6 +431,8 @@ - - pullups { - pins = "gpio39"; -+ function = "nand"; -+ drive-strength = <10>; - bias-pull-up; - }; - -@@ -431,9 +440,32 @@ - pins = "gpio40", "gpio41", "gpio42", - "gpio43", "gpio44", "gpio45", - "gpio46", "gpio47"; -+ function = "nand"; -+ drive-strength = <10>; - bias-bus-hold; - }; - }; -+ -+ mdio0_pins: mdio0-pins { -+ mux { -+ pins = "gpio0", "gpio1"; -+ function = "mdio"; -+ drive-strength = <8>; -+ bias-disable; -+ }; -+ }; -+ -+ rgmii2_pins: rgmii2-pins { -+ mux { -+ pins = "gpio27", "gpio28", "gpio29", -+ "gpio30", "gpio31", "gpio32", -+ "gpio51", "gpio52", "gpio59", -+ "gpio60", "gpio61", "gpio62"; -+ function = "rgmii2"; -+ drive-strength = <8>; -+ bias-disable; -+ }; -+ }; - }; - - intc: interrupt-controller@2000000 { diff --git a/target/linux/ipq806x/patches-5.15/104-v6.0-02-ARM-dts-qcom-ipq8064-add-gsbi6-missing-definition.patch b/target/linux/ipq806x/patches-5.15/104-v6.0-02-ARM-dts-qcom-ipq8064-add-gsbi6-missing-definition.patch deleted file mode 100644 index 1f4e288fb81..00000000000 --- a/target/linux/ipq806x/patches-5.15/104-v6.0-02-ARM-dts-qcom-ipq8064-add-gsbi6-missing-definition.patch +++ /dev/null @@ -1,67 +0,0 @@ -From d883a12a547b6d42e795ff3b5ac87cfd013b5423 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 7 Jul 2022 03:09:36 +0200 -Subject: [PATCH 2/8] ARM: dts: qcom: ipq8064: add gsbi6 missing definition - -Add gsbi6 missing definition for ipq8064. - -Signed-off-by: Christian Marangi -Tested-by: Jonathan McDowell -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220707010943.20857-3-ansuelsmth@gmail.com ---- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 43 +++++++++++++++++++++++++++++ - 1 file changed, 43 insertions(+) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -663,6 +663,49 @@ - }; - }; - -+ gsbi6: gsbi@16500000 { -+ compatible = "qcom,gsbi-v1.0.0"; -+ reg = <0x16500000 0x100>; -+ cell-index = <6>; -+ clocks = <&gcc GSBI6_H_CLK>; -+ clock-names = "iface"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ syscon-tcsr = <&tcsr>; -+ -+ status = "disabled"; -+ -+ gsbi6_i2c: i2c@16580000 { -+ compatible = "qcom,i2c-qup-v1.1.1"; -+ reg = <0x16580000 0x1000>; -+ interrupts = ; -+ -+ clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; -+ clock-names = "core", "iface"; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ status = "disabled"; -+ }; -+ -+ gsbi6_spi: spi@16580000 { -+ compatible = "qcom,spi-qup-v1.1.1"; -+ reg = <0x16580000 0x1000>; -+ interrupts = ; -+ -+ clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; -+ clock-names = "core", "iface"; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ status = "disabled"; -+ }; -+ }; -+ - gsbi7: gsbi@16600000 { - status = "disabled"; - compatible = "qcom,gsbi-v1.0.0"; diff --git a/target/linux/ipq806x/patches-5.15/104-v6.0-03-ARM-dts-qcom-ipq8064-add-specific-dtsi-with-smb208-r.patch b/target/linux/ipq806x/patches-5.15/104-v6.0-03-ARM-dts-qcom-ipq8064-add-specific-dtsi-with-smb208-r.patch deleted file mode 100644 index dbba722caaf..00000000000 --- a/target/linux/ipq806x/patches-5.15/104-v6.0-03-ARM-dts-qcom-ipq8064-add-specific-dtsi-with-smb208-r.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 5c47a46d5e942ea6b041c8b7727b201817c1ff76 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 7 Jul 2022 03:09:37 +0200 -Subject: [PATCH 3/8] ARM: dts: qcom: ipq8064: add specific dtsi with smb208 - rpm regulators - -Add specific ipq8064 dtsi with smb208 rpm regulators. - -Qcom advise to use this configuration but it's not mandatory and OEM -can decide to implement their own regulators. -smb208 regulators are used to scale CPU voltage, L2 cache voltage and -Ubi32 cores. - -There regulators are controlled by rpm and to correctly works gsbi4-i2c -require to be NEVER disabled or rpm will reject any regulator change -request. - -Signed-off-by: Christian Marangi -Tested-by: Jonathan McDowell -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220707010943.20857-4-ansuelsmth@gmail.com ---- - arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi | 37 ++++++++++++++++++++++ - 1 file changed, 37 insertions(+) - create mode 100644 arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi - ---- /dev/null -+++ b/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi -@@ -0,0 +1,37 @@ -+// SPDX-License-Identifier: GPL-2.0 -+ -+#include "qcom-ipq8064.dtsi" -+ -+&rpm { -+ smb208_regulators: regulators { -+ compatible = "qcom,rpm-smb208-regulators"; -+ -+ smb208_s1a: s1a { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1150000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s1b: s1b { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1150000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s2a: s2a { -+ regulator-min-microvolt = < 800000>; -+ regulator-max-microvolt = <1250000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s2b: s2b { -+ regulator-min-microvolt = < 800000>; -+ regulator-max-microvolt = <1250000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ }; -+}; diff --git a/target/linux/ipq806x/patches-5.15/104-v6.0-04-ARM-dts-qcom-ipq8064-add-missing-snps-dwmac-compatib.patch b/target/linux/ipq806x/patches-5.15/104-v6.0-04-ARM-dts-qcom-ipq8064-add-missing-snps-dwmac-compatib.patch deleted file mode 100644 index 1a3185f500d..00000000000 --- a/target/linux/ipq806x/patches-5.15/104-v6.0-04-ARM-dts-qcom-ipq8064-add-missing-snps-dwmac-compatib.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 0ce34e0c13e99c239cce6099f64b0e95697f36b1 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 7 Jul 2022 03:09:38 +0200 -Subject: [PATCH 4/8] ARM: dts: qcom: ipq8064: add missing snps,dwmac - compatible for gmac - -Add missing snps,dwmac compatible for gmac ipq8064 dtsi. - -Signed-off-by: Christian Marangi -Tested-by: Jonathan McDowell -Reviewed-by: Krzysztof Kozlowski -Reviewed-by: Konrad Dybcio -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220707010943.20857-5-ansuelsmth@gmail.com ---- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -1042,7 +1042,7 @@ - - gmac0: ethernet@37000000 { - device_type = "network"; -- compatible = "qcom,ipq806x-gmac"; -+ compatible = "qcom,ipq806x-gmac", "snps,dwmac"; - reg = <0x37000000 0x200000>; - interrupts = ; - interrupt-names = "macirq"; -@@ -1066,7 +1066,7 @@ - - gmac1: ethernet@37200000 { - device_type = "network"; -- compatible = "qcom,ipq806x-gmac"; -+ compatible = "qcom,ipq806x-gmac", "snps,dwmac"; - reg = <0x37200000 0x200000>; - interrupts = ; - interrupt-names = "macirq"; -@@ -1090,7 +1090,7 @@ - - gmac2: ethernet@37400000 { - device_type = "network"; -- compatible = "qcom,ipq806x-gmac"; -+ compatible = "qcom,ipq806x-gmac", "snps,dwmac"; - reg = <0x37400000 0x200000>; - interrupts = ; - interrupt-names = "macirq"; -@@ -1114,7 +1114,7 @@ - - gmac3: ethernet@37600000 { - device_type = "network"; -- compatible = "qcom,ipq806x-gmac"; -+ compatible = "qcom,ipq806x-gmac", "snps,dwmac"; - reg = <0x37600000 0x200000>; - interrupts = ; - interrupt-names = "macirq"; diff --git a/target/linux/ipq806x/patches-5.15/104-v6.0-05-ARM-dts-qcom-ipq8064-disable-usb-phy-by-default.patch b/target/linux/ipq806x/patches-5.15/104-v6.0-05-ARM-dts-qcom-ipq8064-disable-usb-phy-by-default.patch deleted file mode 100644 index 43dac4b7fa2..00000000000 --- a/target/linux/ipq806x/patches-5.15/104-v6.0-05-ARM-dts-qcom-ipq8064-disable-usb-phy-by-default.patch +++ /dev/null @@ -1,37 +0,0 @@ -From d63d3124c0a5cdbe8b91d81b922fe56b2462e1b9 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 7 Jul 2022 03:09:39 +0200 -Subject: [PATCH 5/8] ARM: dts: qcom: ipq8064: disable usb phy by default - -Disable usb phy by default. When the usb phy were pushed, half of them -were flagged as disabled by mistake. -Correctly disable all usb phy and enable them only if a device actually -use them. - -Signed-off-by: Christian Marangi -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220707010943.20857-6-ansuelsmth@gmail.com ---- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -1188,6 +1188,8 @@ - clocks = <&gcc USB30_1_UTMI_CLK>; - clock-names = "ref"; - #phy-cells = <0>; -+ -+ status = "disabled"; - }; - - ss_phy_1: phy@110f8830 { -@@ -1196,6 +1198,8 @@ - clocks = <&gcc USB30_1_MASTER_CLK>; - clock-names = "ref"; - #phy-cells = <0>; -+ -+ status = "disabled"; - }; - - usb3_1: usb3@110f8800 { diff --git a/target/linux/ipq806x/patches-5.15/104-v6.0-07-ARM-dts-qcom-ipq8064-fix-and-add-some-missing-gsbi-n.patch b/target/linux/ipq806x/patches-5.15/104-v6.0-07-ARM-dts-qcom-ipq8064-fix-and-add-some-missing-gsbi-n.patch deleted file mode 100644 index ca5e5aa3c4c..00000000000 --- a/target/linux/ipq806x/patches-5.15/104-v6.0-07-ARM-dts-qcom-ipq8064-fix-and-add-some-missing-gsbi-n.patch +++ /dev/null @@ -1,94 +0,0 @@ -From 6c421a9c08286389bb331fe783e2625c9efcc187 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 7 Jul 2022 03:09:41 +0200 -Subject: [PATCH 7/8] ARM: dts: qcom: ipq8064: fix and add some missing gsbi - node - -Add some tag for gsbi to make them usable for ipq8064 SoC. Add missing -gsbi7 i2c node and gsbi1 node. - -Signed-off-by: Christian Marangi -Tested-by: Jonathan McDowell -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220707010943.20857-8-ansuelsmth@gmail.com ---- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 54 ++++++++++++++++++++++++++++- - 1 file changed, 53 insertions(+), 1 deletion(-) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -539,6 +539,44 @@ - regulator; - }; - -+ gsbi1: gsbi@12440000 { -+ compatible = "qcom,gsbi-v1.0.0"; -+ reg = <0x12440000 0x100>; -+ cell-index = <1>; -+ clocks = <&gcc GSBI1_H_CLK>; -+ clock-names = "iface"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ syscon-tcsr = <&tcsr>; -+ -+ status = "disabled"; -+ -+ gsbi1_serial: serial@12450000 { -+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; -+ reg = <0x12450000 0x100>, -+ <0x12400000 0x03>; -+ interrupts = ; -+ clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; -+ clock-names = "core", "iface"; -+ -+ status = "disabled"; -+ }; -+ -+ gsbi1_i2c: i2c@12460000 { -+ compatible = "qcom,i2c-qup-v1.1.1"; -+ reg = <0x12460000 0x1000>; -+ interrupts = ; -+ clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; -+ clock-names = "core", "iface"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ status = "disabled"; -+ }; -+ }; -+ - gsbi2: gsbi@12480000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <2>; -@@ -562,7 +600,7 @@ - status = "disabled"; - }; - -- i2c@124a0000 { -+ gsbi2_i2c: i2c@124a0000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x124a0000 0x1000>; - interrupts = ; -@@ -727,6 +765,20 @@ - clock-names = "core", "iface"; - status = "disabled"; - }; -+ -+ gsbi7_i2c: i2c@16680000 { -+ compatible = "qcom,i2c-qup-v1.1.1"; -+ reg = <0x16680000 0x1000>; -+ interrupts = ; -+ -+ clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; -+ clock-names = "core", "iface"; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ status = "disabled"; -+ }; - }; - - rng@1a500000 { diff --git a/target/linux/ipq806x/patches-5.15/104-v6.0-08-ARM-dts-qcom-ipq8064-add-speedbin-efuse-nvmem-node.patch b/target/linux/ipq806x/patches-5.15/104-v6.0-08-ARM-dts-qcom-ipq8064-add-speedbin-efuse-nvmem-node.patch deleted file mode 100644 index 463c3d4a658..00000000000 --- a/target/linux/ipq806x/patches-5.15/104-v6.0-08-ARM-dts-qcom-ipq8064-add-speedbin-efuse-nvmem-node.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 7f5aecdd4ffcc018f73171bc0e028cd4e3361acd Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 7 Jul 2022 03:09:43 +0200 -Subject: [PATCH 8/8] ARM: dts: qcom: ipq8064: add speedbin efuse nvmem node - -Add speedbin efuse nvmem cell needed for the opp table for the CPU -freqs. - -Signed-off-by: Christian Marangi -Tested-by: Jonathan McDowell -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220707010943.20857-10-ansuelsmth@gmail.com ---- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -854,6 +854,9 @@ - reg = <0x00700000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; -+ speedbin_efuse: speedbin@c0 { -+ reg = <0xc0 0x4>; -+ }; - tsens_calib: calib@400 { - reg = <0x400 0xb>; - }; diff --git a/target/linux/ipq806x/patches-5.15/105-v6.0-01-hwspinlock-qcom-Add-support-for-mmio-usage-to-sfpb-m.patch b/target/linux/ipq806x/patches-5.15/105-v6.0-01-hwspinlock-qcom-Add-support-for-mmio-usage-to-sfpb-m.patch deleted file mode 100644 index 2c6f6b10c48..00000000000 --- a/target/linux/ipq806x/patches-5.15/105-v6.0-01-hwspinlock-qcom-Add-support-for-mmio-usage-to-sfpb-m.patch +++ /dev/null @@ -1,71 +0,0 @@ -From cdab30b44518513003607ecfc8a22de3dbbb78ed Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 7 Jul 2022 12:20:38 +0200 -Subject: [PATCH 1/1] hwspinlock: qcom: Add support for mmio usage to - sfpb-mutex - -Allow sfpb-mutex to use mmio in addition to syscon. - -Signed-off-by: Christian Marangi -Reviewed-by: Bjorn Andersson -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220707102040.1859-1-ansuelsmth@gmail.com ---- - drivers/hwspinlock/qcom_hwspinlock.c | 28 +++++++++++++++++++++++----- - 1 file changed, 23 insertions(+), 5 deletions(-) - ---- a/drivers/hwspinlock/qcom_hwspinlock.c -+++ b/drivers/hwspinlock/qcom_hwspinlock.c -@@ -19,6 +19,11 @@ - #define QCOM_MUTEX_APPS_PROC_ID 1 - #define QCOM_MUTEX_NUM_LOCKS 32 - -+struct qcom_hwspinlock_of_data { -+ u32 offset; -+ u32 stride; -+}; -+ - static int qcom_hwspinlock_trylock(struct hwspinlock *lock) - { - struct regmap_field *field = lock->priv; -@@ -63,9 +68,20 @@ static const struct hwspinlock_ops qcom_ - .unlock = qcom_hwspinlock_unlock, - }; - -+static const struct qcom_hwspinlock_of_data of_sfpb_mutex = { -+ .offset = 0x4, -+ .stride = 0x4, -+}; -+ -+/* All modern platform has offset 0 and stride of 4k */ -+static const struct qcom_hwspinlock_of_data of_tcsr_mutex = { -+ .offset = 0, -+ .stride = 0x1000, -+}; -+ - static const struct of_device_id qcom_hwspinlock_of_match[] = { -- { .compatible = "qcom,sfpb-mutex" }, -- { .compatible = "qcom,tcsr-mutex" }, -+ { .compatible = "qcom,sfpb-mutex", .data = &of_sfpb_mutex }, -+ { .compatible = "qcom,tcsr-mutex", .data = &of_tcsr_mutex }, - { } - }; - MODULE_DEVICE_TABLE(of, qcom_hwspinlock_of_match); -@@ -112,12 +128,14 @@ static const struct regmap_config tcsr_m - static struct regmap *qcom_hwspinlock_probe_mmio(struct platform_device *pdev, - u32 *offset, u32 *stride) - { -+ const struct qcom_hwspinlock_of_data *data; - struct device *dev = &pdev->dev; - void __iomem *base; - -- /* All modern platform has offset 0 and stride of 4k */ -- *offset = 0; -- *stride = 0x1000; -+ data = of_device_get_match_data(dev); -+ -+ *offset = data->offset; -+ *stride = data->stride; - - base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) diff --git a/target/linux/ipq806x/patches-5.15/105-v6.0-02-ARM-dts-qcom-ipq8064-add-missing-hwlock.patch b/target/linux/ipq806x/patches-5.15/105-v6.0-02-ARM-dts-qcom-ipq8064-add-missing-hwlock.patch deleted file mode 100644 index d8303442f7e..00000000000 --- a/target/linux/ipq806x/patches-5.15/105-v6.0-02-ARM-dts-qcom-ipq8064-add-missing-hwlock.patch +++ /dev/null @@ -1,31 +0,0 @@ -From fbe4be367b2169602f6a5949a20d2917b25714d4 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 7 Jul 2022 12:20:39 +0200 -Subject: [PATCH 1/2] ARM: dts: qcom: ipq8064: add missing hwlock - -Add missing hwlock for ipq8064 dtsi provided by qcom,sfpb-mutex. - -Signed-off-by: Christian Marangi -Acked-by: Krzysztof Kozlowski -[bjorn: Moved the node inside /soc] -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220707102040.1859-2-ansuelsmth@gmail.com ---- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -1357,5 +1357,12 @@ - dma-names = "tx", "rx"; - }; - }; -+ -+ sfpb_mutex: hwlock@1200600 { -+ compatible = "qcom,sfpb-mutex"; -+ reg = <0x01200600 0x100>; -+ -+ #hwlock-cells = <1>; -+ }; - }; - }; diff --git a/target/linux/ipq806x/patches-5.15/105-v6.0-03-ARM-dts-qcom-ipq8064-add-missing-smem-compatible.patch b/target/linux/ipq806x/patches-5.15/105-v6.0-03-ARM-dts-qcom-ipq8064-add-missing-smem-compatible.patch deleted file mode 100644 index 8b91eeb5116..00000000000 --- a/target/linux/ipq806x/patches-5.15/105-v6.0-03-ARM-dts-qcom-ipq8064-add-missing-smem-compatible.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 4fefb5434c4b735daf913abaef12431405368031 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 7 Jul 2022 12:20:40 +0200 -Subject: [PATCH 2/2] ARM: dts: qcom: ipq8064: add missing smem compatible - -Add missing smem compatible and hwlocks phandle for ipq8064 dtsi -smem node. - -Signed-off-by: Christian Marangi -Acked-by: Krzysztof Kozlowski -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220707102040.1859-3-ansuelsmth@gmail.com ---- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -292,8 +292,11 @@ - }; - - smem: smem@41000000 { -+ compatible = "qcom,smem"; - reg = <0x41000000 0x200000>; - no-map; -+ -+ hwlocks = <&sfpb_mutex 3>; - }; - }; - diff --git a/target/linux/ipq806x/patches-5.15/106-v6.1-01-ARM-dts-qcom-ipq8064-add-v2-dtsi-variant.patch b/target/linux/ipq806x/patches-5.15/106-v6.1-01-ARM-dts-qcom-ipq8064-add-v2-dtsi-variant.patch deleted file mode 100644 index 8b20a550f6f..00000000000 --- a/target/linux/ipq806x/patches-5.15/106-v6.1-01-ARM-dts-qcom-ipq8064-add-v2-dtsi-variant.patch +++ /dev/null @@ -1,129 +0,0 @@ -From 9f7097a8b1948533a6db1b53b5c0480cc75bbd16 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Mon, 18 Jul 2022 18:05:16 +0200 -Subject: [PATCH 1/3] ARM: dts: qcom: ipq8064: add v2 dtsi variant - -Add ipq8064-v2.0 dtsi variant that differ from original ipq8064 SoC for -some additional pcie, sata and usb configuration values, additional -reserved memory and serial output. - -Signed-off-by: Christian Marangi ---- - .../boot/dts/qcom-ipq8064-v2.0-smb208.dtsi | 37 ++++++++++ - arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi | 69 +++++++++++++++++++ - 2 files changed, 106 insertions(+) - create mode 100644 arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi - create mode 100644 arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi - ---- /dev/null -+++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi -@@ -0,0 +1,37 @@ -+// SPDX-License-Identifier: GPL-2.0 -+ -+#include "qcom-ipq8064-v2.0.dtsi" -+ -+&rpm { -+ smb208_regulators: regulators { -+ compatible = "qcom,rpm-smb208-regulators"; -+ -+ smb208_s1a: s1a { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1150000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s1b: s1b { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1150000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s2a: s2a { -+ regulator-min-microvolt = < 800000>; -+ regulator-max-microvolt = <1250000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s2b: s2b { -+ regulator-min-microvolt = < 800000>; -+ regulator-max-microvolt = <1250000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi -@@ -0,0 +1,69 @@ -+// SPDX-License-Identifier: GPL-2.0 -+ -+#include "qcom-ipq8064.dtsi" -+ -+/ { -+ model = "Qualcomm Technologies, Inc. IPQ8064-v2.0"; -+ -+ aliases { -+ serial0 = &gsbi4_serial; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ reserved-memory { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ rsvd@41200000 { -+ reg = <0x41200000 0x300000>; -+ no-map; -+ }; -+ }; -+}; -+ -+&gsbi4 { -+ qcom,mode = ; -+ status = "okay"; -+ -+ serial@16340000 { -+ status = "okay"; -+ }; -+ /* -+ * The i2c device on gsbi4 should not be enabled. -+ * On ipq806x designs gsbi4 i2c is meant for exclusive -+ * RPM usage. Turning this on in kernel manifests as -+ * i2c failure for the RPM. -+ */ -+}; -+ -+&pcie0 { -+ compatible = "qcom,pcie-ipq8064-v2"; -+}; -+ -+&pcie1 { -+ compatible = "qcom,pcie-ipq8064-v2"; -+}; -+ -+&pcie2 { -+ compatible = "qcom,pcie-ipq8064-v2"; -+}; -+ -+&sata { -+ ports-implemented = <0x1>; -+}; -+ -+&ss_phy_0 { -+ qcom,rx-eq = <2>; -+ qcom,tx-deamp_3_5db = <32>; -+ qcom,mpll = <5>; -+}; -+ -+&ss_phy_1 { -+ qcom,rx-eq = <2>; -+ qcom,tx-deamp_3_5db = <32>; -+ qcom,mpll = <5>; -+}; diff --git a/target/linux/ipq806x/patches-5.15/106-v6.1-02-ARM-dts-qcom-ipq8064-add-ipq8062-variant.patch b/target/linux/ipq806x/patches-5.15/106-v6.1-02-ARM-dts-qcom-ipq8064-add-ipq8062-variant.patch deleted file mode 100644 index fdff292480e..00000000000 --- a/target/linux/ipq806x/patches-5.15/106-v6.1-02-ARM-dts-qcom-ipq8064-add-ipq8062-variant.patch +++ /dev/null @@ -1,67 +0,0 @@ -From 41d9fa8de7845bd92d9c963196fdfd7ea9232bb2 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Mon, 18 Jul 2022 18:07:26 +0200 -Subject: [PATCH 2/3] ARM: dts: qcom: ipq8064: add ipq8062 variant - -ipq8062 SoC is based on ipq8064-v2.0 with lower supported freq, lack of -usb port and a reduced voltage output with the smb208 regulators. - -Signed-off-by: Christian Marangi ---- - arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi | 37 ++++++++++++++++++++++ - arch/arm/boot/dts/qcom-ipq8062.dtsi | 8 +++++ - 2 files changed, 45 insertions(+) - create mode 100644 arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi - create mode 100644 arch/arm/boot/dts/qcom-ipq8062.dtsi - ---- /dev/null -+++ b/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi -@@ -0,0 +1,37 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+ -+#include "qcom-ipq8062.dtsi" -+ -+&rpm { -+ smb208_regulators: regulators { -+ compatible = "qcom,rpm-smb208-regulators"; -+ -+ smb208_s1a: s1a { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1150000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s1b: s1b { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1150000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s2a: s2a { -+ regulator-min-microvolt = < 800000>; -+ regulator-max-microvolt = <1150000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s2b: s2b { -+ regulator-min-microvolt = < 800000>; -+ regulator-max-microvolt = <1150000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/qcom-ipq8062.dtsi -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+ -+#include "qcom-ipq8064-v2.0.dtsi" -+ -+/ { -+ model = "Qualcomm Technologies, Inc. IPQ8062"; -+ compatible = "qcom,ipq8062", "qcom,ipq8064"; -+}; diff --git a/target/linux/ipq806x/patches-5.15/106-v6.1-03-ARM-dts-qcom-ipq8064-add-ipq8065-variant.patch b/target/linux/ipq806x/patches-5.15/106-v6.1-03-ARM-dts-qcom-ipq8064-add-ipq8065-variant.patch deleted file mode 100644 index bccc577b91c..00000000000 --- a/target/linux/ipq806x/patches-5.15/106-v6.1-03-ARM-dts-qcom-ipq8064-add-ipq8065-variant.patch +++ /dev/null @@ -1,67 +0,0 @@ -From 01e7aa3fe6f76f7960f2382038136235eee9c6cd Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Mon, 18 Jul 2022 18:09:35 +0200 -Subject: [PATCH 3/3] ARM: dts: qcom: ipq8064: add ipq8065 variant - -ipq8065 SoC is based on ipq8064-v2.0 with a more clocked CPU and -an increased voltage output with the smb208 regulators. - -Signed-off-by: Christian Marangi ---- - arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi | 37 ++++++++++++++++++++++ - arch/arm/boot/dts/qcom-ipq8065.dtsi | 8 +++++ - 2 files changed, 45 insertions(+) - create mode 100644 arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi - create mode 100644 arch/arm/boot/dts/qcom-ipq8065.dtsi - ---- /dev/null -+++ b/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi -@@ -0,0 +1,37 @@ -+// SPDX-License-Identifier: GPL-2.0 -+ -+#include "qcom-ipq8065.dtsi" -+ -+&rpm { -+ smb208_regulators: regulators { -+ compatible = "qcom,rpm-smb208-regulators"; -+ -+ smb208_s1a: s1a { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1150000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s1b: s1b { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1150000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s2a: s2a { -+ regulator-min-microvolt = <775000>; -+ regulator-max-microvolt = <1275000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s2b: s2b { -+ regulator-min-microvolt = <775000>; -+ regulator-max-microvolt = <1275000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/qcom-ipq8065.dtsi -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: GPL-2.0 -+ -+#include "qcom-ipq8064-v2.0.dtsi" -+ -+/ { -+ model = "Qualcomm Technologies, Inc. IPQ8065"; -+ compatible = "qcom,ipq8065", "qcom,ipq8064"; -+}; diff --git a/target/linux/ipq806x/patches-5.15/107-10-ARM-dts-qcom-add-saw-for-l2-cache-and-kraitcc-for.patch b/target/linux/ipq806x/patches-5.15/107-10-ARM-dts-qcom-add-saw-for-l2-cache-and-kraitcc-for.patch deleted file mode 100644 index 418d6b26ce7..00000000000 --- a/target/linux/ipq806x/patches-5.15/107-10-ARM-dts-qcom-add-saw-for-l2-cache-and-kraitcc-for.patch +++ /dev/null @@ -1,95 +0,0 @@ -From bef5018abb7cf94efafdc05087b4c998891ae4ec Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Mon, 17 Jan 2022 23:39:34 +0100 -Subject: [PATCH v3 10/18] ARM: dts: qcom: add saw for l2 cache and kraitcc for - ipq8064 - -Add saw compatible for l2 cache and kraitcc node for ipq8064 dtsi. -Also declare clock-output-names for acc0 and acc1 and qsb fixed clock -for the secondary mux. - -Signed-off-by: Ansuel Smith -Tested-by: Jonathan McDowell ---- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 34 +++++++++++++++++++++++++++-- - 1 file changed, 32 insertions(+), 2 deletions(-) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -301,6 +301,12 @@ - }; - - clocks { -+ qsb: qsb { -+ compatible = "fixed-clock"; -+ clock-frequency = <225000000>; -+ #clock-cells = <0>; -+ }; -+ - cxo_board: cxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; -@@ -503,11 +509,19 @@ - acc0: clock-controller@2088000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02088000 0x1000>, <0x02008000 0x1000>; -+ clock-output-names = "acpu0_aux"; -+ clocks = <&gcc PLL8_VOTE>, <&pxo_board>; -+ clock-names = "pll8_vote", "pxo"; -+ #clock-cells = <0>; - }; - - acc1: clock-controller@2098000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02098000 0x1000>, <0x02008000 0x1000>; -+ clock-output-names = "acpu1_aux"; -+ clocks = <&gcc PLL8_VOTE>, <&pxo_board>; -+ clock-names = "pll8_vote", "pxo"; -+ #clock-cells = <0>; - }; - - adm_dma: dma-controller@18300000 { -@@ -531,17 +545,23 @@ - }; - - saw0: regulator@2089000 { -- compatible = "qcom,saw2"; -+ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon"; - reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - saw1: regulator@2099000 { -- compatible = "qcom,saw2"; -+ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon"; - reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - -+ saw_l2: regulator@02012000 { -+ compatible = "qcom,saw2", "syscon"; -+ reg = <0x02012000 0x1000>; -+ regulator; -+ }; -+ - gsbi1: gsbi@12440000 { - compatible = "qcom,gsbi-v1.0.0"; - reg = <0x12440000 0x100>; -@@ -920,6 +940,17 @@ - clocks = <&gcc PLL8_VOTE>, <&pxo_board>; - clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu_l2_aux"; -+ #clock-cells = <0>; -+ }; -+ -+ kraitcc: clock-controller { -+ compatible = "qcom,krait-cc-v1"; -+ clocks = <&gcc PLL9>, <&gcc PLL10>, <&gcc PLL12>, -+ <&acc0>, <&acc1>, <&l2cc>, <&qsb>, <&pxo_board>; -+ clock-names = "hfpll0", "hfpll1", "hfpll_l2", -+ "acpu0_aux", "acpu1_aux", "acpu_l2_aux", -+ "qsb", "pxo"; -+ #clock-cells = <1>; - }; - - lcc: clock-controller@28000000 { diff --git a/target/linux/ipq806x/patches-5.15/107-13-ARM-dts-qcom-add-opp-table-for-cpu-and-l2-for-ipq.patch b/target/linux/ipq806x/patches-5.15/107-13-ARM-dts-qcom-add-opp-table-for-cpu-and-l2-for-ipq.patch deleted file mode 100644 index f3c8f18f1de..00000000000 --- a/target/linux/ipq806x/patches-5.15/107-13-ARM-dts-qcom-add-opp-table-for-cpu-and-l2-for-ipq.patch +++ /dev/null @@ -1,268 +0,0 @@ -From 076ebb6e1799c4c7a1d2e07510d88b9e9b57b551 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Tue, 18 Jan 2022 00:03:47 +0100 -Subject: [PATCH v3 13/18] ARM: dts: qcom: add opp table for cpu and l2 for - ipq8064 - -Add opp table for cpu and l2 cache. While the current cpufreq is -the generic one that doesn't scale the L2 cache, we add the l2 -cache opp anyway for the sake of completeness. This will be handy in the -future when a dedicated cpufreq driver is introduced for krait cores -that will correctly scale l2 cache with the core freq. - -Opp-level is set based on the logic of -0: idle level -1: normal level -2: turbo level - -Signed-off-by: Ansuel Smith -Tested-by: Jonathan McDowell ---- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 99 +++++++++++++++++++++++++++++ - 1 file changed, 99 insertions(+) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -48,6 +48,105 @@ - }; - }; - -+ opp_table_l2: opp_table_l2 { -+ compatible = "operating-points-v2"; -+ -+ opp-384000000 { -+ opp-hz = /bits/ 64 <384000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <100000>; -+ opp-level = <0>; -+ }; -+ -+ opp-1000000000 { -+ opp-hz = /bits/ 64 <1000000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <100000>; -+ opp-level = <1>; -+ }; -+ -+ opp-1200000000 { -+ opp-hz = /bits/ 64 <1200000000>; -+ opp-microvolt = <1150000>; -+ clock-latency-ns = <100000>; -+ opp-level = <2>; -+ }; -+ }; -+ -+ opp_table0: opp_table0 { -+ compatible = "operating-points-v2-kryo-cpu"; -+ nvmem-cells = <&speedbin_efuse>; -+ -+ /* -+ * Voltage thresholds are -+ */ -+ opp-384000000 { -+ opp-hz = /bits/ 64 <384000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>; -+ opp-microvolt-speed0-pvs1-v0 = <925000 878750 971250>; -+ opp-microvolt-speed0-pvs2-v0 = <875000 831250 918750>; -+ opp-microvolt-speed0-pvs3-v0 = <800000 760000 840000>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <0>; -+ }; -+ -+ opp-600000000 { -+ opp-hz = /bits/ 64 <600000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>; -+ opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>; -+ opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>; -+ opp-microvolt-speed0-pvs3-v0 = <850000 807500 892500>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <1>; -+ }; -+ -+ opp-800000000 { -+ opp-hz = /bits/ 64 <800000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>; -+ opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>; -+ opp-microvolt-speed0-pvs2-v0 = <995000 945250 1044750>; -+ opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <1>; -+ }; -+ -+ opp-1000000000 { -+ opp-hz = /bits/ 64 <1000000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>; -+ opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>; -+ opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>; -+ opp-microvolt-speed0-pvs3-v0 = <950000 902500 997500>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <1>; -+ }; -+ -+ opp-1200000000 { -+ opp-hz = /bits/ 64 <1200000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1200000 1140000 1260000>; -+ opp-microvolt-speed0-pvs1-v0 = <1125000 1068750 1181250>; -+ opp-microvolt-speed0-pvs2-v0 = <1075000 1021250 1128750>; -+ opp-microvolt-speed0-pvs3-v0 = <1000000 950000 1050000>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <2>; -+ }; -+ -+ opp-1400000000 { -+ opp-hz = /bits/ 64 <1400000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1250000 1187500 1312500>; -+ opp-microvolt-speed0-pvs1-v0 = <1175000 1116250 1233750>; -+ opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>; -+ opp-microvolt-speed0-pvs3-v0 = <1050000 997500 1102500>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <2>; -+ }; -+ }; -+ - thermal-zones { - tsens_tz_sensor0 { - polling-delay-passive = <0>; ---- a/arch/arm/boot/dts/qcom-ipq8065.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8065.dtsi -@@ -6,3 +6,92 @@ - model = "Qualcomm Technologies, Inc. IPQ8065"; - compatible = "qcom,ipq8065", "qcom,ipq8064"; - }; -+ -+&opp_table_l2 { -+ /delete-node/opp-1200000000; -+ -+ opp-1400000000 { -+ opp-hz = /bits/ 64 <1400000000>; -+ opp-microvolt = <1150000>; -+ clock-latency-ns = <100000>; -+ opp-level = <2>; -+ }; -+}; -+ -+&opp_table0 { -+ /* -+ * On ipq8065 1.2 ghz freq is not present -+ * Remove it to make cpufreq work and not -+ * complain for missing definition -+ */ -+ -+ /delete-node/opp-1200000000; -+ -+ /* -+ * Voltage thresholds are -+ */ -+ opp-384000000 { -+ opp-microvolt-speed0-pvs0-v0 = <975000 926250 1023750>; -+ opp-microvolt-speed0-pvs1-v0 = <950000 902500 997500>; -+ opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>; -+ opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>; -+ opp-microvolt-speed0-pvs4-v0 = <875000 831250 918750>; -+ opp-microvolt-speed0-pvs5-v0 = <825000 783750 866250>; -+ opp-microvolt-speed0-pvs6-v0 = <775000 736250 813750>; -+ }; -+ -+ opp-600000000 { -+ opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>; -+ opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>; -+ opp-microvolt-speed0-pvs2-v0 = <950000 902500 997500>; -+ opp-microvolt-speed0-pvs3-v0 = <925000 878750 971250>; -+ opp-microvolt-speed0-pvs4-v0 = <900000 855000 945000>; -+ opp-microvolt-speed0-pvs5-v0 = <850000 807500 892500>; -+ opp-microvolt-speed0-pvs6-v0 = <800000 760000 840000>; -+ }; -+ -+ opp-800000000 { -+ opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>; -+ opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>; -+ opp-microvolt-speed0-pvs2-v0 = <1000000 950000 1050000>; -+ opp-microvolt-speed0-pvs3-v0 = <975000 926250 1023750>; -+ opp-microvolt-speed0-pvs4-v0 = <950000 902500 997500>; -+ opp-microvolt-speed0-pvs5-v0 = <900000 855000 945000>; -+ opp-microvolt-speed0-pvs6-v0 = <850000 807500 892500>; -+ }; -+ -+ opp-1000000000 { -+ opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>; -+ opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>; -+ opp-microvolt-speed0-pvs2-v0 = <1050000 997500 1102500>; -+ opp-microvolt-speed0-pvs3-v0 = <1025000 973750 1076250>; -+ opp-microvolt-speed0-pvs4-v0 = <1000000 950000 1050000>; -+ opp-microvolt-speed0-pvs5-v0 = <950000 902500 997500>; -+ opp-microvolt-speed0-pvs6-v0 = <900000 855000 945000>; -+ }; -+ -+ opp-1400000000 { -+ opp-microvolt-speed0-pvs0-v0 = <1175000 1116250 1233750>; -+ opp-microvolt-speed0-pvs1-v0 = <1150000 1092500 1207500>; -+ opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>; -+ opp-microvolt-speed0-pvs3-v0 = <1100000 1045000 1155000>; -+ opp-microvolt-speed0-pvs4-v0 = <1075000 1021250 1128750>; -+ opp-microvolt-speed0-pvs5-v0 = <1025000 973750 1076250>; -+ opp-microvolt-speed0-pvs6-v0 = <975000 926250 1023750>; -+ opp-level = <1>; -+ }; -+ -+ opp-1725000000 { -+ opp-hz = /bits/ 64 <1725000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1262500 1199375 1325625>; -+ opp-microvolt-speed0-pvs1-v0 = <1225000 1163750 1286250>; -+ opp-microvolt-speed0-pvs2-v0 = <1200000 1140000 1260000>; -+ opp-microvolt-speed0-pvs3-v0 = <1175000 1116250 1233750>; -+ opp-microvolt-speed0-pvs4-v0 = <1150000 1092500 1207500>; -+ opp-microvolt-speed0-pvs5-v0 = <1100000 1045000 1155000>; -+ opp-microvolt-speed0-pvs6-v0 = <1050000 997500 1102500>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <2>; -+ }; -+}; ---- a/arch/arm/boot/dts/qcom-ipq8062.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8062.dtsi -@@ -6,3 +6,39 @@ - model = "Qualcomm Technologies, Inc. IPQ8062"; - compatible = "qcom,ipq8062", "qcom,ipq8064"; - }; -+ -+&opp_table0 { -+ /delete-node/opp-1200000000; -+ /delete-node/opp-1400000000; -+ -+ /* -+ * Voltage thresholds are -+ */ -+ opp-384000000 { -+ opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>; -+ opp-microvolt-speed0-pvs1-v0 = < 925000 878750 971250>; -+ opp-microvolt-speed0-pvs2-v0 = < 875000 831250 918750>; -+ opp-microvolt-speed0-pvs3-v0 = < 800000 760000 840000>; -+ }; -+ -+ opp-600000000 { -+ opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>; -+ opp-microvolt-speed0-pvs1-v0 = < 975000 926250 1023750>; -+ opp-microvolt-speed0-pvs2-v0 = < 925000 878750 971250>; -+ opp-microvolt-speed0-pvs3-v0 = < 850000 807500 892500>; -+ }; -+ -+ opp-800000000 { -+ opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>; -+ opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>; -+ opp-microvolt-speed0-pvs2-v0 = < 995000 945250 1044750>; -+ opp-microvolt-speed0-pvs3-v0 = < 900000 855000 945000>; -+ }; -+ -+ opp-1000000000 { -+ opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>; -+ opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>; -+ opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>; -+ opp-microvolt-speed0-pvs3-v0 = < 950000 902500 997500>; -+ }; -+}; diff --git a/target/linux/ipq806x/patches-5.15/107-15-ARM-dts-qcom-add-multiple-missing-binding-for-cpu.patch b/target/linux/ipq806x/patches-5.15/107-15-ARM-dts-qcom-add-multiple-missing-binding-for-cpu.patch deleted file mode 100644 index cf27aaa08b6..00000000000 --- a/target/linux/ipq806x/patches-5.15/107-15-ARM-dts-qcom-add-multiple-missing-binding-for-cpu.patch +++ /dev/null @@ -1,153 +0,0 @@ -From 211fc0c0a63c99b68663a27182e643316c2d8cbe Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Tue, 18 Jan 2022 00:07:57 +0100 -Subject: [PATCH v3 15/18] ARM: dts: qcom: add multiple missing binding for cpu - and l2 for ipq8064 - -Add multiple binding for cpu node, l2 node and add idle-states -definition for ipq8064 dtsi. - -Signed-off-by: Ansuel Smith -Tested-by: Jonathan McDowell ---- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 36 +++++++++++++++++++++++++++++ - 1 file changed, 36 insertions(+) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -30,6 +30,15 @@ - next-level-cache = <&L2>; - qcom,acc = <&acc0>; - qcom,saw = <&saw0>; -+ clocks = <&kraitcc 0>, <&kraitcc 4>; -+ clock-names = "cpu", "l2"; -+ clock-latency = <100000>; -+ operating-points-v2 = <&opp_table0>; -+ voltage-tolerance = <5>; -+ cooling-min-state = <0>; -+ cooling-max-state = <10>; -+ #cooling-cells = <2>; -+ cpu-idle-states = <&CPU_SPC>; - }; - - cpu1: cpu@1 { -@@ -40,11 +49,35 @@ - next-level-cache = <&L2>; - qcom,acc = <&acc1>; - qcom,saw = <&saw1>; -+ clocks = <&kraitcc 1>, <&kraitcc 4>; -+ clock-names = "cpu", "l2"; -+ clock-latency = <100000>; -+ operating-points-v2 = <&opp_table0>; -+ voltage-tolerance = <5>; -+ cooling-min-state = <0>; -+ cooling-max-state = <10>; -+ #cooling-cells = <2>; -+ cpu-idle-states = <&CPU_SPC>; -+ }; -+ -+ idle-states { -+ CPU_SPC: spc { -+ compatible = "qcom,idle-state-spc"; -+ status = "disabled"; -+ entry-latency-us = <400>; -+ exit-latency-us = <900>; -+ min-residency-us = <3000>; -+ }; - }; - - L2: l2-cache { - compatible = "cache"; - cache-level = <2>; -+ qcom,saw = <&saw_l2>; -+ -+ clocks = <&kraitcc 4>; -+ clock-names = "l2"; -+ operating-points-v2 = <&opp_table_l2>; - }; - }; - ---- a/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi -@@ -2,6 +2,18 @@ - - #include "qcom-ipq8064.dtsi" - -+&cpu0 { -+ cpu-supply = <&smb208_s2a>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&smb208_s2b>; -+}; -+ -+&L2 { -+ l2-supply = <&smb208_s1a>; -+}; -+ - &rpm { - smb208_regulators: regulators { - compatible = "qcom,rpm-smb208-regulators"; ---- a/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi -@@ -2,6 +2,18 @@ - - #include "qcom-ipq8064-v2.0.dtsi" - -+&cpu0 { -+ cpu-supply = <&smb208_s2a>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&smb208_s2b>; -+}; -+ -+&L2 { -+ l2-supply = <&smb208_s1a>; -+}; -+ - &rpm { - smb208_regulators: regulators { - compatible = "qcom,rpm-smb208-regulators"; ---- a/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi -@@ -2,6 +2,18 @@ - - #include "qcom-ipq8062.dtsi" - -+&cpu0 { -+ cpu-supply = <&smb208_s2a>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&smb208_s2b>; -+}; -+ -+&L2 { -+ l2-supply = <&smb208_s1a>; -+}; -+ - &rpm { - smb208_regulators: regulators { - compatible = "qcom,rpm-smb208-regulators"; ---- a/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi -@@ -2,6 +2,18 @@ - - #include "qcom-ipq8065.dtsi" - -+&cpu0 { -+ cpu-supply = <&smb208_s2a>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&smb208_s2b>; -+}; -+ -+&L2 { -+ l2-supply = <&smb208_s1a>; -+}; -+ - &rpm { - smb208_regulators: regulators { - compatible = "qcom,rpm-smb208-regulators"; diff --git a/target/linux/ipq806x/patches-5.15/108-01-ARM-dts-qcom-fix-wrong-nad_pins-definition-for-ipq80.patch b/target/linux/ipq806x/patches-5.15/108-01-ARM-dts-qcom-fix-wrong-nad_pins-definition-for-ipq80.patch deleted file mode 100644 index d3f821a6a0f..00000000000 --- a/target/linux/ipq806x/patches-5.15/108-01-ARM-dts-qcom-fix-wrong-nad_pins-definition-for-ipq80.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 6c94e0184e56f9e9f1f5d5f54b20758433e498d2 Mon Sep 17 00:00:00 2001 -From: Christian 'Ansuel' Marangi -Date: Wed, 15 Jun 2022 16:47:09 +0200 -Subject: [PATCH 1/2] ARM: dts: qcom: fix wrong nad_pins definition for ipq806x - -Fix wrong nand_pings definition for bias-disable pins. - -Signed-off-by: Christian 'Ansuel' Marangi ---- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 7 ++----- - 1 file changed, 2 insertions(+), 5 deletions(-) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -559,12 +559,9 @@ - }; - - nand_pins: nand_pins { -- mux { -+ disable { - pins = "gpio34", "gpio35", "gpio36", -- "gpio37", "gpio38", "gpio39", -- "gpio40", "gpio41", "gpio42", -- "gpio43", "gpio44", "gpio45", -- "gpio46", "gpio47"; -+ "gpio37", "gpio38"; - function = "nand"; - drive-strength = <10>; - bias-disable; diff --git a/target/linux/ipq806x/patches-5.15/108-02-ARM-dts-qcom-add-MDIO-dedicated-controller-node-for-.patch b/target/linux/ipq806x/patches-5.15/108-02-ARM-dts-qcom-add-MDIO-dedicated-controller-node-for-.patch deleted file mode 100644 index 4a57fc0330b..00000000000 --- a/target/linux/ipq806x/patches-5.15/108-02-ARM-dts-qcom-add-MDIO-dedicated-controller-node-for-.patch +++ /dev/null @@ -1,188 +0,0 @@ -From 504188183408fac0f61b59f5ed8ea1773fe43669 Mon Sep 17 00:00:00 2001 -From: Christian 'Ansuel' Marangi -Date: Wed, 15 Jun 2022 16:59:30 +0200 -Subject: [PATCH 2/2] ARM: dts: qcom: add MDIO dedicated controller node for - ipq806x - -Add MDIO dedicated controller attached to gmac0 and fix rb3011 dts to -correctly use the new tag. - -Signed-off-by: Christian 'Ansuel' Marangi ---- - arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 134 +++++++++++----------- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 14 +++ - 2 files changed, 81 insertions(+), 67 deletions(-) - ---- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts -+++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts -@@ -24,73 +24,6 @@ - device_type = "memory"; - }; - -- mdio0: mdio-0 { -- status = "okay"; -- compatible = "virtual,mdio-gpio"; -- gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>, -- <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>; -- #address-cells = <1>; -- #size-cells = <0>; -- -- pinctrl-0 = <&mdio0_pins>; -- pinctrl-names = "default"; -- -- switch0: switch@10 { -- compatible = "qca,qca8337"; -- #address-cells = <1>; -- #size-cells = <0>; -- -- dsa,member = <0 0>; -- -- pinctrl-0 = <&sw0_reset_pin>; -- pinctrl-names = "default"; -- -- reset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>; -- reg = <0x10>; -- -- ports { -- #address-cells = <1>; -- #size-cells = <0>; -- -- switch0cpu: port@0 { -- reg = <0>; -- label = "cpu"; -- ethernet = <&gmac0>; -- phy-mode = "rgmii-id"; -- fixed-link { -- speed = <1000>; -- full-duplex; -- }; -- }; -- -- port@1 { -- reg = <1>; -- label = "sw1"; -- }; -- -- port@2 { -- reg = <2>; -- label = "sw2"; -- }; -- -- port@3 { -- reg = <3>; -- label = "sw3"; -- }; -- -- port@4 { -- reg = <4>; -- label = "sw4"; -- }; -- -- port@5 { -- reg = <5>; -- label = "sw5"; -- }; -- }; -- }; -- }; -- - mdio1: mdio-1 { - status = "okay"; - compatible = "virtual,mdio-gpio"; -@@ -220,6 +153,73 @@ - status = "okay"; - }; - -+&mdio0 { -+ status = "okay"; -+ compatible = "virtual,mdio-gpio"; -+ gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>, -+ <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ pinctrl-0 = <&mdio0_pins>; -+ pinctrl-names = "default"; -+ -+ switch0: switch@10 { -+ compatible = "qca,qca8337"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ dsa,member = <0 0>; -+ -+ pinctrl-0 = <&sw0_reset_pin>; -+ pinctrl-names = "default"; -+ -+ reset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>; -+ reg = <0x10>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ switch0cpu: port@0 { -+ reg = <0>; -+ label = "cpu"; -+ ethernet = <&gmac0>; -+ phy-mode = "rgmii-id"; -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "sw1"; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "sw2"; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "sw3"; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "sw4"; -+ }; -+ -+ port@5 { -+ reg = <5>; -+ label = "sw5"; -+ }; -+ }; -+ }; -+}; -+ - &gmac0 { - status = "okay"; - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -1446,6 +1446,20 @@ - }; - }; - -+ mdio0: mdio@37000000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ compatible = "qcom,ipq8064-mdio", "syscon"; -+ reg = <0x37000000 0x200000>; -+ resets = <&gcc GMAC_CORE1_RESET>; -+ reset-names = "stmmaceth"; -+ clocks = <&gcc GMAC_CORE1_CLK>; -+ clock-names = "stmmaceth"; -+ -+ status = "disabled"; -+ }; -+ - vsdcc_fixed: vsdcc-regulator { - compatible = "regulator-fixed"; - regulator-name = "SDCC Power"; diff --git a/target/linux/ipq806x/patches-5.15/109-v6.1-01-dt-bindings-clock-add-pcm-reset-for-ipq806x-lcc.patch b/target/linux/ipq806x/patches-5.15/109-v6.1-01-dt-bindings-clock-add-pcm-reset-for-ipq806x-lcc.patch deleted file mode 100644 index 72e70b613c8..00000000000 --- a/target/linux/ipq806x/patches-5.15/109-v6.1-01-dt-bindings-clock-add-pcm-reset-for-ipq806x-lcc.patch +++ /dev/null @@ -1,29 +0,0 @@ -From fc7dc1d0c10e8e3d72b68ddae8a61c8aa02a62c1 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Wed, 15 Jun 2022 17:13:32 +0200 -Subject: [PATCH v4 1/3] dt-bindings: clock: add pcm reset for ipq806x lcc - -Add pcm reset define for ipq806x lcc. - -Signed-off-by: Christian Marangi -Reviewed-by: Dmitry Baryshkov -Acked-by: Rob Herring ---- -v3: - - Added review tag - - Added ack tag -v2: - - Fix Sob tag - - include/dt-bindings/clock/qcom,lcc-ipq806x.h | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/include/dt-bindings/clock/qcom,lcc-ipq806x.h -+++ b/include/dt-bindings/clock/qcom,lcc-ipq806x.h -@@ -19,4 +19,6 @@ - #define SPDIF_CLK 10 - #define AHBIX_CLK 11 - -+#define LCC_PCM_RESET 0 -+ - #endif diff --git a/target/linux/ipq806x/patches-5.15/109-v6.1-02-clk-qcom-lcc-ipq806x-add-reset-definition.patch b/target/linux/ipq806x/patches-5.15/109-v6.1-02-clk-qcom-lcc-ipq806x-add-reset-definition.patch deleted file mode 100644 index 23936513064..00000000000 --- a/target/linux/ipq806x/patches-5.15/109-v6.1-02-clk-qcom-lcc-ipq806x-add-reset-definition.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 3587d768bdf4683a53244be1acca5d095044671f Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Wed, 15 Jun 2022 17:19:55 +0200 -Subject: [PATCH v4 2/3] clk: qcom: lcc-ipq806x: add reset definition - -Add reset definition for lcc-ipq806x. - -Signed-off-by: Christian Marangi -Reviewed-by: Dmitry Baryshkov ---- -v3: - - Added review tag -v2: - - Fix Sob tag - - drivers/clk/qcom/lcc-ipq806x.c | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/drivers/clk/qcom/lcc-ipq806x.c -+++ b/drivers/clk/qcom/lcc-ipq806x.c -@@ -22,6 +22,7 @@ - #include "clk-branch.h" - #include "clk-regmap-divider.h" - #include "clk-regmap-mux.h" -+#include "reset.h" - - static struct clk_pll pll4 = { - .l_reg = 0x4, -@@ -405,6 +406,10 @@ static struct clk_regmap *lcc_ipq806x_cl - [AHBIX_CLK] = &ahbix_clk.clkr, - }; - -+static const struct qcom_reset_map lcc_ipq806x_resets[] = { -+ [LCC_PCM_RESET] = { 0x54, 13 }, -+}; -+ - static const struct regmap_config lcc_ipq806x_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, -@@ -417,6 +422,8 @@ static const struct qcom_cc_desc lcc_ipq - .config = &lcc_ipq806x_regmap_config, - .clks = lcc_ipq806x_clks, - .num_clks = ARRAY_SIZE(lcc_ipq806x_clks), -+ .resets = lcc_ipq806x_resets, -+ .num_resets = ARRAY_SIZE(lcc_ipq806x_resets), - }; - - static const struct of_device_id lcc_ipq806x_match_table[] = { diff --git a/target/linux/ipq806x/patches-5.15/109-v6.1-03-clk-qcom-lcc-ipq806x-convert-to-parent-data.patch b/target/linux/ipq806x/patches-5.15/109-v6.1-03-clk-qcom-lcc-ipq806x-convert-to-parent-data.patch deleted file mode 100644 index 905dc5bf40b..00000000000 --- a/target/linux/ipq806x/patches-5.15/109-v6.1-03-clk-qcom-lcc-ipq806x-convert-to-parent-data.patch +++ /dev/null @@ -1,217 +0,0 @@ -From 92ef900a4a53b62e0dc32554eb088a422657606c Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Wed, 15 Jun 2022 17:35:13 +0200 -Subject: [PATCH v5 3/3] clk: qcom: lcc-ipq806x: convert to parent data - -Convert lcc-ipq806x driver to parent_data API. - -Signed-off-by: Christian Marangi ---- -v5: -- Fix the same compilation error (don't know what the hell happen - to my buildroot) -v4: -- Fix compilation error -v3: - - Inline pxo pll4 parent - - Change .name from pxo to pxo_board - - drivers/clk/qcom/lcc-ipq806x.c | 77 ++++++++++++++++++---------------- - 1 file changed, 42 insertions(+), 35 deletions(-) - ---- a/drivers/clk/qcom/lcc-ipq806x.c -+++ b/drivers/clk/qcom/lcc-ipq806x.c -@@ -34,7 +34,9 @@ static struct clk_pll pll4 = { - .status_bit = 16, - .clkr.hw.init = &(struct clk_init_data){ - .name = "pll4", -- .parent_names = (const char *[]){ "pxo" }, -+ .parent_data = &(const struct clk_parent_data) { -+ .fw_name = "pxo", .name = "pxo_board", -+ }, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -@@ -64,9 +66,9 @@ static const struct parent_map lcc_pxo_p - { P_PLL4, 2 } - }; - --static const char * const lcc_pxo_pll4[] = { -- "pxo", -- "pll4_vote", -+static const struct clk_parent_data lcc_pxo_pll4[] = { -+ { .fw_name = "pxo", .name = "pxo" }, -+ { .fw_name = "pll4_vote", .name = "pll4_vote" }, - }; - - static struct freq_tbl clk_tbl_aif_mi2s[] = { -@@ -131,18 +133,14 @@ static struct clk_rcg mi2s_osr_src = { - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "mi2s_osr_src", -- .parent_names = lcc_pxo_pll4, -- .num_parents = 2, -+ .parent_data = lcc_pxo_pll4, -+ .num_parents = ARRAY_SIZE(lcc_pxo_pll4), - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, - }, - }, - }; - --static const char * const lcc_mi2s_parents[] = { -- "mi2s_osr_src", --}; -- - static struct clk_branch mi2s_osr_clk = { - .halt_reg = 0x50, - .halt_bit = 1, -@@ -152,7 +150,9 @@ static struct clk_branch mi2s_osr_clk = - .enable_mask = BIT(17), - .hw.init = &(struct clk_init_data){ - .name = "mi2s_osr_clk", -- .parent_names = lcc_mi2s_parents, -+ .parent_hws = (const struct clk_hw*[]){ -+ &mi2s_osr_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -167,7 +167,9 @@ static struct clk_regmap_div mi2s_div_cl - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "mi2s_div_clk", -- .parent_names = lcc_mi2s_parents, -+ .parent_hws = (const struct clk_hw*[]){ -+ &mi2s_osr_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_regmap_div_ops, - }, -@@ -183,7 +185,9 @@ static struct clk_branch mi2s_bit_div_cl - .enable_mask = BIT(15), - .hw.init = &(struct clk_init_data){ - .name = "mi2s_bit_div_clk", -- .parent_names = (const char *[]){ "mi2s_div_clk" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &mi2s_div_clk.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -191,6 +195,10 @@ static struct clk_branch mi2s_bit_div_cl - }, - }; - -+static const struct clk_parent_data lcc_mi2s_bit_div_codec_clk[] = { -+ { .hw = &mi2s_bit_div_clk.clkr.hw, }, -+ { .fw_name = "mi2s_codec_clk", .name = "mi2s_codec_clk" }, -+}; - - static struct clk_regmap_mux mi2s_bit_clk = { - .reg = 0x48, -@@ -199,11 +207,8 @@ static struct clk_regmap_mux mi2s_bit_cl - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "mi2s_bit_clk", -- .parent_names = (const char *[]){ -- "mi2s_bit_div_clk", -- "mi2s_codec_clk", -- }, -- .num_parents = 2, -+ .parent_data = lcc_mi2s_bit_div_codec_clk, -+ .num_parents = ARRAY_SIZE(lcc_mi2s_bit_div_codec_clk), - .ops = &clk_regmap_mux_closest_ops, - .flags = CLK_SET_RATE_PARENT, - }, -@@ -245,8 +250,8 @@ static struct clk_rcg pcm_src = { - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "pcm_src", -- .parent_names = lcc_pxo_pll4, -- .num_parents = 2, -+ .parent_data = lcc_pxo_pll4, -+ .num_parents = ARRAY_SIZE(lcc_pxo_pll4), - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, - }, -@@ -262,7 +267,9 @@ static struct clk_branch pcm_clk_out = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "pcm_clk_out", -- .parent_names = (const char *[]){ "pcm_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &pcm_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -270,6 +277,11 @@ static struct clk_branch pcm_clk_out = { - }, - }; - -+static const struct clk_parent_data lcc_pcm_clk_out_codec_clk[] = { -+ { .hw = &pcm_clk_out.clkr.hw, }, -+ { .fw_name = "pcm_codec_clk", .name = "pcm_codec_clk" }, -+}; -+ - static struct clk_regmap_mux pcm_clk = { - .reg = 0x54, - .shift = 10, -@@ -277,11 +289,8 @@ static struct clk_regmap_mux pcm_clk = { - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "pcm_clk", -- .parent_names = (const char *[]){ -- "pcm_clk_out", -- "pcm_codec_clk", -- }, -- .num_parents = 2, -+ .parent_data = lcc_pcm_clk_out_codec_clk, -+ .num_parents = ARRAY_SIZE(lcc_pcm_clk_out_codec_clk), - .ops = &clk_regmap_mux_closest_ops, - .flags = CLK_SET_RATE_PARENT, - }, -@@ -325,18 +334,14 @@ static struct clk_rcg spdif_src = { - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "spdif_src", -- .parent_names = lcc_pxo_pll4, -- .num_parents = 2, -+ .parent_data = lcc_pxo_pll4, -+ .num_parents = ARRAY_SIZE(lcc_pxo_pll4), - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, - }, - }, - }; - --static const char * const lcc_spdif_parents[] = { -- "spdif_src", --}; -- - static struct clk_branch spdif_clk = { - .halt_reg = 0xd4, - .halt_bit = 1, -@@ -346,7 +351,9 @@ static struct clk_branch spdif_clk = { - .enable_mask = BIT(12), - .hw.init = &(struct clk_init_data){ - .name = "spdif_clk", -- .parent_names = lcc_spdif_parents, -+ .parent_hws = (const struct clk_hw*[]){ -+ &spdif_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -384,8 +391,8 @@ static struct clk_rcg ahbix_clk = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "ahbix", -- .parent_names = lcc_pxo_pll4, -- .num_parents = 2, -+ .parent_data = lcc_pxo_pll4, -+ .num_parents = ARRAY_SIZE(lcc_pxo_pll4), - .ops = &clk_rcg_lcc_ops, - }, - }, diff --git a/target/linux/ipq806x/patches-5.15/110-01-thermal-qcom-tsens-init-debugfs-only-with-successful.patch b/target/linux/ipq806x/patches-5.15/110-01-thermal-qcom-tsens-init-debugfs-only-with-successful.patch deleted file mode 100644 index 4caa2a9560e..00000000000 --- a/target/linux/ipq806x/patches-5.15/110-01-thermal-qcom-tsens-init-debugfs-only-with-successful.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 8f32d48a309246a80bdca505968085a484d54408 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Mon, 19 Apr 2021 03:01:53 +0200 -Subject: [thermal-next PATCH v2 1/2] thermal: qcom: tsens: init debugfs only with - successful probe - -calibrate and tsens_register can fail or PROBE_DEFER. This will cause a -double or a wrong init of the debugfs information. Init debugfs only -with successful probe fixing warning about directory already present. - -Signed-off-by: Ansuel Smith -Acked-by: Thara Gopinath ---- - drivers/thermal/qcom/tsens.c | 9 ++++++--- - 1 file changed, 6 insertions(+), 3 deletions(-) - ---- a/drivers/thermal/qcom/tsens.c -+++ b/drivers/thermal/qcom/tsens.c -@@ -917,8 +917,6 @@ int __init init_common(struct tsens_priv - if (tsens_version(priv) >= VER_0_1) - tsens_enable_irq(priv); - -- tsens_debug_init(op); -- - err_put_device: - put_device(&op->dev); - return ret; -@@ -1163,7 +1161,12 @@ static int tsens_probe(struct platform_d - } - } - -- return tsens_register(priv); -+ ret = tsens_register(priv); -+ -+ if (!ret) -+ tsens_debug_init(pdev); -+ -+ return ret; - } - - static int tsens_remove(struct platform_device *pdev) diff --git a/target/linux/ipq806x/patches-5.15/110-02-thermal-qcom-tsens-simplify-debugfs-init-function.patch b/target/linux/ipq806x/patches-5.15/110-02-thermal-qcom-tsens-simplify-debugfs-init-function.patch deleted file mode 100644 index add2ab45987..00000000000 --- a/target/linux/ipq806x/patches-5.15/110-02-thermal-qcom-tsens-simplify-debugfs-init-function.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 4204f22060f7a5d42c6ccb4d4c25a6a875571099 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Mon, 19 Apr 2021 03:08:37 +0200 -Subject: [thermal-next PATCH v2 2/2] thermal: qcom: tsens: simplify debugfs init - function - -Simplify debugfs init function. -- Add check for existing dev directory. -- Fix wrong version in dbg_version_show (with version 0.0.0, 0.1.0 was - incorrectly reported) - -Signed-off-by: Ansuel Smith -Reviewed-by: Thara Gopinath ---- - drivers/thermal/qcom/tsens.c | 16 +++++++--------- - 1 file changed, 7 insertions(+), 9 deletions(-) - ---- a/drivers/thermal/qcom/tsens.c -+++ b/drivers/thermal/qcom/tsens.c -@@ -691,7 +691,7 @@ static int dbg_version_show(struct seq_f - return ret; - seq_printf(s, "%d.%d.%d\n", maj_ver, min_ver, step_ver); - } else { -- seq_puts(s, "0.1.0\n"); -+ seq_printf(s, "0.%d.0\n", priv->feat->ver_major); - } - - return 0; -@@ -703,21 +703,17 @@ DEFINE_SHOW_ATTRIBUTE(dbg_sensors); - static void tsens_debug_init(struct platform_device *pdev) - { - struct tsens_priv *priv = platform_get_drvdata(pdev); -- struct dentry *root, *file; - -- root = debugfs_lookup("tsens", NULL); -- if (!root) -+ priv->debug_root = debugfs_lookup("tsens", NULL); -+ if (!priv->debug_root) - priv->debug_root = debugfs_create_dir("tsens", NULL); -- else -- priv->debug_root = root; - -- file = debugfs_lookup("version", priv->debug_root); -- if (!file) -+ if (!debugfs_lookup("version", priv->debug_root)) - debugfs_create_file("version", 0444, priv->debug_root, - pdev, &dbg_version_fops); - - /* A directory for each instance of the TSENS IP */ -- priv->debug = debugfs_create_dir(dev_name(&pdev->dev), priv->debug_root); -+ priv->debug = debugfs_lookup(dev_name(&pdev->dev), priv->debug_root); - debugfs_create_file("sensors", 0444, priv->debug, pdev, &dbg_sensors_fops); - } - #else diff --git a/target/linux/ipq806x/patches-5.15/111-v5.19-01-PM-devfreq-Export-devfreq_get_freq_range-symbol-with.patch b/target/linux/ipq806x/patches-5.15/111-v5.19-01-PM-devfreq-Export-devfreq_get_freq_range-symbol-with.patch deleted file mode 100644 index 6b7a68952ea..00000000000 --- a/target/linux/ipq806x/patches-5.15/111-v5.19-01-PM-devfreq-Export-devfreq_get_freq_range-symbol-with.patch +++ /dev/null @@ -1,113 +0,0 @@ -From 713472e53e6e53c985e283782b0fd76b8ecfd47e Mon Sep 17 00:00:00 2001 -From: Chanwoo Choi -Date: Mon, 1 Mar 2021 02:07:29 +0900 -Subject: [PATCH 1/5] PM / devfreq: Export devfreq_get_freq_range symbol within - devfreq - -In order to get frequency range within devfreq governors, -export devfreq_get_freq_range symbol within devfreq. - -Reviewed-by: Matthias Kaehlcke -Tested-by: Chen-Yu Tsai -Tested-by: Johnson Wang -Signed-off-by: Chanwoo Choi ---- - drivers/devfreq/devfreq.c | 20 ++++++++++++-------- - drivers/devfreq/governor.h | 2 ++ - 2 files changed, 14 insertions(+), 8 deletions(-) - ---- a/drivers/devfreq/devfreq.c -+++ b/drivers/devfreq/devfreq.c -@@ -112,16 +112,16 @@ static unsigned long find_available_max_ - } - - /** -- * get_freq_range() - Get the current freq range -+ * devfreq_get_freq_range() - Get the current freq range - * @devfreq: the devfreq instance - * @min_freq: the min frequency - * @max_freq: the max frequency - * - * This takes into consideration all constraints. - */ --static void get_freq_range(struct devfreq *devfreq, -- unsigned long *min_freq, -- unsigned long *max_freq) -+void devfreq_get_freq_range(struct devfreq *devfreq, -+ unsigned long *min_freq, -+ unsigned long *max_freq) - { - unsigned long *freq_table = devfreq->profile->freq_table; - s32 qos_min_freq, qos_max_freq; -@@ -158,6 +158,7 @@ static void get_freq_range(struct devfre - if (*min_freq > *max_freq) - *min_freq = *max_freq; - } -+EXPORT_SYMBOL(devfreq_get_freq_range); - - /** - * devfreq_get_freq_level() - Lookup freq_table for the frequency -@@ -418,7 +419,7 @@ int devfreq_update_target(struct devfreq - err = devfreq->governor->get_target_freq(devfreq, &freq); - if (err) - return err; -- get_freq_range(devfreq, &min_freq, &max_freq); -+ devfreq_get_freq_range(devfreq, &min_freq, &max_freq); - - if (freq < min_freq) { - freq = min_freq; -@@ -784,6 +785,7 @@ struct devfreq *devfreq_add_device(struc - { - struct devfreq *devfreq; - struct devfreq_governor *governor; -+ unsigned long min_freq, max_freq; - int err = 0; - - if (!dev || !profile || !governor_name) { -@@ -848,6 +850,8 @@ struct devfreq *devfreq_add_device(struc - goto err_dev; - } - -+ devfreq_get_freq_range(devfreq, &min_freq, &max_freq); -+ - devfreq->suspend_freq = dev_pm_opp_get_suspend_opp_freq(dev); - devfreq->opp_table = dev_pm_opp_get_opp_table(dev); - if (IS_ERR(devfreq->opp_table)) -@@ -1559,7 +1563,7 @@ static ssize_t min_freq_show(struct devi - unsigned long min_freq, max_freq; - - mutex_lock(&df->lock); -- get_freq_range(df, &min_freq, &max_freq); -+ devfreq_get_freq_range(df, &min_freq, &max_freq); - mutex_unlock(&df->lock); - - return sprintf(buf, "%lu\n", min_freq); -@@ -1613,7 +1617,7 @@ static ssize_t max_freq_show(struct devi - unsigned long min_freq, max_freq; - - mutex_lock(&df->lock); -- get_freq_range(df, &min_freq, &max_freq); -+ devfreq_get_freq_range(df, &min_freq, &max_freq); - mutex_unlock(&df->lock); - - return sprintf(buf, "%lu\n", max_freq); -@@ -1927,7 +1931,7 @@ static int devfreq_summary_show(struct s - - mutex_lock(&devfreq->lock); - cur_freq = devfreq->previous_freq; -- get_freq_range(devfreq, &min_freq, &max_freq); -+ devfreq_get_freq_range(devfreq, &min_freq, &max_freq); - timer = devfreq->profile->timer; - - if (IS_SUPPORTED_ATTR(devfreq->governor->attrs, POLLING_INTERVAL)) ---- a/drivers/devfreq/governor.h -+++ b/drivers/devfreq/governor.h -@@ -86,6 +86,8 @@ int devfreq_remove_governor(struct devfr - - int devfreq_update_status(struct devfreq *devfreq, unsigned long freq); - int devfreq_update_target(struct devfreq *devfreq, unsigned long freq); -+void devfreq_get_freq_range(struct devfreq *devfreq, unsigned long *min_freq, -+ unsigned long *max_freq); - - static inline int devfreq_update_stats(struct devfreq *df) - { diff --git a/target/linux/ipq806x/patches-5.15/111-v5.19-02-PM-devfreq-Add-cpu-based-scaling-support-to-passive-.patch b/target/linux/ipq806x/patches-5.15/111-v5.19-02-PM-devfreq-Add-cpu-based-scaling-support-to-passive-.patch deleted file mode 100644 index 3dd61985b28..00000000000 --- a/target/linux/ipq806x/patches-5.15/111-v5.19-02-PM-devfreq-Add-cpu-based-scaling-support-to-passive-.patch +++ /dev/null @@ -1,461 +0,0 @@ -From a03dacb0316f74400846aaf144d6c73f4217ca08 Mon Sep 17 00:00:00 2001 -From: Saravana Kannan -Date: Tue, 2 Mar 2021 15:58:21 +0900 -Subject: [PATCH 2/5] PM / devfreq: Add cpu based scaling support to passive - governor - -Many CPU architectures have caches that can scale independent of the -CPUs. Frequency scaling of the caches is necessary to make sure that the -cache is not a performance bottleneck that leads to poor performance and -power. The same idea applies for RAM/DDR. - -To achieve this, this patch adds support for cpu based scaling to the -passive governor. This is accomplished by taking the current frequency -of each CPU frequency domain and then adjust the frequency of the cache -(or any devfreq device) based on the frequency of the CPUs. It listens -to CPU frequency transition notifiers to keep itself up to date on the -current CPU frequency. - -To decide the frequency of the device, the governor does one of the -following: -* Derives the optimal devfreq device opp from required-opps property of - the parent cpu opp_table. - -* Scales the device frequency in proportion to the CPU frequency. So, if - the CPUs are running at their max frequency, the device runs at its - max frequency. If the CPUs are running at their min frequency, the - device runs at its min frequency. It is interpolated for frequencies - in between. - -Tested-by: Chen-Yu Tsai -Tested-by: Johnson Wang -Signed-off-by: Saravana Kannan -[Sibi: Integrated cpu-freqmap governor into passive_governor] -Signed-off-by: Sibi Sankar -[Chanwoo: Fix conflict with latest code and cleanup code] -Signed-off-by: Chanwoo Choi ---- - drivers/devfreq/governor.h | 22 +++ - drivers/devfreq/governor_passive.c | 298 +++++++++++++++++++++++++++-- - include/linux/devfreq.h | 17 +- - 3 files changed, 323 insertions(+), 14 deletions(-) - ---- a/drivers/devfreq/governor.h -+++ b/drivers/devfreq/governor.h -@@ -48,6 +48,28 @@ - #define DEVFREQ_GOV_ATTR_TIMER BIT(1) - - /** -+ * struct devfreq_cpu_data - Hold the per-cpu data -+ * @dev: reference to cpu device. -+ * @first_cpu: the cpumask of the first cpu of a policy. -+ * @opp_table: reference to cpu opp table. -+ * @cur_freq: the current frequency of the cpu. -+ * @min_freq: the min frequency of the cpu. -+ * @max_freq: the max frequency of the cpu. -+ * -+ * This structure stores the required cpu_data of a cpu. -+ * This is auto-populated by the governor. -+ */ -+struct devfreq_cpu_data { -+ struct device *dev; -+ unsigned int first_cpu; -+ -+ struct opp_table *opp_table; -+ unsigned int cur_freq; -+ unsigned int min_freq; -+ unsigned int max_freq; -+}; -+ -+/** - * struct devfreq_governor - Devfreq policy governor - * @node: list node - contains registered devfreq governors - * @name: Governor's name ---- a/drivers/devfreq/governor_passive.c -+++ b/drivers/devfreq/governor_passive.c -@@ -8,11 +8,85 @@ - */ - - #include -+#include -+#include -+#include -+#include - #include - #include - #include "governor.h" - --static int devfreq_passive_get_target_freq(struct devfreq *devfreq, -+#define HZ_PER_KHZ 1000 -+ -+static unsigned long get_target_freq_by_required_opp(struct device *p_dev, -+ struct opp_table *p_opp_table, -+ struct opp_table *opp_table, -+ unsigned long *freq) -+{ -+ struct dev_pm_opp *opp = NULL, *p_opp = NULL; -+ unsigned long target_freq; -+ -+ if (!p_dev || !p_opp_table || !opp_table || !freq) -+ return 0; -+ -+ p_opp = devfreq_recommended_opp(p_dev, freq, 0); -+ if (IS_ERR(p_opp)) -+ return 0; -+ -+ opp = dev_pm_opp_xlate_required_opp(p_opp_table, opp_table, p_opp); -+ dev_pm_opp_put(p_opp); -+ -+ if (IS_ERR(opp)) -+ return 0; -+ -+ target_freq = dev_pm_opp_get_freq(opp); -+ dev_pm_opp_put(opp); -+ -+ return target_freq; -+} -+ -+static int get_target_freq_with_cpufreq(struct devfreq *devfreq, -+ unsigned long *target_freq) -+{ -+ struct devfreq_passive_data *p_data = -+ (struct devfreq_passive_data *)devfreq->data; -+ struct devfreq_cpu_data *parent_cpu_data; -+ unsigned long cpu, cpu_cur, cpu_min, cpu_max, cpu_percent; -+ unsigned long dev_min, dev_max; -+ unsigned long freq = 0; -+ -+ for_each_online_cpu(cpu) { -+ parent_cpu_data = p_data->parent_cpu_data[cpu]; -+ if (!parent_cpu_data || parent_cpu_data->first_cpu != cpu) -+ continue; -+ -+ /* Get target freq via required opps */ -+ cpu_cur = parent_cpu_data->cur_freq * HZ_PER_KHZ; -+ freq = get_target_freq_by_required_opp(parent_cpu_data->dev, -+ parent_cpu_data->opp_table, -+ devfreq->opp_table, &cpu_cur); -+ if (freq) { -+ *target_freq = max(freq, *target_freq); -+ continue; -+ } -+ -+ /* Use interpolation if required opps is not available */ -+ devfreq_get_freq_range(devfreq, &dev_min, &dev_max); -+ -+ cpu_min = parent_cpu_data->min_freq; -+ cpu_max = parent_cpu_data->max_freq; -+ cpu_cur = parent_cpu_data->cur_freq; -+ -+ cpu_percent = ((cpu_cur - cpu_min) * 100) / (cpu_max - cpu_min); -+ freq = dev_min + mult_frac(dev_max - dev_min, cpu_percent, 100); -+ -+ *target_freq = max(freq, *target_freq); -+ } -+ -+ return 0; -+} -+ -+static int get_target_freq_with_devfreq(struct devfreq *devfreq, - unsigned long *freq) - { - struct devfreq_passive_data *p_data -@@ -99,6 +173,181 @@ no_required_opp: - return 0; - } - -+static int devfreq_passive_get_target_freq(struct devfreq *devfreq, -+ unsigned long *freq) -+{ -+ struct devfreq_passive_data *p_data = -+ (struct devfreq_passive_data *)devfreq->data; -+ int ret; -+ -+ if (!p_data) -+ return -EINVAL; -+ -+ /* -+ * If the devfreq device with passive governor has the specific method -+ * to determine the next frequency, should use the get_target_freq() -+ * of struct devfreq_passive_data. -+ */ -+ if (p_data->get_target_freq) -+ return p_data->get_target_freq(devfreq, freq); -+ -+ switch (p_data->parent_type) { -+ case DEVFREQ_PARENT_DEV: -+ ret = get_target_freq_with_devfreq(devfreq, freq); -+ break; -+ case CPUFREQ_PARENT_DEV: -+ ret = get_target_freq_with_cpufreq(devfreq, freq); -+ break; -+ default: -+ ret = -EINVAL; -+ dev_err(&devfreq->dev, "Invalid parent type\n"); -+ break; -+ } -+ -+ return ret; -+} -+ -+static int cpufreq_passive_notifier_call(struct notifier_block *nb, -+ unsigned long event, void *ptr) -+{ -+ struct devfreq_passive_data *p_data = -+ container_of(nb, struct devfreq_passive_data, nb); -+ struct devfreq *devfreq = (struct devfreq *)p_data->this; -+ struct devfreq_cpu_data *parent_cpu_data; -+ struct cpufreq_freqs *freqs = ptr; -+ unsigned int cur_freq; -+ int ret; -+ -+ if (event != CPUFREQ_POSTCHANGE || !freqs || -+ !p_data->parent_cpu_data[freqs->policy->cpu]) -+ return 0; -+ -+ parent_cpu_data = p_data->parent_cpu_data[freqs->policy->cpu]; -+ if (parent_cpu_data->cur_freq == freqs->new) -+ return 0; -+ -+ cur_freq = parent_cpu_data->cur_freq; -+ parent_cpu_data->cur_freq = freqs->new; -+ -+ mutex_lock(&devfreq->lock); -+ ret = devfreq_update_target(devfreq, freqs->new); -+ mutex_unlock(&devfreq->lock); -+ if (ret) { -+ parent_cpu_data->cur_freq = cur_freq; -+ dev_err(&devfreq->dev, "failed to update the frequency.\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int cpufreq_passive_unregister_notifier(struct devfreq *devfreq) -+{ -+ struct devfreq_passive_data *p_data -+ = (struct devfreq_passive_data *)devfreq->data; -+ struct devfreq_cpu_data *parent_cpu_data; -+ int cpu, ret; -+ -+ if (p_data->nb.notifier_call) { -+ ret = cpufreq_unregister_notifier(&p_data->nb, -+ CPUFREQ_TRANSITION_NOTIFIER); -+ if (ret < 0) -+ return ret; -+ } -+ -+ for_each_possible_cpu(cpu) { -+ parent_cpu_data = p_data->parent_cpu_data[cpu]; -+ if (!parent_cpu_data) -+ continue; -+ -+ if (parent_cpu_data->opp_table) -+ dev_pm_opp_put_opp_table(parent_cpu_data->opp_table); -+ kfree(parent_cpu_data); -+ } -+ -+ return 0; -+} -+ -+static int cpufreq_passive_register_notifier(struct devfreq *devfreq) -+{ -+ struct devfreq_passive_data *p_data -+ = (struct devfreq_passive_data *)devfreq->data; -+ struct device *dev = devfreq->dev.parent; -+ struct opp_table *opp_table = NULL; -+ struct devfreq_cpu_data *parent_cpu_data; -+ struct cpufreq_policy *policy; -+ struct device *cpu_dev; -+ unsigned int cpu; -+ int ret; -+ -+ p_data->nb.notifier_call = cpufreq_passive_notifier_call; -+ ret = cpufreq_register_notifier(&p_data->nb, CPUFREQ_TRANSITION_NOTIFIER); -+ if (ret) { -+ dev_err(dev, "failed to register cpufreq notifier\n"); -+ p_data->nb.notifier_call = NULL; -+ goto err; -+ } -+ -+ for_each_possible_cpu(cpu) { -+ if (p_data->parent_cpu_data[cpu]) -+ continue; -+ -+ policy = cpufreq_cpu_get(cpu); -+ if (!policy) { -+ ret = -EPROBE_DEFER; -+ goto err; -+ } -+ -+ parent_cpu_data = kzalloc(sizeof(*parent_cpu_data), -+ GFP_KERNEL); -+ if (!parent_cpu_data) { -+ ret = -ENOMEM; -+ goto err_put_policy; -+ } -+ -+ cpu_dev = get_cpu_device(cpu); -+ if (!cpu_dev) { -+ dev_err(dev, "failed to get cpu device\n"); -+ ret = -ENODEV; -+ goto err_free_cpu_data; -+ } -+ -+ opp_table = dev_pm_opp_get_opp_table(cpu_dev); -+ if (IS_ERR(opp_table)) { -+ dev_err(dev, "failed to get opp_table of cpu%d\n", cpu); -+ ret = PTR_ERR(opp_table); -+ goto err_free_cpu_data; -+ } -+ -+ parent_cpu_data->dev = cpu_dev; -+ parent_cpu_data->opp_table = opp_table; -+ parent_cpu_data->first_cpu = cpumask_first(policy->related_cpus); -+ parent_cpu_data->cur_freq = policy->cur; -+ parent_cpu_data->min_freq = policy->cpuinfo.min_freq; -+ parent_cpu_data->max_freq = policy->cpuinfo.max_freq; -+ -+ p_data->parent_cpu_data[cpu] = parent_cpu_data; -+ cpufreq_cpu_put(policy); -+ } -+ -+ mutex_lock(&devfreq->lock); -+ ret = devfreq_update_target(devfreq, 0L); -+ mutex_unlock(&devfreq->lock); -+ if (ret) -+ dev_err(dev, "failed to update the frequency\n"); -+ -+ return ret; -+ -+err_free_cpu_data: -+ kfree(parent_cpu_data); -+err_put_policy: -+ cpufreq_cpu_put(policy); -+err: -+ WARN_ON(cpufreq_passive_unregister_notifier(devfreq)); -+ -+ return ret; -+} -+ - static int devfreq_passive_notifier_call(struct notifier_block *nb, - unsigned long event, void *ptr) - { -@@ -131,30 +380,55 @@ static int devfreq_passive_notifier_call - return NOTIFY_DONE; - } - --static int devfreq_passive_event_handler(struct devfreq *devfreq, -- unsigned int event, void *data) -+static int devfreq_passive_unregister_notifier(struct devfreq *devfreq) -+{ -+ struct devfreq_passive_data *p_data -+ = (struct devfreq_passive_data *)devfreq->data; -+ struct devfreq *parent = (struct devfreq *)p_data->parent; -+ struct notifier_block *nb = &p_data->nb; -+ -+ return devfreq_unregister_notifier(parent, nb, DEVFREQ_TRANSITION_NOTIFIER); -+} -+ -+static int devfreq_passive_register_notifier(struct devfreq *devfreq) - { - struct devfreq_passive_data *p_data - = (struct devfreq_passive_data *)devfreq->data; - struct devfreq *parent = (struct devfreq *)p_data->parent; - struct notifier_block *nb = &p_data->nb; -- int ret = 0; - - if (!parent) - return -EPROBE_DEFER; - -+ nb->notifier_call = devfreq_passive_notifier_call; -+ return devfreq_register_notifier(parent, nb, DEVFREQ_TRANSITION_NOTIFIER); -+} -+ -+static int devfreq_passive_event_handler(struct devfreq *devfreq, -+ unsigned int event, void *data) -+{ -+ struct devfreq_passive_data *p_data -+ = (struct devfreq_passive_data *)devfreq->data; -+ int ret = -EINVAL; -+ -+ if (!p_data) -+ return -EINVAL; -+ -+ if (!p_data->this) -+ p_data->this = devfreq; -+ - switch (event) { - case DEVFREQ_GOV_START: -- if (!p_data->this) -- p_data->this = devfreq; -- -- nb->notifier_call = devfreq_passive_notifier_call; -- ret = devfreq_register_notifier(parent, nb, -- DEVFREQ_TRANSITION_NOTIFIER); -+ if (p_data->parent_type == DEVFREQ_PARENT_DEV) -+ ret = devfreq_passive_register_notifier(devfreq); -+ else if (p_data->parent_type == CPUFREQ_PARENT_DEV) -+ ret = cpufreq_passive_register_notifier(devfreq); - break; - case DEVFREQ_GOV_STOP: -- WARN_ON(devfreq_unregister_notifier(parent, nb, -- DEVFREQ_TRANSITION_NOTIFIER)); -+ if (p_data->parent_type == DEVFREQ_PARENT_DEV) -+ WARN_ON(devfreq_passive_unregister_notifier(devfreq)); -+ else if (p_data->parent_type == CPUFREQ_PARENT_DEV) -+ WARN_ON(cpufreq_passive_unregister_notifier(devfreq)); - break; - default: - break; ---- a/include/linux/devfreq.h -+++ b/include/linux/devfreq.h -@@ -38,6 +38,7 @@ enum devfreq_timer { - - struct devfreq; - struct devfreq_governor; -+struct devfreq_cpu_data; - struct thermal_cooling_device; - - /** -@@ -289,6 +290,11 @@ struct devfreq_simple_ondemand_data { - #endif - - #if IS_ENABLED(CONFIG_DEVFREQ_GOV_PASSIVE) -+enum devfreq_parent_dev_type { -+ DEVFREQ_PARENT_DEV, -+ CPUFREQ_PARENT_DEV, -+}; -+ - /** - * struct devfreq_passive_data - ``void *data`` fed to struct devfreq - * and devfreq_add_device -@@ -300,8 +306,11 @@ struct devfreq_simple_ondemand_data { - * using governors except for passive governor. - * If the devfreq device has the specific method to decide - * the next frequency, should use this callback. -- * @this: the devfreq instance of own device. -- * @nb: the notifier block for DEVFREQ_TRANSITION_NOTIFIER list -+ * @parent_type: the parent type of the device. -+ * @this: the devfreq instance of own device. -+ * @nb: the notifier block for DEVFREQ_TRANSITION_NOTIFIER or -+ * CPUFREQ_TRANSITION_NOTIFIER list. -+ * @parent_cpu_data: the state min/max/current frequency of all online cpu's. - * - * The devfreq_passive_data have to set the devfreq instance of parent - * device with governors except for the passive governor. But, don't need to -@@ -315,9 +324,13 @@ struct devfreq_passive_data { - /* Optional callback to decide the next frequency of passvice device */ - int (*get_target_freq)(struct devfreq *this, unsigned long *freq); - -+ /* Should set the type of parent device */ -+ enum devfreq_parent_dev_type parent_type; -+ - /* For passive governor's internal use. Don't need to set them */ - struct devfreq *this; - struct notifier_block nb; -+ struct devfreq_cpu_data *parent_cpu_data[NR_CPUS]; - }; - #endif - diff --git a/target/linux/ipq806x/patches-5.15/111-v5.19-03-PM-devfreq-passive-Reduce-duplicate-code-when-passiv.patch b/target/linux/ipq806x/patches-5.15/111-v5.19-03-PM-devfreq-passive-Reduce-duplicate-code-when-passiv.patch deleted file mode 100644 index cb10bd1b62c..00000000000 --- a/target/linux/ipq806x/patches-5.15/111-v5.19-03-PM-devfreq-passive-Reduce-duplicate-code-when-passiv.patch +++ /dev/null @@ -1,110 +0,0 @@ -From 05723e71234b60a1a47313ea1a889797ec648f1c Mon Sep 17 00:00:00 2001 -From: Chanwoo Choi -Date: Tue, 2 Mar 2021 17:22:50 +0900 -Subject: [PATCH 3/5] PM / devfreq: passive: Reduce duplicate code when - passive_devfreq case - -In order to keep the consistent coding style between passive_devfreq -and passive_cpufreq, use common code for handling required opp property. -Also remove the unneed conditional statement and unify the comment -of both passive_devfreq and passive_cpufreq when getting the target frequency. - -Tested-by: Chen-Yu Tsai -Tested-by: Johnson Wang -Signed-off-by: Chanwoo Choi ---- - drivers/devfreq/governor_passive.c | 66 ++++-------------------------- - 1 file changed, 8 insertions(+), 58 deletions(-) - ---- a/drivers/devfreq/governor_passive.c -+++ b/drivers/devfreq/governor_passive.c -@@ -93,65 +93,16 @@ static int get_target_freq_with_devfreq( - = (struct devfreq_passive_data *)devfreq->data; - struct devfreq *parent_devfreq = (struct devfreq *)p_data->parent; - unsigned long child_freq = ULONG_MAX; -- struct dev_pm_opp *opp, *p_opp; - int i, count; - -- /* -- * If the devfreq device with passive governor has the specific method -- * to determine the next frequency, should use the get_target_freq() -- * of struct devfreq_passive_data. -- */ -- if (p_data->get_target_freq) -- return p_data->get_target_freq(devfreq, freq); -- -- /* -- * If the parent and passive devfreq device uses the OPP table, -- * get the next frequency by using the OPP table. -- */ -- -- /* -- * - parent devfreq device uses the governors except for passive. -- * - passive devfreq device uses the passive governor. -- * -- * Each devfreq has the OPP table. After deciding the new frequency -- * from the governor of parent devfreq device, the passive governor -- * need to get the index of new frequency on OPP table of parent -- * device. And then the index is used for getting the suitable -- * new frequency for passive devfreq device. -- */ -- if (!devfreq->profile || !devfreq->profile->freq_table -- || devfreq->profile->max_state <= 0) -- return -EINVAL; -- -- /* -- * The passive governor have to get the correct frequency from OPP -- * list of parent device. Because in this case, *freq is temporary -- * value which is decided by ondemand governor. -- */ -- if (devfreq->opp_table && parent_devfreq->opp_table) { -- p_opp = devfreq_recommended_opp(parent_devfreq->dev.parent, -- freq, 0); -- if (IS_ERR(p_opp)) -- return PTR_ERR(p_opp); -- -- opp = dev_pm_opp_xlate_required_opp(parent_devfreq->opp_table, -- devfreq->opp_table, p_opp); -- dev_pm_opp_put(p_opp); -- -- if (IS_ERR(opp)) -- goto no_required_opp; -- -- *freq = dev_pm_opp_get_freq(opp); -- dev_pm_opp_put(opp); -- -- return 0; -- } -+ /* Get target freq via required opps */ -+ child_freq = get_target_freq_by_required_opp(parent_devfreq->dev.parent, -+ parent_devfreq->opp_table, -+ devfreq->opp_table, freq); -+ if (child_freq) -+ goto out; - --no_required_opp: -- /* -- * Get the OPP table's index of decided frequency by governor -- * of parent device. -- */ -+ /* Use interpolation if required opps is not available */ - for (i = 0; i < parent_devfreq->profile->max_state; i++) - if (parent_devfreq->profile->freq_table[i] == *freq) - break; -@@ -159,7 +110,6 @@ no_required_opp: - if (i == parent_devfreq->profile->max_state) - return -EINVAL; - -- /* Get the suitable frequency by using index of parent device. */ - if (i < devfreq->profile->max_state) { - child_freq = devfreq->profile->freq_table[i]; - } else { -@@ -167,7 +117,7 @@ no_required_opp: - child_freq = devfreq->profile->freq_table[count - 1]; - } - -- /* Return the suitable frequency for passive device. */ -+out: - *freq = child_freq; - - return 0; diff --git a/target/linux/ipq806x/patches-5.15/111-v5.19-04-PM-devfreq-passive-Keep-cpufreq_policy-for-possible-.patch b/target/linux/ipq806x/patches-5.15/111-v5.19-04-PM-devfreq-passive-Keep-cpufreq_policy-for-possible-.patch deleted file mode 100644 index 9ef02d0ea35..00000000000 --- a/target/linux/ipq806x/patches-5.15/111-v5.19-04-PM-devfreq-passive-Keep-cpufreq_policy-for-possible-.patch +++ /dev/null @@ -1,232 +0,0 @@ -From 26984d9d581e5049bd75091d2e789b9cc3ea12e0 Mon Sep 17 00:00:00 2001 -From: Chanwoo Choi -Date: Wed, 27 Apr 2022 03:49:19 +0900 -Subject: [PATCH 4/5] PM / devfreq: passive: Keep cpufreq_policy for possible - cpus - -The passive governor requires the cpu data to get the next target frequency -of devfreq device if depending on cpu. In order to reduce the unnecessary -memory data, keep cpufreq_policy data for possible cpus instead of NR_CPU. - -Tested-by: Chen-Yu Tsai -Tested-by: Johnson Wang -Signed-off-by: Chanwoo Choi ---- - drivers/devfreq/governor.h | 3 ++ - drivers/devfreq/governor_passive.c | 75 +++++++++++++++++++++++------- - include/linux/devfreq.h | 4 +- - 3 files changed, 64 insertions(+), 18 deletions(-) - ---- a/drivers/devfreq/governor.h -+++ b/drivers/devfreq/governor.h -@@ -49,6 +49,7 @@ - - /** - * struct devfreq_cpu_data - Hold the per-cpu data -+ * @node: list node - * @dev: reference to cpu device. - * @first_cpu: the cpumask of the first cpu of a policy. - * @opp_table: reference to cpu opp table. -@@ -60,6 +61,8 @@ - * This is auto-populated by the governor. - */ - struct devfreq_cpu_data { -+ struct list_head node; -+ - struct device *dev; - unsigned int first_cpu; - ---- a/drivers/devfreq/governor_passive.c -+++ b/drivers/devfreq/governor_passive.c -@@ -1,4 +1,4 @@ --// SPDX-License-Identifier: GPL-2.0-only -+ // SPDX-License-Identifier: GPL-2.0-only - /* - * linux/drivers/devfreq/governor_passive.c - * -@@ -18,6 +18,22 @@ - - #define HZ_PER_KHZ 1000 - -+static struct devfreq_cpu_data * -+get_parent_cpu_data(struct devfreq_passive_data *p_data, -+ struct cpufreq_policy *policy) -+{ -+ struct devfreq_cpu_data *parent_cpu_data; -+ -+ if (!p_data || !policy) -+ return NULL; -+ -+ list_for_each_entry(parent_cpu_data, &p_data->cpu_data_list, node) -+ if (parent_cpu_data->first_cpu == cpumask_first(policy->related_cpus)) -+ return parent_cpu_data; -+ -+ return NULL; -+} -+ - static unsigned long get_target_freq_by_required_opp(struct device *p_dev, - struct opp_table *p_opp_table, - struct opp_table *opp_table, -@@ -51,14 +67,24 @@ static int get_target_freq_with_cpufreq( - struct devfreq_passive_data *p_data = - (struct devfreq_passive_data *)devfreq->data; - struct devfreq_cpu_data *parent_cpu_data; -+ struct cpufreq_policy *policy; - unsigned long cpu, cpu_cur, cpu_min, cpu_max, cpu_percent; - unsigned long dev_min, dev_max; - unsigned long freq = 0; -+ int ret = 0; - - for_each_online_cpu(cpu) { -- parent_cpu_data = p_data->parent_cpu_data[cpu]; -- if (!parent_cpu_data || parent_cpu_data->first_cpu != cpu) -+ policy = cpufreq_cpu_get(cpu); -+ if (!policy) { -+ ret = -EINVAL; -+ continue; -+ } -+ -+ parent_cpu_data = get_parent_cpu_data(p_data, policy); -+ if (!parent_cpu_data) { -+ cpufreq_cpu_put(policy); - continue; -+ } - - /* Get target freq via required opps */ - cpu_cur = parent_cpu_data->cur_freq * HZ_PER_KHZ; -@@ -67,6 +93,7 @@ static int get_target_freq_with_cpufreq( - devfreq->opp_table, &cpu_cur); - if (freq) { - *target_freq = max(freq, *target_freq); -+ cpufreq_cpu_put(policy); - continue; - } - -@@ -81,9 +108,10 @@ static int get_target_freq_with_cpufreq( - freq = dev_min + mult_frac(dev_max - dev_min, cpu_percent, 100); - - *target_freq = max(freq, *target_freq); -+ cpufreq_cpu_put(policy); - } - -- return 0; -+ return ret; - } - - static int get_target_freq_with_devfreq(struct devfreq *devfreq, -@@ -168,12 +196,11 @@ static int cpufreq_passive_notifier_call - unsigned int cur_freq; - int ret; - -- if (event != CPUFREQ_POSTCHANGE || !freqs || -- !p_data->parent_cpu_data[freqs->policy->cpu]) -+ if (event != CPUFREQ_POSTCHANGE || !freqs) - return 0; - -- parent_cpu_data = p_data->parent_cpu_data[freqs->policy->cpu]; -- if (parent_cpu_data->cur_freq == freqs->new) -+ parent_cpu_data = get_parent_cpu_data(p_data, freqs->policy); -+ if (!parent_cpu_data || parent_cpu_data->cur_freq == freqs->new) - return 0; - - cur_freq = parent_cpu_data->cur_freq; -@@ -196,7 +223,7 @@ static int cpufreq_passive_unregister_no - struct devfreq_passive_data *p_data - = (struct devfreq_passive_data *)devfreq->data; - struct devfreq_cpu_data *parent_cpu_data; -- int cpu, ret; -+ int cpu, ret = 0; - - if (p_data->nb.notifier_call) { - ret = cpufreq_unregister_notifier(&p_data->nb, -@@ -206,16 +233,26 @@ static int cpufreq_passive_unregister_no - } - - for_each_possible_cpu(cpu) { -- parent_cpu_data = p_data->parent_cpu_data[cpu]; -- if (!parent_cpu_data) -+ struct cpufreq_policy *policy = cpufreq_cpu_get(cpu); -+ if (!policy) { -+ ret = -EINVAL; -+ continue; -+ } -+ -+ parent_cpu_data = get_parent_cpu_data(p_data, policy); -+ if (!parent_cpu_data) { -+ cpufreq_cpu_put(policy); - continue; -+ } - -+ list_del(&parent_cpu_data->node); - if (parent_cpu_data->opp_table) - dev_pm_opp_put_opp_table(parent_cpu_data->opp_table); - kfree(parent_cpu_data); -+ cpufreq_cpu_put(policy); - } - -- return 0; -+ return ret; - } - - static int cpufreq_passive_register_notifier(struct devfreq *devfreq) -@@ -230,6 +267,9 @@ static int cpufreq_passive_register_noti - unsigned int cpu; - int ret; - -+ p_data->cpu_data_list -+ = (struct list_head)LIST_HEAD_INIT(p_data->cpu_data_list); -+ - p_data->nb.notifier_call = cpufreq_passive_notifier_call; - ret = cpufreq_register_notifier(&p_data->nb, CPUFREQ_TRANSITION_NOTIFIER); - if (ret) { -@@ -239,15 +279,18 @@ static int cpufreq_passive_register_noti - } - - for_each_possible_cpu(cpu) { -- if (p_data->parent_cpu_data[cpu]) -- continue; -- - policy = cpufreq_cpu_get(cpu); - if (!policy) { - ret = -EPROBE_DEFER; - goto err; - } - -+ parent_cpu_data = get_parent_cpu_data(p_data, policy); -+ if (parent_cpu_data) { -+ cpufreq_cpu_put(policy); -+ continue; -+ } -+ - parent_cpu_data = kzalloc(sizeof(*parent_cpu_data), - GFP_KERNEL); - if (!parent_cpu_data) { -@@ -276,7 +319,7 @@ static int cpufreq_passive_register_noti - parent_cpu_data->min_freq = policy->cpuinfo.min_freq; - parent_cpu_data->max_freq = policy->cpuinfo.max_freq; - -- p_data->parent_cpu_data[cpu] = parent_cpu_data; -+ list_add_tail(&parent_cpu_data->node, &p_data->cpu_data_list); - cpufreq_cpu_put(policy); - } - ---- a/include/linux/devfreq.h -+++ b/include/linux/devfreq.h -@@ -310,7 +310,7 @@ enum devfreq_parent_dev_type { - * @this: the devfreq instance of own device. - * @nb: the notifier block for DEVFREQ_TRANSITION_NOTIFIER or - * CPUFREQ_TRANSITION_NOTIFIER list. -- * @parent_cpu_data: the state min/max/current frequency of all online cpu's. -+ * @cpu_data_list: the list of cpu frequency data for all cpufreq_policy. - * - * The devfreq_passive_data have to set the devfreq instance of parent - * device with governors except for the passive governor. But, don't need to -@@ -330,7 +330,7 @@ struct devfreq_passive_data { - /* For passive governor's internal use. Don't need to set them */ - struct devfreq *this; - struct notifier_block nb; -- struct devfreq_cpu_data *parent_cpu_data[NR_CPUS]; -+ struct list_head cpu_data_list; - }; - #endif - diff --git a/target/linux/ipq806x/patches-5.15/111-v5.19-05-PM-devfreq-passive-Return-non-error-when-not-support.patch b/target/linux/ipq806x/patches-5.15/111-v5.19-05-PM-devfreq-passive-Return-non-error-when-not-support.patch deleted file mode 100644 index 69160fd77a5..00000000000 --- a/target/linux/ipq806x/patches-5.15/111-v5.19-05-PM-devfreq-passive-Return-non-error-when-not-support.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 42d2607d91c4ec37ea1970899c2d614824f3014b Mon Sep 17 00:00:00 2001 -From: Chanwoo Choi -Date: Thu, 19 May 2022 10:07:53 +0900 -Subject: [PATCH 5/5] PM / devfreq: passive: Return non-error when - not-supported event is required - -Each devfreq governor specifies the supported governor event -such as GOV_START and GOV_STOP. When not-supported event is required, -just return non-error. But, commit ce9a0d88d97a ("PM / devfreq: Add -cpu based scaling support to passive governor") returned the error -value. So that return non-error value when not-supported event is required. - -Fixes: ce9a0d88d97a ("PM / devfreq: Add cpu based scaling support to passive governor") -Reported-by: Marek Szyprowski -Signed-off-by: Chanwoo Choi -Signed-off-by: Rafael J. Wysocki ---- - drivers/devfreq/governor_passive.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/devfreq/governor_passive.c -+++ b/drivers/devfreq/governor_passive.c -@@ -402,7 +402,7 @@ static int devfreq_passive_event_handler - { - struct devfreq_passive_data *p_data - = (struct devfreq_passive_data *)devfreq->data; -- int ret = -EINVAL; -+ int ret = 0; - - if (!p_data) - return -EINVAL; diff --git a/target/linux/ipq806x/patches-5.15/112-v5.19-PM-devfreq-Fix-kernel-warning-with-cpufreq-passive-r.patch b/target/linux/ipq806x/patches-5.15/112-v5.19-PM-devfreq-Fix-kernel-warning-with-cpufreq-passive-r.patch deleted file mode 100644 index 3d2bb2de05b..00000000000 --- a/target/linux/ipq806x/patches-5.15/112-v5.19-PM-devfreq-Fix-kernel-warning-with-cpufreq-passive-r.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 82c66d2bbbeda9e493487e7413769087a0b46250 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Mon, 20 Jun 2022 00:29:39 +0200 -Subject: [PATCH 1/1] PM / devfreq: Fix kernel warning with cpufreq passive - register fail - -Remove cpufreq_passive_unregister_notifier from -cpufreq_passive_register_notifier in case of error as devfreq core -already call unregister on GOV_START fail. - -This fix the kernel always printing a WARN on governor PROBE_DEFER as -cpufreq_passive_unregister_notifier is called two times and return -error on the second call as the cpufreq is already unregistered. - -Fixes: a03dacb0316f ("PM / devfreq: Add cpu based scaling support to passive governor") -Signed-off-by: Christian Marangi -Signed-off-by: Chanwoo Choi ---- - drivers/devfreq/governor_passive.c | 1 - - 1 file changed, 1 deletion(-) - ---- a/drivers/devfreq/governor_passive.c -+++ b/drivers/devfreq/governor_passive.c -@@ -336,7 +336,6 @@ err_free_cpu_data: - err_put_policy: - cpufreq_cpu_put(policy); - err: -- WARN_ON(cpufreq_passive_unregister_notifier(devfreq)); - - return ret; - } diff --git a/target/linux/ipq806x/patches-5.15/113-v5.19-01-PM-devfreq-Fix-cpufreq-passive-unregister-errorin.patch b/target/linux/ipq806x/patches-5.15/113-v5.19-01-PM-devfreq-Fix-cpufreq-passive-unregister-errorin.patch deleted file mode 100644 index 08834245486..00000000000 --- a/target/linux/ipq806x/patches-5.15/113-v5.19-01-PM-devfreq-Fix-cpufreq-passive-unregister-errorin.patch +++ /dev/null @@ -1,85 +0,0 @@ -From 8953603eb5447be52f6fc3d8fcae1b3ce9899189 Mon Sep 17 00:00:00 2001 -From: Christian 'Ansuel' Marangi -Date: Mon, 6 Jun 2022 11:58:49 +0200 -Subject: [PATCH v4 1/4] PM / devfreq: Fix cpufreq passive unregister erroring - on PROBE_DEFER - -With the passive governor, the cpu based scaling can PROBE_DEFER due to -the fact that CPU policy are not ready. -The cpufreq passive unregister notifier is called both from the -GOV_START errors and for the GOV_STOP and assume the notifier is -successfully registred every time. With GOV_START failing it's wrong to -loop over each possible CPU since the register path has failed for -some CPU policy not ready. Change the logic and unregister the notifer -based on the current allocated parent_cpu_data list to correctly handle -errors and the governor unregister path. - -Fixes: a03dacb0316f ("PM / devfreq: Add cpu based scaling support to passive governor") -Signed-off-by: Christian 'Ansuel' Marangi ---- - drivers/devfreq/governor_passive.c | 39 +++++++++++++----------------- - 1 file changed, 17 insertions(+), 22 deletions(-) - ---- a/drivers/devfreq/governor_passive.c -+++ b/drivers/devfreq/governor_passive.c -@@ -34,6 +34,20 @@ get_parent_cpu_data(struct devfreq_passi - return NULL; - } - -+static void delete_parent_cpu_data(struct devfreq_passive_data *p_data) -+{ -+ struct devfreq_cpu_data *parent_cpu_data, *tmp; -+ -+ list_for_each_entry_safe(parent_cpu_data, tmp, &p_data->cpu_data_list, node) { -+ list_del(&parent_cpu_data->node); -+ -+ if (parent_cpu_data->opp_table) -+ dev_pm_opp_put_opp_table(parent_cpu_data->opp_table); -+ -+ kfree(parent_cpu_data); -+ } -+} -+ - static unsigned long get_target_freq_by_required_opp(struct device *p_dev, - struct opp_table *p_opp_table, - struct opp_table *opp_table, -@@ -222,8 +236,7 @@ static int cpufreq_passive_unregister_no - { - struct devfreq_passive_data *p_data - = (struct devfreq_passive_data *)devfreq->data; -- struct devfreq_cpu_data *parent_cpu_data; -- int cpu, ret = 0; -+ int ret; - - if (p_data->nb.notifier_call) { - ret = cpufreq_unregister_notifier(&p_data->nb, -@@ -232,27 +245,9 @@ static int cpufreq_passive_unregister_no - return ret; - } - -- for_each_possible_cpu(cpu) { -- struct cpufreq_policy *policy = cpufreq_cpu_get(cpu); -- if (!policy) { -- ret = -EINVAL; -- continue; -- } -- -- parent_cpu_data = get_parent_cpu_data(p_data, policy); -- if (!parent_cpu_data) { -- cpufreq_cpu_put(policy); -- continue; -- } -- -- list_del(&parent_cpu_data->node); -- if (parent_cpu_data->opp_table) -- dev_pm_opp_put_opp_table(parent_cpu_data->opp_table); -- kfree(parent_cpu_data); -- cpufreq_cpu_put(policy); -- } -+ delete_parent_cpu_data(p_data); - -- return ret; -+ return 0; - } - - static int cpufreq_passive_register_notifier(struct devfreq *devfreq) diff --git a/target/linux/ipq806x/patches-5.15/113-v5.19-02-PM-devfreq-Fix-kernel-panic-with-cpu-based-scaling-t.patch b/target/linux/ipq806x/patches-5.15/113-v5.19-02-PM-devfreq-Fix-kernel-panic-with-cpu-based-scaling-t.patch deleted file mode 100644 index 867ea83e0c9..00000000000 --- a/target/linux/ipq806x/patches-5.15/113-v5.19-02-PM-devfreq-Fix-kernel-panic-with-cpu-based-scaling-t.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 57e00b40033a376de3f3cf0bb9bf7590d2dd679d Mon Sep 17 00:00:00 2001 -From: Christian 'Ansuel' Marangi -Date: Tue, 14 Jun 2022 13:06:59 +0200 -Subject: [PATCH 1/1] PM / devfreq: Fix kernel panic with cpu based scaling to - passive gov - -The cpufreq passive register notifier can PROBE_DEFER and the devfreq -struct is freed and then reallocaed on probe retry. -The current logic assume that the code can't PROBE_DEFER so the devfreq -struct in the this variable in devfreq_passive_data is assumed to be -(if already set) always correct. -This cause kernel panic as the code try to access the wrong address. -To correctly handle this, update the this variable in -devfreq_passive_data to the devfreq reallocated struct. - -Fixes: a03dacb0316f ("PM / devfreq: Add cpu based scaling support to passive governor") -Signed-off-by: Christian 'Ansuel' Marangi -Signed-off-by: Chanwoo Choi ---- - drivers/devfreq/governor_passive.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - ---- a/drivers/devfreq/governor_passive.c -+++ b/drivers/devfreq/governor_passive.c -@@ -401,8 +401,7 @@ static int devfreq_passive_event_handler - if (!p_data) - return -EINVAL; - -- if (!p_data->this) -- p_data->this = devfreq; -+ p_data->this = devfreq; - - switch (event) { - case DEVFREQ_GOV_START: diff --git a/target/linux/ipq806x/patches-5.15/113-v5.19-03-PM-devfreq-Rework-freq_table-to-be-local-to-devfr.patch b/target/linux/ipq806x/patches-5.15/113-v5.19-03-PM-devfreq-Rework-freq_table-to-be-local-to-devfr.patch deleted file mode 100644 index 210f57bd7e6..00000000000 --- a/target/linux/ipq806x/patches-5.15/113-v5.19-03-PM-devfreq-Rework-freq_table-to-be-local-to-devfr.patch +++ /dev/null @@ -1,269 +0,0 @@ -From 46d05776a1a5dd8eb479e868f5ff4f4b97d68238 Mon Sep 17 00:00:00 2001 -From: Christian 'Ansuel' Marangi -Date: Mon, 6 Jun 2022 12:39:19 +0200 -Subject: [PATCH v4 3/4] PM / devfreq: Rework freq_table to be local to devfreq - struct - -Currently we reference the freq_table to the profile defined one and we -make changes on it. Devfreq never supported PROBE_DEFER before the cpu -based scaling support to the passive governor and assumed that a devfreq -device could only had error and be done with it. -Now that a device can PROBE_DEFER a rework to the freq_table logic is -required. - -If a device PROBE_DEFER on the GOV_START, the freq_table is already set -in the device profile struct and its init is skipped. This is due to the -fact that it's common for devs to declare this kind of struct static. -This cause the devfreq logic to find a freq table declared (freq_table -not NULL) with random data and poiting to the old addrs freed by devm. - -This problem CAN be solved by devs by clearing the freq_table in their -profile struct on driver exit path but it should not be trusted and it -looks to use a flawed logic. - -A better solution is to move the freq_table and max_state to the -devfreq struct and never change the profile struct. -This permit to correctly handle PROBE_DEFER since the devfreq struct is -reallocated and contains new values. -Also the profile struct should only be used to init the driver and should -not be used by the devfreq to write the freq_table if it's not provided -by the driver. - -Fixes: a03dacb0316f ("PM / devfreq: Add cpu based scaling support to passive governor") -Signed-off-by: Christian 'Ansuel' Marangi ---- - drivers/devfreq/devfreq.c | 71 ++++++++++++++---------------- - drivers/devfreq/governor_passive.c | 14 +++--- - include/linux/devfreq.h | 4 ++ - 3 files changed, 45 insertions(+), 44 deletions(-) - ---- a/drivers/devfreq/devfreq.c -+++ b/drivers/devfreq/devfreq.c -@@ -123,7 +123,7 @@ void devfreq_get_freq_range(struct devfr - unsigned long *min_freq, - unsigned long *max_freq) - { -- unsigned long *freq_table = devfreq->profile->freq_table; -+ unsigned long *freq_table = devfreq->freq_table; - s32 qos_min_freq, qos_max_freq; - - lockdep_assert_held(&devfreq->lock); -@@ -133,11 +133,11 @@ void devfreq_get_freq_range(struct devfr - * The devfreq drivers can initialize this in either ascending or - * descending order and devfreq core supports both. - */ -- if (freq_table[0] < freq_table[devfreq->profile->max_state - 1]) { -+ if (freq_table[0] < freq_table[devfreq->max_state - 1]) { - *min_freq = freq_table[0]; -- *max_freq = freq_table[devfreq->profile->max_state - 1]; -+ *max_freq = freq_table[devfreq->max_state - 1]; - } else { -- *min_freq = freq_table[devfreq->profile->max_state - 1]; -+ *min_freq = freq_table[devfreq->max_state - 1]; - *max_freq = freq_table[0]; - } - -@@ -169,8 +169,8 @@ static int devfreq_get_freq_level(struct - { - int lev; - -- for (lev = 0; lev < devfreq->profile->max_state; lev++) -- if (freq == devfreq->profile->freq_table[lev]) -+ for (lev = 0; lev < devfreq->max_state; lev++) -+ if (freq == devfreq->freq_table[lev]) - return lev; - - return -EINVAL; -@@ -178,7 +178,6 @@ static int devfreq_get_freq_level(struct - - static int set_freq_table(struct devfreq *devfreq) - { -- struct devfreq_dev_profile *profile = devfreq->profile; - struct dev_pm_opp *opp; - unsigned long freq; - int i, count; -@@ -188,25 +187,22 @@ static int set_freq_table(struct devfreq - if (count <= 0) - return -EINVAL; - -- profile->max_state = count; -- profile->freq_table = devm_kcalloc(devfreq->dev.parent, -- profile->max_state, -- sizeof(*profile->freq_table), -- GFP_KERNEL); -- if (!profile->freq_table) { -- profile->max_state = 0; -+ devfreq->max_state = count; -+ devfreq->freq_table = devm_kcalloc(devfreq->dev.parent, -+ devfreq->max_state, -+ sizeof(*devfreq->freq_table), -+ GFP_KERNEL); -+ if (!devfreq->freq_table) - return -ENOMEM; -- } - -- for (i = 0, freq = 0; i < profile->max_state; i++, freq++) { -+ for (i = 0, freq = 0; i < devfreq->max_state; i++, freq++) { - opp = dev_pm_opp_find_freq_ceil(devfreq->dev.parent, &freq); - if (IS_ERR(opp)) { -- devm_kfree(devfreq->dev.parent, profile->freq_table); -- profile->max_state = 0; -+ devm_kfree(devfreq->dev.parent, devfreq->freq_table); - return PTR_ERR(opp); - } - dev_pm_opp_put(opp); -- profile->freq_table[i] = freq; -+ devfreq->freq_table[i] = freq; - } - - return 0; -@@ -246,7 +242,7 @@ int devfreq_update_status(struct devfreq - - if (lev != prev_lev) { - devfreq->stats.trans_table[ -- (prev_lev * devfreq->profile->max_state) + lev]++; -+ (prev_lev * devfreq->max_state) + lev]++; - devfreq->stats.total_trans++; - } - -@@ -834,6 +830,9 @@ struct devfreq *devfreq_add_device(struc - if (err < 0) - goto err_dev; - mutex_lock(&devfreq->lock); -+ } else { -+ devfreq->freq_table = devfreq->profile->freq_table; -+ devfreq->max_state = devfreq->profile->max_state; - } - - devfreq->scaling_min_freq = find_available_min_freq(devfreq); -@@ -869,8 +868,8 @@ struct devfreq *devfreq_add_device(struc - - devfreq->stats.trans_table = devm_kzalloc(&devfreq->dev, - array3_size(sizeof(unsigned int), -- devfreq->profile->max_state, -- devfreq->profile->max_state), -+ devfreq->max_state, -+ devfreq->max_state), - GFP_KERNEL); - if (!devfreq->stats.trans_table) { - mutex_unlock(&devfreq->lock); -@@ -879,7 +878,7 @@ struct devfreq *devfreq_add_device(struc - } - - devfreq->stats.time_in_state = devm_kcalloc(&devfreq->dev, -- devfreq->profile->max_state, -+ devfreq->max_state, - sizeof(*devfreq->stats.time_in_state), - GFP_KERNEL); - if (!devfreq->stats.time_in_state) { -@@ -1637,9 +1636,9 @@ static ssize_t available_frequencies_sho - - mutex_lock(&df->lock); - -- for (i = 0; i < df->profile->max_state; i++) -+ for (i = 0; i < df->max_state; i++) - count += scnprintf(&buf[count], (PAGE_SIZE - count - 2), -- "%lu ", df->profile->freq_table[i]); -+ "%lu ", df->freq_table[i]); - - mutex_unlock(&df->lock); - /* Truncate the trailing space */ -@@ -1662,7 +1661,7 @@ static ssize_t trans_stat_show(struct de - - if (!df->profile) - return -EINVAL; -- max_state = df->profile->max_state; -+ max_state = df->max_state; - - if (max_state == 0) - return sprintf(buf, "Not Supported.\n"); -@@ -1679,19 +1678,17 @@ static ssize_t trans_stat_show(struct de - len += sprintf(buf + len, " :"); - for (i = 0; i < max_state; i++) - len += sprintf(buf + len, "%10lu", -- df->profile->freq_table[i]); -+ df->freq_table[i]); - - len += sprintf(buf + len, " time(ms)\n"); - - for (i = 0; i < max_state; i++) { -- if (df->profile->freq_table[i] -- == df->previous_freq) { -+ if (df->freq_table[i] == df->previous_freq) - len += sprintf(buf + len, "*"); -- } else { -+ else - len += sprintf(buf + len, " "); -- } -- len += sprintf(buf + len, "%10lu:", -- df->profile->freq_table[i]); -+ -+ len += sprintf(buf + len, "%10lu:", df->freq_table[i]); - for (j = 0; j < max_state; j++) - len += sprintf(buf + len, "%10u", - df->stats.trans_table[(i * max_state) + j]); -@@ -1715,7 +1712,7 @@ static ssize_t trans_stat_store(struct d - if (!df->profile) - return -EINVAL; - -- if (df->profile->max_state == 0) -+ if (df->max_state == 0) - return count; - - err = kstrtoint(buf, 10, &value); -@@ -1723,11 +1720,11 @@ static ssize_t trans_stat_store(struct d - return -EINVAL; - - mutex_lock(&df->lock); -- memset(df->stats.time_in_state, 0, (df->profile->max_state * -+ memset(df->stats.time_in_state, 0, (df->max_state * - sizeof(*df->stats.time_in_state))); - memset(df->stats.trans_table, 0, array3_size(sizeof(unsigned int), -- df->profile->max_state, -- df->profile->max_state)); -+ df->max_state, -+ df->max_state)); - df->stats.total_trans = 0; - df->stats.last_update = get_jiffies_64(); - mutex_unlock(&df->lock); ---- a/drivers/devfreq/governor_passive.c -+++ b/drivers/devfreq/governor_passive.c -@@ -145,18 +145,18 @@ static int get_target_freq_with_devfreq( - goto out; - - /* Use interpolation if required opps is not available */ -- for (i = 0; i < parent_devfreq->profile->max_state; i++) -- if (parent_devfreq->profile->freq_table[i] == *freq) -+ for (i = 0; i < parent_devfreq->max_state; i++) -+ if (parent_devfreq->freq_table[i] == *freq) - break; - -- if (i == parent_devfreq->profile->max_state) -+ if (i == parent_devfreq->max_state) - return -EINVAL; - -- if (i < devfreq->profile->max_state) { -- child_freq = devfreq->profile->freq_table[i]; -+ if (i < devfreq->max_state) { -+ child_freq = devfreq->freq_table[i]; - } else { -- count = devfreq->profile->max_state; -- child_freq = devfreq->profile->freq_table[count - 1]; -+ count = devfreq->max_state; -+ child_freq = devfreq->freq_table[count - 1]; - } - - out: ---- a/include/linux/devfreq.h -+++ b/include/linux/devfreq.h -@@ -185,6 +185,10 @@ struct devfreq { - struct notifier_block nb; - struct delayed_work work; - -+ /* devfreq local freq_table */ -+ unsigned long *freq_table; -+ unsigned int max_state; -+ - unsigned long previous_freq; - struct devfreq_dev_status last_status; - diff --git a/target/linux/ipq806x/patches-5.15/113-v5.19-04-PM-devfreq-Mute-warning-on-governor-PROBE_DEFER.patch b/target/linux/ipq806x/patches-5.15/113-v5.19-04-PM-devfreq-Mute-warning-on-governor-PROBE_DEFER.patch deleted file mode 100644 index 591340c6f22..00000000000 --- a/target/linux/ipq806x/patches-5.15/113-v5.19-04-PM-devfreq-Mute-warning-on-governor-PROBE_DEFER.patch +++ /dev/null @@ -1,28 +0,0 @@ -From eee9f767c41b03a2744d4b0f0c1a144e4ff41e78 Mon Sep 17 00:00:00 2001 -From: Christian 'Ansuel' Marangi -Date: Mon, 6 Jun 2022 13:01:02 +0200 -Subject: [PATCH v4 4/4] PM / devfreq: Mute warning on governor PROBE_DEFER - -Don't print warning when a governor PROBE_DEFER as it's not a real -GOV_START fail. - -Fixes: a03dacb0316f ("PM / devfreq: Add cpu based scaling support to passive governor") -Signed-off-by: Christian 'Ansuel' Marangi ---- - drivers/devfreq/devfreq.c | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - ---- a/drivers/devfreq/devfreq.c -+++ b/drivers/devfreq/devfreq.c -@@ -930,8 +930,9 @@ struct devfreq *devfreq_add_device(struc - err = devfreq->governor->event_handler(devfreq, DEVFREQ_GOV_START, - NULL); - if (err) { -- dev_err(dev, "%s: Unable to start governor for the device\n", -- __func__); -+ dev_err_probe(dev, err, -+ "%s: Unable to start governor for the device\n", -+ __func__); - goto err_init; - } - create_sysfs_files(devfreq, devfreq->governor); diff --git a/target/linux/ipq806x/patches-5.15/114-01-devfreq-qcom-Add-L2-Krait-Cache-devfreq-scaling-driv.patch b/target/linux/ipq806x/patches-5.15/114-01-devfreq-qcom-Add-L2-Krait-Cache-devfreq-scaling-driv.patch deleted file mode 100644 index 85feb89148b..00000000000 --- a/target/linux/ipq806x/patches-5.15/114-01-devfreq-qcom-Add-L2-Krait-Cache-devfreq-scaling-driv.patch +++ /dev/null @@ -1,242 +0,0 @@ -From b044ae89862132a86fb511648e9c52ea3cdf8c30 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Wed, 5 Aug 2020 14:19:23 +0200 -Subject: [PATCH 1/4] devfreq: qcom: Add L2 Krait Cache devfreq scaling driver - -Qcom L2 Krait CPUs use the generic cpufreq-dt driver and doesn't actually -scale the Cache frequency when the CPU frequency is changed. This -devfreq driver register with the cpu notifier and scale the Cache -based on the max Freq across all core as the CPU cache is shared across -all of them. If provided this also scale the voltage of the regulator -attached to the CPU cache. The scaling logic is based on the CPU freq -and the 3 scaling interval are set by the device dts. - -Signed-off-by: Christian Marangi ---- - drivers/devfreq/Kconfig | 11 ++ - drivers/devfreq/Makefile | 1 + - drivers/devfreq/krait-cache-devfreq.c | 188 ++++++++++++++++++++++++++ - 3 files changed, 200 insertions(+) - create mode 100644 drivers/devfreq/krait-cache-devfreq.c - ---- a/drivers/devfreq/Kconfig -+++ b/drivers/devfreq/Kconfig -@@ -132,6 +132,17 @@ config ARM_RK3399_DMC_DEVFREQ - It sets the frequency for the memory controller and reads the usage counts - from hardware. - -+config ARM_KRAIT_CACHE_DEVFREQ -+ tristate "Scaling support for Krait CPU Cache Devfreq" -+ depends on ARCH_QCOM || COMPILE_TEST -+ select DEVFREQ_GOV_PASSIVE -+ help -+ This adds the DEVFREQ driver for the Krait CPU L2 Cache shared by all cores. -+ -+ The driver register with the cpufreq notifier and find the right frequency -+ based on the max frequency across all core and the range set in the device -+ dts. If provided this scale also the regulator attached to the l2 cache. -+ - source "drivers/devfreq/event/Kconfig" - - endif # PM_DEVFREQ ---- a/drivers/devfreq/Makefile -+++ b/drivers/devfreq/Makefile -@@ -13,6 +13,7 @@ obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx - obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o - obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o - obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o -+obj-$(CONFIG_ARM_KRAIT_CACHE_DEVFREQ) += krait-cache-devfreq.o - - # DEVFREQ Event Drivers - obj-$(CONFIG_PM_DEVFREQ_EVENT) += event/ ---- /dev/null -+++ b/drivers/devfreq/krait-cache-devfreq.c -@@ -0,0 +1,188 @@ -+// SPDX-License-Identifier: GPL-2.0 -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "governor.h" -+ -+struct krait_cache_data { -+ struct clk *clk; -+ unsigned long idle_freq; -+}; -+ -+static int krait_cache_set_opp(struct dev_pm_set_opp_data *data) -+{ -+ unsigned long old_freq = data->old_opp.rate, freq = data->new_opp.rate; -+ struct dev_pm_opp_supply *supply = &data->new_opp.supplies[0]; -+ struct regulator *reg = data->regulators[0]; -+ struct krait_cache_data *kdata; -+ struct clk *clk = data->clk; -+ unsigned long idle_freq; -+ int ret; -+ -+ kdata = dev_get_drvdata(data->dev); -+ idle_freq = kdata->idle_freq; -+ -+ if (reg) { -+ ret = regulator_set_voltage_triplet(reg, supply->u_volt_min, -+ supply->u_volt, -+ supply->u_volt_max); -+ if (ret) -+ goto exit; -+ } -+ -+ /* -+ * Set to idle bin if switching from normal to high bin -+ * or vice versa. It has been notice that a bug is triggered -+ * in cache scaling when more than one bin is scaled, to fix -+ * this we first need to transition to the base rate and then -+ * to target rate -+ */ -+ if (likely(freq != idle_freq && old_freq != idle_freq)) { -+ ret = clk_set_rate(clk, idle_freq); -+ if (ret) -+ goto exit; -+ } -+ -+ ret = clk_set_rate(clk, freq); -+ if (ret) -+ goto exit; -+ -+exit: -+ return ret; -+}; -+ -+static int krait_cache_get_cur_freq(struct device *dev, unsigned long *freq) -+{ -+ struct krait_cache_data *data = dev_get_drvdata(dev); -+ -+ *freq = clk_get_rate(data->clk); -+ -+ return 0; -+}; -+ -+static int krait_cache_target(struct device *dev, unsigned long *freq, -+ u32 flags) -+{ -+ struct dev_pm_opp *opp; -+ -+ opp = dev_pm_opp_find_freq_ceil(dev, freq); -+ if (unlikely(IS_ERR(opp))) -+ return PTR_ERR(opp); -+ -+ dev_pm_opp_put(opp); -+ -+ return dev_pm_opp_set_rate(dev, *freq); -+}; -+ -+static int krait_cache_get_dev_status(struct device *dev, -+ struct devfreq_dev_status *stat) -+{ -+ struct krait_cache_data *data = dev_get_drvdata(dev); -+ -+ stat->busy_time = 0; -+ stat->total_time = 0; -+ stat->current_frequency = clk_get_rate(data->clk); -+ -+ return 0; -+}; -+ -+static struct devfreq_dev_profile krait_cache_devfreq_profile = { -+ .target = krait_cache_target, -+ .get_dev_status = krait_cache_get_dev_status, -+ .get_cur_freq = krait_cache_get_cur_freq -+}; -+ -+static struct devfreq_passive_data devfreq_gov_data = { -+ .parent_type = CPUFREQ_PARENT_DEV, -+}; -+ -+static int krait_cache_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct krait_cache_data *data; -+ struct opp_table *table; -+ struct devfreq *devfreq; -+ struct dev_pm_opp *opp; -+ struct clk *clk; -+ int ret; -+ -+ krait_cache_devfreq_profile.freq_table = NULL; -+ -+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); -+ if (!data) -+ return -ENOMEM; -+ -+ clk = devm_clk_get(dev, "l2"); -+ if (IS_ERR(clk)) -+ return PTR_ERR(clk); -+ -+ table = dev_pm_opp_set_regulators(dev, (const char *[]){ "l2" }, 1); -+ if (IS_ERR(table)) { -+ ret = PTR_ERR(table); -+ dev_err_probe(dev, -EPROBE_DEFER, "failed to set regulators %d\n", ret); -+ return ret; -+ } -+ -+ ret = PTR_ERR_OR_ZERO( -+ dev_pm_opp_register_set_opp_helper(dev, krait_cache_set_opp)); -+ if (ret) -+ return ret; -+ -+ ret = dev_pm_opp_of_add_table(dev); -+ if (ret) { -+ dev_err(dev, "failed to parse L2 freq thresholds\n"); -+ return ret; -+ } -+ -+ data->clk = clk; -+ opp = dev_pm_opp_find_freq_ceil(dev, &data->idle_freq); -+ dev_pm_opp_put(opp); -+ -+ dev_set_drvdata(dev, data); -+ -+ devfreq = devm_devfreq_add_device(&pdev->dev, &krait_cache_devfreq_profile, -+ DEVFREQ_GOV_PASSIVE, &devfreq_gov_data); -+ if (IS_ERR(devfreq)) { -+ dev_pm_opp_remove_table(dev); -+ dev_pm_opp_put_regulators(table); -+ dev_pm_opp_unregister_set_opp_helper(table); -+ } -+ -+ return PTR_ERR_OR_ZERO(devfreq); -+}; -+ -+static int krait_cache_remove(struct platform_device *pdev) -+{ -+ dev_pm_opp_remove_table(&pdev->dev); -+ -+ return 0; -+}; -+ -+static const struct of_device_id krait_cache_match_table[] = { -+ { .compatible = "qcom,krait-cache" }, -+ {} -+}; -+ -+static struct platform_driver krait_cache_driver = { -+ .probe = krait_cache_probe, -+ .remove = krait_cache_remove, -+ .driver = { -+ .name = "krait-cache-scaling", -+ .of_match_table = krait_cache_match_table, -+ }, -+}; -+module_platform_driver(krait_cache_driver); -+ -+MODULE_DESCRIPTION("Krait CPU Cache Scaling driver"); -+MODULE_AUTHOR("Christian 'Ansuel' Marangi "); -+MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ipq806x/patches-5.15/114-02-ARM-dts-qcom-add-krait-cache-compatible-for-ipq806x-.patch b/target/linux/ipq806x/patches-5.15/114-02-ARM-dts-qcom-add-krait-cache-compatible-for-ipq806x-.patch deleted file mode 100644 index f42729fd509..00000000000 --- a/target/linux/ipq806x/patches-5.15/114-02-ARM-dts-qcom-add-krait-cache-compatible-for-ipq806x-.patch +++ /dev/null @@ -1,50 +0,0 @@ -From ef124ad0ff8abfbf4ebe3fe6d7dcef4541dec13a Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 16 Jun 2022 18:39:21 +0200 -Subject: [PATCH] ARM: dts: qcom: add krait-cache compatible for ipq806x dtsi - -Add qcom,krait-cache compatible to enable cache devfreq driver for -ipq806x SoC and move the L2 node to the soc node to make the devfreq -driver correctly probe. - -Signed-off-by: Christian Marangi ---- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 22 +++++++++++----------- - 1 file changed, 11 insertions(+), 11 deletions(-) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -69,16 +69,6 @@ - min-residency-us = <3000>; - }; - }; -- -- L2: l2-cache { -- compatible = "cache"; -- cache-level = <2>; -- qcom,saw = <&saw_l2>; -- -- clocks = <&kraitcc 4>; -- clock-names = "l2"; -- operating-points-v2 = <&opp_table_l2>; -- }; - }; - - opp_table_l2: opp_table_l2 { -@@ -470,6 +460,16 @@ - ranges; - compatible = "simple-bus"; - -+ L2: l2-cache { -+ compatible = "cache", "qcom,krait-cache"; -+ cache-level = <2>; -+ qcom,saw = <&saw_l2>; -+ -+ clocks = <&kraitcc 4>; -+ clock-names = "l2"; -+ operating-points-v2 = <&opp_table_l2>; -+ }; -+ - lpass@28100000 { - compatible = "qcom,lpass-cpu"; - status = "disabled"; diff --git a/target/linux/ipq806x/patches-5.15/115-01-devfreq-add-ipq806x-fabric-scaling-driver.patch b/target/linux/ipq806x/patches-5.15/115-01-devfreq-add-ipq806x-fabric-scaling-driver.patch deleted file mode 100644 index 340c58a0c18..00000000000 --- a/target/linux/ipq806x/patches-5.15/115-01-devfreq-add-ipq806x-fabric-scaling-driver.patch +++ /dev/null @@ -1,203 +0,0 @@ -From 13f075999935bb696dbab63243923179f06fa05e Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 16 Jun 2022 19:56:08 +0200 -Subject: [PATCH 3/4] devfreq: add ipq806x fabric scaling driver - -Add ipq806x fabric scaling driver using the devfreq passive governor. - -Signed-off-by: Christian Marangi ---- - drivers/devfreq/Kconfig | 11 ++ - drivers/devfreq/Makefile | 1 + - drivers/devfreq/ipq806x-fab-devfreq.c | 155 ++++++++++++++++++++++++++ - 3 files changed, 167 insertions(+) - create mode 100644 drivers/devfreq/ipq806x-fab-devfreq.c - ---- a/drivers/devfreq/Kconfig -+++ b/drivers/devfreq/Kconfig -@@ -143,6 +143,17 @@ config ARM_KRAIT_CACHE_DEVFREQ - based on the max frequency across all core and the range set in the device - dts. If provided this scale also the regulator attached to the l2 cache. - -+config ARM_IPQ806X_FAB_DEVFREQ -+ tristate "Scaling support for ipq806x Soc Fabric" -+ depends on ARCH_QCOM || COMPILE_TEST -+ select DEVFREQ_GOV_PASSIVE -+ help -+ This adds the DEVFREQ driver for the ipq806x Soc Fabric. -+ -+ The driver register with the cpufreq notifier and find the right frequency -+ based on the max frequency across all core and the range set in the device -+ dts. -+ - source "drivers/devfreq/event/Kconfig" - - endif # PM_DEVFREQ ---- a/drivers/devfreq/Makefile -+++ b/drivers/devfreq/Makefile -@@ -14,6 +14,7 @@ obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += - obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o - obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o - obj-$(CONFIG_ARM_KRAIT_CACHE_DEVFREQ) += krait-cache-devfreq.o -+obj-$(CONFIG_ARM_IPQ806X_FAB_DEVFREQ) += ipq806x-fab-devfreq.o - - # DEVFREQ Event Drivers - obj-$(CONFIG_PM_DEVFREQ_EVENT) += event/ ---- /dev/null -+++ b/drivers/devfreq/ipq806x-fab-devfreq.c -@@ -0,0 +1,155 @@ -+// SPDX-License-Identifier: GPL-2.0 -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "governor.h" -+ -+struct ipq806x_fab_data { -+ struct clk *fab_clk; -+ struct clk *ddr_clk; -+}; -+ -+static int ipq806x_fab_get_cur_freq(struct device *dev, unsigned long *freq) -+{ -+ struct ipq806x_fab_data *data = dev_get_drvdata(dev); -+ -+ *freq = clk_get_rate(data->fab_clk); -+ -+ return 0; -+}; -+ -+static int ipq806x_fab_target(struct device *dev, unsigned long *freq, -+ u32 flags) -+{ -+ struct ipq806x_fab_data *data = dev_get_drvdata(dev); -+ struct dev_pm_opp *opp; -+ int ret; -+ -+ opp = dev_pm_opp_find_freq_ceil(dev, freq); -+ if (unlikely(IS_ERR(opp))) -+ return PTR_ERR(opp); -+ -+ dev_pm_opp_put(opp); -+ -+ ret = clk_set_rate(data->fab_clk, *freq); -+ if (ret) -+ return ret; -+ -+ return clk_set_rate(data->ddr_clk, *freq); -+}; -+ -+static int ipq806x_fab_get_dev_status(struct device *dev, -+ struct devfreq_dev_status *stat) -+{ -+ struct ipq806x_fab_data *data = dev_get_drvdata(dev); -+ -+ stat->busy_time = 0; -+ stat->total_time = 0; -+ stat->current_frequency = clk_get_rate(data->fab_clk); -+ -+ return 0; -+}; -+ -+static struct devfreq_dev_profile ipq806x_fab_devfreq_profile = { -+ .target = ipq806x_fab_target, -+ .get_dev_status = ipq806x_fab_get_dev_status, -+ .get_cur_freq = ipq806x_fab_get_cur_freq -+}; -+ -+static struct devfreq_passive_data devfreq_gov_data = { -+ .parent_type = CPUFREQ_PARENT_DEV, -+}; -+ -+static int ipq806x_fab_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct ipq806x_fab_data *data; -+ struct devfreq *devfreq; -+ struct clk *clk; -+ int ret; -+ -+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); -+ if (!data) -+ return -ENOMEM; -+ -+ clk = devm_clk_get(dev, "apps-fab-clk"); -+ if (IS_ERR(clk)) { -+ dev_err_probe(dev, PTR_ERR(clk), "failed to get apps fab clk\n"); -+ return PTR_ERR(clk); -+ } -+ -+ clk_prepare_enable(clk); -+ data->fab_clk = clk; -+ -+ clk = devm_clk_get(dev, "ddr-fab-clk"); -+ if (IS_ERR(clk)) { -+ dev_err_probe(dev, PTR_ERR(clk), "failed to get ddr fab clk\n"); -+ goto err_ddr; -+ } -+ -+ clk_prepare_enable(clk); -+ data->ddr_clk = clk; -+ -+ ret = dev_pm_opp_of_add_table(dev); -+ if (ret) { -+ dev_err(dev, "failed to parse fab freq thresholds\n"); -+ return ret; -+ } -+ -+ dev_set_drvdata(dev, data); -+ -+ devfreq = devm_devfreq_add_device(&pdev->dev, &ipq806x_fab_devfreq_profile, -+ DEVFREQ_GOV_PASSIVE, &devfreq_gov_data); -+ if (IS_ERR(devfreq)) -+ dev_pm_opp_remove_table(dev); -+ -+ return PTR_ERR_OR_ZERO(devfreq); -+ -+err_ddr: -+ clk_unprepare(data->fab_clk); -+ clk_put(data->fab_clk); -+ return PTR_ERR(clk); -+}; -+ -+static int ipq806x_fab_remove(struct platform_device *pdev) -+{ -+ struct ipq806x_fab_data *data = dev_get_drvdata(&pdev->dev); -+ -+ clk_unprepare(data->fab_clk); -+ clk_put(data->fab_clk); -+ -+ clk_unprepare(data->ddr_clk); -+ clk_put(data->ddr_clk); -+ -+ dev_pm_opp_remove_table(&pdev->dev); -+ -+ return 0; -+}; -+ -+static const struct of_device_id ipq806x_fab_match_table[] = { -+ { .compatible = "qcom,fab-scaling" }, -+ {} -+}; -+ -+static struct platform_driver ipq806x_fab_driver = { -+ .probe = ipq806x_fab_probe, -+ .remove = ipq806x_fab_remove, -+ .driver = { -+ .name = "ipq806x-fab-scaling", -+ .of_match_table = ipq806x_fab_match_table, -+ }, -+}; -+module_platform_driver(ipq806x_fab_driver); -+ -+MODULE_DESCRIPTION("ipq806x Fab Scaling driver"); -+MODULE_AUTHOR("Christian Marangi "); -+MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ipq806x/patches-5.15/115-02-ARM-dts-qcom-add-fab-scaling-node-for-ipq806x.patch b/target/linux/ipq806x/patches-5.15/115-02-ARM-dts-qcom-add-fab-scaling-node-for-ipq806x.patch deleted file mode 100644 index f4de1dbb52c..00000000000 --- a/target/linux/ipq806x/patches-5.15/115-02-ARM-dts-qcom-add-fab-scaling-node-for-ipq806x.patch +++ /dev/null @@ -1,48 +0,0 @@ -From c3573f0907dadb0a6e9933aae2a46a489abcbd48 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 16 Jun 2022 20:03:05 +0200 -Subject: [PATCH 4/4] ARM: dts: qcom: add fab scaling node for ipq806x - -Add fabric scaling node for ipq806x to correctly scale apps and ddr -fabric clk. - -Signed-off-by: Christian Marangi ---- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 19 +++++++++++++++++++ - 1 file changed, 19 insertions(+) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -170,6 +170,18 @@ - }; - }; - -+ opp_table_fab: opp_table_fab { -+ compatible = "operating-points-v2"; -+ -+ opp-533000000 { -+ opp-hz = /bits/ 64 <533000000>; -+ }; -+ -+ opp-400000000 { -+ opp-hz = /bits/ 64 <400000000>; -+ }; -+ }; -+ - thermal-zones { - tsens_tz_sensor0 { - polling-delay-passive = <0>; -@@ -470,6 +482,13 @@ - operating-points-v2 = <&opp_table_l2>; - }; - -+ fab-scaling { -+ compatible = "qcom,fab-scaling"; -+ clocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>; -+ clock-names = "apps-fab-clk", "ddr-fab-clk"; -+ operating-points-v2 = <&opp_table_fab>; -+ }; -+ - lpass@28100000 { - compatible = "qcom,lpass-cpu"; - status = "disabled"; diff --git a/target/linux/ipq806x/patches-5.15/116-v6.0-01-mtd-nand-raw-qcom_nandc-reorder-qcom_nand_host-struc.patch b/target/linux/ipq806x/patches-5.15/116-v6.0-01-mtd-nand-raw-qcom_nandc-reorder-qcom_nand_host-struc.patch deleted file mode 100644 index c595b10dd74..00000000000 --- a/target/linux/ipq806x/patches-5.15/116-v6.0-01-mtd-nand-raw-qcom_nandc-reorder-qcom_nand_host-struc.patch +++ /dev/null @@ -1,268 +0,0 @@ -From b360514edb4743cbf86fc377699c75e98b1264c7 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 16 Jun 2022 02:18:33 +0200 -Subject: [PATCH 1/2] mtd: nand: raw: qcom_nandc: reorder qcom_nand_host struct - -Reorder structs in nandc driver to save holes. - -Signed-off-by: Christian Marangi -Reviewed-by: Manivannan Sadhasivam -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20220616001835.24393-2-ansuelsmth@gmail.com ---- - drivers/mtd/nand/raw/qcom_nandc.c | 107 +++++++++++++++++------------- - 1 file changed, 62 insertions(+), 45 deletions(-) - ---- a/drivers/mtd/nand/raw/qcom_nandc.c -+++ b/drivers/mtd/nand/raw/qcom_nandc.c -@@ -237,6 +237,9 @@ nandc_set_reg(chip, reg, \ - * @bam_ce - the array of BAM command elements - * @cmd_sgl - sgl for NAND BAM command pipe - * @data_sgl - sgl for NAND BAM consumer/producer pipe -+ * @last_data_desc - last DMA desc in data channel (tx/rx). -+ * @last_cmd_desc - last DMA desc in command channel. -+ * @txn_done - completion for NAND transfer. - * @bam_ce_pos - the index in bam_ce which is available for next sgl - * @bam_ce_start - the index in bam_ce which marks the start position ce - * for current sgl. It will be used for size calculation -@@ -249,14 +252,14 @@ nandc_set_reg(chip, reg, \ - * @rx_sgl_start - start index in data sgl for rx. - * @wait_second_completion - wait for second DMA desc completion before making - * the NAND transfer completion. -- * @txn_done - completion for NAND transfer. -- * @last_data_desc - last DMA desc in data channel (tx/rx). -- * @last_cmd_desc - last DMA desc in command channel. - */ - struct bam_transaction { - struct bam_cmd_element *bam_ce; - struct scatterlist *cmd_sgl; - struct scatterlist *data_sgl; -+ struct dma_async_tx_descriptor *last_data_desc; -+ struct dma_async_tx_descriptor *last_cmd_desc; -+ struct completion txn_done; - u32 bam_ce_pos; - u32 bam_ce_start; - u32 cmd_sgl_pos; -@@ -266,25 +269,23 @@ struct bam_transaction { - u32 rx_sgl_pos; - u32 rx_sgl_start; - bool wait_second_completion; -- struct completion txn_done; -- struct dma_async_tx_descriptor *last_data_desc; -- struct dma_async_tx_descriptor *last_cmd_desc; - }; - - /* - * This data type corresponds to the nand dma descriptor -+ * @dma_desc - low level DMA engine descriptor - * @list - list for desc_info -- * @dir - DMA transfer direction -+ * - * @adm_sgl - sgl which will be used for single sgl dma descriptor. Only used by - * ADM - * @bam_sgl - sgl which will be used for dma descriptor. Only used by BAM - * @sgl_cnt - number of SGL in bam_sgl. Only used by BAM -- * @dma_desc - low level DMA engine descriptor -+ * @dir - DMA transfer direction - */ - struct desc_info { -+ struct dma_async_tx_descriptor *dma_desc; - struct list_head node; - -- enum dma_data_direction dir; - union { - struct scatterlist adm_sgl; - struct { -@@ -292,7 +293,7 @@ struct desc_info { - int sgl_cnt; - }; - }; -- struct dma_async_tx_descriptor *dma_desc; -+ enum dma_data_direction dir; - }; - - /* -@@ -336,52 +337,64 @@ struct nandc_regs { - /* - * NAND controller data struct - * -- * @controller: base controller structure -- * @host_list: list containing all the chips attached to the -- * controller - * @dev: parent device -+ * - * @base: MMIO base -- * @base_phys: physical base address of controller registers -- * @base_dma: dma base address of controller registers -+ * - * @core_clk: controller clock - * @aon_clk: another controller clock - * -+ * @regs: a contiguous chunk of memory for DMA register -+ * writes. contains the register values to be -+ * written to controller -+ * -+ * @props: properties of current NAND controller, -+ * initialized via DT match data -+ * -+ * @controller: base controller structure -+ * @host_list: list containing all the chips attached to the -+ * controller -+ * - * @chan: dma channel - * @cmd_crci: ADM DMA CRCI for command flow control - * @data_crci: ADM DMA CRCI for data flow control -+ * - * @desc_list: DMA descriptor list (list of desc_infos) - * - * @data_buffer: our local DMA buffer for page read/writes, - * used when we can't use the buffer provided - * by upper layers directly -- * @buf_size/count/start: markers for chip->legacy.read_buf/write_buf -- * functions - * @reg_read_buf: local buffer for reading back registers via DMA -+ * -+ * @base_phys: physical base address of controller registers -+ * @base_dma: dma base address of controller registers - * @reg_read_dma: contains dma address for register read buffer -- * @reg_read_pos: marker for data read in reg_read_buf - * -- * @regs: a contiguous chunk of memory for DMA register -- * writes. contains the register values to be -- * written to controller -- * @cmd1/vld: some fixed controller register values -- * @props: properties of current NAND controller, -- * initialized via DT match data -+ * @buf_size/count/start: markers for chip->legacy.read_buf/write_buf -+ * functions - * @max_cwperpage: maximum QPIC codewords required. calculated - * from all connected NAND devices pagesize -+ * -+ * @reg_read_pos: marker for data read in reg_read_buf -+ * -+ * @cmd1/vld: some fixed controller register values - */ - struct qcom_nand_controller { -- struct nand_controller controller; -- struct list_head host_list; -- - struct device *dev; - - void __iomem *base; -- phys_addr_t base_phys; -- dma_addr_t base_dma; - - struct clk *core_clk; - struct clk *aon_clk; - -+ struct nandc_regs *regs; -+ struct bam_transaction *bam_txn; -+ -+ const struct qcom_nandc_props *props; -+ -+ struct nand_controller controller; -+ struct list_head host_list; -+ - union { - /* will be used only by QPIC for BAM DMA */ - struct { -@@ -399,22 +412,22 @@ struct qcom_nand_controller { - }; - - struct list_head desc_list; -- struct bam_transaction *bam_txn; - - u8 *data_buffer; -+ __le32 *reg_read_buf; -+ -+ phys_addr_t base_phys; -+ dma_addr_t base_dma; -+ dma_addr_t reg_read_dma; -+ - int buf_size; - int buf_count; - int buf_start; - unsigned int max_cwperpage; - -- __le32 *reg_read_buf; -- dma_addr_t reg_read_dma; - int reg_read_pos; - -- struct nandc_regs *regs; -- - u32 cmd1, vld; -- const struct qcom_nandc_props *props; - }; - - /* -@@ -430,19 +443,21 @@ struct qcom_nand_controller { - * and reserved bytes - * @cw_data: the number of bytes within a codeword protected - * by ECC -- * @use_ecc: request the controller to use ECC for the -- * upcoming read/write -- * @bch_enabled: flag to tell whether BCH ECC mode is used - * @ecc_bytes_hw: ECC bytes used by controller hardware for this - * chip -- * @status: value to be returned if NAND_CMD_STATUS command -- * is executed -+ * - * @last_command: keeps track of last command on this chip. used - * for reading correct status - * - * @cfg0, cfg1, cfg0_raw..: NANDc register configurations needed for - * ecc/non-ecc mode for the current nand flash - * device -+ * -+ * @status: value to be returned if NAND_CMD_STATUS command -+ * is executed -+ * @use_ecc: request the controller to use ECC for the -+ * upcoming read/write -+ * @bch_enabled: flag to tell whether BCH ECC mode is used - */ - struct qcom_nand_host { - struct nand_chip chip; -@@ -451,12 +466,10 @@ struct qcom_nand_host { - int cs; - int cw_size; - int cw_data; -- bool use_ecc; -- bool bch_enabled; - int ecc_bytes_hw; - int spare_bytes; - int bbm_size; -- u8 status; -+ - int last_command; - - u32 cfg0, cfg1; -@@ -465,23 +478,27 @@ struct qcom_nand_host { - u32 ecc_bch_cfg; - u32 clrflashstatus; - u32 clrreadstatus; -+ -+ u8 status; -+ bool use_ecc; -+ bool bch_enabled; - }; - - /* - * This data type corresponds to the NAND controller properties which varies - * among different NAND controllers. - * @ecc_modes - ecc mode for NAND -+ * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset - * @is_bam - whether NAND controller is using BAM - * @is_qpic - whether NAND CTRL is part of qpic IP - * @qpic_v2 - flag to indicate QPIC IP version 2 -- * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset - */ - struct qcom_nandc_props { - u32 ecc_modes; -+ u32 dev_cmd_reg_start; - bool is_bam; - bool is_qpic; - bool qpic_v2; -- u32 dev_cmd_reg_start; - }; - - /* Frees the BAM transaction memory */ diff --git a/target/linux/ipq806x/patches-5.15/116-v6.0-02-mtd-nand-raw-qcom_nandc-add-support-for-unprotected-.patch b/target/linux/ipq806x/patches-5.15/116-v6.0-02-mtd-nand-raw-qcom_nandc-add-support-for-unprotected-.patch deleted file mode 100644 index 2a661953044..00000000000 --- a/target/linux/ipq806x/patches-5.15/116-v6.0-02-mtd-nand-raw-qcom_nandc-add-support-for-unprotected-.patch +++ /dev/null @@ -1,406 +0,0 @@ -From 862bdedd7f4b8aebf00fdb422062e64896e97809 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 16 Jun 2022 02:18:34 +0200 -Subject: [PATCH 2/2] mtd: nand: raw: qcom_nandc: add support for unprotected - spare data pages - -IPQ8064 nand have special pages where a different layout scheme is used. -These special page are used by boot partition and on reading them -lots of warning are reported about wrong ECC data and if written to -results in broken data and not bootable device. - -The layout scheme used by these special page consist in using 512 bytes -as the codeword size (even for the last codeword) while writing to CFG0 -register. This forces the NAND controller to unprotect the 4 bytes of -spare data. - -Since the kernel is unaware of this different layout for these special -page, it does try to protect the spare data too during read/write and -warn about CRC errors. - -Add support for this by permitting the user to declare these special -pages in dts by declaring offset and size of the partition. The driver -internally will convert these value to nand pages. - -On user read/write the page is checked and if it's a boot page the -correct layout is used. - -Signed-off-by: Christian Marangi -Reviewed-by: Manivannan Sadhasivam -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20220616001835.24393-3-ansuelsmth@gmail.com ---- - drivers/mtd/nand/raw/qcom_nandc.c | 199 +++++++++++++++++++++++++++++- - 1 file changed, 194 insertions(+), 5 deletions(-) - ---- a/drivers/mtd/nand/raw/qcom_nandc.c -+++ b/drivers/mtd/nand/raw/qcom_nandc.c -@@ -79,8 +79,10 @@ - #define DISABLE_STATUS_AFTER_WRITE 4 - #define CW_PER_PAGE 6 - #define UD_SIZE_BYTES 9 -+#define UD_SIZE_BYTES_MASK GENMASK(18, 9) - #define ECC_PARITY_SIZE_BYTES_RS 19 - #define SPARE_SIZE_BYTES 23 -+#define SPARE_SIZE_BYTES_MASK GENMASK(26, 23) - #define NUM_ADDR_CYCLES 27 - #define STATUS_BFR_READ 30 - #define SET_RD_MODE_AFTER_STATUS 31 -@@ -101,6 +103,7 @@ - #define ECC_MODE 4 - #define ECC_PARITY_SIZE_BYTES_BCH 8 - #define ECC_NUM_DATA_BYTES 16 -+#define ECC_NUM_DATA_BYTES_MASK GENMASK(25, 16) - #define ECC_FORCE_CLK_OPEN 30 - - /* NAND_DEV_CMD1 bits */ -@@ -431,12 +434,31 @@ struct qcom_nand_controller { - }; - - /* -+ * NAND special boot partitions -+ * -+ * @page_offset: offset of the partition where spare data is not protected -+ * by ECC (value in pages) -+ * @page_offset: size of the partition where spare data is not protected -+ * by ECC (value in pages) -+ */ -+struct qcom_nand_boot_partition { -+ u32 page_offset; -+ u32 page_size; -+}; -+ -+/* - * NAND chip structure - * -+ * @boot_partitions: array of boot partitions where offset and size of the -+ * boot partitions are stored -+ * - * @chip: base NAND chip structure - * @node: list node to add itself to host_list in - * qcom_nand_controller - * -+ * @nr_boot_partitions: count of the boot partitions where spare data is not -+ * protected by ECC -+ * - * @cs: chip select value for this chip - * @cw_size: the number of bytes in a single step/codeword - * of a page, consisting of all data, ecc, spare -@@ -455,14 +477,20 @@ struct qcom_nand_controller { - * - * @status: value to be returned if NAND_CMD_STATUS command - * is executed -+ * @codeword_fixup: keep track of the current layout used by -+ * the driver for read/write operation. - * @use_ecc: request the controller to use ECC for the - * upcoming read/write - * @bch_enabled: flag to tell whether BCH ECC mode is used - */ - struct qcom_nand_host { -+ struct qcom_nand_boot_partition *boot_partitions; -+ - struct nand_chip chip; - struct list_head node; - -+ int nr_boot_partitions; -+ - int cs; - int cw_size; - int cw_data; -@@ -480,6 +508,7 @@ struct qcom_nand_host { - u32 clrreadstatus; - - u8 status; -+ bool codeword_fixup; - bool use_ecc; - bool bch_enabled; - }; -@@ -492,6 +521,7 @@ struct qcom_nand_host { - * @is_bam - whether NAND controller is using BAM - * @is_qpic - whether NAND CTRL is part of qpic IP - * @qpic_v2 - flag to indicate QPIC IP version 2 -+ * @use_codeword_fixup - whether NAND has different layout for boot partitions - */ - struct qcom_nandc_props { - u32 ecc_modes; -@@ -499,6 +529,7 @@ struct qcom_nandc_props { - bool is_bam; - bool is_qpic; - bool qpic_v2; -+ bool use_codeword_fixup; - }; - - /* Frees the BAM transaction memory */ -@@ -1708,7 +1739,7 @@ qcom_nandc_read_cw_raw(struct mtd_info * - data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1); - oob_size1 = host->bbm_size; - -- if (qcom_nandc_is_last_cw(ecc, cw)) { -+ if (qcom_nandc_is_last_cw(ecc, cw) && !host->codeword_fixup) { - data_size2 = ecc->size - data_size1 - - ((ecc->steps - 1) * 4); - oob_size2 = (ecc->steps * 4) + host->ecc_bytes_hw + -@@ -1789,7 +1820,7 @@ check_for_erased_page(struct qcom_nand_h - } - - for_each_set_bit(cw, &uncorrectable_cws, ecc->steps) { -- if (qcom_nandc_is_last_cw(ecc, cw)) { -+ if (qcom_nandc_is_last_cw(ecc, cw) && !host->codeword_fixup) { - data_size = ecc->size - ((ecc->steps - 1) * 4); - oob_size = (ecc->steps * 4) + host->ecc_bytes_hw; - } else { -@@ -1947,7 +1978,7 @@ static int read_page_ecc(struct qcom_nan - for (i = 0; i < ecc->steps; i++) { - int data_size, oob_size; - -- if (qcom_nandc_is_last_cw(ecc, i)) { -+ if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) { - data_size = ecc->size - ((ecc->steps - 1) << 2); - oob_size = (ecc->steps << 2) + host->ecc_bytes_hw + - host->spare_bytes; -@@ -2044,6 +2075,69 @@ static int copy_last_cw(struct qcom_nand - return ret; - } - -+static bool qcom_nandc_is_boot_partition(struct qcom_nand_host *host, int page) -+{ -+ struct qcom_nand_boot_partition *boot_partition; -+ u32 start, end; -+ int i; -+ -+ /* -+ * Since the frequent access will be to the non-boot partitions like rootfs, -+ * optimize the page check by: -+ * -+ * 1. Checking if the page lies after the last boot partition. -+ * 2. Checking from the boot partition end. -+ */ -+ -+ /* First check the last boot partition */ -+ boot_partition = &host->boot_partitions[host->nr_boot_partitions - 1]; -+ start = boot_partition->page_offset; -+ end = start + boot_partition->page_size; -+ -+ /* Page is after the last boot partition end. This is NOT a boot partition */ -+ if (page > end) -+ return false; -+ -+ /* Actually check if it's a boot partition */ -+ if (page < end && page >= start) -+ return true; -+ -+ /* Check the other boot partitions starting from the second-last partition */ -+ for (i = host->nr_boot_partitions - 2; i >= 0; i--) { -+ boot_partition = &host->boot_partitions[i]; -+ start = boot_partition->page_offset; -+ end = start + boot_partition->page_size; -+ -+ if (page < end && page >= start) -+ return true; -+ } -+ -+ return false; -+} -+ -+static void qcom_nandc_codeword_fixup(struct qcom_nand_host *host, int page) -+{ -+ bool codeword_fixup = qcom_nandc_is_boot_partition(host, page); -+ -+ /* Skip conf write if we are already in the correct mode */ -+ if (codeword_fixup == host->codeword_fixup) -+ return; -+ -+ host->codeword_fixup = codeword_fixup; -+ -+ host->cw_data = codeword_fixup ? 512 : 516; -+ host->spare_bytes = host->cw_size - host->ecc_bytes_hw - -+ host->bbm_size - host->cw_data; -+ -+ host->cfg0 &= ~(SPARE_SIZE_BYTES_MASK | UD_SIZE_BYTES_MASK); -+ host->cfg0 |= host->spare_bytes << SPARE_SIZE_BYTES | -+ host->cw_data << UD_SIZE_BYTES; -+ -+ host->ecc_bch_cfg &= ~ECC_NUM_DATA_BYTES_MASK; -+ host->ecc_bch_cfg |= host->cw_data << ECC_NUM_DATA_BYTES; -+ host->ecc_buf_cfg = (host->cw_data - 1) << NUM_STEPS; -+} -+ - /* implements ecc->read_page() */ - static int qcom_nandc_read_page(struct nand_chip *chip, uint8_t *buf, - int oob_required, int page) -@@ -2052,6 +2146,9 @@ static int qcom_nandc_read_page(struct n - struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); - u8 *data_buf, *oob_buf = NULL; - -+ if (host->nr_boot_partitions) -+ qcom_nandc_codeword_fixup(host, page); -+ - nand_read_page_op(chip, page, 0, NULL, 0); - data_buf = buf; - oob_buf = oob_required ? chip->oob_poi : NULL; -@@ -2071,6 +2168,9 @@ static int qcom_nandc_read_page_raw(stru - int cw, ret; - u8 *data_buf = buf, *oob_buf = chip->oob_poi; - -+ if (host->nr_boot_partitions) -+ qcom_nandc_codeword_fixup(host, page); -+ - for (cw = 0; cw < ecc->steps; cw++) { - ret = qcom_nandc_read_cw_raw(mtd, chip, data_buf, oob_buf, - page, cw); -@@ -2091,6 +2191,9 @@ static int qcom_nandc_read_oob(struct na - struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); - struct nand_ecc_ctrl *ecc = &chip->ecc; - -+ if (host->nr_boot_partitions) -+ qcom_nandc_codeword_fixup(host, page); -+ - clear_read_regs(nandc); - clear_bam_transaction(nandc); - -@@ -2111,6 +2214,9 @@ static int qcom_nandc_write_page(struct - u8 *data_buf, *oob_buf; - int i, ret; - -+ if (host->nr_boot_partitions) -+ qcom_nandc_codeword_fixup(host, page); -+ - nand_prog_page_begin_op(chip, page, 0, NULL, 0); - - clear_read_regs(nandc); -@@ -2126,7 +2232,7 @@ static int qcom_nandc_write_page(struct - for (i = 0; i < ecc->steps; i++) { - int data_size, oob_size; - -- if (qcom_nandc_is_last_cw(ecc, i)) { -+ if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) { - data_size = ecc->size - ((ecc->steps - 1) << 2); - oob_size = (ecc->steps << 2) + host->ecc_bytes_hw + - host->spare_bytes; -@@ -2183,6 +2289,9 @@ static int qcom_nandc_write_page_raw(str - u8 *data_buf, *oob_buf; - int i, ret; - -+ if (host->nr_boot_partitions) -+ qcom_nandc_codeword_fixup(host, page); -+ - nand_prog_page_begin_op(chip, page, 0, NULL, 0); - clear_read_regs(nandc); - clear_bam_transaction(nandc); -@@ -2201,7 +2310,7 @@ static int qcom_nandc_write_page_raw(str - data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1); - oob_size1 = host->bbm_size; - -- if (qcom_nandc_is_last_cw(ecc, i)) { -+ if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) { - data_size2 = ecc->size - data_size1 - - ((ecc->steps - 1) << 2); - oob_size2 = (ecc->steps << 2) + host->ecc_bytes_hw + -@@ -2261,6 +2370,9 @@ static int qcom_nandc_write_oob(struct n - int data_size, oob_size; - int ret; - -+ if (host->nr_boot_partitions) -+ qcom_nandc_codeword_fixup(host, page); -+ - host->use_ecc = true; - clear_bam_transaction(nandc); - -@@ -2922,6 +3034,74 @@ static int qcom_nandc_setup(struct qcom_ - - static const char * const probes[] = { "cmdlinepart", "ofpart", "qcomsmem", NULL }; - -+static int qcom_nand_host_parse_boot_partitions(struct qcom_nand_controller *nandc, -+ struct qcom_nand_host *host, -+ struct device_node *dn) -+{ -+ struct nand_chip *chip = &host->chip; -+ struct mtd_info *mtd = nand_to_mtd(chip); -+ struct qcom_nand_boot_partition *boot_partition; -+ struct device *dev = nandc->dev; -+ int partitions_count, i, j, ret; -+ -+ if (!of_find_property(dn, "qcom,boot-partitions", NULL)) -+ return 0; -+ -+ partitions_count = of_property_count_u32_elems(dn, "qcom,boot-partitions"); -+ if (partitions_count <= 0) { -+ dev_err(dev, "Error parsing boot partition\n"); -+ return partitions_count ? partitions_count : -EINVAL; -+ } -+ -+ host->nr_boot_partitions = partitions_count / 2; -+ host->boot_partitions = devm_kcalloc(dev, host->nr_boot_partitions, -+ sizeof(*host->boot_partitions), GFP_KERNEL); -+ if (!host->boot_partitions) { -+ host->nr_boot_partitions = 0; -+ return -ENOMEM; -+ } -+ -+ for (i = 0, j = 0; i < host->nr_boot_partitions; i++, j += 2) { -+ boot_partition = &host->boot_partitions[i]; -+ -+ ret = of_property_read_u32_index(dn, "qcom,boot-partitions", j, -+ &boot_partition->page_offset); -+ if (ret) { -+ dev_err(dev, "Error parsing boot partition offset at index %d\n", i); -+ host->nr_boot_partitions = 0; -+ return ret; -+ } -+ -+ if (boot_partition->page_offset % mtd->writesize) { -+ dev_err(dev, "Boot partition offset not multiple of writesize at index %i\n", -+ i); -+ host->nr_boot_partitions = 0; -+ return -EINVAL; -+ } -+ /* Convert offset to nand pages */ -+ boot_partition->page_offset /= mtd->writesize; -+ -+ ret = of_property_read_u32_index(dn, "qcom,boot-partitions", j + 1, -+ &boot_partition->page_size); -+ if (ret) { -+ dev_err(dev, "Error parsing boot partition size at index %d\n", i); -+ host->nr_boot_partitions = 0; -+ return ret; -+ } -+ -+ if (boot_partition->page_size % mtd->writesize) { -+ dev_err(dev, "Boot partition size not multiple of writesize at index %i\n", -+ i); -+ host->nr_boot_partitions = 0; -+ return -EINVAL; -+ } -+ /* Convert size to nand pages */ -+ boot_partition->page_size /= mtd->writesize; -+ } -+ -+ return 0; -+} -+ - static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc, - struct qcom_nand_host *host, - struct device_node *dn) -@@ -2979,6 +3159,14 @@ static int qcom_nand_host_init_and_regis - if (ret) - nand_cleanup(chip); - -+ if (nandc->props->use_codeword_fixup) { -+ ret = qcom_nand_host_parse_boot_partitions(nandc, host, dn); -+ if (ret) { -+ nand_cleanup(chip); -+ return ret; -+ } -+ } -+ - return ret; - } - -@@ -3144,6 +3332,7 @@ static int qcom_nandc_remove(struct plat - static const struct qcom_nandc_props ipq806x_nandc_props = { - .ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT), - .is_bam = false, -+ .use_codeword_fixup = true, - .dev_cmd_reg_start = 0x0, - }; - diff --git a/target/linux/ipq806x/patches-5.15/117-v6.0-01-clk-qcom-clk-hfpll-use-poll_timeout-macro.patch b/target/linux/ipq806x/patches-5.15/117-v6.0-01-clk-qcom-clk-hfpll-use-poll_timeout-macro.patch deleted file mode 100644 index 3008fff9b7f..00000000000 --- a/target/linux/ipq806x/patches-5.15/117-v6.0-01-clk-qcom-clk-hfpll-use-poll_timeout-macro.patch +++ /dev/null @@ -1,41 +0,0 @@ -From fcfbfe373d41b4728ffec075f8f91b6572a88c27 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 30 Apr 2022 07:44:56 +0200 -Subject: [PATCH 1/3] clk: qcom: clk-hfpll: use poll_timeout macro - -Use regmap_read_poll_timeout macro instead of do-while structure to tidy -things up. Also set a timeout to prevent any sort of system stall. - -Signed-off-by: Ansuel Smith -Reviewed-by: Dmitry Baryshkov -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220430054458.31321-2-ansuelsmth@gmail.com ---- - drivers/clk/qcom/clk-hfpll.c | 15 +++++++++------ - 1 file changed, 9 insertions(+), 6 deletions(-) - ---- a/drivers/clk/qcom/clk-hfpll.c -+++ b/drivers/clk/qcom/clk-hfpll.c -@@ -72,13 +72,16 @@ static void __clk_hfpll_enable(struct cl - regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N); - - /* Wait for PLL to lock. */ -- if (hd->status_reg) { -- do { -- regmap_read(regmap, hd->status_reg, &val); -- } while (!(val & BIT(hd->lock_bit))); -- } else { -+ if (hd->status_reg) -+ /* -+ * Busy wait. Should never timeout, we add a timeout to -+ * prevent any sort of stall. -+ */ -+ regmap_read_poll_timeout(regmap, hd->status_reg, val, -+ !(val & BIT(hd->lock_bit)), 0, -+ 100 * USEC_PER_MSEC); -+ else - udelay(60); -- } - - /* Enable PLL output. */ - regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL); diff --git a/target/linux/ipq806x/patches-5.15/117-v6.0-03-clk-qcom-clk-krait-add-apq-ipq8064-errata-workaround.patch b/target/linux/ipq806x/patches-5.15/117-v6.0-03-clk-qcom-clk-krait-add-apq-ipq8064-errata-workaround.patch deleted file mode 100644 index 4012e16f9bc..00000000000 --- a/target/linux/ipq806x/patches-5.15/117-v6.0-03-clk-qcom-clk-krait-add-apq-ipq8064-errata-workaround.patch +++ /dev/null @@ -1,86 +0,0 @@ -From 898d0d6483a9360f1968e0a900465c1fa152a4a9 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 30 Apr 2022 07:44:58 +0200 -Subject: [PATCH 3/3] clk: qcom: clk-krait: add apq/ipq8064 errata workaround - -Add apq/ipq8064 errata workaround where the sec_src clock gating needs to -be disabled during switching. krait-cc compatible is not enough to -handle this and limit this workaround to apq/ipq8064. We check machine -compatible to handle this. - -Signed-off-by: Ansuel Smith -Reviewed-by: Dmitry Baryshkov -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220430054458.31321-4-ansuelsmth@gmail.com ---- - drivers/clk/qcom/clk-krait.c | 16 ++++++++++++++++ - drivers/clk/qcom/clk-krait.h | 1 + - drivers/clk/qcom/krait-cc.c | 8 ++++++++ - 3 files changed, 25 insertions(+) - ---- a/drivers/clk/qcom/clk-krait.c -+++ b/drivers/clk/qcom/clk-krait.c -@@ -18,13 +18,23 @@ - static DEFINE_SPINLOCK(krait_clock_reg_lock); - - #define LPL_SHIFT 8 -+#define SECCLKAGD BIT(4) -+ - static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel) - { - unsigned long flags; - u32 regval; - - spin_lock_irqsave(&krait_clock_reg_lock, flags); -+ - regval = krait_get_l2_indirect_reg(mux->offset); -+ -+ /* apq/ipq8064 Errata: disable sec_src clock gating during switch. */ -+ if (mux->disable_sec_src_gating) { -+ regval |= SECCLKAGD; -+ krait_set_l2_indirect_reg(mux->offset, regval); -+ } -+ - regval &= ~(mux->mask << mux->shift); - regval |= (sel & mux->mask) << mux->shift; - if (mux->lpl) { -@@ -33,6 +43,12 @@ static void __krait_mux_set_sel(struct k - } - krait_set_l2_indirect_reg(mux->offset, regval); - -+ /* apq/ipq8064 Errata: re-enabled sec_src clock gating. */ -+ if (mux->disable_sec_src_gating) { -+ regval &= ~SECCLKAGD; -+ krait_set_l2_indirect_reg(mux->offset, regval); -+ } -+ - /* Wait for switch to complete. */ - mb(); - udelay(1); ---- a/drivers/clk/qcom/clk-krait.h -+++ b/drivers/clk/qcom/clk-krait.h -@@ -15,6 +15,7 @@ struct krait_mux_clk { - u8 safe_sel; - u8 old_index; - bool reparent; -+ bool disable_sec_src_gating; - - struct clk_hw hw; - struct notifier_block clk_nb; ---- a/drivers/clk/qcom/krait-cc.c -+++ b/drivers/clk/qcom/krait-cc.c -@@ -139,6 +139,14 @@ krait_add_sec_mux(struct device *dev, in - mux->hw.init = &init; - mux->safe_sel = 0; - -+ /* Checking for qcom,krait-cc-v1 or qcom,krait-cc-v2 is not -+ * enough to limit this to apq/ipq8064. Directly check machine -+ * compatible to correctly handle this errata. -+ */ -+ if (of_machine_is_compatible("qcom,ipq8064") || -+ of_machine_is_compatible("qcom,apq8064")) -+ mux->disable_sec_src_gating = true; -+ - init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); - if (!init.name) - return -ENOMEM; diff --git a/target/linux/ipq806x/patches-5.15/118-v6.1-03-clk-introduce-devm_-hw_register_mux_parent_data_tabl.patch b/target/linux/ipq806x/patches-5.15/118-v6.1-03-clk-introduce-devm_-hw_register_mux_parent_data_tabl.patch deleted file mode 100644 index 8567d0802bc..00000000000 --- a/target/linux/ipq806x/patches-5.15/118-v6.1-03-clk-introduce-devm_-hw_register_mux_parent_data_tabl.patch +++ /dev/null @@ -1,46 +0,0 @@ -From e4cacac0cae3ce7399b70df3bce92eac03151624 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Tue, 12 Apr 2022 16:48:39 +0200 -Subject: [PATCH 3/4] clk: introduce (devm_)hw_register_mux_parent_data_table - API - -Introduce (devm_)hw_register_mux_parent_data_table new API. We have -basic support for clk_register_mux using parent_data but we lack any API -to provide a custom parent_map. Add these 2 new API to correctly handle -these special configuration instead of using the generic -__(devm_)clk_hw_register_mux API. - -Signed-off-by: Christian Marangi ---- - include/linux/clk-provider.h | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - ---- a/include/linux/clk-provider.h -+++ b/include/linux/clk-provider.h -@@ -955,12 +955,26 @@ struct clk *clk_register_mux_table(struc - __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \ - (parent_data), (flags), (reg), (shift), \ - BIT((width)) - 1, (clk_mux_flags), NULL, (lock)) -+#define clk_hw_register_mux_parent_data_table(dev, name, parent_data, \ -+ num_parents, flags, reg, shift, \ -+ width, clk_mux_flags, table, \ -+ lock) \ -+ __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \ -+ (parent_data), (flags), (reg), (shift), \ -+ BIT((width)) - 1, (clk_mux_flags), table, (lock)) - #define devm_clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \ - shift, width, clk_mux_flags, lock) \ - __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), \ - (parent_names), NULL, NULL, (flags), (reg), \ - (shift), BIT((width)) - 1, (clk_mux_flags), \ - NULL, (lock)) -+#define devm_clk_hw_register_mux_parent_data_table(dev, name, parent_data, \ -+ num_parents, flags, reg, shift, \ -+ width, clk_mux_flags, table, \ -+ lock) \ -+ __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \ -+ NULL, (parent_data), (flags), (reg), (shift), \ -+ BIT((width)) - 1, (clk_mux_flags), table, (lock)) - - int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags, - unsigned int val); diff --git a/target/linux/ipq806x/patches-5.15/118-v6.1-04-clk-qcom-kpss-xcc-convert-to-parent-data-API.patch b/target/linux/ipq806x/patches-5.15/118-v6.1-04-clk-qcom-kpss-xcc-convert-to-parent-data-API.patch deleted file mode 100644 index 6c5f5ea96b2..00000000000 --- a/target/linux/ipq806x/patches-5.15/118-v6.1-04-clk-qcom-kpss-xcc-convert-to-parent-data-API.patch +++ /dev/null @@ -1,70 +0,0 @@ -From d08c79b818767f24c3c9cbba585d8a3ec896c1a1 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 17 Feb 2022 22:43:34 +0100 -Subject: [PATCH 4/4] clk: qcom: kpss-xcc: convert to parent data API - -Convert the driver to parent data API. From the Documentation pll8_vote -and pxo should be declared in the DTS so fw_name can be used instead of -parent_names. Name is still used to save regression on old definition. - -Signed-off-by: Christian Marangi ---- - drivers/clk/qcom/kpss-xcc.c | 26 +++++++++----------------- - 1 file changed, 9 insertions(+), 17 deletions(-) - ---- a/drivers/clk/qcom/kpss-xcc.c -+++ b/drivers/clk/qcom/kpss-xcc.c -@@ -12,9 +12,9 @@ - #include - #include - --static const char *aux_parents[] = { -- "pll8_vote", -- "pxo", -+static const struct clk_parent_data aux_parents[] = { -+ { .name = "pll8_vote", .fw_name = "pll8_vote" }, -+ { .name = "pxo", .fw_name = "pxo" }, - }; - - static unsigned int aux_parent_map[] = { -@@ -32,9 +32,9 @@ MODULE_DEVICE_TABLE(of, kpss_xcc_match_t - static int kpss_xcc_driver_probe(struct platform_device *pdev) - { - const struct of_device_id *id; -- struct clk *clk; - struct resource *res; - void __iomem *base; -+ struct clk_hw *hw; - const char *name; - - id = of_match_device(kpss_xcc_match_table, &pdev->dev); -@@ -57,24 +57,16 @@ static int kpss_xcc_driver_probe(struct - base += 0x28; - } - -- clk = clk_register_mux_table(&pdev->dev, name, aux_parents, -- ARRAY_SIZE(aux_parents), 0, base, 0, 0x3, -- 0, aux_parent_map, NULL); -+ hw = devm_clk_hw_register_mux_parent_data_table(&pdev->dev, name, aux_parents, -+ ARRAY_SIZE(aux_parents), 0, -+ base, 0, 0x3, -+ 0, aux_parent_map, NULL); - -- platform_set_drvdata(pdev, clk); -- -- return PTR_ERR_OR_ZERO(clk); --} -- --static int kpss_xcc_driver_remove(struct platform_device *pdev) --{ -- clk_unregister_mux(platform_get_drvdata(pdev)); -- return 0; -+ return PTR_ERR_OR_ZERO(hw); - } - - static struct platform_driver kpss_xcc_driver = { - .probe = kpss_xcc_driver_probe, -- .remove = kpss_xcc_driver_remove, - .driver = { - .name = "kpss-xcc", - .of_match_table = kpss_xcc_match_table, diff --git a/target/linux/ipq806x/patches-5.15/119-v6.0-02-ARM-dts-qcom-add-rpmcc-missing-clocks-for-apq-ipq806.patch b/target/linux/ipq806x/patches-5.15/119-v6.0-02-ARM-dts-qcom-add-rpmcc-missing-clocks-for-apq-ipq806.patch deleted file mode 100644 index f853b5d2f24..00000000000 --- a/target/linux/ipq806x/patches-5.15/119-v6.0-02-ARM-dts-qcom-add-rpmcc-missing-clocks-for-apq-ipq806.patch +++ /dev/null @@ -1,61 +0,0 @@ -From aa7fd3bb6017b343585e97a909f9b7d2fe174018 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 7 Jul 2022 00:53:19 +0200 -Subject: [PATCH] ARM: dts: qcom: add rpmcc missing clocks for apq/ipq8064 and - msm8660 - -Add missing rpmcc pxo and cxo clock for apq8064, ipq8064 and -msm8660 dtsi. - -Signed-off-by: Christian Marangi -Reviewed-by: Dmitry Baryshkov -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220706225321.26215-3-ansuelsmth@gmail.com ---- - arch/arm/boot/dts/qcom-apq8064.dtsi | 2 ++ - arch/arm/boot/dts/qcom-ipq8064.dtsi | 2 ++ - arch/arm/boot/dts/qcom-msm8660.dtsi | 4 +++- - 3 files changed, 7 insertions(+), 1 deletion(-) - ---- a/arch/arm/boot/dts/qcom-apq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi -@@ -862,6 +862,8 @@ - rpmcc: clock-controller { - compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc"; - #clock-cells = <1>; -+ clocks = <&pxo_board>, <&cxo_board>; -+ clock-names = "pxo", "cxo"; - }; - - regulators { ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -1074,6 +1074,8 @@ - rpmcc: clock-controller { - compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc"; - #clock-cells = <1>; -+ clocks = <&pxo_board>; -+ clock-names = "pxo"; - }; - }; - ---- a/arch/arm/boot/dts/qcom-msm8660.dtsi -+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi -@@ -56,7 +56,7 @@ - clock-frequency = <19200000>; - }; - -- pxo_board { -+ pxo_board: pxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; -@@ -420,6 +420,8 @@ - rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc"; - #clock-cells = <1>; -+ clocks = <&pxo_board>; -+ clock-names = "pxo"; - }; - - pm8901-regulators { diff --git a/target/linux/ipq806x/patches-5.15/119-v6.0-03-clk-qcom-clk-rpm-convert-to-parent_data-API.patch b/target/linux/ipq806x/patches-5.15/119-v6.0-03-clk-qcom-clk-rpm-convert-to-parent_data-API.patch deleted file mode 100644 index 8481b636708..00000000000 --- a/target/linux/ipq806x/patches-5.15/119-v6.0-03-clk-qcom-clk-rpm-convert-to-parent_data-API.patch +++ /dev/null @@ -1,78 +0,0 @@ -From 129d9cd9c25041f8b8681fd6e8584fa47c385f3b Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 7 Jul 2022 00:53:20 +0200 -Subject: [PATCH] clk: qcom: clk-rpm: convert to parent_data API - -Convert clk-rpm driver to parent_data API. -We keep the old pxo/cxo_board parent naming to keep compatibility with -old DT and we use the new pxo/cxo for new implementation where these -clock are defined in DTS. - -Signed-off-by: Christian Marangi -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220706225321.26215-4-ansuelsmth@gmail.com ---- - drivers/clk/qcom/clk-rpm.c | 24 ++++++++++++++++-------- - 1 file changed, 16 insertions(+), 8 deletions(-) - ---- a/drivers/clk/qcom/clk-rpm.c -+++ b/drivers/clk/qcom/clk-rpm.c -@@ -23,6 +23,14 @@ - #define QCOM_RPM_SCALING_ENABLE_ID 0x2 - #define QCOM_RPM_XO_MODE_ON 0x2 - -+static const struct clk_parent_data gcc_pxo[] = { -+ { .fw_name = "pxo", .name = "pxo_board" }, -+}; -+ -+static const struct clk_parent_data gcc_cxo[] = { -+ { .fw_name = "cxo", .name = "cxo_board" }, -+}; -+ - #define DEFINE_CLK_RPM(_platform, _name, _active, r_id) \ - static struct clk_rpm _platform##_##_active; \ - static struct clk_rpm _platform##_##_name = { \ -@@ -32,8 +40,8 @@ - .hw.init = &(struct clk_init_data){ \ - .ops = &clk_rpm_ops, \ - .name = #_name, \ -- .parent_names = (const char *[]){ "pxo_board" }, \ -- .num_parents = 1, \ -+ .parent_data = gcc_pxo, \ -+ .num_parents = ARRAY_SIZE(gcc_pxo), \ - }, \ - }; \ - static struct clk_rpm _platform##_##_active = { \ -@@ -44,8 +52,8 @@ - .hw.init = &(struct clk_init_data){ \ - .ops = &clk_rpm_ops, \ - .name = #_active, \ -- .parent_names = (const char *[]){ "pxo_board" }, \ -- .num_parents = 1, \ -+ .parent_data = gcc_pxo, \ -+ .num_parents = ARRAY_SIZE(gcc_pxo), \ - }, \ - } - -@@ -56,8 +64,8 @@ - .hw.init = &(struct clk_init_data){ \ - .ops = &clk_rpm_xo_ops, \ - .name = #_name, \ -- .parent_names = (const char *[]){ "cxo_board" }, \ -- .num_parents = 1, \ -+ .parent_data = gcc_cxo, \ -+ .num_parents = ARRAY_SIZE(gcc_cxo), \ - }, \ - } - -@@ -68,8 +76,8 @@ - .hw.init = &(struct clk_init_data){ \ - .ops = &clk_rpm_fixed_ops, \ - .name = #_name, \ -- .parent_names = (const char *[]){ "pxo" }, \ -- .num_parents = 1, \ -+ .parent_data = gcc_pxo, \ -+ .num_parents = ARRAY_SIZE(gcc_pxo), \ - }, \ - } - diff --git a/target/linux/ipq806x/patches-5.15/120-v6.2-clk-qcom-kpss-xcc-register-it-as-clk-provider.patch b/target/linux/ipq806x/patches-5.15/120-v6.2-clk-qcom-kpss-xcc-register-it-as-clk-provider.patch deleted file mode 100644 index ace313663d5..00000000000 --- a/target/linux/ipq806x/patches-5.15/120-v6.2-clk-qcom-kpss-xcc-register-it-as-clk-provider.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 09be1a39e685d8c5edd471fd1cac9a8f8280d2de Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Tue, 8 Nov 2022 22:17:34 +0100 -Subject: [PATCH] clk: qcom: kpss-xcc: register it as clk provider - -krait-cc use this driver for the secondary mux. Register it as a clk -provider to correctly use this clk in other drivers. - -Signed-off-by: Christian Marangi -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20221108211734.3707-1-ansuelsmth@gmail.com ---- - drivers/clk/qcom/kpss-xcc.c | 13 +++++++++---- - 1 file changed, 9 insertions(+), 4 deletions(-) - ---- a/drivers/clk/qcom/kpss-xcc.c -+++ b/drivers/clk/qcom/kpss-xcc.c -@@ -31,13 +31,14 @@ MODULE_DEVICE_TABLE(of, kpss_xcc_match_t - - static int kpss_xcc_driver_probe(struct platform_device *pdev) - { -+ struct device *dev = &pdev->dev; - const struct of_device_id *id; - struct resource *res; - void __iomem *base; - struct clk_hw *hw; - const char *name; - -- id = of_match_device(kpss_xcc_match_table, &pdev->dev); -+ id = of_match_device(kpss_xcc_match_table, dev); - if (!id) - return -ENODEV; - -@@ -47,7 +48,7 @@ static int kpss_xcc_driver_probe(struct - return PTR_ERR(base); - - if (id->data) { -- if (of_property_read_string_index(pdev->dev.of_node, -+ if (of_property_read_string_index(dev->of_node, - "clock-output-names", - 0, &name)) - return -ENODEV; -@@ -57,12 +58,16 @@ static int kpss_xcc_driver_probe(struct - base += 0x28; - } - -- hw = devm_clk_hw_register_mux_parent_data_table(&pdev->dev, name, aux_parents, -+ hw = devm_clk_hw_register_mux_parent_data_table(dev, name, aux_parents, - ARRAY_SIZE(aux_parents), 0, - base, 0, 0x3, - 0, aux_parent_map, NULL); -+ if (IS_ERR(hw)) -+ return PTR_ERR(hw); - -- return PTR_ERR_OR_ZERO(hw); -+ of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, hw); -+ -+ return 0; - } - - static struct platform_driver kpss_xcc_driver = { diff --git a/target/linux/ipq806x/patches-5.15/121-v6.2-01-clk-qcom-krait-cc-use-devm-variant-for-clk-notifier-.patch b/target/linux/ipq806x/patches-5.15/121-v6.2-01-clk-qcom-krait-cc-use-devm-variant-for-clk-notifier-.patch deleted file mode 100644 index 65c1fc17f21..00000000000 --- a/target/linux/ipq806x/patches-5.15/121-v6.2-01-clk-qcom-krait-cc-use-devm-variant-for-clk-notifier-.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 3198106a99e73dbc4c02bd5128cec0997c73af82 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Tue, 8 Nov 2022 22:58:27 +0100 -Subject: [PATCH 1/6] clk: qcom: krait-cc: use devm variant for clk notifier - register - -Use devm variant for clk notifier register and correctly handle free -resource on driver remove. - -Signed-off-by: Christian Marangi -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20221108215827.30475-1-ansuelsmth@gmail.com ---- - drivers/clk/qcom/krait-cc.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/clk/qcom/krait-cc.c -+++ b/drivers/clk/qcom/krait-cc.c -@@ -62,7 +62,7 @@ static int krait_notifier_register(struc - int ret = 0; - - mux->clk_nb.notifier_call = krait_notifier_cb; -- ret = clk_notifier_register(clk, &mux->clk_nb); -+ ret = devm_clk_notifier_register(dev, clk, &mux->clk_nb); - if (ret) - dev_err(dev, "failed to register clock notifier: %d\n", ret); - diff --git a/target/linux/ipq806x/patches-5.15/121-v6.2-02-clk-qcom-krait-cc-fix-wrong-parent-order-for-seconda.patch b/target/linux/ipq806x/patches-5.15/121-v6.2-02-clk-qcom-krait-cc-fix-wrong-parent-order-for-seconda.patch deleted file mode 100644 index 2dcb69399cf..00000000000 --- a/target/linux/ipq806x/patches-5.15/121-v6.2-02-clk-qcom-krait-cc-fix-wrong-parent-order-for-seconda.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 8e456411abcbf899c04740b9dbb3dcefcd61c946 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Wed, 9 Nov 2022 01:56:27 +0100 -Subject: [PATCH 2/6] clk: qcom: krait-cc: fix wrong parent order for secondary - mux - -The secondary mux parent order is swapped. -This currently doesn't cause problems as the secondary mux is used for idle -clk and as a safe clk source while reprogramming the hfpll. - -Each mux have 2 or more output but he always have a safe source to -switch while reprogramming the connected pll. We use a clk notifier to -switch to the correct parent before clk core can apply the correct rate. -The parent to switch is hardcoded in the mux struct. - -For the secondary mux the safe source to use is the qsb parent as it's -the only fixed clk as the acpus_aux is a pll that can source from pxo or -from pll8. - -The hardcoded safe parent for the secondary mux is set to index 0 that -in the secondary mux map is set to 2. - -But the index 0 is actually acpu_aux in the parent list. - -Fix the swapped parents to correctly handle idle frequency and output a -sane clk_summary report. - -Signed-off-by: Christian Marangi -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20221109005631.3189-1-ansuelsmth@gmail.com ---- - drivers/clk/qcom/krait-cc.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/clk/qcom/krait-cc.c -+++ b/drivers/clk/qcom/krait-cc.c -@@ -116,8 +116,8 @@ krait_add_sec_mux(struct device *dev, in - int ret; - struct krait_mux_clk *mux; - static const char *sec_mux_list[] = { -- "acpu_aux", - "qsb", -+ "acpu_aux", - }; - struct clk_init_data init = { - .parent_names = sec_mux_list, diff --git a/target/linux/ipq806x/patches-5.15/121-v6.2-03-clk-qcom-krait-cc-also-enable-secondary-mux-and-div-.patch b/target/linux/ipq806x/patches-5.15/121-v6.2-03-clk-qcom-krait-cc-also-enable-secondary-mux-and-div-.patch deleted file mode 100644 index 6261a940d71..00000000000 --- a/target/linux/ipq806x/patches-5.15/121-v6.2-03-clk-qcom-krait-cc-also-enable-secondary-mux-and-div-.patch +++ /dev/null @@ -1,68 +0,0 @@ -From 18ae57b1e8abee6c453381470f6e18991d2901a8 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Wed, 9 Nov 2022 01:56:28 +0100 -Subject: [PATCH 3/6] clk: qcom: krait-cc: also enable secondary mux and div - clk - -clk-krait ignore any rate change if clk is not flagged as enabled. -Correctly enable the secondary mux and div clk to correctly change rate -instead of silently ignoring the request. - -Signed-off-by: Christian Marangi -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20221109005631.3189-2-ansuelsmth@gmail.com ---- - drivers/clk/qcom/krait-cc.c | 21 ++++++++++++++++++++- - 1 file changed, 20 insertions(+), 1 deletion(-) - ---- a/drivers/clk/qcom/krait-cc.c -+++ b/drivers/clk/qcom/krait-cc.c -@@ -80,6 +80,7 @@ krait_add_div(struct device *dev, int id - }; - const char *p_names[1]; - struct clk *clk; -+ int cpu; - - div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); - if (!div) -@@ -103,6 +104,17 @@ krait_add_div(struct device *dev, int id - } - - clk = devm_clk_register(dev, &div->hw); -+ if (IS_ERR(clk)) -+ goto err; -+ -+ /* clk-krait ignore any rate change if mux is not flagged as enabled */ -+ if (id < 0) -+ for_each_online_cpu(cpu) -+ clk_prepare_enable(div->hw.clk); -+ else -+ clk_prepare_enable(div->hw.clk); -+ -+err: - kfree(p_names[0]); - kfree(init.name); - -@@ -113,7 +125,7 @@ static int - krait_add_sec_mux(struct device *dev, int id, const char *s, - unsigned int offset, bool unique_aux) - { -- int ret; -+ int cpu, ret; - struct krait_mux_clk *mux; - static const char *sec_mux_list[] = { - "qsb", -@@ -165,6 +177,13 @@ krait_add_sec_mux(struct device *dev, in - if (ret) - goto unique_aux; - -+ /* clk-krait ignore any rate change if mux is not flagged as enabled */ -+ if (id < 0) -+ for_each_online_cpu(cpu) -+ clk_prepare_enable(mux->hw.clk); -+ else -+ clk_prepare_enable(mux->hw.clk); -+ - unique_aux: - if (unique_aux) - kfree(sec_mux_list[0]); diff --git a/target/linux/ipq806x/patches-5.15/121-v6.2-04-clk-qcom-krait-cc-handle-secondary-mux-sourcing-out-.patch b/target/linux/ipq806x/patches-5.15/121-v6.2-04-clk-qcom-krait-cc-handle-secondary-mux-sourcing-out-.patch deleted file mode 100644 index fabb299f427..00000000000 --- a/target/linux/ipq806x/patches-5.15/121-v6.2-04-clk-qcom-krait-cc-handle-secondary-mux-sourcing-out-.patch +++ /dev/null @@ -1,48 +0,0 @@ -From e5dc1a4c01510da8438dddfdf4200b79d73990dc Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Wed, 9 Nov 2022 01:56:29 +0100 -Subject: [PATCH 4/6] clk: qcom: krait-cc: handle secondary mux sourcing out of - acpu_aux - -Some bootloader may leave the system in an even more undefined state -with the secondary mux of L2 or other cores sourcing out of the acpu_aux -parent. This results in the clk set to the PXO rate or a PLL8 rate. - -The current logic to reset the mux and set them to a defined state only -handle if the mux are configured to source out of QSB. Change this and -force a new and defined state if the current clk is lower than the aux -rate. This way we can handle any wrong configuration where the mux is -sourcing out of QSB (rate 225MHz, currently set to a virtual rate of 1), -PXO rate (rate 25MHz) or PLL8 (needs to be configured to run at 384Mhz). - -Signed-off-by: Christian Marangi -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20221109005631.3189-3-ansuelsmth@gmail.com ---- - drivers/clk/qcom/krait-cc.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - ---- a/drivers/clk/qcom/krait-cc.c -+++ b/drivers/clk/qcom/krait-cc.c -@@ -383,8 +383,8 @@ static int krait_cc_probe(struct platfor - */ - cur_rate = clk_get_rate(l2_pri_mux_clk); - aux_rate = 384000000; -- if (cur_rate == 1) { -- pr_info("L2 @ QSB rate. Forcing new rate.\n"); -+ if (cur_rate < aux_rate) { -+ pr_info("L2 @ Undefined rate. Forcing new rate.\n"); - cur_rate = aux_rate; - } - clk_set_rate(l2_pri_mux_clk, aux_rate); -@@ -394,8 +394,8 @@ static int krait_cc_probe(struct platfor - for_each_possible_cpu(cpu) { - clk = clks[cpu]; - cur_rate = clk_get_rate(clk); -- if (cur_rate == 1) { -- pr_info("CPU%d @ QSB rate. Forcing new rate.\n", cpu); -+ if (cur_rate < aux_rate) { -+ pr_info("CPU%d @ Undefined rate. Forcing new rate.\n", cpu); - cur_rate = aux_rate; - } - diff --git a/target/linux/ipq806x/patches-5.15/121-v6.2-05-clk-qcom-krait-cc-convert-to-devm_clk_hw_register.patch b/target/linux/ipq806x/patches-5.15/121-v6.2-05-clk-qcom-krait-cc-convert-to-devm_clk_hw_register.patch deleted file mode 100644 index 049b1fa49f1..00000000000 --- a/target/linux/ipq806x/patches-5.15/121-v6.2-05-clk-qcom-krait-cc-convert-to-devm_clk_hw_register.patch +++ /dev/null @@ -1,104 +0,0 @@ -From 8ea9fb841a7e528bc8ae79d726ce951dcf7b46e2 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Wed, 9 Nov 2022 01:56:30 +0100 -Subject: [PATCH 5/6] clk: qcom: krait-cc: convert to devm_clk_hw_register - -clk_register is now deprecated. Convert the driver to devm_clk_hw_register. - -Signed-off-by: Christian Marangi -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20221109005631.3189-4-ansuelsmth@gmail.com ---- - drivers/clk/qcom/krait-cc.c | 31 +++++++++++++++++++------------ - 1 file changed, 19 insertions(+), 12 deletions(-) - ---- a/drivers/clk/qcom/krait-cc.c -+++ b/drivers/clk/qcom/krait-cc.c -@@ -79,8 +79,7 @@ krait_add_div(struct device *dev, int id - .flags = CLK_SET_RATE_PARENT, - }; - const char *p_names[1]; -- struct clk *clk; -- int cpu; -+ int cpu, ret; - - div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); - if (!div) -@@ -103,8 +102,8 @@ krait_add_div(struct device *dev, int id - return -ENOMEM; - } - -- clk = devm_clk_register(dev, &div->hw); -- if (IS_ERR(clk)) -+ ret = devm_clk_hw_register(dev, &div->hw); -+ if (ret) - goto err; - - /* clk-krait ignore any rate change if mux is not flagged as enabled */ -@@ -118,7 +117,7 @@ err: - kfree(p_names[0]); - kfree(init.name); - -- return PTR_ERR_OR_ZERO(clk); -+ return ret; - } - - static int -@@ -137,7 +136,6 @@ krait_add_sec_mux(struct device *dev, in - .ops = &krait_mux_clk_ops, - .flags = CLK_SET_RATE_PARENT, - }; -- struct clk *clk; - - mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); - if (!mux) -@@ -166,14 +164,16 @@ krait_add_sec_mux(struct device *dev, in - if (unique_aux) { - sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s); - if (!sec_mux_list[0]) { -- clk = ERR_PTR(-ENOMEM); -+ ret = -ENOMEM; - goto err_aux; - } - } - -- clk = devm_clk_register(dev, &mux->hw); -+ ret = devm_clk_hw_register(dev, &mux->hw); -+ if (ret) -+ goto unique_aux; - -- ret = krait_notifier_register(dev, clk, mux); -+ ret = krait_notifier_register(dev, mux->hw.clk, mux); - if (ret) - goto unique_aux; - -@@ -189,7 +189,7 @@ unique_aux: - kfree(sec_mux_list[0]); - err_aux: - kfree(init.name); -- return PTR_ERR_OR_ZERO(clk); -+ return ret; - } - - static struct clk * -@@ -241,11 +241,18 @@ krait_add_pri_mux(struct device *dev, in - goto err_p2; - } - -- clk = devm_clk_register(dev, &mux->hw); -+ ret = devm_clk_hw_register(dev, &mux->hw); -+ if (ret) { -+ clk = ERR_PTR(ret); -+ goto err_p3; -+ } -+ -+ clk = mux->hw.clk; - - ret = krait_notifier_register(dev, clk, mux); - if (ret) -- goto err_p3; -+ clk = ERR_PTR(ret); -+ - err_p3: - kfree(p_names[2]); - err_p2: diff --git a/target/linux/ipq806x/patches-5.15/121-v6.2-06-clk-qcom-krait-cc-convert-to-parent_data-API.patch b/target/linux/ipq806x/patches-5.15/121-v6.2-06-clk-qcom-krait-cc-convert-to-parent_data-API.patch deleted file mode 100644 index 453a37dfc08..00000000000 --- a/target/linux/ipq806x/patches-5.15/121-v6.2-06-clk-qcom-krait-cc-convert-to-parent_data-API.patch +++ /dev/null @@ -1,414 +0,0 @@ -From 56a655e1c41a86445cf2de656649ad93424b2a63 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Wed, 9 Nov 2022 01:56:31 +0100 -Subject: [PATCH 6/6] clk: qcom: krait-cc: convert to parent_data API - -Modernize the krait-cc driver to parent-data API and refactor to drop -any use of parent_names. From Documentation all the required clocks should -be declared in DTS so fw_name can be correctly used to get the parents -for all the muxes. .name is also declared to save compatibility with old -DT. - -While at it also drop some hardcoded index and introduce an enum to make -index values more clear. - -Signed-off-by: Christian Marangi -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20221109005631.3189-5-ansuelsmth@gmail.com ---- - drivers/clk/qcom/krait-cc.c | 202 ++++++++++++++++++++---------------- - 1 file changed, 112 insertions(+), 90 deletions(-) - ---- a/drivers/clk/qcom/krait-cc.c -+++ b/drivers/clk/qcom/krait-cc.c -@@ -15,6 +15,16 @@ - - #include "clk-krait.h" - -+enum { -+ cpu0_mux = 0, -+ cpu1_mux, -+ cpu2_mux, -+ cpu3_mux, -+ l2_mux, -+ -+ clks_max, -+}; -+ - static unsigned int sec_mux_map[] = { - 2, - 0, -@@ -69,21 +79,23 @@ static int krait_notifier_register(struc - return ret; - } - --static int -+static struct clk_hw * - krait_add_div(struct device *dev, int id, const char *s, unsigned int offset) - { - struct krait_div2_clk *div; -+ static struct clk_parent_data p_data[1]; - struct clk_init_data init = { -- .num_parents = 1, -+ .num_parents = ARRAY_SIZE(p_data), - .ops = &krait_div2_clk_ops, - .flags = CLK_SET_RATE_PARENT, - }; -- const char *p_names[1]; -+ struct clk_hw *clk; -+ char *parent_name; - int cpu, ret; - - div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); - if (!div) -- return -ENOMEM; -+ return ERR_PTR(-ENOMEM); - - div->width = 2; - div->shift = 6; -@@ -93,18 +105,25 @@ krait_add_div(struct device *dev, int id - - init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s); - if (!init.name) -- return -ENOMEM; -+ return ERR_PTR(-ENOMEM); - -- init.parent_names = p_names; -- p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s); -- if (!p_names[0]) { -- kfree(init.name); -- return -ENOMEM; -+ init.parent_data = p_data; -+ parent_name = kasprintf(GFP_KERNEL, "hfpll%s", s); -+ if (!parent_name) { -+ clk = ERR_PTR(-ENOMEM); -+ goto err_parent_name; - } - -+ p_data[0].fw_name = parent_name; -+ p_data[0].name = parent_name; -+ - ret = devm_clk_hw_register(dev, &div->hw); -- if (ret) -- goto err; -+ if (ret) { -+ clk = ERR_PTR(ret); -+ goto err_clk; -+ } -+ -+ clk = &div->hw; - - /* clk-krait ignore any rate change if mux is not flagged as enabled */ - if (id < 0) -@@ -113,33 +132,36 @@ krait_add_div(struct device *dev, int id - else - clk_prepare_enable(div->hw.clk); - --err: -- kfree(p_names[0]); -+err_clk: -+ kfree(parent_name); -+err_parent_name: - kfree(init.name); - -- return ret; -+ return clk; - } - --static int -+static struct clk_hw * - krait_add_sec_mux(struct device *dev, int id, const char *s, - unsigned int offset, bool unique_aux) - { - int cpu, ret; - struct krait_mux_clk *mux; -- static const char *sec_mux_list[] = { -- "qsb", -- "acpu_aux", -+ static struct clk_parent_data sec_mux_list[2] = { -+ { .name = "qsb", .fw_name = "qsb" }, -+ {}, - }; - struct clk_init_data init = { -- .parent_names = sec_mux_list, -+ .parent_data = sec_mux_list, - .num_parents = ARRAY_SIZE(sec_mux_list), - .ops = &krait_mux_clk_ops, - .flags = CLK_SET_RATE_PARENT, - }; -+ struct clk_hw *clk; -+ char *parent_name; - - mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); - if (!mux) -- return -ENOMEM; -+ return ERR_PTR(-ENOMEM); - - mux->offset = offset; - mux->lpl = id >= 0; -@@ -159,23 +181,33 @@ krait_add_sec_mux(struct device *dev, in - - init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); - if (!init.name) -- return -ENOMEM; -+ return ERR_PTR(-ENOMEM); - - if (unique_aux) { -- sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s); -- if (!sec_mux_list[0]) { -- ret = -ENOMEM; -+ parent_name = kasprintf(GFP_KERNEL, "acpu%s_aux", s); -+ if (!parent_name) { -+ clk = ERR_PTR(-ENOMEM); - goto err_aux; - } -+ sec_mux_list[1].fw_name = parent_name; -+ sec_mux_list[1].name = parent_name; -+ } else { -+ sec_mux_list[1].name = "apu_aux"; - } - - ret = devm_clk_hw_register(dev, &mux->hw); -- if (ret) -- goto unique_aux; -+ if (ret) { -+ clk = ERR_PTR(ret); -+ goto err_clk; -+ } -+ -+ clk = &mux->hw; - - ret = krait_notifier_register(dev, mux->hw.clk, mux); -- if (ret) -- goto unique_aux; -+ if (ret) { -+ clk = ERR_PTR(ret); -+ goto err_clk; -+ } - - /* clk-krait ignore any rate change if mux is not flagged as enabled */ - if (id < 0) -@@ -184,28 +216,29 @@ krait_add_sec_mux(struct device *dev, in - else - clk_prepare_enable(mux->hw.clk); - --unique_aux: -+err_clk: - if (unique_aux) -- kfree(sec_mux_list[0]); -+ kfree(parent_name); - err_aux: - kfree(init.name); -- return ret; -+ return clk; - } - --static struct clk * --krait_add_pri_mux(struct device *dev, int id, const char *s, -- unsigned int offset) -+static struct clk_hw * -+krait_add_pri_mux(struct device *dev, struct clk_hw *hfpll_div, struct clk_hw *sec_mux, -+ int id, const char *s, unsigned int offset) - { - int ret; - struct krait_mux_clk *mux; -- const char *p_names[3]; -+ static struct clk_parent_data p_data[3]; - struct clk_init_data init = { -- .parent_names = p_names, -- .num_parents = ARRAY_SIZE(p_names), -+ .parent_data = p_data, -+ .num_parents = ARRAY_SIZE(p_data), - .ops = &krait_mux_clk_ops, - .flags = CLK_SET_RATE_PARENT, - }; -- struct clk *clk; -+ struct clk_hw *clk; -+ char *hfpll_name; - - mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); - if (!mux) -@@ -223,55 +256,44 @@ krait_add_pri_mux(struct device *dev, in - if (!init.name) - return ERR_PTR(-ENOMEM); - -- p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s); -- if (!p_names[0]) { -+ hfpll_name = kasprintf(GFP_KERNEL, "hfpll%s", s); -+ if (!hfpll_name) { - clk = ERR_PTR(-ENOMEM); -- goto err_p0; -+ goto err_hfpll; - } - -- p_names[1] = kasprintf(GFP_KERNEL, "hfpll%s_div", s); -- if (!p_names[1]) { -- clk = ERR_PTR(-ENOMEM); -- goto err_p1; -- } -+ p_data[0].fw_name = hfpll_name; -+ p_data[0].name = hfpll_name; - -- p_names[2] = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); -- if (!p_names[2]) { -- clk = ERR_PTR(-ENOMEM); -- goto err_p2; -- } -+ p_data[1].hw = hfpll_div; -+ p_data[2].hw = sec_mux; - - ret = devm_clk_hw_register(dev, &mux->hw); - if (ret) { - clk = ERR_PTR(ret); -- goto err_p3; -+ goto err_clk; - } - -- clk = mux->hw.clk; -+ clk = &mux->hw; - -- ret = krait_notifier_register(dev, clk, mux); -+ ret = krait_notifier_register(dev, mux->hw.clk, mux); - if (ret) - clk = ERR_PTR(ret); - --err_p3: -- kfree(p_names[2]); --err_p2: -- kfree(p_names[1]); --err_p1: -- kfree(p_names[0]); --err_p0: -+err_clk: -+ kfree(hfpll_name); -+err_hfpll: - kfree(init.name); - return clk; - } - - /* id < 0 for L2, otherwise id == physical CPU number */ --static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux) -+static struct clk_hw *krait_add_clks(struct device *dev, int id, bool unique_aux) - { -- int ret; -+ struct clk_hw *hfpll_div, *sec_mux, *pri_mux; - unsigned int offset; - void *p = NULL; - const char *s; -- struct clk *clk; - - if (id >= 0) { - offset = 0x4501 + (0x1000 * id); -@@ -283,22 +305,23 @@ static struct clk *krait_add_clks(struct - s = "_l2"; - } - -- ret = krait_add_div(dev, id, s, offset); -- if (ret) { -- clk = ERR_PTR(ret); -+ hfpll_div = krait_add_div(dev, id, s, offset); -+ if (IS_ERR(hfpll_div)) { -+ pri_mux = hfpll_div; - goto err; - } - -- ret = krait_add_sec_mux(dev, id, s, offset, unique_aux); -- if (ret) { -- clk = ERR_PTR(ret); -+ sec_mux = krait_add_sec_mux(dev, id, s, offset, unique_aux); -+ if (IS_ERR(sec_mux)) { -+ pri_mux = sec_mux; - goto err; - } - -- clk = krait_add_pri_mux(dev, id, s, offset); -+ pri_mux = krait_add_pri_mux(dev, hfpll_div, sec_mux, id, s, offset); -+ - err: - kfree(p); -- return clk; -+ return pri_mux; - } - - static struct clk *krait_of_get(struct of_phandle_args *clkspec, void *data) -@@ -306,7 +329,7 @@ static struct clk *krait_of_get(struct o - unsigned int idx = clkspec->args[0]; - struct clk **clks = data; - -- if (idx >= 5) { -+ if (idx >= clks_max) { - pr_err("%s: invalid clock index %d\n", __func__, idx); - return ERR_PTR(-EINVAL); - } -@@ -327,9 +350,8 @@ static int krait_cc_probe(struct platfor - const struct of_device_id *id; - unsigned long cur_rate, aux_rate; - int cpu; -- struct clk *clk; -- struct clk **clks; -- struct clk *l2_pri_mux_clk; -+ struct clk_hw *mux, *l2_pri_mux; -+ struct clk *clk, **clks; - - id = of_match_device(krait_cc_match_table, dev); - if (!id) -@@ -348,21 +370,21 @@ static int krait_cc_probe(struct platfor - } - - /* Krait configurations have at most 4 CPUs and one L2 */ -- clks = devm_kcalloc(dev, 5, sizeof(*clks), GFP_KERNEL); -+ clks = devm_kcalloc(dev, clks_max, sizeof(*clks), GFP_KERNEL); - if (!clks) - return -ENOMEM; - - for_each_possible_cpu(cpu) { -- clk = krait_add_clks(dev, cpu, id->data); -+ mux = krait_add_clks(dev, cpu, id->data); - if (IS_ERR(clk)) - return PTR_ERR(clk); -- clks[cpu] = clk; -+ clks[cpu] = mux->clk; - } - -- l2_pri_mux_clk = krait_add_clks(dev, -1, id->data); -- if (IS_ERR(l2_pri_mux_clk)) -- return PTR_ERR(l2_pri_mux_clk); -- clks[4] = l2_pri_mux_clk; -+ l2_pri_mux = krait_add_clks(dev, -1, id->data); -+ if (IS_ERR(l2_pri_mux)) -+ return PTR_ERR(l2_pri_mux); -+ clks[l2_mux] = l2_pri_mux->clk; - - /* - * We don't want the CPU or L2 clocks to be turned off at late init -@@ -372,7 +394,7 @@ static int krait_cc_probe(struct platfor - * they take over. - */ - for_each_online_cpu(cpu) { -- clk_prepare_enable(l2_pri_mux_clk); -+ clk_prepare_enable(clks[l2_mux]); - WARN(clk_prepare_enable(clks[cpu]), - "Unable to turn on CPU%d clock", cpu); - } -@@ -388,16 +410,16 @@ static int krait_cc_probe(struct platfor - * two different rates to force a HFPLL reinit under all - * circumstances. - */ -- cur_rate = clk_get_rate(l2_pri_mux_clk); -+ cur_rate = clk_get_rate(clks[l2_mux]); - aux_rate = 384000000; - if (cur_rate < aux_rate) { - pr_info("L2 @ Undefined rate. Forcing new rate.\n"); - cur_rate = aux_rate; - } -- clk_set_rate(l2_pri_mux_clk, aux_rate); -- clk_set_rate(l2_pri_mux_clk, 2); -- clk_set_rate(l2_pri_mux_clk, cur_rate); -- pr_info("L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000); -+ clk_set_rate(clks[l2_mux], aux_rate); -+ clk_set_rate(clks[l2_mux], 2); -+ clk_set_rate(clks[l2_mux], cur_rate); -+ pr_info("L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000); - for_each_possible_cpu(cpu) { - clk = clks[cpu]; - cur_rate = clk_get_rate(clk); diff --git a/target/linux/ipq806x/patches-5.15/122-01-clk-qcom-krait-cc-handle-qsb-clock-defined-in-DTS.patch b/target/linux/ipq806x/patches-5.15/122-01-clk-qcom-krait-cc-handle-qsb-clock-defined-in-DTS.patch deleted file mode 100644 index c30c245d0a5..00000000000 --- a/target/linux/ipq806x/patches-5.15/122-01-clk-qcom-krait-cc-handle-qsb-clock-defined-in-DTS.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 666c1b745e93ccddde841d5057c33f97b29a316a Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 15 Sep 2022 02:19:28 +0200 -Subject: [PATCH 3/9] clk: qcom: krait-cc: handle qsb clock defined in DTS - -qsb fixed clk may be defined in DTS and correctly passed in the clocks -list. Add related code to handle this and modify the logic to -dynamically read qsb clock frequency. - -Signed-off-by: Christian Marangi ---- - drivers/clk/qcom/krait-cc.c | 14 +++++++++++--- - 1 file changed, 11 insertions(+), 3 deletions(-) - ---- a/drivers/clk/qcom/krait-cc.c -+++ b/drivers/clk/qcom/krait-cc.c -@@ -348,7 +348,7 @@ static int krait_cc_probe(struct platfor - { - struct device *dev = &pdev->dev; - const struct of_device_id *id; -- unsigned long cur_rate, aux_rate; -+ unsigned long cur_rate, aux_rate, qsb_rate; - int cpu; - struct clk_hw *mux, *l2_pri_mux; - struct clk *clk, **clks; -@@ -357,11 +357,19 @@ static int krait_cc_probe(struct platfor - if (!id) - return -ENODEV; - -- /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */ -- clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); -+ /* -+ * Per Documentation qsb should be provided from DTS. -+ * To address old implementation, register the fixed clock anyway. -+ * Rate is 1 because 0 causes problems for __clk_mux_determine_rate -+ */ -+ clk = clk_get(dev, "qsb"); -+ if (IS_ERR(clk)) -+ clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); - if (IS_ERR(clk)) - return PTR_ERR(clk); - -+ qsb_rate = clk_get_rate(clk); -+ - if (!id->data) { - clk = clk_register_fixed_factor(dev, "acpu_aux", - "gpll0_vote", 0, 1, 2); diff --git a/target/linux/ipq806x/patches-5.15/122-02-clk-qcom-krait-cc-register-REAL-qsb-fixed-clock.patch b/target/linux/ipq806x/patches-5.15/122-02-clk-qcom-krait-cc-register-REAL-qsb-fixed-clock.patch deleted file mode 100644 index e2f78f79fb1..00000000000 --- a/target/linux/ipq806x/patches-5.15/122-02-clk-qcom-krait-cc-register-REAL-qsb-fixed-clock.patch +++ /dev/null @@ -1,36 +0,0 @@ -From fca6f185a9d9ef0892a719bc6da955b22d326ec7 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 15 Sep 2022 02:24:33 +0200 -Subject: [PATCH 4/9] clk: qcom: krait-cc: register REAL qsb fixed clock - -With some tools it was discovered the real frequency of the qsb fixed -clock. While not 100% correct it's still better than using 1 as a dummy -frequency. -Correctly register the qsb fixed clock with the frequency of 225 MHz -instead of 1. - -Signed-off-by: Christian Marangi ---- - drivers/clk/qcom/krait-cc.c | 8 +++++--- - 1 file changed, 5 insertions(+), 3 deletions(-) - ---- a/drivers/clk/qcom/krait-cc.c -+++ b/drivers/clk/qcom/krait-cc.c -@@ -25,6 +25,8 @@ enum { - clks_max, - }; - -+#define QSB_RATE 2250000000 -+ - static unsigned int sec_mux_map[] = { - 2, - 0, -@@ -364,7 +366,7 @@ static int krait_cc_probe(struct platfor - */ - clk = clk_get(dev, "qsb"); - if (IS_ERR(clk)) -- clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); -+ clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, QSB_RATE); - if (IS_ERR(clk)) - return PTR_ERR(clk); - diff --git a/target/linux/ipq806x/patches-5.15/122-03-clk-qcom-krait-cc-drop-pr_info-and-use-dev_info.patch b/target/linux/ipq806x/patches-5.15/122-03-clk-qcom-krait-cc-drop-pr_info-and-use-dev_info.patch deleted file mode 100644 index d95a63fc44f..00000000000 --- a/target/linux/ipq806x/patches-5.15/122-03-clk-qcom-krait-cc-drop-pr_info-and-use-dev_info.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 2399d181557d94ae9a2686926cd25768f132e4b4 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Fri, 18 Mar 2022 16:12:14 +0100 -Subject: [PATCH 7/9] clk: qcom: krait-cc: drop pr_info and use dev_info - -Replace pr_info() with dev_info() to provide better diagnostics. - -Signed-off-by: Christian Marangi ---- - drivers/clk/qcom/krait-cc.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - ---- a/drivers/clk/qcom/krait-cc.c -+++ b/drivers/clk/qcom/krait-cc.c -@@ -423,25 +423,25 @@ static int krait_cc_probe(struct platfor - cur_rate = clk_get_rate(clks[l2_mux]); - aux_rate = 384000000; - if (cur_rate < aux_rate) { -- pr_info("L2 @ Undefined rate. Forcing new rate.\n"); -+ dev_info(dev, "L2 @ Undefined rate. Forcing new rate.\n"); - cur_rate = aux_rate; - } - clk_set_rate(clks[l2_mux], aux_rate); - clk_set_rate(clks[l2_mux], 2); - clk_set_rate(clks[l2_mux], cur_rate); -- pr_info("L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000); -+ dev_info(dev, "L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000); - for_each_possible_cpu(cpu) { - clk = clks[cpu]; - cur_rate = clk_get_rate(clk); - if (cur_rate < aux_rate) { -- pr_info("CPU%d @ Undefined rate. Forcing new rate.\n", cpu); -+ dev_info(dev, "CPU%d @ Undefined rate. Forcing new rate.\n", cpu); - cur_rate = aux_rate; - } - - clk_set_rate(clk, aux_rate); - clk_set_rate(clk, 2); - clk_set_rate(clk, cur_rate); -- pr_info("CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000); -+ dev_info(dev, "CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000); - } - - of_clk_add_provider(dev->of_node, krait_of_get, clks); diff --git a/target/linux/ipq806x/patches-5.15/122-04-clk-qcom-krait-cc-rework-mux-reset-logic-and-reset-h.patch b/target/linux/ipq806x/patches-5.15/122-04-clk-qcom-krait-cc-rework-mux-reset-logic-and-reset-h.patch deleted file mode 100644 index 8f88e069912..00000000000 --- a/target/linux/ipq806x/patches-5.15/122-04-clk-qcom-krait-cc-rework-mux-reset-logic-and-reset-h.patch +++ /dev/null @@ -1,88 +0,0 @@ -From 6a77cf3f5f95ec0058e1b4d1ada018748cb0b83b Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 15 Sep 2022 03:33:13 +0200 -Subject: [PATCH 9/9] clk: qcom: krait-cc: rework mux reset logic and reset - hfpll - -Rework and clean mux reset logic. -Compact it to a for loop to handle both CPU and L2 in one place. -Move hardcoded aux_rate to define and add a new hfpll_rate value to -reset hfpll settings. -Change logic to now reset the hfpll to the lowest value of 600 Mhz and -then restoring the previous frequency. This permits to reset the hfpll if -the primary mux was set to source out of the secondary mux. - -Signed-off-by: Christian Marangi ---- - drivers/clk/qcom/krait-cc.c | 50 +++++++++++++++++-------------------- - 1 file changed, 23 insertions(+), 27 deletions(-) - ---- a/drivers/clk/qcom/krait-cc.c -+++ b/drivers/clk/qcom/krait-cc.c -@@ -25,7 +25,9 @@ enum { - clks_max, - }; - --#define QSB_RATE 2250000000 -+#define QSB_RATE 225000000 -+#define AUX_RATE 384000000 -+#define HFPLL_RATE 600000000 - - static unsigned int sec_mux_map[] = { - 2, -@@ -350,7 +352,7 @@ static int krait_cc_probe(struct platfor - { - struct device *dev = &pdev->dev; - const struct of_device_id *id; -- unsigned long cur_rate, aux_rate, qsb_rate; -+ unsigned long cur_rate, qsb_rate; - int cpu; - struct clk_hw *mux, *l2_pri_mux; - struct clk *clk, **clks; -@@ -420,28 +422,29 @@ static int krait_cc_probe(struct platfor - * two different rates to force a HFPLL reinit under all - * circumstances. - */ -- cur_rate = clk_get_rate(clks[l2_mux]); -- aux_rate = 384000000; -- if (cur_rate < aux_rate) { -- dev_info(dev, "L2 @ Undefined rate. Forcing new rate.\n"); -- cur_rate = aux_rate; -- } -- clk_set_rate(clks[l2_mux], aux_rate); -- clk_set_rate(clks[l2_mux], 2); -- clk_set_rate(clks[l2_mux], cur_rate); -- dev_info(dev, "L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000); -- for_each_possible_cpu(cpu) { -+ for (cpu = 0; cpu < 5; cpu++) { -+ const char *l2_s = "L2"; -+ char cpu_s[5]; -+ - clk = clks[cpu]; -+ if (!clk) -+ continue; -+ -+ if (cpu < 4) -+ snprintf(cpu_s, 5, "CPU%d", cpu); -+ - cur_rate = clk_get_rate(clk); -- if (cur_rate < aux_rate) { -- dev_info(dev, "CPU%d @ Undefined rate. Forcing new rate.\n", cpu); -- cur_rate = aux_rate; -+ if (cur_rate < AUX_RATE) { -+ dev_info(dev, "%s @ Undefined rate. Forcing new rate.\n", -+ cpu < 4 ? cpu_s : l2_s); -+ cur_rate = AUX_RATE; - } - -- clk_set_rate(clk, aux_rate); -- clk_set_rate(clk, 2); -+ clk_set_rate(clk, AUX_RATE); -+ clk_set_rate(clk, HFPLL_RATE); - clk_set_rate(clk, cur_rate); -- dev_info(dev, "CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000); -+ dev_info(dev, "%s @ %lu KHz\n", cpu < 4 ? cpu_s : l2_s, -+ clk_get_rate(clk) / 1000); - } - - of_clk_add_provider(dev->of_node, krait_of_get, clks); diff --git a/target/linux/ipq806x/patches-5.15/122-05-clk-qcom-clk-krait-generilize-div-functions.patch b/target/linux/ipq806x/patches-5.15/122-05-clk-qcom-clk-krait-generilize-div-functions.patch deleted file mode 100644 index a7c0f046c84..00000000000 --- a/target/linux/ipq806x/patches-5.15/122-05-clk-qcom-clk-krait-generilize-div-functions.patch +++ /dev/null @@ -1,156 +0,0 @@ -From 908c361b3c3a139eb3e6a798cb620a6da7514d5c Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Fri, 23 Sep 2022 19:05:39 +0200 -Subject: [PATCH 2/4] clk: qcom: clk-krait: generilize div functions - -Generilize div functions and remove hardcode to a divisor of 2. -This is just a cleanup and permit to make it more clear the settings of -the devisor when used by the krait-cc driver. - -Signed-off-by: Christian Marangi ---- - drivers/clk/qcom/clk-krait.c | 57 ++++++++++++++++++++---------------- - drivers/clk/qcom/clk-krait.h | 11 ++++--- - drivers/clk/qcom/krait-cc.c | 7 +++-- - 3 files changed, 42 insertions(+), 33 deletions(-) - ---- a/drivers/clk/qcom/clk-krait.c -+++ b/drivers/clk/qcom/clk-krait.c -@@ -97,53 +97,58 @@ const struct clk_ops krait_mux_clk_ops = - EXPORT_SYMBOL_GPL(krait_mux_clk_ops); - - /* The divider can divide by 2, 4, 6 and 8. But we only really need div-2. */ --static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate, -+static long krait_div_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) - { -- *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2); -- return DIV_ROUND_UP(*parent_rate, 2); -+ struct krait_div_clk *d = to_krait_div_clk(hw); -+ -+ *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), -+ rate * d->divisor); -+ -+ return DIV_ROUND_UP(*parent_rate, d->divisor); - } - --static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate, -+static int krait_div_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) - { -- struct krait_div2_clk *d = to_krait_div2_clk(hw); -+ struct krait_div_clk *d = to_krait_div_clk(hw); -+ u8 div_val = krait_div_to_val(d->divisor); - unsigned long flags; -- u32 val; -- u32 mask = BIT(d->width) - 1; -- -- if (d->lpl) -- mask = mask << (d->shift + LPL_SHIFT) | mask << d->shift; -- else -- mask <<= d->shift; -+ u32 regval; - - spin_lock_irqsave(&krait_clock_reg_lock, flags); -- val = krait_get_l2_indirect_reg(d->offset); -- val &= ~mask; -- krait_set_l2_indirect_reg(d->offset, val); -+ regval = krait_get_l2_indirect_reg(d->offset); -+ -+ regval &= ~(d->mask << d->shift); -+ regval |= (div_val & d->mask) << d->shift; -+ -+ if (d->lpl) { -+ regval &= ~(d->mask << (d->shift + LPL_SHIFT)); -+ regval |= (div_val & d->mask) << (d->shift + LPL_SHIFT); -+ } -+ -+ krait_set_l2_indirect_reg(d->offset, regval); - spin_unlock_irqrestore(&krait_clock_reg_lock, flags); - - return 0; - } - - static unsigned long --krait_div2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) -+krait_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) - { -- struct krait_div2_clk *d = to_krait_div2_clk(hw); -- u32 mask = BIT(d->width) - 1; -+ struct krait_div_clk *d = to_krait_div_clk(hw); - u32 div; - - div = krait_get_l2_indirect_reg(d->offset); - div >>= d->shift; -- div &= mask; -- div = (div + 1) * 2; -+ div &= d->mask; - -- return DIV_ROUND_UP(parent_rate, div); -+ return DIV_ROUND_UP(parent_rate, krait_val_to_div(div)); - } - --const struct clk_ops krait_div2_clk_ops = { -- .round_rate = krait_div2_round_rate, -- .set_rate = krait_div2_set_rate, -- .recalc_rate = krait_div2_recalc_rate, -+const struct clk_ops krait_div_clk_ops = { -+ .round_rate = krait_div_round_rate, -+ .set_rate = krait_div_set_rate, -+ .recalc_rate = krait_div_recalc_rate, - }; --EXPORT_SYMBOL_GPL(krait_div2_clk_ops); -+EXPORT_SYMBOL_GPL(krait_div_clk_ops); ---- a/drivers/clk/qcom/clk-krait.h -+++ b/drivers/clk/qcom/clk-krait.h -@@ -25,17 +25,20 @@ struct krait_mux_clk { - - extern const struct clk_ops krait_mux_clk_ops; - --struct krait_div2_clk { -+struct krait_div_clk { - u32 offset; -- u8 width; -+ u32 mask; -+ u8 divisor; - u32 shift; - bool lpl; - - struct clk_hw hw; - }; - --#define to_krait_div2_clk(_hw) container_of(_hw, struct krait_div2_clk, hw) -+#define to_krait_div_clk(_hw) container_of(_hw, struct krait_div_clk, hw) -+#define krait_div_to_val(_div) ((_div) / 2) - 1 -+#define krait_val_to_div(_val) ((_val) + 1) * 2 - --extern const struct clk_ops krait_div2_clk_ops; -+extern const struct clk_ops krait_div_clk_ops; - - #endif ---- a/drivers/clk/qcom/krait-cc.c -+++ b/drivers/clk/qcom/krait-cc.c -@@ -86,11 +86,11 @@ static int krait_notifier_register(struc - static struct clk_hw * - krait_add_div(struct device *dev, int id, const char *s, unsigned int offset) - { -- struct krait_div2_clk *div; -+ struct krait_div_clk *div; - static struct clk_parent_data p_data[1]; - struct clk_init_data init = { - .num_parents = ARRAY_SIZE(p_data), -- .ops = &krait_div2_clk_ops, -+ .ops = &krait_div_clk_ops, - .flags = CLK_SET_RATE_PARENT, - }; - struct clk_hw *clk; -@@ -101,7 +101,8 @@ krait_add_div(struct device *dev, int id - if (!div) - return ERR_PTR(-ENOMEM); - -- div->width = 2; -+ div->mask = 0x3; -+ div->divisor = 2; - div->shift = 6; - div->lpl = id >= 0; - div->offset = offset; diff --git a/target/linux/ipq806x/patches-5.15/123-clk-qcom-gcc-ipq806x-remove-cc_register_board-for.patch b/target/linux/ipq806x/patches-5.15/123-clk-qcom-gcc-ipq806x-remove-cc_register_board-for.patch deleted file mode 100644 index 20e7440ace8..00000000000 --- a/target/linux/ipq806x/patches-5.15/123-clk-qcom-gcc-ipq806x-remove-cc_register_board-for.patch +++ /dev/null @@ -1,31 +0,0 @@ -From ac84ac819a2e8fd3d87122b452c502a386c54437 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Tue, 5 Jul 2022 18:30:18 +0200 -Subject: [PATCH v2 4/4] clk: qcom: gcc-ipq806x: remove cc_register_board for - pxo and cxo - -Now that these clock are defined as fixed clk in dts, we can drop the -register_board_clk for cxo_board and pxo_board in gcc_ipq806x_probe. - -Signed-off-by: Christian Marangi ---- - drivers/clk/qcom/gcc-ipq806x.c | 8 -------- - 1 file changed, 8 deletions(-) - ---- a/drivers/clk/qcom/gcc-ipq806x.c -+++ b/drivers/clk/qcom/gcc-ipq806x.c -@@ -3384,14 +3384,6 @@ static int gcc_ipq806x_probe(struct plat - struct regmap *regmap; - int ret; - -- ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 25000000); -- if (ret) -- return ret; -- -- ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 25000000); -- if (ret) -- return ret; -- - if (of_machine_is_compatible("qcom,ipq8065")) { - ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8065; - ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8065; diff --git a/target/linux/ipq806x/patches-5.15/130-6.1-mtd-rawnand-qcom-handle-ret-from-parse-with-codeword.patch b/target/linux/ipq806x/patches-5.15/130-6.1-mtd-rawnand-qcom-handle-ret-from-parse-with-codeword.patch deleted file mode 100644 index 2e7e6833bb8..00000000000 --- a/target/linux/ipq806x/patches-5.15/130-6.1-mtd-rawnand-qcom-handle-ret-from-parse-with-codeword.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 7df140e84a75c89962feef659d686303d3ce75e5 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Fri, 21 Oct 2022 18:53:04 +0200 -Subject: [PATCH] mtd: rawnand: qcom: handle ret from parse with codeword_fixup - -With use_codeword_fixup enabled, any return from -mtd_device_parse_register gets overwritten. Aside from the clear bug, this -is also problematic as a parser can EPROBE_DEFER and because this is not -correctly handled, the nand is never rescanned later in the bootup -process. - -An example of this problem is when smem requires additional time to be -probed and nandc use qcomsmempart as parser. Parser will return -EPROBE_DEFER but in the current code this ret gets overwritten by -qcom_nand_host_parse_boot_partitions and qcom_nand_host_init_and_register -return 0. - -Correctly handle the return code from mtd_device_parse_register so that -any error from this function is not ignored. - -Fixes: 862bdedd7f4b ("mtd: nand: raw: qcom_nandc: add support for unprotected spare data pages") -Cc: stable@vger.kernel.org # v6.0+ -Signed-off-by: Christian Marangi -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20221021165304.19991-1-ansuelsmth@gmail.com ---- - drivers/mtd/nand/raw/qcom_nandc.c | 12 +++++++----- - 1 file changed, 7 insertions(+), 5 deletions(-) - ---- a/drivers/mtd/nand/raw/qcom_nandc.c -+++ b/drivers/mtd/nand/raw/qcom_nandc.c -@@ -3157,16 +3157,18 @@ static int qcom_nand_host_init_and_regis - - ret = mtd_device_parse_register(mtd, probes, NULL, NULL, 0); - if (ret) -- nand_cleanup(chip); -+ goto err; - - if (nandc->props->use_codeword_fixup) { - ret = qcom_nand_host_parse_boot_partitions(nandc, host, dn); -- if (ret) { -- nand_cleanup(chip); -- return ret; -- } -+ if (ret) -+ goto err; - } - -+ return 0; -+ -+err: -+ nand_cleanup(chip); - return ret; - } - diff --git a/target/linux/ipq806x/patches-5.15/131-6.2-ARM-dts-qcom-ipq8064-disable-mmc-ddr-1_8v-for-sdcc1.patch b/target/linux/ipq806x/patches-5.15/131-6.2-ARM-dts-qcom-ipq8064-disable-mmc-ddr-1_8v-for-sdcc1.patch deleted file mode 100644 index 8493f380fe0..00000000000 --- a/target/linux/ipq806x/patches-5.15/131-6.2-ARM-dts-qcom-ipq8064-disable-mmc-ddr-1_8v-for-sdcc1.patch +++ /dev/null @@ -1,28 +0,0 @@ -From c9713e4ede1e5d044b64fe4d3cbb84223625637f Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Tue, 25 Oct 2022 01:38:17 +0200 -Subject: [PATCH] ARM: dts: qcom: ipq8064: disable mmc-ddr-1_8v for sdcc1 - -It was reported non working mmc with this option enabled. -Both mmc for ipq8064 are supplied by a fixed 3.3v regulator so mmc can't -be run at 1.8v. -Disable it to restore correct functionality of this SoC feature. - -Tested-by: Hendrik Koerner -Signed-off-by: Christian Marangi -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20221024233817.27410-1-ansuelsmth@gmail.com ---- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 1 - - 1 file changed, 1 deletion(-) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -1529,7 +1529,6 @@ - non-removable; - cap-sd-highspeed; - cap-mmc-highspeed; -- mmc-ddr-1_8v; - vmmc-supply = <&vsdcc_fixed>; - dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; - dma-names = "tx", "rx"; diff --git a/target/linux/ipq806x/patches-5.15/850-soc-add-qualcomm-syscon.patch b/target/linux/ipq806x/patches-5.15/850-soc-add-qualcomm-syscon.patch deleted file mode 100644 index 0d983410ec1..00000000000 --- a/target/linux/ipq806x/patches-5.15/850-soc-add-qualcomm-syscon.patch +++ /dev/null @@ -1,121 +0,0 @@ -From: Christian Lamparter -Subject: SoC: add qualcomm syscon ---- a/drivers/soc/qcom/Makefile -+++ b/drivers/soc/qcom/Makefile -@@ -21,6 +21,7 @@ obj-$(CONFIG_QCOM_SMP2P) += smp2p.o - obj-$(CONFIG_QCOM_SMSM) += smsm.o - obj-$(CONFIG_QCOM_SOCINFO) += socinfo.o - obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o -+obj-$(CONFIG_QCOM_TCSR) += qcom_tcsr.o - obj-$(CONFIG_QCOM_APR) += apr.o - obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o - obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o ---- a/drivers/soc/qcom/Kconfig -+++ b/drivers/soc/qcom/Kconfig -@@ -192,6 +192,13 @@ config QCOM_SOCINFO - Say yes here to support the Qualcomm socinfo driver, providing - information about the SoC to user space. - -+config QCOM_TCSR -+ tristate "QCOM Top Control and Status Registers" -+ depends on ARCH_QCOM -+ help -+ Say y here to enable TCSR support. The TCSR provides control -+ functions for various peripherals. -+ - config QCOM_WCNSS_CTRL - tristate "Qualcomm WCNSS control driver" - depends on ARCH_QCOM || COMPILE_TEST ---- /dev/null -+++ b/drivers/soc/qcom/qcom_tcsr.c -@@ -0,0 +1,64 @@ -+/* -+ * Copyright (c) 2014, The Linux foundation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License rev 2 and -+ * only rev 2 as published by the free Software foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define TCSR_USB_PORT_SEL 0xb0 -+ -+static int tcsr_probe(struct platform_device *pdev) -+{ -+ struct resource *res; -+ const struct device_node *node = pdev->dev.of_node; -+ void __iomem *base; -+ u32 val; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ base = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(base)) -+ return PTR_ERR(base); -+ -+ if (!of_property_read_u32(node, "qcom,usb-ctrl-select", &val)) { -+ dev_err(&pdev->dev, "setting usb port select = %d\n", val); -+ writel(val, base + TCSR_USB_PORT_SEL); -+ } -+ -+ return 0; -+} -+ -+static const struct of_device_id tcsr_dt_match[] = { -+ { .compatible = "qcom,tcsr", }, -+ { }, -+}; -+ -+MODULE_DEVICE_TABLE(of, tcsr_dt_match); -+ -+static struct platform_driver tcsr_driver = { -+ .driver = { -+ .name = "tcsr", -+ .owner = THIS_MODULE, -+ .of_match_table = tcsr_dt_match, -+ }, -+ .probe = tcsr_probe, -+}; -+ -+module_platform_driver(tcsr_driver); -+ -+MODULE_AUTHOR("Andy Gross "); -+MODULE_DESCRIPTION("QCOM TCSR driver"); -+MODULE_LICENSE("GPL v2"); ---- /dev/null -+++ b/include/dt-bindings/soc/qcom,tcsr.h -@@ -0,0 +1,23 @@ -+/* Copyright (c) 2014, The Linux Foundation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 and -+ * only version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+#ifndef __DT_BINDINGS_QCOM_TCSR_H -+#define __DT_BINDINGS_QCOM_TCSR_H -+ -+#define TCSR_USB_SELECT_USB3_P0 0x1 -+#define TCSR_USB_SELECT_USB3_P1 0x2 -+#define TCSR_USB_SELECT_USB3_DUAL 0x3 -+ -+/* TCSR A/B REG */ -+#define IPQ806X_TCSR_REG_A_ADM_CRCI_MUX_SEL 0 -+#define IPQ806X_TCSR_REG_B_ADM_CRCI_MUX_SEL 1 -+ -+#endif diff --git a/target/linux/ipq806x/patches-5.15/900-arm-add-cmdline-override.patch b/target/linux/ipq806x/patches-5.15/900-arm-add-cmdline-override.patch deleted file mode 100644 index 23cec10f445..00000000000 --- a/target/linux/ipq806x/patches-5.15/900-arm-add-cmdline-override.patch +++ /dev/null @@ -1,37 +0,0 @@ ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -1740,6 +1740,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGL - - endchoice - -+config CMDLINE_OVERRIDE -+ bool "Use alternative cmdline from device tree" -+ help -+ Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can -+ be used, this is not a good option for kernels that are shared across -+ devices. This setting enables using "chosen/cmdline-override" as the -+ cmdline if it exists in the device tree. -+ - config CMDLINE - string "Default kernel command string" - default "" ---- a/drivers/of/fdt.c -+++ b/drivers/of/fdt.c -@@ -1162,6 +1162,17 @@ int __init early_init_dt_scan_chosen(uns - if (p != NULL && l > 0) - strlcat(data, p, min_t(int, strlen(data) + (int)l, COMMAND_LINE_SIZE)); - -+ /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different -+ * device tree option of chosen/bootargs-override. This is -+ * helpful on boards where u-boot sets bootargs, and is unable -+ * to be modified. -+ */ -+#ifdef CONFIG_CMDLINE_OVERRIDE -+ p = of_get_flat_dt_prop(node, "bootargs-override", &l); -+ if (p != NULL && l > 0) -+ strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE)); -+#endif -+ - /* - * CONFIG_CMDLINE is meant to be a default in case nothing else - * managed to set the command line, unless CONFIG_CMDLINE_FORCE diff --git a/target/linux/ipq806x/patches-6.1/140-v6.5-hwspinlock-qcom-add-missing-regmap-config-for-SFPB-M.patch b/target/linux/ipq806x/patches-6.1/140-v6.5-hwspinlock-qcom-add-missing-regmap-config-for-SFPB-M.patch new file mode 100644 index 00000000000..faa9044d338 --- /dev/null +++ b/target/linux/ipq806x/patches-6.1/140-v6.5-hwspinlock-qcom-add-missing-regmap-config-for-SFPB-M.patch @@ -0,0 +1,49 @@ +From 23316be8a9d450f33a21f1efe7d89570becbec58 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Sun, 16 Jul 2023 04:28:04 +0200 +Subject: [PATCH] hwspinlock: qcom: add missing regmap config for SFPB MMIO + implementation + +Commit 5d4753f741d8 ("hwspinlock: qcom: add support for MMIO on older +SoCs") introduced and made regmap_config mandatory in the of_data struct +but didn't add the regmap_config for sfpb based devices. + +SFPB based devices can both use the legacy syscon way to probe or the +new MMIO way and currently device that use the MMIO way are broken as +they lack the definition of the now required regmap_config and always +return -EINVAL (and indirectly makes fail probing everything that +depends on it, smem, nandc with smem-parser...) + +Fix this by correctly adding the missing regmap_config and restore +function of hwspinlock on SFPB based devices with MMIO implementation. + +Cc: stable@vger.kernel.org +Fixes: 5d4753f741d8 ("hwspinlock: qcom: add support for MMIO on older SoCs") +Signed-off-by: Christian Marangi +Link: https://lore.kernel.org/r/20230716022804.21239-1-ansuelsmth@gmail.com +Signed-off-by: Bjorn Andersson +--- + drivers/hwspinlock/qcom_hwspinlock.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/drivers/hwspinlock/qcom_hwspinlock.c ++++ b/drivers/hwspinlock/qcom_hwspinlock.c +@@ -69,9 +69,18 @@ static const struct hwspinlock_ops qcom_ + .unlock = qcom_hwspinlock_unlock, + }; + ++static const struct regmap_config sfpb_mutex_config = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = 0x100, ++ .fast_io = true, ++}; ++ + static const struct qcom_hwspinlock_of_data of_sfpb_mutex = { + .offset = 0x4, + .stride = 0x4, ++ .regmap_config = &sfpb_mutex_config, + }; + + static const struct regmap_config tcsr_msm8226_mutex_config = { diff --git a/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-wr30u-112m-nmbm.dts b/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-wr30u-112m-nmbm.dts new file mode 100644 index 00000000000..7244cdfd610 --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-wr30u-112m-nmbm.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; +#include "mt7981b-xiaomi-mi-router-wr30u.dtsi" + +/ { + model = "Xiaomi Mi Router WR30U (112M UBI with NMBM-Enabled layout)"; + compatible = "xiaomi,mi-router-wr30u-112m-nmbm", "mediatek,mt7981"; +}; + +&spi_nand { + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <64>; +}; + +&partitions { + partition@600000 { + label = "ubi"; + reg = <0x600000 0x7000000>; + }; +}; diff --git a/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-wr30u-stock.dts b/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-wr30u-stock.dts new file mode 100644 index 00000000000..7faa6e84ef8 --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-wr30u-stock.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; +#include "mt7981b-xiaomi-mi-router-wr30u.dtsi" + +/ { + model = "Xiaomi Mi Router WR30U (stock layout)"; + compatible = "xiaomi,mi-router-wr30u-stock", "mediatek,mt7981"; +}; + +&spi_nand { + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <64>; +}; + +&partitions { + // ubi_kernel is the ubi partition in stock. + partition@600000 { + label = "ubi_kernel"; + reg = <0x600000 0x2200000>; + }; + + /* ubi is the result of squashing + * consecutive stock partitions: + * - ubi1 + * - overlay + * - data + */ + partition@2800000 { + label = "ubi"; + reg = <0x2800000 0x4e00000>; + }; +}; diff --git a/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-wr30u-ubootmod.dts b/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-wr30u-ubootmod.dts new file mode 100644 index 00000000000..6d0f3feb45b --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-wr30u-ubootmod.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; +#include "mt7981b-xiaomi-mi-router-wr30u.dtsi" + +/ { + model = "Xiaomi Mi Router WR30U (OpenWrt U-Boot layout)"; + compatible = "xiaomi,mi-router-wr30u-ubootmod", "mediatek,mt7981"; +}; + +&partitions { + partition@600000 { + label = "ubi"; + reg = <0x600000 0x7000000>; + }; +}; diff --git a/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-wr30u.dtsi b/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-wr30u.dtsi new file mode 100644 index 00000000000..9467b18a7e0 --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-wr30u.dtsi @@ -0,0 +1,249 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; +#include +#include + +#include "mt7981.dtsi" + +/ { + aliases { + serial0 = &uart0; + led-boot = &led_system_yellow; + led-failsafe = &led_system_yellow; + led-running = &led_system_blue; + led-upgrade = &led_system_yellow; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0 0x40000000 0 0x10000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + mesh { + label = "mesh"; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_system_blue: system_blue { + label = "blue:system"; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + + led_system_yellow: system_yellow { + label = "yellow:system"; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + + led_network_blue { + label = "blue:network"; + gpios = <&pio 11 GPIO_ACTIVE_LOW>; + }; + + led_network_yellow { + label = "yellow:network"; + gpios = <&pio 12 GPIO_ACTIVE_LOW>; + }; + }; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + nvmem-cells = <&macaddr_factory_4>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <(-1)>; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; +}; + +&mdio_bus { + switch: switch@0 { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "wan"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + status = "okay"; + + spi_nand: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + reg = <0>; + + spi-max-frequency = <52000000>; + spi-tx-buswidth = <4>; + spi-rx-buswidth = <4>; + + partitions: partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "BL2"; + reg = <0x00 0x100000>; + read-only; + }; + + partition@100000 { + label = "Nvram"; + reg = <0x100000 0x40000>; + }; + + partition@140000 { + label = "Bdata"; + reg = <0x140000 0x40000>; + }; + + factory: partition@180000 { + label = "Factory"; + reg = <0x180000 0x200000>; + read-only; + + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_factory_4: macaddr@4 { + reg = <0x4 0x6>; + }; + }; + + partition@380000 { + label = "FIP"; + reg = <0x380000 0x200000>; + read-only; + }; + + partition@580000 { + label = "crash"; + reg = <0x580000 0x40000>; + read-only; + }; + + partition@5c0000 { + label = "crash_log"; + reg = <0x5c0000 0x40000>; + read-only; + }; + + partition@7600000 { + label = "KF"; + reg = <0x7600000 0x40000>; + read-only; + }; + }; + }; +}; + +&pio { + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + + conf-pu { + pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; + drive-strength = ; + bias-pull-up = ; + }; + + conf-pd { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; + drive-strength = ; + bias-pull-down = ; + }; + }; +}; + +&wifi { + status = "okay"; + + mediatek,mtd-eeprom = <&factory 0x0>; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; diff --git a/target/linux/mediatek/dts/mt7981b-zyxel-nwa50ax-pro.dts b/target/linux/mediatek/dts/mt7981b-zyxel-nwa50ax-pro.dts new file mode 100644 index 00000000000..6ca7ba040a1 --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-zyxel-nwa50ax-pro.dts @@ -0,0 +1,226 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/dts-v1/; + +#include "mt7981.dtsi" + +/ { + model = "ZyXEL NWA50AX Pro"; + compatible = "zyxel,nwa50ax-pro", "mediatek,mt7981"; + + aliases { + led-boot = &led_green; + led-failsafe = &led_red; + led-running = &led_green; + led-upgrade = &led_red; + serial0 = &uart0; + label-mac-device = &gmac1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = ; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_green: led@0 { + label = "green:system"; + gpios = <&pio 4 GPIO_ACTIVE_HIGH>; + }; + + led@1 { + label = "blue:system"; + gpios = <&pio 6 GPIO_ACTIVE_HIGH>; + }; + + led_red: led@2 { + label = "red:system"; + gpios = <&pio 7 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + + status = "okay"; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; + + phy-handle = <&phy0>; + + nvmem-cells = <&macaddr_mrd_1fff8>; + nvmem-cell-names = "mac-address"; + }; +}; + +&mdio_bus { + reset-gpios = <&pio 12 GPIO_ACTIVE_LOW>; + reset-delay-us = <1500000>; + reset-post-delay-us = <1000000>; + + phy0: ethernet-phy@5 { + reg = <5>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + status = "okay"; + + spi_nand: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <52000000>; + + spi-cal-enable; + spi-cal-mode = "read-data"; + spi-cal-datalen = <7>; + spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; + spi-cal-addrlen = <5>; + spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; + + spi-tx-buswidth = <4>; + spi-rx-buswidth = <4>; + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <64>; + + mediatek,bmt-remap-range = + <0x0 0x580000>, + <0xef00000 0xef80000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "BL2"; + reg = <0x00000 0x0100000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env"; + reg = <0x0100000 0x0080000>; + }; + + factory: partition@180000 { + label = "Factory"; + reg = <0x180000 0x0200000>; + read-only; + + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr: macaddr@a { + reg = <0xa 0x6>; + }; + }; + + partition@380000 { + label = "FIP"; + reg = <0x380000 0x0200000>; + read-only; + }; + + partition@580000 { + label = "ubi"; + reg = <0x580000 0x3200000>; + }; + + partition@3780000 { + label = "ubi_1"; + reg = <0x3780000 0x3200000>; + read-only; + }; + + partition@6980000 { + label = "rootfs-data"; + reg = <0x6980000 0x3c00000>; + read-only; + }; + + partition@a580000 { + label = "logs"; + reg = <0xa580000 0x3a80000>; + read-only; + }; + + partition@e000000 { + label = "myzyxel"; + reg = <0xe000000 0xf00000>; + read-only; + }; + + partition@ef00000 { + label = "bootconfig"; + reg = <0xef00000 0x80000>; + }; + + partition@ef80000 { + label = "mrd"; + reg = <0xef80000 0x80000>; + read-only; + + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_mrd_1fff8: macaddr@1fff8 { + reg = <0x1fff8 0x6>; + }; + }; + }; + }; +}; + +&pio { + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + + pwm_pins: pwm0-pins { + mux { + function = "pwm"; + groups = "pwm0_1"; + }; + }; +}; + +&wifi { + status = "okay"; + + mediatek,mtd-eeprom = <&factory 0x0>; +}; diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds b/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds index c81bd2cd975..ea126bc46f9 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds @@ -20,6 +20,11 @@ netgear,wax220) ucidef_set_led_netdev "wlan2g" "WLAN2G" "blue:wlan2g" "phy0-ap0" ucidef_set_led_netdev "wlan5g" "WLAN5G" "blue:wlan5g" "phy1-ap0" ;; +xiaomi,mi-router-wr30u-112m-nmbm|\ +xiaomi,mi-router-wr30u-stock|\ +xiaomi,mi-router-wr30u-ubootmod) + ucidef_set_led_netdev "wan" "wan" "blue:network" "wan" + ;; xiaomi,redmi-router-ax6000-stock|\ xiaomi,redmi-router-ax6000-ubootmod) ucidef_set_led_netdev "wan" "wan" "rgb:network" "wan" diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network index 6abc81a0b05..51903eeace5 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network @@ -11,7 +11,8 @@ mediatek_setup_interfaces() asus,tuf-ax4200) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" eth1 ;; - netgear,wax220) + netgear,wax220|\ + zyxel,nwa50ax-pro) ucidef_set_interface_lan "eth0" ;; bananapi,bpi-r3) @@ -48,6 +49,9 @@ mediatek_setup_interfaces() tplink,tl-xdr6086) ucidef_set_interfaces_lan_wan "lan1 lan2" eth1 ;; + xiaomi,mi-router-wr30u-112m-nmbm|\ + xiaomi,mi-router-wr30u-stock|\ + xiaomi,mi-router-wr30u-ubootmod|\ xiaomi,redmi-router-ax6000-stock|\ xiaomi,redmi-router-ax6000-ubootmod) ucidef_set_interfaces_lan_wan "lan2 lan3 lan4" wan @@ -93,6 +97,9 @@ mediatek_setup_macs() wan_mac=$(macaddr_add "$lan_mac" 1) label_mac=$wan_mac ;; + xiaomi,mi-router-wr30u-112m-nmbm|\ + xiaomi,mi-router-wr30u-stock|\ + xiaomi,mi-router-wr30u-ubootmod|\ xiaomi,redmi-router-ax6000-stock|\ xiaomi,redmi-router-ax6000-ubootmod) wan_mac=$(mtd_get_mac_ascii Bdata ethaddr_wan) diff --git a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac index ab23b100444..3620e3a6fbc 100644 --- a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac +++ b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac @@ -61,4 +61,9 @@ case "$board" in addr=$(mtd_get_mac_binary "Factory" 0x4) [ "$PHYNBR" = "1" ] && macaddr_add $addr 1 > /sys${DEVPATH}/macaddress ;; + zyxel,nwa50ax-pro) + hw_mac_addr="$(mtd_get_mac_binary mrd 0x1fff8)" + [ "$PHYNBR" = "0" ] && macaddr_add $hw_mac_addr 1 > /sys${DEVPATH}/macaddress + [ "$PHYNBR" = "1" ] && macaddr_add $hw_mac_addr 2 > /sys${DEVPATH}/macaddress + ;; esac diff --git a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh index 186abfa5a8d..858e11ff00d 100755 --- a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh +++ b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh @@ -1,6 +1,6 @@ REQUIRE_IMAGE_METADATA=1 -redmi_ax6000_initial_setup() +xiaomi_initial_setup() { # initialize UBI and setup uboot-env if it's running on initramfs [ "$(rootfs_type)" = "tmpfs" ] || return 0 @@ -35,7 +35,16 @@ redmi_ax6000_initial_setup() fw_setenv flag_boot_success 1 fw_setenv flag_try_sys1_failed 8 fw_setenv flag_try_sys2_failed 8 - fw_setenv mtdparts "nmbm0:1024k(bl2),256k(Nvram),256k(Bdata),2048k(factory),2048k(fip),256k(crash),256k(crash_log),30720k(ubi),30720k(ubi1),51200k(overlay)" + + local board=$(board_name) + case "$board" in + xiaomi,mi-router-wr30u-stock) + fw_setenv mtdparts "nmbm0:1024k(bl2),256k(Nvram),256k(Bdata),2048k(factory),2048k(fip),256k(crash),256k(crash_log),34816k(ubi),34816k(ubi1),32768k(overlay),12288k(data),256k(KF)" + ;; + xiaomi,redmi-router-ax6000-stock) + fw_setenv mtdparts "nmbm0:1024k(bl2),256k(Nvram),256k(Bdata),2048k(factory),2048k(fip),256k(crash),256k(crash_log),30720k(ubi),30720k(ubi1),51200k(overlay)" + ;; + esac } platform_do_upgrade() { @@ -79,10 +88,13 @@ platform_do_upgrade() { tplink,tl-xdr4288|\ tplink,tl-xdr6086|\ tplink,tl-xdr6088|\ + xiaomi,mi-router-wr30u-112m-nmbm|\ + xiaomi,mi-router-wr30u-ubootmod|\ xiaomi,redmi-router-ax6000-ubootmod) CI_KERNPART="fit" nand_do_upgrade "$1" ;; + xiaomi,mi-router-wr30u-stock|\ xiaomi,redmi-router-ax6000-stock) CI_KERN_UBIPART=ubi_kernel CI_ROOT_UBIPART=ubi @@ -135,8 +147,9 @@ platform_pre_upgrade() { local board=$(board_name) case "$board" in + xiaomi,mi-router-wr30u-stock|\ xiaomi,redmi-router-ax6000-stock) - redmi_ax6000_initial_setup + xiaomi_initial_setup ;; esac } diff --git a/target/linux/mediatek/image/filogic.mk b/target/linux/mediatek/image/filogic.mk index 2ace305140b..d79e9299018 100644 --- a/target/linux/mediatek/image/filogic.mk +++ b/target/linux/mediatek/image/filogic.mk @@ -75,6 +75,13 @@ define Build/append-gl-metadata } endef +define Build/zyxel-nwa-fit-filogic + $(TOPDIR)/scripts/mkits-zyxel-fit-filogic.sh \ + $@.its $@ "80 e1 ff ff ff ff ff ff ff ff" + PATH=$(LINUX_DIR)/scripts/dtc:$(PATH) mkimage -f $@.its $@.new + @mv $@.new $@ +endef + define Device/asus_tuf-ax4200 DEVICE_VENDOR := ASUS DEVICE_MODEL := TUF-AX4200 @@ -98,6 +105,7 @@ define Device/bananapi_bpi-r3 DEVICE_DTS_CONFIG := config-mt7986a-bananapi-bpi-r3 DEVICE_DTS_OVERLAY:= mt7986a-bananapi-bpi-r3-emmc mt7986a-bananapi-bpi-r3-nand mt7986a-bananapi-bpi-r3-nor mt7986a-bananapi-bpi-r3-sd DEVICE_DTS_DIR := $(DTS_DIR)/ + DEVICE_DTS_LOADADDR := 0x43f00000 DEVICE_PACKAGES := kmod-hwmon-pwmfan kmod-i2c-gpio kmod-mt7986-firmware kmod-sfp kmod-usb3 e2fsprogs f2fsck mkf2fs mt7986-wo-firmware IMAGES := sysupgrade.itb KERNEL_LOADADDR := 0x44000000 @@ -357,6 +365,68 @@ define Device/tplink_tl-xdr6088 endef TARGET_DEVICES += tplink_tl-xdr6088 +define Device/xiaomi_mi-router-wr30u-112m-nmbm + DEVICE_VENDOR := Xiaomi + DEVICE_MODEL := Mi Router WR30U (112M UBI with NMBM-Enabled layout) + DEVICE_DTS := mt7981b-xiaomi-mi-router-wr30u-112m-nmbm + DEVICE_DTS_DIR := ../dts + UBINIZE_OPTS := -E 5 + BLOCKSIZE := 128k + PAGESIZE := 2048 + DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware +ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + ARTIFACTS := initramfs-factory.ubi + ARTIFACT/initramfs-factory.ubi := append-image-stage initramfs-kernel.bin | ubinize-kernel +endif + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata +endef +TARGET_DEVICES += xiaomi_mi-router-wr30u-112m-nmbm + +define Device/xiaomi_mi-router-wr30u-stock + DEVICE_VENDOR := Xiaomi + DEVICE_MODEL := Mi Router WR30U (stock layout) + DEVICE_DTS := mt7981b-xiaomi-mi-router-wr30u-stock + DEVICE_DTS_DIR := ../dts + UBINIZE_OPTS := -E 5 + BLOCKSIZE := 128k + PAGESIZE := 2048 + DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware +ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + ARTIFACTS := initramfs-factory.ubi + ARTIFACT/initramfs-factory.ubi := append-image-stage initramfs-kernel.bin | ubinize-kernel +endif + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata +endef +TARGET_DEVICES += xiaomi_mi-router-wr30u-stock + +define Device/xiaomi_mi-router-wr30u-ubootmod + DEVICE_VENDOR := Xiaomi + DEVICE_MODEL := Mi Router WR30U (OpenWrt U-Boot layout) + DEVICE_DTS := mt7981b-xiaomi-mi-router-wr30u-ubootmod + DEVICE_DTS_DIR := ../dts + UBINIZE_OPTS := -E 5 + BLOCKSIZE := 128k + PAGESIZE := 2048 + DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware + KERNEL_IN_UBI := 1 + UBOOTENV_IN_UBI := 1 + IMAGES := sysupgrade.itb + KERNEL_INITRAMFS_SUFFIX := -recovery.itb + KERNEL := kernel-bin | gzip + KERNEL_INITRAMFS := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k + IMAGE/sysupgrade.itb := append-kernel | \ + fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata + ARTIFACTS := preloader.bin bl31-uboot.fip + ARTIFACT/preloader.bin := mt7981-bl2 spim-nand-ddr3 + ARTIFACT/bl31-uboot.fip := mt7981-bl31-uboot xiaomi_mi-router-wr30u +ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + ARTIFACTS += initramfs-factory.ubi + ARTIFACT/initramfs-factory.ubi := append-image-stage initramfs-recovery.itb | ubinize-kernel +endif +endef +TARGET_DEVICES += xiaomi_mi-router-wr30u-ubootmod + define Device/xiaomi_redmi-router-ax6000-stock DEVICE_VENDOR := Xiaomi DEVICE_MODEL := Redmi Router AX6000 (stock layout) @@ -423,3 +493,21 @@ define Device/zyxel_ex5601-t0-stock fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd endef TARGET_DEVICES += zyxel_ex5601-t0-stock + +define Device/zyxel_nwa50ax-pro + DEVICE_VENDOR := ZyXEL + DEVICE_MODEL := NWA50AX Pro + DEVICE_DTS := mt7981b-zyxel-nwa50ax-pro + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware zyxel-bootconfig + DEVICE_DTS_LOADADDR := 0x44000000 + UBINIZE_OPTS := -E 5 + BLOCKSIZE := 128k + PAGESIZE := 2048 + IMAGE_SIZE := 51200k + KERNEL_IN_UBI := 1 + IMAGES += factory.bin + IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE) | zyxel-nwa-fit-filogic + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata +endef +TARGET_DEVICES += zyxel_nwa50ax-pro diff --git a/target/linux/mediatek/patches-6.1/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch b/target/linux/mediatek/patches-6.1/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch index 6acd3d607fb..49cd62d0ae5 100644 --- a/target/linux/mediatek/patches-6.1/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch +++ b/target/linux/mediatek/patches-6.1/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch @@ -15,7 +15,7 @@ Signed-off-by: Sam Shih --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -702,6 +702,15 @@ static const struct mtk_cpufreq_platform +@@ -709,6 +709,15 @@ static const struct mtk_cpufreq_platform .ccifreq_supported = false, }; @@ -31,10 +31,10 @@ Signed-off-by: Sam Shih static const struct mtk_cpufreq_platform_data mt8183_platform_data = { .min_volt_shift = 100000, .max_volt_shift = 200000, -@@ -735,6 +744,7 @@ static const struct of_device_id mtk_cpu +@@ -742,6 +751,7 @@ static const struct of_device_id mtk_cpu { .compatible = "mediatek,mt2712", .data = &mt2701_platform_data }, { .compatible = "mediatek,mt7622", .data = &mt7622_platform_data }, - { .compatible = "mediatek,mt7623", .data = &mt7622_platform_data }, + { .compatible = "mediatek,mt7623", .data = &mt7623_platform_data }, + { .compatible = "mediatek,mt7988", .data = &mt7988_platform_data }, { .compatible = "mediatek,mt8167", .data = &mt8516_platform_data }, { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data }, diff --git a/target/linux/mediatek/patches-6.1/351-cpufreq-mediatek-correct-voltages-for-MT7622-and-MT7.patch b/target/linux/mediatek/patches-6.1/351-cpufreq-mediatek-correct-voltages-for-MT7622-and-MT7.patch deleted file mode 100644 index 6ab05b897c3..00000000000 --- a/target/linux/mediatek/patches-6.1/351-cpufreq-mediatek-correct-voltages-for-MT7622-and-MT7.patch +++ /dev/null @@ -1,53 +0,0 @@ -From e7697814c142c99f470c3458d49e41b25a575f23 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Fri, 26 May 2023 10:31:40 +0100 -Subject: [PATCH] cpufreq: mediatek: correct voltages for MT7622 and MT7623 - -The MT6380 regulator typically used together with MT7622 does not -support the current maximum processor and SRAM voltage in the cpufreq -driver (1360000uV). -For MT7622 limit processor and SRAM supply voltages to 1350000uV to -avoid having the tracking algorithm request unsupported voltages from -the regulator. - -On MT7623 there is no separate SRAM supply and the maximum voltage used -is 1300000uV. Create dedicated platform data for MT7623 to cover that -case as well. - -Fixes: 0883426fd07e3 ("cpufreq: mediatek: Raise proc and sram max voltage for MT7622/7623") -Suggested-by: Jia-wei Chang -Signed-off-by: Daniel Golle ---- - drivers/cpufreq/mediatek-cpufreq.c | 13 ++++++++++--- - 1 file changed, 10 insertions(+), 3 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -696,9 +696,16 @@ static const struct mtk_cpufreq_platform - static const struct mtk_cpufreq_platform_data mt7622_platform_data = { - .min_volt_shift = 100000, - .max_volt_shift = 200000, -- .proc_max_volt = 1360000, -+ .proc_max_volt = 1350000, - .sram_min_volt = 0, -- .sram_max_volt = 1360000, -+ .sram_max_volt = 1350000, -+ .ccifreq_supported = false, -+}; -+ -+static const struct mtk_cpufreq_platform_data mt7623_platform_data = { -+ .min_volt_shift = 100000, -+ .max_volt_shift = 200000, -+ .proc_max_volt = 1300000, - .ccifreq_supported = false, - }; - -@@ -743,7 +750,7 @@ static const struct of_device_id mtk_cpu - { .compatible = "mediatek,mt2701", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt2712", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt7622", .data = &mt7622_platform_data }, -- { .compatible = "mediatek,mt7623", .data = &mt7622_platform_data }, -+ { .compatible = "mediatek,mt7623", .data = &mt7623_platform_data }, - { .compatible = "mediatek,mt7988", .data = &mt7988_platform_data }, - { .compatible = "mediatek,mt8167", .data = &mt8516_platform_data }, - { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data }, diff --git a/target/linux/mediatek/patches-6.1/410-bt-mtk-serial-fix.patch b/target/linux/mediatek/patches-6.1/410-bt-mtk-serial-fix.patch index 5b94c9216d9..072883e7fec 100644 --- a/target/linux/mediatek/patches-6.1/410-bt-mtk-serial-fix.patch +++ b/target/linux/mediatek/patches-6.1/410-bt-mtk-serial-fix.patch @@ -19,7 +19,7 @@ }, [PORT_NPCM] = { .name = "Nuvoton 16550", -@@ -2773,6 +2773,11 @@ serial8250_do_set_termios(struct uart_po +@@ -2770,6 +2770,11 @@ serial8250_do_set_termios(struct uart_po unsigned long flags; unsigned int baud, quot, frac = 0; diff --git a/target/linux/octeon/files/arch/mips/boot/dts/cavium-octeon/cn6130_cisco_vedge1000.dts b/target/linux/octeon/files/arch/mips/boot/dts/cavium-octeon/cn6130_cisco_vedge1000.dts index e1f308dd528..4680d6ea145 100644 --- a/target/linux/octeon/files/arch/mips/boot/dts/cavium-octeon/cn6130_cisco_vedge1000.dts +++ b/target/linux/octeon/files/arch/mips/boot/dts/cavium-octeon/cn6130_cisco_vedge1000.dts @@ -24,7 +24,7 @@ <0x11800 0xe0002000 0x00 0x08>; cell-index = <0x00>; interrupts = <0x00 0x3e 0x01 0x2e>; - nvmem-cells = <&macaddr_eeprom>; + nvmem-cells = <&macaddr_eeprom 0>; nvmem-cell-names = "mac-address"; phy-handle = <&mgmtphy>; }; @@ -32,25 +32,22 @@ pip: pip@11800a0000000 { interface@0 { ethernet@0 { - nvmem-cells = <&macaddr_eeprom>; + nvmem-cells = <&macaddr_eeprom 3>; nvmem-cell-names = "mac-address"; - mac-address-increment = <(3)>; label = "lan2"; /delete-property/ local-mac-address; }; ethernet@1 { - nvmem-cells = <&macaddr_eeprom>; + nvmem-cells = <&macaddr_eeprom 4>; nvmem-cell-names = "mac-address"; - mac-address-increment = <(4)>; label = "lan3"; /delete-property/ local-mac-address; }; ethernet@2 { - nvmem-cells = <&macaddr_eeprom>; + nvmem-cells = <&macaddr_eeprom 1>; nvmem-cell-names = "mac-address"; - mac-address-increment = <(1)>; label = "lan0"; /delete-property/ local-mac-address; }; @@ -58,9 +55,8 @@ ethernet@3 { compatible = "cavium,octeon-3860-pip-port"; reg = <0x3>; - nvmem-cells = <&macaddr_eeprom>; + nvmem-cells = <&macaddr_eeprom 2>; nvmem-cell-names = "mac-address"; - mac-address-increment = <(2)>; label = "lan1"; }; }; @@ -69,36 +65,32 @@ ethernet@0 { compatible = "cavium,octeon-3860-pip-port"; reg = <0x0>; - nvmem-cells = <&macaddr_eeprom>; + nvmem-cells = <&macaddr_eeprom 7>; nvmem-cell-names = "mac-address"; - mac-address-increment = <(7)>; label = "lan6"; }; ethernet@1 { compatible = "cavium,octeon-3860-pip-port"; reg = <0x1>; - nvmem-cells = <&macaddr_eeprom>; + nvmem-cells = <&macaddr_eeprom 8>; nvmem-cell-names = "mac-address"; - mac-address-increment = <(8)>; label = "lan7"; }; ethernet@2 { compatible = "cavium,octeon-3860-pip-port"; reg = <0x2>; - nvmem-cells = <&macaddr_eeprom>; + nvmem-cells = <&macaddr_eeprom 5>; nvmem-cell-names = "mac-address"; - mac-address-increment = <(5)>; label = "lan4"; }; ethernet@3 { compatible = "cavium,octeon-3860-pip-port"; reg = <0x3>; - nvmem-cells = <&macaddr_eeprom>; + nvmem-cells = <&macaddr_eeprom 6>; nvmem-cell-names = "mac-address"; - mac-address-increment = <(6)>; label = "lan5"; }; }; @@ -135,11 +127,17 @@ compatible = "atmel,24c512"; reg = <0x54>; pagesize = <0x80>; - #address-cells = <1>; - #size-cells = <1>; - macaddr_eeprom: mac-address@8 { - reg = <0x8 6>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_eeprom: mac-address@8 { + compatible = "mac-base"; + reg = <0x8 6>; + #nvmem-cell-cells = <1>; + }; }; }; }; diff --git a/target/linux/qualcommax/image/ipq807x.mk b/target/linux/qualcommax/image/ipq807x.mk index 54f8caf5d7a..555c723c5f4 100644 --- a/target/linux/qualcommax/image/ipq807x.mk +++ b/target/linux/qualcommax/image/ipq807x.mk @@ -115,7 +115,8 @@ define Device/prpl_haze DEVICE_MODEL := Haze DEVICE_DTS_CONFIG := config@hk09 SOC := ipq8072 - DEVICE_PACKAGES += ath11k-firmware-qcn9074 ipq-wifi-prpl_haze kmod-ath11k-pci + DEVICE_PACKAGES += ath11k-firmware-qcn9074 ipq-wifi-prpl_haze kmod-ath11k-pci \ + mkf2fs f2fsck kmod-fs-f2fs endef TARGET_DEVICES += prpl_haze diff --git a/target/linux/qualcommax/patches-6.1/0008-v6.2-clk-qcom-reset-support-resetting-multiple-bits.patch b/target/linux/qualcommax/patches-6.1/0008-v6.2-clk-qcom-reset-support-resetting-multiple-bits.patch deleted file mode 100644 index e0725a66129..00000000000 --- a/target/linux/qualcommax/patches-6.1/0008-v6.2-clk-qcom-reset-support-resetting-multiple-bits.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 813ba3e427671ba3ff35c825087b03f0ad91cf02 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Mon, 7 Nov 2022 14:28:59 +0100 -Subject: [PATCH] clk: qcom: reset: support resetting multiple bits - -This patch adds the support for giving the complete bitmask -in reset structure and reset operation will use this bitmask -for all reset operations. - -Currently, reset structure only takes a single bit for each reset -and then calculates the bitmask by using the BIT() macro. - -However, this is not sufficient anymore for newer SoC-s like IPQ8074, -IPQ6018 and more, since their networking resets require multiple bits -to be asserted in order to properly reset the HW block completely. - -So, in order to allow asserting multiple bits add "bitmask" field to -qcom_reset_map, and then use that bitmask value if its populated in the -driver, if its not populated, then we just default to existing behaviour -and calculate the bitmask on the fly. - -Signed-off-by: Robert Marko -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20221107132901.489240-1-robimarko@gmail.com ---- - drivers/clk/qcom/reset.c | 4 ++-- - drivers/clk/qcom/reset.h | 1 + - 2 files changed, 3 insertions(+), 2 deletions(-) - ---- a/drivers/clk/qcom/reset.c -+++ b/drivers/clk/qcom/reset.c -@@ -30,7 +30,7 @@ qcom_reset_assert(struct reset_controlle - - rst = to_qcom_reset_controller(rcdev); - map = &rst->reset_map[id]; -- mask = BIT(map->bit); -+ mask = map->bitmask ? map->bitmask : BIT(map->bit); - - return regmap_update_bits(rst->regmap, map->reg, mask, mask); - } -@@ -44,7 +44,7 @@ qcom_reset_deassert(struct reset_control - - rst = to_qcom_reset_controller(rcdev); - map = &rst->reset_map[id]; -- mask = BIT(map->bit); -+ mask = map->bitmask ? map->bitmask : BIT(map->bit); - - return regmap_update_bits(rst->regmap, map->reg, mask, 0); - } ---- a/drivers/clk/qcom/reset.h -+++ b/drivers/clk/qcom/reset.h -@@ -12,6 +12,7 @@ struct qcom_reset_map { - unsigned int reg; - u8 bit; - u8 udelay; -+ u32 bitmask; - }; - - struct regmap; diff --git a/target/linux/qualcommax/patches-6.1/0020-v6.3-PCI-qcom-Add-support-for-IPQ8074-Gen3-port.patch b/target/linux/qualcommax/patches-6.1/0020-v6.3-PCI-qcom-Add-support-for-IPQ8074-Gen3-port.patch index 60caee46cab..8f4ef91b762 100644 --- a/target/linux/qualcommax/patches-6.1/0020-v6.3-PCI-qcom-Add-support-for-IPQ8074-Gen3-port.patch +++ b/target/linux/qualcommax/patches-6.1/0020-v6.3-PCI-qcom-Add-support-for-IPQ8074-Gen3-port.patch @@ -16,7 +16,7 @@ Signed-off-by: Bjorn Helgaas --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c -@@ -1745,6 +1745,7 @@ static const struct of_device_id qcom_pc +@@ -1764,6 +1764,7 @@ static const struct of_device_id qcom_pc { .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 }, { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 }, { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 }, diff --git a/target/linux/qualcommax/patches-6.1/0022-v6.5-soc-qcom-mdt_loader-Fix-unconditional-call-to-scm_pa.patch b/target/linux/qualcommax/patches-6.1/0022-v6.5-soc-qcom-mdt_loader-Fix-unconditional-call-to-scm_pa.patch deleted file mode 100644 index 72b38270c46..00000000000 --- a/target/linux/qualcommax/patches-6.1/0022-v6.5-soc-qcom-mdt_loader-Fix-unconditional-call-to-scm_pa.patch +++ /dev/null @@ -1,77 +0,0 @@ -From b8295c6eb276b60f7b75c53a9703ca8fee01eba2 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Fri, 26 May 2023 13:09:17 +0200 -Subject: [PATCH] soc: qcom: mdt_loader: Fix unconditional call to - scm_pas_mem_setup - -Commit ebeb20a9cd3f ("soc: qcom: mdt_loader: Always invoke PAS -mem_setup") dropped the relocate check and made pas_mem_setup run -unconditionally. The code was later moved with commit f4e526ff7e38 -("soc: qcom: mdt_loader: Extract PAS operations") to -qcom_mdt_pas_init() effectively losing track of what was actually -done. - -The assumption that PAS mem_setup can be done anytime was effectively -wrong, with no good reason and this caused regression on some SoC -that use remoteproc to bringup ath11k. One example is IPQ8074 SoC that -effectively broke resulting in remoteproc silently die and ath11k not -working. - -On this SoC FW relocate is not enabled and PAS mem_setup was correctly -skipped in previous kernel version resulting in correct bringup and -function of remoteproc and ath11k. - -To fix the regression, reintroduce the relocate check in -qcom_mdt_pas_init() and correctly skip PAS mem_setup where relocate is -not enabled. - -Fixes: ebeb20a9cd3f ("soc: qcom: mdt_loader: Always invoke PAS mem_setup") -Reported-by: Robert Marko -Tested-by: Robert Marko -Co-developed-by: Robert Marko -Signed-off-by: Robert Marko -Signed-off-by: Christian Marangi -Cc: stable@vger.kernel.org ---- - drivers/soc/qcom/mdt_loader.c | 16 +++++++++++----- - 1 file changed, 11 insertions(+), 5 deletions(-) - ---- a/drivers/soc/qcom/mdt_loader.c -+++ b/drivers/soc/qcom/mdt_loader.c -@@ -210,6 +210,7 @@ int qcom_mdt_pas_init(struct device *dev - const struct elf32_hdr *ehdr; - phys_addr_t min_addr = PHYS_ADDR_MAX; - phys_addr_t max_addr = 0; -+ bool relocate = false; - size_t metadata_len; - void *metadata; - int ret; -@@ -224,6 +225,9 @@ int qcom_mdt_pas_init(struct device *dev - if (!mdt_phdr_valid(phdr)) - continue; - -+ if (phdr->p_flags & QCOM_MDT_RELOCATABLE) -+ relocate = true; -+ - if (phdr->p_paddr < min_addr) - min_addr = phdr->p_paddr; - -@@ -246,11 +250,13 @@ int qcom_mdt_pas_init(struct device *dev - goto out; - } - -- ret = qcom_scm_pas_mem_setup(pas_id, mem_phys, max_addr - min_addr); -- if (ret) { -- /* Unable to set up relocation */ -- dev_err(dev, "error %d setting up firmware %s\n", ret, fw_name); -- goto out; -+ if (relocate) { -+ ret = qcom_scm_pas_mem_setup(pas_id, mem_phys, max_addr - min_addr); -+ if (ret) { -+ /* Unable to set up relocation */ -+ dev_err(dev, "error %d setting up firmware %s\n", ret, fw_name); -+ goto out; -+ } - } - - out: diff --git a/target/linux/qualcommax/patches-6.1/0132-mmc-core-disable-TRIM-on-Micron-MTFC4GACAJCN-1M.patch b/target/linux/qualcommax/patches-6.1/0132-mmc-core-disable-TRIM-on-Micron-MTFC4GACAJCN-1M.patch index 8c2e59eeb48..0da71f1b097 100644 --- a/target/linux/qualcommax/patches-6.1/0132-mmc-core-disable-TRIM-on-Micron-MTFC4GACAJCN-1M.patch +++ b/target/linux/qualcommax/patches-6.1/0132-mmc-core-disable-TRIM-on-Micron-MTFC4GACAJCN-1M.patch @@ -20,7 +20,7 @@ Signed-off-by: Robert Marko --- a/drivers/mmc/core/quirks.h +++ b/drivers/mmc/core/quirks.h -@@ -101,6 +101,13 @@ static const struct mmc_fixup __maybe_un +@@ -124,6 +124,13 @@ static const struct mmc_fixup __maybe_un MMC_QUIRK_TRIM_BROKEN), /* diff --git a/target/linux/qualcommax/patches-6.1/0133-mmc-core-disable-TRIM-on-Kingston-EMMC04G-M627.patch b/target/linux/qualcommax/patches-6.1/0133-mmc-core-disable-TRIM-on-Kingston-EMMC04G-M627.patch index ac7af52a74e..cc6f29e38e2 100644 --- a/target/linux/qualcommax/patches-6.1/0133-mmc-core-disable-TRIM-on-Kingston-EMMC04G-M627.patch +++ b/target/linux/qualcommax/patches-6.1/0133-mmc-core-disable-TRIM-on-Kingston-EMMC04G-M627.patch @@ -22,7 +22,7 @@ Signed-off-by: Robert Marko --- a/drivers/mmc/core/quirks.h +++ b/drivers/mmc/core/quirks.h -@@ -108,6 +108,13 @@ static const struct mmc_fixup __maybe_un +@@ -131,6 +131,13 @@ static const struct mmc_fixup __maybe_un MMC_QUIRK_TRIM_BROKEN), /* diff --git a/target/linux/ramips/dts/mt7621_netgear_r6220.dts b/target/linux/ramips/dts/mt7621_netgear_r6220.dts index 146b7ee752a..f960d8f66fe 100644 --- a/target/linux/ramips/dts/mt7621_netgear_r6220.dts +++ b/target/linux/ramips/dts/mt7621_netgear_r6220.dts @@ -52,11 +52,19 @@ #address-cells = <1>; #size-cells = <1>; + eeprom0: eeprom@0 { + reg = <0x0 0x400>; + }; + macaddr_factory_4: macaddr@4 { compatible = "mac-base"; reg = <0x4 0x6>; #nvmem-cell-cells = <1>; }; + + eeprom1: eeprom@8000 { + reg = <0x8000 0x200>; + }; }; }; diff --git a/target/linux/ramips/dts/mt7621_netgear_sercomm_ayx.dtsi b/target/linux/ramips/dts/mt7621_netgear_sercomm_ayx.dtsi index 691aba10634..052b2a4babe 100644 --- a/target/linux/ramips/dts/mt7621_netgear_sercomm_ayx.dtsi +++ b/target/linux/ramips/dts/mt7621_netgear_sercomm_ayx.dtsi @@ -91,8 +91,9 @@ wifi@0,0 { compatible = "mediatek,mt76"; reg = <0x0 0 0 0 0>; - mediatek,mtd-eeprom = <&factory 0x8000>; ieee80211-freq-limit = <5000000 6000000>; + nvmem-cells = <&eeprom1>; + nvmem-cell-names = "eeprom"; }; }; @@ -100,8 +101,9 @@ wifi@0,0 { compatible = "mediatek,mt76"; reg = <0x0 0 0 0 0>; - mediatek,mtd-eeprom = <&factory 0x0>; ieee80211-freq-limit = <2400000 2500000>; + nvmem-cells = <&eeprom0>; + nvmem-cell-names = "eeprom"; }; }; diff --git a/target/linux/ramips/dts/mt7621_netgear_wndr3700-v5.dts b/target/linux/ramips/dts/mt7621_netgear_wndr3700-v5.dts index 276e7c959f5..8252d2b9ff7 100644 --- a/target/linux/ramips/dts/mt7621_netgear_wndr3700-v5.dts +++ b/target/linux/ramips/dts/mt7621_netgear_wndr3700-v5.dts @@ -40,6 +40,26 @@ label = "factory"; reg = <0xf30000 0x10000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom0: eeprom@0 { + reg = <0x0 0x400>; + }; + + macaddr_factory_4: macaddr@4 { + compatible = "mac-base"; + reg = <0x4 0x6>; + #nvmem-cell-cells = <1>; + }; + + eeprom1: eeprom@8000 { + reg = <0x8000 0x200>; + }; + }; }; partition@50000 { @@ -52,22 +72,11 @@ }; &gmac0 { - nvmem-cells = <&macaddr_factory_4>; + nvmem-cells = <&macaddr_factory_4 0>; nvmem-cell-names = "mac-address"; }; &gmac1 { - nvmem-cells = <&macaddr_factory_4>; + nvmem-cells = <&macaddr_factory_4 1>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; -}; - -&factory { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_factory_4: macaddr@4 { - reg = <0x4 0x6>; - }; }; diff --git a/target/linux/ramips/dts/mt7621_raisecom_msg1500-x-00.dts b/target/linux/ramips/dts/mt7621_raisecom_msg1500-x-00.dts index 5d713c00987..07297df0833 100644 --- a/target/linux/ramips/dts/mt7621_raisecom_msg1500-x-00.dts +++ b/target/linux/ramips/dts/mt7621_raisecom_msg1500-x-00.dts @@ -82,15 +82,23 @@ read-only; compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - macaddr_config_8014: macaddr@8014 { - reg = <0x8014 0x11>; - }; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_config_8036: macaddr@8036 { - reg = <0x8036 0x11>; + macaddr_config_8014: macaddr@8014 { + compatible = "mac-base"; + reg = <0x8014 0x11>; + #nvmem-cell-cells = <1>; + }; + + macaddr_config_8036: macaddr@8036 { + compatible = "mac-base"; + reg = <0x8036 0x11>; + #nvmem-cell-cells = <1>; + }; }; }; @@ -137,8 +145,8 @@ }; &gmac0 { - nvmem-cells = <&macaddr_config_8014>; - nvmem-cell-names = "mac-address-ascii"; + nvmem-cells = <&macaddr_config_8014 0>; + nvmem-cell-names = "mac-address"; }; &gmac1 { @@ -146,8 +154,8 @@ label = "wan"; phy-handle = <ðphy4>; - nvmem-cells = <&macaddr_config_8036>; - nvmem-cell-names = "mac-address-ascii"; + nvmem-cells = <&macaddr_config_8036 0>; + nvmem-cell-names = "mac-address"; }; &mdio { diff --git a/target/linux/ramips/dts/mt7621_tplink_ec330-g5u-v1.dts b/target/linux/ramips/dts/mt7621_tplink_ec330-g5u-v1.dts index 6c9cc407015..537b6f70a73 100644 --- a/target/linux/ramips/dts/mt7621_tplink_ec330-g5u-v1.dts +++ b/target/linux/ramips/dts/mt7621_tplink_ec330-g5u-v1.dts @@ -230,12 +230,20 @@ read-only; compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - macaddr_factory_165: macaddr@165 { - reg = <0x165 0x11>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_factory_165: macaddr@165 { + compatible = "mac-base"; + reg = <0x165 0x11>; + #nvmem-cell-cells = <1>; + }; }; + + }; partition@0_wholeflash { @@ -257,8 +265,8 @@ mediatek,mtd-eeprom = <&factory 0x8000>; ieee80211-freq-limit = <2400000 2500000>; - nvmem-cells = <&macaddr_factory_165>; - nvmem-cell-names = "mac-address-ascii"; + nvmem-cells = <&macaddr_factory_165 0>; + nvmem-cell-names = "mac-address"; }; }; @@ -269,15 +277,14 @@ mediatek,mtd-eeprom = <&factory 0x14000>; ieee80211-freq-limit = <5000000 6000000>; - nvmem-cells = <&macaddr_factory_165>; - nvmem-cell-names = "mac-address-ascii"; - mac-address-increment = <(2)>; + nvmem-cells = <&macaddr_factory_165 2>; + nvmem-cell-names = "mac-address"; }; }; &gmac0 { - nvmem-cells = <&macaddr_factory_165>; - nvmem-cell-names = "mac-address-ascii"; + nvmem-cells = <&macaddr_factory_165 0>; + nvmem-cell-names = "mac-address"; }; &gmac1 { @@ -285,9 +292,8 @@ label = "wan"; phy-handle = <ðphy0>; - nvmem-cells = <&macaddr_factory_165>; - nvmem-cell-names = "mac-address-ascii"; - mac-address-increment = <(1)>; + nvmem-cells = <&macaddr_factory_165 1>; + nvmem-cell-names = "mac-address"; }; &mdio { diff --git a/target/linux/ramips/mt7621/config-5.15 b/target/linux/ramips/mt7621/config-5.15 index b366dac723a..05e4c1ce877 100644 --- a/target/linux/ramips/mt7621/config-5.15 +++ b/target/linux/ramips/mt7621/config-5.15 @@ -7,7 +7,6 @@ CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_AT803X_PHY=y CONFIG_BLK_MQ_PCI=y CONFIG_BOARD_SCACHE=y -CONFIG_BOUNCE=y CONFIG_CEVT_R4K=y CONFIG_CLKSRC_MIPS_GIC=y CONFIG_CLK_MT7621=y @@ -91,7 +90,6 @@ CONFIG_HARDWARE_WATCHPOINTS=y CONFIG_HAS_DMA=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y -CONFIG_HIGHMEM=y CONFIG_I2C=y CONFIG_I2C_ALGOBIT=y CONFIG_I2C_BOARDINFO=y @@ -106,7 +104,6 @@ CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_IRQ_FORCED_THREADING=y CONFIG_IRQ_MIPS_CPU=y CONFIG_IRQ_WORK=y -CONFIG_KMAP_LOCAL=y CONFIG_LED_TRIGGER_PHY=y CONFIG_LIBFDT=y CONFIG_LOCK_DEBUGGING_SUPPORT=y diff --git a/target/linux/ramips/patches-5.15/808-pinctrl-mtmips-support-requesting-different-function.patch b/target/linux/ramips/patches-5.15/808-pinctrl-mtmips-support-requesting-different-function.patch new file mode 100644 index 00000000000..047808f1e69 --- /dev/null +++ b/target/linux/ramips/patches-5.15/808-pinctrl-mtmips-support-requesting-different-function.patch @@ -0,0 +1,45 @@ +From: Shiji Yang +Date: Wed, 26 Jul 2023 01:32:55 +0800 +Subject: [PATCH] pinctrl: mtmips: support requesting different functions for + same group + +Sometimes pinctrl consumers may request different functions for the +same pin group in different situations. This patch can help to reset +the group function flag when requesting a different function. + +Signed-off-by: Shiji Yang +--- + drivers/pinctrl/ralink/pinctrl-ralink.c | 21 +++++++++++++++++---- + 1 file changed, 17 insertions(+), 4 deletions(-) + +--- a/drivers/pinctrl/ralink/pinctrl-ralink.c ++++ b/drivers/pinctrl/ralink/pinctrl-ralink.c +@@ -123,11 +123,24 @@ static int ralink_pmx_group_enable(struc + int i; + int shift; + +- /* dont allow double use */ ++ /* ++ * for the same pin group, if request a different function, ++ * then clear the group function flag and continue, else exit. ++ */ + if (p->groups[group].enabled) { +- dev_err(p->dev, "%s is already enabled\n", +- p->groups[group].name); +- return 0; ++ for (i = 0; i < p->groups[group].func_count; i++) { ++ if (p->groups[group].func[i].enabled == 1) { ++ if (!strcmp(p->func[func]->name, ++ p->groups[group].func[i].name)) ++ return 0; ++ p->groups[group].func[i].enabled = 0; ++ break; ++ } ++ } ++ ++ /* exit if request the "gpio" function again */ ++ if (i == p->groups[group].func_count && func == 0) ++ return 0; + } + + p->groups[group].enabled = 1; diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk index 063dc6fd644..dc977859a6d 100644 --- a/target/linux/rockchip/image/armv8.mk +++ b/target/linux/rockchip/image/armv8.mk @@ -15,6 +15,15 @@ define Device/firefly_roc-rk3328-cc endef TARGET_DEVICES += firefly_roc-rk3328-cc +define Device/friendlyarm_nanopc-t4 + DEVICE_VENDOR := FriendlyARM + DEVICE_MODEL := NanoPC T4 + SOC := rk3399 + IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata + DEVICE_PACKAGES := kmod-brcmfmac brcmfmac-nvram-4356-sdio cypress-firmware-4356-sdio +endef +TARGET_DEVICES += friendlyarm_nanopc-t4 + define Device/friendlyarm_nanopi-r2c DEVICE_VENDOR := FriendlyARM DEVICE_MODEL := NanoPi R2C diff --git a/target/linux/rockchip/patches-5.15/109-nanopc-t4-add-led-aliases.patch b/target/linux/rockchip/patches-5.15/109-nanopc-t4-add-led-aliases.patch new file mode 100644 index 00000000000..1a80dadd48b --- /dev/null +++ b/target/linux/rockchip/patches-5.15/109-nanopc-t4-add-led-aliases.patch @@ -0,0 +1,16 @@ +--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts +@@ -15,6 +15,13 @@ + model = "FriendlyElec NanoPC-T4"; + compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399"; + ++ aliases { ++ led-boot = &status_led; ++ led-failsafe = &status_led; ++ led-running = &status_led; ++ led-upgrade = &status_led; ++ }; ++ + vcc12v0_sys: vcc12v0-sys { + compatible = "regulator-fixed"; + regulator-always-on; diff --git a/target/linux/rockchip/patches-6.1/109-nanopc-t4-add-led-aliases.patch b/target/linux/rockchip/patches-6.1/109-nanopc-t4-add-led-aliases.patch new file mode 100644 index 00000000000..1a80dadd48b --- /dev/null +++ b/target/linux/rockchip/patches-6.1/109-nanopc-t4-add-led-aliases.patch @@ -0,0 +1,16 @@ +--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts +@@ -15,6 +15,13 @@ + model = "FriendlyElec NanoPC-T4"; + compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399"; + ++ aliases { ++ led-boot = &status_led; ++ led-failsafe = &status_led; ++ led-running = &status_led; ++ led-upgrade = &status_led; ++ }; ++ + vcc12v0_sys: vcc12v0-sys { + compatible = "regulator-fixed"; + regulator-always-on; diff --git a/toolchain/kernel-headers/Makefile b/toolchain/kernel-headers/Makefile index c1a8710a4fb..8e3324816bf 100644 --- a/toolchain/kernel-headers/Makefile +++ b/toolchain/kernel-headers/Makefile @@ -23,7 +23,10 @@ ifneq ($(call qstrip,$(CONFIG_KERNEL_GIT_CLONE_URI)),) PKG_SOURCE_VERSION:=$(call qstrip,$(CONFIG_KERNEL_GIT_REF)) PKG_MIRROR_HASH:=$(call qstrip,$(CONFIG_KERNEL_GIT_MIRROR_HASH)) ifdef CHECK + PLATFORM_DIR:=$(firstword $(wildcard $(TOPDIR)/target/linux/feeds/$(BOARD) $(TOPDIR)/target/linux/$(BOARD))) + include $(PLATFORM_DIR)/Makefile include $(INCLUDE_DIR)/kernel-version.mk + include $(INCLUDE_DIR)/kernel-build.mk PKG_VERSION:=$(LINUX_VERSION) else PKG_SOURCE:=$(LINUX_SOURCE) @@ -90,7 +93,6 @@ define Host/Prepare endef define Host/Configure - env yes '' | $(HOST_KMAKE) oldconfig $(call Host/Configure/all) $(call Host/Configure/post/$(ARCH))