ipq806x: replace patches with upstream version
Replace all the custom patches with the backported upstream version Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> [refresh patches] Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
This commit is contained in:
Ansuel Smith
Adrian Schmutzler
parent
4f1a51f438
commit
df3ad130d5
8 changed files with 218 additions and 166 deletions
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@ -1,79 +0,0 @@
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From 2034addc7e193dc81d7ca60d8884832751b76758 Mon Sep 17 00:00:00 2001
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From: Ajay Kishore <akisho@codeaurora.org>
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Date: Tue, 24 Jan 2017 14:14:16 +0530
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Subject: pinctrl: qcom: use scm_call to route GPIO irq to Apps
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For IPQ806x targets, TZ protects the registers that are used to
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configure the routing of interrupts to a target processor.
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To resolve this, this patch uses scm call to route GPIO interrupts
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to application processor. Also the scm call interface is changed.
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Change-Id: Ib6c06829d04bc8c20483c36e63da92e26cdef9ce
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Signed-off-by: Ajay Kishore <akisho@codeaurora.org>
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---
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--- a/drivers/pinctrl/qcom/pinctrl-msm.c
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+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
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@@ -22,7 +22,8 @@
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#include <linux/reboot.h>
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#include <linux/pm.h>
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#include <linux/log2.h>
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-
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+#include <linux/qcom_scm.h>
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+#include <linux/io.h>
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#include "../core.h"
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#include "../pinconf.h"
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#include "pinctrl-msm.h"
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@@ -706,6 +707,9 @@ static void msm_gpio_irq_mask(struct irq
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const struct msm_pingroup *g;
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unsigned long flags;
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u32 val;
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+ u32 addr;
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+ int ret;
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+ const __be32 *reg;
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g = &pctrl->soc->groups[d->hwirq];
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@@ -819,6 +823,7 @@ static int msm_gpio_irq_set_type(struct
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const struct msm_pingroup *g;
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unsigned long flags;
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u32 val;
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+ int ret;
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g = &pctrl->soc->groups[d->hwirq];
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@@ -832,11 +837,30 @@ static int msm_gpio_irq_set_type(struct
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else
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clear_bit(d->hwirq, pctrl->dual_edge_irqs);
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+ ret = of_device_is_compatible(pctrl->dev->of_node,
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+ "qcom,ipq8064-pinctrl");
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/* Route interrupts to application cpu */
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- val = msm_readl_intr_target(pctrl, g);
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- val &= ~(7 << g->intr_target_bit);
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- val |= g->intr_target_kpss_val << g->intr_target_bit;
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- msm_writel_intr_target(val, pctrl, g);
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+ if (!ret) {
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+ val = msm_readl_intr_target(pctrl, g);
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+ val &= ~(7 << g->intr_target_bit);
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+ val |= g->intr_target_kpss_val << g->intr_target_bit;
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+ msm_writel_intr_target(val, pctrl, g);
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+ } else {
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+ const __be32 *reg = of_get_property(pctrl->dev->of_node, "reg", NULL);
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+ if (reg) {
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+ u32 addr = be32_to_cpup(reg) + g->intr_target_reg;
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+ qcom_scm_io_readl(addr, &val);
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+ __iormb();
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+
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+ val &= ~(7 << g->intr_target_bit);
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+ val |= g->intr_target_kpss_val << g->intr_target_bit;
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+
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+ __iowmb();
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+ ret = qcom_scm_io_writel(addr, val);
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+ if (ret)
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+ pr_err("\n Routing interrupts to Apps proc failed");
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+ }
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+ }
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/* Update configuration for gpio.
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* RAW_STATUS_EN is left on for all gpio irqs. Due to the
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@ -0,0 +1,104 @@
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From 13bec8d49bdf10aab4e1570ef42417f6bfbb6126 Mon Sep 17 00:00:00 2001
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From: Ajay Kishore <akisho@codeaurora.org>
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Date: Fri, 27 Mar 2020 23:32:08 +0100
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Subject: pinctrl: qcom: use scm_call to route GPIO irq to Apps
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For IPQ806x targets, TZ protects the registers that are used to
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configure the routing of interrupts to a target processor.
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To resolve this, this patch uses scm call to route GPIO interrupts
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to application processor. Also the scm call interface is changed.
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Signed-off-by: Ajay Kishore <akisho@codeaurora.org>
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Link: https://lore.kernel.org/r/20200327223209.20409-1-ansuelsmth@gmail.com
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Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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---
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drivers/pinctrl/qcom/pinctrl-msm.c | 43 ++++++++++++++++++++++++++++++++------
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1 file changed, 37 insertions(+), 6 deletions(-)
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(limited to 'drivers/pinctrl/qcom/pinctrl-msm.c')
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--- a/drivers/pinctrl/qcom/pinctrl-msm.c
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+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
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@@ -22,6 +22,8 @@
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#include <linux/reboot.h>
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#include <linux/pm.h>
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#include <linux/log2.h>
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+#include <linux/qcom_scm.h>
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+#include <linux/io.h>
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#include "../core.h"
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#include "../pinconf.h"
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@@ -57,6 +59,8 @@ struct msm_pinctrl {
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struct irq_chip irq_chip;
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int irq;
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+ bool intr_target_use_scm;
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+
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raw_spinlock_t lock;
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DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
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@@ -64,6 +68,7 @@ struct msm_pinctrl {
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const struct msm_pinctrl_soc_data *soc;
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void __iomem *regs[MAX_NR_TILES];
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+ u32 phys_base[MAX_NR_TILES];
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};
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#define MSM_ACCESSOR(name) \
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@@ -832,11 +837,30 @@ static int msm_gpio_irq_set_type(struct
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else
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clear_bit(d->hwirq, pctrl->dual_edge_irqs);
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- /* Route interrupts to application cpu */
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- val = msm_readl_intr_target(pctrl, g);
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- val &= ~(7 << g->intr_target_bit);
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- val |= g->intr_target_kpss_val << g->intr_target_bit;
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- msm_writel_intr_target(val, pctrl, g);
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+ /* Route interrupts to application cpu.
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+ * With intr_target_use_scm interrupts are routed to
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+ * application cpu using scm calls.
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+ */
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+ if (pctrl->intr_target_use_scm) {
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+ u32 addr = pctrl->phys_base[0] + g->intr_target_reg;
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+ int ret;
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+
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+ qcom_scm_io_readl(addr, &val);
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+
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+ val &= ~(7 << g->intr_target_bit);
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+ val |= g->intr_target_kpss_val << g->intr_target_bit;
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+
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+ ret = qcom_scm_io_writel(addr, val);
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+ if (ret)
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+ dev_err(pctrl->dev,
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+ "Failed routing %lu interrupt to Apps proc",
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+ d->hwirq);
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+ } else {
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+ val = msm_readl_intr_target(pctrl, g);
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+ val &= ~(7 << g->intr_target_bit);
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+ val |= g->intr_target_kpss_val << g->intr_target_bit;
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+ msm_writel_intr_target(val, pctrl, g);
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+ }
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/* Update configuration for gpio.
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* RAW_STATUS_EN is left on for all gpio irqs. Due to the
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@@ -1138,6 +1162,9 @@ int msm_pinctrl_probe(struct platform_de
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pctrl->dev = &pdev->dev;
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pctrl->soc = soc_data;
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pctrl->chip = msm_gpio_template;
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+ pctrl->intr_target_use_scm = of_device_is_compatible(
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+ pctrl->dev->of_node,
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+ "qcom,ipq8064-pinctrl");
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raw_spin_lock_init(&pctrl->lock);
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@@ -1154,6 +1181,8 @@ int msm_pinctrl_probe(struct platform_de
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pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(pctrl->regs[0]))
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return PTR_ERR(pctrl->regs[0]);
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+
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+ pctrl->phys_base[0] = res->start;
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}
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msm_pinctrl_setup_pm_reset(pctrl);
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@ -1,9 +1,15 @@
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From a3488aa9bed37c56e405967d44e821c484b5d6b9 Mon Sep 17 00:00:00 2001
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From: Ram Chandra Jangir <rjangir@codeaurora.org>
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Date: Fri, 28 Sep 2018 15:19:50 +0530
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Subject: [PATCH] ipq8064: pinctrl: Fixed missing RGMII pincontrol definitions
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From 8d8cec9bf6e9260397872785f249dfb59a417d08 Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Wed, 19 Feb 2020 18:59:39 +0100
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Subject: ipq8064: pinctrl: Fixed missing RGMII pincontrol definitions
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Add missing gpio definition for mdio and rgmii2.
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Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Link: https://lore.kernel.org/r/20200219175940.744-1-ansuelsmth@gmail.com
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Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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---
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drivers/pinctrl/qcom/pinctrl-ipq8064.c | 10 +++++-----
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1 file changed, 5 insertions(+), 5 deletions(-)
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@ -1,7 +1,7 @@
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From 53ae145a7afa7686e03332d61eed90b7fa7c2529 Mon Sep 17 00:00:00 2001
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From 000de5417107623925a4cf0310579f744ff43c28 Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Tue, 4 Feb 2020 19:38:06 +0100
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Subject: [PATCH v2] watchdog: qcom-wdt: disable pretimeout on timer platform
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Date: Tue, 4 Feb 2020 20:56:48 +0100
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Subject: watchdog: qcom-wdt: disable pretimeout on timer platform
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Some platform like ipq806x doesn't support pretimeout and define
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some interrupts used by qcom,msm-timer. Change the driver to check
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@ -9,6 +9,11 @@ and use pretimeout only on qcom,kpss-wdt as it's the only platform
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that actually supports it.
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Reviewed-by: Guenter Roeck <linux@roeck-us.net>
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Link: https://lore.kernel.org/r/20200204195648.23350-1-ansuelsmth@gmail.com
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[groeck: Conflict resolution]
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Signed-off-by: Guenter Roeck <linux@roeck-us.net>
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Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
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---
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drivers/watchdog/qcom-wdt.c | 31 +++++++++++++++++++++++--------
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1 file changed, 23 insertions(+), 8 deletions(-)
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@ -1,13 +1,16 @@
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From a16fcf911a020e46439a3bb3e702463fc3159831 Mon Sep 17 00:00:00 2001
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From 1aec193ea41d672d11592714cdda8167eb3b38fc Mon Sep 17 00:00:00 2001
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From: Abhishek Sahu <absahu@codeaurora.org>
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Date: Wed, 18 Nov 2015 12:38:56 +0530
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Subject: [PATCH 62/69] ipq806x: gcc: Added the enable regs and mask for PRNG
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Date: Wed, 18 Mar 2020 14:16:56 +0100
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Subject: ipq806x: gcc: Added the enable regs and mask for PRNG
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kernel got hanged while reading from /dev/hwrng at the
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Kernel got hanged while reading from /dev/hwrng at the
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time of PRNG clock enable
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Change-Id: I89856c7e19e6639508e6a2774304583a3ec91172
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Fixes: 24d8fba44af3 "clk: qcom: Add support for IPQ8064's global clock controller (GCC)"
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Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Link: https://lkml.kernel.org/r/20200318131657.345-1-ansuelsmth@gmail.com
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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drivers/clk/qcom/gcc-ipq806x.c | 2 ++
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1 file changed, 2 insertions(+)
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@ -1,9 +1,16 @@
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From d30840e2b1cf79d90392e6051b0c0b6006d29d8b Mon Sep 17 00:00:00 2001
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From: John Crispin <john@phrozen.org>
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Date: Thu, 9 Mar 2017 09:32:40 +0100
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Subject: [PATCH 64/69] clk: clk-rpm fixes
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From eec152734be10c72d2d413a27ca9d282c28cdb61 Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Tue, 10 Mar 2020 15:37:56 +0100
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Subject: clk: qcom: clk-rpm: add missing rpm clk for ipq806x
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Add missing definition of rpm clk for ipq806x soc
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Signed-off-by: John Crispin <john@phrozen.org>
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Acked-by: John Crispin <john@phrozen.org>
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Reviewed-by: Rob Herring <robh@kernel.org>
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Link: https://lkml.kernel.org/r/20200310143756.244-1-ansuelsmth@gmail.com
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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.../devicetree/bindings/clock/qcom,rpmcc.txt | 1 +
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drivers/clk/qcom/clk-rpm.c | 35 ++++++++++++++++++++++
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@ -12,32 +19,19 @@ Signed-off-by: John Crispin <john@phrozen.org>
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--- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
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+++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
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@@ -16,6 +16,7 @@ Required properties :
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@@ -15,6 +15,7 @@ Required properties :
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"qcom,rpmcc-msm8916", "qcom,rpmcc"
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"qcom,rpmcc-msm8974", "qcom,rpmcc"
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"qcom,rpmcc-apq8064", "qcom,rpmcc"
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"qcom,rpmcc-msm8996", "qcom,rpmcc"
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+ "qcom,rpmcc-ipq806x", "qcom,rpmcc"
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"qcom,rpmcc-msm8996", "qcom,rpmcc"
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"qcom,rpmcc-msm8998", "qcom,rpmcc"
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"qcom,rpmcc-qcs404", "qcom,rpmcc"
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--- a/include/dt-bindings/clock/qcom,rpmcc.h
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+++ b/include/dt-bindings/clock/qcom,rpmcc.h
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@@ -37,6 +37,10 @@
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#define RPM_XO_A0 27
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#define RPM_XO_A1 28
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#define RPM_XO_A2 29
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+#define RPM_NSS_FABRIC_0_CLK 30
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+#define RPM_NSS_FABRIC_0_A_CLK 31
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+#define RPM_NSS_FABRIC_1_CLK 32
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+#define RPM_NSS_FABRIC_1_A_CLK 33
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/* SMD RPM clocks */
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#define RPM_SMD_XO_CLK_SRC 0
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--- a/drivers/clk/qcom/clk-rpm.c
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+++ b/drivers/clk/qcom/clk-rpm.c
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@@ -512,6 +512,16 @@ DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a0_
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DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a1_clk, xo_a1_a_clk, 24);
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DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a2_clk, xo_a2_a_clk, 28);
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@@ -543,10 +543,45 @@ static const struct rpm_clk_desc rpm_clk
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.num_clks = ARRAY_SIZE(apq8064_clks),
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};
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+/* ipq806x */
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+DEFINE_CLK_RPM(ipq806x, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK);
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@ -49,13 +43,6 @@ Signed-off-by: John Crispin <john@phrozen.org>
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+DEFINE_CLK_RPM(ipq806x, nss_fabric_0_clk, nss_fabric_0_a_clk, QCOM_RPM_NSS_FABRIC_0_CLK);
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+DEFINE_CLK_RPM(ipq806x, nss_fabric_1_clk, nss_fabric_1_a_clk, QCOM_RPM_NSS_FABRIC_1_CLK);
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+
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static struct clk_rpm *apq8064_clks[] = {
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[RPM_APPS_FABRIC_CLK] = &apq8064_afab_clk,
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[RPM_APPS_FABRIC_A_CLK] = &apq8064_afab_a_clk,
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@@ -538,15 +548,40 @@ static struct clk_rpm *apq8064_clks[] =
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[RPM_XO_A2] = &apq8064_xo_a2_clk,
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};
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+static struct clk_rpm *ipq806x_clks[] = {
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+ [RPM_APPS_FABRIC_CLK] = &ipq806x_afab_clk,
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+ [RPM_APPS_FABRIC_A_CLK] = &ipq806x_afab_a_clk,
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@ -75,11 +62,6 @@ Signed-off-by: John Crispin <john@phrozen.org>
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+ [RPM_NSS_FABRIC_1_A_CLK] = &ipq806x_nss_fabric_1_a_clk,
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+};
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+
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static const struct rpm_clk_desc rpm_clk_apq8064 = {
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.clks = apq8064_clks,
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.num_clks = ARRAY_SIZE(apq8064_clks),
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};
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+static const struct rpm_clk_desc rpm_clk_ipq806x = {
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+ .clks = ipq806x_clks,
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+ .num_clks = ARRAY_SIZE(ipq806x_clks),
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@ -93,3 +75,16 @@ Signed-off-by: John Crispin <john@phrozen.org>
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{ }
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};
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MODULE_DEVICE_TABLE(of, rpm_clk_match_table);
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--- a/include/dt-bindings/clock/qcom,rpmcc.h
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+++ b/include/dt-bindings/clock/qcom,rpmcc.h
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@@ -37,6 +37,10 @@
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#define RPM_XO_A0 27
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#define RPM_XO_A1 28
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#define RPM_XO_A2 29
|
||||
+#define RPM_NSS_FABRIC_0_CLK 30
|
||||
+#define RPM_NSS_FABRIC_0_A_CLK 31
|
||||
+#define RPM_NSS_FABRIC_1_CLK 32
|
||||
+#define RPM_NSS_FABRIC_1_A_CLK 33
|
||||
|
||||
/* SMD RPM clocks */
|
||||
#define RPM_SMD_XO_CLK_SRC 0
|
||||
|
|
@ -1,9 +1,17 @@
|
|||
From ef10381ca4d01848ebedb4afb2c78feb8052f103 Mon Sep 17 00:00:00 2001
|
||||
From: Adrian Panella <ianchi74@outlook.com>
|
||||
Date: Thu, 9 Mar 2017 08:26:54 +0100
|
||||
Subject: [PATCH 53/69] regulator: add smb208 support
|
||||
From b5f25304aece9f2e7eaab275bbb5461c666bf38c Mon Sep 17 00:00:00 2001
|
||||
From: Ansuel Smith <ansuelsmth@gmail.com>
|
||||
Date: Wed, 19 Feb 2020 17:37:11 +0100
|
||||
Subject: regulator: add smb208 support
|
||||
|
||||
Smb208 regulators are used on some ipq806x soc.
|
||||
Add support for it to make it avaiable on some routers
|
||||
that use it.
|
||||
|
||||
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
|
||||
Signed-off-by: Adrian Panella <ianchi74@outlook.com>
|
||||
Acked-by: Lee Jones <lee.jones@linaro.org>
|
||||
Link: https://lore.kernel.org/r/20200219163711.479-1-ansuelsmth@gmail.com
|
||||
Signed-off-by: Mark Brown <broonie@kernel.org>
|
||||
---
|
||||
Documentation/devicetree/bindings/mfd/qcom-rpm.txt | 4 ++++
|
||||
drivers/regulator/qcom_rpm-regulator.c | 9 +++++++++
|
||||
|
|
@ -1,14 +1,21 @@
|
|||
From 5de1da6c862de6a92ac9aed521f21fd5a180f22b Mon Sep 17 00:00:00 2001
|
||||
From: Christian Lamparter <chunkeey@gmail.com>
|
||||
Date: Sat, 2 Feb 2019 02:48:35 +0100
|
||||
Subject: [PATCH] net: mdio: add ipq8064 mdio driver
|
||||
From caaa71fac36ec8c19145dbf8262a9b77ab09f1a1 Mon Sep 17 00:00:00 2001
|
||||
From: Ansuel Smith <ansuelsmth@gmail.com>
|
||||
Date: Wed, 4 Mar 2020 22:38:32 +0100
|
||||
Subject: net: mdio: add ipq8064 mdio driver
|
||||
|
||||
Currently ipq806x soc use generic bitbang driver to
|
||||
comunicate with the gmac ethernet interface.
|
||||
Add a dedicated driver created by chunkeey to fix this.
|
||||
|
||||
Co-developed-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
|
||||
Signed-off-by: David S. Miller <davem@davemloft.net>
|
||||
---
|
||||
drivers/net/phy/Kconfig | 8 ++
|
||||
drivers/net/phy/Makefile | 1 +
|
||||
drivers/net/phy/mdio-ipq8064.c | 163 +++++++++++++++++++++++++++++++++
|
||||
3 files changed, 172 insertions(+)
|
||||
drivers/net/phy/mdio-ipq8064.c | 166 +++++++++++++++++++++++++++++++++++++++++
|
||||
3 files changed, 175 insertions(+)
|
||||
create mode 100644 drivers/net/phy/mdio-ipq8064.c
|
||||
|
||||
--- a/drivers/net/phy/Kconfig
|
||||
|
|
@ -40,12 +47,13 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
|||
obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/net/phy/mdio-ipq8064.c
|
||||
@@ -0,0 +1,163 @@
|
||||
@@ -0,0 +1,166 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0
|
||||
+//
|
||||
+// Qualcomm IPQ8064 MDIO interface driver
|
||||
+//
|
||||
+// Copyright (C) 2019 Christian Lamparter <chunkeey@gmail.com>
|
||||
+/* Qualcomm IPQ8064 MDIO interface driver
|
||||
+ *
|
||||
+ * Copyright (C) 2019 Christian Lamparter <chunkeey@gmail.com>
|
||||
+ * Copyright (C) 2020 Ansuel Smith <ansuelsmth@gmail.com>
|
||||
+ */
|
||||
+
|
||||
+#include <linux/delay.h>
|
||||
+#include <linux/kernel.h>
|
||||
|
|
@ -74,8 +82,8 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
|||
+
|
||||
+#define MII_DATA_REG_ADDR 0x14
|
||||
+
|
||||
+#define MII_MDIO_DELAY (1000)
|
||||
+#define MII_MDIO_RETRY (10)
|
||||
+#define MII_MDIO_DELAY_USEC (1000)
|
||||
+#define MII_MDIO_RETRY_MSEC (10)
|
||||
+
|
||||
+struct ipq8064_mdio {
|
||||
+ struct regmap *base; /* NSS_GMAC0_BASE */
|
||||
|
|
@ -84,34 +92,30 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
|||
+static int
|
||||
+ipq8064_mdio_wait_busy(struct ipq8064_mdio *priv)
|
||||
+{
|
||||
+ int i;
|
||||
+ u32 busy;
|
||||
+
|
||||
+ for (i = 0; i < MII_MDIO_RETRY; i++) {
|
||||
+ unsigned int busy;
|
||||
+
|
||||
+ regmap_read(priv->base, MII_ADDR_REG_ADDR, &busy);
|
||||
+ if (!(busy & MII_BUSY))
|
||||
+ return 0;
|
||||
+
|
||||
+ udelay(MII_MDIO_DELAY);
|
||||
+ }
|
||||
+
|
||||
+ return -ETIMEDOUT;
|
||||
+ return regmap_read_poll_timeout(priv->base, MII_ADDR_REG_ADDR, busy,
|
||||
+ !(busy & MII_BUSY), MII_MDIO_DELAY_USEC,
|
||||
+ MII_MDIO_RETRY_MSEC * USEC_PER_MSEC);
|
||||
+}
|
||||
+
|
||||
+static int
|
||||
+ipq8064_mdio_read(struct mii_bus *bus, int phy_addr, int reg_offset)
|
||||
+{
|
||||
+ struct ipq8064_mdio *priv = bus->priv;
|
||||
+ u32 miiaddr = MII_BUSY | MII_CLKRANGE_250_300M;
|
||||
+ struct ipq8064_mdio *priv = bus->priv;
|
||||
+ u32 ret_val;
|
||||
+ int err;
|
||||
+
|
||||
+ /* Reject clause 45 */
|
||||
+ if (reg_offset & MII_ADDR_C45)
|
||||
+ return -EOPNOTSUPP;
|
||||
+
|
||||
+ miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) |
|
||||
+ ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK);
|
||||
+
|
||||
+ regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr);
|
||||
+ udelay(10);
|
||||
+ usleep_range(8, 10);
|
||||
+
|
||||
+ err = ipq8064_mdio_wait_busy(priv);
|
||||
+ if (err)
|
||||
|
|
@ -124,8 +128,12 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
|||
+static int
|
||||
+ipq8064_mdio_write(struct mii_bus *bus, int phy_addr, int reg_offset, u16 data)
|
||||
+{
|
||||
+ struct ipq8064_mdio *priv = bus->priv;
|
||||
+ u32 miiaddr = MII_WRITE | MII_BUSY | MII_CLKRANGE_250_300M;
|
||||
+ struct ipq8064_mdio *priv = bus->priv;
|
||||
+
|
||||
+ /* Reject clause 45 */
|
||||
+ if (reg_offset & MII_ADDR_C45)
|
||||
+ return -EOPNOTSUPP;
|
||||
+
|
||||
+ regmap_write(priv->base, MII_DATA_REG_ADDR, data);
|
||||
+
|
||||
|
|
@ -133,7 +141,7 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
|||
+ ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK);
|
||||
+
|
||||
+ regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr);
|
||||
+ udelay(10);
|
||||
+ usleep_range(8, 10);
|
||||
+
|
||||
+ return ipq8064_mdio_wait_busy(priv);
|
||||
+}
|
||||
|
|
@ -157,13 +165,14 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
|||
+ bus->parent = &pdev->dev;
|
||||
+
|
||||
+ priv = bus->priv;
|
||||
+ priv->base = syscon_node_to_regmap(np);
|
||||
+ if (IS_ERR_OR_NULL(priv->base)) {
|
||||
+ priv->base = syscon_regmap_lookup_by_phandle(np, "master");
|
||||
+ if (IS_ERR_OR_NULL(priv->base)) {
|
||||
+ pr_err("master phandle not found\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+ priv->base = device_node_to_regmap(np);
|
||||
+ if (IS_ERR(priv->base)) {
|
||||
+ if (priv->base == ERR_PTR(-EPROBE_DEFER))
|
||||
+ return -EPROBE_DEFER;
|
||||
+
|
||||
+ dev_err(&pdev->dev, "error getting device regmap, error=%pe\n",
|
||||
+ priv->base);
|
||||
+ return PTR_ERR(priv->base);
|
||||
+ }
|
||||
+
|
||||
+ ret = of_mdiobus_register(bus, np);
|
||||
|
|
@ -203,4 +212,5 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
|||
+
|
||||
+MODULE_DESCRIPTION("Qualcomm IPQ8064 MDIO interface driver");
|
||||
+MODULE_AUTHOR("Christian Lamparter <chunkeey@gmail.com>");
|
||||
+MODULE_AUTHOR("Ansuel Smith <ansuelsmth@gmail.com>");
|
||||
+MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in a new issue