From 53c2f174ad79397b53db0e52d43f44a0702a93da Mon Sep 17 00:00:00 2001 From: Zoltan HERPAI Date: Wed, 7 Jun 2023 12:13:11 +0200 Subject: [PATCH 01/29] uboot-sunxi: bump to 2023.04 Compile-tested: all boards Runtime-tested: - Cortex-A8: pcDuino - Cortex-A7: Bananapro, Bananapi M3 - Cortex-A53:Pine64+ Notes: - binman tries to add firmware for the SCP (system control processor), which we don't build, and is optional for the boot process on 64-bit. Disable this via setting the SCP envvar to /dev/null. For further info, see [1] . [1] https://github.com/u-boot/u-boot/blob/master/board/sunxi/README.sunxi64 Signed-off-by: Zoltan HERPAI --- package/boot/uboot-sunxi/Makefile | 6 +- .../003-add-theobroma-a31-pangolin.patch | 375 ------------------ .../patches/062-A20-improve-gmac-upload.patch | 2 +- .../063-fix-lime2-revK-add-micrel-PHY.patch | 44 -- ...1-sun6i-sync-PLL1-multdiv-with-Boot1.patch | 2 +- .../093-sun6i-fix-PLL-LDO-voltselect.patch | 6 +- .../100-sun6i-alternate-on-UART2.patch | 16 - .../101-sun6i-support-console-on-UART2.patch | 30 -- ...2-sunxi-make_CONS_INDEX-configurable.patch | 23 -- ...-environment-for-dtc-binary-location.patch | 2 +- .../patches/210-sunxi-deactivate-binman.patch | 37 -- .../230-disable-axp209-on-a13-olinuxino.diff | 19 - .../250-sun8i-h3-add-support-for-zeropi.patch | 148 ------- ...2-sunxi-h3-add-support-for-nanopi-r1.patch | 159 -------- ...nxi-h5-add-support-for-nanopi-r1s-h5.patch | 261 ------------ ...-arm-sunxi-increase-SYS_MALLOC_F_LEN.patch | 29 -- .../patches/300-force-pylibfdt-build.patch | 30 ++ 17 files changed, 39 insertions(+), 1150 deletions(-) delete mode 100644 package/boot/uboot-sunxi/patches/003-add-theobroma-a31-pangolin.patch delete mode 100644 package/boot/uboot-sunxi/patches/063-fix-lime2-revK-add-micrel-PHY.patch delete mode 100644 package/boot/uboot-sunxi/patches/100-sun6i-alternate-on-UART2.patch delete mode 100644 package/boot/uboot-sunxi/patches/101-sun6i-support-console-on-UART2.patch delete mode 100644 package/boot/uboot-sunxi/patches/102-sunxi-make_CONS_INDEX-configurable.patch delete mode 100644 package/boot/uboot-sunxi/patches/210-sunxi-deactivate-binman.patch delete mode 100644 package/boot/uboot-sunxi/patches/230-disable-axp209-on-a13-olinuxino.diff delete mode 100644 package/boot/uboot-sunxi/patches/250-sun8i-h3-add-support-for-zeropi.patch delete mode 100644 package/boot/uboot-sunxi/patches/253-sunxi-h5-add-support-for-nanopi-r1s-h5.patch delete mode 100644 package/boot/uboot-sunxi/patches/270-arm-sunxi-increase-SYS_MALLOC_F_LEN.patch create mode 100644 package/boot/uboot-sunxi/patches/300-force-pylibfdt-build.patch diff --git a/package/boot/uboot-sunxi/Makefile b/package/boot/uboot-sunxi/Makefile index 7cadf6ff32b..be4c8411a96 100644 --- a/package/boot/uboot-sunxi/Makefile +++ b/package/boot/uboot-sunxi/Makefile @@ -9,9 +9,9 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk -PKG_VERSION:=2020.07 +PKG_VERSION:=2023.04 -PKG_HASH:=c1f5bf9ee6bb6e648edbf19ce2ca9452f614b08a9f886f1a566aa42e8cf05f6a +PKG_HASH:=e31cac91545ff41b71cec5d8c22afd695645cd6e2a442ccdacacd60534069341 PKG_MAINTAINER:=Zoltan HERPAI @@ -392,7 +392,7 @@ UBOOT_TARGETS := \ UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes UBOOT_MAKE_FLAGS += \ - BL31=$(STAGING_DIR_IMAGE)/bl31_sunxi-$(ATF).bin + BL31=$(STAGING_DIR_IMAGE)/bl31_sunxi-$(ATF).bin SCP=/dev/null define Build/InstallDev $(INSTALL_DIR) $(STAGING_DIR_IMAGE) diff --git a/package/boot/uboot-sunxi/patches/003-add-theobroma-a31-pangolin.patch b/package/boot/uboot-sunxi/patches/003-add-theobroma-a31-pangolin.patch deleted file mode 100644 index fab06e6a8e7..00000000000 --- a/package/boot/uboot-sunxi/patches/003-add-theobroma-a31-pangolin.patch +++ /dev/null @@ -1,375 +0,0 @@ ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -475,6 +475,7 @@ dtb-$(CONFIG_MACH_SUN6I) += \ - sun6i-a31-m9.dtb \ - sun6i-a31-mele-a1000g-quad.dtb \ - sun6i-a31-mixtile-loftq.dtb \ -+ sun6i-a31-pangolin.dtb \ - sun6i-a31s-colorfly-e708-q1.dtb \ - sun6i-a31s-cs908.dtb \ - sun6i-a31s-inet-q972.dtb \ ---- a/arch/arm/dts/sun6i-a31.dtsi -+++ b/arch/arm/dts/sun6i-a31.dtsi -@@ -641,6 +641,11 @@ - function = "lcd0"; - }; - -+ i2c3_pins_a: i2c3@0 { -+ allwinner,pins = "PB5", "PB6"; -+ allwinner,function = "i2c3"; -+ }; -+ - mmc0_pins_a: mmc0@0 { - pins = "PF0", "PF1", "PF2", - "PF3", "PF4", "PF5"; ---- /dev/null -+++ b/arch/arm/dts/sun6i-a31-pangolin.dts -@@ -0,0 +1,292 @@ -+/* -+ * Copyright 2015, Theobroma Systems Design und Consulting GmbH -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPL or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This file is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * This file is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+/dts-v1/; -+#include "sun6i-a31.dtsi" -+#include "sunxi-common-regulators.dtsi" -+ -+#include -+#include -+ -+/ { -+ model = "Theobroma Systems A31 Pangolin"; -+ compatible = "tsd,a31-pangolin", "allwinner,sun6i-a31"; -+ -+ aliases { -+ serial0 = &uart0; -+ serial2 = &uart2; -+ spi0 = &spi0; -+ spi1 = &spi1; -+ spi2 = &spi2; -+ spi3 = &spi3; -+ }; -+ -+ chosen { -+ stdout-path = "serial2:115200n8"; -+ }; -+}; -+ -+&ehci0 { -+ status = "okay"; -+}; -+ -+&ohci0 { -+ status = "okay"; -+}; -+ -+&ehci1 { -+ status = "okay"; -+}; -+ -+&ohci1 { -+ status = "okay"; -+}; -+ -+&ohci2 { -+ status = "okay"; -+}; -+ -+&gmac { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gmac_pins_rgmii_a>; -+ phy = <&phy1>; -+ phy-mode = "rgmii"; -+ snps,reset-gpio = <&pio 0 7 GPIO_ACTIVE_LOW>; -+ snps,reset-active-low; -+ snps,reset-delays-us = <0 10000 30000>; -+ status = "okay"; -+ -+ phy1: ethernet-phy@4 { -+ reg = <4>; -+ }; -+}; -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins_a>; -+ status = "okay"; -+}; -+ -+&i2c1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c1_pins_a>; -+ status = "okay"; -+}; -+ -+&i2c2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c2_pins_a>; -+ status = "okay"; -+}; -+ -+&i2c3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c3_pins_a>; -+ status = "okay"; -+ -+ rtc_twi: rtc@6f { -+ compatible = "isil,isl1208"; -+ reg = <0x6f>; -+ }; -+ fan: fan@18 { -+ compatible = "ti,amc6821"; -+ reg = <0x18>; -+ cooling-min-state = <0>; -+ cooling-max-state = <9>; -+ #cooling-cells = <2>; -+ }; -+}; -+ -+&spi0 { -+ status = "okay"; -+ -+ flash: flash@0 { -+ compatible = "spansion,m25p40"; -+ spi-max-frequency = <16000000>; -+ spi-cpol; -+ spi-cpha; -+ }; -+}; -+ -+&spi1 { -+ status = "okay"; -+}; -+ -+&ir { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&ir_pins_a>; -+ status = "okay"; -+}; -+ -+&mmc0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_pangolin>; -+ vmmc-supply = <®_vcc3v0>; -+ bus-width = <4>; -+ cd-gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; /* PC19 */ -+ status = "okay"; -+}; -+ -+&mmc0_pins_a { -+ /* external pull-ups missing for some pins */ -+ allwinner,pull = ; -+}; -+ -+&mmc2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc2_pins_a>; -+ vmmc-supply = <®_vcc3v0>; -+ bus-width = <8>; -+ non-removable; -+ status = "okay"; -+}; -+ -+&pio { -+ mmc0_cd_pin_pangolin: mmc0_cd_pin@0 { -+ allwinner,pins = "PC19"; -+ allwinner,function = "gpio_in"; -+ allwinner,drive = ; -+ allwinner,pull = ; -+ }; -+ -+ leds_pins_pangolin: led_pins@0 { -+ allwinner,pins = "PH7", "PC16"; -+ allwinner,function = "gpio_out"; -+ allwinner,drive = ; -+ allwinner,pull = ; -+ }; -+ -+ mmc2_pins_a: mmc2@0 { -+ allwinner,pins = "PC6","PC7","PC8","PC9","PC10","PC11", -+ "PC12","PC13","PC14","PC15"; -+ allwinner,function = "mmc2"; -+ allwinner,drive = ; -+ allwinner,pull = ; -+ }; -+}; -+ -+&p2wi { -+ status = "okay"; -+ -+ axp221: pmic@68 { -+ compatible = "x-powers,axp221"; -+ reg = <0x68>; -+ interrupt-parent = <&nmi_intc>; -+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ dcdc1-supply = <&vcc_3v0>; -+ dcdc5-supply = <&vcc_dram>; -+ -+ regulators { -+ x-powers,dcdc-freq = <3000>; -+ -+ vcc_3v0: dcdc1 { -+ regulator-always-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-name = "vcc-3v0"; -+ }; -+ -+ vdd_cpu: dcdc2 { -+ regulator-always-on; -+ regulator-min-microvolt = <700000>; -+ regulator-max-microvolt = <1320000>; -+ regulator-name = "vdd-cpu"; -+ }; -+ -+ vdd_gpu: dcdc3 { -+ regulator-always-on; -+ regulator-min-microvolt = <700000>; -+ regulator-max-microvolt = <1320000>; -+ regulator-name = "vdd-gpu"; -+ }; -+ -+ vdd_sys_dll: dcdc4 { -+ regulator-always-on; -+ regulator-min-microvolt = <1100000>; -+ regulator-max-microvolt = <1100000>; -+ regulator-name = "vdd-sys-dll"; -+ }; -+ -+ vcc_dram: dcdc5 { -+ regulator-always-on; -+ regulator-min-microvolt = <1500000>; -+ regulator-max-microvolt = <1500000>; -+ regulator-name = "vcc-dram"; -+ }; -+ -+ vcc_wifi: aldo1 { -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc_wifi"; -+ }; -+ -+ avcc: aldo3 { -+ regulator-always-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-name = "avcc"; -+ }; -+ }; -+ }; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pins_a>; -+ status = "okay"; -+}; -+ -+&usb1_vbus_pin_a { -+ allwinner,pins = "PD23"; -+}; -+ -+®_usb1_vbus { -+ gpio = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD 23 */ -+ status = "okay"; -+}; -+ -+&usbphy { -+ status = "okay"; -+ usb1_vbus-supply = <®_usb1_vbus>; -+}; ---- /dev/null -+++ b/configs/pangolin_defconfig -@@ -0,0 +1,36 @@ -+CONFIG_SUNXI_PANGOLIN=y -+CONFIG_SPL=y -+CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC,RGMII" -+CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-pangolin" -+CONFIG_VIDEO_VGA_VIA_LCD=y -+CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25" -+CONFIG_ARM=y -+CONFIG_ARCH_SUNXI=y -+CONFIG_MACH_SUN6I=y -+CONFIG_DRAM_CHANNELS=1 -+CONFIG_DRAM_CLK=360 -+CONFIG_DRAM_ZQ=70 -+CONFIG_AXP_DCDC1_VOLT=3300 -+CONFIG_AXP_ALDO1_VOLT=0 -+CONFIG_AXP_ALDO2_VOLT=1800 -+CONFIG_AXP_ALDO3_VOLT=3000 -+CONFIG_AXP_DLDO4_VOLT=3300 -+CONFIG_AXP_ELDO1_VOLT=1200 -+CONFIG_AXP_ELDO2_VOLT=2500 -+CONFIG_AXP_ELDO3_VOLT=3300 -+CONFIG_MMC_SUNXI_SLOT_EXTRA=2 -+CONFIG_CONS_INDEX=3 -+# Vbus gpio for usb1 -+CONFIG_USB1_VBUS_PIN="" -+# No Vbus gpio for usb2 -+CONFIG_USB2_VBUS_PIN="" -+CONFIG_USB=y -+CONFIG_DM_USB=y -+CONFIG_USB_EHCI=y -+CONFIG_USB_KEYBOARD=y -+CONFIG_DM_ETH=y -+CONFIG_CMD_IMLS=n -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_DM_SPI=y -+CONFIG_DM_SPI_FLASH=y -+CONFIG_SUNXI_SPI=y ---- a/arch/arm/mach-sunxi/Kconfig -+++ b/arch/arm/mach-sunxi/Kconfig -@@ -896,6 +896,14 @@ config VIDEO_LCD_PANEL_I2C_SCL - Set the SCL pin for the LCD i2c interface. This takes a string in the - format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. - -+choice -+ prompt "Sunxi Board Variant" -+ optional -+ -+config SUNXI_PANGOLIN -+ bool "Theobroma A31 uQ7 Board" -+ -+endchoice - - # Note only one of these may be selected at a time! But hidden choices are - # not supported by Kconfig diff --git a/package/boot/uboot-sunxi/patches/062-A20-improve-gmac-upload.patch b/package/boot/uboot-sunxi/patches/062-A20-improve-gmac-upload.patch index 27b476472cf..13a703f307d 100644 --- a/package/boot/uboot-sunxi/patches/062-A20-improve-gmac-upload.patch +++ b/package/boot/uboot-sunxi/patches/062-A20-improve-gmac-upload.patch @@ -2,7 +2,7 @@ --- a/configs/A20-OLinuXino-Lime2_defconfig +++ b/configs/A20-OLinuXino-Lime2_defconfig -@@ -23,6 +23,7 @@ CONFIG_ETH_DESIGNWARE=y +@@ -26,6 +26,7 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y CONFIG_MII=y CONFIG_SUN7I_GMAC=y diff --git a/package/boot/uboot-sunxi/patches/063-fix-lime2-revK-add-micrel-PHY.patch b/package/boot/uboot-sunxi/patches/063-fix-lime2-revK-add-micrel-PHY.patch deleted file mode 100644 index e1ed58ee0d2..00000000000 --- a/package/boot/uboot-sunxi/patches/063-fix-lime2-revK-add-micrel-PHY.patch +++ /dev/null @@ -1,44 +0,0 @@ ---- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig -+++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig -@@ -8,6 +8,8 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 - CONFIG_USB0_VBUS_PIN="PC17" - CONFIG_USB0_VBUS_DET="PH5" - CONFIG_I2C1_ENABLE=y -+CONFIG_PHY_MICREL=y -+CONFIG_PHY_MICREL_KSZ90X1=y - CONFIG_SATAPWR="PC3" - CONFIG_SPL_SPI_SUNXI=y - CONFIG_AHCI=y ---- a/configs/A20-OLinuXino-Lime2_defconfig -+++ b/configs/A20-OLinuXino-Lime2_defconfig -@@ -7,6 +7,8 @@ CONFIG_MMC0_CD_PIN="PH1" - CONFIG_USB0_VBUS_PIN="PC17" - CONFIG_USB0_VBUS_DET="PH5" - CONFIG_I2C1_ENABLE=y -+CONFIG_PHY_MICREL=y -+CONFIG_PHY_MICREL_KSZ90X1=y - CONFIG_SATAPWR="PC3" - CONFIG_AHCI=y - # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ---- a/drivers/net/phy/micrel_ksz90x1.c -+++ b/drivers/net/phy/micrel_ksz90x1.c -@@ -14,6 +14,8 @@ - #include - #include - #include -+#include -+#include - - /* - * KSZ9021 - KSZ9031 common -@@ -344,6 +346,10 @@ static int ksz9031_phy_extwrite(struct p - static int ksz9031_config(struct phy_device *phydev) - { - int ret; -+ struct sunxi_ccm_reg *const ccm = -+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; -+ -+ setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_DELAY(4)); - - ret = ksz9031_of_config(phydev); - if (ret) diff --git a/package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch b/package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch index c637ccb792a..8605436b1ae 100644 --- a/package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch +++ b/package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch @@ -14,7 +14,7 @@ More specifically, the following settings are now used: --- a/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c -@@ -114,11 +114,12 @@ void clock_set_pll1(unsigned int clk) +@@ -131,11 +131,12 @@ void clock_set_pll1(unsigned int clk) struct sunxi_ccm_reg * const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; const int p = 0; diff --git a/package/boot/uboot-sunxi/patches/093-sun6i-fix-PLL-LDO-voltselect.patch b/package/boot/uboot-sunxi/patches/093-sun6i-fix-PLL-LDO-voltselect.patch index c20db1352ed..b5fa2a14157 100644 --- a/package/boot/uboot-sunxi/patches/093-sun6i-fix-PLL-LDO-voltselect.patch +++ b/package/boot/uboot-sunxi/patches/093-sun6i-fix-PLL-LDO-voltselect.patch @@ -18,7 +18,7 @@ required setting for the PLL LDO is 1.37v as per the A31 manual. --- a/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c -@@ -27,13 +27,26 @@ void clock_init_safe(void) +@@ -28,13 +28,26 @@ void clock_init_safe(void) struct sunxi_prcm_reg * const prcm = (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; @@ -47,8 +47,8 @@ required setting for the PLL LDO is 1.37v as per the A31 manual. #endif #if defined(CONFIG_MACH_SUN8I_R40) || defined(CONFIG_MACH_SUN50I) ---- a/arch/arm/include/asm/arch-sunxi/prcm.h -+++ b/arch/arm/include/asm/arch-sunxi/prcm.h +--- a/arch/arm/include/asm/arch-sunxi/prcm_sun6i.h ++++ b/arch/arm/include/asm/arch-sunxi/prcm_sun6i.h @@ -110,13 +110,13 @@ #define PRCM_PLL_CTRL_LDO_OUT_MASK \ __PRCM_PLL_CTRL_LDO_OUT(0x7) diff --git a/package/boot/uboot-sunxi/patches/100-sun6i-alternate-on-UART2.patch b/package/boot/uboot-sunxi/patches/100-sun6i-alternate-on-UART2.patch deleted file mode 100644 index a7afa513041..00000000000 --- a/package/boot/uboot-sunxi/patches/100-sun6i-alternate-on-UART2.patch +++ /dev/null @@ -1,16 +0,0 @@ -From d7311b6e7cdd1fc0e92665188e650934718cb2b1 Mon Sep 17 00:00:00 2001 -From: Philipp Tomsich -Date: Tue, 16 Jun 2015 10:52:01 +0200 -Subject: sun6i: define alternate-function for UART2 on GPG - - ---- a/arch/arm/include/asm/arch-sunxi/gpio.h -+++ b/arch/arm/include/asm/arch-sunxi/gpio.h -@@ -190,6 +190,7 @@ enum sunxi_gpio_number { - #define SUN6I_GPG_SDC1 2 - #define SUN8I_GPG_SDC1 2 - #define SUN6I_GPG_TWI3 2 -+#define SUN6I_GPG_UART2 2 - #define SUN5I_GPG_UART1 4 - - #define SUN6I_GPH_PWM 2 diff --git a/package/boot/uboot-sunxi/patches/101-sun6i-support-console-on-UART2.patch b/package/boot/uboot-sunxi/patches/101-sun6i-support-console-on-UART2.patch deleted file mode 100644 index 4cbf0ea1d8a..00000000000 --- a/package/boot/uboot-sunxi/patches/101-sun6i-support-console-on-UART2.patch +++ /dev/null @@ -1,30 +0,0 @@ -From c058dfb69136d62f88ae8b121104bdb7ce2df03f Mon Sep 17 00:00:00 2001 -From: Philipp Tomsich -Date: Tue, 16 Jun 2015 10:53:11 +0200 -Subject: ARM: sun6i: Support console on UART2 (GPG6/GPG7) - - ---- a/arch/arm/mach-sunxi/board.c -+++ b/arch/arm/mach-sunxi/board.c -@@ -132,6 +132,10 @@ static int gpio_init(void) - sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1); - sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1); - sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP); -+#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN6I) -+ sunxi_gpio_set_cfgpin(SUNXI_GPG(6), SUN6I_GPG_UART2); -+ sunxi_gpio_set_cfgpin(SUNXI_GPG(7), SUN6I_GPG_UART2); -+ sunxi_gpio_set_pull(SUNXI_GPG(7), SUNXI_GPIO_PULL_UP); - #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I) - sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2); - sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2); ---- a/include/configs/sunxi-common.h -+++ b/include/configs/sunxi-common.h -@@ -244,6 +244,8 @@ extern int soft_i2c_gpio_scl; - #endif - #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I) - #define OF_STDOUT_PATH "/soc@01c00000/serial@01c28400:115200" -+#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN6I) -+#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28800:115200" - #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I) - #define OF_STDOUT_PATH "/soc@01c00000/serial@01c28800:115200" - #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I) diff --git a/package/boot/uboot-sunxi/patches/102-sunxi-make_CONS_INDEX-configurable.patch b/package/boot/uboot-sunxi/patches/102-sunxi-make_CONS_INDEX-configurable.patch deleted file mode 100644 index b85e2af9fce..00000000000 --- a/package/boot/uboot-sunxi/patches/102-sunxi-make_CONS_INDEX-configurable.patch +++ /dev/null @@ -1,23 +0,0 @@ -From 78d5fab8e345b1273ec8c22d06f1a1d27670b518 Mon Sep 17 00:00:00 2001 -From: Philipp Tomsich -Date: Tue, 16 Jun 2015 10:59:38 +0200 -Subject: ARM: sunxi: Make CONS_INDEX configurable - - ---- a/arch/arm/mach-sunxi/Kconfig -+++ b/arch/arm/mach-sunxi/Kconfig -@@ -559,6 +559,14 @@ config SYS_BOARD - config SYS_SOC - default "sunxi" - -+config CONS_INDEX -+ int "UART used for console" -+ range 1 5 -+ default 1 -+ ---help--- -+ Defines the UART port used for serial output. It starts at 1 so UART0 is 1, -+ UART1 is 2 and so on. -+ - config UART0_PORT_F - bool "UART0 on MicroSD breakout board" - default n diff --git a/package/boot/uboot-sunxi/patches/200-mkimage-check-environment-for-dtc-binary-location.patch b/package/boot/uboot-sunxi/patches/200-mkimage-check-environment-for-dtc-binary-location.patch index 8aeae91ef46..fcc30ce35cd 100644 --- a/package/boot/uboot-sunxi/patches/200-mkimage-check-environment-for-dtc-binary-location.patch +++ b/package/boot/uboot-sunxi/patches/200-mkimage-check-environment-for-dtc-binary-location.patch @@ -17,7 +17,7 @@ Cc: Simon Glass --- a/tools/fit_image.c +++ b/tools/fit_image.c -@@ -751,9 +751,14 @@ static int fit_handle_file(struct image_ +@@ -754,9 +754,14 @@ static int fit_handle_file(struct image_ } *cmd = '\0'; } else if (params->datafile) { diff --git a/package/boot/uboot-sunxi/patches/210-sunxi-deactivate-binman.patch b/package/boot/uboot-sunxi/patches/210-sunxi-deactivate-binman.patch deleted file mode 100644 index 48ddf6d318d..00000000000 --- a/package/boot/uboot-sunxi/patches/210-sunxi-deactivate-binman.patch +++ /dev/null @@ -1,37 +0,0 @@ -From def280c4792262a368c8861312dc6b376181021f Mon Sep 17 00:00:00 2001 -From: Hauke Mehrtens -Date: Mon, 1 Jan 2018 23:10:56 +0100 -Subject: sunxi: deactivate binman - -Use the old way to generate the images instead of binman. -binman needs python with swig to avoid this host tool dependency use the -old way of generating images. ---- - Makefile | 7 ++++--- - 1 file changed, 4 insertions(+), 3 deletions(-) - ---- a/Makefile -+++ b/Makefile -@@ -1607,8 +1607,10 @@ endif - - ifneq ($(CONFIG_ARCH_SUNXI),) - ifeq ($(CONFIG_ARM64),) --u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img u-boot.dtb FORCE -- $(call if_changed,binman) -+OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \ -+ --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff -+u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img FORCE -+ $(call if_changed,pad_cat) - else - u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.itb FORCE - $(call if_changed,cat) ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -995,7 +995,6 @@ config ARCH_SOCFPGA - - config ARCH_SUNXI - bool "Support sunxi (Allwinner) SoCs" -- select BINMAN - select CMD_GPIO - select CMD_MMC if MMC - select CMD_USB if DISTRO_DEFAULTS diff --git a/package/boot/uboot-sunxi/patches/230-disable-axp209-on-a13-olinuxino.diff b/package/boot/uboot-sunxi/patches/230-disable-axp209-on-a13-olinuxino.diff deleted file mode 100644 index bc8bd144d6a..00000000000 --- a/package/boot/uboot-sunxi/patches/230-disable-axp209-on-a13-olinuxino.diff +++ /dev/null @@ -1,19 +0,0 @@ ---- a/configs/A13-OLinuXino_defconfig -+++ b/configs/A13-OLinuXino_defconfig -@@ -7,7 +7,6 @@ CONFIG_DRAM_EMR1=0 - CONFIG_MMC0_CD_PIN="PG0" - CONFIG_USB0_VBUS_DET="PG1" - CONFIG_USB1_VBUS_PIN="PG11" --CONFIG_AXP_GPIO=y - # CONFIG_VIDEO_HDMI is not set - CONFIG_VIDEO_VGA_VIA_LCD=y - CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y -@@ -20,7 +19,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y - CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino" - CONFIG_DFU_RAM=y - CONFIG_FASTBOOT_CMD_OEM_FORMAT=y --CONFIG_AXP_ALDO3_VOLT=3300 -+CONFIG_SUNXI_NO_PMIC=y - CONFIG_CONS_INDEX=2 - CONFIG_USB_EHCI_HCD=y - CONFIG_USB_OHCI_HCD=y diff --git a/package/boot/uboot-sunxi/patches/250-sun8i-h3-add-support-for-zeropi.patch b/package/boot/uboot-sunxi/patches/250-sun8i-h3-add-support-for-zeropi.patch deleted file mode 100644 index 838d90a7b00..00000000000 --- a/package/boot/uboot-sunxi/patches/250-sun8i-h3-add-support-for-zeropi.patch +++ /dev/null @@ -1,148 +0,0 @@ -From 2527b24f39d8f27ba2fd922ca27a1f14119cfa1b Mon Sep 17 00:00:00 2001 -From: Yu-Tung Chang -Date: Sat, 19 Jun 2021 16:16:45 +0800 -Subject: [PATCH] sunxi: h3: Add initial ZeroPi support - -ZeroPi is a new board of high performance with low cost -designed by FriendlyElec., using the Allwinner H3 SOC. - -ZeroPi features -- Allwinner H3, Quad-core Cortex-A7@1.2GHz -- 256MB/512MB DDR3 RAM -- microsd slot -- 10/100/1000Mbps Ethernet -- Debug Serial Port -- DC 5V/2A power-supply - -Signed-off-by: Yu-Tung Chang -Reviewed-by: Andre Przywara -Signed-off-by: Andre Przywara ---- ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -560,7 +560,8 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \ - sun8i-h3-orangepi-plus.dtb \ - sun8i-h3-orangepi-plus2e.dtb \ - sun8i-h3-orangepi-zero-plus2.dtb \ -- sun8i-h3-rervision-dvk.dtb -+ sun8i-h3-rervision-dvk.dtb \ -+ sun8i-h3-zeropi.dtb - dtb-$(CONFIG_MACH_SUN8I_R40) += \ - sun8i-r40-bananapi-m2-ultra.dtb \ - sun8i-v40-bananapi-m2-berry.dtb ---- /dev/null -+++ b/arch/arm/dts/sun8i-h3-zeropi.dts -@@ -0,0 +1,85 @@ -+/* -+ * Copyright (C) 2020 Yu-Tung Chang -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPL or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This file is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * This file is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+#include "sun8i-h3-nanopi.dtsi" -+ -+/ { -+ model = "FriendlyARM ZeroPi"; -+ compatible = "friendlyarm,zeropi", "allwinner,sun8i-h3"; -+ -+ aliases { -+ ethernet0 = &emac; -+ }; -+ -+ reg_gmac_3v3: gmac-3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "gmac-3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <100000>; -+ enable-active-high; -+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ -+ }; -+}; -+ -+&external_mdio { -+ ext_rgmii_phy: ethernet-phy@7 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <7>; -+ }; -+}; -+ -+&emac { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emac_rgmii_pins>; -+ phy-supply = <®_gmac_3v3>; -+ phy-handle = <&ext_rgmii_phy>; -+ phy-mode = "rgmii-id"; -+ -+ allwinner,leds-active-low; -+ status = "okay"; -+}; -+ -+&usb_otg { -+ status = "okay"; -+ dr_mode = "host"; -+}; ---- a/board/sunxi/MAINTAINERS -+++ b/board/sunxi/MAINTAINERS -@@ -508,3 +508,9 @@ YONES TOPTECH BS1078 V2 BOARD - M: Peter Korsgaard - S: Maintained - F: configs/Yones_Toptech_BS1078_V2_defconfig -+ -+ZEROPI BOARD -+M: Yu-Tung Chang -+S: Maintained -+F: configs/zeropi_defconfig -+F: arch/arm/dts/sun8i-h3-zeropi.dts ---- /dev/null -+++ b/configs/zeropi_defconfig -@@ -0,0 +1,13 @@ -+CONFIG_ARM=y -+CONFIG_ARCH_SUNXI=y -+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-zeropi" -+CONFIG_SPL=y -+CONFIG_MACH_SUN8I_H3=y -+CONFIG_DRAM_CLK=408 -+CONFIG_MACPWR="PD6" -+# CONFIG_VIDEO_DE2 is not set -+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -+CONFIG_CONSOLE_MUX=y -+CONFIG_SUN8I_EMAC=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_OHCI_HCD=y diff --git a/package/boot/uboot-sunxi/patches/252-sunxi-h3-add-support-for-nanopi-r1.patch b/package/boot/uboot-sunxi/patches/252-sunxi-h3-add-support-for-nanopi-r1.patch index 5b3a68c602b..51b4d7d045b 100644 --- a/package/boot/uboot-sunxi/patches/252-sunxi-h3-add-support-for-nanopi-r1.patch +++ b/package/boot/uboot-sunxi/patches/252-sunxi-h3-add-support-for-nanopi-r1.patch @@ -12,165 +12,6 @@ Signed-off-by: Jayantajit Gogoi create mode 100644 arch/arm/dts/sun8i-h3-nanopi-r1.dts create mode 100644 configs/nanopi_r1_defconfig ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -551,6 +551,7 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \ - sun8i-h3-nanopi-m1-plus.dtb \ - sun8i-h3-nanopi-neo.dtb \ - sun8i-h3-nanopi-neo-air.dtb \ -+ sun8i-h3-nanopi-r1.dtb \ - sun8i-h3-orangepi-2.dtb \ - sun8i-h3-orangepi-lite.dtb \ - sun8i-h3-orangepi-one.dtb \ ---- /dev/null -+++ b/arch/arm/dts/sun8i-h3-nanopi-r1.dts -@@ -0,0 +1,146 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (C) 2019 Igor Pecovnik -+ * Copyright (C) 2020 Jayantajit Gogoi -+ */ -+ -+/* NanoPi R1 is based on the NanoPi-H3 design from FriendlyARM */ -+#include "sun8i-h3-nanopi.dtsi" -+ -+/ { -+ model = "FriendlyARM NanoPi R1"; -+ compatible = "friendlyarm,nanopi-r1", "allwinner,sun8i-h3"; -+ -+ reg_gmac_3v3: gmac-3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "gmac-3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <100000>; -+ enable-active-high; -+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ vdd_cpux: gpio-regulator { -+ compatible = "regulator-gpio"; -+ pinctrl-names = "default"; -+ regulator-name = "vdd-cpux"; -+ regulator-type = "voltage"; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-min-microvolt = <1100000>; -+ regulator-max-microvolt = <1300000>; -+ regulator-ramp-delay = <50>; -+ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; -+ gpios-states = <0x1>; -+ states = <1100000 0x0 -+ 1300000 0x1>; -+ }; -+ -+ wifi_pwrseq: wifi_pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ pinctrl-names = "default"; -+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; -+ }; -+ -+ leds { -+ /delete-node/ pwr; -+ status { -+ label = "nanopi:red:status"; -+ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "heartbeat"; -+ }; -+ -+ wan { -+ label = "nanopi:green:wan"; -+ gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ lan { -+ label = "nanopi:green:lan"; -+ gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+ -+ r_gpio_keys { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sw_r_npi>; -+ -+ /delete-node/ k1; -+ reset { -+ label = "reset"; -+ linux,code = ; -+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vdd_cpux>; -+}; -+ -+&ehci1 { -+ status = "okay"; -+}; -+ -+&ehci2 { -+ status = "okay"; -+}; -+ -+&emac { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emac_rgmii_pins>; -+ phy-supply = <®_gmac_3v3>; -+ phy-handle = <&ext_rgmii_phy>; -+ phy-mode = "rgmii"; -+ status = "okay"; -+}; -+ -+&external_mdio { -+ ext_rgmii_phy: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <7>; -+ }; -+}; -+ -+&mmc1 { -+ vmmc-supply = <®_vcc3v3>; -+ vqmmc-supply = <®_vcc3v3>; -+ mmc-pwrseq = <&wifi_pwrseq>; -+ bus-width = <4>; -+ non-removable; -+ status = "okay"; -+ -+ sdio_wifi: sdio_wifi@1 { -+ reg = <1>; -+ compatible = "brcm,bcm4329-fmac"; -+ interrupt-parent = <&pio>; -+ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-names = "host-wake"; -+ }; -+}; -+ -+&mmc2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc2_8bit_pins>; -+ vmmc-supply = <®_vcc3v3>; -+ vqmmc-supply = <®_vcc3v3>; -+ bus-width = <8>; -+ non-removable; -+ status = "okay"; -+}; -+ -+&ohci1 { -+ status = "okay"; -+}; -+ -+&ohci2 { -+ status = "okay"; -+}; -+ -+&r_pio { -+ sw_r_npi: key_pins { -+ pins = "PL3"; -+ function = "gpio_in"; -+ }; -+}; --- /dev/null +++ b/configs/nanopi_r1_defconfig @@ -0,0 +1,21 @@ diff --git a/package/boot/uboot-sunxi/patches/253-sunxi-h5-add-support-for-nanopi-r1s-h5.patch b/package/boot/uboot-sunxi/patches/253-sunxi-h5-add-support-for-nanopi-r1s-h5.patch deleted file mode 100644 index 2c8d5a94593..00000000000 --- a/package/boot/uboot-sunxi/patches/253-sunxi-h5-add-support-for-nanopi-r1s-h5.patch +++ /dev/null @@ -1,261 +0,0 @@ -From e7510d24cab4741f72489b9d67c2d42b18fe5374 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Sun, 10 Oct 2021 21:36:57 +0800 -Subject: [PATCH] sunxi: Add support for FriendlyARM NanoPi R1S H5 - -This adds support for the NanoPi R1S H5 board. - -Allwinner H5 SoC -512MB DDR3 RAM -10/100/1000M Ethernet x 2 -RTL8189ETV WiFi 802.11b/g/n -USB 2.0 host port (A) -MicroSD Slot -Reset button -Serial Debug Port -WAN - LAN - SYS LED - -Signed-off-by: Chukun Pan ---- - arch/arm/dts/Makefile | 1 + - arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts | 195 +++++++++++++++++++++++ - board/sunxi/MAINTAINERS | 5 + - configs/nanopi_r1s_h5_defconfig | 14 ++ - 4 files changed, 215 insertions(+) - create mode 100644 arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts - create mode 100644 configs/nanopi_r1s_h5_defconfig - ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -575,6 +575,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \ - sun50i-h5-libretech-all-h5-cc.dtb \ - sun50i-h5-nanopi-neo2.dtb \ - sun50i-h5-nanopi-neo-plus2.dtb \ -+ sun50i-h5-nanopi-r1s-h5.dtb \ - sun50i-h5-orangepi-zero-plus.dtb \ - sun50i-h5-orangepi-pc2.dtb \ - sun50i-h5-orangepi-prime.dtb \ ---- /dev/null -+++ b/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts -@@ -0,0 +1,190 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (C) 2021 Chukun Pan -+ * -+ * Based on sun50i-h5-nanopi-neo-plus2.dts, which is: -+ * Copyright (C) 2017 Antony Antony -+ * Copyright (C) 2016 ARM Ltd. -+ */ -+ -+/dts-v1/; -+#include "sun50i-h5.dtsi" -+ -+#include -+#include -+ -+/ { -+ model = "FriendlyARM NanoPi R1S H5"; -+ compatible = "friendlyarm,nanopi-r1s-h5", "allwinner,sun50i-h5"; -+ -+ aliases { -+ ethernet0 = &emac; -+ ethernet1 = &rtl8189etv; -+ serial0 = &uart0; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ sys { -+ label = "nanopi:red:sys"; -+ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "heartbeat"; -+ }; -+ -+ lan { -+ label = "nanopi:green:lan"; -+ gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ wan { -+ label = "nanopi:green:wan"; -+ gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+ -+ r-gpio-keys { -+ compatible = "gpio-keys"; -+ -+ reset { -+ label = "reset"; -+ linux,code = ; -+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ reg_gmac_3v3: gmac-3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "gmac-3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <100000>; -+ enable-active-high; -+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ reg_vcc3v3: vcc3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ -+ reg_usb0_vbus: usb0-vbus { -+ compatible = "regulator-fixed"; -+ regulator-name = "usb0-vbus"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ enable-active-high; -+ gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ -+ status = "okay"; -+ }; -+ -+ vdd_cpux: gpio-regulator { -+ compatible = "regulator-gpio"; -+ regulator-name = "vdd-cpux"; -+ regulator-type = "voltage"; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-min-microvolt = <1100000>; -+ regulator-max-microvolt = <1300000>; -+ regulator-ramp-delay = <50>; /* 4ms */ -+ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; -+ gpios-states = <0x1>; -+ states = <1100000 0x0>, <1300000 0x1>; -+ }; -+ -+ wifi_pwrseq: wifi_pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ -+ post-power-on-delay-ms = <200>; -+ }; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vdd_cpux>; -+}; -+ -+&ehci1 { -+ status = "okay"; -+}; -+ -+&ehci2 { -+ status = "okay"; -+}; -+ -+&emac { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emac_rgmii_pins>; -+ phy-supply = <®_gmac_3v3>; -+ phy-handle = <&ext_rgmii_phy>; -+ phy-mode = "rgmii-id"; -+ status = "okay"; -+}; -+ -+&external_mdio { -+ ext_rgmii_phy: ethernet-phy@7 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <7>; -+ }; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ eeprom@51 { -+ compatible = "microchip,24c02"; -+ reg = <0x51>; -+ pagesize = <16>; -+ }; -+}; -+ -+&mmc0 { -+ vmmc-supply = <®_vcc3v3>; -+ bus-width = <4>; -+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ -+ status = "okay"; -+}; -+ -+&mmc1 { -+ vmmc-supply = <®_vcc3v3>; -+ vqmmc-supply = <®_vcc3v3>; -+ mmc-pwrseq = <&wifi_pwrseq>; -+ bus-width = <4>; -+ non-removable; -+ status = "okay"; -+ -+ rtl8189etv: sdio_wifi@1 { -+ reg = <1>; -+ }; -+}; -+ -+&ohci1 { -+ status = "okay"; -+}; -+ -+&ohci2 { -+ status = "okay"; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pa_pins>; -+ status = "okay"; -+}; -+ -+&usb_otg { -+ dr_mode = "peripheral"; -+ status = "okay"; -+}; -+ -+&usbphy { -+ /* USB Type-A port's VBUS is always on */ -+ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ -+ usb0_vbus-supply = <®_usb0_vbus>; -+ status = "okay"; -+}; ---- a/board/sunxi/MAINTAINERS -+++ b/board/sunxi/MAINTAINERS -@@ -358,6 +358,11 @@ M: Jelle van der Waa - S: Maintained - F: configs/nanopi_neo_air_defconfig - -+NANOPI-R1S-H5 BOARD -+M: Chukun Pan -+S: Maintained -+F: configs/nanopi_r1s_h5_defconfig -+ - NANOPI-A64 BOARD - M: Jagan Teki - S: Maintained ---- /dev/null -+++ b/configs/nanopi_r1s_h5_defconfig -@@ -0,0 +1,14 @@ -+CONFIG_ARM=y -+CONFIG_ARCH_SUNXI=y -+CONFIG_SPL=y -+CONFIG_MACH_SUN50I_H5=y -+CONFIG_DRAM_CLK=672 -+CONFIG_DRAM_ZQ=3881977 -+# CONFIG_DRAM_ODT_EN is not set -+CONFIG_MACPWR="PD6" -+CONFIG_MMC_SUNXI_SLOT_EXTRA=2 -+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-r1s-h5" -+CONFIG_SUN8I_EMAC=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_OHCI_HCD=y diff --git a/package/boot/uboot-sunxi/patches/270-arm-sunxi-increase-SYS_MALLOC_F_LEN.patch b/package/boot/uboot-sunxi/patches/270-arm-sunxi-increase-SYS_MALLOC_F_LEN.patch deleted file mode 100644 index 6ce2be908db..00000000000 --- a/package/boot/uboot-sunxi/patches/270-arm-sunxi-increase-SYS_MALLOC_F_LEN.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 20abdd7feefbb4fccef5c653e045911670237e8b Mon Sep 17 00:00:00 2001 -From: Stijn Tintel -Date: Thu, 22 Dec 2022 00:35:07 +0200 -Subject: [PATCH] arm: sunxi: increase SYS_MALLOC_F_LEN - -Version 2020.10 throws the following output after loading bl31: -alloc space exhausted - -This has been fixed in v2022.07, but the change is too intrusive to -backport. Instead, just modify the default for ARCH_SUNXI for now. - -See e05689242238 ("Kconfig: Change SYS_MALLOC_F_LEN default to 0x2000"). - -Signed-off-by: Stijn Tintel ---- - Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/Kconfig -+++ b/Kconfig -@@ -146,7 +146,7 @@ config SYS_MALLOC_F_LEN - default 0x2000 if (ARCH_IMX8 || ARCH_IMX8M || ARCH_MX7 || \ - ARCH_MX7ULP || ARCH_MX6 || ARCH_MX5 || \ - ARCH_LS1012A || ARCH_LS1021A || ARCH_LS1043A || \ -- ARCH_LS1046A || ARCH_QEMU) -+ ARCH_LS1046A || ARCH_QEMU || ARCH_SUNXI) - default 0x400 - help - Before relocation, memory is very limited on many platforms. Still, diff --git a/package/boot/uboot-sunxi/patches/300-force-pylibfdt-build.patch b/package/boot/uboot-sunxi/patches/300-force-pylibfdt-build.patch new file mode 100644 index 00000000000..d34ed6f2ae5 --- /dev/null +++ b/package/boot/uboot-sunxi/patches/300-force-pylibfdt-build.patch @@ -0,0 +1,30 @@ +--- a/Makefile ++++ b/Makefile +@@ -2000,26 +2000,7 @@ endif + # Check dtc and pylibfdt, if DTC is provided, else build them + PHONY += scripts_dtc + scripts_dtc: scripts_basic +- $(Q)if test "$(DTC)" = "$(DTC_INTREE)"; then \ +- $(MAKE) $(build)=scripts/dtc; \ +- else \ +- if ! $(DTC) -v >/dev/null; then \ +- echo '*** Failed to check dtc version: $(DTC)'; \ +- false; \ +- else \ +- if test "$(call dtc-version)" -lt $(DTC_MIN_VERSION); then \ +- echo '*** Your dtc is too old, please upgrade to dtc $(DTC_MIN_VERSION) or newer'; \ +- false; \ +- else \ +- if [ -n "$(CONFIG_PYLIBFDT)" ]; then \ +- if ! echo "import libfdt" | $(PYTHON3) 2>/dev/null; then \ +- echo '*** pylibfdt does not seem to be available with $(PYTHON3)'; \ +- false; \ +- fi; \ +- fi; \ +- fi; \ +- fi; \ +- fi ++ $(MAKE) $(build)=scripts/dtc + + # --------------------------------------------------------------------------- + quiet_cmd_cpp_lds = LDS $@ From b22d382ae4eaa1af42930115d91855f402314cac Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fabian=20Bl=C3=A4se?= Date: Sun, 6 Aug 2023 19:57:16 +0200 Subject: [PATCH 02/29] ipq40xx: re-add label MAC address for FritzBox 4040 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The MAC address of the GMAC is contained inside the CWMP-Account number on the label. The label MAC address alias was defined previously, but it has been removed with the switch to IPQESS / DSA. Restore the label MAC address alias. Fixes: 27b441cbaf42 ("ipq40xx: drop ESSEDMA + AR40xx DTS nodes") Signed-off-by: Fabian Bläse Reviewed-by: Robert Marko --- .../files/arch/arm/boot/dts/qcom-ipq4018-fritzbox-4040.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-fritzbox-4040.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-fritzbox-4040.dts index e448206c369..ec1112ee2bc 100644 --- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-fritzbox-4040.dts +++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-fritzbox-4040.dts @@ -14,6 +14,7 @@ led-failsafe = &flash; led-running = &power; led-upgrade = &flash; + label-mac-device = &gmac; }; soc { From 9e50708687507d1d10380532094b6e3ede4b39af Mon Sep 17 00:00:00 2001 From: John Audia Date: Sat, 26 Aug 2023 08:36:37 -0400 Subject: [PATCH 03/29] kernel: bump 6.1 to 6.1.48 Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.1.48 No patches changed in this bump, only update was to checksum. Build system: x86/64 Build-tested: x86/64/AMD Cezanne, filogic/xiaomi_redmi-router-ax6000-ubootmod Run-tested: x86/64/AMD Cezanne, filogic/xiaomi_redmi-router-ax6000-ubootmod Signed-off-by: John Audia --- include/kernel-6.1 | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/kernel-6.1 b/include/kernel-6.1 index 61bad0e5ca7..599ad1461ee 100644 --- a/include/kernel-6.1 +++ b/include/kernel-6.1 @@ -1,2 +1,2 @@ -LINUX_VERSION-6.1 = .47 -LINUX_KERNEL_HASH-6.1.47 = 93d58b6af007a5f44dd26831ff310707deb1ab9380c5136a534287eb3fddfcab +LINUX_VERSION-6.1 = .48 +LINUX_KERNEL_HASH-6.1.48 = c606cbd0353e677df6fae73cc16ba3c9244b98372ed7771d551024016f55ac31 From e80a3875172178cdcc02d13826717413cc1534a8 Mon Sep 17 00:00:00 2001 From: John Audia Date: Sat, 26 Aug 2023 12:56:53 -0400 Subject: [PATCH 04/29] kernel: bump 5.15 to 5.15.128 Changelog: https://cdn.kernel.org/pub/linux/kernel/v5.x/ChangeLog-5.15.128 All patches automatically rebased. Build system: x86_64 Build-tested: ramips/tplink_archer-a6-v3 Run-tested: ramips/tplink_archer-a6-v3 Signed-off-by: John Audia --- include/kernel-5.15 | 4 ++-- .../815-v6.4-05-net-phy-Add-a-binding-for-PHY-LEDs.patch | 2 +- ...Bluetooth-btusb-Support-public-address-configuration.patch | 4 ++-- ...Bluetooth-btusb-Fix-application-of-sizeof-to-pointer.patch | 2 +- .../711-net-dsa-mv88e6xxx-disable-ATU-violation.patch | 2 +- ...-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch | 2 +- 6 files changed, 8 insertions(+), 8 deletions(-) diff --git a/include/kernel-5.15 b/include/kernel-5.15 index c1c1e791f71..0f6e5c09d04 100644 --- a/include/kernel-5.15 +++ b/include/kernel-5.15 @@ -1,2 +1,2 @@ -LINUX_VERSION-5.15 = .127 -LINUX_KERNEL_HASH-5.15.127 = add0a575341b263a06e93599fc220a5dd34cb4ca5b9d05097a5db2a061928f26 +LINUX_VERSION-5.15 = .128 +LINUX_KERNEL_HASH-5.15.128 = 0f2eca845183fd76f53b0c867c97f12b9ace2d7e8ee2cdeec7eb2897651b80de diff --git a/target/linux/generic/backport-5.15/815-v6.4-05-net-phy-Add-a-binding-for-PHY-LEDs.patch b/target/linux/generic/backport-5.15/815-v6.4-05-net-phy-Add-a-binding-for-PHY-LEDs.patch index 7ca128b17d6..3e60f91a2a9 100644 --- a/target/linux/generic/backport-5.15/815-v6.4-05-net-phy-Add-a-binding-for-PHY-LEDs.patch +++ b/target/linux/generic/backport-5.15/815-v6.4-05-net-phy-Add-a-binding-for-PHY-LEDs.patch @@ -131,7 +131,7 @@ Signed-off-by: David S. Miller /** * fwnode_mdio_find_device - Given a fwnode, find the mdio_device * @fwnode: pointer to the mdio_device's fwnode -@@ -3118,6 +3189,11 @@ static int phy_probe(struct device *dev) +@@ -3120,6 +3191,11 @@ static int phy_probe(struct device *dev) /* Set the state to READY by default */ phydev->state = PHY_READY; diff --git a/target/linux/generic/backport-5.15/821-v5.16-Bluetooth-btusb-Support-public-address-configuration.patch b/target/linux/generic/backport-5.15/821-v5.16-Bluetooth-btusb-Support-public-address-configuration.patch index 98687126487..b23f9a4b9e2 100644 --- a/target/linux/generic/backport-5.15/821-v5.16-Bluetooth-btusb-Support-public-address-configuration.patch +++ b/target/linux/generic/backport-5.15/821-v5.16-Bluetooth-btusb-Support-public-address-configuration.patch @@ -17,7 +17,7 @@ Signed-off-by: Marcel Holtmann --- a/drivers/bluetooth/btusb.c +++ b/drivers/bluetooth/btusb.c -@@ -2272,6 +2272,23 @@ struct btmtk_section_map { +@@ -2275,6 +2275,23 @@ struct btmtk_section_map { }; } __packed; @@ -41,7 +41,7 @@ Signed-off-by: Marcel Holtmann static void btusb_mtk_wmt_recv(struct urb *urb) { struct hci_dev *hdev = urb->context; -@@ -3923,6 +3940,7 @@ static int btusb_probe(struct usb_interf +@@ -3926,6 +3943,7 @@ static int btusb_probe(struct usb_interf hdev->shutdown = btusb_mtk_shutdown; hdev->manufacturer = 70; hdev->cmd_timeout = btusb_mtk_cmd_timeout; diff --git a/target/linux/generic/backport-5.15/822-v5.17-Bluetooth-btusb-Fix-application-of-sizeof-to-pointer.patch b/target/linux/generic/backport-5.15/822-v5.17-Bluetooth-btusb-Fix-application-of-sizeof-to-pointer.patch index cff537a8669..6fe61a9defe 100644 --- a/target/linux/generic/backport-5.15/822-v5.17-Bluetooth-btusb-Fix-application-of-sizeof-to-pointer.patch +++ b/target/linux/generic/backport-5.15/822-v5.17-Bluetooth-btusb-Fix-application-of-sizeof-to-pointer.patch @@ -18,7 +18,7 @@ Signed-off-by: Marcel Holtmann --- a/drivers/bluetooth/btusb.c +++ b/drivers/bluetooth/btusb.c -@@ -2277,7 +2277,7 @@ static int btusb_set_bdaddr_mtk(struct h +@@ -2280,7 +2280,7 @@ static int btusb_set_bdaddr_mtk(struct h struct sk_buff *skb; long ret; diff --git a/target/linux/generic/hack-5.15/711-net-dsa-mv88e6xxx-disable-ATU-violation.patch b/target/linux/generic/hack-5.15/711-net-dsa-mv88e6xxx-disable-ATU-violation.patch index e62f45f3c33..f6dacb6e503 100644 --- a/target/linux/generic/hack-5.15/711-net-dsa-mv88e6xxx-disable-ATU-violation.patch +++ b/target/linux/generic/hack-5.15/711-net-dsa-mv88e6xxx-disable-ATU-violation.patch @@ -9,7 +9,7 @@ Subject: [PATCH] net/dsa/mv88e6xxx: disable ATU violation --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c -@@ -2985,6 +2985,9 @@ static int mv88e6xxx_setup_port(struct m +@@ -2993,6 +2993,9 @@ static int mv88e6xxx_setup_port(struct m else reg = 1 << port; diff --git a/target/linux/generic/pending-5.15/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch b/target/linux/generic/pending-5.15/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch index 18933de3a03..5aa540acf77 100644 --- a/target/linux/generic/pending-5.15/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch +++ b/target/linux/generic/pending-5.15/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch @@ -17,7 +17,7 @@ Signed-off-by: Tobias Waldekranz --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c -@@ -6333,6 +6333,7 @@ static int mv88e6xxx_register_switch(str +@@ -6341,6 +6341,7 @@ static int mv88e6xxx_register_switch(str ds->ops = &mv88e6xxx_switch_ops; ds->ageing_time_min = chip->info->age_time_coeff; ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; From a4eb1ea3319296d99d36be8c4d786f4e3ee6acb9 Mon Sep 17 00:00:00 2001 From: Rani Hod Date: Tue, 25 Apr 2023 01:26:28 +0300 Subject: [PATCH 05/29] ramips: add support for D-Link DRA-1360 The DRA-1360 rev A is a wall-plug AC1300 repeater. Hardware is identical (same FCC ID, black case instead of white) to D-Link DAP-1620 rev B, which is already supported, but a different model name, revision, and hardware ID are needed. Thus, the bulk of the DAP-1620 device tree is extracted to a common dtsi included by the two models' device trees. Repeating specs and installation instructions from e4c7703: (note that the RAM size mentioned there was incorrect, oops) Specs: - SoC: MT7621AT (880MHz dual-core MIPS1004Kc) - Memory: 128 MiB RAM, 16 MiB NOR SPI - WiFi: MT7615DN 2x2 802.11n + 2x2 802.11ac (DBDC) - Ethernet: 1 RJ45 port 10/100/1000 - Power/status LED: red+green - LED RSSI bargraph: 2x green, 1x red+green Installation: - Keep reset button pressed during plug-in - Web Recovery Updater is at 192.168.0.50 (pings are ignored, it listens only for http) - Upload factory.bin, confirm flashing (seems to work best with Chromium-based browsers) Revert to OEM firmware: - tail -c+117 DRA1360A1_FW112B03.bin | \ openssl aes-256-cbc -d -md md5 -out decrypted.bin \ -k c471706398cb147c6619f8a04a18d53e9c17ede8 - flash decrypted.bin via D-Link Web Recovery Signed-off-by: Rani Hod --- .../ramips/dts/mt7621_dlink_dap-1620-b1.dts | 152 +---------------- .../ramips/dts/mt7621_dlink_dra-1360-a1.dts | 8 + .../ramips/dts/mt7621_dlink_dxx-1xx0-x1.dtsi | 154 ++++++++++++++++++ target/linux/ramips/image/mt7621.mk | 20 ++- .../mt7621/base-files/etc/board.d/01_leds | 3 +- .../mt7621/base-files/etc/board.d/02_network | 1 + .../etc/hotplug.d/ieee80211/10_fix_wifi_mac | 3 +- 7 files changed, 184 insertions(+), 157 deletions(-) create mode 100644 target/linux/ramips/dts/mt7621_dlink_dra-1360-a1.dts create mode 100644 target/linux/ramips/dts/mt7621_dlink_dxx-1xx0-x1.dtsi diff --git a/target/linux/ramips/dts/mt7621_dlink_dap-1620-b1.dts b/target/linux/ramips/dts/mt7621_dlink_dap-1620-b1.dts index 919e5be4b9c..5005eb1a724 100644 --- a/target/linux/ramips/dts/mt7621_dlink_dap-1620-b1.dts +++ b/target/linux/ramips/dts/mt7621_dlink_dap-1620-b1.dts @@ -1,158 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT -#include "mt7621.dtsi" - -#include -#include +#include "mt7621_dlink_dxx-1xx0-x1.dtsi" / { compatible = "dlink,dap-1620-b1", "mediatek,mt7621-soc"; model = "D-Link DAP-1620 B1"; - - aliases { - label-mac-device = &gmac0; - - led-boot = &led_status_red; - led-failsafe = &led_status_green; - led-running = &led_status_green; - led-upgrade = &led_status_red; - }; - - keys { - compatible = "gpio-keys"; - - reset { - label = "reset"; - gpios = <&gpio 7 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - }; - - wps { - label = "wps"; - gpios = <&gpio 18 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - - led_status_red: status_red { - label = "red:status"; - gpios = <&gpio 16 GPIO_ACTIVE_LOW>; - }; - - led_status_green: status_green { - label = "green:status"; - gpios = <&gpio 13 GPIO_ACTIVE_LOW>; - }; - - rssi_low_red { - label = "red:rssilow"; - gpios = <&gpio 25 GPIO_ACTIVE_LOW>; - }; - - rssi_low_green { - label = "green:rssilow"; - gpios = <&gpio 24 GPIO_ACTIVE_LOW>; - }; - - rssi_med_green { - label = "green:rssimed"; - gpios = <&gpio 23 GPIO_ACTIVE_LOW>; - }; - - rssi_high_green { - label = "green:rssihigh"; - gpios = <&gpio 22 GPIO_ACTIVE_LOW>; - }; - }; }; - -&spi0 { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_factory_e000: macaddr@e000 { - reg = <0xe000 0x6>; - }; - }; - - partition@50000 { - compatible = "denx,uimage"; - label = "firmware"; - reg = <0x50000 0xfb0000>; - }; - }; - }; -}; - -&pcie { - status = "okay"; -}; - -&pcie0 { - wifi@0,0 { - compatible = "mediatek,mt76"; - reg = <0x0000 0 0 0 0>; - mediatek,mtd-eeprom = <&factory 0x0>; - /* The correct MAC addresses are set in 10_fix_wifi_mac. */ - }; -}; - -&gmac0 { - nvmem-cells = <&macaddr_factory_e000>; - nvmem-cell-names = "mac-address"; -}; - -&switch0 { - ports { - port@0 { - status = "okay"; - label = "lan"; - }; - }; -}; - -ðernet { - pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>; -}; - -&state_default { - gpio { - groups = "uart3", "jtag", "wdt"; - function = "gpio"; - }; -}; - diff --git a/target/linux/ramips/dts/mt7621_dlink_dra-1360-a1.dts b/target/linux/ramips/dts/mt7621_dlink_dra-1360-a1.dts new file mode 100644 index 00000000000..294093b6ff1 --- /dev/null +++ b/target/linux/ramips/dts/mt7621_dlink_dra-1360-a1.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "mt7621_dlink_dxx-1xx0-x1.dtsi" + +/ { + compatible = "dlink,dra-1360-a1", "mediatek,mt7621-soc"; + model = "D-Link DRA-1360 A1"; +}; diff --git a/target/linux/ramips/dts/mt7621_dlink_dxx-1xx0-x1.dtsi b/target/linux/ramips/dts/mt7621_dlink_dxx-1xx0-x1.dtsi new file mode 100644 index 00000000000..8fb6de7c480 --- /dev/null +++ b/target/linux/ramips/dts/mt7621_dlink_dxx-1xx0-x1.dtsi @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "mt7621.dtsi" + +#include +#include + +/ { + aliases { + label-mac-device = &gmac0; + + led-boot = &led_status_red; + led-failsafe = &led_status_green; + led-running = &led_status_green; + led-upgrade = &led_status_red; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + gpios = <&gpio 7 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + }; + + wps { + label = "wps"; + gpios = <&gpio 18 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_status_red: status_red { + label = "red:status"; + gpios = <&gpio 16 GPIO_ACTIVE_LOW>; + }; + + led_status_green: status_green { + label = "green:status"; + gpios = <&gpio 13 GPIO_ACTIVE_LOW>; + }; + + rssi_low_red { + label = "red:rssilow"; + gpios = <&gpio 25 GPIO_ACTIVE_LOW>; + }; + + rssi_low_green { + label = "green:rssilow"; + gpios = <&gpio 24 GPIO_ACTIVE_LOW>; + }; + + rssi_med_green { + label = "green:rssimed"; + gpios = <&gpio 23 GPIO_ACTIVE_LOW>; + }; + + rssi_high_green { + label = "green:rssihigh"; + gpios = <&gpio 22 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&spi0 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_factory_e000: macaddr@e000 { + reg = <0xe000 0x6>; + }; + }; + + partition@50000 { + compatible = "denx,uimage"; + label = "firmware"; + reg = <0x50000 0xfb0000>; + }; + }; + }; +}; + +&pcie { + status = "okay"; +}; + +&pcie0 { + wifi@0,0 { + compatible = "mediatek,mt76"; + reg = <0x0000 0 0 0 0>; + mediatek,mtd-eeprom = <&factory 0x0>; + /* The correct MAC addresses are set in 10_fix_wifi_mac. */ + }; +}; + +&gmac0 { + nvmem-cells = <&macaddr_factory_e000>; + nvmem-cell-names = "mac-address"; +}; + +&switch0 { + ports { + port@0 { + status = "okay"; + label = "lan"; + }; + }; +}; + +ðernet { + pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>; +}; + +&state_default { + gpio { + groups = "uart3", "jtag", "wdt"; + function = "gpio"; + }; +}; diff --git a/target/linux/ramips/image/mt7621.mk b/target/linux/ramips/image/mt7621.mk index ad45613a0b4..338cbae5b6a 100644 --- a/target/linux/ramips/image/mt7621.mk +++ b/target/linux/ramips/image/mt7621.mk @@ -614,12 +614,9 @@ define Device/cudy_x6-v2 endef TARGET_DEVICES += cudy_x6-v2 -define Device/dlink_dap-1620-b1 +define Device/dlink_dxx-1xx0-x1 DEVICE_VENDOR := D-Link - DEVICE_MODEL := DAP-1620 - DEVICE_VARIANT := B1 DEVICE_PACKAGES := kmod-mt7615-firmware rssileds - DLINK_HWID := MT76XMT7621-RP-PR2475-NA IMAGE_SIZE := 16064k IMAGES += factory.bin IMAGE/factory.bin := $$(sysupgrade_bin) | \ @@ -628,6 +625,13 @@ define Device/dlink_dap-1620-b1 append-string $$(DLINK_HWID) | \ check-size endef + +define Device/dlink_dap-1620-b1 + $(Device/dlink_dxx-1xx0-x1) + DEVICE_MODEL := DAP-1620 + DEVICE_VARIANT := B1 + DLINK_HWID := MT76XMT7621-RP-PR2475-NA +endef TARGET_DEVICES += dlink_dap-1620-b1 define Device/dlink_dap-x1860-a1 @@ -799,6 +803,14 @@ define Device/dlink_dir-882-r1 endef TARGET_DEVICES += dlink_dir-882-r1 +define Device/dlink_dra-1360-a1 + $(Device/dlink_dxx-1xx0-x1) + DEVICE_MODEL := DRA-1360 + DEVICE_VARIANT := A1 + DLINK_HWID := MT76XMT7621-RP-RA1360-NA +endef +TARGET_DEVICES += dlink_dra-1360-a1 + define Device/dual-q_h721 $(Device/dsa-migration) $(Device/uimage-lzma-loader) diff --git a/target/linux/ramips/mt7621/base-files/etc/board.d/01_leds b/target/linux/ramips/mt7621/base-files/etc/board.d/01_leds index 1de35104c32..1e13c04c2f2 100644 --- a/target/linux/ramips/mt7621/base-files/etc/board.d/01_leds +++ b/target/linux/ramips/mt7621/base-files/etc/board.d/01_leds @@ -69,7 +69,8 @@ jcg,y2|\ xzwifi,creativebox-v1) ucidef_set_led_netdev "internet" "internet" "blue:internet" "wan" ;; -dlink,dap-1620-b1) +dlink,dap-1620-b1|\ +dlink,dra-1360-a1) ucidef_set_rssimon "wlan1" "200000" "1" ucidef_set_led_rssi "rssilow" "RSSILOW" "red:rssilow" "wlan1" "1" "40" ucidef_set_led_rssi "rssimediumlow" "RSSIMEDIUMLOW" "green:rssilow" "wlan1" "21" "100" diff --git a/target/linux/ramips/mt7621/base-files/etc/board.d/02_network b/target/linux/ramips/mt7621/base-files/etc/board.d/02_network index bd4cb508126..7bd5e83c5a1 100644 --- a/target/linux/ramips/mt7621/base-files/etc/board.d/02_network +++ b/target/linux/ramips/mt7621/base-files/etc/board.d/02_network @@ -16,6 +16,7 @@ ramips_setup_interfaces() asus,rp-ac87|\ dlink,dap-1620-b1|\ dlink,dap-x1860-a1|\ + dlink,dra-1360-a1|\ edimax,re23s|\ linksys,re7000|\ mikrotik,ltap-2hnd|\ diff --git a/target/linux/ramips/mt7621/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac b/target/linux/ramips/mt7621/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac index a15b4a225f2..96b49ff00ae 100644 --- a/target/linux/ramips/mt7621/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac +++ b/target/linux/ramips/mt7621/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac @@ -38,7 +38,8 @@ case "$board" in macaddr_setbit_la "$(macaddr_add $hw_mac_addr 0x100000)" > /sys${DEVPATH}/macaddress ;; dlink,dap-1620-b1|\ - dlink,dir-853-a1) + dlink,dir-853-a1|\ + dlink,dra-1360-a1) lan_mac_addr="$(mtd_get_mac_binary factory 0xe000)" [ "$PHYNBR" = "0" ] && \ macaddr_add $lan_mac_addr 1 > /sys${DEVPATH}/macaddress From 0405e11a7125cce2454f36035a9a772e25fc5258 Mon Sep 17 00:00:00 2001 From: Antonio Flores Date: Sat, 8 Jul 2023 13:26:31 -0400 Subject: [PATCH 06/29] uboot-rockchip: add support for PINE64 ROCK64 Add uboot support for PINE64 ROCK64, rockchip rk3328 board. Signed-off-by: Antonio Flores --- package/boot/uboot-rockchip/Makefile | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index 2d44c218f24..f424abbd445 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -66,6 +66,13 @@ define U-Boot/roc-cc-rk3328 firefly_roc-rk3328-cc endef +define U-Boot/rock64-rk3328 + $(U-Boot/rk3328/Default) + NAME:=Rock64 + BUILD_DEVICES:= \ + pine64_rock64 +endef + # RK3399 boards define U-Boot/rk3399/Default @@ -111,7 +118,8 @@ UBOOT_TARGETS := \ nanopi-r2s-rk3328 \ orangepi-r1-plus-rk3328 \ orangepi-r1-plus-lts-rk3328 \ - roc-cc-rk3328 + roc-cc-rk3328 \ + rock64-rk3328 UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes From c0c4efe6f1443074e5cb0ef336cd0440bd972b61 Mon Sep 17 00:00:00 2001 From: Antonio Flores Date: Sat, 8 Jul 2023 13:29:56 -0400 Subject: [PATCH 07/29] uboot-rockchip: fix swig dependency for ROCK64 Pre build files to fix swig dependency. Signed-off-by: Antonio Flores --- .../src/of-platdata/rock64-rk3328/dt-decl.h | 27 +++ .../src/of-platdata/rock64-rk3328/dt-plat.c | 219 ++++++++++++++++++ .../rock64-rk3328/dt-structs-gen.h | 63 +++++ 3 files changed, 309 insertions(+) create mode 100644 package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-decl.h create mode 100644 package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-plat.c create mode 100644 package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-structs-gen.h diff --git a/package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-decl.h b/package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-decl.h new file mode 100644 index 00000000000..a13aaea1fb1 --- /dev/null +++ b/package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-decl.h @@ -0,0 +1,27 @@ +/* + * DO NOT MODIFY + * + * Declares externs for all device/uclass instances. + * This was generated by dtoc from a .dtb (device tree binary) file. + */ + +#include +#include + +/* driver declarations - these allow DM_DRIVER_GET() to be used */ +extern U_BOOT_DRIVER(rockchip_rk3328_cru); +extern U_BOOT_DRIVER(rockchip_rk3328_dmc); +extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc); +extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc); +extern U_BOOT_DRIVER(ns16550_serial); +extern U_BOOT_DRIVER(rockchip_rk3328_spi); +extern U_BOOT_DRIVER(jedec_spi_nor); +extern U_BOOT_DRIVER(rockchip_rk3328_grf); + +/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */ +extern UCLASS_DRIVER(clk); +extern UCLASS_DRIVER(mmc); +extern UCLASS_DRIVER(ram); +extern UCLASS_DRIVER(serial); +extern UCLASS_DRIVER(spi_flash); +extern UCLASS_DRIVER(syscon); diff --git a/package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-plat.c b/package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-plat.c new file mode 100644 index 00000000000..70a8c001a3f --- /dev/null +++ b/package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-plat.c @@ -0,0 +1,219 @@ +/* + * DO NOT MODIFY + * + * Declares the U_BOOT_DRIVER() records and platform data. + * This was generated by dtoc from a .dtb (device tree binary) file. + */ + +/* Allow use of U_BOOT_DRVINFO() in this file */ +#define DT_PLAT_C + +#include +#include +#include + +/* + * driver_info declarations, ordered by 'struct driver_info' linker_list idx: + * + * idx driver_info driver + * --- -------------------- -------------------- + * 0: clock_controller_at_ff440000 rockchip_rk3328_cru + * 1: dmc rockchip_rk3328_dmc + * 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc + * 3: mmc_at_ff520000 rockchip_rk3288_dw_mshc + * 4: serial_at_ff130000 ns16550_serial + * 5: spi_at_ff190000 rockchip_rk3328_spi + * 6: spiflash_at_0 jedec_spi_nor + * 7: syscon_at_ff100000 rockchip_rk3328_grf + * --- -------------------- -------------------- + */ + +/* + * Node /clock-controller@ff440000 index 0 + * driver rockchip_rk3328_cru parent None + */ +static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = { + .reg = {0xff440000, 0x1000}, + .rockchip_grf = 0x3b, +}; +U_BOOT_DRVINFO(clock_controller_at_ff440000) = { + .name = "rockchip_rk3328_cru", + .plat = &dtv_clock_controller_at_ff440000, + .plat_size = sizeof(dtv_clock_controller_at_ff440000), + .parent_idx = -1, +}; + +/* + * Node /dmc index 1 + * driver rockchip_rk3328_dmc parent None + */ +static struct dtd_rockchip_rk3328_dmc dtv_dmc = { + .reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000, + 0xff720000, 0x1000, 0xff798000, 0x1000}, + .rockchip_sdram_params = {0x1, 0xc, 0x3, 0x1, 0x0, 0x0, 0x10, 0x10, + 0x10, 0x10, 0x0, 0x98899459, 0x0, 0x2e, 0x544, 0x15, + 0x432, 0xff, 0x320, 0x6, 0x1, 0x0, 0x1, 0x0, + 0x43041008, 0x64, 0x300054, 0xd0, 0x500002, 0xd4, 0x10000, 0xd8, + 0xe03, 0xdc, 0x43001a, 0xe0, 0x10000, 0xe4, 0xe0005, 0xf4, + 0xf011f, 0x100, 0xb141b11, 0x104, 0x3031a, 0x108, 0x3060809, 0x10c, + 0x606000, 0x110, 0x8020409, 0x114, 0x1010606, 0x118, 0x2020004, 0x120, + 0x404, 0x138, 0x58, 0x180, 0x900024, 0x184, 0x1400000, 0x190, + 0x7050002, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240, 0xa020b28, 0x244, + 0x101, 0x250, 0xf00, 0x490, 0x1, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xb, 0x28, 0xc, 0x2c, + 0x0, 0x30, 0x6, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79, + 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87, + 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78, + 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, + 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, + 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, + 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, + 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9, + 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, + 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77, + 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78, + 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, + 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77, + 0x77, 0x77, 0x79, 0x9}, +}; +U_BOOT_DRVINFO(dmc) = { + .name = "rockchip_rk3328_dmc", + .plat = &dtv_dmc, + .plat_size = sizeof(dtv_dmc), + .parent_idx = -1, +}; + +/* + * Node /mmc@ff500000 index 2 + * driver rockchip_rk3288_dw_mshc parent None + */ +static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = { + .bus_width = 0x4, + .cap_mmc_highspeed = true, + .cap_sd_highspeed = true, + .clocks = { + {0, {317}}, + {0, {33}}, + {0, {74}}, + {0, {78}},}, + .disable_wp = true, + .fifo_depth = 0x100, + .interrupts = {0x0, 0xc, 0x4}, + .max_frequency = 0x8f0d180, + .pinctrl_0 = {0x4a, 0x4b, 0x4c, 0x4d}, + .pinctrl_names = "default", + .reg = {0xff500000, 0x4000}, + .u_boot_spl_fifo_mode = true, + .vmmc_supply = 0x4e, +}; +U_BOOT_DRVINFO(mmc_at_ff500000) = { + .name = "rockchip_rk3288_dw_mshc", + .plat = &dtv_mmc_at_ff500000, + .plat_size = sizeof(dtv_mmc_at_ff500000), + .parent_idx = -1, +}; + +/* + * Node /mmc@ff520000 index 3 + * driver rockchip_rk3288_dw_mshc parent None + */ +static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff520000 = { + .bus_width = 0x8, + .cap_mmc_highspeed = true, + .clocks = { + {0, {319}}, + {0, {35}}, + {0, {76}}, + {0, {80}},}, + .fifo_depth = 0x100, + .interrupts = {0x0, 0xe, 0x4}, + .max_frequency = 0x8f0d180, + .mmc_hs200_1_8v = true, + .non_removable = true, + .pinctrl_0 = {0x4f, 0x50, 0x51, 0x0}, + .pinctrl_names = "default", + .reg = {0xff520000, 0x4000}, + .u_boot_spl_fifo_mode = true, + .vmmc_supply = 0x1e, + .vqmmc_supply = 0x1f, +}; +U_BOOT_DRVINFO(mmc_at_ff520000) = { + .name = "rockchip_rk3288_dw_mshc", + .plat = &dtv_mmc_at_ff520000, + .plat_size = sizeof(dtv_mmc_at_ff520000), + .parent_idx = -1, +}; + +/* + * Node /serial@ff130000 index 4 + * driver ns16550_serial parent None + */ +static struct dtd_ns16550_serial dtv_serial_at_ff130000 = { + .clock_frequency = 0x16e3600, + .clocks = { + {0, {40}}, + {0, {212}},}, + .dma_names = {"tx", "rx"}, + .dmas = {0x10, 0x6, 0x10, 0x7}, + .interrupts = {0x0, 0x39, 0x4}, + .pinctrl_0 = 0x27, + .pinctrl_names = "default", + .reg = {0xff130000, 0x100}, + .reg_io_width = 0x4, + .reg_shift = 0x2, +}; +U_BOOT_DRVINFO(serial_at_ff130000) = { + .name = "ns16550_serial", + .plat = &dtv_serial_at_ff130000, + .plat_size = sizeof(dtv_serial_at_ff130000), + .parent_idx = -1, +}; + +/* Node /spi@ff190000 index 5 */ +static struct dtd_rockchip_rk3328_spi dtv_spi_at_ff190000 = { + .clocks = { + {0, {32}}, + {0, {209}},}, + .dma_names = {"tx", "rx"}, + .dmas = {0x10, 0x8, 0x10, 0x9}, + .interrupts = {0x0, 0x31, 0x4}, + .pinctrl_0 = {0x2f, 0x30, 0x31, 0x32}, + .pinctrl_names = "default", + .reg = {0xff190000, 0x1000}, +}; +U_BOOT_DRVINFO(spi_at_ff190000) = { + .name = "rockchip_rk3328_spi", + .plat = &dtv_spi_at_ff190000, + .plat_size = sizeof(dtv_spi_at_ff190000), + .parent_idx = -1, +}; + +/* + * Node /spi@ff190000/spiflash@0 index 6 + * driver jedec_spi_nor parent None + */ +static struct dtd_jedec_spi_nor dtv_spiflash_at_0 = { + .reg = {0x0}, + .spi_max_frequency = 0x2faf080, +}; +U_BOOT_DRVINFO(spiflash_at_0) = { + .name = "jedec_spi_nor", + .plat = &dtv_spiflash_at_0, + .plat_size = sizeof(dtv_spiflash_at_0), + .parent_idx = 5, +}; + +/* + * Node /syscon@ff100000 index 7 + * driver rockchip_rk3328_grf parent None + */ +static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = { + .reg = {0xff100000, 0x1000}, +}; +U_BOOT_DRVINFO(syscon_at_ff100000) = { + .name = "rockchip_rk3328_grf", + .plat = &dtv_syscon_at_ff100000, + .plat_size = sizeof(dtv_syscon_at_ff100000), + .parent_idx = -1, +}; + diff --git a/package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-structs-gen.h b/package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-structs-gen.h new file mode 100644 index 00000000000..e15d8487295 --- /dev/null +++ b/package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-structs-gen.h @@ -0,0 +1,63 @@ +/* + * DO NOT MODIFY + * + * Defines the structs used to hold devicetree data. + * This was generated by dtoc from a .dtb (device tree binary) file. + */ + +#include +#include +struct dtd_jedec_spi_nor { + fdt32_t reg[1]; + fdt32_t spi_max_frequency; +}; +struct dtd_ns16550_serial { + fdt32_t clock_frequency; + struct phandle_1_arg clocks[2]; + const char * dma_names[2]; + fdt32_t dmas[4]; + fdt32_t interrupts[3]; + fdt32_t pinctrl_0; + const char * pinctrl_names; + fdt64_t reg[2]; + fdt32_t reg_io_width; + fdt32_t reg_shift; +}; +struct dtd_rockchip_rk3288_dw_mshc { + fdt32_t bus_width; + bool cap_mmc_highspeed; + bool cap_sd_highspeed; + struct phandle_1_arg clocks[4]; + bool disable_wp; + fdt32_t fifo_depth; + fdt32_t interrupts[3]; + fdt32_t max_frequency; + bool mmc_hs200_1_8v; + bool non_removable; + fdt32_t pinctrl_0[4]; + const char * pinctrl_names; + fdt64_t reg[2]; + bool u_boot_spl_fifo_mode; + fdt32_t vmmc_supply; + fdt32_t vqmmc_supply; +}; +struct dtd_rockchip_rk3328_cru { + fdt64_t reg[2]; + fdt32_t rockchip_grf; +}; +struct dtd_rockchip_rk3328_dmc { + fdt64_t reg[12]; + fdt32_t rockchip_sdram_params[196]; +}; +struct dtd_rockchip_rk3328_grf { + fdt64_t reg[2]; +}; +struct dtd_rockchip_rk3328_spi { + struct phandle_1_arg clocks[2]; + const char * dma_names[2]; + fdt32_t dmas[4]; + fdt32_t interrupts[3]; + fdt32_t pinctrl_0[4]; + const char * pinctrl_names; + fdt64_t reg[2]; +}; From f0138de3e5feb5ec57e0d195debe4b15da2aea85 Mon Sep 17 00:00:00 2001 From: Antonio Flores Date: Sat, 8 Jul 2023 13:31:49 -0400 Subject: [PATCH 08/29] rockchip: add support for PINE64 ROCK64 This add support for PINE64 ROCK64, rockchip rk3328 board. Specifications: 4 x ARM Cortex A53 cores @ 1.5 GHz ARM Mali 450 MP2 GPU LPDDR3 RAM (up to 4GB) Gigabit Ethernet Micro SD Slot eMMC module slot SPI Flash 128Mbit 4K digital video out 2x USB 2.0 Host 1x USB 3.0 Host PI-2 bus PI-P5+ bus IR R/X port Real Time Clock (RTC) port Power Over Ethernet (POE) (when using optional HAT module) A/V jack Power, Reset and Recovery buttons 3.5mm barrel power (5V 3A) port To install write image to the sd using dd (dd if=*.img of=/*) Signed-off-by: Antonio Flores --- target/linux/rockchip/image/armv8.mk | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk index dc977859a6d..df16505d29d 100644 --- a/target/linux/rockchip/image/armv8.mk +++ b/target/linux/rockchip/image/armv8.mk @@ -52,6 +52,15 @@ define Device/friendlyarm_nanopi-r4s endef TARGET_DEVICES += friendlyarm_nanopi-r4s +define Device/pine64_rock64 + DEVICE_VENDOR := Pine64 + DEVICE_MODEL := Rock64 + SOC := rk3328 + UBOOT_DEVICE_NAME := rock64-rk3328 + IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata +endef +TARGET_DEVICES += pine64_rock64 + define Device/pine64_rockpro64 DEVICE_VENDOR := Pine64 DEVICE_MODEL := RockPro64 From 27633cefac14fe0e0fde4e6285b9241076124c62 Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Tue, 22 Aug 2023 12:37:10 +0200 Subject: [PATCH 09/29] ltq-ifxos: fix compilation error with kernel 6.1 Conditionally use the newer APIs. Signed-off-by: Andre Heider --- .../lantiq/ltq-ifxos/patches/100-compat.patch | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/package/kernel/lantiq/ltq-ifxos/patches/100-compat.patch b/package/kernel/lantiq/ltq-ifxos/patches/100-compat.patch index 45059890e11..a3f210487ea 100644 --- a/package/kernel/lantiq/ltq-ifxos/patches/100-compat.patch +++ b/package/kernel/lantiq/ltq-ifxos/patches/100-compat.patch @@ -90,3 +90,17 @@ return ret; } +--- a/src/linux/ifxos_linux_thread_drv.c ++++ b/src/linux/ifxos_linux_thread_drv.c +@@ -154,7 +154,11 @@ IFXOS_STATIC int IFXOS_KernelThreadStart + retVal = pThrCntrl->pThrFct(&pThrCntrl->thrParams); + pThrCntrl->thrParams.bRunning = IFX_FALSE; + ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5,17,0)) ++ kthread_complete_and_exit(&pThrCntrl->thrCompletion, (long)retVal); ++#else + complete_and_exit(&pThrCntrl->thrCompletion, (long)retVal); ++#endif + + IFXOS_PRN_USR_DBG_NL( IFXOS, IFXOS_PRN_LEVEL_NORMAL, + ("EXIT - Kernel Thread Startup <%s>" IFXOS_CRLF, From e8e5dbc3c91e92ccaa6ea11da208b89f65f79f3d Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Tue, 22 Aug 2023 13:07:02 +0200 Subject: [PATCH 10/29] vrx518_ep: fix compilation error with kernel 6.1 Unconditionally use the newer APIs, since our oldest supported kernel contains them too. Signed-off-by: Andre Heider --- .../lantiq/vrx518_ep/patches/100-compat.patch | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/package/kernel/lantiq/vrx518_ep/patches/100-compat.patch b/package/kernel/lantiq/vrx518_ep/patches/100-compat.patch index f5b917e7078..a139c7a8624 100644 --- a/package/kernel/lantiq/vrx518_ep/patches/100-compat.patch +++ b/package/kernel/lantiq/vrx518_ep/patches/100-compat.patch @@ -42,6 +42,25 @@ dev_err(&pdev->dev, "%s: Failed to enable MSI interrupts error code: %d\n", __func__, err); +@@ -589,15 +589,15 @@ static int dc_ep_probe(struct pci_dev *p + /* Target structures have a limit of 32 bit DMA pointers. + * DMA pointers can be wider than 32 bits by default on some systems. + */ +- ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); ++ ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); + if (ret) { + dev_err(&pdev->dev, "32-bit DMA not available: %d\n", ret); + goto err_region; + } + +- ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); ++ ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); + if (ret) { +- dev_err(&pdev->dev, "cannot enable 32-bit consistent DMA\n"); ++ dev_err(&pdev->dev, "cannot enable 32-bit coherent DMA\n"); + goto err_region; + } + @@ -654,7 +654,7 @@ static int dc_ep_probe(struct pci_dev *p goto err_iomap; From 63635696dcf3816469a2b532db6534a46c5acb7e Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Tue, 22 Aug 2023 14:19:43 +0200 Subject: [PATCH 11/29] vrx518_tc: fix compilation error with kernel 6.1 Define the old PDE_DATA marco to the new pde_data function and conditionally use the newer APIs. Signed-off-by: Andre Heider --- .../lantiq/vrx518_tc/patches/100-compat.patch | 120 +++++++++++++----- .../lantiq/vrx518_tc/patches/200-swplat.patch | 14 +- .../vrx518_tc/patches/201-desc-length.patch | 28 ++-- .../lantiq/vrx518_tc/patches/202-napi.patch | 19 ++- ...05-dcdp-ptm_tc-dynamically-alloc-mib.patch | 8 +- 5 files changed, 126 insertions(+), 63 deletions(-) diff --git a/package/kernel/lantiq/vrx518_tc/patches/100-compat.patch b/package/kernel/lantiq/vrx518_tc/patches/100-compat.patch index 2c92912adef..d04c1ed5df0 100644 --- a/package/kernel/lantiq/vrx518_tc/patches/100-compat.patch +++ b/package/kernel/lantiq/vrx518_tc/patches/100-compat.patch @@ -243,7 +243,33 @@ #include "inc/tc_main.h" #include "inc/reg_addr.h" -@@ -182,8 +182,8 @@ static int ptm_get_qid(struct net_device +@@ -62,6 +62,9 @@ + #include "inc/fw/vrx518_addr_def.h" + #include "inc/fw/vrx518_ppe_fw.h" + ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5,17,0)) ++#define PDE_DATA pde_data ++#endif + + static struct ptm_priv *g_ptm_priv; + static struct ptm_ep_priv g_ep_priv[BOND_MAX]; +@@ -84,6 +87,7 @@ static int ptm_erb_addr_get(const unsign + unsigned int *data_addr, unsigned int *desc_addr); + + ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,16,0)) + static inline void tc_ether_addr_copy(u8 *dst, const u8 *src) + { + #if defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) +@@ -98,6 +102,7 @@ static inline void tc_ether_addr_copy(u8 + a[2] = b[2]; + #endif + } ++#endif + + static inline int is_ptm_sl(struct ptm_ep_priv *priv) + { +@@ -182,8 +187,8 @@ static int ptm_get_qid(struct net_device return qid; } @@ -254,7 +280,7 @@ { struct ptm_priv *ptm_tc = netdev_priv(dev); -@@ -191,8 +191,6 @@ static struct rtnl_link_stats64 *ptm_get +@@ -191,8 +196,6 @@ static struct rtnl_link_stats64 *ptm_get memcpy(storage, &ptm_tc->stats64, sizeof(ptm_tc->stats64)); else storage->tx_errors += ptm_tc->stats64.tx_errors; @@ -263,7 +289,16 @@ } static int ptm_set_mac_address(struct net_device *dev, void *p) -@@ -209,7 +207,7 @@ static int ptm_set_mac_address(struct ne +@@ -204,12 +207,16 @@ static int ptm_set_mac_address(struct ne + return -EBUSY; + + tc_info(ptm_tc->tc_priv, MSG_EVENT, "ptm mac address update!\n"); ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5,16,0)) ++ eth_hw_addr_set(dev, addr->sa_data); ++#else + tc_ether_addr_copy(dev->dev_addr, addr->sa_data); ++#endif + return 0; } @@ -272,7 +307,7 @@ { struct ptm_priv *ptm_tc = netdev_priv(dev); -@@ -503,7 +501,7 @@ static int ptm_xmit(struct sk_buff *skb, +@@ -503,7 +510,7 @@ static int ptm_xmit(struct sk_buff *skb, if (!showtime_stat(ptm_tc->tc_priv)) goto PTM_XMIT_DROP; @@ -281,7 +316,7 @@ goto PTM_XMIT_DROP; dump_skb_info(ptm_tc->tc_priv, skb, (MSG_TX | MSG_TXDATA)); -@@ -632,11 +630,8 @@ static int ptm_dev_init(struct tc_priv * +@@ -632,11 +639,8 @@ static int ptm_dev_init(struct tc_priv * struct ptm_priv *ptm_tc; const char macaddr[ETH_ALEN] = {0xAC, 0x9A, 0x96, 0x11, 0x22, 0x33}; @@ -295,7 +330,19 @@ if (!dev) { tc_dbg(tc_priv, MSG_INIT, "Cannot alloc net device\n"); return -ENOMEM; -@@ -2103,7 +2098,6 @@ static int ptm_showtime_exit(const unsig +@@ -644,7 +648,11 @@ static int ptm_dev_init(struct tc_priv * + ptm_tc = netdev_priv(dev); + ptm_tc->dev = dev; + ptm_tc->tc_priv = tc_priv; ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5,16,0)) ++ eth_hw_addr_set(dev, macaddr); ++#else + tc_ether_addr_copy(dev->dev_addr, macaddr); ++#endif + spin_lock_init(&ptm_tc->ptm_lock); + memcpy(ptm_tc->outq_map, def_outq_map, sizeof(def_outq_map)); + SET_NETDEV_DEV(ptm_tc->dev, tc_priv->ep_dev[id].dev); +@@ -2103,7 +2111,6 @@ static int ptm_showtime_exit(const unsig struct ptm_ep_priv *priv = tc_ep_priv(idx); u32 stop = ACA_TXIN_EN; struct dc_ep_dev *ep; @@ -398,7 +445,18 @@ #include #include #include "inc/tc_main.h" -@@ -353,7 +355,7 @@ static ssize_t mem_proc_write(struct fil +@@ -35,6 +37,10 @@ + #include "inc/platform.h" + #include "inc/dsl_tc.h" + ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5,17,0)) ++#define PDE_DATA pde_data ++#endif ++ + #define ATM_HEADER_SIZE (ATM_CELL_SIZE - ATM_CELL_PAYLOAD) + static char *dbg_flag_str[] = { + "rx", +@@ -353,7 +359,7 @@ static ssize_t mem_proc_write(struct fil } addr = set_val = repeat_cnt = 0; @@ -407,7 +465,7 @@ return -EFAULT; len = count < sizeof(str) ? count : sizeof(str) - 1; -@@ -450,13 +452,12 @@ static int proc_read_mem_seq_open(struct +@@ -450,13 +456,12 @@ static int proc_read_mem_seq_open(struct return single_open(file, proc_read_mem, NULL); } @@ -427,7 +485,7 @@ }; static ssize_t pp32_proc_write(struct file *file, const char __user *buf, -@@ -748,13 +749,12 @@ static int proc_read_pp32_seq_open(struc +@@ -748,13 +753,12 @@ static int proc_read_pp32_seq_open(struc return single_open(file, proc_read_pp32, PDE_DATA(inode)); } @@ -447,7 +505,7 @@ }; static int proc_read_tc_cfg(struct seq_file *seq, void *v) -@@ -865,13 +865,12 @@ static int proc_read_tc_cfg_seq_open(str +@@ -865,13 +869,12 @@ static int proc_read_tc_cfg_seq_open(str return single_open(file, proc_read_tc_cfg, PDE_DATA(inode)); } @@ -467,7 +525,7 @@ }; static ssize_t proc_write_dbg(struct file *file, const char __user *buf, -@@ -951,13 +950,12 @@ static int proc_read_dbg_seq_open(struct +@@ -951,13 +954,12 @@ static int proc_read_dbg_seq_open(struct return single_open(file, proc_read_dbg, PDE_DATA(inode)); } @@ -487,7 +545,7 @@ }; static ssize_t proc_write_tc_switch(struct file *file, const char __user *buf, -@@ -1018,11 +1016,11 @@ proc_tc_switch_help: +@@ -1018,11 +1020,11 @@ proc_tc_switch_help: return count; } @@ -503,7 +561,7 @@ static ssize_t proc_write_show_time(struct file *file, const char __user *buf, size_t count, loff_t *data) { -@@ -1077,10 +1075,9 @@ proc_show_time_help: +@@ -1077,10 +1079,9 @@ proc_show_time_help: return count; } @@ -517,7 +575,7 @@ }; static int proc_read_ver(struct seq_file *seq, void *v) -@@ -1128,12 +1125,11 @@ static int proc_read_ver_seq_open(struct +@@ -1128,12 +1129,11 @@ static int proc_read_ver_seq_open(struct return single_open(file, proc_read_ver, PDE_DATA(inode)); } @@ -535,7 +593,7 @@ }; static int proc_read_soc(struct seq_file *seq, void *v) -@@ -1142,20 +1138,18 @@ static int proc_read_soc(struct seq_file +@@ -1142,20 +1142,18 @@ static int proc_read_soc(struct seq_file tcpriv = (struct tc_priv *)seq->private; @@ -564,7 +622,7 @@ return 0; } -@@ -1165,15 +1159,13 @@ static int proc_read_soc_seq_open(struct +@@ -1165,15 +1163,13 @@ static int proc_read_soc_seq_open(struct return single_open(file, proc_read_soc, PDE_DATA(inode)); } @@ -585,7 +643,7 @@ static struct tc_proc_list tc_procs[] = { {TC_PROC_DIR, 0, NULL, 1}, {"cfg", 0644, &tc_cfg_proc_fops, 0}, -@@ -1241,13 +1233,12 @@ static int proc_read_ptm_wanmib_seq_open +@@ -1241,13 +1237,12 @@ static int proc_read_ptm_wanmib_seq_open return single_open(file, proc_read_ptm_wanmib, PDE_DATA(inode)); } @@ -605,7 +663,7 @@ }; static int proc_ptm_read_cfg(struct seq_file *seq, void *v) -@@ -1300,7 +1291,7 @@ static ssize_t ptm_cfg_proc_write(struct +@@ -1300,7 +1295,7 @@ static ssize_t ptm_cfg_proc_write(struct return -EINVAL; } @@ -614,7 +672,7 @@ return -EFAULT; len = count < sizeof(str) ? count : sizeof(str) - 1; -@@ -1343,13 +1334,12 @@ proc_ptm_cfg_help: +@@ -1343,13 +1338,12 @@ proc_ptm_cfg_help: } @@ -634,7 +692,7 @@ }; static ssize_t proc_ptm_write_prio(struct file *file, const char __user *buf, -@@ -1455,13 +1445,12 @@ static int proc_ptm_read_prio_seq_open(s +@@ -1455,13 +1449,12 @@ static int proc_ptm_read_prio_seq_open(s return single_open(file, proc_ptm_read_prio, PDE_DATA(inode)); } @@ -654,7 +712,7 @@ }; static int proc_ptm_read_bond_seq_open(struct inode *inode, struct file *file) -@@ -1469,12 +1458,11 @@ static int proc_ptm_read_bond_seq_open(s +@@ -1469,12 +1462,11 @@ static int proc_ptm_read_bond_seq_open(s return single_open(file, proc_ptm_read_bond, PDE_DATA(inode)); } @@ -672,7 +730,7 @@ }; static int proc_ptm_read_bondmib_seq_open(struct inode *inode, -@@ -1483,13 +1471,12 @@ static int proc_ptm_read_bondmib_seq_ope +@@ -1483,13 +1475,12 @@ static int proc_ptm_read_bondmib_seq_ope return single_open(file, proc_ptm_read_bondmib, PDE_DATA(inode)); } @@ -692,7 +750,7 @@ }; struct fwdbg_t { -@@ -1910,14 +1897,14 @@ static int proc_read_fwdbg_seq_open(stru +@@ -1910,14 +1901,14 @@ static int proc_read_fwdbg_seq_open(stru { return single_open(file, proc_read_fwdbg, NULL); } @@ -714,7 +772,7 @@ static struct tc_proc_list ptm_sl_procs[] = { {TC_PROC_PTM_DIR, 0, NULL, 1}, {"mem", 0644, &mem_proc_fops, 0}, -@@ -2077,7 +2064,7 @@ static ssize_t atm_cfg_proc_write(struct +@@ -2077,7 +2068,7 @@ static ssize_t atm_cfg_proc_write(struct priv = (struct atm_priv *)PDE_DATA(file_inode(file)); @@ -723,7 +781,7 @@ return -EFAULT; len = count < sizeof(str) ? count : sizeof(str) - 1; -@@ -2119,13 +2106,12 @@ proc_atm_cfg_help: +@@ -2119,13 +2110,12 @@ proc_atm_cfg_help: return count; } @@ -743,7 +801,7 @@ }; static ssize_t proc_write_atm_wanmib(struct file *file, const char __user *buf, -@@ -2173,13 +2159,12 @@ static int proc_read_atm_wanmib_seq_open +@@ -2173,13 +2163,12 @@ static int proc_read_atm_wanmib_seq_open @@ -763,7 +821,7 @@ }; static int proc_read_htu_seq_open(struct inode *inode, struct file *file) -@@ -2187,12 +2172,11 @@ static int proc_read_htu_seq_open(struct +@@ -2187,12 +2176,11 @@ static int proc_read_htu_seq_open(struct return single_open(file, proc_read_htu, PDE_DATA(inode)); } @@ -781,7 +839,7 @@ }; static int proc_read_queue_seq_open(struct inode *inode, struct file *file) -@@ -2200,12 +2184,11 @@ static int proc_read_queue_seq_open(stru +@@ -2200,12 +2188,11 @@ static int proc_read_queue_seq_open(stru return single_open(file, proc_read_queue, PDE_DATA(inode)); } @@ -799,7 +857,7 @@ }; static void set_q_prio(struct atm_priv *priv, -@@ -2428,13 +2411,12 @@ static const struct seq_operations pvc_m +@@ -2428,13 +2415,12 @@ static const struct seq_operations pvc_m .show = pvc_mib_seq_show, }; @@ -819,7 +877,7 @@ }; static int proc_read_pvc_mib_seq_open(struct inode *inode, struct file *file) -@@ -2447,12 +2429,11 @@ static int proc_read_pvc_mib_seq_open(st +@@ -2447,12 +2433,11 @@ static int proc_read_pvc_mib_seq_open(st return ret; } @@ -837,7 +895,7 @@ }; static ssize_t proc_write_cell(struct file *file, -@@ -2592,13 +2573,12 @@ static int proc_read_cell_seq_open(struc +@@ -2592,13 +2577,12 @@ static int proc_read_cell_seq_open(struc return single_open(file, proc_read_cell, NULL); } diff --git a/package/kernel/lantiq/vrx518_tc/patches/200-swplat.patch b/package/kernel/lantiq/vrx518_tc/patches/200-swplat.patch index 793adefdd65..edc97998b73 100644 --- a/package/kernel/lantiq/vrx518_tc/patches/200-swplat.patch +++ b/package/kernel/lantiq/vrx518_tc/patches/200-swplat.patch @@ -79,7 +79,7 @@ This replaces it by a basic working implementation. tc_dbg(priv->tc_priv, MSG_TX, "ATM: TX fail\n"); --- a/dcdp/ptm_tc.c +++ b/dcdp/ptm_tc.c -@@ -497,6 +497,7 @@ static int ptm_xmit(struct sk_buff *skb, +@@ -506,6 +506,7 @@ static int ptm_xmit(struct sk_buff *skb, struct ptm_priv *ptm_tc = netdev_priv(dev); int qid; enum tc_pkt_type type; @@ -87,7 +87,7 @@ This replaces it by a basic working implementation. if (!showtime_stat(ptm_tc->tc_priv)) goto PTM_XMIT_DROP; -@@ -510,11 +511,13 @@ static int ptm_xmit(struct sk_buff *skb, +@@ -519,11 +520,13 @@ static int ptm_xmit(struct sk_buff *skb, type = ptm_tc->tc_priv->tc_mode == TC_PTM_BND_MODE ? PTM_BOND_PKT : PTM_SL_PKT; @@ -102,7 +102,7 @@ This replaces it by a basic working implementation. } return 0; -@@ -631,7 +634,7 @@ static int ptm_dev_init(struct tc_priv * +@@ -640,7 +643,7 @@ static int ptm_dev_init(struct tc_priv * const char macaddr[ETH_ALEN] = {0xAC, 0x9A, 0x96, 0x11, 0x22, 0x33}; @@ -111,7 +111,7 @@ This replaces it by a basic working implementation. if (!dev) { tc_dbg(tc_priv, MSG_INIT, "Cannot alloc net device\n"); return -ENOMEM; -@@ -2324,7 +2327,11 @@ static void ptm_aca_init(struct ptm_ep_p +@@ -2337,7 +2340,11 @@ static void ptm_aca_init(struct ptm_ep_p cfg = &priv->tc_priv->cfg; txin = ¶m.aca_txin; @@ -123,7 +123,7 @@ This replaces it by a basic working implementation. txin->hd_size_in_dw = cfg->txin.soc_desc_dwsz; txin->pd_desc_base = SB_XBAR_ADDR(__ACA_TX_IN_PD_LIST_BASE); txin->pd_desc_num = __ACA_TX_IN_PD_LIST_NUM; -@@ -2347,7 +2354,11 @@ static void ptm_aca_init(struct ptm_ep_p +@@ -2360,7 +2367,11 @@ static void ptm_aca_init(struct ptm_ep_p txin->soc_cmlt_cnt_addr); txout = ¶m.aca_txout; @@ -135,7 +135,7 @@ This replaces it by a basic working implementation. txout->hd_size_in_dw = cfg->txout.soc_desc_dwsz; if (priv->tc_priv->param.cdma_desc_loc == LOC_IN_FPI) txout->pd_desc_base = sb_r32(__TX_OUT_SHADOW_PTR) - phybase; -@@ -2373,7 +2384,11 @@ static void ptm_aca_init(struct ptm_ep_p +@@ -2386,7 +2397,11 @@ static void ptm_aca_init(struct ptm_ep_p txout->soc_cmlt_cnt_addr); rxout = ¶m.aca_rxout; @@ -147,7 +147,7 @@ This replaces it by a basic working implementation. rxout->hd_size_in_dw = cfg->rxout.soc_desc_dwsz; if (priv->tc_priv->param.cdma_desc_loc == LOC_IN_FPI) rxout->pd_desc_base = sb_r32(__RX_OUT_SHADOW_PTR) - phybase; -@@ -2399,7 +2414,11 @@ static void ptm_aca_init(struct ptm_ep_p +@@ -2412,7 +2427,11 @@ static void ptm_aca_init(struct ptm_ep_p rxout->soc_cmlt_cnt_addr); rxin = ¶m.aca_rxin; diff --git a/package/kernel/lantiq/vrx518_tc/patches/201-desc-length.patch b/package/kernel/lantiq/vrx518_tc/patches/201-desc-length.patch index 8b30914df96..134f119f3c0 100644 --- a/package/kernel/lantiq/vrx518_tc/patches/201-desc-length.patch +++ b/package/kernel/lantiq/vrx518_tc/patches/201-desc-length.patch @@ -54,7 +54,7 @@ significantly lower latencies when the line is saturated. struct cdma { --- a/dcdp/ptm_tc.c +++ b/dcdp/ptm_tc.c -@@ -75,7 +75,11 @@ static const u32 tx_kvec[] = { +@@ -78,7 +78,11 @@ static const u32 tx_kvec[] = { 0x30B1B233, 0xB43536B7, 0xB8393ABB, 0x3CBDBE3F, 0xC04142C3, 0x44C5C647, 0x48C9CA4B, 0xCC4D4ECF }; @@ -66,7 +66,7 @@ significantly lower latencies when the line is saturated. static const char ptm_drv_name[] = "PTM SL"; static const char ptm_bond_name[][IFNAMSIZ] = {"PTM US BOND", "PTM DS BOND"}; -@@ -1005,6 +1009,10 @@ static void us_fp_desq_cfg_ctxt_init(str +@@ -1018,6 +1022,10 @@ static void us_fp_desq_cfg_ctxt_init(str int i; u32 desc_addr; rx_descriptor_t desc; @@ -77,7 +77,7 @@ significantly lower latencies when the line is saturated. memset(&desq_cfg, 0, sizeof(desq_cfg)); /* Initialize US Fast-Path Descriptor Queue Config/Context */ -@@ -1012,7 +1020,11 @@ static void us_fp_desq_cfg_ctxt_init(str +@@ -1025,7 +1033,11 @@ static void us_fp_desq_cfg_ctxt_init(str desq_cfg.fast_path = 1; desq_cfg.mbox_int_en = 0; desq_cfg.des_sync_needed = 0; @@ -89,7 +89,7 @@ significantly lower latencies when the line is saturated. desq_cfg.des_base_addr = __US_FAST_PATH_DES_LIST_BASE; tc_mem_write(priv, fpi_addr(__US_FP_INQ_DES_CFG_CTXT), -@@ -1036,12 +1048,20 @@ static void us_qos_desq_cfg_ctxt_init(st +@@ -1049,12 +1061,20 @@ static void us_qos_desq_cfg_ctxt_init(st int offset, i; rx_descriptor_t desc; u32 phy_addr; @@ -110,7 +110,7 @@ significantly lower latencies when the line is saturated. offset = 0; for (i = 0; i < QOSQ_NUM; i++) { -@@ -1080,6 +1100,10 @@ static void us_outq_desq_cfg_ctxt_init(s +@@ -1093,6 +1113,10 @@ static void us_outq_desq_cfg_ctxt_init(s u32 phy_addr; int i; u32 offset; @@ -121,7 +121,7 @@ significantly lower latencies when the line is saturated. /* Setup OUTQ_QoS_CFG_CTXT */ /* NOTE: By default, Shaping & WFQ both are DISABLED!! */ -@@ -1108,7 +1132,11 @@ static void us_outq_desq_cfg_ctxt_init(s +@@ -1121,7 +1145,11 @@ static void us_outq_desq_cfg_ctxt_init(s desq_cfg.des_in_own_val = US_OUTQ_DES_OWN; desq_cfg.mbox_int_en = 0; desq_cfg.des_sync_needed = 0; @@ -134,7 +134,7 @@ significantly lower latencies when the line is saturated. /** * Only BC0 is used in VRX518 */ -@@ -1174,7 +1202,11 @@ static void us_qos_cfg_init(struct ptm_e +@@ -1187,7 +1215,11 @@ static void us_qos_cfg_init(struct ptm_e /* Set QoS NO DROP */ sb_w32(1, __QOSQ_NO_DROP); /* Enable Preemption function/Disable QoS by default */ @@ -146,7 +146,7 @@ significantly lower latencies when the line is saturated. /* By default, all qid mappint to non-preemption queue */ sb_w32(0x0, _QID2PREEMP_MAP); -@@ -1376,6 +1408,11 @@ static void ptm_local_desq_cfg_ctxt_init +@@ -1389,6 +1421,11 @@ static void ptm_local_desq_cfg_ctxt_init u32 dcnt, addr, pdbram_base; unsigned int us_des_alloc[] = { __US_TC_LOCAL_Q0_DES_LIST_NUM, __US_TC_LOCAL_Q1_DES_LIST_NUM}; @@ -158,7 +158,7 @@ significantly lower latencies when the line is saturated. /* Setup the Local DESQ Configuration/Context for UpStream Queues */ memset(&desq_cfg, 0, sizeof(desq_cfg)); -@@ -2321,6 +2358,10 @@ static void ptm_aca_init(struct ptm_ep_p +@@ -2334,6 +2371,10 @@ static void ptm_aca_init(struct ptm_ep_p u32 phybase = priv->ep->phy_membase; u32 start; u32 type; @@ -169,7 +169,7 @@ significantly lower latencies when the line is saturated. priv->tc_priv->tc_ops.soc_cfg_get(&priv->tc_priv->cfg, ptm_id(priv)); memset(¶m, 0, sizeof(param)); -@@ -2334,7 +2375,11 @@ static void ptm_aca_init(struct ptm_ep_p +@@ -2347,7 +2388,11 @@ static void ptm_aca_init(struct ptm_ep_p #endif txin->hd_size_in_dw = cfg->txin.soc_desc_dwsz; txin->pd_desc_base = SB_XBAR_ADDR(__ACA_TX_IN_PD_LIST_BASE); @@ -198,7 +198,7 @@ significantly lower latencies when the line is saturated. --- a/dcdp/tc_proc.c +++ b/dcdp/tc_proc.c -@@ -1114,6 +1114,9 @@ static int proc_read_ver(struct seq_file +@@ -1118,6 +1118,9 @@ static int proc_read_ver(struct seq_file (date >> 16) & 0xff, (date & 0xffff)); @@ -208,7 +208,7 @@ significantly lower latencies when the line is saturated. #ifdef FEATURE_POWER_DOWN seq_puts(seq, " + Support Power Down enhancement feature\n"); #endif -@@ -1166,6 +1169,113 @@ static const struct proc_ops tc_soc_proc +@@ -1170,6 +1173,113 @@ static const struct proc_ops tc_soc_proc .proc_release = single_release, }; @@ -322,7 +322,7 @@ significantly lower latencies when the line is saturated. static struct tc_proc_list tc_procs[] = { {TC_PROC_DIR, 0, NULL, 1}, {"cfg", 0644, &tc_cfg_proc_fops, 0}, -@@ -1174,6 +1284,9 @@ static struct tc_proc_list tc_procs[] = +@@ -1178,6 +1288,9 @@ static struct tc_proc_list tc_procs[] = {"showtime", 0200, &tc_show_time_proc_fops, 0}, {"ver", 0644, &tc_ver_proc_fops, 0}, {"soc", 0644, &tc_soc_proc_fops, 0}, @@ -332,7 +332,7 @@ significantly lower latencies when the line is saturated. }; int tc_proc_init(struct tc_priv *priv) -@@ -1333,7 +1446,6 @@ proc_ptm_cfg_help: +@@ -1337,7 +1450,6 @@ proc_ptm_cfg_help: return count; } diff --git a/package/kernel/lantiq/vrx518_tc/patches/202-napi.patch b/package/kernel/lantiq/vrx518_tc/patches/202-napi.patch index 55f0cc10667..266beba1a7e 100644 --- a/package/kernel/lantiq/vrx518_tc/patches/202-napi.patch +++ b/package/kernel/lantiq/vrx518_tc/patches/202-napi.patch @@ -334,7 +334,7 @@ int (*umt_init)(u32 umt_id, u32 umt_period, u32 umt_dst); --- a/dcdp/ptm_tc.c +++ b/dcdp/ptm_tc.c -@@ -141,7 +141,11 @@ static int ptm_open(struct net_device *d +@@ -146,7 +146,11 @@ static int ptm_open(struct net_device *d struct ptm_priv *ptm_tc = netdev_priv(dev); tc_info(ptm_tc->tc_priv, MSG_EVENT, "ptm open\n"); @@ -346,7 +346,7 @@ #ifdef CONFIG_SOC_TYPE_XWAY xet_phy_wan_port(7, NULL, 1, 1); if (ppa_hook_ppa_phys_port_add_fn) -@@ -158,7 +162,11 @@ static int ptm_stop(struct net_device *d +@@ -163,7 +167,11 @@ static int ptm_stop(struct net_device *d struct ptm_priv *ptm_tc = netdev_priv(dev); tc_info(ptm_tc->tc_priv, MSG_EVENT, "ptm stop\n"); @@ -358,7 +358,7 @@ #ifdef CONFIG_SOC_TYPE_XWAY if (ppa_drv_datapath_mac_entry_setting) ppa_drv_datapath_mac_entry_setting(dev->dev_addr, 0, 6, 10, 1, 2); -@@ -555,7 +563,7 @@ static void ptm_rx(struct net_device *de +@@ -564,7 +572,7 @@ static void ptm_rx(struct net_device *de ptm_tc->stats64.rx_packets++; ptm_tc->stats64.rx_bytes += skb->len; @@ -367,17 +367,22 @@ ptm_tc->stats64.rx_dropped++; return; -@@ -651,6 +659,9 @@ static int ptm_dev_init(struct tc_priv * +@@ -664,6 +672,14 @@ static int ptm_dev_init(struct tc_priv * memcpy(ptm_tc->outq_map, def_outq_map, sizeof(def_outq_map)); SET_NETDEV_DEV(ptm_tc->dev, tc_priv->ep_dev[id].dev); ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5,17,0)) ++ netif_napi_add(ptm_tc->dev, &ptm_tc->napi_rx, tc_priv->tc_ops.napi_rx); ++ netif_napi_add_tx(ptm_tc->dev, &ptm_tc->napi_tx, tc_priv->tc_ops.napi_tx); ++#else + netif_napi_add(ptm_tc->dev, &ptm_tc->napi_rx, tc_priv->tc_ops.napi_rx, NAPI_POLL_WEIGHT); + netif_tx_napi_add(ptm_tc->dev, &ptm_tc->napi_tx, tc_priv->tc_ops.napi_tx, NAPI_POLL_WEIGHT); + ++#endif err = register_netdev(ptm_tc->dev); if (err) goto err1; -@@ -2605,7 +2616,9 @@ static int ptm_ring_init(struct ptm_ep_p +@@ -2618,7 +2634,9 @@ static int ptm_ring_init(struct ptm_ep_p { ptm_aca_ring_config_init(priv, id, bonding); return priv->tc_priv->tc_ops.dev_reg(priv->ptm_tc->dev, @@ -388,7 +393,7 @@ } /** -@@ -2960,7 +2973,9 @@ void ptm_tc_unload(enum dsl_tc_mode tc_m +@@ -2973,7 +2991,9 @@ void ptm_tc_unload(enum dsl_tc_mode tc_m /* unregister device */ if (ptm_tc->tc_priv->tc_ops.dev_unreg != NULL) ptm_tc->tc_priv->tc_ops.dev_unreg(ptm_tc->dev, @@ -399,7 +404,7 @@ /* remove PTM callback function */ ptm_cb_setup(ptm_tc, 0); -@@ -2978,6 +2993,10 @@ void ptm_exit(void) +@@ -2991,6 +3011,10 @@ void ptm_exit(void) if (!priv) return; diff --git a/package/kernel/lantiq/vrx518_tc/patches/205-dcdp-ptm_tc-dynamically-alloc-mib.patch b/package/kernel/lantiq/vrx518_tc/patches/205-dcdp-ptm_tc-dynamically-alloc-mib.patch index ca4c041b210..e239ba33466 100644 --- a/package/kernel/lantiq/vrx518_tc/patches/205-dcdp-ptm_tc-dynamically-alloc-mib.patch +++ b/package/kernel/lantiq/vrx518_tc/patches/205-dcdp-ptm_tc-dynamically-alloc-mib.patch @@ -1,6 +1,6 @@ --- a/dcdp/ptm_tc.c +++ b/dcdp/ptm_tc.c -@@ -298,15 +298,19 @@ static int ptm_tc_get_stats(struct ptm_e +@@ -307,15 +307,19 @@ static int ptm_tc_get_stats(struct ptm_e ) { struct rtnl_link_stats64 *stat; @@ -21,7 +21,7 @@ if (bonding) stats->tc_info = TC_PTM_BND_MODE; else -@@ -340,11 +344,11 @@ static int ptm_tc_get_stats(struct ptm_e +@@ -349,11 +353,11 @@ static int ptm_tc_get_stats(struct ptm_e ? cur_cnt - last_cnt : cur_cnt + ((unsigned int)(-1) - last_cnt); @@ -36,7 +36,7 @@ cur_cnt = tc_r32(GIF0_RX_CRC_ERR_CNT); last_cnt = priv->ptm_mib.rx_crc_err_pdu[0]; -@@ -358,7 +362,7 @@ static int ptm_tc_get_stats(struct ptm_e +@@ -367,7 +371,7 @@ static int ptm_tc_get_stats(struct ptm_e ? cur_cnt - last_cnt : cur_cnt + ((unsigned int)(-1) - last_cnt); @@ -45,7 +45,7 @@ cur_cnt = sb_r32(__US_TC_LOCAL_Q_CFG_CTXT_BASE + offsetof(desq_cfg_ctxt_t, deq_pkt_cnt) / 4); last_cnt = priv->ptm_mib.tx_total_pdu[0]; -@@ -376,90 +380,108 @@ static int ptm_tc_get_stats(struct ptm_e +@@ -385,90 +389,108 @@ static int ptm_tc_get_stats(struct ptm_e /* For bonding information */ if (bonding) { int i; From 520ade686b6d2a8ca04196423d7b44b3decda50a Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Tue, 22 Aug 2023 14:50:24 +0200 Subject: [PATCH 12/29] ltq-vdsl-vr11-mei: fix compilation error with kernel 6.1 Define the old PDE_DATA marco to the new pde_data function. Signed-off-by: Andre Heider --- .../ltq-vdsl-vr11-mei/patches/100-compat.patch | 13 +++++++++++++ .../122-cp_linux-fix-compilation-warning.patch | 4 ++-- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/package/kernel/lantiq/ltq-vdsl-vr11-mei/patches/100-compat.patch b/package/kernel/lantiq/ltq-vdsl-vr11-mei/patches/100-compat.patch index a2e42ccb03f..74e88894d8f 100644 --- a/package/kernel/lantiq/ltq-vdsl-vr11-mei/patches/100-compat.patch +++ b/package/kernel/lantiq/ltq-vdsl-vr11-mei/patches/100-compat.patch @@ -8,3 +8,16 @@ MODULE_LICENSE ("GPL"); #endif /* #ifdef MODULE*/ +--- a/src/drv_mei_cpe_linux.h ++++ b/src/drv_mei_cpe_linux.h +@@ -110,6 +110,10 @@ typedef irqreturn_t (*usedIsrHandler_t)( + # endif + #endif + ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5,17,0)) ++#define PDE_DATA pde_data ++#endif ++ + /** + Function typedef for the Linux request_threaded_irq() + */ diff --git a/package/kernel/lantiq/ltq-vdsl-vr11-mei/patches/122-cp_linux-fix-compilation-warning.patch b/package/kernel/lantiq/ltq-vdsl-vr11-mei/patches/122-cp_linux-fix-compilation-warning.patch index 63a530b6c51..6f180a284ec 100644 --- a/package/kernel/lantiq/ltq-vdsl-vr11-mei/patches/122-cp_linux-fix-compilation-warning.patch +++ b/package/kernel/lantiq/ltq-vdsl-vr11-mei/patches/122-cp_linux-fix-compilation-warning.patch @@ -1,6 +1,6 @@ ---- a/src/drv_mei_cpe_linux.c +--- a/src/drv_mei_cpe_linux.c +++ b/src/drv_mei_cpe_linux.c -@@ -1267,7 +1267,9 @@ static long MEI_Ioctl( struct file *filp, +@@ -1267,7 +1267,9 @@ static long MEI_Ioctl( struct file *filp MEI_IOCTL_RETURN: local_args.drv_ioctl.retCode = ret; From 9ea5487ea51a2279633410ee7a70168e0253223c Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Fri, 11 Aug 2023 17:49:58 -0700 Subject: [PATCH 13/29] ipq806x: chromium: Disable kernel's CONFIG_QCOM_SPM The qcom spm driver is currently broken for IPQ8064 OnHub devices on kernel 6.1, such that it hangs the system when booting, much to the consternation of users. This is especially bad as these devices don't yet have a fully-supported release branch, and are still sometimes landing on snapshot builds. OnHub devices have their own kernel config, so it's not that wide of an impact to disable this. I haven't fully gotten to the bottom of this, but: (a) The vendor kernel didn't have any SPM driver at all, and didn't utilize cpuidle. (b) The device tree has never included any (non-disabled) cpuidle states, so even when this driver was present on 5.15 (last known-working kernel), it didn't actually do anything -- it bailed early, before ever doing any SPM initialization. (c) Refactoring in Linux 5.16 [1] caused the SPM driver to be activated unconditionally, including setting us into standby mode (PM_SLEEP_MODE_STBY) by default. Removing the one PM_SLEEP_MODE_STBY line from drivers/soc/qcom/spm.c seems to fix the problem, but that isn't much different than simply disabling the driver, so I go with that for now. I also disable CONFIG_ARM_QCOM_SPM_CPUIDLE, becuase it 'select's QCOM_SPM. NB: it's possible there's some other deeper root cause involved in here. For one, I notice that CPU hotplug (e.g., echo 0 > /sys/devices/system/cpu/cpu1/online, echo 1 > ...) doesn't work right either. Perhaps there's some mismatch on upstream Linux qcom-scm behavior and the old boot firmware used for these systems? It wouldn't be the first time, as we've had some similar incompatibilities on the next generation of these devices, Google WiFi [2]. [1] Commit 60f3692b5f0b ("cpuidle: qcom_spm: Detach state machine from main SPM handling") [2] [RFC] qcom_scm: IPQ4019 firmware does not support atomic API? https://lore.kernel.org/linux-arm-kernel/20200913201608.GA3162100@bDebian/ Signed-off-by: Brian Norris --- target/linux/ipq806x/chromium/config-default | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/linux/ipq806x/chromium/config-default b/target/linux/ipq806x/chromium/config-default index d7db9f7db35..927aba360f4 100644 --- a/target/linux/ipq806x/chromium/config-default +++ b/target/linux/ipq806x/chromium/config-default @@ -1,7 +1,9 @@ +# CONFIG_ARM_QCOM_SPM_CPUIDLE is not set CONFIG_BLK_DEV_SD=y CONFIG_LEDS_LP5523=y CONFIG_LEDS_LP55XX_COMMON=y CONFIG_PHY_QCOM_IPQ806X_USB=y +# CONFIG_QCOM_SPM is not set CONFIG_SCSI=y CONFIG_SCSI_COMMON=y CONFIG_SG_POOL=y From 1611c21ac60287c8c1b533118482d698c6495fbc Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Fri, 11 Aug 2023 17:49:59 -0700 Subject: [PATCH 14/29] ipq806x: onhub: Enable adm_dma node One of our SPI devices references this node, but we never enabled it. This clutters up probe deferral logs. (NB: this SPI device still doesn't have a real driver, so it's just here for documentation and/or tinkering.) Signed-off-by: Brian Norris --- .../ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-onhub.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-onhub.dtsi b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-onhub.dtsi index 549c4620261..53661059547 100644 --- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-onhub.dtsi +++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-onhub.dtsi @@ -288,6 +288,10 @@ }; }; +&adm_dma { + status = "okay"; +}; + &gmac0 { status = "okay"; phy-mode = "rgmii"; From ef76b6ff3e8f93a719d9c88fb2ae1ee6d641b42e Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 19 Jun 2023 08:36:16 +0200 Subject: [PATCH 15/29] bcm53xx: Add support for D-Link DIR-890L The DIR-890L is very similar to DIR-885L, but has both USB2 and USB3. The signature for the wrgac36 board was copied from DD-Wrt. The DIR-890L bootstrap will only load the first 2 MB after the SEAMA header in the NAND flash, uncompress it with LZMA and execute it. Since the compressed kernel will not fit in 2 MB we have a problem. Solve this by putting a LZMA compressed U-Boot into the first 128 KB of the flash followed by the kernel. The bootstrap will then uncompress and execute U-Boot and then we let U-Boot read the kernel from flash and execute it. Signed-off-by: Linus Walleij --- .../base-files/etc/uci-defaults/09_fix_crc | 3 ++- .../base-files/lib/upgrade/platform.sh | 1 + target/linux/bcm53xx/image/Makefile | 21 +++++++++++++++++++ 3 files changed, 24 insertions(+), 1 deletion(-) diff --git a/target/linux/bcm53xx/base-files/etc/uci-defaults/09_fix_crc b/target/linux/bcm53xx/base-files/etc/uci-defaults/09_fix_crc index 89ce8970d75..c39625b8653 100644 --- a/target/linux/bcm53xx/base-files/etc/uci-defaults/09_fix_crc +++ b/target/linux/bcm53xx/base-files/etc/uci-defaults/09_fix_crc @@ -13,7 +13,8 @@ fixseama() { } case "$board" in -dlink,dir-885l) +dlink,dir-885l | \ +dlink,dir-890l) fixseama ;; *) diff --git a/target/linux/bcm53xx/base-files/lib/upgrade/platform.sh b/target/linux/bcm53xx/base-files/lib/upgrade/platform.sh index d9dc497cdac..0697d3dc80b 100644 --- a/target/linux/bcm53xx/base-files/lib/upgrade/platform.sh +++ b/target/linux/bcm53xx/base-files/lib/upgrade/platform.sh @@ -37,6 +37,7 @@ platform_expected_image() { case "$machine" in "dlink,dir-885l") echo "seamaseal wrgac42_dlink.2015_dir885l"; return;; + "dlink,dir-890l") echo "seamaseal wrgac36_dlink.2013gui_dir890"; return;; "luxul,abr-4500-v1") echo "lxl ABR-4500"; return;; "luxul,xap-810-v1") echo "lxl XAP-810"; return;; "luxul,xap-1410-v1") echo "lxl XAP-1410"; return;; diff --git a/target/linux/bcm53xx/image/Makefile b/target/linux/bcm53xx/image/Makefile index 5158b432b3b..39b7efbef78 100644 --- a/target/linux/bcm53xx/image/Makefile +++ b/target/linux/bcm53xx/image/Makefile @@ -88,6 +88,12 @@ define Build/luxul-lxl mv $@.new $@ endef +# Outputs a lzma compressed U-Boot that start at 0x00008000 +# just like the D-Link boot loaders expect +define Build/dlink-uboot-bin + $(STAGING_DIR_HOST)/bin/lzma e $(STAGING_DIR_IMAGE)/$(DEVICE_NAME)-u-boot.bin -d16 $@ +endef + define Build/seama-nand # Seama entity $(STAGING_DIR_HOST)/bin/oseama \ @@ -274,6 +280,21 @@ define Device/dlink_dir-885l endef TARGET_DEVICES += dlink_dir-885l +define Device/dlink_dir-890l + DEVICE_VENDOR := D-Link + DEVICE_MODEL := DIR-890L + DEVICE_PACKAGES := $(BRCMFMAC_43602A1) $(USB2_PACKAGES) $(USB3_PACKAGES) + # Layout: U-boot (128kb max) followed by kernel and appended DTB. + # This is done because the boot loader will only read the first 2 MB + # from the flash and decompress the LZMA it finds there after the + # SEAMA header. Since the compressed kernel will not fit in 2 MB, + # we put U-Boot there and let U-Boot read and execute the kernel. + KERNEL := dlink-uboot-bin | pad-to 128k | append-kernel | append-dtb + $(Device/dlink) + SIGNATURE := wrgac36_dlink.2013gui_dir890 +endef +TARGET_DEVICES += dlink_dir-890l + define Device/dlink_dwl-8610ap DEVICE_VENDOR := D-Link DEVICE_MODEL := DWL-8610AP From 06a150aed795066ce79a623011884cc0abf290f1 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Fri, 25 Aug 2023 14:00:09 +0100 Subject: [PATCH 16/29] mediatek: re-add dropped properties on BPi-R3 Unfortunately some device tree properties have slipped under the table when switching from our downstream device tree. Bring back 3W power for SFP cages and restore thermal trip points to make sense again. Fixes: 7a0ec001ff ("mediatek: sync MT7986 device trees with upstream") Signed-off-by: Daniel Golle --- .../dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 12 ++-- .../arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 20 +++++-- ...i-r3-leds-port-names-and-wifi-eeprom.patch | 4 +- ...-define-3W-max-power-to-both-SFP-on-.patch | 34 +++++++++++ ...rm64-dts-mt7986-change-cooling-trips.patch | 59 +++++++++++++++++++ ...t7986-change-thermal-trips-on-BPI-R3.patch | 38 ++++++++++++ ...i-r3-leds-port-names-and-wifi-eeprom.patch | 4 +- 7 files changed, 158 insertions(+), 13 deletions(-) create mode 100644 target/linux/mediatek/patches-6.1/020-arm64-dts-mt7986-define-3W-max-power-to-both-SFP-on-.patch create mode 100644 target/linux/mediatek/patches-6.1/021-arm64-dts-mt7986-change-cooling-trips.patch create mode 100644 target/linux/mediatek/patches-6.1/022-arm64-dts-mt7986-change-thermal-trips-on-BPI-R3.patch diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts index af4a4309bda..1d3c575b7d4 100644 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts @@ -129,6 +129,7 @@ mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>; tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>; tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt = <3000>; }; /* right SFP cage (lan) */ @@ -139,6 +140,7 @@ mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>; tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>; tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt = <3000>; }; }; @@ -150,16 +152,16 @@ trip = <&cpu_trip_active_high>; }; - cpu-active-low { + cpu-active-med { /* active: set fan to cooling level 1 */ cooling-device = <&fan 1 1>; - trip = <&cpu_trip_active_low>; + trip = <&cpu_trip_active_med>; }; - cpu-passive { - /* passive: set fan to cooling level 0 */ + cpu-active-low { + /* active: set fan to cooling level 0 */ cooling-device = <&fan 0 0>; - trip = <&cpu_trip_passive>; + trip = <&cpu_trip_active_low>; }; }; }; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index 68539ea788d..64f2cf3756a 100644 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -610,22 +610,34 @@ thermal-sensors = <&thermal 0>; trips { + cpu_trip_crit: crit { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu_trip_hot: hot { + temperature = <120000>; + hysteresis = <2000>; + type = "hot"; + }; + cpu_trip_active_high: active-high { temperature = <115000>; hysteresis = <2000>; type = "active"; }; - cpu_trip_active_low: active-low { + cpu_trip_active_med: active-med { temperature = <85000>; hysteresis = <2000>; type = "active"; }; - cpu_trip_passive: passive { - temperature = <40000>; + cpu_trip_active_low: active-low { + temperature = <60000>; hysteresis = <2000>; - type = "passive"; + type = "active"; }; }; }; diff --git a/target/linux/mediatek/patches-5.15/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch b/target/linux/mediatek/patches-5.15/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch index 7126da788be..336920bafea 100644 --- a/target/linux/mediatek/patches-5.15/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch +++ b/target/linux/mediatek/patches-5.15/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch @@ -11,7 +11,7 @@ }; chosen { -@@ -417,27 +421,27 @@ +@@ -419,27 +423,27 @@ port@1 { reg = <1>; @@ -44,7 +44,7 @@ phy-mode = "2500base-x"; sfp = <&sfp2>; managed = "in-band-status"; -@@ -488,9 +492,137 @@ +@@ -490,9 +494,137 @@ &wifi { status = "okay"; diff --git a/target/linux/mediatek/patches-6.1/020-arm64-dts-mt7986-define-3W-max-power-to-both-SFP-on-.patch b/target/linux/mediatek/patches-6.1/020-arm64-dts-mt7986-define-3W-max-power-to-both-SFP-on-.patch new file mode 100644 index 00000000000..8cba3b2059c --- /dev/null +++ b/target/linux/mediatek/patches-6.1/020-arm64-dts-mt7986-define-3W-max-power-to-both-SFP-on-.patch @@ -0,0 +1,34 @@ +From f8ed4088ed9c61ae92193da6130d04c37e7b19f2 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Sun, 20 Aug 2023 17:31:33 +0200 +Subject: [PATCH 20/22] arm64: dts: mt7986: define 3W max power to both SFP on + BPI-R3 + +All SFP power supplies are connected to the system VDD33 which is 3v3/8A. +Set 3A per SFP slot to allow SFPs work which need more power than the +default 1W. + +Fixes: 8e01fb15b815 ("arm64: dts: mt7986: add Bananapi R3") +Signed-off-by: Frank Wunderlich +--- + arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts +@@ -126,6 +126,7 @@ + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp1>; + los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>; ++ maximum-power-milliwatt = <3000>; + mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; +@@ -137,6 +138,7 @@ + i2c-bus = <&i2c_sfp2>; + los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>; ++ maximum-power-milliwatt = <3000>; + tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>; + }; diff --git a/target/linux/mediatek/patches-6.1/021-arm64-dts-mt7986-change-cooling-trips.patch b/target/linux/mediatek/patches-6.1/021-arm64-dts-mt7986-change-cooling-trips.patch new file mode 100644 index 00000000000..20d4468cf0d --- /dev/null +++ b/target/linux/mediatek/patches-6.1/021-arm64-dts-mt7986-change-cooling-trips.patch @@ -0,0 +1,59 @@ +From aa3d6df9803c267725dc72286bb91602b7579882 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Sun, 20 Aug 2023 17:31:34 +0200 +Subject: [PATCH 21/22] arm64: dts: mt7986: change cooling trips + +Add Critical and hot trips for emergency system shutdown and limiting +system load. + +Change passive trip to active to make sure fan is activated on the +lowest trip. + +Fixes: 1f5be05132f3 ("arm64: dts: mt7986: add thermal-zones") +Suggested-by: Daniel Golle +Signed-off-by: Frank Wunderlich +--- + arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 20 ++++++++++++++++---- + 1 file changed, 16 insertions(+), 4 deletions(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +@@ -610,22 +610,34 @@ + thermal-sensors = <&thermal 0>; + + trips { ++ cpu_trip_crit: crit { ++ temperature = <125000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ ++ cpu_trip_hot: hot { ++ temperature = <120000>; ++ hysteresis = <2000>; ++ type = "hot"; ++ }; ++ + cpu_trip_active_high: active-high { + temperature = <115000>; + hysteresis = <2000>; + type = "active"; + }; + +- cpu_trip_active_low: active-low { ++ cpu_trip_active_med: active-med { + temperature = <85000>; + hysteresis = <2000>; + type = "active"; + }; + +- cpu_trip_passive: passive { +- temperature = <40000>; ++ cpu_trip_active_low: active-low { ++ temperature = <60000>; + hysteresis = <2000>; +- type = "passive"; ++ type = "active"; + }; + }; + }; diff --git a/target/linux/mediatek/patches-6.1/022-arm64-dts-mt7986-change-thermal-trips-on-BPI-R3.patch b/target/linux/mediatek/patches-6.1/022-arm64-dts-mt7986-change-thermal-trips-on-BPI-R3.patch new file mode 100644 index 00000000000..7166ab6a144 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/022-arm64-dts-mt7986-change-thermal-trips-on-BPI-R3.patch @@ -0,0 +1,38 @@ +From 6ddf23526955b8dbedfeaa57e691261fd73f9d4e Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Sun, 20 Aug 2023 17:31:35 +0200 +Subject: [PATCH 22/22] arm64: dts: mt7986: change thermal trips on BPI-R3 + +Apply new naming after mt7986 thermal trips were changed. + +Fixes: c26f779a2295 ("arm64: dts: mt7986: add pwm-fan and cooling-maps to BPI-R3 dts") +Suggested-by: Daniel Golle +Signed-off-by: Frank Wunderlich +--- + .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts +@@ -152,16 +152,16 @@ + trip = <&cpu_trip_active_high>; + }; + +- cpu-active-low { ++ cpu-active-med { + /* active: set fan to cooling level 1 */ + cooling-device = <&fan 1 1>; +- trip = <&cpu_trip_active_low>; ++ trip = <&cpu_trip_active_med>; + }; + +- cpu-passive { +- /* passive: set fan to cooling level 0 */ ++ cpu-active-low { ++ /* active: set fan to cooling level 0 */ + cooling-device = <&fan 0 0>; +- trip = <&cpu_trip_passive>; ++ trip = <&cpu_trip_active_low>; + }; + }; + }; diff --git a/target/linux/mediatek/patches-6.1/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch b/target/linux/mediatek/patches-6.1/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch index 7126da788be..336920bafea 100644 --- a/target/linux/mediatek/patches-6.1/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch +++ b/target/linux/mediatek/patches-6.1/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch @@ -11,7 +11,7 @@ }; chosen { -@@ -417,27 +421,27 @@ +@@ -419,27 +423,27 @@ port@1 { reg = <1>; @@ -44,7 +44,7 @@ phy-mode = "2500base-x"; sfp = <&sfp2>; managed = "in-band-status"; -@@ -488,9 +492,137 @@ +@@ -490,9 +494,137 @@ &wifi { status = "okay"; From 69a498f95304ca9bea9276317ea4cc9fc784f510 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sun, 27 Aug 2023 16:32:50 +0100 Subject: [PATCH 17/29] mediatek: re-add missing patch for Linux 6.1 The patch was wrongly tagged as being part of Linux 6.0 even though it was only committed with Linux 6.2 and hence needs to be backported for Linux 6.1. Fixes: fa79baf4a6 ("generic: copy backport, hack, pending patch and config from 5.15 to 6.1") Signed-off-by: Daniel Golle --- ...eth_soc-enable-flow-offloading-supp.patch} | 0 ..._eth_soc-enable-flow-offloading-supp.patch | 26 +++++++++++++++++++ ...t-mtk_eth_soc-add-support-for-MT7981.patch | 2 +- ...iatek-ppe-add-support-for-flow-accou.patch | 4 +-- ..._eth_soc-move-MAX_DEVS-in-mtk_soc_da.patch | 6 ++--- ...k_eth_soc-add-support-for-MT7988-SoC.patch | 4 +-- 6 files changed, 34 insertions(+), 8 deletions(-) rename target/linux/generic/backport-5.15/{724-v6.0-net-ethernet-mtk_eth_soc-enable-flow-offloading-supp.patch => 724-v6.2-net-ethernet-mtk_eth_soc-enable-flow-offloading-supp.patch} (100%) create mode 100644 target/linux/generic/backport-6.1/724-v6.2-net-ethernet-mtk_eth_soc-enable-flow-offloading-supp.patch diff --git a/target/linux/generic/backport-5.15/724-v6.0-net-ethernet-mtk_eth_soc-enable-flow-offloading-supp.patch b/target/linux/generic/backport-5.15/724-v6.2-net-ethernet-mtk_eth_soc-enable-flow-offloading-supp.patch similarity index 100% rename from target/linux/generic/backport-5.15/724-v6.0-net-ethernet-mtk_eth_soc-enable-flow-offloading-supp.patch rename to target/linux/generic/backport-5.15/724-v6.2-net-ethernet-mtk_eth_soc-enable-flow-offloading-supp.patch diff --git a/target/linux/generic/backport-6.1/724-v6.2-net-ethernet-mtk_eth_soc-enable-flow-offloading-supp.patch b/target/linux/generic/backport-6.1/724-v6.2-net-ethernet-mtk_eth_soc-enable-flow-offloading-supp.patch new file mode 100644 index 00000000000..dcef5ff2893 --- /dev/null +++ b/target/linux/generic/backport-6.1/724-v6.2-net-ethernet-mtk_eth_soc-enable-flow-offloading-supp.patch @@ -0,0 +1,26 @@ +From 1b9827ceab08450308f7971d6fd700ec88b6ce67 Mon Sep 17 00:00:00 2001 +From: Lorenzo Bianconi +Date: Sat, 3 Dec 2022 14:20:37 +0100 +Subject: [PATCH 098/250] net: mtk_eth_soc: enable flow offload support for + MT7986 SoC + +Since Wireless Ethernet Dispatcher is now available for mt7986 in mt76, +enable hw flow support for MT7986 SoC. + +Signed-off-by: Lorenzo Bianconi +Link: https://lore.kernel.org/r/fdcaacd827938e6a8c4aa1ac2c13e46d2c08c821.1670072898.git.lorenzo@kernel.org +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -4331,6 +4331,7 @@ static const struct mtk_soc_data mt7986_ + .hw_features = MTK_HW_FEATURES, + .required_clks = MT7986_CLKS_BITMAP, + .required_pctl = false, ++ .offload_version = 2, + .hash_offset = 4, + .foe_entry_size = sizeof(struct mtk_foe_entry), + .txrx = { diff --git a/target/linux/generic/backport-6.1/733-v6.3-18-net-ethernet-mtk_eth_soc-add-support-for-MT7981.patch b/target/linux/generic/backport-6.1/733-v6.3-18-net-ethernet-mtk_eth_soc-add-support-for-MT7981.patch index dae1c6de452..8c0f320fa8f 100644 --- a/target/linux/generic/backport-6.1/733-v6.3-18-net-ethernet-mtk_eth_soc-add-support-for-MT7981.patch +++ b/target/linux/generic/backport-6.1/733-v6.3-18-net-ethernet-mtk_eth_soc-add-support-for-MT7981.patch @@ -78,7 +78,7 @@ Signed-off-by: Jakub Kicinski static const struct mtk_soc_data mt7986_data = { .reg_map = &mt7986_reg_map, .ana_rgc3 = 0x128, -@@ -4842,6 +4862,7 @@ const struct of_device_id of_mtk_match[] +@@ -4843,6 +4863,7 @@ const struct of_device_id of_mtk_match[] { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data}, diff --git a/target/linux/generic/pending-6.1/731-net-ethernet-mediatek-ppe-add-support-for-flow-accou.patch b/target/linux/generic/pending-6.1/731-net-ethernet-mediatek-ppe-add-support-for-flow-accou.patch index f942512e11c..4b4ffc63164 100644 --- a/target/linux/generic/pending-6.1/731-net-ethernet-mediatek-ppe-add-support-for-flow-accou.patch +++ b/target/linux/generic/pending-6.1/731-net-ethernet-mediatek-ppe-add-support-for-flow-accou.patch @@ -88,8 +88,8 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov .txrx = { .txd_size = sizeof(struct mtk_tx_dma_v2), .rxd_size = sizeof(struct mtk_rx_dma_v2), -@@ -4892,6 +4895,7 @@ static const struct mtk_soc_data mt7986_ - .required_pctl = false, +@@ -4893,6 +4896,7 @@ static const struct mtk_soc_data mt7986_ + .offload_version = 2, .hash_offset = 4, .foe_entry_size = sizeof(struct mtk_foe_entry), + .has_accounting = true, diff --git a/target/linux/generic/pending-6.1/737-02-net-ethernet-mtk_eth_soc-move-MAX_DEVS-in-mtk_soc_da.patch b/target/linux/generic/pending-6.1/737-02-net-ethernet-mtk_eth_soc-move-MAX_DEVS-in-mtk_soc_da.patch index e509663fa0e..bdd62a763f2 100644 --- a/target/linux/generic/pending-6.1/737-02-net-ethernet-mtk_eth_soc-move-MAX_DEVS-in-mtk_soc_da.patch +++ b/target/linux/generic/pending-6.1/737-02-net-ethernet-mtk_eth_soc-move-MAX_DEVS-in-mtk_soc_da.patch @@ -117,15 +117,15 @@ Signed-off-by: Daniel Golle .txrx = { .txd_size = sizeof(struct mtk_tx_dma_v2), .rxd_size = sizeof(struct mtk_rx_dma_v2), -@@ -4901,6 +4927,7 @@ static const struct mtk_soc_data mt7986_ - .required_clks = MT7986_CLKS_BITMAP, +@@ -4902,6 +4928,7 @@ static const struct mtk_soc_data mt7986_ .required_pctl = false, + .offload_version = 2, .hash_offset = 4, + .num_devs = 2, .foe_entry_size = sizeof(struct mtk_foe_entry), .has_accounting = true, .txrx = { -@@ -4919,6 +4946,7 @@ static const struct mtk_soc_data rt5350_ +@@ -4920,6 +4947,7 @@ static const struct mtk_soc_data rt5350_ .hw_features = MTK_HW_FEATURES_MT7628, .required_clks = MT7628_CLKS_BITMAP, .required_pctl = false, diff --git a/target/linux/generic/pending-6.1/737-06-net-ethernet-mtk_eth_soc-add-support-for-MT7988-SoC.patch b/target/linux/generic/pending-6.1/737-06-net-ethernet-mtk_eth_soc-add-support-for-MT7988-SoC.patch index f1a3df2181a..9c4408cec88 100644 --- a/target/linux/generic/pending-6.1/737-06-net-ethernet-mtk_eth_soc-add-support-for-MT7988-SoC.patch +++ b/target/linux/generic/pending-6.1/737-06-net-ethernet-mtk_eth_soc-add-support-for-MT7988-SoC.patch @@ -150,7 +150,7 @@ mtk_eth_soc driver. data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid); WRITE_ONCE(desc->txd4, data); -@@ -5009,6 +5110,25 @@ static const struct mtk_soc_data mt7986_ +@@ -5010,6 +5111,25 @@ static const struct mtk_soc_data mt7986_ }, }; @@ -176,7 +176,7 @@ mtk_eth_soc driver. static const struct mtk_soc_data rt5350_data = { .reg_map = &mt7628_reg_map, .caps = MT7628_CAPS, -@@ -5027,14 +5147,15 @@ static const struct mtk_soc_data rt5350_ +@@ -5028,14 +5148,15 @@ static const struct mtk_soc_data rt5350_ }; const struct of_device_id of_mtk_match[] = { From 2544dc34f2a6e5721096ee62efa66d36d45b2dd1 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sat, 26 Aug 2023 22:26:37 +0100 Subject: [PATCH 18/29] mediatek: i2c: mt65xx: allow optional pmic clock Using the I2C host controller on the MT7981 SoC requires 4 clocks to be enabled. One of them, the pmic clk, is only enabled in case 'mediatek,have-pmic' is also set which has other consequences which are not desired in this case. Allow defining a pmic clk even in case the 'mediatek,have-pmic' propterty is not present and the bus is not used to connect to a pmic, but may still require to enable the pmic clock. Signed-off-by: Daniel Golle --- ...i2c-mt65xx-allow-optional-pmic-clock.patch | 45 +++++++++++++++++++ ...i2c-mt65xx-allow-optional-pmic-clock.patch | 45 +++++++++++++++++++ 2 files changed, 90 insertions(+) create mode 100644 target/linux/mediatek/patches-5.15/855-i2c-mt65xx-allow-optional-pmic-clock.patch create mode 100644 target/linux/mediatek/patches-6.1/855-i2c-mt65xx-allow-optional-pmic-clock.patch diff --git a/target/linux/mediatek/patches-5.15/855-i2c-mt65xx-allow-optional-pmic-clock.patch b/target/linux/mediatek/patches-5.15/855-i2c-mt65xx-allow-optional-pmic-clock.patch new file mode 100644 index 00000000000..69cc155d8d2 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/855-i2c-mt65xx-allow-optional-pmic-clock.patch @@ -0,0 +1,45 @@ +From 3bf827929a44c17bfb1bf1000b143c02ce26a929 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Sat, 26 Aug 2023 21:56:51 +0100 +Subject: [PATCH] i2c: mt65xx: allow optional pmic clock + +Using the I2C host controller on the MT7981 SoC requires 4 clocks to +be enabled. One of them, the pmic clk, is only enabled in case +'mediatek,have-pmic' is also set which has other consequences which +are not desired in this case. + +Allow defining a pmic clk even in case the 'mediatek,have-pmic' propterty +is not present and the bus is not used to connect to a pmic, but may +still require to enable the pmic clock. + +Signed-off-by: Daniel Golle +--- + drivers/i2c/busses/i2c-mt65xx.c | 12 ++++++++---- + 1 file changed, 8 insertions(+), 4 deletions(-) + +--- a/drivers/i2c/busses/i2c-mt65xx.c ++++ b/drivers/i2c/busses/i2c-mt65xx.c +@@ -1444,15 +1444,19 @@ static int mtk_i2c_probe(struct platform + if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk)) + return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk); + ++ i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get_optional(&pdev->dev, "pmic"); ++ if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) { ++ dev_err(&pdev->dev, "cannot get pmic clock\n"); ++ return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk); ++ } ++ + if (i2c->have_pmic) { +- i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get(&pdev->dev, "pmic"); +- if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) { ++ if (!i2c->clocks[I2C_MT65XX_CLK_PMIC].clk) { + dev_err(&pdev->dev, "cannot get pmic clock\n"); +- return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk); ++ return -ENODEV; + } + speed_clk = I2C_MT65XX_CLK_PMIC; + } else { +- i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = NULL; + speed_clk = I2C_MT65XX_CLK_MAIN; + } + diff --git a/target/linux/mediatek/patches-6.1/855-i2c-mt65xx-allow-optional-pmic-clock.patch b/target/linux/mediatek/patches-6.1/855-i2c-mt65xx-allow-optional-pmic-clock.patch new file mode 100644 index 00000000000..69cc155d8d2 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/855-i2c-mt65xx-allow-optional-pmic-clock.patch @@ -0,0 +1,45 @@ +From 3bf827929a44c17bfb1bf1000b143c02ce26a929 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Sat, 26 Aug 2023 21:56:51 +0100 +Subject: [PATCH] i2c: mt65xx: allow optional pmic clock + +Using the I2C host controller on the MT7981 SoC requires 4 clocks to +be enabled. One of them, the pmic clk, is only enabled in case +'mediatek,have-pmic' is also set which has other consequences which +are not desired in this case. + +Allow defining a pmic clk even in case the 'mediatek,have-pmic' propterty +is not present and the bus is not used to connect to a pmic, but may +still require to enable the pmic clock. + +Signed-off-by: Daniel Golle +--- + drivers/i2c/busses/i2c-mt65xx.c | 12 ++++++++---- + 1 file changed, 8 insertions(+), 4 deletions(-) + +--- a/drivers/i2c/busses/i2c-mt65xx.c ++++ b/drivers/i2c/busses/i2c-mt65xx.c +@@ -1444,15 +1444,19 @@ static int mtk_i2c_probe(struct platform + if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk)) + return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk); + ++ i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get_optional(&pdev->dev, "pmic"); ++ if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) { ++ dev_err(&pdev->dev, "cannot get pmic clock\n"); ++ return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk); ++ } ++ + if (i2c->have_pmic) { +- i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get(&pdev->dev, "pmic"); +- if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) { ++ if (!i2c->clocks[I2C_MT65XX_CLK_PMIC].clk) { + dev_err(&pdev->dev, "cannot get pmic clock\n"); +- return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk); ++ return -ENODEV; + } + speed_clk = I2C_MT65XX_CLK_PMIC; + } else { +- i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = NULL; + speed_clk = I2C_MT65XX_CLK_MAIN; + } + From 9f8fde216d994ce47b1eca15de190aa9b8f67b9a Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sun, 27 Aug 2023 00:38:38 +0100 Subject: [PATCH 19/29] mediatek: filogic: improve pinctrl drivers Set correct pull-type data and add additional uart groups for MT7981. Assign functions to configure pin bias for MT7986. Signed-off-by: Daniel Golle --- .../drivers/pinctrl/mediatek/pinctrl-mt7981.c | 55 ++++++-------- .../drivers/pinctrl/mediatek/pinctrl-mt7986.c | 8 ++ ...diatek-fix-pull_type-data-for-MT7981.patch | 76 +++++++++++++++++++ ...ek-mt7981-add-additional-uart-groups.patch | 65 ++++++++++++++++ ...-assign-functions-to-configure-pin-b.patch | 41 ++++++++++ 5 files changed, 214 insertions(+), 31 deletions(-) create mode 100644 target/linux/mediatek/patches-6.1/217-v6.5-pinctrl-mediatek-fix-pull_type-data-for-MT7981.patch create mode 100644 target/linux/mediatek/patches-6.1/218-pinctrl-mediatek-mt7981-add-additional-uart-groups.patch create mode 100644 target/linux/mediatek/patches-6.1/219-pinctrl-mediatek-assign-functions-to-configure-pin-b.patch diff --git a/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7981.c b/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7981.c index 18abc578001..7c082dd207b 100644 --- a/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7981.c +++ b/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7981.c @@ -457,37 +457,15 @@ static const unsigned int mt7981_pull_type[] = { MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/ MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/ MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/ - MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/ - MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/ - MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/ - MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/ - MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/ - MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/ - MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/ - MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/ - MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/ - MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/ - MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/ - MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/ - MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/ - MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/ - MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/ - MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/ - MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/ - MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/ - MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/ - MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/ - MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/ - MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/ - MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/ - MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/ - MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/ - MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/ - MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/ - MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/ - MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/ - MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/ - MTK_PULL_PU_PD_TYPE,/*100*/ + MTK_PULL_PU_PD_TYPE,/*40*/ MTK_PULL_PU_PD_TYPE,/*41*/ + MTK_PULL_PU_PD_TYPE,/*42*/ MTK_PULL_PU_PD_TYPE,/*43*/ + MTK_PULL_PU_PD_TYPE,/*44*/ MTK_PULL_PU_PD_TYPE,/*45*/ + MTK_PULL_PU_PD_TYPE,/*46*/ MTK_PULL_PU_PD_TYPE,/*47*/ + MTK_PULL_PU_PD_TYPE,/*48*/ MTK_PULL_PU_PD_TYPE,/*49*/ + MTK_PULL_PU_PD_TYPE,/*50*/ MTK_PULL_PU_PD_TYPE,/*51*/ + MTK_PULL_PU_PD_TYPE,/*52*/ MTK_PULL_PU_PD_TYPE,/*53*/ + MTK_PULL_PU_PD_TYPE,/*54*/ MTK_PULL_PU_PD_TYPE,/*55*/ + MTK_PULL_PU_PD_TYPE,/*56*/ }; static const struct mtk_pin_reg_calc mt7981_reg_cals[] = { @@ -633,6 +611,9 @@ static int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, }; static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, }; +static int mt7981_uart2_0_tx_rx_pins[] = { 4, 5, }; +static int mt7981_uart2_0_tx_rx_funcs[] = { 3, 3, }; + /* GBE_LED0 */ static int mt7981_gbe_led0_pins[] = { 8, }; static int mt7981_gbe_led0_funcs[] = { 3, }; @@ -753,6 +734,9 @@ static int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, }; static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, }; static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, }; +static int mt7981_uart1_2_pins[] = { 9, 10, }; +static int mt7981_uart1_2_funcs[] = { 2, 2, }; + /* UART2 */ static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, }; static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, }; @@ -827,6 +811,8 @@ static const struct group_desc mt7981_groups[] = { PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0), /* @GPIO(4,7) WM_JTAG(3) */ PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0), + /* @GPIO(4,5) WM_JTAG(4) */ + PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7981_uart2_0_tx_rx), /* @GPIO(8) GBE_LED0(3) */ PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0), /* @GPIO(4,6) PTA_EXT(4) */ @@ -883,6 +869,8 @@ static const struct group_desc mt7981_groups[] = { PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0), /* @GPIO(26,29): UART1(2) */ PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1), + /* @GPIO(9,10): UART1(2) */ + PINCTRL_PIN_GROUP("uart1_2", mt7981_uart1_2), /* @GPIO(22,25): UART1(3) */ PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1), /* @GPIO(22,24) PTA_EXT(4) */ @@ -945,6 +933,7 @@ static const struct group_desc mt7981_groups[] = { static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1", "wa_aice3", "wm_aice1_2", }; static const char *mt7981_uart_groups[] = { "wm_uart_0", "uart2_0", + "uart1_2", "uart2_0_tx_rx", "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2", "uart1_0", "uart1_1", "uart2_1", "wm_aurt_1", "wm_aurt_2", "uart0", }; static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", }; @@ -1014,6 +1003,10 @@ static struct mtk_pin_soc mt7981_data = { .ies_present = false, .base_names = mt7981_pinctrl_register_base_names, .nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names), + .bias_disable_set = mtk_pinconf_bias_disable_set, + .bias_disable_get = mtk_pinconf_bias_disable_get, + .bias_set = mtk_pinconf_bias_set, + .bias_get = mtk_pinconf_bias_get, .pull_type = mt7981_pull_type, .bias_set_combo = mtk_pinconf_bias_set_combo, .bias_get_combo = mtk_pinconf_bias_get_combo, diff --git a/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7986.c b/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7986.c index aa0ccd67f4f..acaac9b38aa 100644 --- a/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7986.c +++ b/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7986.c @@ -922,6 +922,10 @@ static struct mtk_pin_soc mt7986a_data = { .ies_present = false, .base_names = mt7986_pinctrl_register_base_names, .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), + .bias_disable_set = mtk_pinconf_bias_disable_set, + .bias_disable_get = mtk_pinconf_bias_disable_get, + .bias_set = mtk_pinconf_bias_set, + .bias_get = mtk_pinconf_bias_get, .pull_type = mt7986_pull_type, .bias_set_combo = mtk_pinconf_bias_set_combo, .bias_get_combo = mtk_pinconf_bias_get_combo, @@ -944,6 +948,10 @@ static struct mtk_pin_soc mt7986b_data = { .ies_present = false, .base_names = mt7986_pinctrl_register_base_names, .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), + .bias_disable_set = mtk_pinconf_bias_disable_set, + .bias_disable_get = mtk_pinconf_bias_disable_get, + .bias_set = mtk_pinconf_bias_set, + .bias_get = mtk_pinconf_bias_get, .pull_type = mt7986_pull_type, .bias_set_combo = mtk_pinconf_bias_set_combo, .bias_get_combo = mtk_pinconf_bias_get_combo, diff --git a/target/linux/mediatek/patches-6.1/217-v6.5-pinctrl-mediatek-fix-pull_type-data-for-MT7981.patch b/target/linux/mediatek/patches-6.1/217-v6.5-pinctrl-mediatek-fix-pull_type-data-for-MT7981.patch new file mode 100644 index 00000000000..db2561695bf --- /dev/null +++ b/target/linux/mediatek/patches-6.1/217-v6.5-pinctrl-mediatek-fix-pull_type-data-for-MT7981.patch @@ -0,0 +1,76 @@ +From 8f6f16fe1553ce63edfb98a39ef9d4754a0c39bf Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Fri, 18 Aug 2023 04:02:35 +0100 +Subject: [PATCH] pinctrl: mediatek: fix pull_type data for MT7981 + +MediaTek has released pull_type data for MT7981 in their SDK. +Use it and set functions to configure pin bias. + +Fixes: 6c83b2d94fcc ("pinctrl: add mt7981 pinctrl driver") +Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/7bcc8ead25dbfabc7f5a85d066224a926fbb4941.1692327317.git.daniel@makrotopia.org +Signed-off-by: Linus Walleij +--- + drivers/pinctrl/mediatek/pinctrl-mt7981.c | 44 +++++++---------------- + 1 file changed, 13 insertions(+), 31 deletions(-) + +--- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c +@@ -457,37 +457,15 @@ static const unsigned int mt7981_pull_ty + MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/ + MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/ + MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/ +- MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/ +- MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/ +- MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/ +- MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/ +- MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/ +- MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/ +- MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/ +- MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/ +- MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/ +- MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/ +- MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/ +- MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/ +- MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/ +- MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/ +- MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/ +- MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/ +- MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/ +- MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/ +- MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/ +- MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/ +- MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/ +- MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/ +- MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/ +- MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/ +- MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/ +- MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/ +- MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/ +- MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/ +- MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/ +- MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/ +- MTK_PULL_PU_PD_TYPE,/*100*/ ++ MTK_PULL_PU_PD_TYPE,/*40*/ MTK_PULL_PU_PD_TYPE,/*41*/ ++ MTK_PULL_PU_PD_TYPE,/*42*/ MTK_PULL_PU_PD_TYPE,/*43*/ ++ MTK_PULL_PU_PD_TYPE,/*44*/ MTK_PULL_PU_PD_TYPE,/*45*/ ++ MTK_PULL_PU_PD_TYPE,/*46*/ MTK_PULL_PU_PD_TYPE,/*47*/ ++ MTK_PULL_PU_PD_TYPE,/*48*/ MTK_PULL_PU_PD_TYPE,/*49*/ ++ MTK_PULL_PU_PD_TYPE,/*50*/ MTK_PULL_PU_PD_TYPE,/*51*/ ++ MTK_PULL_PU_PD_TYPE,/*52*/ MTK_PULL_PU_PD_TYPE,/*53*/ ++ MTK_PULL_PU_PD_TYPE,/*54*/ MTK_PULL_PU_PD_TYPE,/*55*/ ++ MTK_PULL_PU_PD_TYPE,/*56*/ + }; + + static const struct mtk_pin_reg_calc mt7981_reg_cals[] = { +@@ -1014,6 +992,10 @@ static struct mtk_pin_soc mt7981_data = + .ies_present = false, + .base_names = mt7981_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names), ++ .bias_disable_set = mtk_pinconf_bias_disable_set, ++ .bias_disable_get = mtk_pinconf_bias_disable_get, ++ .bias_set = mtk_pinconf_bias_set, ++ .bias_get = mtk_pinconf_bias_get, + .pull_type = mt7981_pull_type, + .bias_set_combo = mtk_pinconf_bias_set_combo, + .bias_get_combo = mtk_pinconf_bias_get_combo, diff --git a/target/linux/mediatek/patches-6.1/218-pinctrl-mediatek-mt7981-add-additional-uart-groups.patch b/target/linux/mediatek/patches-6.1/218-pinctrl-mediatek-mt7981-add-additional-uart-groups.patch new file mode 100644 index 00000000000..d2f055836ba --- /dev/null +++ b/target/linux/mediatek/patches-6.1/218-pinctrl-mediatek-mt7981-add-additional-uart-groups.patch @@ -0,0 +1,65 @@ +From 11db447f257231e08065989100311df57b7f1f1c Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Sat, 26 Aug 2023 21:06:14 +0100 +Subject: [PATCH] pinctrl: mediatek: mt7981: add additional uart groups + +Add uart2_0_tx_rx (pin 4, 5) and uart1_2 (pins 9, 10) groups. + +Signed-off-by: Daniel Golle +--- + drivers/pinctrl/mediatek/pinctrl-mt7981.c | 16 +++++++++++++--- + 1 file changed, 13 insertions(+), 3 deletions(-) + +--- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c +@@ -611,6 +611,9 @@ static int mt7981_wo0_jtag_1_funcs[] = { + static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, }; + static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, }; + ++static int mt7981_uart2_0_tx_rx_pins[] = { 4, 5, }; ++static int mt7981_uart2_0_tx_rx_funcs[] = { 3, 3, }; ++ + /* GBE_LED0 */ + static int mt7981_gbe_led0_pins[] = { 8, }; + static int mt7981_gbe_led0_funcs[] = { 3, }; +@@ -731,6 +734,9 @@ static int mt7981_uart1_0_funcs[] = { 4, + static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, }; + static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, }; + ++static int mt7981_uart1_2_pins[] = { 9, 10, }; ++static int mt7981_uart1_2_funcs[] = { 2, 2, }; ++ + /* UART2 */ + static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, }; + static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, }; +@@ -805,6 +811,8 @@ static const struct group_desc mt7981_gr + PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0), + /* @GPIO(4,7) WM_JTAG(3) */ + PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0), ++ /* @GPIO(4,5) WM_JTAG(4) */ ++ PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7981_uart2_0_tx_rx), + /* @GPIO(8) GBE_LED0(3) */ + PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0), + /* @GPIO(4,6) PTA_EXT(4) */ +@@ -861,6 +869,8 @@ static const struct group_desc mt7981_gr + PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0), + /* @GPIO(26,29): UART1(2) */ + PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1), ++ /* @GPIO(9,10): UART1(2) */ ++ PINCTRL_PIN_GROUP("uart1_2", mt7981_uart1_2), + /* @GPIO(22,25): UART1(3) */ + PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1), + /* @GPIO(22,24) PTA_EXT(4) */ +@@ -922,9 +932,9 @@ static const struct group_desc mt7981_gr + */ + static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1", + "wa_aice3", "wm_aice1_2", }; +-static const char *mt7981_uart_groups[] = { "wm_uart_0", "uart2_0", +- "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2", +- "uart1_0", "uart1_1", "uart2_1", "wm_aurt_1", "wm_aurt_2", "uart0", }; ++static const char *mt7981_uart_groups[] = { "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", ++ "net_wo0_uart_txd_2", "uart0", "uart1_0", "uart1_1", "uart1_2", "uart2_0", ++ "uart2_0_tx_rx", "uart2_1", "wm_uart_0", "wm_aurt_1", "wm_aurt_2", }; + static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", }; + static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", }; + static const char *mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", "pcie_wake", }; diff --git a/target/linux/mediatek/patches-6.1/219-pinctrl-mediatek-assign-functions-to-configure-pin-b.patch b/target/linux/mediatek/patches-6.1/219-pinctrl-mediatek-assign-functions-to-configure-pin-b.patch new file mode 100644 index 00000000000..7992a026774 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/219-pinctrl-mediatek-assign-functions-to-configure-pin-b.patch @@ -0,0 +1,41 @@ +From 0d8387fba9f151220e48dc3dcdc2335539708f13 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Fri, 18 Aug 2023 04:03:26 +0100 +Subject: [PATCH] pinctrl: mediatek: assign functions to configure pin bias on + MT7986 + +Assign bias_disable_get/set and bias_get/set functions to allow +configuring pin bias on MT7986. + +Fixes: 2c58d8dc9cd0 ("pinctrl: mediatek: add pull_type attribute for mediatek MT7986 SoC") +Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/47f72372354312a839b9337e09476aadcc206e8b.1692327317.git.daniel@makrotopia.org +Signed-off-by: Linus Walleij +--- + drivers/pinctrl/mediatek/pinctrl-mt7986.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c +@@ -922,6 +922,10 @@ static struct mtk_pin_soc mt7986a_data = + .ies_present = false, + .base_names = mt7986_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), ++ .bias_disable_set = mtk_pinconf_bias_disable_set, ++ .bias_disable_get = mtk_pinconf_bias_disable_get, ++ .bias_set = mtk_pinconf_bias_set, ++ .bias_get = mtk_pinconf_bias_get, + .pull_type = mt7986_pull_type, + .bias_set_combo = mtk_pinconf_bias_set_combo, + .bias_get_combo = mtk_pinconf_bias_get_combo, +@@ -944,6 +948,10 @@ static struct mtk_pin_soc mt7986b_data = + .ies_present = false, + .base_names = mt7986_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), ++ .bias_disable_set = mtk_pinconf_bias_disable_set, ++ .bias_disable_get = mtk_pinconf_bias_disable_get, ++ .bias_set = mtk_pinconf_bias_set, ++ .bias_get = mtk_pinconf_bias_get, + .pull_type = mt7986_pull_type, + .bias_set_combo = mtk_pinconf_bias_set_combo, + .bias_get_combo = mtk_pinconf_bias_get_combo, From 3ef8760e876e09fa91b54a09b2a5003c175829d3 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sun, 27 Aug 2023 15:57:00 +0100 Subject: [PATCH 20/29] mediatek: improve mt7981.dtsi * re-factor WED components to boot fine also on limited loaders * add LEDs of integrated GE PHY Signed-off-by: Daniel Golle --- .../arch/arm64/boot/dts/mediatek/mt7981.dtsi | 71 ++++++++++++++----- .../arch/arm64/boot/dts/mediatek/mt7981.dtsi | 71 ++++++++++++++----- 2 files changed, 104 insertions(+), 38 deletions(-) diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981.dtsi index 3629a6f6dda..05d4b7d91da 100644 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981.dtsi +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -191,21 +192,6 @@ reg = <0 0x47dc0000 0 0x240000>; no-map; }; - - wo_ilm0: wo-ilm@151e0000 { - reg = <0 0x151e0000 0 0x8000>; - no-map; - }; - - wo_dlm0: wo-dlm@151e8000 { - reg = <0 0x151e8000 0 0x2000>; - no-map; - }; - - wo_boot: wo-boot@15194000 { - reg = <0 0x15194000 0 0x1000>; - no-map; - }; }; psci { @@ -432,6 +418,20 @@ drive-strength = <4>; }; }; + + gbe_led0_pins: gbe-led0-pins { + mux { + function = "led"; + groups = "gbe_led0"; + }; + }; + + gbe_led1_pins: gbe-led1-pins { + mux { + function = "led"; + groups = "gbe_led1"; + }; + }; }; ethsys: syscon@15000000 { @@ -452,11 +452,12 @@ reg = <0 0x15010000 0 0x1000>; interrupt-parent = <&gic>; interrupts = ; - memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, - <&wo_data>, <&wo_boot>; - memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", - "wo-data", "wo-boot"; + memory-region = <&wo_emi0>, <&wo_data>; + memory-region-names = "wo-emi", "wo-data"; mediatek,wo-ccif = <&wo_ccif0>; + mediatek,wo-ilm = <&wo_ilm0>; + mediatek,wo-dlm = <&wo_dlm0>; + mediatek,wo-cpuboot = <&wo_cpuboot>; }; eth: ethernet@15100000 { @@ -511,10 +512,42 @@ phy-is-integrated; nvmem-cells = <&phy_calibration>; nvmem-cell-names = "phy-cal-data"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + int_gbe_phy_led0: int-gbe-phy-led0@0 { + reg = <0>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + + int_gbe_phy_led1: int-gbe-phy-led1@1 { + reg = <1>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + }; }; }; }; + wo_dlm0: syscon@151e8000 { + compatible = "mediatek,mt7986-wo-dlm", "syscon"; + reg = <0 0x151e8000 0 0x2000>; + }; + + wo_ilm0: syscon@151e0000 { + compatible = "mediatek,mt7986-wo-ilm", "syscon"; + reg = <0 0x151e0000 0 0x8000>; + }; + + wo_cpuboot: syscon@15194000 { + compatible = "mediatek,mt7986-wo-cpuboot", "syscon"; + reg = <0 0x15194000 0 0x1000>; + }; + wo_ccif0: syscon@151a5000 { compatible = "mediatek,mt7986-wo-ccif", "syscon"; reg = <0 0x151a5000 0 0x1000>; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi index 3629a6f6dda..05d4b7d91da 100644 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -191,21 +192,6 @@ reg = <0 0x47dc0000 0 0x240000>; no-map; }; - - wo_ilm0: wo-ilm@151e0000 { - reg = <0 0x151e0000 0 0x8000>; - no-map; - }; - - wo_dlm0: wo-dlm@151e8000 { - reg = <0 0x151e8000 0 0x2000>; - no-map; - }; - - wo_boot: wo-boot@15194000 { - reg = <0 0x15194000 0 0x1000>; - no-map; - }; }; psci { @@ -432,6 +418,20 @@ drive-strength = <4>; }; }; + + gbe_led0_pins: gbe-led0-pins { + mux { + function = "led"; + groups = "gbe_led0"; + }; + }; + + gbe_led1_pins: gbe-led1-pins { + mux { + function = "led"; + groups = "gbe_led1"; + }; + }; }; ethsys: syscon@15000000 { @@ -452,11 +452,12 @@ reg = <0 0x15010000 0 0x1000>; interrupt-parent = <&gic>; interrupts = ; - memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, - <&wo_data>, <&wo_boot>; - memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", - "wo-data", "wo-boot"; + memory-region = <&wo_emi0>, <&wo_data>; + memory-region-names = "wo-emi", "wo-data"; mediatek,wo-ccif = <&wo_ccif0>; + mediatek,wo-ilm = <&wo_ilm0>; + mediatek,wo-dlm = <&wo_dlm0>; + mediatek,wo-cpuboot = <&wo_cpuboot>; }; eth: ethernet@15100000 { @@ -511,10 +512,42 @@ phy-is-integrated; nvmem-cells = <&phy_calibration>; nvmem-cell-names = "phy-cal-data"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + int_gbe_phy_led0: int-gbe-phy-led0@0 { + reg = <0>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + + int_gbe_phy_led1: int-gbe-phy-led1@1 { + reg = <1>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + }; }; }; }; + wo_dlm0: syscon@151e8000 { + compatible = "mediatek,mt7986-wo-dlm", "syscon"; + reg = <0 0x151e8000 0 0x2000>; + }; + + wo_ilm0: syscon@151e0000 { + compatible = "mediatek,mt7986-wo-ilm", "syscon"; + reg = <0 0x151e0000 0 0x8000>; + }; + + wo_cpuboot: syscon@15194000 { + compatible = "mediatek,mt7986-wo-cpuboot", "syscon"; + reg = <0 0x15194000 0 0x1000>; + }; + wo_ccif0: syscon@151a5000 { compatible = "mediatek,mt7986-wo-ccif", "syscon"; reg = <0 0x151a5000 0 0x1000>; From 1d5778e18d9a6bef26aff3a8594306fc45e9be76 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Fri, 25 Aug 2023 03:58:33 +0100 Subject: [PATCH 21/29] uboot-mediatek: build fully-featured U-Boot for MT7988 RFB Select many potentially useful options for the MT7988 RFB U-Boot builds. The resulting loader is intended as a development tool and intends to be generic. It does *not* have a default bootcmd set, but allows to boot pretty much everything, including EFI executables. To install this U-Boot build to the eMMC: opkg install mmc-utils partx-utils mmc bootpart enable 1 1 /dev/mmcblk0 echo 0 > /sys/block/mmcblk0boot0/force_ro dd if=*mediatek_mt7988a-rfb-nand-emmc-preloader.bin of=/dev/mmcblk0boot0 dd if=*mediatek_mt7988a-rfb-nand-emmc-gpt.bin of=/dev/mmcblk0 partx -a /dev/mmcblk0 dd if=*mediatek_mt7988a-rfb-nand-emmc-bl31-uboot.fip of=/dev/mmcblk0p3 Signed-off-by: Daniel Golle --- package/boot/uboot-mediatek/Makefile | 29 +- ...d-ability-to-select-item-by-shortkey.patch | 11 + ...mediatek-add-MT7988-reference-boards.patch | 4 +- ...figs-add-usefull-stuff-to-mt7988-rfb.patch | 314 ++++++++++++++++++ 4 files changed, 342 insertions(+), 16 deletions(-) create mode 100644 package/boot/uboot-mediatek/patches/105-configs-add-usefull-stuff-to-mt7988-rfb.patch diff --git a/package/boot/uboot-mediatek/Makefile b/package/boot/uboot-mediatek/Makefile index a5401860c2b..a04e629f122 100644 --- a/package/boot/uboot-mediatek/Makefile +++ b/package/boot/uboot-mediatek/Makefile @@ -324,60 +324,61 @@ endef define U-Boot/mt7988_rfb-spim-nand NAME:=MT7988 Reference Board BUILD_SUBTARGET:=filogic - BUILD_DEVICES:=mediatek_mt7988a-rfb-nand + BUILD_DEVICES:=mediatek_mt7988a-rfb UBOOT_CONFIG:=mt7988_rfb UBOOT_IMAGE:=u-boot.fip BL2_BOOTDEV:=spim-nand BL2_SOC:=mt7988 - BL2_DDRTYPE:=ddr4 - DEPENDS:=+trusted-firmware-a-mt7988-spim-nand-ddr4 + BL2_DDRTYPE:=comb + DEPENDS:=+trusted-firmware-a-mt7988-spim-nand-comb endef define U-Boot/mt7988_rfb-snand NAME:=MT7988 Reference Board BUILD_SUBTARGET:=filogic - BUILD_DEVICES:=mediatek_mt7988a-rfb-nand + BUILD_DEVICES:=mediatek_mt7988a-rfb UBOOT_CONFIG:=mt7988_rfb UBOOT_IMAGE:=u-boot.fip BL2_BOOTDEV:=snand BL2_SOC:=mt7988 - BL2_DDRTYPE:=ddr4 - DEPENDS:=+trusted-firmware-a-mt7988-snand-ddr4 + BL2_DDRTYPE:=comb + DEPENDS:=+trusted-firmware-a-mt7988-snand-comb endef define U-Boot/mt7988_rfb-nor NAME:=MT7988 Reference Board BUILD_SUBTARGET:=filogic - BUILD_DEVICES:=mediatek_mt7988a-rfb-nand + BUILD_DEVICES:=mediatek_mt7988a-rfb UBOOT_CONFIG:=mt7988_rfb UBOOT_IMAGE:=u-boot.fip BL2_BOOTDEV:=nor BL2_SOC:=mt7988 - BL2_DDRTYPE:=ddr4 - DEPENDS:=+trusted-firmware-a-mt7988-nor-ddr4 + BL2_DDRTYPE:=comb + DEPENDS:=+trusted-firmware-a-mt7988-nor-comb + FIP_COMPRESS:=1 endef define U-Boot/mt7988_rfb-emmc NAME:=MT7988 Reference Board BUILD_SUBTARGET:=filogic - BUILD_DEVICES:=mediatek_mt7988a-rfb-nand + BUILD_DEVICES:=mediatek_mt7988a-rfb UBOOT_CONFIG:=mt7988_rfb UBOOT_IMAGE:=u-boot.fip BL2_BOOTDEV:=emmc BL2_SOC:=mt7988 - BL2_DDRTYPE:=ddr4 - DEPENDS:=+trusted-firmware-a-mt7988-emmc-ddr4 + BL2_DDRTYPE:=comb + DEPENDS:=+trusted-firmware-a-mt7988-emmc-comb endef define U-Boot/mt7988_rfb-sd NAME:=MT7988 Reference Board BUILD_SUBTARGET:=filogic - BUILD_DEVICES:=mediatek_mt7988a-rfb-nand + BUILD_DEVICES:=mediatek_mt7988a-rfb UBOOT_CONFIG:=mt7988_sd_rfb UBOOT_IMAGE:=u-boot.fip BL2_BOOTDEV:=sdmmc BL2_SOC:=mt7988 - BL2_DDRTYPE:=ddr4 + BL2_DDRTYPE:=comb DEPENDS:=+trusted-firmware-a-mt7988-sdmmc-ddr4 endef diff --git a/package/boot/uboot-mediatek/patches/100-16-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch b/package/boot/uboot-mediatek/patches/100-16-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch index 6a9ac54dfd8..315f7f92a3d 100644 --- a/package/boot/uboot-mediatek/patches/100-16-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch +++ b/package/boot/uboot-mediatek/patches/100-16-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch @@ -310,3 +310,14 @@ Signed-off-by: Weijie Gao switch (key) { case BKEY_PLUS: +--- a/boot/bootflow_menu.c ++++ b/boot/bootflow_menu.c +@@ -231,7 +231,7 @@ int bootflow_menu_run(struct bootstd_pri + + key = 0; + if (ichar) { +- key = bootmenu_conv_key(ichar); ++ key = bootmenu_conv_key(NULL, ichar, NULL); + if (key == BKEY_NONE) + key = ichar; + } diff --git a/package/boot/uboot-mediatek/patches/101-29-board-mediatek-add-MT7988-reference-boards.patch b/package/boot/uboot-mediatek/patches/101-29-board-mediatek-add-MT7988-reference-boards.patch index e2a7309e7e1..ef41f4d56a0 100644 --- a/package/boot/uboot-mediatek/patches/101-29-board-mediatek-add-MT7988-reference-boards.patch +++ b/package/boot/uboot-mediatek/patches/101-29-board-mediatek-add-MT7988-reference-boards.patch @@ -411,7 +411,7 @@ Signed-off-by: Weijie Gao +CONFIG_TARGET_MT7988=y +CONFIG_DEBUG_UART_BASE=0x11000000 +CONFIG_DEBUG_UART_CLOCK=40000000 -+CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_SYS_LOAD_ADDR=0x50000000 +CONFIG_DEBUG_UART=y +# CONFIG_AUTOBOOT is not set +CONFIG_DEFAULT_FDT_FILE="mt7988-rfb" @@ -497,7 +497,7 @@ Signed-off-by: Weijie Gao +CONFIG_TARGET_MT7988=y +CONFIG_DEBUG_UART_BASE=0x11000000 +CONFIG_DEBUG_UART_CLOCK=40000000 -+CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_SYS_LOAD_ADDR=0x50000000 +CONFIG_DEBUG_UART=y +# CONFIG_AUTOBOOT is not set +CONFIG_DEFAULT_FDT_FILE="mt7988-sd-rfb" diff --git a/package/boot/uboot-mediatek/patches/105-configs-add-usefull-stuff-to-mt7988-rfb.patch b/package/boot/uboot-mediatek/patches/105-configs-add-usefull-stuff-to-mt7988-rfb.patch new file mode 100644 index 00000000000..c7dcf9a1ba7 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/105-configs-add-usefull-stuff-to-mt7988-rfb.patch @@ -0,0 +1,314 @@ +--- a/configs/mt7988_sd_rfb_defconfig ++++ b/configs/mt7988_sd_rfb_defconfig +@@ -12,6 +12,24 @@ CONFIG_DEBUG_UART_BASE=0x11000000 + CONFIG_DEBUG_UART_CLOCK=40000000 + CONFIG_SYS_LOAD_ADDR=0x50000000 + CONFIG_DEBUG_UART=y ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_SPI_BOOT=y ++CONFIG_SD_BOOT=y ++CONFIG_NAND_BOOT=y ++CONFIG_BOOTSTD_DEFAULTS=y ++CONFIG_BOOTSTD_FULL=y + # CONFIG_AUTOBOOT is not set + CONFIG_DEFAULT_FDT_FILE="mt7988-sd-rfb" + CONFIG_LOGLEVEL=7 +@@ -22,15 +40,118 @@ CONFIG_SYS_PBSIZE=1049 + # CONFIG_BOOTM_PLAN9 is not set + # CONFIG_BOOTM_RTEMS is not set + # CONFIG_BOOTM_VXWORKS is not set +-# CONFIG_CMD_ELF is not set ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_ELF=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y + CONFIG_CMD_CLK=y + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_NAND=y ++CONFIG_CMD_NAND_TRIMFFS=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y + CONFIG_CMD_PWM=y + CONFIG_CMD_MMC=y + CONFIG_CMD_MTD=y + CONFIG_CMD_PING=y ++CONFIG_CMD_SF=y + CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_CMD_UBIFS=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_MMC=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_USB=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_NETCONSOLE=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_SCSI=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_PCI=y ++CONFIG_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y ++# CONFIG_MTD_RAW_NAND is not set ++CONFIG_DM_PCI=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PINCTRL_MT7988=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_USB=y ++CONFIG_USB_HOST=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_ENV_OFFSET=0x400000 ++CONFIG_ENV_OFFSET_REDUND=0x440000 ++CONFIG_ENV_SIZE=0x40000 ++CONFIG_ENV_SIZE_REDUND=0x40000 + CONFIG_DOS_PARTITION=y + CONFIG_EFI_PARTITION=y + CONFIG_PARTITION_TYPE_GUID=y +@@ -46,6 +167,9 @@ CONFIG_PROT_TCP=y + CONFIG_REGMAP=y + CONFIG_SYSCON=y + CONFIG_CLK=y ++CONFIG_MMC=y ++CONFIG_MMC_DEFAULT_DEV=1 ++CONFIG_MMC_SUPPORTS_TUNING=y + CONFIG_MMC_HS200_SUPPORT=y + CONFIG_MMC_MTK=y + CONFIG_MTD=y +--- a/configs/mt7988_rfb_defconfig ++++ b/configs/mt7988_rfb_defconfig +@@ -12,6 +12,24 @@ CONFIG_DEBUG_UART_BASE=0x11000000 + CONFIG_DEBUG_UART_CLOCK=40000000 + CONFIG_SYS_LOAD_ADDR=0x50000000 + CONFIG_DEBUG_UART=y ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_SPI_BOOT=y ++CONFIG_SD_BOOT=y ++CONFIG_NAND_BOOT=y ++CONFIG_BOOTSTD_DEFAULTS=y ++CONFIG_BOOTSTD_FULL=y + # CONFIG_AUTOBOOT is not set + CONFIG_DEFAULT_FDT_FILE="mt7988-rfb" + CONFIG_LOGLEVEL=7 +@@ -22,15 +40,118 @@ CONFIG_SYS_PBSIZE=1049 + # CONFIG_BOOTM_PLAN9 is not set + # CONFIG_BOOTM_RTEMS is not set + # CONFIG_BOOTM_VXWORKS is not set +-# CONFIG_CMD_ELF is not set ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_ELF=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y + CONFIG_CMD_CLK=y + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_NAND=y ++CONFIG_CMD_NAND_TRIMFFS=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y + CONFIG_CMD_PWM=y + CONFIG_CMD_MMC=y + CONFIG_CMD_MTD=y + CONFIG_CMD_PING=y ++CONFIG_CMD_SF=y + CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_CMD_UBIFS=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_MMC=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_USB=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_NETCONSOLE=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_SCSI=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_PCI=y ++CONFIG_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y ++# CONFIG_MTD_RAW_NAND is not set ++CONFIG_DM_PCI=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PINCTRL_MT7988=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_USB=y ++CONFIG_USB_HOST=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_ENV_OFFSET=0x400000 ++CONFIG_ENV_OFFSET_REDUND=0x440000 ++CONFIG_ENV_SIZE=0x40000 ++CONFIG_ENV_SIZE_REDUND=0x40000 + CONFIG_DOS_PARTITION=y + CONFIG_EFI_PARTITION=y + CONFIG_PARTITION_TYPE_GUID=y +@@ -46,6 +167,9 @@ CONFIG_PROT_TCP=y + CONFIG_REGMAP=y + CONFIG_SYSCON=y + CONFIG_CLK=y ++CONFIG_MMC=y ++CONFIG_MMC_DEFAULT_DEV=1 ++CONFIG_MMC_SUPPORTS_TUNING=y + CONFIG_MMC_HS200_SUPPORT=y + CONFIG_MMC_MTK=y + CONFIG_MTD=y From 035a88ae5564ac680c64ed7219b8b66733ac84c6 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Fri, 25 Aug 2023 04:09:28 +0100 Subject: [PATCH 22/29] mediatek: generate bootloader artifacts for mt7988_rfb Switch to OpenWrt uImage.FIT bootmethod and include various bootloader artifacts with the generated binaries. Signed-off-by: Daniel Golle --- .../mediatek/mt7988a-dsa-10g-spim-nand.dts | 134 ------- .../boot/dts/mediatek/mt7988a-rfb-emmc.dtso | 33 ++ .../dts/mediatek/mt7988a-rfb-eth1-aqr.dtso | 41 +++ .../mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso | 30 ++ .../dts/mediatek/mt7988a-rfb-eth1-mxl.dtso | 39 +++ .../dts/mediatek/mt7988a-rfb-eth1-sfp.dtso | 47 +++ .../dts/mediatek/mt7988a-rfb-eth2-aqr.dtso | 41 +++ .../dts/mediatek/mt7988a-rfb-eth2-mxl.dtso | 39 +++ .../dts/mediatek/mt7988a-rfb-eth2-sfp.dtso | 47 +++ .../boot/dts/mediatek/mt7988a-rfb-sd.dtso | 31 ++ .../dts/mediatek/mt7988a-rfb-snfi-nand.dtso | 69 ++++ .../dts/mediatek/mt7988a-rfb-spim-nand.dtsi | 70 ---- .../dts/mediatek/mt7988a-rfb-spim-nand.dtso | 64 ++++ .../dts/mediatek/mt7988a-rfb-spim-nor.dtso | 59 ++++ .../arm64/boot/dts/mediatek/mt7988a-rfb.dts} | 117 ++++--- .../arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 330 +++++++++++++++++- .../mediatek/mt7988a-dsa-10g-spim-nand.dts | 134 ------- .../boot/dts/mediatek/mt7988a-rfb-emmc.dtso | 33 ++ .../dts/mediatek/mt7988a-rfb-eth1-aqr.dtso | 41 +++ .../mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso | 30 ++ .../dts/mediatek/mt7988a-rfb-eth1-mxl.dtso | 39 +++ .../dts/mediatek/mt7988a-rfb-eth1-sfp.dtso | 47 +++ .../dts/mediatek/mt7988a-rfb-eth2-aqr.dtso | 41 +++ .../dts/mediatek/mt7988a-rfb-eth2-mxl.dtso | 39 +++ .../dts/mediatek/mt7988a-rfb-eth2-sfp.dtso | 47 +++ .../boot/dts/mediatek/mt7988a-rfb-sd.dtso | 31 ++ .../dts/mediatek/mt7988a-rfb-snfi-nand.dtso | 69 ++++ .../dts/mediatek/mt7988a-rfb-spim-nand.dtsi | 70 ---- .../dts/mediatek/mt7988a-rfb-spim-nand.dtso | 64 ++++ .../dts/mediatek/mt7988a-rfb-spim-nor.dtso | 59 ++++ .../arm64/boot/dts/mediatek/mt7988a-rfb.dts} | 117 ++++--- .../arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 330 +++++++++++++++++- .../filogic/base-files/etc/board.d/02_network | 4 +- target/linux/mediatek/image/filogic.mk | 86 ++++- 34 files changed, 1921 insertions(+), 551 deletions(-) delete mode 100644 target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts create mode 100644 target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso create mode 100644 target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso create mode 100644 target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso create mode 100644 target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso create mode 100644 target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso create mode 100644 target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso create mode 100644 target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso create mode 100644 target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso create mode 100644 target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso create mode 100644 target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso delete mode 100644 target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtsi create mode 100644 target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso create mode 100644 target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nor.dtso rename target/linux/mediatek/{files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dtsi => files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts} (68%) delete mode 100644 target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts create mode 100644 target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso create mode 100644 target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso create mode 100644 target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso create mode 100644 target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso create mode 100644 target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso create mode 100644 target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso create mode 100644 target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso create mode 100644 target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso create mode 100644 target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso create mode 100644 target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso delete mode 100644 target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtsi create mode 100644 target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso create mode 100644 target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nor.dtso rename target/linux/mediatek/{files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dtsi => files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts} (68%) diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts deleted file mode 100644 index 27ef19c46dd..00000000000 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts +++ /dev/null @@ -1,134 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -#include "mt7988a-rfb-spim-nand.dtsi" -#include -#include - -/ { - model = "MediaTek MT7988A DSA 10G SPIM-NAND RFB"; - compatible = "mediatek,mt7988a-dsa-10g-spim-snand", - "mediatek,mt7988a-rfb-snand", - "mediatek,mt7988"; - - chosen { - bootargs = "console=ttyS0,115200n1 loglevel=8 \ - earlycon=uart8250,mmio32,0x11000000 \ - pci=pcie_bus_perf"; - }; - - memory { - reg = <0 0x40000000 0 0x40000000>; - }; -}; - -ð { - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&gmac0 { - status = "okay"; -}; - -&gmac1 { - status = "okay"; - phy-mode = "internal"; - phy-connection-type = "internal"; - phy = <&int_2p5g_phy>; -}; - -&gmac2 { - status = "okay"; - phy-mode = "usxgmii"; - phy-connection-type = "usxgmii"; - phy = <&phy8>; -}; - -&mdio_bus { - /* external Aquantia AQR113C */ - phy0: ethernet-phy@0 { - reg = <0>; - compatible = "ethernet-phy-ieee802.3-c45"; - reset-gpios = <&pio 72 1>; - reset-assert-us = <100000>; - reset-deassert-us = <221000>; - }; - - /* external Aquantia AQR113C */ - phy8: ethernet-phy@8 { - reg = <8>; - compatible = "ethernet-phy-ieee802.3-c45"; - reset-gpios = <&pio 71 1>; - reset-assert-us = <100000>; - reset-deassert-us = <221000>; - }; - - /* external Maxlinear GPY211C */ - phy5: ethernet-phy@5 { - reg = <5>; - compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "2500base-x"; - }; - - /* external Maxlinear GPY211C */ - phy13: ethernet-phy@13 { - reg = <13>; - compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "2500base-x"; - }; -}; - -&int_2p5g_phy { - pinctrl-names = "i2p5gbe-led"; - pinctrl-0 = <&i2p5gbe_led0_pins>; -}; - -&switch { - status = "okay"; -}; - -&gsw_phy0 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe0_led0_pins>; -}; - -&gsw_phy0_led0 { - status = "okay"; - color = ; -}; - -&gsw_phy1 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe1_led0_pins>; -}; - -&gsw_phy1_led0 { - status = "okay"; - color = ; -}; - -&gsw_phy2 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe2_led0_pins>; -}; - -&gsw_phy2_led0 { - status = "okay"; - color = ; -}; - -&gsw_phy3 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe3_led0_pins>; -}; - -&gsw_phy3_led0 { - status = "okay"; - color = ; -}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso new file mode 100644 index 00000000000..3f8ac2ae382 --- /dev/null +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Frank Wunderlich + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; + + fragment@0 { + target = <&mmc0>; + __overlay__ { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_emmc_51>; + pinctrl-1 = <&mmc0_pins_emmc_51>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + hs400-ds-delay = <0x12814>; + vqmmc-supply = <®_1p8v>; + vmmc-supply = <®_3p3v>; + non-removable; + no-sd; + no-sdio; + status = "okay"; + }; + }; +}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso new file mode 100644 index 00000000000..d21a61ad19f --- /dev/null +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +/plugin/; + +#include + +/ { + compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; + + fragment@0 { + target = <&mdio_bus>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* external Aquantia AQR113C */ + phy0: ethernet-phy@0 { + reg = <0>; + compatible = "ethernet-phy-ieee802.3-c45"; + reset-gpios = <&pio 72 GPIO_ACTIVE_LOW>; + reset-assert-us = <100000>; + reset-deassert-us = <221000>; + }; + }; + }; + + fragment@1 { + target = <&gmac1>; + __overlay__ { + phy-mode = "usxgmii"; + phy-connection-type = "usxgmii"; + phy = <&phy0>; + status = "okay"; + }; + }; +}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso new file mode 100644 index 00000000000..86ab7566dc2 --- /dev/null +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; + + fragment@0 { + target = <&gmac1>; + __overlay__ { + phy-mode = "internal"; + phy-connection-type = "internal"; + phy = <&int_2p5g_phy>; + status = "okay"; + }; + }; + + fragment@1 { + target = <&int_2p5g_phy>; + __overlay__ { + pinctrl-names = "i2p5gbe-led"; + pinctrl-0 = <&i2p5gbe_led0_pins>; + }; + }; +}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso new file mode 100644 index 00000000000..34a23bbd7eb --- /dev/null +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +/plugin/; + +#include + +/ { + compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; + + fragment@0 { + target = <&mdio_bus>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* external Maxlinear GPY211C */ + phy13: ethernet-phy@13 { + reg = <13>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "2500base-x"; + }; + }; + }; + + fragment@1 { + target = <&gmac1>; + __overlay__ { + phy-mode = "2500base-x"; + phy-connection-type = "2500base-x"; + phy = <&phy13>; + status = "okay"; + }; + }; +}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso new file mode 100644 index 00000000000..ba40a119cbd --- /dev/null +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +/plugin/; + +#include + +/ { + compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; + + fragment@0 { + target = <&i2c2>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_0_pins>; + status = "okay"; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + sfp_esp1: sfp@1 { + compatible = "sff,sfp"; + i2c-bus = <&i2c2>; + mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>; + los-gpios = <&pio 81 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&pio 36 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt = <3000>; + }; + }; + }; + + fragment@2 { + target = <&gmac1>; + __overlay__ { + phy-mode = "10gbase-r"; + managed = "in-band-status"; + sfp = <&sfp_esp1>; + status = "okay"; + }; + }; +}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso new file mode 100644 index 00000000000..140391fc45a --- /dev/null +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +/plugin/; + +#include + +/ { + compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; + + fragment@0 { + target = <&mdio_bus>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* external Aquantia AQR113C */ + phy8: ethernet-phy@8 { + reg = <8>; + compatible = "ethernet-phy-ieee802.3-c45"; + reset-gpios = <&pio 71 GPIO_ACTIVE_LOW>; + reset-assert-us = <100000>; + reset-deassert-us = <221000>; + }; + }; + }; + + fragment@1 { + target = <&gmac2>; + __overlay__ { + phy-mode = "usxgmii"; + phy-connection-type = "usxgmii"; + phy = <&phy8>; + status = "okay"; + }; + }; +}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso new file mode 100644 index 00000000000..19e0b2799fc --- /dev/null +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +/plugin/; + +#include + +/ { + compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; + + fragment@0 { + target = <&mdio_bus>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* external Maxlinear GPY211C */ + phy5: ethernet-phy@5 { + reg = <5>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "2500base-x"; + }; + }; + }; + + fragment@1 { + target = <&gmac2>; + __overlay__ { + phy-mode = "2500base-x"; + phy-connection-type = "2500base-x"; + phy = <&phy5>; + status = "okay"; + }; + }; +}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso new file mode 100644 index 00000000000..b9aabd2726e --- /dev/null +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +/plugin/; + +#include + +/ { + compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; + + fragment@0 { + target = <&i2c1>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_sfp_pins>; + status = "okay"; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + sfp_esp0: sfp@0 { + compatible = "sff,sfp"; + i2c-bus = <&i2c1>; + mod-def0-gpios = <&pio 35 GPIO_ACTIVE_LOW>; + los-gpios = <&pio 33 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&pio 29 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt = <3000>; + }; + }; + }; + + fragment@2 { + target = <&gmac2>; + __overlay__ { + phy-mode = "10gbase-r"; + managed = "in-band-status"; + sfp = <&sfp_esp0>; + status = "okay"; + }; + }; +}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso new file mode 100644 index 00000000000..04472cc12dc --- /dev/null +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 MediaTek Inc. + * Author: Frank Wunderlich + */ + +/dts-v1/; +/plugin/; + +#include + +/ { + compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; + + fragment@1 { + target-path = <&mmc0>; + __overlay__ { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_sdcard>; + pinctrl-1 = <&mmc0_pins_sdcard>; + cd-gpios = <&pio 69 GPIO_ACTIVE_LOW>; + bus-width = <4>; + max-frequency = <52000000>; + cap-sd-highspeed; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + no-mmc; + status = "okay"; + }; + }; +}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso new file mode 100644 index 00000000000..61801651778 --- /dev/null +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; + + fragment@0 { + target = <&snand>; + __overlay__ { + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-tx-buswidth = <4>; + spi-rx-buswidth = <4>; + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <64>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "BL2"; + reg = <0x00000 0x0100000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env"; + reg = <0x0100000 0x0080000>; + }; + + partition@180000 { + label = "Factory"; + reg = <0x180000 0x0400000>; + }; + + partition@580000 { + label = "FIP"; + reg = <0x580000 0x0200000>; + }; + + partition@780000 { + label = "ubi"; + reg = <0x780000 0x7080000>; + }; + }; + }; + }; + }; + + fragment@1 { + target = <&bch>; + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtsi deleted file mode 100644 index e4c05712509..00000000000 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtsi +++ /dev/null @@ -1,70 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -#include "mt7988a-rfb.dtsi" - -&pio { - spi0_flash_pins: spi0-pins { - mux { - function = "spi"; - groups = "spi0", "spi0_wp_hold"; - }; - }; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_flash_pins>; - status = "okay"; - - spi_nand: spi_nand@0 { - compatible = "spi-nand"; - reg = <0>; - spi-max-frequency = <52000000>; - spi-tx-buswidth = <4>; - spi-rx-buswidth = <4>; - }; - -}; - -&spi_nand { - mediatek,nmbm; - mediatek,bmt-max-ratio = <1>; - mediatek,bmt-max-reserved-blocks = <64>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "BL2"; - reg = <0x00000 0x0100000>; - read-only; - }; - - partition@100000 { - label = "u-boot-env"; - reg = <0x0100000 0x0080000>; - }; - - factory: partition@180000 { - label = "Factory"; - reg = <0x180000 0x0400000>; - }; - - partition@580000 { - label = "FIP"; - reg = <0x580000 0x0200000>; - }; - - partition@780000 { - label = "ubi"; - reg = <0x780000 0x7080000>; - }; - }; -}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso new file mode 100644 index 00000000000..e63436fa556 --- /dev/null +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; + + fragment@0 { + target = <&spi0>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-tx-buswidth = <4>; + spi-rx-buswidth = <4>; + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <64>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "BL2"; + reg = <0x00000 0x0100000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env"; + reg = <0x0100000 0x0080000>; + }; + + partition@180000 { + label = "Factory"; + reg = <0x180000 0x0400000>; + }; + + partition@580000 { + label = "FIP"; + reg = <0x580000 0x0200000>; + }; + + partition@780000 { + label = "ubi"; + reg = <0x780000 0x7080000>; + }; + }; + }; + }; + }; +}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nor.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nor.dtso new file mode 100644 index 00000000000..33bd57b3fb6 --- /dev/null +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nor.dtso @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; + + fragment@0 { + target = <&spi2>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_flash_pins>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-cal-enable; + spi-cal-mode = "read-data"; + spi-cal-datalen = <7>; + spi-cal-data = /bits/ 8 < + 0x53 0x46 0x5F 0x42 0x4F 0x4F 0x54>; /* SF_BOOT */ + spi-cal-addrlen = <1>; + spi-cal-addr = /bits/ 32 <0x0>; + reg = <0>; + spi-max-frequency = <52000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + partition@00000 { + label = "BL2"; + reg = <0x00000 0x0040000>; + }; + partition@40000 { + label = "u-boot-env"; + reg = <0x40000 0x0010000>; + }; + partition@50000 { + label = "Factory"; + reg = <0x50000 0x0200000>; + }; + partition@250000 { + label = "FIP"; + reg = <0x250000 0x0080000>; + }; + partition@2D0000 { + label = "firmware"; + reg = <0x2D0000 0x1D30000>; + }; + }; + }; + }; +}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts similarity index 68% rename from target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dtsi rename to target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts index 423b3860c6c..11dbf98301e 100644 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dtsi +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts @@ -6,8 +6,35 @@ /dts-v1/; #include "mt7988a.dtsi" +#include +#include #include +/ { + model = "MediaTek MT7988A Reference Board"; + compatible = "mediatek,mt7988a-rfb", + "mediatek,mt7988"; + + chosen { + bootargs = "console=ttyS0,115200n1 loglevel=8 \ + earlycon=uart8250,mmio32,0x11000000 \ + pci=pcie_bus_perf"; + }; + + memory { + reg = <0 0x40000000 0 0x40000000>; + }; +}; + +ð { + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; +}; + +&gmac0 { + status = "okay"; +}; + &cpu0 { proc-supply = <&rt5190_buck3>; }; @@ -32,6 +59,50 @@ status = "okay"; }; +&switch { + status = "okay"; +}; + +&gsw_phy0 { + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe0_led0_pins>; +}; + +&gsw_phy0_led0 { + status = "okay"; + color = ; +}; + +&gsw_phy1 { + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe1_led0_pins>; +}; + +&gsw_phy1_led0 { + status = "okay"; + color = ; +}; + +&gsw_phy2 { + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe2_led0_pins>; +}; + +&gsw_phy2_led0 { + status = "okay"; + color = ; +}; + +&gsw_phy3 { + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe3_led0_pins>; +}; + +&gsw_phy3_led0 { + status = "okay"; + color = ; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; @@ -89,26 +160,18 @@ }; &pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_pins>; status = "okay"; }; &pcie1 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie1_pins>; status = "okay"; }; &pcie2 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_pins>; status = "disabled"; }; &pcie3 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie3_pins>; status = "okay"; }; @@ -124,44 +187,6 @@ status = "okay"; }; -&pio { - pcie0_pins: pcie0-pins { - mux { - function = "pcie"; - groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", - "pcie_wake_n0_0"; - }; - }; - - pcie1_pins: pcie1-pins { - mux { - function = "pcie"; - groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", - "pcie_wake_n1_0"; - }; - }; - - pcie2_pins: pcie2-pins { - mux { - function = "pcie"; - groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", - "pcie_wake_n2_0"; - }; - }; - - pcie3_pins: pcie3-pins { - mux { - function = "pcie"; - groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", - "pcie_wake_n3_0"; - }; - }; -}; - -&spi0 { - status = "disabled"; -}; - &uart0 { status = "okay"; }; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 462218c65d4..7fed1e13843 100644 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -152,6 +152,65 @@ }; }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + thermal-sensors = <&lvts 0>; + trips { + cpu_trip_crit: crit { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu_trip_hot: hot { + temperature = <120000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_trip_active_high: active-high { + temperature = <115000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_med: active-med { + temperature = <85000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_low: active-low { + temperature = <40000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + cpu-active-high { + /* active: set fan to cooling level 2 */ + cooling-device = <&fan 3 3>; + trip = <&cpu_trip_active_high>; + }; + + cpu-active-low { + /* active: set fan to cooling level 1 */ + cooling-device = <&fan 2 2>; + trip = <&cpu_trip_active_med>; + }; + + cpu-passive { + /* passive: set fan to cooling level 0 */ + cooling-device = <&fan 1 1>; + trip = <&cpu_trip_active_low>; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; @@ -161,6 +220,24 @@ ; }; + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + soc { #address-cells = <2>; #size-cells = <2>; @@ -386,6 +463,80 @@ groups = "uart0"; }; }; + + snfi_pins: snfi-pins { + mux { + function = "flash"; + groups = "snfi"; + }; + }; + + spi0_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0"; + }; + }; + + spi0_flash_pins: spi0-flash-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + + spi1_pins: spi1-pins { + mux { + function = "spi"; + groups = "spi1"; + }; + }; + + spi2_pins: spi2-pins { + mux { + function = "spi"; + groups = "spi2"; + }; + }; + + spi2_flash_pins: spi2-flash-pins { + mux { + function = "spi"; + groups = "spi2", "spi2_wp_hold"; + }; + }; + + pcie0_pins: pcie0-pins { + mux { + function = "pcie"; + groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", + "pcie_wake_n0_0"; + }; + }; + + pcie1_pins: pcie1-pins { + mux { + function = "pcie"; + groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", + "pcie_wake_n1_0"; + }; + }; + + pcie2_pins: pcie2-pins { + mux { + function = "pcie"; + groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", + "pcie_wake_n2_0"; + }; + }; + + pcie3_pins: pcie3-pins { + mux { + function = "pcie"; + groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", + "pcie_wake_n3_0"; + }; + }; }; sgmiisys0: syscon@10060000 { @@ -420,24 +571,24 @@ #clock-cells = <1>; }; - xfi_pextp0: xfi_pextp@11f20000 { - compatible = "mediatek,mt7988-xfi_pextp", - "mediatek,mt7988-xfi_pextp_0", + xfi_pextp0: xfi-pextp@11f20000 { + compatible = "mediatek,mt7988-xfi-pextp", + "mediatek,mt7988-xfi-pextp_0", "syscon"; reg = <0 0x11f20000 0 0x10000>; #clock-cells = <1>; }; - xfi_pextp1: xfi_pextp@11f30000 { - compatible = "mediatek,mt7988-xfi_pextp", - "mediatek,mt7988-xfi_pextp_1", + xfi_pextp1: xfi-pextp@11f30000 { + compatible = "mediatek,mt7988-xfi-pextp", + "mediatek,mt7988-xfi-pextp_1", "syscon"; reg = <0 0x11f30000 0 0x10000>; #clock-cells = <1>; }; - xfi_pll: xfi_pll@11f40000 { - compatible = "mediatek,mt7988-xfi_pll", "syscon"; + xfi_pll: xfi-pll@11f40000 { + compatible = "mediatek,mt7988-xfi-pll", "syscon"; reg = <0 0x11f40000 0 0x1000>; #clock-cells = <1>; }; @@ -470,6 +621,35 @@ status = "disabled"; }; + snand: spi@11001000 { + compatible = "mediatek,mt7986-snand"; + reg = <0 0x11001000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_SPINFI>, + <&infracfg CLK_INFRA_NFI>; + clock-names = "pad_clk", "nfi_clk"; + assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>, + <&topckgen CLK_TOP_NFI1X_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>, + <&topckgen CLK_TOP_MPLL_D8>; + nand-ecc-engine = <&bch>; + mediatek,quad-spi; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&snfi_pins>; + status = "disabled"; + }; + + bch: ecc@11002000 { + compatible = "mediatek,mt7686-ecc"; + reg = <0 0x11002000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_NFI1X_SEL>; + clock-names = "nfiecc_clk"; + status = "disabled"; + }; + i2c0: i2c@11003000 { compatible = "mediatek,mt7988-i2c", "mediatek,mt7981-i2c"; @@ -525,10 +705,118 @@ <&infracfg CLK_INFRA_66M_SPI0_HCK>; clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk"; - #address-cells = <1>; #size-cells = <0>; + status = "disabled"; + }; + spi1: spi@11008000 { + compatible = "mediatek,ipm-spi-single", "mediatek,spi-ipm"; + reg = <0 0x11008000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MPLL_D2>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_104M_SPI1>, + <&infracfg CLK_INFRA_66M_SPI1_HCK>; + clock-names = "parent-clk", "sel-clk", "spi-clk", + "spi-hclk"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + status = "disabled"; + }; + + spi2: spi@11009000 { + compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm"; + reg = <0 0x11009000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MPLL_D2>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_104M_SPI2_BCK>, + <&infracfg CLK_INFRA_66M_SPI2_HCK>; + clock-names = "parent-clk", "sel-clk", "spi-clk", + "spi-hclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pwm: pwm@10048000 { + compatible = "mediatek,mt7988-pwm"; + reg = <0 0x10048000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>, + <&infracfg CLK_INFRA_66M_PWM_HCK>, + <&infracfg CLK_INFRA_66M_PWM_CK1>, + <&infracfg CLK_INFRA_66M_PWM_CK2>, + <&infracfg CLK_INFRA_66M_PWM_CK3>, + <&infracfg CLK_INFRA_66M_PWM_CK4>, + <&infracfg CLK_INFRA_66M_PWM_CK5>, + <&infracfg CLK_INFRA_66M_PWM_CK6>, + <&infracfg CLK_INFRA_66M_PWM_CK7>, + <&infracfg CLK_INFRA_66M_PWM_CK8>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3", + "pwm4","pwm5","pwm6","pwm7","pwm8"; + status = "disabled"; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + /* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */ + cooling-levels = <0 128 255>; + #cooling-cells = <2>; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + + lvts: lvts@1100a000 { + compatible = "mediatek,mt7988-lvts"; + #thermal-sensor-cells = <1>; + reg = <0 0x1100a000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>; + clock-names = "lvts_clk"; + nvmem-cells = <&lvts_calibration>; + nvmem-cell-names = "e_data1"; + }; + + crypto: crypto@15600000 { + compatible = "inside-secure,safexcel-eip197b"; + reg = <0 0x15600000 0 0x180000>; + interrupts = , + , + , + ; + interrupt-names = "ring0", "ring1", "ring2", "ring3"; + status = "okay"; + }; + + afe: audio-controller@11210000 { + compatible = "mediatek,mt79xx-audio"; + reg = <0 0x11210000 0 0x9000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>, + <&infracfg CLK_INFRA_AUD_26M>, + <&infracfg CLK_INFRA_AUD_L>, + <&infracfg CLK_INFRA_AUD_AUD>, + <&infracfg CLK_INFRA_AUD_EG2>, + <&topckgen CLK_TOP_AUD_SEL>, + <&topckgen CLK_TOP_AUD_I2S_M>; + clock-names = "aud_bus_ck", + "aud_26m_ck", + "aud_l_ck", + "aud_aud_ck", + "aud_eg2_ck", + "aud_sel", + "aud_i2s_m"; + assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>, + <&topckgen CLK_TOP_A1SYS_SEL>, + <&topckgen CLK_TOP_AUD_L_SEL>, + <&topckgen CLK_TOP_A_TUNER_SEL>; + assigned-clock-parents = <&apmixedsys CLK_APMIXED_APLL2>, + <&topckgen CLK_TOP_APLL2_D4>, + <&apmixedsys CLK_APMIXED_APLL2>, + <&topckgen CLK_TOP_APLL2_D4>; status = "disabled"; }; @@ -554,6 +842,8 @@ <&infracfg CLK_INFRA_133M_PCIE_CK_P2>; clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_pins>; status = "disabled"; phys = <&xphyu3port0 PHY_TYPE_PCIE>; @@ -594,6 +884,8 @@ <&infracfg CLK_INFRA_133M_PCIE_CK_P3>; clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_pins>; status = "disabled"; #interrupt-cells = <1>; @@ -631,6 +923,8 @@ <&infracfg CLK_INFRA_133M_PCIE_CK_P0>; clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>; status = "disabled"; #interrupt-cells = <1>; @@ -668,6 +962,8 @@ <&infracfg CLK_INFRA_133M_PCIE_CK_P1>; clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins>; status = "disabled"; #interrupt-cells = <1>; @@ -909,7 +1205,7 @@ mediatek,pio = <&pio>; gsw_phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id03a2.9481"; + compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; phy-mode = "internal"; nvmem-cells = <&phy_calibration_p0>; @@ -934,7 +1230,7 @@ }; gsw_phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id03a2.9481"; + compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; phy-mode = "internal"; nvmem-cells = <&phy_calibration_p1>; @@ -959,7 +1255,7 @@ }; gsw_phy2: ethernet-phy@2 { - compatible = "ethernet-phy-id03a2.9481"; + compatible = "ethernet-phy-ieee802.3-c22"; reg = <2>; phy-mode = "internal"; nvmem-cells = <&phy_calibration_p2>; @@ -984,7 +1280,7 @@ }; gsw_phy3: ethernet-phy@3 { - compatible = "ethernet-phy-id03a2.9481"; + compatible = "ethernet-phy-ieee802.3-c22"; reg = <3>; phy-mode = "internal"; nvmem-cells = <&phy_calibration_p3>; @@ -1096,19 +1392,19 @@ mediatek,ethsys = <ðsys>; mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>; - mediatek,xfi_pextp = <&xfi_pextp0>, <&xfi_pextp1>; - mediatek,xfi_pll = <&xfi_pll>; + mediatek,xfi-pextp = <&xfi_pextp0>, <&xfi_pextp1>; + mediatek,xfi-pll = <&xfi_pll>; mediatek,infracfg = <&topmisc>; mediatek,toprgu = <&watchdog>; #reset-cells = <1>; #address-cells = <1>; #size-cells = <0>; - status = "disabled"; gmac0: mac@0 { compatible = "mediatek,eth-mac"; reg = <0>; phy-mode = "internal"; + status = "disabled"; fixed-link { speed = <10000>; @@ -1120,11 +1416,13 @@ gmac1: mac@1 { compatible = "mediatek,eth-mac"; reg = <1>; + status = "disabled"; }; gmac2: mac@2 { compatible = "mediatek,eth-mac"; reg = <2>; + status = "disabled"; }; mdio_bus: mdio-bus { diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts deleted file mode 100644 index 27ef19c46dd..00000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts +++ /dev/null @@ -1,134 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -#include "mt7988a-rfb-spim-nand.dtsi" -#include -#include - -/ { - model = "MediaTek MT7988A DSA 10G SPIM-NAND RFB"; - compatible = "mediatek,mt7988a-dsa-10g-spim-snand", - "mediatek,mt7988a-rfb-snand", - "mediatek,mt7988"; - - chosen { - bootargs = "console=ttyS0,115200n1 loglevel=8 \ - earlycon=uart8250,mmio32,0x11000000 \ - pci=pcie_bus_perf"; - }; - - memory { - reg = <0 0x40000000 0 0x40000000>; - }; -}; - -ð { - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&gmac0 { - status = "okay"; -}; - -&gmac1 { - status = "okay"; - phy-mode = "internal"; - phy-connection-type = "internal"; - phy = <&int_2p5g_phy>; -}; - -&gmac2 { - status = "okay"; - phy-mode = "usxgmii"; - phy-connection-type = "usxgmii"; - phy = <&phy8>; -}; - -&mdio_bus { - /* external Aquantia AQR113C */ - phy0: ethernet-phy@0 { - reg = <0>; - compatible = "ethernet-phy-ieee802.3-c45"; - reset-gpios = <&pio 72 1>; - reset-assert-us = <100000>; - reset-deassert-us = <221000>; - }; - - /* external Aquantia AQR113C */ - phy8: ethernet-phy@8 { - reg = <8>; - compatible = "ethernet-phy-ieee802.3-c45"; - reset-gpios = <&pio 71 1>; - reset-assert-us = <100000>; - reset-deassert-us = <221000>; - }; - - /* external Maxlinear GPY211C */ - phy5: ethernet-phy@5 { - reg = <5>; - compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "2500base-x"; - }; - - /* external Maxlinear GPY211C */ - phy13: ethernet-phy@13 { - reg = <13>; - compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "2500base-x"; - }; -}; - -&int_2p5g_phy { - pinctrl-names = "i2p5gbe-led"; - pinctrl-0 = <&i2p5gbe_led0_pins>; -}; - -&switch { - status = "okay"; -}; - -&gsw_phy0 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe0_led0_pins>; -}; - -&gsw_phy0_led0 { - status = "okay"; - color = ; -}; - -&gsw_phy1 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe1_led0_pins>; -}; - -&gsw_phy1_led0 { - status = "okay"; - color = ; -}; - -&gsw_phy2 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe2_led0_pins>; -}; - -&gsw_phy2_led0 { - status = "okay"; - color = ; -}; - -&gsw_phy3 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe3_led0_pins>; -}; - -&gsw_phy3_led0 { - status = "okay"; - color = ; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso new file mode 100644 index 00000000000..3f8ac2ae382 --- /dev/null +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Frank Wunderlich + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; + + fragment@0 { + target = <&mmc0>; + __overlay__ { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_emmc_51>; + pinctrl-1 = <&mmc0_pins_emmc_51>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + hs400-ds-delay = <0x12814>; + vqmmc-supply = <®_1p8v>; + vmmc-supply = <®_3p3v>; + non-removable; + no-sd; + no-sdio; + status = "okay"; + }; + }; +}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso new file mode 100644 index 00000000000..d21a61ad19f --- /dev/null +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +/plugin/; + +#include + +/ { + compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; + + fragment@0 { + target = <&mdio_bus>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* external Aquantia AQR113C */ + phy0: ethernet-phy@0 { + reg = <0>; + compatible = "ethernet-phy-ieee802.3-c45"; + reset-gpios = <&pio 72 GPIO_ACTIVE_LOW>; + reset-assert-us = <100000>; + reset-deassert-us = <221000>; + }; + }; + }; + + fragment@1 { + target = <&gmac1>; + __overlay__ { + phy-mode = "usxgmii"; + phy-connection-type = "usxgmii"; + phy = <&phy0>; + status = "okay"; + }; + }; +}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso new file mode 100644 index 00000000000..86ab7566dc2 --- /dev/null +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; + + fragment@0 { + target = <&gmac1>; + __overlay__ { + phy-mode = "internal"; + phy-connection-type = "internal"; + phy = <&int_2p5g_phy>; + status = "okay"; + }; + }; + + fragment@1 { + target = <&int_2p5g_phy>; + __overlay__ { + pinctrl-names = "i2p5gbe-led"; + pinctrl-0 = <&i2p5gbe_led0_pins>; + }; + }; +}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso new file mode 100644 index 00000000000..34a23bbd7eb --- /dev/null +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +/plugin/; + +#include + +/ { + compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; + + fragment@0 { + target = <&mdio_bus>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* external Maxlinear GPY211C */ + phy13: ethernet-phy@13 { + reg = <13>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "2500base-x"; + }; + }; + }; + + fragment@1 { + target = <&gmac1>; + __overlay__ { + phy-mode = "2500base-x"; + phy-connection-type = "2500base-x"; + phy = <&phy13>; + status = "okay"; + }; + }; +}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso new file mode 100644 index 00000000000..ba40a119cbd --- /dev/null +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +/plugin/; + +#include + +/ { + compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; + + fragment@0 { + target = <&i2c2>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_0_pins>; + status = "okay"; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + sfp_esp1: sfp@1 { + compatible = "sff,sfp"; + i2c-bus = <&i2c2>; + mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>; + los-gpios = <&pio 81 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&pio 36 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt = <3000>; + }; + }; + }; + + fragment@2 { + target = <&gmac1>; + __overlay__ { + phy-mode = "10gbase-r"; + managed = "in-band-status"; + sfp = <&sfp_esp1>; + status = "okay"; + }; + }; +}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso new file mode 100644 index 00000000000..140391fc45a --- /dev/null +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +/plugin/; + +#include + +/ { + compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; + + fragment@0 { + target = <&mdio_bus>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* external Aquantia AQR113C */ + phy8: ethernet-phy@8 { + reg = <8>; + compatible = "ethernet-phy-ieee802.3-c45"; + reset-gpios = <&pio 71 GPIO_ACTIVE_LOW>; + reset-assert-us = <100000>; + reset-deassert-us = <221000>; + }; + }; + }; + + fragment@1 { + target = <&gmac2>; + __overlay__ { + phy-mode = "usxgmii"; + phy-connection-type = "usxgmii"; + phy = <&phy8>; + status = "okay"; + }; + }; +}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso new file mode 100644 index 00000000000..19e0b2799fc --- /dev/null +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +/plugin/; + +#include + +/ { + compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; + + fragment@0 { + target = <&mdio_bus>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* external Maxlinear GPY211C */ + phy5: ethernet-phy@5 { + reg = <5>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "2500base-x"; + }; + }; + }; + + fragment@1 { + target = <&gmac2>; + __overlay__ { + phy-mode = "2500base-x"; + phy-connection-type = "2500base-x"; + phy = <&phy5>; + status = "okay"; + }; + }; +}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso new file mode 100644 index 00000000000..b9aabd2726e --- /dev/null +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +/plugin/; + +#include + +/ { + compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; + + fragment@0 { + target = <&i2c1>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_sfp_pins>; + status = "okay"; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + sfp_esp0: sfp@0 { + compatible = "sff,sfp"; + i2c-bus = <&i2c1>; + mod-def0-gpios = <&pio 35 GPIO_ACTIVE_LOW>; + los-gpios = <&pio 33 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&pio 29 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt = <3000>; + }; + }; + }; + + fragment@2 { + target = <&gmac2>; + __overlay__ { + phy-mode = "10gbase-r"; + managed = "in-band-status"; + sfp = <&sfp_esp0>; + status = "okay"; + }; + }; +}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso new file mode 100644 index 00000000000..04472cc12dc --- /dev/null +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 MediaTek Inc. + * Author: Frank Wunderlich + */ + +/dts-v1/; +/plugin/; + +#include + +/ { + compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; + + fragment@1 { + target-path = <&mmc0>; + __overlay__ { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_sdcard>; + pinctrl-1 = <&mmc0_pins_sdcard>; + cd-gpios = <&pio 69 GPIO_ACTIVE_LOW>; + bus-width = <4>; + max-frequency = <52000000>; + cap-sd-highspeed; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + no-mmc; + status = "okay"; + }; + }; +}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso new file mode 100644 index 00000000000..61801651778 --- /dev/null +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; + + fragment@0 { + target = <&snand>; + __overlay__ { + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-tx-buswidth = <4>; + spi-rx-buswidth = <4>; + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <64>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "BL2"; + reg = <0x00000 0x0100000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env"; + reg = <0x0100000 0x0080000>; + }; + + partition@180000 { + label = "Factory"; + reg = <0x180000 0x0400000>; + }; + + partition@580000 { + label = "FIP"; + reg = <0x580000 0x0200000>; + }; + + partition@780000 { + label = "ubi"; + reg = <0x780000 0x7080000>; + }; + }; + }; + }; + }; + + fragment@1 { + target = <&bch>; + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtsi b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtsi deleted file mode 100644 index e4c05712509..00000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtsi +++ /dev/null @@ -1,70 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -#include "mt7988a-rfb.dtsi" - -&pio { - spi0_flash_pins: spi0-pins { - mux { - function = "spi"; - groups = "spi0", "spi0_wp_hold"; - }; - }; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_flash_pins>; - status = "okay"; - - spi_nand: spi_nand@0 { - compatible = "spi-nand"; - reg = <0>; - spi-max-frequency = <52000000>; - spi-tx-buswidth = <4>; - spi-rx-buswidth = <4>; - }; - -}; - -&spi_nand { - mediatek,nmbm; - mediatek,bmt-max-ratio = <1>; - mediatek,bmt-max-reserved-blocks = <64>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "BL2"; - reg = <0x00000 0x0100000>; - read-only; - }; - - partition@100000 { - label = "u-boot-env"; - reg = <0x0100000 0x0080000>; - }; - - factory: partition@180000 { - label = "Factory"; - reg = <0x180000 0x0400000>; - }; - - partition@580000 { - label = "FIP"; - reg = <0x580000 0x0200000>; - }; - - partition@780000 { - label = "ubi"; - reg = <0x780000 0x7080000>; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso new file mode 100644 index 00000000000..e63436fa556 --- /dev/null +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; + + fragment@0 { + target = <&spi0>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-tx-buswidth = <4>; + spi-rx-buswidth = <4>; + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <64>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "BL2"; + reg = <0x00000 0x0100000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env"; + reg = <0x0100000 0x0080000>; + }; + + partition@180000 { + label = "Factory"; + reg = <0x180000 0x0400000>; + }; + + partition@580000 { + label = "FIP"; + reg = <0x580000 0x0200000>; + }; + + partition@780000 { + label = "ubi"; + reg = <0x780000 0x7080000>; + }; + }; + }; + }; + }; +}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nor.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nor.dtso new file mode 100644 index 00000000000..33bd57b3fb6 --- /dev/null +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nor.dtso @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; + + fragment@0 { + target = <&spi2>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_flash_pins>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-cal-enable; + spi-cal-mode = "read-data"; + spi-cal-datalen = <7>; + spi-cal-data = /bits/ 8 < + 0x53 0x46 0x5F 0x42 0x4F 0x4F 0x54>; /* SF_BOOT */ + spi-cal-addrlen = <1>; + spi-cal-addr = /bits/ 32 <0x0>; + reg = <0>; + spi-max-frequency = <52000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + partition@00000 { + label = "BL2"; + reg = <0x00000 0x0040000>; + }; + partition@40000 { + label = "u-boot-env"; + reg = <0x40000 0x0010000>; + }; + partition@50000 { + label = "Factory"; + reg = <0x50000 0x0200000>; + }; + partition@250000 { + label = "FIP"; + reg = <0x250000 0x0080000>; + }; + partition@2D0000 { + label = "firmware"; + reg = <0x2D0000 0x1D30000>; + }; + }; + }; + }; +}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dtsi b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts similarity index 68% rename from target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dtsi rename to target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts index 423b3860c6c..11dbf98301e 100644 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dtsi +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts @@ -6,8 +6,35 @@ /dts-v1/; #include "mt7988a.dtsi" +#include +#include #include +/ { + model = "MediaTek MT7988A Reference Board"; + compatible = "mediatek,mt7988a-rfb", + "mediatek,mt7988"; + + chosen { + bootargs = "console=ttyS0,115200n1 loglevel=8 \ + earlycon=uart8250,mmio32,0x11000000 \ + pci=pcie_bus_perf"; + }; + + memory { + reg = <0 0x40000000 0 0x40000000>; + }; +}; + +ð { + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; +}; + +&gmac0 { + status = "okay"; +}; + &cpu0 { proc-supply = <&rt5190_buck3>; }; @@ -32,6 +59,50 @@ status = "okay"; }; +&switch { + status = "okay"; +}; + +&gsw_phy0 { + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe0_led0_pins>; +}; + +&gsw_phy0_led0 { + status = "okay"; + color = ; +}; + +&gsw_phy1 { + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe1_led0_pins>; +}; + +&gsw_phy1_led0 { + status = "okay"; + color = ; +}; + +&gsw_phy2 { + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe2_led0_pins>; +}; + +&gsw_phy2_led0 { + status = "okay"; + color = ; +}; + +&gsw_phy3 { + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe3_led0_pins>; +}; + +&gsw_phy3_led0 { + status = "okay"; + color = ; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; @@ -89,26 +160,18 @@ }; &pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_pins>; status = "okay"; }; &pcie1 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie1_pins>; status = "okay"; }; &pcie2 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_pins>; status = "disabled"; }; &pcie3 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie3_pins>; status = "okay"; }; @@ -124,44 +187,6 @@ status = "okay"; }; -&pio { - pcie0_pins: pcie0-pins { - mux { - function = "pcie"; - groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", - "pcie_wake_n0_0"; - }; - }; - - pcie1_pins: pcie1-pins { - mux { - function = "pcie"; - groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", - "pcie_wake_n1_0"; - }; - }; - - pcie2_pins: pcie2-pins { - mux { - function = "pcie"; - groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", - "pcie_wake_n2_0"; - }; - }; - - pcie3_pins: pcie3-pins { - mux { - function = "pcie"; - groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", - "pcie_wake_n3_0"; - }; - }; -}; - -&spi0 { - status = "disabled"; -}; - &uart0 { status = "okay"; }; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 462218c65d4..7fed1e13843 100644 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -152,6 +152,65 @@ }; }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + thermal-sensors = <&lvts 0>; + trips { + cpu_trip_crit: crit { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu_trip_hot: hot { + temperature = <120000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_trip_active_high: active-high { + temperature = <115000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_med: active-med { + temperature = <85000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_low: active-low { + temperature = <40000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + cpu-active-high { + /* active: set fan to cooling level 2 */ + cooling-device = <&fan 3 3>; + trip = <&cpu_trip_active_high>; + }; + + cpu-active-low { + /* active: set fan to cooling level 1 */ + cooling-device = <&fan 2 2>; + trip = <&cpu_trip_active_med>; + }; + + cpu-passive { + /* passive: set fan to cooling level 0 */ + cooling-device = <&fan 1 1>; + trip = <&cpu_trip_active_low>; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; @@ -161,6 +220,24 @@ ; }; + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + soc { #address-cells = <2>; #size-cells = <2>; @@ -386,6 +463,80 @@ groups = "uart0"; }; }; + + snfi_pins: snfi-pins { + mux { + function = "flash"; + groups = "snfi"; + }; + }; + + spi0_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0"; + }; + }; + + spi0_flash_pins: spi0-flash-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + + spi1_pins: spi1-pins { + mux { + function = "spi"; + groups = "spi1"; + }; + }; + + spi2_pins: spi2-pins { + mux { + function = "spi"; + groups = "spi2"; + }; + }; + + spi2_flash_pins: spi2-flash-pins { + mux { + function = "spi"; + groups = "spi2", "spi2_wp_hold"; + }; + }; + + pcie0_pins: pcie0-pins { + mux { + function = "pcie"; + groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", + "pcie_wake_n0_0"; + }; + }; + + pcie1_pins: pcie1-pins { + mux { + function = "pcie"; + groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", + "pcie_wake_n1_0"; + }; + }; + + pcie2_pins: pcie2-pins { + mux { + function = "pcie"; + groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", + "pcie_wake_n2_0"; + }; + }; + + pcie3_pins: pcie3-pins { + mux { + function = "pcie"; + groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", + "pcie_wake_n3_0"; + }; + }; }; sgmiisys0: syscon@10060000 { @@ -420,24 +571,24 @@ #clock-cells = <1>; }; - xfi_pextp0: xfi_pextp@11f20000 { - compatible = "mediatek,mt7988-xfi_pextp", - "mediatek,mt7988-xfi_pextp_0", + xfi_pextp0: xfi-pextp@11f20000 { + compatible = "mediatek,mt7988-xfi-pextp", + "mediatek,mt7988-xfi-pextp_0", "syscon"; reg = <0 0x11f20000 0 0x10000>; #clock-cells = <1>; }; - xfi_pextp1: xfi_pextp@11f30000 { - compatible = "mediatek,mt7988-xfi_pextp", - "mediatek,mt7988-xfi_pextp_1", + xfi_pextp1: xfi-pextp@11f30000 { + compatible = "mediatek,mt7988-xfi-pextp", + "mediatek,mt7988-xfi-pextp_1", "syscon"; reg = <0 0x11f30000 0 0x10000>; #clock-cells = <1>; }; - xfi_pll: xfi_pll@11f40000 { - compatible = "mediatek,mt7988-xfi_pll", "syscon"; + xfi_pll: xfi-pll@11f40000 { + compatible = "mediatek,mt7988-xfi-pll", "syscon"; reg = <0 0x11f40000 0 0x1000>; #clock-cells = <1>; }; @@ -470,6 +621,35 @@ status = "disabled"; }; + snand: spi@11001000 { + compatible = "mediatek,mt7986-snand"; + reg = <0 0x11001000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_SPINFI>, + <&infracfg CLK_INFRA_NFI>; + clock-names = "pad_clk", "nfi_clk"; + assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>, + <&topckgen CLK_TOP_NFI1X_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>, + <&topckgen CLK_TOP_MPLL_D8>; + nand-ecc-engine = <&bch>; + mediatek,quad-spi; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&snfi_pins>; + status = "disabled"; + }; + + bch: ecc@11002000 { + compatible = "mediatek,mt7686-ecc"; + reg = <0 0x11002000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_NFI1X_SEL>; + clock-names = "nfiecc_clk"; + status = "disabled"; + }; + i2c0: i2c@11003000 { compatible = "mediatek,mt7988-i2c", "mediatek,mt7981-i2c"; @@ -525,10 +705,118 @@ <&infracfg CLK_INFRA_66M_SPI0_HCK>; clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk"; - #address-cells = <1>; #size-cells = <0>; + status = "disabled"; + }; + spi1: spi@11008000 { + compatible = "mediatek,ipm-spi-single", "mediatek,spi-ipm"; + reg = <0 0x11008000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MPLL_D2>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_104M_SPI1>, + <&infracfg CLK_INFRA_66M_SPI1_HCK>; + clock-names = "parent-clk", "sel-clk", "spi-clk", + "spi-hclk"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + status = "disabled"; + }; + + spi2: spi@11009000 { + compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm"; + reg = <0 0x11009000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MPLL_D2>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_104M_SPI2_BCK>, + <&infracfg CLK_INFRA_66M_SPI2_HCK>; + clock-names = "parent-clk", "sel-clk", "spi-clk", + "spi-hclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pwm: pwm@10048000 { + compatible = "mediatek,mt7988-pwm"; + reg = <0 0x10048000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>, + <&infracfg CLK_INFRA_66M_PWM_HCK>, + <&infracfg CLK_INFRA_66M_PWM_CK1>, + <&infracfg CLK_INFRA_66M_PWM_CK2>, + <&infracfg CLK_INFRA_66M_PWM_CK3>, + <&infracfg CLK_INFRA_66M_PWM_CK4>, + <&infracfg CLK_INFRA_66M_PWM_CK5>, + <&infracfg CLK_INFRA_66M_PWM_CK6>, + <&infracfg CLK_INFRA_66M_PWM_CK7>, + <&infracfg CLK_INFRA_66M_PWM_CK8>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3", + "pwm4","pwm5","pwm6","pwm7","pwm8"; + status = "disabled"; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + /* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */ + cooling-levels = <0 128 255>; + #cooling-cells = <2>; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + + lvts: lvts@1100a000 { + compatible = "mediatek,mt7988-lvts"; + #thermal-sensor-cells = <1>; + reg = <0 0x1100a000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>; + clock-names = "lvts_clk"; + nvmem-cells = <&lvts_calibration>; + nvmem-cell-names = "e_data1"; + }; + + crypto: crypto@15600000 { + compatible = "inside-secure,safexcel-eip197b"; + reg = <0 0x15600000 0 0x180000>; + interrupts = , + , + , + ; + interrupt-names = "ring0", "ring1", "ring2", "ring3"; + status = "okay"; + }; + + afe: audio-controller@11210000 { + compatible = "mediatek,mt79xx-audio"; + reg = <0 0x11210000 0 0x9000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>, + <&infracfg CLK_INFRA_AUD_26M>, + <&infracfg CLK_INFRA_AUD_L>, + <&infracfg CLK_INFRA_AUD_AUD>, + <&infracfg CLK_INFRA_AUD_EG2>, + <&topckgen CLK_TOP_AUD_SEL>, + <&topckgen CLK_TOP_AUD_I2S_M>; + clock-names = "aud_bus_ck", + "aud_26m_ck", + "aud_l_ck", + "aud_aud_ck", + "aud_eg2_ck", + "aud_sel", + "aud_i2s_m"; + assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>, + <&topckgen CLK_TOP_A1SYS_SEL>, + <&topckgen CLK_TOP_AUD_L_SEL>, + <&topckgen CLK_TOP_A_TUNER_SEL>; + assigned-clock-parents = <&apmixedsys CLK_APMIXED_APLL2>, + <&topckgen CLK_TOP_APLL2_D4>, + <&apmixedsys CLK_APMIXED_APLL2>, + <&topckgen CLK_TOP_APLL2_D4>; status = "disabled"; }; @@ -554,6 +842,8 @@ <&infracfg CLK_INFRA_133M_PCIE_CK_P2>; clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_pins>; status = "disabled"; phys = <&xphyu3port0 PHY_TYPE_PCIE>; @@ -594,6 +884,8 @@ <&infracfg CLK_INFRA_133M_PCIE_CK_P3>; clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_pins>; status = "disabled"; #interrupt-cells = <1>; @@ -631,6 +923,8 @@ <&infracfg CLK_INFRA_133M_PCIE_CK_P0>; clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>; status = "disabled"; #interrupt-cells = <1>; @@ -668,6 +962,8 @@ <&infracfg CLK_INFRA_133M_PCIE_CK_P1>; clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins>; status = "disabled"; #interrupt-cells = <1>; @@ -909,7 +1205,7 @@ mediatek,pio = <&pio>; gsw_phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id03a2.9481"; + compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; phy-mode = "internal"; nvmem-cells = <&phy_calibration_p0>; @@ -934,7 +1230,7 @@ }; gsw_phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id03a2.9481"; + compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; phy-mode = "internal"; nvmem-cells = <&phy_calibration_p1>; @@ -959,7 +1255,7 @@ }; gsw_phy2: ethernet-phy@2 { - compatible = "ethernet-phy-id03a2.9481"; + compatible = "ethernet-phy-ieee802.3-c22"; reg = <2>; phy-mode = "internal"; nvmem-cells = <&phy_calibration_p2>; @@ -984,7 +1280,7 @@ }; gsw_phy3: ethernet-phy@3 { - compatible = "ethernet-phy-id03a2.9481"; + compatible = "ethernet-phy-ieee802.3-c22"; reg = <3>; phy-mode = "internal"; nvmem-cells = <&phy_calibration_p3>; @@ -1096,19 +1392,19 @@ mediatek,ethsys = <ðsys>; mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>; - mediatek,xfi_pextp = <&xfi_pextp0>, <&xfi_pextp1>; - mediatek,xfi_pll = <&xfi_pll>; + mediatek,xfi-pextp = <&xfi_pextp0>, <&xfi_pextp1>; + mediatek,xfi-pll = <&xfi_pll>; mediatek,infracfg = <&topmisc>; mediatek,toprgu = <&watchdog>; #reset-cells = <1>; #address-cells = <1>; #size-cells = <0>; - status = "disabled"; gmac0: mac@0 { compatible = "mediatek,eth-mac"; reg = <0>; phy-mode = "internal"; + status = "disabled"; fixed-link { speed = <10000>; @@ -1120,11 +1416,13 @@ gmac1: mac@1 { compatible = "mediatek,eth-mac"; reg = <1>; + status = "disabled"; }; gmac2: mac@2 { compatible = "mediatek,eth-mac"; reg = <2>; + status = "disabled"; }; mdio_bus: mdio-bus { diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network index 4013c149f1e..1ea2ada0984 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network @@ -36,8 +36,8 @@ mediatek_setup_interfaces() mediatek,mt7986b-rfb) ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3" eth1 ;; - mediatek,mt7988a-dsa-10g-spim-snand) - ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3" "eth1 eth2" + mediatek,mt7988a-rfb) + ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3 eth1" eth2" ;; mercusys,mr90x-v1) ucidef_set_interfaces_lan_wan "lan0 lan1 lan2" eth1 diff --git a/target/linux/mediatek/image/filogic.mk b/target/linux/mediatek/image/filogic.mk index 53ccede1f9e..a799c7b5ee8 100644 --- a/target/linux/mediatek/image/filogic.mk +++ b/target/linux/mediatek/image/filogic.mk @@ -22,7 +22,15 @@ define Build/mt7986-bl31-uboot cat $(STAGING_DIR_IMAGE)/mt7986_$1-u-boot.fip >> $@ endef -define Build/mt7986-gpt +define Build/mt7988-bl2 + cat $(STAGING_DIR_IMAGE)/mt7988-$1-bl2.img >> $@ +endef + +define Build/mt7988-bl31-uboot + cat $(STAGING_DIR_IMAGE)/mt7988_$1-u-boot.fip >> $@ +endef + +define Build/mt798x-gpt cp $@ $@.tmp 2>/dev/null || true ptgen -g -o $@.tmp -a 1 -l 1024 \ $(if $(findstring sdmmc,$1), \ @@ -136,7 +144,7 @@ define Device/bananapi_bpi-r3 ARTIFACT/nor-bl31-uboot.fip := mt7986-bl31-uboot bananapi_bpi-r3-nor ARTIFACT/snand-preloader.bin := mt7986-bl2 spim-nand-ddr4 ARTIFACT/snand-bl31-uboot.fip := mt7986-bl31-uboot bananapi_bpi-r3-snand - ARTIFACT/sdcard.img.gz := mt7986-gpt sdmmc |\ + ARTIFACT/sdcard.img.gz := mt798x-gpt sdmmc |\ pad-to 17k | mt7986-bl2 sdmmc-ddr4 |\ pad-to 6656k | mt7986-bl31-uboot bananapi_bpi-r3-sdmmc |\ $(if $(CONFIG_TARGET_ROOTFS_INITRAMFS),\ @@ -148,7 +156,7 @@ define Device/bananapi_bpi-r3 pad-to 50M | mt7986-bl31-uboot bananapi_bpi-r3-nor |\ pad-to 51M | mt7986-bl2 emmc-ddr4 |\ pad-to 52M | mt7986-bl31-uboot bananapi_bpi-r3-emmc |\ - pad-to 56M | mt7986-gpt emmc |\ + pad-to 56M | mt798x-gpt emmc |\ $(if $(CONFIG_TARGET_ROOTFS_SQUASHFS),\ pad-to 64M | append-image squashfs-sysupgrade.itb | check-size |\ ) \ @@ -282,23 +290,67 @@ define Device/mediatek_mt7986b-rfb endef TARGET_DEVICES += mediatek_mt7986b-rfb -define Device/mediatek_mt7988a-rfb-nand +define Device/mediatek_mt7988a-rfb DEVICE_VENDOR := MediaTek - DEVICE_MODEL := MT7988a nand rfb - DEVICE_DTS := mt7988a-dsa-10g-spim-nand + DEVICE_MODEL := MT7988A rfb + DEVICE_DTS := mt7988a-rfb + DEVICE_DTS_OVERLAY:= \ + mt7988a-rfb-emmc \ + mt7988a-rfb-sd \ + mt7988a-rfb-snfi-nand \ + mt7988a-rfb-spim-nand \ + mt7988a-rfb-spim-nor \ + mt7988a-rfb-eth1-aqr \ + mt7988a-rfb-eth1-i2p5g-phy \ + mt7988a-rfb-eth1-mxl \ + mt7988a-rfb-eth1-sfp \ + mt7988a-rfb-eth2-aqr \ + mt7988a-rfb-eth2-mxl \ + mt7988a-rfb-eth2-sfp DEVICE_DTS_DIR := $(DTS_DIR)/ - KERNEL_LOADADDR := 0x48000000 - SUPPORTED_DEVICES := mediatek,mt7988a-rfb - UBINIZE_OPTS := -E 5 - BLOCKSIZE := 128k - PAGESIZE := 2048 - IMAGE_SIZE := 65536k + DEVICE_DTC_FLAGS := --pad 4096 + DEVICE_DTS_LOADADDR := 0x45f00000 + DEVICE_PACKAGES := kmod-sfp + KERNEL_LOADADDR := 0x46000000 + KERNEL := kernel-bin | gzip + KERNEL_INITRAMFS := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k + KERNEL_INITRAMFS_SUFFIX := .itb KERNEL_IN_UBI := 1 - IMAGES += factory.bin - IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE) - IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata + IMAGE_SIZE := $$(shell expr 64 + $$(CONFIG_TARGET_ROOTFS_PARTSIZE))m + IMAGES := sysupgrade.itb + IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-with-rootfs | pad-rootfs | append-metadata + ARTIFACTS := \ + emmc-gpt.bin emmc-preloader.bin emmc-bl31-uboot.fip \ + nor-preloader.bin nor-bl31-uboot.fip \ + sdcard.img.gz \ + snand-preloader.bin snand-bl31-uboot.fip + ARTIFACT/emmc-gpt.bin := mt798x-gpt emmc + ARTIFACT/emmc-preloader.bin := mt7988-bl2 emmc-comb + ARTIFACT/emmc-bl31-uboot.fip := mt7988-bl31-uboot rfb-emmc + ARTIFACT/nor-preloader.bin := mt7988-bl2 nor-comb + ARTIFACT/nor-bl31-uboot.fip := mt7988-bl31-uboot rfb-nor + ARTIFACT/snand-preloader.bin := mt7988-bl2 spim-nand-comb + ARTIFACT/snand-bl31-uboot.fip := mt7988-bl31-uboot rfb-snand + ARTIFACT/sdcard.img.gz := mt798x-gpt sdmmc |\ + pad-to 17k | mt7988-bl2 sdmmc-comb |\ + pad-to 6656k | mt7988-bl31-uboot rfb-sd |\ + $(if $(CONFIG_TARGET_ROOTFS_INITRAMFS),\ + pad-to 12M | append-image-stage initramfs.itb | check-size 44m |\ + ) \ + pad-to 44M | mt7988-bl2 spim-nand-comb |\ + pad-to 45M | mt7988-bl31-uboot rfb-snand |\ + pad-to 51M | mt7988-bl2 nor-comb |\ + pad-to 51M | mt7988-bl31-uboot rfb-nor |\ + pad-to 55M | mt7988-bl2 emmc-comb |\ + pad-to 56M | mt7988-bl31-uboot rfb-emmc |\ + pad-to 62M | mt798x-gpt emmc |\ + $(if $(CONFIG_TARGET_ROOTFS_SQUASHFS),\ + pad-to 64M | append-image squashfs-sysupgrade.itb | check-size |\ + ) \ + gzip endef -TARGET_DEVICES += mediatek_mt7988a-rfb-nand +TARGET_DEVICES += mediatek_mt7988a-rfb define Device/mercusys_mr90x-v1 DEVICE_VENDOR := Mercusys @@ -352,7 +404,7 @@ define Device/tplink_tl-xdr-common KERNEL_INITRAMFS := kernel-bin | lzma | \ fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k IMAGE/sysupgrade.itb := append-kernel | \ - fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata + fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-with-rootfs | append-metadata DEVICE_PACKAGES := kmod-usb3 kmod-mt7986-firmware mt7986-wo-firmware ARTIFACTS := preloader.bin bl31-uboot.fip ARTIFACT/preloader.bin := mt7986-bl2 spim-nand-ddr3 From fff4441135ed9290eb2f947f931b826a60d6c167 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Mon, 28 Aug 2023 00:13:05 +0100 Subject: [PATCH 23/29] uboot-mediatek: add builds for UniFi 6 LR v2 and v3 While the v2 is nearly identical to v1, v3 uses a different PHY and needs a different build for Ethernet to work in U-Boot. Signed-off-by: Daniel Golle --- package/boot/uboot-mediatek/Makefile | 34 +- .../patches/412-add-ubnt-unifi-6-lr.patch | 606 +++++++++++++++++- 2 files changed, 634 insertions(+), 6 deletions(-) diff --git a/package/boot/uboot-mediatek/Makefile b/package/boot/uboot-mediatek/Makefile index a04e629f122..021d444a97a 100644 --- a/package/boot/uboot-mediatek/Makefile +++ b/package/boot/uboot-mediatek/Makefile @@ -124,10 +124,34 @@ define U-Boot/mt7622_bananapi_bpi-r64-snand DEPENDS:=+trusted-firmware-a-mt7622-snand-2ddr endef -define U-Boot/mt7622_ubnt_unifi-6-lr +define U-Boot/mt7622_ubnt_unifi-6-lr-v1 NAME:=Ubiquiti UniFi 6 LR - UBOOT_CONFIG:=mt7622_ubnt_unifi-6-lr - BUILD_DEVICES:=ubnt_unifi-6-lr-v1-ubootmod ubnt_unifi-6-lr-v2-ubootmod + UBOOT_CONFIG:=mt7622_ubnt_unifi-6-lr-v1 + BUILD_DEVICES:=ubnt_unifi-6-lr-v1-ubootmod + BUILD_SUBTARGET:=mt7622 + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=nor + BL2_DDRBLOB:=2 + DEPENDS:=+trusted-firmware-a-mt7622-nor-2ddr + FIP_COMPRESS:=1 +endef + +define U-Boot/mt7622_ubnt_unifi-6-lr-v2 + NAME:=Ubiquiti UniFi 6 LR v2 + UBOOT_CONFIG:=mt7622_ubnt_unifi-6-lr-v2 + BUILD_DEVICES:=ubnt_unifi-6-lr-v2-ubootmod + BUILD_SUBTARGET:=mt7622 + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=nor + BL2_DDRBLOB:=2 + DEPENDS:=+trusted-firmware-a-mt7622-nor-2ddr + FIP_COMPRESS:=1 +endef + +define U-Boot/mt7622_ubnt_unifi-6-lr-v3 + NAME:=Ubiquiti UniFi 6 LR v3 + UBOOT_CONFIG:=mt7622_ubnt_unifi-6-lr-v3 + BUILD_DEVICES:=ubnt_unifi-6-lr-v3-ubootmod BUILD_SUBTARGET:=mt7622 UBOOT_IMAGE:=u-boot.fip BL2_BOOTDEV:=nor @@ -392,7 +416,9 @@ UBOOT_TARGETS := \ mt7622_bananapi_bpi-r64-snand \ mt7622_linksys_e8450 \ mt7622_rfb1 \ - mt7622_ubnt_unifi-6-lr \ + mt7622_ubnt_unifi-6-lr-v1 \ + mt7622_ubnt_unifi-6-lr-v2 \ + mt7622_ubnt_unifi-6-lr-v3 \ mt7623n_bpir2 \ mt7623a_unielec_u7623 \ mt7628_rfb \ diff --git a/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch b/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch index 4bde0617653..aad6c53b9bb 100644 --- a/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch +++ b/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch @@ -1,5 +1,5 @@ --- /dev/null -+++ b/configs/mt7622_ubnt_unifi-6-lr_defconfig ++++ b/configs/mt7622_ubnt_unifi-6-lr-v1_defconfig @@ -0,0 +1,147 @@ +CONFIG_ARM=y +CONFIG_POSITION_INDEPENDENT=y @@ -149,6 +149,305 @@ +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.254" --- /dev/null ++++ b/configs/mt7622_ubnt_unifi-6-lr-v2_defconfig +@@ -0,0 +1,147 @@ ++CONFIG_ARM=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TARGET_MT7622=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_SYS_LOAD_ADDR=0x40080000 ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_MTDPARTS_DEFAULT="mtdparts=nor0:128k(bl2),640k(fip),64k(u-boot-env),256k(factory),64k(eeprom),15232k(recovery),-(firmware)" ++CONFIG_ENV_IS_IN_MTD=y ++CONFIG_ENV_MTD_NAME="nor0" ++CONFIG_ENV_SIZE_REDUND=0x4000 ++CONFIG_ENV_SIZE=0x4000 ++CONFIG_ENV_OFFSET=0xc0000 ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_RESET_BUTTON_SETTLE_DELAY=400 ++CONFIG_BOOTP_SEND_HOSTNAME=y ++CONFIG_DEFAULT_ENV_FILE="ubnt_unifi-6-lr-v2_env" ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=25000000 ++CONFIG_DEFAULT_DEVICE_TREE="mt7622-ubnt-unifi-6-lr" ++CONFIG_DEBUG_UART=y ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_DEFAULT_FDT_FILE="mt7622-ubnt-unifi-6-lr" ++CONFIG_SYS_PROMPT="MT7622> " ++# CONFIG_LEGACY_IMAGE_FORMAT is not set ++# CONFIG_BOOTM_PLAN9 is not set ++# CONFIG_BOOTM_RTEMS is not set ++# CONFIG_BOOTM_VXWORKS is not set ++# CONFIG_EFI is not set ++# CONFIG_EFI_LOADER is not set ++CONFIG_CMD_BOOTMENU=y ++# CONFIG_CMD_BOOTEFI is not set ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++# CONFIG_CMD_ELF is not set ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LINK_LOCAL=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_MTD=y ++CONFIG_CMD_MTDPARTS=y ++# CONFIG_CMD_PCI is not set ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++# CONFIG_CMD_UNLZ4 is not set ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_ETH=y ++CONFIG_DM_ETH_PHY=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_MDIO=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++# CONFIG_DM_MMC is not set ++CONFIG_DM_SERIAL=y ++CONFIG_DM_SPI=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_HUSH_PARSER=y ++# CONFIG_PARTITION_UUIDS is not set ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++# CONFIG_LED is not set ++# CONFIG_LZ4 is not set ++CONFIG_VERSION_VARIABLE=y ++CONFIG_NETCONSOLE=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_PHY=y ++CONFIG_PHY_FIXED=y ++CONFIG_PHYLIB_10G=y ++CONFIG_PHY_AQUANTIA=y ++CONFIG_PHY_ADDR_ENABLE=y ++CONFIG_PHY_ADDR=8 ++CONFIG_MEDIATEK_ETH=y ++CONFIG_MTD=y ++# CONFIG_MMC is not set ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7622=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_RAM=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++CONFIG_MTK_SNFI_SPI=y ++CONFIG_MTK_SNOR=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_SPI_FLASH=y ++CONFIG_SPI_FLASH_BAR=y ++CONFIG_SPI_FLASH_MTD=y ++CONFIG_SPI_FLASH_UNLOCK_ALL=y ++CONFIG_SPI_FLASH_EON=y ++CONFIG_SPI_FLASH_GIGADEVICE=y ++CONFIG_SPI_FLASH_MACRONIX=y ++CONFIG_SPI_FLASH_SPANSION=y ++CONFIG_SPI_FLASH_STMICRO=y ++CONFIG_SPI_FLASH_SST=y ++CONFIG_SPI_FLASH_WINBOND=y ++CONFIG_SPI_FLASH_XMC=y ++CONFIG_SPI_FLASH_USE_4K_SECTORS=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +--- /dev/null ++++ b/configs/mt7622_ubnt_unifi-6-lr-v3_defconfig +@@ -0,0 +1,146 @@ ++CONFIG_ARM=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TARGET_MT7622=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_SYS_LOAD_ADDR=0x40080000 ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_MTDPARTS_DEFAULT="mtdparts=nor0:128k(bl2),640k(fip),64k(u-boot-env),256k(factory),64k(eeprom),15232k(recovery),-(firmware)" ++CONFIG_ENV_IS_IN_MTD=y ++CONFIG_ENV_MTD_NAME="nor0" ++CONFIG_ENV_SIZE_REDUND=0x4000 ++CONFIG_ENV_SIZE=0x4000 ++CONFIG_ENV_OFFSET=0xc0000 ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_RESET_BUTTON_SETTLE_DELAY=400 ++CONFIG_BOOTP_SEND_HOSTNAME=y ++CONFIG_DEFAULT_ENV_FILE="ubnt_unifi-6-lr_env" ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=25000000 ++CONFIG_DEFAULT_DEVICE_TREE="mt7622-ubnt-unifi-6-lr-v3" ++CONFIG_DEBUG_UART=y ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_DEFAULT_FDT_FILE="mt7622-ubnt-unifi-6-lr-v3" ++CONFIG_SYS_PROMPT="MT7622> " ++# CONFIG_LEGACY_IMAGE_FORMAT is not set ++# CONFIG_BOOTM_PLAN9 is not set ++# CONFIG_BOOTM_RTEMS is not set ++# CONFIG_BOOTM_VXWORKS is not set ++# CONFIG_EFI is not set ++# CONFIG_EFI_LOADER is not set ++CONFIG_CMD_BOOTMENU=y ++# CONFIG_CMD_BOOTEFI is not set ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++# CONFIG_CMD_ELF is not set ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LINK_LOCAL=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_MTD=y ++CONFIG_CMD_MTDPARTS=y ++# CONFIG_CMD_PCI is not set ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++# CONFIG_CMD_UNLZ4 is not set ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_ETH=y ++CONFIG_DM_ETH_PHY=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_MDIO=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++# CONFIG_DM_MMC is not set ++CONFIG_DM_SERIAL=y ++CONFIG_DM_SPI=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_HUSH_PARSER=y ++# CONFIG_PARTITION_UUIDS is not set ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++# CONFIG_LED is not set ++# CONFIG_LZ4 is not set ++CONFIG_VERSION_VARIABLE=y ++CONFIG_NETCONSOLE=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_PHY=y ++CONFIG_PHY_FIXED=y ++CONFIG_PHY_REALTEK=y ++CONFIG_PHY_ADDR_ENABLE=y ++CONFIG_PHY_ADDR=0 ++CONFIG_MEDIATEK_ETH=y ++CONFIG_MTD=y ++# CONFIG_MMC is not set ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7622=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_RAM=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++CONFIG_MTK_SNFI_SPI=y ++CONFIG_MTK_SNOR=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_SPI_FLASH=y ++CONFIG_SPI_FLASH_BAR=y ++CONFIG_SPI_FLASH_MTD=y ++CONFIG_SPI_FLASH_UNLOCK_ALL=y ++CONFIG_SPI_FLASH_EON=y ++CONFIG_SPI_FLASH_GIGADEVICE=y ++CONFIG_SPI_FLASH_MACRONIX=y ++CONFIG_SPI_FLASH_SPANSION=y ++CONFIG_SPI_FLASH_STMICRO=y ++CONFIG_SPI_FLASH_SST=y ++CONFIG_SPI_FLASH_WINBOND=y ++CONFIG_SPI_FLASH_XMC=y ++CONFIG_SPI_FLASH_USE_4K_SECTORS=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +--- /dev/null +++ b/arch/arm/dts/mt7622-ubnt-unifi-6-lr.dts @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: GPL-2.0 @@ -344,13 +643,210 @@ + }; + }; +}; +--- /dev/null ++++ b/arch/arm/dts/mt7622-ubnt-unifi-6-lr-v3.dts +@@ -0,0 +1,193 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2019 MediaTek Inc. ++ * Author: Sam Shih ++ */ ++ ++/dts-v1/; ++#include ++#include "mt7622.dtsi" ++#include "mt7622-u-boot.dtsi" ++ ++/ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "mt7622-ubnt-unifi-6-lr-v3"; ++ compatible = "mediatek,mt7622", "ubnt,unifi-6-lr-v3"; ++ ++ chosen { ++ stdout-path = &uart0; ++ tick-timer = &timer0; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0x40000000 0x20000000>; ++ }; ++ ++ aliases { ++ spi0 = &snor; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ ++ reset { ++ label = "reset"; ++ gpios = <&gpio 62 GPIO_ACTIVE_LOW>; ++ linux,code = ; ++ }; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0x40000000 0x20000000>; ++ }; ++ ++ reg_1p8v: regulator-1p8v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-1.8V"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ reg_3p3v: regulator-3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-3.3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ reg_5v: regulator-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-5V"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++}; ++ ++&pcie { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>; ++ status = "okay"; ++ ++ pcie@0,0 { ++ status = "okay"; ++ }; ++ ++ pcie@1,0 { ++ status = "okay"; ++ }; ++}; ++ ++&pinctrl { ++ eth_pins: eth-pins { ++ mux { ++ function = "eth"; ++ groups = "mdc_mdio", "rgmii_via_gmac2"; ++ }; ++ }; ++ ++ pcie0_pins: pcie0-pins { ++ mux { ++ function = "pcie"; ++ groups = "pcie0_pad_perst", ++ "pcie0_1_waken", ++ "pcie0_1_clkreq"; ++ }; ++ }; ++ ++ pcie1_pins: pcie1-pins { ++ mux { ++ function = "pcie"; ++ groups = "pcie1_pad_perst", ++ "pcie1_0_waken", ++ "pcie1_0_clkreq"; ++ }; ++ }; ++ ++ snfi_pins: snfi-pins { ++ mux { ++ function = "flash"; ++ groups = "snfi"; ++ }; ++ }; ++ ++ snor_pins: snor-pins { ++ mux { ++ function = "flash"; ++ groups = "spi_nor"; ++ }; ++ }; ++ ++ uart0_pins: uart0 { ++ mux { ++ function = "uart"; ++ groups = "uart0_0_tx_rx" ; ++ }; ++ }; ++ ++ watchdog_pins: watchdog-default { ++ mux { ++ function = "watchdog"; ++ groups = "watchdog"; ++ }; ++ }; ++}; ++ ++&snor { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&snor_pins>; ++ status = "okay"; ++ ++ spi-flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-tx-bus-width = <1>; ++ spi-rx-bus-width = <4>; ++ u-boot,dm-pre-reloc; ++ }; ++}; ++ ++&uart0 { ++ mediatek,force-highspeed; ++ status = "okay"; ++}; ++ ++&watchdog { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&watchdog_pins>; ++ status = "okay"; ++}; ++ ++ð { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <ð_pins>; ++ ++ mediatek,gmac-id = <0>; ++ phy-mode = "sgmii"; ++ phy-handle = <&gphy>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ }; ++ ++ mdio-bus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ gphy: ethernet-phy@0 { ++ /* RealTek RTL8211FS */ ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <0x0>; ++ }; ++ }; ++}; --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -1306,6 +1306,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ +@@ -1306,6 +1306,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7623a-unielec-u7623-02-emmc.dtb \ mt7622-bananapi-bpi-r64.dtb \ mt7622-linksys-e8450-ubi.dtb \ + mt7622-ubnt-unifi-6-lr.dtb \ ++ mt7622-ubnt-unifi-6-lr-v3.dtb \ mt7623n-bananapi-bpi-r2.dtb \ mt7629-rfb.dtb \ mt7981-rfb.dtb \ @@ -407,6 +903,112 @@ +_firstboot=setenv _firstboot ; run _switch_to_menu ; run ethaddr_factory ; run _init_env ; run boot_first +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title $ver" +--- /dev/null ++++ b/ubnt_unifi-6-lr-v2_env +@@ -0,0 +1,50 @@ ++ethaddr_factory=mtd read nor0 $loadaddr 0x110000 0x10000 && env readmem -b ethaddr $loadaddr 0x6 ; setenv ethaddr_factory ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x48000000 ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_nor ; fi ++bootdelay=0 ++bootfile=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-v2-ubootmod-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-v2-ubootmod-preloader.bin ++bootfile_fip=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-v2-ubootmod-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-v2-ubootmod-squashfs-sysupgrade.itb ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= ( ( ( OpenWrt ) ) ) ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from flash.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from flash.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to flash.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to flash.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=Load BL31+U-Boot FIP via TFTP then write to flash.=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=Load BL2 preloader via TFTP then write to flash.=run boot_tftp_write_preloader ; run bootmenu_confirm_return ++bootmenu_8=Reboot.=reset ++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=run nor_read_production && bootm $loadaddr ++boot_recovery=run nor_read_recovery ; bootm $loadaddr ++boot_serial_write_fip=loadx $loadaddr 115200 && run boot_write_fip ++boot_serial_write_preloader=loadx $loadaddr 115200 && run boot_write_preloader ++boot_tftp_forever=while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run nor_write_production ; if env exists noboot ; then else bootm $loadaddr ; fi ++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run nor_write_recovery ; if env exists noboot ; then else bootm $loadaddr ; fi ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run boot_write_fip ++boot_tftp_write_preloader=tftpboot $loadaddr $bootfile_bl2 && run boot_write_preloader ++boot_nor=run boot_production ; run boot_recovery ++boot_write_fip=mtd erase nor0 0x20000 0x80000 && mtd write nor0 $loadaddr 0x20000 0x80000 ++boot_write_preloader=mtd erase nor0 0x0 0x20000 && mtd write nor0 $loadaddr 0x0 0x20000 ++reset_factory=mtd erase nor0 0xc0000 0x10000 && reset ++nor_read_production=mtd read nor0 $loadaddr 0x1000000 0x1000 && imsz $loadaddr image_size && mtd read nor0 $loadaddr 0x1000000 $image_size ++nor_read_recovery=mtd read nor0 $loadaddr 0x120000 0x1000 && imsz $loadaddr image_size && mtd read nor0 $loadaddr 0x120000 $image_size ++nor_pad_size=imsz $loadaddr image_size ; setexpr image_eb 0x$image_size / 0x1000 ; setexpr tmp1 0x$image_size % 0x1000 ; test 0x$tmp1 -gt 0 && setexpr image_eb 0x$image_eb + 1 ; setexpr image_eb 0x$image_eb * 0x1000 ++nor_write_production=run nor_pad_size ; test 0x$image_eb -le 0x3000000 && mtd erase nor0 0x1000000 0x$image_eb && mtd write nor0 $loadaddr 0x1000000 $filesize ++nor_write_recovery=run nor_pad_size ; test 0x$image_eb -le 0xee0000 && mtd erase nor0 0x120000 0x$image_eb && mtd write nor0 $loadaddr 0x120000 $filesize ++_init_env=setenv _init_env ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run ethaddr_factory ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title $ver"--- /dev/null +--- /dev/null ++++ b/ubnt_unifi-6-lr-v3_env +@@ -0,0 +1,50 @@ ++ethaddr_factory=mtd read nor0 $loadaddr 0x110000 0x10000 && env readmem -b ethaddr $loadaddr 0x6 ; setenv ethaddr_factory ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x48000000 ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_nor ; fi ++bootdelay=0 ++bootfile=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-v3-ubootmod-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-v3-ubootmod-preloader.bin ++bootfile_fip=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-v3-ubootmod-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-v3-ubootmod-squashfs-sysupgrade.itb ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= ( ( ( OpenWrt ) ) ) ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from flash.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from flash.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to flash.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to flash.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=Load BL31+U-Boot FIP via TFTP then write to flash.=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=Load BL2 preloader via TFTP then write to flash.=run boot_tftp_write_preloader ; run bootmenu_confirm_return ++bootmenu_8=Reboot.=reset ++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=run nor_read_production && bootm $loadaddr ++boot_recovery=run nor_read_recovery ; bootm $loadaddr ++boot_serial_write_fip=loadx $loadaddr 115200 && run boot_write_fip ++boot_serial_write_preloader=loadx $loadaddr 115200 && run boot_write_preloader ++boot_tftp_forever=while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run nor_write_production ; if env exists noboot ; then else bootm $loadaddr ; fi ++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run nor_write_recovery ; if env exists noboot ; then else bootm $loadaddr ; fi ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run boot_write_fip ++boot_tftp_write_preloader=tftpboot $loadaddr $bootfile_bl2 && run boot_write_preloader ++boot_nor=run boot_production ; run boot_recovery ++boot_write_fip=mtd erase nor0 0x20000 0x80000 && mtd write nor0 $loadaddr 0x20000 0x80000 ++boot_write_preloader=mtd erase nor0 0x0 0x20000 && mtd write nor0 $loadaddr 0x0 0x20000 ++reset_factory=mtd erase nor0 0xc0000 0x10000 && reset ++nor_read_production=mtd read nor0 $loadaddr 0x1000000 0x1000 && imsz $loadaddr image_size && mtd read nor0 $loadaddr 0x1000000 $image_size ++nor_read_recovery=mtd read nor0 $loadaddr 0x120000 0x1000 && imsz $loadaddr image_size && mtd read nor0 $loadaddr 0x120000 $image_size ++nor_pad_size=imsz $loadaddr image_size ; setexpr image_eb 0x$image_size / 0x1000 ; setexpr tmp1 0x$image_size % 0x1000 ; test 0x$tmp1 -gt 0 && setexpr image_eb 0x$image_eb + 1 ; setexpr image_eb 0x$image_eb * 0x1000 ++nor_write_production=run nor_pad_size ; test 0x$image_eb -le 0x3000000 && mtd erase nor0 0x1000000 0x$image_eb && mtd write nor0 $loadaddr 0x1000000 $filesize ++nor_write_recovery=run nor_pad_size ; test 0x$image_eb -le 0xee0000 && mtd erase nor0 0x120000 0x$image_eb && mtd write nor0 $loadaddr 0x120000 $filesize ++_init_env=setenv _init_env ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run ethaddr_factory ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title $ver" --- a/common/board_r.c +++ b/common/board_r.c @@ -66,6 +66,7 @@ From a0f4eadf6a25fb54c189bde91425673e11125d35 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Mon, 28 Aug 2023 00:14:10 +0100 Subject: [PATCH 24/29] mediatek: add support for Ubiquiti UniFi 6 LR v3 Some recent models of the Ubiquiti Networks UniFi 6 LR access point come with a RealTek RTL8211FS 1000M/100M/10M PHY instead of the Aquantia AQR112 2500M/1000M/100M/10M PHY used in both v1 and v2. Add build for this variant so we can support Ethernet with the PHY. Signed-off-by: Daniel Golle --- .../dts/mt7622-ubnt-unifi-6-lr-v1.dtsi | 25 +++++ .../dts/mt7622-ubnt-unifi-6-lr-v2.dtsi | 26 +++++ .../mt7622-ubnt-unifi-6-lr-v3-ubootmod.dts | 84 +++++++++++++++ .../dts/mt7622-ubnt-unifi-6-lr-v3.dts | 100 ++++++++++++++++++ .../dts/mt7622-ubnt-unifi-6-lr-v3.dtsi | 50 +++++++++ .../mediatek/dts/mt7622-ubnt-unifi-6-lr.dtsi | 25 ----- target/linux/mediatek/image/mt7622.mk | 33 +++++- 7 files changed, 316 insertions(+), 27 deletions(-) create mode 100644 target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v3-ubootmod.dts create mode 100644 target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v3.dts create mode 100644 target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v3.dtsi diff --git a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1.dtsi b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1.dtsi index b3299a988fe..91719865dd7 100644 --- a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1.dtsi +++ b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1.dtsi @@ -1,5 +1,30 @@ #include "mt7622-ubnt-unifi-6-lr.dtsi" +ð { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <ð_pins>; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + + phy-mode = "2500base-x"; + phy-handle = <&phy0>; + phy-connection-type = "2500base-x"; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@8 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x8>; + }; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; diff --git a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2.dtsi b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2.dtsi index 4d278805d40..ab3c5929258 100644 --- a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2.dtsi +++ b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2.dtsi @@ -22,3 +22,29 @@ }; }; }; + +ð { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <ð_pins>; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + + phy-mode = "2500base-x"; + phy-handle = <&phy0>; + phy-connection-type = "2500base-x"; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@8 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x8>; + }; + }; +}; + diff --git a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v3-ubootmod.dts b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v3-ubootmod.dts new file mode 100644 index 00000000000..46faf8da307 --- /dev/null +++ b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v3-ubootmod.dts @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "mt7622-ubnt-unifi-6-lr-v3.dtsi" + +/ { + model = "Ubiquiti UniFi 6 LR v3 (U-Boot mod)"; + compatible = "ubnt,unifi-6-lr-v3-ubootmod", "mediatek,mt7622"; +}; + +&nor_partitions { + partition@0 { + label = "bl2"; + reg = <0x0 0x20000>; + }; + + partition@20000 { + label = "fip"; + reg = <0x20000 0xa0000>; + }; + + partition@c0000 { + label = "u-boot-env"; + reg = <0xc0000 0x10000>; + }; + + factory: partition@d0000 { + label = "factory"; + reg = <0xd0000 0x40000>; + read-only; + }; + + eeprom: partition@110000 { + label = "eeprom"; + reg = <0x110000 0x10000>; + read-only; + }; + + partition@120000 { + label = "recovery"; + reg = <0x120000 0xee0000>; + }; + + partition@1000000 { + compatible = "denx,fit"; + label = "firmware"; + reg = <0x1000000 0x3000000>; + }; +}; + +&wmac { + mediatek,mtd-eeprom = <&factory 0x0>; + nvmem-cells = <&macaddr_eeprom_0>; + nvmem-cell-names = "mac-address"; + status = "okay"; +}; + +&slot0 { + wifi@0,0 { + reg = <0x0 0 0 0 0>; + mediatek,mtd-eeprom = <&factory 0x20000>; + nvmem-cells = <&macaddr_eeprom_6>; + nvmem-cell-names = "mac-address"; + ieee80211-freq-limit = <5000000 6000000>; + }; +}; + +&gmac0 { + nvmem-cells = <&macaddr_eeprom_0>; + nvmem-cell-names = "mac-address"; +}; + +&eeprom { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_eeprom_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_eeprom_6: macaddr@6 { + reg = <0x6 0x6>; + }; +}; diff --git a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v3.dts b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v3.dts new file mode 100644 index 00000000000..34bdaa6254a --- /dev/null +++ b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v3.dts @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "mt7622-ubnt-unifi-6-lr-v3.dtsi" + +/ { + model = "Ubiquiti UniFi 6 LR v3"; + compatible = "ubnt,unifi-6-lr-v3", "mediatek,mt7622"; +}; + +&nor_partitions { + partition@0 { + label = "preloader"; + reg = <0x0 0x40000>; + }; + + partition@40000 { + label = "atf"; + reg = <0x40000 0x20000>; + }; + + partition@60000 { + label = "u-boot"; + reg = <0x60000 0x60000>; + }; + + partition@c0000 { + label = "u-boot-env"; + reg = <0xc0000 0x10000>; + }; + + factory: partition@d0000 { + label = "factory"; + reg = <0xd0000 0x40000>; + read-only; + }; + + eeprom: partition@110000 { + label = "eeprom"; + reg = <0x110000 0x10000>; + read-only; + }; + + partition@120000 { + label = "bs"; + reg = <0x120000 0x10000>; + }; + + partition@130000 { + label = "cfg"; + reg = <0x130000 0x100000>; + read-only; + }; + + partition@230000 { + compatible = "denx,fit"; + label = "firmware"; + reg = <0x230000 0x1ee0000>; + }; + + partition@2110000 { + label = "kernel1"; + reg = <0x2110000 0x1ee0000>; + }; +}; + +&wmac { + mediatek,mtd-eeprom = <&factory 0x0>; + nvmem-cells = <&macaddr_eeprom_0>; + nvmem-cell-names = "mac-address"; + status = "okay"; +}; + +&slot0 { + wifi@0,0 { + reg = <0x0 0 0 0 0>; + mediatek,mtd-eeprom = <&factory 0x20000>; + nvmem-cells = <&macaddr_eeprom_6>; + nvmem-cell-names = "mac-address"; + ieee80211-freq-limit = <5000000 6000000>; + }; +}; + +&gmac0 { + nvmem-cells = <&macaddr_eeprom_0>; + nvmem-cell-names = "mac-address"; +}; + +&eeprom { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_eeprom_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_eeprom_6: macaddr@6 { + reg = <0x6 0x6>; + }; +}; diff --git a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v3.dtsi b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v3.dtsi new file mode 100644 index 00000000000..c581bd7d905 --- /dev/null +++ b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v3.dtsi @@ -0,0 +1,50 @@ +#include "mt7622-ubnt-unifi-6-lr.dtsi" + +/ { + aliases { + led-boot = &led_white; + led-failsafe = &led_white; + led-running = &led_blue; + led-upgrade = &led_blue; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led_white: dome_white { + label = "white:dome"; + gpios = <&pio 0x43 GPIO_ACTIVE_LOW>; + }; + + led_blue: dome_blue { + label = "blue:dome"; + gpios = <&pio 0x44 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +ð { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <ð_pins>; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + + phy-mode = "sgmii"; + phy-handle = <&phy0>; + phy-connection-type = "sgmii"; + managed = "in-band-status"; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; + }; +}; diff --git a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr.dtsi b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr.dtsi index 4231cc1f79d..783b0c388e6 100644 --- a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr.dtsi +++ b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr.dtsi @@ -151,31 +151,6 @@ status = "disabled"; }; -ð { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <ð_pins>; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - - phy-mode = "2500base-x"; - phy-handle = <&phy0>; - phy-connection-type = "2500base-x"; - }; - - mdio: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@8 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <0x8>; - }; - }; -}; - &pwrap { pinctrl-names = "default"; pinctrl-0 = <&pmic_bus_pins>; diff --git a/target/linux/mediatek/image/mt7622.mk b/target/linux/mediatek/image/mt7622.mk index 040ef957db9..d40eb54cb73 100644 --- a/target/linux/mediatek/image/mt7622.mk +++ b/target/linux/mediatek/image/mt7622.mk @@ -307,7 +307,7 @@ define Device/ubnt_unifi-6-lr-v1-ubootmod IMAGE/sysupgrade.itb := append-kernel | fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | pad-rootfs | append-metadata ARTIFACTS := preloader.bin bl31-uboot.fip ARTIFACT/preloader.bin := bl2 nor-2ddr - ARTIFACT/bl31-uboot.fip := bl31-uboot ubnt_unifi-6-lr + ARTIFACT/bl31-uboot.fip := bl31-uboot ubnt_unifi-6-lr-v1 SUPPORTED_DEVICES += ubnt,unifi-6-lr-ubootmod endef TARGET_DEVICES += ubnt_unifi-6-lr-v1-ubootmod @@ -337,10 +337,39 @@ define Device/ubnt_unifi-6-lr-v2-ubootmod IMAGE/sysupgrade.itb := append-kernel | fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | pad-rootfs | append-metadata ARTIFACTS := preloader.bin bl31-uboot.fip ARTIFACT/preloader.bin := bl2 nor-2ddr - ARTIFACT/bl31-uboot.fip := bl31-uboot ubnt_unifi-6-lr + ARTIFACT/bl31-uboot.fip := bl31-uboot ubnt_unifi-6-lr-v2 endef TARGET_DEVICES += ubnt_unifi-6-lr-v2-ubootmod +define Device/ubnt_unifi-6-lr-v3 + DEVICE_VENDOR := Ubiquiti + DEVICE_MODEL := UniFi 6 LR + DEVICE_VARIANT := v3 + DEVICE_DTS_CONFIG := config@1 + DEVICE_DTS := mt7622-ubnt-unifi-6-lr-v3 + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-mt7915-firmware +endef +TARGET_DEVICES += ubnt_unifi-6-lr-v3 + +define Device/ubnt_unifi-6-lr-v3-ubootmod + DEVICE_VENDOR := Ubiquiti + DEVICE_MODEL := UniFi 6 LR + DEVICE_VARIANT := v3 U-Boot mod + DEVICE_DTS := mt7622-ubnt-unifi-6-lr-v3-ubootmod + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-mt7915-firmware + KERNEL := kernel-bin | lzma + KERNEL_INITRAMFS_SUFFIX := -recovery.itb + KERNEL_INITRAMFS := kernel-bin | lzma | fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k + IMAGES := sysupgrade.itb + IMAGE/sysupgrade.itb := append-kernel | fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | pad-rootfs | append-metadata + ARTIFACTS := preloader.bin bl31-uboot.fip + ARTIFACT/preloader.bin := bl2 nor-2ddr + ARTIFACT/bl31-uboot.fip := bl31-uboot ubnt_unifi-6-lr-v3 +endef +TARGET_DEVICES += ubnt_unifi-6-lr-v3-ubootmod + define Device/xiaomi_redmi-router-ax6s DEVICE_VENDOR := Xiaomi DEVICE_MODEL := Redmi Router AX6S From f631c7bbb16f1d39d59c4cdf3f7189abab4fd9c6 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sat, 26 Aug 2023 02:19:18 +0100 Subject: [PATCH 25/29] generic: sync MediaTek Ethernet driver with upstream Import commits from upstream Linux replacing some downstream patches. Move accepted patches from pending-{5.15,6.1} to backport-{5.15,6.1}. Signed-off-by: Daniel Golle --- ..._eth_soc-fix-resource-leak-in-error-.patch | 35 + ..._eth_soc-fix-memory-leak-in-error-pa.patch | 107 + ..._eth_soc-align-reset-procedure-to-ve.patch | 4 +- ..._eth_soc-avoid-port_mg-assignment-on.patch | 4 +- ...iatek-ppe-assign-per-port-queues-for.patch | 2 +- ..._eth_soc-compile-out-netsys-v2-code-.patch | 28 - ..._eth_soc-fix-VLAN-rx-hardware-accele.patch | 2 +- ...ii-ensure-the-SGMII-PHY-is-powered-d.patch | 2 +- ...t-mtk_eth_soc-add-support-for-MT7981.patch | 8 +- ..._eth_soc-switch-to-external-PCS-driv.patch | 10 +- ...eth_soc-add-missing-ppe-cache-flush.patch} | 2 +- ..._eth_soc-use-WO-firmware-for-MT7981.patch} | 0 ...eth_soc-fix-NULL-pointer-dereferenc.patch} | 0 ...eth_soc-ppe-add-support-for-flow-ac.patch} | 26 +- ...atek-fix-ppe-flow-accounting-for-v1.patch} | 4 +- ...eth_soc-drop-generic-vlan-rx-offloa.patch} | 0 ..._eth_soc-always-mtk_get_ib1_pkt_type.patch | 31 + ..._ppe-add-MTK_FOE_ENTRY_V-1-2-_SIZE-m.patch | 78 + ..._eth_soc-remove-incorrect-PLL-config.patch | 141 ++ ..._eth_soc-remove-mac_pcs_get_state-an.patch | 81 + ..._eth_soc-add-version-in-mtk_soc_data.patch | 550 +++++ ...t-mtk_eth_soc-increase-MAX_DEVS-to-3.patch | 29 + ...eth_soc-rely-on-MTK_MAX_DEVS-and-re.patch} | 109 +- ...eth_soc-add-NETSYS_V3-version-suppo.patch} | 177 +- ...eth_soc-convert-caps-in-mtk_soc_dat.patch} | 26 +- ..._eth_soc-convert-clock-bitmap-to-u64.patch | 132 ++ ..._eth_soc-add-basic-support-for-MT798.patch | 477 +++++ ..._eth_soc-enable-page_pool-support-fo.patch | 27 + ..._eth_soc-enable-nft-hw-flowtable_off.patch | 135 ++ ..._eth_soc-support-per-flow-accounting.patch | 78 + ..._eth_soc-fix-NULL-pointer-on-hw-rese.patch | 52 + ..._eth_soc-fix-register-definitions-fo.patch | 44 + ...tk_eth_soc-add-reset-bits-for-MT7988.patch | 188 ++ ..._eth_soc-add-support-for-in-SoC-SRAM.patch | 254 +++ ..._eth_soc-support-36-bit-DMA-addressi.patch | 166 ++ ...ble-PCS-polling-over-major-configura.patch | 81 + ...NULL-pl-pcs-dereference-during-phyli.patch | 38 + ...k-add-pcs_enable-pcs_disable-methods.patch | 172 ++ ...t-pcs-lynxi-implement-pcs_disable-op.patch | 44 + ..._eth_soc-compile-out-netsys-v2-code-.patch | 28 - ..._eth_soc-fix-VLAN-rx-hardware-accele.patch | 2 +- ...ii-ensure-the-SGMII-PHY-is-powered-d.patch | 2 +- ...t-mtk_eth_soc-add-support-for-MT7981.patch | 10 +- ..._eth_soc-switch-to-external-PCS-driv.patch | 8 +- ...eth_soc-ppe-add-support-for-flow-ac.patch} | 95 +- ...atek-fix-ppe-flow-accounting-for-v1.patch} | 19 +- ...eth_soc-drop-generic-vlan-rx-offloa.patch} | 0 ..._eth_soc-always-mtk_get_ib1_pkt_type.patch | 31 + ..._ppe-add-MTK_FOE_ENTRY_V-1-2-_SIZE-m.patch | 78 + ..._eth_soc-remove-incorrect-PLL-config.patch | 141 ++ ..._eth_soc-remove-mac_pcs_get_state-an.patch | 81 + ..._eth_soc-add-version-in-mtk_soc_data.patch | 550 +++++ ...t-mtk_eth_soc-increase-MAX_DEVS-to-3.patch | 29 + ...eth_soc-rely-on-MTK_MAX_DEVS-and-re.patch} | 109 +- ...eth_soc-add-NETSYS_V3-version-suppo.patch} | 177 +- ...eth_soc-convert-caps-in-mtk_soc_dat.patch} | 26 +- ..._eth_soc-convert-clock-bitmap-to-u64.patch | 132 ++ ..._eth_soc-add-basic-support-for-MT798.patch | 477 +++++ ..._eth_soc-enable-page_pool-support-fo.patch | 27 + ..._eth_soc-enable-nft-hw-flowtable_off.patch | 135 ++ ..._eth_soc-support-per-flow-accounting.patch | 78 + ..._eth_soc-fix-NULL-pointer-on-hw-rese.patch | 52 + ..._eth_soc-fix-register-definitions-fo.patch | 44 + ...tk_eth_soc-add-reset-bits-for-MT7988.patch | 188 ++ ..._eth_soc-add-support-for-in-SoC-SRAM.patch | 254 +++ ..._eth_soc-support-36-bit-DMA-addressi.patch | 166 ++ ...ntroduce-driver-for-MT7988-built-in-.patch | 4 +- ...k-add-pcs_enable-pcs_disable-methods.patch | 172 ++ ...t-pcs-lynxi-implement-pcs_disable-op.patch | 44 + .../795-backport-phylink_pcs-helpers.patch | 8 +- ...net-mtk_eth_soc-enable-threaded-NAPI.patch | 6 +- ..._eth_soc-compile-out-netsys-v2-code-.patch | 44 + ..._eth_soc-work-around-issue-with-send.patch | 12 +- ...rnet-mtk_eth_soc-set-NETIF_F_ALL_TSO.patch | 2 +- ..._eth_soc-fix-remaining-throughput-re.patch | 4 +- ..._eth_soc-ppe-fix-L2-offloading-with-.patch | 2 +- ..._eth_soc-add-code-for-offloading-flo.patch | 6 +- ...iatek-mtk_ppe-prefer-newly-added-l2-.patch | 2 +- ..._eth_soc-improve-keeping-track-of-of.patch | 22 +- ...iatek-fix-ppe-flow-accounting-for-L2.patch | 57 +- ..._eth_soc-add-MTK_NETSYS_V1-capabilit.patch | 223 -- ..._eth_soc-move-MAX_DEVS-in-mtk_soc_da.patch | 181 -- ...k_eth_soc-add-support-for-MT7988-SoC.patch | 495 ----- ..._eth_soc-add-paths-and-SerDes-modes-.patch | 1867 ----------------- ..._eth_soc-add-paths-and-SerDes-modes-.patch | 1604 ++++++++++++++ ...net-mtk_eth_soc-enable-threaded-NAPI.patch | 6 +- ..._eth_soc-compile-out-netsys-v2-code-.patch | 44 + ..._eth_soc-work-around-issue-with-send.patch | 12 +- ...rnet-mtk_eth_soc-set-NETIF_F_ALL_TSO.patch | 2 +- ..._eth_soc-fix-remaining-throughput-re.patch | 4 +- ..._eth_soc-ppe-fix-L2-offloading-with-.patch | 2 +- ..._eth_soc-add-code-for-offloading-flo.patch | 11 +- ...iatek-mtk_ppe-prefer-newly-added-l2-.patch | 2 +- ..._eth_soc-improve-keeping-track-of-of.patch | 25 +- ...iatek-fix-ppe-flow-accounting-for-L2.patch | 55 +- ..._eth_soc-add-MTK_NETSYS_V1-capabilit.patch | 223 -- ..._eth_soc-move-MAX_DEVS-in-mtk_soc_da.patch | 181 -- ...k_eth_soc-add-support-for-MT7988-SoC.patch | 495 ----- ..._eth_soc-add-paths-and-SerDes-modes-.patch | 1867 ----------------- ..._eth_soc-add-paths-and-SerDes-modes-.patch | 1604 ++++++++++++++ ...phy-define-PSGMII-PHY-interface-mode.patch | 4 +- ...02-phy-Add-2.5G-SGMII-interface-mode.patch | 4 +- target/linux/mediatek/filogic/config-6.1 | 3 +- ..._eth_soc-implement-Clause-45-MDIO-ac.patch | 4 +- ...tk_wed-move-dlm-a-dedicated-dts-node.patch | 4 +- ...-ge-soc-initialize-MT7988-PHY-LEDs-d.patch | 213 -- ...phy-mediatek-ge-soc-support-PHY-LEDs.patch | 524 +++++ ...tk_wed-move-dlm-a-dedicated-dts-node.patch | 4 +- ...ethernet-mediatek-support-net-labels.patch | 4 +- ...y-simplify-phy_link_change-arguments.patch | 2 +- ...vers-net-phy-eee-support-for-rtl838x.patch | 6 +- ...04-include-linux-add-phy-hsgmii-mode.patch | 4 +- 112 files changed, 10043 insertions(+), 6304 deletions(-) create mode 100644 target/linux/generic/backport-5.15/728-v6.1-04-net-ethernet-mtk_eth_soc-fix-resource-leak-in-error-.patch create mode 100644 target/linux/generic/backport-5.15/728-v6.1-05-net-ethernet-mtk_eth_soc-fix-memory-leak-in-error-pa.patch delete mode 100644 target/linux/generic/backport-5.15/730-07-v6.3-net-ethernet-mtk_eth_soc-compile-out-netsys-v2-code-.patch rename target/linux/generic/{pending-5.15/736-05-net-ethernet-mtk_eth_soc-add-missing-ppe-cache-flush.patch => backport-5.15/733-v6.3-21-net-ethernet-mtk_eth_soc-add-missing-ppe-cache-flush.patch} (90%) rename target/linux/generic/backport-5.15/{733-v6.4-21-net-mtk_eth_soc-use-WO-firmware-for-MT7981.patch => 733-v6.4-22-net-mtk_eth_soc-use-WO-firmware-for-MT7981.patch} (100%) rename target/linux/generic/backport-5.15/{733-v6.4-22-net-ethernet-mtk_eth_soc-fix-NULL-pointer-dereferenc.patch => 733-v6.4-23-net-ethernet-mtk_eth_soc-fix-NULL-pointer-dereferenc.patch} (100%) rename target/linux/generic/{pending-6.1/731-net-ethernet-mediatek-ppe-add-support-for-flow-accou.patch => backport-5.15/733-v6.4-24-net-ethernet-mtk_eth_soc-ppe-add-support-for-flow-ac.patch} (94%) rename target/linux/generic/{pending-5.15/736-06-net-ethernet-mediatek-fix-ppe-flow-accounting-for-v1.patch => backport-5.15/733-v6.4-25-net-ethernet-mediatek-fix-ppe-flow-accounting-for-v1.patch} (92%) rename target/linux/generic/{pending-5.15/732-00-net-ethernet-mtk_eth_soc-drop-generic-vlan-rx-offloa.patch => backport-5.15/733-v6.4-26-net-ethernet-mtk_eth_soc-drop-generic-vlan-rx-offloa.patch} (100%) create mode 100644 target/linux/generic/backport-5.15/733-v6.5-27-net-ethernet-mtk_eth_soc-always-mtk_get_ib1_pkt_type.patch create mode 100644 target/linux/generic/backport-5.15/750-v6.5-01-net-ethernet-mtk_ppe-add-MTK_FOE_ENTRY_V-1-2-_SIZE-m.patch create mode 100644 target/linux/generic/backport-5.15/750-v6.5-02-net-ethernet-mtk_eth_soc-remove-incorrect-PLL-config.patch create mode 100644 target/linux/generic/backport-5.15/750-v6.5-03-net-ethernet-mtk_eth_soc-remove-mac_pcs_get_state-an.patch create mode 100644 target/linux/generic/backport-5.15/750-v6.5-05-net-ethernet-mtk_eth_soc-add-version-in-mtk_soc_data.patch create mode 100644 target/linux/generic/backport-5.15/750-v6.5-06-net-ethernet-mtk_eth_soc-increase-MAX_DEVS-to-3.patch rename target/linux/generic/{pending-5.15/737-03-net-ethernet-mtk_eth_soc-rely-on-num_devs-and-remove.patch => backport-5.15/750-v6.5-07-net-ethernet-mtk_eth_soc-rely-on-MTK_MAX_DEVS-and-re.patch} (50%) rename target/linux/generic/{pending-5.15/737-04-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V3-capabilit.patch => backport-5.15/750-v6.5-08-net-ethernet-mtk_eth_soc-add-NETSYS_V3-version-suppo.patch} (63%) rename target/linux/generic/{pending-5.15/737-05-net-ethernet-mtk_eth_soc-convert-caps-in-mtk_soc_dat.patch => backport-5.15/750-v6.5-09-net-ethernet-mtk_eth_soc-convert-caps-in-mtk_soc_dat.patch} (89%) create mode 100644 target/linux/generic/backport-5.15/750-v6.5-10-net-ethernet-mtk_eth_soc-convert-clock-bitmap-to-u64.patch create mode 100644 target/linux/generic/backport-5.15/750-v6.5-11-net-ethernet-mtk_eth_soc-add-basic-support-for-MT798.patch create mode 100644 target/linux/generic/backport-5.15/750-v6.5-12-net-ethernet-mtk_eth_soc-enable-page_pool-support-fo.patch create mode 100644 target/linux/generic/backport-5.15/750-v6.5-13-net-ethernet-mtk_eth_soc-enable-nft-hw-flowtable_off.patch create mode 100644 target/linux/generic/backport-5.15/750-v6.5-14-net-ethernet-mtk_eth_soc-support-per-flow-accounting.patch create mode 100644 target/linux/generic/backport-5.15/750-v6.5-15-net-ethernet-mtk_eth_soc-fix-NULL-pointer-on-hw-rese.patch create mode 100644 target/linux/generic/backport-5.15/750-v6.5-16-net-ethernet-mtk_eth_soc-fix-register-definitions-fo.patch create mode 100644 target/linux/generic/backport-5.15/750-v6.5-17-net-ethernet-mtk_eth_soc-add-reset-bits-for-MT7988.patch create mode 100644 target/linux/generic/backport-5.15/750-v6.5-18-net-ethernet-mtk_eth_soc-add-support-for-in-SoC-SRAM.patch create mode 100644 target/linux/generic/backport-5.15/750-v6.5-19-net-ethernet-mtk_eth_soc-support-36-bit-DMA-addressi.patch create mode 100644 target/linux/generic/backport-5.15/792-01-v6.0-net-phylink-disable-PCS-polling-over-major-configura.patch create mode 100644 target/linux/generic/backport-5.15/792-02-v6.0-net-phylink-fix-NULL-pl-pcs-dereference-during-phyli.patch create mode 100644 target/linux/generic/backport-5.15/792-03-v6.6-net-phylink-add-pcs_enable-pcs_disable-methods.patch create mode 100644 target/linux/generic/backport-5.15/793-v6.6-net-pcs-lynxi-implement-pcs_disable-op.patch delete mode 100644 target/linux/generic/backport-6.1/730-07-v6.3-net-ethernet-mtk_eth_soc-compile-out-netsys-v2-code-.patch rename target/linux/generic/{pending-5.15/731-net-ethernet-mediatek-ppe-add-support-for-flow-accou.patch => backport-6.1/733-v6.4-23-net-ethernet-mtk_eth_soc-ppe-add-support-for-flow-ac.patch} (79%) rename target/linux/generic/{pending-6.1/736-06-net-ethernet-mediatek-fix-ppe-flow-accounting-for-v1.patch => backport-6.1/733-v6.4-24-net-ethernet-mediatek-fix-ppe-flow-accounting-for-v1.patch} (63%) rename target/linux/generic/{pending-6.1/732-00-net-ethernet-mtk_eth_soc-drop-generic-vlan-rx-offloa.patch => backport-6.1/733-v6.4-25-net-ethernet-mtk_eth_soc-drop-generic-vlan-rx-offloa.patch} (100%) create mode 100644 target/linux/generic/backport-6.1/733-v6.5-26-net-ethernet-mtk_eth_soc-always-mtk_get_ib1_pkt_type.patch create mode 100644 target/linux/generic/backport-6.1/750-v6.5-01-net-ethernet-mtk_ppe-add-MTK_FOE_ENTRY_V-1-2-_SIZE-m.patch create mode 100644 target/linux/generic/backport-6.1/750-v6.5-02-net-ethernet-mtk_eth_soc-remove-incorrect-PLL-config.patch create mode 100644 target/linux/generic/backport-6.1/750-v6.5-03-net-ethernet-mtk_eth_soc-remove-mac_pcs_get_state-an.patch create mode 100644 target/linux/generic/backport-6.1/750-v6.5-05-net-ethernet-mtk_eth_soc-add-version-in-mtk_soc_data.patch create mode 100644 target/linux/generic/backport-6.1/750-v6.5-06-net-ethernet-mtk_eth_soc-increase-MAX_DEVS-to-3.patch rename target/linux/generic/{pending-6.1/737-03-net-ethernet-mtk_eth_soc-rely-on-num_devs-and-remove.patch => backport-6.1/750-v6.5-07-net-ethernet-mtk_eth_soc-rely-on-MTK_MAX_DEVS-and-re.patch} (50%) rename target/linux/generic/{pending-6.1/737-04-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V3-capabilit.patch => backport-6.1/750-v6.5-08-net-ethernet-mtk_eth_soc-add-NETSYS_V3-version-suppo.patch} (63%) rename target/linux/generic/{pending-6.1/737-05-net-ethernet-mtk_eth_soc-convert-caps-in-mtk_soc_dat.patch => backport-6.1/750-v6.5-09-net-ethernet-mtk_eth_soc-convert-caps-in-mtk_soc_dat.patch} (89%) create mode 100644 target/linux/generic/backport-6.1/750-v6.5-10-net-ethernet-mtk_eth_soc-convert-clock-bitmap-to-u64.patch create mode 100644 target/linux/generic/backport-6.1/750-v6.5-11-net-ethernet-mtk_eth_soc-add-basic-support-for-MT798.patch create mode 100644 target/linux/generic/backport-6.1/750-v6.5-12-net-ethernet-mtk_eth_soc-enable-page_pool-support-fo.patch create mode 100644 target/linux/generic/backport-6.1/750-v6.5-13-net-ethernet-mtk_eth_soc-enable-nft-hw-flowtable_off.patch create mode 100644 target/linux/generic/backport-6.1/750-v6.5-14-net-ethernet-mtk_eth_soc-support-per-flow-accounting.patch create mode 100644 target/linux/generic/backport-6.1/750-v6.5-15-net-ethernet-mtk_eth_soc-fix-NULL-pointer-on-hw-rese.patch create mode 100644 target/linux/generic/backport-6.1/750-v6.5-16-net-ethernet-mtk_eth_soc-fix-register-definitions-fo.patch create mode 100644 target/linux/generic/backport-6.1/750-v6.5-17-net-ethernet-mtk_eth_soc-add-reset-bits-for-MT7988.patch create mode 100644 target/linux/generic/backport-6.1/750-v6.5-18-net-ethernet-mtk_eth_soc-add-support-for-in-SoC-SRAM.patch create mode 100644 target/linux/generic/backport-6.1/750-v6.5-19-net-ethernet-mtk_eth_soc-support-36-bit-DMA-addressi.patch create mode 100644 target/linux/generic/backport-6.1/792-v6.6-net-phylink-add-pcs_enable-pcs_disable-methods.patch create mode 100644 target/linux/generic/backport-6.1/793-v6.6-net-pcs-lynxi-implement-pcs_disable-op.patch create mode 100644 target/linux/generic/pending-5.15/732-00-net-ethernet-mtk_eth_soc-compile-out-netsys-v2-code-.patch delete mode 100644 target/linux/generic/pending-5.15/737-01-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V1-capabilit.patch delete mode 100644 target/linux/generic/pending-5.15/737-02-net-ethernet-mtk_eth_soc-move-MAX_DEVS-in-mtk_soc_da.patch delete mode 100644 target/linux/generic/pending-5.15/737-06-net-ethernet-mtk_eth_soc-add-support-for-MT7988-SoC.patch delete mode 100644 target/linux/generic/pending-5.15/737-07-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch create mode 100644 target/linux/generic/pending-5.15/737-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch create mode 100644 target/linux/generic/pending-6.1/732-00-net-ethernet-mtk_eth_soc-compile-out-netsys-v2-code-.patch delete mode 100644 target/linux/generic/pending-6.1/737-01-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V1-capabilit.patch delete mode 100644 target/linux/generic/pending-6.1/737-02-net-ethernet-mtk_eth_soc-move-MAX_DEVS-in-mtk_soc_da.patch delete mode 100644 target/linux/generic/pending-6.1/737-06-net-ethernet-mtk_eth_soc-add-support-for-MT7988-SoC.patch delete mode 100644 target/linux/generic/pending-6.1/737-07-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch create mode 100644 target/linux/generic/pending-6.1/737-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch delete mode 100644 target/linux/mediatek/patches-6.1/731-net-phy-mediatek-ge-soc-initialize-MT7988-PHY-LEDs-d.patch create mode 100644 target/linux/mediatek/patches-6.1/731-v6.5-net-phy-mediatek-ge-soc-support-PHY-LEDs.patch diff --git a/target/linux/generic/backport-5.15/728-v6.1-04-net-ethernet-mtk_eth_soc-fix-resource-leak-in-error-.patch b/target/linux/generic/backport-5.15/728-v6.1-04-net-ethernet-mtk_eth_soc-fix-resource-leak-in-error-.patch new file mode 100644 index 00000000000..ae3acfef725 --- /dev/null +++ b/target/linux/generic/backport-5.15/728-v6.1-04-net-ethernet-mtk_eth_soc-fix-resource-leak-in-error-.patch @@ -0,0 +1,35 @@ +From 8110437e59616293228cd781c486d8495a61e36a Mon Sep 17 00:00:00 2001 +From: Yan Cangang +Date: Sun, 20 Nov 2022 13:52:58 +0800 +Subject: [PATCH] net: ethernet: mtk_eth_soc: fix resource leak in error path + +In mtk_probe(), when mtk_ppe_init() or mtk_eth_offload_init() failed, +mtk_mdio_cleanup() isn't called. Fix it. + +Fixes: ba37b7caf1ed ("net: ethernet: mtk_eth_soc: add support for initializing the PPE") +Fixes: 502e84e2382d ("net: ethernet: mtk_eth_soc: add flow offloading support") +Signed-off-by: Yan Cangang +Reviewed-by: Leon Romanovsky +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -4087,13 +4087,13 @@ static int mtk_probe(struct platform_dev + eth->soc->offload_version, i); + if (!eth->ppe[i]) { + err = -ENOMEM; +- goto err_free_dev; ++ goto err_deinit_mdio; + } + } + + err = mtk_eth_offload_init(eth); + if (err) +- goto err_free_dev; ++ goto err_deinit_mdio; + } + + for (i = 0; i < MTK_MAX_DEVS; i++) { diff --git a/target/linux/generic/backport-5.15/728-v6.1-05-net-ethernet-mtk_eth_soc-fix-memory-leak-in-error-pa.patch b/target/linux/generic/backport-5.15/728-v6.1-05-net-ethernet-mtk_eth_soc-fix-memory-leak-in-error-pa.patch new file mode 100644 index 00000000000..b0f5723f7bf --- /dev/null +++ b/target/linux/generic/backport-5.15/728-v6.1-05-net-ethernet-mtk_eth_soc-fix-memory-leak-in-error-pa.patch @@ -0,0 +1,107 @@ +From 603ea5e7ffa73c7fac07d8713d97285990695213 Mon Sep 17 00:00:00 2001 +From: Yan Cangang +Date: Sun, 20 Nov 2022 13:52:59 +0800 +Subject: [PATCH] net: ethernet: mtk_eth_soc: fix memory leak in error path + +In mtk_ppe_init(), when dmam_alloc_coherent() or devm_kzalloc() failed, +the rhashtable ppe->l2_flows isn't destroyed. Fix it. + +In mtk_probe(), when mtk_ppe_init() or mtk_eth_offload_init() or +register_netdev() failed, have the same problem. Fix it. + +Fixes: 33fc42de3327 ("net: ethernet: mtk_eth_soc: support creating mac address based offload entries") +Signed-off-by: Yan Cangang +Reviewed-by: Leon Romanovsky +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 9 +++++---- + drivers/net/ethernet/mediatek/mtk_ppe.c | 19 +++++++++++++++++-- + drivers/net/ethernet/mediatek/mtk_ppe.h | 1 + + 3 files changed, 23 insertions(+), 6 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -4087,13 +4087,13 @@ static int mtk_probe(struct platform_dev + eth->soc->offload_version, i); + if (!eth->ppe[i]) { + err = -ENOMEM; +- goto err_deinit_mdio; ++ goto err_deinit_ppe; + } + } + + err = mtk_eth_offload_init(eth); + if (err) +- goto err_deinit_mdio; ++ goto err_deinit_ppe; + } + + for (i = 0; i < MTK_MAX_DEVS; i++) { +@@ -4103,7 +4103,7 @@ static int mtk_probe(struct platform_dev + err = register_netdev(eth->netdev[i]); + if (err) { + dev_err(eth->dev, "error bringing up device\n"); +- goto err_deinit_mdio; ++ goto err_deinit_ppe; + } else + netif_info(eth, probe, eth->netdev[i], + "mediatek frame engine at 0x%08lx, irq %d\n", +@@ -4123,7 +4123,8 @@ static int mtk_probe(struct platform_dev + + return 0; + +-err_deinit_mdio: ++err_deinit_ppe: ++ mtk_ppe_deinit(eth); + mtk_mdio_cleanup(eth); + err_free_dev: + mtk_free_dev(eth); +--- a/drivers/net/ethernet/mediatek/mtk_ppe.c ++++ b/drivers/net/ethernet/mediatek/mtk_ppe.c +@@ -743,7 +743,7 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_ + MTK_PPE_ENTRIES * soc->foe_entry_size, + &ppe->foe_phys, GFP_KERNEL); + if (!foe) +- return NULL; ++ goto err_free_l2_flows; + + ppe->foe_table = foe; + +@@ -751,11 +751,26 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_ + sizeof(*ppe->foe_flow); + ppe->foe_flow = devm_kzalloc(dev, foe_flow_size, GFP_KERNEL); + if (!ppe->foe_flow) +- return NULL; ++ goto err_free_l2_flows; + + mtk_ppe_debugfs_init(ppe, index); + + return ppe; ++ ++err_free_l2_flows: ++ rhashtable_destroy(&ppe->l2_flows); ++ return NULL; ++} ++ ++void mtk_ppe_deinit(struct mtk_eth *eth) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) { ++ if (!eth->ppe[i]) ++ return; ++ rhashtable_destroy(ð->ppe[i]->l2_flows); ++ } + } + + static void mtk_ppe_init_foe_table(struct mtk_ppe *ppe) +--- a/drivers/net/ethernet/mediatek/mtk_ppe.h ++++ b/drivers/net/ethernet/mediatek/mtk_ppe.h +@@ -304,6 +304,7 @@ struct mtk_ppe { + + struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base, + int version, int index); ++void mtk_ppe_deinit(struct mtk_eth *eth); + void mtk_ppe_start(struct mtk_ppe *ppe); + int mtk_ppe_stop(struct mtk_ppe *ppe); + diff --git a/target/linux/generic/backport-5.15/729-20-v6.3-net-ethernet-mtk_eth_soc-align-reset-procedure-to-ve.patch b/target/linux/generic/backport-5.15/729-20-v6.3-net-ethernet-mtk_eth_soc-align-reset-procedure-to-ve.patch index f87b4c9e5b1..7dde9a54824 100644 --- a/target/linux/generic/backport-5.15/729-20-v6.3-net-ethernet-mtk_eth_soc-align-reset-procedure-to-ve.patch +++ b/target/linux/generic/backport-5.15/729-20-v6.3-net-ethernet-mtk_eth_soc-align-reset-procedure-to-ve.patch @@ -237,8 +237,8 @@ Signed-off-by: Paolo Abeni { --- a/drivers/net/ethernet/mediatek/mtk_ppe.h +++ b/drivers/net/ethernet/mediatek/mtk_ppe.h -@@ -306,6 +306,7 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_ - int version, int index); +@@ -307,6 +307,7 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_ + void mtk_ppe_deinit(struct mtk_eth *eth); void mtk_ppe_start(struct mtk_ppe *ppe); int mtk_ppe_stop(struct mtk_ppe *ppe); +int mtk_ppe_prepare_reset(struct mtk_ppe *ppe); diff --git a/target/linux/generic/backport-5.15/730-03-v6.3-net-ethernet-mtk_eth_soc-avoid-port_mg-assignment-on.patch b/target/linux/generic/backport-5.15/730-03-v6.3-net-ethernet-mtk_eth_soc-avoid-port_mg-assignment-on.patch index 1e1ac560db7..af987c42e25 100644 --- a/target/linux/generic/backport-5.15/730-03-v6.3-net-ethernet-mtk_eth_soc-avoid-port_mg-assignment-on.patch +++ b/target/linux/generic/backport-5.15/730-03-v6.3-net-ethernet-mtk_eth_soc-avoid-port_mg-assignment-on.patch @@ -12,7 +12,7 @@ Signed-off-by: Felix Fietkau --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -4421,7 +4421,7 @@ static const struct mtk_soc_data mt7621_ +@@ -4422,7 +4422,7 @@ static const struct mtk_soc_data mt7621_ .hw_features = MTK_HW_FEATURES, .required_clks = MT7621_CLKS_BITMAP, .required_pctl = false, @@ -21,7 +21,7 @@ Signed-off-by: Felix Fietkau .hash_offset = 2, .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, .txrx = { -@@ -4460,7 +4460,7 @@ static const struct mtk_soc_data mt7623_ +@@ -4461,7 +4461,7 @@ static const struct mtk_soc_data mt7623_ .hw_features = MTK_HW_FEATURES, .required_clks = MT7623_CLKS_BITMAP, .required_pctl = true, diff --git a/target/linux/generic/backport-5.15/730-06-v6.3-net-ethernet-mediatek-ppe-assign-per-port-queues-for.patch b/target/linux/generic/backport-5.15/730-06-v6.3-net-ethernet-mediatek-ppe-assign-per-port-queues-for.patch index 8935eb673ae..e05042c2047 100644 --- a/target/linux/generic/backport-5.15/730-06-v6.3-net-ethernet-mediatek-ppe-assign-per-port-queues-for.patch +++ b/target/linux/generic/backport-5.15/730-06-v6.3-net-ethernet-mediatek-ppe-assign-per-port-queues-for.patch @@ -47,7 +47,7 @@ Signed-off-by: Felix Fietkau #define MTK_FOE_IB2_DEST_PORT_V2 GENMASK(12, 9) #define MTK_FOE_IB2_MULTICAST_V2 BIT(13) #define MTK_FOE_IB2_WDMA_WINFO_V2 BIT(19) -@@ -351,6 +353,8 @@ int mtk_foe_entry_set_pppoe(struct mtk_e +@@ -352,6 +354,8 @@ int mtk_foe_entry_set_pppoe(struct mtk_e int sid); int mtk_foe_entry_set_wdma(struct mtk_eth *eth, struct mtk_foe_entry *entry, int wdma_idx, int txq, int bss, int wcid); diff --git a/target/linux/generic/backport-5.15/730-07-v6.3-net-ethernet-mtk_eth_soc-compile-out-netsys-v2-code-.patch b/target/linux/generic/backport-5.15/730-07-v6.3-net-ethernet-mtk_eth_soc-compile-out-netsys-v2-code-.patch deleted file mode 100644 index 44af9128b75..00000000000 --- a/target/linux/generic/backport-5.15/730-07-v6.3-net-ethernet-mtk_eth_soc-compile-out-netsys-v2-code-.patch +++ /dev/null @@ -1,28 +0,0 @@ -From: Felix Fietkau -Date: Thu, 27 Oct 2022 23:39:52 +0200 -Subject: [PATCH] net: ethernet: mtk_eth_soc: compile out netsys v2 code - on mt7621 - -Avoid some branches in the hot path on low-end devices with limited CPU power, -and reduce code size - -Signed-off-by: Felix Fietkau ---- - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -917,7 +917,13 @@ enum mkt_eth_capabilities { - #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ - (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) - --#define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) -+#ifdef CONFIG_SOC_MT7621 -+#define MTK_CAP_MASK MTK_NETSYS_V2 -+#else -+#define MTK_CAP_MASK 0 -+#endif -+ -+#define MTK_HAS_CAPS(caps, _x) (((caps) & (_x) & ~(MTK_CAP_MASK)) == (_x)) - - #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ - MTK_GMAC2_RGMII | MTK_SHARED_INT | \ diff --git a/target/linux/generic/backport-5.15/730-09-v6.3-net-ethernet-mtk_eth_soc-fix-VLAN-rx-hardware-accele.patch b/target/linux/generic/backport-5.15/730-09-v6.3-net-ethernet-mtk_eth_soc-fix-VLAN-rx-hardware-accele.patch index 6ebd1abcd0f..f9d822ad447 100644 --- a/target/linux/generic/backport-5.15/730-09-v6.3-net-ethernet-mtk_eth_soc-fix-VLAN-rx-hardware-accele.patch +++ b/target/linux/generic/backport-5.15/730-09-v6.3-net-ethernet-mtk_eth_soc-fix-VLAN-rx-hardware-accele.patch @@ -181,7 +181,7 @@ Signed-off-by: Felix Fietkau /* CDMP Ingress Control Register */ #define MTK_CDMP_IG_CTRL 0x400 #define MTK_CDMP_STAG_EN BIT(0) -@@ -1166,6 +1172,8 @@ struct mtk_eth { +@@ -1160,6 +1166,8 @@ struct mtk_eth { int ip_align; diff --git a/target/linux/generic/backport-5.15/733-v6.2-12-net-mediatek-sgmii-ensure-the-SGMII-PHY-is-powered-d.patch b/target/linux/generic/backport-5.15/733-v6.2-12-net-mediatek-sgmii-ensure-the-SGMII-PHY-is-powered-d.patch index 8d2991f4500..598788d9984 100644 --- a/target/linux/generic/backport-5.15/733-v6.2-12-net-mediatek-sgmii-ensure-the-SGMII-PHY-is-powered-d.patch +++ b/target/linux/generic/backport-5.15/733-v6.2-12-net-mediatek-sgmii-ensure-the-SGMII-PHY-is-powered-d.patch @@ -34,7 +34,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -1070,11 +1070,13 @@ struct mtk_soc_data { +@@ -1064,11 +1064,13 @@ struct mtk_soc_data { * @regmap: The register map pointing at the range used to setup * SGMII modes * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap diff --git a/target/linux/generic/backport-5.15/733-v6.3-18-net-ethernet-mtk_eth_soc-add-support-for-MT7981.patch b/target/linux/generic/backport-5.15/733-v6.3-18-net-ethernet-mtk_eth_soc-add-support-for-MT7981.patch index 36fa94a7905..1ae4e833632 100644 --- a/target/linux/generic/backport-5.15/733-v6.3-18-net-ethernet-mtk_eth_soc-add-support-for-MT7981.patch +++ b/target/linux/generic/backport-5.15/733-v6.3-18-net-ethernet-mtk_eth_soc-add-support-for-MT7981.patch @@ -51,7 +51,7 @@ Signed-off-by: Jakub Kicinski mtk_eth_path_name(path), __func__, updated); --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -4748,6 +4748,26 @@ static const struct mtk_soc_data mt7629_ +@@ -4749,6 +4749,26 @@ static const struct mtk_soc_data mt7629_ }, }; @@ -78,7 +78,7 @@ Signed-off-by: Jakub Kicinski static const struct mtk_soc_data mt7986_data = { .reg_map = &mt7986_reg_map, .ana_rgc3 = 0x128, -@@ -4790,6 +4810,7 @@ const struct of_device_id of_mtk_match[] +@@ -4791,6 +4811,7 @@ const struct of_device_id of_mtk_match[] { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data}, @@ -145,7 +145,7 @@ Signed-off-by: Jakub Kicinski #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) -@@ -963,6 +987,11 @@ enum mkt_eth_capabilities { +@@ -957,6 +981,11 @@ enum mkt_eth_capabilities { MTK_MUX_U3_GMAC2_TO_QPHY | \ MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) @@ -157,7 +157,7 @@ Signed-off-by: Jakub Kicinski #define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1) -@@ -1076,12 +1105,14 @@ struct mtk_soc_data { +@@ -1070,12 +1099,14 @@ struct mtk_soc_data { * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap * @interface: Currently configured interface mode * @pcs: Phylink PCS structure diff --git a/target/linux/generic/backport-5.15/733-v6.3-20-net-ethernet-mtk_eth_soc-switch-to-external-PCS-driv.patch b/target/linux/generic/backport-5.15/733-v6.3-20-net-ethernet-mtk_eth_soc-switch-to-external-PCS-driv.patch index 2e6a70d7255..42a700d5439 100644 --- a/target/linux/generic/backport-5.15/733-v6.3-20-net-ethernet-mtk_eth_soc-switch-to-external-PCS-driv.patch +++ b/target/linux/generic/backport-5.15/733-v6.3-20-net-ethernet-mtk_eth_soc-switch-to-external-PCS-driv.patch @@ -151,7 +151,7 @@ Signed-off-by: Jakub Kicinski } if (eth->soc->offload_version) { -@@ -4648,6 +4685,8 @@ err_deinit_hw: +@@ -4649,6 +4686,8 @@ err_deinit_hw: mtk_hw_deinit(eth); err_wed_exit: mtk_wed_exit(); @@ -228,7 +228,7 @@ Signed-off-by: Jakub Kicinski /* Infrasys subsystem config registers */ #define INFRA_MISC2 0x70c #define CO_QPHY_SEL BIT(0) -@@ -1105,31 +1046,6 @@ struct mtk_soc_data { +@@ -1099,31 +1040,6 @@ struct mtk_soc_data { /* currently no SoC has more than 2 macs */ #define MTK_MAX_DEVS 2 @@ -260,7 +260,7 @@ Signed-off-by: Jakub Kicinski /* struct mtk_eth - This is the main datasructure for holding the state * of the driver * @dev: The device pointer -@@ -1149,6 +1065,7 @@ struct mtk_sgmii { +@@ -1143,6 +1059,7 @@ struct mtk_sgmii { * MII modes * @infra: The register map pointing at the range used to setup * SGMII and GePHY path @@ -268,7 +268,7 @@ Signed-off-by: Jakub Kicinski * @pctl: The register map pointing at the range used to setup * GMAC port drive/slew values * @dma_refcnt: track how many netdevs are using the DMA engine -@@ -1189,8 +1106,8 @@ struct mtk_eth { +@@ -1183,8 +1100,8 @@ struct mtk_eth { u32 msg_enable; unsigned long sysclk; struct regmap *ethsys; @@ -279,7 +279,7 @@ Signed-off-by: Jakub Kicinski struct regmap *pctl; bool hwlro; refcount_t dma_refcnt; -@@ -1352,10 +1269,6 @@ void mtk_stats_update_mac(struct mtk_mac +@@ -1346,10 +1263,6 @@ void mtk_stats_update_mac(struct mtk_mac void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); u32 mtk_r32(struct mtk_eth *eth, unsigned reg); diff --git a/target/linux/generic/pending-5.15/736-05-net-ethernet-mtk_eth_soc-add-missing-ppe-cache-flush.patch b/target/linux/generic/backport-5.15/733-v6.3-21-net-ethernet-mtk_eth_soc-add-missing-ppe-cache-flush.patch similarity index 90% rename from target/linux/generic/pending-5.15/736-05-net-ethernet-mtk_eth_soc-add-missing-ppe-cache-flush.patch rename to target/linux/generic/backport-5.15/733-v6.3-21-net-ethernet-mtk_eth_soc-add-missing-ppe-cache-flush.patch index 30839319c7d..7742b0925bc 100644 --- a/target/linux/generic/pending-5.15/736-05-net-ethernet-mtk_eth_soc-add-missing-ppe-cache-flush.patch +++ b/target/linux/generic/backport-5.15/733-v6.3-21-net-ethernet-mtk_eth_soc-add-missing-ppe-cache-flush.patch @@ -11,7 +11,7 @@ Signed-off-by: Felix Fietkau --- a/drivers/net/ethernet/mediatek/mtk_ppe.c +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c -@@ -523,6 +523,7 @@ __mtk_foe_entry_clear(struct mtk_ppe *pp +@@ -464,6 +464,7 @@ __mtk_foe_entry_clear(struct mtk_ppe *pp hwe->ib1 &= ~MTK_FOE_IB1_STATE; hwe->ib1 |= FIELD_PREP(MTK_FOE_IB1_STATE, MTK_FOE_STATE_INVALID); dma_wmb(); diff --git a/target/linux/generic/backport-5.15/733-v6.4-21-net-mtk_eth_soc-use-WO-firmware-for-MT7981.patch b/target/linux/generic/backport-5.15/733-v6.4-22-net-mtk_eth_soc-use-WO-firmware-for-MT7981.patch similarity index 100% rename from target/linux/generic/backport-5.15/733-v6.4-21-net-mtk_eth_soc-use-WO-firmware-for-MT7981.patch rename to target/linux/generic/backport-5.15/733-v6.4-22-net-mtk_eth_soc-use-WO-firmware-for-MT7981.patch diff --git a/target/linux/generic/backport-5.15/733-v6.4-22-net-ethernet-mtk_eth_soc-fix-NULL-pointer-dereferenc.patch b/target/linux/generic/backport-5.15/733-v6.4-23-net-ethernet-mtk_eth_soc-fix-NULL-pointer-dereferenc.patch similarity index 100% rename from target/linux/generic/backport-5.15/733-v6.4-22-net-ethernet-mtk_eth_soc-fix-NULL-pointer-dereferenc.patch rename to target/linux/generic/backport-5.15/733-v6.4-23-net-ethernet-mtk_eth_soc-fix-NULL-pointer-dereferenc.patch diff --git a/target/linux/generic/pending-6.1/731-net-ethernet-mediatek-ppe-add-support-for-flow-accou.patch b/target/linux/generic/backport-5.15/733-v6.4-24-net-ethernet-mtk_eth_soc-ppe-add-support-for-flow-ac.patch similarity index 94% rename from target/linux/generic/pending-6.1/731-net-ethernet-mediatek-ppe-add-support-for-flow-accou.patch rename to target/linux/generic/backport-5.15/733-v6.4-24-net-ethernet-mtk_eth_soc-ppe-add-support-for-flow-ac.patch index 4b4ffc63164..51ebcfe8f11 100644 --- a/target/linux/generic/pending-6.1/731-net-ethernet-mediatek-ppe-add-support-for-flow-accou.patch +++ b/target/linux/generic/backport-5.15/733-v6.4-24-net-ethernet-mtk_eth_soc-ppe-add-support-for-flow-ac.patch @@ -53,7 +53,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -4689,8 +4689,8 @@ static int mtk_probe(struct platform_dev +@@ -4635,8 +4635,8 @@ static int mtk_probe(struct platform_dev for (i = 0; i < num_ppe; i++) { u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400; @@ -64,7 +64,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov if (!eth->ppe[i]) { err = -ENOMEM; goto err_deinit_ppe; -@@ -4816,6 +4816,7 @@ static const struct mtk_soc_data mt7622_ +@@ -4762,6 +4762,7 @@ static const struct mtk_soc_data mt7622_ .required_pctl = false, .offload_version = 2, .hash_offset = 2, @@ -72,7 +72,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, .txrx = { .txd_size = sizeof(struct mtk_tx_dma), -@@ -4853,6 +4854,7 @@ static const struct mtk_soc_data mt7629_ +@@ -4799,6 +4800,7 @@ static const struct mtk_soc_data mt7629_ .hw_features = MTK_HW_FEATURES, .required_clks = MT7629_CLKS_BITMAP, .required_pctl = false, @@ -80,7 +80,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov .txrx = { .txd_size = sizeof(struct mtk_tx_dma), .rxd_size = sizeof(struct mtk_rx_dma), -@@ -4873,6 +4875,7 @@ static const struct mtk_soc_data mt7981_ +@@ -4819,6 +4821,7 @@ static const struct mtk_soc_data mt7981_ .offload_version = 2, .hash_offset = 4, .foe_entry_size = sizeof(struct mtk_foe_entry), @@ -88,7 +88,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov .txrx = { .txd_size = sizeof(struct mtk_tx_dma_v2), .rxd_size = sizeof(struct mtk_rx_dma_v2), -@@ -4893,6 +4896,7 @@ static const struct mtk_soc_data mt7986_ +@@ -4839,6 +4842,7 @@ static const struct mtk_soc_data mt7986_ .offload_version = 2, .hash_offset = 4, .foe_entry_size = sizeof(struct mtk_foe_entry), @@ -98,7 +98,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov .rxd_size = sizeof(struct mtk_rx_dma_v2), --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -1017,6 +1017,8 @@ struct mtk_reg_map { +@@ -1008,6 +1008,8 @@ struct mtk_reg_map { * the extra setup for those pins used by GMAC. * @hash_offset Flow table hash offset. * @foe_entry_size Foe table entry size. @@ -107,7 +107,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov * @txd_size Tx DMA descriptor size. * @rxd_size Rx DMA descriptor size. * @rx_irq_done_mask Rx irq done register mask. -@@ -1034,6 +1036,7 @@ struct mtk_soc_data { +@@ -1025,6 +1027,7 @@ struct mtk_soc_data { u8 hash_offset; u16 foe_entry_size; netdev_features_t hw_features; @@ -166,7 +166,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov static void mtk_ppe_cache_clear(struct mtk_ppe *ppe) { ppe_set(ppe, MTK_PPE_CACHE_CTL, MTK_PPE_CACHE_CTL_CLEAR); -@@ -459,6 +501,13 @@ __mtk_foe_entry_clear(struct mtk_ppe *pp +@@ -465,6 +507,13 @@ __mtk_foe_entry_clear(struct mtk_ppe *pp hwe->ib1 |= FIELD_PREP(MTK_FOE_IB1_STATE, MTK_FOE_STATE_INVALID); dma_wmb(); mtk_ppe_cache_clear(ppe); @@ -180,7 +180,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov } entry->hash = 0xffff; -@@ -566,6 +615,9 @@ __mtk_foe_entry_commit(struct mtk_ppe *p +@@ -572,6 +621,9 @@ __mtk_foe_entry_commit(struct mtk_ppe *p wmb(); hwe->ib1 = entry->ib1; @@ -190,7 +190,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov dma_wmb(); mtk_ppe_cache_clear(ppe); -@@ -757,11 +809,39 @@ int mtk_ppe_prepare_reset(struct mtk_ppe +@@ -763,11 +815,39 @@ int mtk_ppe_prepare_reset(struct mtk_ppe return mtk_ppe_wait_busy(ppe); } @@ -232,7 +232,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov struct mtk_ppe *ppe; u32 foe_flow_size; void *foe; -@@ -778,7 +858,8 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_ +@@ -784,7 +864,8 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_ ppe->base = base; ppe->eth = eth; ppe->dev = dev; @@ -242,7 +242,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov foe = dmam_alloc_coherent(ppe->dev, MTK_PPE_ENTRIES * soc->foe_entry_size, -@@ -794,6 +875,23 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_ +@@ -800,6 +881,23 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_ if (!ppe->foe_flow) goto err_free_l2_flows; @@ -266,7 +266,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov mtk_ppe_debugfs_init(ppe, index); return ppe; -@@ -923,6 +1021,16 @@ void mtk_ppe_start(struct mtk_ppe *ppe) +@@ -929,6 +1027,16 @@ void mtk_ppe_start(struct mtk_ppe *ppe) ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT1, 0xcb777); ppe_w32(ppe, MTK_PPE_SBW_CTRL, 0x7f); } diff --git a/target/linux/generic/pending-5.15/736-06-net-ethernet-mediatek-fix-ppe-flow-accounting-for-v1.patch b/target/linux/generic/backport-5.15/733-v6.4-25-net-ethernet-mediatek-fix-ppe-flow-accounting-for-v1.patch similarity index 92% rename from target/linux/generic/pending-5.15/736-06-net-ethernet-mediatek-fix-ppe-flow-accounting-for-v1.patch rename to target/linux/generic/backport-5.15/733-v6.4-25-net-ethernet-mediatek-fix-ppe-flow-accounting-for-v1.patch index 3dfa193e707..3a02c3a718f 100644 --- a/target/linux/generic/pending-5.15/736-06-net-ethernet-mediatek-fix-ppe-flow-accounting-for-v1.patch +++ b/target/linux/generic/backport-5.15/733-v6.4-25-net-ethernet-mediatek-fix-ppe-flow-accounting-for-v1.patch @@ -11,7 +11,7 @@ Signed-off-by: Felix Fietkau --- a/drivers/net/ethernet/mediatek/mtk_ppe.c +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c -@@ -646,6 +646,7 @@ __mtk_foe_entry_commit(struct mtk_ppe *p +@@ -605,6 +605,7 @@ __mtk_foe_entry_commit(struct mtk_ppe *p struct mtk_eth *eth = ppe->eth; u16 timestamp = mtk_eth_timestamp(eth); struct mtk_foe_entry *hwe; @@ -19,7 +19,7 @@ Signed-off-by: Felix Fietkau if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { entry->ib1 &= ~MTK_FOE_IB1_BIND_TIMESTAMP_V2; -@@ -662,8 +663,13 @@ __mtk_foe_entry_commit(struct mtk_ppe *p +@@ -621,8 +622,13 @@ __mtk_foe_entry_commit(struct mtk_ppe *p wmb(); hwe->ib1 = entry->ib1; diff --git a/target/linux/generic/pending-5.15/732-00-net-ethernet-mtk_eth_soc-drop-generic-vlan-rx-offloa.patch b/target/linux/generic/backport-5.15/733-v6.4-26-net-ethernet-mtk_eth_soc-drop-generic-vlan-rx-offloa.patch similarity index 100% rename from target/linux/generic/pending-5.15/732-00-net-ethernet-mtk_eth_soc-drop-generic-vlan-rx-offloa.patch rename to target/linux/generic/backport-5.15/733-v6.4-26-net-ethernet-mtk_eth_soc-drop-generic-vlan-rx-offloa.patch diff --git a/target/linux/generic/backport-5.15/733-v6.5-27-net-ethernet-mtk_eth_soc-always-mtk_get_ib1_pkt_type.patch b/target/linux/generic/backport-5.15/733-v6.5-27-net-ethernet-mtk_eth_soc-always-mtk_get_ib1_pkt_type.patch new file mode 100644 index 00000000000..2704faec12b --- /dev/null +++ b/target/linux/generic/backport-5.15/733-v6.5-27-net-ethernet-mtk_eth_soc-always-mtk_get_ib1_pkt_type.patch @@ -0,0 +1,31 @@ +From b804f765485109f9644cc05d1e8fc79ca6c6e4aa Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Wed, 19 Jul 2023 01:39:36 +0100 +Subject: [PATCH 094/250] net: ethernet: mtk_eth_soc: always + mtk_get_ib1_pkt_type + +entries and bind debugfs files would display wrong data on NETSYS_V2 and +later because instead of using mtk_get_ib1_pkt_type the driver would use +MTK_FOE_IB1_PACKET_TYPE which corresponds to NETSYS_V1(.x) SoCs. +Use mtk_get_ib1_pkt_type so entries and bind records display correctly. + +Fixes: 03a3180e5c09e ("net: ethernet: mtk_eth_soc: introduce flow offloading support for mt7986") +Signed-off-by: Daniel Golle +Acked-by: Lorenzo Bianconi +Link: https://lore.kernel.org/r/c0ae03d0182f4d27b874cbdf0059bc972c317f3c.1689727134.git.daniel@makrotopia.org +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_ppe_debugfs.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/ethernet/mediatek/mtk_ppe_debugfs.c ++++ b/drivers/net/ethernet/mediatek/mtk_ppe_debugfs.c +@@ -98,7 +98,7 @@ mtk_ppe_debugfs_foe_show(struct seq_file + + acct = mtk_foe_entry_get_mib(ppe, i, NULL); + +- type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1); ++ type = mtk_get_ib1_pkt_type(ppe->eth, entry->ib1); + seq_printf(m, "%05x %s %7s", i, + mtk_foe_entry_state_str(state), + mtk_foe_pkt_type_str(type)); diff --git a/target/linux/generic/backport-5.15/750-v6.5-01-net-ethernet-mtk_ppe-add-MTK_FOE_ENTRY_V-1-2-_SIZE-m.patch b/target/linux/generic/backport-5.15/750-v6.5-01-net-ethernet-mtk_ppe-add-MTK_FOE_ENTRY_V-1-2-_SIZE-m.patch new file mode 100644 index 00000000000..0ba8bb8ec43 --- /dev/null +++ b/target/linux/generic/backport-5.15/750-v6.5-01-net-ethernet-mtk_ppe-add-MTK_FOE_ENTRY_V-1-2-_SIZE-m.patch @@ -0,0 +1,78 @@ +From 5ea0e1312bcfebc06b5f91d1bb82b823d6395125 Mon Sep 17 00:00:00 2001 +From: Lorenzo Bianconi +Date: Wed, 19 Jul 2023 12:29:49 +0200 +Subject: [PATCH 095/250] net: ethernet: mtk_ppe: add MTK_FOE_ENTRY_V{1,2}_SIZE + macros + +Introduce MTK_FOE_ENTRY_V{1,2}_SIZE macros in order to make more +explicit foe_entry size for different chipset revisions. + +Signed-off-by: Lorenzo Bianconi +Reviewed-by: Simon Horman +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 10 +++++----- + drivers/net/ethernet/mediatek/mtk_ppe.h | 3 +++ + 2 files changed, 8 insertions(+), 5 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -4711,7 +4711,7 @@ static const struct mtk_soc_data mt7621_ + .required_pctl = false, + .offload_version = 1, + .hash_offset = 2, +- .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, ++ .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma), + .rxd_size = sizeof(struct mtk_rx_dma), +@@ -4732,7 +4732,7 @@ static const struct mtk_soc_data mt7622_ + .offload_version = 2, + .hash_offset = 2, + .has_accounting = true, +- .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, ++ .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma), + .rxd_size = sizeof(struct mtk_rx_dma), +@@ -4751,7 +4751,7 @@ static const struct mtk_soc_data mt7623_ + .required_pctl = true, + .offload_version = 1, + .hash_offset = 2, +- .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, ++ .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma), + .rxd_size = sizeof(struct mtk_rx_dma), +@@ -4789,8 +4789,8 @@ static const struct mtk_soc_data mt7981_ + .required_pctl = false, + .offload_version = 2, + .hash_offset = 4, +- .foe_entry_size = sizeof(struct mtk_foe_entry), + .has_accounting = true, ++ .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma_v2), + .rxd_size = sizeof(struct mtk_rx_dma_v2), +@@ -4810,8 +4810,8 @@ static const struct mtk_soc_data mt7986_ + .required_pctl = false, + .offload_version = 2, + .hash_offset = 4, +- .foe_entry_size = sizeof(struct mtk_foe_entry), + .has_accounting = true, ++ .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma_v2), + .rxd_size = sizeof(struct mtk_rx_dma_v2), +--- a/drivers/net/ethernet/mediatek/mtk_ppe.h ++++ b/drivers/net/ethernet/mediatek/mtk_ppe.h +@@ -216,6 +216,9 @@ struct mtk_foe_ipv6_6rd { + struct mtk_foe_mac_info l2; + }; + ++#define MTK_FOE_ENTRY_V1_SIZE 80 ++#define MTK_FOE_ENTRY_V2_SIZE 96 ++ + struct mtk_foe_entry { + u32 ib1; + diff --git a/target/linux/generic/backport-5.15/750-v6.5-02-net-ethernet-mtk_eth_soc-remove-incorrect-PLL-config.patch b/target/linux/generic/backport-5.15/750-v6.5-02-net-ethernet-mtk_eth_soc-remove-incorrect-PLL-config.patch new file mode 100644 index 00000000000..681022078cb --- /dev/null +++ b/target/linux/generic/backport-5.15/750-v6.5-02-net-ethernet-mtk_eth_soc-remove-incorrect-PLL-config.patch @@ -0,0 +1,141 @@ +From 8cfa2576d79f9379d167a8994f0fca935c07a8bc Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Sat, 22 Jul 2023 21:32:49 +0100 +Subject: [PATCH 096/250] net: ethernet: mtk_eth_soc: remove incorrect PLL + configuration + +MT7623 GMAC0 attempts to configure the system clocking according to the +required speed in the .mac_config callback for non-SGMII, non-baseX and +non-TRGMII modes. + +state->speed setting has never been reliable in the .mac_config +callback - there are cases where this is not the link speed, +particularly via ethtool paths, so this has always been unreliable (as +detailed in phylink's documentation.) + +There is the additional issue that mtk_gmac0_rgmii_adjust() will only +be called if state->interface changes, which means it only configures +the system clocking on the very first .mac_config call, which will be +made when the network device is first brought up before any link is +established. + +Essentially, this code is incredibly buggy, and probably never worked. + +Moreover, checking the in-kernel DT files, it seems no platform makes +use of this code path. + +Therefore, let's remove it, and disable interface modes for port 0 that +are not SGMII, 1000base-X, 2500base-X or TRGMII on the MT7623. + +Reviewed-by: Daniel Golle +Tested-by: Daniel Golle +Tested-by: Frank Wunderlich +Signed-off-by: Russell King (Oracle) +Signed-off-by: Paolo Abeni +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 54 ++++++--------------- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 1 + + 2 files changed, 17 insertions(+), 38 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -309,7 +309,7 @@ static int mt7621_gmac0_rgmii_adjust(str + } + + static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, +- phy_interface_t interface, int speed) ++ phy_interface_t interface) + { + u32 val; + int ret; +@@ -323,26 +323,7 @@ static void mtk_gmac0_rgmii_adjust(struc + return; + } + +- val = (speed == SPEED_1000) ? +- INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100; +- mtk_w32(eth, val, INTF_MODE); +- +- regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, +- ETHSYS_TRGMII_CLK_SEL362_5, +- ETHSYS_TRGMII_CLK_SEL362_5); +- +- val = (speed == SPEED_1000) ? 250000000 : 500000000; +- ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); +- if (ret) +- dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); +- +- val = (speed == SPEED_1000) ? +- RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100; +- mtk_w32(eth, val, TRGMII_RCK_CTRL); +- +- val = (speed == SPEED_1000) ? +- TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100; +- mtk_w32(eth, val, TRGMII_TCK_CTRL); ++ dev_err(eth->dev, "Missing PLL configuration, ethernet may not work\n"); + } + + static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config, +@@ -428,17 +409,8 @@ static void mtk_mac_config(struct phylin + state->interface)) + goto err_phy; + } else { +- /* FIXME: this is incorrect. Not only does it +- * use state->speed (which is not guaranteed +- * to be correct) but it also makes use of it +- * in a code path that will only be reachable +- * when the PHY interface mode changes, not +- * when the speed changes. Consequently, RGMII +- * is probably broken. +- */ + mtk_gmac0_rgmii_adjust(mac->hw, +- state->interface, +- state->speed); ++ state->interface); + + /* mt7623_pad_clk_setup */ + for (i = 0 ; i < NUM_TRGMII_CTRL; i++) +@@ -4286,13 +4258,19 @@ static int mtk_add_mac(struct mtk_eth *e + mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | + MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD; + +- __set_bit(PHY_INTERFACE_MODE_MII, +- mac->phylink_config.supported_interfaces); +- __set_bit(PHY_INTERFACE_MODE_GMII, +- mac->phylink_config.supported_interfaces); ++ /* MT7623 gmac0 is now missing its speed-specific PLL configuration ++ * in its .mac_config method (since state->speed is not valid there. ++ * Disable support for MII, GMII and RGMII. ++ */ ++ if (!mac->hw->soc->disable_pll_modes || mac->id != 0) { ++ __set_bit(PHY_INTERFACE_MODE_MII, ++ mac->phylink_config.supported_interfaces); ++ __set_bit(PHY_INTERFACE_MODE_GMII, ++ mac->phylink_config.supported_interfaces); + +- if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) +- phy_interface_set_rgmii(mac->phylink_config.supported_interfaces); ++ if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) ++ phy_interface_set_rgmii(mac->phylink_config.supported_interfaces); ++ } + + if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id) + __set_bit(PHY_INTERFACE_MODE_TRGMII, +@@ -4752,6 +4730,7 @@ static const struct mtk_soc_data mt7623_ + .offload_version = 1, + .hash_offset = 2, + .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, ++ .disable_pll_modes = true, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma), + .rxd_size = sizeof(struct mtk_rx_dma), +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -1027,6 +1027,7 @@ struct mtk_soc_data { + u16 foe_entry_size; + netdev_features_t hw_features; + bool has_accounting; ++ bool disable_pll_modes; + struct { + u32 txd_size; + u32 rxd_size; diff --git a/target/linux/generic/backport-5.15/750-v6.5-03-net-ethernet-mtk_eth_soc-remove-mac_pcs_get_state-an.patch b/target/linux/generic/backport-5.15/750-v6.5-03-net-ethernet-mtk_eth_soc-remove-mac_pcs_get_state-an.patch new file mode 100644 index 00000000000..816f98ecc53 --- /dev/null +++ b/target/linux/generic/backport-5.15/750-v6.5-03-net-ethernet-mtk_eth_soc-remove-mac_pcs_get_state-an.patch @@ -0,0 +1,81 @@ +From a4c2233b1e4359b6c64b6f9ba98c8718a11fffee Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Sat, 22 Jul 2023 21:32:54 +0100 +Subject: [PATCH 097/250] net: ethernet: mtk_eth_soc: remove mac_pcs_get_state + and modernise + +Remove the .mac_pcs_get_state function, since as far as I can tell is +never called - no DT appears to specify an in-band-status management +nor SFP support for this driver. + +Removal of this, along with the previous patch to remove the incorrect +clocking configuration, means that the driver becomes non-legacy, so +we can remove the "legacy_pre_march2020" status from this driver. + +Reviewed-by: Daniel Golle +Tested-by: Daniel Golle +Tested-by: Frank Wunderlich +Signed-off-by: Russell King (Oracle) +Signed-off-by: Paolo Abeni +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 35 --------------------- + 1 file changed, 35 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -512,38 +512,6 @@ static int mtk_mac_finish(struct phylink + return 0; + } + +-static void mtk_mac_pcs_get_state(struct phylink_config *config, +- struct phylink_link_state *state) +-{ +- struct mtk_mac *mac = container_of(config, struct mtk_mac, +- phylink_config); +- u32 pmsr = mtk_r32(mac->hw, MTK_MAC_MSR(mac->id)); +- +- state->link = (pmsr & MAC_MSR_LINK); +- state->duplex = (pmsr & MAC_MSR_DPX) >> 1; +- +- switch (pmsr & (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)) { +- case 0: +- state->speed = SPEED_10; +- break; +- case MAC_MSR_SPEED_100: +- state->speed = SPEED_100; +- break; +- case MAC_MSR_SPEED_1000: +- state->speed = SPEED_1000; +- break; +- default: +- state->speed = SPEED_UNKNOWN; +- break; +- } +- +- state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX); +- if (pmsr & MAC_MSR_RX_FC) +- state->pause |= MLO_PAUSE_RX; +- if (pmsr & MAC_MSR_TX_FC) +- state->pause |= MLO_PAUSE_TX; +-} +- + static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode, + phy_interface_t interface) + { +@@ -666,7 +634,6 @@ static void mtk_mac_link_up(struct phyli + static const struct phylink_mac_ops mtk_phylink_ops = { + .validate = phylink_generic_validate, + .mac_select_pcs = mtk_mac_select_pcs, +- .mac_pcs_get_state = mtk_mac_pcs_get_state, + .mac_config = mtk_mac_config, + .mac_finish = mtk_mac_finish, + .mac_link_down = mtk_mac_link_down, +@@ -4253,8 +4220,6 @@ static int mtk_add_mac(struct mtk_eth *e + + mac->phylink_config.dev = ð->netdev[id]->dev; + mac->phylink_config.type = PHYLINK_NETDEV; +- /* This driver makes use of state->speed in mac_config */ +- mac->phylink_config.legacy_pre_march2020 = true; + mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | + MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD; + diff --git a/target/linux/generic/backport-5.15/750-v6.5-05-net-ethernet-mtk_eth_soc-add-version-in-mtk_soc_data.patch b/target/linux/generic/backport-5.15/750-v6.5-05-net-ethernet-mtk_eth_soc-add-version-in-mtk_soc_data.patch new file mode 100644 index 00000000000..d836acc4b04 --- /dev/null +++ b/target/linux/generic/backport-5.15/750-v6.5-05-net-ethernet-mtk_eth_soc-add-version-in-mtk_soc_data.patch @@ -0,0 +1,550 @@ +From 5d8d05fbf804b4485646d39551ac27452e45afd3 Mon Sep 17 00:00:00 2001 +From: Lorenzo Bianconi +Date: Tue, 25 Jul 2023 01:52:02 +0100 +Subject: [PATCH 099/250] net: ethernet: mtk_eth_soc: add version in + mtk_soc_data + +Introduce version field in mtk_soc_data data structure in order to +make mtk_eth driver easier to maintain for chipset configuration +codebase. Get rid of MTK_NETSYS_V2 bit in chip capabilities. +This is a preliminary patch to introduce support for MT7988 SoC. + +Signed-off-by: Lorenzo Bianconi +Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/e52fae302ca135436e5cdd26d38d87be2da63055.1690246066.git.daniel@makrotopia.org +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 55 +++++++++++-------- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 36 +++++++----- + drivers/net/ethernet/mediatek/mtk_ppe.c | 18 +++--- + .../net/ethernet/mediatek/mtk_ppe_offload.c | 2 +- + drivers/net/ethernet/mediatek/mtk_wed.c | 4 +- + 5 files changed, 66 insertions(+), 49 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -537,7 +537,7 @@ static void mtk_set_queue_speed(struct m + FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | + FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | + MTK_QTX_SCH_LEAKY_BUCKET_SIZE; +- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v1(eth)) + val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; + + if (IS_ENABLED(CONFIG_SOC_MT7621)) { +@@ -912,7 +912,7 @@ static bool mtk_rx_get_desc(struct mtk_e + rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); + rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); + rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ if (mtk_is_netsys_v2_or_greater(eth)) { + rxd->rxd5 = READ_ONCE(dma_rxd->rxd5); + rxd->rxd6 = READ_ONCE(dma_rxd->rxd6); + } +@@ -970,7 +970,7 @@ static int mtk_init_fq_dma(struct mtk_et + + txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE); + txd->txd4 = 0; +- if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) { ++ if (mtk_is_netsys_v2_or_greater(eth)) { + txd->txd5 = 0; + txd->txd6 = 0; + txd->txd7 = 0; +@@ -1159,7 +1159,7 @@ static void mtk_tx_set_dma_desc(struct n + struct mtk_mac *mac = netdev_priv(dev); + struct mtk_eth *eth = mac->hw; + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + mtk_tx_set_dma_desc_v2(dev, txd, info); + else + mtk_tx_set_dma_desc_v1(dev, txd, info); +@@ -1466,7 +1466,7 @@ static void mtk_update_rx_cpu_idx(struct + + static bool mtk_page_pool_enabled(struct mtk_eth *eth) + { +- return MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2); ++ return eth->soc->version == 2; + } + + static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth, +@@ -1806,7 +1806,7 @@ static int mtk_poll_rx(struct napi_struc + break; + + /* find out which mac the packet come from. values start at 1 */ +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1; + else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && + !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) +@@ -1902,7 +1902,7 @@ static int mtk_poll_rx(struct napi_struc + skb->dev = netdev; + bytes += skb->len; + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ if (mtk_is_netsys_v2_or_greater(eth)) { + reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5); + hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY; + if (hash != MTK_RXD5_FOE_ENTRY) +@@ -1927,8 +1927,8 @@ static int mtk_poll_rx(struct napi_struc + /* When using VLAN untagging in combination with DSA, the + * hardware treats the MTK special tag as a VLAN and untags it. + */ +- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) && +- (trxd.rxd2 & RX_DMA_VTAG) && netdev_uses_dsa(netdev)) { ++ if (mtk_is_netsys_v1(eth) && (trxd.rxd2 & RX_DMA_VTAG) && ++ netdev_uses_dsa(netdev)) { + unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0); + + if (port < ARRAY_SIZE(eth->dsa_meta) && +@@ -2232,7 +2232,7 @@ static int mtk_tx_alloc(struct mtk_eth * + txd->txd2 = next_ptr; + txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; + txd->txd4 = 0; +- if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) { ++ if (mtk_is_netsys_v2_or_greater(eth)) { + txd->txd5 = 0; + txd->txd6 = 0; + txd->txd7 = 0; +@@ -2285,14 +2285,14 @@ static int mtk_tx_alloc(struct mtk_eth * + FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | + FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | + MTK_QTX_SCH_LEAKY_BUCKET_SIZE; +- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v1(eth)) + val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; + mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); + ofs += MTK_QTX_OFFSET; + } + val = MTK_QDMA_TX_SCH_MAX_WFQ | (MTK_QDMA_TX_SCH_MAX_WFQ << 16); + mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate); +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate + 4); + } else { + mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0); +@@ -2419,7 +2419,7 @@ static int mtk_rx_alloc(struct mtk_eth * + + rxd->rxd3 = 0; + rxd->rxd4 = 0; +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ if (mtk_is_netsys_v2_or_greater(eth)) { + rxd->rxd5 = 0; + rxd->rxd6 = 0; + rxd->rxd7 = 0; +@@ -2967,7 +2967,7 @@ static int mtk_start_dma(struct mtk_eth + MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO | + MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE; + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + val |= MTK_MUTLI_CNT | MTK_RESV_BUF | + MTK_WCOMP_EN | MTK_DMAD_WR_WDONE | + MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN; +@@ -3111,7 +3111,7 @@ static int mtk_open(struct net_device *d + phylink_start(mac->phylink); + netif_tx_start_all_queues(dev); + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + return 0; + + if (mtk_uses_dsa(dev) && !eth->prog) { +@@ -3376,7 +3376,7 @@ static void mtk_hw_reset(struct mtk_eth + { + u32 val; + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ if (mtk_is_netsys_v2_or_greater(eth)) { + regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); + val = RSTCTRL_PPE0_V2; + } else { +@@ -3388,7 +3388,7 @@ static void mtk_hw_reset(struct mtk_eth + + ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val); + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, + 0x3ffffff); + } +@@ -3414,7 +3414,7 @@ static void mtk_hw_warm_reset(struct mtk + return; + } + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2; + else + rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0; +@@ -3584,7 +3584,7 @@ static int mtk_hw_init(struct mtk_eth *e + else + mtk_hw_reset(eth); + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ if (mtk_is_netsys_v2_or_greater(eth)) { + /* Set FE to PDMAv2 if necessary */ + val = mtk_r32(eth, MTK_FE_GLO_MISC); + mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC); +@@ -3621,7 +3621,7 @@ static int mtk_hw_init(struct mtk_eth *e + */ + val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); + mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); +- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ if (mtk_is_netsys_v1(eth)) { + val = mtk_r32(eth, MTK_CDMP_IG_CTRL); + mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL); + +@@ -3643,7 +3643,7 @@ static int mtk_hw_init(struct mtk_eth *e + mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4); + mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ if (mtk_is_netsys_v2_or_greater(eth)) { + /* PSE should not drop port8 and port9 packets from WDMA Tx */ + mtk_w32(eth, 0x00000300, PSE_DROP_CFG); + +@@ -4432,7 +4432,7 @@ static int mtk_probe(struct platform_dev + } + } + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ if (mtk_is_netsys_v2_or_greater(eth)) { + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + err = -EINVAL; +@@ -4540,9 +4540,8 @@ static int mtk_probe(struct platform_dev + } + + if (eth->soc->offload_version) { +- u32 num_ppe; ++ u32 num_ppe = mtk_is_netsys_v2_or_greater(eth) ? 2 : 1; + +- num_ppe = MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ? 2 : 1; + num_ppe = min_t(u32, ARRAY_SIZE(eth->ppe), num_ppe); + for (i = 0; i < num_ppe; i++) { + u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400; +@@ -4636,6 +4635,7 @@ static const struct mtk_soc_data mt2701_ + .hw_features = MTK_HW_FEATURES, + .required_clks = MT7623_CLKS_BITMAP, + .required_pctl = true, ++ .version = 1, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma), + .rxd_size = sizeof(struct mtk_rx_dma), +@@ -4652,6 +4652,7 @@ static const struct mtk_soc_data mt7621_ + .hw_features = MTK_HW_FEATURES, + .required_clks = MT7621_CLKS_BITMAP, + .required_pctl = false, ++ .version = 1, + .offload_version = 1, + .hash_offset = 2, + .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, +@@ -4672,6 +4673,7 @@ static const struct mtk_soc_data mt7622_ + .hw_features = MTK_HW_FEATURES, + .required_clks = MT7622_CLKS_BITMAP, + .required_pctl = false, ++ .version = 1, + .offload_version = 2, + .hash_offset = 2, + .has_accounting = true, +@@ -4692,6 +4694,7 @@ static const struct mtk_soc_data mt7623_ + .hw_features = MTK_HW_FEATURES, + .required_clks = MT7623_CLKS_BITMAP, + .required_pctl = true, ++ .version = 1, + .offload_version = 1, + .hash_offset = 2, + .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, +@@ -4714,6 +4717,7 @@ static const struct mtk_soc_data mt7629_ + .required_clks = MT7629_CLKS_BITMAP, + .required_pctl = false, + .has_accounting = true, ++ .version = 1, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma), + .rxd_size = sizeof(struct mtk_rx_dma), +@@ -4731,6 +4735,7 @@ static const struct mtk_soc_data mt7981_ + .hw_features = MTK_HW_FEATURES, + .required_clks = MT7981_CLKS_BITMAP, + .required_pctl = false, ++ .version = 2, + .offload_version = 2, + .hash_offset = 4, + .has_accounting = true, +@@ -4752,6 +4757,7 @@ static const struct mtk_soc_data mt7986_ + .hw_features = MTK_HW_FEATURES, + .required_clks = MT7986_CLKS_BITMAP, + .required_pctl = false, ++ .version = 2, + .offload_version = 2, + .hash_offset = 4, + .has_accounting = true, +@@ -4772,6 +4778,7 @@ static const struct mtk_soc_data rt5350_ + .hw_features = MTK_HW_FEATURES_MT7628, + .required_clks = MT7628_CLKS_BITMAP, + .required_pctl = false, ++ .version = 1, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma), + .rxd_size = sizeof(struct mtk_rx_dma), +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -817,7 +817,6 @@ enum mkt_eth_capabilities { + MTK_SHARED_INT_BIT, + MTK_TRGMII_MT7621_CLK_BIT, + MTK_QDMA_BIT, +- MTK_NETSYS_V2_BIT, + MTK_SOC_MT7628_BIT, + MTK_RSTCTRL_PPE1_BIT, + MTK_U3_COPHY_V2_BIT, +@@ -852,7 +851,6 @@ enum mkt_eth_capabilities { + #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT) + #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) + #define MTK_QDMA BIT(MTK_QDMA_BIT) +-#define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) + #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) + #define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT) + #define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT) +@@ -931,11 +929,11 @@ enum mkt_eth_capabilities { + #define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ + MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ + MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \ +- MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1) ++ MTK_RSTCTRL_PPE1) + + #define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ + MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ +- MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1) ++ MTK_RSTCTRL_PPE1) + + struct mtk_tx_dma_desc_info { + dma_addr_t addr; +@@ -1006,6 +1004,7 @@ struct mtk_reg_map { + * @required_pctl A bool value to show whether the SoC requires + * the extra setup for those pins used by GMAC. + * @hash_offset Flow table hash offset. ++ * @version SoC version. + * @foe_entry_size Foe table entry size. + * @has_accounting Bool indicating support for accounting of + * offloaded flows. +@@ -1024,6 +1023,7 @@ struct mtk_soc_data { + bool required_pctl; + u8 offload_version; + u8 hash_offset; ++ u8 version; + u16 foe_entry_size; + netdev_features_t hw_features; + bool has_accounting; +@@ -1180,6 +1180,16 @@ struct mtk_mac { + /* the struct describing the SoC. these are declared in the soc_xyz.c files */ + extern const struct of_device_id of_mtk_match[]; + ++static inline bool mtk_is_netsys_v1(struct mtk_eth *eth) ++{ ++ return eth->soc->version == 1; ++} ++ ++static inline bool mtk_is_netsys_v2_or_greater(struct mtk_eth *eth) ++{ ++ return eth->soc->version > 1; ++} ++ + static inline struct mtk_foe_entry * + mtk_foe_get_entry(struct mtk_ppe *ppe, u16 hash) + { +@@ -1190,7 +1200,7 @@ mtk_foe_get_entry(struct mtk_ppe *ppe, u + + static inline u32 mtk_get_ib1_ts_mask(struct mtk_eth *eth) + { +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + return MTK_FOE_IB1_BIND_TIMESTAMP_V2; + + return MTK_FOE_IB1_BIND_TIMESTAMP; +@@ -1198,7 +1208,7 @@ static inline u32 mtk_get_ib1_ts_mask(st + + static inline u32 mtk_get_ib1_ppoe_mask(struct mtk_eth *eth) + { +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + return MTK_FOE_IB1_BIND_PPPOE_V2; + + return MTK_FOE_IB1_BIND_PPPOE; +@@ -1206,7 +1216,7 @@ static inline u32 mtk_get_ib1_ppoe_mask( + + static inline u32 mtk_get_ib1_vlan_tag_mask(struct mtk_eth *eth) + { +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + return MTK_FOE_IB1_BIND_VLAN_TAG_V2; + + return MTK_FOE_IB1_BIND_VLAN_TAG; +@@ -1214,7 +1224,7 @@ static inline u32 mtk_get_ib1_vlan_tag_m + + static inline u32 mtk_get_ib1_vlan_layer_mask(struct mtk_eth *eth) + { +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + return MTK_FOE_IB1_BIND_VLAN_LAYER_V2; + + return MTK_FOE_IB1_BIND_VLAN_LAYER; +@@ -1222,7 +1232,7 @@ static inline u32 mtk_get_ib1_vlan_layer + + static inline u32 mtk_prep_ib1_vlan_layer(struct mtk_eth *eth, u32 val) + { +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val); + + return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, val); +@@ -1230,7 +1240,7 @@ static inline u32 mtk_prep_ib1_vlan_laye + + static inline u32 mtk_get_ib1_vlan_layer(struct mtk_eth *eth, u32 val) + { +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val); + + return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER, val); +@@ -1238,7 +1248,7 @@ static inline u32 mtk_get_ib1_vlan_layer + + static inline u32 mtk_get_ib1_pkt_type_mask(struct mtk_eth *eth) + { +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + return MTK_FOE_IB1_PACKET_TYPE_V2; + + return MTK_FOE_IB1_PACKET_TYPE; +@@ -1246,7 +1256,7 @@ static inline u32 mtk_get_ib1_pkt_type_m + + static inline u32 mtk_get_ib1_pkt_type(struct mtk_eth *eth, u32 val) + { +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE_V2, val); + + return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, val); +@@ -1254,7 +1264,7 @@ static inline u32 mtk_get_ib1_pkt_type(s + + static inline u32 mtk_get_ib2_multicast_mask(struct mtk_eth *eth) + { +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + return MTK_FOE_IB2_MULTICAST_V2; + + return MTK_FOE_IB2_MULTICAST; +--- a/drivers/net/ethernet/mediatek/mtk_ppe.c ++++ b/drivers/net/ethernet/mediatek/mtk_ppe.c +@@ -207,7 +207,7 @@ int mtk_foe_entry_prepare(struct mtk_eth + + memset(entry, 0, sizeof(*entry)); + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ if (mtk_is_netsys_v2_or_greater(eth)) { + val = FIELD_PREP(MTK_FOE_IB1_STATE, MTK_FOE_STATE_BIND) | + FIELD_PREP(MTK_FOE_IB1_PACKET_TYPE_V2, type) | + FIELD_PREP(MTK_FOE_IB1_UDP, l4proto == IPPROTO_UDP) | +@@ -271,7 +271,7 @@ int mtk_foe_entry_set_pse_port(struct mt + u32 *ib2 = mtk_foe_entry_ib2(eth, entry); + u32 val = *ib2; + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ if (mtk_is_netsys_v2_or_greater(eth)) { + val &= ~MTK_FOE_IB2_DEST_PORT_V2; + val |= FIELD_PREP(MTK_FOE_IB2_DEST_PORT_V2, port); + } else { +@@ -422,7 +422,7 @@ int mtk_foe_entry_set_wdma(struct mtk_et + struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(eth, entry); + u32 *ib2 = mtk_foe_entry_ib2(eth, entry); + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ if (mtk_is_netsys_v2_or_greater(eth)) { + *ib2 &= ~MTK_FOE_IB2_PORT_MG_V2; + *ib2 |= FIELD_PREP(MTK_FOE_IB2_RX_IDX, txq) | + MTK_FOE_IB2_WDMA_WINFO_V2; +@@ -452,7 +452,7 @@ int mtk_foe_entry_set_queue(struct mtk_e + { + u32 *ib2 = mtk_foe_entry_ib2(eth, entry); + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ if (mtk_is_netsys_v2_or_greater(eth)) { + *ib2 &= ~MTK_FOE_IB2_QID_V2; + *ib2 |= FIELD_PREP(MTK_FOE_IB2_QID_V2, queue); + *ib2 |= MTK_FOE_IB2_PSE_QOS_V2; +@@ -607,7 +607,7 @@ __mtk_foe_entry_commit(struct mtk_ppe *p + struct mtk_foe_entry *hwe; + u32 val; + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ if (mtk_is_netsys_v2_or_greater(eth)) { + entry->ib1 &= ~MTK_FOE_IB1_BIND_TIMESTAMP_V2; + entry->ib1 |= FIELD_PREP(MTK_FOE_IB1_BIND_TIMESTAMP_V2, + timestamp); +@@ -623,7 +623,7 @@ __mtk_foe_entry_commit(struct mtk_ppe *p + hwe->ib1 = entry->ib1; + + if (ppe->accounting) { +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + val = MTK_FOE_IB2_MIB_CNT_V2; + else + val = MTK_FOE_IB2_MIB_CNT; +@@ -971,7 +971,7 @@ void mtk_ppe_start(struct mtk_ppe *ppe) + MTK_PPE_SCAN_MODE_KEEPALIVE_AGE) | + FIELD_PREP(MTK_PPE_TB_CFG_ENTRY_NUM, + MTK_PPE_ENTRIES_SHIFT); +- if (MTK_HAS_CAPS(ppe->eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(ppe->eth)) + val |= MTK_PPE_TB_CFG_INFO_SEL; + ppe_w32(ppe, MTK_PPE_TB_CFG, val); + +@@ -987,7 +987,7 @@ void mtk_ppe_start(struct mtk_ppe *ppe) + MTK_PPE_FLOW_CFG_IP4_NAPT | + MTK_PPE_FLOW_CFG_IP4_DSLITE | + MTK_PPE_FLOW_CFG_IP4_NAT_FRAG; +- if (MTK_HAS_CAPS(ppe->eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(ppe->eth)) + val |= MTK_PPE_MD_TOAP_BYP_CRSN0 | + MTK_PPE_MD_TOAP_BYP_CRSN1 | + MTK_PPE_MD_TOAP_BYP_CRSN2 | +@@ -1029,7 +1029,7 @@ void mtk_ppe_start(struct mtk_ppe *ppe) + + ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT, 0); + +- if (MTK_HAS_CAPS(ppe->eth->soc->caps, MTK_NETSYS_V2)) { ++ if (mtk_is_netsys_v2_or_greater(ppe->eth)) { + ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT1, 0xcb777); + ppe_w32(ppe, MTK_PPE_SBW_CTRL, 0x7f); + } +--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c ++++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c +@@ -193,7 +193,7 @@ mtk_flow_set_output_device(struct mtk_et + if (mtk_flow_get_wdma_info(dev, dest_mac, &info) == 0) { + mtk_foe_entry_set_wdma(eth, foe, info.wdma_idx, info.queue, + info.bss, info.wcid); +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ if (mtk_is_netsys_v2_or_greater(eth)) { + switch (info.wdma_idx) { + case 0: + pse_port = 8; +--- a/drivers/net/ethernet/mediatek/mtk_wed.c ++++ b/drivers/net/ethernet/mediatek/mtk_wed.c +@@ -1091,7 +1091,7 @@ mtk_wed_rx_reset(struct mtk_wed_device * + } else { + struct mtk_eth *eth = dev->hw->eth; + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + wed_set(dev, MTK_WED_RESET_IDX, + MTK_WED_RESET_IDX_RX_V2); + else +@@ -1813,7 +1813,7 @@ void mtk_wed_add_hw(struct device_node * + hw->wdma = wdma; + hw->index = index; + hw->irq = irq; +- hw->version = MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ? 2 : 1; ++ hw->version = mtk_is_netsys_v1(eth) ? 1 : 2; + + if (hw->version == 1) { + hw->mirror = syscon_regmap_lookup_by_phandle(eth_np, diff --git a/target/linux/generic/backport-5.15/750-v6.5-06-net-ethernet-mtk_eth_soc-increase-MAX_DEVS-to-3.patch b/target/linux/generic/backport-5.15/750-v6.5-06-net-ethernet-mtk_eth_soc-increase-MAX_DEVS-to-3.patch new file mode 100644 index 00000000000..5a08b9dddf3 --- /dev/null +++ b/target/linux/generic/backport-5.15/750-v6.5-06-net-ethernet-mtk_eth_soc-increase-MAX_DEVS-to-3.patch @@ -0,0 +1,29 @@ +From f8fb8dbd158c585be7574faf92db7d614b6722ff Mon Sep 17 00:00:00 2001 +From: Lorenzo Bianconi +Date: Tue, 25 Jul 2023 01:52:27 +0100 +Subject: [PATCH 100/250] net: ethernet: mtk_eth_soc: increase MAX_DEVS to 3 + +This is a preliminary patch to add MT7988 SoC support since it runs 3 +macs instead of 2. + +Signed-off-by: Lorenzo Bianconi +Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/3563e5fab367e7d79a7f1296fabaa5c20f202d7a.1690246066.git.daniel@makrotopia.org +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -1040,8 +1040,8 @@ struct mtk_soc_data { + + #define MTK_DMA_MONITOR_TIMEOUT msecs_to_jiffies(1000) + +-/* currently no SoC has more than 2 macs */ +-#define MTK_MAX_DEVS 2 ++/* currently no SoC has more than 3 macs */ ++#define MTK_MAX_DEVS 3 + + /* struct mtk_eth - This is the main datasructure for holding the state + * of the driver diff --git a/target/linux/generic/pending-5.15/737-03-net-ethernet-mtk_eth_soc-rely-on-num_devs-and-remove.patch b/target/linux/generic/backport-5.15/750-v6.5-07-net-ethernet-mtk_eth_soc-rely-on-MTK_MAX_DEVS-and-re.patch similarity index 50% rename from target/linux/generic/pending-5.15/737-03-net-ethernet-mtk_eth_soc-rely-on-num_devs-and-remove.patch rename to target/linux/generic/backport-5.15/750-v6.5-07-net-ethernet-mtk_eth_soc-rely-on-MTK_MAX_DEVS-and-re.patch index b11915ec104..58729cec521 100644 --- a/target/linux/generic/pending-5.15/737-03-net-ethernet-mtk_eth_soc-rely-on-num_devs-and-remove.patch +++ b/target/linux/generic/backport-5.15/750-v6.5-07-net-ethernet-mtk_eth_soc-rely-on-MTK_MAX_DEVS-and-re.patch @@ -1,143 +1,176 @@ -From 4e35e80750b33727e606be9e7ce447bde2e0deb7 Mon Sep 17 00:00:00 2001 +From 856be974290f28d7943be2ac5a382c4139486196 Mon Sep 17 00:00:00 2001 From: Lorenzo Bianconi -Date: Tue, 7 Mar 2023 15:55:35 +0000 -Subject: [PATCH 3/7] net: ethernet: mtk_eth_soc: rely on num_devs and remove - MTK_MAC_COUNT +Date: Tue, 25 Jul 2023 01:52:44 +0100 +Subject: [PATCH 101/250] net: ethernet: mtk_eth_soc: rely on MTK_MAX_DEVS and + remove MTK_MAC_COUNT -Get rid of MTK_MAC_COUNT since it is a duplicated of eth->soc->num_devs. +Get rid of MTK_MAC_COUNT since it is a duplicated of MTK_MAX_DEVS. Signed-off-by: Lorenzo Bianconi Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/1856f4266f2fc80677807b1bad867659e7b00c65.1690246066.git.daniel@makrotopia.org +Signed-off-by: Jakub Kicinski --- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 30 ++++++++++----------- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 49 ++++++++++++--------- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 1 - - 2 files changed, 15 insertions(+), 16 deletions(-) + 2 files changed, 27 insertions(+), 23 deletions(-) --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -900,7 +900,7 @@ static void mtk_stats_update(struct mtk_ +@@ -838,7 +838,7 @@ static void mtk_stats_update(struct mtk_ { int i; - for (i = 0; i < MTK_MAC_COUNT; i++) { -+ for (i = 0; i < eth->soc->num_devs; i++) { ++ for (i = 0; i < MTK_MAX_DEVS; i++) { if (!eth->mac[i] || !eth->mac[i]->hw_stats) continue; if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { -@@ -1403,7 +1403,7 @@ static int mtk_queue_stopped(struct mtk_ +@@ -1341,7 +1341,7 @@ static int mtk_queue_stopped(struct mtk_ { int i; - for (i = 0; i < MTK_MAC_COUNT; i++) { -+ for (i = 0; i < eth->soc->num_devs; i++) { ++ for (i = 0; i < MTK_MAX_DEVS; i++) { if (!eth->netdev[i]) continue; if (netif_queue_stopped(eth->netdev[i])) -@@ -1417,7 +1417,7 @@ static void mtk_wake_queue(struct mtk_et +@@ -1355,7 +1355,7 @@ static void mtk_wake_queue(struct mtk_et { int i; - for (i = 0; i < MTK_MAC_COUNT; i++) { -+ for (i = 0; i < eth->soc->num_devs; i++) { ++ for (i = 0; i < MTK_MAX_DEVS; i++) { if (!eth->netdev[i]) continue; netif_tx_wake_all_queues(eth->netdev[i]); -@@ -1908,7 +1908,7 @@ static int mtk_poll_rx(struct napi_struc +@@ -1812,7 +1812,7 @@ static int mtk_poll_rx(struct napi_struc !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1; - if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT || -+ if (unlikely(mac < 0 || mac >= eth->soc->num_devs || ++ if (unlikely(mac < 0 || mac >= MTK_MAX_DEVS || !eth->netdev[mac])) goto release_desc; -@@ -2937,7 +2937,7 @@ static void mtk_dma_free(struct mtk_eth +@@ -2841,7 +2841,7 @@ static void mtk_dma_free(struct mtk_eth const struct mtk_soc_data *soc = eth->soc; int i; - for (i = 0; i < MTK_MAC_COUNT; i++) -+ for (i = 0; i < soc->num_devs; i++) ++ for (i = 0; i < MTK_MAX_DEVS; i++) if (eth->netdev[i]) netdev_reset_queue(eth->netdev[i]); if (eth->scratch_ring) { -@@ -3091,7 +3091,7 @@ static void mtk_gdm_config(struct mtk_et +@@ -2995,8 +2995,13 @@ static void mtk_gdm_config(struct mtk_et if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) return; - for (i = 0; i < MTK_MAC_COUNT; i++) { -+ for (i = 0; i < eth->soc->num_devs; i++) { - u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); +- u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); ++ for (i = 0; i < MTK_MAX_DEVS; i++) { ++ u32 val; ++ ++ if (!eth->netdev[i]) ++ continue; ++ ++ val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); /* default setup the forward port to send frame to PDMA */ -@@ -3704,7 +3704,7 @@ static int mtk_hw_init(struct mtk_eth *e + val &= ~0xffff; +@@ -3006,7 +3011,7 @@ static void mtk_gdm_config(struct mtk_et + + val |= config; + +- if (eth->netdev[i] && netdev_uses_dsa(eth->netdev[i])) ++ if (netdev_uses_dsa(eth->netdev[i])) + val |= MTK_GDMA_SPECIAL_TAG; + + mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); +@@ -3605,15 +3610,15 @@ static int mtk_hw_init(struct mtk_eth *e * up with the more appropriate value when mtk_mac_config call is being * invoked. */ - for (i = 0; i < MTK_MAC_COUNT; i++) { -+ for (i = 0; i < eth->soc->num_devs; i++) { ++ for (i = 0; i < MTK_MAX_DEVS; i++) { struct net_device *dev = eth->netdev[i]; - mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); -@@ -3892,7 +3892,7 @@ static void mtk_pending_work(struct work +- mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); +- if (dev) { +- struct mtk_mac *mac = netdev_priv(dev); ++ if (!dev) ++ continue; + +- mtk_set_mcr_max_rx(mac, dev->mtu + MTK_RX_ETH_HLEN); +- } ++ mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); ++ mtk_set_mcr_max_rx(netdev_priv(dev), ++ dev->mtu + MTK_RX_ETH_HLEN); + } + + /* Indicates CDM to parse the MTK special tag from CPU +@@ -3793,7 +3798,7 @@ static void mtk_pending_work(struct work mtk_prepare_for_reset(eth); /* stop all devices to make sure that dma is properly shut down */ - for (i = 0; i < MTK_MAC_COUNT; i++) { -+ for (i = 0; i < eth->soc->num_devs; i++) { ++ for (i = 0; i < MTK_MAX_DEVS; i++) { if (!eth->netdev[i] || !netif_running(eth->netdev[i])) continue; -@@ -3908,7 +3908,7 @@ static void mtk_pending_work(struct work +@@ -3809,8 +3814,8 @@ static void mtk_pending_work(struct work mtk_hw_init(eth, true); /* restart DMA and enable IRQs */ - for (i = 0; i < MTK_MAC_COUNT; i++) { -+ for (i = 0; i < eth->soc->num_devs; i++) { - if (!test_bit(i, &restart)) +- if (!test_bit(i, &restart)) ++ for (i = 0; i < MTK_MAX_DEVS; i++) { ++ if (!eth->netdev[i] || !test_bit(i, &restart)) continue; -@@ -3936,7 +3936,7 @@ static int mtk_free_dev(struct mtk_eth * + if (mtk_open(eth->netdev[i])) { +@@ -3837,7 +3842,7 @@ static int mtk_free_dev(struct mtk_eth * { int i; - for (i = 0; i < MTK_MAC_COUNT; i++) { -+ for (i = 0; i < eth->soc->num_devs; i++) { ++ for (i = 0; i < MTK_MAX_DEVS; i++) { if (!eth->netdev[i]) continue; free_netdev(eth->netdev[i]); -@@ -3955,7 +3955,7 @@ static int mtk_unreg_dev(struct mtk_eth +@@ -3856,7 +3861,7 @@ static int mtk_unreg_dev(struct mtk_eth { int i; - for (i = 0; i < MTK_MAC_COUNT; i++) { -+ for (i = 0; i < eth->soc->num_devs; i++) { ++ for (i = 0; i < MTK_MAX_DEVS; i++) { struct mtk_mac *mac; if (!eth->netdev[i]) continue; -@@ -4259,7 +4259,7 @@ static int mtk_add_mac(struct mtk_eth *e +@@ -4157,7 +4162,7 @@ static int mtk_add_mac(struct mtk_eth *e } id = be32_to_cpup(_id); - if (id >= MTK_MAC_COUNT) { -+ if (id >= eth->soc->num_devs) { ++ if (id >= MTK_MAX_DEVS) { dev_err(eth->dev, "%d is not a valid mac id\n", id); return -EINVAL; } -@@ -4400,7 +4400,7 @@ void mtk_eth_set_dma_device(struct mtk_e +@@ -4302,7 +4307,7 @@ void mtk_eth_set_dma_device(struct mtk_e rtnl_lock(); - for (i = 0; i < MTK_MAC_COUNT; i++) { -+ for (i = 0; i < eth->soc->num_devs; i++) { ++ for (i = 0; i < MTK_MAX_DEVS; i++) { dev = eth->netdev[i]; if (!dev || !(dev->flags & IFF_UP)) -@@ -4727,7 +4727,7 @@ static int mtk_remove(struct platform_de +@@ -4610,7 +4615,7 @@ static int mtk_remove(struct platform_de int i; /* stop all devices to make sure that dma is properly shut down */ - for (i = 0; i < MTK_MAC_COUNT; i++) { -+ for (i = 0; i < eth->soc->num_devs; i++) { ++ for (i = 0; i < MTK_MAX_DEVS; i++) { if (!eth->netdev[i]) continue; mtk_stop(eth->netdev[i]); diff --git a/target/linux/generic/pending-5.15/737-04-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V3-capabilit.patch b/target/linux/generic/backport-5.15/750-v6.5-08-net-ethernet-mtk_eth_soc-add-NETSYS_V3-version-suppo.patch similarity index 63% rename from target/linux/generic/pending-5.15/737-04-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V3-capabilit.patch rename to target/linux/generic/backport-5.15/750-v6.5-08-net-ethernet-mtk_eth_soc-add-NETSYS_V3-version-suppo.patch index 54b3fd024a4..09f59c291ce 100644 --- a/target/linux/generic/pending-5.15/737-04-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V3-capabilit.patch +++ b/target/linux/generic/backport-5.15/750-v6.5-08-net-ethernet-mtk_eth_soc-add-NETSYS_V3-version-suppo.patch @@ -1,22 +1,24 @@ -From ab817f559d505329d8a413c7d29250f6d87d77a0 Mon Sep 17 00:00:00 2001 +From a41d535855976838d246c079143c948dcf0f7931 Mon Sep 17 00:00:00 2001 From: Lorenzo Bianconi -Date: Tue, 7 Mar 2023 15:55:47 +0000 -Subject: [PATCH 4/7] net: ethernet: mtk_eth_soc: add MTK_NETSYS_V3 capability - bit +Date: Tue, 25 Jul 2023 01:52:59 +0100 +Subject: [PATCH 102/250] net: ethernet: mtk_eth_soc: add NETSYS_V3 version + support -Introduce MTK_NETSYS_V3 bit in the device capabilities. +Introduce NETSYS_V3 chipset version support. This is a preliminary patch to introduce support for MT7988 SoC. Signed-off-by: Lorenzo Bianconi Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/0db2260910755d76fa48e303b9f9bdf4e5a82340.1690246066.git.daniel@makrotopia.org +Signed-off-by: Jakub Kicinski --- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 115 ++++++++++++++++---- - drivers/net/ethernet/mediatek/mtk_eth_soc.h | 44 +++++++- - 2 files changed, 134 insertions(+), 25 deletions(-) + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 105 ++++++++++++++------ + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 48 +++++++-- + 2 files changed, 116 insertions(+), 37 deletions(-) --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -880,17 +880,32 @@ void mtk_stats_update_mac(struct mtk_mac +@@ -818,17 +818,32 @@ void mtk_stats_update_mac(struct mtk_mac mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs); hw_stats->rx_flow_control_packets += mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs); @@ -32,7 +34,7 @@ Signed-off-by: Daniel Golle - hw_stats->tx_packets += - mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs); + -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { ++ if (mtk_is_netsys_v3_or_greater(eth)) { + hw_stats->tx_skip += + mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x50 + offs); + hw_stats->tx_collisions += @@ -60,7 +62,7 @@ Signed-off-by: Daniel Golle } u64_stats_update_end(&hw_stats->syncp); -@@ -1192,7 +1207,10 @@ static void mtk_tx_set_dma_desc_v2(struc +@@ -1130,7 +1145,10 @@ static void mtk_tx_set_dma_desc_v2(struc data |= TX_DMA_LS0; WRITE_ONCE(desc->txd3, data); @@ -72,57 +74,53 @@ Signed-off-by: Daniel Golle data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid); WRITE_ONCE(desc->txd4, data); -@@ -1203,6 +1221,9 @@ static void mtk_tx_set_dma_desc_v2(struc +@@ -1141,6 +1159,8 @@ static void mtk_tx_set_dma_desc_v2(struc /* tx checksum offload */ if (info->csum) data |= TX_DMA_CHKSUM_V2; -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3) && -+ netdev_uses_dsa(dev)) ++ if (mtk_is_netsys_v3_or_greater(eth) && netdev_uses_dsa(dev)) + data |= TX_DMA_SPTAG_V3; } WRITE_ONCE(desc->txd5, data); -@@ -1268,8 +1289,13 @@ static int mtk_tx_map(struct sk_buff *sk +@@ -1206,8 +1226,7 @@ static int mtk_tx_map(struct sk_buff *sk mtk_tx_set_dma_desc(dev, itxd, &txd_info); itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; - itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : - MTK_TX_FLAGS_FPORT1; -+ if (mac->id == MTK_GMAC1_ID) -+ itx_buf->flags |= MTK_TX_FLAGS_FPORT0; -+ else if (mac->id == MTK_GMAC2_ID) -+ itx_buf->flags |= MTK_TX_FLAGS_FPORT1; -+ else -+ itx_buf->flags |= MTK_TX_FLAGS_FPORT2; -+ ++ itx_buf->mac_id = mac->id; setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size, k++); -@@ -1317,8 +1343,13 @@ static int mtk_tx_map(struct sk_buff *sk +@@ -1255,8 +1274,7 @@ static int mtk_tx_map(struct sk_buff *sk memset(tx_buf, 0, sizeof(*tx_buf)); tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; tx_buf->flags |= MTK_TX_FLAGS_PAGE0; - tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : - MTK_TX_FLAGS_FPORT1; -+ -+ if (mac->id == MTK_GMAC1_ID) -+ tx_buf->flags |= MTK_TX_FLAGS_FPORT0; -+ else if (mac->id == MTK_GMAC2_ID) -+ tx_buf->flags |= MTK_TX_FLAGS_FPORT1; -+ else -+ tx_buf->flags |= MTK_TX_FLAGS_FPORT2; ++ tx_buf->mac_id = mac->id; setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr, txd_info.size, k++); -@@ -1902,11 +1933,24 @@ static int mtk_poll_rx(struct napi_struc +@@ -1558,7 +1576,7 @@ static int mtk_xdp_frame_map(struct mtk_ + } + mtk_tx_set_dma_desc(dev, txd, txd_info); + +- tx_buf->flags |= !mac->id ? MTK_TX_FLAGS_FPORT0 : MTK_TX_FLAGS_FPORT1; ++ tx_buf->mac_id = mac->id; + tx_buf->type = dma_map ? MTK_TYPE_XDP_NDO : MTK_TYPE_XDP_TX; + tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; + +@@ -1806,11 +1824,24 @@ static int mtk_poll_rx(struct napi_struc break; /* find out which mac the packet come from. values start at 1 */ -- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) +- if (mtk_is_netsys_v2_or_greater(eth)) - mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1; - else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && - !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) -+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { ++ if (mtk_is_netsys_v2_or_greater(eth)) { + u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5); + + switch (val) { @@ -137,29 +135,44 @@ Signed-off-by: Daniel Golle + break; + } + } else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && -+ !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) { ++ !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) { mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1; + } - if (unlikely(mac < 0 || mac >= eth->soc->num_devs || + if (unlikely(mac < 0 || mac >= MTK_MAX_DEVS || !eth->netdev[mac])) -@@ -2135,7 +2179,9 @@ static int mtk_poll_tx_qdma(struct mtk_e +@@ -2030,7 +2061,6 @@ static int mtk_poll_tx_qdma(struct mtk_e + + while ((cpu != dma) && budget) { + u32 next_cpu = desc->txd2; +- int mac = 0; + + desc = mtk_qdma_phys_to_virt(ring, desc->txd2); + if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) +@@ -2038,15 +2068,13 @@ static int mtk_poll_tx_qdma(struct mtk_e + tx_buf = mtk_desc_to_tx_buf(ring, desc, eth->soc->txrx.txd_size); - if (tx_buf->flags & MTK_TX_FLAGS_FPORT1) +- if (tx_buf->flags & MTK_TX_FLAGS_FPORT1) - mac = 1; -+ mac = MTK_GMAC2_ID; -+ else if (tx_buf->flags & MTK_TX_FLAGS_FPORT2) -+ mac = MTK_GMAC3_ID; - +- if (!tx_buf->data) break; -@@ -3742,7 +3788,26 @@ static int mtk_hw_init(struct mtk_eth *e + + if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { + if (tx_buf->type == MTK_TYPE_SKB) +- mtk_poll_tx_done(eth, state, mac, tx_buf->data); ++ mtk_poll_tx_done(eth, state, tx_buf->mac_id, ++ tx_buf->data); + + budget--; + } +@@ -3648,7 +3676,24 @@ static int mtk_hw_init(struct mtk_eth *e mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4); mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); -- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { +- if (mtk_is_netsys_v2_or_greater(eth)) { ++ if (mtk_is_netsys_v3_or_greater(eth)) { + /* PSE should not drop port1, port8 and port9 packets */ + mtk_w32(eth, 0x00000302, PSE_DROP_CFG); + @@ -168,9 +181,7 @@ Signed-off-by: Daniel Golle + mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES); + + /* Disable GDM1 RX CRC stripping */ -+ val = mtk_r32(eth, MTK_GDMA_FWD_CFG(0)); -+ val &= ~MTK_GDMA_STRP_CRC; -+ mtk_w32(eth, val, MTK_GDMA_FWD_CFG(0)); ++ mtk_m32(eth, MTK_GDMA_STRP_CRC, 0, MTK_GDMA_FWD_CFG(0)); + + /* PSE GDM3 MIB counter has incorrect hw default values, + * so the driver ought to read clear the values beforehand @@ -178,17 +189,17 @@ Signed-off-by: Daniel Golle + */ + for (i = 0; i < 0x80; i += 0x4) + mtk_r32(eth, reg_map->gdm1_cnt + 0x100 + i); -+ } else if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ } else if (!mtk_is_netsys_v1(eth)) { /* PSE should not drop port8 and port9 packets from WDMA Tx */ mtk_w32(eth, 0x00000300, PSE_DROP_CFG); -@@ -4307,7 +4372,11 @@ static int mtk_add_mac(struct mtk_eth *e +@@ -4210,7 +4255,11 @@ static int mtk_add_mac(struct mtk_eth *e } spin_lock_init(&mac->hw_stats->stats_lock); u64_stats_init(&mac->hw_stats->syncp); - mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; + -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) ++ if (mtk_is_netsys_v3_or_greater(eth)) + mac->hw_stats->reg_offset = id * 0x80; + else + mac->hw_stats->reg_offset = id * 0x40; @@ -197,7 +208,7 @@ Signed-off-by: Daniel Golle err = of_get_phy_mode(np, &phy_mode); --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -121,6 +121,7 @@ +@@ -122,6 +122,7 @@ #define MTK_GDMA_ICS_EN BIT(22) #define MTK_GDMA_TCS_EN BIT(21) #define MTK_GDMA_UCS_EN BIT(20) @@ -205,7 +216,7 @@ Signed-off-by: Daniel Golle #define MTK_GDMA_TO_PDMA 0x0 #define MTK_GDMA_DROP_ALL 0x7777 -@@ -286,8 +287,6 @@ +@@ -287,8 +288,6 @@ /* QDMA Interrupt grouping registers */ #define MTK_RLS_DONE_INT BIT(0) @@ -214,7 +225,7 @@ Signed-off-by: Daniel Golle /* QDMA TX NUM */ #define QID_BITS_V2(x) (((x) & 0x3f) << 16) #define MTK_QDMA_GMAC2_QID 8 -@@ -300,6 +299,8 @@ +@@ -301,6 +300,8 @@ #define TX_DMA_CHKSUM_V2 (0x7 << 28) #define TX_DMA_TSO_V2 BIT(31) @@ -223,15 +234,20 @@ Signed-off-by: Daniel Golle /* QDMA V2 descriptor txd4 */ #define TX_DMA_FPORT_SHIFT_V2 8 #define TX_DMA_FPORT_MASK_V2 0xf -@@ -636,6 +637,7 @@ enum mtk_tx_flags { +@@ -631,12 +632,6 @@ enum mtk_tx_flags { */ - MTK_TX_FLAGS_FPORT0 = 0x04, - MTK_TX_FLAGS_FPORT1 = 0x08, -+ MTK_TX_FLAGS_FPORT2 = 0x10, + MTK_TX_FLAGS_SINGLE0 = 0x01, + MTK_TX_FLAGS_PAGE0 = 0x02, +- +- /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted +- * SKB out instead of looking up through hardware TX descriptor. +- */ +- MTK_TX_FLAGS_FPORT0 = 0x04, +- MTK_TX_FLAGS_FPORT1 = 0x08, }; /* This enum allows us to identify how the clock is defined on the array of the -@@ -721,6 +723,42 @@ enum mtk_dev_state { +@@ -722,6 +717,35 @@ enum mtk_dev_state { MTK_RESETTING }; @@ -263,30 +279,29 @@ Signed-off-by: Daniel Golle + MTK_GMAC3_ID, + MTK_GMAC_ID_MAX +}; -+ -+/* GDM Type */ -+enum mtk_gdm_type { -+ MTK_GDM_TYPE = 0, -+ MTK_XGDM_TYPE, -+ MTK_GDM_TYPE_MAX -+}; + enum mtk_tx_buf_type { MTK_TYPE_SKB, MTK_TYPE_XDP_TX, -@@ -817,6 +855,7 @@ enum mkt_eth_capabilities { - MTK_QDMA_BIT, - MTK_NETSYS_V1_BIT, - MTK_NETSYS_V2_BIT, -+ MTK_NETSYS_V3_BIT, - MTK_SOC_MT7628_BIT, - MTK_RSTCTRL_PPE1_BIT, - MTK_U3_COPHY_V2_BIT, -@@ -853,6 +892,7 @@ enum mkt_eth_capabilities { - #define MTK_QDMA BIT(MTK_QDMA_BIT) - #define MTK_NETSYS_V1 BIT(MTK_NETSYS_V1_BIT) - #define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) -+#define MTK_NETSYS_V3 BIT(MTK_NETSYS_V3_BIT) - #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) - #define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT) - #define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT) +@@ -740,7 +764,8 @@ struct mtk_tx_buf { + enum mtk_tx_buf_type type; + void *data; + +- u32 flags; ++ u16 mac_id; ++ u16 flags; + DEFINE_DMA_UNMAP_ADDR(dma_addr0); + DEFINE_DMA_UNMAP_LEN(dma_len0); + DEFINE_DMA_UNMAP_ADDR(dma_addr1); +@@ -1189,6 +1214,11 @@ static inline bool mtk_is_netsys_v2_or_g + return eth->soc->version > 1; + } + ++static inline bool mtk_is_netsys_v3_or_greater(struct mtk_eth *eth) ++{ ++ return eth->soc->version > 2; ++} ++ + static inline struct mtk_foe_entry * + mtk_foe_get_entry(struct mtk_ppe *ppe, u16 hash) + { diff --git a/target/linux/generic/pending-5.15/737-05-net-ethernet-mtk_eth_soc-convert-caps-in-mtk_soc_dat.patch b/target/linux/generic/backport-5.15/750-v6.5-09-net-ethernet-mtk_eth_soc-convert-caps-in-mtk_soc_dat.patch similarity index 89% rename from target/linux/generic/pending-5.15/737-05-net-ethernet-mtk_eth_soc-convert-caps-in-mtk_soc_dat.patch rename to target/linux/generic/backport-5.15/750-v6.5-09-net-ethernet-mtk_eth_soc-convert-caps-in-mtk_soc_dat.patch index bd26cca305d..0a72eec2fc1 100644 --- a/target/linux/generic/pending-5.15/737-05-net-ethernet-mtk_eth_soc-convert-caps-in-mtk_soc_dat.patch +++ b/target/linux/generic/backport-5.15/750-v6.5-09-net-ethernet-mtk_eth_soc-convert-caps-in-mtk_soc_dat.patch @@ -1,17 +1,19 @@ -From 45b575fd9e6a455090820248bf1b98b1f2c7b6c8 Mon Sep 17 00:00:00 2001 +From db797ae0542220a98658229397da464c383c991c Mon Sep 17 00:00:00 2001 From: Lorenzo Bianconi -Date: Tue, 7 Mar 2023 15:56:00 +0000 -Subject: [PATCH 5/7] net: ethernet: mtk_eth_soc: convert caps in mtk_soc_data - struct to u64 +Date: Tue, 25 Jul 2023 01:53:13 +0100 +Subject: [PATCH 103/250] net: ethernet: mtk_eth_soc: convert caps in + mtk_soc_data struct to u64 This is a preliminary patch to introduce support for MT7988 SoC. Signed-off-by: Lorenzo Bianconi Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/9499ac3670b2fc5b444404b84e8a4a169beabbf2.1690246066.git.daniel@makrotopia.org +Signed-off-by: Jakub Kicinski --- - drivers/net/ethernet/mediatek/mtk_eth_path.c | 22 +++---- - drivers/net/ethernet/mediatek/mtk_eth_soc.h | 62 ++++++++++---------- - 2 files changed, 42 insertions(+), 42 deletions(-) + drivers/net/ethernet/mediatek/mtk_eth_path.c | 22 ++++---- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 56 ++++++++++---------- + 2 files changed, 39 insertions(+), 39 deletions(-) --- a/drivers/net/ethernet/mediatek/mtk_eth_path.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c @@ -111,7 +113,7 @@ Signed-off-by: Daniel Golle MTK_ETH_PATH_GMAC2_RGMII; --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -878,44 +878,44 @@ enum mkt_eth_capabilities { +@@ -863,41 +863,41 @@ enum mkt_eth_capabilities { }; /* Supported hardware group on SoCs */ @@ -127,9 +129,6 @@ Signed-off-by: Daniel Golle -#define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT) -#define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) -#define MTK_QDMA BIT(MTK_QDMA_BIT) --#define MTK_NETSYS_V1 BIT(MTK_NETSYS_V1_BIT) --#define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) --#define MTK_NETSYS_V3 BIT(MTK_NETSYS_V3_BIT) -#define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) -#define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT) -#define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT) @@ -145,9 +144,6 @@ Signed-off-by: Daniel Golle +#define MTK_SHARED_INT BIT_ULL(MTK_SHARED_INT_BIT) +#define MTK_TRGMII_MT7621_CLK BIT_ULL(MTK_TRGMII_MT7621_CLK_BIT) +#define MTK_QDMA BIT_ULL(MTK_QDMA_BIT) -+#define MTK_NETSYS_V1 BIT_ULL(MTK_NETSYS_V1_BIT) -+#define MTK_NETSYS_V2 BIT_ULL(MTK_NETSYS_V2_BIT) -+#define MTK_NETSYS_V3 BIT_ULL(MTK_NETSYS_V3_BIT) +#define MTK_SOC_MT7628 BIT_ULL(MTK_SOC_MT7628_BIT) +#define MTK_RSTCTRL_PPE1 BIT_ULL(MTK_RSTCTRL_PPE1_BIT) +#define MTK_U3_COPHY_V2 BIT_ULL(MTK_U3_COPHY_V2_BIT) @@ -186,7 +182,7 @@ Signed-off-by: Daniel Golle #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) -@@ -1071,7 +1071,7 @@ struct mtk_reg_map { +@@ -1042,7 +1042,7 @@ struct mtk_reg_map { struct mtk_soc_data { const struct mtk_reg_map *reg_map; u32 ana_rgc3; diff --git a/target/linux/generic/backport-5.15/750-v6.5-10-net-ethernet-mtk_eth_soc-convert-clock-bitmap-to-u64.patch b/target/linux/generic/backport-5.15/750-v6.5-10-net-ethernet-mtk_eth_soc-convert-clock-bitmap-to-u64.patch new file mode 100644 index 00000000000..4e5b857d48b --- /dev/null +++ b/target/linux/generic/backport-5.15/750-v6.5-10-net-ethernet-mtk_eth_soc-convert-clock-bitmap-to-u64.patch @@ -0,0 +1,132 @@ +From a1c9f7d1d24e90294f6a6755b137fcf306851e93 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Tue, 25 Jul 2023 01:53:28 +0100 +Subject: [PATCH 104/250] net: ethernet: mtk_eth_soc: convert clock bitmap to + u64 + +The to-be-added MT7988 SoC adds many new clocks which need to be +controlled by the Ethernet driver, which will result in their total +number exceeding 32. +Prepare by converting clock bitmaps into 64-bit types. + +Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/6960a39bb0078cf84d7642a9558e6a91c6cc9df3.1690246066.git.daniel@makrotopia.org +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 96 +++++++++++---------- + 1 file changed, 49 insertions(+), 47 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -663,54 +663,56 @@ enum mtk_clks_map { + MTK_CLK_MAX + }; + +-#define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ +- BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \ +- BIT(MTK_CLK_TRGPLL)) +-#define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ +- BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ +- BIT(MTK_CLK_GP2) | \ +- BIT(MTK_CLK_SGMII_TX_250M) | \ +- BIT(MTK_CLK_SGMII_RX_250M) | \ +- BIT(MTK_CLK_SGMII_CDR_REF) | \ +- BIT(MTK_CLK_SGMII_CDR_FB) | \ +- BIT(MTK_CLK_SGMII_CK) | \ +- BIT(MTK_CLK_ETH2PLL)) ++#define MT7623_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \ ++ BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \ ++ BIT_ULL(MTK_CLK_TRGPLL)) ++#define MT7622_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \ ++ BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \ ++ BIT_ULL(MTK_CLK_GP2) | \ ++ BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ ++ BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ ++ BIT_ULL(MTK_CLK_SGMII_CK) | \ ++ BIT_ULL(MTK_CLK_ETH2PLL)) + #define MT7621_CLKS_BITMAP (0) + #define MT7628_CLKS_BITMAP (0) +-#define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ +- BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ +- BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \ +- BIT(MTK_CLK_SGMII_TX_250M) | \ +- BIT(MTK_CLK_SGMII_RX_250M) | \ +- BIT(MTK_CLK_SGMII_CDR_REF) | \ +- BIT(MTK_CLK_SGMII_CDR_FB) | \ +- BIT(MTK_CLK_SGMII2_TX_250M) | \ +- BIT(MTK_CLK_SGMII2_RX_250M) | \ +- BIT(MTK_CLK_SGMII2_CDR_REF) | \ +- BIT(MTK_CLK_SGMII2_CDR_FB) | \ +- BIT(MTK_CLK_SGMII_CK) | \ +- BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP)) +-#define MT7981_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \ +- BIT(MTK_CLK_WOCPU0) | \ +- BIT(MTK_CLK_SGMII_TX_250M) | \ +- BIT(MTK_CLK_SGMII_RX_250M) | \ +- BIT(MTK_CLK_SGMII_CDR_REF) | \ +- BIT(MTK_CLK_SGMII_CDR_FB) | \ +- BIT(MTK_CLK_SGMII2_TX_250M) | \ +- BIT(MTK_CLK_SGMII2_RX_250M) | \ +- BIT(MTK_CLK_SGMII2_CDR_REF) | \ +- BIT(MTK_CLK_SGMII2_CDR_FB) | \ +- BIT(MTK_CLK_SGMII_CK)) +-#define MT7986_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \ +- BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \ +- BIT(MTK_CLK_SGMII_TX_250M) | \ +- BIT(MTK_CLK_SGMII_RX_250M) | \ +- BIT(MTK_CLK_SGMII_CDR_REF) | \ +- BIT(MTK_CLK_SGMII_CDR_FB) | \ +- BIT(MTK_CLK_SGMII2_TX_250M) | \ +- BIT(MTK_CLK_SGMII2_RX_250M) | \ +- BIT(MTK_CLK_SGMII2_CDR_REF) | \ +- BIT(MTK_CLK_SGMII2_CDR_FB)) ++#define MT7629_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \ ++ BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \ ++ BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_FE) | \ ++ BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ ++ BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ ++ BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ ++ BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \ ++ BIT_ULL(MTK_CLK_SGMII_CK) | \ ++ BIT_ULL(MTK_CLK_ETH2PLL) | BIT_ULL(MTK_CLK_SGMIITOP)) ++#define MT7981_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \ ++ BIT_ULL(MTK_CLK_GP1) | \ ++ BIT_ULL(MTK_CLK_WOCPU0) | \ ++ BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ ++ BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ ++ BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ ++ BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \ ++ BIT_ULL(MTK_CLK_SGMII_CK)) ++#define MT7986_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \ ++ BIT_ULL(MTK_CLK_GP1) | \ ++ BIT_ULL(MTK_CLK_WOCPU1) | BIT_ULL(MTK_CLK_WOCPU0) | \ ++ BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ ++ BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ ++ BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ ++ BIT_ULL(MTK_CLK_SGMII2_CDR_FB)) + + enum mtk_dev_state { + MTK_HW_INIT, +@@ -1043,7 +1045,7 @@ struct mtk_soc_data { + const struct mtk_reg_map *reg_map; + u32 ana_rgc3; + u64 caps; +- u32 required_clks; ++ u64 required_clks; + bool required_pctl; + u8 offload_version; + u8 hash_offset; diff --git a/target/linux/generic/backport-5.15/750-v6.5-11-net-ethernet-mtk_eth_soc-add-basic-support-for-MT798.patch b/target/linux/generic/backport-5.15/750-v6.5-11-net-ethernet-mtk_eth_soc-add-basic-support-for-MT798.patch new file mode 100644 index 00000000000..028c28b1f74 --- /dev/null +++ b/target/linux/generic/backport-5.15/750-v6.5-11-net-ethernet-mtk_eth_soc-add-basic-support-for-MT798.patch @@ -0,0 +1,477 @@ +From 94f825a7eadfc8b4c8828efdb7705d9703f9c73e Mon Sep 17 00:00:00 2001 +From: Lorenzo Bianconi +Date: Tue, 25 Jul 2023 01:57:42 +0100 +Subject: [PATCH 105/250] net: ethernet: mtk_eth_soc: add basic support for + MT7988 SoC + +Introduce support for ethernet chip available in MT7988 SoC to +mtk_eth_soc driver. As a first step support only the first GMAC which +is hard-wired to the internal DSA switch having 4 built-in gigabit +Ethernet PHYs. + +Signed-off-by: Lorenzo Bianconi +Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/25c8377095b95d186872eeda7aa055da83e8f0ca.1690246605.git.daniel@makrotopia.org +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_path.c | 14 +- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 201 +++++++++++++++++-- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 86 +++++++- + 3 files changed, 273 insertions(+), 28 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_path.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c +@@ -43,7 +43,7 @@ static const char *mtk_eth_path_name(u64 + static int set_mux_gdm1_to_gmac1_esw(struct mtk_eth *eth, u64 path) + { + bool updated = true; +- u32 val, mask, set; ++ u32 mask, set, reg; + + switch (path) { + case MTK_ETH_PATH_GMAC1_SGMII: +@@ -59,11 +59,13 @@ static int set_mux_gdm1_to_gmac1_esw(str + break; + } + +- if (updated) { +- val = mtk_r32(eth, MTK_MAC_MISC); +- val = (val & mask) | set; +- mtk_w32(eth, val, MTK_MAC_MISC); +- } ++ if (mtk_is_netsys_v3_or_greater(eth)) ++ reg = MTK_MAC_MISC_V3; ++ else ++ reg = MTK_MAC_MISC; ++ ++ if (updated) ++ mtk_m32(eth, mask, set, reg); + + dev_dbg(eth->dev, "path %s in %s updated = %d\n", + mtk_eth_path_name(path), __func__, updated); +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -152,6 +152,54 @@ static const struct mtk_reg_map mt7986_r + .pse_oq_sta = 0x01a0, + }; + ++static const struct mtk_reg_map mt7988_reg_map = { ++ .tx_irq_mask = 0x461c, ++ .tx_irq_status = 0x4618, ++ .pdma = { ++ .rx_ptr = 0x6900, ++ .rx_cnt_cfg = 0x6904, ++ .pcrx_ptr = 0x6908, ++ .glo_cfg = 0x6a04, ++ .rst_idx = 0x6a08, ++ .delay_irq = 0x6a0c, ++ .irq_status = 0x6a20, ++ .irq_mask = 0x6a28, ++ .adma_rx_dbg0 = 0x6a38, ++ .int_grp = 0x6a50, ++ }, ++ .qdma = { ++ .qtx_cfg = 0x4400, ++ .qtx_sch = 0x4404, ++ .rx_ptr = 0x4500, ++ .rx_cnt_cfg = 0x4504, ++ .qcrx_ptr = 0x4508, ++ .glo_cfg = 0x4604, ++ .rst_idx = 0x4608, ++ .delay_irq = 0x460c, ++ .fc_th = 0x4610, ++ .int_grp = 0x4620, ++ .hred = 0x4644, ++ .ctx_ptr = 0x4700, ++ .dtx_ptr = 0x4704, ++ .crx_ptr = 0x4710, ++ .drx_ptr = 0x4714, ++ .fq_head = 0x4720, ++ .fq_tail = 0x4724, ++ .fq_count = 0x4728, ++ .fq_blen = 0x472c, ++ .tx_sch_rate = 0x4798, ++ }, ++ .gdm1_cnt = 0x1c00, ++ .gdma_to_ppe0 = 0x3333, ++ .ppe_base = 0x2000, ++ .wdma_base = { ++ [0] = 0x4800, ++ [1] = 0x4c00, ++ }, ++ .pse_iq_sta = 0x0180, ++ .pse_oq_sta = 0x01a0, ++}; ++ + /* strings used by ethtool */ + static const struct mtk_ethtool_stats { + char str[ETH_GSTRING_LEN]; +@@ -179,10 +227,54 @@ static const struct mtk_ethtool_stats { + }; + + static const char * const mtk_clks_source_name[] = { +- "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll", +- "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", +- "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb", +- "sgmii_ck", "eth2pll", "wocpu0", "wocpu1", "netsys0", "netsys1" ++ "ethif", ++ "sgmiitop", ++ "esw", ++ "gp0", ++ "gp1", ++ "gp2", ++ "gp3", ++ "xgp1", ++ "xgp2", ++ "xgp3", ++ "crypto", ++ "fe", ++ "trgpll", ++ "sgmii_tx250m", ++ "sgmii_rx250m", ++ "sgmii_cdr_ref", ++ "sgmii_cdr_fb", ++ "sgmii2_tx250m", ++ "sgmii2_rx250m", ++ "sgmii2_cdr_ref", ++ "sgmii2_cdr_fb", ++ "sgmii_ck", ++ "eth2pll", ++ "wocpu0", ++ "wocpu1", ++ "netsys0", ++ "netsys1", ++ "ethwarp_wocpu2", ++ "ethwarp_wocpu1", ++ "ethwarp_wocpu0", ++ "top_usxgmii0_sel", ++ "top_usxgmii1_sel", ++ "top_sgm0_sel", ++ "top_sgm1_sel", ++ "top_xfi_phy0_xtal_sel", ++ "top_xfi_phy1_xtal_sel", ++ "top_eth_gmii_sel", ++ "top_eth_refck_50m_sel", ++ "top_eth_sys_200m_sel", ++ "top_eth_sys_sel", ++ "top_eth_xgmii_sel", ++ "top_eth_mii_sel", ++ "top_netsys_sel", ++ "top_netsys_500m_sel", ++ "top_netsys_pao_2x_sel", ++ "top_netsys_sync_250m_sel", ++ "top_netsys_ppefb_250m_sel", ++ "top_netsys_warp_sel", + }; + + void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) +@@ -195,7 +287,7 @@ u32 mtk_r32(struct mtk_eth *eth, unsigne + return __raw_readl(eth->base + reg); + } + +-static u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg) ++u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg) + { + u32 val; + +@@ -326,6 +418,19 @@ static void mtk_gmac0_rgmii_adjust(struc + dev_err(eth->dev, "Missing PLL configuration, ethernet may not work\n"); + } + ++static void mtk_setup_bridge_switch(struct mtk_eth *eth) ++{ ++ /* Force Port1 XGMAC Link Up */ ++ mtk_m32(eth, 0, MTK_XGMAC_FORCE_LINK(MTK_GMAC1_ID), ++ MTK_XGMAC_STS(MTK_GMAC1_ID)); ++ ++ /* Adjust GSW bridge IPG to 11 */ ++ mtk_m32(eth, GSWTX_IPG_MASK | GSWRX_IPG_MASK, ++ (GSW_IPG_11 << GSWTX_IPG_SHIFT) | ++ (GSW_IPG_11 << GSWRX_IPG_SHIFT), ++ MTK_GSW_CFG); ++} ++ + static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config, + phy_interface_t interface) + { +@@ -395,6 +500,8 @@ static void mtk_mac_config(struct phylin + goto init_err; + } + break; ++ case PHY_INTERFACE_MODE_INTERNAL: ++ break; + default: + goto err_phy; + } +@@ -472,6 +579,15 @@ static void mtk_mac_config(struct phylin + return; + } + ++ /* Setup gmac */ ++ if (mtk_is_netsys_v3_or_greater(eth) && ++ mac->interface == PHY_INTERFACE_MODE_INTERNAL) { ++ mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id)); ++ mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id)); ++ ++ mtk_setup_bridge_switch(eth); ++ } ++ + return; + + err_phy: +@@ -682,11 +798,15 @@ static int mtk_mdio_init(struct mtk_eth + } + divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63); + ++ /* Configure MDC Turbo Mode */ ++ if (mtk_is_netsys_v3_or_greater(eth)) ++ mtk_m32(eth, 0, MISC_MDC_TURBO, MTK_MAC_MISC_V3); ++ + /* Configure MDC Divider */ +- val = mtk_r32(eth, MTK_PPSC); +- val &= ~PPSC_MDC_CFG; +- val |= FIELD_PREP(PPSC_MDC_CFG, divider) | PPSC_MDC_TURBO; +- mtk_w32(eth, val, MTK_PPSC); ++ val = FIELD_PREP(PPSC_MDC_CFG, divider); ++ if (!mtk_is_netsys_v3_or_greater(eth)) ++ val |= PPSC_MDC_TURBO; ++ mtk_m32(eth, PPSC_MDC_CFG, val, MTK_PPSC); + + dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider); + +@@ -1145,10 +1265,19 @@ static void mtk_tx_set_dma_desc_v2(struc + data |= TX_DMA_LS0; + WRITE_ONCE(desc->txd3, data); + +- if (mac->id == MTK_GMAC3_ID) +- data = PSE_GDM3_PORT; +- else +- data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */ ++ /* set forward port */ ++ switch (mac->id) { ++ case MTK_GMAC1_ID: ++ data = PSE_GDM1_PORT << TX_DMA_FPORT_SHIFT_V2; ++ break; ++ case MTK_GMAC2_ID: ++ data = PSE_GDM2_PORT << TX_DMA_FPORT_SHIFT_V2; ++ break; ++ case MTK_GMAC3_ID: ++ data = PSE_GDM3_PORT << TX_DMA_FPORT_SHIFT_V2; ++ break; ++ } ++ + data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid); + WRITE_ONCE(desc->txd4, data); + +@@ -4304,6 +4433,17 @@ static int mtk_add_mac(struct mtk_eth *e + mac->phylink_config.supported_interfaces); + } + ++ if (mtk_is_netsys_v3_or_greater(mac->hw) && ++ MTK_HAS_CAPS(mac->hw->soc->caps, MTK_ESW_BIT) && ++ id == MTK_GMAC1_ID) { ++ mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | ++ MAC_SYM_PAUSE | ++ MAC_10000FD; ++ phy_interface_zero(mac->phylink_config.supported_interfaces); ++ __set_bit(PHY_INTERFACE_MODE_INTERNAL, ++ mac->phylink_config.supported_interfaces); ++ } ++ + phylink = phylink_create(&mac->phylink_config, + of_fwnode_handle(mac->of_node), + phy_mode, &mtk_phylink_ops); +@@ -4826,6 +4966,24 @@ static const struct mtk_soc_data mt7986_ + }, + }; + ++static const struct mtk_soc_data mt7988_data = { ++ .reg_map = &mt7988_reg_map, ++ .ana_rgc3 = 0x128, ++ .caps = MT7988_CAPS, ++ .hw_features = MTK_HW_FEATURES, ++ .required_clks = MT7988_CLKS_BITMAP, ++ .required_pctl = false, ++ .version = 3, ++ .txrx = { ++ .txd_size = sizeof(struct mtk_tx_dma_v2), ++ .rxd_size = sizeof(struct mtk_rx_dma_v2), ++ .rx_irq_done_mask = MTK_RX_DONE_INT_V2, ++ .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, ++ .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, ++ .dma_len_offset = 8, ++ }, ++}; ++ + static const struct mtk_soc_data rt5350_data = { + .reg_map = &mt7628_reg_map, + .caps = MT7628_CAPS, +@@ -4844,14 +5002,15 @@ static const struct mtk_soc_data rt5350_ + }; + + const struct of_device_id of_mtk_match[] = { +- { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data}, +- { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data}, +- { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, +- { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, +- { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data}, +- { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data}, +- { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data}, +- { .compatible = "ralink,rt5350-eth", .data = &rt5350_data}, ++ { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data }, ++ { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data }, ++ { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data }, ++ { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data }, ++ { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data }, ++ { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data }, ++ { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data }, ++ { .compatible = "mediatek,mt7988-eth", .data = &mt7988_data }, ++ { .compatible = "ralink,rt5350-eth", .data = &rt5350_data }, + {}, + }; + MODULE_DEVICE_TABLE(of, of_mtk_match); +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -117,7 +117,8 @@ + #define MTK_CDMP_EG_CTRL 0x404 + + /* GDM Exgress Control Register */ +-#define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) ++#define MTK_GDMA_FWD_CFG(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \ ++ 0x540 : 0x500 + (_x * 0x1000); }) + #define MTK_GDMA_SPECIAL_TAG BIT(24) + #define MTK_GDMA_ICS_EN BIT(22) + #define MTK_GDMA_TCS_EN BIT(21) +@@ -126,6 +127,11 @@ + #define MTK_GDMA_TO_PDMA 0x0 + #define MTK_GDMA_DROP_ALL 0x7777 + ++/* GDM Egress Control Register */ ++#define MTK_GDMA_EG_CTRL(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \ ++ 0x544 : 0x504 + (_x * 0x1000); }) ++#define MTK_GDMA_XGDM_SEL BIT(31) ++ + /* Unicast Filter MAC Address Register - Low */ + #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) + +@@ -386,7 +392,26 @@ + #define PHY_IAC_TIMEOUT HZ + + #define MTK_MAC_MISC 0x1000c ++#define MTK_MAC_MISC_V3 0x10010 + #define MTK_MUX_TO_ESW BIT(0) ++#define MISC_MDC_TURBO BIT(4) ++ ++/* XMAC status registers */ ++#define MTK_XGMAC_STS(x) (((x) == MTK_GMAC3_ID) ? 0x1001C : 0x1000C) ++#define MTK_XGMAC_FORCE_LINK(x) (((x) == MTK_GMAC2_ID) ? BIT(31) : BIT(15)) ++#define MTK_USXGMII_PCS_LINK BIT(8) ++#define MTK_XGMAC_RX_FC BIT(5) ++#define MTK_XGMAC_TX_FC BIT(4) ++#define MTK_USXGMII_PCS_MODE GENMASK(3, 1) ++#define MTK_XGMAC_LINK_STS BIT(0) ++ ++/* GSW bridge registers */ ++#define MTK_GSW_CFG (0x10080) ++#define GSWTX_IPG_MASK GENMASK(19, 16) ++#define GSWTX_IPG_SHIFT 16 ++#define GSWRX_IPG_MASK GENMASK(3, 0) ++#define GSWRX_IPG_SHIFT 0 ++#define GSW_IPG_11 11 + + /* Mac control registers */ + #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) +@@ -644,6 +669,11 @@ enum mtk_clks_map { + MTK_CLK_GP0, + MTK_CLK_GP1, + MTK_CLK_GP2, ++ MTK_CLK_GP3, ++ MTK_CLK_XGP1, ++ MTK_CLK_XGP2, ++ MTK_CLK_XGP3, ++ MTK_CLK_CRYPTO, + MTK_CLK_FE, + MTK_CLK_TRGPLL, + MTK_CLK_SGMII_TX_250M, +@@ -660,6 +690,27 @@ enum mtk_clks_map { + MTK_CLK_WOCPU1, + MTK_CLK_NETSYS0, + MTK_CLK_NETSYS1, ++ MTK_CLK_ETHWARP_WOCPU2, ++ MTK_CLK_ETHWARP_WOCPU1, ++ MTK_CLK_ETHWARP_WOCPU0, ++ MTK_CLK_TOP_USXGMII_SBUS_0_SEL, ++ MTK_CLK_TOP_USXGMII_SBUS_1_SEL, ++ MTK_CLK_TOP_SGM_0_SEL, ++ MTK_CLK_TOP_SGM_1_SEL, ++ MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL, ++ MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL, ++ MTK_CLK_TOP_ETH_GMII_SEL, ++ MTK_CLK_TOP_ETH_REFCK_50M_SEL, ++ MTK_CLK_TOP_ETH_SYS_200M_SEL, ++ MTK_CLK_TOP_ETH_SYS_SEL, ++ MTK_CLK_TOP_ETH_XGMII_SEL, ++ MTK_CLK_TOP_ETH_MII_SEL, ++ MTK_CLK_TOP_NETSYS_SEL, ++ MTK_CLK_TOP_NETSYS_500M_SEL, ++ MTK_CLK_TOP_NETSYS_PAO_2X_SEL, ++ MTK_CLK_TOP_NETSYS_SYNC_250M_SEL, ++ MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL, ++ MTK_CLK_TOP_NETSYS_WARP_SEL, + MTK_CLK_MAX + }; + +@@ -713,6 +764,36 @@ enum mtk_clks_map { + BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ + BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ + BIT_ULL(MTK_CLK_SGMII2_CDR_FB)) ++#define MT7988_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_ESW) | \ ++ BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \ ++ BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \ ++ BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \ ++ BIT_ULL(MTK_CLK_CRYPTO) | \ ++ BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ ++ BIT_ULL(MTK_CLK_ETHWARP_WOCPU2) | \ ++ BIT_ULL(MTK_CLK_ETHWARP_WOCPU1) | \ ++ BIT_ULL(MTK_CLK_ETHWARP_WOCPU0) | \ ++ BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_0_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_1_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_SGM_0_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_SGM_1_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_ETH_SYS_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_ETH_XGMII_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_ETH_MII_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_NETSYS_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_NETSYS_500M_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_NETSYS_PAO_2X_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_NETSYS_SYNC_250M_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_NETSYS_WARP_SEL)) + + enum mtk_dev_state { + MTK_HW_INIT, +@@ -961,6 +1042,8 @@ enum mkt_eth_capabilities { + MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ + MTK_RSTCTRL_PPE1) + ++#define MT7988_CAPS (MTK_GDM1_ESW | MTK_QDMA | MTK_RSTCTRL_PPE1) ++ + struct mtk_tx_dma_desc_info { + dma_addr_t addr; + u32 size; +@@ -1306,6 +1389,7 @@ void mtk_stats_update_mac(struct mtk_mac + + void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); + u32 mtk_r32(struct mtk_eth *eth, unsigned reg); ++u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg); + + int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); + int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); diff --git a/target/linux/generic/backport-5.15/750-v6.5-12-net-ethernet-mtk_eth_soc-enable-page_pool-support-fo.patch b/target/linux/generic/backport-5.15/750-v6.5-12-net-ethernet-mtk_eth_soc-enable-page_pool-support-fo.patch new file mode 100644 index 00000000000..0a2bc6ae783 --- /dev/null +++ b/target/linux/generic/backport-5.15/750-v6.5-12-net-ethernet-mtk_eth_soc-enable-page_pool-support-fo.patch @@ -0,0 +1,27 @@ +From 38a7eb76220731eff40602cf433f24880be0a6c2 Mon Sep 17 00:00:00 2001 +From: Lorenzo Bianconi +Date: Thu, 27 Jul 2023 09:02:26 +0200 +Subject: [PATCH 106/250] net: ethernet: mtk_eth_soc: enable page_pool support + for MT7988 SoC + +In order to recycle pages, enable page_pool allocator for MT7988 SoC. + +Tested-by: Daniel Golle +Signed-off-by: Lorenzo Bianconi +Link: https://lore.kernel.org/r/fd4e8693980e47385a543e7b002eec0b88bd09df.1690440675.git.lorenzo@kernel.org +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -1613,7 +1613,7 @@ static void mtk_update_rx_cpu_idx(struct + + static bool mtk_page_pool_enabled(struct mtk_eth *eth) + { +- return eth->soc->version == 2; ++ return mtk_is_netsys_v2_or_greater(eth); + } + + static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth, diff --git a/target/linux/generic/backport-5.15/750-v6.5-13-net-ethernet-mtk_eth_soc-enable-nft-hw-flowtable_off.patch b/target/linux/generic/backport-5.15/750-v6.5-13-net-ethernet-mtk_eth_soc-enable-nft-hw-flowtable_off.patch new file mode 100644 index 00000000000..b32670d7a49 --- /dev/null +++ b/target/linux/generic/backport-5.15/750-v6.5-13-net-ethernet-mtk_eth_soc-enable-nft-hw-flowtable_off.patch @@ -0,0 +1,135 @@ +From 199e7d5a7f03dd377f3a7a458360dbedd71d50ba Mon Sep 17 00:00:00 2001 +From: Lorenzo Bianconi +Date: Thu, 27 Jul 2023 09:07:28 +0200 +Subject: [PATCH 107/250] net: ethernet: mtk_eth_soc: enable nft hw + flowtable_offload for MT7988 SoC + +Enable hw Packet Process Engine (PPE) for MT7988 SoC. + +Tested-by: Daniel Golle +Signed-off-by: Lorenzo Bianconi +Link: https://lore.kernel.org/r/5e86341b0220a49620dadc02d77970de5ded9efc.1690441576.git.lorenzo@kernel.org +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 3 +++ + drivers/net/ethernet/mediatek/mtk_ppe.c | 19 +++++++++++++++---- + drivers/net/ethernet/mediatek/mtk_ppe.h | 19 ++++++++++++++++++- + 3 files changed, 36 insertions(+), 5 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -4974,6 +4974,9 @@ static const struct mtk_soc_data mt7988_ + .required_clks = MT7988_CLKS_BITMAP, + .required_pctl = false, + .version = 3, ++ .offload_version = 2, ++ .hash_offset = 4, ++ .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma_v2), + .rxd_size = sizeof(struct mtk_rx_dma_v2), +--- a/drivers/net/ethernet/mediatek/mtk_ppe.c ++++ b/drivers/net/ethernet/mediatek/mtk_ppe.c +@@ -422,13 +422,22 @@ int mtk_foe_entry_set_wdma(struct mtk_et + struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(eth, entry); + u32 *ib2 = mtk_foe_entry_ib2(eth, entry); + +- if (mtk_is_netsys_v2_or_greater(eth)) { ++ switch (eth->soc->version) { ++ case 3: ++ *ib2 &= ~MTK_FOE_IB2_PORT_MG_V2; ++ *ib2 |= FIELD_PREP(MTK_FOE_IB2_RX_IDX, txq) | ++ MTK_FOE_IB2_WDMA_WINFO_V2; ++ l2->w3info = FIELD_PREP(MTK_FOE_WINFO_WCID_V3, wcid) | ++ FIELD_PREP(MTK_FOE_WINFO_BSS_V3, bss); ++ break; ++ case 2: + *ib2 &= ~MTK_FOE_IB2_PORT_MG_V2; + *ib2 |= FIELD_PREP(MTK_FOE_IB2_RX_IDX, txq) | + MTK_FOE_IB2_WDMA_WINFO_V2; + l2->winfo = FIELD_PREP(MTK_FOE_WINFO_WCID, wcid) | + FIELD_PREP(MTK_FOE_WINFO_BSS, bss); +- } else { ++ break; ++ default: + *ib2 &= ~MTK_FOE_IB2_PORT_MG; + *ib2 |= MTK_FOE_IB2_WDMA_WINFO; + if (wdma_idx) +@@ -436,6 +445,7 @@ int mtk_foe_entry_set_wdma(struct mtk_et + l2->vlan2 = FIELD_PREP(MTK_FOE_VLAN2_WINFO_BSS, bss) | + FIELD_PREP(MTK_FOE_VLAN2_WINFO_WCID, wcid) | + FIELD_PREP(MTK_FOE_VLAN2_WINFO_RING, txq); ++ break; + } + + return 0; +@@ -956,8 +966,7 @@ void mtk_ppe_start(struct mtk_ppe *ppe) + mtk_ppe_init_foe_table(ppe); + ppe_w32(ppe, MTK_PPE_TB_BASE, ppe->foe_phys); + +- val = MTK_PPE_TB_CFG_ENTRY_80B | +- MTK_PPE_TB_CFG_AGE_NON_L4 | ++ val = MTK_PPE_TB_CFG_AGE_NON_L4 | + MTK_PPE_TB_CFG_AGE_UNBIND | + MTK_PPE_TB_CFG_AGE_TCP | + MTK_PPE_TB_CFG_AGE_UDP | +@@ -973,6 +982,8 @@ void mtk_ppe_start(struct mtk_ppe *ppe) + MTK_PPE_ENTRIES_SHIFT); + if (mtk_is_netsys_v2_or_greater(ppe->eth)) + val |= MTK_PPE_TB_CFG_INFO_SEL; ++ if (!mtk_is_netsys_v3_or_greater(ppe->eth)) ++ val |= MTK_PPE_TB_CFG_ENTRY_80B; + ppe_w32(ppe, MTK_PPE_TB_CFG, val); + + ppe_w32(ppe, MTK_PPE_IP_PROTO_CHK, +--- a/drivers/net/ethernet/mediatek/mtk_ppe.h ++++ b/drivers/net/ethernet/mediatek/mtk_ppe.h +@@ -85,6 +85,17 @@ enum { + #define MTK_FOE_WINFO_BSS GENMASK(5, 0) + #define MTK_FOE_WINFO_WCID GENMASK(15, 6) + ++#define MTK_FOE_WINFO_BSS_V3 GENMASK(23, 16) ++#define MTK_FOE_WINFO_WCID_V3 GENMASK(15, 0) ++ ++#define MTK_FOE_WINFO_PAO_USR_INFO GENMASK(15, 0) ++#define MTK_FOE_WINFO_PAO_TID GENMASK(19, 16) ++#define MTK_FOE_WINFO_PAO_IS_FIXEDRATE BIT(20) ++#define MTK_FOE_WINFO_PAO_IS_PRIOR BIT(21) ++#define MTK_FOE_WINFO_PAO_IS_SP BIT(22) ++#define MTK_FOE_WINFO_PAO_HF BIT(23) ++#define MTK_FOE_WINFO_PAO_AMSDU_EN BIT(24) ++ + enum { + MTK_FOE_STATE_INVALID, + MTK_FOE_STATE_UNBIND, +@@ -106,8 +117,13 @@ struct mtk_foe_mac_info { + u16 pppoe_id; + u16 src_mac_lo; + ++ /* netsys_v2 */ + u16 minfo; + u16 winfo; ++ ++ /* netsys_v3 */ ++ u32 w3info; ++ u32 wpao; + }; + + /* software-only entry type */ +@@ -218,6 +234,7 @@ struct mtk_foe_ipv6_6rd { + + #define MTK_FOE_ENTRY_V1_SIZE 80 + #define MTK_FOE_ENTRY_V2_SIZE 96 ++#define MTK_FOE_ENTRY_V3_SIZE 128 + + struct mtk_foe_entry { + u32 ib1; +@@ -228,7 +245,7 @@ struct mtk_foe_entry { + struct mtk_foe_ipv4_dslite dslite; + struct mtk_foe_ipv6 ipv6; + struct mtk_foe_ipv6_6rd ipv6_6rd; +- u32 data[23]; ++ u32 data[31]; + }; + }; + diff --git a/target/linux/generic/backport-5.15/750-v6.5-14-net-ethernet-mtk_eth_soc-support-per-flow-accounting.patch b/target/linux/generic/backport-5.15/750-v6.5-14-net-ethernet-mtk_eth_soc-support-per-flow-accounting.patch new file mode 100644 index 00000000000..f314550af64 --- /dev/null +++ b/target/linux/generic/backport-5.15/750-v6.5-14-net-ethernet-mtk_eth_soc-support-per-flow-accounting.patch @@ -0,0 +1,78 @@ +From 0c024632c1e7ff69914329bfd87bec749b9c0aed Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Wed, 2 Aug 2023 04:31:09 +0100 +Subject: [PATCH 108/250] net: ethernet: mtk_eth_soc: support per-flow + accounting on MT7988 + +NETSYS_V3 uses 64 bits for each counters while older SoCs are using +48/40 bits for each counter. +Support reading per-flow byte and package counters on NETSYS_V3. + +Signed-off-by: Daniel Golle +Reviewed-by: Simon Horman +Link: https://lore.kernel.org/r/37a0928fa8c1253b197884c68ce1f54239421ac5.1690946442.git.daniel@makrotopia.org +Signed-off-by: Paolo Abeni +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 1 + + drivers/net/ethernet/mediatek/mtk_ppe.c | 21 +++++++++++++------- + drivers/net/ethernet/mediatek/mtk_ppe_regs.h | 2 ++ + 3 files changed, 17 insertions(+), 7 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -4976,6 +4976,7 @@ static const struct mtk_soc_data mt7988_ + .version = 3, + .offload_version = 2, + .hash_offset = 4, ++ .has_accounting = true, + .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma_v2), +--- a/drivers/net/ethernet/mediatek/mtk_ppe.c ++++ b/drivers/net/ethernet/mediatek/mtk_ppe.c +@@ -91,7 +91,6 @@ static int mtk_ppe_mib_wait_busy(struct + + static int mtk_mib_entry_read(struct mtk_ppe *ppe, u16 index, u64 *bytes, u64 *packets) + { +- u32 byte_cnt_low, byte_cnt_high, pkt_cnt_low, pkt_cnt_high; + u32 val, cnt_r0, cnt_r1, cnt_r2; + int ret; + +@@ -106,12 +105,20 @@ static int mtk_mib_entry_read(struct mtk + cnt_r1 = readl(ppe->base + MTK_PPE_MIB_SER_R1); + cnt_r2 = readl(ppe->base + MTK_PPE_MIB_SER_R2); + +- byte_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R0_BYTE_CNT_LOW, cnt_r0); +- byte_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH, cnt_r1); +- pkt_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R1_PKT_CNT_LOW, cnt_r1); +- pkt_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH, cnt_r2); +- *bytes = ((u64)byte_cnt_high << 32) | byte_cnt_low; +- *packets = (pkt_cnt_high << 16) | pkt_cnt_low; ++ if (mtk_is_netsys_v3_or_greater(ppe->eth)) { ++ /* 64 bit for each counter */ ++ u32 cnt_r3 = readl(ppe->base + MTK_PPE_MIB_SER_R3); ++ *bytes = ((u64)cnt_r1 << 32) | cnt_r0; ++ *packets = ((u64)cnt_r3 << 32) | cnt_r2; ++ } else { ++ /* 48 bit byte counter, 40 bit packet counter */ ++ u32 byte_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R0_BYTE_CNT_LOW, cnt_r0); ++ u32 byte_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH, cnt_r1); ++ u32 pkt_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R1_PKT_CNT_LOW, cnt_r1); ++ u32 pkt_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH, cnt_r2); ++ *bytes = ((u64)byte_cnt_high << 32) | byte_cnt_low; ++ *packets = (pkt_cnt_high << 16) | pkt_cnt_low; ++ } + + return 0; + } +--- a/drivers/net/ethernet/mediatek/mtk_ppe_regs.h ++++ b/drivers/net/ethernet/mediatek/mtk_ppe_regs.h +@@ -163,6 +163,8 @@ enum { + #define MTK_PPE_MIB_SER_R2 0x348 + #define MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH GENMASK(23, 0) + ++#define MTK_PPE_MIB_SER_R3 0x34c ++ + #define MTK_PPE_MIB_CACHE_CTL 0x350 + #define MTK_PPE_MIB_CACHE_CTL_EN BIT(0) + #define MTK_PPE_MIB_CACHE_CTL_FLUSH BIT(2) diff --git a/target/linux/generic/backport-5.15/750-v6.5-15-net-ethernet-mtk_eth_soc-fix-NULL-pointer-on-hw-rese.patch b/target/linux/generic/backport-5.15/750-v6.5-15-net-ethernet-mtk_eth_soc-fix-NULL-pointer-on-hw-rese.patch new file mode 100644 index 00000000000..6f1639a5720 --- /dev/null +++ b/target/linux/generic/backport-5.15/750-v6.5-15-net-ethernet-mtk_eth_soc-fix-NULL-pointer-on-hw-rese.patch @@ -0,0 +1,52 @@ +From 3b12f42772c26869d60398c1710aa27b27cd945c Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Mon, 21 Aug 2023 17:12:44 +0100 +Subject: [PATCH 109/250] net: ethernet: mtk_eth_soc: fix NULL pointer on hw + reset + +When a hardware reset is triggered on devices not initializing WED the +calls to mtk_wed_fe_reset and mtk_wed_fe_reset_complete dereference a +pointer on uninitialized stack memory. +Break out of both functions in case a hw_list entry is 0. + +Fixes: 08a764a7c51b ("net: ethernet: mtk_wed: add reset/reset_complete callbacks") +Signed-off-by: Daniel Golle +Reviewed-by: Simon Horman +Acked-by: Lorenzo Bianconi +Link: https://lore.kernel.org/r/5465c1609b464cc7407ae1530c40821dcdf9d3e6.1692634266.git.daniel@makrotopia.org +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_wed.c | 12 ++++++++++-- + 1 file changed, 10 insertions(+), 2 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_wed.c ++++ b/drivers/net/ethernet/mediatek/mtk_wed.c +@@ -214,9 +214,13 @@ void mtk_wed_fe_reset(void) + + for (i = 0; i < ARRAY_SIZE(hw_list); i++) { + struct mtk_wed_hw *hw = hw_list[i]; +- struct mtk_wed_device *dev = hw->wed_dev; ++ struct mtk_wed_device *dev; + int err; + ++ if (!hw) ++ break; ++ ++ dev = hw->wed_dev; + if (!dev || !dev->wlan.reset) + continue; + +@@ -237,8 +241,12 @@ void mtk_wed_fe_reset_complete(void) + + for (i = 0; i < ARRAY_SIZE(hw_list); i++) { + struct mtk_wed_hw *hw = hw_list[i]; +- struct mtk_wed_device *dev = hw->wed_dev; ++ struct mtk_wed_device *dev; ++ ++ if (!hw) ++ break; + ++ dev = hw->wed_dev; + if (!dev || !dev->wlan.reset_complete) + continue; + diff --git a/target/linux/generic/backport-5.15/750-v6.5-16-net-ethernet-mtk_eth_soc-fix-register-definitions-fo.patch b/target/linux/generic/backport-5.15/750-v6.5-16-net-ethernet-mtk_eth_soc-fix-register-definitions-fo.patch new file mode 100644 index 00000000000..35977946d36 --- /dev/null +++ b/target/linux/generic/backport-5.15/750-v6.5-16-net-ethernet-mtk_eth_soc-fix-register-definitions-fo.patch @@ -0,0 +1,44 @@ +From 489aea123d74a846ce746bfdb3efe1e7ad512e0d Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Tue, 22 Aug 2023 17:31:24 +0100 +Subject: [PATCH 110/250] net: ethernet: mtk_eth_soc: fix register definitions + for MT7988 + +More register macros need to be adjusted for the 3rd GMAC on MT7988. +Account for added bit in SYSCFG0_SGMII_MASK. + +Fixes: 445eb6448ed3 ("net: ethernet: mtk_eth_soc: add basic support for MT7988 SoC") +Signed-off-by: Daniel Golle +Reviewed-by: Simon Horman +Link: https://lore.kernel.org/r/1c8da012e2ca80939906d85f314138c552139f0f.1692721443.git.daniel@makrotopia.org +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -133,10 +133,12 @@ + #define MTK_GDMA_XGDM_SEL BIT(31) + + /* Unicast Filter MAC Address Register - Low */ +-#define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) ++#define MTK_GDMA_MAC_ADRL(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \ ++ 0x548 : 0x508 + (_x * 0x1000); }) + + /* Unicast Filter MAC Address Register - High */ +-#define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) ++#define MTK_GDMA_MAC_ADRH(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \ ++ 0x54C : 0x50C + (_x * 0x1000); }) + + /* FE global misc reg*/ + #define MTK_FE_GLO_MISC 0x124 +@@ -500,7 +502,7 @@ + #define ETHSYS_SYSCFG0 0x14 + #define SYSCFG0_GE_MASK 0x3 + #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) +-#define SYSCFG0_SGMII_MASK GENMASK(9, 8) ++#define SYSCFG0_SGMII_MASK GENMASK(9, 7) + #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK) + #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) + #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) diff --git a/target/linux/generic/backport-5.15/750-v6.5-17-net-ethernet-mtk_eth_soc-add-reset-bits-for-MT7988.patch b/target/linux/generic/backport-5.15/750-v6.5-17-net-ethernet-mtk_eth_soc-add-reset-bits-for-MT7988.patch new file mode 100644 index 00000000000..5f6651b7b02 --- /dev/null +++ b/target/linux/generic/backport-5.15/750-v6.5-17-net-ethernet-mtk_eth_soc-add-reset-bits-for-MT7988.patch @@ -0,0 +1,188 @@ +From 15a84d1c44ae8c1451c265ee60500588a24e8cd6 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Tue, 22 Aug 2023 17:32:03 +0100 +Subject: [PATCH 111/250] net: ethernet: mtk_eth_soc: add reset bits for MT7988 + +Add bits needed to reset the frame engine on MT7988. + +Fixes: 445eb6448ed3 ("net: ethernet: mtk_eth_soc: add basic support for MT7988 SoC") +Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/89b6c38380e7a3800c1362aa7575600717bc7543.1692721443.git.daniel@makrotopia.org +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 76 +++++++++++++++------ + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 16 +++-- + 2 files changed, 68 insertions(+), 24 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -3538,19 +3538,34 @@ static void mtk_hw_reset(struct mtk_eth + { + u32 val; + +- if (mtk_is_netsys_v2_or_greater(eth)) { ++ if (mtk_is_netsys_v2_or_greater(eth)) + regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); ++ ++ if (mtk_is_netsys_v3_or_greater(eth)) { ++ val = RSTCTRL_PPE0_V3; ++ ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) ++ val |= RSTCTRL_PPE1_V3; ++ ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) ++ val |= RSTCTRL_PPE2; ++ ++ val |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2; ++ } else if (mtk_is_netsys_v2_or_greater(eth)) { + val = RSTCTRL_PPE0_V2; ++ ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) ++ val |= RSTCTRL_PPE1; + } else { + val = RSTCTRL_PPE0; + } + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) +- val |= RSTCTRL_PPE1; +- + ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val); + +- if (mtk_is_netsys_v2_or_greater(eth)) ++ if (mtk_is_netsys_v3_or_greater(eth)) ++ regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, ++ 0x6f8ff); ++ else if (mtk_is_netsys_v2_or_greater(eth)) + regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, + 0x3ffffff); + } +@@ -3576,13 +3591,21 @@ static void mtk_hw_warm_reset(struct mtk + return; + } + +- if (mtk_is_netsys_v2_or_greater(eth)) ++ if (mtk_is_netsys_v3_or_greater(eth)) { ++ rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V3; ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) ++ rst_mask |= RSTCTRL_PPE1_V3; ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) ++ rst_mask |= RSTCTRL_PPE2; ++ ++ rst_mask |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2; ++ } else if (mtk_is_netsys_v2_or_greater(eth)) { + rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2; +- else ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) ++ rst_mask |= RSTCTRL_PPE1; ++ } else { + rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0; +- +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) +- rst_mask |= RSTCTRL_PPE1; ++ } + + regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, rst_mask); + +@@ -3934,11 +3957,17 @@ static void mtk_prepare_for_reset(struct + u32 val; + int i; + +- /* disabe FE P3 and P4 */ +- val = mtk_r32(eth, MTK_FE_GLO_CFG) | MTK_FE_LINK_DOWN_P3; +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) +- val |= MTK_FE_LINK_DOWN_P4; +- mtk_w32(eth, val, MTK_FE_GLO_CFG); ++ /* set FE PPE ports link down */ ++ for (i = MTK_GMAC1_ID; ++ i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID); ++ i += 2) { ++ val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) | MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT); ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) ++ val |= MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT); ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) ++ val |= MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT); ++ mtk_w32(eth, val, MTK_FE_GLO_CFG(i)); ++ } + + /* adjust PPE configurations to prepare for reset */ + for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) +@@ -3999,11 +4028,18 @@ static void mtk_pending_work(struct work + } + } + +- /* enabe FE P3 and P4 */ +- val = mtk_r32(eth, MTK_FE_GLO_CFG) & ~MTK_FE_LINK_DOWN_P3; +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) +- val &= ~MTK_FE_LINK_DOWN_P4; +- mtk_w32(eth, val, MTK_FE_GLO_CFG); ++ /* set FE PPE ports link up */ ++ for (i = MTK_GMAC1_ID; ++ i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID); ++ i += 2) { ++ val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) & ~MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT); ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) ++ val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT); ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) ++ val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT); ++ ++ mtk_w32(eth, val, MTK_FE_GLO_CFG(i)); ++ } + + clear_bit(MTK_RESETTING, ð->state); + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -76,9 +76,8 @@ + #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 + + /* Frame Engine Global Configuration */ +-#define MTK_FE_GLO_CFG 0x00 +-#define MTK_FE_LINK_DOWN_P3 BIT(11) +-#define MTK_FE_LINK_DOWN_P4 BIT(12) ++#define MTK_FE_GLO_CFG(x) (((x) == MTK_GMAC3_ID) ? 0x24 : 0x00) ++#define MTK_FE_LINK_DOWN_P(x) BIT(((x) + 8) % 16) + + /* Frame Engine Global Reset Register */ + #define MTK_RST_GL 0x04 +@@ -519,9 +518,15 @@ + /* ethernet reset control register */ + #define ETHSYS_RSTCTRL 0x34 + #define RSTCTRL_FE BIT(6) ++#define RSTCTRL_WDMA0 BIT(24) ++#define RSTCTRL_WDMA1 BIT(25) ++#define RSTCTRL_WDMA2 BIT(26) + #define RSTCTRL_PPE0 BIT(31) + #define RSTCTRL_PPE0_V2 BIT(30) + #define RSTCTRL_PPE1 BIT(31) ++#define RSTCTRL_PPE0_V3 BIT(29) ++#define RSTCTRL_PPE1_V3 BIT(30) ++#define RSTCTRL_PPE2 BIT(31) + #define RSTCTRL_ETH BIT(23) + + /* ethernet reset check idle register */ +@@ -928,6 +933,7 @@ enum mkt_eth_capabilities { + MTK_QDMA_BIT, + MTK_SOC_MT7628_BIT, + MTK_RSTCTRL_PPE1_BIT, ++ MTK_RSTCTRL_PPE2_BIT, + MTK_U3_COPHY_V2_BIT, + + /* MUX BITS*/ +@@ -962,6 +968,7 @@ enum mkt_eth_capabilities { + #define MTK_QDMA BIT_ULL(MTK_QDMA_BIT) + #define MTK_SOC_MT7628 BIT_ULL(MTK_SOC_MT7628_BIT) + #define MTK_RSTCTRL_PPE1 BIT_ULL(MTK_RSTCTRL_PPE1_BIT) ++#define MTK_RSTCTRL_PPE2 BIT_ULL(MTK_RSTCTRL_PPE2_BIT) + #define MTK_U3_COPHY_V2 BIT_ULL(MTK_U3_COPHY_V2_BIT) + + #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ +@@ -1044,7 +1051,8 @@ enum mkt_eth_capabilities { + MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ + MTK_RSTCTRL_PPE1) + +-#define MT7988_CAPS (MTK_GDM1_ESW | MTK_QDMA | MTK_RSTCTRL_PPE1) ++#define MT7988_CAPS (MTK_GDM1_ESW | MTK_QDMA | MTK_RSTCTRL_PPE1 | \ ++ MTK_RSTCTRL_PPE2) + + struct mtk_tx_dma_desc_info { + dma_addr_t addr; diff --git a/target/linux/generic/backport-5.15/750-v6.5-18-net-ethernet-mtk_eth_soc-add-support-for-in-SoC-SRAM.patch b/target/linux/generic/backport-5.15/750-v6.5-18-net-ethernet-mtk_eth_soc-add-support-for-in-SoC-SRAM.patch new file mode 100644 index 00000000000..67ba1a5f0a5 --- /dev/null +++ b/target/linux/generic/backport-5.15/750-v6.5-18-net-ethernet-mtk_eth_soc-add-support-for-in-SoC-SRAM.patch @@ -0,0 +1,254 @@ +From 25ce45fe40b574e5d7ffa407f7f2db03e7d5a910 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Tue, 22 Aug 2023 17:32:54 +0100 +Subject: [PATCH 112/250] net: ethernet: mtk_eth_soc: add support for in-SoC + SRAM + +MT7981, MT7986 and MT7988 come with in-SoC SRAM dedicated for Ethernet +DMA rings. Support using the SRAM without breaking existing device tree +bindings, ie. only new SoC starting from MT7988 will have the SRAM +declared as additional resource in device tree. For MT7981 and MT7986 +an offset on top of the main I/O base is used. + +Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/e45e0f230c63ad58869e8fe35b95a2fb8925b625.1692721443.git.daniel@makrotopia.org +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 88 ++++++++++++++++----- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 12 ++- + 2 files changed, 78 insertions(+), 22 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -1075,10 +1075,13 @@ static int mtk_init_fq_dma(struct mtk_et + dma_addr_t dma_addr; + int i; + +- eth->scratch_ring = dma_alloc_coherent(eth->dma_dev, +- cnt * soc->txrx.txd_size, +- ð->phy_scratch_ring, +- GFP_KERNEL); ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) ++ eth->scratch_ring = eth->sram_base; ++ else ++ eth->scratch_ring = dma_alloc_coherent(eth->dma_dev, ++ cnt * soc->txrx.txd_size, ++ ð->phy_scratch_ring, ++ GFP_KERNEL); + if (unlikely(!eth->scratch_ring)) + return -ENOMEM; + +@@ -2376,8 +2379,14 @@ static int mtk_tx_alloc(struct mtk_eth * + if (!ring->buf) + goto no_tx_mem; + +- ring->dma = dma_alloc_coherent(eth->dma_dev, ring_size * sz, +- &ring->phys, GFP_KERNEL); ++ if (MTK_HAS_CAPS(soc->caps, MTK_SRAM)) { ++ ring->dma = eth->sram_base + ring_size * sz; ++ ring->phys = eth->phy_scratch_ring + ring_size * (dma_addr_t)sz; ++ } else { ++ ring->dma = dma_alloc_coherent(eth->dma_dev, ring_size * sz, ++ &ring->phys, GFP_KERNEL); ++ } ++ + if (!ring->dma) + goto no_tx_mem; + +@@ -2476,8 +2485,7 @@ static void mtk_tx_clean(struct mtk_eth + kfree(ring->buf); + ring->buf = NULL; + } +- +- if (ring->dma) { ++ if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && ring->dma) { + dma_free_coherent(eth->dma_dev, + ring->dma_size * soc->txrx.txd_size, + ring->dma, ring->phys); +@@ -2496,9 +2504,14 @@ static int mtk_rx_alloc(struct mtk_eth * + { + const struct mtk_reg_map *reg_map = eth->soc->reg_map; + struct mtk_rx_ring *ring; +- int rx_data_len, rx_dma_size; ++ int rx_data_len, rx_dma_size, tx_ring_size; + int i; + ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) ++ tx_ring_size = MTK_QDMA_RING_SIZE; ++ else ++ tx_ring_size = MTK_DMA_SIZE; ++ + if (rx_flag == MTK_RX_FLAGS_QDMA) { + if (ring_no) + return -EINVAL; +@@ -2533,9 +2546,20 @@ static int mtk_rx_alloc(struct mtk_eth * + ring->page_pool = pp; + } + +- ring->dma = dma_alloc_coherent(eth->dma_dev, +- rx_dma_size * eth->soc->txrx.rxd_size, +- &ring->phys, GFP_KERNEL); ++ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM) || ++ rx_flag != MTK_RX_FLAGS_NORMAL) { ++ ring->dma = dma_alloc_coherent(eth->dma_dev, ++ rx_dma_size * eth->soc->txrx.rxd_size, ++ &ring->phys, GFP_KERNEL); ++ } else { ++ struct mtk_tx_ring *tx_ring = ð->tx_ring; ++ ++ ring->dma = tx_ring->dma + tx_ring_size * ++ eth->soc->txrx.txd_size * (ring_no + 1); ++ ring->phys = tx_ring->phys + tx_ring_size * ++ eth->soc->txrx.txd_size * (ring_no + 1); ++ } ++ + if (!ring->dma) + return -ENOMEM; + +@@ -2618,7 +2642,7 @@ static int mtk_rx_alloc(struct mtk_eth * + return 0; + } + +-static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring) ++static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring, bool in_sram) + { + int i; + +@@ -2641,7 +2665,7 @@ static void mtk_rx_clean(struct mtk_eth + ring->data = NULL; + } + +- if (ring->dma) { ++ if (!in_sram && ring->dma) { + dma_free_coherent(eth->dma_dev, + ring->dma_size * eth->soc->txrx.rxd_size, + ring->dma, ring->phys); +@@ -3001,7 +3025,7 @@ static void mtk_dma_free(struct mtk_eth + for (i = 0; i < MTK_MAX_DEVS; i++) + if (eth->netdev[i]) + netdev_reset_queue(eth->netdev[i]); +- if (eth->scratch_ring) { ++ if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) { + dma_free_coherent(eth->dma_dev, + MTK_QDMA_RING_SIZE * soc->txrx.txd_size, + eth->scratch_ring, eth->phy_scratch_ring); +@@ -3009,13 +3033,13 @@ static void mtk_dma_free(struct mtk_eth + eth->phy_scratch_ring = 0; + } + mtk_tx_clean(eth); +- mtk_rx_clean(eth, ð->rx_ring[0]); +- mtk_rx_clean(eth, ð->rx_ring_qdma); ++ mtk_rx_clean(eth, ð->rx_ring[0], MTK_HAS_CAPS(soc->caps, MTK_SRAM)); ++ mtk_rx_clean(eth, ð->rx_ring_qdma, false); + + if (eth->hwlro) { + mtk_hwlro_rx_uninit(eth); + for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) +- mtk_rx_clean(eth, ð->rx_ring[i]); ++ mtk_rx_clean(eth, ð->rx_ring[i], false); + } + + kfree(eth->scratch_head); +@@ -4585,7 +4609,7 @@ static int mtk_sgmii_init(struct mtk_eth + + static int mtk_probe(struct platform_device *pdev) + { +- struct resource *res = NULL; ++ struct resource *res = NULL, *res_sram; + struct device_node *mac_np; + struct mtk_eth *eth; + int err, i; +@@ -4605,6 +4629,20 @@ static int mtk_probe(struct platform_dev + if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) + eth->ip_align = NET_IP_ALIGN; + ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) { ++ /* SRAM is actual memory and supports transparent access just like DRAM. ++ * Hence we don't require __iomem being set and don't need to use accessor ++ * functions to read from or write to SRAM. ++ */ ++ if (mtk_is_netsys_v3_or_greater(eth)) { ++ eth->sram_base = (void __force *)devm_platform_ioremap_resource(pdev, 1); ++ if (IS_ERR(eth->sram_base)) ++ return PTR_ERR(eth->sram_base); ++ } else { ++ eth->sram_base = (void __force *)eth->base + MTK_ETH_SRAM_OFFSET; ++ } ++ } ++ + spin_lock_init(ð->page_lock); + spin_lock_init(ð->tx_irq_lock); + spin_lock_init(ð->rx_irq_lock); +@@ -4668,6 +4706,18 @@ static int mtk_probe(struct platform_dev + err = -EINVAL; + goto err_destroy_sgmii; + } ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) { ++ if (mtk_is_netsys_v3_or_greater(eth)) { ++ res_sram = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ if (!res_sram) { ++ err = -EINVAL; ++ goto err_destroy_sgmii; ++ } ++ eth->phy_scratch_ring = res_sram->start; ++ } else { ++ eth->phy_scratch_ring = res->start + MTK_ETH_SRAM_OFFSET; ++ } ++ } + } + + if (eth->soc->offload_version) { +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -139,6 +139,9 @@ + #define MTK_GDMA_MAC_ADRH(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \ + 0x54C : 0x50C + (_x * 0x1000); }) + ++/* Internal SRAM offset */ ++#define MTK_ETH_SRAM_OFFSET 0x40000 ++ + /* FE global misc reg*/ + #define MTK_FE_GLO_MISC 0x124 + +@@ -935,6 +938,7 @@ enum mkt_eth_capabilities { + MTK_RSTCTRL_PPE1_BIT, + MTK_RSTCTRL_PPE2_BIT, + MTK_U3_COPHY_V2_BIT, ++ MTK_SRAM_BIT, + + /* MUX BITS*/ + MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, +@@ -970,6 +974,7 @@ enum mkt_eth_capabilities { + #define MTK_RSTCTRL_PPE1 BIT_ULL(MTK_RSTCTRL_PPE1_BIT) + #define MTK_RSTCTRL_PPE2 BIT_ULL(MTK_RSTCTRL_PPE2_BIT) + #define MTK_U3_COPHY_V2 BIT_ULL(MTK_U3_COPHY_V2_BIT) ++#define MTK_SRAM BIT_ULL(MTK_SRAM_BIT) + + #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ + BIT_ULL(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) +@@ -1045,14 +1050,14 @@ enum mkt_eth_capabilities { + #define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ + MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ + MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \ +- MTK_RSTCTRL_PPE1) ++ MTK_RSTCTRL_PPE1 | MTK_SRAM) + + #define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ + MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ +- MTK_RSTCTRL_PPE1) ++ MTK_RSTCTRL_PPE1 | MTK_SRAM) + + #define MT7988_CAPS (MTK_GDM1_ESW | MTK_QDMA | MTK_RSTCTRL_PPE1 | \ +- MTK_RSTCTRL_PPE2) ++ MTK_RSTCTRL_PPE2 | MTK_SRAM) + + struct mtk_tx_dma_desc_info { + dma_addr_t addr; +@@ -1212,6 +1217,7 @@ struct mtk_eth { + struct device *dev; + struct device *dma_dev; + void __iomem *base; ++ void *sram_base; + spinlock_t page_lock; + spinlock_t tx_irq_lock; + spinlock_t rx_irq_lock; diff --git a/target/linux/generic/backport-5.15/750-v6.5-19-net-ethernet-mtk_eth_soc-support-36-bit-DMA-addressi.patch b/target/linux/generic/backport-5.15/750-v6.5-19-net-ethernet-mtk_eth_soc-support-36-bit-DMA-addressi.patch new file mode 100644 index 00000000000..175db56c37b --- /dev/null +++ b/target/linux/generic/backport-5.15/750-v6.5-19-net-ethernet-mtk_eth_soc-support-36-bit-DMA-addressi.patch @@ -0,0 +1,166 @@ +From 0b0d606eb9650fa01dd5621e072aa29a10544399 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Tue, 22 Aug 2023 17:33:12 +0100 +Subject: [PATCH 113/250] net: ethernet: mtk_eth_soc: support 36-bit DMA + addressing on MT7988 + +Systems having 4 GiB of RAM and more require DMA addressing beyond the +current 32-bit limit. Starting from MT7988 the hardware now supports +36-bit DMA addressing, let's use that new capability in the driver to +avoid running into swiotlb on systems with 4 GiB of RAM or more. + +Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/95b919c98876c9e49761e44662e7c937479eecb8.1692721443.git.daniel@makrotopia.org +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 30 +++++++++++++++++++-- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 22 +++++++++++++-- + 2 files changed, 48 insertions(+), 4 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -1266,6 +1266,10 @@ static void mtk_tx_set_dma_desc_v2(struc + data = TX_DMA_PLEN0(info->size); + if (info->last) + data |= TX_DMA_LS0; ++ ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) ++ data |= TX_DMA_PREP_ADDR64(info->addr); ++ + WRITE_ONCE(desc->txd3, data); + + /* set forward port */ +@@ -1933,6 +1937,7 @@ static int mtk_poll_rx(struct napi_struc + bool xdp_flush = false; + int idx; + struct sk_buff *skb; ++ u64 addr64 = 0; + u8 *data, *new_data; + struct mtk_rx_dma_v2 *rxd, trxd; + int done = 0, bytes = 0; +@@ -2048,7 +2053,10 @@ static int mtk_poll_rx(struct napi_struc + goto release_desc; + } + +- dma_unmap_single(eth->dma_dev, trxd.rxd1, ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) ++ addr64 = RX_DMA_GET_ADDR64(trxd.rxd2); ++ ++ dma_unmap_single(eth->dma_dev, ((u64)trxd.rxd1 | addr64), + ring->buf_size, DMA_FROM_DEVICE); + + skb = build_skb(data, ring->frag_size); +@@ -2114,6 +2122,9 @@ release_desc: + else + rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); + ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) ++ rxd->rxd2 |= RX_DMA_PREP_ADDR64(dma_addr); ++ + ring->calc_idx = idx; + done++; + } +@@ -2598,6 +2609,9 @@ static int mtk_rx_alloc(struct mtk_eth * + else + rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); + ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) ++ rxd->rxd2 |= RX_DMA_PREP_ADDR64(dma_addr); ++ + rxd->rxd3 = 0; + rxd->rxd4 = 0; + if (mtk_is_netsys_v2_or_greater(eth)) { +@@ -2644,6 +2658,7 @@ static int mtk_rx_alloc(struct mtk_eth * + + static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring, bool in_sram) + { ++ u64 addr64 = 0; + int i; + + if (ring->data && ring->dma) { +@@ -2657,7 +2672,10 @@ static void mtk_rx_clean(struct mtk_eth + if (!rxd->rxd1) + continue; + +- dma_unmap_single(eth->dma_dev, rxd->rxd1, ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) ++ addr64 = RX_DMA_GET_ADDR64(rxd->rxd2); ++ ++ dma_unmap_single(eth->dma_dev, ((u64)rxd->rxd1 | addr64), + ring->buf_size, DMA_FROM_DEVICE); + mtk_rx_put_buff(ring, ring->data[i], false); + } +@@ -4643,6 +4661,14 @@ static int mtk_probe(struct platform_dev + } + } + ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) { ++ err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(36)); ++ if (err) { ++ dev_err(&pdev->dev, "Wrong DMA config\n"); ++ return -EINVAL; ++ } ++ } ++ + spin_lock_init(ð->page_lock); + spin_lock_init(ð->tx_irq_lock); + spin_lock_init(ð->rx_irq_lock); +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -331,6 +331,14 @@ + #define TX_DMA_PLEN1(x) ((x) & eth->soc->txrx.dma_max_len) + #define TX_DMA_SWC BIT(14) + #define TX_DMA_PQID GENMASK(3, 0) ++#define TX_DMA_ADDR64_MASK GENMASK(3, 0) ++#if IS_ENABLED(CONFIG_64BIT) ++# define TX_DMA_GET_ADDR64(x) (((u64)FIELD_GET(TX_DMA_ADDR64_MASK, (x))) << 32) ++# define TX_DMA_PREP_ADDR64(x) FIELD_PREP(TX_DMA_ADDR64_MASK, ((x) >> 32)) ++#else ++# define TX_DMA_GET_ADDR64(x) (0) ++# define TX_DMA_PREP_ADDR64(x) (0) ++#endif + + /* PDMA on MT7628 */ + #define TX_DMA_DONE BIT(31) +@@ -343,6 +351,14 @@ + #define RX_DMA_PREP_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset) + #define RX_DMA_GET_PLEN0(x) (((x) >> eth->soc->txrx.dma_len_offset) & eth->soc->txrx.dma_max_len) + #define RX_DMA_VTAG BIT(15) ++#define RX_DMA_ADDR64_MASK GENMASK(3, 0) ++#if IS_ENABLED(CONFIG_64BIT) ++# define RX_DMA_GET_ADDR64(x) (((u64)FIELD_GET(RX_DMA_ADDR64_MASK, (x))) << 32) ++# define RX_DMA_PREP_ADDR64(x) FIELD_PREP(RX_DMA_ADDR64_MASK, ((x) >> 32)) ++#else ++# define RX_DMA_GET_ADDR64(x) (0) ++# define RX_DMA_PREP_ADDR64(x) (0) ++#endif + + /* QDMA descriptor rxd3 */ + #define RX_DMA_VID(x) ((x) & VLAN_VID_MASK) +@@ -939,6 +955,7 @@ enum mkt_eth_capabilities { + MTK_RSTCTRL_PPE2_BIT, + MTK_U3_COPHY_V2_BIT, + MTK_SRAM_BIT, ++ MTK_36BIT_DMA_BIT, + + /* MUX BITS*/ + MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, +@@ -975,6 +992,7 @@ enum mkt_eth_capabilities { + #define MTK_RSTCTRL_PPE2 BIT_ULL(MTK_RSTCTRL_PPE2_BIT) + #define MTK_U3_COPHY_V2 BIT_ULL(MTK_U3_COPHY_V2_BIT) + #define MTK_SRAM BIT_ULL(MTK_SRAM_BIT) ++#define MTK_36BIT_DMA BIT_ULL(MTK_36BIT_DMA_BIT) + + #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ + BIT_ULL(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) +@@ -1056,8 +1074,8 @@ enum mkt_eth_capabilities { + MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ + MTK_RSTCTRL_PPE1 | MTK_SRAM) + +-#define MT7988_CAPS (MTK_GDM1_ESW | MTK_QDMA | MTK_RSTCTRL_PPE1 | \ +- MTK_RSTCTRL_PPE2 | MTK_SRAM) ++#define MT7988_CAPS (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_QDMA | \ ++ MTK_RSTCTRL_PPE1 | MTK_RSTCTRL_PPE2 | MTK_SRAM) + + struct mtk_tx_dma_desc_info { + dma_addr_t addr; diff --git a/target/linux/generic/backport-5.15/792-01-v6.0-net-phylink-disable-PCS-polling-over-major-configura.patch b/target/linux/generic/backport-5.15/792-01-v6.0-net-phylink-disable-PCS-polling-over-major-configura.patch new file mode 100644 index 00000000000..cda77e3e2d8 --- /dev/null +++ b/target/linux/generic/backport-5.15/792-01-v6.0-net-phylink-disable-PCS-polling-over-major-configura.patch @@ -0,0 +1,81 @@ +From bfac8c490d605bea03b1f1927582b6f396462164 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Mon, 27 Jun 2022 12:44:43 +0100 +Subject: [PATCH] net: phylink: disable PCS polling over major configuration + +While we are performing a major configuration, there is no point having +the PCS polling timer running. Stop it before we begin preparing for +the configuration change, and restart it only once we've successfully +completed the change. + +Reviewed-by: Andrew Lunn +Signed-off-by: Russell King (Oracle) +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/phylink.c | 30 ++++++++++++++++++++---------- + 1 file changed, 20 insertions(+), 10 deletions(-) + +--- a/drivers/net/phy/phylink.c ++++ b/drivers/net/phy/phylink.c +@@ -756,6 +756,18 @@ static void phylink_resolve_flow(struct + } + } + ++static void phylink_pcs_poll_stop(struct phylink *pl) ++{ ++ if (pl->cfg_link_an_mode == MLO_AN_INBAND) ++ del_timer(&pl->link_poll); ++} ++ ++static void phylink_pcs_poll_start(struct phylink *pl) ++{ ++ if (pl->pcs->poll && pl->cfg_link_an_mode == MLO_AN_INBAND) ++ mod_timer(&pl->link_poll, jiffies + HZ); ++} ++ + static void phylink_mac_config(struct phylink *pl, + const struct phylink_link_state *state) + { +@@ -787,6 +799,7 @@ static void phylink_major_config(struct + const struct phylink_link_state *state) + { + struct phylink_pcs *pcs = NULL; ++ bool pcs_changed = false; + int err; + + phylink_dbg(pl, "major config %s\n", phy_modes(state->interface)); +@@ -799,8 +812,12 @@ static void phylink_major_config(struct + pcs); + return; + } ++ ++ pcs_changed = pcs && pl->pcs != pcs; + } + ++ phylink_pcs_poll_stop(pl); ++ + if (pl->mac_ops->mac_prepare) { + err = pl->mac_ops->mac_prepare(pl->config, pl->cur_link_an_mode, + state->interface); +@@ -814,8 +831,10 @@ static void phylink_major_config(struct + /* If we have a new PCS, switch to the new PCS after preparing the MAC + * for the change. + */ +- if (pcs) +- phylink_set_pcs(pl, pcs); ++ if (pcs_changed) { ++ pl->pcs = pcs; ++ pl->pcs_ops = pcs->ops; ++ } + + phylink_mac_config(pl, state); + +@@ -841,6 +860,8 @@ static void phylink_major_config(struct + phylink_err(pl, "mac_finish failed: %pe\n", + ERR_PTR(err)); + } ++ ++ phylink_pcs_poll_start(pl); + } + + /* diff --git a/target/linux/generic/backport-5.15/792-02-v6.0-net-phylink-fix-NULL-pl-pcs-dereference-during-phyli.patch b/target/linux/generic/backport-5.15/792-02-v6.0-net-phylink-fix-NULL-pl-pcs-dereference-during-phyli.patch new file mode 100644 index 00000000000..f1f359bad7a --- /dev/null +++ b/target/linux/generic/backport-5.15/792-02-v6.0-net-phylink-fix-NULL-pl-pcs-dereference-during-phyli.patch @@ -0,0 +1,38 @@ +From b7d78b46d5e8dc77c656c13885d31e931923b915 Mon Sep 17 00:00:00 2001 +From: Vladimir Oltean +Date: Wed, 29 Jun 2022 22:33:58 +0300 +Subject: [PATCH] net: phylink: fix NULL pl->pcs dereference during + phylink_pcs_poll_start + +The current link mode of the phylink instance may not require an +attached PCS. However, phylink_major_config() unconditionally +dereferences this potentially NULL pointer when restarting the link poll +timer, which will panic the kernel. + +Fix the problem by checking whether a PCS exists in phylink_pcs_poll_start(), +otherwise do nothing. The code prior to the blamed patch also only +looked at pcs->poll within an "if (pcs)" block. + +Fixes: bfac8c490d60 ("net: phylink: disable PCS polling over major configuration") +Signed-off-by: Vladimir Oltean +Reviewed-by: Russell King (Oracle) +Tested-by: Gerhard Engleder +Tested-by: Michael Walle # on kontron-kbox-a-230-ls +Tested-by: Nicolas Ferre # on sam9x60ek +Link: https://lore.kernel.org/r/20220629193358.4007923-1-vladimir.oltean@nxp.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/phylink.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/phy/phylink.c ++++ b/drivers/net/phy/phylink.c +@@ -764,7 +764,7 @@ static void phylink_pcs_poll_stop(struct + + static void phylink_pcs_poll_start(struct phylink *pl) + { +- if (pl->pcs->poll && pl->cfg_link_an_mode == MLO_AN_INBAND) ++ if (pl->pcs && pl->pcs->poll && pl->cfg_link_an_mode == MLO_AN_INBAND) + mod_timer(&pl->link_poll, jiffies + HZ); + } + diff --git a/target/linux/generic/backport-5.15/792-03-v6.6-net-phylink-add-pcs_enable-pcs_disable-methods.patch b/target/linux/generic/backport-5.15/792-03-v6.6-net-phylink-add-pcs_enable-pcs_disable-methods.patch new file mode 100644 index 00000000000..ceec58466e1 --- /dev/null +++ b/target/linux/generic/backport-5.15/792-03-v6.6-net-phylink-add-pcs_enable-pcs_disable-methods.patch @@ -0,0 +1,172 @@ +From 90ef0a7b0622c62758b2638604927867775479ea Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Thu, 13 Jul 2023 09:42:07 +0100 +Subject: [PATCH] net: phylink: add pcs_enable()/pcs_disable() methods + +Add phylink PCS enable/disable callbacks that will allow us to place +IEEE 802.3 register compliant PCS in power-down mode while not being +used. + +Signed-off-by: Russell King (Oracle) +Signed-off-by: David S. Miller +--- + drivers/net/phy/phylink.c | 48 +++++++++++++++++++++++++++++++-------- + include/linux/phylink.h | 16 +++++++++++++ + 2 files changed, 55 insertions(+), 9 deletions(-) + +--- a/drivers/net/phy/phylink.c ++++ b/drivers/net/phy/phylink.c +@@ -34,6 +34,10 @@ enum { + PHYLINK_DISABLE_STOPPED, + PHYLINK_DISABLE_LINK, + PHYLINK_DISABLE_MAC_WOL, ++ ++ PCS_STATE_DOWN = 0, ++ PCS_STATE_STARTING, ++ PCS_STATE_STARTED, + }; + + /** +@@ -72,6 +76,7 @@ struct phylink { + struct mutex state_mutex; + struct phylink_link_state phy_state; + struct work_struct resolve; ++ unsigned int pcs_state; + + bool mac_link_dropped; + bool using_mac_select_pcs; +@@ -795,6 +800,22 @@ static void phylink_mac_pcs_an_restart(s + } + } + ++static void phylink_pcs_disable(struct phylink_pcs *pcs) ++{ ++ if (pcs && pcs->ops->pcs_disable) ++ pcs->ops->pcs_disable(pcs); ++} ++ ++static int phylink_pcs_enable(struct phylink_pcs *pcs) ++{ ++ int err = 0; ++ ++ if (pcs && pcs->ops->pcs_enable) ++ err = pcs->ops->pcs_enable(pcs); ++ ++ return err; ++} ++ + static void phylink_major_config(struct phylink *pl, bool restart, + const struct phylink_link_state *state) + { +@@ -832,12 +853,16 @@ static void phylink_major_config(struct + * for the change. + */ + if (pcs_changed) { ++ phylink_pcs_disable(pl->pcs); + pl->pcs = pcs; + pl->pcs_ops = pcs->ops; + } + + phylink_mac_config(pl, state); + ++ if (pl->pcs_state == PCS_STATE_STARTING || pcs_changed) ++ phylink_pcs_enable(pl->pcs); ++ + if (pl->pcs_ops) { + err = pl->pcs_ops->pcs_config(pl->pcs, pl->cur_link_an_mode, + state->interface, +@@ -1260,6 +1285,7 @@ struct phylink *phylink_create(struct ph + pl->link_config.speed = SPEED_UNKNOWN; + pl->link_config.duplex = DUPLEX_UNKNOWN; + pl->link_config.an_enabled = true; ++ pl->pcs_state = PCS_STATE_DOWN; + pl->mac_ops = mac_ops; + __set_bit(PHYLINK_DISABLE_STOPPED, &pl->phylink_disable_state); + timer_setup(&pl->link_poll, phylink_fixed_poll, 0); +@@ -1651,6 +1677,8 @@ void phylink_start(struct phylink *pl) + if (pl->netdev) + netif_carrier_off(pl->netdev); + ++ pl->pcs_state = PCS_STATE_STARTING; ++ + /* Apply the link configuration to the MAC when starting. This allows + * a fixed-link to start with the correct parameters, and also + * ensures that we set the appropriate advertisement for Serdes links. +@@ -1661,6 +1689,8 @@ void phylink_start(struct phylink *pl) + */ + phylink_mac_initial_config(pl, true); + ++ pl->pcs_state = PCS_STATE_STARTED; ++ + clear_bit(PHYLINK_DISABLE_STOPPED, &pl->phylink_disable_state); + phylink_run_resolve(pl); + +@@ -1680,16 +1710,9 @@ void phylink_start(struct phylink *pl) + poll = true; + } + +- switch (pl->cfg_link_an_mode) { +- case MLO_AN_FIXED: ++ if (pl->cfg_link_an_mode == MLO_AN_FIXED) + poll |= pl->config->poll_fixed_state; +- break; +- case MLO_AN_INBAND: +- poll |= pl->config->pcs_poll; +- if (pl->pcs) +- poll |= pl->pcs->poll; +- break; +- } ++ + if (poll) + mod_timer(&pl->link_poll, jiffies + HZ); + if (pl->phydev) +@@ -1726,6 +1749,10 @@ void phylink_stop(struct phylink *pl) + } + + phylink_run_resolve_and_disable(pl, PHYLINK_DISABLE_STOPPED); ++ ++ pl->pcs_state = PCS_STATE_DOWN; ++ ++ phylink_pcs_disable(pl->pcs); + } + EXPORT_SYMBOL_GPL(phylink_stop); + +--- a/include/linux/phylink.h ++++ b/include/linux/phylink.h +@@ -419,6 +419,8 @@ struct phylink_pcs { + /** + * struct phylink_pcs_ops - MAC PCS operations structure. + * @pcs_validate: validate the link configuration. ++ * @pcs_enable: enable the PCS. ++ * @pcs_disable: disable the PCS. + * @pcs_get_state: read the current MAC PCS link state from the hardware. + * @pcs_config: configure the MAC PCS for the selected mode and state. + * @pcs_an_restart: restart 802.3z BaseX autonegotiation. +@@ -428,6 +430,8 @@ struct phylink_pcs { + struct phylink_pcs_ops { + int (*pcs_validate)(struct phylink_pcs *pcs, unsigned long *supported, + const struct phylink_link_state *state); ++ int (*pcs_enable)(struct phylink_pcs *pcs); ++ void (*pcs_disable)(struct phylink_pcs *pcs); + void (*pcs_get_state)(struct phylink_pcs *pcs, + struct phylink_link_state *state); + int (*pcs_config)(struct phylink_pcs *pcs, unsigned int mode, +@@ -458,6 +462,18 @@ int pcs_validate(struct phylink_pcs *pcs + const struct phylink_link_state *state); + + /** ++ * pcs_enable() - enable the PCS. ++ * @pcs: a pointer to a &struct phylink_pcs. ++ */ ++int pcs_enable(struct phylink_pcs *pcs); ++ ++/** ++ * pcs_disable() - disable the PCS. ++ * @pcs: a pointer to a &struct phylink_pcs. ++ */ ++void pcs_disable(struct phylink_pcs *pcs); ++ ++/** + * pcs_get_state() - Read the current inband link state from the hardware + * @pcs: a pointer to a &struct phylink_pcs. + * @state: a pointer to a &struct phylink_link_state. diff --git a/target/linux/generic/backport-5.15/793-v6.6-net-pcs-lynxi-implement-pcs_disable-op.patch b/target/linux/generic/backport-5.15/793-v6.6-net-pcs-lynxi-implement-pcs_disable-op.patch new file mode 100644 index 00000000000..eb9b4b7c09e --- /dev/null +++ b/target/linux/generic/backport-5.15/793-v6.6-net-pcs-lynxi-implement-pcs_disable-op.patch @@ -0,0 +1,44 @@ +From e4ccdfb78a47132f2d215658aab8902fc457c4b4 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Fri, 18 Aug 2023 04:07:46 +0100 +Subject: [PATCH 082/125] net: pcs: lynxi: implement pcs_disable op + +When switching from 10GBase-R/5GBase-R/USXGMII to one of the interface +modes provided by mtk-pcs-lynxi we need to make sure to always perform +a full configuration of the PHYA. + +Implement pcs_disable op which resets the stored interface mode to +PHY_INTERFACE_MODE_NA to trigger a full reconfiguration once the LynxI +PCS driver had previously been deselected in favor of another PCS +driver such as the to-be-added driver for the USXGMII PCS found in +MT7988. + +Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/f23d1a60d2c9d2fb72e32dcb0eaa5f7e867a3d68.1692327891.git.daniel@makrotopia.org +Signed-off-by: Jakub Kicinski +--- + drivers/net/pcs/pcs-mtk-lynxi.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/drivers/net/pcs/pcs-mtk-lynxi.c ++++ b/drivers/net/pcs/pcs-mtk-lynxi.c +@@ -241,11 +241,19 @@ static void mtk_pcs_lynxi_link_up(struct + } + } + ++static void mtk_pcs_lynxi_disable(struct phylink_pcs *pcs) ++{ ++ struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs); ++ ++ mpcs->interface = PHY_INTERFACE_MODE_NA; ++} ++ + static const struct phylink_pcs_ops mtk_pcs_lynxi_ops = { + .pcs_get_state = mtk_pcs_lynxi_get_state, + .pcs_config = mtk_pcs_lynxi_config, + .pcs_an_restart = mtk_pcs_lynxi_restart_an, + .pcs_link_up = mtk_pcs_lynxi_link_up, ++ .pcs_disable = mtk_pcs_lynxi_disable, + }; + + struct phylink_pcs *mtk_pcs_lynxi_create(struct device *dev, diff --git a/target/linux/generic/backport-6.1/730-07-v6.3-net-ethernet-mtk_eth_soc-compile-out-netsys-v2-code-.patch b/target/linux/generic/backport-6.1/730-07-v6.3-net-ethernet-mtk_eth_soc-compile-out-netsys-v2-code-.patch deleted file mode 100644 index 31a8ca3ea86..00000000000 --- a/target/linux/generic/backport-6.1/730-07-v6.3-net-ethernet-mtk_eth_soc-compile-out-netsys-v2-code-.patch +++ /dev/null @@ -1,28 +0,0 @@ -From: Felix Fietkau -Date: Thu, 27 Oct 2022 23:39:52 +0200 -Subject: [PATCH] net: ethernet: mtk_eth_soc: compile out netsys v2 code - on mt7621 - -Avoid some branches in the hot path on low-end devices with limited CPU power, -and reduce code size - -Signed-off-by: Felix Fietkau ---- - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -921,7 +921,13 @@ enum mkt_eth_capabilities { - #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ - (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) - --#define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) -+#ifdef CONFIG_SOC_MT7621 -+#define MTK_CAP_MASK MTK_NETSYS_V2 -+#else -+#define MTK_CAP_MASK 0 -+#endif -+ -+#define MTK_HAS_CAPS(caps, _x) (((caps) & (_x) & ~(MTK_CAP_MASK)) == (_x)) - - #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ - MTK_GMAC2_RGMII | MTK_SHARED_INT | \ diff --git a/target/linux/generic/backport-6.1/730-09-v6.3-net-ethernet-mtk_eth_soc-fix-VLAN-rx-hardware-accele.patch b/target/linux/generic/backport-6.1/730-09-v6.3-net-ethernet-mtk_eth_soc-fix-VLAN-rx-hardware-accele.patch index 3a2780aff63..fda017f7fc1 100644 --- a/target/linux/generic/backport-6.1/730-09-v6.3-net-ethernet-mtk_eth_soc-fix-VLAN-rx-hardware-accele.patch +++ b/target/linux/generic/backport-6.1/730-09-v6.3-net-ethernet-mtk_eth_soc-fix-VLAN-rx-hardware-accele.patch @@ -181,7 +181,7 @@ Signed-off-by: Felix Fietkau /* CDMP Ingress Control Register */ #define MTK_CDMP_IG_CTRL 0x400 #define MTK_CDMP_STAG_EN BIT(0) -@@ -1170,6 +1176,8 @@ struct mtk_eth { +@@ -1164,6 +1170,8 @@ struct mtk_eth { int ip_align; diff --git a/target/linux/generic/backport-6.1/733-v6.2-12-net-mediatek-sgmii-ensure-the-SGMII-PHY-is-powered-d.patch b/target/linux/generic/backport-6.1/733-v6.2-12-net-mediatek-sgmii-ensure-the-SGMII-PHY-is-powered-d.patch index 7db59ad871b..a02c583deba 100644 --- a/target/linux/generic/backport-6.1/733-v6.2-12-net-mediatek-sgmii-ensure-the-SGMII-PHY-is-powered-d.patch +++ b/target/linux/generic/backport-6.1/733-v6.2-12-net-mediatek-sgmii-ensure-the-SGMII-PHY-is-powered-d.patch @@ -34,7 +34,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -1073,11 +1073,13 @@ struct mtk_soc_data { +@@ -1067,11 +1067,13 @@ struct mtk_soc_data { * @regmap: The register map pointing at the range used to setup * SGMII modes * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap diff --git a/target/linux/generic/backport-6.1/733-v6.3-18-net-ethernet-mtk_eth_soc-add-support-for-MT7981.patch b/target/linux/generic/backport-6.1/733-v6.3-18-net-ethernet-mtk_eth_soc-add-support-for-MT7981.patch index 8c0f320fa8f..4b53ef903a2 100644 --- a/target/linux/generic/backport-6.1/733-v6.3-18-net-ethernet-mtk_eth_soc-add-support-for-MT7981.patch +++ b/target/linux/generic/backport-6.1/733-v6.3-18-net-ethernet-mtk_eth_soc-add-support-for-MT7981.patch @@ -14,6 +14,12 @@ new device-tree attribute 'mediatek,pn_swap' to support them. Signed-off-by: Daniel Golle Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_path.c | 14 +++++++-- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 21 +++++++++++++ + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 31 ++++++++++++++++++++ + drivers/net/ethernet/mediatek/mtk_sgmii.c | 10 +++++++ + 4 files changed, 73 insertions(+), 3 deletions(-) --- a/drivers/net/ethernet/mediatek/mtk_eth_path.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c @@ -145,7 +151,7 @@ Signed-off-by: Jakub Kicinski #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) -@@ -966,6 +990,11 @@ enum mkt_eth_capabilities { +@@ -960,6 +984,11 @@ enum mkt_eth_capabilities { MTK_MUX_U3_GMAC2_TO_QPHY | \ MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) @@ -157,7 +163,7 @@ Signed-off-by: Jakub Kicinski #define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1) -@@ -1079,12 +1108,14 @@ struct mtk_soc_data { +@@ -1073,12 +1102,14 @@ struct mtk_soc_data { * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap * @interface: Currently configured interface mode * @pcs: Phylink PCS structure diff --git a/target/linux/generic/backport-6.1/733-v6.3-20-net-ethernet-mtk_eth_soc-switch-to-external-PCS-driv.patch b/target/linux/generic/backport-6.1/733-v6.3-20-net-ethernet-mtk_eth_soc-switch-to-external-PCS-driv.patch index 95647835fa8..e40d658ddcf 100644 --- a/target/linux/generic/backport-6.1/733-v6.3-20-net-ethernet-mtk_eth_soc-switch-to-external-PCS-driv.patch +++ b/target/linux/generic/backport-6.1/733-v6.3-20-net-ethernet-mtk_eth_soc-switch-to-external-PCS-driv.patch @@ -228,7 +228,7 @@ Signed-off-by: Jakub Kicinski /* Infrasys subsystem config registers */ #define INFRA_MISC2 0x70c #define CO_QPHY_SEL BIT(0) -@@ -1108,31 +1049,6 @@ struct mtk_soc_data { +@@ -1102,31 +1043,6 @@ struct mtk_soc_data { /* currently no SoC has more than 2 macs */ #define MTK_MAX_DEVS 2 @@ -260,7 +260,7 @@ Signed-off-by: Jakub Kicinski /* struct mtk_eth - This is the main datasructure for holding the state * of the driver * @dev: The device pointer -@@ -1152,6 +1068,7 @@ struct mtk_sgmii { +@@ -1146,6 +1062,7 @@ struct mtk_sgmii { * MII modes * @infra: The register map pointing at the range used to setup * SGMII and GePHY path @@ -268,7 +268,7 @@ Signed-off-by: Jakub Kicinski * @pctl: The register map pointing at the range used to setup * GMAC port drive/slew values * @dma_refcnt: track how many netdevs are using the DMA engine -@@ -1192,8 +1109,8 @@ struct mtk_eth { +@@ -1186,8 +1103,8 @@ struct mtk_eth { u32 msg_enable; unsigned long sysclk; struct regmap *ethsys; @@ -279,7 +279,7 @@ Signed-off-by: Jakub Kicinski struct regmap *pctl; bool hwlro; refcount_t dma_refcnt; -@@ -1355,10 +1272,6 @@ void mtk_stats_update_mac(struct mtk_mac +@@ -1349,10 +1266,6 @@ void mtk_stats_update_mac(struct mtk_mac void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); u32 mtk_r32(struct mtk_eth *eth, unsigned reg); diff --git a/target/linux/generic/pending-5.15/731-net-ethernet-mediatek-ppe-add-support-for-flow-accou.patch b/target/linux/generic/backport-6.1/733-v6.4-23-net-ethernet-mtk_eth_soc-ppe-add-support-for-flow-ac.patch similarity index 79% rename from target/linux/generic/pending-5.15/731-net-ethernet-mediatek-ppe-add-support-for-flow-accou.patch rename to target/linux/generic/backport-6.1/733-v6.4-23-net-ethernet-mtk_eth_soc-ppe-add-support-for-flow-ac.patch index 91ffd65c6cb..3384086bdc6 100644 --- a/target/linux/generic/pending-5.15/731-net-ethernet-mediatek-ppe-add-support-for-flow-accou.patch +++ b/target/linux/generic/backport-6.1/733-v6.4-23-net-ethernet-mtk_eth_soc-ppe-add-support-for-flow-ac.patch @@ -1,59 +1,33 @@ -From patchwork Wed Nov 2 00:58:01 2022 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Daniel Golle -X-Patchwork-Id: 13027653 -X-Patchwork-Delegate: kuba@kernel.org -Return-Path: -Date: Wed, 2 Nov 2022 00:58:01 +0000 +From f601293f37c4be618c5efaef85d2ee21f97e82e0 Mon Sep 17 00:00:00 2001 From: Daniel Golle -To: Felix Fietkau , John Crispin , - Sean Wang , - Mark Lee , - "David S. Miller" , - Eric Dumazet , - Jakub Kicinski , - Paolo Abeni , - Matthias Brugger , - netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, - linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org -Subject: [PATCH v4] net: ethernet: mediatek: ppe: add support for flow +Date: Sun, 19 Mar 2023 12:57:35 +0000 +Subject: [PATCH 092/250] net: ethernet: mtk_eth_soc: ppe: add support for flow accounting -Message-ID: MIME-Version: 1.0 -Content-Disposition: inline -Precedence: bulk -List-ID: -X-Mailing-List: netdev@vger.kernel.org -X-Patchwork-Delegate: kuba@kernel.org +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit The PPE units found in MT7622 and newer support packet and byte -accounting of hw-offloaded flows. Add support for reading those -counters as found in MediaTek's SDK[1]. +accounting of hw-offloaded flows. Add support for reading those counters +as found in MediaTek's SDK[1]. [1]: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/bc6a6a375c800dc2b80e1a325a2c732d1737df92 +Tested-by: Bjørn Mork Signed-off-by: Daniel Golle +Signed-off-by: Jakub Kicinski --- -v4: declare function mtk_mib_entry_read as static -v3: don't bother to set 'false' values in any zero-initialized struct - use mtk_foe_entry_ib2 - both changes were requested by Felix Fietkau - -v2: fix wrong variable name in return value check spotted by Denis Kirjanov - - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 7 +- - drivers/net/ethernet/mediatek/mtk_eth_soc.h | 1 + - drivers/net/ethernet/mediatek/mtk_ppe.c | 110 +++++++++++++++++- - drivers/net/ethernet/mediatek/mtk_ppe.h | 23 +++- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 8 +- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 3 + + drivers/net/ethernet/mediatek/mtk_ppe.c | 114 +++++++++++++++++- + drivers/net/ethernet/mediatek/mtk_ppe.h | 25 +++- .../net/ethernet/mediatek/mtk_ppe_debugfs.c | 9 +- - .../net/ethernet/mediatek/mtk_ppe_offload.c | 7 ++ + .../net/ethernet/mediatek/mtk_ppe_offload.c | 8 ++ drivers/net/ethernet/mediatek/mtk_ppe_regs.h | 14 +++ - 7 files changed, 166 insertions(+), 5 deletions(-) + 7 files changed, 172 insertions(+), 9 deletions(-) --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -4635,8 +4635,8 @@ static int mtk_probe(struct platform_dev +@@ -4689,8 +4689,8 @@ static int mtk_probe(struct platform_dev for (i = 0; i < num_ppe; i++) { u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400; @@ -63,8 +37,8 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov + if (!eth->ppe[i]) { err = -ENOMEM; - goto err_free_dev; -@@ -4763,6 +4763,7 @@ static const struct mtk_soc_data mt7622_ + goto err_deinit_ppe; +@@ -4814,6 +4814,7 @@ static const struct mtk_soc_data mt7622_ .required_pctl = false, .offload_version = 2, .hash_offset = 2, @@ -72,7 +46,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, .txrx = { .txd_size = sizeof(struct mtk_tx_dma), -@@ -4800,6 +4801,7 @@ static const struct mtk_soc_data mt7629_ +@@ -4851,6 +4852,7 @@ static const struct mtk_soc_data mt7629_ .hw_features = MTK_HW_FEATURES, .required_clks = MT7629_CLKS_BITMAP, .required_pctl = false, @@ -80,7 +54,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov .txrx = { .txd_size = sizeof(struct mtk_tx_dma), .rxd_size = sizeof(struct mtk_rx_dma), -@@ -4820,6 +4822,7 @@ static const struct mtk_soc_data mt7981_ +@@ -4871,6 +4873,7 @@ static const struct mtk_soc_data mt7981_ .offload_version = 2, .hash_offset = 4, .foe_entry_size = sizeof(struct mtk_foe_entry), @@ -88,7 +62,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov .txrx = { .txd_size = sizeof(struct mtk_tx_dma_v2), .rxd_size = sizeof(struct mtk_rx_dma_v2), -@@ -4840,6 +4843,7 @@ static const struct mtk_soc_data mt7986_ +@@ -4891,6 +4894,7 @@ static const struct mtk_soc_data mt7986_ .offload_version = 2, .hash_offset = 4, .foe_entry_size = sizeof(struct mtk_foe_entry), @@ -98,7 +72,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov .rxd_size = sizeof(struct mtk_rx_dma_v2), --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -1014,6 +1014,8 @@ struct mtk_reg_map { +@@ -1011,6 +1011,8 @@ struct mtk_reg_map { * the extra setup for those pins used by GMAC. * @hash_offset Flow table hash offset. * @foe_entry_size Foe table entry size. @@ -107,7 +81,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov * @txd_size Tx DMA descriptor size. * @rxd_size Rx DMA descriptor size. * @rx_irq_done_mask Rx irq done register mask. -@@ -1031,6 +1033,7 @@ struct mtk_soc_data { +@@ -1028,6 +1030,7 @@ struct mtk_soc_data { u8 hash_offset; u16 foe_entry_size; netdev_features_t hw_features; @@ -166,10 +140,10 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov static void mtk_ppe_cache_clear(struct mtk_ppe *ppe) { ppe_set(ppe, MTK_PPE_CACHE_CTL, MTK_PPE_CACHE_CTL_CLEAR); -@@ -464,6 +506,13 @@ __mtk_foe_entry_clear(struct mtk_ppe *pp - hwe->ib1 &= ~MTK_FOE_IB1_STATE; +@@ -459,6 +501,13 @@ __mtk_foe_entry_clear(struct mtk_ppe *pp hwe->ib1 |= FIELD_PREP(MTK_FOE_IB1_STATE, MTK_FOE_STATE_INVALID); dma_wmb(); + mtk_ppe_cache_clear(ppe); + if (ppe->accounting) { + struct mtk_foe_accounting *acct; + @@ -180,7 +154,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov } entry->hash = 0xffff; -@@ -571,6 +620,9 @@ __mtk_foe_entry_commit(struct mtk_ppe *p +@@ -566,6 +615,9 @@ __mtk_foe_entry_commit(struct mtk_ppe *p wmb(); hwe->ib1 = entry->ib1; @@ -190,7 +164,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov dma_wmb(); mtk_ppe_cache_clear(ppe); -@@ -762,11 +814,39 @@ int mtk_ppe_prepare_reset(struct mtk_ppe +@@ -757,11 +809,39 @@ int mtk_ppe_prepare_reset(struct mtk_ppe return mtk_ppe_wait_busy(ppe); } @@ -232,7 +206,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov struct mtk_ppe *ppe; u32 foe_flow_size; void *foe; -@@ -783,7 +863,8 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_ +@@ -778,7 +858,8 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_ ppe->base = base; ppe->eth = eth; ppe->dev = dev; @@ -242,9 +216,9 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov foe = dmam_alloc_coherent(ppe->dev, MTK_PPE_ENTRIES * soc->foe_entry_size, -@@ -799,6 +880,23 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_ +@@ -794,6 +875,23 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_ if (!ppe->foe_flow) - return NULL; + goto err_free_l2_flows; + if (accounting) { + mib = dmam_alloc_coherent(ppe->dev, MTK_PPE_ENTRIES * sizeof(*mib), @@ -266,7 +240,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov mtk_ppe_debugfs_init(ppe, index); return ppe; -@@ -913,6 +1011,16 @@ void mtk_ppe_start(struct mtk_ppe *ppe) +@@ -923,6 +1021,16 @@ void mtk_ppe_start(struct mtk_ppe *ppe) ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT1, 0xcb777); ppe_w32(ppe, MTK_PPE_SBW_CTRL, 0x7f); } @@ -328,17 +302,18 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov u16 foe_check_time[MTK_PPE_ENTRIES]; struct hlist_head *foe_flow; -@@ -303,8 +322,7 @@ struct mtk_ppe { +@@ -303,8 +322,8 @@ struct mtk_ppe { void *acct_table; }; -struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base, - int version, int index); +struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base, int index); ++ + void mtk_ppe_deinit(struct mtk_eth *eth); void mtk_ppe_start(struct mtk_ppe *ppe); int mtk_ppe_stop(struct mtk_ppe *ppe); - int mtk_ppe_prepare_reset(struct mtk_ppe *ppe); -@@ -358,5 +376,7 @@ int mtk_foe_entry_commit(struct mtk_ppe +@@ -359,5 +378,7 @@ int mtk_foe_entry_commit(struct mtk_ppe void mtk_foe_entry_clear(struct mtk_ppe *ppe, struct mtk_flow_entry *entry); int mtk_foe_entry_idle_time(struct mtk_ppe *ppe, struct mtk_flow_entry *entry); int mtk_ppe_debugfs_init(struct mtk_ppe *ppe, int index); diff --git a/target/linux/generic/pending-6.1/736-06-net-ethernet-mediatek-fix-ppe-flow-accounting-for-v1.patch b/target/linux/generic/backport-6.1/733-v6.4-24-net-ethernet-mediatek-fix-ppe-flow-accounting-for-v1.patch similarity index 63% rename from target/linux/generic/pending-6.1/736-06-net-ethernet-mediatek-fix-ppe-flow-accounting-for-v1.patch rename to target/linux/generic/backport-6.1/733-v6.4-24-net-ethernet-mediatek-fix-ppe-flow-accounting-for-v1.patch index 33c98383272..64352426ae5 100644 --- a/target/linux/generic/pending-6.1/736-06-net-ethernet-mediatek-fix-ppe-flow-accounting-for-v1.patch +++ b/target/linux/generic/backport-6.1/733-v6.4-24-net-ethernet-mediatek-fix-ppe-flow-accounting-for-v1.patch @@ -1,17 +1,24 @@ +From 88a0fd5927b7c2c7aecd6dc747d898eb38043d2b Mon Sep 17 00:00:00 2001 From: Felix Fietkau -Date: Thu, 23 Mar 2023 21:45:43 +0100 -Subject: [PATCH] net: ethernet: mediatek: fix ppe flow accounting for v1 - hardware +Date: Thu, 20 Apr 2023 22:06:42 +0100 +Subject: [PATCH 093/250] net: mtk_eth_soc: mediatek: fix ppe flow accounting + for v1 hardware Older chips (like MT7622) use a different bit in ib2 to enable hardware -counter support. +counter support. Add macros for both and select the appropriate bit. +Fixes: 3fbe4d8c0e53 ("net: ethernet: mtk_eth_soc: ppe: add support for flow accounting") Signed-off-by: Felix Fietkau +Signed-off-by: Daniel Golle +Signed-off-by: David S. Miller --- + drivers/net/ethernet/mediatek/mtk_ppe.c | 10 ++++++++-- + drivers/net/ethernet/mediatek/mtk_ppe.h | 3 ++- + 2 files changed, 10 insertions(+), 3 deletions(-) --- a/drivers/net/ethernet/mediatek/mtk_ppe.c +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c -@@ -640,6 +640,7 @@ __mtk_foe_entry_commit(struct mtk_ppe *p +@@ -599,6 +599,7 @@ __mtk_foe_entry_commit(struct mtk_ppe *p struct mtk_eth *eth = ppe->eth; u16 timestamp = mtk_eth_timestamp(eth); struct mtk_foe_entry *hwe; @@ -19,7 +26,7 @@ Signed-off-by: Felix Fietkau if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { entry->ib1 &= ~MTK_FOE_IB1_BIND_TIMESTAMP_V2; -@@ -656,8 +657,13 @@ __mtk_foe_entry_commit(struct mtk_ppe *p +@@ -615,8 +616,13 @@ __mtk_foe_entry_commit(struct mtk_ppe *p wmb(); hwe->ib1 = entry->ib1; diff --git a/target/linux/generic/pending-6.1/732-00-net-ethernet-mtk_eth_soc-drop-generic-vlan-rx-offloa.patch b/target/linux/generic/backport-6.1/733-v6.4-25-net-ethernet-mtk_eth_soc-drop-generic-vlan-rx-offloa.patch similarity index 100% rename from target/linux/generic/pending-6.1/732-00-net-ethernet-mtk_eth_soc-drop-generic-vlan-rx-offloa.patch rename to target/linux/generic/backport-6.1/733-v6.4-25-net-ethernet-mtk_eth_soc-drop-generic-vlan-rx-offloa.patch diff --git a/target/linux/generic/backport-6.1/733-v6.5-26-net-ethernet-mtk_eth_soc-always-mtk_get_ib1_pkt_type.patch b/target/linux/generic/backport-6.1/733-v6.5-26-net-ethernet-mtk_eth_soc-always-mtk_get_ib1_pkt_type.patch new file mode 100644 index 00000000000..2704faec12b --- /dev/null +++ b/target/linux/generic/backport-6.1/733-v6.5-26-net-ethernet-mtk_eth_soc-always-mtk_get_ib1_pkt_type.patch @@ -0,0 +1,31 @@ +From b804f765485109f9644cc05d1e8fc79ca6c6e4aa Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Wed, 19 Jul 2023 01:39:36 +0100 +Subject: [PATCH 094/250] net: ethernet: mtk_eth_soc: always + mtk_get_ib1_pkt_type + +entries and bind debugfs files would display wrong data on NETSYS_V2 and +later because instead of using mtk_get_ib1_pkt_type the driver would use +MTK_FOE_IB1_PACKET_TYPE which corresponds to NETSYS_V1(.x) SoCs. +Use mtk_get_ib1_pkt_type so entries and bind records display correctly. + +Fixes: 03a3180e5c09e ("net: ethernet: mtk_eth_soc: introduce flow offloading support for mt7986") +Signed-off-by: Daniel Golle +Acked-by: Lorenzo Bianconi +Link: https://lore.kernel.org/r/c0ae03d0182f4d27b874cbdf0059bc972c317f3c.1689727134.git.daniel@makrotopia.org +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_ppe_debugfs.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/ethernet/mediatek/mtk_ppe_debugfs.c ++++ b/drivers/net/ethernet/mediatek/mtk_ppe_debugfs.c +@@ -98,7 +98,7 @@ mtk_ppe_debugfs_foe_show(struct seq_file + + acct = mtk_foe_entry_get_mib(ppe, i, NULL); + +- type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1); ++ type = mtk_get_ib1_pkt_type(ppe->eth, entry->ib1); + seq_printf(m, "%05x %s %7s", i, + mtk_foe_entry_state_str(state), + mtk_foe_pkt_type_str(type)); diff --git a/target/linux/generic/backport-6.1/750-v6.5-01-net-ethernet-mtk_ppe-add-MTK_FOE_ENTRY_V-1-2-_SIZE-m.patch b/target/linux/generic/backport-6.1/750-v6.5-01-net-ethernet-mtk_ppe-add-MTK_FOE_ENTRY_V-1-2-_SIZE-m.patch new file mode 100644 index 00000000000..aceeaa9fe56 --- /dev/null +++ b/target/linux/generic/backport-6.1/750-v6.5-01-net-ethernet-mtk_ppe-add-MTK_FOE_ENTRY_V-1-2-_SIZE-m.patch @@ -0,0 +1,78 @@ +From 5ea0e1312bcfebc06b5f91d1bb82b823d6395125 Mon Sep 17 00:00:00 2001 +From: Lorenzo Bianconi +Date: Wed, 19 Jul 2023 12:29:49 +0200 +Subject: [PATCH 095/250] net: ethernet: mtk_ppe: add MTK_FOE_ENTRY_V{1,2}_SIZE + macros + +Introduce MTK_FOE_ENTRY_V{1,2}_SIZE macros in order to make more +explicit foe_entry size for different chipset revisions. + +Signed-off-by: Lorenzo Bianconi +Reviewed-by: Simon Horman +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 10 +++++----- + drivers/net/ethernet/mediatek/mtk_ppe.h | 3 +++ + 2 files changed, 8 insertions(+), 5 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -4763,7 +4763,7 @@ static const struct mtk_soc_data mt7621_ + .required_pctl = false, + .offload_version = 1, + .hash_offset = 2, +- .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, ++ .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma), + .rxd_size = sizeof(struct mtk_rx_dma), +@@ -4784,7 +4784,7 @@ static const struct mtk_soc_data mt7622_ + .offload_version = 2, + .hash_offset = 2, + .has_accounting = true, +- .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, ++ .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma), + .rxd_size = sizeof(struct mtk_rx_dma), +@@ -4803,7 +4803,7 @@ static const struct mtk_soc_data mt7623_ + .required_pctl = true, + .offload_version = 1, + .hash_offset = 2, +- .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, ++ .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma), + .rxd_size = sizeof(struct mtk_rx_dma), +@@ -4841,8 +4841,8 @@ static const struct mtk_soc_data mt7981_ + .required_pctl = false, + .offload_version = 2, + .hash_offset = 4, +- .foe_entry_size = sizeof(struct mtk_foe_entry), + .has_accounting = true, ++ .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma_v2), + .rxd_size = sizeof(struct mtk_rx_dma_v2), +@@ -4862,8 +4862,8 @@ static const struct mtk_soc_data mt7986_ + .required_pctl = false, + .offload_version = 2, + .hash_offset = 4, +- .foe_entry_size = sizeof(struct mtk_foe_entry), + .has_accounting = true, ++ .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma_v2), + .rxd_size = sizeof(struct mtk_rx_dma_v2), +--- a/drivers/net/ethernet/mediatek/mtk_ppe.h ++++ b/drivers/net/ethernet/mediatek/mtk_ppe.h +@@ -216,6 +216,9 @@ struct mtk_foe_ipv6_6rd { + struct mtk_foe_mac_info l2; + }; + ++#define MTK_FOE_ENTRY_V1_SIZE 80 ++#define MTK_FOE_ENTRY_V2_SIZE 96 ++ + struct mtk_foe_entry { + u32 ib1; + diff --git a/target/linux/generic/backport-6.1/750-v6.5-02-net-ethernet-mtk_eth_soc-remove-incorrect-PLL-config.patch b/target/linux/generic/backport-6.1/750-v6.5-02-net-ethernet-mtk_eth_soc-remove-incorrect-PLL-config.patch new file mode 100644 index 00000000000..ae56a99e838 --- /dev/null +++ b/target/linux/generic/backport-6.1/750-v6.5-02-net-ethernet-mtk_eth_soc-remove-incorrect-PLL-config.patch @@ -0,0 +1,141 @@ +From 8cfa2576d79f9379d167a8994f0fca935c07a8bc Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Sat, 22 Jul 2023 21:32:49 +0100 +Subject: [PATCH 096/250] net: ethernet: mtk_eth_soc: remove incorrect PLL + configuration + +MT7623 GMAC0 attempts to configure the system clocking according to the +required speed in the .mac_config callback for non-SGMII, non-baseX and +non-TRGMII modes. + +state->speed setting has never been reliable in the .mac_config +callback - there are cases where this is not the link speed, +particularly via ethtool paths, so this has always been unreliable (as +detailed in phylink's documentation.) + +There is the additional issue that mtk_gmac0_rgmii_adjust() will only +be called if state->interface changes, which means it only configures +the system clocking on the very first .mac_config call, which will be +made when the network device is first brought up before any link is +established. + +Essentially, this code is incredibly buggy, and probably never worked. + +Moreover, checking the in-kernel DT files, it seems no platform makes +use of this code path. + +Therefore, let's remove it, and disable interface modes for port 0 that +are not SGMII, 1000base-X, 2500base-X or TRGMII on the MT7623. + +Reviewed-by: Daniel Golle +Tested-by: Daniel Golle +Tested-by: Frank Wunderlich +Signed-off-by: Russell King (Oracle) +Signed-off-by: Paolo Abeni +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 54 ++++++--------------- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 1 + + 2 files changed, 17 insertions(+), 38 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -352,7 +352,7 @@ static int mt7621_gmac0_rgmii_adjust(str + } + + static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, +- phy_interface_t interface, int speed) ++ phy_interface_t interface) + { + u32 val; + int ret; +@@ -366,26 +366,7 @@ static void mtk_gmac0_rgmii_adjust(struc + return; + } + +- val = (speed == SPEED_1000) ? +- INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100; +- mtk_w32(eth, val, INTF_MODE); +- +- regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, +- ETHSYS_TRGMII_CLK_SEL362_5, +- ETHSYS_TRGMII_CLK_SEL362_5); +- +- val = (speed == SPEED_1000) ? 250000000 : 500000000; +- ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); +- if (ret) +- dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); +- +- val = (speed == SPEED_1000) ? +- RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100; +- mtk_w32(eth, val, TRGMII_RCK_CTRL); +- +- val = (speed == SPEED_1000) ? +- TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100; +- mtk_w32(eth, val, TRGMII_TCK_CTRL); ++ dev_err(eth->dev, "Missing PLL configuration, ethernet may not work\n"); + } + + static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config, +@@ -471,17 +452,8 @@ static void mtk_mac_config(struct phylin + state->interface)) + goto err_phy; + } else { +- /* FIXME: this is incorrect. Not only does it +- * use state->speed (which is not guaranteed +- * to be correct) but it also makes use of it +- * in a code path that will only be reachable +- * when the PHY interface mode changes, not +- * when the speed changes. Consequently, RGMII +- * is probably broken. +- */ + mtk_gmac0_rgmii_adjust(mac->hw, +- state->interface, +- state->speed); ++ state->interface); + + /* mt7623_pad_clk_setup */ + for (i = 0 ; i < NUM_TRGMII_CTRL; i++) +@@ -4340,13 +4312,19 @@ static int mtk_add_mac(struct mtk_eth *e + mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | + MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD; + +- __set_bit(PHY_INTERFACE_MODE_MII, +- mac->phylink_config.supported_interfaces); +- __set_bit(PHY_INTERFACE_MODE_GMII, +- mac->phylink_config.supported_interfaces); ++ /* MT7623 gmac0 is now missing its speed-specific PLL configuration ++ * in its .mac_config method (since state->speed is not valid there. ++ * Disable support for MII, GMII and RGMII. ++ */ ++ if (!mac->hw->soc->disable_pll_modes || mac->id != 0) { ++ __set_bit(PHY_INTERFACE_MODE_MII, ++ mac->phylink_config.supported_interfaces); ++ __set_bit(PHY_INTERFACE_MODE_GMII, ++ mac->phylink_config.supported_interfaces); + +- if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) +- phy_interface_set_rgmii(mac->phylink_config.supported_interfaces); ++ if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) ++ phy_interface_set_rgmii(mac->phylink_config.supported_interfaces); ++ } + + if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id) + __set_bit(PHY_INTERFACE_MODE_TRGMII, +@@ -4804,6 +4782,7 @@ static const struct mtk_soc_data mt7623_ + .offload_version = 1, + .hash_offset = 2, + .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, ++ .disable_pll_modes = true, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma), + .rxd_size = sizeof(struct mtk_rx_dma), +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -1030,6 +1030,7 @@ struct mtk_soc_data { + u16 foe_entry_size; + netdev_features_t hw_features; + bool has_accounting; ++ bool disable_pll_modes; + struct { + u32 txd_size; + u32 rxd_size; diff --git a/target/linux/generic/backport-6.1/750-v6.5-03-net-ethernet-mtk_eth_soc-remove-mac_pcs_get_state-an.patch b/target/linux/generic/backport-6.1/750-v6.5-03-net-ethernet-mtk_eth_soc-remove-mac_pcs_get_state-an.patch new file mode 100644 index 00000000000..2893a073fde --- /dev/null +++ b/target/linux/generic/backport-6.1/750-v6.5-03-net-ethernet-mtk_eth_soc-remove-mac_pcs_get_state-an.patch @@ -0,0 +1,81 @@ +From a4c2233b1e4359b6c64b6f9ba98c8718a11fffee Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Sat, 22 Jul 2023 21:32:54 +0100 +Subject: [PATCH 097/250] net: ethernet: mtk_eth_soc: remove mac_pcs_get_state + and modernise + +Remove the .mac_pcs_get_state function, since as far as I can tell is +never called - no DT appears to specify an in-band-status management +nor SFP support for this driver. + +Removal of this, along with the previous patch to remove the incorrect +clocking configuration, means that the driver becomes non-legacy, so +we can remove the "legacy_pre_march2020" status from this driver. + +Reviewed-by: Daniel Golle +Tested-by: Daniel Golle +Tested-by: Frank Wunderlich +Signed-off-by: Russell King (Oracle) +Signed-off-by: Paolo Abeni +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 35 --------------------- + 1 file changed, 35 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -555,38 +555,6 @@ static int mtk_mac_finish(struct phylink + return 0; + } + +-static void mtk_mac_pcs_get_state(struct phylink_config *config, +- struct phylink_link_state *state) +-{ +- struct mtk_mac *mac = container_of(config, struct mtk_mac, +- phylink_config); +- u32 pmsr = mtk_r32(mac->hw, MTK_MAC_MSR(mac->id)); +- +- state->link = (pmsr & MAC_MSR_LINK); +- state->duplex = (pmsr & MAC_MSR_DPX) >> 1; +- +- switch (pmsr & (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)) { +- case 0: +- state->speed = SPEED_10; +- break; +- case MAC_MSR_SPEED_100: +- state->speed = SPEED_100; +- break; +- case MAC_MSR_SPEED_1000: +- state->speed = SPEED_1000; +- break; +- default: +- state->speed = SPEED_UNKNOWN; +- break; +- } +- +- state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX); +- if (pmsr & MAC_MSR_RX_FC) +- state->pause |= MLO_PAUSE_RX; +- if (pmsr & MAC_MSR_TX_FC) +- state->pause |= MLO_PAUSE_TX; +-} +- + static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode, + phy_interface_t interface) + { +@@ -709,7 +677,6 @@ static void mtk_mac_link_up(struct phyli + static const struct phylink_mac_ops mtk_phylink_ops = { + .validate = phylink_generic_validate, + .mac_select_pcs = mtk_mac_select_pcs, +- .mac_pcs_get_state = mtk_mac_pcs_get_state, + .mac_config = mtk_mac_config, + .mac_finish = mtk_mac_finish, + .mac_link_down = mtk_mac_link_down, +@@ -4307,8 +4274,6 @@ static int mtk_add_mac(struct mtk_eth *e + + mac->phylink_config.dev = ð->netdev[id]->dev; + mac->phylink_config.type = PHYLINK_NETDEV; +- /* This driver makes use of state->speed in mac_config */ +- mac->phylink_config.legacy_pre_march2020 = true; + mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | + MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD; + diff --git a/target/linux/generic/backport-6.1/750-v6.5-05-net-ethernet-mtk_eth_soc-add-version-in-mtk_soc_data.patch b/target/linux/generic/backport-6.1/750-v6.5-05-net-ethernet-mtk_eth_soc-add-version-in-mtk_soc_data.patch new file mode 100644 index 00000000000..9151702d01b --- /dev/null +++ b/target/linux/generic/backport-6.1/750-v6.5-05-net-ethernet-mtk_eth_soc-add-version-in-mtk_soc_data.patch @@ -0,0 +1,550 @@ +From 5d8d05fbf804b4485646d39551ac27452e45afd3 Mon Sep 17 00:00:00 2001 +From: Lorenzo Bianconi +Date: Tue, 25 Jul 2023 01:52:02 +0100 +Subject: [PATCH 099/250] net: ethernet: mtk_eth_soc: add version in + mtk_soc_data + +Introduce version field in mtk_soc_data data structure in order to +make mtk_eth driver easier to maintain for chipset configuration +codebase. Get rid of MTK_NETSYS_V2 bit in chip capabilities. +This is a preliminary patch to introduce support for MT7988 SoC. + +Signed-off-by: Lorenzo Bianconi +Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/e52fae302ca135436e5cdd26d38d87be2da63055.1690246066.git.daniel@makrotopia.org +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 55 +++++++++++-------- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 36 +++++++----- + drivers/net/ethernet/mediatek/mtk_ppe.c | 18 +++--- + .../net/ethernet/mediatek/mtk_ppe_offload.c | 2 +- + drivers/net/ethernet/mediatek/mtk_wed.c | 4 +- + 5 files changed, 66 insertions(+), 49 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -580,7 +580,7 @@ static void mtk_set_queue_speed(struct m + FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | + FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | + MTK_QTX_SCH_LEAKY_BUCKET_SIZE; +- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v1(eth)) + val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; + + if (IS_ENABLED(CONFIG_SOC_MT7621)) { +@@ -956,7 +956,7 @@ static bool mtk_rx_get_desc(struct mtk_e + rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); + rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); + rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ if (mtk_is_netsys_v2_or_greater(eth)) { + rxd->rxd5 = READ_ONCE(dma_rxd->rxd5); + rxd->rxd6 = READ_ONCE(dma_rxd->rxd6); + } +@@ -1014,7 +1014,7 @@ static int mtk_init_fq_dma(struct mtk_et + + txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE); + txd->txd4 = 0; +- if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) { ++ if (mtk_is_netsys_v2_or_greater(eth)) { + txd->txd5 = 0; + txd->txd6 = 0; + txd->txd7 = 0; +@@ -1205,7 +1205,7 @@ static void mtk_tx_set_dma_desc(struct n + struct mtk_mac *mac = netdev_priv(dev); + struct mtk_eth *eth = mac->hw; + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + mtk_tx_set_dma_desc_v2(dev, txd, info); + else + mtk_tx_set_dma_desc_v1(dev, txd, info); +@@ -1512,7 +1512,7 @@ static void mtk_update_rx_cpu_idx(struct + + static bool mtk_page_pool_enabled(struct mtk_eth *eth) + { +- return MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2); ++ return eth->soc->version == 2; + } + + static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth, +@@ -1854,7 +1854,7 @@ static int mtk_poll_rx(struct napi_struc + break; + + /* find out which mac the packet come from. values start at 1 */ +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1; + else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && + !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) +@@ -1950,7 +1950,7 @@ static int mtk_poll_rx(struct napi_struc + skb->dev = netdev; + bytes += skb->len; + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ if (mtk_is_netsys_v2_or_greater(eth)) { + reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5); + hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY; + if (hash != MTK_RXD5_FOE_ENTRY) +@@ -1975,8 +1975,8 @@ static int mtk_poll_rx(struct napi_struc + /* When using VLAN untagging in combination with DSA, the + * hardware treats the MTK special tag as a VLAN and untags it. + */ +- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) && +- (trxd.rxd2 & RX_DMA_VTAG) && netdev_uses_dsa(netdev)) { ++ if (mtk_is_netsys_v1(eth) && (trxd.rxd2 & RX_DMA_VTAG) && ++ netdev_uses_dsa(netdev)) { + unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0); + + if (port < ARRAY_SIZE(eth->dsa_meta) && +@@ -2286,7 +2286,7 @@ static int mtk_tx_alloc(struct mtk_eth * + txd->txd2 = next_ptr; + txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; + txd->txd4 = 0; +- if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) { ++ if (mtk_is_netsys_v2_or_greater(eth)) { + txd->txd5 = 0; + txd->txd6 = 0; + txd->txd7 = 0; +@@ -2339,14 +2339,14 @@ static int mtk_tx_alloc(struct mtk_eth * + FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | + FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | + MTK_QTX_SCH_LEAKY_BUCKET_SIZE; +- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v1(eth)) + val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; + mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); + ofs += MTK_QTX_OFFSET; + } + val = MTK_QDMA_TX_SCH_MAX_WFQ | (MTK_QDMA_TX_SCH_MAX_WFQ << 16); + mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate); +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate + 4); + } else { + mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0); +@@ -2475,7 +2475,7 @@ static int mtk_rx_alloc(struct mtk_eth * + + rxd->rxd3 = 0; + rxd->rxd4 = 0; +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ if (mtk_is_netsys_v2_or_greater(eth)) { + rxd->rxd5 = 0; + rxd->rxd6 = 0; + rxd->rxd7 = 0; +@@ -3023,7 +3023,7 @@ static int mtk_start_dma(struct mtk_eth + MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO | + MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE; + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + val |= MTK_MUTLI_CNT | MTK_RESV_BUF | + MTK_WCOMP_EN | MTK_DMAD_WR_WDONE | + MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN; +@@ -3165,7 +3165,7 @@ static int mtk_open(struct net_device *d + phylink_start(mac->phylink); + netif_tx_start_all_queues(dev); + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + return 0; + + if (mtk_uses_dsa(dev) && !eth->prog) { +@@ -3430,7 +3430,7 @@ static void mtk_hw_reset(struct mtk_eth + { + u32 val; + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ if (mtk_is_netsys_v2_or_greater(eth)) { + regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); + val = RSTCTRL_PPE0_V2; + } else { +@@ -3442,7 +3442,7 @@ static void mtk_hw_reset(struct mtk_eth + + ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val); + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, + 0x3ffffff); + } +@@ -3468,7 +3468,7 @@ static void mtk_hw_warm_reset(struct mtk + return; + } + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2; + else + rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0; +@@ -3638,7 +3638,7 @@ static int mtk_hw_init(struct mtk_eth *e + else + mtk_hw_reset(eth); + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ if (mtk_is_netsys_v2_or_greater(eth)) { + /* Set FE to PDMAv2 if necessary */ + val = mtk_r32(eth, MTK_FE_GLO_MISC); + mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC); +@@ -3675,7 +3675,7 @@ static int mtk_hw_init(struct mtk_eth *e + */ + val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); + mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); +- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ if (mtk_is_netsys_v1(eth)) { + val = mtk_r32(eth, MTK_CDMP_IG_CTRL); + mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL); + +@@ -3697,7 +3697,7 @@ static int mtk_hw_init(struct mtk_eth *e + mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4); + mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ if (mtk_is_netsys_v2_or_greater(eth)) { + /* PSE should not drop port8 and port9 packets from WDMA Tx */ + mtk_w32(eth, 0x00000300, PSE_DROP_CFG); + +@@ -4486,7 +4486,7 @@ static int mtk_probe(struct platform_dev + } + } + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ if (mtk_is_netsys_v2_or_greater(eth)) { + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + err = -EINVAL; +@@ -4594,9 +4594,8 @@ static int mtk_probe(struct platform_dev + } + + if (eth->soc->offload_version) { +- u32 num_ppe; ++ u32 num_ppe = mtk_is_netsys_v2_or_greater(eth) ? 2 : 1; + +- num_ppe = MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ? 2 : 1; + num_ppe = min_t(u32, ARRAY_SIZE(eth->ppe), num_ppe); + for (i = 0; i < num_ppe; i++) { + u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400; +@@ -4688,6 +4687,7 @@ static const struct mtk_soc_data mt2701_ + .hw_features = MTK_HW_FEATURES, + .required_clks = MT7623_CLKS_BITMAP, + .required_pctl = true, ++ .version = 1, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma), + .rxd_size = sizeof(struct mtk_rx_dma), +@@ -4704,6 +4704,7 @@ static const struct mtk_soc_data mt7621_ + .hw_features = MTK_HW_FEATURES, + .required_clks = MT7621_CLKS_BITMAP, + .required_pctl = false, ++ .version = 1, + .offload_version = 1, + .hash_offset = 2, + .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, +@@ -4724,6 +4725,7 @@ static const struct mtk_soc_data mt7622_ + .hw_features = MTK_HW_FEATURES, + .required_clks = MT7622_CLKS_BITMAP, + .required_pctl = false, ++ .version = 1, + .offload_version = 2, + .hash_offset = 2, + .has_accounting = true, +@@ -4744,6 +4746,7 @@ static const struct mtk_soc_data mt7623_ + .hw_features = MTK_HW_FEATURES, + .required_clks = MT7623_CLKS_BITMAP, + .required_pctl = true, ++ .version = 1, + .offload_version = 1, + .hash_offset = 2, + .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, +@@ -4766,6 +4769,7 @@ static const struct mtk_soc_data mt7629_ + .required_clks = MT7629_CLKS_BITMAP, + .required_pctl = false, + .has_accounting = true, ++ .version = 1, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma), + .rxd_size = sizeof(struct mtk_rx_dma), +@@ -4783,6 +4787,7 @@ static const struct mtk_soc_data mt7981_ + .hw_features = MTK_HW_FEATURES, + .required_clks = MT7981_CLKS_BITMAP, + .required_pctl = false, ++ .version = 2, + .offload_version = 2, + .hash_offset = 4, + .has_accounting = true, +@@ -4804,6 +4809,7 @@ static const struct mtk_soc_data mt7986_ + .hw_features = MTK_HW_FEATURES, + .required_clks = MT7986_CLKS_BITMAP, + .required_pctl = false, ++ .version = 2, + .offload_version = 2, + .hash_offset = 4, + .has_accounting = true, +@@ -4824,6 +4830,7 @@ static const struct mtk_soc_data rt5350_ + .hw_features = MTK_HW_FEATURES_MT7628, + .required_clks = MT7628_CLKS_BITMAP, + .required_pctl = false, ++ .version = 1, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma), + .rxd_size = sizeof(struct mtk_rx_dma), +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -820,7 +820,6 @@ enum mkt_eth_capabilities { + MTK_SHARED_INT_BIT, + MTK_TRGMII_MT7621_CLK_BIT, + MTK_QDMA_BIT, +- MTK_NETSYS_V2_BIT, + MTK_SOC_MT7628_BIT, + MTK_RSTCTRL_PPE1_BIT, + MTK_U3_COPHY_V2_BIT, +@@ -855,7 +854,6 @@ enum mkt_eth_capabilities { + #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT) + #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) + #define MTK_QDMA BIT(MTK_QDMA_BIT) +-#define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) + #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) + #define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT) + #define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT) +@@ -934,11 +932,11 @@ enum mkt_eth_capabilities { + #define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ + MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ + MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \ +- MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1) ++ MTK_RSTCTRL_PPE1) + + #define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ + MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ +- MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1) ++ MTK_RSTCTRL_PPE1) + + struct mtk_tx_dma_desc_info { + dma_addr_t addr; +@@ -1009,6 +1007,7 @@ struct mtk_reg_map { + * @required_pctl A bool value to show whether the SoC requires + * the extra setup for those pins used by GMAC. + * @hash_offset Flow table hash offset. ++ * @version SoC version. + * @foe_entry_size Foe table entry size. + * @has_accounting Bool indicating support for accounting of + * offloaded flows. +@@ -1027,6 +1026,7 @@ struct mtk_soc_data { + bool required_pctl; + u8 offload_version; + u8 hash_offset; ++ u8 version; + u16 foe_entry_size; + netdev_features_t hw_features; + bool has_accounting; +@@ -1183,6 +1183,16 @@ struct mtk_mac { + /* the struct describing the SoC. these are declared in the soc_xyz.c files */ + extern const struct of_device_id of_mtk_match[]; + ++static inline bool mtk_is_netsys_v1(struct mtk_eth *eth) ++{ ++ return eth->soc->version == 1; ++} ++ ++static inline bool mtk_is_netsys_v2_or_greater(struct mtk_eth *eth) ++{ ++ return eth->soc->version > 1; ++} ++ + static inline struct mtk_foe_entry * + mtk_foe_get_entry(struct mtk_ppe *ppe, u16 hash) + { +@@ -1193,7 +1203,7 @@ mtk_foe_get_entry(struct mtk_ppe *ppe, u + + static inline u32 mtk_get_ib1_ts_mask(struct mtk_eth *eth) + { +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + return MTK_FOE_IB1_BIND_TIMESTAMP_V2; + + return MTK_FOE_IB1_BIND_TIMESTAMP; +@@ -1201,7 +1211,7 @@ static inline u32 mtk_get_ib1_ts_mask(st + + static inline u32 mtk_get_ib1_ppoe_mask(struct mtk_eth *eth) + { +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + return MTK_FOE_IB1_BIND_PPPOE_V2; + + return MTK_FOE_IB1_BIND_PPPOE; +@@ -1209,7 +1219,7 @@ static inline u32 mtk_get_ib1_ppoe_mask( + + static inline u32 mtk_get_ib1_vlan_tag_mask(struct mtk_eth *eth) + { +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + return MTK_FOE_IB1_BIND_VLAN_TAG_V2; + + return MTK_FOE_IB1_BIND_VLAN_TAG; +@@ -1217,7 +1227,7 @@ static inline u32 mtk_get_ib1_vlan_tag_m + + static inline u32 mtk_get_ib1_vlan_layer_mask(struct mtk_eth *eth) + { +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + return MTK_FOE_IB1_BIND_VLAN_LAYER_V2; + + return MTK_FOE_IB1_BIND_VLAN_LAYER; +@@ -1225,7 +1235,7 @@ static inline u32 mtk_get_ib1_vlan_layer + + static inline u32 mtk_prep_ib1_vlan_layer(struct mtk_eth *eth, u32 val) + { +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val); + + return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, val); +@@ -1233,7 +1243,7 @@ static inline u32 mtk_prep_ib1_vlan_laye + + static inline u32 mtk_get_ib1_vlan_layer(struct mtk_eth *eth, u32 val) + { +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val); + + return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER, val); +@@ -1241,7 +1251,7 @@ static inline u32 mtk_get_ib1_vlan_layer + + static inline u32 mtk_get_ib1_pkt_type_mask(struct mtk_eth *eth) + { +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + return MTK_FOE_IB1_PACKET_TYPE_V2; + + return MTK_FOE_IB1_PACKET_TYPE; +@@ -1249,7 +1259,7 @@ static inline u32 mtk_get_ib1_pkt_type_m + + static inline u32 mtk_get_ib1_pkt_type(struct mtk_eth *eth, u32 val) + { +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE_V2, val); + + return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, val); +@@ -1257,7 +1267,7 @@ static inline u32 mtk_get_ib1_pkt_type(s + + static inline u32 mtk_get_ib2_multicast_mask(struct mtk_eth *eth) + { +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + return MTK_FOE_IB2_MULTICAST_V2; + + return MTK_FOE_IB2_MULTICAST; +--- a/drivers/net/ethernet/mediatek/mtk_ppe.c ++++ b/drivers/net/ethernet/mediatek/mtk_ppe.c +@@ -207,7 +207,7 @@ int mtk_foe_entry_prepare(struct mtk_eth + + memset(entry, 0, sizeof(*entry)); + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ if (mtk_is_netsys_v2_or_greater(eth)) { + val = FIELD_PREP(MTK_FOE_IB1_STATE, MTK_FOE_STATE_BIND) | + FIELD_PREP(MTK_FOE_IB1_PACKET_TYPE_V2, type) | + FIELD_PREP(MTK_FOE_IB1_UDP, l4proto == IPPROTO_UDP) | +@@ -271,7 +271,7 @@ int mtk_foe_entry_set_pse_port(struct mt + u32 *ib2 = mtk_foe_entry_ib2(eth, entry); + u32 val = *ib2; + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ if (mtk_is_netsys_v2_or_greater(eth)) { + val &= ~MTK_FOE_IB2_DEST_PORT_V2; + val |= FIELD_PREP(MTK_FOE_IB2_DEST_PORT_V2, port); + } else { +@@ -422,7 +422,7 @@ int mtk_foe_entry_set_wdma(struct mtk_et + struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(eth, entry); + u32 *ib2 = mtk_foe_entry_ib2(eth, entry); + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ if (mtk_is_netsys_v2_or_greater(eth)) { + *ib2 &= ~MTK_FOE_IB2_PORT_MG_V2; + *ib2 |= FIELD_PREP(MTK_FOE_IB2_RX_IDX, txq) | + MTK_FOE_IB2_WDMA_WINFO_V2; +@@ -446,7 +446,7 @@ int mtk_foe_entry_set_queue(struct mtk_e + { + u32 *ib2 = mtk_foe_entry_ib2(eth, entry); + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ if (mtk_is_netsys_v2_or_greater(eth)) { + *ib2 &= ~MTK_FOE_IB2_QID_V2; + *ib2 |= FIELD_PREP(MTK_FOE_IB2_QID_V2, queue); + *ib2 |= MTK_FOE_IB2_PSE_QOS_V2; +@@ -601,7 +601,7 @@ __mtk_foe_entry_commit(struct mtk_ppe *p + struct mtk_foe_entry *hwe; + u32 val; + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ if (mtk_is_netsys_v2_or_greater(eth)) { + entry->ib1 &= ~MTK_FOE_IB1_BIND_TIMESTAMP_V2; + entry->ib1 |= FIELD_PREP(MTK_FOE_IB1_BIND_TIMESTAMP_V2, + timestamp); +@@ -617,7 +617,7 @@ __mtk_foe_entry_commit(struct mtk_ppe *p + hwe->ib1 = entry->ib1; + + if (ppe->accounting) { +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + val = MTK_FOE_IB2_MIB_CNT_V2; + else + val = MTK_FOE_IB2_MIB_CNT; +@@ -965,7 +965,7 @@ void mtk_ppe_start(struct mtk_ppe *ppe) + MTK_PPE_SCAN_MODE_KEEPALIVE_AGE) | + FIELD_PREP(MTK_PPE_TB_CFG_ENTRY_NUM, + MTK_PPE_ENTRIES_SHIFT); +- if (MTK_HAS_CAPS(ppe->eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(ppe->eth)) + val |= MTK_PPE_TB_CFG_INFO_SEL; + ppe_w32(ppe, MTK_PPE_TB_CFG, val); + +@@ -981,7 +981,7 @@ void mtk_ppe_start(struct mtk_ppe *ppe) + MTK_PPE_FLOW_CFG_IP4_NAPT | + MTK_PPE_FLOW_CFG_IP4_DSLITE | + MTK_PPE_FLOW_CFG_IP4_NAT_FRAG; +- if (MTK_HAS_CAPS(ppe->eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(ppe->eth)) + val |= MTK_PPE_MD_TOAP_BYP_CRSN0 | + MTK_PPE_MD_TOAP_BYP_CRSN1 | + MTK_PPE_MD_TOAP_BYP_CRSN2 | +@@ -1023,7 +1023,7 @@ void mtk_ppe_start(struct mtk_ppe *ppe) + + ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT, 0); + +- if (MTK_HAS_CAPS(ppe->eth->soc->caps, MTK_NETSYS_V2)) { ++ if (mtk_is_netsys_v2_or_greater(ppe->eth)) { + ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT1, 0xcb777); + ppe_w32(ppe, MTK_PPE_SBW_CTRL, 0x7f); + } +--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c ++++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c +@@ -193,7 +193,7 @@ mtk_flow_set_output_device(struct mtk_et + if (mtk_flow_get_wdma_info(dev, dest_mac, &info) == 0) { + mtk_foe_entry_set_wdma(eth, foe, info.wdma_idx, info.queue, + info.bss, info.wcid); +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ if (mtk_is_netsys_v2_or_greater(eth)) { + switch (info.wdma_idx) { + case 0: + pse_port = 8; +--- a/drivers/net/ethernet/mediatek/mtk_wed.c ++++ b/drivers/net/ethernet/mediatek/mtk_wed.c +@@ -1084,7 +1084,7 @@ mtk_wed_rx_reset(struct mtk_wed_device * + } else { + struct mtk_eth *eth = dev->hw->eth; + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (mtk_is_netsys_v2_or_greater(eth)) + wed_set(dev, MTK_WED_RESET_IDX, + MTK_WED_RESET_IDX_RX_V2); + else +@@ -1806,7 +1806,7 @@ void mtk_wed_add_hw(struct device_node * + hw->wdma = wdma; + hw->index = index; + hw->irq = irq; +- hw->version = MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ? 2 : 1; ++ hw->version = mtk_is_netsys_v1(eth) ? 1 : 2; + + if (hw->version == 1) { + hw->mirror = syscon_regmap_lookup_by_phandle(eth_np, diff --git a/target/linux/generic/backport-6.1/750-v6.5-06-net-ethernet-mtk_eth_soc-increase-MAX_DEVS-to-3.patch b/target/linux/generic/backport-6.1/750-v6.5-06-net-ethernet-mtk_eth_soc-increase-MAX_DEVS-to-3.patch new file mode 100644 index 00000000000..7b945bb869b --- /dev/null +++ b/target/linux/generic/backport-6.1/750-v6.5-06-net-ethernet-mtk_eth_soc-increase-MAX_DEVS-to-3.patch @@ -0,0 +1,29 @@ +From f8fb8dbd158c585be7574faf92db7d614b6722ff Mon Sep 17 00:00:00 2001 +From: Lorenzo Bianconi +Date: Tue, 25 Jul 2023 01:52:27 +0100 +Subject: [PATCH 100/250] net: ethernet: mtk_eth_soc: increase MAX_DEVS to 3 + +This is a preliminary patch to add MT7988 SoC support since it runs 3 +macs instead of 2. + +Signed-off-by: Lorenzo Bianconi +Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/3563e5fab367e7d79a7f1296fabaa5c20f202d7a.1690246066.git.daniel@makrotopia.org +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -1043,8 +1043,8 @@ struct mtk_soc_data { + + #define MTK_DMA_MONITOR_TIMEOUT msecs_to_jiffies(1000) + +-/* currently no SoC has more than 2 macs */ +-#define MTK_MAX_DEVS 2 ++/* currently no SoC has more than 3 macs */ ++#define MTK_MAX_DEVS 3 + + /* struct mtk_eth - This is the main datasructure for holding the state + * of the driver diff --git a/target/linux/generic/pending-6.1/737-03-net-ethernet-mtk_eth_soc-rely-on-num_devs-and-remove.patch b/target/linux/generic/backport-6.1/750-v6.5-07-net-ethernet-mtk_eth_soc-rely-on-MTK_MAX_DEVS-and-re.patch similarity index 50% rename from target/linux/generic/pending-6.1/737-03-net-ethernet-mtk_eth_soc-rely-on-num_devs-and-remove.patch rename to target/linux/generic/backport-6.1/750-v6.5-07-net-ethernet-mtk_eth_soc-rely-on-MTK_MAX_DEVS-and-re.patch index 1989eb677a3..d7ba0d4a572 100644 --- a/target/linux/generic/pending-6.1/737-03-net-ethernet-mtk_eth_soc-rely-on-num_devs-and-remove.patch +++ b/target/linux/generic/backport-6.1/750-v6.5-07-net-ethernet-mtk_eth_soc-rely-on-MTK_MAX_DEVS-and-re.patch @@ -1,143 +1,176 @@ -From 4e35e80750b33727e606be9e7ce447bde2e0deb7 Mon Sep 17 00:00:00 2001 +From 856be974290f28d7943be2ac5a382c4139486196 Mon Sep 17 00:00:00 2001 From: Lorenzo Bianconi -Date: Tue, 7 Mar 2023 15:55:35 +0000 -Subject: [PATCH 3/7] net: ethernet: mtk_eth_soc: rely on num_devs and remove - MTK_MAC_COUNT +Date: Tue, 25 Jul 2023 01:52:44 +0100 +Subject: [PATCH 101/250] net: ethernet: mtk_eth_soc: rely on MTK_MAX_DEVS and + remove MTK_MAC_COUNT -Get rid of MTK_MAC_COUNT since it is a duplicated of eth->soc->num_devs. +Get rid of MTK_MAC_COUNT since it is a duplicated of MTK_MAX_DEVS. Signed-off-by: Lorenzo Bianconi Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/1856f4266f2fc80677807b1bad867659e7b00c65.1690246066.git.daniel@makrotopia.org +Signed-off-by: Jakub Kicinski --- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 30 ++++++++++----------- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 49 ++++++++++++--------- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 1 - - 2 files changed, 15 insertions(+), 16 deletions(-) + 2 files changed, 27 insertions(+), 23 deletions(-) --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -944,7 +944,7 @@ static void mtk_stats_update(struct mtk_ +@@ -882,7 +882,7 @@ static void mtk_stats_update(struct mtk_ { int i; - for (i = 0; i < MTK_MAC_COUNT; i++) { -+ for (i = 0; i < eth->soc->num_devs; i++) { ++ for (i = 0; i < MTK_MAX_DEVS; i++) { if (!eth->mac[i] || !eth->mac[i]->hw_stats) continue; if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { -@@ -1449,7 +1449,7 @@ static int mtk_queue_stopped(struct mtk_ +@@ -1387,7 +1387,7 @@ static int mtk_queue_stopped(struct mtk_ { int i; - for (i = 0; i < MTK_MAC_COUNT; i++) { -+ for (i = 0; i < eth->soc->num_devs; i++) { ++ for (i = 0; i < MTK_MAX_DEVS; i++) { if (!eth->netdev[i]) continue; if (netif_queue_stopped(eth->netdev[i])) -@@ -1463,7 +1463,7 @@ static void mtk_wake_queue(struct mtk_et +@@ -1401,7 +1401,7 @@ static void mtk_wake_queue(struct mtk_et { int i; - for (i = 0; i < MTK_MAC_COUNT; i++) { -+ for (i = 0; i < eth->soc->num_devs; i++) { ++ for (i = 0; i < MTK_MAX_DEVS; i++) { if (!eth->netdev[i]) continue; netif_tx_wake_all_queues(eth->netdev[i]); -@@ -1956,7 +1956,7 @@ static int mtk_poll_rx(struct napi_struc +@@ -1860,7 +1860,7 @@ static int mtk_poll_rx(struct napi_struc !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1; - if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT || -+ if (unlikely(mac < 0 || mac >= eth->soc->num_devs || ++ if (unlikely(mac < 0 || mac >= MTK_MAX_DEVS || !eth->netdev[mac])) goto release_desc; -@@ -2993,7 +2993,7 @@ static void mtk_dma_free(struct mtk_eth +@@ -2897,7 +2897,7 @@ static void mtk_dma_free(struct mtk_eth const struct mtk_soc_data *soc = eth->soc; int i; - for (i = 0; i < MTK_MAC_COUNT; i++) -+ for (i = 0; i < soc->num_devs; i++) ++ for (i = 0; i < MTK_MAX_DEVS; i++) if (eth->netdev[i]) netdev_reset_queue(eth->netdev[i]); if (eth->scratch_ring) { -@@ -3147,7 +3147,7 @@ static void mtk_gdm_config(struct mtk_et +@@ -3051,8 +3051,13 @@ static void mtk_gdm_config(struct mtk_et if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) return; - for (i = 0; i < MTK_MAC_COUNT; i++) { -+ for (i = 0; i < eth->soc->num_devs; i++) { - u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); +- u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); ++ for (i = 0; i < MTK_MAX_DEVS; i++) { ++ u32 val; ++ ++ if (!eth->netdev[i]) ++ continue; ++ ++ val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); /* default setup the forward port to send frame to PDMA */ -@@ -3758,7 +3758,7 @@ static int mtk_hw_init(struct mtk_eth *e + val &= ~0xffff; +@@ -3062,7 +3067,7 @@ static void mtk_gdm_config(struct mtk_et + + val |= config; + +- if (eth->netdev[i] && netdev_uses_dsa(eth->netdev[i])) ++ if (netdev_uses_dsa(eth->netdev[i])) + val |= MTK_GDMA_SPECIAL_TAG; + + mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); +@@ -3659,15 +3664,15 @@ static int mtk_hw_init(struct mtk_eth *e * up with the more appropriate value when mtk_mac_config call is being * invoked. */ - for (i = 0; i < MTK_MAC_COUNT; i++) { -+ for (i = 0; i < eth->soc->num_devs; i++) { ++ for (i = 0; i < MTK_MAX_DEVS; i++) { struct net_device *dev = eth->netdev[i]; - mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); -@@ -3946,7 +3946,7 @@ static void mtk_pending_work(struct work +- mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); +- if (dev) { +- struct mtk_mac *mac = netdev_priv(dev); ++ if (!dev) ++ continue; + +- mtk_set_mcr_max_rx(mac, dev->mtu + MTK_RX_ETH_HLEN); +- } ++ mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); ++ mtk_set_mcr_max_rx(netdev_priv(dev), ++ dev->mtu + MTK_RX_ETH_HLEN); + } + + /* Indicates CDM to parse the MTK special tag from CPU +@@ -3847,7 +3852,7 @@ static void mtk_pending_work(struct work mtk_prepare_for_reset(eth); /* stop all devices to make sure that dma is properly shut down */ - for (i = 0; i < MTK_MAC_COUNT; i++) { -+ for (i = 0; i < eth->soc->num_devs; i++) { ++ for (i = 0; i < MTK_MAX_DEVS; i++) { if (!eth->netdev[i] || !netif_running(eth->netdev[i])) continue; -@@ -3962,7 +3962,7 @@ static void mtk_pending_work(struct work +@@ -3863,8 +3868,8 @@ static void mtk_pending_work(struct work mtk_hw_init(eth, true); /* restart DMA and enable IRQs */ - for (i = 0; i < MTK_MAC_COUNT; i++) { -+ for (i = 0; i < eth->soc->num_devs; i++) { - if (!test_bit(i, &restart)) +- if (!test_bit(i, &restart)) ++ for (i = 0; i < MTK_MAX_DEVS; i++) { ++ if (!eth->netdev[i] || !test_bit(i, &restart)) continue; -@@ -3990,7 +3990,7 @@ static int mtk_free_dev(struct mtk_eth * + if (mtk_open(eth->netdev[i])) { +@@ -3891,7 +3896,7 @@ static int mtk_free_dev(struct mtk_eth * { int i; - for (i = 0; i < MTK_MAC_COUNT; i++) { -+ for (i = 0; i < eth->soc->num_devs; i++) { ++ for (i = 0; i < MTK_MAX_DEVS; i++) { if (!eth->netdev[i]) continue; free_netdev(eth->netdev[i]); -@@ -4009,7 +4009,7 @@ static int mtk_unreg_dev(struct mtk_eth +@@ -3910,7 +3915,7 @@ static int mtk_unreg_dev(struct mtk_eth { int i; - for (i = 0; i < MTK_MAC_COUNT; i++) { -+ for (i = 0; i < eth->soc->num_devs; i++) { ++ for (i = 0; i < MTK_MAX_DEVS; i++) { struct mtk_mac *mac; if (!eth->netdev[i]) continue; -@@ -4313,7 +4313,7 @@ static int mtk_add_mac(struct mtk_eth *e +@@ -4211,7 +4216,7 @@ static int mtk_add_mac(struct mtk_eth *e } id = be32_to_cpup(_id); - if (id >= MTK_MAC_COUNT) { -+ if (id >= eth->soc->num_devs) { ++ if (id >= MTK_MAX_DEVS) { dev_err(eth->dev, "%d is not a valid mac id\n", id); return -EINVAL; } -@@ -4454,7 +4454,7 @@ void mtk_eth_set_dma_device(struct mtk_e +@@ -4356,7 +4361,7 @@ void mtk_eth_set_dma_device(struct mtk_e rtnl_lock(); - for (i = 0; i < MTK_MAC_COUNT; i++) { -+ for (i = 0; i < eth->soc->num_devs; i++) { ++ for (i = 0; i < MTK_MAX_DEVS; i++) { dev = eth->netdev[i]; if (!dev || !(dev->flags & IFF_UP)) -@@ -4780,7 +4780,7 @@ static int mtk_remove(struct platform_de +@@ -4662,7 +4667,7 @@ static int mtk_remove(struct platform_de int i; /* stop all devices to make sure that dma is properly shut down */ - for (i = 0; i < MTK_MAC_COUNT; i++) { -+ for (i = 0; i < eth->soc->num_devs; i++) { ++ for (i = 0; i < MTK_MAX_DEVS; i++) { if (!eth->netdev[i]) continue; mtk_stop(eth->netdev[i]); diff --git a/target/linux/generic/pending-6.1/737-04-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V3-capabilit.patch b/target/linux/generic/backport-6.1/750-v6.5-08-net-ethernet-mtk_eth_soc-add-NETSYS_V3-version-suppo.patch similarity index 63% rename from target/linux/generic/pending-6.1/737-04-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V3-capabilit.patch rename to target/linux/generic/backport-6.1/750-v6.5-08-net-ethernet-mtk_eth_soc-add-NETSYS_V3-version-suppo.patch index 9c7b47f15b6..f06fcce618b 100644 --- a/target/linux/generic/pending-6.1/737-04-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V3-capabilit.patch +++ b/target/linux/generic/backport-6.1/750-v6.5-08-net-ethernet-mtk_eth_soc-add-NETSYS_V3-version-suppo.patch @@ -1,22 +1,24 @@ -From ab817f559d505329d8a413c7d29250f6d87d77a0 Mon Sep 17 00:00:00 2001 +From a41d535855976838d246c079143c948dcf0f7931 Mon Sep 17 00:00:00 2001 From: Lorenzo Bianconi -Date: Tue, 7 Mar 2023 15:55:47 +0000 -Subject: [PATCH 4/7] net: ethernet: mtk_eth_soc: add MTK_NETSYS_V3 capability - bit +Date: Tue, 25 Jul 2023 01:52:59 +0100 +Subject: [PATCH 102/250] net: ethernet: mtk_eth_soc: add NETSYS_V3 version + support -Introduce MTK_NETSYS_V3 bit in the device capabilities. +Introduce NETSYS_V3 chipset version support. This is a preliminary patch to introduce support for MT7988 SoC. Signed-off-by: Lorenzo Bianconi Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/0db2260910755d76fa48e303b9f9bdf4e5a82340.1690246066.git.daniel@makrotopia.org +Signed-off-by: Jakub Kicinski --- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 115 ++++++++++++++++---- - drivers/net/ethernet/mediatek/mtk_eth_soc.h | 44 +++++++- - 2 files changed, 134 insertions(+), 25 deletions(-) + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 105 ++++++++++++++------ + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 48 +++++++-- + 2 files changed, 116 insertions(+), 37 deletions(-) --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -924,17 +924,32 @@ void mtk_stats_update_mac(struct mtk_mac +@@ -862,17 +862,32 @@ void mtk_stats_update_mac(struct mtk_mac mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs); hw_stats->rx_flow_control_packets += mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs); @@ -32,7 +34,7 @@ Signed-off-by: Daniel Golle - hw_stats->tx_packets += - mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs); + -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { ++ if (mtk_is_netsys_v3_or_greater(eth)) { + hw_stats->tx_skip += + mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x50 + offs); + hw_stats->tx_collisions += @@ -60,7 +62,7 @@ Signed-off-by: Daniel Golle } u64_stats_update_end(&hw_stats->syncp); -@@ -1238,7 +1253,10 @@ static void mtk_tx_set_dma_desc_v2(struc +@@ -1176,7 +1191,10 @@ static void mtk_tx_set_dma_desc_v2(struc data |= TX_DMA_LS0; WRITE_ONCE(desc->txd3, data); @@ -72,57 +74,53 @@ Signed-off-by: Daniel Golle data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid); WRITE_ONCE(desc->txd4, data); -@@ -1249,6 +1267,9 @@ static void mtk_tx_set_dma_desc_v2(struc +@@ -1187,6 +1205,8 @@ static void mtk_tx_set_dma_desc_v2(struc /* tx checksum offload */ if (info->csum) data |= TX_DMA_CHKSUM_V2; -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3) && -+ netdev_uses_dsa(dev)) ++ if (mtk_is_netsys_v3_or_greater(eth) && netdev_uses_dsa(dev)) + data |= TX_DMA_SPTAG_V3; } WRITE_ONCE(desc->txd5, data); -@@ -1314,8 +1335,13 @@ static int mtk_tx_map(struct sk_buff *sk +@@ -1252,8 +1272,7 @@ static int mtk_tx_map(struct sk_buff *sk mtk_tx_set_dma_desc(dev, itxd, &txd_info); itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; - itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : - MTK_TX_FLAGS_FPORT1; -+ if (mac->id == MTK_GMAC1_ID) -+ itx_buf->flags |= MTK_TX_FLAGS_FPORT0; -+ else if (mac->id == MTK_GMAC2_ID) -+ itx_buf->flags |= MTK_TX_FLAGS_FPORT1; -+ else -+ itx_buf->flags |= MTK_TX_FLAGS_FPORT2; -+ ++ itx_buf->mac_id = mac->id; setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size, k++); -@@ -1363,8 +1389,13 @@ static int mtk_tx_map(struct sk_buff *sk +@@ -1301,8 +1320,7 @@ static int mtk_tx_map(struct sk_buff *sk memset(tx_buf, 0, sizeof(*tx_buf)); tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; tx_buf->flags |= MTK_TX_FLAGS_PAGE0; - tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : - MTK_TX_FLAGS_FPORT1; -+ -+ if (mac->id == MTK_GMAC1_ID) -+ tx_buf->flags |= MTK_TX_FLAGS_FPORT0; -+ else if (mac->id == MTK_GMAC2_ID) -+ tx_buf->flags |= MTK_TX_FLAGS_FPORT1; -+ else -+ tx_buf->flags |= MTK_TX_FLAGS_FPORT2; ++ tx_buf->mac_id = mac->id; setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr, txd_info.size, k++); -@@ -1950,11 +1981,24 @@ static int mtk_poll_rx(struct napi_struc +@@ -1604,7 +1622,7 @@ static int mtk_xdp_frame_map(struct mtk_ + } + mtk_tx_set_dma_desc(dev, txd, txd_info); + +- tx_buf->flags |= !mac->id ? MTK_TX_FLAGS_FPORT0 : MTK_TX_FLAGS_FPORT1; ++ tx_buf->mac_id = mac->id; + tx_buf->type = dma_map ? MTK_TYPE_XDP_NDO : MTK_TYPE_XDP_TX; + tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; + +@@ -1854,11 +1872,24 @@ static int mtk_poll_rx(struct napi_struc break; /* find out which mac the packet come from. values start at 1 */ -- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) +- if (mtk_is_netsys_v2_or_greater(eth)) - mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1; - else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && - !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) -+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { ++ if (mtk_is_netsys_v2_or_greater(eth)) { + u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5); + + switch (val) { @@ -137,29 +135,44 @@ Signed-off-by: Daniel Golle + break; + } + } else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && -+ !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) { ++ !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) { mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1; + } - if (unlikely(mac < 0 || mac >= eth->soc->num_devs || + if (unlikely(mac < 0 || mac >= MTK_MAX_DEVS || !eth->netdev[mac])) -@@ -2185,7 +2229,9 @@ static int mtk_poll_tx_qdma(struct mtk_e +@@ -2080,7 +2111,6 @@ static int mtk_poll_tx_qdma(struct mtk_e + + while ((cpu != dma) && budget) { + u32 next_cpu = desc->txd2; +- int mac = 0; + + desc = mtk_qdma_phys_to_virt(ring, desc->txd2); + if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) +@@ -2088,15 +2118,13 @@ static int mtk_poll_tx_qdma(struct mtk_e + tx_buf = mtk_desc_to_tx_buf(ring, desc, eth->soc->txrx.txd_size); - if (tx_buf->flags & MTK_TX_FLAGS_FPORT1) +- if (tx_buf->flags & MTK_TX_FLAGS_FPORT1) - mac = 1; -+ mac = MTK_GMAC2_ID; -+ else if (tx_buf->flags & MTK_TX_FLAGS_FPORT2) -+ mac = MTK_GMAC3_ID; - +- if (!tx_buf->data) break; -@@ -3796,7 +3842,26 @@ static int mtk_hw_init(struct mtk_eth *e + + if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { + if (tx_buf->type == MTK_TYPE_SKB) +- mtk_poll_tx_done(eth, state, mac, tx_buf->data); ++ mtk_poll_tx_done(eth, state, tx_buf->mac_id, ++ tx_buf->data); + + budget--; + } +@@ -3702,7 +3730,24 @@ static int mtk_hw_init(struct mtk_eth *e mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4); mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); -- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { +- if (mtk_is_netsys_v2_or_greater(eth)) { ++ if (mtk_is_netsys_v3_or_greater(eth)) { + /* PSE should not drop port1, port8 and port9 packets */ + mtk_w32(eth, 0x00000302, PSE_DROP_CFG); + @@ -168,9 +181,7 @@ Signed-off-by: Daniel Golle + mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES); + + /* Disable GDM1 RX CRC stripping */ -+ val = mtk_r32(eth, MTK_GDMA_FWD_CFG(0)); -+ val &= ~MTK_GDMA_STRP_CRC; -+ mtk_w32(eth, val, MTK_GDMA_FWD_CFG(0)); ++ mtk_m32(eth, MTK_GDMA_STRP_CRC, 0, MTK_GDMA_FWD_CFG(0)); + + /* PSE GDM3 MIB counter has incorrect hw default values, + * so the driver ought to read clear the values beforehand @@ -178,17 +189,17 @@ Signed-off-by: Daniel Golle + */ + for (i = 0; i < 0x80; i += 0x4) + mtk_r32(eth, reg_map->gdm1_cnt + 0x100 + i); -+ } else if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ } else if (!mtk_is_netsys_v1(eth)) { /* PSE should not drop port8 and port9 packets from WDMA Tx */ mtk_w32(eth, 0x00000300, PSE_DROP_CFG); -@@ -4361,7 +4426,11 @@ static int mtk_add_mac(struct mtk_eth *e +@@ -4264,7 +4309,11 @@ static int mtk_add_mac(struct mtk_eth *e } spin_lock_init(&mac->hw_stats->stats_lock); u64_stats_init(&mac->hw_stats->syncp); - mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; + -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) ++ if (mtk_is_netsys_v3_or_greater(eth)) + mac->hw_stats->reg_offset = id * 0x80; + else + mac->hw_stats->reg_offset = id * 0x40; @@ -197,7 +208,7 @@ Signed-off-by: Daniel Golle err = of_get_phy_mode(np, &phy_mode); --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -121,6 +121,7 @@ +@@ -122,6 +122,7 @@ #define MTK_GDMA_ICS_EN BIT(22) #define MTK_GDMA_TCS_EN BIT(21) #define MTK_GDMA_UCS_EN BIT(20) @@ -205,7 +216,7 @@ Signed-off-by: Daniel Golle #define MTK_GDMA_TO_PDMA 0x0 #define MTK_GDMA_DROP_ALL 0x7777 -@@ -286,8 +287,6 @@ +@@ -287,8 +288,6 @@ /* QDMA Interrupt grouping registers */ #define MTK_RLS_DONE_INT BIT(0) @@ -214,7 +225,7 @@ Signed-off-by: Daniel Golle /* QDMA TX NUM */ #define QID_BITS_V2(x) (((x) & 0x3f) << 16) #define MTK_QDMA_GMAC2_QID 8 -@@ -300,6 +299,8 @@ +@@ -301,6 +300,8 @@ #define TX_DMA_CHKSUM_V2 (0x7 << 28) #define TX_DMA_TSO_V2 BIT(31) @@ -223,15 +234,20 @@ Signed-off-by: Daniel Golle /* QDMA V2 descriptor txd4 */ #define TX_DMA_FPORT_SHIFT_V2 8 #define TX_DMA_FPORT_MASK_V2 0xf -@@ -639,6 +640,7 @@ enum mtk_tx_flags { +@@ -634,12 +635,6 @@ enum mtk_tx_flags { */ - MTK_TX_FLAGS_FPORT0 = 0x04, - MTK_TX_FLAGS_FPORT1 = 0x08, -+ MTK_TX_FLAGS_FPORT2 = 0x10, + MTK_TX_FLAGS_SINGLE0 = 0x01, + MTK_TX_FLAGS_PAGE0 = 0x02, +- +- /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted +- * SKB out instead of looking up through hardware TX descriptor. +- */ +- MTK_TX_FLAGS_FPORT0 = 0x04, +- MTK_TX_FLAGS_FPORT1 = 0x08, }; /* This enum allows us to identify how the clock is defined on the array of the -@@ -724,6 +726,42 @@ enum mtk_dev_state { +@@ -725,6 +720,35 @@ enum mtk_dev_state { MTK_RESETTING }; @@ -263,30 +279,29 @@ Signed-off-by: Daniel Golle + MTK_GMAC3_ID, + MTK_GMAC_ID_MAX +}; -+ -+/* GDM Type */ -+enum mtk_gdm_type { -+ MTK_GDM_TYPE = 0, -+ MTK_XGDM_TYPE, -+ MTK_GDM_TYPE_MAX -+}; + enum mtk_tx_buf_type { MTK_TYPE_SKB, MTK_TYPE_XDP_TX, -@@ -820,6 +858,7 @@ enum mkt_eth_capabilities { - MTK_QDMA_BIT, - MTK_NETSYS_V1_BIT, - MTK_NETSYS_V2_BIT, -+ MTK_NETSYS_V3_BIT, - MTK_SOC_MT7628_BIT, - MTK_RSTCTRL_PPE1_BIT, - MTK_U3_COPHY_V2_BIT, -@@ -856,6 +895,7 @@ enum mkt_eth_capabilities { - #define MTK_QDMA BIT(MTK_QDMA_BIT) - #define MTK_NETSYS_V1 BIT(MTK_NETSYS_V1_BIT) - #define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) -+#define MTK_NETSYS_V3 BIT(MTK_NETSYS_V3_BIT) - #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) - #define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT) - #define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT) +@@ -743,7 +767,8 @@ struct mtk_tx_buf { + enum mtk_tx_buf_type type; + void *data; + +- u32 flags; ++ u16 mac_id; ++ u16 flags; + DEFINE_DMA_UNMAP_ADDR(dma_addr0); + DEFINE_DMA_UNMAP_LEN(dma_len0); + DEFINE_DMA_UNMAP_ADDR(dma_addr1); +@@ -1192,6 +1217,11 @@ static inline bool mtk_is_netsys_v2_or_g + return eth->soc->version > 1; + } + ++static inline bool mtk_is_netsys_v3_or_greater(struct mtk_eth *eth) ++{ ++ return eth->soc->version > 2; ++} ++ + static inline struct mtk_foe_entry * + mtk_foe_get_entry(struct mtk_ppe *ppe, u16 hash) + { diff --git a/target/linux/generic/pending-6.1/737-05-net-ethernet-mtk_eth_soc-convert-caps-in-mtk_soc_dat.patch b/target/linux/generic/backport-6.1/750-v6.5-09-net-ethernet-mtk_eth_soc-convert-caps-in-mtk_soc_dat.patch similarity index 89% rename from target/linux/generic/pending-6.1/737-05-net-ethernet-mtk_eth_soc-convert-caps-in-mtk_soc_dat.patch rename to target/linux/generic/backport-6.1/750-v6.5-09-net-ethernet-mtk_eth_soc-convert-caps-in-mtk_soc_dat.patch index 068201cf7df..7a0b285f2ca 100644 --- a/target/linux/generic/pending-6.1/737-05-net-ethernet-mtk_eth_soc-convert-caps-in-mtk_soc_dat.patch +++ b/target/linux/generic/backport-6.1/750-v6.5-09-net-ethernet-mtk_eth_soc-convert-caps-in-mtk_soc_dat.patch @@ -1,17 +1,19 @@ -From 45b575fd9e6a455090820248bf1b98b1f2c7b6c8 Mon Sep 17 00:00:00 2001 +From db797ae0542220a98658229397da464c383c991c Mon Sep 17 00:00:00 2001 From: Lorenzo Bianconi -Date: Tue, 7 Mar 2023 15:56:00 +0000 -Subject: [PATCH 5/7] net: ethernet: mtk_eth_soc: convert caps in mtk_soc_data - struct to u64 +Date: Tue, 25 Jul 2023 01:53:13 +0100 +Subject: [PATCH 103/250] net: ethernet: mtk_eth_soc: convert caps in + mtk_soc_data struct to u64 This is a preliminary patch to introduce support for MT7988 SoC. Signed-off-by: Lorenzo Bianconi Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/9499ac3670b2fc5b444404b84e8a4a169beabbf2.1690246066.git.daniel@makrotopia.org +Signed-off-by: Jakub Kicinski --- - drivers/net/ethernet/mediatek/mtk_eth_path.c | 22 +++---- - drivers/net/ethernet/mediatek/mtk_eth_soc.h | 62 ++++++++++---------- - 2 files changed, 42 insertions(+), 42 deletions(-) + drivers/net/ethernet/mediatek/mtk_eth_path.c | 22 ++++---- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 56 ++++++++++---------- + 2 files changed, 39 insertions(+), 39 deletions(-) --- a/drivers/net/ethernet/mediatek/mtk_eth_path.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c @@ -111,7 +113,7 @@ Signed-off-by: Daniel Golle MTK_ETH_PATH_GMAC2_RGMII; --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -881,44 +881,44 @@ enum mkt_eth_capabilities { +@@ -866,41 +866,41 @@ enum mkt_eth_capabilities { }; /* Supported hardware group on SoCs */ @@ -127,9 +129,6 @@ Signed-off-by: Daniel Golle -#define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT) -#define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) -#define MTK_QDMA BIT(MTK_QDMA_BIT) --#define MTK_NETSYS_V1 BIT(MTK_NETSYS_V1_BIT) --#define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) --#define MTK_NETSYS_V3 BIT(MTK_NETSYS_V3_BIT) -#define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) -#define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT) -#define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT) @@ -145,9 +144,6 @@ Signed-off-by: Daniel Golle +#define MTK_SHARED_INT BIT_ULL(MTK_SHARED_INT_BIT) +#define MTK_TRGMII_MT7621_CLK BIT_ULL(MTK_TRGMII_MT7621_CLK_BIT) +#define MTK_QDMA BIT_ULL(MTK_QDMA_BIT) -+#define MTK_NETSYS_V1 BIT_ULL(MTK_NETSYS_V1_BIT) -+#define MTK_NETSYS_V2 BIT_ULL(MTK_NETSYS_V2_BIT) -+#define MTK_NETSYS_V3 BIT_ULL(MTK_NETSYS_V3_BIT) +#define MTK_SOC_MT7628 BIT_ULL(MTK_SOC_MT7628_BIT) +#define MTK_RSTCTRL_PPE1 BIT_ULL(MTK_RSTCTRL_PPE1_BIT) +#define MTK_U3_COPHY_V2 BIT_ULL(MTK_U3_COPHY_V2_BIT) @@ -186,7 +182,7 @@ Signed-off-by: Daniel Golle #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) -@@ -1074,7 +1074,7 @@ struct mtk_reg_map { +@@ -1045,7 +1045,7 @@ struct mtk_reg_map { struct mtk_soc_data { const struct mtk_reg_map *reg_map; u32 ana_rgc3; diff --git a/target/linux/generic/backport-6.1/750-v6.5-10-net-ethernet-mtk_eth_soc-convert-clock-bitmap-to-u64.patch b/target/linux/generic/backport-6.1/750-v6.5-10-net-ethernet-mtk_eth_soc-convert-clock-bitmap-to-u64.patch new file mode 100644 index 00000000000..5947d385f25 --- /dev/null +++ b/target/linux/generic/backport-6.1/750-v6.5-10-net-ethernet-mtk_eth_soc-convert-clock-bitmap-to-u64.patch @@ -0,0 +1,132 @@ +From a1c9f7d1d24e90294f6a6755b137fcf306851e93 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Tue, 25 Jul 2023 01:53:28 +0100 +Subject: [PATCH 104/250] net: ethernet: mtk_eth_soc: convert clock bitmap to + u64 + +The to-be-added MT7988 SoC adds many new clocks which need to be +controlled by the Ethernet driver, which will result in their total +number exceeding 32. +Prepare by converting clock bitmaps into 64-bit types. + +Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/6960a39bb0078cf84d7642a9558e6a91c6cc9df3.1690246066.git.daniel@makrotopia.org +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 96 +++++++++++---------- + 1 file changed, 49 insertions(+), 47 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -666,54 +666,56 @@ enum mtk_clks_map { + MTK_CLK_MAX + }; + +-#define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ +- BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \ +- BIT(MTK_CLK_TRGPLL)) +-#define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ +- BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ +- BIT(MTK_CLK_GP2) | \ +- BIT(MTK_CLK_SGMII_TX_250M) | \ +- BIT(MTK_CLK_SGMII_RX_250M) | \ +- BIT(MTK_CLK_SGMII_CDR_REF) | \ +- BIT(MTK_CLK_SGMII_CDR_FB) | \ +- BIT(MTK_CLK_SGMII_CK) | \ +- BIT(MTK_CLK_ETH2PLL)) ++#define MT7623_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \ ++ BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \ ++ BIT_ULL(MTK_CLK_TRGPLL)) ++#define MT7622_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \ ++ BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \ ++ BIT_ULL(MTK_CLK_GP2) | \ ++ BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ ++ BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ ++ BIT_ULL(MTK_CLK_SGMII_CK) | \ ++ BIT_ULL(MTK_CLK_ETH2PLL)) + #define MT7621_CLKS_BITMAP (0) + #define MT7628_CLKS_BITMAP (0) +-#define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ +- BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ +- BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \ +- BIT(MTK_CLK_SGMII_TX_250M) | \ +- BIT(MTK_CLK_SGMII_RX_250M) | \ +- BIT(MTK_CLK_SGMII_CDR_REF) | \ +- BIT(MTK_CLK_SGMII_CDR_FB) | \ +- BIT(MTK_CLK_SGMII2_TX_250M) | \ +- BIT(MTK_CLK_SGMII2_RX_250M) | \ +- BIT(MTK_CLK_SGMII2_CDR_REF) | \ +- BIT(MTK_CLK_SGMII2_CDR_FB) | \ +- BIT(MTK_CLK_SGMII_CK) | \ +- BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP)) +-#define MT7981_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \ +- BIT(MTK_CLK_WOCPU0) | \ +- BIT(MTK_CLK_SGMII_TX_250M) | \ +- BIT(MTK_CLK_SGMII_RX_250M) | \ +- BIT(MTK_CLK_SGMII_CDR_REF) | \ +- BIT(MTK_CLK_SGMII_CDR_FB) | \ +- BIT(MTK_CLK_SGMII2_TX_250M) | \ +- BIT(MTK_CLK_SGMII2_RX_250M) | \ +- BIT(MTK_CLK_SGMII2_CDR_REF) | \ +- BIT(MTK_CLK_SGMII2_CDR_FB) | \ +- BIT(MTK_CLK_SGMII_CK)) +-#define MT7986_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \ +- BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \ +- BIT(MTK_CLK_SGMII_TX_250M) | \ +- BIT(MTK_CLK_SGMII_RX_250M) | \ +- BIT(MTK_CLK_SGMII_CDR_REF) | \ +- BIT(MTK_CLK_SGMII_CDR_FB) | \ +- BIT(MTK_CLK_SGMII2_TX_250M) | \ +- BIT(MTK_CLK_SGMII2_RX_250M) | \ +- BIT(MTK_CLK_SGMII2_CDR_REF) | \ +- BIT(MTK_CLK_SGMII2_CDR_FB)) ++#define MT7629_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \ ++ BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \ ++ BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_FE) | \ ++ BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ ++ BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ ++ BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ ++ BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \ ++ BIT_ULL(MTK_CLK_SGMII_CK) | \ ++ BIT_ULL(MTK_CLK_ETH2PLL) | BIT_ULL(MTK_CLK_SGMIITOP)) ++#define MT7981_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \ ++ BIT_ULL(MTK_CLK_GP1) | \ ++ BIT_ULL(MTK_CLK_WOCPU0) | \ ++ BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ ++ BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ ++ BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ ++ BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \ ++ BIT_ULL(MTK_CLK_SGMII_CK)) ++#define MT7986_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \ ++ BIT_ULL(MTK_CLK_GP1) | \ ++ BIT_ULL(MTK_CLK_WOCPU1) | BIT_ULL(MTK_CLK_WOCPU0) | \ ++ BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ ++ BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ ++ BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ ++ BIT_ULL(MTK_CLK_SGMII2_CDR_FB)) + + enum mtk_dev_state { + MTK_HW_INIT, +@@ -1046,7 +1048,7 @@ struct mtk_soc_data { + const struct mtk_reg_map *reg_map; + u32 ana_rgc3; + u64 caps; +- u32 required_clks; ++ u64 required_clks; + bool required_pctl; + u8 offload_version; + u8 hash_offset; diff --git a/target/linux/generic/backport-6.1/750-v6.5-11-net-ethernet-mtk_eth_soc-add-basic-support-for-MT798.patch b/target/linux/generic/backport-6.1/750-v6.5-11-net-ethernet-mtk_eth_soc-add-basic-support-for-MT798.patch new file mode 100644 index 00000000000..a7195236c38 --- /dev/null +++ b/target/linux/generic/backport-6.1/750-v6.5-11-net-ethernet-mtk_eth_soc-add-basic-support-for-MT798.patch @@ -0,0 +1,477 @@ +From 94f825a7eadfc8b4c8828efdb7705d9703f9c73e Mon Sep 17 00:00:00 2001 +From: Lorenzo Bianconi +Date: Tue, 25 Jul 2023 01:57:42 +0100 +Subject: [PATCH 105/250] net: ethernet: mtk_eth_soc: add basic support for + MT7988 SoC + +Introduce support for ethernet chip available in MT7988 SoC to +mtk_eth_soc driver. As a first step support only the first GMAC which +is hard-wired to the internal DSA switch having 4 built-in gigabit +Ethernet PHYs. + +Signed-off-by: Lorenzo Bianconi +Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/25c8377095b95d186872eeda7aa055da83e8f0ca.1690246605.git.daniel@makrotopia.org +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_path.c | 14 +- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 201 +++++++++++++++++-- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 86 +++++++- + 3 files changed, 273 insertions(+), 28 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_path.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c +@@ -43,7 +43,7 @@ static const char *mtk_eth_path_name(u64 + static int set_mux_gdm1_to_gmac1_esw(struct mtk_eth *eth, u64 path) + { + bool updated = true; +- u32 val, mask, set; ++ u32 mask, set, reg; + + switch (path) { + case MTK_ETH_PATH_GMAC1_SGMII: +@@ -59,11 +59,13 @@ static int set_mux_gdm1_to_gmac1_esw(str + break; + } + +- if (updated) { +- val = mtk_r32(eth, MTK_MAC_MISC); +- val = (val & mask) | set; +- mtk_w32(eth, val, MTK_MAC_MISC); +- } ++ if (mtk_is_netsys_v3_or_greater(eth)) ++ reg = MTK_MAC_MISC_V3; ++ else ++ reg = MTK_MAC_MISC; ++ ++ if (updated) ++ mtk_m32(eth, mask, set, reg); + + dev_dbg(eth->dev, "path %s in %s updated = %d\n", + mtk_eth_path_name(path), __func__, updated); +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -152,6 +152,54 @@ static const struct mtk_reg_map mt7986_r + .pse_oq_sta = 0x01a0, + }; + ++static const struct mtk_reg_map mt7988_reg_map = { ++ .tx_irq_mask = 0x461c, ++ .tx_irq_status = 0x4618, ++ .pdma = { ++ .rx_ptr = 0x6900, ++ .rx_cnt_cfg = 0x6904, ++ .pcrx_ptr = 0x6908, ++ .glo_cfg = 0x6a04, ++ .rst_idx = 0x6a08, ++ .delay_irq = 0x6a0c, ++ .irq_status = 0x6a20, ++ .irq_mask = 0x6a28, ++ .adma_rx_dbg0 = 0x6a38, ++ .int_grp = 0x6a50, ++ }, ++ .qdma = { ++ .qtx_cfg = 0x4400, ++ .qtx_sch = 0x4404, ++ .rx_ptr = 0x4500, ++ .rx_cnt_cfg = 0x4504, ++ .qcrx_ptr = 0x4508, ++ .glo_cfg = 0x4604, ++ .rst_idx = 0x4608, ++ .delay_irq = 0x460c, ++ .fc_th = 0x4610, ++ .int_grp = 0x4620, ++ .hred = 0x4644, ++ .ctx_ptr = 0x4700, ++ .dtx_ptr = 0x4704, ++ .crx_ptr = 0x4710, ++ .drx_ptr = 0x4714, ++ .fq_head = 0x4720, ++ .fq_tail = 0x4724, ++ .fq_count = 0x4728, ++ .fq_blen = 0x472c, ++ .tx_sch_rate = 0x4798, ++ }, ++ .gdm1_cnt = 0x1c00, ++ .gdma_to_ppe = 0x3333, ++ .ppe_base = 0x2000, ++ .wdma_base = { ++ [0] = 0x4800, ++ [1] = 0x4c00, ++ }, ++ .pse_iq_sta = 0x0180, ++ .pse_oq_sta = 0x01a0, ++}; ++ + /* strings used by ethtool */ + static const struct mtk_ethtool_stats { + char str[ETH_GSTRING_LEN]; +@@ -179,10 +227,54 @@ static const struct mtk_ethtool_stats { + }; + + static const char * const mtk_clks_source_name[] = { +- "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll", +- "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", +- "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb", +- "sgmii_ck", "eth2pll", "wocpu0", "wocpu1", "netsys0", "netsys1" ++ "ethif", ++ "sgmiitop", ++ "esw", ++ "gp0", ++ "gp1", ++ "gp2", ++ "gp3", ++ "xgp1", ++ "xgp2", ++ "xgp3", ++ "crypto", ++ "fe", ++ "trgpll", ++ "sgmii_tx250m", ++ "sgmii_rx250m", ++ "sgmii_cdr_ref", ++ "sgmii_cdr_fb", ++ "sgmii2_tx250m", ++ "sgmii2_rx250m", ++ "sgmii2_cdr_ref", ++ "sgmii2_cdr_fb", ++ "sgmii_ck", ++ "eth2pll", ++ "wocpu0", ++ "wocpu1", ++ "netsys0", ++ "netsys1", ++ "ethwarp_wocpu2", ++ "ethwarp_wocpu1", ++ "ethwarp_wocpu0", ++ "top_usxgmii0_sel", ++ "top_usxgmii1_sel", ++ "top_sgm0_sel", ++ "top_sgm1_sel", ++ "top_xfi_phy0_xtal_sel", ++ "top_xfi_phy1_xtal_sel", ++ "top_eth_gmii_sel", ++ "top_eth_refck_50m_sel", ++ "top_eth_sys_200m_sel", ++ "top_eth_sys_sel", ++ "top_eth_xgmii_sel", ++ "top_eth_mii_sel", ++ "top_netsys_sel", ++ "top_netsys_500m_sel", ++ "top_netsys_pao_2x_sel", ++ "top_netsys_sync_250m_sel", ++ "top_netsys_ppefb_250m_sel", ++ "top_netsys_warp_sel", + }; + + void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) +@@ -195,7 +287,7 @@ u32 mtk_r32(struct mtk_eth *eth, unsigne + return __raw_readl(eth->base + reg); + } + +-static u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg) ++u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg) + { + u32 val; + +@@ -369,6 +461,19 @@ static void mtk_gmac0_rgmii_adjust(struc + dev_err(eth->dev, "Missing PLL configuration, ethernet may not work\n"); + } + ++static void mtk_setup_bridge_switch(struct mtk_eth *eth) ++{ ++ /* Force Port1 XGMAC Link Up */ ++ mtk_m32(eth, 0, MTK_XGMAC_FORCE_LINK(MTK_GMAC1_ID), ++ MTK_XGMAC_STS(MTK_GMAC1_ID)); ++ ++ /* Adjust GSW bridge IPG to 11 */ ++ mtk_m32(eth, GSWTX_IPG_MASK | GSWRX_IPG_MASK, ++ (GSW_IPG_11 << GSWTX_IPG_SHIFT) | ++ (GSW_IPG_11 << GSWRX_IPG_SHIFT), ++ MTK_GSW_CFG); ++} ++ + static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config, + phy_interface_t interface) + { +@@ -438,6 +543,8 @@ static void mtk_mac_config(struct phylin + goto init_err; + } + break; ++ case PHY_INTERFACE_MODE_INTERNAL: ++ break; + default: + goto err_phy; + } +@@ -515,6 +622,15 @@ static void mtk_mac_config(struct phylin + return; + } + ++ /* Setup gmac */ ++ if (mtk_is_netsys_v3_or_greater(eth) && ++ mac->interface == PHY_INTERFACE_MODE_INTERNAL) { ++ mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id)); ++ mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id)); ++ ++ mtk_setup_bridge_switch(eth); ++ } ++ + return; + + err_phy: +@@ -726,11 +842,15 @@ static int mtk_mdio_init(struct mtk_eth + } + divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63); + ++ /* Configure MDC Turbo Mode */ ++ if (mtk_is_netsys_v3_or_greater(eth)) ++ mtk_m32(eth, 0, MISC_MDC_TURBO, MTK_MAC_MISC_V3); ++ + /* Configure MDC Divider */ +- val = mtk_r32(eth, MTK_PPSC); +- val &= ~PPSC_MDC_CFG; +- val |= FIELD_PREP(PPSC_MDC_CFG, divider) | PPSC_MDC_TURBO; +- mtk_w32(eth, val, MTK_PPSC); ++ val = FIELD_PREP(PPSC_MDC_CFG, divider); ++ if (!mtk_is_netsys_v3_or_greater(eth)) ++ val |= PPSC_MDC_TURBO; ++ mtk_m32(eth, PPSC_MDC_CFG, val, MTK_PPSC); + + dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider); + +@@ -1191,10 +1311,19 @@ static void mtk_tx_set_dma_desc_v2(struc + data |= TX_DMA_LS0; + WRITE_ONCE(desc->txd3, data); + +- if (mac->id == MTK_GMAC3_ID) +- data = PSE_GDM3_PORT; +- else +- data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */ ++ /* set forward port */ ++ switch (mac->id) { ++ case MTK_GMAC1_ID: ++ data = PSE_GDM1_PORT << TX_DMA_FPORT_SHIFT_V2; ++ break; ++ case MTK_GMAC2_ID: ++ data = PSE_GDM2_PORT << TX_DMA_FPORT_SHIFT_V2; ++ break; ++ case MTK_GMAC3_ID: ++ data = PSE_GDM3_PORT << TX_DMA_FPORT_SHIFT_V2; ++ break; ++ } ++ + data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid); + WRITE_ONCE(desc->txd4, data); + +@@ -4358,6 +4487,17 @@ static int mtk_add_mac(struct mtk_eth *e + mac->phylink_config.supported_interfaces); + } + ++ if (mtk_is_netsys_v3_or_greater(mac->hw) && ++ MTK_HAS_CAPS(mac->hw->soc->caps, MTK_ESW_BIT) && ++ id == MTK_GMAC1_ID) { ++ mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | ++ MAC_SYM_PAUSE | ++ MAC_10000FD; ++ phy_interface_zero(mac->phylink_config.supported_interfaces); ++ __set_bit(PHY_INTERFACE_MODE_INTERNAL, ++ mac->phylink_config.supported_interfaces); ++ } ++ + phylink = phylink_create(&mac->phylink_config, + of_fwnode_handle(mac->of_node), + phy_mode, &mtk_phylink_ops); +@@ -4878,6 +5018,24 @@ static const struct mtk_soc_data mt7986_ + }, + }; + ++static const struct mtk_soc_data mt7988_data = { ++ .reg_map = &mt7988_reg_map, ++ .ana_rgc3 = 0x128, ++ .caps = MT7988_CAPS, ++ .hw_features = MTK_HW_FEATURES, ++ .required_clks = MT7988_CLKS_BITMAP, ++ .required_pctl = false, ++ .version = 3, ++ .txrx = { ++ .txd_size = sizeof(struct mtk_tx_dma_v2), ++ .rxd_size = sizeof(struct mtk_rx_dma_v2), ++ .rx_irq_done_mask = MTK_RX_DONE_INT_V2, ++ .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, ++ .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, ++ .dma_len_offset = 8, ++ }, ++}; ++ + static const struct mtk_soc_data rt5350_data = { + .reg_map = &mt7628_reg_map, + .caps = MT7628_CAPS, +@@ -4896,14 +5054,15 @@ static const struct mtk_soc_data rt5350_ + }; + + const struct of_device_id of_mtk_match[] = { +- { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data}, +- { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data}, +- { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, +- { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, +- { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data}, +- { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data}, +- { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data}, +- { .compatible = "ralink,rt5350-eth", .data = &rt5350_data}, ++ { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data }, ++ { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data }, ++ { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data }, ++ { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data }, ++ { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data }, ++ { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data }, ++ { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data }, ++ { .compatible = "mediatek,mt7988-eth", .data = &mt7988_data }, ++ { .compatible = "ralink,rt5350-eth", .data = &rt5350_data }, + {}, + }; + MODULE_DEVICE_TABLE(of, of_mtk_match); +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -117,7 +117,8 @@ + #define MTK_CDMP_EG_CTRL 0x404 + + /* GDM Exgress Control Register */ +-#define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) ++#define MTK_GDMA_FWD_CFG(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \ ++ 0x540 : 0x500 + (_x * 0x1000); }) + #define MTK_GDMA_SPECIAL_TAG BIT(24) + #define MTK_GDMA_ICS_EN BIT(22) + #define MTK_GDMA_TCS_EN BIT(21) +@@ -126,6 +127,11 @@ + #define MTK_GDMA_TO_PDMA 0x0 + #define MTK_GDMA_DROP_ALL 0x7777 + ++/* GDM Egress Control Register */ ++#define MTK_GDMA_EG_CTRL(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \ ++ 0x544 : 0x504 + (_x * 0x1000); }) ++#define MTK_GDMA_XGDM_SEL BIT(31) ++ + /* Unicast Filter MAC Address Register - Low */ + #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) + +@@ -389,7 +395,26 @@ + #define PHY_IAC_TIMEOUT HZ + + #define MTK_MAC_MISC 0x1000c ++#define MTK_MAC_MISC_V3 0x10010 + #define MTK_MUX_TO_ESW BIT(0) ++#define MISC_MDC_TURBO BIT(4) ++ ++/* XMAC status registers */ ++#define MTK_XGMAC_STS(x) (((x) == MTK_GMAC3_ID) ? 0x1001C : 0x1000C) ++#define MTK_XGMAC_FORCE_LINK(x) (((x) == MTK_GMAC2_ID) ? BIT(31) : BIT(15)) ++#define MTK_USXGMII_PCS_LINK BIT(8) ++#define MTK_XGMAC_RX_FC BIT(5) ++#define MTK_XGMAC_TX_FC BIT(4) ++#define MTK_USXGMII_PCS_MODE GENMASK(3, 1) ++#define MTK_XGMAC_LINK_STS BIT(0) ++ ++/* GSW bridge registers */ ++#define MTK_GSW_CFG (0x10080) ++#define GSWTX_IPG_MASK GENMASK(19, 16) ++#define GSWTX_IPG_SHIFT 16 ++#define GSWRX_IPG_MASK GENMASK(3, 0) ++#define GSWRX_IPG_SHIFT 0 ++#define GSW_IPG_11 11 + + /* Mac control registers */ + #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) +@@ -647,6 +672,11 @@ enum mtk_clks_map { + MTK_CLK_GP0, + MTK_CLK_GP1, + MTK_CLK_GP2, ++ MTK_CLK_GP3, ++ MTK_CLK_XGP1, ++ MTK_CLK_XGP2, ++ MTK_CLK_XGP3, ++ MTK_CLK_CRYPTO, + MTK_CLK_FE, + MTK_CLK_TRGPLL, + MTK_CLK_SGMII_TX_250M, +@@ -663,6 +693,27 @@ enum mtk_clks_map { + MTK_CLK_WOCPU1, + MTK_CLK_NETSYS0, + MTK_CLK_NETSYS1, ++ MTK_CLK_ETHWARP_WOCPU2, ++ MTK_CLK_ETHWARP_WOCPU1, ++ MTK_CLK_ETHWARP_WOCPU0, ++ MTK_CLK_TOP_USXGMII_SBUS_0_SEL, ++ MTK_CLK_TOP_USXGMII_SBUS_1_SEL, ++ MTK_CLK_TOP_SGM_0_SEL, ++ MTK_CLK_TOP_SGM_1_SEL, ++ MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL, ++ MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL, ++ MTK_CLK_TOP_ETH_GMII_SEL, ++ MTK_CLK_TOP_ETH_REFCK_50M_SEL, ++ MTK_CLK_TOP_ETH_SYS_200M_SEL, ++ MTK_CLK_TOP_ETH_SYS_SEL, ++ MTK_CLK_TOP_ETH_XGMII_SEL, ++ MTK_CLK_TOP_ETH_MII_SEL, ++ MTK_CLK_TOP_NETSYS_SEL, ++ MTK_CLK_TOP_NETSYS_500M_SEL, ++ MTK_CLK_TOP_NETSYS_PAO_2X_SEL, ++ MTK_CLK_TOP_NETSYS_SYNC_250M_SEL, ++ MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL, ++ MTK_CLK_TOP_NETSYS_WARP_SEL, + MTK_CLK_MAX + }; + +@@ -716,6 +767,36 @@ enum mtk_clks_map { + BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ + BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ + BIT_ULL(MTK_CLK_SGMII2_CDR_FB)) ++#define MT7988_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_ESW) | \ ++ BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \ ++ BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \ ++ BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \ ++ BIT_ULL(MTK_CLK_CRYPTO) | \ ++ BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ ++ BIT_ULL(MTK_CLK_ETHWARP_WOCPU2) | \ ++ BIT_ULL(MTK_CLK_ETHWARP_WOCPU1) | \ ++ BIT_ULL(MTK_CLK_ETHWARP_WOCPU0) | \ ++ BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_0_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_1_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_SGM_0_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_SGM_1_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_ETH_SYS_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_ETH_XGMII_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_ETH_MII_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_NETSYS_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_NETSYS_500M_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_NETSYS_PAO_2X_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_NETSYS_SYNC_250M_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_NETSYS_WARP_SEL)) + + enum mtk_dev_state { + MTK_HW_INIT, +@@ -964,6 +1045,8 @@ enum mkt_eth_capabilities { + MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ + MTK_RSTCTRL_PPE1) + ++#define MT7988_CAPS (MTK_GDM1_ESW | MTK_QDMA | MTK_RSTCTRL_PPE1) ++ + struct mtk_tx_dma_desc_info { + dma_addr_t addr; + u32 size; +@@ -1309,6 +1392,7 @@ void mtk_stats_update_mac(struct mtk_mac + + void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); + u32 mtk_r32(struct mtk_eth *eth, unsigned reg); ++u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg); + + int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); + int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); diff --git a/target/linux/generic/backport-6.1/750-v6.5-12-net-ethernet-mtk_eth_soc-enable-page_pool-support-fo.patch b/target/linux/generic/backport-6.1/750-v6.5-12-net-ethernet-mtk_eth_soc-enable-page_pool-support-fo.patch new file mode 100644 index 00000000000..62c38c7137f --- /dev/null +++ b/target/linux/generic/backport-6.1/750-v6.5-12-net-ethernet-mtk_eth_soc-enable-page_pool-support-fo.patch @@ -0,0 +1,27 @@ +From 38a7eb76220731eff40602cf433f24880be0a6c2 Mon Sep 17 00:00:00 2001 +From: Lorenzo Bianconi +Date: Thu, 27 Jul 2023 09:02:26 +0200 +Subject: [PATCH 106/250] net: ethernet: mtk_eth_soc: enable page_pool support + for MT7988 SoC + +In order to recycle pages, enable page_pool allocator for MT7988 SoC. + +Tested-by: Daniel Golle +Signed-off-by: Lorenzo Bianconi +Link: https://lore.kernel.org/r/fd4e8693980e47385a543e7b002eec0b88bd09df.1690440675.git.lorenzo@kernel.org +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -1659,7 +1659,7 @@ static void mtk_update_rx_cpu_idx(struct + + static bool mtk_page_pool_enabled(struct mtk_eth *eth) + { +- return eth->soc->version == 2; ++ return mtk_is_netsys_v2_or_greater(eth); + } + + static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth, diff --git a/target/linux/generic/backport-6.1/750-v6.5-13-net-ethernet-mtk_eth_soc-enable-nft-hw-flowtable_off.patch b/target/linux/generic/backport-6.1/750-v6.5-13-net-ethernet-mtk_eth_soc-enable-nft-hw-flowtable_off.patch new file mode 100644 index 00000000000..49f4bd6a9d3 --- /dev/null +++ b/target/linux/generic/backport-6.1/750-v6.5-13-net-ethernet-mtk_eth_soc-enable-nft-hw-flowtable_off.patch @@ -0,0 +1,135 @@ +From 199e7d5a7f03dd377f3a7a458360dbedd71d50ba Mon Sep 17 00:00:00 2001 +From: Lorenzo Bianconi +Date: Thu, 27 Jul 2023 09:07:28 +0200 +Subject: [PATCH 107/250] net: ethernet: mtk_eth_soc: enable nft hw + flowtable_offload for MT7988 SoC + +Enable hw Packet Process Engine (PPE) for MT7988 SoC. + +Tested-by: Daniel Golle +Signed-off-by: Lorenzo Bianconi +Link: https://lore.kernel.org/r/5e86341b0220a49620dadc02d77970de5ded9efc.1690441576.git.lorenzo@kernel.org +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 3 +++ + drivers/net/ethernet/mediatek/mtk_ppe.c | 19 +++++++++++++++---- + drivers/net/ethernet/mediatek/mtk_ppe.h | 19 ++++++++++++++++++- + 3 files changed, 36 insertions(+), 5 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -5026,6 +5026,9 @@ static const struct mtk_soc_data mt7988_ + .required_clks = MT7988_CLKS_BITMAP, + .required_pctl = false, + .version = 3, ++ .offload_version = 2, ++ .hash_offset = 4, ++ .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma_v2), + .rxd_size = sizeof(struct mtk_rx_dma_v2), +--- a/drivers/net/ethernet/mediatek/mtk_ppe.c ++++ b/drivers/net/ethernet/mediatek/mtk_ppe.c +@@ -422,13 +422,22 @@ int mtk_foe_entry_set_wdma(struct mtk_et + struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(eth, entry); + u32 *ib2 = mtk_foe_entry_ib2(eth, entry); + +- if (mtk_is_netsys_v2_or_greater(eth)) { ++ switch (eth->soc->version) { ++ case 3: ++ *ib2 &= ~MTK_FOE_IB2_PORT_MG_V2; ++ *ib2 |= FIELD_PREP(MTK_FOE_IB2_RX_IDX, txq) | ++ MTK_FOE_IB2_WDMA_WINFO_V2; ++ l2->w3info = FIELD_PREP(MTK_FOE_WINFO_WCID_V3, wcid) | ++ FIELD_PREP(MTK_FOE_WINFO_BSS_V3, bss); ++ break; ++ case 2: + *ib2 &= ~MTK_FOE_IB2_PORT_MG_V2; + *ib2 |= FIELD_PREP(MTK_FOE_IB2_RX_IDX, txq) | + MTK_FOE_IB2_WDMA_WINFO_V2; + l2->winfo = FIELD_PREP(MTK_FOE_WINFO_WCID, wcid) | + FIELD_PREP(MTK_FOE_WINFO_BSS, bss); +- } else { ++ break; ++ default: + *ib2 &= ~MTK_FOE_IB2_PORT_MG; + *ib2 |= MTK_FOE_IB2_WDMA_WINFO; + if (wdma_idx) +@@ -436,6 +445,7 @@ int mtk_foe_entry_set_wdma(struct mtk_et + l2->vlan2 = FIELD_PREP(MTK_FOE_VLAN2_WINFO_BSS, bss) | + FIELD_PREP(MTK_FOE_VLAN2_WINFO_WCID, wcid) | + FIELD_PREP(MTK_FOE_VLAN2_WINFO_RING, txq); ++ break; + } + + return 0; +@@ -950,8 +960,7 @@ void mtk_ppe_start(struct mtk_ppe *ppe) + mtk_ppe_init_foe_table(ppe); + ppe_w32(ppe, MTK_PPE_TB_BASE, ppe->foe_phys); + +- val = MTK_PPE_TB_CFG_ENTRY_80B | +- MTK_PPE_TB_CFG_AGE_NON_L4 | ++ val = MTK_PPE_TB_CFG_AGE_NON_L4 | + MTK_PPE_TB_CFG_AGE_UNBIND | + MTK_PPE_TB_CFG_AGE_TCP | + MTK_PPE_TB_CFG_AGE_UDP | +@@ -967,6 +976,8 @@ void mtk_ppe_start(struct mtk_ppe *ppe) + MTK_PPE_ENTRIES_SHIFT); + if (mtk_is_netsys_v2_or_greater(ppe->eth)) + val |= MTK_PPE_TB_CFG_INFO_SEL; ++ if (!mtk_is_netsys_v3_or_greater(ppe->eth)) ++ val |= MTK_PPE_TB_CFG_ENTRY_80B; + ppe_w32(ppe, MTK_PPE_TB_CFG, val); + + ppe_w32(ppe, MTK_PPE_IP_PROTO_CHK, +--- a/drivers/net/ethernet/mediatek/mtk_ppe.h ++++ b/drivers/net/ethernet/mediatek/mtk_ppe.h +@@ -85,6 +85,17 @@ enum { + #define MTK_FOE_WINFO_BSS GENMASK(5, 0) + #define MTK_FOE_WINFO_WCID GENMASK(15, 6) + ++#define MTK_FOE_WINFO_BSS_V3 GENMASK(23, 16) ++#define MTK_FOE_WINFO_WCID_V3 GENMASK(15, 0) ++ ++#define MTK_FOE_WINFO_PAO_USR_INFO GENMASK(15, 0) ++#define MTK_FOE_WINFO_PAO_TID GENMASK(19, 16) ++#define MTK_FOE_WINFO_PAO_IS_FIXEDRATE BIT(20) ++#define MTK_FOE_WINFO_PAO_IS_PRIOR BIT(21) ++#define MTK_FOE_WINFO_PAO_IS_SP BIT(22) ++#define MTK_FOE_WINFO_PAO_HF BIT(23) ++#define MTK_FOE_WINFO_PAO_AMSDU_EN BIT(24) ++ + enum { + MTK_FOE_STATE_INVALID, + MTK_FOE_STATE_UNBIND, +@@ -106,8 +117,13 @@ struct mtk_foe_mac_info { + u16 pppoe_id; + u16 src_mac_lo; + ++ /* netsys_v2 */ + u16 minfo; + u16 winfo; ++ ++ /* netsys_v3 */ ++ u32 w3info; ++ u32 wpao; + }; + + /* software-only entry type */ +@@ -218,6 +234,7 @@ struct mtk_foe_ipv6_6rd { + + #define MTK_FOE_ENTRY_V1_SIZE 80 + #define MTK_FOE_ENTRY_V2_SIZE 96 ++#define MTK_FOE_ENTRY_V3_SIZE 128 + + struct mtk_foe_entry { + u32 ib1; +@@ -228,7 +245,7 @@ struct mtk_foe_entry { + struct mtk_foe_ipv4_dslite dslite; + struct mtk_foe_ipv6 ipv6; + struct mtk_foe_ipv6_6rd ipv6_6rd; +- u32 data[23]; ++ u32 data[31]; + }; + }; + diff --git a/target/linux/generic/backport-6.1/750-v6.5-14-net-ethernet-mtk_eth_soc-support-per-flow-accounting.patch b/target/linux/generic/backport-6.1/750-v6.5-14-net-ethernet-mtk_eth_soc-support-per-flow-accounting.patch new file mode 100644 index 00000000000..88987d7bc94 --- /dev/null +++ b/target/linux/generic/backport-6.1/750-v6.5-14-net-ethernet-mtk_eth_soc-support-per-flow-accounting.patch @@ -0,0 +1,78 @@ +From 0c024632c1e7ff69914329bfd87bec749b9c0aed Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Wed, 2 Aug 2023 04:31:09 +0100 +Subject: [PATCH 108/250] net: ethernet: mtk_eth_soc: support per-flow + accounting on MT7988 + +NETSYS_V3 uses 64 bits for each counters while older SoCs are using +48/40 bits for each counter. +Support reading per-flow byte and package counters on NETSYS_V3. + +Signed-off-by: Daniel Golle +Reviewed-by: Simon Horman +Link: https://lore.kernel.org/r/37a0928fa8c1253b197884c68ce1f54239421ac5.1690946442.git.daniel@makrotopia.org +Signed-off-by: Paolo Abeni +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 1 + + drivers/net/ethernet/mediatek/mtk_ppe.c | 21 +++++++++++++------- + drivers/net/ethernet/mediatek/mtk_ppe_regs.h | 2 ++ + 3 files changed, 17 insertions(+), 7 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -5028,6 +5028,7 @@ static const struct mtk_soc_data mt7988_ + .version = 3, + .offload_version = 2, + .hash_offset = 4, ++ .has_accounting = true, + .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma_v2), +--- a/drivers/net/ethernet/mediatek/mtk_ppe.c ++++ b/drivers/net/ethernet/mediatek/mtk_ppe.c +@@ -91,7 +91,6 @@ static int mtk_ppe_mib_wait_busy(struct + + static int mtk_mib_entry_read(struct mtk_ppe *ppe, u16 index, u64 *bytes, u64 *packets) + { +- u32 byte_cnt_low, byte_cnt_high, pkt_cnt_low, pkt_cnt_high; + u32 val, cnt_r0, cnt_r1, cnt_r2; + int ret; + +@@ -106,12 +105,20 @@ static int mtk_mib_entry_read(struct mtk + cnt_r1 = readl(ppe->base + MTK_PPE_MIB_SER_R1); + cnt_r2 = readl(ppe->base + MTK_PPE_MIB_SER_R2); + +- byte_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R0_BYTE_CNT_LOW, cnt_r0); +- byte_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH, cnt_r1); +- pkt_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R1_PKT_CNT_LOW, cnt_r1); +- pkt_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH, cnt_r2); +- *bytes = ((u64)byte_cnt_high << 32) | byte_cnt_low; +- *packets = (pkt_cnt_high << 16) | pkt_cnt_low; ++ if (mtk_is_netsys_v3_or_greater(ppe->eth)) { ++ /* 64 bit for each counter */ ++ u32 cnt_r3 = readl(ppe->base + MTK_PPE_MIB_SER_R3); ++ *bytes = ((u64)cnt_r1 << 32) | cnt_r0; ++ *packets = ((u64)cnt_r3 << 32) | cnt_r2; ++ } else { ++ /* 48 bit byte counter, 40 bit packet counter */ ++ u32 byte_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R0_BYTE_CNT_LOW, cnt_r0); ++ u32 byte_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH, cnt_r1); ++ u32 pkt_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R1_PKT_CNT_LOW, cnt_r1); ++ u32 pkt_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH, cnt_r2); ++ *bytes = ((u64)byte_cnt_high << 32) | byte_cnt_low; ++ *packets = (pkt_cnt_high << 16) | pkt_cnt_low; ++ } + + return 0; + } +--- a/drivers/net/ethernet/mediatek/mtk_ppe_regs.h ++++ b/drivers/net/ethernet/mediatek/mtk_ppe_regs.h +@@ -163,6 +163,8 @@ enum { + #define MTK_PPE_MIB_SER_R2 0x348 + #define MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH GENMASK(23, 0) + ++#define MTK_PPE_MIB_SER_R3 0x34c ++ + #define MTK_PPE_MIB_CACHE_CTL 0x350 + #define MTK_PPE_MIB_CACHE_CTL_EN BIT(0) + #define MTK_PPE_MIB_CACHE_CTL_FLUSH BIT(2) diff --git a/target/linux/generic/backport-6.1/750-v6.5-15-net-ethernet-mtk_eth_soc-fix-NULL-pointer-on-hw-rese.patch b/target/linux/generic/backport-6.1/750-v6.5-15-net-ethernet-mtk_eth_soc-fix-NULL-pointer-on-hw-rese.patch new file mode 100644 index 00000000000..6f1639a5720 --- /dev/null +++ b/target/linux/generic/backport-6.1/750-v6.5-15-net-ethernet-mtk_eth_soc-fix-NULL-pointer-on-hw-rese.patch @@ -0,0 +1,52 @@ +From 3b12f42772c26869d60398c1710aa27b27cd945c Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Mon, 21 Aug 2023 17:12:44 +0100 +Subject: [PATCH 109/250] net: ethernet: mtk_eth_soc: fix NULL pointer on hw + reset + +When a hardware reset is triggered on devices not initializing WED the +calls to mtk_wed_fe_reset and mtk_wed_fe_reset_complete dereference a +pointer on uninitialized stack memory. +Break out of both functions in case a hw_list entry is 0. + +Fixes: 08a764a7c51b ("net: ethernet: mtk_wed: add reset/reset_complete callbacks") +Signed-off-by: Daniel Golle +Reviewed-by: Simon Horman +Acked-by: Lorenzo Bianconi +Link: https://lore.kernel.org/r/5465c1609b464cc7407ae1530c40821dcdf9d3e6.1692634266.git.daniel@makrotopia.org +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_wed.c | 12 ++++++++++-- + 1 file changed, 10 insertions(+), 2 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_wed.c ++++ b/drivers/net/ethernet/mediatek/mtk_wed.c +@@ -214,9 +214,13 @@ void mtk_wed_fe_reset(void) + + for (i = 0; i < ARRAY_SIZE(hw_list); i++) { + struct mtk_wed_hw *hw = hw_list[i]; +- struct mtk_wed_device *dev = hw->wed_dev; ++ struct mtk_wed_device *dev; + int err; + ++ if (!hw) ++ break; ++ ++ dev = hw->wed_dev; + if (!dev || !dev->wlan.reset) + continue; + +@@ -237,8 +241,12 @@ void mtk_wed_fe_reset_complete(void) + + for (i = 0; i < ARRAY_SIZE(hw_list); i++) { + struct mtk_wed_hw *hw = hw_list[i]; +- struct mtk_wed_device *dev = hw->wed_dev; ++ struct mtk_wed_device *dev; ++ ++ if (!hw) ++ break; + ++ dev = hw->wed_dev; + if (!dev || !dev->wlan.reset_complete) + continue; + diff --git a/target/linux/generic/backport-6.1/750-v6.5-16-net-ethernet-mtk_eth_soc-fix-register-definitions-fo.patch b/target/linux/generic/backport-6.1/750-v6.5-16-net-ethernet-mtk_eth_soc-fix-register-definitions-fo.patch new file mode 100644 index 00000000000..2190761fdd4 --- /dev/null +++ b/target/linux/generic/backport-6.1/750-v6.5-16-net-ethernet-mtk_eth_soc-fix-register-definitions-fo.patch @@ -0,0 +1,44 @@ +From 489aea123d74a846ce746bfdb3efe1e7ad512e0d Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Tue, 22 Aug 2023 17:31:24 +0100 +Subject: [PATCH 110/250] net: ethernet: mtk_eth_soc: fix register definitions + for MT7988 + +More register macros need to be adjusted for the 3rd GMAC on MT7988. +Account for added bit in SYSCFG0_SGMII_MASK. + +Fixes: 445eb6448ed3 ("net: ethernet: mtk_eth_soc: add basic support for MT7988 SoC") +Signed-off-by: Daniel Golle +Reviewed-by: Simon Horman +Link: https://lore.kernel.org/r/1c8da012e2ca80939906d85f314138c552139f0f.1692721443.git.daniel@makrotopia.org +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -133,10 +133,12 @@ + #define MTK_GDMA_XGDM_SEL BIT(31) + + /* Unicast Filter MAC Address Register - Low */ +-#define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) ++#define MTK_GDMA_MAC_ADRL(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \ ++ 0x548 : 0x508 + (_x * 0x1000); }) + + /* Unicast Filter MAC Address Register - High */ +-#define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) ++#define MTK_GDMA_MAC_ADRH(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \ ++ 0x54C : 0x50C + (_x * 0x1000); }) + + /* FE global misc reg*/ + #define MTK_FE_GLO_MISC 0x124 +@@ -503,7 +505,7 @@ + #define ETHSYS_SYSCFG0 0x14 + #define SYSCFG0_GE_MASK 0x3 + #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) +-#define SYSCFG0_SGMII_MASK GENMASK(9, 8) ++#define SYSCFG0_SGMII_MASK GENMASK(9, 7) + #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK) + #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) + #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) diff --git a/target/linux/generic/backport-6.1/750-v6.5-17-net-ethernet-mtk_eth_soc-add-reset-bits-for-MT7988.patch b/target/linux/generic/backport-6.1/750-v6.5-17-net-ethernet-mtk_eth_soc-add-reset-bits-for-MT7988.patch new file mode 100644 index 00000000000..b94ca7ebc5a --- /dev/null +++ b/target/linux/generic/backport-6.1/750-v6.5-17-net-ethernet-mtk_eth_soc-add-reset-bits-for-MT7988.patch @@ -0,0 +1,188 @@ +From 15a84d1c44ae8c1451c265ee60500588a24e8cd6 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Tue, 22 Aug 2023 17:32:03 +0100 +Subject: [PATCH 111/250] net: ethernet: mtk_eth_soc: add reset bits for MT7988 + +Add bits needed to reset the frame engine on MT7988. + +Fixes: 445eb6448ed3 ("net: ethernet: mtk_eth_soc: add basic support for MT7988 SoC") +Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/89b6c38380e7a3800c1362aa7575600717bc7543.1692721443.git.daniel@makrotopia.org +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 76 +++++++++++++++------ + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 16 +++-- + 2 files changed, 68 insertions(+), 24 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -3592,19 +3592,34 @@ static void mtk_hw_reset(struct mtk_eth + { + u32 val; + +- if (mtk_is_netsys_v2_or_greater(eth)) { ++ if (mtk_is_netsys_v2_or_greater(eth)) + regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); ++ ++ if (mtk_is_netsys_v3_or_greater(eth)) { ++ val = RSTCTRL_PPE0_V3; ++ ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) ++ val |= RSTCTRL_PPE1_V3; ++ ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) ++ val |= RSTCTRL_PPE2; ++ ++ val |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2; ++ } else if (mtk_is_netsys_v2_or_greater(eth)) { + val = RSTCTRL_PPE0_V2; ++ ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) ++ val |= RSTCTRL_PPE1; + } else { + val = RSTCTRL_PPE0; + } + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) +- val |= RSTCTRL_PPE1; +- + ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val); + +- if (mtk_is_netsys_v2_or_greater(eth)) ++ if (mtk_is_netsys_v3_or_greater(eth)) ++ regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, ++ 0x6f8ff); ++ else if (mtk_is_netsys_v2_or_greater(eth)) + regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, + 0x3ffffff); + } +@@ -3630,13 +3645,21 @@ static void mtk_hw_warm_reset(struct mtk + return; + } + +- if (mtk_is_netsys_v2_or_greater(eth)) ++ if (mtk_is_netsys_v3_or_greater(eth)) { ++ rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V3; ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) ++ rst_mask |= RSTCTRL_PPE1_V3; ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) ++ rst_mask |= RSTCTRL_PPE2; ++ ++ rst_mask |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2; ++ } else if (mtk_is_netsys_v2_or_greater(eth)) { + rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2; +- else ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) ++ rst_mask |= RSTCTRL_PPE1; ++ } else { + rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0; +- +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) +- rst_mask |= RSTCTRL_PPE1; ++ } + + regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, rst_mask); + +@@ -3988,11 +4011,17 @@ static void mtk_prepare_for_reset(struct + u32 val; + int i; + +- /* disabe FE P3 and P4 */ +- val = mtk_r32(eth, MTK_FE_GLO_CFG) | MTK_FE_LINK_DOWN_P3; +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) +- val |= MTK_FE_LINK_DOWN_P4; +- mtk_w32(eth, val, MTK_FE_GLO_CFG); ++ /* set FE PPE ports link down */ ++ for (i = MTK_GMAC1_ID; ++ i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID); ++ i += 2) { ++ val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) | MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT); ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) ++ val |= MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT); ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) ++ val |= MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT); ++ mtk_w32(eth, val, MTK_FE_GLO_CFG(i)); ++ } + + /* adjust PPE configurations to prepare for reset */ + for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) +@@ -4053,11 +4082,18 @@ static void mtk_pending_work(struct work + } + } + +- /* enabe FE P3 and P4 */ +- val = mtk_r32(eth, MTK_FE_GLO_CFG) & ~MTK_FE_LINK_DOWN_P3; +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) +- val &= ~MTK_FE_LINK_DOWN_P4; +- mtk_w32(eth, val, MTK_FE_GLO_CFG); ++ /* set FE PPE ports link up */ ++ for (i = MTK_GMAC1_ID; ++ i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID); ++ i += 2) { ++ val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) & ~MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT); ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) ++ val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT); ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) ++ val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT); ++ ++ mtk_w32(eth, val, MTK_FE_GLO_CFG(i)); ++ } + + clear_bit(MTK_RESETTING, ð->state); + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -76,9 +76,8 @@ + #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 + + /* Frame Engine Global Configuration */ +-#define MTK_FE_GLO_CFG 0x00 +-#define MTK_FE_LINK_DOWN_P3 BIT(11) +-#define MTK_FE_LINK_DOWN_P4 BIT(12) ++#define MTK_FE_GLO_CFG(x) (((x) == MTK_GMAC3_ID) ? 0x24 : 0x00) ++#define MTK_FE_LINK_DOWN_P(x) BIT(((x) + 8) % 16) + + /* Frame Engine Global Reset Register */ + #define MTK_RST_GL 0x04 +@@ -522,9 +521,15 @@ + /* ethernet reset control register */ + #define ETHSYS_RSTCTRL 0x34 + #define RSTCTRL_FE BIT(6) ++#define RSTCTRL_WDMA0 BIT(24) ++#define RSTCTRL_WDMA1 BIT(25) ++#define RSTCTRL_WDMA2 BIT(26) + #define RSTCTRL_PPE0 BIT(31) + #define RSTCTRL_PPE0_V2 BIT(30) + #define RSTCTRL_PPE1 BIT(31) ++#define RSTCTRL_PPE0_V3 BIT(29) ++#define RSTCTRL_PPE1_V3 BIT(30) ++#define RSTCTRL_PPE2 BIT(31) + #define RSTCTRL_ETH BIT(23) + + /* ethernet reset check idle register */ +@@ -931,6 +936,7 @@ enum mkt_eth_capabilities { + MTK_QDMA_BIT, + MTK_SOC_MT7628_BIT, + MTK_RSTCTRL_PPE1_BIT, ++ MTK_RSTCTRL_PPE2_BIT, + MTK_U3_COPHY_V2_BIT, + + /* MUX BITS*/ +@@ -965,6 +971,7 @@ enum mkt_eth_capabilities { + #define MTK_QDMA BIT_ULL(MTK_QDMA_BIT) + #define MTK_SOC_MT7628 BIT_ULL(MTK_SOC_MT7628_BIT) + #define MTK_RSTCTRL_PPE1 BIT_ULL(MTK_RSTCTRL_PPE1_BIT) ++#define MTK_RSTCTRL_PPE2 BIT_ULL(MTK_RSTCTRL_PPE2_BIT) + #define MTK_U3_COPHY_V2 BIT_ULL(MTK_U3_COPHY_V2_BIT) + + #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ +@@ -1047,7 +1054,8 @@ enum mkt_eth_capabilities { + MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ + MTK_RSTCTRL_PPE1) + +-#define MT7988_CAPS (MTK_GDM1_ESW | MTK_QDMA | MTK_RSTCTRL_PPE1) ++#define MT7988_CAPS (MTK_GDM1_ESW | MTK_QDMA | MTK_RSTCTRL_PPE1 | \ ++ MTK_RSTCTRL_PPE2) + + struct mtk_tx_dma_desc_info { + dma_addr_t addr; diff --git a/target/linux/generic/backport-6.1/750-v6.5-18-net-ethernet-mtk_eth_soc-add-support-for-in-SoC-SRAM.patch b/target/linux/generic/backport-6.1/750-v6.5-18-net-ethernet-mtk_eth_soc-add-support-for-in-SoC-SRAM.patch new file mode 100644 index 00000000000..43fbffc51b8 --- /dev/null +++ b/target/linux/generic/backport-6.1/750-v6.5-18-net-ethernet-mtk_eth_soc-add-support-for-in-SoC-SRAM.patch @@ -0,0 +1,254 @@ +From 25ce45fe40b574e5d7ffa407f7f2db03e7d5a910 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Tue, 22 Aug 2023 17:32:54 +0100 +Subject: [PATCH 112/250] net: ethernet: mtk_eth_soc: add support for in-SoC + SRAM + +MT7981, MT7986 and MT7988 come with in-SoC SRAM dedicated for Ethernet +DMA rings. Support using the SRAM without breaking existing device tree +bindings, ie. only new SoC starting from MT7988 will have the SRAM +declared as additional resource in device tree. For MT7981 and MT7986 +an offset on top of the main I/O base is used. + +Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/e45e0f230c63ad58869e8fe35b95a2fb8925b625.1692721443.git.daniel@makrotopia.org +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 88 ++++++++++++++++----- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 12 ++- + 2 files changed, 78 insertions(+), 22 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -1119,10 +1119,13 @@ static int mtk_init_fq_dma(struct mtk_et + dma_addr_t dma_addr; + int i; + +- eth->scratch_ring = dma_alloc_coherent(eth->dma_dev, +- cnt * soc->txrx.txd_size, +- ð->phy_scratch_ring, +- GFP_KERNEL); ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) ++ eth->scratch_ring = eth->sram_base; ++ else ++ eth->scratch_ring = dma_alloc_coherent(eth->dma_dev, ++ cnt * soc->txrx.txd_size, ++ ð->phy_scratch_ring, ++ GFP_KERNEL); + if (unlikely(!eth->scratch_ring)) + return -ENOMEM; + +@@ -2430,8 +2433,14 @@ static int mtk_tx_alloc(struct mtk_eth * + if (!ring->buf) + goto no_tx_mem; + +- ring->dma = dma_alloc_coherent(eth->dma_dev, ring_size * sz, +- &ring->phys, GFP_KERNEL); ++ if (MTK_HAS_CAPS(soc->caps, MTK_SRAM)) { ++ ring->dma = eth->sram_base + ring_size * sz; ++ ring->phys = eth->phy_scratch_ring + ring_size * (dma_addr_t)sz; ++ } else { ++ ring->dma = dma_alloc_coherent(eth->dma_dev, ring_size * sz, ++ &ring->phys, GFP_KERNEL); ++ } ++ + if (!ring->dma) + goto no_tx_mem; + +@@ -2530,8 +2539,7 @@ static void mtk_tx_clean(struct mtk_eth + kfree(ring->buf); + ring->buf = NULL; + } +- +- if (ring->dma) { ++ if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && ring->dma) { + dma_free_coherent(eth->dma_dev, + ring->dma_size * soc->txrx.txd_size, + ring->dma, ring->phys); +@@ -2550,9 +2558,14 @@ static int mtk_rx_alloc(struct mtk_eth * + { + const struct mtk_reg_map *reg_map = eth->soc->reg_map; + struct mtk_rx_ring *ring; +- int rx_data_len, rx_dma_size; ++ int rx_data_len, rx_dma_size, tx_ring_size; + int i; + ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) ++ tx_ring_size = MTK_QDMA_RING_SIZE; ++ else ++ tx_ring_size = MTK_DMA_SIZE; ++ + if (rx_flag == MTK_RX_FLAGS_QDMA) { + if (ring_no) + return -EINVAL; +@@ -2587,9 +2600,20 @@ static int mtk_rx_alloc(struct mtk_eth * + ring->page_pool = pp; + } + +- ring->dma = dma_alloc_coherent(eth->dma_dev, +- rx_dma_size * eth->soc->txrx.rxd_size, +- &ring->phys, GFP_KERNEL); ++ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM) || ++ rx_flag != MTK_RX_FLAGS_NORMAL) { ++ ring->dma = dma_alloc_coherent(eth->dma_dev, ++ rx_dma_size * eth->soc->txrx.rxd_size, ++ &ring->phys, GFP_KERNEL); ++ } else { ++ struct mtk_tx_ring *tx_ring = ð->tx_ring; ++ ++ ring->dma = tx_ring->dma + tx_ring_size * ++ eth->soc->txrx.txd_size * (ring_no + 1); ++ ring->phys = tx_ring->phys + tx_ring_size * ++ eth->soc->txrx.txd_size * (ring_no + 1); ++ } ++ + if (!ring->dma) + return -ENOMEM; + +@@ -2674,7 +2698,7 @@ static int mtk_rx_alloc(struct mtk_eth * + return 0; + } + +-static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring) ++static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring, bool in_sram) + { + int i; + +@@ -2697,7 +2721,7 @@ static void mtk_rx_clean(struct mtk_eth + ring->data = NULL; + } + +- if (ring->dma) { ++ if (!in_sram && ring->dma) { + dma_free_coherent(eth->dma_dev, + ring->dma_size * eth->soc->txrx.rxd_size, + ring->dma, ring->phys); +@@ -3057,7 +3081,7 @@ static void mtk_dma_free(struct mtk_eth + for (i = 0; i < MTK_MAX_DEVS; i++) + if (eth->netdev[i]) + netdev_reset_queue(eth->netdev[i]); +- if (eth->scratch_ring) { ++ if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) { + dma_free_coherent(eth->dma_dev, + MTK_QDMA_RING_SIZE * soc->txrx.txd_size, + eth->scratch_ring, eth->phy_scratch_ring); +@@ -3065,13 +3089,13 @@ static void mtk_dma_free(struct mtk_eth + eth->phy_scratch_ring = 0; + } + mtk_tx_clean(eth); +- mtk_rx_clean(eth, ð->rx_ring[0]); +- mtk_rx_clean(eth, ð->rx_ring_qdma); ++ mtk_rx_clean(eth, ð->rx_ring[0], MTK_HAS_CAPS(soc->caps, MTK_SRAM)); ++ mtk_rx_clean(eth, ð->rx_ring_qdma, false); + + if (eth->hwlro) { + mtk_hwlro_rx_uninit(eth); + for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) +- mtk_rx_clean(eth, ð->rx_ring[i]); ++ mtk_rx_clean(eth, ð->rx_ring[i], false); + } + + kfree(eth->scratch_head); +@@ -4639,7 +4663,7 @@ static int mtk_sgmii_init(struct mtk_eth + + static int mtk_probe(struct platform_device *pdev) + { +- struct resource *res = NULL; ++ struct resource *res = NULL, *res_sram; + struct device_node *mac_np; + struct mtk_eth *eth; + int err, i; +@@ -4659,6 +4683,20 @@ static int mtk_probe(struct platform_dev + if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) + eth->ip_align = NET_IP_ALIGN; + ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) { ++ /* SRAM is actual memory and supports transparent access just like DRAM. ++ * Hence we don't require __iomem being set and don't need to use accessor ++ * functions to read from or write to SRAM. ++ */ ++ if (mtk_is_netsys_v3_or_greater(eth)) { ++ eth->sram_base = (void __force *)devm_platform_ioremap_resource(pdev, 1); ++ if (IS_ERR(eth->sram_base)) ++ return PTR_ERR(eth->sram_base); ++ } else { ++ eth->sram_base = (void __force *)eth->base + MTK_ETH_SRAM_OFFSET; ++ } ++ } ++ + spin_lock_init(ð->page_lock); + spin_lock_init(ð->tx_irq_lock); + spin_lock_init(ð->rx_irq_lock); +@@ -4722,6 +4760,18 @@ static int mtk_probe(struct platform_dev + err = -EINVAL; + goto err_destroy_sgmii; + } ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) { ++ if (mtk_is_netsys_v3_or_greater(eth)) { ++ res_sram = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ if (!res_sram) { ++ err = -EINVAL; ++ goto err_destroy_sgmii; ++ } ++ eth->phy_scratch_ring = res_sram->start; ++ } else { ++ eth->phy_scratch_ring = res->start + MTK_ETH_SRAM_OFFSET; ++ } ++ } + } + + if (eth->soc->offload_version) { +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -139,6 +139,9 @@ + #define MTK_GDMA_MAC_ADRH(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \ + 0x54C : 0x50C + (_x * 0x1000); }) + ++/* Internal SRAM offset */ ++#define MTK_ETH_SRAM_OFFSET 0x40000 ++ + /* FE global misc reg*/ + #define MTK_FE_GLO_MISC 0x124 + +@@ -938,6 +941,7 @@ enum mkt_eth_capabilities { + MTK_RSTCTRL_PPE1_BIT, + MTK_RSTCTRL_PPE2_BIT, + MTK_U3_COPHY_V2_BIT, ++ MTK_SRAM_BIT, + + /* MUX BITS*/ + MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, +@@ -973,6 +977,7 @@ enum mkt_eth_capabilities { + #define MTK_RSTCTRL_PPE1 BIT_ULL(MTK_RSTCTRL_PPE1_BIT) + #define MTK_RSTCTRL_PPE2 BIT_ULL(MTK_RSTCTRL_PPE2_BIT) + #define MTK_U3_COPHY_V2 BIT_ULL(MTK_U3_COPHY_V2_BIT) ++#define MTK_SRAM BIT_ULL(MTK_SRAM_BIT) + + #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ + BIT_ULL(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) +@@ -1048,14 +1053,14 @@ enum mkt_eth_capabilities { + #define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ + MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ + MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \ +- MTK_RSTCTRL_PPE1) ++ MTK_RSTCTRL_PPE1 | MTK_SRAM) + + #define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ + MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ +- MTK_RSTCTRL_PPE1) ++ MTK_RSTCTRL_PPE1 | MTK_SRAM) + + #define MT7988_CAPS (MTK_GDM1_ESW | MTK_QDMA | MTK_RSTCTRL_PPE1 | \ +- MTK_RSTCTRL_PPE2) ++ MTK_RSTCTRL_PPE2 | MTK_SRAM) + + struct mtk_tx_dma_desc_info { + dma_addr_t addr; +@@ -1215,6 +1220,7 @@ struct mtk_eth { + struct device *dev; + struct device *dma_dev; + void __iomem *base; ++ void *sram_base; + spinlock_t page_lock; + spinlock_t tx_irq_lock; + spinlock_t rx_irq_lock; diff --git a/target/linux/generic/backport-6.1/750-v6.5-19-net-ethernet-mtk_eth_soc-support-36-bit-DMA-addressi.patch b/target/linux/generic/backport-6.1/750-v6.5-19-net-ethernet-mtk_eth_soc-support-36-bit-DMA-addressi.patch new file mode 100644 index 00000000000..3933997003a --- /dev/null +++ b/target/linux/generic/backport-6.1/750-v6.5-19-net-ethernet-mtk_eth_soc-support-36-bit-DMA-addressi.patch @@ -0,0 +1,166 @@ +From 0b0d606eb9650fa01dd5621e072aa29a10544399 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Tue, 22 Aug 2023 17:33:12 +0100 +Subject: [PATCH 113/250] net: ethernet: mtk_eth_soc: support 36-bit DMA + addressing on MT7988 + +Systems having 4 GiB of RAM and more require DMA addressing beyond the +current 32-bit limit. Starting from MT7988 the hardware now supports +36-bit DMA addressing, let's use that new capability in the driver to +avoid running into swiotlb on systems with 4 GiB of RAM or more. + +Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/95b919c98876c9e49761e44662e7c937479eecb8.1692721443.git.daniel@makrotopia.org +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 30 +++++++++++++++++++-- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 22 +++++++++++++-- + 2 files changed, 48 insertions(+), 4 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -1312,6 +1312,10 @@ static void mtk_tx_set_dma_desc_v2(struc + data = TX_DMA_PLEN0(info->size); + if (info->last) + data |= TX_DMA_LS0; ++ ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) ++ data |= TX_DMA_PREP_ADDR64(info->addr); ++ + WRITE_ONCE(desc->txd3, data); + + /* set forward port */ +@@ -1981,6 +1985,7 @@ static int mtk_poll_rx(struct napi_struc + bool xdp_flush = false; + int idx; + struct sk_buff *skb; ++ u64 addr64 = 0; + u8 *data, *new_data; + struct mtk_rx_dma_v2 *rxd, trxd; + int done = 0, bytes = 0; +@@ -2096,7 +2101,10 @@ static int mtk_poll_rx(struct napi_struc + goto release_desc; + } + +- dma_unmap_single(eth->dma_dev, trxd.rxd1, ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) ++ addr64 = RX_DMA_GET_ADDR64(trxd.rxd2); ++ ++ dma_unmap_single(eth->dma_dev, ((u64)trxd.rxd1 | addr64), + ring->buf_size, DMA_FROM_DEVICE); + + skb = build_skb(data, ring->frag_size); +@@ -2162,6 +2170,9 @@ release_desc: + else + rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); + ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) ++ rxd->rxd2 |= RX_DMA_PREP_ADDR64(dma_addr); ++ + ring->calc_idx = idx; + done++; + } +@@ -2654,6 +2665,9 @@ static int mtk_rx_alloc(struct mtk_eth * + else + rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); + ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) ++ rxd->rxd2 |= RX_DMA_PREP_ADDR64(dma_addr); ++ + rxd->rxd3 = 0; + rxd->rxd4 = 0; + if (mtk_is_netsys_v2_or_greater(eth)) { +@@ -2700,6 +2714,7 @@ static int mtk_rx_alloc(struct mtk_eth * + + static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring, bool in_sram) + { ++ u64 addr64 = 0; + int i; + + if (ring->data && ring->dma) { +@@ -2713,7 +2728,10 @@ static void mtk_rx_clean(struct mtk_eth + if (!rxd->rxd1) + continue; + +- dma_unmap_single(eth->dma_dev, rxd->rxd1, ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) ++ addr64 = RX_DMA_GET_ADDR64(rxd->rxd2); ++ ++ dma_unmap_single(eth->dma_dev, ((u64)rxd->rxd1 | addr64), + ring->buf_size, DMA_FROM_DEVICE); + mtk_rx_put_buff(ring, ring->data[i], false); + } +@@ -4697,6 +4715,14 @@ static int mtk_probe(struct platform_dev + } + } + ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) { ++ err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(36)); ++ if (err) { ++ dev_err(&pdev->dev, "Wrong DMA config\n"); ++ return -EINVAL; ++ } ++ } ++ + spin_lock_init(ð->page_lock); + spin_lock_init(ð->tx_irq_lock); + spin_lock_init(ð->rx_irq_lock); +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -331,6 +331,14 @@ + #define TX_DMA_PLEN1(x) ((x) & eth->soc->txrx.dma_max_len) + #define TX_DMA_SWC BIT(14) + #define TX_DMA_PQID GENMASK(3, 0) ++#define TX_DMA_ADDR64_MASK GENMASK(3, 0) ++#if IS_ENABLED(CONFIG_64BIT) ++# define TX_DMA_GET_ADDR64(x) (((u64)FIELD_GET(TX_DMA_ADDR64_MASK, (x))) << 32) ++# define TX_DMA_PREP_ADDR64(x) FIELD_PREP(TX_DMA_ADDR64_MASK, ((x) >> 32)) ++#else ++# define TX_DMA_GET_ADDR64(x) (0) ++# define TX_DMA_PREP_ADDR64(x) (0) ++#endif + + /* PDMA on MT7628 */ + #define TX_DMA_DONE BIT(31) +@@ -343,6 +351,14 @@ + #define RX_DMA_PREP_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset) + #define RX_DMA_GET_PLEN0(x) (((x) >> eth->soc->txrx.dma_len_offset) & eth->soc->txrx.dma_max_len) + #define RX_DMA_VTAG BIT(15) ++#define RX_DMA_ADDR64_MASK GENMASK(3, 0) ++#if IS_ENABLED(CONFIG_64BIT) ++# define RX_DMA_GET_ADDR64(x) (((u64)FIELD_GET(RX_DMA_ADDR64_MASK, (x))) << 32) ++# define RX_DMA_PREP_ADDR64(x) FIELD_PREP(RX_DMA_ADDR64_MASK, ((x) >> 32)) ++#else ++# define RX_DMA_GET_ADDR64(x) (0) ++# define RX_DMA_PREP_ADDR64(x) (0) ++#endif + + /* QDMA descriptor rxd3 */ + #define RX_DMA_VID(x) ((x) & VLAN_VID_MASK) +@@ -942,6 +958,7 @@ enum mkt_eth_capabilities { + MTK_RSTCTRL_PPE2_BIT, + MTK_U3_COPHY_V2_BIT, + MTK_SRAM_BIT, ++ MTK_36BIT_DMA_BIT, + + /* MUX BITS*/ + MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, +@@ -978,6 +995,7 @@ enum mkt_eth_capabilities { + #define MTK_RSTCTRL_PPE2 BIT_ULL(MTK_RSTCTRL_PPE2_BIT) + #define MTK_U3_COPHY_V2 BIT_ULL(MTK_U3_COPHY_V2_BIT) + #define MTK_SRAM BIT_ULL(MTK_SRAM_BIT) ++#define MTK_36BIT_DMA BIT_ULL(MTK_36BIT_DMA_BIT) + + #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ + BIT_ULL(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) +@@ -1059,8 +1077,8 @@ enum mkt_eth_capabilities { + MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ + MTK_RSTCTRL_PPE1 | MTK_SRAM) + +-#define MT7988_CAPS (MTK_GDM1_ESW | MTK_QDMA | MTK_RSTCTRL_PPE1 | \ +- MTK_RSTCTRL_PPE2 | MTK_SRAM) ++#define MT7988_CAPS (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_QDMA | \ ++ MTK_RSTCTRL_PPE1 | MTK_RSTCTRL_PPE2 | MTK_SRAM) + + struct mtk_tx_dma_desc_info { + dma_addr_t addr; diff --git a/target/linux/generic/backport-6.1/790-v6.4-0012-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch b/target/linux/generic/backport-6.1/790-v6.4-0012-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch index 4dac4464fee..abe6bbb04c4 100644 --- a/target/linux/generic/backport-6.1/790-v6.4-0012-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch +++ b/target/linux/generic/backport-6.1/790-v6.4-0012-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch @@ -21,9 +21,9 @@ Signed-off-by: David S. Miller drivers/net/dsa/Kconfig | 12 +++ drivers/net/dsa/Makefile | 1 + drivers/net/dsa/mt7530-mmio.c | 101 +++++++++++++++++++++++++ - drivers/net/dsa/mt7530.c | 137 +++++++++++++++++++++++++++++++++- + drivers/net/dsa/mt7530.c | 135 +++++++++++++++++++++++++++++++++- drivers/net/dsa/mt7530.h | 12 +-- - 6 files changed, 255 insertions(+), 10 deletions(-) + 6 files changed, 253 insertions(+), 10 deletions(-) create mode 100644 drivers/net/dsa/mt7530-mmio.c --- a/MAINTAINERS diff --git a/target/linux/generic/backport-6.1/792-v6.6-net-phylink-add-pcs_enable-pcs_disable-methods.patch b/target/linux/generic/backport-6.1/792-v6.6-net-phylink-add-pcs_enable-pcs_disable-methods.patch new file mode 100644 index 00000000000..6ade45ee3ed --- /dev/null +++ b/target/linux/generic/backport-6.1/792-v6.6-net-phylink-add-pcs_enable-pcs_disable-methods.patch @@ -0,0 +1,172 @@ +From 90ef0a7b0622c62758b2638604927867775479ea Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Thu, 13 Jul 2023 09:42:07 +0100 +Subject: [PATCH] net: phylink: add pcs_enable()/pcs_disable() methods + +Add phylink PCS enable/disable callbacks that will allow us to place +IEEE 802.3 register compliant PCS in power-down mode while not being +used. + +Signed-off-by: Russell King (Oracle) +Signed-off-by: David S. Miller +--- + drivers/net/phy/phylink.c | 48 +++++++++++++++++++++++++++++++-------- + include/linux/phylink.h | 16 +++++++++++++ + 2 files changed, 55 insertions(+), 9 deletions(-) + +--- a/drivers/net/phy/phylink.c ++++ b/drivers/net/phy/phylink.c +@@ -34,6 +34,10 @@ enum { + PHYLINK_DISABLE_STOPPED, + PHYLINK_DISABLE_LINK, + PHYLINK_DISABLE_MAC_WOL, ++ ++ PCS_STATE_DOWN = 0, ++ PCS_STATE_STARTING, ++ PCS_STATE_STARTED, + }; + + /** +@@ -71,6 +75,7 @@ struct phylink { + struct mutex state_mutex; + struct phylink_link_state phy_state; + struct work_struct resolve; ++ unsigned int pcs_state; + + bool mac_link_dropped; + bool using_mac_select_pcs; +@@ -987,6 +992,22 @@ static void phylink_mac_pcs_an_restart(s + } + } + ++static void phylink_pcs_disable(struct phylink_pcs *pcs) ++{ ++ if (pcs && pcs->ops->pcs_disable) ++ pcs->ops->pcs_disable(pcs); ++} ++ ++static int phylink_pcs_enable(struct phylink_pcs *pcs) ++{ ++ int err = 0; ++ ++ if (pcs && pcs->ops->pcs_enable) ++ err = pcs->ops->pcs_enable(pcs); ++ ++ return err; ++} ++ + static void phylink_major_config(struct phylink *pl, bool restart, + const struct phylink_link_state *state) + { +@@ -1023,11 +1044,16 @@ static void phylink_major_config(struct + /* If we have a new PCS, switch to the new PCS after preparing the MAC + * for the change. + */ +- if (pcs_changed) ++ if (pcs_changed) { ++ phylink_pcs_disable(pl->pcs); + pl->pcs = pcs; ++ } + + phylink_mac_config(pl, state); + ++ if (pl->pcs_state == PCS_STATE_STARTING || pcs_changed) ++ phylink_pcs_enable(pl->pcs); ++ + if (pl->pcs) { + err = pl->pcs->ops->pcs_config(pl->pcs, pl->cur_link_an_mode, + state->interface, +@@ -1498,6 +1524,7 @@ struct phylink *phylink_create(struct ph + pl->link_config.speed = SPEED_UNKNOWN; + pl->link_config.duplex = DUPLEX_UNKNOWN; + pl->link_config.an_enabled = true; ++ pl->pcs_state = PCS_STATE_DOWN; + pl->mac_ops = mac_ops; + __set_bit(PHYLINK_DISABLE_STOPPED, &pl->phylink_disable_state); + timer_setup(&pl->link_poll, phylink_fixed_poll, 0); +@@ -1899,6 +1926,8 @@ void phylink_start(struct phylink *pl) + if (pl->netdev) + netif_carrier_off(pl->netdev); + ++ pl->pcs_state = PCS_STATE_STARTING; ++ + /* Apply the link configuration to the MAC when starting. This allows + * a fixed-link to start with the correct parameters, and also + * ensures that we set the appropriate advertisement for Serdes links. +@@ -1909,6 +1938,8 @@ void phylink_start(struct phylink *pl) + */ + phylink_mac_initial_config(pl, true); + ++ pl->pcs_state = PCS_STATE_STARTED; ++ + phylink_enable_and_run_resolve(pl, PHYLINK_DISABLE_STOPPED); + + if (pl->cfg_link_an_mode == MLO_AN_FIXED && pl->link_gpio) { +@@ -1927,15 +1958,9 @@ void phylink_start(struct phylink *pl) + poll = true; + } + +- switch (pl->cfg_link_an_mode) { +- case MLO_AN_FIXED: ++ if (pl->cfg_link_an_mode == MLO_AN_FIXED) + poll |= pl->config->poll_fixed_state; +- break; +- case MLO_AN_INBAND: +- if (pl->pcs) +- poll |= pl->pcs->poll; +- break; +- } ++ + if (poll) + mod_timer(&pl->link_poll, jiffies + HZ); + if (pl->phydev) +@@ -1972,6 +1997,10 @@ void phylink_stop(struct phylink *pl) + } + + phylink_run_resolve_and_disable(pl, PHYLINK_DISABLE_STOPPED); ++ ++ pl->pcs_state = PCS_STATE_DOWN; ++ ++ phylink_pcs_disable(pl->pcs); + } + EXPORT_SYMBOL_GPL(phylink_stop); + +--- a/include/linux/phylink.h ++++ b/include/linux/phylink.h +@@ -446,6 +446,8 @@ struct phylink_pcs { + /** + * struct phylink_pcs_ops - MAC PCS operations structure. + * @pcs_validate: validate the link configuration. ++ * @pcs_enable: enable the PCS. ++ * @pcs_disable: disable the PCS. + * @pcs_get_state: read the current MAC PCS link state from the hardware. + * @pcs_config: configure the MAC PCS for the selected mode and state. + * @pcs_an_restart: restart 802.3z BaseX autonegotiation. +@@ -455,6 +457,8 @@ struct phylink_pcs { + struct phylink_pcs_ops { + int (*pcs_validate)(struct phylink_pcs *pcs, unsigned long *supported, + const struct phylink_link_state *state); ++ int (*pcs_enable)(struct phylink_pcs *pcs); ++ void (*pcs_disable)(struct phylink_pcs *pcs); + void (*pcs_get_state)(struct phylink_pcs *pcs, + struct phylink_link_state *state); + int (*pcs_config)(struct phylink_pcs *pcs, unsigned int mode, +@@ -485,6 +489,18 @@ int pcs_validate(struct phylink_pcs *pcs + const struct phylink_link_state *state); + + /** ++ * pcs_enable() - enable the PCS. ++ * @pcs: a pointer to a &struct phylink_pcs. ++ */ ++int pcs_enable(struct phylink_pcs *pcs); ++ ++/** ++ * pcs_disable() - disable the PCS. ++ * @pcs: a pointer to a &struct phylink_pcs. ++ */ ++void pcs_disable(struct phylink_pcs *pcs); ++ ++/** + * pcs_get_state() - Read the current inband link state from the hardware + * @pcs: a pointer to a &struct phylink_pcs. + * @state: a pointer to a &struct phylink_link_state. diff --git a/target/linux/generic/backport-6.1/793-v6.6-net-pcs-lynxi-implement-pcs_disable-op.patch b/target/linux/generic/backport-6.1/793-v6.6-net-pcs-lynxi-implement-pcs_disable-op.patch new file mode 100644 index 00000000000..eb9b4b7c09e --- /dev/null +++ b/target/linux/generic/backport-6.1/793-v6.6-net-pcs-lynxi-implement-pcs_disable-op.patch @@ -0,0 +1,44 @@ +From e4ccdfb78a47132f2d215658aab8902fc457c4b4 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Fri, 18 Aug 2023 04:07:46 +0100 +Subject: [PATCH 082/125] net: pcs: lynxi: implement pcs_disable op + +When switching from 10GBase-R/5GBase-R/USXGMII to one of the interface +modes provided by mtk-pcs-lynxi we need to make sure to always perform +a full configuration of the PHYA. + +Implement pcs_disable op which resets the stored interface mode to +PHY_INTERFACE_MODE_NA to trigger a full reconfiguration once the LynxI +PCS driver had previously been deselected in favor of another PCS +driver such as the to-be-added driver for the USXGMII PCS found in +MT7988. + +Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/f23d1a60d2c9d2fb72e32dcb0eaa5f7e867a3d68.1692327891.git.daniel@makrotopia.org +Signed-off-by: Jakub Kicinski +--- + drivers/net/pcs/pcs-mtk-lynxi.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/drivers/net/pcs/pcs-mtk-lynxi.c ++++ b/drivers/net/pcs/pcs-mtk-lynxi.c +@@ -241,11 +241,19 @@ static void mtk_pcs_lynxi_link_up(struct + } + } + ++static void mtk_pcs_lynxi_disable(struct phylink_pcs *pcs) ++{ ++ struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs); ++ ++ mpcs->interface = PHY_INTERFACE_MODE_NA; ++} ++ + static const struct phylink_pcs_ops mtk_pcs_lynxi_ops = { + .pcs_get_state = mtk_pcs_lynxi_get_state, + .pcs_config = mtk_pcs_lynxi_config, + .pcs_an_restart = mtk_pcs_lynxi_restart_an, + .pcs_link_up = mtk_pcs_lynxi_link_up, ++ .pcs_disable = mtk_pcs_lynxi_disable, + }; + + struct phylink_pcs *mtk_pcs_lynxi_create(struct device *dev, diff --git a/target/linux/generic/hack-5.15/795-backport-phylink_pcs-helpers.patch b/target/linux/generic/hack-5.15/795-backport-phylink_pcs-helpers.patch index b1e7065a8b9..33c5c271212 100644 --- a/target/linux/generic/hack-5.15/795-backport-phylink_pcs-helpers.patch +++ b/target/linux/generic/hack-5.15/795-backport-phylink_pcs-helpers.patch @@ -17,7 +17,7 @@ Signed-off-by: Daniel Golle --- a/include/linux/phylink.h +++ b/include/linux/phylink.h -@@ -584,10 +584,37 @@ int phylink_speed_up(struct phylink *pl) +@@ -600,10 +600,37 @@ int phylink_speed_up(struct phylink *pl) #define phylink_test(bm, mode) __phylink_do_bit(test_bit, bm, mode) void phylink_set_port_modes(unsigned long *bits); @@ -57,7 +57,7 @@ Signed-off-by: Daniel Golle const unsigned long *advertising); --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c -@@ -885,7 +885,6 @@ static int phylink_change_inband_advert( +@@ -931,7 +931,6 @@ static int phylink_change_inband_advert( return 0; } @@ -65,7 +65,7 @@ Signed-off-by: Daniel Golle static void phylink_mac_pcs_get_state(struct phylink *pl, struct phylink_link_state *state) { -@@ -2966,6 +2965,52 @@ void phylink_mii_c22_pcs_get_state(struc +@@ -3014,6 +3013,52 @@ void phylink_mii_c22_pcs_get_state(struc EXPORT_SYMBOL_GPL(phylink_mii_c22_pcs_get_state); /** @@ -118,7 +118,7 @@ Signed-off-by: Daniel Golle * phylink_mii_c22_pcs_set_advertisement() - configure the clause 37 PCS * advertisement * @pcs: a pointer to a &struct mdio_device. -@@ -3037,6 +3082,46 @@ int phylink_mii_c22_pcs_set_advertisemen +@@ -3085,6 +3130,46 @@ int phylink_mii_c22_pcs_set_advertisemen EXPORT_SYMBOL_GPL(phylink_mii_c22_pcs_set_advertisement); /** diff --git a/target/linux/generic/pending-5.15/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch b/target/linux/generic/pending-5.15/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch index 2bc78fa05e5..9a1c26e7aeb 100644 --- a/target/linux/generic/pending-5.15/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch +++ b/target/linux/generic/pending-5.15/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch @@ -10,7 +10,7 @@ Signed-off-by: Felix Fietkau --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -2992,8 +2992,8 @@ static irqreturn_t mtk_handle_irq_rx(int +@@ -3095,8 +3095,8 @@ static irqreturn_t mtk_handle_irq_rx(int eth->rx_events++; if (likely(napi_schedule_prep(ð->rx_napi))) { @@ -20,7 +20,7 @@ Signed-off-by: Felix Fietkau } return IRQ_HANDLED; -@@ -3005,8 +3005,8 @@ static irqreturn_t mtk_handle_irq_tx(int +@@ -3108,8 +3108,8 @@ static irqreturn_t mtk_handle_irq_tx(int eth->tx_events++; if (likely(napi_schedule_prep(ð->tx_napi))) { @@ -30,7 +30,7 @@ Signed-off-by: Felix Fietkau } return IRQ_HANDLED; -@@ -4666,6 +4666,8 @@ static int mtk_probe(struct platform_dev +@@ -4883,6 +4883,8 @@ static int mtk_probe(struct platform_dev * for NAPI to work */ init_dummy_netdev(ð->dummy_dev); diff --git a/target/linux/generic/pending-5.15/732-00-net-ethernet-mtk_eth_soc-compile-out-netsys-v2-code-.patch b/target/linux/generic/pending-5.15/732-00-net-ethernet-mtk_eth_soc-compile-out-netsys-v2-code-.patch new file mode 100644 index 00000000000..1d84ea9ced5 --- /dev/null +++ b/target/linux/generic/pending-5.15/732-00-net-ethernet-mtk_eth_soc-compile-out-netsys-v2-code-.patch @@ -0,0 +1,44 @@ +From: Felix Fietkau +Date: Thu, 27 Oct 2022 23:39:52 +0200 +Subject: [PATCH] net: ethernet: mtk_eth_soc: compile out netsys v2 code + on mt7621 + +Avoid some branches in the hot path on low-end devices with limited CPU power, +and reduce code size + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -1323,6 +1323,22 @@ struct mtk_mac { + /* the struct describing the SoC. these are declared in the soc_xyz.c files */ + extern const struct of_device_id of_mtk_match[]; + ++#ifdef CONFIG_SOC_MT7621 ++static inline bool mtk_is_netsys_v1(struct mtk_eth *eth) ++{ ++ return true; ++} ++ ++static inline bool mtk_is_netsys_v2_or_greater(struct mtk_eth *eth) ++{ ++ return false; ++} ++ ++static inline bool mtk_is_netsys_v3_or_greater(struct mtk_eth *eth) ++{ ++ return false; ++} ++#else + static inline bool mtk_is_netsys_v1(struct mtk_eth *eth) + { + return eth->soc->version == 1; +@@ -1337,6 +1353,7 @@ static inline bool mtk_is_netsys_v3_or_g + { + return eth->soc->version > 2; + } ++#endif + + static inline struct mtk_foe_entry * + mtk_foe_get_entry(struct mtk_ppe *ppe, u16 hash) diff --git a/target/linux/generic/pending-5.15/732-01-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch b/target/linux/generic/pending-5.15/732-01-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch index fbf0cb5735e..56edb632345 100644 --- a/target/linux/generic/pending-5.15/732-01-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch +++ b/target/linux/generic/pending-5.15/732-01-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch @@ -16,7 +16,7 @@ Signed-off-by: Felix Fietkau --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -1423,12 +1423,28 @@ static void mtk_wake_queue(struct mtk_et +@@ -1516,12 +1516,28 @@ static void mtk_wake_queue(struct mtk_et } } @@ -45,11 +45,11 @@ Signed-off-by: Felix Fietkau bool gso = false; int tx_num; -@@ -1450,6 +1466,18 @@ static netdev_tx_t mtk_start_xmit(struct +@@ -1543,6 +1559,18 @@ static netdev_tx_t mtk_start_xmit(struct return NETDEV_TX_BUSY; } -+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) && ++ if (mtk_is_netsys_v1(eth) && + skb_is_gso(skb) && mtk_skb_has_small_frag(skb)) { + segs = skb_gso_segment(skb, dev->features & ~NETIF_F_ALL_TSO); + if (IS_ERR(segs)) @@ -64,14 +64,14 @@ Signed-off-by: Felix Fietkau /* TSO: fill MSS info in tcp checksum field */ if (skb_is_gso(skb)) { if (skb_cow_head(skb, 0)) { -@@ -1465,8 +1493,14 @@ static netdev_tx_t mtk_start_xmit(struct +@@ -1558,8 +1586,14 @@ static netdev_tx_t mtk_start_xmit(struct } } - if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) - goto drop; + skb_list_walk_safe(skb, skb, next) { -+ if ((!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) && ++ if ((mtk_is_netsys_v1(eth) && + mtk_skb_has_small_frag(skb) && skb_linearize(skb)) || + mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) { + stats->tx_dropped++; @@ -83,7 +83,7 @@ Signed-off-by: Felix Fietkau netif_tx_stop_all_queues(dev); --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -258,7 +258,7 @@ +@@ -268,7 +268,7 @@ #define MTK_CHK_DDONE_EN BIT(28) #define MTK_DMAD_WR_WDONE BIT(26) #define MTK_WCOMP_EN BIT(24) diff --git a/target/linux/generic/pending-5.15/732-02-net-ethernet-mtk_eth_soc-set-NETIF_F_ALL_TSO.patch b/target/linux/generic/pending-5.15/732-02-net-ethernet-mtk_eth_soc-set-NETIF_F_ALL_TSO.patch index 3c6359ee419..11a81dd0bfd 100644 --- a/target/linux/generic/pending-5.15/732-02-net-ethernet-mtk_eth_soc-set-NETIF_F_ALL_TSO.patch +++ b/target/linux/generic/pending-5.15/732-02-net-ethernet-mtk_eth_soc-set-NETIF_F_ALL_TSO.patch @@ -9,7 +9,7 @@ Signed-off-by: Felix Fietkau --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -48,8 +48,7 @@ +@@ -47,8 +47,7 @@ #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ NETIF_F_RXCSUM | \ NETIF_F_HW_VLAN_CTAG_TX | \ diff --git a/target/linux/generic/pending-5.15/732-03-net-ethernet-mtk_eth_soc-fix-remaining-throughput-re.patch b/target/linux/generic/pending-5.15/732-03-net-ethernet-mtk_eth_soc-fix-remaining-throughput-re.patch index 0aa9382b6bd..452e486e896 100644 --- a/target/linux/generic/pending-5.15/732-03-net-ethernet-mtk_eth_soc-fix-remaining-throughput-re.patch +++ b/target/linux/generic/pending-5.15/732-03-net-ethernet-mtk_eth_soc-fix-remaining-throughput-re.patch @@ -22,7 +22,7 @@ Signed-off-by: Felix Fietkau --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -667,6 +667,7 @@ static void mtk_mac_link_up(struct phyli +@@ -723,6 +723,7 @@ static void mtk_mac_link_up(struct phyli MAC_MCR_FORCE_RX_FC); /* Configure speed */ @@ -30,7 +30,7 @@ Signed-off-by: Felix Fietkau switch (speed) { case SPEED_2500: case SPEED_1000: -@@ -3145,6 +3146,9 @@ found: +@@ -3288,6 +3289,9 @@ found: if (dp->index >= MTK_QDMA_NUM_QUEUES) return NOTIFY_DONE; diff --git a/target/linux/generic/pending-5.15/734-net-ethernet-mtk_eth_soc-ppe-fix-L2-offloading-with-.patch b/target/linux/generic/pending-5.15/734-net-ethernet-mtk_eth_soc-ppe-fix-L2-offloading-with-.patch index 9ef65ec16f7..104ce00b7eb 100644 --- a/target/linux/generic/pending-5.15/734-net-ethernet-mtk_eth_soc-ppe-fix-L2-offloading-with-.patch +++ b/target/linux/generic/pending-5.15/734-net-ethernet-mtk_eth_soc-ppe-fix-L2-offloading-with-.patch @@ -20,7 +20,7 @@ Signed-off-by: Felix Fietkau #include #include "mtk_eth_soc.h" #include "mtk_ppe.h" -@@ -757,7 +758,9 @@ void __mtk_ppe_check_skb(struct mtk_ppe +@@ -781,7 +782,9 @@ void __mtk_ppe_check_skb(struct mtk_ppe skb->dev->dsa_ptr->tag_ops->proto != DSA_TAG_PROTO_MTK) goto out; diff --git a/target/linux/generic/pending-5.15/736-01-net-ethernet-mtk_eth_soc-add-code-for-offloading-flo.patch b/target/linux/generic/pending-5.15/736-01-net-ethernet-mtk_eth_soc-add-code-for-offloading-flo.patch index 4f765c5c145..d648ba4dc7f 100644 --- a/target/linux/generic/pending-5.15/736-01-net-ethernet-mtk_eth_soc-add-code-for-offloading-flo.patch +++ b/target/linux/generic/pending-5.15/736-01-net-ethernet-mtk_eth_soc-add-code-for-offloading-flo.patch @@ -14,7 +14,7 @@ Signed-off-by: Felix Fietkau --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -1277,6 +1277,9 @@ int mtk_gmac_rgmii_path_setup(struct mtk +@@ -1448,6 +1448,9 @@ int mtk_gmac_rgmii_path_setup(struct mtk int mtk_eth_offload_init(struct mtk_eth *eth); int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, void *type_data); @@ -120,7 +120,7 @@ Signed-off-by: Felix Fietkau static void wed_m32(struct mtk_wed_device *dev, u32 reg, u32 mask, u32 val) { -@@ -1752,6 +1759,99 @@ out: +@@ -1760,6 +1767,99 @@ out: mutex_unlock(&hw_lock); } @@ -220,7 +220,7 @@ Signed-off-by: Felix Fietkau void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth, void __iomem *wdma, phys_addr_t wdma_phy, int index) -@@ -1771,6 +1871,7 @@ void mtk_wed_add_hw(struct device_node * +@@ -1779,6 +1879,7 @@ void mtk_wed_add_hw(struct device_node * .irq_set_mask = mtk_wed_irq_set_mask, .detach = mtk_wed_detach, .ppe_check = mtk_wed_ppe_check, diff --git a/target/linux/generic/pending-5.15/736-02-net-ethernet-mediatek-mtk_ppe-prefer-newly-added-l2-.patch b/target/linux/generic/pending-5.15/736-02-net-ethernet-mediatek-mtk_ppe-prefer-newly-added-l2-.patch index 6e17e4dc529..e89d4cd97b9 100644 --- a/target/linux/generic/pending-5.15/736-02-net-ethernet-mediatek-mtk_ppe-prefer-newly-added-l2-.patch +++ b/target/linux/generic/pending-5.15/736-02-net-ethernet-mediatek-mtk_ppe-prefer-newly-added-l2-.patch @@ -12,7 +12,7 @@ Signed-off-by: Felix Fietkau --- a/drivers/net/ethernet/mediatek/mtk_ppe.c +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c -@@ -639,10 +639,20 @@ void mtk_foe_entry_clear(struct mtk_ppe +@@ -663,10 +663,20 @@ void mtk_foe_entry_clear(struct mtk_ppe static int mtk_foe_entry_commit_l2(struct mtk_ppe *ppe, struct mtk_flow_entry *entry) { diff --git a/target/linux/generic/pending-5.15/736-03-net-ethernet-mtk_eth_soc-improve-keeping-track-of-of.patch b/target/linux/generic/pending-5.15/736-03-net-ethernet-mtk_eth_soc-improve-keeping-track-of-of.patch index 29d6e0b0991..c8be7a9e2b2 100644 --- a/target/linux/generic/pending-5.15/736-03-net-ethernet-mtk_eth_soc-improve-keeping-track-of-of.patch +++ b/target/linux/generic/pending-5.15/736-03-net-ethernet-mtk_eth_soc-improve-keeping-track-of-of.patch @@ -12,7 +12,7 @@ Signed-off-by: Felix Fietkau --- a/drivers/net/ethernet/mediatek/mtk_ppe.c +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c -@@ -466,42 +466,43 @@ int mtk_foe_entry_set_queue(struct mtk_e +@@ -483,42 +483,43 @@ int mtk_foe_entry_set_queue(struct mtk_e return 0; } @@ -72,7 +72,7 @@ Signed-off-by: Felix Fietkau struct mtk_foe_entry *hwe = mtk_foe_get_entry(ppe, entry->hash); hwe->ib1 &= ~MTK_FOE_IB1_STATE; -@@ -520,7 +521,8 @@ __mtk_foe_entry_clear(struct mtk_ppe *pp +@@ -538,7 +539,8 @@ __mtk_foe_entry_clear(struct mtk_ppe *pp if (entry->type != MTK_FLOW_TYPE_L2_SUBFLOW) return; @@ -82,7 +82,7 @@ Signed-off-by: Felix Fietkau kfree(entry); } -@@ -536,66 +538,55 @@ static int __mtk_foe_entry_idle_time(str +@@ -554,66 +556,55 @@ static int __mtk_foe_entry_idle_time(str return now - timestamp; } @@ -178,7 +178,7 @@ Signed-off-by: Felix Fietkau } static void -@@ -632,7 +623,8 @@ __mtk_foe_entry_commit(struct mtk_ppe *p +@@ -656,7 +647,8 @@ __mtk_foe_entry_commit(struct mtk_ppe *p void mtk_foe_entry_clear(struct mtk_ppe *ppe, struct mtk_flow_entry *entry) { spin_lock_bh(&ppe_lock); @@ -188,7 +188,7 @@ Signed-off-by: Felix Fietkau spin_unlock_bh(&ppe_lock); } -@@ -679,8 +671,8 @@ mtk_foe_entry_commit_subflow(struct mtk_ +@@ -703,8 +695,8 @@ mtk_foe_entry_commit_subflow(struct mtk_ { const struct mtk_soc_data *soc = ppe->eth->soc; struct mtk_flow_entry *flow_info; @@ -198,7 +198,7 @@ Signed-off-by: Felix Fietkau u32 ib1_mask = mtk_get_ib1_pkt_type_mask(ppe->eth) | MTK_FOE_IB1_UDP; int type; -@@ -688,30 +680,30 @@ mtk_foe_entry_commit_subflow(struct mtk_ +@@ -712,30 +704,30 @@ mtk_foe_entry_commit_subflow(struct mtk_ if (!flow_info) return; @@ -239,7 +239,7 @@ Signed-off-by: Felix Fietkau } void __mtk_ppe_check_skb(struct mtk_ppe *ppe, struct sk_buff *skb, u16 hash) -@@ -721,9 +713,11 @@ void __mtk_ppe_check_skb(struct mtk_ppe +@@ -745,9 +737,11 @@ void __mtk_ppe_check_skb(struct mtk_ppe struct mtk_foe_entry *hwe = mtk_foe_get_entry(ppe, hash); struct mtk_flow_entry *entry; struct mtk_foe_bridge key = {}; @@ -251,7 +251,7 @@ Signed-off-by: Felix Fietkau u8 *tag; spin_lock_bh(&ppe_lock); -@@ -731,20 +725,14 @@ void __mtk_ppe_check_skb(struct mtk_ppe +@@ -755,20 +749,14 @@ void __mtk_ppe_check_skb(struct mtk_ppe if (FIELD_GET(MTK_FOE_IB1_STATE, hwe->ib1) == MTK_FOE_STATE_BIND) goto out; @@ -278,7 +278,7 @@ Signed-off-by: Felix Fietkau continue; } -@@ -795,9 +783,17 @@ out: +@@ -819,9 +807,17 @@ out: int mtk_foe_entry_idle_time(struct mtk_ppe *ppe, struct mtk_flow_entry *entry) { @@ -300,7 +300,7 @@ Signed-off-by: Felix Fietkau int mtk_ppe_prepare_reset(struct mtk_ppe *ppe) --- a/drivers/net/ethernet/mediatek/mtk_ppe.h +++ b/drivers/net/ethernet/mediatek/mtk_ppe.h -@@ -265,7 +265,12 @@ enum { +@@ -286,7 +286,12 @@ enum { struct mtk_flow_entry { union { @@ -314,7 +314,7 @@ Signed-off-by: Felix Fietkau struct { struct rhash_head l2_node; struct hlist_head l2_flows; -@@ -275,13 +280,7 @@ struct mtk_flow_entry { +@@ -296,13 +301,7 @@ struct mtk_flow_entry { s8 wed_index; u8 ppe_index; u16 hash; diff --git a/target/linux/generic/pending-5.15/736-04-net-ethernet-mediatek-fix-ppe-flow-accounting-for-L2.patch b/target/linux/generic/pending-5.15/736-04-net-ethernet-mediatek-fix-ppe-flow-accounting-for-L2.patch index fdc3d520c11..7f04fd9fa86 100644 --- a/target/linux/generic/pending-5.15/736-04-net-ethernet-mediatek-fix-ppe-flow-accounting-for-L2.patch +++ b/target/linux/generic/pending-5.15/736-04-net-ethernet-mediatek-fix-ppe-flow-accounting-for-L2.patch @@ -27,7 +27,7 @@ Signed-off-by: Felix Fietkau if (ret) dev_err(ppe->dev, "MIB table busy"); -@@ -90,18 +90,32 @@ static int mtk_ppe_mib_wait_busy(struct +@@ -90,17 +90,31 @@ static int mtk_ppe_mib_wait_busy(struct return ret; } @@ -43,7 +43,6 @@ Signed-off-by: Felix Fietkau + +struct mtk_foe_accounting *mtk_ppe_mib_entry_read(struct mtk_ppe *ppe, u16 index) { - u32 byte_cnt_low, byte_cnt_high, pkt_cnt_low, pkt_cnt_high; u32 val, cnt_r0, cnt_r1, cnt_r2; + struct mtk_foe_accounting *acct; int ret; @@ -62,25 +61,35 @@ Signed-off-by: Felix Fietkau cnt_r0 = readl(ppe->base + MTK_PPE_MIB_SER_R0); cnt_r1 = readl(ppe->base + MTK_PPE_MIB_SER_R1); -@@ -111,10 +125,11 @@ static int mtk_mib_entry_read(struct mtk - byte_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH, cnt_r1); - pkt_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R1_PKT_CNT_LOW, cnt_r1); - pkt_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH, cnt_r2); -- *bytes = ((u64)byte_cnt_high << 32) | byte_cnt_low; -- *packets = (pkt_cnt_high << 16) | pkt_cnt_low; +@@ -109,19 +123,19 @@ static int mtk_mib_entry_read(struct mtk + if (mtk_is_netsys_v3_or_greater(ppe->eth)) { + /* 64 bit for each counter */ + u32 cnt_r3 = readl(ppe->base + MTK_PPE_MIB_SER_R3); +- *bytes = ((u64)cnt_r1 << 32) | cnt_r0; +- *packets = ((u64)cnt_r3 << 32) | cnt_r2; ++ acct->bytes += ((u64)cnt_r1 << 32) | cnt_r0; ++ acct->packets += ((u64)cnt_r3 << 32) | cnt_r2; + } else { + /* 48 bit byte counter, 40 bit packet counter */ + u32 byte_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R0_BYTE_CNT_LOW, cnt_r0); + u32 byte_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH, cnt_r1); + u32 pkt_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R1_PKT_CNT_LOW, cnt_r1); + u32 pkt_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH, cnt_r2); +- *bytes = ((u64)byte_cnt_high << 32) | byte_cnt_low; +- *packets = (pkt_cnt_high << 16) | pkt_cnt_low; ++ acct->bytes += ((u64)byte_cnt_high << 32) | byte_cnt_low; ++ acct->packets += (pkt_cnt_high << 16) | pkt_cnt_low; + } - return 0; -+ acct->bytes += ((u64)byte_cnt_high << 32) | byte_cnt_low; -+ acct->packets += (pkt_cnt_high << 16) | pkt_cnt_low; -+ + return acct; } static void mtk_ppe_cache_clear(struct mtk_ppe *ppe) -@@ -508,13 +523,6 @@ __mtk_foe_entry_clear(struct mtk_ppe *pp - hwe->ib1 &= ~MTK_FOE_IB1_STATE; +@@ -526,13 +540,6 @@ __mtk_foe_entry_clear(struct mtk_ppe *pp hwe->ib1 |= FIELD_PREP(MTK_FOE_IB1_STATE, MTK_FOE_STATE_INVALID); dma_wmb(); + mtk_ppe_cache_clear(ppe); - if (ppe->accounting) { - struct mtk_foe_accounting *acct; - @@ -91,7 +100,7 @@ Signed-off-by: Felix Fietkau } entry->hash = 0xffff; -@@ -539,11 +547,14 @@ static int __mtk_foe_entry_idle_time(str +@@ -557,11 +564,14 @@ static int __mtk_foe_entry_idle_time(str } static bool @@ -107,7 +116,7 @@ Signed-off-by: Felix Fietkau int len; if (hash == 0xffff) -@@ -554,18 +565,35 @@ mtk_flow_entry_update(struct mtk_ppe *pp +@@ -572,18 +582,35 @@ mtk_flow_entry_update(struct mtk_ppe *pp memcpy(&foe, hwe, len); if (!mtk_flow_entry_match(ppe->eth, entry, &foe, len) || @@ -146,7 +155,7 @@ Signed-off-by: Felix Fietkau struct mtk_flow_entry *cur; struct hlist_node *tmp; int idle; -@@ -574,7 +602,9 @@ mtk_flow_entry_update_l2(struct mtk_ppe +@@ -592,7 +619,9 @@ mtk_flow_entry_update_l2(struct mtk_ppe hlist_for_each_entry_safe(cur, tmp, &entry->l2_flows, l2_list) { int cur_idle; @@ -157,7 +166,7 @@ Signed-off-by: Felix Fietkau __mtk_foe_entry_clear(ppe, entry, false); continue; } -@@ -589,10 +619,29 @@ mtk_flow_entry_update_l2(struct mtk_ppe +@@ -607,10 +636,29 @@ mtk_flow_entry_update_l2(struct mtk_ppe } } @@ -187,7 +196,7 @@ Signed-off-by: Felix Fietkau struct mtk_eth *eth = ppe->eth; u16 timestamp = mtk_eth_timestamp(eth); struct mtk_foe_entry *hwe; -@@ -617,6 +666,12 @@ __mtk_foe_entry_commit(struct mtk_ppe *p +@@ -641,6 +689,12 @@ __mtk_foe_entry_commit(struct mtk_ppe *p dma_wmb(); @@ -200,7 +209,7 @@ Signed-off-by: Felix Fietkau mtk_ppe_cache_clear(ppe); } -@@ -781,21 +836,6 @@ out: +@@ -805,21 +859,6 @@ out: spin_unlock_bh(&ppe_lock); } @@ -222,7 +231,7 @@ Signed-off-by: Felix Fietkau int mtk_ppe_prepare_reset(struct mtk_ppe *ppe) { if (!ppe) -@@ -823,32 +863,6 @@ int mtk_ppe_prepare_reset(struct mtk_ppe +@@ -847,32 +886,6 @@ int mtk_ppe_prepare_reset(struct mtk_ppe return mtk_ppe_wait_busy(ppe); } @@ -257,7 +266,7 @@ Signed-off-by: Felix Fietkau bool accounting = eth->soc->has_accounting; --- a/drivers/net/ethernet/mediatek/mtk_ppe.h +++ b/drivers/net/ethernet/mediatek/mtk_ppe.h -@@ -283,6 +283,8 @@ struct mtk_flow_entry { +@@ -304,6 +304,8 @@ struct mtk_flow_entry { struct mtk_foe_entry data; struct rhash_head node; unsigned long cookie; @@ -266,7 +275,7 @@ Signed-off-by: Felix Fietkau }; struct mtk_mib_entry { -@@ -325,6 +327,7 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_ +@@ -347,6 +349,7 @@ void mtk_ppe_deinit(struct mtk_eth *eth) void mtk_ppe_start(struct mtk_ppe *ppe); int mtk_ppe_stop(struct mtk_ppe *ppe); int mtk_ppe_prepare_reset(struct mtk_ppe *ppe); @@ -274,7 +283,7 @@ Signed-off-by: Felix Fietkau void __mtk_ppe_check_skb(struct mtk_ppe *ppe, struct sk_buff *skb, u16 hash); -@@ -373,9 +376,8 @@ int mtk_foe_entry_set_queue(struct mtk_e +@@ -395,9 +398,8 @@ int mtk_foe_entry_set_queue(struct mtk_e unsigned int queue); int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_flow_entry *entry); void mtk_foe_entry_clear(struct mtk_ppe *ppe, struct mtk_flow_entry *entry); @@ -295,7 +304,7 @@ Signed-off-by: Felix Fietkau - acct = mtk_foe_entry_get_mib(ppe, i, NULL); + acct = mtk_ppe_mib_entry_read(ppe, i); - type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1); + type = mtk_get_ib1_pkt_type(ppe->eth, entry->ib1); seq_printf(m, "%05x %s %7s", i, --- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c +++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c diff --git a/target/linux/generic/pending-5.15/737-01-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V1-capabilit.patch b/target/linux/generic/pending-5.15/737-01-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V1-capabilit.patch deleted file mode 100644 index 621a7b0fcf0..00000000000 --- a/target/linux/generic/pending-5.15/737-01-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V1-capabilit.patch +++ /dev/null @@ -1,223 +0,0 @@ -From 663fa1b7e0cb2c929008482014a70c6625caad75 Mon Sep 17 00:00:00 2001 -From: Lorenzo Bianconi -Date: Tue, 7 Mar 2023 15:55:13 +0000 -Subject: [PATCH 1/7] net: ethernet: mtk_eth_soc: add MTK_NETSYS_V1 capability - bit - -Introduce MTK_NETSYS_V1 bit in the device capabilities for -MT7621/MT7622/MT7623/MT7628/MT7629 SoCs. -Use !MTK_NETSYS_V1 instead of MTK_NETSYS_V2 in the driver codebase. -This is a preliminary patch to introduce support for MT7988 SoC. - -Signed-off-by: Lorenzo Bianconi -Signed-off-by: Daniel Golle ---- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 30 +++++++------- - drivers/net/ethernet/mediatek/mtk_eth_soc.h | 45 ++++++++++++--------- - 2 files changed, 41 insertions(+), 34 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -597,7 +597,7 @@ static void mtk_set_queue_speed(struct m - FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | - FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | - MTK_QTX_SCH_LEAKY_BUCKET_SIZE; -- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) - val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; - - if (IS_ENABLED(CONFIG_SOC_MT7621)) { -@@ -974,7 +974,7 @@ static bool mtk_rx_get_desc(struct mtk_e - rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); - rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); - rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); -- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { -+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { - rxd->rxd5 = READ_ONCE(dma_rxd->rxd5); - rxd->rxd6 = READ_ONCE(dma_rxd->rxd6); - } -@@ -1032,7 +1032,7 @@ static int mtk_init_fq_dma(struct mtk_et - - txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE); - txd->txd4 = 0; -- if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) { -+ if (!MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V1)) { - txd->txd5 = 0; - txd->txd6 = 0; - txd->txd7 = 0; -@@ -1221,7 +1221,7 @@ static void mtk_tx_set_dma_desc(struct n - struct mtk_mac *mac = netdev_priv(dev); - struct mtk_eth *eth = mac->hw; - -- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) -+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) - mtk_tx_set_dma_desc_v2(dev, txd, info); - else - mtk_tx_set_dma_desc_v1(dev, txd, info); -@@ -1902,7 +1902,7 @@ static int mtk_poll_rx(struct napi_struc - break; - - /* find out which mac the packet come from. values start at 1 */ -- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) -+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) - mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1; - else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && - !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) -@@ -1998,7 +1998,7 @@ static int mtk_poll_rx(struct napi_struc - skb->dev = netdev; - bytes += skb->len; - -- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { -+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { - reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5); - hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY; - if (hash != MTK_RXD5_FOE_ENTRY) -@@ -2023,7 +2023,7 @@ static int mtk_poll_rx(struct napi_struc - /* When using VLAN untagging in combination with DSA, the - * hardware treats the MTK special tag as a VLAN and untags it. - */ -- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) && -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1) && - (trxd.rxd2 & RX_DMA_VTAG) && netdev_uses_dsa(netdev)) { - unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0); - -@@ -2328,7 +2328,7 @@ static int mtk_tx_alloc(struct mtk_eth * - txd->txd2 = next_ptr; - txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; - txd->txd4 = 0; -- if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) { -+ if (!MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V1)) { - txd->txd5 = 0; - txd->txd6 = 0; - txd->txd7 = 0; -@@ -2381,7 +2381,7 @@ static int mtk_tx_alloc(struct mtk_eth * - FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | - FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | - MTK_QTX_SCH_LEAKY_BUCKET_SIZE; -- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) - val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; - mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); - ofs += MTK_QTX_OFFSET; -@@ -2515,7 +2515,7 @@ static int mtk_rx_alloc(struct mtk_eth * - - rxd->rxd3 = 0; - rxd->rxd4 = 0; -- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { -+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { - rxd->rxd5 = 0; - rxd->rxd6 = 0; - rxd->rxd7 = 0; -@@ -3063,7 +3063,7 @@ static int mtk_start_dma(struct mtk_eth - MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO | - MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE; - -- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) -+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) - val |= MTK_MUTLI_CNT | MTK_RESV_BUF | - MTK_WCOMP_EN | MTK_DMAD_WR_WDONE | - MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN; -@@ -3475,7 +3475,7 @@ static void mtk_hw_reset(struct mtk_eth - { - u32 val; - -- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { -+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { - regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); - val = RSTCTRL_PPE0_V2; - } else { -@@ -3487,7 +3487,7 @@ static void mtk_hw_reset(struct mtk_eth - - ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val); - -- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) -+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) - regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, - 0x3ffffff); - } -@@ -3683,7 +3683,7 @@ static int mtk_hw_init(struct mtk_eth *e - else - mtk_hw_reset(eth); - -- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { -+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { - /* Set FE to PDMAv2 if necessary */ - val = mtk_r32(eth, MTK_FE_GLO_MISC); - mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC); -@@ -3720,7 +3720,7 @@ static int mtk_hw_init(struct mtk_eth *e - */ - val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); - mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); -- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { - val = mtk_r32(eth, MTK_CDMP_IG_CTRL); - mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL); - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -816,6 +816,7 @@ enum mkt_eth_capabilities { - MTK_SHARED_INT_BIT, - MTK_TRGMII_MT7621_CLK_BIT, - MTK_QDMA_BIT, -+ MTK_NETSYS_V1_BIT, - MTK_NETSYS_V2_BIT, - MTK_SOC_MT7628_BIT, - MTK_RSTCTRL_PPE1_BIT, -@@ -851,6 +852,7 @@ enum mkt_eth_capabilities { - #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT) - #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) - #define MTK_QDMA BIT(MTK_QDMA_BIT) -+#define MTK_NETSYS_V1 BIT(MTK_NETSYS_V1_BIT) - #define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) - #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) - #define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT) -@@ -913,25 +915,30 @@ enum mkt_eth_capabilities { - - #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x) & ~(MTK_CAP_MASK)) == (_x)) - --#define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ -- MTK_GMAC2_RGMII | MTK_SHARED_INT | \ -- MTK_TRGMII_MT7621_CLK | MTK_QDMA) -- --#define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \ -- MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ -- MTK_MUX_GDM1_TO_GMAC1_ESW | \ -- MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA) -- --#define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \ -- MTK_QDMA) -- --#define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628) -- --#define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ -- MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ -- MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ -- MTK_MUX_U3_GMAC2_TO_QPHY | \ -- MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) -+#define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ -+ MTK_GMAC2_RGMII | MTK_SHARED_INT | \ -+ MTK_TRGMII_MT7621_CLK | MTK_QDMA | \ -+ MTK_NETSYS_V1) -+ -+#define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | \ -+ MTK_GMAC2_RGMII | MTK_GMAC2_SGMII | \ -+ MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW |\ -+ MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | \ -+ MTK_QDMA | MTK_NETSYS_V1) -+ -+#define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ -+ MTK_GMAC2_RGMII | MTK_QDMA | \ -+ MTK_NETSYS_V1) -+ -+#define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628 | \ -+ MTK_NETSYS_V1) -+ -+#define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ -+ MTK_GMAC2_GEPHY | MTK_GDM1_ESW | \ -+ MTK_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_QDMA | \ -+ MTK_MUX_U3_GMAC2_TO_QPHY | MTK_NETSYS_V1 |\ -+ MTK_MUX_GDM1_TO_GMAC1_ESW | \ -+ MTK_MUX_GMAC12_TO_GEPHY_SGMII) - - #define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ - MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ diff --git a/target/linux/generic/pending-5.15/737-02-net-ethernet-mtk_eth_soc-move-MAX_DEVS-in-mtk_soc_da.patch b/target/linux/generic/pending-5.15/737-02-net-ethernet-mtk_eth_soc-move-MAX_DEVS-in-mtk_soc_da.patch deleted file mode 100644 index 837a8bf0ad2..00000000000 --- a/target/linux/generic/pending-5.15/737-02-net-ethernet-mtk_eth_soc-move-MAX_DEVS-in-mtk_soc_da.patch +++ /dev/null @@ -1,181 +0,0 @@ -From 5af2b2dc4d6ba0ff7696e79f18e5b2bf862194eb Mon Sep 17 00:00:00 2001 -From: Lorenzo Bianconi -Date: Tue, 7 Mar 2023 15:55:24 +0000 -Subject: [PATCH 2/7] net: ethernet: mtk_eth_soc: move MAX_DEVS in mtk_soc_data - -This is a preliminary patch to add MT7988 SoC support since it runs 3 -macs instead of 2. - -Signed-off-by: Lorenzo Bianconi -Signed-off-by: Daniel Golle ---- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 34 +++++++++++++++++++-- - drivers/net/ethernet/mediatek/mtk_eth_soc.h | 11 +++---- - 2 files changed, 36 insertions(+), 9 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -3972,7 +3972,10 @@ static void mtk_sgmii_destroy(struct mtk - { - int i; - -- for (i = 0; i < MTK_MAX_DEVS; i++) -+ if (!eth->sgmii_pcs) -+ return; -+ -+ for (i = 0; i < eth->soc->num_devs; i++) - mtk_pcs_lynxi_destroy(eth->sgmii_pcs[i]); - } - -@@ -4425,7 +4428,12 @@ static int mtk_sgmii_init(struct mtk_eth - u32 flags; - int i; - -- for (i = 0; i < MTK_MAX_DEVS; i++) { -+ eth->sgmii_pcs = devm_kzalloc(eth->dev, -+ sizeof(*eth->sgmii_pcs) * -+ eth->soc->num_devs, -+ GFP_KERNEL); -+ -+ for (i = 0; i < eth->soc->num_devs; i++) { - np = of_parse_phandle(eth->dev->of_node, "mediatek,sgmiisys", i); - if (!np) - break; -@@ -4470,6 +4478,18 @@ static int mtk_probe(struct platform_dev - if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) - eth->ip_align = NET_IP_ALIGN; - -+ eth->netdev = devm_kzalloc(eth->dev, -+ sizeof(*eth->netdev) * eth->soc->num_devs, -+ GFP_KERNEL); -+ if (!eth->netdev) -+ return -ENOMEM; -+ -+ eth->mac = devm_kzalloc(eth->dev, -+ sizeof(*eth->mac) * eth->soc->num_devs, -+ GFP_KERNEL); -+ if (!eth->mac) -+ return -ENOMEM; -+ - spin_lock_init(ð->page_lock); - spin_lock_init(ð->tx_irq_lock); - spin_lock_init(ð->rx_irq_lock); -@@ -4655,7 +4675,7 @@ static int mtk_probe(struct platform_dev - goto err_free_dev; - } - -- for (i = 0; i < MTK_MAX_DEVS; i++) { -+ for (i = 0; i < eth->soc->num_devs; i++) { - if (!eth->netdev[i]) - continue; - -@@ -4732,6 +4752,7 @@ static const struct mtk_soc_data mt2701_ - .hw_features = MTK_HW_FEATURES, - .required_clks = MT7623_CLKS_BITMAP, - .required_pctl = true, -+ .num_devs = 2, - .txrx = { - .txd_size = sizeof(struct mtk_tx_dma), - .rxd_size = sizeof(struct mtk_rx_dma), -@@ -4750,6 +4771,7 @@ static const struct mtk_soc_data mt7621_ - .required_pctl = false, - .offload_version = 1, - .hash_offset = 2, -+ .num_devs = 2, - .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, - .txrx = { - .txd_size = sizeof(struct mtk_tx_dma), -@@ -4771,6 +4793,7 @@ static const struct mtk_soc_data mt7622_ - .offload_version = 2, - .hash_offset = 2, - .has_accounting = true, -+ .num_devs = 2, - .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, - .txrx = { - .txd_size = sizeof(struct mtk_tx_dma), -@@ -4790,6 +4813,7 @@ static const struct mtk_soc_data mt7623_ - .required_pctl = true, - .offload_version = 1, - .hash_offset = 2, -+ .num_devs = 2, - .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, - .txrx = { - .txd_size = sizeof(struct mtk_tx_dma), -@@ -4809,6 +4833,7 @@ static const struct mtk_soc_data mt7629_ - .required_clks = MT7629_CLKS_BITMAP, - .required_pctl = false, - .has_accounting = true, -+ .num_devs = 2, - .txrx = { - .txd_size = sizeof(struct mtk_tx_dma), - .rxd_size = sizeof(struct mtk_rx_dma), -@@ -4830,6 +4855,7 @@ static const struct mtk_soc_data mt7981_ - .hash_offset = 4, - .foe_entry_size = sizeof(struct mtk_foe_entry), - .has_accounting = true, -+ .num_devs = 2, - .txrx = { - .txd_size = sizeof(struct mtk_tx_dma_v2), - .rxd_size = sizeof(struct mtk_rx_dma_v2), -@@ -4849,6 +4875,7 @@ static const struct mtk_soc_data mt7986_ - .required_pctl = false, - .offload_version = 2, - .hash_offset = 4, -+ .num_devs = 2, - .foe_entry_size = sizeof(struct mtk_foe_entry), - .has_accounting = true, - .txrx = { -@@ -4867,6 +4894,7 @@ static const struct mtk_soc_data rt5350_ - .hw_features = MTK_HW_FEATURES_MT7628, - .required_clks = MT7628_CLKS_BITMAP, - .required_pctl = false, -+ .num_devs = 2, - .txrx = { - .txd_size = sizeof(struct mtk_tx_dma), - .rxd_size = sizeof(struct mtk_rx_dma), ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -1018,6 +1018,7 @@ struct mtk_reg_map { - * @required_pctl A bool value to show whether the SoC requires - * the extra setup for those pins used by GMAC. - * @hash_offset Flow table hash offset. -+ * @num_devs SoC number of macs. - * @foe_entry_size Foe table entry size. - * @has_accounting Bool indicating support for accounting of - * offloaded flows. -@@ -1036,6 +1037,7 @@ struct mtk_soc_data { - bool required_pctl; - u8 offload_version; - u8 hash_offset; -+ u8 num_devs; - u16 foe_entry_size; - netdev_features_t hw_features; - bool has_accounting; -@@ -1051,9 +1053,6 @@ struct mtk_soc_data { - - #define MTK_DMA_MONITOR_TIMEOUT msecs_to_jiffies(1000) - --/* currently no SoC has more than 2 macs */ --#define MTK_MAX_DEVS 2 -- - /* struct mtk_eth - This is the main datasructure for holding the state - * of the driver - * @dev: The device pointer -@@ -1108,14 +1107,14 @@ struct mtk_eth { - spinlock_t tx_irq_lock; - spinlock_t rx_irq_lock; - struct net_device dummy_dev; -- struct net_device *netdev[MTK_MAX_DEVS]; -- struct mtk_mac *mac[MTK_MAX_DEVS]; -+ struct net_device **netdev; -+ struct mtk_mac **mac; - int irq[3]; - u32 msg_enable; - unsigned long sysclk; - struct regmap *ethsys; - struct regmap *infra; -- struct phylink_pcs *sgmii_pcs[MTK_MAX_DEVS]; -+ struct phylink_pcs **sgmii_pcs; - struct regmap *pctl; - bool hwlro; - refcount_t dma_refcnt; diff --git a/target/linux/generic/pending-5.15/737-06-net-ethernet-mtk_eth_soc-add-support-for-MT7988-SoC.patch b/target/linux/generic/pending-5.15/737-06-net-ethernet-mtk_eth_soc-add-support-for-MT7988-SoC.patch deleted file mode 100644 index e8402c0974c..00000000000 --- a/target/linux/generic/pending-5.15/737-06-net-ethernet-mtk_eth_soc-add-support-for-MT7988-SoC.patch +++ /dev/null @@ -1,495 +0,0 @@ -From 661bacf4363ca68939c15e20056b5f72fbd034e7 Mon Sep 17 00:00:00 2001 -From: Lorenzo Bianconi -Date: Sat, 25 Feb 2023 00:08:24 +0100 -Subject: [PATCH 6/7] net: ethernet: mtk_eth_soc: add support for MT7988 SoC - -Introduce support for ethernet chip available in MT7988 SoC to -mtk_eth_soc driver. ---- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 153 ++++++++++++++-- - drivers/net/ethernet/mediatek/mtk_eth_soc.h | 193 ++++++++++++++------ - 2 files changed, 279 insertions(+), 67 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -152,6 +152,54 @@ static const struct mtk_reg_map mt7986_r - .pse_oq_sta = 0x01a0, - }; - -+static const struct mtk_reg_map mt7988_reg_map = { -+ .tx_irq_mask = 0x461c, -+ .tx_irq_status = 0x4618, -+ .pdma = { -+ .rx_ptr = 0x6900, -+ .rx_cnt_cfg = 0x6904, -+ .pcrx_ptr = 0x6908, -+ .glo_cfg = 0x6a04, -+ .rst_idx = 0x6a08, -+ .delay_irq = 0x6a0c, -+ .irq_status = 0x6a20, -+ .irq_mask = 0x6a28, -+ .adma_rx_dbg0 = 0x6a38, -+ .int_grp = 0x6a50, -+ }, -+ .qdma = { -+ .qtx_cfg = 0x4400, -+ .qtx_sch = 0x4404, -+ .rx_ptr = 0x4500, -+ .rx_cnt_cfg = 0x4504, -+ .qcrx_ptr = 0x4508, -+ .glo_cfg = 0x4604, -+ .rst_idx = 0x4608, -+ .delay_irq = 0x460c, -+ .fc_th = 0x4610, -+ .int_grp = 0x4620, -+ .hred = 0x4644, -+ .ctx_ptr = 0x4700, -+ .dtx_ptr = 0x4704, -+ .crx_ptr = 0x4710, -+ .drx_ptr = 0x4714, -+ .fq_head = 0x4720, -+ .fq_tail = 0x4724, -+ .fq_count = 0x4728, -+ .fq_blen = 0x472c, -+ .tx_sch_rate = 0x4798, -+ }, -+ .gdm1_cnt = 0x1c00, -+ .gdma_to_ppe0 = 0x3333, -+ .ppe_base = 0x2200, -+ .wdma_base = { -+ [0] = 0x4800, -+ [1] = 0x4c00, -+ }, -+ .pse_iq_sta = 0x0180, -+ .pse_oq_sta = 0x01a0, -+}; -+ - /* strings used by ethtool */ - static const struct mtk_ethtool_stats { - char str[ETH_GSTRING_LEN]; -@@ -179,10 +227,54 @@ static const struct mtk_ethtool_stats { - }; - - static const char * const mtk_clks_source_name[] = { -- "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll", -- "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", -- "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb", -- "sgmii_ck", "eth2pll", "wocpu0", "wocpu1", "netsys0", "netsys1" -+ "ethif", -+ "sgmiitop", -+ "esw", -+ "gp0", -+ "gp1", -+ "gp2", -+ "gp3", -+ "xgp1", -+ "xgp2", -+ "xgp3", -+ "crypto", -+ "fe", -+ "trgpll", -+ "sgmii_tx250m", -+ "sgmii_rx250m", -+ "sgmii_cdr_ref", -+ "sgmii_cdr_fb", -+ "sgmii2_tx250m", -+ "sgmii2_rx250m", -+ "sgmii2_cdr_ref", -+ "sgmii2_cdr_fb", -+ "sgmii_ck", -+ "eth2pll", -+ "wocpu0", -+ "wocpu1", -+ "netsys0", -+ "netsys1", -+ "ethwarp_wocpu2", -+ "ethwarp_wocpu1", -+ "ethwarp_wocpu0", -+ "top_usxgmii0_sel", -+ "top_usxgmii1_sel", -+ "top_sgm0_sel", -+ "top_sgm1_sel", -+ "top_xfi_phy0_xtal_sel", -+ "top_xfi_phy1_xtal_sel", -+ "top_eth_gmii_sel", -+ "top_eth_refck_50m_sel", -+ "top_eth_sys_200m_sel", -+ "top_eth_sys_sel", -+ "top_eth_xgmii_sel", -+ "top_eth_mii_sel", -+ "top_netsys_sel", -+ "top_netsys_500m_sel", -+ "top_netsys_pao_2x_sel", -+ "top_netsys_sync_250m_sel", -+ "top_netsys_ppefb_250m_sel", -+ "top_netsys_warp_sel", - }; - - void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) -@@ -1207,10 +1299,19 @@ static void mtk_tx_set_dma_desc_v2(struc - data |= TX_DMA_LS0; - WRITE_ONCE(desc->txd3, data); - -- if (mac->id == MTK_GMAC3_ID) -- data = PSE_GDM3_PORT; -- else -- data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */ -+ /* set forward port */ -+ switch (mac->id) { -+ case MTK_GMAC1_ID: -+ data = PSE_GDM1_PORT << TX_DMA_FPORT_SHIFT_V2; -+ break; -+ case MTK_GMAC2_ID: -+ data = PSE_GDM2_PORT << TX_DMA_FPORT_SHIFT_V2; -+ break; -+ case MTK_GMAC3_ID: -+ data = PSE_GDM3_PORT << TX_DMA_FPORT_SHIFT_V2; -+ break; -+ } -+ - data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid); - WRITE_ONCE(desc->txd4, data); - -@@ -4957,6 +5058,25 @@ static const struct mtk_soc_data mt7986_ - }, - }; - -+static const struct mtk_soc_data mt7988_data = { -+ .reg_map = &mt7988_reg_map, -+ .ana_rgc3 = 0x128, -+ .caps = MT7988_CAPS, -+ .hw_features = MTK_HW_FEATURES, -+ .required_clks = MT7988_CLKS_BITMAP, -+ .required_pctl = false, -+ .num_devs = 3, -+ .txrx = { -+ .txd_size = sizeof(struct mtk_tx_dma_v2), -+ .rxd_size = sizeof(struct mtk_rx_dma_v2), -+ .rx_irq_done_mask = MTK_RX_DONE_INT_V2, -+ .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, -+ .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, -+ .dma_len_offset = 8, -+ }, -+}; -+ -+ - static const struct mtk_soc_data rt5350_data = { - .reg_map = &mt7628_reg_map, - .caps = MT7628_CAPS, -@@ -4975,14 +5095,15 @@ static const struct mtk_soc_data rt5350_ - }; - - const struct of_device_id of_mtk_match[] = { -- { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data}, -- { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data}, -- { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, -- { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, -- { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data}, -- { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data}, -- { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data}, -- { .compatible = "ralink,rt5350-eth", .data = &rt5350_data}, -+ { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data }, -+ { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data }, -+ { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data }, -+ { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data }, -+ { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data }, -+ { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data }, -+ { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data }, -+ { .compatible = "mediatek,mt7988-eth", .data = &mt7988_data }, -+ { .compatible = "ralink,rt5350-eth", .data = &rt5350_data }, - {}, - }; - MODULE_DEVICE_TABLE(of, of_mtk_match); ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -116,7 +116,8 @@ - #define MTK_CDMP_EG_CTRL 0x404 - - /* GDM Exgress Control Register */ --#define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) -+#define MTK_GDMA_FWD_CFG(x) ((x == MTK_GMAC3_ID) ? \ -+ 0x540 : 0x500 + (x * 0x1000)) - #define MTK_GDMA_SPECIAL_TAG BIT(24) - #define MTK_GDMA_ICS_EN BIT(22) - #define MTK_GDMA_TCS_EN BIT(21) -@@ -650,6 +651,11 @@ enum mtk_clks_map { - MTK_CLK_GP0, - MTK_CLK_GP1, - MTK_CLK_GP2, -+ MTK_CLK_GP3, -+ MTK_CLK_XGP1, -+ MTK_CLK_XGP2, -+ MTK_CLK_XGP3, -+ MTK_CLK_CRYPTO, - MTK_CLK_FE, - MTK_CLK_TRGPLL, - MTK_CLK_SGMII_TX_250M, -@@ -666,57 +672,108 @@ enum mtk_clks_map { - MTK_CLK_WOCPU1, - MTK_CLK_NETSYS0, - MTK_CLK_NETSYS1, -+ MTK_CLK_ETHWARP_WOCPU2, -+ MTK_CLK_ETHWARP_WOCPU1, -+ MTK_CLK_ETHWARP_WOCPU0, -+ MTK_CLK_TOP_USXGMII_SBUS_0_SEL, -+ MTK_CLK_TOP_USXGMII_SBUS_1_SEL, -+ MTK_CLK_TOP_SGM_0_SEL, -+ MTK_CLK_TOP_SGM_1_SEL, -+ MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL, -+ MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL, -+ MTK_CLK_TOP_ETH_GMII_SEL, -+ MTK_CLK_TOP_ETH_REFCK_50M_SEL, -+ MTK_CLK_TOP_ETH_SYS_200M_SEL, -+ MTK_CLK_TOP_ETH_SYS_SEL, -+ MTK_CLK_TOP_ETH_XGMII_SEL, -+ MTK_CLK_TOP_ETH_MII_SEL, -+ MTK_CLK_TOP_NETSYS_SEL, -+ MTK_CLK_TOP_NETSYS_500M_SEL, -+ MTK_CLK_TOP_NETSYS_PAO_2X_SEL, -+ MTK_CLK_TOP_NETSYS_SYNC_250M_SEL, -+ MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL, -+ MTK_CLK_TOP_NETSYS_WARP_SEL, - MTK_CLK_MAX - }; - --#define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ -- BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \ -- BIT(MTK_CLK_TRGPLL)) --#define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ -- BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ -- BIT(MTK_CLK_GP2) | \ -- BIT(MTK_CLK_SGMII_TX_250M) | \ -- BIT(MTK_CLK_SGMII_RX_250M) | \ -- BIT(MTK_CLK_SGMII_CDR_REF) | \ -- BIT(MTK_CLK_SGMII_CDR_FB) | \ -- BIT(MTK_CLK_SGMII_CK) | \ -- BIT(MTK_CLK_ETH2PLL)) -+#define MT7623_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \ -+ BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \ -+ BIT_ULL(MTK_CLK_TRGPLL)) -+#define MT7622_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \ -+ BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \ -+ BIT_ULL(MTK_CLK_GP2) | \ -+ BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ -+ BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ -+ BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ -+ BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ -+ BIT_ULL(MTK_CLK_SGMII_CK) | \ -+ BIT_ULL(MTK_CLK_ETH2PLL)) - #define MT7621_CLKS_BITMAP (0) - #define MT7628_CLKS_BITMAP (0) --#define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ -- BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ -- BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \ -- BIT(MTK_CLK_SGMII_TX_250M) | \ -- BIT(MTK_CLK_SGMII_RX_250M) | \ -- BIT(MTK_CLK_SGMII_CDR_REF) | \ -- BIT(MTK_CLK_SGMII_CDR_FB) | \ -- BIT(MTK_CLK_SGMII2_TX_250M) | \ -- BIT(MTK_CLK_SGMII2_RX_250M) | \ -- BIT(MTK_CLK_SGMII2_CDR_REF) | \ -- BIT(MTK_CLK_SGMII2_CDR_FB) | \ -- BIT(MTK_CLK_SGMII_CK) | \ -- BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP)) --#define MT7981_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \ -- BIT(MTK_CLK_WOCPU0) | \ -- BIT(MTK_CLK_SGMII_TX_250M) | \ -- BIT(MTK_CLK_SGMII_RX_250M) | \ -- BIT(MTK_CLK_SGMII_CDR_REF) | \ -- BIT(MTK_CLK_SGMII_CDR_FB) | \ -- BIT(MTK_CLK_SGMII2_TX_250M) | \ -- BIT(MTK_CLK_SGMII2_RX_250M) | \ -- BIT(MTK_CLK_SGMII2_CDR_REF) | \ -- BIT(MTK_CLK_SGMII2_CDR_FB) | \ -- BIT(MTK_CLK_SGMII_CK)) --#define MT7986_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \ -- BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \ -- BIT(MTK_CLK_SGMII_TX_250M) | \ -- BIT(MTK_CLK_SGMII_RX_250M) | \ -- BIT(MTK_CLK_SGMII_CDR_REF) | \ -- BIT(MTK_CLK_SGMII_CDR_FB) | \ -- BIT(MTK_CLK_SGMII2_TX_250M) | \ -- BIT(MTK_CLK_SGMII2_RX_250M) | \ -- BIT(MTK_CLK_SGMII2_CDR_REF) | \ -- BIT(MTK_CLK_SGMII2_CDR_FB)) -+#define MT7629_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \ -+ BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \ -+ BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_FE) | \ -+ BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ -+ BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ -+ BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ -+ BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ -+ BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ -+ BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ -+ BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ -+ BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \ -+ BIT_ULL(MTK_CLK_SGMII_CK) | \ -+ BIT_ULL(MTK_CLK_ETH2PLL) | BIT_ULL(MTK_CLK_SGMIITOP)) -+#define MT7981_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_GP1) | \ -+ BIT_ULL(MTK_CLK_WOCPU0) | \ -+ BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ -+ BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ -+ BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ -+ BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ -+ BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ -+ BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ -+ BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ -+ BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \ -+ BIT_ULL(MTK_CLK_SGMII_CK)) -+#define MT7986_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_GP1) | \ -+ BIT_ULL(MTK_CLK_WOCPU1) | BIT_ULL(MTK_CLK_WOCPU0) | \ -+ BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ -+ BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ -+ BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ -+ BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ -+ BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ -+ BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ -+ BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ -+ BIT_ULL(MTK_CLK_SGMII2_CDR_FB)) -+#define MT7988_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_ESW) | \ -+ BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \ -+ BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \ -+ BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \ -+ BIT_ULL(MTK_CLK_CRYPTO) | \ -+ BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ -+ BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ -+ BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ -+ BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ -+ BIT_ULL(MTK_CLK_ETHWARP_WOCPU2) | \ -+ BIT_ULL(MTK_CLK_ETHWARP_WOCPU1) | \ -+ BIT_ULL(MTK_CLK_ETHWARP_WOCPU0) | \ -+ BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_0_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_1_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_SGM_0_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_SGM_1_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_ETH_SYS_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_ETH_XGMII_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_ETH_MII_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_NETSYS_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_NETSYS_500M_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_NETSYS_PAO_2X_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_NETSYS_SYNC_250M_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_NETSYS_WARP_SEL)) - - enum mtk_dev_state { - MTK_HW_INIT, -@@ -844,6 +901,7 @@ enum mkt_eth_capabilities { - MTK_RGMII_BIT = 0, - MTK_TRGMII_BIT, - MTK_SGMII_BIT, -+ MTK_USXGMII_BIT, - MTK_ESW_BIT, - MTK_GEPHY_BIT, - MTK_MUX_BIT, -@@ -866,6 +924,8 @@ enum mkt_eth_capabilities { - MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, - MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, - MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, -+ MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT, -+ MTK_ETH_MUX_GMAC123_TO_USXGMII_BIT, - - /* PATH BITS */ - MTK_ETH_PATH_GMAC1_RGMII_BIT, -@@ -874,13 +934,18 @@ enum mkt_eth_capabilities { - MTK_ETH_PATH_GMAC2_RGMII_BIT, - MTK_ETH_PATH_GMAC2_SGMII_BIT, - MTK_ETH_PATH_GMAC2_GEPHY_BIT, -+ MTK_ETH_PATH_GMAC3_SGMII_BIT, - MTK_ETH_PATH_GDM1_ESW_BIT, -+ MTK_ETH_PATH_GMAC1_USXGMII_BIT, -+ MTK_ETH_PATH_GMAC2_USXGMII_BIT, -+ MTK_ETH_PATH_GMAC3_USXGMII_BIT, - }; - - /* Supported hardware group on SoCs */ - #define MTK_RGMII BIT_ULL(MTK_RGMII_BIT) - #define MTK_TRGMII BIT_ULL(MTK_TRGMII_BIT) - #define MTK_SGMII BIT_ULL(MTK_SGMII_BIT) -+#define MTK_USXGMII BIT_ULL(MTK_USXGMII_BIT) - #define MTK_ESW BIT_ULL(MTK_ESW_BIT) - #define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT) - #define MTK_MUX BIT_ULL(MTK_MUX_BIT) -@@ -907,6 +972,10 @@ enum mkt_eth_capabilities { - BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) - #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ - BIT_ULL(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) -+#define MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII \ -+ BIT_ULL(MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT) -+#define MTK_ETH_MUX_GMAC123_TO_USXGMII \ -+ BIT_ULL(MTK_ETH_MUX_GMAC123_TO_USXGMII_BIT) - - /* Supported path present on SoCs */ - #define MTK_ETH_PATH_GMAC1_RGMII BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT) -@@ -915,7 +984,11 @@ enum mkt_eth_capabilities { - #define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT) - #define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT) - #define MTK_ETH_PATH_GMAC2_GEPHY BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT) -+#define MTK_ETH_PATH_GMAC3_SGMII BIT_ULL(MTK_ETH_PATH_GMAC3_SGMII_BIT) - #define MTK_ETH_PATH_GDM1_ESW BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT) -+#define MTK_ETH_PATH_GMAC1_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC1_USXGMII_BIT) -+#define MTK_ETH_PATH_GMAC2_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC2_USXGMII_BIT) -+#define MTK_ETH_PATH_GMAC3_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC3_USXGMII_BIT) - - #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) - #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) -@@ -923,7 +996,11 @@ enum mkt_eth_capabilities { - #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) - #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) - #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) -+#define MTK_GMAC3_SGMII (MTK_ETH_PATH_GMAC3_SGMII | MTK_SGMII) - #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) -+#define MTK_GMAC1_USXGMII (MTK_ETH_PATH_GMAC1_USXGMII | MTK_USXGMII) -+#define MTK_GMAC2_USXGMII (MTK_ETH_PATH_GMAC2_USXGMII | MTK_USXGMII) -+#define MTK_GMAC3_USXGMII (MTK_ETH_PATH_GMAC3_USXGMII | MTK_USXGMII) - - /* MUXes present on SoCs */ - /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ -@@ -946,6 +1023,12 @@ enum mkt_eth_capabilities { - #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ - (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) - -+#define MTK_MUX_GMAC123_TO_GEPHY_SGMII \ -+ (MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII | MTK_MUX) -+ -+#define MTK_MUX_GMAC123_TO_USXGMII \ -+ (MTK_ETH_MUX_GMAC123_TO_USXGMII | MTK_MUX | MTK_INFRA) -+ - #ifdef CONFIG_SOC_MT7621 - #define MTK_CAP_MASK MTK_NETSYS_V2 - #else -@@ -984,9 +1067,17 @@ enum mkt_eth_capabilities { - MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \ - MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1) - --#define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ -- MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ -- MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1) -+#define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ -+ MTK_MUX_GMAC12_TO_GEPHY_SGMII | \ -+ MTK_QDMA | MTK_NETSYS_V2 | \ -+ MTK_RSTCTRL_PPE1) -+ -+#define MT7988_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ -+ MTK_GMAC3_SGMII | MTK_QDMA | \ -+ MTK_MUX_GMAC123_TO_GEPHY_SGMII | \ -+ MTK_NETSYS_V3 | MTK_RSTCTRL_PPE1 | \ -+ MTK_GMAC1_USXGMII | MTK_GMAC2_USXGMII | \ -+ MTK_GMAC3_USXGMII | MTK_MUX_GMAC123_TO_USXGMII) - - struct mtk_tx_dma_desc_info { - dma_addr_t addr; -@@ -1072,7 +1163,7 @@ struct mtk_soc_data { - const struct mtk_reg_map *reg_map; - u32 ana_rgc3; - u64 caps; -- u32 required_clks; -+ u64 required_clks; - bool required_pctl; - u8 offload_version; - u8 hash_offset; diff --git a/target/linux/generic/pending-5.15/737-07-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch b/target/linux/generic/pending-5.15/737-07-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch deleted file mode 100644 index 4518bcb510a..00000000000 --- a/target/linux/generic/pending-5.15/737-07-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch +++ /dev/null @@ -1,1867 +0,0 @@ -From 3d833ad2cfc1ab503d9aae2967b7f10811bb3c9c Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Wed, 1 Mar 2023 11:56:04 +0000 -Subject: [PATCH 7/7] net: ethernet: mtk_eth_soc: add paths and SerDes modes - for MT7988 - -MT7988 comes with a built-in 2.5G PHY as well as -USXGMII/10GBase-KR/5GBase-KR compatible SerDes lanes for external PHYs. -Add support for configuring the MAC and SerDes parts for the new paths. - -Signed-off-by: Daniel Golle ---- - drivers/net/ethernet/mediatek/Kconfig | 7 + - drivers/net/ethernet/mediatek/Makefile | 1 + - drivers/net/ethernet/mediatek/mtk_eth_path.c | 154 +++- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 270 +++++- - drivers/net/ethernet/mediatek/mtk_eth_soc.h | 194 ++++- - drivers/net/ethernet/mediatek/mtk_usxgmii.c | 835 +++++++++++++++++++ - 6 files changed, 1428 insertions(+), 33 deletions(-) - create mode 100644 drivers/net/ethernet/mediatek/mtk_usxgmii.c - ---- a/drivers/net/ethernet/mediatek/Kconfig -+++ b/drivers/net/ethernet/mediatek/Kconfig -@@ -24,6 +24,13 @@ config NET_MEDIATEK_SOC - This driver supports the gigabit ethernet MACs in the - MediaTek SoC family. - -+config NET_MEDIATEK_SOC_USXGMII -+ bool "Support USXGMII SerDes on MT7988" -+ depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST -+ def_bool NET_MEDIATEK_SOC != n -+ help -+ Include support for 10G SerDes which can be found on MT7988. -+ - config NET_MEDIATEK_STAR_EMAC - tristate "MediaTek STAR Ethernet MAC support" - select PHYLIB ---- a/drivers/net/ethernet/mediatek/Makefile -+++ b/drivers/net/ethernet/mediatek/Makefile -@@ -5,6 +5,7 @@ - - obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o - mtk_eth-y := mtk_eth_soc.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o -+mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_USXGMII) += mtk_usxgmii.o - mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o mtk_wed_mcu.o mtk_wed_wo.o - ifdef CONFIG_DEBUG_FS - mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_debugfs.o ---- a/drivers/net/ethernet/mediatek/mtk_eth_path.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c -@@ -31,10 +31,20 @@ static const char *mtk_eth_path_name(u64 - return "gmac2_rgmii"; - case MTK_ETH_PATH_GMAC2_SGMII: - return "gmac2_sgmii"; -+ case MTK_ETH_PATH_GMAC2_2P5GPHY: -+ return "gmac2_2p5gphy"; - case MTK_ETH_PATH_GMAC2_GEPHY: - return "gmac2_gephy"; -+ case MTK_ETH_PATH_GMAC3_SGMII: -+ return "gmac3_sgmii"; - case MTK_ETH_PATH_GDM1_ESW: - return "gdm1_esw"; -+ case MTK_ETH_PATH_GMAC1_USXGMII: -+ return "gmac1_usxgmii"; -+ case MTK_ETH_PATH_GMAC2_USXGMII: -+ return "gmac2_usxgmii"; -+ case MTK_ETH_PATH_GMAC3_USXGMII: -+ return "gmac3_usxgmii"; - default: - return "unknown path"; - } -@@ -42,8 +52,8 @@ static const char *mtk_eth_path_name(u64 - - static int set_mux_gdm1_to_gmac1_esw(struct mtk_eth *eth, u64 path) - { -+ u32 val, mask, set, reg; - bool updated = true; -- u32 val, mask, set; - - switch (path) { - case MTK_ETH_PATH_GMAC1_SGMII: -@@ -59,10 +69,15 @@ static int set_mux_gdm1_to_gmac1_esw(str - break; - } - -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) -+ reg = MTK_MAC_MISC_V3; -+ else -+ reg = MTK_MAC_MISC; -+ - if (updated) { -- val = mtk_r32(eth, MTK_MAC_MISC); -+ val = mtk_r32(eth, reg); - val = (val & mask) | set; -- mtk_w32(eth, val, MTK_MAC_MISC); -+ mtk_w32(eth, val, reg); - } - - dev_dbg(eth->dev, "path %s in %s updated = %d\n", -@@ -125,6 +140,31 @@ static int set_mux_u3_gmac2_to_qphy(stru - return 0; - } - -+static int set_mux_gmac2_to_2p5gphy(struct mtk_eth *eth, u64 path) -+{ -+ unsigned int val = 0; -+ bool updated = true; -+ int mac_id = 0; -+ -+ regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); -+ -+ switch (path) { -+ case MTK_ETH_PATH_GMAC2_2P5GPHY: -+ val &= ~(u32)SYSCFG0_SGMII_GMAC2_V2; -+ mac_id = MTK_GMAC2_ID; -+ break; -+ default: -+ updated = false; -+ break; -+ }; -+ -+ if (updated) -+ regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, -+ SYSCFG0_SGMII_MASK, val); -+ -+ return 0; -+} -+ - static int set_mux_gmac1_gmac2_to_sgmii_rgmii(struct mtk_eth *eth, u64 path) - { - unsigned int val = 0; -@@ -163,7 +203,61 @@ static int set_mux_gmac1_gmac2_to_sgmii_ - return 0; - } - --static int set_mux_gmac12_to_gephy_sgmii(struct mtk_eth *eth, u64 path) -+static int set_mux_gmac123_to_usxgmii(struct mtk_eth *eth, u64 path) -+{ -+ unsigned int val = 0; -+ bool updated = true; -+ int mac_id = 0; -+ -+ dev_dbg(eth->dev, "path %s in %s updated = %d\n", -+ mtk_eth_path_name(path), __func__, updated); -+ -+ /* Disable SYSCFG1 SGMII */ -+ regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); -+ -+ switch (path) { -+ case MTK_ETH_PATH_GMAC1_USXGMII: -+ val &= ~(u32)SYSCFG0_SGMII_GMAC1_V2; -+ mac_id = MTK_GMAC1_ID; -+ break; -+ case MTK_ETH_PATH_GMAC2_USXGMII: -+ val &= ~(u32)SYSCFG0_SGMII_GMAC2_V2; -+ mac_id = MTK_GMAC2_ID; -+ break; -+ case MTK_ETH_PATH_GMAC3_USXGMII: -+ val &= ~(u32)SYSCFG0_SGMII_GMAC3_V2; -+ mac_id = MTK_GMAC3_ID; -+ break; -+ default: -+ updated = false; -+ }; -+ -+ if (updated) { -+ regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, -+ SYSCFG0_SGMII_MASK, val); -+ -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3) && -+ mac_id == MTK_GMAC2_ID) { -+ regmap_update_bits(eth->infra, -+ TOP_MISC_NETSYS_PCS_MUX, -+ NETSYS_PCS_MUX_MASK, -+ MUX_G2_USXGMII_SEL); -+ } -+ } -+ -+ /* Enable XGDM Path */ -+ val = mtk_r32(eth, MTK_GDMA_EG_CTRL(mac_id)); -+ val |= MTK_GDMA_XGDM_SEL; -+ mtk_w32(eth, val, MTK_GDMA_EG_CTRL(mac_id)); -+ -+ dev_dbg(eth->dev, "path %s in %s updated = %d\n", -+ mtk_eth_path_name(path), __func__, updated); -+ -+ -+ return 0; -+} -+ -+static int set_mux_gmac123_to_gephy_sgmii(struct mtk_eth *eth, u64 path) - { - unsigned int val = 0; - bool updated = true; -@@ -180,6 +274,9 @@ static int set_mux_gmac12_to_gephy_sgmii - case MTK_ETH_PATH_GMAC2_SGMII: - val |= SYSCFG0_SGMII_GMAC2_V2; - break; -+ case MTK_ETH_PATH_GMAC3_SGMII: -+ val |= SYSCFG0_SGMII_GMAC3_V2; -+ break; - default: - updated = false; - } -@@ -208,13 +305,25 @@ static const struct mtk_eth_muxc mtk_eth - .cap_bit = MTK_ETH_MUX_U3_GMAC2_TO_QPHY, - .set_path = set_mux_u3_gmac2_to_qphy, - }, { -+ .name = "mux_gmac2_to_2p5gphy", -+ .cap_bit = MTK_ETH_MUX_GMAC2_TO_2P5GPHY, -+ .set_path = set_mux_gmac2_to_2p5gphy, -+ }, { - .name = "mux_gmac1_gmac2_to_sgmii_rgmii", - .cap_bit = MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII, - .set_path = set_mux_gmac1_gmac2_to_sgmii_rgmii, - }, { - .name = "mux_gmac12_to_gephy_sgmii", - .cap_bit = MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII, -- .set_path = set_mux_gmac12_to_gephy_sgmii, -+ .set_path = set_mux_gmac123_to_gephy_sgmii, -+ }, { -+ .name = "mux_gmac123_to_gephy_sgmii", -+ .cap_bit = MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII, -+ .set_path = set_mux_gmac123_to_gephy_sgmii, -+ }, { -+ .name = "mux_gmac123_to_usxgmii", -+ .cap_bit = MTK_ETH_MUX_GMAC123_TO_USXGMII, -+ .set_path = set_mux_gmac123_to_usxgmii, - }, - }; - -@@ -243,16 +352,46 @@ static int mtk_eth_mux_setup(struct mtk_ - } - } - -+ dev_dbg(eth->dev, "leaving mux_setup %s\n", -+ mtk_eth_path_name(path)); -+ - out: - return err; - } - -+int mtk_gmac_usxgmii_path_setup(struct mtk_eth *eth, int mac_id) -+{ -+ u64 path; -+ -+ path = (mac_id == MTK_GMAC1_ID) ? MTK_ETH_PATH_GMAC1_USXGMII : -+ (mac_id == MTK_GMAC2_ID) ? MTK_ETH_PATH_GMAC2_USXGMII : -+ MTK_ETH_PATH_GMAC3_USXGMII; -+ -+ /* Setup proper MUXes along the path */ -+ return mtk_eth_mux_setup(eth, path); -+} -+ - int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id) - { - u64 path; - -- path = (mac_id == 0) ? MTK_ETH_PATH_GMAC1_SGMII : -- MTK_ETH_PATH_GMAC2_SGMII; -+ path = (mac_id == MTK_GMAC1_ID) ? MTK_ETH_PATH_GMAC1_SGMII : -+ (mac_id == MTK_GMAC2_ID) ? MTK_ETH_PATH_GMAC2_SGMII : -+ MTK_ETH_PATH_GMAC3_SGMII; -+ -+ /* Setup proper MUXes along the path */ -+ return mtk_eth_mux_setup(eth, path); -+} -+ -+int mtk_gmac_2p5gphy_path_setup(struct mtk_eth *eth, int mac_id) -+{ -+ u64 path = 0; -+ -+ if (mac_id == MTK_GMAC2_ID) -+ path = MTK_ETH_PATH_GMAC2_2P5GPHY; -+ -+ if (!path) -+ return -EINVAL; - - /* Setup proper MUXes along the path */ - return mtk_eth_mux_setup(eth, path); -@@ -282,4 +421,3 @@ int mtk_gmac_rgmii_path_setup(struct mtk - /* Setup proper MUXes along the path */ - return mtk_eth_mux_setup(eth, path); - } -- ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -437,6 +437,23 @@ static void mtk_gmac0_rgmii_adjust(struc - mtk_w32(eth, val, TRGMII_TCK_CTRL); - } - -+static void mtk_setup_bridge_switch(struct mtk_eth *eth) -+{ -+ int val; -+ -+ /* Force Port1 XGMAC Link Up */ -+ val = mtk_r32(eth, MTK_XGMAC_STS(MTK_GMAC1_ID)); -+ mtk_w32(eth, val | MTK_XGMAC_FORCE_LINK(MTK_GMAC1_ID), -+ MTK_XGMAC_STS(MTK_GMAC1_ID)); -+ -+ /* Adjust GSW bridge IPG to 11*/ -+ val = mtk_r32(eth, MTK_GSW_CFG); -+ val &= ~(GSWTX_IPG_MASK | GSWRX_IPG_MASK); -+ val |= (GSW_IPG_11 << GSWTX_IPG_SHIFT) | -+ (GSW_IPG_11 << GSWRX_IPG_SHIFT); -+ mtk_w32(eth, val, MTK_GSW_CFG); -+} -+ - static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config, - phy_interface_t interface) - { -@@ -451,6 +468,12 @@ static struct phylink_pcs *mtk_mac_selec - 0 : mac->id; - - return eth->sgmii_pcs[sid]; -+ } else if ((interface == PHY_INTERFACE_MODE_USXGMII || -+ interface == PHY_INTERFACE_MODE_10GKR || -+ interface == PHY_INTERFACE_MODE_5GBASER) && -+ MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3) && -+ mac->id != MTK_GMAC1_ID) { -+ return mtk_usxgmii_select_pcs(eth, mac->id); - } - - return NULL; -@@ -462,7 +485,7 @@ static void mtk_mac_config(struct phylin - struct mtk_mac *mac = container_of(config, struct mtk_mac, - phylink_config); - struct mtk_eth *eth = mac->hw; -- int val, ge_mode, err = 0; -+ int val, ge_mode, force_link, err = 0; - u32 i; - - /* MT76x8 has no hardware settings between for the MAC */ -@@ -506,6 +529,23 @@ static void mtk_mac_config(struct phylin - goto init_err; - } - break; -+ case PHY_INTERFACE_MODE_USXGMII: -+ case PHY_INTERFACE_MODE_10GKR: -+ case PHY_INTERFACE_MODE_5GBASER: -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII)) { -+ err = mtk_gmac_usxgmii_path_setup(eth, mac->id); -+ if (err) -+ goto init_err; -+ } -+ break; -+ case PHY_INTERFACE_MODE_INTERNAL: -+ if (mac->id == MTK_GMAC2_ID && -+ MTK_HAS_CAPS(eth->soc->caps, MTK_2P5GPHY)) { -+ err = mtk_gmac_2p5gphy_path_setup(eth, mac->id); -+ if (err) -+ goto init_err; -+ } -+ break; - default: - goto err_phy; - } -@@ -584,14 +624,78 @@ static void mtk_mac_config(struct phylin - SYSCFG0_SGMII_MASK, - ~(u32)SYSCFG0_SGMII_MASK); - -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { -+ mtk_xfi_pll_enable(eth); -+ mtk_sgmii_reset(eth, mac->id); -+ if (phylink_autoneg_inband(mode)) -+ mtk_sgmii_setup_phya_gen1(eth, mac->id); -+ else -+ mtk_sgmii_setup_phya_gen2(eth, mac->id); -+ } - /* Save the syscfg0 value for mac_finish */ - mac->syscfg0 = val; -- } else if (phylink_autoneg_inband(mode)) { -+ } else if (state->interface != PHY_INTERFACE_MODE_USXGMII && -+ state->interface != PHY_INTERFACE_MODE_10GKR && -+ state->interface != PHY_INTERFACE_MODE_5GBASER && -+ phylink_autoneg_inband(mode)) { - dev_err(eth->dev, -- "In-band mode not supported in non SGMII mode!\n"); -+ "In-band mode not supported in non-SerDes modes!\n"); - return; - } - -+ /* Setup gmac */ -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3) && -+ (mtk_interface_mode_is_xgmii(state->interface) || -+ mac->interface == PHY_INTERFACE_MODE_INTERNAL)) { -+ mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id)); -+ mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id)); -+ -+ switch (mac->id) { -+ case MTK_GMAC1_ID: -+ mtk_setup_bridge_switch(eth); -+ break; -+ case MTK_GMAC2_ID: -+ force_link = (mac->interface == -+ PHY_INTERFACE_MODE_INTERNAL) ? -+ MTK_XGMAC_FORCE_LINK(mac->id) : 0; -+ val = mtk_r32(eth, MTK_XGMAC_STS(mac->id)); -+ mtk_w32(eth, val | force_link, -+ MTK_XGMAC_STS(mac->id)); -+ break; -+ case MTK_GMAC3_ID: -+ val = mtk_r32(eth, MTK_XGMAC_STS(mac->id)); -+ mtk_w32(eth, val | MTK_XGMAC_FORCE_LINK(mac->id), -+ MTK_XGMAC_STS(mac->id)); -+ break; -+ } -+ } else { -+ val = mtk_r32(eth, MTK_GDMA_EG_CTRL(mac->id)); -+ mtk_w32(eth, val & ~MTK_GDMA_XGDM_SEL, -+ MTK_GDMA_EG_CTRL(mac->id)); -+ -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { -+ switch (mac->id) { -+ case MTK_GMAC2_ID: -+ case MTK_GMAC3_ID: -+ val = mtk_r32(eth, MTK_XGMAC_STS(mac->id)); -+ mtk_w32(eth, -+ val & ~MTK_XGMAC_FORCE_LINK(mac->id), -+ MTK_XGMAC_STS(mac->id)); -+ break; -+ } -+ } -+ -+/* -+ if (mac->type != mac_type) { -+ if (atomic_read(&reset_pending) == 0) { -+ atomic_inc(&force); -+ schedule_work(ð->pending_work); -+ atomic_inc(&reset_pending); -+ } else -+ atomic_dec(&reset_pending); -+ } -+*/ -+ } - return; - - err_phy: -@@ -632,11 +736,40 @@ static int mtk_mac_finish(struct phylink - return 0; - } - --static void mtk_mac_pcs_get_state(struct phylink_config *config, -+static void mtk_xgdm_pcs_get_state(struct mtk_mac *mac, -+ struct phylink_link_state *state) -+{ -+ u32 sts = mtk_r32(mac->hw, MTK_XGMAC_STS(mac->id)); -+ -+ if (mac->id == MTK_GMAC2_ID) -+ sts = sts >> 16; -+ -+ state->link = FIELD_GET(MTK_USXGMII_PCS_LINK, sts); -+ if (!state->link) -+ return; -+ -+ state->duplex = DUPLEX_FULL; -+ state->interface = mac->interface; -+ -+ switch (FIELD_GET(MTK_USXGMII_PCS_MODE, sts)) { -+ case 0: -+ state->speed = SPEED_10000; -+ break; -+ case 1: -+ state->speed = SPEED_5000; -+ break; -+ case 2: -+ state->speed = SPEED_2500; -+ break; -+ case 3: -+ state->speed = SPEED_1000; -+ break; -+ } -+} -+ -+static void mtk_gdm_pcs_get_state(struct mtk_mac *mac, - struct phylink_link_state *state) - { -- struct mtk_mac *mac = container_of(config, struct mtk_mac, -- phylink_config); - u32 pmsr = mtk_r32(mac->hw, MTK_MAC_MSR(mac->id)); - - state->link = (pmsr & MAC_MSR_LINK); -@@ -664,15 +797,35 @@ static void mtk_mac_pcs_get_state(struct - state->pause |= MLO_PAUSE_TX; - } - -+static void mtk_mac_pcs_get_state(struct phylink_config *config, -+ struct phylink_link_state *state) -+{ -+ struct mtk_mac *mac = container_of(config, struct mtk_mac, -+ phylink_config); -+ -+ if (mtk_interface_mode_is_xgmii(state->interface)) -+ mtk_xgdm_pcs_get_state(mac, state); -+ else -+ mtk_gdm_pcs_get_state(mac, state); -+} -+ - static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode, - phy_interface_t interface) - { - struct mtk_mac *mac = container_of(config, struct mtk_mac, - phylink_config); -- u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); -+ u32 mcr; - -- mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN); -- mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); -+ if (!mtk_interface_mode_is_xgmii(interface)) { -+ mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); -+ mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN); -+ mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); -+ } else if (mac->id != MTK_GMAC1_ID) { -+ mcr = mtk_r32(mac->hw, MTK_XMAC_MCR(mac->id)); -+ mcr &= 0xfffffff0; -+ mcr |= XMAC_MCR_TRX_DISABLE; -+ mtk_w32(mac->hw, mcr, MTK_XMAC_MCR(mac->id)); -+ } - } - - static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx, -@@ -744,13 +897,11 @@ static void mtk_set_queue_speed(struct m - mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); - } - --static void mtk_mac_link_up(struct phylink_config *config, -- struct phy_device *phy, -- unsigned int mode, phy_interface_t interface, -- int speed, int duplex, bool tx_pause, bool rx_pause) -+static void mtk_gdm_mac_link_up(struct mtk_mac *mac, -+ struct phy_device *phy, -+ unsigned int mode, phy_interface_t interface, -+ int speed, int duplex, bool tx_pause, bool rx_pause) - { -- struct mtk_mac *mac = container_of(config, struct mtk_mac, -- phylink_config); - u32 mcr; - - mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); -@@ -784,6 +935,47 @@ static void mtk_mac_link_up(struct phyli - mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); - } - -+static void mtk_xgdm_mac_link_up(struct mtk_mac *mac, -+ struct phy_device *phy, -+ unsigned int mode, phy_interface_t interface, -+ int speed, int duplex, bool tx_pause, bool rx_pause) -+{ -+ u32 mcr; -+ -+ if (mac->id == MTK_GMAC1_ID) -+ return; -+ -+ mcr = mtk_r32(mac->hw, MTK_XMAC_MCR(mac->id)); -+ -+ mcr &= ~(XMAC_MCR_FORCE_TX_FC | XMAC_MCR_FORCE_RX_FC); -+ /* Configure pause modes - -+ * phylink will avoid these for half duplex -+ */ -+ if (tx_pause) -+ mcr |= XMAC_MCR_FORCE_TX_FC; -+ if (rx_pause) -+ mcr |= XMAC_MCR_FORCE_RX_FC; -+ -+ mcr &= ~(XMAC_MCR_TRX_DISABLE); -+ mtk_w32(mac->hw, mcr, MTK_XMAC_MCR(mac->id)); -+} -+ -+static void mtk_mac_link_up(struct phylink_config *config, -+ struct phy_device *phy, -+ unsigned int mode, phy_interface_t interface, -+ int speed, int duplex, bool tx_pause, bool rx_pause) -+{ -+ struct mtk_mac *mac = container_of(config, struct mtk_mac, -+ phylink_config); -+ -+ if (mtk_interface_mode_is_xgmii(interface)) -+ mtk_xgdm_mac_link_up(mac, phy, mode, interface, speed, duplex, -+ tx_pause, rx_pause); -+ else -+ mtk_gdm_mac_link_up(mac, phy, mode, interface, speed, duplex, -+ tx_pause, rx_pause); -+} -+ - static const struct phylink_mac_ops mtk_phylink_ops = { - .validate = phylink_generic_validate, - .mac_select_pcs = mtk_mac_select_pcs, -@@ -836,10 +1028,21 @@ static int mtk_mdio_init(struct mtk_eth - } - divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63); - -+ /* Configure MDC Turbo Mode */ -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { -+ val = mtk_r32(eth, MTK_MAC_MISC_V3); -+ val |= MISC_MDC_TURBO; -+ mtk_w32(eth, val, MTK_MAC_MISC_V3); -+ } else { -+ val = mtk_r32(eth, MTK_PPSC); -+ val |= PPSC_MDC_TURBO; -+ mtk_w32(eth, val, MTK_PPSC); -+ } -+ - /* Configure MDC Divider */ - val = mtk_r32(eth, MTK_PPSC); - val &= ~PPSC_MDC_CFG; -- val |= FIELD_PREP(PPSC_MDC_CFG, divider) | PPSC_MDC_TURBO; -+ val |= FIELD_PREP(PPSC_MDC_CFG, divider); - mtk_w32(eth, val, MTK_PPSC); - - dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider); -@@ -4415,8 +4618,8 @@ static int mtk_add_mac(struct mtk_eth *e - const __be32 *_id = of_get_property(np, "reg", NULL); - phy_interface_t phy_mode; - struct phylink *phylink; -- struct mtk_mac *mac; - int id, err; -+ struct mtk_mac *mac; - int txqs = 1; - - if (!_id) { -@@ -4518,6 +4721,32 @@ static int mtk_add_mac(struct mtk_eth *e - mac->phylink_config.supported_interfaces); - } - -+ if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_USXGMII)) { -+ if (id == MTK_GMAC1_ID) { -+ mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | -+ MAC_SYM_PAUSE | -+ MAC_10000FD; -+ phy_interface_zero( -+ mac->phylink_config.supported_interfaces); -+ __set_bit(PHY_INTERFACE_MODE_INTERNAL, -+ mac->phylink_config.supported_interfaces); -+ } else { -+ mac->phylink_config.mac_capabilities |= MAC_5000FD | MAC_10000FD; -+ __set_bit(PHY_INTERFACE_MODE_5GBASER, -+ mac->phylink_config.supported_interfaces); -+ __set_bit(PHY_INTERFACE_MODE_10GKR, -+ mac->phylink_config.supported_interfaces); -+ __set_bit(PHY_INTERFACE_MODE_USXGMII, -+ mac->phylink_config.supported_interfaces); -+ } -+ } -+ -+ if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_2P5GPHY)) { -+ if (id == MTK_GMAC2_ID) -+ __set_bit(PHY_INTERFACE_MODE_INTERNAL, -+ mac->phylink_config.supported_interfaces); -+ } -+ - phylink = phylink_create(&mac->phylink_config, - of_fwnode_handle(mac->of_node), - phy_mode, &mtk_phylink_ops); -@@ -4705,6 +4934,13 @@ static int mtk_probe(struct platform_dev - - if (err) - return err; -+ } -+ -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII)) { -+ err = mtk_usxgmii_init(eth); -+ -+ if (err) -+ return err; - } - - if (eth->soc->required_pctl) { ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -126,6 +126,11 @@ - #define MTK_GDMA_TO_PDMA 0x0 - #define MTK_GDMA_DROP_ALL 0x7777 - -+/* GDM Egress Control Register */ -+#define MTK_GDMA_EG_CTRL(x) ((x == MTK_GMAC3_ID) ? \ -+ 0x544 : 0x504 + (x * 0x1000)) -+#define MTK_GDMA_XGDM_SEL BIT(31) -+ - /* Unicast Filter MAC Address Register - Low */ - #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) - -@@ -386,7 +391,26 @@ - #define PHY_IAC_TIMEOUT HZ - - #define MTK_MAC_MISC 0x1000c -+#define MTK_MAC_MISC_V3 0x10010 - #define MTK_MUX_TO_ESW BIT(0) -+#define MISC_MDC_TURBO BIT(4) -+ -+/* XMAC status registers */ -+#define MTK_XGMAC_STS(x) ((x == MTK_GMAC3_ID) ? 0x1001C : 0x1000C) -+#define MTK_XGMAC_FORCE_LINK(x) ((x == MTK_GMAC2_ID) ? BIT(31) : BIT(15)) -+#define MTK_USXGMII_PCS_LINK BIT(8) -+#define MTK_XGMAC_RX_FC BIT(5) -+#define MTK_XGMAC_TX_FC BIT(4) -+#define MTK_USXGMII_PCS_MODE GENMASK(3, 1) -+#define MTK_XGMAC_LINK_STS BIT(0) -+ -+/* GSW bridge registers */ -+#define MTK_GSW_CFG (0x10080) -+#define GSWTX_IPG_MASK GENMASK(19, 16) -+#define GSWTX_IPG_SHIFT 16 -+#define GSWRX_IPG_MASK GENMASK(3, 0) -+#define GSWRX_IPG_SHIFT 0 -+#define GSW_IPG_11 11 - - /* Mac control registers */ - #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) -@@ -411,6 +435,17 @@ - #define MAC_MCR_FORCE_LINK BIT(0) - #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE) - -+/* Mac EEE control registers */ -+#define MTK_MAC_EEE(x) (0x10104 + (x * 0x100)) -+#define MAC_EEE_WAKEUP_TIME_1000 GENMASK(31, 24) -+#define MAC_EEE_WAKEUP_TIME_100 GENMASK(23, 16) -+#define MAC_EEE_LPI_TXIDLE_THD GENMASK(15, 8) -+#define MAC_EEE_RESV0 GENMASK(7, 4) -+#define MAC_EEE_CKG_TXILDE BIT(3) -+#define MAC_EEE_CKG_RXLPI BIT(2) -+#define MAC_EEE_TX_DOWN_REQ BIT(1) -+#define MAC_EEE_LPI_MODE BIT(0) -+ - /* Mac status registers */ - #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100)) - #define MAC_MSR_EEE1G BIT(7) -@@ -455,6 +490,12 @@ - #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) - #define INTF_MODE_RGMII_10_100 0 - -+/* XFI Mac control registers */ -+#define MTK_XMAC_MCR(x) (0x12000 + ((x - 1) * 0x1000)) -+#define XMAC_MCR_TRX_DISABLE 0xf -+#define XMAC_MCR_FORCE_TX_FC BIT(5) -+#define XMAC_MCR_FORCE_RX_FC BIT(4) -+ - /* GPIO port control registers for GMAC 2*/ - #define GPIO_OD33_CTRL8 0x4c0 - #define GPIO_BIAS_CTRL 0xed0 -@@ -480,6 +521,7 @@ - #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) - #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) - #define SYSCFG0_SGMII_GMAC2_V2 BIT(8) -+#define SYSCFG0_SGMII_GMAC3_V2 BIT(7) - - - /* ethernet subsystem clock register */ -@@ -506,16 +548,91 @@ - #define ETHSYS_DMA_AG_MAP_QDMA BIT(1) - #define ETHSYS_DMA_AG_MAP_PPE BIT(2) - -+/* USXGMII subsystem config registers */ -+/* Register to control speed */ -+#define RG_PHY_TOP_SPEED_CTRL1 0x80C -+#define USXGMII_RATE_UPDATE_MODE BIT(31) -+#define USXGMII_MAC_CK_GATED BIT(29) -+#define USXGMII_IF_FORCE_EN BIT(28) -+#define USXGMII_RATE_ADAPT_MODE GENMASK(10, 8) -+#define USXGMII_RATE_ADAPT_MODE_X1 0 -+#define USXGMII_RATE_ADAPT_MODE_X2 1 -+#define USXGMII_RATE_ADAPT_MODE_X4 2 -+#define USXGMII_RATE_ADAPT_MODE_X10 3 -+#define USXGMII_RATE_ADAPT_MODE_X100 4 -+#define USXGMII_RATE_ADAPT_MODE_X5 5 -+#define USXGMII_RATE_ADAPT_MODE_X50 6 -+#define USXGMII_XFI_RX_MODE GENMASK(6, 4) -+#define USXGMII_XFI_RX_MODE_10G 0 -+#define USXGMII_XFI_RX_MODE_5G 1 -+#define USXGMII_XFI_TX_MODE GENMASK(2, 0) -+#define USXGMII_XFI_TX_MODE_10G 0 -+#define USXGMII_XFI_TX_MODE_5G 1 -+ -+/* Register to control PCS AN */ -+#define RG_PCS_AN_CTRL0 0x810 -+#define USXGMII_AN_RESTART BIT(31) -+#define USXGMII_AN_SYNC_CNT GENMASK(30, 11) -+#define USXGMII_AN_ENABLE BIT(0) -+ -+#define RG_PCS_AN_CTRL2 0x818 -+#define USXGMII_LINK_TIMER_IDLE_DETECT GENMASK(29, 20) -+#define USXGMII_LINK_TIMER_COMP_ACK_DETECT GENMASK(19, 10) -+#define USXGMII_LINK_TIMER_AN_RESTART GENMASK(9, 0) -+ -+/* Register to read PCS AN status */ -+#define RG_PCS_AN_STS0 0x81c -+#define USXGMII_LPA_SPEED_MASK GENMASK(11, 9) -+#define USXGMII_LPA_SPEED_10 0 -+#define USXGMII_LPA_SPEED_100 1 -+#define USXGMII_LPA_SPEED_1000 2 -+#define USXGMII_LPA_SPEED_10000 3 -+#define USXGMII_LPA_SPEED_2500 4 -+#define USXGMII_LPA_SPEED_5000 5 -+#define USXGMII_LPA_DUPLEX BIT(12) -+#define USXGMII_LPA_LINK BIT(15) -+#define USXGMII_LPA_LATCH BIT(31) -+ -+/* Register to control USXGMII XFI PLL digital */ -+#define XFI_PLL_DIG_GLB8 0x08 -+#define RG_XFI_PLL_EN BIT(31) -+ -+/* Register to control USXGMII XFI PLL analog */ -+#define XFI_PLL_ANA_GLB8 0x108 -+#define RG_XFI_PLL_ANA_SWWA 0x02283248 -+ - /* Infrasys subsystem config registers */ - #define INFRA_MISC2 0x70c - #define CO_QPHY_SEL BIT(0) - #define GEPHY_MAC_SEL BIT(1) - -+/* Toprgu subsystem config registers */ -+#define TOPRGU_SWSYSRST 0x18 -+#define SWSYSRST_UNLOCK_KEY GENMASK(31, 24) -+#define SWSYSRST_XFI_PLL_GRST BIT(16) -+#define SWSYSRST_XFI_PEXPT1_GRST BIT(15) -+#define SWSYSRST_XFI_PEXPT0_GRST BIT(14) -+#define SWSYSRST_XFI1_GRST BIT(13) -+#define SWSYSRST_XFI0_GRST BIT(12) -+#define SWSYSRST_SGMII1_GRST BIT(2) -+#define SWSYSRST_SGMII0_GRST BIT(1) -+#define TOPRGU_SWSYSRST_EN 0xFC -+ - /* Top misc registers */ -+#define TOP_MISC_NETSYS_PCS_MUX 0x84 -+#define NETSYS_PCS_MUX_MASK GENMASK(1, 0) -+#define MUX_G2_USXGMII_SEL BIT(1) -+#define MUX_HSGMII1_G1_SEL BIT(0) -+ - #define USB_PHY_SWITCH_REG 0x218 - #define QPHY_SEL_MASK GENMASK(1, 0) - #define SGMII_QPHY_SEL 0x2 - -+/* MDIO control */ -+#define MII_MMD_ACC_CTL_REG 0x0d -+#define MII_MMD_ADDR_DATA_REG 0x0e -+#define MMD_OP_MODE_DATA BIT(14) -+ - /* MT7628/88 specific stuff */ - #define MT7628_PDMA_OFFSET 0x0800 - #define MT7628_SDM_OFFSET 0x0c00 -@@ -809,13 +926,6 @@ enum mtk_gmac_id { - MTK_GMAC_ID_MAX - }; - --/* GDM Type */ --enum mtk_gdm_type { -- MTK_GDM_TYPE = 0, -- MTK_XGDM_TYPE, -- MTK_GDM_TYPE_MAX --}; -- - enum mtk_tx_buf_type { - MTK_TYPE_SKB, - MTK_TYPE_XDP_TX, -@@ -902,6 +1012,7 @@ enum mkt_eth_capabilities { - MTK_TRGMII_BIT, - MTK_SGMII_BIT, - MTK_USXGMII_BIT, -+ MTK_2P5GPHY_BIT, - MTK_ESW_BIT, - MTK_GEPHY_BIT, - MTK_MUX_BIT, -@@ -922,6 +1033,7 @@ enum mkt_eth_capabilities { - MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, - MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT, - MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, -+ MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT, - MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, - MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, - MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT, -@@ -933,6 +1045,7 @@ enum mkt_eth_capabilities { - MTK_ETH_PATH_GMAC1_SGMII_BIT, - MTK_ETH_PATH_GMAC2_RGMII_BIT, - MTK_ETH_PATH_GMAC2_SGMII_BIT, -+ MTK_ETH_PATH_GMAC2_2P5GPHY_BIT, - MTK_ETH_PATH_GMAC2_GEPHY_BIT, - MTK_ETH_PATH_GMAC3_SGMII_BIT, - MTK_ETH_PATH_GDM1_ESW_BIT, -@@ -946,6 +1059,7 @@ enum mkt_eth_capabilities { - #define MTK_TRGMII BIT_ULL(MTK_TRGMII_BIT) - #define MTK_SGMII BIT_ULL(MTK_SGMII_BIT) - #define MTK_USXGMII BIT_ULL(MTK_USXGMII_BIT) -+#define MTK_2P5GPHY BIT_ULL(MTK_2P5GPHY_BIT) - #define MTK_ESW BIT_ULL(MTK_ESW_BIT) - #define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT) - #define MTK_MUX BIT_ULL(MTK_MUX_BIT) -@@ -968,6 +1082,8 @@ enum mkt_eth_capabilities { - BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) - #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ - BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) -+#define MTK_ETH_MUX_GMAC2_TO_2P5GPHY \ -+ BIT_ULL(MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT) - #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ - BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) - #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ -@@ -983,6 +1099,7 @@ enum mkt_eth_capabilities { - #define MTK_ETH_PATH_GMAC1_SGMII BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT) - #define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT) - #define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT) -+#define MTK_ETH_PATH_GMAC2_2P5GPHY BIT_ULL(MTK_ETH_PATH_GMAC2_2P5GPHY_BIT) - #define MTK_ETH_PATH_GMAC2_GEPHY BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT) - #define MTK_ETH_PATH_GMAC3_SGMII BIT_ULL(MTK_ETH_PATH_GMAC3_SGMII_BIT) - #define MTK_ETH_PATH_GDM1_ESW BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT) -@@ -996,6 +1113,7 @@ enum mkt_eth_capabilities { - #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) - #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) - #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) -+#define MTK_GMAC2_2P5GPHY (MTK_ETH_PATH_GMAC2_2P5GPHY | MTK_2P5GPHY) - #define MTK_GMAC3_SGMII (MTK_ETH_PATH_GMAC3_SGMII | MTK_SGMII) - #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) - #define MTK_GMAC1_USXGMII (MTK_ETH_PATH_GMAC1_USXGMII | MTK_USXGMII) -@@ -1019,6 +1137,10 @@ enum mkt_eth_capabilities { - (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \ - MTK_SHARED_SGMII) - -+/* 2: GMAC2 -> XGMII */ -+#define MTK_MUX_GMAC2_TO_2P5GPHY \ -+ (MTK_ETH_MUX_GMAC2_TO_2P5GPHY | MTK_MUX | MTK_INFRA) -+ - /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */ - #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ - (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) -@@ -1077,7 +1199,8 @@ enum mkt_eth_capabilities { - MTK_MUX_GMAC123_TO_GEPHY_SGMII | \ - MTK_NETSYS_V3 | MTK_RSTCTRL_PPE1 | \ - MTK_GMAC1_USXGMII | MTK_GMAC2_USXGMII | \ -- MTK_GMAC3_USXGMII | MTK_MUX_GMAC123_TO_USXGMII) -+ MTK_GMAC3_USXGMII | MTK_MUX_GMAC123_TO_USXGMII | \ -+ MTK_GMAC2_2P5GPHY | MTK_MUX_GMAC2_TO_2P5GPHY) - - struct mtk_tx_dma_desc_info { - dma_addr_t addr; -@@ -1183,6 +1306,22 @@ struct mtk_soc_data { - - #define MTK_DMA_MONITOR_TIMEOUT msecs_to_jiffies(1000) - -+/* struct mtk_usxgmii_pcs - This structure holds each usxgmii regmap and -+ * associated data -+ * @regmap: The register map pointing at the range used to setup -+ * USXGMII modes -+ * @interface: Currently selected interface mode -+ * @id: The element is used to record the index of PCS -+ * @pcs: Phylink PCS structure -+ */ -+struct mtk_usxgmii_pcs { -+ struct mtk_eth *eth; -+ struct regmap *regmap; -+ phy_interface_t interface; -+ u8 id; -+ struct phylink_pcs pcs; -+}; -+ - /* struct mtk_eth - This is the main datasructure for holding the state - * of the driver - * @dev: The device pointer -@@ -1203,6 +1342,11 @@ struct mtk_soc_data { - * @infra: The register map pointing at the range used to setup - * SGMII and GePHY path - * @sgmii_pcs: Pointers to mtk-pcs-lynxi phylink_pcs instances -+ * @usxgmii_pll: The register map pointing at the range used to control -+ * the USXGMII SerDes PLL -+ * @regmap_pextp: The register map pointing at the range used to setup -+ * PHYA -+ * @usxgmii_pcs: Pointer to array of pointers to struct for USXGMII PCS - * @pctl: The register map pointing at the range used to setup - * GMAC port drive/slew values - * @dma_refcnt: track how many netdevs are using the DMA engine -@@ -1244,7 +1388,11 @@ struct mtk_eth { - unsigned long sysclk; - struct regmap *ethsys; - struct regmap *infra; -+ struct regmap *toprgu; - struct phylink_pcs **sgmii_pcs; -+ struct regmap *usxgmii_pll; -+ struct regmap **regmap_pextp; -+ struct mtk_usxgmii_pcs **usxgmii_pcs; - struct regmap *pctl; - bool hwlro; - refcount_t dma_refcnt; -@@ -1400,6 +1548,19 @@ static inline u32 mtk_get_ib2_multicast_ - return MTK_FOE_IB2_MULTICAST; - } - -+static inline bool mtk_interface_mode_is_xgmii(phy_interface_t interface) -+{ -+ switch (interface) { -+ case PHY_INTERFACE_MODE_USXGMII: -+ case PHY_INTERFACE_MODE_10GKR: -+ case PHY_INTERFACE_MODE_5GBASER: -+ return true; -+ break; -+ default: -+ return false; -+ } -+} -+ - /* read the hardware status register */ - void mtk_stats_update_mac(struct mtk_mac *mac); - -@@ -1407,8 +1568,10 @@ void mtk_w32(struct mtk_eth *eth, u32 va - u32 mtk_r32(struct mtk_eth *eth, unsigned reg); - - int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); -+int mtk_gmac_2p5gphy_path_setup(struct mtk_eth *eth, int mac_id); - int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); - int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); -+int mtk_gmac_usxgmii_path_setup(struct mtk_eth *eth, int mac_id); - - int mtk_eth_offload_init(struct mtk_eth *eth); - int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, -@@ -1418,5 +1581,20 @@ int mtk_flow_offload_cmd(struct mtk_eth - void mtk_flow_offload_cleanup(struct mtk_eth *eth, struct list_head *list); - void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev); - -+#ifdef CONFIG_NET_MEDIATEK_SOC_USXGMII -+struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int id); -+int mtk_usxgmii_init(struct mtk_eth *eth); -+int mtk_xfi_pll_enable(struct mtk_eth *eth); -+void mtk_sgmii_setup_phya_gen1(struct mtk_eth *eth, int mac_id); -+void mtk_sgmii_setup_phya_gen2(struct mtk_eth *eth, int mac_id); -+void mtk_sgmii_reset(struct mtk_eth *eth, int mac_id); -+#else -+static inline struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int id) { return NULL; } -+static inline int mtk_usxgmii_init(struct mtk_eth *eth) { return 0; } -+static inline int mtk_xfi_pll_enable(struct mtk_eth *eth) { return 0; } -+static inline void mtk_sgmii_setup_phya_gen1(struct mtk_eth *eth, int mac_id) { } -+static inline void mtk_sgmii_setup_phya_gen2(struct mtk_eth *eth, int mac_id) { } -+static inline void mtk_sgmii_reset(struct mtk_eth *eth, int mac_id) { } -+#endif /* NET_MEDIATEK_SOC_USXGMII */ - - #endif /* MTK_ETH_H */ ---- /dev/null -+++ b/drivers/net/ethernet/mediatek/mtk_usxgmii.c -@@ -0,0 +1,835 @@ -+/* SPDX-License-Identifier: GPL-2.0 -+ * -+ * Copyright (c) 2022 MediaTek Inc. -+ * Author: Henry Yen -+ * Daniel Golle -+ */ -+ -+#include -+#include -+#include -+#include "mtk_eth_soc.h" -+ -+static struct mtk_usxgmii_pcs *pcs_to_mtk_usxgmii_pcs(struct phylink_pcs *pcs) -+{ -+ return container_of(pcs, struct mtk_usxgmii_pcs, pcs); -+} -+ -+static int mtk_xfi_pextp_init(struct mtk_eth *eth) -+{ -+ struct device *dev = eth->dev; -+ struct device_node *r = dev->of_node; -+ struct device_node *np; -+ int i; -+ -+ eth->regmap_pextp = devm_kcalloc(dev, eth->soc->num_devs, sizeof(eth->regmap_pextp), GFP_KERNEL); -+ if (!eth->regmap_pextp) -+ return -ENOMEM; -+ -+ for (i = 0; i < eth->soc->num_devs; i++) { -+ np = of_parse_phandle(r, "mediatek,xfi_pextp", i); -+ if (!np) -+ break; -+ -+ eth->regmap_pextp[i] = syscon_node_to_regmap(np); -+ if (IS_ERR(eth->regmap_pextp[i])) -+ return PTR_ERR(eth->regmap_pextp[i]); -+ } -+ -+ return 0; -+} -+ -+static int mtk_xfi_pll_init(struct mtk_eth *eth) -+{ -+ struct device_node *r = eth->dev->of_node; -+ struct device_node *np; -+ -+ np = of_parse_phandle(r, "mediatek,xfi_pll", 0); -+ if (!np) -+ return -1; -+ -+ eth->usxgmii_pll = syscon_node_to_regmap(np); -+ if (IS_ERR(eth->usxgmii_pll)) -+ return PTR_ERR(eth->usxgmii_pll); -+ -+ return 0; -+} -+ -+static int mtk_toprgu_init(struct mtk_eth *eth) -+{ -+ struct device_node *r = eth->dev->of_node; -+ struct device_node *np; -+ -+ np = of_parse_phandle(r, "mediatek,toprgu", 0); -+ if (!np) -+ return -1; -+ -+ eth->toprgu = syscon_node_to_regmap(np); -+ if (IS_ERR(eth->toprgu)) -+ return PTR_ERR(eth->toprgu); -+ -+ return 0; -+} -+ -+int mtk_xfi_pll_enable(struct mtk_eth *eth) -+{ -+ u32 val = 0; -+ -+ if (!eth->usxgmii_pll) -+ return -EINVAL; -+ -+ /* Add software workaround for USXGMII PLL TCL issue */ -+ regmap_write(eth->usxgmii_pll, XFI_PLL_ANA_GLB8, RG_XFI_PLL_ANA_SWWA); -+ -+ regmap_read(eth->usxgmii_pll, XFI_PLL_DIG_GLB8, &val); -+ val |= RG_XFI_PLL_EN; -+ regmap_write(eth->usxgmii_pll, XFI_PLL_DIG_GLB8, val); -+ -+ return 0; -+} -+ -+static int mtk_mac2xgmii_id(struct mtk_eth *eth, int mac_id) -+{ -+ int xgmii_id = mac_id; -+ -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { -+ switch (mac_id) { -+ case MTK_GMAC1_ID: -+ case MTK_GMAC2_ID: -+ xgmii_id = 1; -+ break; -+ case MTK_GMAC3_ID: -+ xgmii_id = 0; -+ break; -+ default: -+ xgmii_id = -1; -+ } -+ } -+ -+ return xgmii_id; -+} -+ -+static int mtk_xgmii2mac_id(struct mtk_eth *eth, int xgmii_id) -+{ -+ int mac_id = xgmii_id; -+ -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { -+ switch (xgmii_id) { -+ case 0: -+ mac_id = 2; -+ break; -+ case 1: -+ mac_id = 1; -+ break; -+ default: -+ mac_id = -1; -+ } -+ } -+ -+ return mac_id; -+} -+ -+ -+static void mtk_usxgmii_setup_phya_usxgmii(struct mtk_usxgmii_pcs *mpcs) -+{ -+ struct regmap *pextp; -+ -+ if (!mpcs->eth) -+ return; -+ -+ pextp = mpcs->eth->regmap_pextp[mpcs->id]; -+ if (!pextp) -+ return; -+ -+ /* Setup operation mode */ -+ regmap_write(pextp, 0x9024, 0x00C9071C); -+ regmap_write(pextp, 0x2020, 0xAA8585AA); -+ regmap_write(pextp, 0x2030, 0x0C020707); -+ regmap_write(pextp, 0x2034, 0x0E050F0F); -+ regmap_write(pextp, 0x2040, 0x00140032); -+ regmap_write(pextp, 0x50F0, 0x00C014AA); -+ regmap_write(pextp, 0x50E0, 0x3777C12B); -+ regmap_write(pextp, 0x506C, 0x005F9CFF); -+ regmap_write(pextp, 0x5070, 0x9D9DFAFA); -+ regmap_write(pextp, 0x5074, 0x27273F3F); -+ regmap_write(pextp, 0x5078, 0xA7883C68); -+ regmap_write(pextp, 0x507C, 0x11661166); -+ regmap_write(pextp, 0x5080, 0x0E000AAF); -+ regmap_write(pextp, 0x5084, 0x08080D0D); -+ regmap_write(pextp, 0x5088, 0x02030909); -+ regmap_write(pextp, 0x50E4, 0x0C0C0000); -+ regmap_write(pextp, 0x50E8, 0x04040000); -+ regmap_write(pextp, 0x50EC, 0x0F0F0C06); -+ regmap_write(pextp, 0x50A8, 0x506E8C8C); -+ regmap_write(pextp, 0x6004, 0x18190000); -+ regmap_write(pextp, 0x00F8, 0x01423342); -+ /* Force SGDT_OUT off and select PCS */ -+ regmap_write(pextp, 0x00F4, 0x80201F20); -+ /* Force GLB_CKDET_OUT */ -+ regmap_write(pextp, 0x0030, 0x00050C00); -+ /* Force AEQ on */ -+ regmap_write(pextp, 0x0070, 0x02002800); -+ ndelay(1020); -+ /* Setup DA default value */ -+ regmap_write(pextp, 0x30B0, 0x00000020); -+ regmap_write(pextp, 0x3028, 0x00008A01); -+ regmap_write(pextp, 0x302C, 0x0000A884); -+ regmap_write(pextp, 0x3024, 0x00083002); -+ regmap_write(pextp, 0x3010, 0x00022220); -+ regmap_write(pextp, 0x5064, 0x0F020A01); -+ regmap_write(pextp, 0x50B4, 0x06100600); -+ regmap_write(pextp, 0x3048, 0x40704000); -+ regmap_write(pextp, 0x3050, 0xA8000000); -+ regmap_write(pextp, 0x3054, 0x000000AA); -+ regmap_write(pextp, 0x306C, 0x00000F00); -+ regmap_write(pextp, 0xA060, 0x00040000); -+ regmap_write(pextp, 0x90D0, 0x00000001); -+ /* Release reset */ -+ regmap_write(pextp, 0x0070, 0x0200E800); -+ udelay(150); -+ /* Switch to P0 */ -+ regmap_write(pextp, 0x0070, 0x0200C111); -+ ndelay(1020); -+ regmap_write(pextp, 0x0070, 0x0200C101); -+ udelay(15); -+ /* Switch to Gen3 */ -+ regmap_write(pextp, 0x0070, 0x0202C111); -+ ndelay(1020); -+ regmap_write(pextp, 0x0070, 0x0202C101); -+ udelay(100); -+ regmap_write(pextp, 0x30B0, 0x00000030); -+ regmap_write(pextp, 0x00F4, 0x80201F00); -+ regmap_write(pextp, 0x3040, 0x30000000); -+ udelay(400); -+} -+ -+static void mtk_usxgmii_setup_phya_5gbaser(struct mtk_usxgmii_pcs *mpcs) -+{ -+ struct regmap *pextp; -+ -+ if (!mpcs->eth) -+ return; -+ -+ pextp = mpcs->eth->regmap_pextp[mpcs->id]; -+ if (!pextp) -+ return; -+ -+ /* Setup operation mode */ -+ regmap_write(pextp, 0x9024, 0x00D9071C); -+ regmap_write(pextp, 0x2020, 0xAAA5A5AA); -+ regmap_write(pextp, 0x2030, 0x0C020707); -+ regmap_write(pextp, 0x2034, 0x0E050F0F); -+ regmap_write(pextp, 0x2040, 0x00140032); -+ regmap_write(pextp, 0x50F0, 0x00C018AA); -+ regmap_write(pextp, 0x50E0, 0x3777812B); -+ regmap_write(pextp, 0x506C, 0x005C9CFF); -+ regmap_write(pextp, 0x5070, 0x9DFAFAFA); -+ regmap_write(pextp, 0x5074, 0x273F3F3F); -+ regmap_write(pextp, 0x5078, 0xA8883868); -+ regmap_write(pextp, 0x507C, 0x14661466); -+ regmap_write(pextp, 0x5080, 0x0E001ABF); -+ regmap_write(pextp, 0x5084, 0x080B0D0D); -+ regmap_write(pextp, 0x5088, 0x02050909); -+ regmap_write(pextp, 0x50E4, 0x0C000000); -+ regmap_write(pextp, 0x50E8, 0x04000000); -+ regmap_write(pextp, 0x50EC, 0x0F0F0C06); -+ regmap_write(pextp, 0x50A8, 0x50808C8C); -+ regmap_write(pextp, 0x6004, 0x18000000); -+ regmap_write(pextp, 0x00F8, 0x00A132A1); -+ /* Force SGDT_OUT off and select PCS */ -+ regmap_write(pextp, 0x00F4, 0x80201F20); -+ /* Force GLB_CKDET_OUT */ -+ regmap_write(pextp, 0x0030, 0x00050C00); -+ /* Force AEQ on */ -+ regmap_write(pextp, 0x0070, 0x02002800); -+ ndelay(1020); -+ /* Setup DA default value */ -+ regmap_write(pextp, 0x30B0, 0x00000020); -+ regmap_write(pextp, 0x3028, 0x00008A01); -+ regmap_write(pextp, 0x302C, 0x0000A884); -+ regmap_write(pextp, 0x3024, 0x00083002); -+ regmap_write(pextp, 0x3010, 0x00022220); -+ regmap_write(pextp, 0x5064, 0x0F020A01); -+ regmap_write(pextp, 0x50B4, 0x06100600); -+ regmap_write(pextp, 0x3048, 0x40704000); -+ regmap_write(pextp, 0x3050, 0xA8000000); -+ regmap_write(pextp, 0x3054, 0x000000AA); -+ regmap_write(pextp, 0x306C, 0x00000F00); -+ regmap_write(pextp, 0xA060, 0x00040000); -+ regmap_write(pextp, 0x90D0, 0x00000003); -+ /* Release reset */ -+ regmap_write(pextp, 0x0070, 0x0200E800); -+ udelay(150); -+ /* Switch to P0 */ -+ regmap_write(pextp, 0x0070, 0x0200C111); -+ ndelay(1020); -+ regmap_write(pextp, 0x0070, 0x0200C101); -+ udelay(15); -+ /* Switch to Gen3 */ -+ regmap_write(pextp, 0x0070, 0x0202C111); -+ ndelay(1020); -+ regmap_write(pextp, 0x0070, 0x0202C101); -+ udelay(100); -+ regmap_write(pextp, 0x30B0, 0x00000030); -+ regmap_write(pextp, 0x00F4, 0x80201F00); -+ regmap_write(pextp, 0x3040, 0x30000000); -+ udelay(400); -+} -+ -+static void mtk_usxgmii_setup_phya_10gbaser(struct mtk_usxgmii_pcs *mpcs) -+{ -+ struct regmap *pextp; -+ -+ if (!mpcs->eth) -+ return; -+ -+ pextp = mpcs->eth->regmap_pextp[mpcs->id]; -+ if (!pextp) -+ return; -+ -+ /* Setup operation mode */ -+ regmap_write(pextp, 0x9024, 0x00C9071C); -+ regmap_write(pextp, 0x2020, 0xAA8585AA); -+ regmap_write(pextp, 0x2030, 0x0C020707); -+ regmap_write(pextp, 0x2034, 0x0E050F0F); -+ regmap_write(pextp, 0x2040, 0x00140032); -+ regmap_write(pextp, 0x50F0, 0x00C014AA); -+ regmap_write(pextp, 0x50E0, 0x3777C12B); -+ regmap_write(pextp, 0x506C, 0x005F9CFF); -+ regmap_write(pextp, 0x5070, 0x9D9DFAFA); -+ regmap_write(pextp, 0x5074, 0x27273F3F); -+ regmap_write(pextp, 0x5078, 0xA7883C68); -+ regmap_write(pextp, 0x507C, 0x11661166); -+ regmap_write(pextp, 0x5080, 0x0E000AAF); -+ regmap_write(pextp, 0x5084, 0x08080D0D); -+ regmap_write(pextp, 0x5088, 0x02030909); -+ regmap_write(pextp, 0x50E4, 0x0C0C0000); -+ regmap_write(pextp, 0x50E8, 0x04040000); -+ regmap_write(pextp, 0x50EC, 0x0F0F0C06); -+ regmap_write(pextp, 0x50A8, 0x506E8C8C); -+ regmap_write(pextp, 0x6004, 0x18190000); -+ regmap_write(pextp, 0x00F8, 0x01423342); -+ /* Force SGDT_OUT off and select PCS */ -+ regmap_write(pextp, 0x00F4, 0x80201F20); -+ /* Force GLB_CKDET_OUT */ -+ regmap_write(pextp, 0x0030, 0x00050C00); -+ /* Force AEQ on */ -+ regmap_write(pextp, 0x0070, 0x02002800); -+ ndelay(1020); -+ /* Setup DA default value */ -+ regmap_write(pextp, 0x30B0, 0x00000020); -+ regmap_write(pextp, 0x3028, 0x00008A01); -+ regmap_write(pextp, 0x302C, 0x0000A884); -+ regmap_write(pextp, 0x3024, 0x00083002); -+ regmap_write(pextp, 0x3010, 0x00022220); -+ regmap_write(pextp, 0x5064, 0x0F020A01); -+ regmap_write(pextp, 0x50B4, 0x06100600); -+ regmap_write(pextp, 0x3048, 0x47684100); -+ regmap_write(pextp, 0x3050, 0x00000000); -+ regmap_write(pextp, 0x3054, 0x00000000); -+ regmap_write(pextp, 0x306C, 0x00000F00); -+ if (mpcs->id == 0) -+ regmap_write(pextp, 0xA008, 0x0007B400); -+ -+ regmap_write(pextp, 0xA060, 0x00040000); -+ regmap_write(pextp, 0x90D0, 0x00000001); -+ /* Release reset */ -+ regmap_write(pextp, 0x0070, 0x0200E800); -+ udelay(150); -+ /* Switch to P0 */ -+ regmap_write(pextp, 0x0070, 0x0200C111); -+ ndelay(1020); -+ regmap_write(pextp, 0x0070, 0x0200C101); -+ udelay(15); -+ /* Switch to Gen3 */ -+ regmap_write(pextp, 0x0070, 0x0202C111); -+ ndelay(1020); -+ regmap_write(pextp, 0x0070, 0x0202C101); -+ udelay(100); -+ regmap_write(pextp, 0x30B0, 0x00000030); -+ regmap_write(pextp, 0x00F4, 0x80201F00); -+ regmap_write(pextp, 0x3040, 0x30000000); -+ udelay(400); -+} -+ -+void mtk_sgmii_setup_phya_gen1(struct mtk_eth *eth, int mac_id) -+{ -+ u32 id = mtk_mac2xgmii_id(eth, mac_id); -+ struct regmap *pextp; -+ -+ if (id >= eth->soc->num_devs) -+ return; -+ -+ pextp = eth->regmap_pextp[id]; -+ if (!pextp) -+ return; -+ -+ /* Setup operation mode */ -+ regmap_write(pextp, 0x9024, 0x00D9071C); -+ regmap_write(pextp, 0x2020, 0xAA8585AA); -+ regmap_write(pextp, 0x2030, 0x0C020207); -+ regmap_write(pextp, 0x2034, 0x0E05050F); -+ regmap_write(pextp, 0x2040, 0x00200032); -+ regmap_write(pextp, 0x50F0, 0x00C014BA); -+ regmap_write(pextp, 0x50E0, 0x3777C12B); -+ regmap_write(pextp, 0x506C, 0x005F9CFF); -+ regmap_write(pextp, 0x5070, 0x9D9DFAFA); -+ regmap_write(pextp, 0x5074, 0x27273F3F); -+ regmap_write(pextp, 0x5078, 0xA7883C68); -+ regmap_write(pextp, 0x507C, 0x11661166); -+ regmap_write(pextp, 0x5080, 0x0E000EAF); -+ regmap_write(pextp, 0x5084, 0x08080E0D); -+ regmap_write(pextp, 0x5088, 0x02030B09); -+ regmap_write(pextp, 0x50E4, 0x0C0C0000); -+ regmap_write(pextp, 0x50E8, 0x04040000); -+ regmap_write(pextp, 0x50EC, 0x0F0F0606); -+ regmap_write(pextp, 0x50A8, 0x506E8C8C); -+ regmap_write(pextp, 0x6004, 0x18190000); -+ regmap_write(pextp, 0x00F8, 0x00FA32FA); -+ /* Force SGDT_OUT off and select PCS */ -+ regmap_write(pextp, 0x00F4, 0x80201F21); -+ /* Force GLB_CKDET_OUT */ -+ regmap_write(pextp, 0x0030, 0x00050C00); -+ /* Force AEQ on */ -+ regmap_write(pextp, 0x0070, 0x02002800); -+ ndelay(1020); -+ /* Setup DA default value */ -+ regmap_write(pextp, 0x30B0, 0x00000020); -+ regmap_write(pextp, 0x3028, 0x00008A01); -+ regmap_write(pextp, 0x302C, 0x0000A884); -+ regmap_write(pextp, 0x3024, 0x00083002); -+ regmap_write(pextp, 0x3010, 0x00011110); -+ regmap_write(pextp, 0x3048, 0x40704000); -+ regmap_write(pextp, 0x3064, 0x0000C000); -+ regmap_write(pextp, 0x3050, 0xA8000000); -+ regmap_write(pextp, 0x3054, 0x000000AA); -+ regmap_write(pextp, 0x306C, 0x20200F00); -+ regmap_write(pextp, 0xA060, 0x00050000); -+ regmap_write(pextp, 0x90D0, 0x00000007); -+ /* Release reset */ -+ regmap_write(pextp, 0x0070, 0x0200E800); -+ udelay(150); -+ /* Switch to P0 */ -+ regmap_write(pextp, 0x0070, 0x0200C111); -+ ndelay(1020); -+ regmap_write(pextp, 0x0070, 0x0200C101); -+ udelay(15); -+ /* Switch to Gen2 */ -+ regmap_write(pextp, 0x0070, 0x0201C111); -+ ndelay(1020); -+ regmap_write(pextp, 0x0070, 0x0201C101); -+ udelay(100); -+ regmap_write(pextp, 0x30B0, 0x00000030); -+ regmap_write(pextp, 0x00F4, 0x80201F01); -+ regmap_write(pextp, 0x3040, 0x30000000); -+ udelay(400); -+} -+ -+void mtk_sgmii_setup_phya_gen2(struct mtk_eth *eth, int mac_id) -+{ -+ u32 id = mtk_mac2xgmii_id(eth, mac_id); -+ struct regmap *pextp; -+ -+ if (id >= eth->soc->num_devs) -+ return; -+ -+ pextp = eth->regmap_pextp[id]; -+ if (!pextp) -+ return; -+ -+ /* Setup operation mode */ -+ regmap_write(pextp, 0x9024, 0x00D9071C); -+ regmap_write(pextp, 0x2020, 0xAA8585AA); -+ regmap_write(pextp, 0x2030, 0x0C020707); -+ regmap_write(pextp, 0x2034, 0x0E050F0F); -+ regmap_write(pextp, 0x2040, 0x00140032); -+ regmap_write(pextp, 0x50F0, 0x00C014AA); -+ regmap_write(pextp, 0x50E0, 0x3777C12B); -+ regmap_write(pextp, 0x506C, 0x005F9CFF); -+ regmap_write(pextp, 0x5070, 0x9D9DFAFA); -+ regmap_write(pextp, 0x5074, 0x27273F3F); -+ regmap_write(pextp, 0x5078, 0xA7883C68); -+ regmap_write(pextp, 0x507C, 0x11661166); -+ regmap_write(pextp, 0x5080, 0x0E000AAF); -+ regmap_write(pextp, 0x5084, 0x08080D0D); -+ regmap_write(pextp, 0x5088, 0x02030909); -+ regmap_write(pextp, 0x50E4, 0x0C0C0000); -+ regmap_write(pextp, 0x50E8, 0x04040000); -+ regmap_write(pextp, 0x50EC, 0x0F0F0C06); -+ regmap_write(pextp, 0x50A8, 0x506E8C8C); -+ regmap_write(pextp, 0x6004, 0x18190000); -+ regmap_write(pextp, 0x00F8, 0x009C329C); -+ /* Force SGDT_OUT off and select PCS */ -+ regmap_write(pextp, 0x00F4, 0x80201F21); -+ /* Force GLB_CKDET_OUT */ -+ regmap_write(pextp, 0x0030, 0x00050C00); -+ /* Force AEQ on */ -+ regmap_write(pextp, 0x0070, 0x02002800); -+ ndelay(1020); -+ /* Setup DA default value */ -+ regmap_write(pextp, 0x30B0, 0x00000020); -+ regmap_write(pextp, 0x3028, 0x00008A01); -+ regmap_write(pextp, 0x302C, 0x0000A884); -+ regmap_write(pextp, 0x3024, 0x00083002); -+ regmap_write(pextp, 0x3010, 0x00011110); -+ regmap_write(pextp, 0x3048, 0x40704000); -+ regmap_write(pextp, 0x3050, 0xA8000000); -+ regmap_write(pextp, 0x3054, 0x000000AA); -+ regmap_write(pextp, 0x306C, 0x22000F00); -+ regmap_write(pextp, 0xA060, 0x00050000); -+ regmap_write(pextp, 0x90D0, 0x00000005); -+ /* Release reset */ -+ regmap_write(pextp, 0x0070, 0x0200E800); -+ udelay(150); -+ /* Switch to P0 */ -+ regmap_write(pextp, 0x0070, 0x0200C111); -+ ndelay(1020); -+ regmap_write(pextp, 0x0070, 0x0200C101); -+ udelay(15); -+ /* Switch to Gen2 */ -+ regmap_write(pextp, 0x0070, 0x0201C111); -+ ndelay(1020); -+ regmap_write(pextp, 0x0070, 0x0201C101); -+ udelay(100); -+ regmap_write(pextp, 0x30B0, 0x00000030); -+ regmap_write(pextp, 0x00F4, 0x80201F01); -+ regmap_write(pextp, 0x3040, 0x30000000); -+ udelay(400); -+} -+ -+static void mtk_usxgmii_reset(struct mtk_eth *eth, int id) -+{ -+ u32 val = 0; -+ -+ if (id >= eth->soc->num_devs || !eth->toprgu) -+ return; -+ -+ switch (id) { -+ case 0: -+ /* Enable software reset */ -+ regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val); -+ val |= SWSYSRST_XFI_PEXPT0_GRST | -+ SWSYSRST_XFI0_GRST; -+ regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val); -+ -+ /* Assert USXGMII reset */ -+ regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val); -+ val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88) | -+ SWSYSRST_XFI_PEXPT0_GRST | -+ SWSYSRST_XFI0_GRST; -+ regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val); -+ -+ udelay(100); -+ -+ /* De-assert USXGMII reset */ -+ regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val); -+ val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88); -+ val &= ~(SWSYSRST_XFI_PEXPT0_GRST | -+ SWSYSRST_XFI0_GRST); -+ regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val); -+ -+ /* Disable software reset */ -+ regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val); -+ val &= ~(SWSYSRST_XFI_PEXPT0_GRST | -+ SWSYSRST_XFI0_GRST); -+ regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val); -+ break; -+ case 1: -+ /* Enable software reset */ -+ regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val); -+ val |= SWSYSRST_XFI_PEXPT1_GRST | -+ SWSYSRST_XFI1_GRST; -+ regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val); -+ -+ /* Assert USXGMII reset */ -+ regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val); -+ val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88) | -+ SWSYSRST_XFI_PEXPT1_GRST | -+ SWSYSRST_XFI1_GRST; -+ regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val); -+ -+ udelay(100); -+ -+ /* De-assert USXGMII reset */ -+ regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val); -+ val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88); -+ val &= ~(SWSYSRST_XFI_PEXPT1_GRST | -+ SWSYSRST_XFI1_GRST); -+ regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val); -+ -+ /* Disable software reset */ -+ regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val); -+ val &= ~(SWSYSRST_XFI_PEXPT1_GRST | -+ SWSYSRST_XFI1_GRST); -+ regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val); -+ break; -+ } -+ -+ mdelay(10); -+} -+ -+void mtk_sgmii_reset(struct mtk_eth *eth, int mac_id) -+{ -+ u32 xgmii_id = mtk_mac2xgmii_id(eth, mac_id); -+ -+ mtk_usxgmii_reset(eth, xgmii_id); -+} -+ -+ -+static int mtk_usxgmii_pcs_config(struct phylink_pcs *pcs, unsigned int mode, -+ phy_interface_t interface, -+ const unsigned long *advertising, -+ bool permit_pause_to_mac) -+{ -+ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs); -+ struct mtk_eth *eth = mpcs->eth; -+ unsigned int an_ctrl = 0, link_timer = 0, xfi_mode = 0, adapt_mode = 0; -+ bool mode_changed = false; -+ -+ if (interface == PHY_INTERFACE_MODE_USXGMII) { -+ an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF) | -+ USXGMII_AN_ENABLE; -+ link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) | -+ FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) | -+ FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B); -+ xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_10G) | -+ FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_10G); -+ } else if (interface == PHY_INTERFACE_MODE_10GKR) { -+ an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF); -+ link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) | -+ FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) | -+ FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B); -+ xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_10G) | -+ FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_10G); -+ adapt_mode = USXGMII_RATE_UPDATE_MODE; -+ } else if (interface == PHY_INTERFACE_MODE_5GBASER) { -+ an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0xFF); -+ link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x3D) | -+ FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x3D) | -+ FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x3D); -+ xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_5G) | -+ FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_5G); -+ adapt_mode = USXGMII_RATE_UPDATE_MODE; -+ } else -+ return -EINVAL; -+ -+ adapt_mode |= FIELD_PREP(USXGMII_RATE_ADAPT_MODE, USXGMII_RATE_ADAPT_MODE_X1); -+ -+ if (mpcs->interface != interface) { -+ mpcs->interface = interface; -+ mode_changed = true; -+ } -+ -+ mtk_xfi_pll_enable(eth); -+ mtk_usxgmii_reset(eth, mpcs->id); -+ -+ /* Setup USXGMII AN ctrl */ -+ regmap_update_bits(mpcs->regmap, RG_PCS_AN_CTRL0, -+ USXGMII_AN_SYNC_CNT | USXGMII_AN_ENABLE, -+ an_ctrl); -+ -+ regmap_update_bits(mpcs->regmap, RG_PCS_AN_CTRL2, -+ USXGMII_LINK_TIMER_IDLE_DETECT | -+ USXGMII_LINK_TIMER_COMP_ACK_DETECT | -+ USXGMII_LINK_TIMER_AN_RESTART, -+ link_timer); -+ -+ /* Gated MAC CK */ -+ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, -+ USXGMII_MAC_CK_GATED, USXGMII_MAC_CK_GATED); -+ -+ /* Enable interface force mode */ -+ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, -+ USXGMII_IF_FORCE_EN, USXGMII_IF_FORCE_EN); -+ -+ /* Setup USXGMII adapt mode */ -+ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, -+ USXGMII_RATE_UPDATE_MODE | USXGMII_RATE_ADAPT_MODE, -+ adapt_mode); -+ -+ /* Setup USXGMII speed */ -+ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, -+ USXGMII_XFI_RX_MODE | USXGMII_XFI_TX_MODE, -+ xfi_mode); -+ -+ udelay(1); -+ -+ /* Un-gated MAC CK */ -+ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, -+ USXGMII_MAC_CK_GATED, 0); -+ -+ udelay(1); -+ -+ /* Disable interface force mode for the AN mode */ -+ if (an_ctrl & USXGMII_AN_ENABLE) -+ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, -+ USXGMII_IF_FORCE_EN, 0); -+ -+ /* Setup USXGMIISYS with the determined property */ -+ if (interface == PHY_INTERFACE_MODE_USXGMII) -+ mtk_usxgmii_setup_phya_usxgmii(mpcs); -+ else if (interface == PHY_INTERFACE_MODE_10GKR) -+ mtk_usxgmii_setup_phya_10gbaser(mpcs); -+ else if (interface == PHY_INTERFACE_MODE_5GBASER) -+ mtk_usxgmii_setup_phya_5gbaser(mpcs); -+ -+ return mode_changed; -+} -+ -+static void mtk_usxgmii_pcs_get_state(struct phylink_pcs *pcs, -+ struct phylink_link_state *state) -+{ -+ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs); -+ struct mtk_eth *eth = mpcs->eth; -+ struct mtk_mac *mac = eth->mac[mtk_xgmii2mac_id(eth, mpcs->id)]; -+ u32 val = 0; -+ -+ regmap_read(mpcs->regmap, RG_PCS_AN_CTRL0, &val); -+ if (FIELD_GET(USXGMII_AN_ENABLE, val)) { -+ /* Refresh LPA by inverting LPA_LATCH */ -+ regmap_read(mpcs->regmap, RG_PCS_AN_STS0, &val); -+ regmap_update_bits(mpcs->regmap, RG_PCS_AN_STS0, -+ USXGMII_LPA_LATCH, -+ !(val & USXGMII_LPA_LATCH)); -+ -+ regmap_read(mpcs->regmap, RG_PCS_AN_STS0, &val); -+ -+ state->interface = mpcs->interface; -+ state->link = FIELD_GET(USXGMII_LPA_LINK, val); -+ state->duplex = FIELD_GET(USXGMII_LPA_DUPLEX, val); -+ -+ switch (FIELD_GET(USXGMII_LPA_SPEED_MASK, val)) { -+ case USXGMII_LPA_SPEED_10: -+ state->speed = SPEED_10; -+ break; -+ case USXGMII_LPA_SPEED_100: -+ state->speed = SPEED_100; -+ break; -+ case USXGMII_LPA_SPEED_1000: -+ state->speed = SPEED_1000; -+ break; -+ case USXGMII_LPA_SPEED_2500: -+ state->speed = SPEED_2500; -+ break; -+ case USXGMII_LPA_SPEED_5000: -+ state->speed = SPEED_5000; -+ break; -+ case USXGMII_LPA_SPEED_10000: -+ state->speed = SPEED_10000; -+ break; -+ } -+ } else { -+ val = mtk_r32(mac->hw, MTK_XGMAC_STS(mac->id)); -+ -+ if (mac->id == MTK_GMAC2_ID) -+ val = val >> 16; -+ -+ switch (FIELD_GET(MTK_USXGMII_PCS_MODE, val)) { -+ case 0: -+ state->speed = SPEED_10000; -+ break; -+ case 1: -+ state->speed = SPEED_5000; -+ break; -+ case 2: -+ state->speed = SPEED_2500; -+ break; -+ case 3: -+ state->speed = SPEED_1000; -+ break; -+ } -+ -+ state->interface = mpcs->interface; -+ state->link = FIELD_GET(MTK_USXGMII_PCS_LINK, val); -+ state->duplex = DUPLEX_FULL; -+ } -+ -+ if (state->link == 0) -+ mtk_usxgmii_pcs_config(pcs, MLO_AN_INBAND, -+ state->interface, NULL, false); -+} -+ -+static void mtk_usxgmii_pcs_restart_an(struct phylink_pcs *pcs) -+{ -+ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs); -+ unsigned int val = 0; -+ -+ if (!mpcs->regmap) -+ return; -+ -+ regmap_read(mpcs->regmap, RG_PCS_AN_CTRL0, &val); -+ val |= USXGMII_AN_RESTART; -+ regmap_write(mpcs->regmap, RG_PCS_AN_CTRL0, val); -+} -+ -+static void mtk_usxgmii_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode, -+ phy_interface_t interface, -+ int speed, int duplex) -+{ -+ /* Reconfiguring USXGMII to ensure the quality of the RX signal -+ * after the line side link up. -+ */ -+ mtk_usxgmii_pcs_config(pcs, mode, -+ interface, NULL, false); -+} -+ -+static const struct phylink_pcs_ops mtk_usxgmii_pcs_ops = { -+ .pcs_config = mtk_usxgmii_pcs_config, -+ .pcs_get_state = mtk_usxgmii_pcs_get_state, -+ .pcs_an_restart = mtk_usxgmii_pcs_restart_an, -+ .pcs_link_up = mtk_usxgmii_pcs_link_up, -+}; -+ -+int mtk_usxgmii_init(struct mtk_eth *eth) -+{ -+ struct device_node *r = eth->dev->of_node; -+ struct device *dev = eth->dev; -+ struct device_node *np; -+ int i, ret; -+ -+ eth->usxgmii_pcs = devm_kcalloc(dev, eth->soc->num_devs, sizeof(eth->usxgmii_pcs), GFP_KERNEL); -+ if (!eth->usxgmii_pcs) -+ return -ENOMEM; -+ -+ for (i = 0; i < eth->soc->num_devs; i++) { -+ np = of_parse_phandle(r, "mediatek,usxgmiisys", i); -+ if (!np) -+ break; -+ -+ eth->usxgmii_pcs[i] = devm_kzalloc(dev, sizeof(*eth->usxgmii_pcs), GFP_KERNEL); -+ if (!eth->usxgmii_pcs[i]) -+ return -ENOMEM; -+ -+ eth->usxgmii_pcs[i]->id = i; -+ eth->usxgmii_pcs[i]->eth = eth; -+ eth->usxgmii_pcs[i]->regmap = syscon_node_to_regmap(np); -+ if (IS_ERR(eth->usxgmii_pcs[i]->regmap)) -+ return PTR_ERR(eth->usxgmii_pcs[i]->regmap); -+ -+ eth->usxgmii_pcs[i]->pcs.ops = &mtk_usxgmii_pcs_ops; -+ eth->usxgmii_pcs[i]->pcs.poll = true; -+ eth->usxgmii_pcs[i]->interface = PHY_INTERFACE_MODE_NA; -+ -+ of_node_put(np); -+ } -+ -+ ret = mtk_xfi_pextp_init(eth); -+ if (ret) -+ return ret; -+ -+ ret = mtk_xfi_pll_init(eth); -+ if (ret) -+ return ret; -+ -+ return mtk_toprgu_init(eth); -+} -+ -+struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int mac_id) -+{ -+ u32 xgmii_id = mtk_mac2xgmii_id(eth, mac_id); -+ -+ if (!eth->usxgmii_pcs[xgmii_id]->regmap) -+ return NULL; -+ -+ return ð->usxgmii_pcs[xgmii_id]->pcs; -+} diff --git a/target/linux/generic/pending-5.15/737-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch b/target/linux/generic/pending-5.15/737-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch new file mode 100644 index 00000000000..5b7591e2273 --- /dev/null +++ b/target/linux/generic/pending-5.15/737-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch @@ -0,0 +1,1604 @@ +From 1e25ca1147579bda8b941be1b9851f5911d44eb0 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Tue, 22 Aug 2023 19:04:42 +0100 +Subject: [PATCH 098/125] net: ethernet: mtk_eth_soc: add paths and SerDes + modes for MT7988 + +MT7988 comes with a built-in 2.5G PHY as well as SerDes lanes to +connect external PHYs or transceivers in USXGMII, 10GBase-R, 5GBase-R, +2500Base-X, 1000Base-X and Cisco SGMII interface modes. + +Implement support for configuring for the new paths to SerDes interfaces +and the internal 2.5G PHY. + +Add USXGMII PCS driver for 10GBase-R, 5GBase-R and USXGMII mode, and +setup the new PHYA on MT7988 to access the also still existing old +LynxI PCS for 1000Base-X, 2500Base-X and Cisco SGMII PCS interface +modes. + +Signed-off-by: Daniel Golle +--- + drivers/net/ethernet/mediatek/Kconfig | 16 + + drivers/net/ethernet/mediatek/Makefile | 1 + + drivers/net/ethernet/mediatek/mtk_eth_path.c | 123 +++- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 182 ++++- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 232 ++++++- + drivers/net/ethernet/mediatek/mtk_usxgmii.c | 692 +++++++++++++++++++ + 6 files changed, 1215 insertions(+), 31 deletions(-) + create mode 100644 drivers/net/ethernet/mediatek/mtk_usxgmii.c + +--- a/drivers/net/ethernet/mediatek/Kconfig ++++ b/drivers/net/ethernet/mediatek/Kconfig +@@ -24,6 +24,22 @@ config NET_MEDIATEK_SOC + This driver supports the gigabit ethernet MACs in the + MediaTek SoC family. + ++config NET_MEDIATEK_SOC_USXGMII ++ bool "Support USXGMII SerDes on MT7988" ++ depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST ++ def_bool NET_MEDIATEK_SOC != n ++ help ++ Include support for 10GE SerDes which can be found on MT7988. ++ If this kernel should run on SoCs with 10 GBit/s Ethernet you ++ will need to select this option to use GMAC2 and GMAC3 with ++ external PHYs, SFP(+) cages in 10GBase-R, 5GBase-R or USXGMII ++ interface modes. ++ ++ Note that as the 2500Base-X/1000Base-X/Cisco SGMII SerDes PCS ++ unit (MediaTek LynxI) in MT7988 is connected via the new 10GE ++ SerDes, you will also need to select this option in case you ++ want to use any of those SerDes modes. ++ + config NET_MEDIATEK_STAR_EMAC + tristate "MediaTek STAR Ethernet MAC support" + select PHYLIB +--- a/drivers/net/ethernet/mediatek/Makefile ++++ b/drivers/net/ethernet/mediatek/Makefile +@@ -5,6 +5,7 @@ + + obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o + mtk_eth-y := mtk_eth_soc.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o ++mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_USXGMII) += mtk_usxgmii.o + mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o mtk_wed_mcu.o mtk_wed_wo.o + ifdef CONFIG_DEBUG_FS + mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_debugfs.o +--- a/drivers/net/ethernet/mediatek/mtk_eth_path.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c +@@ -31,10 +31,20 @@ static const char *mtk_eth_path_name(u64 + return "gmac2_rgmii"; + case MTK_ETH_PATH_GMAC2_SGMII: + return "gmac2_sgmii"; ++ case MTK_ETH_PATH_GMAC2_2P5GPHY: ++ return "gmac2_2p5gphy"; + case MTK_ETH_PATH_GMAC2_GEPHY: + return "gmac2_gephy"; ++ case MTK_ETH_PATH_GMAC3_SGMII: ++ return "gmac3_sgmii"; + case MTK_ETH_PATH_GDM1_ESW: + return "gdm1_esw"; ++ case MTK_ETH_PATH_GMAC1_USXGMII: ++ return "gmac1_usxgmii"; ++ case MTK_ETH_PATH_GMAC2_USXGMII: ++ return "gmac2_usxgmii"; ++ case MTK_ETH_PATH_GMAC3_USXGMII: ++ return "gmac3_usxgmii"; + default: + return "unknown path"; + } +@@ -127,6 +137,27 @@ static int set_mux_u3_gmac2_to_qphy(stru + return 0; + } + ++static int set_mux_gmac2_to_2p5gphy(struct mtk_eth *eth, u64 path) ++{ ++ int ret; ++ ++ if (path == MTK_ETH_PATH_GMAC2_2P5GPHY) { ++ ret = regmap_clear_bits(eth->ethsys, ETHSYS_SYSCFG0, SYSCFG0_SGMII_GMAC2_V2); ++ if (ret) ++ return ret; ++ ++ /* Setup mux to 2p5g PHY */ ++ ret = regmap_clear_bits(eth->infra, TOP_MISC_NETSYS_PCS_MUX, MUX_G2_USXGMII_SEL); ++ if (ret) ++ return ret; ++ ++ dev_dbg(eth->dev, "path %s in %s updated\n", ++ mtk_eth_path_name(path), __func__); ++ } ++ ++ return 0; ++} ++ + static int set_mux_gmac1_gmac2_to_sgmii_rgmii(struct mtk_eth *eth, u64 path) + { + unsigned int val = 0; +@@ -165,7 +196,48 @@ static int set_mux_gmac1_gmac2_to_sgmii_ + return 0; + } + +-static int set_mux_gmac12_to_gephy_sgmii(struct mtk_eth *eth, u64 path) ++static int set_mux_gmac123_to_usxgmii(struct mtk_eth *eth, u64 path) ++{ ++ unsigned int val = 0; ++ bool updated = true; ++ int mac_id = 0; ++ ++ /* Disable SYSCFG1 SGMII */ ++ regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); ++ ++ switch (path) { ++ case MTK_ETH_PATH_GMAC1_USXGMII: ++ val &= ~(u32)SYSCFG0_SGMII_GMAC1_V2; ++ mac_id = MTK_GMAC1_ID; ++ break; ++ case MTK_ETH_PATH_GMAC2_USXGMII: ++ val &= ~(u32)SYSCFG0_SGMII_GMAC2_V2; ++ mac_id = MTK_GMAC2_ID; ++ break; ++ case MTK_ETH_PATH_GMAC3_USXGMII: ++ val &= ~(u32)SYSCFG0_SGMII_GMAC3_V2; ++ mac_id = MTK_GMAC3_ID; ++ break; ++ default: ++ updated = false; ++ }; ++ ++ if (updated) { ++ regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, ++ SYSCFG0_SGMII_MASK, val); ++ ++ if (mac_id == MTK_GMAC2_ID) ++ regmap_set_bits(eth->infra, TOP_MISC_NETSYS_PCS_MUX, ++ MUX_G2_USXGMII_SEL); ++ } ++ ++ dev_dbg(eth->dev, "path %s in %s updated = %d\n", ++ mtk_eth_path_name(path), __func__, updated); ++ ++ return 0; ++} ++ ++static int set_mux_gmac123_to_gephy_sgmii(struct mtk_eth *eth, u64 path) + { + unsigned int val = 0; + bool updated = true; +@@ -182,6 +254,9 @@ static int set_mux_gmac12_to_gephy_sgmii + case MTK_ETH_PATH_GMAC2_SGMII: + val |= SYSCFG0_SGMII_GMAC2_V2; + break; ++ case MTK_ETH_PATH_GMAC3_SGMII: ++ val |= SYSCFG0_SGMII_GMAC3_V2; ++ break; + default: + updated = false; + } +@@ -210,13 +285,25 @@ static const struct mtk_eth_muxc mtk_eth + .cap_bit = MTK_ETH_MUX_U3_GMAC2_TO_QPHY, + .set_path = set_mux_u3_gmac2_to_qphy, + }, { ++ .name = "mux_gmac2_to_2p5gphy", ++ .cap_bit = MTK_ETH_MUX_GMAC2_TO_2P5GPHY, ++ .set_path = set_mux_gmac2_to_2p5gphy, ++ }, { + .name = "mux_gmac1_gmac2_to_sgmii_rgmii", + .cap_bit = MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII, + .set_path = set_mux_gmac1_gmac2_to_sgmii_rgmii, + }, { + .name = "mux_gmac12_to_gephy_sgmii", + .cap_bit = MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII, +- .set_path = set_mux_gmac12_to_gephy_sgmii, ++ .set_path = set_mux_gmac123_to_gephy_sgmii, ++ }, { ++ .name = "mux_gmac123_to_gephy_sgmii", ++ .cap_bit = MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII, ++ .set_path = set_mux_gmac123_to_gephy_sgmii, ++ }, { ++ .name = "mux_gmac123_to_usxgmii", ++ .cap_bit = MTK_ETH_MUX_GMAC123_TO_USXGMII, ++ .set_path = set_mux_gmac123_to_usxgmii, + }, + }; + +@@ -249,12 +336,39 @@ out: + return err; + } + ++int mtk_gmac_usxgmii_path_setup(struct mtk_eth *eth, int mac_id) ++{ ++ u64 path; ++ ++ path = (mac_id == MTK_GMAC1_ID) ? MTK_ETH_PATH_GMAC1_USXGMII : ++ (mac_id == MTK_GMAC2_ID) ? MTK_ETH_PATH_GMAC2_USXGMII : ++ MTK_ETH_PATH_GMAC3_USXGMII; ++ ++ /* Setup proper MUXes along the path */ ++ return mtk_eth_mux_setup(eth, path); ++} ++ + int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id) + { + u64 path; + +- path = (mac_id == 0) ? MTK_ETH_PATH_GMAC1_SGMII : +- MTK_ETH_PATH_GMAC2_SGMII; ++ path = (mac_id == MTK_GMAC1_ID) ? MTK_ETH_PATH_GMAC1_SGMII : ++ (mac_id == MTK_GMAC2_ID) ? MTK_ETH_PATH_GMAC2_SGMII : ++ MTK_ETH_PATH_GMAC3_SGMII; ++ ++ /* Setup proper MUXes along the path */ ++ return mtk_eth_mux_setup(eth, path); ++} ++ ++int mtk_gmac_2p5gphy_path_setup(struct mtk_eth *eth, int mac_id) ++{ ++ u64 path = 0; ++ ++ if (mac_id == MTK_GMAC2_ID) ++ path = MTK_ETH_PATH_GMAC2_2P5GPHY; ++ ++ if (!path) ++ return -EINVAL; + + /* Setup proper MUXes along the path */ + return mtk_eth_mux_setup(eth, path); +@@ -284,4 +398,3 @@ int mtk_gmac_rgmii_path_setup(struct mtk + /* Setup proper MUXes along the path */ + return mtk_eth_mux_setup(eth, path); + } +- +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -431,6 +431,30 @@ static void mtk_setup_bridge_switch(stru + MTK_GSW_CFG); + } + ++static bool mtk_check_gmac23_idle(struct mtk_mac *mac) ++{ ++ u32 mac_fsm, gdm_fsm; ++ ++ mac_fsm = mtk_r32(mac->hw, MTK_MAC_FSM(mac->id)); ++ ++ switch (mac->id) { ++ case MTK_GMAC2_ID: ++ gdm_fsm = mtk_r32(mac->hw, MTK_FE_GDM2_FSM); ++ break; ++ case MTK_GMAC3_ID: ++ gdm_fsm = mtk_r32(mac->hw, MTK_FE_GDM3_FSM); ++ break; ++ default: ++ return true; ++ }; ++ ++ if ((mac_fsm & 0xFFFF0000) == 0x01010000 && ++ (gdm_fsm & 0xFFFF0000) == 0x00000000) ++ return true; ++ ++ return false; ++} ++ + static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config, + phy_interface_t interface) + { +@@ -439,12 +463,20 @@ static struct phylink_pcs *mtk_mac_selec + struct mtk_eth *eth = mac->hw; + unsigned int sid; + +- if (interface == PHY_INTERFACE_MODE_SGMII || +- phy_interface_mode_is_8023z(interface)) { +- sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? +- 0 : mac->id; +- +- return eth->sgmii_pcs[sid]; ++ if ((interface == PHY_INTERFACE_MODE_SGMII || ++ phy_interface_mode_is_8023z(interface)) && ++ MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { ++ sid = mtk_mac2xgmii_id(eth, mac->id); ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII)) ++ return mtk_sgmii_wrapper_select_pcs(eth, mac->id); ++ else ++ return eth->sgmii_pcs[sid]; ++ } else if ((interface == PHY_INTERFACE_MODE_USXGMII || ++ interface == PHY_INTERFACE_MODE_10GBASER || ++ interface == PHY_INTERFACE_MODE_5GBASER) && ++ MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII) && ++ mac->id != MTK_GMAC1_ID) { ++ return mtk_usxgmii_select_pcs(eth, mac->id); + } + + return NULL; +@@ -500,7 +532,22 @@ static void mtk_mac_config(struct phylin + goto init_err; + } + break; ++ case PHY_INTERFACE_MODE_USXGMII: ++ case PHY_INTERFACE_MODE_10GBASER: ++ case PHY_INTERFACE_MODE_5GBASER: ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII)) { ++ err = mtk_gmac_usxgmii_path_setup(eth, mac->id); ++ if (err) ++ goto init_err; ++ } ++ break; + case PHY_INTERFACE_MODE_INTERNAL: ++ if (mac->id == MTK_GMAC2_ID && ++ MTK_HAS_CAPS(eth->soc->caps, MTK_2P5GPHY)) { ++ err = mtk_gmac_2p5gphy_path_setup(eth, mac->id); ++ if (err) ++ goto init_err; ++ } + break; + default: + goto err_phy; +@@ -555,8 +602,6 @@ static void mtk_mac_config(struct phylin + val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); + val |= SYSCFG0_GE_MODE(ge_mode, mac->id); + regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); +- +- mac->interface = state->interface; + } + + /* SGMII */ +@@ -573,21 +618,40 @@ static void mtk_mac_config(struct phylin + + /* Save the syscfg0 value for mac_finish */ + mac->syscfg0 = val; +- } else if (phylink_autoneg_inband(mode)) { ++ } else if (state->interface != PHY_INTERFACE_MODE_USXGMII && ++ state->interface != PHY_INTERFACE_MODE_10GBASER && ++ state->interface != PHY_INTERFACE_MODE_5GBASER && ++ phylink_autoneg_inband(mode)) { + dev_err(eth->dev, +- "In-band mode not supported in non SGMII mode!\n"); ++ "In-band mode not supported in non-SerDes modes!\n"); + return; + } + + /* Setup gmac */ +- if (mtk_is_netsys_v3_or_greater(eth) && +- mac->interface == PHY_INTERFACE_MODE_INTERNAL) { +- mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id)); +- mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id)); ++ if (mtk_is_netsys_v3_or_greater(eth)) { ++ if (mtk_interface_mode_is_xgmii(state->interface)) { ++ mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id)); ++ mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id)); ++ ++ if (mac->id == MTK_GMAC1_ID) ++ mtk_setup_bridge_switch(eth); ++ } else { ++ mtk_w32(eth, 0, MTK_GDMA_EG_CTRL(mac->id)); + +- mtk_setup_bridge_switch(eth); ++ /* FIXME: In current hardware design, we have to reset FE ++ * when swtiching XGDM to GDM. Therefore, here trigger an SER ++ * to let GDM go back to the initial state. ++ */ ++ if ((mtk_interface_mode_is_xgmii(mac->interface) || ++ mac->interface == PHY_INTERFACE_MODE_NA) && ++ !mtk_check_gmac23_idle(mac) && ++ !test_bit(MTK_RESETTING, ð->state)) ++ schedule_work(ð->pending_work); ++ } + } + ++ mac->interface = state->interface; ++ + return; + + err_phy: +@@ -633,10 +697,13 @@ static void mtk_mac_link_down(struct phy + { + struct mtk_mac *mac = container_of(config, struct mtk_mac, + phylink_config); +- u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); + +- mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN); +- mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); ++ if (!mtk_interface_mode_is_xgmii(interface)) { ++ mtk_m32(mac->hw, MAC_MCR_TX_EN | MAC_MCR_RX_EN, 0, MTK_MAC_MCR(mac->id)); ++ mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id), 0, MTK_XGMAC_STS(mac->id)); ++ } else if (mac->id != MTK_GMAC1_ID) { ++ mtk_m32(mac->hw, XMAC_MCR_TRX_DISABLE, XMAC_MCR_TRX_DISABLE, MTK_XMAC_MCR(mac->id)); ++ } + } + + static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx, +@@ -708,13 +775,11 @@ static void mtk_set_queue_speed(struct m + mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); + } + +-static void mtk_mac_link_up(struct phylink_config *config, +- struct phy_device *phy, +- unsigned int mode, phy_interface_t interface, +- int speed, int duplex, bool tx_pause, bool rx_pause) ++static void mtk_gdm_mac_link_up(struct mtk_mac *mac, ++ struct phy_device *phy, ++ unsigned int mode, phy_interface_t interface, ++ int speed, int duplex, bool tx_pause, bool rx_pause) + { +- struct mtk_mac *mac = container_of(config, struct mtk_mac, +- phylink_config); + u32 mcr; + + mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); +@@ -748,6 +813,55 @@ static void mtk_mac_link_up(struct phyli + mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); + } + ++static void mtk_xgdm_mac_link_up(struct mtk_mac *mac, ++ struct phy_device *phy, ++ unsigned int mode, phy_interface_t interface, ++ int speed, int duplex, bool tx_pause, bool rx_pause) ++{ ++ u32 mcr, force_link = 0; ++ ++ if (mac->id == MTK_GMAC1_ID) ++ return; ++ ++ /* Eliminate the interference(before link-up) caused by PHY noise */ ++ mtk_m32(mac->hw, XMAC_LOGIC_RST, 0, MTK_XMAC_LOGIC_RST(mac->id)); ++ mdelay(20); ++ mtk_m32(mac->hw, XMAC_GLB_CNTCLR, XMAC_GLB_CNTCLR, MTK_XMAC_CNT_CTRL(mac->id)); ++ ++ if (mac->interface == PHY_INTERFACE_MODE_INTERNAL || mac->id == MTK_GMAC3_ID) ++ force_link = MTK_XGMAC_FORCE_LINK(mac->id); ++ ++ mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id), force_link, MTK_XGMAC_STS(mac->id)); ++ ++ mcr = mtk_r32(mac->hw, MTK_XMAC_MCR(mac->id)); ++ mcr &= ~(XMAC_MCR_FORCE_TX_FC | XMAC_MCR_FORCE_RX_FC | XMAC_MCR_TRX_DISABLE); ++ /* Configure pause modes - ++ * phylink will avoid these for half duplex ++ */ ++ if (tx_pause) ++ mcr |= XMAC_MCR_FORCE_TX_FC; ++ if (rx_pause) ++ mcr |= XMAC_MCR_FORCE_RX_FC; ++ ++ mtk_w32(mac->hw, mcr, MTK_XMAC_MCR(mac->id)); ++} ++ ++static void mtk_mac_link_up(struct phylink_config *config, ++ struct phy_device *phy, ++ unsigned int mode, phy_interface_t interface, ++ int speed, int duplex, bool tx_pause, bool rx_pause) ++{ ++ struct mtk_mac *mac = container_of(config, struct mtk_mac, ++ phylink_config); ++ ++ if (mtk_interface_mode_is_xgmii(interface)) ++ mtk_xgdm_mac_link_up(mac, phy, mode, interface, speed, duplex, ++ tx_pause, rx_pause); ++ else ++ mtk_gdm_mac_link_up(mac, phy, mode, interface, speed, duplex, ++ tx_pause, rx_pause); ++} ++ + static const struct phylink_mac_ops mtk_phylink_ops = { + .validate = phylink_generic_validate, + .mac_select_pcs = mtk_mac_select_pcs, +@@ -4558,8 +4672,21 @@ static int mtk_add_mac(struct mtk_eth *e + phy_interface_zero(mac->phylink_config.supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_INTERNAL, + mac->phylink_config.supported_interfaces); ++ } else if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_USXGMII)) { ++ mac->phylink_config.mac_capabilities |= MAC_5000FD | MAC_10000FD; ++ __set_bit(PHY_INTERFACE_MODE_5GBASER, ++ mac->phylink_config.supported_interfaces); ++ __set_bit(PHY_INTERFACE_MODE_10GBASER, ++ mac->phylink_config.supported_interfaces); ++ __set_bit(PHY_INTERFACE_MODE_USXGMII, ++ mac->phylink_config.supported_interfaces); + } + ++ if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_2P5GPHY) && ++ id == MTK_GMAC2_ID) ++ __set_bit(PHY_INTERFACE_MODE_INTERNAL, ++ mac->phylink_config.supported_interfaces); ++ + phylink = phylink_create(&mac->phylink_config, + of_fwnode_handle(mac->of_node), + phy_mode, &mtk_phylink_ops); +@@ -4752,6 +4879,13 @@ static int mtk_probe(struct platform_dev + + if (err) + return err; ++ } ++ ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII)) { ++ err = mtk_usxgmii_init(eth); ++ ++ if (err) ++ return err; + } + + if (eth->soc->required_pctl) { +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -499,6 +499,21 @@ + #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) + #define INTF_MODE_RGMII_10_100 0 + ++/* XFI Mac control registers */ ++#define MTK_XMAC_BASE(x) (0x12000 + (((x) - 1) * 0x1000)) ++#define MTK_XMAC_MCR(x) (MTK_XMAC_BASE(x)) ++#define XMAC_MCR_TRX_DISABLE 0xf ++#define XMAC_MCR_FORCE_TX_FC BIT(5) ++#define XMAC_MCR_FORCE_RX_FC BIT(4) ++ ++/* XFI Mac logic reset registers */ ++#define MTK_XMAC_LOGIC_RST(x) (MTK_XMAC_BASE(x) + 0x10) ++#define XMAC_LOGIC_RST BIT(0) ++ ++/* XFI Mac count global control */ ++#define MTK_XMAC_CNT_CTRL(x) (MTK_XMAC_BASE(x) + 0x100) ++#define XMAC_GLB_CNTCLR BIT(0) ++ + /* GPIO port control registers for GMAC 2*/ + #define GPIO_OD33_CTRL8 0x4c0 + #define GPIO_BIAS_CTRL 0xed0 +@@ -524,6 +539,7 @@ + #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) + #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) + #define SYSCFG0_SGMII_GMAC2_V2 BIT(8) ++#define SYSCFG0_SGMII_GMAC3_V2 BIT(7) + + + /* ethernet subsystem clock register */ +@@ -556,12 +572,74 @@ + #define ETHSYS_DMA_AG_MAP_QDMA BIT(1) + #define ETHSYS_DMA_AG_MAP_PPE BIT(2) + ++/* USXGMII subsystem config registers */ ++/* Register to control speed */ ++#define RG_PHY_TOP_SPEED_CTRL1 0x80C ++#define USXGMII_RATE_UPDATE_MODE BIT(31) ++#define USXGMII_MAC_CK_GATED BIT(29) ++#define USXGMII_IF_FORCE_EN BIT(28) ++#define USXGMII_RATE_ADAPT_MODE GENMASK(10, 8) ++#define USXGMII_RATE_ADAPT_MODE_X1 0 ++#define USXGMII_RATE_ADAPT_MODE_X2 1 ++#define USXGMII_RATE_ADAPT_MODE_X4 2 ++#define USXGMII_RATE_ADAPT_MODE_X10 3 ++#define USXGMII_RATE_ADAPT_MODE_X100 4 ++#define USXGMII_RATE_ADAPT_MODE_X5 5 ++#define USXGMII_RATE_ADAPT_MODE_X50 6 ++#define USXGMII_XFI_RX_MODE GENMASK(6, 4) ++#define USXGMII_XFI_RX_MODE_10G 0 ++#define USXGMII_XFI_RX_MODE_5G 1 ++#define USXGMII_XFI_TX_MODE GENMASK(2, 0) ++#define USXGMII_XFI_TX_MODE_10G 0 ++#define USXGMII_XFI_TX_MODE_5G 1 ++ ++/* Register to control PCS AN */ ++#define RG_PCS_AN_CTRL0 0x810 ++#define USXGMII_AN_RESTART BIT(31) ++#define USXGMII_AN_SYNC_CNT GENMASK(30, 11) ++#define USXGMII_AN_ENABLE BIT(0) ++ ++#define RG_PCS_AN_CTRL2 0x818 ++#define USXGMII_LINK_TIMER_IDLE_DETECT GENMASK(29, 20) ++#define USXGMII_LINK_TIMER_COMP_ACK_DETECT GENMASK(19, 10) ++#define USXGMII_LINK_TIMER_AN_RESTART GENMASK(9, 0) ++ ++/* Register to read PCS AN status */ ++#define RG_PCS_AN_STS0 0x81c ++#define USXGMII_PCS_AN_WORD GENMASK(15, 0) ++#define USXGMII_LPA_LATCH BIT(31) ++ ++/* Register to control USXGMII XFI PLL digital */ ++#define XFI_PLL_DIG_GLB8 0x08 ++#define RG_XFI_PLL_EN BIT(31) ++ ++/* Register to control USXGMII XFI PLL analog */ ++#define XFI_PLL_ANA_GLB8 0x108 ++#define RG_XFI_PLL_ANA_SWWA 0x02283248 ++ + /* Infrasys subsystem config registers */ + #define INFRA_MISC2 0x70c + #define CO_QPHY_SEL BIT(0) + #define GEPHY_MAC_SEL BIT(1) + ++/* Toprgu subsystem config registers */ ++#define TOPRGU_SWSYSRST 0x18 ++#define SWSYSRST_UNLOCK_KEY GENMASK(31, 24) ++#define SWSYSRST_XFI_PLL_GRST BIT(16) ++#define SWSYSRST_XFI_PEXPT1_GRST BIT(15) ++#define SWSYSRST_XFI_PEXPT0_GRST BIT(14) ++#define SWSYSRST_XFI1_GRST BIT(13) ++#define SWSYSRST_XFI0_GRST BIT(12) ++#define SWSYSRST_SGMII1_GRST BIT(2) ++#define SWSYSRST_SGMII0_GRST BIT(1) ++#define TOPRGU_SWSYSRST_EN 0xFC ++ + /* Top misc registers */ ++#define TOP_MISC_NETSYS_PCS_MUX 0x84 ++#define NETSYS_PCS_MUX_MASK GENMASK(1, 0) ++#define MUX_G2_USXGMII_SEL BIT(1) ++#define MUX_HSGMII1_G1_SEL BIT(0) ++ + #define USB_PHY_SWITCH_REG 0x218 + #define QPHY_SEL_MASK GENMASK(1, 0) + #define SGMII_QPHY_SEL 0x2 +@@ -586,6 +664,8 @@ + #define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c) + #define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110) + ++/* Debug Purpose Register */ ++#define MTK_PSE_FQFC_CFG 0x100 + #define MTK_FE_CDM1_FSM 0x220 + #define MTK_FE_CDM2_FSM 0x224 + #define MTK_FE_CDM3_FSM 0x238 +@@ -594,6 +674,11 @@ + #define MTK_FE_CDM6_FSM 0x328 + #define MTK_FE_GDM1_FSM 0x228 + #define MTK_FE_GDM2_FSM 0x22C ++#define MTK_FE_GDM3_FSM 0x23C ++#define MTK_FE_PSE_FREE 0x240 ++#define MTK_FE_DROP_FQ 0x244 ++#define MTK_FE_DROP_FC 0x248 ++#define MTK_FE_DROP_PPE 0x24C + + #define MTK_MAC_FSM(x) (0x1010C + ((x) * 0x100)) + +@@ -940,6 +1025,8 @@ enum mkt_eth_capabilities { + MTK_RGMII_BIT = 0, + MTK_TRGMII_BIT, + MTK_SGMII_BIT, ++ MTK_USXGMII_BIT, ++ MTK_2P5GPHY_BIT, + MTK_ESW_BIT, + MTK_GEPHY_BIT, + MTK_MUX_BIT, +@@ -960,8 +1047,11 @@ enum mkt_eth_capabilities { + MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, + MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT, + MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, ++ MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT, + MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, + MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, ++ MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT, ++ MTK_ETH_MUX_GMAC123_TO_USXGMII_BIT, + + /* PATH BITS */ + MTK_ETH_PATH_GMAC1_RGMII_BIT, +@@ -969,14 +1059,21 @@ enum mkt_eth_capabilities { + MTK_ETH_PATH_GMAC1_SGMII_BIT, + MTK_ETH_PATH_GMAC2_RGMII_BIT, + MTK_ETH_PATH_GMAC2_SGMII_BIT, ++ MTK_ETH_PATH_GMAC2_2P5GPHY_BIT, + MTK_ETH_PATH_GMAC2_GEPHY_BIT, ++ MTK_ETH_PATH_GMAC3_SGMII_BIT, + MTK_ETH_PATH_GDM1_ESW_BIT, ++ MTK_ETH_PATH_GMAC1_USXGMII_BIT, ++ MTK_ETH_PATH_GMAC2_USXGMII_BIT, ++ MTK_ETH_PATH_GMAC3_USXGMII_BIT, + }; + + /* Supported hardware group on SoCs */ + #define MTK_RGMII BIT_ULL(MTK_RGMII_BIT) + #define MTK_TRGMII BIT_ULL(MTK_TRGMII_BIT) + #define MTK_SGMII BIT_ULL(MTK_SGMII_BIT) ++#define MTK_USXGMII BIT_ULL(MTK_USXGMII_BIT) ++#define MTK_2P5GPHY BIT_ULL(MTK_2P5GPHY_BIT) + #define MTK_ESW BIT_ULL(MTK_ESW_BIT) + #define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT) + #define MTK_MUX BIT_ULL(MTK_MUX_BIT) +@@ -999,10 +1096,16 @@ enum mkt_eth_capabilities { + BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) + #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ + BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) ++#define MTK_ETH_MUX_GMAC2_TO_2P5GPHY \ ++ BIT_ULL(MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT) + #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ + BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) + #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ + BIT_ULL(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) ++#define MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII \ ++ BIT_ULL(MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT) ++#define MTK_ETH_MUX_GMAC123_TO_USXGMII \ ++ BIT_ULL(MTK_ETH_MUX_GMAC123_TO_USXGMII_BIT) + + /* Supported path present on SoCs */ + #define MTK_ETH_PATH_GMAC1_RGMII BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT) +@@ -1010,8 +1113,13 @@ enum mkt_eth_capabilities { + #define MTK_ETH_PATH_GMAC1_SGMII BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT) + #define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT) + #define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT) ++#define MTK_ETH_PATH_GMAC2_2P5GPHY BIT_ULL(MTK_ETH_PATH_GMAC2_2P5GPHY_BIT) + #define MTK_ETH_PATH_GMAC2_GEPHY BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT) ++#define MTK_ETH_PATH_GMAC3_SGMII BIT_ULL(MTK_ETH_PATH_GMAC3_SGMII_BIT) + #define MTK_ETH_PATH_GDM1_ESW BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT) ++#define MTK_ETH_PATH_GMAC1_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC1_USXGMII_BIT) ++#define MTK_ETH_PATH_GMAC2_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC2_USXGMII_BIT) ++#define MTK_ETH_PATH_GMAC3_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC3_USXGMII_BIT) + + #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) + #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) +@@ -1019,7 +1127,12 @@ enum mkt_eth_capabilities { + #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) + #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) + #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) ++#define MTK_GMAC2_2P5GPHY (MTK_ETH_PATH_GMAC2_2P5GPHY | MTK_2P5GPHY) ++#define MTK_GMAC3_SGMII (MTK_ETH_PATH_GMAC3_SGMII | MTK_SGMII) + #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) ++#define MTK_GMAC1_USXGMII (MTK_ETH_PATH_GMAC1_USXGMII | MTK_USXGMII) ++#define MTK_GMAC2_USXGMII (MTK_ETH_PATH_GMAC2_USXGMII | MTK_USXGMII) ++#define MTK_GMAC3_USXGMII (MTK_ETH_PATH_GMAC3_USXGMII | MTK_USXGMII) + + /* MUXes present on SoCs */ + /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ +@@ -1038,10 +1151,20 @@ enum mkt_eth_capabilities { + (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \ + MTK_SHARED_SGMII) + ++/* 2: GMAC2 -> XGMII */ ++#define MTK_MUX_GMAC2_TO_2P5GPHY \ ++ (MTK_ETH_MUX_GMAC2_TO_2P5GPHY | MTK_MUX | MTK_INFRA) ++ + /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */ + #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ + (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) + ++#define MTK_MUX_GMAC123_TO_GEPHY_SGMII \ ++ (MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII | MTK_MUX) ++ ++#define MTK_MUX_GMAC123_TO_USXGMII \ ++ (MTK_ETH_MUX_GMAC123_TO_USXGMII | MTK_MUX | MTK_INFRA) ++ + #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) + + #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ +@@ -1073,8 +1196,12 @@ enum mkt_eth_capabilities { + MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ + MTK_RSTCTRL_PPE1 | MTK_SRAM) + +-#define MT7988_CAPS (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_QDMA | \ +- MTK_RSTCTRL_PPE1 | MTK_RSTCTRL_PPE2 | MTK_SRAM) ++#define MT7988_CAPS (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_GMAC1_SGMII | \ ++ MTK_GMAC2_2P5GPHY | MTK_GMAC2_SGMII | MTK_GMAC2_USXGMII | \ ++ MTK_GMAC3_SGMII | MTK_GMAC3_USXGMII | \ ++ MTK_MUX_GMAC123_TO_GEPHY_SGMII | \ ++ MTK_MUX_GMAC123_TO_USXGMII | MTK_MUX_GMAC2_TO_2P5GPHY | \ ++ MTK_QDMA | MTK_RSTCTRL_PPE1 | MTK_RSTCTRL_PPE2 | MTK_SRAM) + + struct mtk_tx_dma_desc_info { + dma_addr_t addr; +@@ -1184,6 +1311,24 @@ struct mtk_soc_data { + /* currently no SoC has more than 3 macs */ + #define MTK_MAX_DEVS 3 + ++/* struct mtk_usxgmii_pcs - This structure holds each usxgmii regmap and ++ * associated data ++ * @regmap: The register map pointing at the range used to setup ++ * USXGMII modes ++ * @interface: Currently selected interface mode ++ * @id: The element is used to record the index of PCS ++ * @pcs: Phylink PCS structure ++ */ ++struct mtk_usxgmii_pcs { ++ struct mtk_eth *eth; ++ struct regmap *regmap; ++ struct phylink_pcs *wrapped_sgmii_pcs; ++ phy_interface_t interface; ++ u8 id; ++ unsigned int mode; ++ struct phylink_pcs pcs; ++}; ++ + /* struct mtk_eth - This is the main datasructure for holding the state + * of the driver + * @dev: The device pointer +@@ -1204,6 +1349,12 @@ struct mtk_soc_data { + * @infra: The register map pointing at the range used to setup + * SGMII and GePHY path + * @sgmii_pcs: Pointers to mtk-pcs-lynxi phylink_pcs instances ++ * @sgmii_wrapped_pcs: Pointers to NETSYSv3 wrapper PCS instances ++ * @usxgmii_pll: The register map pointing at the range used to control ++ * the USXGMII SerDes PLL ++ * @regmap_pextp: The register map pointing at the range used to setup ++ * PHYA ++ * @usxgmii_pcs: Pointer to array of pointers to struct for USXGMII PCS + * @pctl: The register map pointing at the range used to setup + * GMAC port drive/slew values + * @dma_refcnt: track how many netdevs are using the DMA engine +@@ -1247,6 +1398,10 @@ struct mtk_eth { + struct regmap *ethsys; + struct regmap *infra; + struct phylink_pcs *sgmii_pcs[MTK_MAX_DEVS]; ++ struct regmap *toprgu; ++ struct regmap *usxgmii_pll; ++ struct regmap *regmap_pextp[MTK_MAX_DEVS]; ++ struct mtk_usxgmii_pcs *usxgmii_pcs[MTK_MAX_DEVS]; + struct regmap *pctl; + bool hwlro; + refcount_t dma_refcnt; +@@ -1434,6 +1589,19 @@ static inline u32 mtk_get_ib2_multicast_ + return MTK_FOE_IB2_MULTICAST; + } + ++static inline bool mtk_interface_mode_is_xgmii(phy_interface_t interface) ++{ ++ switch (interface) { ++ case PHY_INTERFACE_MODE_INTERNAL: ++ case PHY_INTERFACE_MODE_USXGMII: ++ case PHY_INTERFACE_MODE_10GBASER: ++ case PHY_INTERFACE_MODE_5GBASER: ++ return true; ++ default: ++ return false; ++ } ++} ++ + /* read the hardware status register */ + void mtk_stats_update_mac(struct mtk_mac *mac); + +@@ -1442,8 +1610,10 @@ u32 mtk_r32(struct mtk_eth *eth, unsigne + u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg); + + int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); ++int mtk_gmac_2p5gphy_path_setup(struct mtk_eth *eth, int mac_id); + int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); + int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); ++int mtk_gmac_usxgmii_path_setup(struct mtk_eth *eth, int mac_id); + + int mtk_eth_offload_init(struct mtk_eth *eth); + int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, +@@ -1453,5 +1623,63 @@ int mtk_flow_offload_cmd(struct mtk_eth + void mtk_flow_offload_cleanup(struct mtk_eth *eth, struct list_head *list); + void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev); + ++static inline int mtk_mac2xgmii_id(struct mtk_eth *eth, int mac_id) ++{ ++ int xgmii_id = mac_id; ++ ++ if (mtk_is_netsys_v3_or_greater(eth)) { ++ switch (mac_id) { ++ case MTK_GMAC1_ID: ++ case MTK_GMAC2_ID: ++ xgmii_id = 1; ++ break; ++ case MTK_GMAC3_ID: ++ xgmii_id = 0; ++ break; ++ default: ++ xgmii_id = -1; ++ } ++ } ++ ++ return MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII) ? 0 : xgmii_id; ++} ++ ++static inline int mtk_xgmii2mac_id(struct mtk_eth *eth, int xgmii_id) ++{ ++ int mac_id = xgmii_id; ++ ++ if (mtk_is_netsys_v3_or_greater(eth)) { ++ switch (xgmii_id) { ++ case 0: ++ mac_id = 2; ++ break; ++ case 1: ++ mac_id = 1; ++ break; ++ default: ++ mac_id = -1; ++ } ++ } ++ ++ return mac_id; ++} ++ ++#ifdef CONFIG_NET_MEDIATEK_SOC_USXGMII ++struct phylink_pcs *mtk_sgmii_wrapper_select_pcs(struct mtk_eth *eth, int id); ++struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int id); ++int mtk_usxgmii_init(struct mtk_eth *eth); ++#else ++static inline struct phylink_pcs *mtk_sgmii_wrapper_select_pcs(struct mtk_eth *eth, int id) ++{ ++ return NULL; ++} ++ ++static inline struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int id) ++{ ++ return NULL; ++} ++ ++static inline int mtk_usxgmii_init(struct mtk_eth *eth) { return 0; } ++#endif /* NET_MEDIATEK_SOC_USXGMII */ + + #endif /* MTK_ETH_H */ +--- /dev/null ++++ b/drivers/net/ethernet/mediatek/mtk_usxgmii.c +@@ -0,0 +1,690 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2023 MediaTek Inc. ++ * Author: Henry Yen ++ * Daniel Golle ++ */ ++ ++#include ++#include ++#include ++#include "mtk_eth_soc.h" ++ ++static struct mtk_usxgmii_pcs *pcs_to_mtk_usxgmii_pcs(struct phylink_pcs *pcs) ++{ ++ return container_of(pcs, struct mtk_usxgmii_pcs, pcs); ++} ++ ++static int mtk_xfi_pextp_init(struct mtk_eth *eth) ++{ ++ struct device *dev = eth->dev; ++ struct device_node *r = dev->of_node; ++ struct device_node *np; ++ int i; ++ ++ for (i = 0; i < MTK_MAX_DEVS; i++) { ++ np = of_parse_phandle(r, "mediatek,xfi-pextp", i); ++ if (!np) ++ break; ++ ++ eth->regmap_pextp[i] = syscon_node_to_regmap(np); ++ if (IS_ERR(eth->regmap_pextp[i])) ++ return PTR_ERR(eth->regmap_pextp[i]); ++ } ++ ++ return 0; ++} ++ ++static int mtk_xfi_pll_init(struct mtk_eth *eth) ++{ ++ struct device_node *r = eth->dev->of_node; ++ struct device_node *np; ++ ++ np = of_parse_phandle(r, "mediatek,xfi-pll", 0); ++ if (!np) ++ return -1; ++ ++ eth->usxgmii_pll = syscon_node_to_regmap(np); ++ if (IS_ERR(eth->usxgmii_pll)) ++ return PTR_ERR(eth->usxgmii_pll); ++ ++ return 0; ++} ++ ++static int mtk_toprgu_init(struct mtk_eth *eth) ++{ ++ struct device_node *r = eth->dev->of_node; ++ struct device_node *np; ++ ++ np = of_parse_phandle(r, "mediatek,toprgu", 0); ++ if (!np) ++ return -1; ++ ++ eth->toprgu = syscon_node_to_regmap(np); ++ if (IS_ERR(eth->toprgu)) ++ return PTR_ERR(eth->toprgu); ++ ++ return 0; ++} ++ ++static int mtk_xfi_pll_enable(struct mtk_eth *eth) ++{ ++ u32 val = 0; ++ ++ if (!eth->usxgmii_pll) ++ return -EINVAL; ++ ++ /* Add software workaround for USXGMII PLL TCL issue */ ++ regmap_write(eth->usxgmii_pll, XFI_PLL_ANA_GLB8, RG_XFI_PLL_ANA_SWWA); ++ ++ regmap_read(eth->usxgmii_pll, XFI_PLL_DIG_GLB8, &val); ++ val |= RG_XFI_PLL_EN; ++ regmap_write(eth->usxgmii_pll, XFI_PLL_DIG_GLB8, val); ++ ++ return 0; ++} ++ ++static void mtk_usxgmii_setup_phya(struct regmap *pextp, phy_interface_t interface, int id) ++{ ++ bool is_10g = (interface == PHY_INTERFACE_MODE_10GBASER || ++ interface == PHY_INTERFACE_MODE_USXGMII); ++ bool is_2p5g = (interface == PHY_INTERFACE_MODE_2500BASEX); ++ bool is_5g = (interface == PHY_INTERFACE_MODE_5GBASER); ++ ++ /* Setup operation mode */ ++ if (is_10g) ++ regmap_write(pextp, 0x9024, 0x00C9071C); ++ else ++ regmap_write(pextp, 0x9024, 0x00D9071C); ++ ++ if (is_5g) ++ regmap_write(pextp, 0x2020, 0xAAA5A5AA); ++ else ++ regmap_write(pextp, 0x2020, 0xAA8585AA); ++ ++ if (is_2p5g || is_5g || is_10g) { ++ regmap_write(pextp, 0x2030, 0x0C020707); ++ regmap_write(pextp, 0x2034, 0x0E050F0F); ++ regmap_write(pextp, 0x2040, 0x00140032); ++ } else { ++ regmap_write(pextp, 0x2030, 0x0C020207); ++ regmap_write(pextp, 0x2034, 0x0E05050F); ++ regmap_write(pextp, 0x2040, 0x00200032); ++ } ++ ++ if (is_2p5g || is_10g) ++ regmap_write(pextp, 0x50F0, 0x00C014AA); ++ else if (is_5g) ++ regmap_write(pextp, 0x50F0, 0x00C018AA); ++ else ++ regmap_write(pextp, 0x50F0, 0x00C014BA); ++ ++ if (is_5g) { ++ regmap_write(pextp, 0x50E0, 0x3777812B); ++ regmap_write(pextp, 0x506C, 0x005C9CFF); ++ regmap_write(pextp, 0x5070, 0x9DFAFAFA); ++ regmap_write(pextp, 0x5074, 0x273F3F3F); ++ regmap_write(pextp, 0x5078, 0xA8883868); ++ regmap_write(pextp, 0x507C, 0x14661466); ++ } else { ++ regmap_write(pextp, 0x50E0, 0x3777C12B); ++ regmap_write(pextp, 0x506C, 0x005F9CFF); ++ regmap_write(pextp, 0x5070, 0x9D9DFAFA); ++ regmap_write(pextp, 0x5074, 0x27273F3F); ++ regmap_write(pextp, 0x5078, 0xA7883C68); ++ regmap_write(pextp, 0x507C, 0x11661166); ++ } ++ ++ if (is_2p5g || is_10g) { ++ regmap_write(pextp, 0x5080, 0x0E000AAF); ++ regmap_write(pextp, 0x5084, 0x08080D0D); ++ regmap_write(pextp, 0x5088, 0x02030909); ++ } else if (is_5g) { ++ regmap_write(pextp, 0x5080, 0x0E001ABF); ++ regmap_write(pextp, 0x5084, 0x080B0D0D); ++ regmap_write(pextp, 0x5088, 0x02050909); ++ } else { ++ regmap_write(pextp, 0x5080, 0x0E000EAF); ++ regmap_write(pextp, 0x5084, 0x08080E0D); ++ regmap_write(pextp, 0x5088, 0x02030B09); ++ } ++ ++ if (is_5g) { ++ regmap_write(pextp, 0x50E4, 0x0C000000); ++ regmap_write(pextp, 0x50E8, 0x04000000); ++ } else { ++ regmap_write(pextp, 0x50E4, 0x0C0C0000); ++ regmap_write(pextp, 0x50E8, 0x04040000); ++ } ++ ++ if (is_2p5g || mtk_interface_mode_is_xgmii(interface)) ++ regmap_write(pextp, 0x50EC, 0x0F0F0C06); ++ else ++ regmap_write(pextp, 0x50EC, 0x0F0F0606); ++ ++ if (is_5g) { ++ regmap_write(pextp, 0x50A8, 0x50808C8C); ++ regmap_write(pextp, 0x6004, 0x18000000); ++ } else { ++ regmap_write(pextp, 0x50A8, 0x506E8C8C); ++ regmap_write(pextp, 0x6004, 0x18190000); ++ } ++ ++ if (is_10g) ++ regmap_write(pextp, 0x00F8, 0x01423342); ++ else if (is_5g) ++ regmap_write(pextp, 0x00F8, 0x00A132A1); ++ else if (is_2p5g) ++ regmap_write(pextp, 0x00F8, 0x009C329C); ++ else ++ regmap_write(pextp, 0x00F8, 0x00FA32FA); ++ ++ /* Force SGDT_OUT off and select PCS */ ++ if (mtk_interface_mode_is_xgmii(interface)) ++ regmap_write(pextp, 0x00F4, 0x80201F20); ++ else ++ regmap_write(pextp, 0x00F4, 0x80201F21); ++ ++ /* Force GLB_CKDET_OUT */ ++ regmap_write(pextp, 0x0030, 0x00050C00); ++ ++ /* Force AEQ on */ ++ regmap_write(pextp, 0x0070, 0x02002800); ++ ndelay(1020); ++ ++ /* Setup DA default value */ ++ regmap_write(pextp, 0x30B0, 0x00000020); ++ regmap_write(pextp, 0x3028, 0x00008A01); ++ regmap_write(pextp, 0x302C, 0x0000A884); ++ regmap_write(pextp, 0x3024, 0x00083002); ++ if (mtk_interface_mode_is_xgmii(interface)) { ++ regmap_write(pextp, 0x3010, 0x00022220); ++ regmap_write(pextp, 0x5064, 0x0F020A01); ++ regmap_write(pextp, 0x50B4, 0x06100600); ++ if (interface == PHY_INTERFACE_MODE_USXGMII) ++ regmap_write(pextp, 0x3048, 0x40704000); ++ else ++ regmap_write(pextp, 0x3048, 0x47684100); ++ } else { ++ regmap_write(pextp, 0x3010, 0x00011110); ++ regmap_write(pextp, 0x3048, 0x40704000); ++ } ++ ++ if (!mtk_interface_mode_is_xgmii(interface) && !is_2p5g) ++ regmap_write(pextp, 0x3064, 0x0000C000); ++ ++ if (interface == PHY_INTERFACE_MODE_USXGMII) { ++ regmap_write(pextp, 0x3050, 0xA8000000); ++ regmap_write(pextp, 0x3054, 0x000000AA); ++ } else if (mtk_interface_mode_is_xgmii(interface)) { ++ regmap_write(pextp, 0x3050, 0x00000000); ++ regmap_write(pextp, 0x3054, 0x00000000); ++ } else { ++ regmap_write(pextp, 0x3050, 0xA8000000); ++ regmap_write(pextp, 0x3054, 0x000000AA); ++ } ++ ++ if (mtk_interface_mode_is_xgmii(interface)) ++ regmap_write(pextp, 0x306C, 0x00000F00); ++ else if (is_2p5g) ++ regmap_write(pextp, 0x306C, 0x22000F00); ++ else ++ regmap_write(pextp, 0x306C, 0x20200F00); ++ ++ if (interface == PHY_INTERFACE_MODE_10GBASER && id == 0) ++ regmap_write(pextp, 0xA008, 0x0007B400); ++ ++ if (mtk_interface_mode_is_xgmii(interface)) ++ regmap_write(pextp, 0xA060, 0x00040000); ++ else ++ regmap_write(pextp, 0xA060, 0x00050000); ++ ++ if (is_10g) ++ regmap_write(pextp, 0x90D0, 0x00000001); ++ else if (is_5g) ++ regmap_write(pextp, 0x90D0, 0x00000003); ++ else if (is_2p5g) ++ regmap_write(pextp, 0x90D0, 0x00000005); ++ else ++ regmap_write(pextp, 0x90D0, 0x00000007); ++ ++ /* Release reset */ ++ regmap_write(pextp, 0x0070, 0x0200E800); ++ usleep_range(150, 500); ++ ++ /* Switch to P0 */ ++ regmap_write(pextp, 0x0070, 0x0200C111); ++ ndelay(1020); ++ regmap_write(pextp, 0x0070, 0x0200C101); ++ usleep_range(15, 50); ++ ++ if (mtk_interface_mode_is_xgmii(interface)) { ++ /* Switch to Gen3 */ ++ regmap_write(pextp, 0x0070, 0x0202C111); ++ } else { ++ /* Switch to Gen2 */ ++ regmap_write(pextp, 0x0070, 0x0201C111); ++ } ++ ndelay(1020); ++ if (mtk_interface_mode_is_xgmii(interface)) ++ regmap_write(pextp, 0x0070, 0x0202C101); ++ else ++ regmap_write(pextp, 0x0070, 0x0201C101); ++ usleep_range(100, 500); ++ regmap_write(pextp, 0x30B0, 0x00000030); ++ if (mtk_interface_mode_is_xgmii(interface)) ++ regmap_write(pextp, 0x00F4, 0x80201F00); ++ else ++ regmap_write(pextp, 0x00F4, 0x80201F01); ++ ++ regmap_write(pextp, 0x3040, 0x30000000); ++ usleep_range(400, 1000); ++} ++ ++static void mtk_usxgmii_reset(struct mtk_eth *eth, int id) ++{ ++ u32 toggle, val; ++ ++ if (id >= MTK_MAX_DEVS || !eth->toprgu) ++ return; ++ ++ switch (id) { ++ case 0: ++ toggle = SWSYSRST_XFI_PEXPT0_GRST | SWSYSRST_XFI0_GRST | ++ SWSYSRST_SGMII0_GRST; ++ break; ++ case 1: ++ toggle = SWSYSRST_XFI_PEXPT1_GRST | SWSYSRST_XFI1_GRST | ++ SWSYSRST_SGMII1_GRST; ++ break; ++ default: ++ return; ++ } ++ ++ /* Enable software reset */ ++ regmap_set_bits(eth->toprgu, TOPRGU_SWSYSRST_EN, toggle); ++ ++ /* Assert USXGMII reset */ ++ regmap_set_bits(eth->toprgu, TOPRGU_SWSYSRST, ++ FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88) | toggle); ++ ++ usleep_range(100, 500); ++ ++ /* De-assert USXGMII reset */ ++ regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val); ++ val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88); ++ val &= ~toggle; ++ regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val); ++ ++ /* Disable software reset */ ++ regmap_clear_bits(eth->toprgu, TOPRGU_SWSYSRST_EN, toggle); ++ ++ mdelay(10); ++} ++ ++/* As the USXGMII PHYA is shared with the 1000Base-X/2500Base-X/Cisco SGMII unit ++ * the psc-mtk-lynxi instance needs to be wrapped, so that calls to .pcs_config ++ * also trigger an initial reset and subsequent configuration of the PHYA. ++ */ ++struct mtk_sgmii_wrapper_pcs { ++ struct mtk_eth *eth; ++ struct phylink_pcs *wrapped_pcs; ++ u8 id; ++ struct phylink_pcs pcs; ++}; ++ ++static int mtk_sgmii_wrapped_pcs_config(struct phylink_pcs *pcs, ++ unsigned int mode, ++ phy_interface_t interface, ++ const unsigned long *advertising, ++ bool permit_pause_to_mac) ++{ ++ struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs); ++ bool full_reconf; ++ int ret; ++ ++ full_reconf = interface != wp->eth->usxgmii_pcs[wp->id]->interface; ++ if (full_reconf) { ++ mtk_xfi_pll_enable(wp->eth); ++ mtk_usxgmii_reset(wp->eth, wp->id); ++ } ++ ++ ret = wp->wrapped_pcs->ops->pcs_config(wp->wrapped_pcs, mode, interface, ++ advertising, permit_pause_to_mac); ++ ++ if (full_reconf) ++ mtk_usxgmii_setup_phya(wp->eth->regmap_pextp[wp->id], interface, wp->id); ++ ++ wp->eth->usxgmii_pcs[wp->id]->interface = interface; ++ ++ return ret; ++} ++ ++static void mtk_sgmii_wrapped_pcs_get_state(struct phylink_pcs *pcs, ++ struct phylink_link_state *state) ++{ ++ struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs); ++ ++ return wp->wrapped_pcs->ops->pcs_get_state(wp->wrapped_pcs, state); ++} ++ ++static void mtk_sgmii_wrapped_pcs_an_restart(struct phylink_pcs *pcs) ++{ ++ struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs); ++ ++ wp->wrapped_pcs->ops->pcs_an_restart(wp->wrapped_pcs); ++} ++ ++static void mtk_sgmii_wrapped_pcs_link_up(struct phylink_pcs *pcs, ++ unsigned int mode, ++ phy_interface_t interface, int speed, ++ int duplex) ++{ ++ struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs); ++ ++ wp->wrapped_pcs->ops->pcs_link_up(wp->wrapped_pcs, mode, interface, speed, duplex); ++} ++ ++static void mtk_sgmii_wrapped_pcs_disable(struct phylink_pcs *pcs) ++{ ++ struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs); ++ ++ wp->wrapped_pcs->ops->pcs_disable(wp->wrapped_pcs); ++ ++ wp->eth->usxgmii_pcs[wp->id]->interface = PHY_INTERFACE_MODE_NA; ++} ++ ++static const struct phylink_pcs_ops mtk_sgmii_wrapped_pcs_ops = { ++ .pcs_get_state = mtk_sgmii_wrapped_pcs_get_state, ++ .pcs_config = mtk_sgmii_wrapped_pcs_config, ++ .pcs_an_restart = mtk_sgmii_wrapped_pcs_an_restart, ++ .pcs_link_up = mtk_sgmii_wrapped_pcs_link_up, ++ .pcs_disable = mtk_sgmii_wrapped_pcs_disable, ++}; ++ ++static int mtk_sgmii_wrapper_init(struct mtk_eth *eth) ++{ ++ struct mtk_sgmii_wrapper_pcs *wp; ++ int i; ++ ++ for (i = 0; i < MTK_MAX_DEVS; i++) { ++ if (!eth->sgmii_pcs[i]) ++ continue; ++ ++ if (!eth->usxgmii_pcs[i]) ++ continue; ++ ++ /* Make sure all PCS ops are supported by wrapped PCS */ ++ if (!eth->sgmii_pcs[i]->ops->pcs_get_state || ++ !eth->sgmii_pcs[i]->ops->pcs_config || ++ !eth->sgmii_pcs[i]->ops->pcs_an_restart || ++ !eth->sgmii_pcs[i]->ops->pcs_link_up || ++ !eth->sgmii_pcs[i]->ops->pcs_disable) ++ return -EOPNOTSUPP; ++ ++ wp = devm_kzalloc(eth->dev, sizeof(*wp), GFP_KERNEL); ++ if (!wp) ++ return -ENOMEM; ++ ++ wp->wrapped_pcs = eth->sgmii_pcs[i]; ++ wp->id = i; ++ wp->pcs.poll = true; ++ wp->pcs.ops = &mtk_sgmii_wrapped_pcs_ops; ++ wp->eth = eth; ++ ++ eth->usxgmii_pcs[i]->wrapped_sgmii_pcs = &wp->pcs; ++ } ++ ++ return 0; ++} ++ ++struct phylink_pcs *mtk_sgmii_wrapper_select_pcs(struct mtk_eth *eth, int mac_id) ++{ ++ u32 xgmii_id = mtk_mac2xgmii_id(eth, mac_id); ++ ++ if (!eth->usxgmii_pcs[xgmii_id]) ++ return NULL; ++ ++ return eth->usxgmii_pcs[xgmii_id]->wrapped_sgmii_pcs; ++} ++ ++static int mtk_usxgmii_pcs_config(struct phylink_pcs *pcs, unsigned int mode, ++ phy_interface_t interface, ++ const unsigned long *advertising, ++ bool permit_pause_to_mac) ++{ ++ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs); ++ struct mtk_eth *eth = mpcs->eth; ++ struct regmap *pextp = eth->regmap_pextp[mpcs->id]; ++ unsigned int an_ctrl = 0, link_timer = 0, xfi_mode = 0, adapt_mode = 0; ++ bool mode_changed = false; ++ ++ if (!pextp) ++ return -ENODEV; ++ ++ if (interface == PHY_INTERFACE_MODE_USXGMII) { ++ an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF) | USXGMII_AN_ENABLE; ++ link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) | ++ FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) | ++ FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B); ++ xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_10G) | ++ FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_10G); ++ } else if (interface == PHY_INTERFACE_MODE_10GBASER) { ++ an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF); ++ link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) | ++ FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) | ++ FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B); ++ xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_10G) | ++ FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_10G); ++ adapt_mode = USXGMII_RATE_UPDATE_MODE; ++ } else if (interface == PHY_INTERFACE_MODE_5GBASER) { ++ an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0xFF); ++ link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x3D) | ++ FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x3D) | ++ FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x3D); ++ xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_5G) | ++ FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_5G); ++ adapt_mode = USXGMII_RATE_UPDATE_MODE; ++ } else { ++ return -EINVAL; ++ } ++ ++ adapt_mode |= FIELD_PREP(USXGMII_RATE_ADAPT_MODE, USXGMII_RATE_ADAPT_MODE_X1); ++ ++ if (mpcs->interface != interface) { ++ mpcs->interface = interface; ++ mode_changed = true; ++ } ++ ++ mtk_xfi_pll_enable(eth); ++ mtk_usxgmii_reset(eth, mpcs->id); ++ ++ /* Setup USXGMII AN ctrl */ ++ regmap_update_bits(mpcs->regmap, RG_PCS_AN_CTRL0, ++ USXGMII_AN_SYNC_CNT | USXGMII_AN_ENABLE, ++ an_ctrl); ++ ++ regmap_update_bits(mpcs->regmap, RG_PCS_AN_CTRL2, ++ USXGMII_LINK_TIMER_IDLE_DETECT | ++ USXGMII_LINK_TIMER_COMP_ACK_DETECT | ++ USXGMII_LINK_TIMER_AN_RESTART, ++ link_timer); ++ ++ mpcs->mode = mode; ++ ++ /* Gated MAC CK */ ++ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, ++ USXGMII_MAC_CK_GATED, USXGMII_MAC_CK_GATED); ++ ++ /* Enable interface force mode */ ++ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, ++ USXGMII_IF_FORCE_EN, USXGMII_IF_FORCE_EN); ++ ++ /* Setup USXGMII adapt mode */ ++ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, ++ USXGMII_RATE_UPDATE_MODE | USXGMII_RATE_ADAPT_MODE, ++ adapt_mode); ++ ++ /* Setup USXGMII speed */ ++ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, ++ USXGMII_XFI_RX_MODE | USXGMII_XFI_TX_MODE, ++ xfi_mode); ++ ++ usleep_range(1, 10); ++ ++ /* Un-gated MAC CK */ ++ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, ++ USXGMII_MAC_CK_GATED, 0); ++ ++ usleep_range(1, 10); ++ ++ /* Disable interface force mode for the AN mode */ ++ if (an_ctrl & USXGMII_AN_ENABLE) ++ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, ++ USXGMII_IF_FORCE_EN, 0); ++ ++ /* Setup USXGMIISYS with the determined property */ ++ mtk_usxgmii_setup_phya(pextp, interface, mpcs->id); ++ ++ return mode_changed; ++} ++ ++static void mtk_usxgmii_pcs_get_state(struct phylink_pcs *pcs, ++ struct phylink_link_state *state) ++{ ++ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs); ++ struct mtk_eth *eth = mpcs->eth; ++ struct mtk_mac *mac = eth->mac[mtk_xgmii2mac_id(eth, mpcs->id)]; ++ u32 val = 0; ++ ++ regmap_read(mpcs->regmap, RG_PCS_AN_CTRL0, &val); ++ if (FIELD_GET(USXGMII_AN_ENABLE, val)) { ++ /* Refresh LPA by inverting LPA_LATCH */ ++ regmap_read(mpcs->regmap, RG_PCS_AN_STS0, &val); ++ regmap_update_bits(mpcs->regmap, RG_PCS_AN_STS0, ++ USXGMII_LPA_LATCH, ++ !(val & USXGMII_LPA_LATCH)); ++ ++ regmap_read(mpcs->regmap, RG_PCS_AN_STS0, &val); ++ ++ phylink_decode_usxgmii_word(state, FIELD_GET(USXGMII_PCS_AN_WORD, ++ val)); ++ ++ state->interface = mpcs->interface; ++ } else { ++ val = mtk_r32(mac->hw, MTK_XGMAC_STS(mac->id)); ++ ++ if (mac->id == MTK_GMAC2_ID) ++ val >>= 16; ++ ++ switch (FIELD_GET(MTK_USXGMII_PCS_MODE, val)) { ++ case 0: ++ state->speed = SPEED_10000; ++ break; ++ case 1: ++ state->speed = SPEED_5000; ++ break; ++ case 2: ++ state->speed = SPEED_2500; ++ break; ++ case 3: ++ state->speed = SPEED_1000; ++ break; ++ } ++ ++ state->interface = mpcs->interface; ++ state->link = FIELD_GET(MTK_USXGMII_PCS_LINK, val); ++ state->duplex = DUPLEX_FULL; ++ } ++ ++ /* Continuously repeat re-configuration sequence until link comes up */ ++ if (state->link == 0) ++ mtk_usxgmii_pcs_config(pcs, mpcs->mode, ++ state->interface, NULL, false); ++} ++ ++static void mtk_usxgmii_pcs_restart_an(struct phylink_pcs *pcs) ++{ ++ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs); ++ unsigned int val = 0; ++ ++ if (!mpcs->regmap) ++ return; ++ ++ regmap_read(mpcs->regmap, RG_PCS_AN_CTRL0, &val); ++ val |= USXGMII_AN_RESTART; ++ regmap_write(mpcs->regmap, RG_PCS_AN_CTRL0, val); ++} ++ ++static void mtk_usxgmii_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode, ++ phy_interface_t interface, ++ int speed, int duplex) ++{ ++ /* Reconfiguring USXGMII to ensure the quality of the RX signal ++ * after the line side link up. ++ */ ++ mtk_usxgmii_pcs_config(pcs, mode, ++ interface, NULL, false); ++} ++ ++static const struct phylink_pcs_ops mtk_usxgmii_pcs_ops = { ++ .pcs_config = mtk_usxgmii_pcs_config, ++ .pcs_get_state = mtk_usxgmii_pcs_get_state, ++ .pcs_an_restart = mtk_usxgmii_pcs_restart_an, ++ .pcs_link_up = mtk_usxgmii_pcs_link_up, ++}; ++ ++int mtk_usxgmii_init(struct mtk_eth *eth) ++{ ++ struct device_node *r = eth->dev->of_node; ++ struct device *dev = eth->dev; ++ struct device_node *np; ++ int i, ret; ++ ++ for (i = 0; i < MTK_MAX_DEVS; i++) { ++ np = of_parse_phandle(r, "mediatek,usxgmiisys", i); ++ if (!np) ++ break; ++ ++ eth->usxgmii_pcs[i] = devm_kzalloc(dev, sizeof(*eth->usxgmii_pcs[i]), GFP_KERNEL); ++ if (!eth->usxgmii_pcs[i]) ++ return -ENOMEM; ++ ++ eth->usxgmii_pcs[i]->id = i; ++ eth->usxgmii_pcs[i]->eth = eth; ++ eth->usxgmii_pcs[i]->regmap = syscon_node_to_regmap(np); ++ if (IS_ERR(eth->usxgmii_pcs[i]->regmap)) ++ return PTR_ERR(eth->usxgmii_pcs[i]->regmap); ++ ++ eth->usxgmii_pcs[i]->pcs.ops = &mtk_usxgmii_pcs_ops; ++ eth->usxgmii_pcs[i]->pcs.poll = true; ++ eth->usxgmii_pcs[i]->interface = PHY_INTERFACE_MODE_NA; ++ eth->usxgmii_pcs[i]->mode = -1; ++ ++ of_node_put(np); ++ } ++ ++ ret = mtk_xfi_pextp_init(eth); ++ if (ret) ++ return ret; ++ ++ ret = mtk_xfi_pll_init(eth); ++ if (ret) ++ return ret; ++ ++ ret = mtk_toprgu_init(eth); ++ if (ret) ++ return ret; ++ ++ return mtk_sgmii_wrapper_init(eth); ++} ++ ++struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int mac_id) ++{ ++ u32 xgmii_id = mtk_mac2xgmii_id(eth, mac_id); ++ ++ if (!eth->usxgmii_pcs[xgmii_id]->regmap) ++ return NULL; ++ ++ return ð->usxgmii_pcs[xgmii_id]->pcs; ++} diff --git a/target/linux/generic/pending-6.1/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch b/target/linux/generic/pending-6.1/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch index 269c639d6c3..da7389689e5 100644 --- a/target/linux/generic/pending-6.1/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch +++ b/target/linux/generic/pending-6.1/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch @@ -10,7 +10,7 @@ Signed-off-by: Felix Fietkau --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -3048,8 +3048,8 @@ static irqreturn_t mtk_handle_irq_rx(int +@@ -3151,8 +3151,8 @@ static irqreturn_t mtk_handle_irq_rx(int eth->rx_events++; if (likely(napi_schedule_prep(ð->rx_napi))) { @@ -20,7 +20,7 @@ Signed-off-by: Felix Fietkau } return IRQ_HANDLED; -@@ -3061,8 +3061,8 @@ static irqreturn_t mtk_handle_irq_tx(int +@@ -3164,8 +3164,8 @@ static irqreturn_t mtk_handle_irq_tx(int eth->tx_events++; if (likely(napi_schedule_prep(ð->tx_napi))) { @@ -30,7 +30,7 @@ Signed-off-by: Felix Fietkau } return IRQ_HANDLED; -@@ -4720,6 +4720,8 @@ static int mtk_probe(struct platform_dev +@@ -4937,6 +4937,8 @@ static int mtk_probe(struct platform_dev * for NAPI to work */ init_dummy_netdev(ð->dummy_dev); diff --git a/target/linux/generic/pending-6.1/732-00-net-ethernet-mtk_eth_soc-compile-out-netsys-v2-code-.patch b/target/linux/generic/pending-6.1/732-00-net-ethernet-mtk_eth_soc-compile-out-netsys-v2-code-.patch new file mode 100644 index 00000000000..decf647bce9 --- /dev/null +++ b/target/linux/generic/pending-6.1/732-00-net-ethernet-mtk_eth_soc-compile-out-netsys-v2-code-.patch @@ -0,0 +1,44 @@ +From: Felix Fietkau +Date: Thu, 27 Oct 2022 23:39:52 +0200 +Subject: [PATCH] net: ethernet: mtk_eth_soc: compile out netsys v2 code + on mt7621 + +Avoid some branches in the hot path on low-end devices with limited CPU power, +and reduce code size + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -1326,6 +1326,22 @@ struct mtk_mac { + /* the struct describing the SoC. these are declared in the soc_xyz.c files */ + extern const struct of_device_id of_mtk_match[]; + ++#ifdef CONFIG_SOC_MT7621 ++static inline bool mtk_is_netsys_v1(struct mtk_eth *eth) ++{ ++ return true; ++} ++ ++static inline bool mtk_is_netsys_v2_or_greater(struct mtk_eth *eth) ++{ ++ return false; ++} ++ ++static inline bool mtk_is_netsys_v3_or_greater(struct mtk_eth *eth) ++{ ++ return false; ++} ++#else + static inline bool mtk_is_netsys_v1(struct mtk_eth *eth) + { + return eth->soc->version == 1; +@@ -1340,6 +1356,7 @@ static inline bool mtk_is_netsys_v3_or_g + { + return eth->soc->version > 2; + } ++#endif + + static inline struct mtk_foe_entry * + mtk_foe_get_entry(struct mtk_ppe *ppe, u16 hash) diff --git a/target/linux/generic/pending-6.1/732-01-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch b/target/linux/generic/pending-6.1/732-01-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch index c0a5a93a456..a1cc109050e 100644 --- a/target/linux/generic/pending-6.1/732-01-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch +++ b/target/linux/generic/pending-6.1/732-01-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch @@ -16,7 +16,7 @@ Signed-off-by: Felix Fietkau --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -1469,12 +1469,28 @@ static void mtk_wake_queue(struct mtk_et +@@ -1562,12 +1562,28 @@ static void mtk_wake_queue(struct mtk_et } } @@ -45,11 +45,11 @@ Signed-off-by: Felix Fietkau bool gso = false; int tx_num; -@@ -1496,6 +1512,18 @@ static netdev_tx_t mtk_start_xmit(struct +@@ -1589,6 +1605,18 @@ static netdev_tx_t mtk_start_xmit(struct return NETDEV_TX_BUSY; } -+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) && ++ if (mtk_is_netsys_v1(eth) && + skb_is_gso(skb) && mtk_skb_has_small_frag(skb)) { + segs = skb_gso_segment(skb, dev->features & ~NETIF_F_ALL_TSO); + if (IS_ERR(segs)) @@ -64,14 +64,14 @@ Signed-off-by: Felix Fietkau /* TSO: fill MSS info in tcp checksum field */ if (skb_is_gso(skb)) { if (skb_cow_head(skb, 0)) { -@@ -1511,8 +1539,14 @@ static netdev_tx_t mtk_start_xmit(struct +@@ -1604,8 +1632,14 @@ static netdev_tx_t mtk_start_xmit(struct } } - if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) - goto drop; + skb_list_walk_safe(skb, skb, next) { -+ if ((!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) && ++ if ((mtk_is_netsys_v1(eth) && + mtk_skb_has_small_frag(skb) && skb_linearize(skb)) || + mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) { + stats->tx_dropped++; @@ -83,7 +83,7 @@ Signed-off-by: Felix Fietkau netif_tx_stop_all_queues(dev); --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -258,7 +258,7 @@ +@@ -268,7 +268,7 @@ #define MTK_CHK_DDONE_EN BIT(28) #define MTK_DMAD_WR_WDONE BIT(26) #define MTK_WCOMP_EN BIT(24) diff --git a/target/linux/generic/pending-6.1/732-02-net-ethernet-mtk_eth_soc-set-NETIF_F_ALL_TSO.patch b/target/linux/generic/pending-6.1/732-02-net-ethernet-mtk_eth_soc-set-NETIF_F_ALL_TSO.patch index 3c6359ee419..11a81dd0bfd 100644 --- a/target/linux/generic/pending-6.1/732-02-net-ethernet-mtk_eth_soc-set-NETIF_F_ALL_TSO.patch +++ b/target/linux/generic/pending-6.1/732-02-net-ethernet-mtk_eth_soc-set-NETIF_F_ALL_TSO.patch @@ -9,7 +9,7 @@ Signed-off-by: Felix Fietkau --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -48,8 +48,7 @@ +@@ -47,8 +47,7 @@ #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ NETIF_F_RXCSUM | \ NETIF_F_HW_VLAN_CTAG_TX | \ diff --git a/target/linux/generic/pending-6.1/732-03-net-ethernet-mtk_eth_soc-fix-remaining-throughput-re.patch b/target/linux/generic/pending-6.1/732-03-net-ethernet-mtk_eth_soc-fix-remaining-throughput-re.patch index 77973180f63..6790ebd94cf 100644 --- a/target/linux/generic/pending-6.1/732-03-net-ethernet-mtk_eth_soc-fix-remaining-throughput-re.patch +++ b/target/linux/generic/pending-6.1/732-03-net-ethernet-mtk_eth_soc-fix-remaining-throughput-re.patch @@ -22,7 +22,7 @@ Signed-off-by: Felix Fietkau --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -710,6 +710,7 @@ static void mtk_mac_link_up(struct phyli +@@ -766,6 +766,7 @@ static void mtk_mac_link_up(struct phyli MAC_MCR_FORCE_RX_FC); /* Configure speed */ @@ -30,7 +30,7 @@ Signed-off-by: Felix Fietkau switch (speed) { case SPEED_2500: case SPEED_1000: -@@ -3201,6 +3202,9 @@ found: +@@ -3344,6 +3345,9 @@ found: if (dp->index >= MTK_QDMA_NUM_QUEUES) return NOTIFY_DONE; diff --git a/target/linux/generic/pending-6.1/734-net-ethernet-mtk_eth_soc-ppe-fix-L2-offloading-with-.patch b/target/linux/generic/pending-6.1/734-net-ethernet-mtk_eth_soc-ppe-fix-L2-offloading-with-.patch index dc2163959d1..72d57434026 100644 --- a/target/linux/generic/pending-6.1/734-net-ethernet-mtk_eth_soc-ppe-fix-L2-offloading-with-.patch +++ b/target/linux/generic/pending-6.1/734-net-ethernet-mtk_eth_soc-ppe-fix-L2-offloading-with-.patch @@ -20,7 +20,7 @@ Signed-off-by: Felix Fietkau #include #include "mtk_eth_soc.h" #include "mtk_ppe.h" -@@ -752,7 +753,9 @@ void __mtk_ppe_check_skb(struct mtk_ppe +@@ -775,7 +776,9 @@ void __mtk_ppe_check_skb(struct mtk_ppe skb->dev->dsa_ptr->tag_ops->proto != DSA_TAG_PROTO_MTK) goto out; diff --git a/target/linux/generic/pending-6.1/736-01-net-ethernet-mtk_eth_soc-add-code-for-offloading-flo.patch b/target/linux/generic/pending-6.1/736-01-net-ethernet-mtk_eth_soc-add-code-for-offloading-flo.patch index c5654a60619..c29c63bb1da 100644 --- a/target/linux/generic/pending-6.1/736-01-net-ethernet-mtk_eth_soc-add-code-for-offloading-flo.patch +++ b/target/linux/generic/pending-6.1/736-01-net-ethernet-mtk_eth_soc-add-code-for-offloading-flo.patch @@ -11,10 +11,15 @@ PPE device. Signed-off-by: Felix Fietkau --- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 3 + + .../net/ethernet/mediatek/mtk_ppe_offload.c | 37 ++++--- + drivers/net/ethernet/mediatek/mtk_wed.c | 101 ++++++++++++++++++ + include/linux/soc/mediatek/mtk_wed.h | 6 ++ + 4 files changed, 133 insertions(+), 14 deletions(-) --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -1280,6 +1280,9 @@ int mtk_gmac_rgmii_path_setup(struct mtk +@@ -1451,6 +1451,9 @@ int mtk_gmac_rgmii_path_setup(struct mtk int mtk_eth_offload_init(struct mtk_eth *eth); int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, void *type_data); @@ -120,7 +125,7 @@ Signed-off-by: Felix Fietkau static void wed_m32(struct mtk_wed_device *dev, u32 reg, u32 mask, u32 val) { -@@ -1745,6 +1752,99 @@ out: +@@ -1753,6 +1760,99 @@ out: mutex_unlock(&hw_lock); } @@ -220,7 +225,7 @@ Signed-off-by: Felix Fietkau void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth, void __iomem *wdma, phys_addr_t wdma_phy, int index) -@@ -1764,6 +1864,7 @@ void mtk_wed_add_hw(struct device_node * +@@ -1772,6 +1872,7 @@ void mtk_wed_add_hw(struct device_node * .irq_set_mask = mtk_wed_irq_set_mask, .detach = mtk_wed_detach, .ppe_check = mtk_wed_ppe_check, diff --git a/target/linux/generic/pending-6.1/736-02-net-ethernet-mediatek-mtk_ppe-prefer-newly-added-l2-.patch b/target/linux/generic/pending-6.1/736-02-net-ethernet-mediatek-mtk_ppe-prefer-newly-added-l2-.patch index 08036e0b17d..74cb562a510 100644 --- a/target/linux/generic/pending-6.1/736-02-net-ethernet-mediatek-mtk_ppe-prefer-newly-added-l2-.patch +++ b/target/linux/generic/pending-6.1/736-02-net-ethernet-mediatek-mtk_ppe-prefer-newly-added-l2-.patch @@ -12,7 +12,7 @@ Signed-off-by: Felix Fietkau --- a/drivers/net/ethernet/mediatek/mtk_ppe.c +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c -@@ -634,10 +634,20 @@ void mtk_foe_entry_clear(struct mtk_ppe +@@ -657,10 +657,20 @@ void mtk_foe_entry_clear(struct mtk_ppe static int mtk_foe_entry_commit_l2(struct mtk_ppe *ppe, struct mtk_flow_entry *entry) { diff --git a/target/linux/generic/pending-6.1/736-03-net-ethernet-mtk_eth_soc-improve-keeping-track-of-of.patch b/target/linux/generic/pending-6.1/736-03-net-ethernet-mtk_eth_soc-improve-keeping-track-of-of.patch index ec04fb35425..ecdb345d699 100644 --- a/target/linux/generic/pending-6.1/736-03-net-ethernet-mtk_eth_soc-improve-keeping-track-of-of.patch +++ b/target/linux/generic/pending-6.1/736-03-net-ethernet-mtk_eth_soc-improve-keeping-track-of-of.patch @@ -9,10 +9,13 @@ flow accounting support. Signed-off-by: Felix Fietkau --- + drivers/net/ethernet/mediatek/mtk_ppe.c | 162 ++++++++++++------------ + drivers/net/ethernet/mediatek/mtk_ppe.h | 15 +-- + 2 files changed, 86 insertions(+), 91 deletions(-) --- a/drivers/net/ethernet/mediatek/mtk_ppe.c +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c -@@ -460,42 +460,43 @@ int mtk_foe_entry_set_queue(struct mtk_e +@@ -477,42 +477,43 @@ int mtk_foe_entry_set_queue(struct mtk_e return 0; } @@ -72,7 +75,7 @@ Signed-off-by: Felix Fietkau struct mtk_foe_entry *hwe = mtk_foe_get_entry(ppe, entry->hash); hwe->ib1 &= ~MTK_FOE_IB1_STATE; -@@ -515,7 +516,8 @@ __mtk_foe_entry_clear(struct mtk_ppe *pp +@@ -532,7 +533,8 @@ __mtk_foe_entry_clear(struct mtk_ppe *pp if (entry->type != MTK_FLOW_TYPE_L2_SUBFLOW) return; @@ -82,7 +85,7 @@ Signed-off-by: Felix Fietkau kfree(entry); } -@@ -531,66 +533,55 @@ static int __mtk_foe_entry_idle_time(str +@@ -548,66 +550,55 @@ static int __mtk_foe_entry_idle_time(str return now - timestamp; } @@ -178,7 +181,7 @@ Signed-off-by: Felix Fietkau } static void -@@ -627,7 +618,8 @@ __mtk_foe_entry_commit(struct mtk_ppe *p +@@ -650,7 +641,8 @@ __mtk_foe_entry_commit(struct mtk_ppe *p void mtk_foe_entry_clear(struct mtk_ppe *ppe, struct mtk_flow_entry *entry) { spin_lock_bh(&ppe_lock); @@ -188,7 +191,7 @@ Signed-off-by: Felix Fietkau spin_unlock_bh(&ppe_lock); } -@@ -674,8 +666,8 @@ mtk_foe_entry_commit_subflow(struct mtk_ +@@ -697,8 +689,8 @@ mtk_foe_entry_commit_subflow(struct mtk_ { const struct mtk_soc_data *soc = ppe->eth->soc; struct mtk_flow_entry *flow_info; @@ -198,7 +201,7 @@ Signed-off-by: Felix Fietkau u32 ib1_mask = mtk_get_ib1_pkt_type_mask(ppe->eth) | MTK_FOE_IB1_UDP; int type; -@@ -683,30 +675,30 @@ mtk_foe_entry_commit_subflow(struct mtk_ +@@ -706,30 +698,30 @@ mtk_foe_entry_commit_subflow(struct mtk_ if (!flow_info) return; @@ -239,7 +242,7 @@ Signed-off-by: Felix Fietkau } void __mtk_ppe_check_skb(struct mtk_ppe *ppe, struct sk_buff *skb, u16 hash) -@@ -716,9 +708,11 @@ void __mtk_ppe_check_skb(struct mtk_ppe +@@ -739,9 +731,11 @@ void __mtk_ppe_check_skb(struct mtk_ppe struct mtk_foe_entry *hwe = mtk_foe_get_entry(ppe, hash); struct mtk_flow_entry *entry; struct mtk_foe_bridge key = {}; @@ -251,7 +254,7 @@ Signed-off-by: Felix Fietkau u8 *tag; spin_lock_bh(&ppe_lock); -@@ -726,20 +720,14 @@ void __mtk_ppe_check_skb(struct mtk_ppe +@@ -749,20 +743,14 @@ void __mtk_ppe_check_skb(struct mtk_ppe if (FIELD_GET(MTK_FOE_IB1_STATE, hwe->ib1) == MTK_FOE_STATE_BIND) goto out; @@ -278,7 +281,7 @@ Signed-off-by: Felix Fietkau continue; } -@@ -790,9 +778,17 @@ out: +@@ -813,9 +801,17 @@ out: int mtk_foe_entry_idle_time(struct mtk_ppe *ppe, struct mtk_flow_entry *entry) { @@ -300,7 +303,7 @@ Signed-off-by: Felix Fietkau int mtk_ppe_prepare_reset(struct mtk_ppe *ppe) --- a/drivers/net/ethernet/mediatek/mtk_ppe.h +++ b/drivers/net/ethernet/mediatek/mtk_ppe.h -@@ -265,7 +265,12 @@ enum { +@@ -286,7 +286,12 @@ enum { struct mtk_flow_entry { union { @@ -314,7 +317,7 @@ Signed-off-by: Felix Fietkau struct { struct rhash_head l2_node; struct hlist_head l2_flows; -@@ -275,13 +280,7 @@ struct mtk_flow_entry { +@@ -296,13 +301,7 @@ struct mtk_flow_entry { s8 wed_index; u8 ppe_index; u16 hash; diff --git a/target/linux/generic/pending-6.1/736-04-net-ethernet-mediatek-fix-ppe-flow-accounting-for-L2.patch b/target/linux/generic/pending-6.1/736-04-net-ethernet-mediatek-fix-ppe-flow-accounting-for-L2.patch index 79386d6cf90..e323baeb184 100644 --- a/target/linux/generic/pending-6.1/736-04-net-ethernet-mediatek-fix-ppe-flow-accounting-for-L2.patch +++ b/target/linux/generic/pending-6.1/736-04-net-ethernet-mediatek-fix-ppe-flow-accounting-for-L2.patch @@ -27,7 +27,7 @@ Signed-off-by: Felix Fietkau if (ret) dev_err(ppe->dev, "MIB table busy"); -@@ -90,18 +90,32 @@ static int mtk_ppe_mib_wait_busy(struct +@@ -90,17 +90,31 @@ static int mtk_ppe_mib_wait_busy(struct return ret; } @@ -43,7 +43,6 @@ Signed-off-by: Felix Fietkau + +struct mtk_foe_accounting *mtk_ppe_mib_entry_read(struct mtk_ppe *ppe, u16 index) { - u32 byte_cnt_low, byte_cnt_high, pkt_cnt_low, pkt_cnt_high; u32 val, cnt_r0, cnt_r1, cnt_r2; + struct mtk_foe_accounting *acct; int ret; @@ -62,22 +61,32 @@ Signed-off-by: Felix Fietkau cnt_r0 = readl(ppe->base + MTK_PPE_MIB_SER_R0); cnt_r1 = readl(ppe->base + MTK_PPE_MIB_SER_R1); -@@ -111,10 +125,11 @@ static int mtk_mib_entry_read(struct mtk - byte_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH, cnt_r1); - pkt_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R1_PKT_CNT_LOW, cnt_r1); - pkt_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH, cnt_r2); -- *bytes = ((u64)byte_cnt_high << 32) | byte_cnt_low; -- *packets = (pkt_cnt_high << 16) | pkt_cnt_low; +@@ -109,19 +123,19 @@ static int mtk_mib_entry_read(struct mtk + if (mtk_is_netsys_v3_or_greater(ppe->eth)) { + /* 64 bit for each counter */ + u32 cnt_r3 = readl(ppe->base + MTK_PPE_MIB_SER_R3); +- *bytes = ((u64)cnt_r1 << 32) | cnt_r0; +- *packets = ((u64)cnt_r3 << 32) | cnt_r2; ++ acct->bytes += ((u64)cnt_r1 << 32) | cnt_r0; ++ acct->packets += ((u64)cnt_r3 << 32) | cnt_r2; + } else { + /* 48 bit byte counter, 40 bit packet counter */ + u32 byte_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R0_BYTE_CNT_LOW, cnt_r0); + u32 byte_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH, cnt_r1); + u32 pkt_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R1_PKT_CNT_LOW, cnt_r1); + u32 pkt_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH, cnt_r2); +- *bytes = ((u64)byte_cnt_high << 32) | byte_cnt_low; +- *packets = (pkt_cnt_high << 16) | pkt_cnt_low; ++ acct->bytes += ((u64)byte_cnt_high << 32) | byte_cnt_low; ++ acct->packets += (pkt_cnt_high << 16) | pkt_cnt_low; + } - return 0; -+ acct->bytes += ((u64)byte_cnt_high << 32) | byte_cnt_low; -+ acct->packets += (pkt_cnt_high << 16) | pkt_cnt_low; -+ + return acct; } static void mtk_ppe_cache_clear(struct mtk_ppe *ppe) -@@ -503,13 +518,6 @@ __mtk_foe_entry_clear(struct mtk_ppe *pp +@@ -520,13 +534,6 @@ __mtk_foe_entry_clear(struct mtk_ppe *pp hwe->ib1 |= FIELD_PREP(MTK_FOE_IB1_STATE, MTK_FOE_STATE_INVALID); dma_wmb(); mtk_ppe_cache_clear(ppe); @@ -91,7 +100,7 @@ Signed-off-by: Felix Fietkau } entry->hash = 0xffff; -@@ -534,11 +542,14 @@ static int __mtk_foe_entry_idle_time(str +@@ -551,11 +558,14 @@ static int __mtk_foe_entry_idle_time(str } static bool @@ -107,7 +116,7 @@ Signed-off-by: Felix Fietkau int len; if (hash == 0xffff) -@@ -549,18 +560,35 @@ mtk_flow_entry_update(struct mtk_ppe *pp +@@ -566,18 +576,35 @@ mtk_flow_entry_update(struct mtk_ppe *pp memcpy(&foe, hwe, len); if (!mtk_flow_entry_match(ppe->eth, entry, &foe, len) || @@ -146,7 +155,7 @@ Signed-off-by: Felix Fietkau struct mtk_flow_entry *cur; struct hlist_node *tmp; int idle; -@@ -569,7 +597,9 @@ mtk_flow_entry_update_l2(struct mtk_ppe +@@ -586,7 +613,9 @@ mtk_flow_entry_update_l2(struct mtk_ppe hlist_for_each_entry_safe(cur, tmp, &entry->l2_flows, l2_list) { int cur_idle; @@ -157,7 +166,7 @@ Signed-off-by: Felix Fietkau __mtk_foe_entry_clear(ppe, entry, false); continue; } -@@ -584,10 +614,29 @@ mtk_flow_entry_update_l2(struct mtk_ppe +@@ -601,10 +630,29 @@ mtk_flow_entry_update_l2(struct mtk_ppe } } @@ -187,7 +196,7 @@ Signed-off-by: Felix Fietkau struct mtk_eth *eth = ppe->eth; u16 timestamp = mtk_eth_timestamp(eth); struct mtk_foe_entry *hwe; -@@ -612,6 +661,12 @@ __mtk_foe_entry_commit(struct mtk_ppe *p +@@ -635,6 +683,12 @@ __mtk_foe_entry_commit(struct mtk_ppe *p dma_wmb(); @@ -200,7 +209,7 @@ Signed-off-by: Felix Fietkau mtk_ppe_cache_clear(ppe); } -@@ -776,21 +831,6 @@ out: +@@ -799,21 +853,6 @@ out: spin_unlock_bh(&ppe_lock); } @@ -222,7 +231,7 @@ Signed-off-by: Felix Fietkau int mtk_ppe_prepare_reset(struct mtk_ppe *ppe) { if (!ppe) -@@ -818,32 +858,6 @@ int mtk_ppe_prepare_reset(struct mtk_ppe +@@ -841,32 +880,6 @@ int mtk_ppe_prepare_reset(struct mtk_ppe return mtk_ppe_wait_busy(ppe); } @@ -257,7 +266,7 @@ Signed-off-by: Felix Fietkau bool accounting = eth->soc->has_accounting; --- a/drivers/net/ethernet/mediatek/mtk_ppe.h +++ b/drivers/net/ethernet/mediatek/mtk_ppe.h -@@ -283,6 +283,8 @@ struct mtk_flow_entry { +@@ -304,6 +304,8 @@ struct mtk_flow_entry { struct mtk_foe_entry data; struct rhash_head node; unsigned long cookie; @@ -266,7 +275,7 @@ Signed-off-by: Felix Fietkau }; struct mtk_mib_entry { -@@ -326,6 +328,7 @@ void mtk_ppe_deinit(struct mtk_eth *eth) +@@ -348,6 +350,7 @@ void mtk_ppe_deinit(struct mtk_eth *eth) void mtk_ppe_start(struct mtk_ppe *ppe); int mtk_ppe_stop(struct mtk_ppe *ppe); int mtk_ppe_prepare_reset(struct mtk_ppe *ppe); @@ -274,7 +283,7 @@ Signed-off-by: Felix Fietkau void __mtk_ppe_check_skb(struct mtk_ppe *ppe, struct sk_buff *skb, u16 hash); -@@ -374,9 +377,8 @@ int mtk_foe_entry_set_queue(struct mtk_e +@@ -396,9 +399,8 @@ int mtk_foe_entry_set_queue(struct mtk_e unsigned int queue); int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_flow_entry *entry); void mtk_foe_entry_clear(struct mtk_ppe *ppe, struct mtk_flow_entry *entry); @@ -295,7 +304,7 @@ Signed-off-by: Felix Fietkau - acct = mtk_foe_entry_get_mib(ppe, i, NULL); + acct = mtk_ppe_mib_entry_read(ppe, i); - type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1); + type = mtk_get_ib1_pkt_type(ppe->eth, entry->ib1); seq_printf(m, "%05x %s %7s", i, --- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c +++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c diff --git a/target/linux/generic/pending-6.1/737-01-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V1-capabilit.patch b/target/linux/generic/pending-6.1/737-01-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V1-capabilit.patch deleted file mode 100644 index bf1bc78b23a..00000000000 --- a/target/linux/generic/pending-6.1/737-01-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V1-capabilit.patch +++ /dev/null @@ -1,223 +0,0 @@ -From 663fa1b7e0cb2c929008482014a70c6625caad75 Mon Sep 17 00:00:00 2001 -From: Lorenzo Bianconi -Date: Tue, 7 Mar 2023 15:55:13 +0000 -Subject: [PATCH 1/7] net: ethernet: mtk_eth_soc: add MTK_NETSYS_V1 capability - bit - -Introduce MTK_NETSYS_V1 bit in the device capabilities for -MT7621/MT7622/MT7623/MT7628/MT7629 SoCs. -Use !MTK_NETSYS_V1 instead of MTK_NETSYS_V2 in the driver codebase. -This is a preliminary patch to introduce support for MT7988 SoC. - -Signed-off-by: Lorenzo Bianconi -Signed-off-by: Daniel Golle ---- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 30 +++++++------- - drivers/net/ethernet/mediatek/mtk_eth_soc.h | 45 ++++++++++++--------- - 2 files changed, 41 insertions(+), 34 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -640,7 +640,7 @@ static void mtk_set_queue_speed(struct m - FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | - FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | - MTK_QTX_SCH_LEAKY_BUCKET_SIZE; -- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) - val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; - - if (IS_ENABLED(CONFIG_SOC_MT7621)) { -@@ -1018,7 +1018,7 @@ static bool mtk_rx_get_desc(struct mtk_e - rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); - rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); - rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); -- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { -+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { - rxd->rxd5 = READ_ONCE(dma_rxd->rxd5); - rxd->rxd6 = READ_ONCE(dma_rxd->rxd6); - } -@@ -1076,7 +1076,7 @@ static int mtk_init_fq_dma(struct mtk_et - - txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE); - txd->txd4 = 0; -- if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) { -+ if (!MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V1)) { - txd->txd5 = 0; - txd->txd6 = 0; - txd->txd7 = 0; -@@ -1267,7 +1267,7 @@ static void mtk_tx_set_dma_desc(struct n - struct mtk_mac *mac = netdev_priv(dev); - struct mtk_eth *eth = mac->hw; - -- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) -+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) - mtk_tx_set_dma_desc_v2(dev, txd, info); - else - mtk_tx_set_dma_desc_v1(dev, txd, info); -@@ -1950,7 +1950,7 @@ static int mtk_poll_rx(struct napi_struc - break; - - /* find out which mac the packet come from. values start at 1 */ -- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) -+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) - mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1; - else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && - !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) -@@ -2046,7 +2046,7 @@ static int mtk_poll_rx(struct napi_struc - skb->dev = netdev; - bytes += skb->len; - -- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { -+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { - reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5); - hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY; - if (hash != MTK_RXD5_FOE_ENTRY) -@@ -2071,7 +2071,7 @@ static int mtk_poll_rx(struct napi_struc - /* When using VLAN untagging in combination with DSA, the - * hardware treats the MTK special tag as a VLAN and untags it. - */ -- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) && -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1) && - (trxd.rxd2 & RX_DMA_VTAG) && netdev_uses_dsa(netdev)) { - unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0); - -@@ -2382,7 +2382,7 @@ static int mtk_tx_alloc(struct mtk_eth * - txd->txd2 = next_ptr; - txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; - txd->txd4 = 0; -- if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) { -+ if (!MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V1)) { - txd->txd5 = 0; - txd->txd6 = 0; - txd->txd7 = 0; -@@ -2435,7 +2435,7 @@ static int mtk_tx_alloc(struct mtk_eth * - FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | - FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | - MTK_QTX_SCH_LEAKY_BUCKET_SIZE; -- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) - val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; - mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); - ofs += MTK_QTX_OFFSET; -@@ -2571,7 +2571,7 @@ static int mtk_rx_alloc(struct mtk_eth * - - rxd->rxd3 = 0; - rxd->rxd4 = 0; -- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { -+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { - rxd->rxd5 = 0; - rxd->rxd6 = 0; - rxd->rxd7 = 0; -@@ -3119,7 +3119,7 @@ static int mtk_start_dma(struct mtk_eth - MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO | - MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE; - -- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) -+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) - val |= MTK_MUTLI_CNT | MTK_RESV_BUF | - MTK_WCOMP_EN | MTK_DMAD_WR_WDONE | - MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN; -@@ -3529,7 +3529,7 @@ static void mtk_hw_reset(struct mtk_eth - { - u32 val; - -- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { -+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { - regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); - val = RSTCTRL_PPE0_V2; - } else { -@@ -3541,7 +3541,7 @@ static void mtk_hw_reset(struct mtk_eth - - ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val); - -- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) -+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) - regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, - 0x3ffffff); - } -@@ -3737,7 +3737,7 @@ static int mtk_hw_init(struct mtk_eth *e - else - mtk_hw_reset(eth); - -- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { -+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { - /* Set FE to PDMAv2 if necessary */ - val = mtk_r32(eth, MTK_FE_GLO_MISC); - mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC); -@@ -3774,7 +3774,7 @@ static int mtk_hw_init(struct mtk_eth *e - */ - val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); - mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); -- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { - val = mtk_r32(eth, MTK_CDMP_IG_CTRL); - mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL); - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -819,6 +819,7 @@ enum mkt_eth_capabilities { - MTK_SHARED_INT_BIT, - MTK_TRGMII_MT7621_CLK_BIT, - MTK_QDMA_BIT, -+ MTK_NETSYS_V1_BIT, - MTK_NETSYS_V2_BIT, - MTK_SOC_MT7628_BIT, - MTK_RSTCTRL_PPE1_BIT, -@@ -854,6 +855,7 @@ enum mkt_eth_capabilities { - #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT) - #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) - #define MTK_QDMA BIT(MTK_QDMA_BIT) -+#define MTK_NETSYS_V1 BIT(MTK_NETSYS_V1_BIT) - #define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) - #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) - #define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT) -@@ -916,25 +918,30 @@ enum mkt_eth_capabilities { - - #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x) & ~(MTK_CAP_MASK)) == (_x)) - --#define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ -- MTK_GMAC2_RGMII | MTK_SHARED_INT | \ -- MTK_TRGMII_MT7621_CLK | MTK_QDMA) -- --#define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \ -- MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ -- MTK_MUX_GDM1_TO_GMAC1_ESW | \ -- MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA) -- --#define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \ -- MTK_QDMA) -- --#define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628) -- --#define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ -- MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ -- MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ -- MTK_MUX_U3_GMAC2_TO_QPHY | \ -- MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) -+#define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ -+ MTK_GMAC2_RGMII | MTK_SHARED_INT | \ -+ MTK_TRGMII_MT7621_CLK | MTK_QDMA | \ -+ MTK_NETSYS_V1) -+ -+#define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | \ -+ MTK_GMAC2_RGMII | MTK_GMAC2_SGMII | \ -+ MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW |\ -+ MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | \ -+ MTK_QDMA | MTK_NETSYS_V1) -+ -+#define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ -+ MTK_GMAC2_RGMII | MTK_QDMA | \ -+ MTK_NETSYS_V1) -+ -+#define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628 | \ -+ MTK_NETSYS_V1) -+ -+#define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ -+ MTK_GMAC2_GEPHY | MTK_GDM1_ESW | \ -+ MTK_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_QDMA | \ -+ MTK_MUX_U3_GMAC2_TO_QPHY | MTK_NETSYS_V1 |\ -+ MTK_MUX_GDM1_TO_GMAC1_ESW | \ -+ MTK_MUX_GMAC12_TO_GEPHY_SGMII) - - #define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ - MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ diff --git a/target/linux/generic/pending-6.1/737-02-net-ethernet-mtk_eth_soc-move-MAX_DEVS-in-mtk_soc_da.patch b/target/linux/generic/pending-6.1/737-02-net-ethernet-mtk_eth_soc-move-MAX_DEVS-in-mtk_soc_da.patch deleted file mode 100644 index bdd62a763f2..00000000000 --- a/target/linux/generic/pending-6.1/737-02-net-ethernet-mtk_eth_soc-move-MAX_DEVS-in-mtk_soc_da.patch +++ /dev/null @@ -1,181 +0,0 @@ -From 5af2b2dc4d6ba0ff7696e79f18e5b2bf862194eb Mon Sep 17 00:00:00 2001 -From: Lorenzo Bianconi -Date: Tue, 7 Mar 2023 15:55:24 +0000 -Subject: [PATCH 2/7] net: ethernet: mtk_eth_soc: move MAX_DEVS in mtk_soc_data - -This is a preliminary patch to add MT7988 SoC support since it runs 3 -macs instead of 2. - -Signed-off-by: Lorenzo Bianconi -Signed-off-by: Daniel Golle ---- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 34 +++++++++++++++++++-- - drivers/net/ethernet/mediatek/mtk_eth_soc.h | 11 +++---- - 2 files changed, 36 insertions(+), 9 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -4026,7 +4026,10 @@ static void mtk_sgmii_destroy(struct mtk - { - int i; - -- for (i = 0; i < MTK_MAX_DEVS; i++) -+ if (!eth->sgmii_pcs) -+ return; -+ -+ for (i = 0; i < eth->soc->num_devs; i++) - mtk_pcs_lynxi_destroy(eth->sgmii_pcs[i]); - } - -@@ -4479,7 +4482,12 @@ static int mtk_sgmii_init(struct mtk_eth - u32 flags; - int i; - -- for (i = 0; i < MTK_MAX_DEVS; i++) { -+ eth->sgmii_pcs = devm_kzalloc(eth->dev, -+ sizeof(*eth->sgmii_pcs) * -+ eth->soc->num_devs, -+ GFP_KERNEL); -+ -+ for (i = 0; i < eth->soc->num_devs; i++) { - np = of_parse_phandle(eth->dev->of_node, "mediatek,sgmiisys", i); - if (!np) - break; -@@ -4524,6 +4532,18 @@ static int mtk_probe(struct platform_dev - if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) - eth->ip_align = NET_IP_ALIGN; - -+ eth->netdev = devm_kzalloc(eth->dev, -+ sizeof(*eth->netdev) * eth->soc->num_devs, -+ GFP_KERNEL); -+ if (!eth->netdev) -+ return -ENOMEM; -+ -+ eth->mac = devm_kzalloc(eth->dev, -+ sizeof(*eth->mac) * eth->soc->num_devs, -+ GFP_KERNEL); -+ if (!eth->mac) -+ return -ENOMEM; -+ - spin_lock_init(ð->page_lock); - spin_lock_init(ð->tx_irq_lock); - spin_lock_init(ð->rx_irq_lock); -@@ -4709,7 +4729,7 @@ static int mtk_probe(struct platform_dev - goto err_deinit_ppe; - } - -- for (i = 0; i < MTK_MAX_DEVS; i++) { -+ for (i = 0; i < eth->soc->num_devs; i++) { - if (!eth->netdev[i]) - continue; - -@@ -4785,6 +4805,7 @@ static const struct mtk_soc_data mt2701_ - .hw_features = MTK_HW_FEATURES, - .required_clks = MT7623_CLKS_BITMAP, - .required_pctl = true, -+ .num_devs = 2, - .txrx = { - .txd_size = sizeof(struct mtk_tx_dma), - .rxd_size = sizeof(struct mtk_rx_dma), -@@ -4803,6 +4824,7 @@ static const struct mtk_soc_data mt7621_ - .required_pctl = false, - .offload_version = 1, - .hash_offset = 2, -+ .num_devs = 2, - .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, - .txrx = { - .txd_size = sizeof(struct mtk_tx_dma), -@@ -4824,6 +4846,7 @@ static const struct mtk_soc_data mt7622_ - .offload_version = 2, - .hash_offset = 2, - .has_accounting = true, -+ .num_devs = 2, - .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, - .txrx = { - .txd_size = sizeof(struct mtk_tx_dma), -@@ -4843,6 +4866,7 @@ static const struct mtk_soc_data mt7623_ - .required_pctl = true, - .offload_version = 1, - .hash_offset = 2, -+ .num_devs = 2, - .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, - .txrx = { - .txd_size = sizeof(struct mtk_tx_dma), -@@ -4862,6 +4886,7 @@ static const struct mtk_soc_data mt7629_ - .required_clks = MT7629_CLKS_BITMAP, - .required_pctl = false, - .has_accounting = true, -+ .num_devs = 2, - .txrx = { - .txd_size = sizeof(struct mtk_tx_dma), - .rxd_size = sizeof(struct mtk_rx_dma), -@@ -4883,6 +4908,7 @@ static const struct mtk_soc_data mt7981_ - .hash_offset = 4, - .foe_entry_size = sizeof(struct mtk_foe_entry), - .has_accounting = true, -+ .num_devs = 2, - .txrx = { - .txd_size = sizeof(struct mtk_tx_dma_v2), - .rxd_size = sizeof(struct mtk_rx_dma_v2), -@@ -4902,6 +4928,7 @@ static const struct mtk_soc_data mt7986_ - .required_pctl = false, - .offload_version = 2, - .hash_offset = 4, -+ .num_devs = 2, - .foe_entry_size = sizeof(struct mtk_foe_entry), - .has_accounting = true, - .txrx = { -@@ -4920,6 +4947,7 @@ static const struct mtk_soc_data rt5350_ - .hw_features = MTK_HW_FEATURES_MT7628, - .required_clks = MT7628_CLKS_BITMAP, - .required_pctl = false, -+ .num_devs = 2, - .txrx = { - .txd_size = sizeof(struct mtk_tx_dma), - .rxd_size = sizeof(struct mtk_rx_dma), ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -1021,6 +1021,7 @@ struct mtk_reg_map { - * @required_pctl A bool value to show whether the SoC requires - * the extra setup for those pins used by GMAC. - * @hash_offset Flow table hash offset. -+ * @num_devs SoC number of macs. - * @foe_entry_size Foe table entry size. - * @has_accounting Bool indicating support for accounting of - * offloaded flows. -@@ -1039,6 +1040,7 @@ struct mtk_soc_data { - bool required_pctl; - u8 offload_version; - u8 hash_offset; -+ u8 num_devs; - u16 foe_entry_size; - netdev_features_t hw_features; - bool has_accounting; -@@ -1054,9 +1056,6 @@ struct mtk_soc_data { - - #define MTK_DMA_MONITOR_TIMEOUT msecs_to_jiffies(1000) - --/* currently no SoC has more than 2 macs */ --#define MTK_MAX_DEVS 2 -- - /* struct mtk_eth - This is the main datasructure for holding the state - * of the driver - * @dev: The device pointer -@@ -1111,14 +1110,14 @@ struct mtk_eth { - spinlock_t tx_irq_lock; - spinlock_t rx_irq_lock; - struct net_device dummy_dev; -- struct net_device *netdev[MTK_MAX_DEVS]; -- struct mtk_mac *mac[MTK_MAX_DEVS]; -+ struct net_device **netdev; -+ struct mtk_mac **mac; - int irq[3]; - u32 msg_enable; - unsigned long sysclk; - struct regmap *ethsys; - struct regmap *infra; -- struct phylink_pcs *sgmii_pcs[MTK_MAX_DEVS]; -+ struct phylink_pcs **sgmii_pcs; - struct regmap *pctl; - bool hwlro; - refcount_t dma_refcnt; diff --git a/target/linux/generic/pending-6.1/737-06-net-ethernet-mtk_eth_soc-add-support-for-MT7988-SoC.patch b/target/linux/generic/pending-6.1/737-06-net-ethernet-mtk_eth_soc-add-support-for-MT7988-SoC.patch deleted file mode 100644 index 9c4408cec88..00000000000 --- a/target/linux/generic/pending-6.1/737-06-net-ethernet-mtk_eth_soc-add-support-for-MT7988-SoC.patch +++ /dev/null @@ -1,495 +0,0 @@ -From 661bacf4363ca68939c15e20056b5f72fbd034e7 Mon Sep 17 00:00:00 2001 -From: Lorenzo Bianconi -Date: Sat, 25 Feb 2023 00:08:24 +0100 -Subject: [PATCH 6/7] net: ethernet: mtk_eth_soc: add support for MT7988 SoC - -Introduce support for ethernet chip available in MT7988 SoC to -mtk_eth_soc driver. ---- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 153 ++++++++++++++-- - drivers/net/ethernet/mediatek/mtk_eth_soc.h | 193 ++++++++++++++------ - 2 files changed, 279 insertions(+), 67 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -152,6 +152,54 @@ static const struct mtk_reg_map mt7986_r - .pse_oq_sta = 0x01a0, - }; - -+static const struct mtk_reg_map mt7988_reg_map = { -+ .tx_irq_mask = 0x461c, -+ .tx_irq_status = 0x4618, -+ .pdma = { -+ .rx_ptr = 0x6900, -+ .rx_cnt_cfg = 0x6904, -+ .pcrx_ptr = 0x6908, -+ .glo_cfg = 0x6a04, -+ .rst_idx = 0x6a08, -+ .delay_irq = 0x6a0c, -+ .irq_status = 0x6a20, -+ .irq_mask = 0x6a28, -+ .adma_rx_dbg0 = 0x6a38, -+ .int_grp = 0x6a50, -+ }, -+ .qdma = { -+ .qtx_cfg = 0x4400, -+ .qtx_sch = 0x4404, -+ .rx_ptr = 0x4500, -+ .rx_cnt_cfg = 0x4504, -+ .qcrx_ptr = 0x4508, -+ .glo_cfg = 0x4604, -+ .rst_idx = 0x4608, -+ .delay_irq = 0x460c, -+ .fc_th = 0x4610, -+ .int_grp = 0x4620, -+ .hred = 0x4644, -+ .ctx_ptr = 0x4700, -+ .dtx_ptr = 0x4704, -+ .crx_ptr = 0x4710, -+ .drx_ptr = 0x4714, -+ .fq_head = 0x4720, -+ .fq_tail = 0x4724, -+ .fq_count = 0x4728, -+ .fq_blen = 0x472c, -+ .tx_sch_rate = 0x4798, -+ }, -+ .gdm1_cnt = 0x1c00, -+ .gdma_to_ppe = 0x3333, -+ .ppe_base = 0x2200, -+ .wdma_base = { -+ [0] = 0x4800, -+ [1] = 0x4c00, -+ }, -+ .pse_iq_sta = 0x0180, -+ .pse_oq_sta = 0x01a0, -+}; -+ - /* strings used by ethtool */ - static const struct mtk_ethtool_stats { - char str[ETH_GSTRING_LEN]; -@@ -179,10 +227,54 @@ static const struct mtk_ethtool_stats { - }; - - static const char * const mtk_clks_source_name[] = { -- "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll", -- "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", -- "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb", -- "sgmii_ck", "eth2pll", "wocpu0", "wocpu1", "netsys0", "netsys1" -+ "ethif", -+ "sgmiitop", -+ "esw", -+ "gp0", -+ "gp1", -+ "gp2", -+ "gp3", -+ "xgp1", -+ "xgp2", -+ "xgp3", -+ "crypto", -+ "fe", -+ "trgpll", -+ "sgmii_tx250m", -+ "sgmii_rx250m", -+ "sgmii_cdr_ref", -+ "sgmii_cdr_fb", -+ "sgmii2_tx250m", -+ "sgmii2_rx250m", -+ "sgmii2_cdr_ref", -+ "sgmii2_cdr_fb", -+ "sgmii_ck", -+ "eth2pll", -+ "wocpu0", -+ "wocpu1", -+ "netsys0", -+ "netsys1", -+ "ethwarp_wocpu2", -+ "ethwarp_wocpu1", -+ "ethwarp_wocpu0", -+ "top_usxgmii0_sel", -+ "top_usxgmii1_sel", -+ "top_sgm0_sel", -+ "top_sgm1_sel", -+ "top_xfi_phy0_xtal_sel", -+ "top_xfi_phy1_xtal_sel", -+ "top_eth_gmii_sel", -+ "top_eth_refck_50m_sel", -+ "top_eth_sys_200m_sel", -+ "top_eth_sys_sel", -+ "top_eth_xgmii_sel", -+ "top_eth_mii_sel", -+ "top_netsys_sel", -+ "top_netsys_500m_sel", -+ "top_netsys_pao_2x_sel", -+ "top_netsys_sync_250m_sel", -+ "top_netsys_ppefb_250m_sel", -+ "top_netsys_warp_sel", - }; - - void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) -@@ -1253,10 +1345,19 @@ static void mtk_tx_set_dma_desc_v2(struc - data |= TX_DMA_LS0; - WRITE_ONCE(desc->txd3, data); - -- if (mac->id == MTK_GMAC3_ID) -- data = PSE_GDM3_PORT; -- else -- data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */ -+ /* set forward port */ -+ switch (mac->id) { -+ case MTK_GMAC1_ID: -+ data = PSE_GDM1_PORT << TX_DMA_FPORT_SHIFT_V2; -+ break; -+ case MTK_GMAC2_ID: -+ data = PSE_GDM2_PORT << TX_DMA_FPORT_SHIFT_V2; -+ break; -+ case MTK_GMAC3_ID: -+ data = PSE_GDM3_PORT << TX_DMA_FPORT_SHIFT_V2; -+ break; -+ } -+ - data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid); - WRITE_ONCE(desc->txd4, data); - -@@ -5010,6 +5111,25 @@ static const struct mtk_soc_data mt7986_ - }, - }; - -+static const struct mtk_soc_data mt7988_data = { -+ .reg_map = &mt7988_reg_map, -+ .ana_rgc3 = 0x128, -+ .caps = MT7988_CAPS, -+ .hw_features = MTK_HW_FEATURES, -+ .required_clks = MT7988_CLKS_BITMAP, -+ .required_pctl = false, -+ .num_devs = 3, -+ .txrx = { -+ .txd_size = sizeof(struct mtk_tx_dma_v2), -+ .rxd_size = sizeof(struct mtk_rx_dma_v2), -+ .rx_irq_done_mask = MTK_RX_DONE_INT_V2, -+ .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, -+ .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, -+ .dma_len_offset = 8, -+ }, -+}; -+ -+ - static const struct mtk_soc_data rt5350_data = { - .reg_map = &mt7628_reg_map, - .caps = MT7628_CAPS, -@@ -5028,14 +5148,15 @@ static const struct mtk_soc_data rt5350_ - }; - - const struct of_device_id of_mtk_match[] = { -- { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data}, -- { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data}, -- { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, -- { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, -- { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data}, -- { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data}, -- { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data}, -- { .compatible = "ralink,rt5350-eth", .data = &rt5350_data}, -+ { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data }, -+ { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data }, -+ { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data }, -+ { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data }, -+ { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data }, -+ { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data }, -+ { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data }, -+ { .compatible = "mediatek,mt7988-eth", .data = &mt7988_data }, -+ { .compatible = "ralink,rt5350-eth", .data = &rt5350_data }, - {}, - }; - MODULE_DEVICE_TABLE(of, of_mtk_match); ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -116,7 +116,8 @@ - #define MTK_CDMP_EG_CTRL 0x404 - - /* GDM Exgress Control Register */ --#define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) -+#define MTK_GDMA_FWD_CFG(x) ((x == MTK_GMAC3_ID) ? \ -+ 0x540 : 0x500 + (x * 0x1000)) - #define MTK_GDMA_SPECIAL_TAG BIT(24) - #define MTK_GDMA_ICS_EN BIT(22) - #define MTK_GDMA_TCS_EN BIT(21) -@@ -653,6 +654,11 @@ enum mtk_clks_map { - MTK_CLK_GP0, - MTK_CLK_GP1, - MTK_CLK_GP2, -+ MTK_CLK_GP3, -+ MTK_CLK_XGP1, -+ MTK_CLK_XGP2, -+ MTK_CLK_XGP3, -+ MTK_CLK_CRYPTO, - MTK_CLK_FE, - MTK_CLK_TRGPLL, - MTK_CLK_SGMII_TX_250M, -@@ -669,57 +675,108 @@ enum mtk_clks_map { - MTK_CLK_WOCPU1, - MTK_CLK_NETSYS0, - MTK_CLK_NETSYS1, -+ MTK_CLK_ETHWARP_WOCPU2, -+ MTK_CLK_ETHWARP_WOCPU1, -+ MTK_CLK_ETHWARP_WOCPU0, -+ MTK_CLK_TOP_USXGMII_SBUS_0_SEL, -+ MTK_CLK_TOP_USXGMII_SBUS_1_SEL, -+ MTK_CLK_TOP_SGM_0_SEL, -+ MTK_CLK_TOP_SGM_1_SEL, -+ MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL, -+ MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL, -+ MTK_CLK_TOP_ETH_GMII_SEL, -+ MTK_CLK_TOP_ETH_REFCK_50M_SEL, -+ MTK_CLK_TOP_ETH_SYS_200M_SEL, -+ MTK_CLK_TOP_ETH_SYS_SEL, -+ MTK_CLK_TOP_ETH_XGMII_SEL, -+ MTK_CLK_TOP_ETH_MII_SEL, -+ MTK_CLK_TOP_NETSYS_SEL, -+ MTK_CLK_TOP_NETSYS_500M_SEL, -+ MTK_CLK_TOP_NETSYS_PAO_2X_SEL, -+ MTK_CLK_TOP_NETSYS_SYNC_250M_SEL, -+ MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL, -+ MTK_CLK_TOP_NETSYS_WARP_SEL, - MTK_CLK_MAX - }; - --#define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ -- BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \ -- BIT(MTK_CLK_TRGPLL)) --#define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ -- BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ -- BIT(MTK_CLK_GP2) | \ -- BIT(MTK_CLK_SGMII_TX_250M) | \ -- BIT(MTK_CLK_SGMII_RX_250M) | \ -- BIT(MTK_CLK_SGMII_CDR_REF) | \ -- BIT(MTK_CLK_SGMII_CDR_FB) | \ -- BIT(MTK_CLK_SGMII_CK) | \ -- BIT(MTK_CLK_ETH2PLL)) -+#define MT7623_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \ -+ BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \ -+ BIT_ULL(MTK_CLK_TRGPLL)) -+#define MT7622_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \ -+ BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \ -+ BIT_ULL(MTK_CLK_GP2) | \ -+ BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ -+ BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ -+ BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ -+ BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ -+ BIT_ULL(MTK_CLK_SGMII_CK) | \ -+ BIT_ULL(MTK_CLK_ETH2PLL)) - #define MT7621_CLKS_BITMAP (0) - #define MT7628_CLKS_BITMAP (0) --#define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ -- BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ -- BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \ -- BIT(MTK_CLK_SGMII_TX_250M) | \ -- BIT(MTK_CLK_SGMII_RX_250M) | \ -- BIT(MTK_CLK_SGMII_CDR_REF) | \ -- BIT(MTK_CLK_SGMII_CDR_FB) | \ -- BIT(MTK_CLK_SGMII2_TX_250M) | \ -- BIT(MTK_CLK_SGMII2_RX_250M) | \ -- BIT(MTK_CLK_SGMII2_CDR_REF) | \ -- BIT(MTK_CLK_SGMII2_CDR_FB) | \ -- BIT(MTK_CLK_SGMII_CK) | \ -- BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP)) --#define MT7981_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \ -- BIT(MTK_CLK_WOCPU0) | \ -- BIT(MTK_CLK_SGMII_TX_250M) | \ -- BIT(MTK_CLK_SGMII_RX_250M) | \ -- BIT(MTK_CLK_SGMII_CDR_REF) | \ -- BIT(MTK_CLK_SGMII_CDR_FB) | \ -- BIT(MTK_CLK_SGMII2_TX_250M) | \ -- BIT(MTK_CLK_SGMII2_RX_250M) | \ -- BIT(MTK_CLK_SGMII2_CDR_REF) | \ -- BIT(MTK_CLK_SGMII2_CDR_FB) | \ -- BIT(MTK_CLK_SGMII_CK)) --#define MT7986_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \ -- BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \ -- BIT(MTK_CLK_SGMII_TX_250M) | \ -- BIT(MTK_CLK_SGMII_RX_250M) | \ -- BIT(MTK_CLK_SGMII_CDR_REF) | \ -- BIT(MTK_CLK_SGMII_CDR_FB) | \ -- BIT(MTK_CLK_SGMII2_TX_250M) | \ -- BIT(MTK_CLK_SGMII2_RX_250M) | \ -- BIT(MTK_CLK_SGMII2_CDR_REF) | \ -- BIT(MTK_CLK_SGMII2_CDR_FB)) -+#define MT7629_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \ -+ BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \ -+ BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_FE) | \ -+ BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ -+ BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ -+ BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ -+ BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ -+ BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ -+ BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ -+ BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ -+ BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \ -+ BIT_ULL(MTK_CLK_SGMII_CK) | \ -+ BIT_ULL(MTK_CLK_ETH2PLL) | BIT_ULL(MTK_CLK_SGMIITOP)) -+#define MT7981_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_GP1) | \ -+ BIT_ULL(MTK_CLK_WOCPU0) | \ -+ BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ -+ BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ -+ BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ -+ BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ -+ BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ -+ BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ -+ BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ -+ BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \ -+ BIT_ULL(MTK_CLK_SGMII_CK)) -+#define MT7986_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_GP1) | \ -+ BIT_ULL(MTK_CLK_WOCPU1) | BIT_ULL(MTK_CLK_WOCPU0) | \ -+ BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ -+ BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ -+ BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ -+ BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ -+ BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ -+ BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ -+ BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ -+ BIT_ULL(MTK_CLK_SGMII2_CDR_FB)) -+#define MT7988_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_ESW) | \ -+ BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \ -+ BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \ -+ BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \ -+ BIT_ULL(MTK_CLK_CRYPTO) | \ -+ BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ -+ BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ -+ BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ -+ BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ -+ BIT_ULL(MTK_CLK_ETHWARP_WOCPU2) | \ -+ BIT_ULL(MTK_CLK_ETHWARP_WOCPU1) | \ -+ BIT_ULL(MTK_CLK_ETHWARP_WOCPU0) | \ -+ BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_0_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_1_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_SGM_0_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_SGM_1_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_ETH_SYS_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_ETH_XGMII_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_ETH_MII_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_NETSYS_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_NETSYS_500M_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_NETSYS_PAO_2X_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_NETSYS_SYNC_250M_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_NETSYS_WARP_SEL)) - - enum mtk_dev_state { - MTK_HW_INIT, -@@ -847,6 +904,7 @@ enum mkt_eth_capabilities { - MTK_RGMII_BIT = 0, - MTK_TRGMII_BIT, - MTK_SGMII_BIT, -+ MTK_USXGMII_BIT, - MTK_ESW_BIT, - MTK_GEPHY_BIT, - MTK_MUX_BIT, -@@ -869,6 +927,8 @@ enum mkt_eth_capabilities { - MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, - MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, - MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, -+ MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT, -+ MTK_ETH_MUX_GMAC123_TO_USXGMII_BIT, - - /* PATH BITS */ - MTK_ETH_PATH_GMAC1_RGMII_BIT, -@@ -877,13 +937,18 @@ enum mkt_eth_capabilities { - MTK_ETH_PATH_GMAC2_RGMII_BIT, - MTK_ETH_PATH_GMAC2_SGMII_BIT, - MTK_ETH_PATH_GMAC2_GEPHY_BIT, -+ MTK_ETH_PATH_GMAC3_SGMII_BIT, - MTK_ETH_PATH_GDM1_ESW_BIT, -+ MTK_ETH_PATH_GMAC1_USXGMII_BIT, -+ MTK_ETH_PATH_GMAC2_USXGMII_BIT, -+ MTK_ETH_PATH_GMAC3_USXGMII_BIT, - }; - - /* Supported hardware group on SoCs */ - #define MTK_RGMII BIT_ULL(MTK_RGMII_BIT) - #define MTK_TRGMII BIT_ULL(MTK_TRGMII_BIT) - #define MTK_SGMII BIT_ULL(MTK_SGMII_BIT) -+#define MTK_USXGMII BIT_ULL(MTK_USXGMII_BIT) - #define MTK_ESW BIT_ULL(MTK_ESW_BIT) - #define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT) - #define MTK_MUX BIT_ULL(MTK_MUX_BIT) -@@ -910,6 +975,10 @@ enum mkt_eth_capabilities { - BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) - #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ - BIT_ULL(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) -+#define MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII \ -+ BIT_ULL(MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT) -+#define MTK_ETH_MUX_GMAC123_TO_USXGMII \ -+ BIT_ULL(MTK_ETH_MUX_GMAC123_TO_USXGMII_BIT) - - /* Supported path present on SoCs */ - #define MTK_ETH_PATH_GMAC1_RGMII BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT) -@@ -918,7 +987,11 @@ enum mkt_eth_capabilities { - #define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT) - #define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT) - #define MTK_ETH_PATH_GMAC2_GEPHY BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT) -+#define MTK_ETH_PATH_GMAC3_SGMII BIT_ULL(MTK_ETH_PATH_GMAC3_SGMII_BIT) - #define MTK_ETH_PATH_GDM1_ESW BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT) -+#define MTK_ETH_PATH_GMAC1_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC1_USXGMII_BIT) -+#define MTK_ETH_PATH_GMAC2_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC2_USXGMII_BIT) -+#define MTK_ETH_PATH_GMAC3_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC3_USXGMII_BIT) - - #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) - #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) -@@ -926,7 +999,11 @@ enum mkt_eth_capabilities { - #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) - #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) - #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) -+#define MTK_GMAC3_SGMII (MTK_ETH_PATH_GMAC3_SGMII | MTK_SGMII) - #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) -+#define MTK_GMAC1_USXGMII (MTK_ETH_PATH_GMAC1_USXGMII | MTK_USXGMII) -+#define MTK_GMAC2_USXGMII (MTK_ETH_PATH_GMAC2_USXGMII | MTK_USXGMII) -+#define MTK_GMAC3_USXGMII (MTK_ETH_PATH_GMAC3_USXGMII | MTK_USXGMII) - - /* MUXes present on SoCs */ - /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ -@@ -949,6 +1026,12 @@ enum mkt_eth_capabilities { - #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ - (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) - -+#define MTK_MUX_GMAC123_TO_GEPHY_SGMII \ -+ (MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII | MTK_MUX) -+ -+#define MTK_MUX_GMAC123_TO_USXGMII \ -+ (MTK_ETH_MUX_GMAC123_TO_USXGMII | MTK_MUX | MTK_INFRA) -+ - #ifdef CONFIG_SOC_MT7621 - #define MTK_CAP_MASK MTK_NETSYS_V2 - #else -@@ -987,9 +1070,17 @@ enum mkt_eth_capabilities { - MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \ - MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1) - --#define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ -- MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ -- MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1) -+#define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ -+ MTK_MUX_GMAC12_TO_GEPHY_SGMII | \ -+ MTK_QDMA | MTK_NETSYS_V2 | \ -+ MTK_RSTCTRL_PPE1) -+ -+#define MT7988_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ -+ MTK_GMAC3_SGMII | MTK_QDMA | \ -+ MTK_MUX_GMAC123_TO_GEPHY_SGMII | \ -+ MTK_NETSYS_V3 | MTK_RSTCTRL_PPE1 | \ -+ MTK_GMAC1_USXGMII | MTK_GMAC2_USXGMII | \ -+ MTK_GMAC3_USXGMII | MTK_MUX_GMAC123_TO_USXGMII) - - struct mtk_tx_dma_desc_info { - dma_addr_t addr; -@@ -1075,7 +1166,7 @@ struct mtk_soc_data { - const struct mtk_reg_map *reg_map; - u32 ana_rgc3; - u64 caps; -- u32 required_clks; -+ u64 required_clks; - bool required_pctl; - u8 offload_version; - u8 hash_offset; diff --git a/target/linux/generic/pending-6.1/737-07-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch b/target/linux/generic/pending-6.1/737-07-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch deleted file mode 100644 index 81b0d2e3f5f..00000000000 --- a/target/linux/generic/pending-6.1/737-07-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch +++ /dev/null @@ -1,1867 +0,0 @@ -From 3d833ad2cfc1ab503d9aae2967b7f10811bb3c9c Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Wed, 1 Mar 2023 11:56:04 +0000 -Subject: [PATCH 7/7] net: ethernet: mtk_eth_soc: add paths and SerDes modes - for MT7988 - -MT7988 comes with a built-in 2.5G PHY as well as -USXGMII/10GBase-KR/5GBase-KR compatible SerDes lanes for external PHYs. -Add support for configuring the MAC and SerDes parts for the new paths. - -Signed-off-by: Daniel Golle ---- - drivers/net/ethernet/mediatek/Kconfig | 7 + - drivers/net/ethernet/mediatek/Makefile | 1 + - drivers/net/ethernet/mediatek/mtk_eth_path.c | 154 +++- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 270 +++++- - drivers/net/ethernet/mediatek/mtk_eth_soc.h | 194 ++++- - drivers/net/ethernet/mediatek/mtk_usxgmii.c | 835 +++++++++++++++++++ - 6 files changed, 1428 insertions(+), 33 deletions(-) - create mode 100644 drivers/net/ethernet/mediatek/mtk_usxgmii.c - ---- a/drivers/net/ethernet/mediatek/Kconfig -+++ b/drivers/net/ethernet/mediatek/Kconfig -@@ -25,6 +25,13 @@ config NET_MEDIATEK_SOC - This driver supports the gigabit ethernet MACs in the - MediaTek SoC family. - -+config NET_MEDIATEK_SOC_USXGMII -+ bool "Support USXGMII SerDes on MT7988" -+ depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST -+ def_bool NET_MEDIATEK_SOC != n -+ help -+ Include support for 10G SerDes which can be found on MT7988. -+ - config NET_MEDIATEK_STAR_EMAC - tristate "MediaTek STAR Ethernet MAC support" - select PHYLIB ---- a/drivers/net/ethernet/mediatek/Makefile -+++ b/drivers/net/ethernet/mediatek/Makefile -@@ -5,6 +5,7 @@ - - obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o - mtk_eth-y := mtk_eth_soc.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o -+mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_USXGMII) += mtk_usxgmii.o - mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o mtk_wed_mcu.o mtk_wed_wo.o - ifdef CONFIG_DEBUG_FS - mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_debugfs.o ---- a/drivers/net/ethernet/mediatek/mtk_eth_path.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c -@@ -31,10 +31,20 @@ static const char *mtk_eth_path_name(u64 - return "gmac2_rgmii"; - case MTK_ETH_PATH_GMAC2_SGMII: - return "gmac2_sgmii"; -+ case MTK_ETH_PATH_GMAC2_2P5GPHY: -+ return "gmac2_2p5gphy"; - case MTK_ETH_PATH_GMAC2_GEPHY: - return "gmac2_gephy"; -+ case MTK_ETH_PATH_GMAC3_SGMII: -+ return "gmac3_sgmii"; - case MTK_ETH_PATH_GDM1_ESW: - return "gdm1_esw"; -+ case MTK_ETH_PATH_GMAC1_USXGMII: -+ return "gmac1_usxgmii"; -+ case MTK_ETH_PATH_GMAC2_USXGMII: -+ return "gmac2_usxgmii"; -+ case MTK_ETH_PATH_GMAC3_USXGMII: -+ return "gmac3_usxgmii"; - default: - return "unknown path"; - } -@@ -42,8 +52,8 @@ static const char *mtk_eth_path_name(u64 - - static int set_mux_gdm1_to_gmac1_esw(struct mtk_eth *eth, u64 path) - { -+ u32 val, mask, set, reg; - bool updated = true; -- u32 val, mask, set; - - switch (path) { - case MTK_ETH_PATH_GMAC1_SGMII: -@@ -59,10 +69,15 @@ static int set_mux_gdm1_to_gmac1_esw(str - break; - } - -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) -+ reg = MTK_MAC_MISC_V3; -+ else -+ reg = MTK_MAC_MISC; -+ - if (updated) { -- val = mtk_r32(eth, MTK_MAC_MISC); -+ val = mtk_r32(eth, reg); - val = (val & mask) | set; -- mtk_w32(eth, val, MTK_MAC_MISC); -+ mtk_w32(eth, val, reg); - } - - dev_dbg(eth->dev, "path %s in %s updated = %d\n", -@@ -125,6 +140,31 @@ static int set_mux_u3_gmac2_to_qphy(stru - return 0; - } - -+static int set_mux_gmac2_to_2p5gphy(struct mtk_eth *eth, u64 path) -+{ -+ unsigned int val = 0; -+ bool updated = true; -+ int mac_id = 0; -+ -+ regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); -+ -+ switch (path) { -+ case MTK_ETH_PATH_GMAC2_2P5GPHY: -+ val &= ~(u32)SYSCFG0_SGMII_GMAC2_V2; -+ mac_id = MTK_GMAC2_ID; -+ break; -+ default: -+ updated = false; -+ break; -+ }; -+ -+ if (updated) -+ regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, -+ SYSCFG0_SGMII_MASK, val); -+ -+ return 0; -+} -+ - static int set_mux_gmac1_gmac2_to_sgmii_rgmii(struct mtk_eth *eth, u64 path) - { - unsigned int val = 0; -@@ -163,7 +203,61 @@ static int set_mux_gmac1_gmac2_to_sgmii_ - return 0; - } - --static int set_mux_gmac12_to_gephy_sgmii(struct mtk_eth *eth, u64 path) -+static int set_mux_gmac123_to_usxgmii(struct mtk_eth *eth, u64 path) -+{ -+ unsigned int val = 0; -+ bool updated = true; -+ int mac_id = 0; -+ -+ dev_dbg(eth->dev, "path %s in %s updated = %d\n", -+ mtk_eth_path_name(path), __func__, updated); -+ -+ /* Disable SYSCFG1 SGMII */ -+ regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); -+ -+ switch (path) { -+ case MTK_ETH_PATH_GMAC1_USXGMII: -+ val &= ~(u32)SYSCFG0_SGMII_GMAC1_V2; -+ mac_id = MTK_GMAC1_ID; -+ break; -+ case MTK_ETH_PATH_GMAC2_USXGMII: -+ val &= ~(u32)SYSCFG0_SGMII_GMAC2_V2; -+ mac_id = MTK_GMAC2_ID; -+ break; -+ case MTK_ETH_PATH_GMAC3_USXGMII: -+ val &= ~(u32)SYSCFG0_SGMII_GMAC3_V2; -+ mac_id = MTK_GMAC3_ID; -+ break; -+ default: -+ updated = false; -+ }; -+ -+ if (updated) { -+ regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, -+ SYSCFG0_SGMII_MASK, val); -+ -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3) && -+ mac_id == MTK_GMAC2_ID) { -+ regmap_update_bits(eth->infra, -+ TOP_MISC_NETSYS_PCS_MUX, -+ NETSYS_PCS_MUX_MASK, -+ MUX_G2_USXGMII_SEL); -+ } -+ } -+ -+ /* Enable XGDM Path */ -+ val = mtk_r32(eth, MTK_GDMA_EG_CTRL(mac_id)); -+ val |= MTK_GDMA_XGDM_SEL; -+ mtk_w32(eth, val, MTK_GDMA_EG_CTRL(mac_id)); -+ -+ dev_dbg(eth->dev, "path %s in %s updated = %d\n", -+ mtk_eth_path_name(path), __func__, updated); -+ -+ -+ return 0; -+} -+ -+static int set_mux_gmac123_to_gephy_sgmii(struct mtk_eth *eth, u64 path) - { - unsigned int val = 0; - bool updated = true; -@@ -180,6 +274,9 @@ static int set_mux_gmac12_to_gephy_sgmii - case MTK_ETH_PATH_GMAC2_SGMII: - val |= SYSCFG0_SGMII_GMAC2_V2; - break; -+ case MTK_ETH_PATH_GMAC3_SGMII: -+ val |= SYSCFG0_SGMII_GMAC3_V2; -+ break; - default: - updated = false; - } -@@ -208,13 +305,25 @@ static const struct mtk_eth_muxc mtk_eth - .cap_bit = MTK_ETH_MUX_U3_GMAC2_TO_QPHY, - .set_path = set_mux_u3_gmac2_to_qphy, - }, { -+ .name = "mux_gmac2_to_2p5gphy", -+ .cap_bit = MTK_ETH_MUX_GMAC2_TO_2P5GPHY, -+ .set_path = set_mux_gmac2_to_2p5gphy, -+ }, { - .name = "mux_gmac1_gmac2_to_sgmii_rgmii", - .cap_bit = MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII, - .set_path = set_mux_gmac1_gmac2_to_sgmii_rgmii, - }, { - .name = "mux_gmac12_to_gephy_sgmii", - .cap_bit = MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII, -- .set_path = set_mux_gmac12_to_gephy_sgmii, -+ .set_path = set_mux_gmac123_to_gephy_sgmii, -+ }, { -+ .name = "mux_gmac123_to_gephy_sgmii", -+ .cap_bit = MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII, -+ .set_path = set_mux_gmac123_to_gephy_sgmii, -+ }, { -+ .name = "mux_gmac123_to_usxgmii", -+ .cap_bit = MTK_ETH_MUX_GMAC123_TO_USXGMII, -+ .set_path = set_mux_gmac123_to_usxgmii, - }, - }; - -@@ -243,16 +352,46 @@ static int mtk_eth_mux_setup(struct mtk_ - } - } - -+ dev_dbg(eth->dev, "leaving mux_setup %s\n", -+ mtk_eth_path_name(path)); -+ - out: - return err; - } - -+int mtk_gmac_usxgmii_path_setup(struct mtk_eth *eth, int mac_id) -+{ -+ u64 path; -+ -+ path = (mac_id == MTK_GMAC1_ID) ? MTK_ETH_PATH_GMAC1_USXGMII : -+ (mac_id == MTK_GMAC2_ID) ? MTK_ETH_PATH_GMAC2_USXGMII : -+ MTK_ETH_PATH_GMAC3_USXGMII; -+ -+ /* Setup proper MUXes along the path */ -+ return mtk_eth_mux_setup(eth, path); -+} -+ - int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id) - { - u64 path; - -- path = (mac_id == 0) ? MTK_ETH_PATH_GMAC1_SGMII : -- MTK_ETH_PATH_GMAC2_SGMII; -+ path = (mac_id == MTK_GMAC1_ID) ? MTK_ETH_PATH_GMAC1_SGMII : -+ (mac_id == MTK_GMAC2_ID) ? MTK_ETH_PATH_GMAC2_SGMII : -+ MTK_ETH_PATH_GMAC3_SGMII; -+ -+ /* Setup proper MUXes along the path */ -+ return mtk_eth_mux_setup(eth, path); -+} -+ -+int mtk_gmac_2p5gphy_path_setup(struct mtk_eth *eth, int mac_id) -+{ -+ u64 path = 0; -+ -+ if (mac_id == MTK_GMAC2_ID) -+ path = MTK_ETH_PATH_GMAC2_2P5GPHY; -+ -+ if (!path) -+ return -EINVAL; - - /* Setup proper MUXes along the path */ - return mtk_eth_mux_setup(eth, path); -@@ -282,4 +421,3 @@ int mtk_gmac_rgmii_path_setup(struct mtk - /* Setup proper MUXes along the path */ - return mtk_eth_mux_setup(eth, path); - } -- ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -480,6 +480,23 @@ static void mtk_gmac0_rgmii_adjust(struc - mtk_w32(eth, val, TRGMII_TCK_CTRL); - } - -+static void mtk_setup_bridge_switch(struct mtk_eth *eth) -+{ -+ int val; -+ -+ /* Force Port1 XGMAC Link Up */ -+ val = mtk_r32(eth, MTK_XGMAC_STS(MTK_GMAC1_ID)); -+ mtk_w32(eth, val | MTK_XGMAC_FORCE_LINK(MTK_GMAC1_ID), -+ MTK_XGMAC_STS(MTK_GMAC1_ID)); -+ -+ /* Adjust GSW bridge IPG to 11*/ -+ val = mtk_r32(eth, MTK_GSW_CFG); -+ val &= ~(GSWTX_IPG_MASK | GSWRX_IPG_MASK); -+ val |= (GSW_IPG_11 << GSWTX_IPG_SHIFT) | -+ (GSW_IPG_11 << GSWRX_IPG_SHIFT); -+ mtk_w32(eth, val, MTK_GSW_CFG); -+} -+ - static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config, - phy_interface_t interface) - { -@@ -494,6 +511,12 @@ static struct phylink_pcs *mtk_mac_selec - 0 : mac->id; - - return eth->sgmii_pcs[sid]; -+ } else if ((interface == PHY_INTERFACE_MODE_USXGMII || -+ interface == PHY_INTERFACE_MODE_10GKR || -+ interface == PHY_INTERFACE_MODE_5GBASER) && -+ MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3) && -+ mac->id != MTK_GMAC1_ID) { -+ return mtk_usxgmii_select_pcs(eth, mac->id); - } - - return NULL; -@@ -505,7 +528,7 @@ static void mtk_mac_config(struct phylin - struct mtk_mac *mac = container_of(config, struct mtk_mac, - phylink_config); - struct mtk_eth *eth = mac->hw; -- int val, ge_mode, err = 0; -+ int val, ge_mode, force_link, err = 0; - u32 i; - - /* MT76x8 has no hardware settings between for the MAC */ -@@ -549,6 +572,23 @@ static void mtk_mac_config(struct phylin - goto init_err; - } - break; -+ case PHY_INTERFACE_MODE_USXGMII: -+ case PHY_INTERFACE_MODE_10GKR: -+ case PHY_INTERFACE_MODE_5GBASER: -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII)) { -+ err = mtk_gmac_usxgmii_path_setup(eth, mac->id); -+ if (err) -+ goto init_err; -+ } -+ break; -+ case PHY_INTERFACE_MODE_INTERNAL: -+ if (mac->id == MTK_GMAC2_ID && -+ MTK_HAS_CAPS(eth->soc->caps, MTK_2P5GPHY)) { -+ err = mtk_gmac_2p5gphy_path_setup(eth, mac->id); -+ if (err) -+ goto init_err; -+ } -+ break; - default: - goto err_phy; - } -@@ -627,14 +667,78 @@ static void mtk_mac_config(struct phylin - SYSCFG0_SGMII_MASK, - ~(u32)SYSCFG0_SGMII_MASK); - -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { -+ mtk_xfi_pll_enable(eth); -+ mtk_sgmii_reset(eth, mac->id); -+ if (phylink_autoneg_inband(mode)) -+ mtk_sgmii_setup_phya_gen1(eth, mac->id); -+ else -+ mtk_sgmii_setup_phya_gen2(eth, mac->id); -+ } - /* Save the syscfg0 value for mac_finish */ - mac->syscfg0 = val; -- } else if (phylink_autoneg_inband(mode)) { -+ } else if (state->interface != PHY_INTERFACE_MODE_USXGMII && -+ state->interface != PHY_INTERFACE_MODE_10GKR && -+ state->interface != PHY_INTERFACE_MODE_5GBASER && -+ phylink_autoneg_inband(mode)) { - dev_err(eth->dev, -- "In-band mode not supported in non SGMII mode!\n"); -+ "In-band mode not supported in non-SerDes modes!\n"); - return; - } - -+ /* Setup gmac */ -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3) && -+ (mtk_interface_mode_is_xgmii(state->interface) || -+ mac->interface == PHY_INTERFACE_MODE_INTERNAL)) { -+ mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id)); -+ mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id)); -+ -+ switch (mac->id) { -+ case MTK_GMAC1_ID: -+ mtk_setup_bridge_switch(eth); -+ break; -+ case MTK_GMAC2_ID: -+ force_link = (mac->interface == -+ PHY_INTERFACE_MODE_INTERNAL) ? -+ MTK_XGMAC_FORCE_LINK(mac->id) : 0; -+ val = mtk_r32(eth, MTK_XGMAC_STS(mac->id)); -+ mtk_w32(eth, val | force_link, -+ MTK_XGMAC_STS(mac->id)); -+ break; -+ case MTK_GMAC3_ID: -+ val = mtk_r32(eth, MTK_XGMAC_STS(mac->id)); -+ mtk_w32(eth, val | MTK_XGMAC_FORCE_LINK(mac->id), -+ MTK_XGMAC_STS(mac->id)); -+ break; -+ } -+ } else { -+ val = mtk_r32(eth, MTK_GDMA_EG_CTRL(mac->id)); -+ mtk_w32(eth, val & ~MTK_GDMA_XGDM_SEL, -+ MTK_GDMA_EG_CTRL(mac->id)); -+ -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { -+ switch (mac->id) { -+ case MTK_GMAC2_ID: -+ case MTK_GMAC3_ID: -+ val = mtk_r32(eth, MTK_XGMAC_STS(mac->id)); -+ mtk_w32(eth, -+ val & ~MTK_XGMAC_FORCE_LINK(mac->id), -+ MTK_XGMAC_STS(mac->id)); -+ break; -+ } -+ } -+ -+/* -+ if (mac->type != mac_type) { -+ if (atomic_read(&reset_pending) == 0) { -+ atomic_inc(&force); -+ schedule_work(ð->pending_work); -+ atomic_inc(&reset_pending); -+ } else -+ atomic_dec(&reset_pending); -+ } -+*/ -+ } - return; - - err_phy: -@@ -675,11 +779,40 @@ static int mtk_mac_finish(struct phylink - return 0; - } - --static void mtk_mac_pcs_get_state(struct phylink_config *config, -+static void mtk_xgdm_pcs_get_state(struct mtk_mac *mac, -+ struct phylink_link_state *state) -+{ -+ u32 sts = mtk_r32(mac->hw, MTK_XGMAC_STS(mac->id)); -+ -+ if (mac->id == MTK_GMAC2_ID) -+ sts = sts >> 16; -+ -+ state->link = FIELD_GET(MTK_USXGMII_PCS_LINK, sts); -+ if (!state->link) -+ return; -+ -+ state->duplex = DUPLEX_FULL; -+ state->interface = mac->interface; -+ -+ switch (FIELD_GET(MTK_USXGMII_PCS_MODE, sts)) { -+ case 0: -+ state->speed = SPEED_10000; -+ break; -+ case 1: -+ state->speed = SPEED_5000; -+ break; -+ case 2: -+ state->speed = SPEED_2500; -+ break; -+ case 3: -+ state->speed = SPEED_1000; -+ break; -+ } -+} -+ -+static void mtk_gdm_pcs_get_state(struct mtk_mac *mac, - struct phylink_link_state *state) - { -- struct mtk_mac *mac = container_of(config, struct mtk_mac, -- phylink_config); - u32 pmsr = mtk_r32(mac->hw, MTK_MAC_MSR(mac->id)); - - state->link = (pmsr & MAC_MSR_LINK); -@@ -707,15 +840,35 @@ static void mtk_mac_pcs_get_state(struct - state->pause |= MLO_PAUSE_TX; - } - -+static void mtk_mac_pcs_get_state(struct phylink_config *config, -+ struct phylink_link_state *state) -+{ -+ struct mtk_mac *mac = container_of(config, struct mtk_mac, -+ phylink_config); -+ -+ if (mtk_interface_mode_is_xgmii(state->interface)) -+ mtk_xgdm_pcs_get_state(mac, state); -+ else -+ mtk_gdm_pcs_get_state(mac, state); -+} -+ - static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode, - phy_interface_t interface) - { - struct mtk_mac *mac = container_of(config, struct mtk_mac, - phylink_config); -- u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); -+ u32 mcr; - -- mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN); -- mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); -+ if (!mtk_interface_mode_is_xgmii(interface)) { -+ mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); -+ mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN); -+ mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); -+ } else if (mac->id != MTK_GMAC1_ID) { -+ mcr = mtk_r32(mac->hw, MTK_XMAC_MCR(mac->id)); -+ mcr &= 0xfffffff0; -+ mcr |= XMAC_MCR_TRX_DISABLE; -+ mtk_w32(mac->hw, mcr, MTK_XMAC_MCR(mac->id)); -+ } - } - - static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx, -@@ -787,13 +940,11 @@ static void mtk_set_queue_speed(struct m - mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); - } - --static void mtk_mac_link_up(struct phylink_config *config, -- struct phy_device *phy, -- unsigned int mode, phy_interface_t interface, -- int speed, int duplex, bool tx_pause, bool rx_pause) -+static void mtk_gdm_mac_link_up(struct mtk_mac *mac, -+ struct phy_device *phy, -+ unsigned int mode, phy_interface_t interface, -+ int speed, int duplex, bool tx_pause, bool rx_pause) - { -- struct mtk_mac *mac = container_of(config, struct mtk_mac, -- phylink_config); - u32 mcr; - - mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); -@@ -827,6 +978,47 @@ static void mtk_mac_link_up(struct phyli - mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); - } - -+static void mtk_xgdm_mac_link_up(struct mtk_mac *mac, -+ struct phy_device *phy, -+ unsigned int mode, phy_interface_t interface, -+ int speed, int duplex, bool tx_pause, bool rx_pause) -+{ -+ u32 mcr; -+ -+ if (mac->id == MTK_GMAC1_ID) -+ return; -+ -+ mcr = mtk_r32(mac->hw, MTK_XMAC_MCR(mac->id)); -+ -+ mcr &= ~(XMAC_MCR_FORCE_TX_FC | XMAC_MCR_FORCE_RX_FC); -+ /* Configure pause modes - -+ * phylink will avoid these for half duplex -+ */ -+ if (tx_pause) -+ mcr |= XMAC_MCR_FORCE_TX_FC; -+ if (rx_pause) -+ mcr |= XMAC_MCR_FORCE_RX_FC; -+ -+ mcr &= ~(XMAC_MCR_TRX_DISABLE); -+ mtk_w32(mac->hw, mcr, MTK_XMAC_MCR(mac->id)); -+} -+ -+static void mtk_mac_link_up(struct phylink_config *config, -+ struct phy_device *phy, -+ unsigned int mode, phy_interface_t interface, -+ int speed, int duplex, bool tx_pause, bool rx_pause) -+{ -+ struct mtk_mac *mac = container_of(config, struct mtk_mac, -+ phylink_config); -+ -+ if (mtk_interface_mode_is_xgmii(interface)) -+ mtk_xgdm_mac_link_up(mac, phy, mode, interface, speed, duplex, -+ tx_pause, rx_pause); -+ else -+ mtk_gdm_mac_link_up(mac, phy, mode, interface, speed, duplex, -+ tx_pause, rx_pause); -+} -+ - static const struct phylink_mac_ops mtk_phylink_ops = { - .validate = phylink_generic_validate, - .mac_select_pcs = mtk_mac_select_pcs, -@@ -880,10 +1072,21 @@ static int mtk_mdio_init(struct mtk_eth - } - divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63); - -+ /* Configure MDC Turbo Mode */ -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { -+ val = mtk_r32(eth, MTK_MAC_MISC_V3); -+ val |= MISC_MDC_TURBO; -+ mtk_w32(eth, val, MTK_MAC_MISC_V3); -+ } else { -+ val = mtk_r32(eth, MTK_PPSC); -+ val |= PPSC_MDC_TURBO; -+ mtk_w32(eth, val, MTK_PPSC); -+ } -+ - /* Configure MDC Divider */ - val = mtk_r32(eth, MTK_PPSC); - val &= ~PPSC_MDC_CFG; -- val |= FIELD_PREP(PPSC_MDC_CFG, divider) | PPSC_MDC_TURBO; -+ val |= FIELD_PREP(PPSC_MDC_CFG, divider); - mtk_w32(eth, val, MTK_PPSC); - - dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider); -@@ -4469,8 +4672,8 @@ static int mtk_add_mac(struct mtk_eth *e - const __be32 *_id = of_get_property(np, "reg", NULL); - phy_interface_t phy_mode; - struct phylink *phylink; -- struct mtk_mac *mac; - int id, err; -+ struct mtk_mac *mac; - int txqs = 1; - - if (!_id) { -@@ -4572,6 +4775,32 @@ static int mtk_add_mac(struct mtk_eth *e - mac->phylink_config.supported_interfaces); - } - -+ if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_USXGMII)) { -+ if (id == MTK_GMAC1_ID) { -+ mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | -+ MAC_SYM_PAUSE | -+ MAC_10000FD; -+ phy_interface_zero( -+ mac->phylink_config.supported_interfaces); -+ __set_bit(PHY_INTERFACE_MODE_INTERNAL, -+ mac->phylink_config.supported_interfaces); -+ } else { -+ mac->phylink_config.mac_capabilities |= MAC_5000FD | MAC_10000FD; -+ __set_bit(PHY_INTERFACE_MODE_5GBASER, -+ mac->phylink_config.supported_interfaces); -+ __set_bit(PHY_INTERFACE_MODE_10GKR, -+ mac->phylink_config.supported_interfaces); -+ __set_bit(PHY_INTERFACE_MODE_USXGMII, -+ mac->phylink_config.supported_interfaces); -+ } -+ } -+ -+ if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_2P5GPHY)) { -+ if (id == MTK_GMAC2_ID) -+ __set_bit(PHY_INTERFACE_MODE_INTERNAL, -+ mac->phylink_config.supported_interfaces); -+ } -+ - phylink = phylink_create(&mac->phylink_config, - of_fwnode_handle(mac->of_node), - phy_mode, &mtk_phylink_ops); -@@ -4759,6 +4988,13 @@ static int mtk_probe(struct platform_dev - - if (err) - return err; -+ } -+ -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII)) { -+ err = mtk_usxgmii_init(eth); -+ -+ if (err) -+ return err; - } - - if (eth->soc->required_pctl) { ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -126,6 +126,11 @@ - #define MTK_GDMA_TO_PDMA 0x0 - #define MTK_GDMA_DROP_ALL 0x7777 - -+/* GDM Egress Control Register */ -+#define MTK_GDMA_EG_CTRL(x) ((x == MTK_GMAC3_ID) ? \ -+ 0x544 : 0x504 + (x * 0x1000)) -+#define MTK_GDMA_XGDM_SEL BIT(31) -+ - /* Unicast Filter MAC Address Register - Low */ - #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) - -@@ -389,7 +394,26 @@ - #define PHY_IAC_TIMEOUT HZ - - #define MTK_MAC_MISC 0x1000c -+#define MTK_MAC_MISC_V3 0x10010 - #define MTK_MUX_TO_ESW BIT(0) -+#define MISC_MDC_TURBO BIT(4) -+ -+/* XMAC status registers */ -+#define MTK_XGMAC_STS(x) ((x == MTK_GMAC3_ID) ? 0x1001C : 0x1000C) -+#define MTK_XGMAC_FORCE_LINK(x) ((x == MTK_GMAC2_ID) ? BIT(31) : BIT(15)) -+#define MTK_USXGMII_PCS_LINK BIT(8) -+#define MTK_XGMAC_RX_FC BIT(5) -+#define MTK_XGMAC_TX_FC BIT(4) -+#define MTK_USXGMII_PCS_MODE GENMASK(3, 1) -+#define MTK_XGMAC_LINK_STS BIT(0) -+ -+/* GSW bridge registers */ -+#define MTK_GSW_CFG (0x10080) -+#define GSWTX_IPG_MASK GENMASK(19, 16) -+#define GSWTX_IPG_SHIFT 16 -+#define GSWRX_IPG_MASK GENMASK(3, 0) -+#define GSWRX_IPG_SHIFT 0 -+#define GSW_IPG_11 11 - - /* Mac control registers */ - #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) -@@ -414,6 +438,17 @@ - #define MAC_MCR_FORCE_LINK BIT(0) - #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE) - -+/* Mac EEE control registers */ -+#define MTK_MAC_EEE(x) (0x10104 + (x * 0x100)) -+#define MAC_EEE_WAKEUP_TIME_1000 GENMASK(31, 24) -+#define MAC_EEE_WAKEUP_TIME_100 GENMASK(23, 16) -+#define MAC_EEE_LPI_TXIDLE_THD GENMASK(15, 8) -+#define MAC_EEE_RESV0 GENMASK(7, 4) -+#define MAC_EEE_CKG_TXILDE BIT(3) -+#define MAC_EEE_CKG_RXLPI BIT(2) -+#define MAC_EEE_TX_DOWN_REQ BIT(1) -+#define MAC_EEE_LPI_MODE BIT(0) -+ - /* Mac status registers */ - #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100)) - #define MAC_MSR_EEE1G BIT(7) -@@ -458,6 +493,12 @@ - #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) - #define INTF_MODE_RGMII_10_100 0 - -+/* XFI Mac control registers */ -+#define MTK_XMAC_MCR(x) (0x12000 + ((x - 1) * 0x1000)) -+#define XMAC_MCR_TRX_DISABLE 0xf -+#define XMAC_MCR_FORCE_TX_FC BIT(5) -+#define XMAC_MCR_FORCE_RX_FC BIT(4) -+ - /* GPIO port control registers for GMAC 2*/ - #define GPIO_OD33_CTRL8 0x4c0 - #define GPIO_BIAS_CTRL 0xed0 -@@ -483,6 +524,7 @@ - #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) - #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) - #define SYSCFG0_SGMII_GMAC2_V2 BIT(8) -+#define SYSCFG0_SGMII_GMAC3_V2 BIT(7) - - - /* ethernet subsystem clock register */ -@@ -509,16 +551,91 @@ - #define ETHSYS_DMA_AG_MAP_QDMA BIT(1) - #define ETHSYS_DMA_AG_MAP_PPE BIT(2) - -+/* USXGMII subsystem config registers */ -+/* Register to control speed */ -+#define RG_PHY_TOP_SPEED_CTRL1 0x80C -+#define USXGMII_RATE_UPDATE_MODE BIT(31) -+#define USXGMII_MAC_CK_GATED BIT(29) -+#define USXGMII_IF_FORCE_EN BIT(28) -+#define USXGMII_RATE_ADAPT_MODE GENMASK(10, 8) -+#define USXGMII_RATE_ADAPT_MODE_X1 0 -+#define USXGMII_RATE_ADAPT_MODE_X2 1 -+#define USXGMII_RATE_ADAPT_MODE_X4 2 -+#define USXGMII_RATE_ADAPT_MODE_X10 3 -+#define USXGMII_RATE_ADAPT_MODE_X100 4 -+#define USXGMII_RATE_ADAPT_MODE_X5 5 -+#define USXGMII_RATE_ADAPT_MODE_X50 6 -+#define USXGMII_XFI_RX_MODE GENMASK(6, 4) -+#define USXGMII_XFI_RX_MODE_10G 0 -+#define USXGMII_XFI_RX_MODE_5G 1 -+#define USXGMII_XFI_TX_MODE GENMASK(2, 0) -+#define USXGMII_XFI_TX_MODE_10G 0 -+#define USXGMII_XFI_TX_MODE_5G 1 -+ -+/* Register to control PCS AN */ -+#define RG_PCS_AN_CTRL0 0x810 -+#define USXGMII_AN_RESTART BIT(31) -+#define USXGMII_AN_SYNC_CNT GENMASK(30, 11) -+#define USXGMII_AN_ENABLE BIT(0) -+ -+#define RG_PCS_AN_CTRL2 0x818 -+#define USXGMII_LINK_TIMER_IDLE_DETECT GENMASK(29, 20) -+#define USXGMII_LINK_TIMER_COMP_ACK_DETECT GENMASK(19, 10) -+#define USXGMII_LINK_TIMER_AN_RESTART GENMASK(9, 0) -+ -+/* Register to read PCS AN status */ -+#define RG_PCS_AN_STS0 0x81c -+#define USXGMII_LPA_SPEED_MASK GENMASK(11, 9) -+#define USXGMII_LPA_SPEED_10 0 -+#define USXGMII_LPA_SPEED_100 1 -+#define USXGMII_LPA_SPEED_1000 2 -+#define USXGMII_LPA_SPEED_10000 3 -+#define USXGMII_LPA_SPEED_2500 4 -+#define USXGMII_LPA_SPEED_5000 5 -+#define USXGMII_LPA_DUPLEX BIT(12) -+#define USXGMII_LPA_LINK BIT(15) -+#define USXGMII_LPA_LATCH BIT(31) -+ -+/* Register to control USXGMII XFI PLL digital */ -+#define XFI_PLL_DIG_GLB8 0x08 -+#define RG_XFI_PLL_EN BIT(31) -+ -+/* Register to control USXGMII XFI PLL analog */ -+#define XFI_PLL_ANA_GLB8 0x108 -+#define RG_XFI_PLL_ANA_SWWA 0x02283248 -+ - /* Infrasys subsystem config registers */ - #define INFRA_MISC2 0x70c - #define CO_QPHY_SEL BIT(0) - #define GEPHY_MAC_SEL BIT(1) - -+/* Toprgu subsystem config registers */ -+#define TOPRGU_SWSYSRST 0x18 -+#define SWSYSRST_UNLOCK_KEY GENMASK(31, 24) -+#define SWSYSRST_XFI_PLL_GRST BIT(16) -+#define SWSYSRST_XFI_PEXPT1_GRST BIT(15) -+#define SWSYSRST_XFI_PEXPT0_GRST BIT(14) -+#define SWSYSRST_XFI1_GRST BIT(13) -+#define SWSYSRST_XFI0_GRST BIT(12) -+#define SWSYSRST_SGMII1_GRST BIT(2) -+#define SWSYSRST_SGMII0_GRST BIT(1) -+#define TOPRGU_SWSYSRST_EN 0xFC -+ - /* Top misc registers */ -+#define TOP_MISC_NETSYS_PCS_MUX 0x84 -+#define NETSYS_PCS_MUX_MASK GENMASK(1, 0) -+#define MUX_G2_USXGMII_SEL BIT(1) -+#define MUX_HSGMII1_G1_SEL BIT(0) -+ - #define USB_PHY_SWITCH_REG 0x218 - #define QPHY_SEL_MASK GENMASK(1, 0) - #define SGMII_QPHY_SEL 0x2 - -+/* MDIO control */ -+#define MII_MMD_ACC_CTL_REG 0x0d -+#define MII_MMD_ADDR_DATA_REG 0x0e -+#define MMD_OP_MODE_DATA BIT(14) -+ - /* MT7628/88 specific stuff */ - #define MT7628_PDMA_OFFSET 0x0800 - #define MT7628_SDM_OFFSET 0x0c00 -@@ -812,13 +929,6 @@ enum mtk_gmac_id { - MTK_GMAC_ID_MAX - }; - --/* GDM Type */ --enum mtk_gdm_type { -- MTK_GDM_TYPE = 0, -- MTK_XGDM_TYPE, -- MTK_GDM_TYPE_MAX --}; -- - enum mtk_tx_buf_type { - MTK_TYPE_SKB, - MTK_TYPE_XDP_TX, -@@ -905,6 +1015,7 @@ enum mkt_eth_capabilities { - MTK_TRGMII_BIT, - MTK_SGMII_BIT, - MTK_USXGMII_BIT, -+ MTK_2P5GPHY_BIT, - MTK_ESW_BIT, - MTK_GEPHY_BIT, - MTK_MUX_BIT, -@@ -925,6 +1036,7 @@ enum mkt_eth_capabilities { - MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, - MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT, - MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, -+ MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT, - MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, - MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, - MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT, -@@ -936,6 +1048,7 @@ enum mkt_eth_capabilities { - MTK_ETH_PATH_GMAC1_SGMII_BIT, - MTK_ETH_PATH_GMAC2_RGMII_BIT, - MTK_ETH_PATH_GMAC2_SGMII_BIT, -+ MTK_ETH_PATH_GMAC2_2P5GPHY_BIT, - MTK_ETH_PATH_GMAC2_GEPHY_BIT, - MTK_ETH_PATH_GMAC3_SGMII_BIT, - MTK_ETH_PATH_GDM1_ESW_BIT, -@@ -949,6 +1062,7 @@ enum mkt_eth_capabilities { - #define MTK_TRGMII BIT_ULL(MTK_TRGMII_BIT) - #define MTK_SGMII BIT_ULL(MTK_SGMII_BIT) - #define MTK_USXGMII BIT_ULL(MTK_USXGMII_BIT) -+#define MTK_2P5GPHY BIT_ULL(MTK_2P5GPHY_BIT) - #define MTK_ESW BIT_ULL(MTK_ESW_BIT) - #define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT) - #define MTK_MUX BIT_ULL(MTK_MUX_BIT) -@@ -971,6 +1085,8 @@ enum mkt_eth_capabilities { - BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) - #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ - BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) -+#define MTK_ETH_MUX_GMAC2_TO_2P5GPHY \ -+ BIT_ULL(MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT) - #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ - BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) - #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ -@@ -986,6 +1102,7 @@ enum mkt_eth_capabilities { - #define MTK_ETH_PATH_GMAC1_SGMII BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT) - #define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT) - #define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT) -+#define MTK_ETH_PATH_GMAC2_2P5GPHY BIT_ULL(MTK_ETH_PATH_GMAC2_2P5GPHY_BIT) - #define MTK_ETH_PATH_GMAC2_GEPHY BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT) - #define MTK_ETH_PATH_GMAC3_SGMII BIT_ULL(MTK_ETH_PATH_GMAC3_SGMII_BIT) - #define MTK_ETH_PATH_GDM1_ESW BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT) -@@ -999,6 +1116,7 @@ enum mkt_eth_capabilities { - #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) - #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) - #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) -+#define MTK_GMAC2_2P5GPHY (MTK_ETH_PATH_GMAC2_2P5GPHY | MTK_2P5GPHY) - #define MTK_GMAC3_SGMII (MTK_ETH_PATH_GMAC3_SGMII | MTK_SGMII) - #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) - #define MTK_GMAC1_USXGMII (MTK_ETH_PATH_GMAC1_USXGMII | MTK_USXGMII) -@@ -1022,6 +1140,10 @@ enum mkt_eth_capabilities { - (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \ - MTK_SHARED_SGMII) - -+/* 2: GMAC2 -> XGMII */ -+#define MTK_MUX_GMAC2_TO_2P5GPHY \ -+ (MTK_ETH_MUX_GMAC2_TO_2P5GPHY | MTK_MUX | MTK_INFRA) -+ - /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */ - #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ - (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) -@@ -1080,7 +1202,8 @@ enum mkt_eth_capabilities { - MTK_MUX_GMAC123_TO_GEPHY_SGMII | \ - MTK_NETSYS_V3 | MTK_RSTCTRL_PPE1 | \ - MTK_GMAC1_USXGMII | MTK_GMAC2_USXGMII | \ -- MTK_GMAC3_USXGMII | MTK_MUX_GMAC123_TO_USXGMII) -+ MTK_GMAC3_USXGMII | MTK_MUX_GMAC123_TO_USXGMII | \ -+ MTK_GMAC2_2P5GPHY | MTK_MUX_GMAC2_TO_2P5GPHY) - - struct mtk_tx_dma_desc_info { - dma_addr_t addr; -@@ -1186,6 +1309,22 @@ struct mtk_soc_data { - - #define MTK_DMA_MONITOR_TIMEOUT msecs_to_jiffies(1000) - -+/* struct mtk_usxgmii_pcs - This structure holds each usxgmii regmap and -+ * associated data -+ * @regmap: The register map pointing at the range used to setup -+ * USXGMII modes -+ * @interface: Currently selected interface mode -+ * @id: The element is used to record the index of PCS -+ * @pcs: Phylink PCS structure -+ */ -+struct mtk_usxgmii_pcs { -+ struct mtk_eth *eth; -+ struct regmap *regmap; -+ phy_interface_t interface; -+ u8 id; -+ struct phylink_pcs pcs; -+}; -+ - /* struct mtk_eth - This is the main datasructure for holding the state - * of the driver - * @dev: The device pointer -@@ -1206,6 +1345,11 @@ struct mtk_soc_data { - * @infra: The register map pointing at the range used to setup - * SGMII and GePHY path - * @sgmii_pcs: Pointers to mtk-pcs-lynxi phylink_pcs instances -+ * @usxgmii_pll: The register map pointing at the range used to control -+ * the USXGMII SerDes PLL -+ * @regmap_pextp: The register map pointing at the range used to setup -+ * PHYA -+ * @usxgmii_pcs: Pointer to array of pointers to struct for USXGMII PCS - * @pctl: The register map pointing at the range used to setup - * GMAC port drive/slew values - * @dma_refcnt: track how many netdevs are using the DMA engine -@@ -1247,7 +1391,11 @@ struct mtk_eth { - unsigned long sysclk; - struct regmap *ethsys; - struct regmap *infra; -+ struct regmap *toprgu; - struct phylink_pcs **sgmii_pcs; -+ struct regmap *usxgmii_pll; -+ struct regmap **regmap_pextp; -+ struct mtk_usxgmii_pcs **usxgmii_pcs; - struct regmap *pctl; - bool hwlro; - refcount_t dma_refcnt; -@@ -1403,6 +1551,19 @@ static inline u32 mtk_get_ib2_multicast_ - return MTK_FOE_IB2_MULTICAST; - } - -+static inline bool mtk_interface_mode_is_xgmii(phy_interface_t interface) -+{ -+ switch (interface) { -+ case PHY_INTERFACE_MODE_USXGMII: -+ case PHY_INTERFACE_MODE_10GKR: -+ case PHY_INTERFACE_MODE_5GBASER: -+ return true; -+ break; -+ default: -+ return false; -+ } -+} -+ - /* read the hardware status register */ - void mtk_stats_update_mac(struct mtk_mac *mac); - -@@ -1410,8 +1571,10 @@ void mtk_w32(struct mtk_eth *eth, u32 va - u32 mtk_r32(struct mtk_eth *eth, unsigned reg); - - int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); -+int mtk_gmac_2p5gphy_path_setup(struct mtk_eth *eth, int mac_id); - int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); - int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); -+int mtk_gmac_usxgmii_path_setup(struct mtk_eth *eth, int mac_id); - - int mtk_eth_offload_init(struct mtk_eth *eth); - int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, -@@ -1421,5 +1584,20 @@ int mtk_flow_offload_cmd(struct mtk_eth - void mtk_flow_offload_cleanup(struct mtk_eth *eth, struct list_head *list); - void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev); - -+#ifdef CONFIG_NET_MEDIATEK_SOC_USXGMII -+struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int id); -+int mtk_usxgmii_init(struct mtk_eth *eth); -+int mtk_xfi_pll_enable(struct mtk_eth *eth); -+void mtk_sgmii_setup_phya_gen1(struct mtk_eth *eth, int mac_id); -+void mtk_sgmii_setup_phya_gen2(struct mtk_eth *eth, int mac_id); -+void mtk_sgmii_reset(struct mtk_eth *eth, int mac_id); -+#else -+static inline struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int id) { return NULL; } -+static inline int mtk_usxgmii_init(struct mtk_eth *eth) { return 0; } -+static inline int mtk_xfi_pll_enable(struct mtk_eth *eth) { return 0; } -+static inline void mtk_sgmii_setup_phya_gen1(struct mtk_eth *eth, int mac_id) { } -+static inline void mtk_sgmii_setup_phya_gen2(struct mtk_eth *eth, int mac_id) { } -+static inline void mtk_sgmii_reset(struct mtk_eth *eth, int mac_id) { } -+#endif /* NET_MEDIATEK_SOC_USXGMII */ - - #endif /* MTK_ETH_H */ ---- /dev/null -+++ b/drivers/net/ethernet/mediatek/mtk_usxgmii.c -@@ -0,0 +1,835 @@ -+/* SPDX-License-Identifier: GPL-2.0 -+ * -+ * Copyright (c) 2022 MediaTek Inc. -+ * Author: Henry Yen -+ * Daniel Golle -+ */ -+ -+#include -+#include -+#include -+#include "mtk_eth_soc.h" -+ -+static struct mtk_usxgmii_pcs *pcs_to_mtk_usxgmii_pcs(struct phylink_pcs *pcs) -+{ -+ return container_of(pcs, struct mtk_usxgmii_pcs, pcs); -+} -+ -+static int mtk_xfi_pextp_init(struct mtk_eth *eth) -+{ -+ struct device *dev = eth->dev; -+ struct device_node *r = dev->of_node; -+ struct device_node *np; -+ int i; -+ -+ eth->regmap_pextp = devm_kcalloc(dev, eth->soc->num_devs, sizeof(eth->regmap_pextp), GFP_KERNEL); -+ if (!eth->regmap_pextp) -+ return -ENOMEM; -+ -+ for (i = 0; i < eth->soc->num_devs; i++) { -+ np = of_parse_phandle(r, "mediatek,xfi_pextp", i); -+ if (!np) -+ break; -+ -+ eth->regmap_pextp[i] = syscon_node_to_regmap(np); -+ if (IS_ERR(eth->regmap_pextp[i])) -+ return PTR_ERR(eth->regmap_pextp[i]); -+ } -+ -+ return 0; -+} -+ -+static int mtk_xfi_pll_init(struct mtk_eth *eth) -+{ -+ struct device_node *r = eth->dev->of_node; -+ struct device_node *np; -+ -+ np = of_parse_phandle(r, "mediatek,xfi_pll", 0); -+ if (!np) -+ return -1; -+ -+ eth->usxgmii_pll = syscon_node_to_regmap(np); -+ if (IS_ERR(eth->usxgmii_pll)) -+ return PTR_ERR(eth->usxgmii_pll); -+ -+ return 0; -+} -+ -+static int mtk_toprgu_init(struct mtk_eth *eth) -+{ -+ struct device_node *r = eth->dev->of_node; -+ struct device_node *np; -+ -+ np = of_parse_phandle(r, "mediatek,toprgu", 0); -+ if (!np) -+ return -1; -+ -+ eth->toprgu = syscon_node_to_regmap(np); -+ if (IS_ERR(eth->toprgu)) -+ return PTR_ERR(eth->toprgu); -+ -+ return 0; -+} -+ -+int mtk_xfi_pll_enable(struct mtk_eth *eth) -+{ -+ u32 val = 0; -+ -+ if (!eth->usxgmii_pll) -+ return -EINVAL; -+ -+ /* Add software workaround for USXGMII PLL TCL issue */ -+ regmap_write(eth->usxgmii_pll, XFI_PLL_ANA_GLB8, RG_XFI_PLL_ANA_SWWA); -+ -+ regmap_read(eth->usxgmii_pll, XFI_PLL_DIG_GLB8, &val); -+ val |= RG_XFI_PLL_EN; -+ regmap_write(eth->usxgmii_pll, XFI_PLL_DIG_GLB8, val); -+ -+ return 0; -+} -+ -+static int mtk_mac2xgmii_id(struct mtk_eth *eth, int mac_id) -+{ -+ int xgmii_id = mac_id; -+ -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { -+ switch (mac_id) { -+ case MTK_GMAC1_ID: -+ case MTK_GMAC2_ID: -+ xgmii_id = 1; -+ break; -+ case MTK_GMAC3_ID: -+ xgmii_id = 0; -+ break; -+ default: -+ xgmii_id = -1; -+ } -+ } -+ -+ return xgmii_id; -+} -+ -+static int mtk_xgmii2mac_id(struct mtk_eth *eth, int xgmii_id) -+{ -+ int mac_id = xgmii_id; -+ -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { -+ switch (xgmii_id) { -+ case 0: -+ mac_id = 2; -+ break; -+ case 1: -+ mac_id = 1; -+ break; -+ default: -+ mac_id = -1; -+ } -+ } -+ -+ return mac_id; -+} -+ -+ -+static void mtk_usxgmii_setup_phya_usxgmii(struct mtk_usxgmii_pcs *mpcs) -+{ -+ struct regmap *pextp; -+ -+ if (!mpcs->eth) -+ return; -+ -+ pextp = mpcs->eth->regmap_pextp[mpcs->id]; -+ if (!pextp) -+ return; -+ -+ /* Setup operation mode */ -+ regmap_write(pextp, 0x9024, 0x00C9071C); -+ regmap_write(pextp, 0x2020, 0xAA8585AA); -+ regmap_write(pextp, 0x2030, 0x0C020707); -+ regmap_write(pextp, 0x2034, 0x0E050F0F); -+ regmap_write(pextp, 0x2040, 0x00140032); -+ regmap_write(pextp, 0x50F0, 0x00C014AA); -+ regmap_write(pextp, 0x50E0, 0x3777C12B); -+ regmap_write(pextp, 0x506C, 0x005F9CFF); -+ regmap_write(pextp, 0x5070, 0x9D9DFAFA); -+ regmap_write(pextp, 0x5074, 0x27273F3F); -+ regmap_write(pextp, 0x5078, 0xA7883C68); -+ regmap_write(pextp, 0x507C, 0x11661166); -+ regmap_write(pextp, 0x5080, 0x0E000AAF); -+ regmap_write(pextp, 0x5084, 0x08080D0D); -+ regmap_write(pextp, 0x5088, 0x02030909); -+ regmap_write(pextp, 0x50E4, 0x0C0C0000); -+ regmap_write(pextp, 0x50E8, 0x04040000); -+ regmap_write(pextp, 0x50EC, 0x0F0F0C06); -+ regmap_write(pextp, 0x50A8, 0x506E8C8C); -+ regmap_write(pextp, 0x6004, 0x18190000); -+ regmap_write(pextp, 0x00F8, 0x01423342); -+ /* Force SGDT_OUT off and select PCS */ -+ regmap_write(pextp, 0x00F4, 0x80201F20); -+ /* Force GLB_CKDET_OUT */ -+ regmap_write(pextp, 0x0030, 0x00050C00); -+ /* Force AEQ on */ -+ regmap_write(pextp, 0x0070, 0x02002800); -+ ndelay(1020); -+ /* Setup DA default value */ -+ regmap_write(pextp, 0x30B0, 0x00000020); -+ regmap_write(pextp, 0x3028, 0x00008A01); -+ regmap_write(pextp, 0x302C, 0x0000A884); -+ regmap_write(pextp, 0x3024, 0x00083002); -+ regmap_write(pextp, 0x3010, 0x00022220); -+ regmap_write(pextp, 0x5064, 0x0F020A01); -+ regmap_write(pextp, 0x50B4, 0x06100600); -+ regmap_write(pextp, 0x3048, 0x40704000); -+ regmap_write(pextp, 0x3050, 0xA8000000); -+ regmap_write(pextp, 0x3054, 0x000000AA); -+ regmap_write(pextp, 0x306C, 0x00000F00); -+ regmap_write(pextp, 0xA060, 0x00040000); -+ regmap_write(pextp, 0x90D0, 0x00000001); -+ /* Release reset */ -+ regmap_write(pextp, 0x0070, 0x0200E800); -+ udelay(150); -+ /* Switch to P0 */ -+ regmap_write(pextp, 0x0070, 0x0200C111); -+ ndelay(1020); -+ regmap_write(pextp, 0x0070, 0x0200C101); -+ udelay(15); -+ /* Switch to Gen3 */ -+ regmap_write(pextp, 0x0070, 0x0202C111); -+ ndelay(1020); -+ regmap_write(pextp, 0x0070, 0x0202C101); -+ udelay(100); -+ regmap_write(pextp, 0x30B0, 0x00000030); -+ regmap_write(pextp, 0x00F4, 0x80201F00); -+ regmap_write(pextp, 0x3040, 0x30000000); -+ udelay(400); -+} -+ -+static void mtk_usxgmii_setup_phya_5gbaser(struct mtk_usxgmii_pcs *mpcs) -+{ -+ struct regmap *pextp; -+ -+ if (!mpcs->eth) -+ return; -+ -+ pextp = mpcs->eth->regmap_pextp[mpcs->id]; -+ if (!pextp) -+ return; -+ -+ /* Setup operation mode */ -+ regmap_write(pextp, 0x9024, 0x00D9071C); -+ regmap_write(pextp, 0x2020, 0xAAA5A5AA); -+ regmap_write(pextp, 0x2030, 0x0C020707); -+ regmap_write(pextp, 0x2034, 0x0E050F0F); -+ regmap_write(pextp, 0x2040, 0x00140032); -+ regmap_write(pextp, 0x50F0, 0x00C018AA); -+ regmap_write(pextp, 0x50E0, 0x3777812B); -+ regmap_write(pextp, 0x506C, 0x005C9CFF); -+ regmap_write(pextp, 0x5070, 0x9DFAFAFA); -+ regmap_write(pextp, 0x5074, 0x273F3F3F); -+ regmap_write(pextp, 0x5078, 0xA8883868); -+ regmap_write(pextp, 0x507C, 0x14661466); -+ regmap_write(pextp, 0x5080, 0x0E001ABF); -+ regmap_write(pextp, 0x5084, 0x080B0D0D); -+ regmap_write(pextp, 0x5088, 0x02050909); -+ regmap_write(pextp, 0x50E4, 0x0C000000); -+ regmap_write(pextp, 0x50E8, 0x04000000); -+ regmap_write(pextp, 0x50EC, 0x0F0F0C06); -+ regmap_write(pextp, 0x50A8, 0x50808C8C); -+ regmap_write(pextp, 0x6004, 0x18000000); -+ regmap_write(pextp, 0x00F8, 0x00A132A1); -+ /* Force SGDT_OUT off and select PCS */ -+ regmap_write(pextp, 0x00F4, 0x80201F20); -+ /* Force GLB_CKDET_OUT */ -+ regmap_write(pextp, 0x0030, 0x00050C00); -+ /* Force AEQ on */ -+ regmap_write(pextp, 0x0070, 0x02002800); -+ ndelay(1020); -+ /* Setup DA default value */ -+ regmap_write(pextp, 0x30B0, 0x00000020); -+ regmap_write(pextp, 0x3028, 0x00008A01); -+ regmap_write(pextp, 0x302C, 0x0000A884); -+ regmap_write(pextp, 0x3024, 0x00083002); -+ regmap_write(pextp, 0x3010, 0x00022220); -+ regmap_write(pextp, 0x5064, 0x0F020A01); -+ regmap_write(pextp, 0x50B4, 0x06100600); -+ regmap_write(pextp, 0x3048, 0x40704000); -+ regmap_write(pextp, 0x3050, 0xA8000000); -+ regmap_write(pextp, 0x3054, 0x000000AA); -+ regmap_write(pextp, 0x306C, 0x00000F00); -+ regmap_write(pextp, 0xA060, 0x00040000); -+ regmap_write(pextp, 0x90D0, 0x00000003); -+ /* Release reset */ -+ regmap_write(pextp, 0x0070, 0x0200E800); -+ udelay(150); -+ /* Switch to P0 */ -+ regmap_write(pextp, 0x0070, 0x0200C111); -+ ndelay(1020); -+ regmap_write(pextp, 0x0070, 0x0200C101); -+ udelay(15); -+ /* Switch to Gen3 */ -+ regmap_write(pextp, 0x0070, 0x0202C111); -+ ndelay(1020); -+ regmap_write(pextp, 0x0070, 0x0202C101); -+ udelay(100); -+ regmap_write(pextp, 0x30B0, 0x00000030); -+ regmap_write(pextp, 0x00F4, 0x80201F00); -+ regmap_write(pextp, 0x3040, 0x30000000); -+ udelay(400); -+} -+ -+static void mtk_usxgmii_setup_phya_10gbaser(struct mtk_usxgmii_pcs *mpcs) -+{ -+ struct regmap *pextp; -+ -+ if (!mpcs->eth) -+ return; -+ -+ pextp = mpcs->eth->regmap_pextp[mpcs->id]; -+ if (!pextp) -+ return; -+ -+ /* Setup operation mode */ -+ regmap_write(pextp, 0x9024, 0x00C9071C); -+ regmap_write(pextp, 0x2020, 0xAA8585AA); -+ regmap_write(pextp, 0x2030, 0x0C020707); -+ regmap_write(pextp, 0x2034, 0x0E050F0F); -+ regmap_write(pextp, 0x2040, 0x00140032); -+ regmap_write(pextp, 0x50F0, 0x00C014AA); -+ regmap_write(pextp, 0x50E0, 0x3777C12B); -+ regmap_write(pextp, 0x506C, 0x005F9CFF); -+ regmap_write(pextp, 0x5070, 0x9D9DFAFA); -+ regmap_write(pextp, 0x5074, 0x27273F3F); -+ regmap_write(pextp, 0x5078, 0xA7883C68); -+ regmap_write(pextp, 0x507C, 0x11661166); -+ regmap_write(pextp, 0x5080, 0x0E000AAF); -+ regmap_write(pextp, 0x5084, 0x08080D0D); -+ regmap_write(pextp, 0x5088, 0x02030909); -+ regmap_write(pextp, 0x50E4, 0x0C0C0000); -+ regmap_write(pextp, 0x50E8, 0x04040000); -+ regmap_write(pextp, 0x50EC, 0x0F0F0C06); -+ regmap_write(pextp, 0x50A8, 0x506E8C8C); -+ regmap_write(pextp, 0x6004, 0x18190000); -+ regmap_write(pextp, 0x00F8, 0x01423342); -+ /* Force SGDT_OUT off and select PCS */ -+ regmap_write(pextp, 0x00F4, 0x80201F20); -+ /* Force GLB_CKDET_OUT */ -+ regmap_write(pextp, 0x0030, 0x00050C00); -+ /* Force AEQ on */ -+ regmap_write(pextp, 0x0070, 0x02002800); -+ ndelay(1020); -+ /* Setup DA default value */ -+ regmap_write(pextp, 0x30B0, 0x00000020); -+ regmap_write(pextp, 0x3028, 0x00008A01); -+ regmap_write(pextp, 0x302C, 0x0000A884); -+ regmap_write(pextp, 0x3024, 0x00083002); -+ regmap_write(pextp, 0x3010, 0x00022220); -+ regmap_write(pextp, 0x5064, 0x0F020A01); -+ regmap_write(pextp, 0x50B4, 0x06100600); -+ regmap_write(pextp, 0x3048, 0x47684100); -+ regmap_write(pextp, 0x3050, 0x00000000); -+ regmap_write(pextp, 0x3054, 0x00000000); -+ regmap_write(pextp, 0x306C, 0x00000F00); -+ if (mpcs->id == 0) -+ regmap_write(pextp, 0xA008, 0x0007B400); -+ -+ regmap_write(pextp, 0xA060, 0x00040000); -+ regmap_write(pextp, 0x90D0, 0x00000001); -+ /* Release reset */ -+ regmap_write(pextp, 0x0070, 0x0200E800); -+ udelay(150); -+ /* Switch to P0 */ -+ regmap_write(pextp, 0x0070, 0x0200C111); -+ ndelay(1020); -+ regmap_write(pextp, 0x0070, 0x0200C101); -+ udelay(15); -+ /* Switch to Gen3 */ -+ regmap_write(pextp, 0x0070, 0x0202C111); -+ ndelay(1020); -+ regmap_write(pextp, 0x0070, 0x0202C101); -+ udelay(100); -+ regmap_write(pextp, 0x30B0, 0x00000030); -+ regmap_write(pextp, 0x00F4, 0x80201F00); -+ regmap_write(pextp, 0x3040, 0x30000000); -+ udelay(400); -+} -+ -+void mtk_sgmii_setup_phya_gen1(struct mtk_eth *eth, int mac_id) -+{ -+ u32 id = mtk_mac2xgmii_id(eth, mac_id); -+ struct regmap *pextp; -+ -+ if (id >= eth->soc->num_devs) -+ return; -+ -+ pextp = eth->regmap_pextp[id]; -+ if (!pextp) -+ return; -+ -+ /* Setup operation mode */ -+ regmap_write(pextp, 0x9024, 0x00D9071C); -+ regmap_write(pextp, 0x2020, 0xAA8585AA); -+ regmap_write(pextp, 0x2030, 0x0C020207); -+ regmap_write(pextp, 0x2034, 0x0E05050F); -+ regmap_write(pextp, 0x2040, 0x00200032); -+ regmap_write(pextp, 0x50F0, 0x00C014BA); -+ regmap_write(pextp, 0x50E0, 0x3777C12B); -+ regmap_write(pextp, 0x506C, 0x005F9CFF); -+ regmap_write(pextp, 0x5070, 0x9D9DFAFA); -+ regmap_write(pextp, 0x5074, 0x27273F3F); -+ regmap_write(pextp, 0x5078, 0xA7883C68); -+ regmap_write(pextp, 0x507C, 0x11661166); -+ regmap_write(pextp, 0x5080, 0x0E000EAF); -+ regmap_write(pextp, 0x5084, 0x08080E0D); -+ regmap_write(pextp, 0x5088, 0x02030B09); -+ regmap_write(pextp, 0x50E4, 0x0C0C0000); -+ regmap_write(pextp, 0x50E8, 0x04040000); -+ regmap_write(pextp, 0x50EC, 0x0F0F0606); -+ regmap_write(pextp, 0x50A8, 0x506E8C8C); -+ regmap_write(pextp, 0x6004, 0x18190000); -+ regmap_write(pextp, 0x00F8, 0x00FA32FA); -+ /* Force SGDT_OUT off and select PCS */ -+ regmap_write(pextp, 0x00F4, 0x80201F21); -+ /* Force GLB_CKDET_OUT */ -+ regmap_write(pextp, 0x0030, 0x00050C00); -+ /* Force AEQ on */ -+ regmap_write(pextp, 0x0070, 0x02002800); -+ ndelay(1020); -+ /* Setup DA default value */ -+ regmap_write(pextp, 0x30B0, 0x00000020); -+ regmap_write(pextp, 0x3028, 0x00008A01); -+ regmap_write(pextp, 0x302C, 0x0000A884); -+ regmap_write(pextp, 0x3024, 0x00083002); -+ regmap_write(pextp, 0x3010, 0x00011110); -+ regmap_write(pextp, 0x3048, 0x40704000); -+ regmap_write(pextp, 0x3064, 0x0000C000); -+ regmap_write(pextp, 0x3050, 0xA8000000); -+ regmap_write(pextp, 0x3054, 0x000000AA); -+ regmap_write(pextp, 0x306C, 0x20200F00); -+ regmap_write(pextp, 0xA060, 0x00050000); -+ regmap_write(pextp, 0x90D0, 0x00000007); -+ /* Release reset */ -+ regmap_write(pextp, 0x0070, 0x0200E800); -+ udelay(150); -+ /* Switch to P0 */ -+ regmap_write(pextp, 0x0070, 0x0200C111); -+ ndelay(1020); -+ regmap_write(pextp, 0x0070, 0x0200C101); -+ udelay(15); -+ /* Switch to Gen2 */ -+ regmap_write(pextp, 0x0070, 0x0201C111); -+ ndelay(1020); -+ regmap_write(pextp, 0x0070, 0x0201C101); -+ udelay(100); -+ regmap_write(pextp, 0x30B0, 0x00000030); -+ regmap_write(pextp, 0x00F4, 0x80201F01); -+ regmap_write(pextp, 0x3040, 0x30000000); -+ udelay(400); -+} -+ -+void mtk_sgmii_setup_phya_gen2(struct mtk_eth *eth, int mac_id) -+{ -+ u32 id = mtk_mac2xgmii_id(eth, mac_id); -+ struct regmap *pextp; -+ -+ if (id >= eth->soc->num_devs) -+ return; -+ -+ pextp = eth->regmap_pextp[id]; -+ if (!pextp) -+ return; -+ -+ /* Setup operation mode */ -+ regmap_write(pextp, 0x9024, 0x00D9071C); -+ regmap_write(pextp, 0x2020, 0xAA8585AA); -+ regmap_write(pextp, 0x2030, 0x0C020707); -+ regmap_write(pextp, 0x2034, 0x0E050F0F); -+ regmap_write(pextp, 0x2040, 0x00140032); -+ regmap_write(pextp, 0x50F0, 0x00C014AA); -+ regmap_write(pextp, 0x50E0, 0x3777C12B); -+ regmap_write(pextp, 0x506C, 0x005F9CFF); -+ regmap_write(pextp, 0x5070, 0x9D9DFAFA); -+ regmap_write(pextp, 0x5074, 0x27273F3F); -+ regmap_write(pextp, 0x5078, 0xA7883C68); -+ regmap_write(pextp, 0x507C, 0x11661166); -+ regmap_write(pextp, 0x5080, 0x0E000AAF); -+ regmap_write(pextp, 0x5084, 0x08080D0D); -+ regmap_write(pextp, 0x5088, 0x02030909); -+ regmap_write(pextp, 0x50E4, 0x0C0C0000); -+ regmap_write(pextp, 0x50E8, 0x04040000); -+ regmap_write(pextp, 0x50EC, 0x0F0F0C06); -+ regmap_write(pextp, 0x50A8, 0x506E8C8C); -+ regmap_write(pextp, 0x6004, 0x18190000); -+ regmap_write(pextp, 0x00F8, 0x009C329C); -+ /* Force SGDT_OUT off and select PCS */ -+ regmap_write(pextp, 0x00F4, 0x80201F21); -+ /* Force GLB_CKDET_OUT */ -+ regmap_write(pextp, 0x0030, 0x00050C00); -+ /* Force AEQ on */ -+ regmap_write(pextp, 0x0070, 0x02002800); -+ ndelay(1020); -+ /* Setup DA default value */ -+ regmap_write(pextp, 0x30B0, 0x00000020); -+ regmap_write(pextp, 0x3028, 0x00008A01); -+ regmap_write(pextp, 0x302C, 0x0000A884); -+ regmap_write(pextp, 0x3024, 0x00083002); -+ regmap_write(pextp, 0x3010, 0x00011110); -+ regmap_write(pextp, 0x3048, 0x40704000); -+ regmap_write(pextp, 0x3050, 0xA8000000); -+ regmap_write(pextp, 0x3054, 0x000000AA); -+ regmap_write(pextp, 0x306C, 0x22000F00); -+ regmap_write(pextp, 0xA060, 0x00050000); -+ regmap_write(pextp, 0x90D0, 0x00000005); -+ /* Release reset */ -+ regmap_write(pextp, 0x0070, 0x0200E800); -+ udelay(150); -+ /* Switch to P0 */ -+ regmap_write(pextp, 0x0070, 0x0200C111); -+ ndelay(1020); -+ regmap_write(pextp, 0x0070, 0x0200C101); -+ udelay(15); -+ /* Switch to Gen2 */ -+ regmap_write(pextp, 0x0070, 0x0201C111); -+ ndelay(1020); -+ regmap_write(pextp, 0x0070, 0x0201C101); -+ udelay(100); -+ regmap_write(pextp, 0x30B0, 0x00000030); -+ regmap_write(pextp, 0x00F4, 0x80201F01); -+ regmap_write(pextp, 0x3040, 0x30000000); -+ udelay(400); -+} -+ -+static void mtk_usxgmii_reset(struct mtk_eth *eth, int id) -+{ -+ u32 val = 0; -+ -+ if (id >= eth->soc->num_devs || !eth->toprgu) -+ return; -+ -+ switch (id) { -+ case 0: -+ /* Enable software reset */ -+ regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val); -+ val |= SWSYSRST_XFI_PEXPT0_GRST | -+ SWSYSRST_XFI0_GRST; -+ regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val); -+ -+ /* Assert USXGMII reset */ -+ regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val); -+ val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88) | -+ SWSYSRST_XFI_PEXPT0_GRST | -+ SWSYSRST_XFI0_GRST; -+ regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val); -+ -+ udelay(100); -+ -+ /* De-assert USXGMII reset */ -+ regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val); -+ val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88); -+ val &= ~(SWSYSRST_XFI_PEXPT0_GRST | -+ SWSYSRST_XFI0_GRST); -+ regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val); -+ -+ /* Disable software reset */ -+ regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val); -+ val &= ~(SWSYSRST_XFI_PEXPT0_GRST | -+ SWSYSRST_XFI0_GRST); -+ regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val); -+ break; -+ case 1: -+ /* Enable software reset */ -+ regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val); -+ val |= SWSYSRST_XFI_PEXPT1_GRST | -+ SWSYSRST_XFI1_GRST; -+ regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val); -+ -+ /* Assert USXGMII reset */ -+ regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val); -+ val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88) | -+ SWSYSRST_XFI_PEXPT1_GRST | -+ SWSYSRST_XFI1_GRST; -+ regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val); -+ -+ udelay(100); -+ -+ /* De-assert USXGMII reset */ -+ regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val); -+ val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88); -+ val &= ~(SWSYSRST_XFI_PEXPT1_GRST | -+ SWSYSRST_XFI1_GRST); -+ regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val); -+ -+ /* Disable software reset */ -+ regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val); -+ val &= ~(SWSYSRST_XFI_PEXPT1_GRST | -+ SWSYSRST_XFI1_GRST); -+ regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val); -+ break; -+ } -+ -+ mdelay(10); -+} -+ -+void mtk_sgmii_reset(struct mtk_eth *eth, int mac_id) -+{ -+ u32 xgmii_id = mtk_mac2xgmii_id(eth, mac_id); -+ -+ mtk_usxgmii_reset(eth, xgmii_id); -+} -+ -+ -+static int mtk_usxgmii_pcs_config(struct phylink_pcs *pcs, unsigned int mode, -+ phy_interface_t interface, -+ const unsigned long *advertising, -+ bool permit_pause_to_mac) -+{ -+ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs); -+ struct mtk_eth *eth = mpcs->eth; -+ unsigned int an_ctrl = 0, link_timer = 0, xfi_mode = 0, adapt_mode = 0; -+ bool mode_changed = false; -+ -+ if (interface == PHY_INTERFACE_MODE_USXGMII) { -+ an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF) | -+ USXGMII_AN_ENABLE; -+ link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) | -+ FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) | -+ FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B); -+ xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_10G) | -+ FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_10G); -+ } else if (interface == PHY_INTERFACE_MODE_10GKR) { -+ an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF); -+ link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) | -+ FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) | -+ FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B); -+ xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_10G) | -+ FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_10G); -+ adapt_mode = USXGMII_RATE_UPDATE_MODE; -+ } else if (interface == PHY_INTERFACE_MODE_5GBASER) { -+ an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0xFF); -+ link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x3D) | -+ FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x3D) | -+ FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x3D); -+ xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_5G) | -+ FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_5G); -+ adapt_mode = USXGMII_RATE_UPDATE_MODE; -+ } else -+ return -EINVAL; -+ -+ adapt_mode |= FIELD_PREP(USXGMII_RATE_ADAPT_MODE, USXGMII_RATE_ADAPT_MODE_X1); -+ -+ if (mpcs->interface != interface) { -+ mpcs->interface = interface; -+ mode_changed = true; -+ } -+ -+ mtk_xfi_pll_enable(eth); -+ mtk_usxgmii_reset(eth, mpcs->id); -+ -+ /* Setup USXGMII AN ctrl */ -+ regmap_update_bits(mpcs->regmap, RG_PCS_AN_CTRL0, -+ USXGMII_AN_SYNC_CNT | USXGMII_AN_ENABLE, -+ an_ctrl); -+ -+ regmap_update_bits(mpcs->regmap, RG_PCS_AN_CTRL2, -+ USXGMII_LINK_TIMER_IDLE_DETECT | -+ USXGMII_LINK_TIMER_COMP_ACK_DETECT | -+ USXGMII_LINK_TIMER_AN_RESTART, -+ link_timer); -+ -+ /* Gated MAC CK */ -+ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, -+ USXGMII_MAC_CK_GATED, USXGMII_MAC_CK_GATED); -+ -+ /* Enable interface force mode */ -+ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, -+ USXGMII_IF_FORCE_EN, USXGMII_IF_FORCE_EN); -+ -+ /* Setup USXGMII adapt mode */ -+ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, -+ USXGMII_RATE_UPDATE_MODE | USXGMII_RATE_ADAPT_MODE, -+ adapt_mode); -+ -+ /* Setup USXGMII speed */ -+ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, -+ USXGMII_XFI_RX_MODE | USXGMII_XFI_TX_MODE, -+ xfi_mode); -+ -+ udelay(1); -+ -+ /* Un-gated MAC CK */ -+ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, -+ USXGMII_MAC_CK_GATED, 0); -+ -+ udelay(1); -+ -+ /* Disable interface force mode for the AN mode */ -+ if (an_ctrl & USXGMII_AN_ENABLE) -+ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, -+ USXGMII_IF_FORCE_EN, 0); -+ -+ /* Setup USXGMIISYS with the determined property */ -+ if (interface == PHY_INTERFACE_MODE_USXGMII) -+ mtk_usxgmii_setup_phya_usxgmii(mpcs); -+ else if (interface == PHY_INTERFACE_MODE_10GKR) -+ mtk_usxgmii_setup_phya_10gbaser(mpcs); -+ else if (interface == PHY_INTERFACE_MODE_5GBASER) -+ mtk_usxgmii_setup_phya_5gbaser(mpcs); -+ -+ return mode_changed; -+} -+ -+static void mtk_usxgmii_pcs_get_state(struct phylink_pcs *pcs, -+ struct phylink_link_state *state) -+{ -+ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs); -+ struct mtk_eth *eth = mpcs->eth; -+ struct mtk_mac *mac = eth->mac[mtk_xgmii2mac_id(eth, mpcs->id)]; -+ u32 val = 0; -+ -+ regmap_read(mpcs->regmap, RG_PCS_AN_CTRL0, &val); -+ if (FIELD_GET(USXGMII_AN_ENABLE, val)) { -+ /* Refresh LPA by inverting LPA_LATCH */ -+ regmap_read(mpcs->regmap, RG_PCS_AN_STS0, &val); -+ regmap_update_bits(mpcs->regmap, RG_PCS_AN_STS0, -+ USXGMII_LPA_LATCH, -+ !(val & USXGMII_LPA_LATCH)); -+ -+ regmap_read(mpcs->regmap, RG_PCS_AN_STS0, &val); -+ -+ state->interface = mpcs->interface; -+ state->link = FIELD_GET(USXGMII_LPA_LINK, val); -+ state->duplex = FIELD_GET(USXGMII_LPA_DUPLEX, val); -+ -+ switch (FIELD_GET(USXGMII_LPA_SPEED_MASK, val)) { -+ case USXGMII_LPA_SPEED_10: -+ state->speed = SPEED_10; -+ break; -+ case USXGMII_LPA_SPEED_100: -+ state->speed = SPEED_100; -+ break; -+ case USXGMII_LPA_SPEED_1000: -+ state->speed = SPEED_1000; -+ break; -+ case USXGMII_LPA_SPEED_2500: -+ state->speed = SPEED_2500; -+ break; -+ case USXGMII_LPA_SPEED_5000: -+ state->speed = SPEED_5000; -+ break; -+ case USXGMII_LPA_SPEED_10000: -+ state->speed = SPEED_10000; -+ break; -+ } -+ } else { -+ val = mtk_r32(mac->hw, MTK_XGMAC_STS(mac->id)); -+ -+ if (mac->id == MTK_GMAC2_ID) -+ val = val >> 16; -+ -+ switch (FIELD_GET(MTK_USXGMII_PCS_MODE, val)) { -+ case 0: -+ state->speed = SPEED_10000; -+ break; -+ case 1: -+ state->speed = SPEED_5000; -+ break; -+ case 2: -+ state->speed = SPEED_2500; -+ break; -+ case 3: -+ state->speed = SPEED_1000; -+ break; -+ } -+ -+ state->interface = mpcs->interface; -+ state->link = FIELD_GET(MTK_USXGMII_PCS_LINK, val); -+ state->duplex = DUPLEX_FULL; -+ } -+ -+ if (state->link == 0) -+ mtk_usxgmii_pcs_config(pcs, MLO_AN_INBAND, -+ state->interface, NULL, false); -+} -+ -+static void mtk_usxgmii_pcs_restart_an(struct phylink_pcs *pcs) -+{ -+ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs); -+ unsigned int val = 0; -+ -+ if (!mpcs->regmap) -+ return; -+ -+ regmap_read(mpcs->regmap, RG_PCS_AN_CTRL0, &val); -+ val |= USXGMII_AN_RESTART; -+ regmap_write(mpcs->regmap, RG_PCS_AN_CTRL0, val); -+} -+ -+static void mtk_usxgmii_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode, -+ phy_interface_t interface, -+ int speed, int duplex) -+{ -+ /* Reconfiguring USXGMII to ensure the quality of the RX signal -+ * after the line side link up. -+ */ -+ mtk_usxgmii_pcs_config(pcs, mode, -+ interface, NULL, false); -+} -+ -+static const struct phylink_pcs_ops mtk_usxgmii_pcs_ops = { -+ .pcs_config = mtk_usxgmii_pcs_config, -+ .pcs_get_state = mtk_usxgmii_pcs_get_state, -+ .pcs_an_restart = mtk_usxgmii_pcs_restart_an, -+ .pcs_link_up = mtk_usxgmii_pcs_link_up, -+}; -+ -+int mtk_usxgmii_init(struct mtk_eth *eth) -+{ -+ struct device_node *r = eth->dev->of_node; -+ struct device *dev = eth->dev; -+ struct device_node *np; -+ int i, ret; -+ -+ eth->usxgmii_pcs = devm_kcalloc(dev, eth->soc->num_devs, sizeof(eth->usxgmii_pcs), GFP_KERNEL); -+ if (!eth->usxgmii_pcs) -+ return -ENOMEM; -+ -+ for (i = 0; i < eth->soc->num_devs; i++) { -+ np = of_parse_phandle(r, "mediatek,usxgmiisys", i); -+ if (!np) -+ break; -+ -+ eth->usxgmii_pcs[i] = devm_kzalloc(dev, sizeof(*eth->usxgmii_pcs), GFP_KERNEL); -+ if (!eth->usxgmii_pcs[i]) -+ return -ENOMEM; -+ -+ eth->usxgmii_pcs[i]->id = i; -+ eth->usxgmii_pcs[i]->eth = eth; -+ eth->usxgmii_pcs[i]->regmap = syscon_node_to_regmap(np); -+ if (IS_ERR(eth->usxgmii_pcs[i]->regmap)) -+ return PTR_ERR(eth->usxgmii_pcs[i]->regmap); -+ -+ eth->usxgmii_pcs[i]->pcs.ops = &mtk_usxgmii_pcs_ops; -+ eth->usxgmii_pcs[i]->pcs.poll = true; -+ eth->usxgmii_pcs[i]->interface = PHY_INTERFACE_MODE_NA; -+ -+ of_node_put(np); -+ } -+ -+ ret = mtk_xfi_pextp_init(eth); -+ if (ret) -+ return ret; -+ -+ ret = mtk_xfi_pll_init(eth); -+ if (ret) -+ return ret; -+ -+ return mtk_toprgu_init(eth); -+} -+ -+struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int mac_id) -+{ -+ u32 xgmii_id = mtk_mac2xgmii_id(eth, mac_id); -+ -+ if (!eth->usxgmii_pcs[xgmii_id]->regmap) -+ return NULL; -+ -+ return ð->usxgmii_pcs[xgmii_id]->pcs; -+} diff --git a/target/linux/generic/pending-6.1/737-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch b/target/linux/generic/pending-6.1/737-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch new file mode 100644 index 00000000000..4a9b0889982 --- /dev/null +++ b/target/linux/generic/pending-6.1/737-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch @@ -0,0 +1,1604 @@ +From 1e25ca1147579bda8b941be1b9851f5911d44eb0 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Tue, 22 Aug 2023 19:04:42 +0100 +Subject: [PATCH 098/125] net: ethernet: mtk_eth_soc: add paths and SerDes + modes for MT7988 + +MT7988 comes with a built-in 2.5G PHY as well as SerDes lanes to +connect external PHYs or transceivers in USXGMII, 10GBase-R, 5GBase-R, +2500Base-X, 1000Base-X and Cisco SGMII interface modes. + +Implement support for configuring for the new paths to SerDes interfaces +and the internal 2.5G PHY. + +Add USXGMII PCS driver for 10GBase-R, 5GBase-R and USXGMII mode, and +setup the new PHYA on MT7988 to access the also still existing old +LynxI PCS for 1000Base-X, 2500Base-X and Cisco SGMII PCS interface +modes. + +Signed-off-by: Daniel Golle +--- + drivers/net/ethernet/mediatek/Kconfig | 16 + + drivers/net/ethernet/mediatek/Makefile | 1 + + drivers/net/ethernet/mediatek/mtk_eth_path.c | 123 +++- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 182 ++++- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 232 ++++++- + drivers/net/ethernet/mediatek/mtk_usxgmii.c | 692 +++++++++++++++++++ + 6 files changed, 1215 insertions(+), 31 deletions(-) + create mode 100644 drivers/net/ethernet/mediatek/mtk_usxgmii.c + +--- a/drivers/net/ethernet/mediatek/Kconfig ++++ b/drivers/net/ethernet/mediatek/Kconfig +@@ -25,6 +25,22 @@ config NET_MEDIATEK_SOC + This driver supports the gigabit ethernet MACs in the + MediaTek SoC family. + ++config NET_MEDIATEK_SOC_USXGMII ++ bool "Support USXGMII SerDes on MT7988" ++ depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST ++ def_bool NET_MEDIATEK_SOC != n ++ help ++ Include support for 10GE SerDes which can be found on MT7988. ++ If this kernel should run on SoCs with 10 GBit/s Ethernet you ++ will need to select this option to use GMAC2 and GMAC3 with ++ external PHYs, SFP(+) cages in 10GBase-R, 5GBase-R or USXGMII ++ interface modes. ++ ++ Note that as the 2500Base-X/1000Base-X/Cisco SGMII SerDes PCS ++ unit (MediaTek LynxI) in MT7988 is connected via the new 10GE ++ SerDes, you will also need to select this option in case you ++ want to use any of those SerDes modes. ++ + config NET_MEDIATEK_STAR_EMAC + tristate "MediaTek STAR Ethernet MAC support" + select PHYLIB +--- a/drivers/net/ethernet/mediatek/Makefile ++++ b/drivers/net/ethernet/mediatek/Makefile +@@ -5,6 +5,7 @@ + + obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o + mtk_eth-y := mtk_eth_soc.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o ++mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_USXGMII) += mtk_usxgmii.o + mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o mtk_wed_mcu.o mtk_wed_wo.o + ifdef CONFIG_DEBUG_FS + mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_debugfs.o +--- a/drivers/net/ethernet/mediatek/mtk_eth_path.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c +@@ -31,10 +31,20 @@ static const char *mtk_eth_path_name(u64 + return "gmac2_rgmii"; + case MTK_ETH_PATH_GMAC2_SGMII: + return "gmac2_sgmii"; ++ case MTK_ETH_PATH_GMAC2_2P5GPHY: ++ return "gmac2_2p5gphy"; + case MTK_ETH_PATH_GMAC2_GEPHY: + return "gmac2_gephy"; ++ case MTK_ETH_PATH_GMAC3_SGMII: ++ return "gmac3_sgmii"; + case MTK_ETH_PATH_GDM1_ESW: + return "gdm1_esw"; ++ case MTK_ETH_PATH_GMAC1_USXGMII: ++ return "gmac1_usxgmii"; ++ case MTK_ETH_PATH_GMAC2_USXGMII: ++ return "gmac2_usxgmii"; ++ case MTK_ETH_PATH_GMAC3_USXGMII: ++ return "gmac3_usxgmii"; + default: + return "unknown path"; + } +@@ -127,6 +137,27 @@ static int set_mux_u3_gmac2_to_qphy(stru + return 0; + } + ++static int set_mux_gmac2_to_2p5gphy(struct mtk_eth *eth, u64 path) ++{ ++ int ret; ++ ++ if (path == MTK_ETH_PATH_GMAC2_2P5GPHY) { ++ ret = regmap_clear_bits(eth->ethsys, ETHSYS_SYSCFG0, SYSCFG0_SGMII_GMAC2_V2); ++ if (ret) ++ return ret; ++ ++ /* Setup mux to 2p5g PHY */ ++ ret = regmap_clear_bits(eth->infra, TOP_MISC_NETSYS_PCS_MUX, MUX_G2_USXGMII_SEL); ++ if (ret) ++ return ret; ++ ++ dev_dbg(eth->dev, "path %s in %s updated\n", ++ mtk_eth_path_name(path), __func__); ++ } ++ ++ return 0; ++} ++ + static int set_mux_gmac1_gmac2_to_sgmii_rgmii(struct mtk_eth *eth, u64 path) + { + unsigned int val = 0; +@@ -165,7 +196,48 @@ static int set_mux_gmac1_gmac2_to_sgmii_ + return 0; + } + +-static int set_mux_gmac12_to_gephy_sgmii(struct mtk_eth *eth, u64 path) ++static int set_mux_gmac123_to_usxgmii(struct mtk_eth *eth, u64 path) ++{ ++ unsigned int val = 0; ++ bool updated = true; ++ int mac_id = 0; ++ ++ /* Disable SYSCFG1 SGMII */ ++ regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); ++ ++ switch (path) { ++ case MTK_ETH_PATH_GMAC1_USXGMII: ++ val &= ~(u32)SYSCFG0_SGMII_GMAC1_V2; ++ mac_id = MTK_GMAC1_ID; ++ break; ++ case MTK_ETH_PATH_GMAC2_USXGMII: ++ val &= ~(u32)SYSCFG0_SGMII_GMAC2_V2; ++ mac_id = MTK_GMAC2_ID; ++ break; ++ case MTK_ETH_PATH_GMAC3_USXGMII: ++ val &= ~(u32)SYSCFG0_SGMII_GMAC3_V2; ++ mac_id = MTK_GMAC3_ID; ++ break; ++ default: ++ updated = false; ++ }; ++ ++ if (updated) { ++ regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, ++ SYSCFG0_SGMII_MASK, val); ++ ++ if (mac_id == MTK_GMAC2_ID) ++ regmap_set_bits(eth->infra, TOP_MISC_NETSYS_PCS_MUX, ++ MUX_G2_USXGMII_SEL); ++ } ++ ++ dev_dbg(eth->dev, "path %s in %s updated = %d\n", ++ mtk_eth_path_name(path), __func__, updated); ++ ++ return 0; ++} ++ ++static int set_mux_gmac123_to_gephy_sgmii(struct mtk_eth *eth, u64 path) + { + unsigned int val = 0; + bool updated = true; +@@ -182,6 +254,9 @@ static int set_mux_gmac12_to_gephy_sgmii + case MTK_ETH_PATH_GMAC2_SGMII: + val |= SYSCFG0_SGMII_GMAC2_V2; + break; ++ case MTK_ETH_PATH_GMAC3_SGMII: ++ val |= SYSCFG0_SGMII_GMAC3_V2; ++ break; + default: + updated = false; + } +@@ -210,13 +285,25 @@ static const struct mtk_eth_muxc mtk_eth + .cap_bit = MTK_ETH_MUX_U3_GMAC2_TO_QPHY, + .set_path = set_mux_u3_gmac2_to_qphy, + }, { ++ .name = "mux_gmac2_to_2p5gphy", ++ .cap_bit = MTK_ETH_MUX_GMAC2_TO_2P5GPHY, ++ .set_path = set_mux_gmac2_to_2p5gphy, ++ }, { + .name = "mux_gmac1_gmac2_to_sgmii_rgmii", + .cap_bit = MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII, + .set_path = set_mux_gmac1_gmac2_to_sgmii_rgmii, + }, { + .name = "mux_gmac12_to_gephy_sgmii", + .cap_bit = MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII, +- .set_path = set_mux_gmac12_to_gephy_sgmii, ++ .set_path = set_mux_gmac123_to_gephy_sgmii, ++ }, { ++ .name = "mux_gmac123_to_gephy_sgmii", ++ .cap_bit = MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII, ++ .set_path = set_mux_gmac123_to_gephy_sgmii, ++ }, { ++ .name = "mux_gmac123_to_usxgmii", ++ .cap_bit = MTK_ETH_MUX_GMAC123_TO_USXGMII, ++ .set_path = set_mux_gmac123_to_usxgmii, + }, + }; + +@@ -249,12 +336,39 @@ out: + return err; + } + ++int mtk_gmac_usxgmii_path_setup(struct mtk_eth *eth, int mac_id) ++{ ++ u64 path; ++ ++ path = (mac_id == MTK_GMAC1_ID) ? MTK_ETH_PATH_GMAC1_USXGMII : ++ (mac_id == MTK_GMAC2_ID) ? MTK_ETH_PATH_GMAC2_USXGMII : ++ MTK_ETH_PATH_GMAC3_USXGMII; ++ ++ /* Setup proper MUXes along the path */ ++ return mtk_eth_mux_setup(eth, path); ++} ++ + int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id) + { + u64 path; + +- path = (mac_id == 0) ? MTK_ETH_PATH_GMAC1_SGMII : +- MTK_ETH_PATH_GMAC2_SGMII; ++ path = (mac_id == MTK_GMAC1_ID) ? MTK_ETH_PATH_GMAC1_SGMII : ++ (mac_id == MTK_GMAC2_ID) ? MTK_ETH_PATH_GMAC2_SGMII : ++ MTK_ETH_PATH_GMAC3_SGMII; ++ ++ /* Setup proper MUXes along the path */ ++ return mtk_eth_mux_setup(eth, path); ++} ++ ++int mtk_gmac_2p5gphy_path_setup(struct mtk_eth *eth, int mac_id) ++{ ++ u64 path = 0; ++ ++ if (mac_id == MTK_GMAC2_ID) ++ path = MTK_ETH_PATH_GMAC2_2P5GPHY; ++ ++ if (!path) ++ return -EINVAL; + + /* Setup proper MUXes along the path */ + return mtk_eth_mux_setup(eth, path); +@@ -284,4 +398,3 @@ int mtk_gmac_rgmii_path_setup(struct mtk + /* Setup proper MUXes along the path */ + return mtk_eth_mux_setup(eth, path); + } +- +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -474,6 +474,30 @@ static void mtk_setup_bridge_switch(stru + MTK_GSW_CFG); + } + ++static bool mtk_check_gmac23_idle(struct mtk_mac *mac) ++{ ++ u32 mac_fsm, gdm_fsm; ++ ++ mac_fsm = mtk_r32(mac->hw, MTK_MAC_FSM(mac->id)); ++ ++ switch (mac->id) { ++ case MTK_GMAC2_ID: ++ gdm_fsm = mtk_r32(mac->hw, MTK_FE_GDM2_FSM); ++ break; ++ case MTK_GMAC3_ID: ++ gdm_fsm = mtk_r32(mac->hw, MTK_FE_GDM3_FSM); ++ break; ++ default: ++ return true; ++ }; ++ ++ if ((mac_fsm & 0xFFFF0000) == 0x01010000 && ++ (gdm_fsm & 0xFFFF0000) == 0x00000000) ++ return true; ++ ++ return false; ++} ++ + static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config, + phy_interface_t interface) + { +@@ -482,12 +506,20 @@ static struct phylink_pcs *mtk_mac_selec + struct mtk_eth *eth = mac->hw; + unsigned int sid; + +- if (interface == PHY_INTERFACE_MODE_SGMII || +- phy_interface_mode_is_8023z(interface)) { +- sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? +- 0 : mac->id; +- +- return eth->sgmii_pcs[sid]; ++ if ((interface == PHY_INTERFACE_MODE_SGMII || ++ phy_interface_mode_is_8023z(interface)) && ++ MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { ++ sid = mtk_mac2xgmii_id(eth, mac->id); ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII)) ++ return mtk_sgmii_wrapper_select_pcs(eth, mac->id); ++ else ++ return eth->sgmii_pcs[sid]; ++ } else if ((interface == PHY_INTERFACE_MODE_USXGMII || ++ interface == PHY_INTERFACE_MODE_10GBASER || ++ interface == PHY_INTERFACE_MODE_5GBASER) && ++ MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII) && ++ mac->id != MTK_GMAC1_ID) { ++ return mtk_usxgmii_select_pcs(eth, mac->id); + } + + return NULL; +@@ -543,7 +575,22 @@ static void mtk_mac_config(struct phylin + goto init_err; + } + break; ++ case PHY_INTERFACE_MODE_USXGMII: ++ case PHY_INTERFACE_MODE_10GBASER: ++ case PHY_INTERFACE_MODE_5GBASER: ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII)) { ++ err = mtk_gmac_usxgmii_path_setup(eth, mac->id); ++ if (err) ++ goto init_err; ++ } ++ break; + case PHY_INTERFACE_MODE_INTERNAL: ++ if (mac->id == MTK_GMAC2_ID && ++ MTK_HAS_CAPS(eth->soc->caps, MTK_2P5GPHY)) { ++ err = mtk_gmac_2p5gphy_path_setup(eth, mac->id); ++ if (err) ++ goto init_err; ++ } + break; + default: + goto err_phy; +@@ -598,8 +645,6 @@ static void mtk_mac_config(struct phylin + val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); + val |= SYSCFG0_GE_MODE(ge_mode, mac->id); + regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); +- +- mac->interface = state->interface; + } + + /* SGMII */ +@@ -616,21 +661,40 @@ static void mtk_mac_config(struct phylin + + /* Save the syscfg0 value for mac_finish */ + mac->syscfg0 = val; +- } else if (phylink_autoneg_inband(mode)) { ++ } else if (state->interface != PHY_INTERFACE_MODE_USXGMII && ++ state->interface != PHY_INTERFACE_MODE_10GBASER && ++ state->interface != PHY_INTERFACE_MODE_5GBASER && ++ phylink_autoneg_inband(mode)) { + dev_err(eth->dev, +- "In-band mode not supported in non SGMII mode!\n"); ++ "In-band mode not supported in non-SerDes modes!\n"); + return; + } + + /* Setup gmac */ +- if (mtk_is_netsys_v3_or_greater(eth) && +- mac->interface == PHY_INTERFACE_MODE_INTERNAL) { +- mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id)); +- mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id)); ++ if (mtk_is_netsys_v3_or_greater(eth)) { ++ if (mtk_interface_mode_is_xgmii(state->interface)) { ++ mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id)); ++ mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id)); ++ ++ if (mac->id == MTK_GMAC1_ID) ++ mtk_setup_bridge_switch(eth); ++ } else { ++ mtk_w32(eth, 0, MTK_GDMA_EG_CTRL(mac->id)); + +- mtk_setup_bridge_switch(eth); ++ /* FIXME: In current hardware design, we have to reset FE ++ * when swtiching XGDM to GDM. Therefore, here trigger an SER ++ * to let GDM go back to the initial state. ++ */ ++ if ((mtk_interface_mode_is_xgmii(mac->interface) || ++ mac->interface == PHY_INTERFACE_MODE_NA) && ++ !mtk_check_gmac23_idle(mac) && ++ !test_bit(MTK_RESETTING, ð->state)) ++ schedule_work(ð->pending_work); ++ } + } + ++ mac->interface = state->interface; ++ + return; + + err_phy: +@@ -676,10 +740,13 @@ static void mtk_mac_link_down(struct phy + { + struct mtk_mac *mac = container_of(config, struct mtk_mac, + phylink_config); +- u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); + +- mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN); +- mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); ++ if (!mtk_interface_mode_is_xgmii(interface)) { ++ mtk_m32(mac->hw, MAC_MCR_TX_EN | MAC_MCR_RX_EN, 0, MTK_MAC_MCR(mac->id)); ++ mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id), 0, MTK_XGMAC_STS(mac->id)); ++ } else if (mac->id != MTK_GMAC1_ID) { ++ mtk_m32(mac->hw, XMAC_MCR_TRX_DISABLE, XMAC_MCR_TRX_DISABLE, MTK_XMAC_MCR(mac->id)); ++ } + } + + static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx, +@@ -751,13 +818,11 @@ static void mtk_set_queue_speed(struct m + mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); + } + +-static void mtk_mac_link_up(struct phylink_config *config, +- struct phy_device *phy, +- unsigned int mode, phy_interface_t interface, +- int speed, int duplex, bool tx_pause, bool rx_pause) ++static void mtk_gdm_mac_link_up(struct mtk_mac *mac, ++ struct phy_device *phy, ++ unsigned int mode, phy_interface_t interface, ++ int speed, int duplex, bool tx_pause, bool rx_pause) + { +- struct mtk_mac *mac = container_of(config, struct mtk_mac, +- phylink_config); + u32 mcr; + + mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); +@@ -791,6 +856,55 @@ static void mtk_mac_link_up(struct phyli + mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); + } + ++static void mtk_xgdm_mac_link_up(struct mtk_mac *mac, ++ struct phy_device *phy, ++ unsigned int mode, phy_interface_t interface, ++ int speed, int duplex, bool tx_pause, bool rx_pause) ++{ ++ u32 mcr, force_link = 0; ++ ++ if (mac->id == MTK_GMAC1_ID) ++ return; ++ ++ /* Eliminate the interference(before link-up) caused by PHY noise */ ++ mtk_m32(mac->hw, XMAC_LOGIC_RST, 0, MTK_XMAC_LOGIC_RST(mac->id)); ++ mdelay(20); ++ mtk_m32(mac->hw, XMAC_GLB_CNTCLR, XMAC_GLB_CNTCLR, MTK_XMAC_CNT_CTRL(mac->id)); ++ ++ if (mac->interface == PHY_INTERFACE_MODE_INTERNAL || mac->id == MTK_GMAC3_ID) ++ force_link = MTK_XGMAC_FORCE_LINK(mac->id); ++ ++ mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id), force_link, MTK_XGMAC_STS(mac->id)); ++ ++ mcr = mtk_r32(mac->hw, MTK_XMAC_MCR(mac->id)); ++ mcr &= ~(XMAC_MCR_FORCE_TX_FC | XMAC_MCR_FORCE_RX_FC | XMAC_MCR_TRX_DISABLE); ++ /* Configure pause modes - ++ * phylink will avoid these for half duplex ++ */ ++ if (tx_pause) ++ mcr |= XMAC_MCR_FORCE_TX_FC; ++ if (rx_pause) ++ mcr |= XMAC_MCR_FORCE_RX_FC; ++ ++ mtk_w32(mac->hw, mcr, MTK_XMAC_MCR(mac->id)); ++} ++ ++static void mtk_mac_link_up(struct phylink_config *config, ++ struct phy_device *phy, ++ unsigned int mode, phy_interface_t interface, ++ int speed, int duplex, bool tx_pause, bool rx_pause) ++{ ++ struct mtk_mac *mac = container_of(config, struct mtk_mac, ++ phylink_config); ++ ++ if (mtk_interface_mode_is_xgmii(interface)) ++ mtk_xgdm_mac_link_up(mac, phy, mode, interface, speed, duplex, ++ tx_pause, rx_pause); ++ else ++ mtk_gdm_mac_link_up(mac, phy, mode, interface, speed, duplex, ++ tx_pause, rx_pause); ++} ++ + static const struct phylink_mac_ops mtk_phylink_ops = { + .validate = phylink_generic_validate, + .mac_select_pcs = mtk_mac_select_pcs, +@@ -4612,8 +4726,21 @@ static int mtk_add_mac(struct mtk_eth *e + phy_interface_zero(mac->phylink_config.supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_INTERNAL, + mac->phylink_config.supported_interfaces); ++ } else if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_USXGMII)) { ++ mac->phylink_config.mac_capabilities |= MAC_5000FD | MAC_10000FD; ++ __set_bit(PHY_INTERFACE_MODE_5GBASER, ++ mac->phylink_config.supported_interfaces); ++ __set_bit(PHY_INTERFACE_MODE_10GBASER, ++ mac->phylink_config.supported_interfaces); ++ __set_bit(PHY_INTERFACE_MODE_USXGMII, ++ mac->phylink_config.supported_interfaces); + } + ++ if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_2P5GPHY) && ++ id == MTK_GMAC2_ID) ++ __set_bit(PHY_INTERFACE_MODE_INTERNAL, ++ mac->phylink_config.supported_interfaces); ++ + phylink = phylink_create(&mac->phylink_config, + of_fwnode_handle(mac->of_node), + phy_mode, &mtk_phylink_ops); +@@ -4806,6 +4933,13 @@ static int mtk_probe(struct platform_dev + + if (err) + return err; ++ } ++ ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII)) { ++ err = mtk_usxgmii_init(eth); ++ ++ if (err) ++ return err; + } + + if (eth->soc->required_pctl) { +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -502,6 +502,21 @@ + #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) + #define INTF_MODE_RGMII_10_100 0 + ++/* XFI Mac control registers */ ++#define MTK_XMAC_BASE(x) (0x12000 + (((x) - 1) * 0x1000)) ++#define MTK_XMAC_MCR(x) (MTK_XMAC_BASE(x)) ++#define XMAC_MCR_TRX_DISABLE 0xf ++#define XMAC_MCR_FORCE_TX_FC BIT(5) ++#define XMAC_MCR_FORCE_RX_FC BIT(4) ++ ++/* XFI Mac logic reset registers */ ++#define MTK_XMAC_LOGIC_RST(x) (MTK_XMAC_BASE(x) + 0x10) ++#define XMAC_LOGIC_RST BIT(0) ++ ++/* XFI Mac count global control */ ++#define MTK_XMAC_CNT_CTRL(x) (MTK_XMAC_BASE(x) + 0x100) ++#define XMAC_GLB_CNTCLR BIT(0) ++ + /* GPIO port control registers for GMAC 2*/ + #define GPIO_OD33_CTRL8 0x4c0 + #define GPIO_BIAS_CTRL 0xed0 +@@ -527,6 +542,7 @@ + #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) + #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) + #define SYSCFG0_SGMII_GMAC2_V2 BIT(8) ++#define SYSCFG0_SGMII_GMAC3_V2 BIT(7) + + + /* ethernet subsystem clock register */ +@@ -559,12 +575,74 @@ + #define ETHSYS_DMA_AG_MAP_QDMA BIT(1) + #define ETHSYS_DMA_AG_MAP_PPE BIT(2) + ++/* USXGMII subsystem config registers */ ++/* Register to control speed */ ++#define RG_PHY_TOP_SPEED_CTRL1 0x80C ++#define USXGMII_RATE_UPDATE_MODE BIT(31) ++#define USXGMII_MAC_CK_GATED BIT(29) ++#define USXGMII_IF_FORCE_EN BIT(28) ++#define USXGMII_RATE_ADAPT_MODE GENMASK(10, 8) ++#define USXGMII_RATE_ADAPT_MODE_X1 0 ++#define USXGMII_RATE_ADAPT_MODE_X2 1 ++#define USXGMII_RATE_ADAPT_MODE_X4 2 ++#define USXGMII_RATE_ADAPT_MODE_X10 3 ++#define USXGMII_RATE_ADAPT_MODE_X100 4 ++#define USXGMII_RATE_ADAPT_MODE_X5 5 ++#define USXGMII_RATE_ADAPT_MODE_X50 6 ++#define USXGMII_XFI_RX_MODE GENMASK(6, 4) ++#define USXGMII_XFI_RX_MODE_10G 0 ++#define USXGMII_XFI_RX_MODE_5G 1 ++#define USXGMII_XFI_TX_MODE GENMASK(2, 0) ++#define USXGMII_XFI_TX_MODE_10G 0 ++#define USXGMII_XFI_TX_MODE_5G 1 ++ ++/* Register to control PCS AN */ ++#define RG_PCS_AN_CTRL0 0x810 ++#define USXGMII_AN_RESTART BIT(31) ++#define USXGMII_AN_SYNC_CNT GENMASK(30, 11) ++#define USXGMII_AN_ENABLE BIT(0) ++ ++#define RG_PCS_AN_CTRL2 0x818 ++#define USXGMII_LINK_TIMER_IDLE_DETECT GENMASK(29, 20) ++#define USXGMII_LINK_TIMER_COMP_ACK_DETECT GENMASK(19, 10) ++#define USXGMII_LINK_TIMER_AN_RESTART GENMASK(9, 0) ++ ++/* Register to read PCS AN status */ ++#define RG_PCS_AN_STS0 0x81c ++#define USXGMII_PCS_AN_WORD GENMASK(15, 0) ++#define USXGMII_LPA_LATCH BIT(31) ++ ++/* Register to control USXGMII XFI PLL digital */ ++#define XFI_PLL_DIG_GLB8 0x08 ++#define RG_XFI_PLL_EN BIT(31) ++ ++/* Register to control USXGMII XFI PLL analog */ ++#define XFI_PLL_ANA_GLB8 0x108 ++#define RG_XFI_PLL_ANA_SWWA 0x02283248 ++ + /* Infrasys subsystem config registers */ + #define INFRA_MISC2 0x70c + #define CO_QPHY_SEL BIT(0) + #define GEPHY_MAC_SEL BIT(1) + ++/* Toprgu subsystem config registers */ ++#define TOPRGU_SWSYSRST 0x18 ++#define SWSYSRST_UNLOCK_KEY GENMASK(31, 24) ++#define SWSYSRST_XFI_PLL_GRST BIT(16) ++#define SWSYSRST_XFI_PEXPT1_GRST BIT(15) ++#define SWSYSRST_XFI_PEXPT0_GRST BIT(14) ++#define SWSYSRST_XFI1_GRST BIT(13) ++#define SWSYSRST_XFI0_GRST BIT(12) ++#define SWSYSRST_SGMII1_GRST BIT(2) ++#define SWSYSRST_SGMII0_GRST BIT(1) ++#define TOPRGU_SWSYSRST_EN 0xFC ++ + /* Top misc registers */ ++#define TOP_MISC_NETSYS_PCS_MUX 0x84 ++#define NETSYS_PCS_MUX_MASK GENMASK(1, 0) ++#define MUX_G2_USXGMII_SEL BIT(1) ++#define MUX_HSGMII1_G1_SEL BIT(0) ++ + #define USB_PHY_SWITCH_REG 0x218 + #define QPHY_SEL_MASK GENMASK(1, 0) + #define SGMII_QPHY_SEL 0x2 +@@ -589,6 +667,8 @@ + #define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c) + #define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110) + ++/* Debug Purpose Register */ ++#define MTK_PSE_FQFC_CFG 0x100 + #define MTK_FE_CDM1_FSM 0x220 + #define MTK_FE_CDM2_FSM 0x224 + #define MTK_FE_CDM3_FSM 0x238 +@@ -597,6 +677,11 @@ + #define MTK_FE_CDM6_FSM 0x328 + #define MTK_FE_GDM1_FSM 0x228 + #define MTK_FE_GDM2_FSM 0x22C ++#define MTK_FE_GDM3_FSM 0x23C ++#define MTK_FE_PSE_FREE 0x240 ++#define MTK_FE_DROP_FQ 0x244 ++#define MTK_FE_DROP_FC 0x248 ++#define MTK_FE_DROP_PPE 0x24C + + #define MTK_MAC_FSM(x) (0x1010C + ((x) * 0x100)) + +@@ -943,6 +1028,8 @@ enum mkt_eth_capabilities { + MTK_RGMII_BIT = 0, + MTK_TRGMII_BIT, + MTK_SGMII_BIT, ++ MTK_USXGMII_BIT, ++ MTK_2P5GPHY_BIT, + MTK_ESW_BIT, + MTK_GEPHY_BIT, + MTK_MUX_BIT, +@@ -963,8 +1050,11 @@ enum mkt_eth_capabilities { + MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, + MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT, + MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, ++ MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT, + MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, + MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, ++ MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT, ++ MTK_ETH_MUX_GMAC123_TO_USXGMII_BIT, + + /* PATH BITS */ + MTK_ETH_PATH_GMAC1_RGMII_BIT, +@@ -972,14 +1062,21 @@ enum mkt_eth_capabilities { + MTK_ETH_PATH_GMAC1_SGMII_BIT, + MTK_ETH_PATH_GMAC2_RGMII_BIT, + MTK_ETH_PATH_GMAC2_SGMII_BIT, ++ MTK_ETH_PATH_GMAC2_2P5GPHY_BIT, + MTK_ETH_PATH_GMAC2_GEPHY_BIT, ++ MTK_ETH_PATH_GMAC3_SGMII_BIT, + MTK_ETH_PATH_GDM1_ESW_BIT, ++ MTK_ETH_PATH_GMAC1_USXGMII_BIT, ++ MTK_ETH_PATH_GMAC2_USXGMII_BIT, ++ MTK_ETH_PATH_GMAC3_USXGMII_BIT, + }; + + /* Supported hardware group on SoCs */ + #define MTK_RGMII BIT_ULL(MTK_RGMII_BIT) + #define MTK_TRGMII BIT_ULL(MTK_TRGMII_BIT) + #define MTK_SGMII BIT_ULL(MTK_SGMII_BIT) ++#define MTK_USXGMII BIT_ULL(MTK_USXGMII_BIT) ++#define MTK_2P5GPHY BIT_ULL(MTK_2P5GPHY_BIT) + #define MTK_ESW BIT_ULL(MTK_ESW_BIT) + #define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT) + #define MTK_MUX BIT_ULL(MTK_MUX_BIT) +@@ -1002,10 +1099,16 @@ enum mkt_eth_capabilities { + BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) + #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ + BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) ++#define MTK_ETH_MUX_GMAC2_TO_2P5GPHY \ ++ BIT_ULL(MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT) + #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ + BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) + #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ + BIT_ULL(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) ++#define MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII \ ++ BIT_ULL(MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT) ++#define MTK_ETH_MUX_GMAC123_TO_USXGMII \ ++ BIT_ULL(MTK_ETH_MUX_GMAC123_TO_USXGMII_BIT) + + /* Supported path present on SoCs */ + #define MTK_ETH_PATH_GMAC1_RGMII BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT) +@@ -1013,8 +1116,13 @@ enum mkt_eth_capabilities { + #define MTK_ETH_PATH_GMAC1_SGMII BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT) + #define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT) + #define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT) ++#define MTK_ETH_PATH_GMAC2_2P5GPHY BIT_ULL(MTK_ETH_PATH_GMAC2_2P5GPHY_BIT) + #define MTK_ETH_PATH_GMAC2_GEPHY BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT) ++#define MTK_ETH_PATH_GMAC3_SGMII BIT_ULL(MTK_ETH_PATH_GMAC3_SGMII_BIT) + #define MTK_ETH_PATH_GDM1_ESW BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT) ++#define MTK_ETH_PATH_GMAC1_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC1_USXGMII_BIT) ++#define MTK_ETH_PATH_GMAC2_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC2_USXGMII_BIT) ++#define MTK_ETH_PATH_GMAC3_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC3_USXGMII_BIT) + + #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) + #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) +@@ -1022,7 +1130,12 @@ enum mkt_eth_capabilities { + #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) + #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) + #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) ++#define MTK_GMAC2_2P5GPHY (MTK_ETH_PATH_GMAC2_2P5GPHY | MTK_2P5GPHY) ++#define MTK_GMAC3_SGMII (MTK_ETH_PATH_GMAC3_SGMII | MTK_SGMII) + #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) ++#define MTK_GMAC1_USXGMII (MTK_ETH_PATH_GMAC1_USXGMII | MTK_USXGMII) ++#define MTK_GMAC2_USXGMII (MTK_ETH_PATH_GMAC2_USXGMII | MTK_USXGMII) ++#define MTK_GMAC3_USXGMII (MTK_ETH_PATH_GMAC3_USXGMII | MTK_USXGMII) + + /* MUXes present on SoCs */ + /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ +@@ -1041,10 +1154,20 @@ enum mkt_eth_capabilities { + (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \ + MTK_SHARED_SGMII) + ++/* 2: GMAC2 -> XGMII */ ++#define MTK_MUX_GMAC2_TO_2P5GPHY \ ++ (MTK_ETH_MUX_GMAC2_TO_2P5GPHY | MTK_MUX | MTK_INFRA) ++ + /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */ + #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ + (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) + ++#define MTK_MUX_GMAC123_TO_GEPHY_SGMII \ ++ (MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII | MTK_MUX) ++ ++#define MTK_MUX_GMAC123_TO_USXGMII \ ++ (MTK_ETH_MUX_GMAC123_TO_USXGMII | MTK_MUX | MTK_INFRA) ++ + #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) + + #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ +@@ -1076,8 +1199,12 @@ enum mkt_eth_capabilities { + MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ + MTK_RSTCTRL_PPE1 | MTK_SRAM) + +-#define MT7988_CAPS (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_QDMA | \ +- MTK_RSTCTRL_PPE1 | MTK_RSTCTRL_PPE2 | MTK_SRAM) ++#define MT7988_CAPS (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_GMAC1_SGMII | \ ++ MTK_GMAC2_2P5GPHY | MTK_GMAC2_SGMII | MTK_GMAC2_USXGMII | \ ++ MTK_GMAC3_SGMII | MTK_GMAC3_USXGMII | \ ++ MTK_MUX_GMAC123_TO_GEPHY_SGMII | \ ++ MTK_MUX_GMAC123_TO_USXGMII | MTK_MUX_GMAC2_TO_2P5GPHY | \ ++ MTK_QDMA | MTK_RSTCTRL_PPE1 | MTK_RSTCTRL_PPE2 | MTK_SRAM) + + struct mtk_tx_dma_desc_info { + dma_addr_t addr; +@@ -1187,6 +1314,24 @@ struct mtk_soc_data { + /* currently no SoC has more than 3 macs */ + #define MTK_MAX_DEVS 3 + ++/* struct mtk_usxgmii_pcs - This structure holds each usxgmii regmap and ++ * associated data ++ * @regmap: The register map pointing at the range used to setup ++ * USXGMII modes ++ * @interface: Currently selected interface mode ++ * @id: The element is used to record the index of PCS ++ * @pcs: Phylink PCS structure ++ */ ++struct mtk_usxgmii_pcs { ++ struct mtk_eth *eth; ++ struct regmap *regmap; ++ struct phylink_pcs *wrapped_sgmii_pcs; ++ phy_interface_t interface; ++ u8 id; ++ unsigned int mode; ++ struct phylink_pcs pcs; ++}; ++ + /* struct mtk_eth - This is the main datasructure for holding the state + * of the driver + * @dev: The device pointer +@@ -1207,6 +1352,12 @@ struct mtk_soc_data { + * @infra: The register map pointing at the range used to setup + * SGMII and GePHY path + * @sgmii_pcs: Pointers to mtk-pcs-lynxi phylink_pcs instances ++ * @sgmii_wrapped_pcs: Pointers to NETSYSv3 wrapper PCS instances ++ * @usxgmii_pll: The register map pointing at the range used to control ++ * the USXGMII SerDes PLL ++ * @regmap_pextp: The register map pointing at the range used to setup ++ * PHYA ++ * @usxgmii_pcs: Pointer to array of pointers to struct for USXGMII PCS + * @pctl: The register map pointing at the range used to setup + * GMAC port drive/slew values + * @dma_refcnt: track how many netdevs are using the DMA engine +@@ -1250,6 +1401,10 @@ struct mtk_eth { + struct regmap *ethsys; + struct regmap *infra; + struct phylink_pcs *sgmii_pcs[MTK_MAX_DEVS]; ++ struct regmap *toprgu; ++ struct regmap *usxgmii_pll; ++ struct regmap *regmap_pextp[MTK_MAX_DEVS]; ++ struct mtk_usxgmii_pcs *usxgmii_pcs[MTK_MAX_DEVS]; + struct regmap *pctl; + bool hwlro; + refcount_t dma_refcnt; +@@ -1437,6 +1592,19 @@ static inline u32 mtk_get_ib2_multicast_ + return MTK_FOE_IB2_MULTICAST; + } + ++static inline bool mtk_interface_mode_is_xgmii(phy_interface_t interface) ++{ ++ switch (interface) { ++ case PHY_INTERFACE_MODE_INTERNAL: ++ case PHY_INTERFACE_MODE_USXGMII: ++ case PHY_INTERFACE_MODE_10GBASER: ++ case PHY_INTERFACE_MODE_5GBASER: ++ return true; ++ default: ++ return false; ++ } ++} ++ + /* read the hardware status register */ + void mtk_stats_update_mac(struct mtk_mac *mac); + +@@ -1445,8 +1613,10 @@ u32 mtk_r32(struct mtk_eth *eth, unsigne + u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg); + + int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); ++int mtk_gmac_2p5gphy_path_setup(struct mtk_eth *eth, int mac_id); + int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); + int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); ++int mtk_gmac_usxgmii_path_setup(struct mtk_eth *eth, int mac_id); + + int mtk_eth_offload_init(struct mtk_eth *eth); + int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, +@@ -1456,5 +1626,63 @@ int mtk_flow_offload_cmd(struct mtk_eth + void mtk_flow_offload_cleanup(struct mtk_eth *eth, struct list_head *list); + void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev); + ++static inline int mtk_mac2xgmii_id(struct mtk_eth *eth, int mac_id) ++{ ++ int xgmii_id = mac_id; ++ ++ if (mtk_is_netsys_v3_or_greater(eth)) { ++ switch (mac_id) { ++ case MTK_GMAC1_ID: ++ case MTK_GMAC2_ID: ++ xgmii_id = 1; ++ break; ++ case MTK_GMAC3_ID: ++ xgmii_id = 0; ++ break; ++ default: ++ xgmii_id = -1; ++ } ++ } ++ ++ return MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII) ? 0 : xgmii_id; ++} ++ ++static inline int mtk_xgmii2mac_id(struct mtk_eth *eth, int xgmii_id) ++{ ++ int mac_id = xgmii_id; ++ ++ if (mtk_is_netsys_v3_or_greater(eth)) { ++ switch (xgmii_id) { ++ case 0: ++ mac_id = 2; ++ break; ++ case 1: ++ mac_id = 1; ++ break; ++ default: ++ mac_id = -1; ++ } ++ } ++ ++ return mac_id; ++} ++ ++#ifdef CONFIG_NET_MEDIATEK_SOC_USXGMII ++struct phylink_pcs *mtk_sgmii_wrapper_select_pcs(struct mtk_eth *eth, int id); ++struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int id); ++int mtk_usxgmii_init(struct mtk_eth *eth); ++#else ++static inline struct phylink_pcs *mtk_sgmii_wrapper_select_pcs(struct mtk_eth *eth, int id) ++{ ++ return NULL; ++} ++ ++static inline struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int id) ++{ ++ return NULL; ++} ++ ++static inline int mtk_usxgmii_init(struct mtk_eth *eth) { return 0; } ++#endif /* NET_MEDIATEK_SOC_USXGMII */ + + #endif /* MTK_ETH_H */ +--- /dev/null ++++ b/drivers/net/ethernet/mediatek/mtk_usxgmii.c +@@ -0,0 +1,690 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2023 MediaTek Inc. ++ * Author: Henry Yen ++ * Daniel Golle ++ */ ++ ++#include ++#include ++#include ++#include "mtk_eth_soc.h" ++ ++static struct mtk_usxgmii_pcs *pcs_to_mtk_usxgmii_pcs(struct phylink_pcs *pcs) ++{ ++ return container_of(pcs, struct mtk_usxgmii_pcs, pcs); ++} ++ ++static int mtk_xfi_pextp_init(struct mtk_eth *eth) ++{ ++ struct device *dev = eth->dev; ++ struct device_node *r = dev->of_node; ++ struct device_node *np; ++ int i; ++ ++ for (i = 0; i < MTK_MAX_DEVS; i++) { ++ np = of_parse_phandle(r, "mediatek,xfi-pextp", i); ++ if (!np) ++ break; ++ ++ eth->regmap_pextp[i] = syscon_node_to_regmap(np); ++ if (IS_ERR(eth->regmap_pextp[i])) ++ return PTR_ERR(eth->regmap_pextp[i]); ++ } ++ ++ return 0; ++} ++ ++static int mtk_xfi_pll_init(struct mtk_eth *eth) ++{ ++ struct device_node *r = eth->dev->of_node; ++ struct device_node *np; ++ ++ np = of_parse_phandle(r, "mediatek,xfi-pll", 0); ++ if (!np) ++ return -1; ++ ++ eth->usxgmii_pll = syscon_node_to_regmap(np); ++ if (IS_ERR(eth->usxgmii_pll)) ++ return PTR_ERR(eth->usxgmii_pll); ++ ++ return 0; ++} ++ ++static int mtk_toprgu_init(struct mtk_eth *eth) ++{ ++ struct device_node *r = eth->dev->of_node; ++ struct device_node *np; ++ ++ np = of_parse_phandle(r, "mediatek,toprgu", 0); ++ if (!np) ++ return -1; ++ ++ eth->toprgu = syscon_node_to_regmap(np); ++ if (IS_ERR(eth->toprgu)) ++ return PTR_ERR(eth->toprgu); ++ ++ return 0; ++} ++ ++static int mtk_xfi_pll_enable(struct mtk_eth *eth) ++{ ++ u32 val = 0; ++ ++ if (!eth->usxgmii_pll) ++ return -EINVAL; ++ ++ /* Add software workaround for USXGMII PLL TCL issue */ ++ regmap_write(eth->usxgmii_pll, XFI_PLL_ANA_GLB8, RG_XFI_PLL_ANA_SWWA); ++ ++ regmap_read(eth->usxgmii_pll, XFI_PLL_DIG_GLB8, &val); ++ val |= RG_XFI_PLL_EN; ++ regmap_write(eth->usxgmii_pll, XFI_PLL_DIG_GLB8, val); ++ ++ return 0; ++} ++ ++static void mtk_usxgmii_setup_phya(struct regmap *pextp, phy_interface_t interface, int id) ++{ ++ bool is_10g = (interface == PHY_INTERFACE_MODE_10GBASER || ++ interface == PHY_INTERFACE_MODE_USXGMII); ++ bool is_2p5g = (interface == PHY_INTERFACE_MODE_2500BASEX); ++ bool is_5g = (interface == PHY_INTERFACE_MODE_5GBASER); ++ ++ /* Setup operation mode */ ++ if (is_10g) ++ regmap_write(pextp, 0x9024, 0x00C9071C); ++ else ++ regmap_write(pextp, 0x9024, 0x00D9071C); ++ ++ if (is_5g) ++ regmap_write(pextp, 0x2020, 0xAAA5A5AA); ++ else ++ regmap_write(pextp, 0x2020, 0xAA8585AA); ++ ++ if (is_2p5g || is_5g || is_10g) { ++ regmap_write(pextp, 0x2030, 0x0C020707); ++ regmap_write(pextp, 0x2034, 0x0E050F0F); ++ regmap_write(pextp, 0x2040, 0x00140032); ++ } else { ++ regmap_write(pextp, 0x2030, 0x0C020207); ++ regmap_write(pextp, 0x2034, 0x0E05050F); ++ regmap_write(pextp, 0x2040, 0x00200032); ++ } ++ ++ if (is_2p5g || is_10g) ++ regmap_write(pextp, 0x50F0, 0x00C014AA); ++ else if (is_5g) ++ regmap_write(pextp, 0x50F0, 0x00C018AA); ++ else ++ regmap_write(pextp, 0x50F0, 0x00C014BA); ++ ++ if (is_5g) { ++ regmap_write(pextp, 0x50E0, 0x3777812B); ++ regmap_write(pextp, 0x506C, 0x005C9CFF); ++ regmap_write(pextp, 0x5070, 0x9DFAFAFA); ++ regmap_write(pextp, 0x5074, 0x273F3F3F); ++ regmap_write(pextp, 0x5078, 0xA8883868); ++ regmap_write(pextp, 0x507C, 0x14661466); ++ } else { ++ regmap_write(pextp, 0x50E0, 0x3777C12B); ++ regmap_write(pextp, 0x506C, 0x005F9CFF); ++ regmap_write(pextp, 0x5070, 0x9D9DFAFA); ++ regmap_write(pextp, 0x5074, 0x27273F3F); ++ regmap_write(pextp, 0x5078, 0xA7883C68); ++ regmap_write(pextp, 0x507C, 0x11661166); ++ } ++ ++ if (is_2p5g || is_10g) { ++ regmap_write(pextp, 0x5080, 0x0E000AAF); ++ regmap_write(pextp, 0x5084, 0x08080D0D); ++ regmap_write(pextp, 0x5088, 0x02030909); ++ } else if (is_5g) { ++ regmap_write(pextp, 0x5080, 0x0E001ABF); ++ regmap_write(pextp, 0x5084, 0x080B0D0D); ++ regmap_write(pextp, 0x5088, 0x02050909); ++ } else { ++ regmap_write(pextp, 0x5080, 0x0E000EAF); ++ regmap_write(pextp, 0x5084, 0x08080E0D); ++ regmap_write(pextp, 0x5088, 0x02030B09); ++ } ++ ++ if (is_5g) { ++ regmap_write(pextp, 0x50E4, 0x0C000000); ++ regmap_write(pextp, 0x50E8, 0x04000000); ++ } else { ++ regmap_write(pextp, 0x50E4, 0x0C0C0000); ++ regmap_write(pextp, 0x50E8, 0x04040000); ++ } ++ ++ if (is_2p5g || mtk_interface_mode_is_xgmii(interface)) ++ regmap_write(pextp, 0x50EC, 0x0F0F0C06); ++ else ++ regmap_write(pextp, 0x50EC, 0x0F0F0606); ++ ++ if (is_5g) { ++ regmap_write(pextp, 0x50A8, 0x50808C8C); ++ regmap_write(pextp, 0x6004, 0x18000000); ++ } else { ++ regmap_write(pextp, 0x50A8, 0x506E8C8C); ++ regmap_write(pextp, 0x6004, 0x18190000); ++ } ++ ++ if (is_10g) ++ regmap_write(pextp, 0x00F8, 0x01423342); ++ else if (is_5g) ++ regmap_write(pextp, 0x00F8, 0x00A132A1); ++ else if (is_2p5g) ++ regmap_write(pextp, 0x00F8, 0x009C329C); ++ else ++ regmap_write(pextp, 0x00F8, 0x00FA32FA); ++ ++ /* Force SGDT_OUT off and select PCS */ ++ if (mtk_interface_mode_is_xgmii(interface)) ++ regmap_write(pextp, 0x00F4, 0x80201F20); ++ else ++ regmap_write(pextp, 0x00F4, 0x80201F21); ++ ++ /* Force GLB_CKDET_OUT */ ++ regmap_write(pextp, 0x0030, 0x00050C00); ++ ++ /* Force AEQ on */ ++ regmap_write(pextp, 0x0070, 0x02002800); ++ ndelay(1020); ++ ++ /* Setup DA default value */ ++ regmap_write(pextp, 0x30B0, 0x00000020); ++ regmap_write(pextp, 0x3028, 0x00008A01); ++ regmap_write(pextp, 0x302C, 0x0000A884); ++ regmap_write(pextp, 0x3024, 0x00083002); ++ if (mtk_interface_mode_is_xgmii(interface)) { ++ regmap_write(pextp, 0x3010, 0x00022220); ++ regmap_write(pextp, 0x5064, 0x0F020A01); ++ regmap_write(pextp, 0x50B4, 0x06100600); ++ if (interface == PHY_INTERFACE_MODE_USXGMII) ++ regmap_write(pextp, 0x3048, 0x40704000); ++ else ++ regmap_write(pextp, 0x3048, 0x47684100); ++ } else { ++ regmap_write(pextp, 0x3010, 0x00011110); ++ regmap_write(pextp, 0x3048, 0x40704000); ++ } ++ ++ if (!mtk_interface_mode_is_xgmii(interface) && !is_2p5g) ++ regmap_write(pextp, 0x3064, 0x0000C000); ++ ++ if (interface == PHY_INTERFACE_MODE_USXGMII) { ++ regmap_write(pextp, 0x3050, 0xA8000000); ++ regmap_write(pextp, 0x3054, 0x000000AA); ++ } else if (mtk_interface_mode_is_xgmii(interface)) { ++ regmap_write(pextp, 0x3050, 0x00000000); ++ regmap_write(pextp, 0x3054, 0x00000000); ++ } else { ++ regmap_write(pextp, 0x3050, 0xA8000000); ++ regmap_write(pextp, 0x3054, 0x000000AA); ++ } ++ ++ if (mtk_interface_mode_is_xgmii(interface)) ++ regmap_write(pextp, 0x306C, 0x00000F00); ++ else if (is_2p5g) ++ regmap_write(pextp, 0x306C, 0x22000F00); ++ else ++ regmap_write(pextp, 0x306C, 0x20200F00); ++ ++ if (interface == PHY_INTERFACE_MODE_10GBASER && id == 0) ++ regmap_write(pextp, 0xA008, 0x0007B400); ++ ++ if (mtk_interface_mode_is_xgmii(interface)) ++ regmap_write(pextp, 0xA060, 0x00040000); ++ else ++ regmap_write(pextp, 0xA060, 0x00050000); ++ ++ if (is_10g) ++ regmap_write(pextp, 0x90D0, 0x00000001); ++ else if (is_5g) ++ regmap_write(pextp, 0x90D0, 0x00000003); ++ else if (is_2p5g) ++ regmap_write(pextp, 0x90D0, 0x00000005); ++ else ++ regmap_write(pextp, 0x90D0, 0x00000007); ++ ++ /* Release reset */ ++ regmap_write(pextp, 0x0070, 0x0200E800); ++ usleep_range(150, 500); ++ ++ /* Switch to P0 */ ++ regmap_write(pextp, 0x0070, 0x0200C111); ++ ndelay(1020); ++ regmap_write(pextp, 0x0070, 0x0200C101); ++ usleep_range(15, 50); ++ ++ if (mtk_interface_mode_is_xgmii(interface)) { ++ /* Switch to Gen3 */ ++ regmap_write(pextp, 0x0070, 0x0202C111); ++ } else { ++ /* Switch to Gen2 */ ++ regmap_write(pextp, 0x0070, 0x0201C111); ++ } ++ ndelay(1020); ++ if (mtk_interface_mode_is_xgmii(interface)) ++ regmap_write(pextp, 0x0070, 0x0202C101); ++ else ++ regmap_write(pextp, 0x0070, 0x0201C101); ++ usleep_range(100, 500); ++ regmap_write(pextp, 0x30B0, 0x00000030); ++ if (mtk_interface_mode_is_xgmii(interface)) ++ regmap_write(pextp, 0x00F4, 0x80201F00); ++ else ++ regmap_write(pextp, 0x00F4, 0x80201F01); ++ ++ regmap_write(pextp, 0x3040, 0x30000000); ++ usleep_range(400, 1000); ++} ++ ++static void mtk_usxgmii_reset(struct mtk_eth *eth, int id) ++{ ++ u32 toggle, val; ++ ++ if (id >= MTK_MAX_DEVS || !eth->toprgu) ++ return; ++ ++ switch (id) { ++ case 0: ++ toggle = SWSYSRST_XFI_PEXPT0_GRST | SWSYSRST_XFI0_GRST | ++ SWSYSRST_SGMII0_GRST; ++ break; ++ case 1: ++ toggle = SWSYSRST_XFI_PEXPT1_GRST | SWSYSRST_XFI1_GRST | ++ SWSYSRST_SGMII1_GRST; ++ break; ++ default: ++ return; ++ } ++ ++ /* Enable software reset */ ++ regmap_set_bits(eth->toprgu, TOPRGU_SWSYSRST_EN, toggle); ++ ++ /* Assert USXGMII reset */ ++ regmap_set_bits(eth->toprgu, TOPRGU_SWSYSRST, ++ FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88) | toggle); ++ ++ usleep_range(100, 500); ++ ++ /* De-assert USXGMII reset */ ++ regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val); ++ val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88); ++ val &= ~toggle; ++ regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val); ++ ++ /* Disable software reset */ ++ regmap_clear_bits(eth->toprgu, TOPRGU_SWSYSRST_EN, toggle); ++ ++ mdelay(10); ++} ++ ++/* As the USXGMII PHYA is shared with the 1000Base-X/2500Base-X/Cisco SGMII unit ++ * the psc-mtk-lynxi instance needs to be wrapped, so that calls to .pcs_config ++ * also trigger an initial reset and subsequent configuration of the PHYA. ++ */ ++struct mtk_sgmii_wrapper_pcs { ++ struct mtk_eth *eth; ++ struct phylink_pcs *wrapped_pcs; ++ u8 id; ++ struct phylink_pcs pcs; ++}; ++ ++static int mtk_sgmii_wrapped_pcs_config(struct phylink_pcs *pcs, ++ unsigned int mode, ++ phy_interface_t interface, ++ const unsigned long *advertising, ++ bool permit_pause_to_mac) ++{ ++ struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs); ++ bool full_reconf; ++ int ret; ++ ++ full_reconf = interface != wp->eth->usxgmii_pcs[wp->id]->interface; ++ if (full_reconf) { ++ mtk_xfi_pll_enable(wp->eth); ++ mtk_usxgmii_reset(wp->eth, wp->id); ++ } ++ ++ ret = wp->wrapped_pcs->ops->pcs_config(wp->wrapped_pcs, mode, interface, ++ advertising, permit_pause_to_mac); ++ ++ if (full_reconf) ++ mtk_usxgmii_setup_phya(wp->eth->regmap_pextp[wp->id], interface, wp->id); ++ ++ wp->eth->usxgmii_pcs[wp->id]->interface = interface; ++ ++ return ret; ++} ++ ++static void mtk_sgmii_wrapped_pcs_get_state(struct phylink_pcs *pcs, ++ struct phylink_link_state *state) ++{ ++ struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs); ++ ++ return wp->wrapped_pcs->ops->pcs_get_state(wp->wrapped_pcs, state); ++} ++ ++static void mtk_sgmii_wrapped_pcs_an_restart(struct phylink_pcs *pcs) ++{ ++ struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs); ++ ++ wp->wrapped_pcs->ops->pcs_an_restart(wp->wrapped_pcs); ++} ++ ++static void mtk_sgmii_wrapped_pcs_link_up(struct phylink_pcs *pcs, ++ unsigned int mode, ++ phy_interface_t interface, int speed, ++ int duplex) ++{ ++ struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs); ++ ++ wp->wrapped_pcs->ops->pcs_link_up(wp->wrapped_pcs, mode, interface, speed, duplex); ++} ++ ++static void mtk_sgmii_wrapped_pcs_disable(struct phylink_pcs *pcs) ++{ ++ struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs); ++ ++ wp->wrapped_pcs->ops->pcs_disable(wp->wrapped_pcs); ++ ++ wp->eth->usxgmii_pcs[wp->id]->interface = PHY_INTERFACE_MODE_NA; ++} ++ ++static const struct phylink_pcs_ops mtk_sgmii_wrapped_pcs_ops = { ++ .pcs_get_state = mtk_sgmii_wrapped_pcs_get_state, ++ .pcs_config = mtk_sgmii_wrapped_pcs_config, ++ .pcs_an_restart = mtk_sgmii_wrapped_pcs_an_restart, ++ .pcs_link_up = mtk_sgmii_wrapped_pcs_link_up, ++ .pcs_disable = mtk_sgmii_wrapped_pcs_disable, ++}; ++ ++static int mtk_sgmii_wrapper_init(struct mtk_eth *eth) ++{ ++ struct mtk_sgmii_wrapper_pcs *wp; ++ int i; ++ ++ for (i = 0; i < MTK_MAX_DEVS; i++) { ++ if (!eth->sgmii_pcs[i]) ++ continue; ++ ++ if (!eth->usxgmii_pcs[i]) ++ continue; ++ ++ /* Make sure all PCS ops are supported by wrapped PCS */ ++ if (!eth->sgmii_pcs[i]->ops->pcs_get_state || ++ !eth->sgmii_pcs[i]->ops->pcs_config || ++ !eth->sgmii_pcs[i]->ops->pcs_an_restart || ++ !eth->sgmii_pcs[i]->ops->pcs_link_up || ++ !eth->sgmii_pcs[i]->ops->pcs_disable) ++ return -EOPNOTSUPP; ++ ++ wp = devm_kzalloc(eth->dev, sizeof(*wp), GFP_KERNEL); ++ if (!wp) ++ return -ENOMEM; ++ ++ wp->wrapped_pcs = eth->sgmii_pcs[i]; ++ wp->id = i; ++ wp->pcs.poll = true; ++ wp->pcs.ops = &mtk_sgmii_wrapped_pcs_ops; ++ wp->eth = eth; ++ ++ eth->usxgmii_pcs[i]->wrapped_sgmii_pcs = &wp->pcs; ++ } ++ ++ return 0; ++} ++ ++struct phylink_pcs *mtk_sgmii_wrapper_select_pcs(struct mtk_eth *eth, int mac_id) ++{ ++ u32 xgmii_id = mtk_mac2xgmii_id(eth, mac_id); ++ ++ if (!eth->usxgmii_pcs[xgmii_id]) ++ return NULL; ++ ++ return eth->usxgmii_pcs[xgmii_id]->wrapped_sgmii_pcs; ++} ++ ++static int mtk_usxgmii_pcs_config(struct phylink_pcs *pcs, unsigned int mode, ++ phy_interface_t interface, ++ const unsigned long *advertising, ++ bool permit_pause_to_mac) ++{ ++ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs); ++ struct mtk_eth *eth = mpcs->eth; ++ struct regmap *pextp = eth->regmap_pextp[mpcs->id]; ++ unsigned int an_ctrl = 0, link_timer = 0, xfi_mode = 0, adapt_mode = 0; ++ bool mode_changed = false; ++ ++ if (!pextp) ++ return -ENODEV; ++ ++ if (interface == PHY_INTERFACE_MODE_USXGMII) { ++ an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF) | USXGMII_AN_ENABLE; ++ link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) | ++ FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) | ++ FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B); ++ xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_10G) | ++ FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_10G); ++ } else if (interface == PHY_INTERFACE_MODE_10GBASER) { ++ an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF); ++ link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) | ++ FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) | ++ FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B); ++ xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_10G) | ++ FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_10G); ++ adapt_mode = USXGMII_RATE_UPDATE_MODE; ++ } else if (interface == PHY_INTERFACE_MODE_5GBASER) { ++ an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0xFF); ++ link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x3D) | ++ FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x3D) | ++ FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x3D); ++ xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_5G) | ++ FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_5G); ++ adapt_mode = USXGMII_RATE_UPDATE_MODE; ++ } else { ++ return -EINVAL; ++ } ++ ++ adapt_mode |= FIELD_PREP(USXGMII_RATE_ADAPT_MODE, USXGMII_RATE_ADAPT_MODE_X1); ++ ++ if (mpcs->interface != interface) { ++ mpcs->interface = interface; ++ mode_changed = true; ++ } ++ ++ mtk_xfi_pll_enable(eth); ++ mtk_usxgmii_reset(eth, mpcs->id); ++ ++ /* Setup USXGMII AN ctrl */ ++ regmap_update_bits(mpcs->regmap, RG_PCS_AN_CTRL0, ++ USXGMII_AN_SYNC_CNT | USXGMII_AN_ENABLE, ++ an_ctrl); ++ ++ regmap_update_bits(mpcs->regmap, RG_PCS_AN_CTRL2, ++ USXGMII_LINK_TIMER_IDLE_DETECT | ++ USXGMII_LINK_TIMER_COMP_ACK_DETECT | ++ USXGMII_LINK_TIMER_AN_RESTART, ++ link_timer); ++ ++ mpcs->mode = mode; ++ ++ /* Gated MAC CK */ ++ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, ++ USXGMII_MAC_CK_GATED, USXGMII_MAC_CK_GATED); ++ ++ /* Enable interface force mode */ ++ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, ++ USXGMII_IF_FORCE_EN, USXGMII_IF_FORCE_EN); ++ ++ /* Setup USXGMII adapt mode */ ++ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, ++ USXGMII_RATE_UPDATE_MODE | USXGMII_RATE_ADAPT_MODE, ++ adapt_mode); ++ ++ /* Setup USXGMII speed */ ++ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, ++ USXGMII_XFI_RX_MODE | USXGMII_XFI_TX_MODE, ++ xfi_mode); ++ ++ usleep_range(1, 10); ++ ++ /* Un-gated MAC CK */ ++ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, ++ USXGMII_MAC_CK_GATED, 0); ++ ++ usleep_range(1, 10); ++ ++ /* Disable interface force mode for the AN mode */ ++ if (an_ctrl & USXGMII_AN_ENABLE) ++ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, ++ USXGMII_IF_FORCE_EN, 0); ++ ++ /* Setup USXGMIISYS with the determined property */ ++ mtk_usxgmii_setup_phya(pextp, interface, mpcs->id); ++ ++ return mode_changed; ++} ++ ++static void mtk_usxgmii_pcs_get_state(struct phylink_pcs *pcs, ++ struct phylink_link_state *state) ++{ ++ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs); ++ struct mtk_eth *eth = mpcs->eth; ++ struct mtk_mac *mac = eth->mac[mtk_xgmii2mac_id(eth, mpcs->id)]; ++ u32 val = 0; ++ ++ regmap_read(mpcs->regmap, RG_PCS_AN_CTRL0, &val); ++ if (FIELD_GET(USXGMII_AN_ENABLE, val)) { ++ /* Refresh LPA by inverting LPA_LATCH */ ++ regmap_read(mpcs->regmap, RG_PCS_AN_STS0, &val); ++ regmap_update_bits(mpcs->regmap, RG_PCS_AN_STS0, ++ USXGMII_LPA_LATCH, ++ !(val & USXGMII_LPA_LATCH)); ++ ++ regmap_read(mpcs->regmap, RG_PCS_AN_STS0, &val); ++ ++ phylink_decode_usxgmii_word(state, FIELD_GET(USXGMII_PCS_AN_WORD, ++ val)); ++ ++ state->interface = mpcs->interface; ++ } else { ++ val = mtk_r32(mac->hw, MTK_XGMAC_STS(mac->id)); ++ ++ if (mac->id == MTK_GMAC2_ID) ++ val >>= 16; ++ ++ switch (FIELD_GET(MTK_USXGMII_PCS_MODE, val)) { ++ case 0: ++ state->speed = SPEED_10000; ++ break; ++ case 1: ++ state->speed = SPEED_5000; ++ break; ++ case 2: ++ state->speed = SPEED_2500; ++ break; ++ case 3: ++ state->speed = SPEED_1000; ++ break; ++ } ++ ++ state->interface = mpcs->interface; ++ state->link = FIELD_GET(MTK_USXGMII_PCS_LINK, val); ++ state->duplex = DUPLEX_FULL; ++ } ++ ++ /* Continuously repeat re-configuration sequence until link comes up */ ++ if (state->link == 0) ++ mtk_usxgmii_pcs_config(pcs, mpcs->mode, ++ state->interface, NULL, false); ++} ++ ++static void mtk_usxgmii_pcs_restart_an(struct phylink_pcs *pcs) ++{ ++ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs); ++ unsigned int val = 0; ++ ++ if (!mpcs->regmap) ++ return; ++ ++ regmap_read(mpcs->regmap, RG_PCS_AN_CTRL0, &val); ++ val |= USXGMII_AN_RESTART; ++ regmap_write(mpcs->regmap, RG_PCS_AN_CTRL0, val); ++} ++ ++static void mtk_usxgmii_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode, ++ phy_interface_t interface, ++ int speed, int duplex) ++{ ++ /* Reconfiguring USXGMII to ensure the quality of the RX signal ++ * after the line side link up. ++ */ ++ mtk_usxgmii_pcs_config(pcs, mode, ++ interface, NULL, false); ++} ++ ++static const struct phylink_pcs_ops mtk_usxgmii_pcs_ops = { ++ .pcs_config = mtk_usxgmii_pcs_config, ++ .pcs_get_state = mtk_usxgmii_pcs_get_state, ++ .pcs_an_restart = mtk_usxgmii_pcs_restart_an, ++ .pcs_link_up = mtk_usxgmii_pcs_link_up, ++}; ++ ++int mtk_usxgmii_init(struct mtk_eth *eth) ++{ ++ struct device_node *r = eth->dev->of_node; ++ struct device *dev = eth->dev; ++ struct device_node *np; ++ int i, ret; ++ ++ for (i = 0; i < MTK_MAX_DEVS; i++) { ++ np = of_parse_phandle(r, "mediatek,usxgmiisys", i); ++ if (!np) ++ break; ++ ++ eth->usxgmii_pcs[i] = devm_kzalloc(dev, sizeof(*eth->usxgmii_pcs[i]), GFP_KERNEL); ++ if (!eth->usxgmii_pcs[i]) ++ return -ENOMEM; ++ ++ eth->usxgmii_pcs[i]->id = i; ++ eth->usxgmii_pcs[i]->eth = eth; ++ eth->usxgmii_pcs[i]->regmap = syscon_node_to_regmap(np); ++ if (IS_ERR(eth->usxgmii_pcs[i]->regmap)) ++ return PTR_ERR(eth->usxgmii_pcs[i]->regmap); ++ ++ eth->usxgmii_pcs[i]->pcs.ops = &mtk_usxgmii_pcs_ops; ++ eth->usxgmii_pcs[i]->pcs.poll = true; ++ eth->usxgmii_pcs[i]->interface = PHY_INTERFACE_MODE_NA; ++ eth->usxgmii_pcs[i]->mode = -1; ++ ++ of_node_put(np); ++ } ++ ++ ret = mtk_xfi_pextp_init(eth); ++ if (ret) ++ return ret; ++ ++ ret = mtk_xfi_pll_init(eth); ++ if (ret) ++ return ret; ++ ++ ret = mtk_toprgu_init(eth); ++ if (ret) ++ return ret; ++ ++ return mtk_sgmii_wrapper_init(eth); ++} ++ ++struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int mac_id) ++{ ++ u32 xgmii_id = mtk_mac2xgmii_id(eth, mac_id); ++ ++ if (!eth->usxgmii_pcs[xgmii_id]->regmap) ++ return NULL; ++ ++ return ð->usxgmii_pcs[xgmii_id]->pcs; ++} diff --git a/target/linux/ipq40xx/patches-5.15/704-net-phy-define-PSGMII-PHY-interface-mode.patch b/target/linux/ipq40xx/patches-5.15/704-net-phy-define-PSGMII-PHY-interface-mode.patch index 7fbf38a7e34..ed5b7b60fb9 100644 --- a/target/linux/ipq40xx/patches-5.15/704-net-phy-define-PSGMII-PHY-interface-mode.patch +++ b/target/linux/ipq40xx/patches-5.15/704-net-phy-define-PSGMII-PHY-interface-mode.patch @@ -32,7 +32,7 @@ Signed-off-by: Gabor Juhos - rev-mii --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c -@@ -366,6 +366,7 @@ void phylink_get_linkmodes(unsigned long +@@ -371,6 +371,7 @@ void phylink_get_linkmodes(unsigned long case PHY_INTERFACE_MODE_RGMII_RXID: case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_RGMII: @@ -40,7 +40,7 @@ Signed-off-by: Gabor Juhos case PHY_INTERFACE_MODE_QSGMII: case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_GMII: -@@ -629,6 +630,7 @@ static int phylink_parse_mode(struct phy +@@ -634,6 +635,7 @@ static int phylink_parse_mode(struct phy switch (pl->link_config.interface) { case PHY_INTERFACE_MODE_SGMII: diff --git a/target/linux/layerscape/patches-5.15/702-phy-Add-2.5G-SGMII-interface-mode.patch b/target/linux/layerscape/patches-5.15/702-phy-Add-2.5G-SGMII-interface-mode.patch index 30fc56e6185..46c304032db 100644 --- a/target/linux/layerscape/patches-5.15/702-phy-Add-2.5G-SGMII-interface-mode.patch +++ b/target/linux/layerscape/patches-5.15/702-phy-Add-2.5G-SGMII-interface-mode.patch @@ -13,7 +13,7 @@ Signed-off-by: Bhaskar Upadhaya --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c -@@ -393,6 +393,7 @@ void phylink_get_linkmodes(unsigned long +@@ -398,6 +398,7 @@ void phylink_get_linkmodes(unsigned long caps |= MAC_1000FD; break; @@ -21,7 +21,7 @@ Signed-off-by: Bhaskar Upadhaya case PHY_INTERFACE_MODE_2500BASEX: caps |= MAC_2500FD; break; -@@ -646,6 +647,10 @@ static int phylink_parse_mode(struct phy +@@ -651,6 +652,10 @@ static int phylink_parse_mode(struct phy phylink_set(pl->supported, 2500baseX_Full); break; diff --git a/target/linux/mediatek/filogic/config-6.1 b/target/linux/mediatek/filogic/config-6.1 index 334dfa8502b..36cb9c1e4e6 100644 --- a/target/linux/mediatek/filogic/config-6.1 +++ b/target/linux/mediatek/filogic/config-6.1 @@ -4,7 +4,6 @@ CONFIG_AQUANTIA_PHY=y CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_FORCE_MAX_ORDER=11 CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_ARCH_MEDIATEK=y CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y @@ -150,7 +149,6 @@ CONFIG_FIT_PARTITION=y CONFIG_FIXED_PHY=y CONFIG_FIX_EARLYCON_MEM=y CONFIG_FRAME_POINTER=y -CONFIG_FRAME_WARN=2048 CONFIG_FS_IOMAP=y CONFIG_FS_MBCACHE=y CONFIG_FWNODE_MDIO=y @@ -324,6 +322,7 @@ CONFIG_PCS_MTK_LYNXI=y CONFIG_PERF_EVENTS=y CONFIG_PGTABLE_LEVELS=3 CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y CONFIG_PHYLINK=y CONFIG_PHYS_ADDR_T_64BIT=y # CONFIG_PHY_MTK_DP is not set diff --git a/target/linux/mediatek/patches-5.15/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch b/target/linux/mediatek/patches-5.15/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch index 84718d300b5..4c144a7b1ca 100644 --- a/target/linux/mediatek/patches-5.15/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch +++ b/target/linux/mediatek/patches-5.15/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch @@ -103,7 +103,7 @@ Signed-off-by: David S. Miller ret = mtk_mdio_busy_wait(eth); if (ret < 0) -@@ -1013,6 +1056,7 @@ static int mtk_mdio_init(struct mtk_eth +@@ -898,6 +941,7 @@ static int mtk_mdio_init(struct mtk_eth eth->mii_bus->name = "mdio"; eth->mii_bus->read = mtk_mdio_read; eth->mii_bus->write = mtk_mdio_write; @@ -113,7 +113,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -382,9 +382,12 @@ +@@ -402,9 +402,12 @@ #define PHY_IAC_ADDR_MASK GENMASK(24, 20) #define PHY_IAC_ADDR(x) FIELD_PREP(PHY_IAC_ADDR_MASK, (x)) #define PHY_IAC_CMD_MASK GENMASK(19, 18) diff --git a/target/linux/mediatek/patches-5.15/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch b/target/linux/mediatek/patches-5.15/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch index a455005504c..eed97b47694 100644 --- a/target/linux/mediatek/patches-5.15/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch +++ b/target/linux/mediatek/patches-5.15/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch @@ -22,7 +22,7 @@ Signed-off-by: Lorenzo Bianconi --- a/drivers/net/ethernet/mediatek/mtk_wed.c +++ b/drivers/net/ethernet/mediatek/mtk_wed.c -@@ -813,6 +813,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device +@@ -821,6 +821,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device struct device_node *np; int index; @@ -47,7 +47,7 @@ Signed-off-by: Lorenzo Bianconi index = of_property_match_string(dev->hw->node, "memory-region-names", "wo-dlm"); if (index < 0) -@@ -829,6 +847,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device +@@ -837,6 +855,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device return -ENODEV; dev->rro.miod_phys = rmem->base; diff --git a/target/linux/mediatek/patches-6.1/731-net-phy-mediatek-ge-soc-initialize-MT7988-PHY-LEDs-d.patch b/target/linux/mediatek/patches-6.1/731-net-phy-mediatek-ge-soc-initialize-MT7988-PHY-LEDs-d.patch deleted file mode 100644 index 83d0f26bf41..00000000000 --- a/target/linux/mediatek/patches-6.1/731-net-phy-mediatek-ge-soc-initialize-MT7988-PHY-LEDs-d.patch +++ /dev/null @@ -1,213 +0,0 @@ -From 5d2d78860f98eb5c03bc404eb024606878901ac8 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Tue, 13 Jun 2023 03:27:14 +0100 -Subject: [PATCH] net: phy: mediatek-ge-soc: initialize MT7988 PHY LEDs default - state - -Initialize LEDs and set sane default values. -Read boottrap register and apply LED polarities accordingly to get -uniform behavior from all LEDs on MT7988. -Requires syscon phandle 'mediatek,pio' present in parenting MDIO bus -which should point to the syscon holding the boottrap register. - -Signed-off-by: Daniel Golle ---- - drivers/net/phy/mediatek-ge-soc.c | 144 ++++++++++++++++++++++++++++-- - 1 file changed, 136 insertions(+), 8 deletions(-) - ---- a/drivers/net/phy/mediatek-ge-soc.c -+++ b/drivers/net/phy/mediatek-ge-soc.c -@@ -1,11 +1,13 @@ - // SPDX-License-Identifier: GPL-2.0+ - #include -+#include - #include - #include - #include - #include - #include - #include -+#include - - #define MTK_GPHY_ID_MT7981 0x03a29461 - #define MTK_GPHY_ID_MT7988 0x03a29481 -@@ -208,9 +210,40 @@ - #define MTK_PHY_DA_TX_R50_PAIR_C 0x53f - #define MTK_PHY_DA_TX_R50_PAIR_D 0x540 - -+/* Registers on MDIO_MMD_VEND2 */ -+#define MTK_PHY_LED0_ON_CTRL 0x24 -+#define MTK_PHY_LED1_ON_CTRL 0x26 -+#define MTK_PHY_LED_ON_MASK GENMASK(6, 0) -+#define MTK_PHY_LED_ON_LINK1000 BIT(0) -+#define MTK_PHY_LED_ON_LINK100 BIT(1) -+#define MTK_PHY_LED_ON_LINK10 BIT(2) -+#define MTK_PHY_LED_ON_LINKDOWN BIT(3) -+#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */ -+#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */ -+#define MTK_PHY_LED_FORCE_ON BIT(6) -+#define MTK_PHY_LED_POLARITY BIT(14) -+#define MTK_PHY_LED_ENABLE BIT(15) -+ -+#define MTK_PHY_LED0_BLINK_CTRL 0x25 -+#define MTK_PHY_LED1_BLINK_CTRL 0x27 -+#define MTK_PHY_LED_1000TX BIT(0) -+#define MTK_PHY_LED_1000RX BIT(1) -+#define MTK_PHY_LED_100TX BIT(2) -+#define MTK_PHY_LED_100RX BIT(3) -+#define MTK_PHY_LED_10TX BIT(4) -+#define MTK_PHY_LED_10RX BIT(5) -+#define MTK_PHY_LED_COLLISION BIT(6) -+#define MTK_PHY_LED_RX_CRC_ERR BIT(7) -+#define MTK_PHY_LED_RX_IDLE_ERR BIT(8) -+#define MTK_PHY_LED_FORCE_BLINK BIT(9) -+ - #define MTK_PHY_RG_BG_RASEL 0x115 - #define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0) - -+/* Register in boottrap syscon defining the initial state of the 4 PHY LEDs */ -+#define RG_GPIO_MISC_TPBANK0 0x6f0 -+#define RG_GPIO_MISC_TPBANK0_BOOTMODE GENMASK(11, 8) -+ - /* These macro privides efuse parsing for internal phy. */ - #define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0)) - #define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0)) -@@ -238,13 +271,6 @@ enum { - PAIR_D, - }; - --enum { -- GPHY_PORT0, -- GPHY_PORT1, -- GPHY_PORT2, -- GPHY_PORT3, --}; -- - enum calibration_mode { - EFUSE_K, - SW_K -@@ -263,6 +289,10 @@ enum CAL_MODE { - SW_M - }; - -+struct mtk_socphy_shared { -+ u32 boottrap; -+}; -+ - static int mtk_socphy_read_page(struct phy_device *phydev) - { - return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); -@@ -1073,6 +1103,104 @@ static int mt798x_phy_config_init(struct - return mt798x_phy_calibration(phydev); - } - -+static int mt798x_phy_setup_led(struct phy_device *phydev, bool inverted) -+{ -+ struct pinctrl *pinctrl; -+ const u16 led_on_ctrl_defaults = MTK_PHY_LED_ENABLE | -+ MTK_PHY_LED_ON_LINK1000 | -+ MTK_PHY_LED_ON_LINK100 | -+ MTK_PHY_LED_ON_LINK10; -+ const u16 led_blink_defaults = MTK_PHY_LED_1000TX | -+ MTK_PHY_LED_1000RX | -+ MTK_PHY_LED_100TX | -+ MTK_PHY_LED_100RX | -+ MTK_PHY_LED_10TX | -+ MTK_PHY_LED_10RX; -+ -+ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, -+ led_on_ctrl_defaults ^ -+ (inverted ? MTK_PHY_LED_POLARITY : 0)); -+ -+ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL, -+ led_on_ctrl_defaults); -+ -+ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_BLINK_CTRL, -+ led_blink_defaults); -+ -+ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_BLINK_CTRL, -+ led_blink_defaults); -+ -+ pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led"); -+ if (IS_ERR(pinctrl)) -+ dev_err(&phydev->mdio.bus->dev, "Failed to setup PHY LED\n"); -+ -+ return 0; -+} -+ -+static int mt7988_phy_probe_shared(struct phy_device *phydev) -+{ -+ struct device_node *np = dev_of_node(&phydev->mdio.bus->dev); -+ struct mtk_socphy_shared *priv = phydev->shared->priv; -+ struct regmap *regmap; -+ u32 reg; -+ int ret; -+ -+ /* The LED0 of the 4 PHYs in MT7988 are wired to SoC pins LED_A, LED_B, -+ * LED_C and LED_D respectively. At the same time those pins are used to -+ * bootstrap configuration of the reference clock source (LED_A), -+ * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D). -+ * In practise this is done using a LED and a resistor pulling the pin -+ * either to GND or to VIO. -+ * The detected value at boot time is accessible at run-time using the -+ * TPBANK0 register located in the gpio base of the pinctrl, in order -+ * to read it here it needs to be referenced by a phandle called -+ * 'mediatek,pio' in the MDIO bus hosting the PHY. -+ * The 4 bits in TPBANK0 are kept as package shared data and are used to -+ * set LED polarity for each of the LED0. -+ */ -+ regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,pio"); -+ if (IS_ERR(regmap)) -+ return PTR_ERR(regmap); -+ -+ ret = regmap_read(regmap, RG_GPIO_MISC_TPBANK0, ®); -+ if (ret) -+ return ret; -+ -+ priv->boottrap = FIELD_GET(RG_GPIO_MISC_TPBANK0_BOOTMODE, reg); -+ -+ return 0; -+} -+ -+static bool mt7988_phy_get_boottrap_polarity(struct phy_device *phydev) -+{ -+ struct mtk_socphy_shared *priv = phydev->shared->priv; -+ -+ if (priv->boottrap & BIT(phydev->mdio.addr)) -+ return false; -+ -+ return true; -+} -+ -+static int mt7988_phy_probe(struct phy_device *phydev) -+{ -+ int err; -+ -+ err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0, -+ sizeof(struct mtk_socphy_shared)); -+ if (err) -+ return err; -+ -+ if (phy_package_probe_once(phydev)) { -+ err = mt7988_phy_probe_shared(phydev); -+ if (err) -+ return err; -+ } -+ -+ mt798x_phy_setup_led(phydev, mt7988_phy_get_boottrap_polarity(phydev)); -+ -+ return mt798x_phy_calibration(phydev); -+} -+ - static struct phy_driver mtk_socphy_driver[] = { - { - PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), -@@ -1092,7 +1220,7 @@ static struct phy_driver mtk_socphy_driv - .config_init = mt798x_phy_config_init, - .config_intr = genphy_no_config_intr, - .handle_interrupt = genphy_handle_interrupt_no_ack, -- .probe = mt798x_phy_calibration, -+ .probe = mt7988_phy_probe, - .suspend = genphy_suspend, - .resume = genphy_resume, - .read_page = mtk_socphy_read_page, diff --git a/target/linux/mediatek/patches-6.1/731-v6.5-net-phy-mediatek-ge-soc-support-PHY-LEDs.patch b/target/linux/mediatek/patches-6.1/731-v6.5-net-phy-mediatek-ge-soc-support-PHY-LEDs.patch new file mode 100644 index 00000000000..286ce96a7de --- /dev/null +++ b/target/linux/mediatek/patches-6.1/731-v6.5-net-phy-mediatek-ge-soc-support-PHY-LEDs.patch @@ -0,0 +1,524 @@ +From c66937b0f8dbb4c6c043663c702b1053fb47fab2 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Mon, 14 Aug 2023 02:58:14 +0100 +Subject: [PATCH] net: phy: mediatek-ge-soc: support PHY LEDs + +Implement netdev trigger and primitive bliking offloading as well as +simple set_brigthness function for both PHY LEDs of the in-SoC PHYs +found in MT7981 and MT7988. + +For MT7988, read boottrap register and apply LED polarities accordingly +to get uniform behavior from all LEDs on MT7988. +This requires syscon phandle 'mediatek,pio' present in parenting MDIO bus +which should point to the syscon holding the boottrap register. + +Signed-off-by: Daniel Golle +Reviewed-by: Andrew Lunn +Link: https://lore.kernel.org/r/dc324d48c00cd7350f3a506eaa785324cae97372.1691977904.git.daniel@makrotopia.org +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/mediatek-ge-soc.c | 435 +++++++++++++++++++++++++++++- + 1 file changed, 426 insertions(+), 9 deletions(-) + +--- a/drivers/net/phy/mediatek-ge-soc.c ++++ b/drivers/net/phy/mediatek-ge-soc.c +@@ -1,11 +1,14 @@ + // SPDX-License-Identifier: GPL-2.0+ + #include ++#include ++#include + #include + #include + #include + #include + #include + #include ++#include + + #define MTK_GPHY_ID_MT7981 0x03a29461 + #define MTK_GPHY_ID_MT7988 0x03a29481 +@@ -208,9 +211,42 @@ + #define MTK_PHY_DA_TX_R50_PAIR_C 0x53f + #define MTK_PHY_DA_TX_R50_PAIR_D 0x540 + ++/* Registers on MDIO_MMD_VEND2 */ ++#define MTK_PHY_LED0_ON_CTRL 0x24 ++#define MTK_PHY_LED1_ON_CTRL 0x26 ++#define MTK_PHY_LED_ON_MASK GENMASK(6, 0) ++#define MTK_PHY_LED_ON_LINK1000 BIT(0) ++#define MTK_PHY_LED_ON_LINK100 BIT(1) ++#define MTK_PHY_LED_ON_LINK10 BIT(2) ++#define MTK_PHY_LED_ON_LINKDOWN BIT(3) ++#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */ ++#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */ ++#define MTK_PHY_LED_ON_FORCE_ON BIT(6) ++#define MTK_PHY_LED_ON_POLARITY BIT(14) ++#define MTK_PHY_LED_ON_ENABLE BIT(15) ++ ++#define MTK_PHY_LED0_BLINK_CTRL 0x25 ++#define MTK_PHY_LED1_BLINK_CTRL 0x27 ++#define MTK_PHY_LED_BLINK_1000TX BIT(0) ++#define MTK_PHY_LED_BLINK_1000RX BIT(1) ++#define MTK_PHY_LED_BLINK_100TX BIT(2) ++#define MTK_PHY_LED_BLINK_100RX BIT(3) ++#define MTK_PHY_LED_BLINK_10TX BIT(4) ++#define MTK_PHY_LED_BLINK_10RX BIT(5) ++#define MTK_PHY_LED_BLINK_COLLISION BIT(6) ++#define MTK_PHY_LED_BLINK_RX_CRC_ERR BIT(7) ++#define MTK_PHY_LED_BLINK_RX_IDLE_ERR BIT(8) ++#define MTK_PHY_LED_BLINK_FORCE_BLINK BIT(9) ++ ++#define MTK_PHY_LED1_DEFAULT_POLARITIES BIT(1) ++ + #define MTK_PHY_RG_BG_RASEL 0x115 + #define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0) + ++/* 'boottrap' register reflecting the configuration of the 4 PHY LEDs */ ++#define RG_GPIO_MISC_TPBANK0 0x6f0 ++#define RG_GPIO_MISC_TPBANK0_BOOTMODE GENMASK(11, 8) ++ + /* These macro privides efuse parsing for internal phy. */ + #define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0)) + #define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0)) +@@ -238,13 +274,6 @@ enum { + PAIR_D, + }; + +-enum { +- GPHY_PORT0, +- GPHY_PORT1, +- GPHY_PORT2, +- GPHY_PORT3, +-}; +- + enum calibration_mode { + EFUSE_K, + SW_K +@@ -263,6 +292,19 @@ enum CAL_MODE { + SW_M + }; + ++#define MTK_PHY_LED_STATE_FORCE_ON 0 ++#define MTK_PHY_LED_STATE_FORCE_BLINK 1 ++#define MTK_PHY_LED_STATE_NETDEV 2 ++ ++struct mtk_socphy_priv { ++ unsigned long led_state; ++}; ++ ++struct mtk_socphy_shared { ++ u32 boottrap; ++ struct mtk_socphy_priv priv[4]; ++}; ++ + static int mtk_socphy_read_page(struct phy_device *phydev) + { + return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); +@@ -1073,6 +1115,371 @@ static int mt798x_phy_config_init(struct + return mt798x_phy_calibration(phydev); + } + ++static int mt798x_phy_hw_led_on_set(struct phy_device *phydev, u8 index, ++ bool on) ++{ ++ unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0); ++ struct mtk_socphy_priv *priv = phydev->priv; ++ bool changed; ++ ++ if (on) ++ changed = !test_and_set_bit(bit_on, &priv->led_state); ++ else ++ changed = !!test_and_clear_bit(bit_on, &priv->led_state); ++ ++ changed |= !!test_and_clear_bit(MTK_PHY_LED_STATE_NETDEV + ++ (index ? 16 : 0), &priv->led_state); ++ if (changed) ++ return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? ++ MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL, ++ MTK_PHY_LED_ON_MASK, ++ on ? MTK_PHY_LED_ON_FORCE_ON : 0); ++ else ++ return 0; ++} ++ ++static int mt798x_phy_hw_led_blink_set(struct phy_device *phydev, u8 index, ++ bool blinking) ++{ ++ unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + (index ? 16 : 0); ++ struct mtk_socphy_priv *priv = phydev->priv; ++ bool changed; ++ ++ if (blinking) ++ changed = !test_and_set_bit(bit_blink, &priv->led_state); ++ else ++ changed = !!test_and_clear_bit(bit_blink, &priv->led_state); ++ ++ changed |= !!test_bit(MTK_PHY_LED_STATE_NETDEV + ++ (index ? 16 : 0), &priv->led_state); ++ if (changed) ++ return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? ++ MTK_PHY_LED1_BLINK_CTRL : MTK_PHY_LED0_BLINK_CTRL, ++ blinking ? MTK_PHY_LED_BLINK_FORCE_BLINK : 0); ++ else ++ return 0; ++} ++ ++static int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index, ++ unsigned long *delay_on, ++ unsigned long *delay_off) ++{ ++ bool blinking = false; ++ int err = 0; ++ ++ if (index > 1) ++ return -EINVAL; ++ ++ if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) { ++ blinking = true; ++ *delay_on = 50; ++ *delay_off = 50; ++ } ++ ++ err = mt798x_phy_hw_led_blink_set(phydev, index, blinking); ++ if (err) ++ return err; ++ ++ return mt798x_phy_hw_led_on_set(phydev, index, false); ++} ++ ++static int mt798x_phy_led_brightness_set(struct phy_device *phydev, ++ u8 index, enum led_brightness value) ++{ ++ int err; ++ ++ err = mt798x_phy_hw_led_blink_set(phydev, index, false); ++ if (err) ++ return err; ++ ++ return mt798x_phy_hw_led_on_set(phydev, index, (value != LED_OFF)); ++} ++ ++static const unsigned long supported_triggers = (BIT(TRIGGER_NETDEV_FULL_DUPLEX) | ++ BIT(TRIGGER_NETDEV_HALF_DUPLEX) | ++ BIT(TRIGGER_NETDEV_LINK) | ++ BIT(TRIGGER_NETDEV_LINK_10) | ++ BIT(TRIGGER_NETDEV_LINK_100) | ++ BIT(TRIGGER_NETDEV_LINK_1000) | ++ BIT(TRIGGER_NETDEV_RX) | ++ BIT(TRIGGER_NETDEV_TX)); ++ ++static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, ++ unsigned long rules) ++{ ++ if (index > 1) ++ return -EINVAL; ++ ++ /* All combinations of the supported triggers are allowed */ ++ if (rules & ~supported_triggers) ++ return -EOPNOTSUPP; ++ ++ return 0; ++}; ++ ++static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index, ++ unsigned long *rules) ++{ ++ unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + (index ? 16 : 0); ++ unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0); ++ unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0); ++ struct mtk_socphy_priv *priv = phydev->priv; ++ int on, blink; ++ ++ if (index > 1) ++ return -EINVAL; ++ ++ on = phy_read_mmd(phydev, MDIO_MMD_VEND2, ++ index ? MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL); ++ ++ if (on < 0) ++ return -EIO; ++ ++ blink = phy_read_mmd(phydev, MDIO_MMD_VEND2, ++ index ? MTK_PHY_LED1_BLINK_CTRL : ++ MTK_PHY_LED0_BLINK_CTRL); ++ if (blink < 0) ++ return -EIO; ++ ++ if ((on & (MTK_PHY_LED_ON_LINK1000 | MTK_PHY_LED_ON_LINK100 | ++ MTK_PHY_LED_ON_LINK10)) || ++ (blink & (MTK_PHY_LED_BLINK_1000RX | MTK_PHY_LED_BLINK_100RX | ++ MTK_PHY_LED_BLINK_10RX | MTK_PHY_LED_BLINK_1000TX | ++ MTK_PHY_LED_BLINK_100TX | MTK_PHY_LED_BLINK_10TX))) ++ set_bit(bit_netdev, &priv->led_state); ++ else ++ clear_bit(bit_netdev, &priv->led_state); ++ ++ if (on & MTK_PHY_LED_ON_FORCE_ON) ++ set_bit(bit_on, &priv->led_state); ++ else ++ clear_bit(bit_on, &priv->led_state); ++ ++ if (blink & MTK_PHY_LED_BLINK_FORCE_BLINK) ++ set_bit(bit_blink, &priv->led_state); ++ else ++ clear_bit(bit_blink, &priv->led_state); ++ ++ if (!rules) ++ return 0; ++ ++ if (on & (MTK_PHY_LED_ON_LINK1000 | MTK_PHY_LED_ON_LINK100 | MTK_PHY_LED_ON_LINK10)) ++ *rules |= BIT(TRIGGER_NETDEV_LINK); ++ ++ if (on & MTK_PHY_LED_ON_LINK10) ++ *rules |= BIT(TRIGGER_NETDEV_LINK_10); ++ ++ if (on & MTK_PHY_LED_ON_LINK100) ++ *rules |= BIT(TRIGGER_NETDEV_LINK_100); ++ ++ if (on & MTK_PHY_LED_ON_LINK1000) ++ *rules |= BIT(TRIGGER_NETDEV_LINK_1000); ++ ++ if (on & MTK_PHY_LED_ON_FDX) ++ *rules |= BIT(TRIGGER_NETDEV_FULL_DUPLEX); ++ ++ if (on & MTK_PHY_LED_ON_HDX) ++ *rules |= BIT(TRIGGER_NETDEV_HALF_DUPLEX); ++ ++ if (blink & (MTK_PHY_LED_BLINK_1000RX | MTK_PHY_LED_BLINK_100RX | MTK_PHY_LED_BLINK_10RX)) ++ *rules |= BIT(TRIGGER_NETDEV_RX); ++ ++ if (blink & (MTK_PHY_LED_BLINK_1000TX | MTK_PHY_LED_BLINK_100TX | MTK_PHY_LED_BLINK_10TX)) ++ *rules |= BIT(TRIGGER_NETDEV_TX); ++ ++ return 0; ++}; ++ ++static int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index, ++ unsigned long rules) ++{ ++ unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0); ++ struct mtk_socphy_priv *priv = phydev->priv; ++ u16 on = 0, blink = 0; ++ int ret; ++ ++ if (index > 1) ++ return -EINVAL; ++ ++ if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX)) ++ on |= MTK_PHY_LED_ON_FDX; ++ ++ if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX)) ++ on |= MTK_PHY_LED_ON_HDX; ++ ++ if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK))) ++ on |= MTK_PHY_LED_ON_LINK10; ++ ++ if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK))) ++ on |= MTK_PHY_LED_ON_LINK100; ++ ++ if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK))) ++ on |= MTK_PHY_LED_ON_LINK1000; ++ ++ if (rules & BIT(TRIGGER_NETDEV_RX)) { ++ blink |= MTK_PHY_LED_BLINK_10RX | ++ MTK_PHY_LED_BLINK_100RX | ++ MTK_PHY_LED_BLINK_1000RX; ++ } ++ ++ if (rules & BIT(TRIGGER_NETDEV_TX)) { ++ blink |= MTK_PHY_LED_BLINK_10TX | ++ MTK_PHY_LED_BLINK_100TX | ++ MTK_PHY_LED_BLINK_1000TX; ++ } ++ ++ if (blink || on) ++ set_bit(bit_netdev, &priv->led_state); ++ else ++ clear_bit(bit_netdev, &priv->led_state); ++ ++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? ++ MTK_PHY_LED1_ON_CTRL : ++ MTK_PHY_LED0_ON_CTRL, ++ MTK_PHY_LED_ON_FDX | ++ MTK_PHY_LED_ON_HDX | ++ MTK_PHY_LED_ON_LINK10 | ++ MTK_PHY_LED_ON_LINK100 | ++ MTK_PHY_LED_ON_LINK1000, ++ on); ++ ++ if (ret) ++ return ret; ++ ++ return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? ++ MTK_PHY_LED1_BLINK_CTRL : ++ MTK_PHY_LED0_BLINK_CTRL, blink); ++}; ++ ++static bool mt7988_phy_led_get_polarity(struct phy_device *phydev, int led_num) ++{ ++ struct mtk_socphy_shared *priv = phydev->shared->priv; ++ u32 polarities; ++ ++ if (led_num == 0) ++ polarities = ~(priv->boottrap); ++ else ++ polarities = MTK_PHY_LED1_DEFAULT_POLARITIES; ++ ++ if (polarities & BIT(phydev->mdio.addr)) ++ return true; ++ ++ return false; ++} ++ ++static int mt7988_phy_fix_leds_polarities(struct phy_device *phydev) ++{ ++ struct pinctrl *pinctrl; ++ int index; ++ ++ /* Setup LED polarity according to bootstrap use of LED pins */ ++ for (index = 0; index < 2; ++index) ++ phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? ++ MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL, ++ MTK_PHY_LED_ON_POLARITY, ++ mt7988_phy_led_get_polarity(phydev, index) ? ++ MTK_PHY_LED_ON_POLARITY : 0); ++ ++ /* Only now setup pinctrl to avoid bogus blinking */ ++ pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led"); ++ if (IS_ERR(pinctrl)) ++ dev_err(&phydev->mdio.bus->dev, "Failed to setup PHY LED pinctrl\n"); ++ ++ return 0; ++} ++ ++static int mt7988_phy_probe_shared(struct phy_device *phydev) ++{ ++ struct device_node *np = dev_of_node(&phydev->mdio.bus->dev); ++ struct mtk_socphy_shared *shared = phydev->shared->priv; ++ struct regmap *regmap; ++ u32 reg; ++ int ret; ++ ++ /* The LED0 of the 4 PHYs in MT7988 are wired to SoC pins LED_A, LED_B, ++ * LED_C and LED_D respectively. At the same time those pins are used to ++ * bootstrap configuration of the reference clock source (LED_A), ++ * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D). ++ * In practise this is done using a LED and a resistor pulling the pin ++ * either to GND or to VIO. ++ * The detected value at boot time is accessible at run-time using the ++ * TPBANK0 register located in the gpio base of the pinctrl, in order ++ * to read it here it needs to be referenced by a phandle called ++ * 'mediatek,pio' in the MDIO bus hosting the PHY. ++ * The 4 bits in TPBANK0 are kept as package shared data and are used to ++ * set LED polarity for each of the LED0. ++ */ ++ regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,pio"); ++ if (IS_ERR(regmap)) ++ return PTR_ERR(regmap); ++ ++ ret = regmap_read(regmap, RG_GPIO_MISC_TPBANK0, ®); ++ if (ret) ++ return ret; ++ ++ shared->boottrap = FIELD_GET(RG_GPIO_MISC_TPBANK0_BOOTMODE, reg); ++ ++ return 0; ++} ++ ++static void mt798x_phy_leds_state_init(struct phy_device *phydev) ++{ ++ int i; ++ ++ for (i = 0; i < 2; ++i) ++ mt798x_phy_led_hw_control_get(phydev, i, NULL); ++} ++ ++static int mt7988_phy_probe(struct phy_device *phydev) ++{ ++ struct mtk_socphy_shared *shared; ++ struct mtk_socphy_priv *priv; ++ int err; ++ ++ if (phydev->mdio.addr > 3) ++ return -EINVAL; ++ ++ err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0, ++ sizeof(struct mtk_socphy_shared)); ++ if (err) ++ return err; ++ ++ if (phy_package_probe_once(phydev)) { ++ err = mt7988_phy_probe_shared(phydev); ++ if (err) ++ return err; ++ } ++ ++ shared = phydev->shared->priv; ++ priv = &shared->priv[phydev->mdio.addr]; ++ ++ phydev->priv = priv; ++ ++ mt798x_phy_leds_state_init(phydev); ++ ++ err = mt7988_phy_fix_leds_polarities(phydev); ++ if (err) ++ return err; ++ ++ return mt798x_phy_calibration(phydev); ++} ++ ++static int mt7981_phy_probe(struct phy_device *phydev) ++{ ++ struct mtk_socphy_priv *priv; ++ ++ priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct mtk_socphy_priv), ++ GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ phydev->priv = priv; ++ ++ mt798x_phy_leds_state_init(phydev); ++ ++ return mt798x_phy_calibration(phydev); ++} ++ + static struct phy_driver mtk_socphy_driver[] = { + { + PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), +@@ -1080,11 +1487,16 @@ static struct phy_driver mtk_socphy_driv + .config_init = mt798x_phy_config_init, + .config_intr = genphy_no_config_intr, + .handle_interrupt = genphy_handle_interrupt_no_ack, +- .probe = mt798x_phy_calibration, ++ .probe = mt7981_phy_probe, + .suspend = genphy_suspend, + .resume = genphy_resume, + .read_page = mtk_socphy_read_page, + .write_page = mtk_socphy_write_page, ++ .led_blink_set = mt798x_phy_led_blink_set, ++ .led_brightness_set = mt798x_phy_led_brightness_set, ++ .led_hw_is_supported = mt798x_phy_led_hw_is_supported, ++ .led_hw_control_set = mt798x_phy_led_hw_control_set, ++ .led_hw_control_get = mt798x_phy_led_hw_control_get, + }, + { + PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988), +@@ -1092,11 +1504,16 @@ static struct phy_driver mtk_socphy_driv + .config_init = mt798x_phy_config_init, + .config_intr = genphy_no_config_intr, + .handle_interrupt = genphy_handle_interrupt_no_ack, +- .probe = mt798x_phy_calibration, ++ .probe = mt7988_phy_probe, + .suspend = genphy_suspend, + .resume = genphy_resume, + .read_page = mtk_socphy_read_page, + .write_page = mtk_socphy_write_page, ++ .led_blink_set = mt798x_phy_led_blink_set, ++ .led_brightness_set = mt798x_phy_led_brightness_set, ++ .led_hw_is_supported = mt798x_phy_led_hw_is_supported, ++ .led_hw_control_set = mt798x_phy_led_hw_control_set, ++ .led_hw_control_get = mt798x_phy_led_hw_control_get, + }, + }; + diff --git a/target/linux/mediatek/patches-6.1/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch b/target/linux/mediatek/patches-6.1/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch index fb3940f5447..209580d64a4 100644 --- a/target/linux/mediatek/patches-6.1/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch +++ b/target/linux/mediatek/patches-6.1/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch @@ -22,7 +22,7 @@ Signed-off-by: Lorenzo Bianconi --- a/drivers/net/ethernet/mediatek/mtk_wed.c +++ b/drivers/net/ethernet/mediatek/mtk_wed.c -@@ -806,6 +806,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device +@@ -814,6 +814,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device struct device_node *np; int index; @@ -47,7 +47,7 @@ Signed-off-by: Lorenzo Bianconi index = of_property_match_string(dev->hw->node, "memory-region-names", "wo-dlm"); if (index < 0) -@@ -822,6 +840,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device +@@ -830,6 +848,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device return -ENODEV; dev->rro.miod_phys = rmem->base; diff --git a/target/linux/ramips/patches-5.15/700-net-ethernet-mediatek-support-net-labels.patch b/target/linux/ramips/patches-5.15/700-net-ethernet-mediatek-support-net-labels.patch index fce5fc856f4..c458237f390 100644 --- a/target/linux/ramips/patches-5.15/700-net-ethernet-mediatek-support-net-labels.patch +++ b/target/linux/ramips/patches-5.15/700-net-ethernet-mediatek-support-net-labels.patch @@ -14,7 +14,7 @@ Signed-off-by: René van Dorst --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -4615,6 +4615,7 @@ static const struct net_device_ops mtk_n +@@ -4553,6 +4553,7 @@ static const struct net_device_ops mtk_n static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) { @@ -22,7 +22,7 @@ Signed-off-by: René van Dorst const __be32 *_id = of_get_property(np, "reg", NULL); phy_interface_t phy_mode; struct phylink *phylink; -@@ -4784,6 +4785,9 @@ static int mtk_add_mac(struct mtk_eth *e +@@ -4724,6 +4725,9 @@ static int mtk_add_mac(struct mtk_eth *e register_netdevice_notifier(&mac->device_notifier); } diff --git a/target/linux/ramips/patches-5.15/720-Revert-net-phy-simplify-phy_link_change-arguments.patch b/target/linux/ramips/patches-5.15/720-Revert-net-phy-simplify-phy_link_change-arguments.patch index 87f319abb56..b8461b0030c 100644 --- a/target/linux/ramips/patches-5.15/720-Revert-net-phy-simplify-phy_link_change-arguments.patch +++ b/target/linux/ramips/patches-5.15/720-Revert-net-phy-simplify-phy_link_change-arguments.patch @@ -95,7 +95,7 @@ still required by target/linux/ramips/files/drivers/net/ethernet/ralink/mdio.c phydev->mii_ts->link_state(phydev->mii_ts, phydev); --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c -@@ -1322,7 +1322,8 @@ void phylink_destroy(struct phylink *pl) +@@ -1369,7 +1369,8 @@ void phylink_destroy(struct phylink *pl) } EXPORT_SYMBOL_GPL(phylink_destroy); diff --git a/target/linux/realtek/patches-5.15/704-drivers-net-phy-eee-support-for-rtl838x.patch b/target/linux/realtek/patches-5.15/704-drivers-net-phy-eee-support-for-rtl838x.patch index 591f0cea13a..183c9dda2fd 100644 --- a/target/linux/realtek/patches-5.15/704-drivers-net-phy-eee-support-for-rtl838x.patch +++ b/target/linux/realtek/patches-5.15/704-drivers-net-phy-eee-support-for-rtl838x.patch @@ -21,7 +21,7 @@ Submitted-by: John Crispin --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c -@@ -1942,6 +1942,11 @@ int phylink_ethtool_ksettings_set(struct +@@ -1990,6 +1990,11 @@ int phylink_ethtool_ksettings_set(struct * the presence of a PHY, this should not be changed as that * should be determined from the media side advertisement. */ @@ -33,7 +33,7 @@ Submitted-by: John Crispin return phy_ethtool_ksettings_set(pl->phydev, kset); } -@@ -2245,8 +2250,11 @@ int phylink_ethtool_get_eee(struct phyli +@@ -2293,8 +2298,11 @@ int phylink_ethtool_get_eee(struct phyli ASSERT_RTNL(); @@ -46,7 +46,7 @@ Submitted-by: John Crispin return ret; } -@@ -2263,8 +2271,11 @@ int phylink_ethtool_set_eee(struct phyli +@@ -2311,8 +2319,11 @@ int phylink_ethtool_set_eee(struct phyli ASSERT_RTNL(); diff --git a/target/linux/realtek/patches-5.15/704-include-linux-add-phy-hsgmii-mode.patch b/target/linux/realtek/patches-5.15/704-include-linux-add-phy-hsgmii-mode.patch index f9411e47d32..2048e22f2e5 100644 --- a/target/linux/realtek/patches-5.15/704-include-linux-add-phy-hsgmii-mode.patch +++ b/target/linux/realtek/patches-5.15/704-include-linux-add-phy-hsgmii-mode.patch @@ -15,7 +15,7 @@ Submitted-by: Birger Koblitz --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c -@@ -403,6 +403,7 @@ void phylink_get_linkmodes(unsigned long +@@ -408,6 +408,7 @@ void phylink_get_linkmodes(unsigned long case PHY_INTERFACE_MODE_XGMII: case PHY_INTERFACE_MODE_RXAUI: @@ -23,7 +23,7 @@ Submitted-by: Birger Koblitz case PHY_INTERFACE_MODE_XAUI: case PHY_INTERFACE_MODE_10GBASER: case PHY_INTERFACE_MODE_10GKR: -@@ -657,6 +658,7 @@ static int phylink_parse_mode(struct phy +@@ -662,6 +663,7 @@ static int phylink_parse_mode(struct phy fallthrough; case PHY_INTERFACE_MODE_USXGMII: case PHY_INTERFACE_MODE_10GKR: From 8f5986355cdc5df921ef8232f559ca7bfb18f1ed Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Mon, 28 Aug 2023 21:54:02 +0100 Subject: [PATCH 26/29] mediatek: filogic: remove stray quote When adapting the network configuration for MT7988 RFB a stray quote was left in a script. Remove it to fix generating the default network configuration. Signed-off-by: Daniel Golle --- target/linux/mediatek/filogic/base-files/etc/board.d/02_network | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network index 1ea2ada0984..e5872e7fe4d 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network @@ -37,7 +37,7 @@ mediatek_setup_interfaces() ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3" eth1 ;; mediatek,mt7988a-rfb) - ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3 eth1" eth2" + ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3 eth1" eth2 ;; mercusys,mr90x-v1) ucidef_set_interfaces_lan_wan "lan0 lan1 lan2" eth1 From 49eedc146aae1e9db98c317f218e1c06dc089e25 Mon Sep 17 00:00:00 2001 From: Linhui Liu Date: Sat, 26 Aug 2023 13:56:53 +0800 Subject: [PATCH 27/29] tools/mpfr: update to 4.2.1 Changes from version 4.2.0 to version 4.2.1: - Bug fixes (see and/or the ChangeLog file). - Improved MPFR manual. - Configure tests: replaced the test of the link with GMP, in order to avoid the use of a function without a prototype (Autoconf issue), as this is obsolescent in ISO C. The new test should be more robust. Signed-off-by: Linhui Liu --- tools/mpfr/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/mpfr/Makefile b/tools/mpfr/Makefile index cdcca5f11af..e7f5106a672 100644 --- a/tools/mpfr/Makefile +++ b/tools/mpfr/Makefile @@ -7,12 +7,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=mpfr -PKG_VERSION:=4.2.0 +PKG_VERSION:=4.2.1 PKG_CPE_ID:=cpe:/a:mpfr:gnu_mpfr PKG_SOURCE_URL:=@GNU/mpfr http://www.mpfr.org/mpfr-$(PKG_VERSION) PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz -PKG_HASH:=06a378df13501248c1b2db5aa977a2c8126ae849a9d9b7be2546fb4a9c26d993 +PKG_HASH:=277807353a6726978996945af13e52829e3abd7a9a5b7fb2793894e18f1fcbb2 HOST_BUILD_PARALLEL:=1 HOST_FIXUP:=autoreconf From 78e3adcaf993cd1a58821a69efccfca8d380f754 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Mon, 28 Aug 2023 23:41:43 +0100 Subject: [PATCH 28/29] uboot-mediatek: fix dependency on TF-A for MT7988 RFB (sdmmc) The U-Boot build for the MT7988 reference board booting from SD card wrongly depended on the 'ddr4' variant of the ARM TrustedFirmware-A build even though the 'comb' variant is used. Fix that dependency. Fixes: 572ea68070 ("uboot-mediatek: add patches for MT7988 and builds for RFB") Signed-off-by: Daniel Golle --- package/boot/uboot-mediatek/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/package/boot/uboot-mediatek/Makefile b/package/boot/uboot-mediatek/Makefile index 021d444a97a..66de3921852 100644 --- a/package/boot/uboot-mediatek/Makefile +++ b/package/boot/uboot-mediatek/Makefile @@ -403,7 +403,7 @@ define U-Boot/mt7988_rfb-sd BL2_BOOTDEV:=sdmmc BL2_SOC:=mt7988 BL2_DDRTYPE:=comb - DEPENDS:=+trusted-firmware-a-mt7988-sdmmc-ddr4 + DEPENDS:=+trusted-firmware-a-mt7988-sdmmc-comb endef UBOOT_TARGETS := \ From 33046d2a471ed687404a617c356b9cdf5652c2d6 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Mon, 28 Aug 2023 23:44:52 +0100 Subject: [PATCH 29/29] arm-trusted-firmware-mediatek: enable built-in 2.5G PHY on MT7988 Always enable built-in 2.5G PHY on MT7988 for now, so that it can be used. In future it would be nice to be able to switch power and MDIO access via address 0 at run-time in Linux, both, to be able to use external PHYs at address 0 and to reduce power consumption on systems not using the built-in 2.5G PHY. Signed-off-by: Daniel Golle --- .../patches/001-mt7988-enable-2p5g-phy.patch | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 package/boot/arm-trusted-firmware-mediatek/patches/001-mt7988-enable-2p5g-phy.patch diff --git a/package/boot/arm-trusted-firmware-mediatek/patches/001-mt7988-enable-2p5g-phy.patch b/package/boot/arm-trusted-firmware-mediatek/patches/001-mt7988-enable-2p5g-phy.patch new file mode 100644 index 00000000000..d377bd8433c --- /dev/null +++ b/package/boot/arm-trusted-firmware-mediatek/patches/001-mt7988-enable-2p5g-phy.patch @@ -0,0 +1,11 @@ +--- a/plat/mediatek/mt7988/bl2/bl2_plat_init.c ++++ b/plat/mediatek/mt7988/bl2/bl2_plat_init.c +@@ -90,6 +90,8 @@ static void mtk_i2p5g_phy_init(void) + * clear bit 22 to use external MDIO. + */ + mmio_setbits_32(GBE_TOP_REG, I2P5G_MDIO); ++ /* Internal 2.5Gphy power on sequence */ ++ eth_2p5g_phy_mtcmos_ctrl(true); + } + + static void mt7988_i2c_init(void)