diff --git a/target/linux/qualcommax/patches-6.12/0001-v6.7-dt-bindings-arm-qcom-ids-Add-IDs-for-IPQ8174-family.patch b/target/linux/qualcommax/patches-6.12/0001-v6.7-dt-bindings-arm-qcom-ids-Add-IDs-for-IPQ8174-family.patch deleted file mode 100644 index c1381a7bf3c..00000000000 --- a/target/linux/qualcommax/patches-6.12/0001-v6.7-dt-bindings-arm-qcom-ids-Add-IDs-for-IPQ8174-family.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 93e161c8f4b9b051e5e746814138cb5520b4b897 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 1 Sep 2023 20:10:04 +0200 -Subject: [PATCH] dt-bindings: arm: qcom,ids: Add IDs for IPQ8174 family - -IPQ8174 (Oak) family is part of the IPQ8074 family, but the ID-s for it -are missing so lets add them. - -Signed-off-by: Robert Marko -Reviewed-by: Kathiravan T -Acked-by: Conor Dooley -Link: https://lore.kernel.org/r/20230901181041.1538999-1-robimarko@gmail.com -Signed-off-by: Bjorn Andersson ---- - include/dt-bindings/arm/qcom,ids.h | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/include/dt-bindings/arm/qcom,ids.h -+++ b/include/dt-bindings/arm/qcom,ids.h -@@ -203,6 +203,9 @@ - #define QCOM_ID_SM6125 394 - #define QCOM_ID_IPQ8070A 395 - #define QCOM_ID_IPQ8071A 396 -+#define QCOM_ID_IPQ8172 397 -+#define QCOM_ID_IPQ8173 398 -+#define QCOM_ID_IPQ8174 399 - #define QCOM_ID_IPQ6018 402 - #define QCOM_ID_IPQ6028 403 - #define QCOM_ID_SDM429W 416 diff --git a/target/linux/qualcommax/patches-6.12/0002-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ6018.patch b/target/linux/qualcommax/patches-6.12/0002-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ6018.patch deleted file mode 100644 index 95c6c9505d6..00000000000 --- a/target/linux/qualcommax/patches-6.12/0002-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ6018.patch +++ /dev/null @@ -1,123 +0,0 @@ -From 47e161a7873b0891f4e01a69a839f6161d816ea8 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 25 Oct 2023 14:57:57 +0530 -Subject: [PATCH] cpufreq: qcom-nvmem: add support for IPQ6018 - -IPQ6018 SoC series comes in multiple SKU-s, and not all of them support -high frequency OPP points. - -SoC itself does however have a single bit in QFPROM to indicate the CPU -speed-bin. -That bit is used to indicate frequency limit of 1.5GHz, but that alone is -not enough as IPQ6000 only goes up to 1.2GHz, but SMEM ID can be used to -limit it further. - -IPQ6018 compatible is blacklisted from DT platdev as the cpufreq device -will get created by NVMEM CPUFreq driver. - -Signed-off-by: Robert Marko -[ Viresh: Fixed rebase conflict. ] -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/cpufreq-dt-platdev.c | 1 + - drivers/cpufreq/qcom-cpufreq-nvmem.c | 58 ++++++++++++++++++++++++++++ - 2 files changed, 59 insertions(+) - ---- a/drivers/cpufreq/cpufreq-dt-platdev.c -+++ b/drivers/cpufreq/cpufreq-dt-platdev.c -@@ -177,6 +177,7 @@ static const struct of_device_id blockli - { .compatible = "ti,am625", }, - { .compatible = "ti,am62a7", }, - -+ { .compatible = "qcom,ipq6018", }, - { .compatible = "qcom,ipq8064", }, - { .compatible = "qcom,apq8064", }, - { .compatible = "qcom,msm8974", }, ---- a/drivers/cpufreq/qcom-cpufreq-nvmem.c -+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c -@@ -30,6 +30,8 @@ - - #include - -+#define IPQ6000_VERSION BIT(2) -+ - struct qcom_cpufreq_drv; - - struct qcom_cpufreq_match_data { -@@ -207,6 +209,57 @@ len_error: - return ret; - } - -+static int qcom_cpufreq_ipq6018_name_version(struct device *cpu_dev, -+ struct nvmem_cell *speedbin_nvmem, -+ char **pvs_name, -+ struct qcom_cpufreq_drv *drv) -+{ -+ u32 msm_id; -+ int ret; -+ u8 *speedbin; -+ *pvs_name = NULL; -+ -+ ret = qcom_smem_get_soc_id(&msm_id); -+ if (ret) -+ return ret; -+ -+ speedbin = nvmem_cell_read(speedbin_nvmem, NULL); -+ if (IS_ERR(speedbin)) -+ return PTR_ERR(speedbin); -+ -+ switch (msm_id) { -+ case QCOM_ID_IPQ6005: -+ case QCOM_ID_IPQ6010: -+ case QCOM_ID_IPQ6018: -+ case QCOM_ID_IPQ6028: -+ /* Fuse Value Freq BIT to set -+ * --------------------------------- -+ * 2’b0 No Limit BIT(0) -+ * 2’b1 1.5 GHz BIT(1) -+ */ -+ drv->versions = 1 << (unsigned int)(*speedbin); -+ break; -+ case QCOM_ID_IPQ6000: -+ /* -+ * IPQ6018 family only has one bit to advertise the CPU -+ * speed-bin, but that is not enough for IPQ6000 which -+ * is only rated up to 1.2GHz. -+ * So for IPQ6000 manually set BIT(2) based on SMEM ID. -+ */ -+ drv->versions = IPQ6000_VERSION; -+ break; -+ default: -+ dev_err(cpu_dev, -+ "SoC ID %u is not part of IPQ6018 family, limiting to 1.2GHz!\n", -+ msm_id); -+ drv->versions = IPQ6000_VERSION; -+ break; -+ } -+ -+ kfree(speedbin); -+ return 0; -+} -+ - static const struct qcom_cpufreq_match_data match_data_kryo = { - .get_version = qcom_cpufreq_kryo_name_version, - }; -@@ -221,6 +274,10 @@ static const struct qcom_cpufreq_match_d - .genpd_names = qcs404_genpd_names, - }; - -+static const struct qcom_cpufreq_match_data match_data_ipq6018 = { -+ .get_version = qcom_cpufreq_ipq6018_name_version, -+}; -+ - static int qcom_cpufreq_probe(struct platform_device *pdev) - { - struct qcom_cpufreq_drv *drv; -@@ -353,6 +410,7 @@ static const struct of_device_id qcom_cp - { .compatible = "qcom,apq8096", .data = &match_data_kryo }, - { .compatible = "qcom,msm8996", .data = &match_data_kryo }, - { .compatible = "qcom,qcs404", .data = &match_data_qcs404 }, -+ { .compatible = "qcom,ipq6018", .data = &match_data_ipq6018 }, - { .compatible = "qcom,ipq8064", .data = &match_data_krait }, - { .compatible = "qcom,apq8064", .data = &match_data_krait }, - { .compatible = "qcom,msm8974", .data = &match_data_krait }, diff --git a/target/linux/qualcommax/patches-6.12/0003-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ8074.patch b/target/linux/qualcommax/patches-6.12/0003-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ8074.patch deleted file mode 100644 index 56400384047..00000000000 --- a/target/linux/qualcommax/patches-6.12/0003-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ8074.patch +++ /dev/null @@ -1,113 +0,0 @@ -From 0b9cd949136f1b63f7aa9424b6e583a1ab261e36 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 13 Oct 2023 19:20:02 +0200 -Subject: [PATCH] cpufreq: qcom-nvmem: add support for IPQ8074 - -IPQ8074 comes in 3 families: -* IPQ8070A/IPQ8071A (Acorn) up to 1.4GHz -* IPQ8172/IPQ8173/IPQ8174 (Oak) up to 1.4GHz -* IPQ8072A/IPQ8074A/IPQ8076A/IPQ8078A (Hawkeye) up to 2.2GHz - -So, in order to be able to share one OPP table lets add support for IPQ8074 -family based of SMEM SoC ID-s as speedbin fuse is always 0 on IPQ8074. - -IPQ8074 compatible is blacklisted from DT platdev as the cpufreq device -will get created by NVMEM CPUFreq driver. - -Signed-off-by: Robert Marko -Acked-by: Konrad Dybcio -[ Viresh: Fixed rebase conflict. ] -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/cpufreq-dt-platdev.c | 1 + - drivers/cpufreq/qcom-cpufreq-nvmem.c | 48 ++++++++++++++++++++++++++++ - 2 files changed, 49 insertions(+) - ---- a/drivers/cpufreq/cpufreq-dt-platdev.c -+++ b/drivers/cpufreq/cpufreq-dt-platdev.c -@@ -179,6 +179,7 @@ static const struct of_device_id blockli - - { .compatible = "qcom,ipq6018", }, - { .compatible = "qcom,ipq8064", }, -+ { .compatible = "qcom,ipq8074", }, - { .compatible = "qcom,apq8064", }, - { .compatible = "qcom,msm8974", }, - { .compatible = "qcom,msm8960", }, ---- a/drivers/cpufreq/qcom-cpufreq-nvmem.c -+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c -@@ -32,6 +32,11 @@ - - #define IPQ6000_VERSION BIT(2) - -+enum ipq8074_versions { -+ IPQ8074_HAWKEYE_VERSION = 0, -+ IPQ8074_ACORN_VERSION, -+}; -+ - struct qcom_cpufreq_drv; - - struct qcom_cpufreq_match_data { -@@ -260,6 +265,44 @@ static int qcom_cpufreq_ipq6018_name_ver - return 0; - } - -+static int qcom_cpufreq_ipq8074_name_version(struct device *cpu_dev, -+ struct nvmem_cell *speedbin_nvmem, -+ char **pvs_name, -+ struct qcom_cpufreq_drv *drv) -+{ -+ u32 msm_id; -+ int ret; -+ *pvs_name = NULL; -+ -+ ret = qcom_smem_get_soc_id(&msm_id); -+ if (ret) -+ return ret; -+ -+ switch (msm_id) { -+ case QCOM_ID_IPQ8070A: -+ case QCOM_ID_IPQ8071A: -+ case QCOM_ID_IPQ8172: -+ case QCOM_ID_IPQ8173: -+ case QCOM_ID_IPQ8174: -+ drv->versions = BIT(IPQ8074_ACORN_VERSION); -+ break; -+ case QCOM_ID_IPQ8072A: -+ case QCOM_ID_IPQ8074A: -+ case QCOM_ID_IPQ8076A: -+ case QCOM_ID_IPQ8078A: -+ drv->versions = BIT(IPQ8074_HAWKEYE_VERSION); -+ break; -+ default: -+ dev_err(cpu_dev, -+ "SoC ID %u is not part of IPQ8074 family, limiting to 1.4GHz!\n", -+ msm_id); -+ drv->versions = BIT(IPQ8074_ACORN_VERSION); -+ break; -+ } -+ -+ return 0; -+} -+ - static const struct qcom_cpufreq_match_data match_data_kryo = { - .get_version = qcom_cpufreq_kryo_name_version, - }; -@@ -278,6 +321,10 @@ static const struct qcom_cpufreq_match_d - .get_version = qcom_cpufreq_ipq6018_name_version, - }; - -+static const struct qcom_cpufreq_match_data match_data_ipq8074 = { -+ .get_version = qcom_cpufreq_ipq8074_name_version, -+}; -+ - static int qcom_cpufreq_probe(struct platform_device *pdev) - { - struct qcom_cpufreq_drv *drv; -@@ -412,6 +459,7 @@ static const struct of_device_id qcom_cp - { .compatible = "qcom,qcs404", .data = &match_data_qcs404 }, - { .compatible = "qcom,ipq6018", .data = &match_data_ipq6018 }, - { .compatible = "qcom,ipq8064", .data = &match_data_krait }, -+ { .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 }, - { .compatible = "qcom,apq8064", .data = &match_data_krait }, - { .compatible = "qcom,msm8974", .data = &match_data_krait }, - { .compatible = "qcom,msm8960", .data = &match_data_krait }, diff --git a/target/linux/qualcommax/patches-6.12/0004-v6.7-clk-qcom-apss-ipq6018-add-the-GPLL0-clock-also-as-cl.patch b/target/linux/qualcommax/patches-6.12/0004-v6.7-clk-qcom-apss-ipq6018-add-the-GPLL0-clock-also-as-cl.patch deleted file mode 100644 index ddd53f9d427..00000000000 --- a/target/linux/qualcommax/patches-6.12/0004-v6.7-clk-qcom-apss-ipq6018-add-the-GPLL0-clock-also-as-cl.patch +++ /dev/null @@ -1,43 +0,0 @@ -From c917237a7cb17b97cc48e073881a9873f3caeaa2 Mon Sep 17 00:00:00 2001 -From: Kathiravan Thirumoorthy -Date: Thu, 14 Sep 2023 12:29:57 +0530 -Subject: [PATCH] clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock - provider - -While the kernel is booting up, APSS PLL will be running at 800MHz with -GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be -configured and select the rate based on the opp table and the source will -be changed to APSS_PLL_EARLY. - -Without this patch, CPU Freq driver reports that CPU is running at 24MHz -instead of the 800MHz. - -Reviewed-by: Konrad Dybcio -Tested-by: Robert Marko -Signed-off-by: Kathiravan Thirumoorthy ---- - drivers/clk/qcom/apss-ipq6018.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/clk/qcom/apss-ipq6018.c -+++ b/drivers/clk/qcom/apss-ipq6018.c -@@ -20,16 +20,19 @@ - - enum { - P_XO, -+ P_GPLL0, - P_APSS_PLL_EARLY, - }; - - static const struct clk_parent_data parents_apcs_alias0_clk_src[] = { - { .fw_name = "xo" }, -+ { .fw_name = "gpll0" }, - { .fw_name = "pll" }, - }; - - static const struct parent_map parents_apcs_alias0_clk_src_map[] = { - { P_XO, 0 }, -+ { P_GPLL0, 4 }, - { P_APSS_PLL_EARLY, 5 }, - }; - diff --git a/target/linux/qualcommax/patches-6.12/0005-v6.7-arm64-dts-qcom-ipq8074-include-the-GPLL0-as-clock-pr.patch b/target/linux/qualcommax/patches-6.12/0005-v6.7-arm64-dts-qcom-ipq8074-include-the-GPLL0-as-clock-pr.patch deleted file mode 100644 index 6b7dd2f2616..00000000000 --- a/target/linux/qualcommax/patches-6.12/0005-v6.7-arm64-dts-qcom-ipq8074-include-the-GPLL0-as-clock-pr.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 3b48a7d925a757b3fa53c04baaf68bb8313c3ffb Mon Sep 17 00:00:00 2001 -From: Kathiravan Thirumoorthy -Date: Thu, 14 Sep 2023 12:29:58 +0530 -Subject: [PATCH] arm64: dts: qcom: ipq8074: include the GPLL0 as clock - provider for mailbox - -While the kernel is booting up, APSS PLL will be running at 800MHz with -GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be -configured to the rate based on the opp table and the source also will -be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0, -with this inclusion, CPU Freq correctly reports that CPU is running at -800MHz rather than 24MHz. - -Signed-off-by: Kathiravan Thirumoorthy -Reviewed-by: Konrad Dybcio ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -723,8 +723,8 @@ - compatible = "qcom,ipq8074-apcs-apps-global", - "qcom,ipq6018-apcs-apps-global"; - reg = <0x0b111000 0x1000>; -- clocks = <&a53pll>, <&xo>; -- clock-names = "pll", "xo"; -+ clocks = <&a53pll>, <&xo>, <&gcc GPLL0>; -+ clock-names = "pll", "xo", "gpll0"; - - #clock-cells = <1>; - #mbox-cells = <1>; diff --git a/target/linux/qualcommax/patches-6.12/0006-v6.7-arm64-dts-qcom-ipq6018-include-the-GPLL0-as.patch b/target/linux/qualcommax/patches-6.12/0006-v6.7-arm64-dts-qcom-ipq6018-include-the-GPLL0-as.patch deleted file mode 100644 index d407b9c5c49..00000000000 --- a/target/linux/qualcommax/patches-6.12/0006-v6.7-arm64-dts-qcom-ipq6018-include-the-GPLL0-as.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 0133c7af3aa0420778d106cb90db708cfa45f2c6 Mon Sep 17 00:00:00 2001 -From: Kathiravan Thirumoorthy -Date: Thu, 14 Sep 2023 12:29:59 +0530 -Subject: [PATCH] arm64: dts: qcom: ipq6018: include the GPLL0 as clock - provider for mailbox - -While the kernel is booting up, APSS clock / CPU clock will be running -at 800MHz with GPLL0 as source. Once the cpufreq driver is available, -APSS PLL will be configured to the rate based on the opp table and the -source also will be changed to APSS_PLL_EARLY. So allow the mailbox to -consume the GPLL0, with this inclusion, CPU Freq correctly reports that -CPU is running at 800MHz rather than 24MHz. - -Signed-off-by: Kathiravan Thirumoorthy -Reviewed-by: Konrad Dybcio -Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-9-c8ceb1a37680@quicinc.com -[bjorn: Updated commit message, as requested by Kathiravan] -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -620,8 +620,8 @@ - compatible = "qcom,ipq6018-apcs-apps-global"; - reg = <0x0 0x0b111000 0x0 0x1000>; - #clock-cells = <1>; -- clocks = <&a53pll>, <&xo>; -- clock-names = "pll", "xo"; -+ clocks = <&a53pll>, <&xo>, <&gcc GPLL0>; -+ clock-names = "pll", "xo", "gpll0"; - #mbox-cells = <1>; - }; - diff --git a/target/linux/qualcommax/patches-6.12/0007-v6.7-clk-qcom-gcc-ipq6018-add-QUP6-I2C-clock.patch b/target/linux/qualcommax/patches-6.12/0007-v6.7-clk-qcom-gcc-ipq6018-add-QUP6-I2C-clock.patch deleted file mode 100644 index eb68b87640b..00000000000 --- a/target/linux/qualcommax/patches-6.12/0007-v6.7-clk-qcom-gcc-ipq6018-add-QUP6-I2C-clock.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 3dcf7b59393812a5fbd83f8cd8d34b94afb4c4d1 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Sat, 21 Oct 2023 13:55:18 +0200 -Subject: [PATCH] clk: qcom: gcc-ipq6018: add QUP6 I2C clock - -QUP6 I2C clock is listed in the dt bindings but it was never included in -the GCC driver. -So lets add support for it, it is marked as criticial as it is used by RPM -to communicate to the external PMIC over I2C so this clock must not be -disabled. - -Signed-off-by: Robert Marko -Reviewed-by: Kathiravan Thirumoorthy -Reviewed-by: Konrad Dybcio -Link: https://lore.kernel.org/r/20231021115545.229060-1-robimarko@gmail.com -Signed-off-by: Bjorn Andersson ---- - drivers/clk/qcom/gcc-ipq6018.c | 21 +++++++++++++++++++++ - 1 file changed, 21 insertions(+) - ---- a/drivers/clk/qcom/gcc-ipq6018.c -+++ b/drivers/clk/qcom/gcc-ipq6018.c -@@ -2121,6 +2121,26 @@ static struct clk_branch gcc_blsp1_qup5_ - }, - }; - -+static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { -+ .halt_reg = 0x07010, -+ .clkr = { -+ .enable_reg = 0x07010, -+ .enable_mask = BIT(0), -+ .hw.init = &(struct clk_init_data){ -+ .name = "gcc_blsp1_qup6_i2c_apps_clk", -+ .parent_hws = (const struct clk_hw *[]){ -+ &blsp1_qup6_i2c_apps_clk_src.clkr.hw }, -+ .num_parents = 1, -+ /* -+ * RPM uses QUP6 I2C to communicate with the external -+ * PMIC so it must not be disabled. -+ */ -+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, -+ .ops = &clk_branch2_ops, -+ }, -+ }, -+}; -+ - static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { - .halt_reg = 0x0700c, - .clkr = { -@@ -4277,6 +4297,7 @@ static struct clk_regmap *gcc_ipq6018_cl - [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, - [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, - [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, -+ [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, - [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, - [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, - [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, diff --git a/target/linux/qualcommax/patches-6.12/0008-v6.8-arm64-dts-qcom-ipq6018-use-CPUFreq-NVMEM.patch b/target/linux/qualcommax/patches-6.12/0008-v6.8-arm64-dts-qcom-ipq6018-use-CPUFreq-NVMEM.patch deleted file mode 100644 index 6198e24f38b..00000000000 --- a/target/linux/qualcommax/patches-6.12/0008-v6.8-arm64-dts-qcom-ipq6018-use-CPUFreq-NVMEM.patch +++ /dev/null @@ -1,85 +0,0 @@ -From 83afcf14edb9217e58837eb119da96d734a4b3b1 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Sat, 21 Oct 2023 14:00:07 +0200 -Subject: [PATCH] arm64: dts: qcom: ipq6018: use CPUFreq NVMEM - -IPQ6018 comes in multiple SKU-s and some of them dont support all of the -OPP-s that are current set, so lets utilize CPUFreq NVMEM to allow only -supported OPP-s based on the SoC dynamically. - -As an example, IPQ6018 is generaly rated at 1.8GHz but some silicon only -goes up to 1.5GHz and is marked as such via an eFuse. - -Signed-off-by: Robert Marko -Reviewed-by: Konrad Dybcio -Link: https://lore.kernel.org/r/20231021120048.231239-1-robimarko@gmail.com -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq6018.dtsi | 14 +++++++++++++- - 1 file changed, 13 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -96,42 +96,49 @@ - }; - - cpu_opp_table: opp-table-cpu { -- compatible = "operating-points-v2"; -+ compatible = "operating-points-v2-kryo-cpu"; -+ nvmem-cells = <&cpu_speed_bin>; - opp-shared; - - opp-864000000 { - opp-hz = /bits/ 64 <864000000>; - opp-microvolt = <725000>; -+ opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - }; - - opp-1056000000 { - opp-hz = /bits/ 64 <1056000000>; - opp-microvolt = <787500>; -+ opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - }; - - opp-1320000000 { - opp-hz = /bits/ 64 <1320000000>; - opp-microvolt = <862500>; -+ opp-supported-hw = <0x3>; - clock-latency-ns = <200000>; - }; - - opp-1440000000 { - opp-hz = /bits/ 64 <1440000000>; - opp-microvolt = <925000>; -+ opp-supported-hw = <0x3>; - clock-latency-ns = <200000>; - }; - - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <987500>; -+ opp-supported-hw = <0x1>; - clock-latency-ns = <200000>; - }; - - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1062500>; -+ opp-supported-hw = <0x1>; - clock-latency-ns = <200000>; - }; - }; -@@ -322,6 +329,11 @@ - reg = <0x0 0x000a4000 0x0 0x2000>; - #address-cells = <1>; - #size-cells = <1>; -+ -+ cpu_speed_bin: cpu-speed-bin@135 { -+ reg = <0x135 0x1>; -+ bits = <7 1>; -+ }; - }; - - prng: qrng@e3000 { diff --git a/target/linux/qualcommax/patches-6.12/0009-v6.8-arm64-dts-ipq6018-Add-remaining-QUP-UART-node.patch b/target/linux/qualcommax/patches-6.12/0009-v6.8-arm64-dts-ipq6018-Add-remaining-QUP-UART-node.patch deleted file mode 100644 index af3e1325846..00000000000 --- a/target/linux/qualcommax/patches-6.12/0009-v6.8-arm64-dts-ipq6018-Add-remaining-QUP-UART-node.patch +++ /dev/null @@ -1,81 +0,0 @@ -From e6c32770ef83f3e8cc057f3920b1c06aa9d1c9c2 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Sun, 3 Dec 2023 23:39:14 +0800 -Subject: [PATCH] arm64: dts: qcom: ipq6018: Add remaining QUP UART node - -Add node to support all the QUP UART node controller inside of IPQ6018. -Some routers use these bus to connect Bluetooth chips. - -Signed-off-by: Chukun Pan -Link: https://lore.kernel.org/r/20231203153914.532654-1-amadeus@jmu.edu.cn -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq6018.dtsi | 50 +++++++++++++++++++++++++++ - 1 file changed, 50 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -459,6 +459,26 @@ - qcom,ee = <0>; - }; - -+ blsp1_uart1: serial@78af000 { -+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; -+ reg = <0x0 0x78af000 0x0 0x200>; -+ interrupts = ; -+ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, -+ <&gcc GCC_BLSP1_AHB_CLK>; -+ clock-names = "core", "iface"; -+ status = "disabled"; -+ }; -+ -+ blsp1_uart2: serial@78b0000 { -+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; -+ reg = <0x0 0x78b0000 0x0 0x200>; -+ interrupts = ; -+ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, -+ <&gcc GCC_BLSP1_AHB_CLK>; -+ clock-names = "core", "iface"; -+ status = "disabled"; -+ }; -+ - blsp1_uart3: serial@78b1000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x0 0x078b1000 0x0 0x200>; -@@ -467,6 +487,36 @@ - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; -+ }; -+ -+ blsp1_uart4: serial@78b2000 { -+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; -+ reg = <0x0 0x078b2000 0x0 0x200>; -+ interrupts = ; -+ clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, -+ <&gcc GCC_BLSP1_AHB_CLK>; -+ clock-names = "core", "iface"; -+ status = "disabled"; -+ }; -+ -+ blsp1_uart5: serial@78b3000 { -+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; -+ reg = <0x0 0x78b3000 0x0 0x200>; -+ interrupts = ; -+ clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, -+ <&gcc GCC_BLSP1_AHB_CLK>; -+ clock-names = "core", "iface"; -+ status = "disabled"; -+ }; -+ -+ blsp1_uart6: serial@78b4000 { -+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; -+ reg = <0x0 0x078b4000 0x0 0x200>; -+ interrupts = ; -+ clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>, -+ <&gcc GCC_BLSP1_AHB_CLK>; -+ clock-names = "core", "iface"; -+ status = "disabled"; - }; - - blsp1_spi1: spi@78b5000 { diff --git a/target/linux/qualcommax/patches-6.12/0010-v6.9-arm64-dts-qcom-Fix-hs_phy_irq-for-QUSB2-targets.patch b/target/linux/qualcommax/patches-6.12/0010-v6.9-arm64-dts-qcom-Fix-hs_phy_irq-for-QUSB2-targets.patch deleted file mode 100644 index 6559f3bbe9e..00000000000 --- a/target/linux/qualcommax/patches-6.12/0010-v6.9-arm64-dts-qcom-Fix-hs_phy_irq-for-QUSB2-targets.patch +++ /dev/null @@ -1,95 +0,0 @@ -From 2c6597c72e9722ac020102d5af40126df0437b82 Mon Sep 17 00:00:00 2001 -From: Krishna Kurapati -Date: Fri, 26 Jan 2024 00:29:18 +0530 -Subject: [PATCH] arm64: dts: qcom: Fix hs_phy_irq for QUSB2 targets - -On several QUSB2 Targets, the hs_phy_irq mentioned is actually -qusb2_phy interrupt specific to QUSB2 PHY's. Rename hs_phy_irq -to qusb2_phy for such targets. - -In actuality, the hs_phy_irq is also present in these targets, but -kept in for debug purposes in hw test environments. This is not -triggered by default and its functionality is mutually exclusive -to that of qusb2_phy interrupt. - -Add missing hs_phy_irq's, pwr_event irq's for QUSB2 PHY targets. -Add missing ss_phy_irq on some targets which allows for remote -wakeup to work on a Super Speed link. - -Also modify order of interrupts in accordance to bindings update. -Since driver looks up for interrupts by name and not by index, it -is safe to modify order of these interrupts in the DT. - -Signed-off-by: Krishna Kurapati -Link: https://lore.kernel.org/r/20240125185921.5062-2-quic_kriskura@quicinc.com -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq6018.dtsi | 13 +++++++++++++ - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++++ - arch/arm64/boot/dts/qcom/msm8953.dtsi | 7 +++++-- - arch/arm64/boot/dts/qcom/msm8996.dtsi | 8 ++++++-- - arch/arm64/boot/dts/qcom/msm8998.dtsi | 7 +++++-- - arch/arm64/boot/dts/qcom/sdm630.dtsi | 17 +++++++++++++---- - arch/arm64/boot/dts/qcom/sm6115.dtsi | 9 +++++++-- - arch/arm64/boot/dts/qcom/sm6125.dtsi | 9 +++++++-- - 8 files changed, 70 insertions(+), 14 deletions(-) - ---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -431,6 +431,12 @@ - <&gcc GCC_USB1_MOCK_UTMI_CLK>; - assigned-clock-rates = <133330000>, - <24000000>; -+ -+ interrupts = , -+ ; -+ interrupt-names = "pwr_event", -+ "qusb2_phy"; -+ - resets = <&gcc GCC_USB1_BCR>; - status = "disabled"; - -@@ -629,6 +635,13 @@ - <133330000>, - <24000000>; - -+ interrupts = , -+ , -+ ; -+ interrupt-names = "pwr_event", -+ "qusb2_phy", -+ "ss_phy_irq"; -+ - resets = <&gcc GCC_USB0_BCR>; - status = "disabled"; - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -632,6 +632,13 @@ - <133330000>, - <19200000>; - -+ interrupts = , -+ , -+ ; -+ interrupt-names = "pwr_event", -+ "qusb2_phy", -+ "ss_phy_irq"; -+ - power-domains = <&gcc USB0_GDSC>; - - resets = <&gcc GCC_USB0_BCR>; -@@ -675,6 +682,13 @@ - <133330000>, - <19200000>; - -+ interrupts = , -+ , -+ ; -+ interrupt-names = "pwr_event", -+ "qusb2_phy", -+ "ss_phy_irq"; -+ - power-domains = <&gcc USB1_GDSC>; - - resets = <&gcc GCC_USB1_BCR>; diff --git a/target/linux/qualcommax/patches-6.12/0011-v6.8-hwspinlock-qcom-Remove-IPQ6018-SOC-specific-.patch b/target/linux/qualcommax/patches-6.12/0011-v6.8-hwspinlock-qcom-Remove-IPQ6018-SOC-specific-.patch deleted file mode 100644 index 25d56870a47..00000000000 --- a/target/linux/qualcommax/patches-6.12/0011-v6.8-hwspinlock-qcom-Remove-IPQ6018-SOC-specific-.patch +++ /dev/null @@ -1,32 +0,0 @@ -From c3dc3d079d191c9149496b3c7fe1ece909386d93 Mon Sep 17 00:00:00 2001 -From: Vignesh Viswanathan -Date: Tue, 5 Sep 2023 15:25:35 +0530 -Subject: [PATCH] hwspinlock: qcom: Remove IPQ6018 SOC specific compatible - -IPQ6018 has 32 tcsr_mutex hwlock registers with stride 0x1000. -The compatible string qcom,ipq6018-tcsr-mutex is mapped to -of_msm8226_tcsr_mutex which has 32 locks configured with stride of 0x80 -and doesn't match the HW present in IPQ6018. - -Remove IPQ6018 specific compatible string so that it fallsback to -of_tcsr_mutex data which maps to the correct configuration for IPQ6018. - -Fixes: 5d4753f741d8 ("hwspinlock: qcom: add support for MMIO on older SoCs") -Signed-off-by: Vignesh Viswanathan -Reviewed-by: Konrad Dybcio -Link: https://lore.kernel.org/r/20230905095535.1263113-3-quic_viswanat@quicinc.com -Signed-off-by: Bjorn Andersson ---- - drivers/hwspinlock/qcom_hwspinlock.c | 1 - - 1 file changed, 1 deletion(-) - ---- a/drivers/hwspinlock/qcom_hwspinlock.c -+++ b/drivers/hwspinlock/qcom_hwspinlock.c -@@ -115,7 +115,6 @@ static const struct of_device_id qcom_hw - { .compatible = "qcom,sfpb-mutex", .data = &of_sfpb_mutex }, - { .compatible = "qcom,tcsr-mutex", .data = &of_tcsr_mutex }, - { .compatible = "qcom,apq8084-tcsr-mutex", .data = &of_msm8226_tcsr_mutex }, -- { .compatible = "qcom,ipq6018-tcsr-mutex", .data = &of_msm8226_tcsr_mutex }, - { .compatible = "qcom,msm8226-tcsr-mutex", .data = &of_msm8226_tcsr_mutex }, - { .compatible = "qcom,msm8974-tcsr-mutex", .data = &of_msm8226_tcsr_mutex }, - { .compatible = "qcom,msm8994-tcsr-mutex", .data = &of_msm8226_tcsr_mutex }, diff --git a/target/linux/qualcommax/patches-6.12/0012-v6.9-arm64-dts-qcom-ipq6018-add-tsens-node.patch b/target/linux/qualcommax/patches-6.12/0012-v6.9-arm64-dts-qcom-ipq6018-add-tsens-node.patch deleted file mode 100644 index 29d2de9b23b..00000000000 --- a/target/linux/qualcommax/patches-6.12/0012-v6.9-arm64-dts-qcom-ipq6018-add-tsens-node.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 0b17197055b528da22e9385200e61b847b499d48 Mon Sep 17 00:00:00 2001 -From: Mantas Pucka -Date: Thu, 25 Jan 2024 11:04:11 +0200 -Subject: [PATCH] arm64: dts: qcom: ipq6018: add tsens node - -IPQ6018 has temperature sensing HW block compatible with IPQ8074. Add -node for it. - -Signed-off-by: Mantas Pucka -Link: https://lore.kernel.org/r/1706173452-1017-3-git-send-email-mantas@8devices.com -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq6018.dtsi | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -343,6 +343,16 @@ - clock-names = "core"; - }; - -+ tsens: thermal-sensor@4a9000 { -+ compatible = "qcom,ipq6018-tsens", "qcom,ipq8074-tsens"; -+ reg = <0x0 0x004a9000 0x0 0x1000>, -+ <0x0 0x004a8000 0x0 0x1000>; -+ interrupts = ; -+ interrupt-names = "combined"; -+ #qcom,sensors = <16>; -+ #thermal-sensor-cells = <1>; -+ }; -+ - cryptobam: dma-controller@704000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x0 0x00704000 0x0 0x20000>; diff --git a/target/linux/qualcommax/patches-6.12/0013-v6.9-arm64-dts-qcom-ipq6018-add-thermal-zones.patch b/target/linux/qualcommax/patches-6.12/0013-v6.9-arm64-dts-qcom-ipq6018-add-thermal-zones.patch deleted file mode 100644 index 7e8c84558eb..00000000000 --- a/target/linux/qualcommax/patches-6.12/0013-v6.9-arm64-dts-qcom-ipq6018-add-thermal-zones.patch +++ /dev/null @@ -1,180 +0,0 @@ -From 8f053e5616352943e16966f195f5a7a161e6fe7d Mon Sep 17 00:00:00 2001 -From: Mantas Pucka -Date: Thu, 25 Jan 2024 11:04:12 +0200 -Subject: [PATCH] arm64: dts: qcom: ipq6018: add thermal zones - -Add thermal zones to make use of thermal sensors data. For CPU zone, -add cooling device that uses CPU frequency scaling. - -Signed-off-by: Mantas Pucka -Link: https://lore.kernel.org/r/1706173452-1017-4-git-send-email-mantas@8devices.com -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq6018.dtsi | 121 ++++++++++++++++++++++++++ - 1 file changed, 121 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -9,6 +9,7 @@ - #include - #include - #include -+#include - - / { - #address-cells = <2>; -@@ -43,6 +44,7 @@ - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; -+ #cooling-cells = <2>; - }; - - CPU1: cpu@1 { -@@ -55,6 +57,7 @@ - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; -+ #cooling-cells = <2>; - }; - - CPU2: cpu@2 { -@@ -67,6 +70,7 @@ - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; -+ #cooling-cells = <2>; - }; - - CPU3: cpu@3 { -@@ -79,6 +83,7 @@ - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; -+ #cooling-cells = <2>; - }; - - L2_0: l2-cache { -@@ -890,6 +895,122 @@ - }; - }; - -+ thermal-zones { -+ nss-top-thermal { -+ polling-delay-passive = <250>; -+ polling-delay = <1000>; -+ thermal-sensors = <&tsens 4>; -+ -+ trips { -+ nss-top-critical { -+ temperature = <125000>; -+ hysteresis = <1000>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ nss-thermal { -+ polling-delay-passive = <250>; -+ polling-delay = <1000>; -+ thermal-sensors = <&tsens 5>; -+ -+ trips { -+ nss-critical { -+ temperature = <125000>; -+ hysteresis = <1000>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ wcss-phya0-thermal { -+ polling-delay-passive = <250>; -+ polling-delay = <1000>; -+ thermal-sensors = <&tsens 7>; -+ -+ trips { -+ wcss-phya0-critical { -+ temperature = <125000>; -+ hysteresis = <1000>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ wcss-phya1-thermal { -+ polling-delay-passive = <250>; -+ polling-delay = <1000>; -+ thermal-sensors = <&tsens 8>; -+ -+ trips { -+ wcss-phya1-critical { -+ temperature = <125000>; -+ hysteresis = <1000>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ cpu-thermal { -+ polling-delay-passive = <250>; -+ polling-delay = <1000>; -+ thermal-sensors = <&tsens 13>; -+ -+ trips { -+ cpu-critical { -+ temperature = <125000>; -+ hysteresis = <1000>; -+ type = "critical"; -+ }; -+ -+ cpu_alert: cpu-passive { -+ temperature = <110000>; -+ hysteresis = <1000>; -+ type = "passive"; -+ }; -+ }; -+ -+ cooling-maps { -+ map0 { -+ trip = <&cpu_alert>; -+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+ -+ lpass-thermal { -+ polling-delay-passive = <250>; -+ polling-delay = <1000>; -+ thermal-sensors = <&tsens 14>; -+ -+ trips { -+ lpass-critical { -+ temperature = <125000>; -+ hysteresis = <1000>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ ddrss-top-thermal { -+ polling-delay-passive = <250>; -+ polling-delay = <1000>; -+ thermal-sensors = <&tsens 15>; -+ -+ trips { -+ ddrss-top-critical { -+ temperature = <125000>; -+ hysteresis = <1000>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ }; -+ - timer { - compatible = "arm,armv8-timer"; - interrupts = , diff --git a/target/linux/qualcommax/patches-6.12/0014-v6.9-clk-qcom-gcc-ipq6018-add-qdss_at-clock-needed-for-wi.patch b/target/linux/qualcommax/patches-6.12/0014-v6.9-clk-qcom-gcc-ipq6018-add-qdss_at-clock-needed-for-wi.patch deleted file mode 100644 index 5f0af1352a8..00000000000 --- a/target/linux/qualcommax/patches-6.12/0014-v6.9-clk-qcom-gcc-ipq6018-add-qdss_at-clock-needed-for-wi.patch +++ /dev/null @@ -1,50 +0,0 @@ -From fd712118aa1aa758da1fd1546b3f8a1b00e42cbc Mon Sep 17 00:00:00 2001 -From: Mantas Pucka -Date: Tue, 23 Jan 2024 11:26:09 +0200 -Subject: [PATCH] clk: qcom: gcc-ipq6018: add qdss_at clock needed for wifi - operation - -Without it system hangs upon wifi firmware load. It should be enabled by -remoteproc/wifi driver. Bindings already exist for it, so add it based -on vendor code. - -Signed-off-by: Mantas Pucka -Link: https://lore.kernel.org/r/1706001970-26032-1-git-send-email-mantas@8devices.com -Signed-off-by: Bjorn Andersson ---- - drivers/clk/qcom/gcc-ipq6018.c | 17 +++++++++++++++++ - 1 file changed, 17 insertions(+) - ---- a/drivers/clk/qcom/gcc-ipq6018.c -+++ b/drivers/clk/qcom/gcc-ipq6018.c -@@ -3524,6 +3524,22 @@ static struct clk_branch gcc_prng_ahb_cl - }, - }; - -+static struct clk_branch gcc_qdss_at_clk = { -+ .halt_reg = 0x29024, -+ .clkr = { -+ .enable_reg = 0x29024, -+ .enable_mask = BIT(0), -+ .hw.init = &(struct clk_init_data){ -+ .name = "gcc_qdss_at_clk", -+ .parent_hws = (const struct clk_hw *[]){ -+ &qdss_at_clk_src.clkr.hw }, -+ .num_parents = 1, -+ .flags = CLK_SET_RATE_PARENT, -+ .ops = &clk_branch2_ops, -+ }, -+ }, -+}; -+ - static struct clk_branch gcc_qdss_dap_clk = { - .halt_reg = 0x29084, - .clkr = { -@@ -4363,6 +4379,7 @@ static struct clk_regmap *gcc_ipq6018_cl - [GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr, - [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr, - [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, -+ [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr, - [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, - [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr, - [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr, diff --git a/target/linux/qualcommax/patches-6.12/0015-v6.8-phy-qcom-qmp-usb-fix-serdes-init-sequence-for-IPQ6018.patch b/target/linux/qualcommax/patches-6.12/0015-v6.8-phy-qcom-qmp-usb-fix-serdes-init-sequence-for-IPQ6018.patch deleted file mode 100644 index 9021b572e8e..00000000000 --- a/target/linux/qualcommax/patches-6.12/0015-v6.8-phy-qcom-qmp-usb-fix-serdes-init-sequence-for-IPQ6018.patch +++ /dev/null @@ -1,58 +0,0 @@ -From 62a5df451ab911421da96655fcc4d1e269ff6e2f Mon Sep 17 00:00:00 2001 -From: Mantas Pucka -Date: Tue, 23 Jan 2024 18:09:20 +0200 -Subject: [PATCH] phy: qcom-qmp-usb: fix serdes init sequence for IPQ6018 - -Commit 23fd679249df ("phy: qcom-qmp: add USB3 PHY support for IPQ6018") -noted that IPQ6018 init is identical to IPQ8074. Yet downstream uses -separate serdes init sequence for IPQ6018. Since already existing IPQ9574 -serdes init sequence is identical, just reuse it and fix failing USB3 mode -in IPQ6018. - -Fixes: 23fd679249df ("phy: qcom-qmp: add USB3 PHY support for IPQ6018") -Signed-off-by: Mantas Pucka -Reviewed-by: Dmitry Baryshkov -Link: https://lore.kernel.org/r/1706026160-17520-3-git-send-email-mantas@8devices.com -Signed-off-by: Vinod Koul ---- - drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 20 +++++++++++++++++++- - 1 file changed, 19 insertions(+), 1 deletion(-) - ---- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c -+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c -@@ -1314,6 +1314,26 @@ static const struct qmp_usb_offsets qmp_ - .rx = 0x1000, - }; - -+static const struct qmp_phy_cfg ipq6018_usb3phy_cfg = { -+ .lanes = 1, -+ -+ .serdes_tbl = ipq9574_usb3_serdes_tbl, -+ .serdes_tbl_num = ARRAY_SIZE(ipq9574_usb3_serdes_tbl), -+ .tx_tbl = msm8996_usb3_tx_tbl, -+ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), -+ .rx_tbl = ipq8074_usb3_rx_tbl, -+ .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl), -+ .pcs_tbl = ipq8074_usb3_pcs_tbl, -+ .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl), -+ .clk_list = msm8996_phy_clk_l, -+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), -+ .reset_list = msm8996_usb3phy_reset_l, -+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), -+ .vreg_list = qmp_phy_vreg_l, -+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), -+ .regs = qmp_v3_usb3phy_regs_layout, -+}; -+ - static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { - .lanes = 1, - -@@ -2239,7 +2259,7 @@ err_node_put: - static const struct of_device_id qmp_usb_of_match_table[] = { - { - .compatible = "qcom,ipq6018-qmp-usb3-phy", -- .data = &ipq8074_usb3phy_cfg, -+ .data = &ipq6018_usb3phy_cfg, - }, { - .compatible = "qcom,ipq8074-qmp-usb3-phy", - .data = &ipq8074_usb3phy_cfg, diff --git a/target/linux/qualcommax/patches-6.12/0016-v6.8-arm64-dts-qcom-ipq8074-Add-QUP4-SPI-node.patch b/target/linux/qualcommax/patches-6.12/0016-v6.8-arm64-dts-qcom-ipq8074-Add-QUP4-SPI-node.patch deleted file mode 100644 index 16d24374903..00000000000 --- a/target/linux/qualcommax/patches-6.12/0016-v6.8-arm64-dts-qcom-ipq8074-Add-QUP4-SPI-node.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 6a25e70214fde6dcf900271c819c8d7fe7b9a4b0 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 23 Nov 2023 13:12:54 +0100 -Subject: [PATCH] arm64: dts: qcom: ipq8074: Add QUP4 SPI node - -Add node to support the QUP4 SPI controller inside of IPQ8074. -Some devices use this bus to communicate to a Bluetooth controller. - -Signed-off-by: Robert Marko -Link: https://lore.kernel.org/r/20231123121324.1046164-1-robimarko@gmail.com -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -536,6 +536,20 @@ - status = "disabled"; - }; - -+ blsp1_spi4: spi@78b8000 { -+ compatible = "qcom,spi-qup-v2.2.1"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x78b8000 0x600>; -+ interrupts = ; -+ clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, -+ <&gcc GCC_BLSP1_AHB_CLK>; -+ clock-names = "core", "iface"; -+ dmas = <&blsp_dma 18>, <&blsp_dma 19>; -+ dma-names = "tx", "rx"; -+ status = "disabled"; -+ }; -+ - blsp1_i2c5: i2c@78b9000 { - compatible = "qcom,i2c-qup-v2.2.1"; - #address-cells = <1>; diff --git a/target/linux/qualcommax/patches-6.12/0017-v6.9-arm64-dts-qcom-ipq8074-Remove-unused-gpio-from-QPIC-.patch b/target/linux/qualcommax/patches-6.12/0017-v6.9-arm64-dts-qcom-ipq8074-Remove-unused-gpio-from-QPIC-.patch deleted file mode 100644 index e075c590fb4..00000000000 --- a/target/linux/qualcommax/patches-6.12/0017-v6.9-arm64-dts-qcom-ipq8074-Remove-unused-gpio-from-QPIC-.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 5f78d9213ae753e2242b0f6a5d4a5e98e55ddc76 Mon Sep 17 00:00:00 2001 -From: Paweł Owoc -Date: Wed, 13 Mar 2024 11:27:06 +0100 -Subject: [PATCH] arm64: dts: qcom: ipq8074: Remove unused gpio from QPIC pins - -gpio16 will only be used for LCD support, as its NAND/LCDC data[8] -so its bit 9 of the parallel QPIC interface, and ONFI NAND is only 8 -or 16-bit with only 8-bit one being supported in our case so that pin -is unused. - -It should be dropped from the default NAND pinctrl configuration -as its unused and only needed for LCD. - -Signed-off-by: Paweł Owoc -Reviewed-by: Kathiravan Thirumoorthy -Link: https://lore.kernel.org/r/20240313102713.1727458-1-frut3k7@gmail.com -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -372,7 +372,7 @@ - "gpio5", "gpio6", "gpio7", - "gpio8", "gpio10", "gpio11", - "gpio12", "gpio13", "gpio14", -- "gpio15", "gpio16", "gpio17"; -+ "gpio15", "gpio17"; - function = "qpic"; - drive-strength = <8>; - bias-disable; diff --git a/target/linux/qualcommax/patches-6.12/0018-v6.7-arm64-dts-qcom-ipq5018-add-watchdog.patch b/target/linux/qualcommax/patches-6.12/0018-v6.7-arm64-dts-qcom-ipq5018-add-watchdog.patch deleted file mode 100644 index 8e973e63f29..00000000000 --- a/target/linux/qualcommax/patches-6.12/0018-v6.7-arm64-dts-qcom-ipq5018-add-watchdog.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 9cbaee8379e620f82112002f973adde19679df31 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 16 Aug 2023 18:14:00 +0200 -Subject: [PATCH] arm64: dts: qcom: ipq5018: add watchdog - -Add the required DT node for watchdog operation. - -Signed-off-by: Robert Marko -Reviewed-by: Konrad Dybcio -Link: https://lore.kernel.org/r/20230816161455.3310629-2-robimarko@gmail.com -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq5018.dtsi | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -181,6 +181,13 @@ - }; - }; - -+ watchdog: watchdog@b017000 { -+ compatible = "qcom,apss-wdt-ipq5018", "qcom,kpss-wdt"; -+ reg = <0x0b017000 0x40>; -+ interrupts = ; -+ clocks = <&sleep_clk>; -+ }; -+ - timer@b120000 { - compatible = "arm,armv7-timer-mem"; - reg = <0x0b120000 0x1000>; diff --git a/target/linux/qualcommax/patches-6.12/0019-v6.7-dt-bindings-firmware-qcom-scm-support-indicating-SDI-default-state.patch b/target/linux/qualcommax/patches-6.12/0019-v6.7-dt-bindings-firmware-qcom-scm-support-indicating-SDI-default-state.patch deleted file mode 100644 index 46d3c61398d..00000000000 --- a/target/linux/qualcommax/patches-6.12/0019-v6.7-dt-bindings-firmware-qcom-scm-support-indicating-SDI-default-state.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 92dab9ea5f389c12828283146c60054642453a91 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 16 Aug 2023 18:45:38 +0200 -Subject: [PATCH] dt-bindings: firmware: qcom,scm: support indicating SDI - default state - -IPQ5018 has SDI (Secure Debug Image) enabled by TZ by default, and that -means that WDT being asserted or just trying to reboot will hang the board -in the debug mode and only pulling the power and repowering will help. -Some IPQ4019 boards like Google WiFI have it enabled as well. - -So, lets add a boolean property to indicate that SDI is enabled by default -and thus needs to be disabled by the kernel. - -Signed-off-by: Robert Marko -Acked-by: Mukesh Ojha -Reviewed-by: Krzysztof Kozlowski -Reviewed-by: Brian Norris -Link: https://lore.kernel.org/r/20230816164641.3371878-1-robimarko@gmail.com -Signed-off-by: Bjorn Andersson ---- - Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml -+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml -@@ -89,6 +89,14 @@ properties: - protocol to handle sleeping SCM calls. - maxItems: 1 - -+ qcom,sdi-enabled: -+ description: -+ Indicates that the SDI (Secure Debug Image) has been enabled by TZ -+ by default and it needs to be disabled. -+ If not disabled WDT assertion or reboot will cause the board to hang -+ in the debug mode. -+ type: boolean -+ - qcom,dload-mode: - $ref: /schemas/types.yaml#/definitions/phandle-array - items: diff --git a/target/linux/qualcommax/patches-6.12/0020-v6.7-firmware-qcom-scm-disable-SDI-if-required.patch b/target/linux/qualcommax/patches-6.12/0020-v6.7-firmware-qcom-scm-disable-SDI-if-required.patch deleted file mode 100644 index 747ba7f2850..00000000000 --- a/target/linux/qualcommax/patches-6.12/0020-v6.7-firmware-qcom-scm-disable-SDI-if-required.patch +++ /dev/null @@ -1,83 +0,0 @@ -From ff4aa3bc98258a240b9bbab53fd8d2fb8184c485 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 16 Aug 2023 18:45:39 +0200 -Subject: [PATCH] firmware: qcom_scm: disable SDI if required - -IPQ5018 has SDI (Secure Debug Image) enabled by TZ by default, and that -means that WDT being asserted or just trying to reboot will hang the board -in the debug mode and only pulling the power and repowering will help. -Some IPQ4019 boards like Google WiFI have it enabled as well. - -Luckily, SDI can be disabled via an SCM call. - -So, lets use the boolean DT property to identify boards that have SDI -enabled by default and use the SCM call to disable SDI during SCM probe. -It is important to disable it as soon as possible as we might have a WDT -assertion at any time which would then leave the board in debug mode, -thus disabling it during SCM removal is not enough. - -Signed-off-by: Robert Marko -Reviewed-by: Guru Das Srinagesh -Link: https://lore.kernel.org/r/20230816164641.3371878-2-robimarko@gmail.com -Signed-off-by: Bjorn Andersson ---- - drivers/firmware/qcom_scm.c | 30 ++++++++++++++++++++++++++++++ - drivers/firmware/qcom_scm.h | 1 + - 2 files changed, 31 insertions(+) - ---- a/drivers/firmware/qcom_scm.c -+++ b/drivers/firmware/qcom_scm.c -@@ -410,6 +410,29 @@ int qcom_scm_set_remote_state(u32 state, - } - EXPORT_SYMBOL_GPL(qcom_scm_set_remote_state); - -+static int qcom_scm_disable_sdi(void) -+{ -+ int ret; -+ struct qcom_scm_desc desc = { -+ .svc = QCOM_SCM_SVC_BOOT, -+ .cmd = QCOM_SCM_BOOT_SDI_CONFIG, -+ .args[0] = 1, /* Disable watchdog debug */ -+ .args[1] = 0, /* Disable SDI */ -+ .arginfo = QCOM_SCM_ARGS(2), -+ .owner = ARM_SMCCC_OWNER_SIP, -+ }; -+ struct qcom_scm_res res; -+ -+ ret = qcom_scm_clk_enable(); -+ if (ret) -+ return ret; -+ ret = qcom_scm_call(__scm->dev, &desc, &res); -+ -+ qcom_scm_clk_disable(); -+ -+ return ret ? : res.result[0]; -+} -+ - static int __qcom_scm_set_dload_mode(struct device *dev, bool enable) - { - struct qcom_scm_desc desc = { -@@ -1474,6 +1497,13 @@ static int qcom_scm_probe(struct platfor - - __get_convention(); - -+ -+ /* -+ * Disable SDI if indicated by DT that it is enabled by default. -+ */ -+ if (of_property_read_bool(pdev->dev.of_node, "qcom,sdi-enabled")) -+ qcom_scm_disable_sdi(); -+ - /* - * If requested enable "download mode", from this point on warmboot - * will cause the boot stages to enter download mode, unless ---- a/drivers/firmware/qcom_scm.h -+++ b/drivers/firmware/qcom_scm.h -@@ -80,6 +80,7 @@ extern int scm_legacy_call(struct device - #define QCOM_SCM_SVC_BOOT 0x01 - #define QCOM_SCM_BOOT_SET_ADDR 0x01 - #define QCOM_SCM_BOOT_TERMINATE_PC 0x02 -+#define QCOM_SCM_BOOT_SDI_CONFIG 0x09 - #define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10 - #define QCOM_SCM_BOOT_SET_ADDR_MC 0x11 - #define QCOM_SCM_BOOT_SET_REMOTE_STATE 0x0a diff --git a/target/linux/qualcommax/patches-6.12/0021-v6.7-dt-bindings-qcom-scm-document-IPQ5018-compatible.patch b/target/linux/qualcommax/patches-6.12/0021-v6.7-dt-bindings-qcom-scm-document-IPQ5018-compatible.patch deleted file mode 100644 index d36ccddd279..00000000000 --- a/target/linux/qualcommax/patches-6.12/0021-v6.7-dt-bindings-qcom-scm-document-IPQ5018-compatible.patch +++ /dev/null @@ -1,25 +0,0 @@ -From f6aa7386bc40b552eea8ec1b1d2168afe3b31110 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 16 Aug 2023 18:45:40 +0200 -Subject: [PATCH] dt-bindings: firmware: qcom,scm: document IPQ5018 compatible - -It seems that IPQ5018 compatible was never documented in the bindings. - -Signed-off-by: Robert Marko -Reviewed-by: Krzysztof Kozlowski -Link: https://lore.kernel.org/r/20230816164641.3371878-3-robimarko@gmail.com -Signed-off-by: Bjorn Andersson ---- - Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 + - 1 file changed, 1 insertion(+) - ---- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml -+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml -@@ -24,6 +24,7 @@ properties: - - qcom,scm-apq8064 - - qcom,scm-apq8084 - - qcom,scm-ipq4019 -+ - qcom,scm-ipq5018 - - qcom,scm-ipq5332 - - qcom,scm-ipq6018 - - qcom,scm-ipq806x diff --git a/target/linux/qualcommax/patches-6.12/0022-v6.7-arm64-dts-qcom-IPQ5018-indicate-that-SDI-shoud-be-disabled.patch b/target/linux/qualcommax/patches-6.12/0022-v6.7-arm64-dts-qcom-IPQ5018-indicate-that-SDI-shoud-be-disabled.patch deleted file mode 100644 index 6d598bf50f6..00000000000 --- a/target/linux/qualcommax/patches-6.12/0022-v6.7-arm64-dts-qcom-IPQ5018-indicate-that-SDI-shoud-be-disabled.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 79796e87215db9587d6c66ec6f6781e091bc6464 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 16 Aug 2023 18:45:41 +0200 -Subject: [PATCH] arm64: dts: qcom: ipq5018: indicate that SDI should be - disabled - -Now that SCM has support for indicating that SDI has been enabled by -default, lets set the property so SCM disables it during probing. - -Signed-off-by: Robert Marko -Link: https://lore.kernel.org/r/20230816164641.3371878-4-robimarko@gmail.com -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq5018.dtsi | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -57,6 +57,7 @@ - firmware { - scm { - compatible = "qcom,scm-ipq5018", "qcom,scm"; -+ qcom,sdi-enabled; - }; - }; - diff --git a/target/linux/qualcommax/patches-6.12/0023-v6.7-dt-bindings-phy-qcom-m31-Add-IPQ5018-compatible.patch b/target/linux/qualcommax/patches-6.12/0023-v6.7-dt-bindings-phy-qcom-m31-Add-IPQ5018-compatible.patch deleted file mode 100644 index 777212249e5..00000000000 --- a/target/linux/qualcommax/patches-6.12/0023-v6.7-dt-bindings-phy-qcom-m31-Add-IPQ5018-compatible.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 1852dfaacd3f4358bbfca134b63a02bbb30c1136 Mon Sep 17 00:00:00 2001 -From: Nitheesh Sekar -Date: Mon, 4 Sep 2023 12:06:32 +0530 -Subject: [PATCH] dt-bindings: phy: qcom,m31: Add IPQ5018 compatible - -IPQ5332 qcom,m31 phy driver can support IPQ5018. - -Reviewed-by: Krzysztof Kozlowski -Signed-off-by: Nitheesh Sekar -Link: https://lore.kernel.org/r/20230904063635.24975-2-quic_nsekar@quicinc.com -Signed-off-by: Vinod Koul ---- - .../devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - ---- a/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml -+++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml -@@ -17,7 +17,9 @@ description: - properties: - compatible: - items: -- - const: qcom,ipq5332-usb-hsphy -+ - enum: -+ - qcom,ipq5018-usb-hsphy -+ - qcom,ipq5332-usb-hsphy - - "#phy-cells": - const: 0 diff --git a/target/linux/qualcommax/patches-6.12/0024-v6.7-phy-qcom-m31-Add-compatible-phy-init-sequence-for-IPQ5018.patch b/target/linux/qualcommax/patches-6.12/0024-v6.7-phy-qcom-m31-Add-compatible-phy-init-sequence-for-IPQ5018.patch deleted file mode 100644 index 248b47c6943..00000000000 --- a/target/linux/qualcommax/patches-6.12/0024-v6.7-phy-qcom-m31-Add-compatible-phy-init-sequence-for-IPQ5018.patch +++ /dev/null @@ -1,89 +0,0 @@ -From 68320e35f8cb1987b4ad34347fc7033832da99e3 Mon Sep 17 00:00:00 2001 -From: Nitheesh Sekar -Date: Mon, 4 Sep 2023 12:06:33 +0530 -Subject: [PATCH] phy: qcom-m31: Add compatible, phy init sequence for IPQ5018 - -Add phy init sequence and compatible string for IPQ5018 -chipset. - -Signed-off-by: Nitheesh Sekar -Link: https://lore.kernel.org/r/20230904063635.24975-3-quic_nsekar@quicinc.com -Signed-off-by: Vinod Koul ---- - drivers/phy/qualcomm/phy-qcom-m31.c | 51 +++++++++++++++++++++++++++++ - 1 file changed, 51 insertions(+) - ---- a/drivers/phy/qualcomm/phy-qcom-m31.c -+++ b/drivers/phy/qualcomm/phy-qcom-m31.c -@@ -82,6 +82,50 @@ struct m31_priv_data { - unsigned int nregs; - }; - -+static const struct m31_phy_regs m31_ipq5018_regs[] = { -+ { -+ .off = USB_PHY_CFG0, -+ .val = UTMI_PHY_OVERRIDE_EN -+ }, -+ { -+ .off = USB_PHY_UTMI_CTRL5, -+ .val = POR_EN, -+ .delay = 15 -+ }, -+ { -+ .off = USB_PHY_FSEL_SEL, -+ .val = FREQ_SEL -+ }, -+ { -+ .off = USB_PHY_HS_PHY_CTRL_COMMON0, -+ .val = COMMONONN | FSEL | RETENABLEN -+ }, -+ { -+ .off = USB_PHY_REFCLK_CTRL, -+ .val = CLKCORE -+ }, -+ { -+ .off = USB_PHY_UTMI_CTRL5, -+ .val = POR_EN -+ }, -+ { -+ .off = USB_PHY_HS_PHY_CTRL2, -+ .val = USB2_SUSPEND_N_SEL | USB2_SUSPEND_N | USB2_UTMI_CLK_EN -+ }, -+ { -+ .off = USB_PHY_UTMI_CTRL5, -+ .val = 0x0 -+ }, -+ { -+ .off = USB_PHY_HS_PHY_CTRL2, -+ .val = USB2_SUSPEND_N | USB2_UTMI_CLK_EN -+ }, -+ { -+ .off = USB_PHY_CFG0, -+ .val = 0x0 -+ }, -+}; -+ - static struct m31_phy_regs m31_ipq5332_regs[] = { - { - USB_PHY_CFG0, -@@ -267,6 +311,12 @@ static int m31usb_phy_probe(struct platf - return PTR_ERR_OR_ZERO(phy_provider); - } - -+static const struct m31_priv_data m31_ipq5018_data = { -+ .ulpi_mode = false, -+ .regs = m31_ipq5018_regs, -+ .nregs = ARRAY_SIZE(m31_ipq5018_regs), -+}; -+ - static const struct m31_priv_data m31_ipq5332_data = { - .ulpi_mode = false, - .regs = m31_ipq5332_regs, -@@ -274,6 +324,7 @@ static const struct m31_priv_data m31_ip - }; - - static const struct of_device_id m31usb_phy_id_table[] = { -+ { .compatible = "qcom,ipq5018-usb-hsphy", .data = &m31_ipq5018_data }, - { .compatible = "qcom,ipq5332-usb-hsphy", .data = &m31_ipq5332_data }, - { }, - }; diff --git a/target/linux/qualcommax/patches-6.12/0025-v6.7-dt-bindings-usb-dwc3-Add-IPQ5018-compatible.patch b/target/linux/qualcommax/patches-6.12/0025-v6.7-dt-bindings-usb-dwc3-Add-IPQ5018-compatible.patch deleted file mode 100644 index 146fcbff098..00000000000 --- a/target/linux/qualcommax/patches-6.12/0025-v6.7-dt-bindings-usb-dwc3-Add-IPQ5018-compatible.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 3865a64284cc4845c61cf3dc6c7246349d80cc49 Mon Sep 17 00:00:00 2001 -From: Nitheesh Sekar -Date: Thu, 31 Aug 2023 08:35:03 +0530 -Subject: [PATCH] dt-bindings: usb: dwc3: Add IPQ5018 compatible - -Document the IPQ5018 dwc3 compatible. - -Reviewed-by: Krzysztof Kozlowski -Signed-off-by: Nitheesh Sekar -Link: https://lore.kernel.org/r/20230831030503.17100-1-quic_nsekar@quicinc.com -Signed-off-by: Greg Kroah-Hartman ---- - Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml -+++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml -@@ -14,6 +14,7 @@ properties: - items: - - enum: - - qcom,ipq4019-dwc3 -+ - qcom,ipq5018-dwc3 - - qcom,ipq5332-dwc3 - - qcom,ipq6018-dwc3 - - qcom,ipq8064-dwc3 -@@ -238,6 +239,7 @@ allOf: - compatible: - contains: - enum: -+ - qcom,ipq5018-dwc3 - - qcom,ipq5332-dwc3 - - qcom,msm8994-dwc3 - - qcom,qcs404-dwc3 -@@ -411,6 +413,7 @@ allOf: - compatible: - contains: - enum: -+ - qcom,ipq5018-dwc3 - - qcom,ipq5332-dwc3 - - qcom,sdm660-dwc3 - then: diff --git a/target/linux/qualcommax/patches-6.12/0026-v6.8-arm64-dts-qcom-ipq5018-Add-USB-related-nodes.patch b/target/linux/qualcommax/patches-6.12/0026-v6.8-arm64-dts-qcom-ipq5018-Add-USB-related-nodes.patch deleted file mode 100644 index 99fdae732a4..00000000000 --- a/target/linux/qualcommax/patches-6.12/0026-v6.8-arm64-dts-qcom-ipq5018-Add-USB-related-nodes.patch +++ /dev/null @@ -1,86 +0,0 @@ -From e7166f2774aafefd29ff26ffbbb7f6d40ac8ea1c Mon Sep 17 00:00:00 2001 -From: Nitheesh Sekar -Date: Mon, 4 Sep 2023 12:06:34 +0530 -Subject: [PATCH] arm64: dts: qcom: ipq5018: Add USB related nodes - -Add USB phy and controller nodes. - -Co-developed-by: Amandeep Singh -Signed-off-by: Amandeep Singh -Signed-off-by: Nitheesh Sekar -Link: https://lore.kernel.org/r/20230904063635.24975-4-quic_nsekar@quicinc.com -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq5018.dtsi | 54 +++++++++++++++++++++++++++ - 1 file changed, 54 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -94,6 +94,19 @@ - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; - -+ usbphy0: phy@5b000 { -+ compatible = "qcom,ipq5018-usb-hsphy"; -+ reg = <0x0005b000 0x120>; -+ -+ clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>; -+ -+ resets = <&gcc GCC_QUSB2_0_PHY_BCR>; -+ -+ #phy-cells = <0>; -+ -+ status = "disabled"; -+ }; -+ - tlmm: pinctrl@1000000 { - compatible = "qcom,ipq5018-tlmm"; - reg = <0x01000000 0x300000>; -@@ -156,6 +169,47 @@ - status = "disabled"; - }; - -+ usb: usb@8af8800 { -+ compatible = "qcom,ipq5018-dwc3", "qcom,dwc3"; -+ reg = <0x08af8800 0x400>; -+ -+ interrupts = ; -+ interrupt-names = "hs_phy_irq"; -+ -+ clocks = <&gcc GCC_USB0_MASTER_CLK>, -+ <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, -+ <&gcc GCC_USB0_SLEEP_CLK>, -+ <&gcc GCC_USB0_MOCK_UTMI_CLK>; -+ clock-names = "core", -+ "iface", -+ "sleep", -+ "mock_utmi"; -+ -+ resets = <&gcc GCC_USB0_BCR>; -+ -+ qcom,select-utmi-as-pipe-clk; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ status = "disabled"; -+ -+ usb_dwc: usb@8a00000 { -+ compatible = "snps,dwc3"; -+ reg = <0x08a00000 0xe000>; -+ clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; -+ clock-names = "ref"; -+ interrupts = ; -+ phy-names = "usb2-phy"; -+ phys = <&usbphy0>; -+ tx-fifo-resize; -+ snps,is-utmi-l1-suspend; -+ snps,hird-threshold = /bits/ 8 <0x0>; -+ snps,dis_u2_susphy_quirk; -+ snps,dis_u3_susphy_quirk; -+ }; -+ }; -+ - intc: interrupt-controller@b000000 { - compatible = "qcom,msm-qgic2"; - reg = <0x0b000000 0x1000>, /* GICD */ diff --git a/target/linux/qualcommax/patches-6.12/0027-v6.8-arm64-dts-qcom-ipq5018-add-QUP1-SPI-controller.patch b/target/linux/qualcommax/patches-6.12/0027-v6.8-arm64-dts-qcom-ipq5018-add-QUP1-SPI-controller.patch deleted file mode 100644 index d0d9e45dec2..00000000000 --- a/target/linux/qualcommax/patches-6.12/0027-v6.8-arm64-dts-qcom-ipq5018-add-QUP1-SPI-controller.patch +++ /dev/null @@ -1,56 +0,0 @@ -From a1f42e08f0f04b72a6597f080db4bfbb3737910c Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 4 Oct 2023 21:12:30 +0200 -Subject: [PATCH] arm64: dts: qcom: ipq5018: add QUP1 SPI controller - -Add the required BAM and QUP nodes for the QUP1 SPI controller on IPQ5018. - -Signed-off-by: Robert Marko -Reviewed-by: Kathiravan Thirumoorthy -Link: https://lore.kernel.org/r/20231004191303.331055-1-robimarko@gmail.com -[bjorn: Padded address to 8 digits, fixed node sort order] -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq5018.dtsi | 24 ++++++++++++++++++++++++ - 1 file changed, 24 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -159,6 +159,16 @@ - status = "disabled"; - }; - -+ blsp_dma: dma-controller@7884000 { -+ compatible = "qcom,bam-v1.7.0"; -+ reg = <0x07884000 0x1d000>; -+ interrupts = ; -+ clocks = <&gcc GCC_BLSP1_AHB_CLK>; -+ clock-names = "bam_clk"; -+ #dma-cells = <1>; -+ qcom,ee = <0>; -+ }; -+ - blsp1_uart1: serial@78af000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x078af000 0x200>; -@@ -169,6 +179,20 @@ - status = "disabled"; - }; - -+ blsp1_spi1: spi@78b5000 { -+ compatible = "qcom,spi-qup-v2.2.1"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x078b5000 0x600>; -+ interrupts = ; -+ clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, -+ <&gcc GCC_BLSP1_AHB_CLK>; -+ clock-names = "core", "iface"; -+ dmas = <&blsp_dma 4>, <&blsp_dma 5>; -+ dma-names = "tx", "rx"; -+ status = "disabled"; -+ }; -+ - usb: usb@8af8800 { - compatible = "qcom,ipq5018-dwc3", "qcom,dwc3"; - reg = <0x08af8800 0x400>; diff --git a/target/linux/qualcommax/patches-6.12/0028-v6.8-dt-bindings-clock-qcom-a53pll-add-IPQ5018-compatible.patch b/target/linux/qualcommax/patches-6.12/0028-v6.8-dt-bindings-clock-qcom-a53pll-add-IPQ5018-compatible.patch deleted file mode 100644 index 314afa76d25..00000000000 --- a/target/linux/qualcommax/patches-6.12/0028-v6.8-dt-bindings-clock-qcom-a53pll-add-IPQ5018-compatible.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 4d45d56e17348c6b6bb2bce126a4a5ea97b19900 Mon Sep 17 00:00:00 2001 -From: Gokul Sriram Palanisamy -Date: Mon, 25 Sep 2023 15:58:24 +0530 -Subject: [PATCH] dt-bindings: clock: qcom,a53pll: add IPQ5018 compatible - -Add IPQ5018 compatible to A53 PLL bindings. - -Signed-off-by: Gokul Sriram Palanisamy -Reviewed-by: Krzysztof Kozlowski -Link: https://lore.kernel.org/r/20230925102826.405446-2-quic_gokulsri@quicinc.com -Signed-off-by: Bjorn Andersson ---- - Documentation/devicetree/bindings/clock/qcom,a53pll.yaml | 1 + - 1 file changed, 1 insertion(+) - ---- a/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml -+++ b/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml -@@ -16,6 +16,7 @@ description: - properties: - compatible: - enum: -+ - qcom,ipq5018-a53pll - - qcom,ipq5332-a53pll - - qcom,ipq6018-a53pll - - qcom,ipq8074-a53pll diff --git a/target/linux/qualcommax/patches-6.12/0029-v6.8-clk-qcom-apss-ipq-pll-add-support-for-IPQ5018.patch b/target/linux/qualcommax/patches-6.12/0029-v6.8-clk-qcom-apss-ipq-pll-add-support-for-IPQ5018.patch deleted file mode 100644 index 46dede07caf..00000000000 --- a/target/linux/qualcommax/patches-6.12/0029-v6.8-clk-qcom-apss-ipq-pll-add-support-for-IPQ5018.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 50492f929486c044b43cb3e2c0e040aa9b61ea2b Mon Sep 17 00:00:00 2001 -From: Gokul Sriram Palanisamy -Date: Mon, 25 Sep 2023 15:58:25 +0530 -Subject: [PATCH] clk: qcom: apss-ipq-pll: add support for IPQ5018 - -IPQ5018 APSS PLL is of type Stromer. Reuse Stromer Plus PLL offsets, -add configuration values and the compatible. - -Co-developed-by: Sricharan Ramabadhran -Signed-off-by: Sricharan Ramabadhran -Signed-off-by: Gokul Sriram Palanisamy -Reviewed-by: Dmitry Baryshkov -Link: https://lore.kernel.org/r/20230925102826.405446-3-quic_gokulsri@quicinc.com -Signed-off-by: Bjorn Andersson ---- - drivers/clk/qcom/apss-ipq-pll.c | 21 +++++++++++++++++++++ - 1 file changed, 21 insertions(+) - ---- a/drivers/clk/qcom/apss-ipq-pll.c -+++ b/drivers/clk/qcom/apss-ipq-pll.c -@@ -73,6 +73,20 @@ static struct clk_alpha_pll ipq_pll_stro - }, - }; - -+static const struct alpha_pll_config ipq5018_pll_config = { -+ .l = 0x32, -+ .config_ctl_val = 0x4001075b, -+ .config_ctl_hi_val = 0x304, -+ .main_output_mask = BIT(0), -+ .aux_output_mask = BIT(1), -+ .early_output_mask = BIT(3), -+ .alpha_en_mask = BIT(24), -+ .status_val = 0x3, -+ .status_mask = GENMASK(10, 8), -+ .lock_det = BIT(2), -+ .test_ctl_hi_val = 0x00400003, -+}; -+ - static const struct alpha_pll_config ipq5332_pll_config = { - .l = 0x2d, - .config_ctl_val = 0x4001075b, -@@ -129,6 +143,12 @@ struct apss_pll_data { - const struct alpha_pll_config *pll_config; - }; - -+static const struct apss_pll_data ipq5018_pll_data = { -+ .pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS, -+ .pll = &ipq_pll_stromer_plus, -+ .pll_config = &ipq5018_pll_config, -+}; -+ - static struct apss_pll_data ipq5332_pll_data = { - .pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS, - .pll = &ipq_pll_stromer_plus, -@@ -195,6 +215,7 @@ static int apss_ipq_pll_probe(struct pla - } - - static const struct of_device_id apss_ipq_pll_match_table[] = { -+ { .compatible = "qcom,ipq5018-a53pll", .data = &ipq5018_pll_data }, - { .compatible = "qcom,ipq5332-a53pll", .data = &ipq5332_pll_data }, - { .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data }, - { .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data }, diff --git a/target/linux/qualcommax/patches-6.12/0030-v6.8-arm64-dts-qcom-ipq5018-enable-the-CPUFreq-support.patch b/target/linux/qualcommax/patches-6.12/0030-v6.8-arm64-dts-qcom-ipq5018-enable-the-CPUFreq-support.patch deleted file mode 100644 index 72bec54cb3c..00000000000 --- a/target/linux/qualcommax/patches-6.12/0030-v6.8-arm64-dts-qcom-ipq5018-enable-the-CPUFreq-support.patch +++ /dev/null @@ -1,98 +0,0 @@ -From 3e4b53e04281ed3d9c7a4329c027097265c04d54 Mon Sep 17 00:00:00 2001 -From: Gokul Sriram Palanisamy -Date: Mon, 25 Sep 2023 15:58:26 +0530 -Subject: [PATCH] arm64: dts: qcom: ipq5018: enable the CPUFreq support - -Add the APCS, A53 PLL, cpu-opp-table nodes to set -the CPU frequency at 800MHz (idle) or 1.008GHz. - -Co-developed-by: Sricharan Ramabadhran -Signed-off-by: Sricharan Ramabadhran -Signed-off-by: Gokul Sriram Palanisamy -Reviewed-by: Dmitry Baryshkov -Reviewed-by: Krzysztof Kozlowski -Link: https://lore.kernel.org/r/20230925102826.405446-4-quic_gokulsri@quicinc.com -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq5018.dtsi | 40 +++++++++++++++++++++++++++ - 1 file changed, 40 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -5,6 +5,7 @@ - * Copyright (c) 2023 The Linux Foundation. All rights reserved. - */ - -+#include - #include - #include - #include -@@ -36,6 +37,8 @@ - reg = <0x0>; - enable-method = "psci"; - next-level-cache = <&L2_0>; -+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; -+ operating-points-v2 = <&cpu_opp_table>; - }; - - CPU1: cpu@1 { -@@ -44,6 +47,8 @@ - reg = <0x1>; - enable-method = "psci"; - next-level-cache = <&L2_0>; -+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; -+ operating-points-v2 = <&cpu_opp_table>; - }; - - L2_0: l2-cache { -@@ -54,6 +59,25 @@ - }; - }; - -+ cpu_opp_table: opp-table-cpu { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ /* -+ opp-800000000 { -+ opp-hz = /bits/ 64 <800000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <200000>; -+ }; -+ */ -+ -+ opp-1008000000 { -+ opp-hz = /bits/ 64 <1008000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <200000>; -+ }; -+ }; -+ - firmware { - scm { - compatible = "qcom,scm-ipq5018", "qcom,scm"; -@@ -267,6 +291,24 @@ - clocks = <&sleep_clk>; - }; - -+ apcs_glb: mailbox@b111000 { -+ compatible = "qcom,ipq5018-apcs-apps-global", -+ "qcom,ipq6018-apcs-apps-global"; -+ reg = <0x0b111000 0x1000>; -+ #clock-cells = <1>; -+ clocks = <&a53pll>, <&xo_board_clk>, <&gcc GPLL0>; -+ clock-names = "pll", "xo", "gpll0"; -+ #mbox-cells = <1>; -+ }; -+ -+ a53pll: clock@b116000 { -+ compatible = "qcom,ipq5018-a53pll"; -+ reg = <0x0b116000 0x40>; -+ #clock-cells = <0>; -+ clocks = <&xo_board_clk>; -+ clock-names = "xo"; -+ }; -+ - timer@b120000 { - compatible = "arm,armv7-timer-mem"; - reg = <0x0b120000 0x1000>; diff --git a/target/linux/qualcommax/patches-6.12/0031-v6.8-arm64-dts-qcom-ipq5018-add-few-more-reserved-memory-regions.patch b/target/linux/qualcommax/patches-6.12/0031-v6.8-arm64-dts-qcom-ipq5018-add-few-more-reserved-memory-regions.patch deleted file mode 100644 index 97631e715a4..00000000000 --- a/target/linux/qualcommax/patches-6.12/0031-v6.8-arm64-dts-qcom-ipq5018-add-few-more-reserved-memory-regions.patch +++ /dev/null @@ -1,66 +0,0 @@ -From a427dd16e61f3d145bc24f0ed09692fc25931250 Mon Sep 17 00:00:00 2001 -From: Kathiravan Thirumoorthy -Date: Wed, 25 Oct 2023 22:12:12 +0530 -Subject: [PATCH] arm64: dts: qcom: ipq5018: add few more reserved memory - regions - -Like all other IPQ SoCs, bootloader will collect the system RAM contents -upon crash for the post morterm analysis. If we don't reserve the memory -region used by bootloader, obviously linux will consume it and upon next -boot on crash, bootloader will be loaded in the same region, which will -lead to loose some of the data, sometimes we may miss out critical -information. So lets reserve the region used by the bootloader. - -Similarly SBL copies some data into the reserved region and it will be -used in the crash scenario. So reserve 1MB for SBL as well. - -While at it, enable the SMEM support along with TCSR mutex. - -Signed-off-by: Kathiravan Thirumoorthy -Reviewed-by: Konrad Dybcio -Link: https://lore.kernel.org/r/20231025-ipq5018-misc-v1-1-7d14fde97fe7@quicinc.com -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq5018.dtsi | 24 ++++++++++++++++++++++++ - 1 file changed, 24 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -106,6 +106,24 @@ - #size-cells = <2>; - ranges; - -+ bootloader@4a800000 { -+ reg = <0x0 0x4a800000 0x0 0x200000>; -+ no-map; -+ }; -+ -+ sbl@4aa00000 { -+ reg = <0x0 0x4aa00000 0x0 0x100000>; -+ no-map; -+ }; -+ -+ smem@4ab00000 { -+ compatible = "qcom,smem"; -+ reg = <0x0 0x4ab00000 0x0 0x100000>; -+ no-map; -+ -+ hwlocks = <&tcsr_mutex 3>; -+ }; -+ - tz_region: tz@4ac00000 { - reg = <0x0 0x4ac00000 0x0 0x200000>; - no-map; -@@ -166,6 +184,12 @@ - #power-domain-cells = <1>; - }; - -+ tcsr_mutex: hwlock@1905000 { -+ compatible = "qcom,tcsr-mutex"; -+ reg = <0x01905000 0x20000>; -+ #hwlock-cells = <1>; -+ }; -+ - sdhc_1: mmc@7804000 { - compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5"; - reg = <0x7804000 0x1000>; diff --git a/target/linux/qualcommax/patches-6.12/0032-v6.10-clk-qcom-apss-ipq-pll-use-stromer-ops-for-IPQ5018-to-fix-boot-failure.patch b/target/linux/qualcommax/patches-6.12/0032-v6.10-clk-qcom-apss-ipq-pll-use-stromer-ops-for-IPQ5018-to-fix-boot-failure.patch deleted file mode 100644 index ea6f61b57fc..00000000000 --- a/target/linux/qualcommax/patches-6.12/0032-v6.10-clk-qcom-apss-ipq-pll-use-stromer-ops-for-IPQ5018-to-fix-boot-failure.patch +++ /dev/null @@ -1,83 +0,0 @@ -From: Gabor Juhos -Subject: [PATCH] clk: qcom: apss-ipq-pll: use stromer ops for IPQ5018 to fix boot failure -Date: Fri, 15 Mar 2024 17:16:41 +0100 - -Booting v6.8 results in a hang on various IPQ5018 based boards. -Investigating the problem showed that the hang happens when the -clk_alpha_pll_stromer_plus_set_rate() function tries to write -into the PLL_MODE register of the APSS PLL. - -Checking the downstream code revealed that it uses [1] stromer -specific operations for IPQ5018, whereas in the current code -the stromer plus specific operations are used. - -The ops in the 'ipq_pll_stromer_plus' clock definition can't be -changed since that is needed for IPQ5332, so add a new alpha pll -clock declaration which uses the correct stromer ops and use this -new clock for IPQ5018 to avoid the boot failure. - -Also, change pll_type in 'ipq5018_pll_data' to -CLK_ALPHA_PLL_TYPE_STROMER to better reflect that it is a Stromer -PLL and change the apss_ipq_pll_probe() function accordingly. - -1. https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4/drivers/clk/qcom/apss-ipq5018.c#L67 - -Fixes: 50492f929486 ("clk: qcom: apss-ipq-pll: add support for IPQ5018") -Signed-off-by: Gabor Juhos ---- - drivers/clk/qcom/apss-ipq-pll.c | 30 +++++++++++++++++++++++++++--- - 1 file changed, 27 insertions(+), 3 deletions(-) - ---- a/drivers/clk/qcom/apss-ipq-pll.c -+++ b/drivers/clk/qcom/apss-ipq-pll.c -@@ -55,6 +55,29 @@ static struct clk_alpha_pll ipq_pll_huay - }, - }; - -+static struct clk_alpha_pll ipq_pll_stromer = { -+ .offset = 0x0, -+ /* -+ * Reuse CLK_ALPHA_PLL_TYPE_STROMER_PLUS register offsets. -+ * Although this is a bit confusing, but the offset values -+ * are correct nevertheless. -+ */ -+ .regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_STROMER_PLUS], -+ .flags = SUPPORTS_DYNAMIC_UPDATE, -+ .clkr = { -+ .enable_reg = 0x0, -+ .enable_mask = BIT(0), -+ .hw.init = &(const struct clk_init_data) { -+ .name = "a53pll", -+ .parent_data = &(const struct clk_parent_data) { -+ .fw_name = "xo", -+ }, -+ .num_parents = 1, -+ .ops = &clk_alpha_pll_stromer_ops, -+ }, -+ }, -+}; -+ - static struct clk_alpha_pll ipq_pll_stromer_plus = { - .offset = 0x0, - .regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_STROMER_PLUS], -@@ -144,8 +167,8 @@ struct apss_pll_data { - }; - - static const struct apss_pll_data ipq5018_pll_data = { -- .pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS, -- .pll = &ipq_pll_stromer_plus, -+ .pll_type = CLK_ALPHA_PLL_TYPE_STROMER, -+ .pll = &ipq_pll_stromer, - .pll_config = &ipq5018_pll_config, - }; - -@@ -203,7 +226,8 @@ static int apss_ipq_pll_probe(struct pla - - if (data->pll_type == CLK_ALPHA_PLL_TYPE_HUAYRA) - clk_alpha_pll_configure(data->pll, regmap, data->pll_config); -- else if (data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER_PLUS) -+ else if (data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER || -+ data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER_PLUS) - clk_stromer_pll_configure(data->pll, regmap, data->pll_config); - - ret = devm_clk_register_regmap(dev, &data->pll->clkr); diff --git a/target/linux/qualcommax/patches-6.12/0033-v6.10-clk-qcom-apss-ipq-pll-fix-PLL-rate-for-IPQ5018.patch b/target/linux/qualcommax/patches-6.12/0033-v6.10-clk-qcom-apss-ipq-pll-fix-PLL-rate-for-IPQ5018.patch deleted file mode 100644 index 4bf0598c360..00000000000 --- a/target/linux/qualcommax/patches-6.12/0033-v6.10-clk-qcom-apss-ipq-pll-fix-PLL-rate-for-IPQ5018.patch +++ /dev/null @@ -1,32 +0,0 @@ -From: Gabor Juhos -Subject: [PATCH] clk: qcom: apss-ipq-pll: fix PLL rate for IPQ5018 -Date: Tue, 26 Mar 2024 14:34:11 +0100 - -According to ipq5018.dtsi, the maximum supported rate by the -CPU is 1.008 GHz on the IPQ5018 platform, however the current -configuration of the PLL results in 1.2 GHz rate. - -Change the 'L' value in the PLL configuration to limit the -rate to 1.008 GHz. The downstream kernel also uses the same -value [1]. Also add a comment to indicate the desired -frequency. - -[1] https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4/drivers/clk/qcom/apss-ipq5018.c?ref_type=heads#L151 - -Fixes: 50492f929486 ("clk: qcom: apss-ipq-pll: add support for IPQ5018") -Signed-off-by: Gabor Juhos ---- - drivers/clk/qcom/apss-ipq-pll.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - ---- a/drivers/clk/qcom/apss-ipq-pll.c -+++ b/drivers/clk/qcom/apss-ipq-pll.c -@@ -97,7 +97,7 @@ static struct clk_alpha_pll ipq_pll_stro - }; - - static const struct alpha_pll_config ipq5018_pll_config = { -- .l = 0x32, -+ .l = 0x2a, - .config_ctl_val = 0x4001075b, - .config_ctl_hi_val = 0x304, - .main_output_mask = BIT(0), diff --git a/target/linux/qualcommax/patches-6.12/0034-v6.11-clk-qcom-gcc-ipq6018-update-sdcc-max-clock-frequency.patch b/target/linux/qualcommax/patches-6.12/0034-v6.11-clk-qcom-gcc-ipq6018-update-sdcc-max-clock-frequency.patch deleted file mode 100644 index ddd54079fbd..00000000000 --- a/target/linux/qualcommax/patches-6.12/0034-v6.11-clk-qcom-gcc-ipq6018-update-sdcc-max-clock-frequency.patch +++ /dev/null @@ -1,26 +0,0 @@ -From f2743ae3ff84579981ac513f512b9df945d109c0 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Thu, 20 Jun 2024 23:01:21 +0800 -Subject: [PATCH] clk: qcom: gcc-ipq6018: update sdcc max clock frequency - -The mmc controller of the IPQ6018 does not support HS400 mode. -So adjust the maximum clock frequency of sdcc to 200 MHz (HS200). - -Signed-off-by: Chukun Pan -Link: https://lore.kernel.org/r/20240620150122.1406631-2-amadeus@jmu.edu.cn -Signed-off-by: Bjorn Andersson ---- - drivers/clk/qcom/gcc-ipq6018.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/clk/qcom/gcc-ipq6018.c -+++ b/drivers/clk/qcom/gcc-ipq6018.c -@@ -1617,7 +1617,7 @@ static const struct freq_tbl ftbl_sdcc_a - F(96000000, P_GPLL2, 12, 0, 0), - F(177777778, P_GPLL0, 4.5, 0, 0), - F(192000000, P_GPLL2, 6, 0, 0), -- F(384000000, P_GPLL2, 3, 0, 0), -+ F(200000000, P_GPLL0, 4, 0, 0), - { } - }; - diff --git a/target/linux/qualcommax/patches-6.12/0035-v6.11-arm64-dts-qcom-ipq6018-add-sdhci-node.patch b/target/linux/qualcommax/patches-6.12/0035-v6.11-arm64-dts-qcom-ipq6018-add-sdhci-node.patch deleted file mode 100644 index ed4b6d9e6dc..00000000000 --- a/target/linux/qualcommax/patches-6.12/0035-v6.11-arm64-dts-qcom-ipq6018-add-sdhci-node.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 5db216f6e1f85394e79dca74ceceb83b2f8566b5 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Thu, 20 Jun 2024 23:01:22 +0800 -Subject: [PATCH] arm64: dts: qcom: ipq6018: add sdhci node - -Add node to support mmc controller inside of IPQ6018. -This controller supports both eMMC and SD cards. - -Tested with: - eMMC (HS200) - SD Card (SDR50/SDR104) - -Signed-off-by: Chukun Pan -Link: https://lore.kernel.org/r/20240620150122.1406631-3-amadeus@jmu.edu.cn -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq6018.dtsi | 19 +++++++++++++++++++ - 1 file changed, 19 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -470,6 +470,25 @@ - }; - }; - -+ sdhc: mmc@7804000 { -+ compatible = "qcom,ipq6018-sdhci", "qcom,sdhci-msm-v5"; -+ reg = <0x0 0x07804000 0x0 0x1000>, -+ <0x0 0x07805000 0x0 0x1000>; -+ reg-names = "hc", "cqhci"; -+ -+ interrupts = , -+ ; -+ interrupt-names = "hc_irq", "pwr_irq"; -+ -+ clocks = <&gcc GCC_SDCC1_AHB_CLK>, -+ <&gcc GCC_SDCC1_APPS_CLK>, -+ <&xo>; -+ clock-names = "iface", "core", "xo"; -+ resets = <&gcc GCC_SDCC1_BCR>; -+ max-frequency = <192000000>; -+ status = "disabled"; -+ }; -+ - blsp_dma: dma-controller@7884000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x0 0x07884000 0x0 0x2b000>; diff --git a/target/linux/qualcommax/patches-6.12/0042-v6.10-clk-qcom-clk-rcg-introduce-support-for-multiple-conf.patch b/target/linux/qualcommax/patches-6.12/0042-v6.10-clk-qcom-clk-rcg-introduce-support-for-multiple-conf.patch deleted file mode 100644 index 937e6446266..00000000000 --- a/target/linux/qualcommax/patches-6.12/0042-v6.10-clk-qcom-clk-rcg-introduce-support-for-multiple-conf.patch +++ /dev/null @@ -1,83 +0,0 @@ -From d06b1043644a1831ab141bbee2669002bba15b0f Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Wed, 20 Dec 2023 23:17:22 +0100 -Subject: [PATCH] clk: qcom: clk-rcg: introduce support for multiple conf for - same freq - -Some RCG frequency can be reached by multiple configuration. - -We currently declare multiple configuration for the same frequency but -that is not supported and always the first configuration will be taken. - -These multiple configuration are needed as based on the current parent -configuration, it may be needed to use a different configuration to -reach the same frequency. - -To handle this introduce 3 new macro, C, FM and FMS: - -- C is used to declare a freq_conf where src, pre_div, m and n are - provided. - -- FM is used to declare a freq_multi_tbl with the frequency and an - array of confs to insert all the config for the provided frequency. - -- FMS is used to declare a freq_multi_tbl with the frequency and an - array of a single conf with the provided src, pre_div, m and n. - -Struct clk_rcg2 is changed to add a union type to reference a simple -freq_tbl or a complex freq_multi_tbl. - -Signed-off-by: Christian Marangi -Acked-by: Stephen Boyd -Link: https://lore.kernel.org/r/20231220221724.3822-2-ansuelsmth@gmail.com -Signed-off-by: Bjorn Andersson ---- - drivers/clk/qcom/clk-rcg.h | 23 ++++++++++++++++++++++- - 1 file changed, 22 insertions(+), 1 deletion(-) - ---- a/drivers/clk/qcom/clk-rcg.h -+++ b/drivers/clk/qcom/clk-rcg.h -@@ -17,6 +17,23 @@ struct freq_tbl { - u16 n; - }; - -+#define C(s, h, m, n) { (s), (2 * (h) - 1), (m), (n) } -+#define FM(f, confs) { (f), ARRAY_SIZE(confs), (confs) } -+#define FMS(f, s, h, m, n) { (f), 1, (const struct freq_conf []){ C(s, h, m, n) } } -+ -+struct freq_conf { -+ u8 src; -+ u8 pre_div; -+ u16 m; -+ u16 n; -+}; -+ -+struct freq_multi_tbl { -+ unsigned long freq; -+ size_t num_confs; -+ const struct freq_conf *confs; -+}; -+ - /** - * struct mn - M/N:D counter - * @mnctr_en_bit: bit to enable mn counter -@@ -138,6 +155,7 @@ extern const struct clk_ops clk_dyn_rcg_ - * @safe_src_index: safe src index value - * @parent_map: map from software's parent index to hardware's src_sel field - * @freq_tbl: frequency table -+ * @freq_multi_tbl: frequency table for clocks reachable with multiple RCGs conf - * @clkr: regmap clock handle - * @cfg_off: defines the cfg register offset from the CMD_RCGR + CFG_REG - * @parked_cfg: cached value of the CFG register for parked RCGs -@@ -149,7 +167,10 @@ struct clk_rcg2 { - u8 hid_width; - u8 safe_src_index; - const struct parent_map *parent_map; -- const struct freq_tbl *freq_tbl; -+ union { -+ const struct freq_tbl *freq_tbl; -+ const struct freq_multi_tbl *freq_multi_tbl; -+ }; - struct clk_regmap clkr; - u8 cfg_off; - u32 parked_cfg; diff --git a/target/linux/qualcommax/patches-6.12/0043-v6.10-clk-qcom-clk-rcg2-add-support-for-rcg2-freq-multi-op.patch b/target/linux/qualcommax/patches-6.12/0043-v6.10-clk-qcom-clk-rcg2-add-support-for-rcg2-freq-multi-op.patch deleted file mode 100644 index 478f60ed44c..00000000000 --- a/target/linux/qualcommax/patches-6.12/0043-v6.10-clk-qcom-clk-rcg2-add-support-for-rcg2-freq-multi-op.patch +++ /dev/null @@ -1,296 +0,0 @@ -From 89da22456af0762477d8c1345fdd17961b3ada80 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Wed, 20 Dec 2023 23:17:23 +0100 -Subject: [PATCH] clk: qcom: clk-rcg2: add support for rcg2 freq multi ops - -Some RCG frequency can be reached by multiple configuration. - -Add clk_rcg2_fm_ops ops to support these special RCG configurations. - -These alternative ops will select the frequency using a CEIL policy. - -When the correct frequency is found, the correct config is selected by -calculating the final rate (by checking the defined parent and values -in the config that is being checked) and deciding based on the one that -is less different than the requested one. - -These check are skipped if there is just one config for the requested -freq. - -qcom_find_freq_multi is added to search the freq with the new struct -freq_multi_tbl. -__clk_rcg2_select_conf is used to select the correct conf by simulating -the final clock. -If a conf can't be found due to parent not reachable, a WARN is printed -and -EINVAL is returned. - -Tested-by: Wei Lei -Signed-off-by: Christian Marangi -Acked-by: Stephen Boyd -Link: https://lore.kernel.org/r/20231220221724.3822-3-ansuelsmth@gmail.com -Signed-off-by: Bjorn Andersson ---- - drivers/clk/qcom/clk-rcg.h | 1 + - drivers/clk/qcom/clk-rcg2.c | 166 ++++++++++++++++++++++++++++++++++++ - drivers/clk/qcom/common.c | 18 ++++ - drivers/clk/qcom/common.h | 2 + - 4 files changed, 187 insertions(+) - ---- a/drivers/clk/qcom/clk-rcg.h -+++ b/drivers/clk/qcom/clk-rcg.h -@@ -190,6 +190,7 @@ struct clk_rcg2_gfx3d { - - extern const struct clk_ops clk_rcg2_ops; - extern const struct clk_ops clk_rcg2_floor_ops; -+extern const struct clk_ops clk_rcg2_fm_ops; - extern const struct clk_ops clk_rcg2_mux_closest_ops; - extern const struct clk_ops clk_edp_pixel_ops; - extern const struct clk_ops clk_byte_ops; ---- a/drivers/clk/qcom/clk-rcg2.c -+++ b/drivers/clk/qcom/clk-rcg2.c -@@ -260,6 +260,115 @@ static int _freq_tbl_determine_rate(stru - return 0; - } - -+static const struct freq_conf * -+__clk_rcg2_select_conf(struct clk_hw *hw, const struct freq_multi_tbl *f, -+ unsigned long req_rate) -+{ -+ unsigned long rate_diff, best_rate_diff = ULONG_MAX; -+ const struct freq_conf *conf, *best_conf = NULL; -+ struct clk_rcg2 *rcg = to_clk_rcg2(hw); -+ const char *name = clk_hw_get_name(hw); -+ unsigned long parent_rate, rate; -+ struct clk_hw *p; -+ int index, i; -+ -+ /* Exit early if only one config is defined */ -+ if (f->num_confs == 1) { -+ best_conf = f->confs; -+ goto exit; -+ } -+ -+ /* Search in each provided config the one that is near the wanted rate */ -+ for (i = 0, conf = f->confs; i < f->num_confs; i++, conf++) { -+ index = qcom_find_src_index(hw, rcg->parent_map, conf->src); -+ if (index < 0) -+ continue; -+ -+ p = clk_hw_get_parent_by_index(hw, index); -+ if (!p) -+ continue; -+ -+ parent_rate = clk_hw_get_rate(p); -+ rate = calc_rate(parent_rate, conf->n, conf->m, conf->n, conf->pre_div); -+ -+ if (rate == req_rate) { -+ best_conf = conf; -+ goto exit; -+ } -+ -+ rate_diff = abs_diff(req_rate, rate); -+ if (rate_diff < best_rate_diff) { -+ best_rate_diff = rate_diff; -+ best_conf = conf; -+ } -+ } -+ -+ /* -+ * Very unlikely. Warn if we couldn't find a correct config -+ * due to parent not found in every config. -+ */ -+ if (unlikely(!best_conf)) { -+ WARN(1, "%s: can't find a configuration for rate %lu\n", -+ name, req_rate); -+ return ERR_PTR(-EINVAL); -+ } -+ -+exit: -+ return best_conf; -+} -+ -+static int _freq_tbl_fm_determine_rate(struct clk_hw *hw, const struct freq_multi_tbl *f, -+ struct clk_rate_request *req) -+{ -+ unsigned long clk_flags, rate = req->rate; -+ struct clk_rcg2 *rcg = to_clk_rcg2(hw); -+ const struct freq_conf *conf; -+ struct clk_hw *p; -+ int index; -+ -+ f = qcom_find_freq_multi(f, rate); -+ if (!f || !f->confs) -+ return -EINVAL; -+ -+ conf = __clk_rcg2_select_conf(hw, f, rate); -+ if (IS_ERR(conf)) -+ return PTR_ERR(conf); -+ index = qcom_find_src_index(hw, rcg->parent_map, conf->src); -+ if (index < 0) -+ return index; -+ -+ clk_flags = clk_hw_get_flags(hw); -+ p = clk_hw_get_parent_by_index(hw, index); -+ if (!p) -+ return -EINVAL; -+ -+ if (clk_flags & CLK_SET_RATE_PARENT) { -+ rate = f->freq; -+ if (conf->pre_div) { -+ if (!rate) -+ rate = req->rate; -+ rate /= 2; -+ rate *= conf->pre_div + 1; -+ } -+ -+ if (conf->n) { -+ u64 tmp = rate; -+ -+ tmp = tmp * conf->n; -+ do_div(tmp, conf->m); -+ rate = tmp; -+ } -+ } else { -+ rate = clk_hw_get_rate(p); -+ } -+ -+ req->best_parent_hw = p; -+ req->best_parent_rate = rate; -+ req->rate = f->freq; -+ -+ return 0; -+} -+ - static int clk_rcg2_determine_rate(struct clk_hw *hw, - struct clk_rate_request *req) - { -@@ -276,6 +385,14 @@ static int clk_rcg2_determine_floor_rate - return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, FLOOR); - } - -+static int clk_rcg2_fm_determine_rate(struct clk_hw *hw, -+ struct clk_rate_request *req) -+{ -+ struct clk_rcg2 *rcg = to_clk_rcg2(hw); -+ -+ return _freq_tbl_fm_determine_rate(hw, rcg->freq_multi_tbl, req); -+} -+ - static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f, - u32 *_cfg) - { -@@ -371,6 +488,30 @@ static int __clk_rcg2_set_rate(struct cl - return clk_rcg2_configure(rcg, f); - } - -+static int __clk_rcg2_fm_set_rate(struct clk_hw *hw, unsigned long rate) -+{ -+ struct clk_rcg2 *rcg = to_clk_rcg2(hw); -+ const struct freq_multi_tbl *f; -+ const struct freq_conf *conf; -+ struct freq_tbl f_tbl = {}; -+ -+ f = qcom_find_freq_multi(rcg->freq_multi_tbl, rate); -+ if (!f || !f->confs) -+ return -EINVAL; -+ -+ conf = __clk_rcg2_select_conf(hw, f, rate); -+ if (IS_ERR(conf)) -+ return PTR_ERR(conf); -+ -+ f_tbl.freq = f->freq; -+ f_tbl.src = conf->src; -+ f_tbl.pre_div = conf->pre_div; -+ f_tbl.m = conf->m; -+ f_tbl.n = conf->n; -+ -+ return clk_rcg2_configure(rcg, &f_tbl); -+} -+ - static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) - { -@@ -383,6 +524,12 @@ static int clk_rcg2_set_floor_rate(struc - return __clk_rcg2_set_rate(hw, rate, FLOOR); - } - -+static int clk_rcg2_fm_set_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long parent_rate) -+{ -+ return __clk_rcg2_fm_set_rate(hw, rate); -+} -+ - static int clk_rcg2_set_rate_and_parent(struct clk_hw *hw, - unsigned long rate, unsigned long parent_rate, u8 index) - { -@@ -395,6 +542,12 @@ static int clk_rcg2_set_floor_rate_and_p - return __clk_rcg2_set_rate(hw, rate, FLOOR); - } - -+static int clk_rcg2_fm_set_rate_and_parent(struct clk_hw *hw, -+ unsigned long rate, unsigned long parent_rate, u8 index) -+{ -+ return __clk_rcg2_fm_set_rate(hw, rate); -+} -+ - static int clk_rcg2_get_duty_cycle(struct clk_hw *hw, struct clk_duty *duty) - { - struct clk_rcg2 *rcg = to_clk_rcg2(hw); -@@ -505,6 +658,19 @@ const struct clk_ops clk_rcg2_floor_ops - }; - EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops); - -+const struct clk_ops clk_rcg2_fm_ops = { -+ .is_enabled = clk_rcg2_is_enabled, -+ .get_parent = clk_rcg2_get_parent, -+ .set_parent = clk_rcg2_set_parent, -+ .recalc_rate = clk_rcg2_recalc_rate, -+ .determine_rate = clk_rcg2_fm_determine_rate, -+ .set_rate = clk_rcg2_fm_set_rate, -+ .set_rate_and_parent = clk_rcg2_fm_set_rate_and_parent, -+ .get_duty_cycle = clk_rcg2_get_duty_cycle, -+ .set_duty_cycle = clk_rcg2_set_duty_cycle, -+}; -+EXPORT_SYMBOL_GPL(clk_rcg2_fm_ops); -+ - const struct clk_ops clk_rcg2_mux_closest_ops = { - .determine_rate = __clk_mux_determine_rate_closest, - .get_parent = clk_rcg2_get_parent, ---- a/drivers/clk/qcom/common.c -+++ b/drivers/clk/qcom/common.c -@@ -41,6 +41,24 @@ struct freq_tbl *qcom_find_freq(const st - } - EXPORT_SYMBOL_GPL(qcom_find_freq); - -+const struct freq_multi_tbl *qcom_find_freq_multi(const struct freq_multi_tbl *f, -+ unsigned long rate) -+{ -+ if (!f) -+ return NULL; -+ -+ if (!f->freq) -+ return f; -+ -+ for (; f->freq; f++) -+ if (rate <= f->freq) -+ return f; -+ -+ /* Default to our fastest rate */ -+ return f - 1; -+} -+EXPORT_SYMBOL_GPL(qcom_find_freq_multi); -+ - const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f, - unsigned long rate) - { ---- a/drivers/clk/qcom/common.h -+++ b/drivers/clk/qcom/common.h -@@ -45,6 +45,8 @@ extern const struct freq_tbl *qcom_find_ - unsigned long rate); - extern const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f, - unsigned long rate); -+extern const struct freq_multi_tbl *qcom_find_freq_multi(const struct freq_multi_tbl *f, -+ unsigned long rate); - extern void - qcom_pll_set_fsm_mode(struct regmap *m, u32 reg, u8 bias_count, u8 lock_count); - extern int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map, diff --git a/target/linux/qualcommax/patches-6.12/0044-v6.10-clk-qcom-gcc-ipq8074-rework-nss_port5-6-clock-to-mul.patch b/target/linux/qualcommax/patches-6.12/0044-v6.10-clk-qcom-gcc-ipq8074-rework-nss_port5-6-clock-to-mul.patch deleted file mode 100644 index 5360771df22..00000000000 --- a/target/linux/qualcommax/patches-6.12/0044-v6.10-clk-qcom-gcc-ipq8074-rework-nss_port5-6-clock-to-mul.patch +++ /dev/null @@ -1,227 +0,0 @@ -From e88f03230dc07aa3293b6aeb078bd27370bb2594 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Wed, 20 Dec 2023 23:17:24 +0100 -Subject: [PATCH] clk: qcom: gcc-ipq8074: rework nss_port5/6 clock to multiple - conf - -Rework nss_port5/6 to use the new multiple configuration implementation -and correctly fix the clocks for these port under some corner case. - -This is particularly relevant for device that have 2.5G or 10G port -connected to port5 or port 6 on ipq8074. As the parent are shared -across multiple port it may be required to select the correct -configuration to accomplish the desired clock. Without this patch such -port doesn't work in some specific ethernet speed as the clock will be -set to the wrong frequency as we just select the first configuration for -the related frequency instead of selecting the best one. - -Signed-off-by: Christian Marangi -Acked-by: Stephen Boyd -Link: https://lore.kernel.org/r/20231220221724.3822-4-ansuelsmth@gmail.com -Signed-off-by: Bjorn Andersson ---- - drivers/clk/qcom/gcc-ipq8074.c | 120 +++++++++++++++++++++------------ - 1 file changed, 76 insertions(+), 44 deletions(-) - ---- a/drivers/clk/qcom/gcc-ipq8074.c -+++ b/drivers/clk/qcom/gcc-ipq8074.c -@@ -1677,15 +1677,23 @@ static struct clk_regmap_div nss_port4_t - }, - }; - --static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = { -- F(19200000, P_XO, 1, 0, 0), -- F(25000000, P_UNIPHY1_RX, 12.5, 0, 0), -- F(25000000, P_UNIPHY0_RX, 5, 0, 0), -- F(78125000, P_UNIPHY1_RX, 4, 0, 0), -- F(125000000, P_UNIPHY1_RX, 2.5, 0, 0), -- F(125000000, P_UNIPHY0_RX, 1, 0, 0), -- F(156250000, P_UNIPHY1_RX, 2, 0, 0), -- F(312500000, P_UNIPHY1_RX, 1, 0, 0), -+static const struct freq_conf ftbl_nss_port5_rx_clk_src_25[] = { -+ C(P_UNIPHY1_RX, 12.5, 0, 0), -+ C(P_UNIPHY0_RX, 5, 0, 0), -+}; -+ -+static const struct freq_conf ftbl_nss_port5_rx_clk_src_125[] = { -+ C(P_UNIPHY1_RX, 2.5, 0, 0), -+ C(P_UNIPHY0_RX, 1, 0, 0), -+}; -+ -+static const struct freq_multi_tbl ftbl_nss_port5_rx_clk_src[] = { -+ FMS(19200000, P_XO, 1, 0, 0), -+ FM(25000000, ftbl_nss_port5_rx_clk_src_25), -+ FMS(78125000, P_UNIPHY1_RX, 4, 0, 0), -+ FM(125000000, ftbl_nss_port5_rx_clk_src_125), -+ FMS(156250000, P_UNIPHY1_RX, 2, 0, 0), -+ FMS(312500000, P_UNIPHY1_RX, 1, 0, 0), - { } - }; - -@@ -1712,14 +1720,14 @@ gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32 - - static struct clk_rcg2 nss_port5_rx_clk_src = { - .cmd_rcgr = 0x68060, -- .freq_tbl = ftbl_nss_port5_rx_clk_src, -+ .freq_multi_tbl = ftbl_nss_port5_rx_clk_src, - .hid_width = 5, - .parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map, - .clkr.hw.init = &(struct clk_init_data){ - .name = "nss_port5_rx_clk_src", - .parent_data = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias, - .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias), -- .ops = &clk_rcg2_ops, -+ .ops = &clk_rcg2_fm_ops, - }, - }; - -@@ -1739,15 +1747,23 @@ static struct clk_regmap_div nss_port5_r - }, - }; - --static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = { -- F(19200000, P_XO, 1, 0, 0), -- F(25000000, P_UNIPHY1_TX, 12.5, 0, 0), -- F(25000000, P_UNIPHY0_TX, 5, 0, 0), -- F(78125000, P_UNIPHY1_TX, 4, 0, 0), -- F(125000000, P_UNIPHY1_TX, 2.5, 0, 0), -- F(125000000, P_UNIPHY0_TX, 1, 0, 0), -- F(156250000, P_UNIPHY1_TX, 2, 0, 0), -- F(312500000, P_UNIPHY1_TX, 1, 0, 0), -+static const struct freq_conf ftbl_nss_port5_tx_clk_src_25[] = { -+ C(P_UNIPHY1_TX, 12.5, 0, 0), -+ C(P_UNIPHY0_TX, 5, 0, 0), -+}; -+ -+static const struct freq_conf ftbl_nss_port5_tx_clk_src_125[] = { -+ C(P_UNIPHY1_TX, 2.5, 0, 0), -+ C(P_UNIPHY0_TX, 1, 0, 0), -+}; -+ -+static const struct freq_multi_tbl ftbl_nss_port5_tx_clk_src[] = { -+ FMS(19200000, P_XO, 1, 0, 0), -+ FM(25000000, ftbl_nss_port5_tx_clk_src_25), -+ FMS(78125000, P_UNIPHY1_TX, 4, 0, 0), -+ FM(125000000, ftbl_nss_port5_tx_clk_src_125), -+ FMS(156250000, P_UNIPHY1_TX, 2, 0, 0), -+ FMS(312500000, P_UNIPHY1_TX, 1, 0, 0), - { } - }; - -@@ -1774,14 +1790,14 @@ gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32 - - static struct clk_rcg2 nss_port5_tx_clk_src = { - .cmd_rcgr = 0x68068, -- .freq_tbl = ftbl_nss_port5_tx_clk_src, -+ .freq_multi_tbl = ftbl_nss_port5_tx_clk_src, - .hid_width = 5, - .parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map, - .clkr.hw.init = &(struct clk_init_data){ - .name = "nss_port5_tx_clk_src", - .parent_data = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias, - .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias), -- .ops = &clk_rcg2_ops, -+ .ops = &clk_rcg2_fm_ops, - }, - }; - -@@ -1801,15 +1817,23 @@ static struct clk_regmap_div nss_port5_t - }, - }; - --static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = { -- F(19200000, P_XO, 1, 0, 0), -- F(25000000, P_UNIPHY2_RX, 5, 0, 0), -- F(25000000, P_UNIPHY2_RX, 12.5, 0, 0), -- F(78125000, P_UNIPHY2_RX, 4, 0, 0), -- F(125000000, P_UNIPHY2_RX, 1, 0, 0), -- F(125000000, P_UNIPHY2_RX, 2.5, 0, 0), -- F(156250000, P_UNIPHY2_RX, 2, 0, 0), -- F(312500000, P_UNIPHY2_RX, 1, 0, 0), -+static const struct freq_conf ftbl_nss_port6_rx_clk_src_25[] = { -+ C(P_UNIPHY2_RX, 5, 0, 0), -+ C(P_UNIPHY2_RX, 12.5, 0, 0), -+}; -+ -+static const struct freq_conf ftbl_nss_port6_rx_clk_src_125[] = { -+ C(P_UNIPHY2_RX, 1, 0, 0), -+ C(P_UNIPHY2_RX, 2.5, 0, 0), -+}; -+ -+static const struct freq_multi_tbl ftbl_nss_port6_rx_clk_src[] = { -+ FMS(19200000, P_XO, 1, 0, 0), -+ FM(25000000, ftbl_nss_port6_rx_clk_src_25), -+ FMS(78125000, P_UNIPHY2_RX, 4, 0, 0), -+ FM(125000000, ftbl_nss_port6_rx_clk_src_125), -+ FMS(156250000, P_UNIPHY2_RX, 2, 0, 0), -+ FMS(312500000, P_UNIPHY2_RX, 1, 0, 0), - { } - }; - -@@ -1831,14 +1855,14 @@ static const struct parent_map gcc_xo_un - - static struct clk_rcg2 nss_port6_rx_clk_src = { - .cmd_rcgr = 0x68070, -- .freq_tbl = ftbl_nss_port6_rx_clk_src, -+ .freq_multi_tbl = ftbl_nss_port6_rx_clk_src, - .hid_width = 5, - .parent_map = gcc_xo_uniphy2_rx_tx_ubi32_bias_map, - .clkr.hw.init = &(struct clk_init_data){ - .name = "nss_port6_rx_clk_src", - .parent_data = gcc_xo_uniphy2_rx_tx_ubi32_bias, - .num_parents = ARRAY_SIZE(gcc_xo_uniphy2_rx_tx_ubi32_bias), -- .ops = &clk_rcg2_ops, -+ .ops = &clk_rcg2_fm_ops, - }, - }; - -@@ -1858,15 +1882,23 @@ static struct clk_regmap_div nss_port6_r - }, - }; - --static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = { -- F(19200000, P_XO, 1, 0, 0), -- F(25000000, P_UNIPHY2_TX, 5, 0, 0), -- F(25000000, P_UNIPHY2_TX, 12.5, 0, 0), -- F(78125000, P_UNIPHY2_TX, 4, 0, 0), -- F(125000000, P_UNIPHY2_TX, 1, 0, 0), -- F(125000000, P_UNIPHY2_TX, 2.5, 0, 0), -- F(156250000, P_UNIPHY2_TX, 2, 0, 0), -- F(312500000, P_UNIPHY2_TX, 1, 0, 0), -+static const struct freq_conf ftbl_nss_port6_tx_clk_src_25[] = { -+ C(P_UNIPHY2_TX, 5, 0, 0), -+ C(P_UNIPHY2_TX, 12.5, 0, 0), -+}; -+ -+static const struct freq_conf ftbl_nss_port6_tx_clk_src_125[] = { -+ C(P_UNIPHY2_TX, 1, 0, 0), -+ C(P_UNIPHY2_TX, 2.5, 0, 0), -+}; -+ -+static const struct freq_multi_tbl ftbl_nss_port6_tx_clk_src[] = { -+ FMS(19200000, P_XO, 1, 0, 0), -+ FM(25000000, ftbl_nss_port6_tx_clk_src_25), -+ FMS(78125000, P_UNIPHY1_RX, 4, 0, 0), -+ FM(125000000, ftbl_nss_port6_tx_clk_src_125), -+ FMS(156250000, P_UNIPHY1_RX, 2, 0, 0), -+ FMS(312500000, P_UNIPHY1_RX, 1, 0, 0), - { } - }; - -@@ -1888,14 +1920,14 @@ static const struct parent_map gcc_xo_un - - static struct clk_rcg2 nss_port6_tx_clk_src = { - .cmd_rcgr = 0x68078, -- .freq_tbl = ftbl_nss_port6_tx_clk_src, -+ .freq_multi_tbl = ftbl_nss_port6_tx_clk_src, - .hid_width = 5, - .parent_map = gcc_xo_uniphy2_tx_rx_ubi32_bias_map, - .clkr.hw.init = &(struct clk_init_data){ - .name = "nss_port6_tx_clk_src", - .parent_data = gcc_xo_uniphy2_tx_rx_ubi32_bias, - .num_parents = ARRAY_SIZE(gcc_xo_uniphy2_tx_rx_ubi32_bias), -- .ops = &clk_rcg2_ops, -+ .ops = &clk_rcg2_fm_ops, - }, - }; - diff --git a/target/linux/qualcommax/patches-6.12/0045-v6.7-arm64-dts-qcom-ipq8074-switch-PCIe-QMP-PHY-to-new-st.patch b/target/linux/qualcommax/patches-6.12/0045-v6.7-arm64-dts-qcom-ipq8074-switch-PCIe-QMP-PHY-to-new-st.patch deleted file mode 100644 index b85d073b9de..00000000000 --- a/target/linux/qualcommax/patches-6.12/0045-v6.7-arm64-dts-qcom-ipq8074-switch-PCIe-QMP-PHY-to-new-st.patch +++ /dev/null @@ -1,122 +0,0 @@ -From 9e5e778f3340a687dd91c533064f963d352921c6 Mon Sep 17 00:00:00 2001 -From: Dmitry Baryshkov -Date: Sun, 20 Aug 2023 17:20:26 +0300 -Subject: [PATCH] arm64: dts: qcom: ipq8074: switch PCIe QMP PHY to new style - of bindings - -Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single -resource region, no per-PHY subnodes). - -Signed-off-by: Dmitry Baryshkov -Link: https://lore.kernel.org/r/20230820142035.89903-10-dmitry.baryshkov@linaro.org -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 67 +++++++++++---------------- - 1 file changed, 28 insertions(+), 39 deletions(-) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -211,59 +211,48 @@ - - pcie_qmp0: phy@84000 { - compatible = "qcom,ipq8074-qmp-gen3-pcie-phy"; -- reg = <0x00084000 0x1bc>; -- #address-cells = <1>; -- #size-cells = <1>; -- ranges; -+ reg = <0x00084000 0x1000>; - - clocks = <&gcc GCC_PCIE0_AUX_CLK>, -- <&gcc GCC_PCIE0_AHB_CLK>; -- clock-names = "aux", "cfg_ahb"; -+ <&gcc GCC_PCIE0_AHB_CLK>, -+ <&gcc GCC_PCIE0_PIPE_CLK>; -+ clock-names = "aux", -+ "cfg_ahb", -+ "pipe"; -+ -+ clock-output-names = "pcie20_phy0_pipe_clk"; -+ #clock-cells = <0>; -+ -+ #phy-cells = <0>; -+ - resets = <&gcc GCC_PCIE0_PHY_BCR>, -- <&gcc GCC_PCIE0PHY_PHY_BCR>; -+ <&gcc GCC_PCIE0PHY_PHY_BCR>; - reset-names = "phy", - "common"; - status = "disabled"; -- -- pcie_phy0: phy@84200 { -- reg = <0x84200 0x16c>, -- <0x84400 0x200>, -- <0x84800 0x1f0>, -- <0x84c00 0xf4>; -- #phy-cells = <0>; -- #clock-cells = <0>; -- clocks = <&gcc GCC_PCIE0_PIPE_CLK>; -- clock-names = "pipe0"; -- clock-output-names = "pcie20_phy0_pipe_clk"; -- }; - }; - - pcie_qmp1: phy@8e000 { - compatible = "qcom,ipq8074-qmp-pcie-phy"; -- reg = <0x0008e000 0x1c4>; -- #address-cells = <1>; -- #size-cells = <1>; -- ranges; -+ reg = <0x0008e000 0x1000>; - - clocks = <&gcc GCC_PCIE1_AUX_CLK>, -- <&gcc GCC_PCIE1_AHB_CLK>; -- clock-names = "aux", "cfg_ahb"; -+ <&gcc GCC_PCIE1_AHB_CLK>, -+ <&gcc GCC_PCIE1_PIPE_CLK>; -+ clock-names = "aux", -+ "cfg_ahb", -+ "pipe"; -+ -+ clock-output-names = "pcie20_phy1_pipe_clk"; -+ #clock-cells = <0>; -+ -+ #phy-cells = <0>; -+ - resets = <&gcc GCC_PCIE1_PHY_BCR>, -- <&gcc GCC_PCIE1PHY_PHY_BCR>; -+ <&gcc GCC_PCIE1PHY_PHY_BCR>; - reset-names = "phy", - "common"; - status = "disabled"; -- -- pcie_phy1: phy@8e200 { -- reg = <0x8e200 0x130>, -- <0x8e400 0x200>, -- <0x8e800 0x1f8>; -- #phy-cells = <0>; -- #clock-cells = <0>; -- clocks = <&gcc GCC_PCIE1_PIPE_CLK>; -- clock-names = "pipe0"; -- clock-output-names = "pcie20_phy1_pipe_clk"; -- }; - }; - - mdio: mdio@90000 { -@@ -839,7 +828,7 @@ - #address-cells = <3>; - #size-cells = <2>; - -- phys = <&pcie_phy1>; -+ phys = <&pcie_qmp1>; - phy-names = "pciephy"; - - ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */ -@@ -901,7 +890,7 @@ - #address-cells = <3>; - #size-cells = <2>; - -- phys = <&pcie_phy0>; -+ phys = <&pcie_qmp0>; - phy-names = "pciephy"; - - ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */ diff --git a/target/linux/qualcommax/patches-6.12/0046-v6.8-arm64-dts-qcom-ipq8074-pass-QMP-PCI-PHY-PIPE-clocks-.patch b/target/linux/qualcommax/patches-6.12/0046-v6.8-arm64-dts-qcom-ipq8074-pass-QMP-PCI-PHY-PIPE-clocks-.patch deleted file mode 100644 index e1bdf01ded5..00000000000 --- a/target/linux/qualcommax/patches-6.12/0046-v6.8-arm64-dts-qcom-ipq8074-pass-QMP-PCI-PHY-PIPE-clocks-.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 591da388c344f934601548cb44f54eab012c6c94 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 13 Oct 2023 18:39:34 +0200 -Subject: [PATCH] arm64: dts: qcom: ipq8074: pass QMP PCI PHY PIPE clocks to - GCC - -Pass QMP PCI PHY PIPE clocks to the GCC controller so it does not have to -find them by matching globaly by name. - -If not passed directly, driver maintains backwards compatibility by then -falling back to global lookup. - -Signed-off-by: Robert Marko -Reviewed-by: Dmitry Baryshkov -Link: https://lore.kernel.org/r/20231013164025.3541606-2-robimarko@gmail.com -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 10 ++++++++-- - 1 file changed, 8 insertions(+), 2 deletions(-) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -371,8 +371,14 @@ - gcc: gcc@1800000 { - compatible = "qcom,gcc-ipq8074"; - reg = <0x01800000 0x80000>; -- clocks = <&xo>, <&sleep_clk>; -- clock-names = "xo", "sleep_clk"; -+ clocks = <&xo>, -+ <&sleep_clk>, -+ <&pcie_qmp0>, -+ <&pcie_qmp1>; -+ clock-names = "xo", -+ "sleep_clk", -+ "pcie0_pipe", -+ "pcie1_pipe"; - #clock-cells = <1>; - #power-domain-cells = <1>; - #reset-cells = <1>; diff --git a/target/linux/qualcommax/patches-6.12/0047-v6.11-PCI-qcom-Use-devm_clk_bulk_get_all-API.patch b/target/linux/qualcommax/patches-6.12/0047-v6.11-PCI-qcom-Use-devm_clk_bulk_get_all-API.patch deleted file mode 100644 index 453620f3201..00000000000 --- a/target/linux/qualcommax/patches-6.12/0047-v6.11-PCI-qcom-Use-devm_clk_bulk_get_all-API.patch +++ /dev/null @@ -1,388 +0,0 @@ -From 652935ba05860eadaa19ac9efe7aea61fb7a3aef Mon Sep 17 00:00:00 2001 -From: Manivannan Sadhasivam -Date: Wed, 17 Apr 2024 12:32:53 +0530 -Subject: [PATCH] PCI: qcom: Use devm_clk_bulk_get_all() API -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -There is no need for the device drivers to validate the clocks defined in -Devicetree. The validation should be performed by the DT schema and the -drivers should just get all the clocks from DT. Right now the driver -hardcodes the clock info and validates them against DT which is redundant. - -So use devm_clk_bulk_get_all() that just gets all the clocks defined in DT -and get rid of all static clocks info from the driver. This simplifies the -driver. - -Link: https://lore.kernel.org/linux-pci/20240417-pci-qcom-clk-bulk-v1-1-52ca19b3d6b2@linaro.org -Signed-off-by: Manivannan Sadhasivam -Signed-off-by: Krzysztof Wilczyński -Signed-off-by: Bjorn Helgaas ---- - drivers/pci/controller/dwc/pcie-qcom.c | 177 ++++++++----------------- - 1 file changed, 58 insertions(+), 119 deletions(-) - ---- a/drivers/pci/controller/dwc/pcie-qcom.c -+++ b/drivers/pci/controller/dwc/pcie-qcom.c -@@ -151,58 +151,56 @@ - - #define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0)) - --#define QCOM_PCIE_1_0_0_MAX_CLOCKS 4 - struct qcom_pcie_resources_1_0_0 { -- struct clk_bulk_data clks[QCOM_PCIE_1_0_0_MAX_CLOCKS]; -+ struct clk_bulk_data *clks; -+ int num_clks; - struct reset_control *core; - struct regulator *vdda; - }; - --#define QCOM_PCIE_2_1_0_MAX_CLOCKS 5 - #define QCOM_PCIE_2_1_0_MAX_RESETS 6 - #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 - struct qcom_pcie_resources_2_1_0 { -- struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS]; -+ struct clk_bulk_data *clks; -+ int num_clks; - struct reset_control_bulk_data resets[QCOM_PCIE_2_1_0_MAX_RESETS]; - int num_resets; - struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY]; - }; - --#define QCOM_PCIE_2_3_2_MAX_CLOCKS 4 - #define QCOM_PCIE_2_3_2_MAX_SUPPLY 2 - struct qcom_pcie_resources_2_3_2 { -- struct clk_bulk_data clks[QCOM_PCIE_2_3_2_MAX_CLOCKS]; -+ struct clk_bulk_data *clks; -+ int num_clks; - struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY]; - }; - --#define QCOM_PCIE_2_3_3_MAX_CLOCKS 5 - #define QCOM_PCIE_2_3_3_MAX_RESETS 7 - struct qcom_pcie_resources_2_3_3 { -- struct clk_bulk_data clks[QCOM_PCIE_2_3_3_MAX_CLOCKS]; -+ struct clk_bulk_data *clks; -+ int num_clks; - struct reset_control_bulk_data rst[QCOM_PCIE_2_3_3_MAX_RESETS]; - }; - --#define QCOM_PCIE_2_4_0_MAX_CLOCKS 4 - #define QCOM_PCIE_2_4_0_MAX_RESETS 12 - struct qcom_pcie_resources_2_4_0 { -- struct clk_bulk_data clks[QCOM_PCIE_2_4_0_MAX_CLOCKS]; -+ struct clk_bulk_data *clks; - int num_clks; - struct reset_control_bulk_data resets[QCOM_PCIE_2_4_0_MAX_RESETS]; - int num_resets; - }; - --#define QCOM_PCIE_2_7_0_MAX_CLOCKS 15 - #define QCOM_PCIE_2_7_0_MAX_SUPPLIES 2 - struct qcom_pcie_resources_2_7_0 { -- struct clk_bulk_data clks[QCOM_PCIE_2_7_0_MAX_CLOCKS]; -+ struct clk_bulk_data *clks; - int num_clks; - struct regulator_bulk_data supplies[QCOM_PCIE_2_7_0_MAX_SUPPLIES]; - struct reset_control *rst; - }; - --#define QCOM_PCIE_2_9_0_MAX_CLOCKS 5 - struct qcom_pcie_resources_2_9_0 { -- struct clk_bulk_data clks[QCOM_PCIE_2_9_0_MAX_CLOCKS]; -+ struct clk_bulk_data *clks; -+ int num_clks; - struct reset_control *rst; - }; - -@@ -313,21 +311,11 @@ static int qcom_pcie_get_resources_2_1_0 - if (ret) - return ret; - -- res->clks[0].id = "iface"; -- res->clks[1].id = "core"; -- res->clks[2].id = "phy"; -- res->clks[3].id = "aux"; -- res->clks[4].id = "ref"; -- -- /* iface, core, phy are required */ -- ret = devm_clk_bulk_get(dev, 3, res->clks); -- if (ret < 0) -- return ret; -- -- /* aux, ref are optional */ -- ret = devm_clk_bulk_get_optional(dev, 2, res->clks + 3); -- if (ret < 0) -- return ret; -+ res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); -+ if (res->num_clks < 0) { -+ dev_err(dev, "Failed to get clocks\n"); -+ return res->num_clks; -+ } - - res->resets[0].id = "pci"; - res->resets[1].id = "axi"; -@@ -349,7 +337,7 @@ static void qcom_pcie_deinit_2_1_0(struc - { - struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; - -- clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); -+ clk_bulk_disable_unprepare(res->num_clks, res->clks); - reset_control_bulk_assert(res->num_resets, res->resets); - - writel(1, pcie->parf + PARF_PHY_CTRL); -@@ -401,7 +389,7 @@ static int qcom_pcie_post_init_2_1_0(str - val &= ~PHY_TEST_PWR_DOWN; - writel(val, pcie->parf + PARF_PHY_CTRL); - -- ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); -+ ret = clk_bulk_prepare_enable(res->num_clks, res->clks); - if (ret) - return ret; - -@@ -452,20 +440,16 @@ static int qcom_pcie_get_resources_1_0_0 - struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; - struct dw_pcie *pci = pcie->pci; - struct device *dev = pci->dev; -- int ret; - - res->vdda = devm_regulator_get(dev, "vdda"); - if (IS_ERR(res->vdda)) - return PTR_ERR(res->vdda); - -- res->clks[0].id = "iface"; -- res->clks[1].id = "aux"; -- res->clks[2].id = "master_bus"; -- res->clks[3].id = "slave_bus"; -- -- ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); -- if (ret < 0) -- return ret; -+ res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); -+ if (res->num_clks < 0) { -+ dev_err(dev, "Failed to get clocks\n"); -+ return res->num_clks; -+ } - - res->core = devm_reset_control_get_exclusive(dev, "core"); - return PTR_ERR_OR_ZERO(res->core); -@@ -476,7 +460,7 @@ static void qcom_pcie_deinit_1_0_0(struc - struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; - - reset_control_assert(res->core); -- clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); -+ clk_bulk_disable_unprepare(res->num_clks, res->clks); - regulator_disable(res->vdda); - } - -@@ -493,7 +477,7 @@ static int qcom_pcie_init_1_0_0(struct q - return ret; - } - -- ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); -+ ret = clk_bulk_prepare_enable(res->num_clks, res->clks); - if (ret) { - dev_err(dev, "cannot prepare/enable clocks\n"); - goto err_assert_reset; -@@ -508,7 +492,7 @@ static int qcom_pcie_init_1_0_0(struct q - return 0; - - err_disable_clks: -- clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); -+ clk_bulk_disable_unprepare(res->num_clks, res->clks); - err_assert_reset: - reset_control_assert(res->core); - -@@ -556,14 +540,11 @@ static int qcom_pcie_get_resources_2_3_2 - if (ret) - return ret; - -- res->clks[0].id = "aux"; -- res->clks[1].id = "cfg"; -- res->clks[2].id = "bus_master"; -- res->clks[3].id = "bus_slave"; -- -- ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); -- if (ret < 0) -- return ret; -+ res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); -+ if (res->num_clks < 0) { -+ dev_err(dev, "Failed to get clocks\n"); -+ return res->num_clks; -+ } - - return 0; - } -@@ -572,7 +553,7 @@ static void qcom_pcie_deinit_2_3_2(struc - { - struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; - -- clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); -+ clk_bulk_disable_unprepare(res->num_clks, res->clks); - regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); - } - -@@ -589,7 +570,7 @@ static int qcom_pcie_init_2_3_2(struct q - return ret; - } - -- ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); -+ ret = clk_bulk_prepare_enable(res->num_clks, res->clks); - if (ret) { - dev_err(dev, "cannot prepare/enable clocks\n"); - regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); -@@ -637,17 +618,11 @@ static int qcom_pcie_get_resources_2_4_0 - bool is_ipq = of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019"); - int ret; - -- res->clks[0].id = "aux"; -- res->clks[1].id = "master_bus"; -- res->clks[2].id = "slave_bus"; -- res->clks[3].id = "iface"; -- -- /* qcom,pcie-ipq4019 is defined without "iface" */ -- res->num_clks = is_ipq ? 3 : 4; -- -- ret = devm_clk_bulk_get(dev, res->num_clks, res->clks); -- if (ret < 0) -- return ret; -+ res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); -+ if (res->num_clks < 0) { -+ dev_err(dev, "Failed to get clocks\n"); -+ return res->num_clks; -+ } - - res->resets[0].id = "axi_m"; - res->resets[1].id = "axi_s"; -@@ -718,15 +693,11 @@ static int qcom_pcie_get_resources_2_3_3 - struct device *dev = pci->dev; - int ret; - -- res->clks[0].id = "iface"; -- res->clks[1].id = "axi_m"; -- res->clks[2].id = "axi_s"; -- res->clks[3].id = "ahb"; -- res->clks[4].id = "aux"; -- -- ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); -- if (ret < 0) -- return ret; -+ res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); -+ if (res->num_clks < 0) { -+ dev_err(dev, "Failed to get clocks\n"); -+ return res->num_clks; -+ } - - res->rst[0].id = "axi_m"; - res->rst[1].id = "axi_s"; -@@ -747,7 +718,7 @@ static void qcom_pcie_deinit_2_3_3(struc - { - struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; - -- clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); -+ clk_bulk_disable_unprepare(res->num_clks, res->clks); - } - - static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) -@@ -777,7 +748,7 @@ static int qcom_pcie_init_2_3_3(struct q - */ - usleep_range(2000, 2500); - -- ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); -+ ret = clk_bulk_prepare_enable(res->num_clks, res->clks); - if (ret) { - dev_err(dev, "cannot prepare/enable clocks\n"); - goto err_assert_resets; -@@ -838,8 +809,6 @@ static int qcom_pcie_get_resources_2_7_0 - struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; - struct dw_pcie *pci = pcie->pci; - struct device *dev = pci->dev; -- unsigned int num_clks, num_opt_clks; -- unsigned int idx; - int ret; - - res->rst = devm_reset_control_array_get_exclusive(dev); -@@ -853,36 +822,11 @@ static int qcom_pcie_get_resources_2_7_0 - if (ret) - return ret; - -- idx = 0; -- res->clks[idx++].id = "aux"; -- res->clks[idx++].id = "cfg"; -- res->clks[idx++].id = "bus_master"; -- res->clks[idx++].id = "bus_slave"; -- res->clks[idx++].id = "slave_q2a"; -- -- num_clks = idx; -- -- ret = devm_clk_bulk_get(dev, num_clks, res->clks); -- if (ret < 0) -- return ret; -- -- res->clks[idx++].id = "tbu"; -- res->clks[idx++].id = "ddrss_sf_tbu"; -- res->clks[idx++].id = "aggre0"; -- res->clks[idx++].id = "aggre1"; -- res->clks[idx++].id = "noc_aggr"; -- res->clks[idx++].id = "noc_aggr_4"; -- res->clks[idx++].id = "noc_aggr_south_sf"; -- res->clks[idx++].id = "cnoc_qx"; -- res->clks[idx++].id = "sleep"; -- res->clks[idx++].id = "cnoc_sf_axi"; -- -- num_opt_clks = idx - num_clks; -- res->num_clks = idx; -- -- ret = devm_clk_bulk_get_optional(dev, num_opt_clks, res->clks + num_clks); -- if (ret < 0) -- return ret; -+ res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); -+ if (res->num_clks < 0) { -+ dev_err(dev, "Failed to get clocks\n"); -+ return res->num_clks; -+ } - - return 0; - } -@@ -1073,17 +1017,12 @@ static int qcom_pcie_get_resources_2_9_0 - struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; - struct dw_pcie *pci = pcie->pci; - struct device *dev = pci->dev; -- int ret; -- -- res->clks[0].id = "iface"; -- res->clks[1].id = "axi_m"; -- res->clks[2].id = "axi_s"; -- res->clks[3].id = "axi_bridge"; -- res->clks[4].id = "rchng"; - -- ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); -- if (ret < 0) -- return ret; -+ res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); -+ if (res->num_clks < 0) { -+ dev_err(dev, "Failed to get clocks\n"); -+ return res->num_clks; -+ } - - res->rst = devm_reset_control_array_get_exclusive(dev); - if (IS_ERR(res->rst)) -@@ -1096,7 +1035,7 @@ static void qcom_pcie_deinit_2_9_0(struc - { - struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; - -- clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); -+ clk_bulk_disable_unprepare(res->num_clks, res->clks); - } - - static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie) -@@ -1125,7 +1064,7 @@ static int qcom_pcie_init_2_9_0(struct q - - usleep_range(2000, 2500); - -- return clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); -+ return clk_bulk_prepare_enable(res->num_clks, res->clks); - } - - static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) diff --git a/target/linux/qualcommax/patches-6.12/0049-v6.10-arm64-dts-qcom-ipq8074-Add-PCIe-bridge-node.patch b/target/linux/qualcommax/patches-6.12/0049-v6.10-arm64-dts-qcom-ipq8074-Add-PCIe-bridge-node.patch deleted file mode 100644 index 8a272785778..00000000000 --- a/target/linux/qualcommax/patches-6.12/0049-v6.10-arm64-dts-qcom-ipq8074-Add-PCIe-bridge-node.patch +++ /dev/null @@ -1,52 +0,0 @@ -From ed3893f6f9b800ca774f63810c5f8838bc7cee78 Mon Sep 17 00:00:00 2001 -From: Manivannan Sadhasivam -Date: Thu, 21 Mar 2024 16:46:35 +0530 -Subject: [PATCH] arm64: dts: qcom: ipq8074: Add PCIe bridge node - -On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge -for each controller instance. Hence, add a node to represent the bridge. - -Signed-off-by: Manivannan Sadhasivam -Reviewed-by: Konrad Dybcio -Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-15-1eb790c53e43@linaro.org -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 20 ++++++++++++++++++++ - 1 file changed, 20 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -878,6 +878,16 @@ - "ahb", - "axi_m_sticky"; - status = "disabled"; -+ -+ pcie@0 { -+ device_type = "pci"; -+ reg = <0x0 0x0 0x0 0x0 0x0>; -+ bus-range = <0x01 0xff>; -+ -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ }; - }; - - pcie0: pci@20000000 { -@@ -943,6 +953,16 @@ - "axi_m_sticky", - "axi_s_sticky"; - status = "disabled"; -+ -+ pcie@0 { -+ device_type = "pci"; -+ reg = <0x0 0x0 0x0 0x0 0x0>; -+ bus-range = <0x01 0xff>; -+ -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ }; - }; - }; - diff --git a/target/linux/qualcommax/patches-6.12/0050-v6.10-arm64-dts-qcom-ipq6018-Add-PCIe-bridge-node.patch b/target/linux/qualcommax/patches-6.12/0050-v6.10-arm64-dts-qcom-ipq6018-Add-PCIe-bridge-node.patch deleted file mode 100644 index e831cd437a0..00000000000 --- a/target/linux/qualcommax/patches-6.12/0050-v6.10-arm64-dts-qcom-ipq6018-Add-PCIe-bridge-node.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 52358c64937e982d3cdcf64be58f08f30d8e518c Mon Sep 17 00:00:00 2001 -From: Manivannan Sadhasivam -Date: Thu, 21 Mar 2024 16:46:36 +0530 -Subject: [PATCH] arm64: dts: qcom: ipq6018: Add PCIe bridge node - -On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge -for each controller instance. Hence, add a node to represent the bridge. - -Signed-off-by: Manivannan Sadhasivam -Reviewed-by: Konrad Dybcio -Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-16-1eb790c53e43@linaro.org -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq6018.dtsi | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -911,6 +911,16 @@ - "axi_s_sticky"; - - status = "disabled"; -+ -+ pcie@0 { -+ device_type = "pci"; -+ reg = <0x0 0x0 0x0 0x0 0x0>; -+ bus-range = <0x01 0xff>; -+ -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ }; - }; - }; -