uboot-mvebu: backport two patches for Marvell A38x
This solves issue with DDR training on Turris Omnia. Log: ******** DRAM initialization Failed (res 0x1) ******** DDR3 Training Sequence - FAILED ERROR ### Please RESET the board ### Signed-off-by: Josef Schlehofer <pepe.schlehofer@gmail.com>
This commit is contained in:
Josef Schlehofer
Hauke Mehrtens
parent
5c804bc199
commit
d16bd89c71
2 changed files with 214 additions and 0 deletions
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From 3fc92a215b69ad448c151489228eb340df9a8703 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <marek.behun@nic.cz>
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Date: Wed, 12 Jan 2022 17:06:59 +0100
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Subject: [PATCH] ddr: marvell: a38x: fix SPLIT_OUT_MIX state decision
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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This is a cleaned up and fixed version of a patch
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mv_ddr: a380: fix SPLIT_OUT_MIX state decision
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in each pattern cycle the bus state can be changed
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in order to avoide it, need to back to the same bus state on each
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pattern cycle
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by
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Moti Boskula <motib@marvell.com>
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The original patch is not in Marvell's mv-ddr-marvell repository. It was
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gives to us by Marvell to fix an issues with DDR training on some
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boards, but it cannot be applied as is to mv-ddr-marvell, because it is
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a very dirty draft patch that would certainly break other things, mainly
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DDR4 training code in mv-ddr-marvell, since it changes common functions.
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I have cleaned up the patch and removed stuff that seemed unnecessary
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(when removed, it still fixed things). Note that I don't understand
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completely what the code does exactly, since I haven't studied the DDR
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training code extensively (and I suspect that no one besides some few
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people in Marvell understand the code completely).
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Anyway after the cleanup the patch still fixes isssues with DDR training
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on the failing boards.
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There was also a problem with the original patch on some of the Allied
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Telesis' x530 boards, reported by Chris Packham. I have asked Chris to
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send me some logs, and managed to fix it:
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- if you look at the change, you'll notice that it introduces
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subtraction of cur_start_win[] and cur_end_win[] members, depending on
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a bit set in the current_byte_status variable
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- the original patch subtracted cur_start_win[] if either
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BYTE_SPLIT_OUT_MIX or BYTE_HOMOGENEOUS_SPLIT_OUT bits were set, but
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subtracted cur_end_win[] only if the first one (BYTE_SPLIT_OUT_MIX)
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was set
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- from Chris Packham logs I discovered that the x530 board where the
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original patch introduced DDR training failure, only the
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BYTE_HOMOGENEOUS_SPLIT_OUT bit was set, and on our boards where the
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patch is needed only the BYTE_SPLIT_OUT_MIX is set in the
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current_byte_status variable
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- this led me to the hypothesis that both cur_start_win[] and
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cur_end_win[] should be subtracted only if BYTE_SPLIT_OUT_MIX bit is
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set, the BYTE_HOMOGENEOUS_SPLIT_OUT bit shouldn't be considered at all
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- this hypothesis also gains credibility when considering the commit
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title ("fix SPLIT_OUT_MIX state decision")
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Hopefully this will fix things without breaking anything else.
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Signed-off-by: Marek Behún <marek.behun@nic.cz>
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Reviewed-by: Stefan Roese <sr@denx.de>
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Tested-by: Chris Packham <judge.packham@gmail.com>
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---
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.../a38x/ddr3_training_centralization.c | 26 +++++++++++++++++++
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1 file changed, 26 insertions(+)
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--- a/drivers/ddr/marvell/a38x/ddr3_training_centralization.c
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+++ b/drivers/ddr/marvell/a38x/ddr3_training_centralization.c
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@@ -55,6 +55,7 @@ static int ddr3_tip_centralization(u32 d
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enum hws_training_ip_stat training_result[MAX_INTERFACE_NUM];
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u32 if_id, pattern_id, bit_id;
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u8 bus_id;
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+ u8 current_byte_status;
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u8 cur_start_win[BUS_WIDTH_IN_BITS];
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u8 centralization_result[MAX_INTERFACE_NUM][BUS_WIDTH_IN_BITS];
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u8 cur_end_win[BUS_WIDTH_IN_BITS];
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@@ -166,6 +167,10 @@ static int ddr3_tip_centralization(u32 d
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result[search_dir_id][7]));
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}
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+ current_byte_status =
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+ mv_ddr_tip_sub_phy_byte_status_get(if_id,
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+ bus_id);
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+
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for (bit_id = 0; bit_id < BUS_WIDTH_IN_BITS;
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bit_id++) {
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/* check if this code is valid for 2 edge, probably not :( */
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@@ -174,11 +179,32 @@ static int ddr3_tip_centralization(u32 d
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[HWS_LOW2HIGH]
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[bit_id],
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EDGE_1);
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+ if (current_byte_status &
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+ BYTE_SPLIT_OUT_MIX) {
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+ if (cur_start_win[bit_id] >= 64)
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+ cur_start_win[bit_id] -= 64;
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+ else
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+ cur_start_win[bit_id] = 0;
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+ DEBUG_CENTRALIZATION_ENGINE
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+ (DEBUG_LEVEL_INFO,
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+ ("pattern %d IF %d pup %d bit %d subtract 64 adll from start\n",
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+ pattern_id, if_id, bus_id, bit_id));
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+ }
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cur_end_win[bit_id] =
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GET_TAP_RESULT(result
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[HWS_HIGH2LOW]
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[bit_id],
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EDGE_1);
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+ if (cur_end_win[bit_id] >= 64 &&
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+ (current_byte_status &
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+ BYTE_SPLIT_OUT_MIX)) {
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+ cur_end_win[bit_id] -= 64;
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+ DEBUG_CENTRALIZATION_ENGINE
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+ (DEBUG_LEVEL_INFO,
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+ ("pattern %d IF %d pup %d bit %d subtract 64 adll from end\n",
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+ pattern_id, if_id, bus_id, bit_id));
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+ }
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+
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/* window length */
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current_window[bit_id] =
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cur_end_win[bit_id] -
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@ -0,0 +1,98 @@
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From eadc4f512fb43bba2fa4e842c982da919da664be Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <marek.behun@nic.cz>
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Date: Tue, 4 Jan 2022 15:57:49 +0100
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Subject: [PATCH] ddr: marvell: a38x: Fix Synchronous vs Asynchronous mode
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determination
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Before commit 4c289425752f ("mv_ddr: a38x: add support for ddr async
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mode"), Asynchornous Mode was only used when the CPU Subsystem Clock
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Options[4:0] field in the SAR1 register was set to value 0x13: CPU at
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2 GHz and DDR at 933 MHz.
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Then commit 4c289425752f ("mv_ddr: a38x: add support for ddr async
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mode") added support for Asynchornous Modes with frequencies other than
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933 MHz (but at least 467 MHz), but the code it added to check for
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whether Asynchornous Mode should be used is wrong: it checks whether the
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frequency setting in board DDR topology map is set to value other than
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MV_DDR_FREQ_SAR.
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Thus boards which define a specific value, greater than 400 MHz, for DDR
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frequency in their board topology (e.g. Turris Omnia defines
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MV_DDR_FREQ_800), are incorrectly put into Asynchornous Mode after that
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commit.
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The A38x Functional Specification, section 10.12 DRAM Clocking, says:
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In Synchornous mode, the DRAM and CPU clocks are edge aligned and run
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in 1:2 or 1:3 CPU to DRAM frequency ratios.
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Change the check for whether Asynchornous Mode should be used according
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to this explanation in Functional Specification.
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Signed-off-by: Marek Behún <marek.behun@nic.cz>
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Tested-by: Chris Packham <judge.packham@gmail.com>
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Reviewed-by: Stefan Roese <sr@denx.de>
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---
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drivers/ddr/marvell/a38x/mv_ddr_plat.c | 19 ++++++++-----------
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1 file changed, 8 insertions(+), 11 deletions(-)
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--- a/drivers/ddr/marvell/a38x/mv_ddr_plat.c
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+++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.c
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@@ -167,8 +167,6 @@ static u16 a38x_vco_freq_per_sar_ref_clk
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};
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-static u32 async_mode_at_tf;
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-
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static u32 dq_bit_map_2_phy_pin[] = {
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1, 0, 2, 6, 9, 8, 3, 7, /* 0 */
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8, 9, 1, 7, 2, 6, 3, 0, /* 1 */
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@@ -734,7 +732,8 @@ static int ddr3_tip_a38x_set_divider(u8
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u32 divider = 0;
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u32 sar_val, ref_clk_satr;
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u32 async_val;
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- u32 freq = mv_ddr_freq_get(frequency);
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+ u32 cpu_freq;
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+ u32 ddr_freq = mv_ddr_freq_get(frequency);
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if (if_id != 0) {
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DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR,
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@@ -751,11 +750,14 @@ static int ddr3_tip_a38x_set_divider(u8
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ref_clk_satr = reg_read(DEVICE_SAMPLE_AT_RESET2_REG);
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if (((ref_clk_satr >> DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_OFFSET) & 0x1) ==
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DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_25MHZ)
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- divider = a38x_vco_freq_per_sar_ref_clk_25_mhz[sar_val] / freq;
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+ cpu_freq = a38x_vco_freq_per_sar_ref_clk_25_mhz[sar_val];
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else
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- divider = a38x_vco_freq_per_sar_ref_clk_40_mhz[sar_val] / freq;
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+ cpu_freq = a38x_vco_freq_per_sar_ref_clk_40_mhz[sar_val];
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+
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+ divider = cpu_freq / ddr_freq;
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- if ((async_mode_at_tf == 1) && (freq > 400)) {
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+ if (((cpu_freq % ddr_freq != 0) || (divider != 2 && divider != 3)) &&
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+ (ddr_freq > 400)) {
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/* Set async mode */
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dunit_write(0x20220, 0x1000, 0x1000);
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dunit_write(0xe42f4, 0x200, 0x200);
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@@ -869,8 +871,6 @@ int ddr3_tip_ext_write(u32 dev_num, u32
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int mv_ddr_early_init(void)
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{
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- struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
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-
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/* FIXME: change this configuration per ddr type
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* configure a380 and a390 to work with receiver odt timing
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* the odt_config is defined:
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@@ -882,9 +882,6 @@ int mv_ddr_early_init(void)
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mv_ddr_sw_db_init(0, 0);
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- if (tm->interface_params[0].memory_freq != MV_DDR_FREQ_SAR)
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- async_mode_at_tf = 1;
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-
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return MV_OK;
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}
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