qualcommbe: add PCS driver fixes
After update to v6.12 some PCS driver fixes were dropped and additional are needed due to updated driver. Signed-off-by: Mantas Pucka <mantas@8devices.com> Link: https://github.com/openwrt/openwrt/pull/18435 Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Mantas Pucka
Robert Marko
parent
8c14f33bb4
commit
c88c2d40d0
4 changed files with 124 additions and 3 deletions
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@ -99,10 +99,10 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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+ };
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+ };
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+ };
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+ };
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+
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+
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+ pcs_uniphy1: ethernet-uniphy@7a10000 {
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+ pcs_uniphy1: ethernet-pcs@7a10000 {
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+ #address-cells = <1>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ #size-cells = <0>;
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+ compatible = "qcom,ipq9574-uniphy";
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+ compatible = "qcom,ipq9574-pcs";
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+ reg = <0x7a10000 0x10000>;
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+ reg = <0x7a10000 0x10000>;
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+ clocks = <&gcc GCC_UNIPHY1_SYS_CLK>,
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+ clocks = <&gcc GCC_UNIPHY1_SYS_CLK>,
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+ <&gcc GCC_UNIPHY1_AHB_CLK>;
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+ <&gcc GCC_UNIPHY1_AHB_CLK>;
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@ -116,7 +116,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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+ "xpcs";
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+ "xpcs";
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+ #clock-cells = <1>;
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+ #clock-cells = <1>;
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+
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+
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+ pcsuniphy1_ch0: uniphy-ch@0 {
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+ pcsuniphy1_ch0: pcs-mii@0 {
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+ reg = <0>;
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+ reg = <0>;
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+ clocks = <&nsscc NSS_CC_UNIPHY_PORT5_RX_CLK>,
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+ clocks = <&nsscc NSS_CC_UNIPHY_PORT5_RX_CLK>,
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+ <&nsscc NSS_CC_UNIPHY_PORT5_TX_CLK>;
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+ <&nsscc NSS_CC_UNIPHY_PORT5_TX_CLK>;
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@ -0,0 +1,72 @@
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From 930203b9bb94dc4ea9342f1ce176851918758ed7 Mon Sep 17 00:00:00 2001
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From: Mantas Pucka <mantas@8devices.com>
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Date: Mon, 2 Jun 2025 17:18:13 +0300
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Subject: [PATCH] net: pcs: ipq-uniphy: control MISC2 register for 2.5G
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support
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When 2500base-x mode is enabled MISC2 regsister needs to have different
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value than for other 1G modes.
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Signed-off-by: Mantas Pucka <mantas@8devices.com>
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---
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drivers/net/pcs/pcs-qcom-ipq9574.c | 17 ++++++++++++++++-
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1 file changed, 16 insertions(+), 1 deletion(-)
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--- a/drivers/net/pcs/pcs-qcom-ipq9574.c
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+++ b/drivers/net/pcs/pcs-qcom-ipq9574.c
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@@ -24,6 +24,11 @@
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#define PCS_CALIBRATION 0x1e0
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#define PCS_CALIBRATION_DONE BIT(7)
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+#define PCS_MISC2 0x218
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+#define PCS_MISC2_MODE_MASK GENMASK(6, 5)
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+#define PCS_MISC2_MODE_SGMII FIELD_PREP(PCS_MISC2_MODE_MASK, 0x1)
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+#define PCS_MISC2_MODE_SGMII_PLUS FIELD_PREP(PCS_MISC2_MODE_MASK, 0x2)
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+
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#define PCS_MODE_CTRL 0x46c
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#define PCS_MODE_SEL_MASK GENMASK(12, 8)
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#define PCS_MODE_SGMII FIELD_PREP(PCS_MODE_SEL_MASK, 0x4)
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@@ -311,7 +316,7 @@ static int ipq_pcs_config_mode(struct ip
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phy_interface_t interface)
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{
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unsigned long rate = 125000000;
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- unsigned int val, mask = PCS_MODE_SEL_MASK;
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+ unsigned int val, misc2 = 0, mask = PCS_MODE_SEL_MASK;
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int ret;
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/* Assert XPCS reset */
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@@ -321,6 +326,7 @@ static int ipq_pcs_config_mode(struct ip
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switch (interface) {
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case PHY_INTERFACE_MODE_SGMII:
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val = PCS_MODE_SGMII;
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+ misc2 = PCS_MISC2_MODE_SGMII;
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break;
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case PHY_INTERFACE_MODE_QSGMII:
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val = PCS_MODE_QSGMII;
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@@ -328,10 +334,12 @@ static int ipq_pcs_config_mode(struct ip
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case PHY_INTERFACE_MODE_1000BASEX:
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mask |= PCS_MODE_SGMII_CTRL_MASK;
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val = PCS_MODE_SGMII | PCS_MODE_SGMII_CTRL_1000BASEX;
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+ misc2 = PCS_MISC2_MODE_SGMII;
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break;
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case PHY_INTERFACE_MODE_2500BASEX:
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val = PCS_MODE_SGMII_PLUS;
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rate = 312500000;
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+ misc2 = PCS_MISC2_MODE_SGMII_PLUS;
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break;
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case PHY_INTERFACE_MODE_PSGMII:
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val = PCS_MODE_PSGMII;
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@@ -360,6 +368,13 @@ static int ipq_pcs_config_mode(struct ip
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if (ret)
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return ret;
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+ if (misc2) {
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+ ret = regmap_update_bits(qpcs->regmap, PCS_MISC2,
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+ PCS_MISC2_MODE_MASK, misc2);
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+ if (ret)
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+ return ret;
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+ }
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+
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/* PCS PLL reset */
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ret = regmap_clear_bits(qpcs->regmap, PCS_PLL_RESET, PCS_ANA_SW_RESET);
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if (ret)
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@ -0,0 +1,25 @@
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From ccdfd293f9e948f0f62ac4e9924d72539a4e81ee Mon Sep 17 00:00:00 2001
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From: Mantas Pucka <mantas@8devices.com>
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Date: Mon, 2 Jun 2025 17:19:45 +0300
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Subject: [PATCH] net: pcs: ipq-uniphy: keep autoneg enabled in SGMII mode
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For PHYs that don't use in-band-status (e.g. 2.5G PHY swiching between
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SGMII and 2500base-x), SGMII autoneg still must be enabled. Only mode
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that should use forced speed is 1000base-x
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Signed-off-by: Mantas Pucka <mantas@8devices.com>
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---
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drivers/net/pcs/pcs-qcom-ipq9574.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/drivers/net/pcs/pcs-qcom-ipq9574.c
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+++ b/drivers/net/pcs/pcs-qcom-ipq9574.c
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@@ -431,7 +431,7 @@ static int ipq_pcs_config_sgmii(struct i
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/* Nothing to do here as in-band autoneg mode is enabled
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* by default for each PCS MII port.
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*/
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- if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
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+ if (interface != PHY_INTERFACE_MODE_1000BASEX)
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return 0;
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/* Set force speed mode */
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@ -0,0 +1,24 @@
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From 0cff1d9bb695bdc0ad7bad234b92eddf849ce88f Mon Sep 17 00:00:00 2001
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From: Mantas Pucka <mantas@8devices.com>
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Date: Mon, 2 Jun 2025 17:20:58 +0300
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Subject: [PATCH] net: pcs: ipq-uniphy: fix USXGMII link-up failure
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USXGMII link-up may fail due to too short delay after PLL reset.
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Increase the delay to fix this.
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Signed-off-by: Mantas Pucka <mantas@8devices.com>
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---
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drivers/net/pcs/pcs-qcom-ipq9574.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/drivers/net/pcs/pcs-qcom-ipq9574.c
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+++ b/drivers/net/pcs/pcs-qcom-ipq9574.c
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@@ -380,7 +380,7 @@ static int ipq_pcs_config_mode(struct ip
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if (ret)
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return ret;
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- fsleep(1000);
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+ fsleep(20000);
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ret = regmap_set_bits(qpcs->regmap, PCS_PLL_RESET, PCS_ANA_SW_RESET);
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if (ret)
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return ret;
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