From c1c11120069b8e04ad4b0c6e815d2e3421944933 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Tue, 22 Jul 2025 11:58:15 +0200 Subject: [PATCH] toolchain/gcc: prevent the use of LDRD/STRD on ARMv5TE These instructions are for 64-bit load/store. On ARMv5TE, the CPU requires addresses to be aligned to 64-bit. When misaligned, behavior is undefined (effectively either loads the same word twice on LDRD, or corrupts surrounding memory on STRD). On ARMv6 and newer, unaligned access is safe. Removing these instructions for ARMv5TE is necessary, because GCC ignores alignment information in pointers and does unsafe optimizations that have shown up as bugs in various places. This patch was originally added more than 11 years ago in commit b050f87d13b5, but got lost 6 years ago, when gcc 9.1 was added in 88c07c655262. This primarily affects the kirkwood and ixp4xx targets Signed-off-by: Felix Fietkau --- .../gcc/patches-12.x/800-arm_v5te_no_ldrd_strd.patch | 11 +++++++++++ .../gcc/patches-13.x/800-arm_v5te_no_ldrd_strd.patch | 11 +++++++++++ .../gcc/patches-14.x/800-arm_v5te_no_ldrd_strd.patch | 11 +++++++++++ .../gcc/patches-15.x/800-arm_v5te_no_ldrd_strd.patch | 11 +++++++++++ 4 files changed, 44 insertions(+) create mode 100644 toolchain/gcc/patches-12.x/800-arm_v5te_no_ldrd_strd.patch create mode 100644 toolchain/gcc/patches-13.x/800-arm_v5te_no_ldrd_strd.patch create mode 100644 toolchain/gcc/patches-14.x/800-arm_v5te_no_ldrd_strd.patch create mode 100644 toolchain/gcc/patches-15.x/800-arm_v5te_no_ldrd_strd.patch diff --git a/toolchain/gcc/patches-12.x/800-arm_v5te_no_ldrd_strd.patch b/toolchain/gcc/patches-12.x/800-arm_v5te_no_ldrd_strd.patch new file mode 100644 index 00000000000..e83cb1bebbb --- /dev/null +++ b/toolchain/gcc/patches-12.x/800-arm_v5te_no_ldrd_strd.patch @@ -0,0 +1,11 @@ +--- a/gcc/config/arm/arm.h ++++ b/gcc/config/arm/arm.h +@@ -165,7 +165,7 @@ emission of floating point pcs attribute + /* Thumb-1 only. */ + #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) + +-#define TARGET_LDRD (arm_arch5te && ARM_DOUBLEWORD_ALIGN \ ++#define TARGET_LDRD (arm_arch6 && ARM_DOUBLEWORD_ALIGN \ + && !TARGET_THUMB1) + + #define TARGET_CRC32 (arm_arch_crc) diff --git a/toolchain/gcc/patches-13.x/800-arm_v5te_no_ldrd_strd.patch b/toolchain/gcc/patches-13.x/800-arm_v5te_no_ldrd_strd.patch new file mode 100644 index 00000000000..e83cb1bebbb --- /dev/null +++ b/toolchain/gcc/patches-13.x/800-arm_v5te_no_ldrd_strd.patch @@ -0,0 +1,11 @@ +--- a/gcc/config/arm/arm.h ++++ b/gcc/config/arm/arm.h +@@ -165,7 +165,7 @@ emission of floating point pcs attribute + /* Thumb-1 only. */ + #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) + +-#define TARGET_LDRD (arm_arch5te && ARM_DOUBLEWORD_ALIGN \ ++#define TARGET_LDRD (arm_arch6 && ARM_DOUBLEWORD_ALIGN \ + && !TARGET_THUMB1) + + #define TARGET_CRC32 (arm_arch_crc) diff --git a/toolchain/gcc/patches-14.x/800-arm_v5te_no_ldrd_strd.patch b/toolchain/gcc/patches-14.x/800-arm_v5te_no_ldrd_strd.patch new file mode 100644 index 00000000000..e83cb1bebbb --- /dev/null +++ b/toolchain/gcc/patches-14.x/800-arm_v5te_no_ldrd_strd.patch @@ -0,0 +1,11 @@ +--- a/gcc/config/arm/arm.h ++++ b/gcc/config/arm/arm.h +@@ -165,7 +165,7 @@ emission of floating point pcs attribute + /* Thumb-1 only. */ + #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) + +-#define TARGET_LDRD (arm_arch5te && ARM_DOUBLEWORD_ALIGN \ ++#define TARGET_LDRD (arm_arch6 && ARM_DOUBLEWORD_ALIGN \ + && !TARGET_THUMB1) + + #define TARGET_CRC32 (arm_arch_crc) diff --git a/toolchain/gcc/patches-15.x/800-arm_v5te_no_ldrd_strd.patch b/toolchain/gcc/patches-15.x/800-arm_v5te_no_ldrd_strd.patch new file mode 100644 index 00000000000..e83cb1bebbb --- /dev/null +++ b/toolchain/gcc/patches-15.x/800-arm_v5te_no_ldrd_strd.patch @@ -0,0 +1,11 @@ +--- a/gcc/config/arm/arm.h ++++ b/gcc/config/arm/arm.h +@@ -165,7 +165,7 @@ emission of floating point pcs attribute + /* Thumb-1 only. */ + #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) + +-#define TARGET_LDRD (arm_arch5te && ARM_DOUBLEWORD_ALIGN \ ++#define TARGET_LDRD (arm_arch6 && ARM_DOUBLEWORD_ALIGN \ + && !TARGET_THUMB1) + + #define TARGET_CRC32 (arm_arch_crc)