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realtek: timer: Fix cosmetic whitespace in comments

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Comments are a bit weird in the timer driver, lets fix those.

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
This commit is contained in:
Olliver Schinagl 2023-01-28 15:26:35 +01:00 committed by Sander Vanheule
parent f6ba61b929
commit afb5d9e9d5
1 changed files with 7 additions and 20 deletions
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27
target/linux/realtek/files-5.15/drivers/clocksource/timer-rtl-otto.c
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@ -27,7 +27,6 @@
* the timer is in operating mode COUNTER it stops. In mode TIMER it will * the timer is in operating mode COUNTER it stops. In mode TIMER it will
* continue to count up. * continue to count up.
*/ */
#define RTTM_CTRL_COUNTER 0 #define RTTM_CTRL_COUNTER 0
#define RTTM_CTRL_TIMER BIT(24) #define RTTM_CTRL_TIMER BIT(24)
@ -43,7 +42,6 @@
* MHz and 153.125 MHz. The greatest common divisor of all explained possible * MHz and 153.125 MHz. The greatest common divisor of all explained possible
* speeds is 3125000. Pin the timers to this 3.125 MHz reference frequency. * speeds is 3125000. Pin the timers to this 3.125 MHz reference frequency.
*/ */
#define RTTM_TICKS_PER_SEC 3125000 #define RTTM_TICKS_PER_SEC 3125000
struct rttm_cs { struct rttm_cs {
@ -51,10 +49,7 @@ struct rttm_cs {
struct clocksource cs; struct clocksource cs;
}; };
/* /* Simple internal register functions */
* Simple internal register functions
*/
static inline void rttm_set_counter(void __iomem *base, unsigned int counter) static inline void rttm_set_counter(void __iomem *base, unsigned int counter)
{ {
iowrite32(counter, base + RTTM_CNT); iowrite32(counter, base + RTTM_CNT);
@ -95,10 +90,7 @@ static inline void rttm_disable_irq(void __iomem *base)
iowrite32(0, base + RTTM_INT); iowrite32(0, base + RTTM_INT);
} }
/* /* Aggregated control functions for kernel clock framework */
* Aggregated control functions for kernel clock framework
*/
#define RTTM_DEBUG(base) \ #define RTTM_DEBUG(base) \
pr_debug("------------- %s %d %08x\n", __func__, \ pr_debug("------------- %s %d %08x\n", __func__, \
smp_processor_id(), (u32)base) smp_processor_id(), (u32)base)
@ -187,10 +179,7 @@ static u64 rttm_read_clocksource(struct clocksource *cs)
return (u64)rttm_get_counter(rcs->to.of_base.base); return (u64)rttm_get_counter(rcs->to.of_base.base);
} }
/* /* Module initialization part. */
* Module initialization part.
*/
static DEFINE_PER_CPU(struct timer_of, rttm_to) = { static DEFINE_PER_CPU(struct timer_of, rttm_to) = {
.flags = TIMER_OF_BASE | TIMER_OF_CLOCK | TIMER_OF_IRQ, .flags = TIMER_OF_BASE | TIMER_OF_CLOCK | TIMER_OF_IRQ,
.of_irq = { .of_irq = {
@ -256,9 +245,8 @@ static int __init rttm_probe(struct device_node *np)
int cpu, cpu_rollback; int cpu, cpu_rollback;
struct timer_of *to; struct timer_of *to;
int clkidx = num_possible_cpus(); int clkidx = num_possible_cpus();
/*
* Use the first n timers as per CPU clock event generators /* Use the first n timers as per CPU clock event generators */
*/
for_each_possible_cpu(cpu) { for_each_possible_cpu(cpu) {
to = per_cpu_ptr(&rttm_to, cpu); to = per_cpu_ptr(&rttm_to, cpu);
to->of_irq.index = to->of_base.index = cpu; to->of_irq.index = to->of_base.index = cpu;
@ -268,9 +256,8 @@ static int __init rttm_probe(struct device_node *np)
} }
rttm_setup_timer(to->of_base.base); rttm_setup_timer(to->of_base.base);
} }
/*
* Activate the n'th+1 timer as a stable CPU clocksource. /* Activate the n'th + 1 timer as a stable CPU clocksource. */
*/
to = &rttm_cs.to; to = &rttm_cs.to;
to->of_base.index = clkidx; to->of_base.index = clkidx;
timer_of_init(np, to); timer_of_init(np, to);