From 75505c5ec724b9b961dcb411bac1d4b9aede3e1d Mon Sep 17 00:00:00 2001 From: Christian Lamparter Date: Tue, 4 Jul 2023 20:42:22 +0200 Subject: [PATCH 01/53] ipq-wifi: fix upstream board-2.bin ZTE M289F snafu The upstream board-2.bin file in the linux-firmware.git repository for the QCA4019 contains a packed board-2.bin for this device for both 2.4G and 5G wifis. This isn't something that the ath10k driver supports. Until this feature either gets implemented - which is very unlikely -, or the upstream boardfile is mended (both, the original submitter and ath10k-firmware custodian have been notified). OpenWrt will go back and use its own bespoke boardfile. This unfortunately means that 2.4G and on some revisions the 5G WiFi is not available in the initramfs image for this device. Fixes: #12886 Reported-by: Christian Heuff Debugged-by: Georgios Kourachanis Signed-off-by: Christian Lamparter --- package/firmware/ipq-wifi/Makefile | 4 +++- target/linux/ipq40xx/image/generic.mk | 2 +- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/package/firmware/ipq-wifi/Makefile b/package/firmware/ipq-wifi/Makefile index 9b0d4c5c9fd..1e4b3a95c20 100644 --- a/package/firmware/ipq-wifi/Makefile +++ b/package/firmware/ipq-wifi/Makefile @@ -2,7 +2,7 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/version.mk PKG_NAME:=ipq-wifi -PKG_RELEASE:=1 +PKG_RELEASE:=2 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/firmware/qca-wireless.git @@ -40,6 +40,7 @@ ALLWIFIBOARDS:= \ wallys_dr40x9 \ xiaomi_ax3600 \ xiaomi_ax9000 \ + zte_mf289f \ zte_mf287plus \ zyxel_nbg7815 @@ -127,6 +128,7 @@ $(eval $(call generate-ipq-wifi-package,redmi_ax6,Redmi AX6)) $(eval $(call generate-ipq-wifi-package,wallys_dr40x9,Wallys DR40X9)) $(eval $(call generate-ipq-wifi-package,xiaomi_ax3600,Xiaomi AX3600)) $(eval $(call generate-ipq-wifi-package,xiaomi_ax9000,Xiaomi AX9000)) +$(eval $(call generate-ipq-wifi-package,zte_mf289f,ZTE MF289F)) $(eval $(call generate-ipq-wifi-package,zte_mf287plus,ZTE MF287Plus)) $(eval $(call generate-ipq-wifi-package,zyxel_nbg7815,Zyxel NBG7815)) diff --git a/target/linux/ipq40xx/image/generic.mk b/target/linux/ipq40xx/image/generic.mk index b9e9e478d9f..f15463ae8ca 100644 --- a/target/linux/ipq40xx/image/generic.mk +++ b/target/linux/ipq40xx/image/generic.mk @@ -1169,7 +1169,7 @@ TARGET_DEVICES += zte_mf287plus define Device/zte_mf289f $(call Device/zte_mf28x_common) DEVICE_MODEL := MF289F - DEVICE_PACKAGES += ath10k-firmware-qca9984-ct + DEVICE_PACKAGES += ipq-wifi-zte_mf289f ath10k-firmware-qca9984-ct endef TARGET_DEVICES += zte_mf289f From 0ea826418947585e40756fd82a82c399101de014 Mon Sep 17 00:00:00 2001 From: Christian Svensson Date: Mon, 3 Jul 2023 00:00:07 +0200 Subject: [PATCH 02/53] kernel: add kmod-hwmon-max6697 support Add package for Maxim MAX6697 I2C based temperature sensor. Signed-off-by: Christian Svensson --- package/kernel/linux/modules/hwmon.mk | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/package/kernel/linux/modules/hwmon.mk b/package/kernel/linux/modules/hwmon.mk index 23e32655b2c..69010faedd0 100644 --- a/package/kernel/linux/modules/hwmon.mk +++ b/package/kernel/linux/modules/hwmon.mk @@ -369,6 +369,21 @@ endef $(eval $(call KernelPackage,hwmon-max6642)) +define KernelPackage/hwmon-max6697 + TITLE:=MAX6697 monitoring support + KCONFIG:=CONFIG_SENSORS_MAX6697 + FILES:=$(LINUX_DIR)/drivers/hwmon/max6697.ko + AUTOLOAD:=$(call AutoProbe,max6697) + $(call AddDepends/hwmon,+kmod-i2c-core) +endef + +define KernelPackage/hwmon-max6697/description + Kernel module for Maxim MAX6697 temperature monitor +endef + +$(eval $(call KernelPackage,hwmon-max6697)) + + define KernelPackage/hwmon-mcp3021 TITLE:=MCP3021/3221 monitoring support KCONFIG:=CONFIG_SENSORS_MCP3021 From b025df645e7e578cdc87e99075062edc82c00484 Mon Sep 17 00:00:00 2001 From: Christian Svensson Date: Mon, 3 Jul 2023 00:02:14 +0200 Subject: [PATCH 03/53] kernel: add kmod-hwmon-jc42 support Add package for Jedec JC42.4 compliant temperature sensor. Signed-off-by: Christian Svensson --- package/kernel/linux/modules/hwmon.mk | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/package/kernel/linux/modules/hwmon.mk b/package/kernel/linux/modules/hwmon.mk index 69010faedd0..5761c4bc6b7 100644 --- a/package/kernel/linux/modules/hwmon.mk +++ b/package/kernel/linux/modules/hwmon.mk @@ -217,6 +217,21 @@ endef $(eval $(call KernelPackage,hwmon-it87)) +define KernelPackage/hwmon-jc42 + TITLE:=Jedec JC42.4 compliant temperature sensors support + KCONFIG:=CONFIG_SENSORS_JC42 + FILES:=$(LINUX_DIR)/drivers/hwmon/jc42.ko + AUTOLOAD:=$(call AutoProbe,jc42) + $(call AddDepends/hwmon,+kmod-i2c-core +kmod-regmap-i2c) +endef + +define KernelPackage/hwmon-jc42/description + Kernel module for Jedec JC42.4 compliant temperature sensors +endef + +$(eval $(call KernelPackage,hwmon-jc42)) + + define KernelPackage/hwmon-lm63 TITLE:=LM63/64 monitoring support KCONFIG:=CONFIG_SENSORS_LM63 From 10616779f11be835da8e56918f2e0e9de3f0539f Mon Sep 17 00:00:00 2001 From: Christian Svensson Date: Mon, 3 Jul 2023 00:03:18 +0200 Subject: [PATCH 04/53] kernel: add kmod-i2c-mux-reg support Add package for register-based I2C bus mux/switching devices. Signed-off-by: Christian Svensson --- package/kernel/linux/modules/i2c.mk | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/package/kernel/linux/modules/i2c.mk b/package/kernel/linux/modules/i2c.mk index 1c65a26edce..7cd69dbb95a 100644 --- a/package/kernel/linux/modules/i2c.mk +++ b/package/kernel/linux/modules/i2c.mk @@ -200,6 +200,22 @@ endef $(eval $(call KernelPackage,i2c-mux-gpio)) +I2C_MUX_REG_MODULES:= \ + CONFIG_I2C_MUX_REG:drivers/i2c/muxes/i2c-mux-reg + +define KernelPackage/i2c-mux-reg + $(call i2c_defaults,$(I2C_MUX_REG_MODULES),51) + TITLE:=Register-based I2C mux/switches + DEPENDS:=+kmod-i2c-mux +endef + +define KernelPackage/i2c-mux-reg/description + Kernel modules for register-based I2C bus mux/switching devices +endef + +$(eval $(call KernelPackage,i2c-mux-reg)) + + I2C_MUX_PCA9541_MODULES:= \ CONFIG_I2C_MUX_PCA9541:drivers/i2c/muxes/i2c-mux-pca9541 From d9070f8d23621931c4869980f6e5ae17abbe3e58 Mon Sep 17 00:00:00 2001 From: David Bauer Date: Wed, 5 Jul 2023 01:35:02 +0200 Subject: [PATCH 05/53] mac80211: partly revert force-mac80211 loss detection This patch will only force mac80211 loss detection upon ath10k by masking the driver-specific loss-detection bit. Ref: commit ed816f6ba8b5 ("mac80211: always use mac80211 loss detection") Signed-off-by: David Bauer --- ...k-always-use-mac80211-loss-detection.patch | 28 +++++++++++++++ ...k-always-use-mac80211-loss-detection.patch | 28 +++++++++++++++ ...1-always-use-mac80211-loss-detection.patch | 36 ------------------- 3 files changed, 56 insertions(+), 36 deletions(-) create mode 100644 package/kernel/ath10k-ct/patches/988-ath10k-always-use-mac80211-loss-detection.patch create mode 100644 package/kernel/mac80211/patches/ath10k/988-ath10k-always-use-mac80211-loss-detection.patch delete mode 100644 package/kernel/mac80211/patches/subsys/340-mac80211-always-use-mac80211-loss-detection.patch diff --git a/package/kernel/ath10k-ct/patches/988-ath10k-always-use-mac80211-loss-detection.patch b/package/kernel/ath10k-ct/patches/988-ath10k-always-use-mac80211-loss-detection.patch new file mode 100644 index 00000000000..40f262464b1 --- /dev/null +++ b/package/kernel/ath10k-ct/patches/988-ath10k-always-use-mac80211-loss-detection.patch @@ -0,0 +1,28 @@ +From f7d6edafe4358e3880a26775cfde4cd5c71ba063 Mon Sep 17 00:00:00 2001 +From: David Bauer +Date: Wed, 5 Jul 2023 01:30:29 +0200 +Subject: [PATCH] ath10k: always use mac80211 loss detection + +ath10k does not report excessive loss in case of broken block-ack +sessions. The loss is communicated to the host-os, but ath10k does not +trigger a low-ack events by itself. + +The mac80211 framework for loss detection however detects this +circumstance well in case of ath10k. So use it regardless of ath10k's +own loss detection mechanism. + +Signed-off-by: David Bauer +--- + ath10k-6.2/mac.c | 1 - + 1 file changed, 1 deletion(-) + +--- a/ath10k-6.2/mac.c ++++ b/ath10k-6.2/mac.c +@@ -11306,7 +11306,6 @@ int ath10k_mac_register(struct ath10k *a + ieee80211_hw_set(ar->hw, CHANCTX_STA_CSA); + ieee80211_hw_set(ar->hw, QUEUE_CONTROL); + ieee80211_hw_set(ar->hw, SUPPORTS_TX_FRAG); +- ieee80211_hw_set(ar->hw, REPORTS_LOW_ACK); + + if (!test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) + ieee80211_hw_set(ar->hw, SW_CRYPTO_CONTROL); diff --git a/package/kernel/mac80211/patches/ath10k/988-ath10k-always-use-mac80211-loss-detection.patch b/package/kernel/mac80211/patches/ath10k/988-ath10k-always-use-mac80211-loss-detection.patch new file mode 100644 index 00000000000..f025fea63b7 --- /dev/null +++ b/package/kernel/mac80211/patches/ath10k/988-ath10k-always-use-mac80211-loss-detection.patch @@ -0,0 +1,28 @@ +From f7d6edafe4358e3880a26775cfde4cd5c71ba063 Mon Sep 17 00:00:00 2001 +From: David Bauer +Date: Wed, 5 Jul 2023 01:30:29 +0200 +Subject: [PATCH] ath10k: always use mac80211 loss detection + +ath10k does not report excessive loss in case of broken block-ack +sessions. The loss is communicated to the host-os, but ath10k does not +trigger a low-ack events by itself. + +The mac80211 framework for loss detection however detects this +circumstance well in case of ath10k. So use it regardless of ath10k's +own loss detection mechanism. + +Signed-off-by: David Bauer +--- + drivers/net/wireless/ath/ath10k/mac.c | 1 - + 1 file changed, 1 deletion(-) + +--- a/drivers/net/wireless/ath/ath10k/mac.c ++++ b/drivers/net/wireless/ath/ath10k/mac.c +@@ -10080,7 +10080,6 @@ int ath10k_mac_register(struct ath10k *a + ieee80211_hw_set(ar->hw, CHANCTX_STA_CSA); + ieee80211_hw_set(ar->hw, QUEUE_CONTROL); + ieee80211_hw_set(ar->hw, SUPPORTS_TX_FRAG); +- ieee80211_hw_set(ar->hw, REPORTS_LOW_ACK); + + if (!test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) + ieee80211_hw_set(ar->hw, SW_CRYPTO_CONTROL); diff --git a/package/kernel/mac80211/patches/subsys/340-mac80211-always-use-mac80211-loss-detection.patch b/package/kernel/mac80211/patches/subsys/340-mac80211-always-use-mac80211-loss-detection.patch deleted file mode 100644 index e084773fd9c..00000000000 --- a/package/kernel/mac80211/patches/subsys/340-mac80211-always-use-mac80211-loss-detection.patch +++ /dev/null @@ -1,36 +0,0 @@ -From cdf461888f900c3a149b10a04d72b4a590ecdec3 Mon Sep 17 00:00:00 2001 -From: David Bauer -Date: Tue, 16 May 2023 23:11:32 +0200 -Subject: [PATCH] mac80211: always use mac80211 loss detection - -ath10k does not report excessive loss in case of broken block-ack -sessions. The loss is communicated to the host-os, but ath10k does not -trigger a low-ack events by itself. - -The mac80211 framework for loss detection however detects this -circumstance well in case of ath10k. So use it regardless of ath10k's -own loss detection mechanism. - -Patching this in mac80211 does allow this hack to be used with any -flavor of ath10k/ath11k. - -Signed-off-by: David Bauer ---- - net/mac80211/status.c | 6 ------ - 1 file changed, 6 deletions(-) - ---- a/net/mac80211/status.c -+++ b/net/mac80211/status.c -@@ -794,12 +794,6 @@ static void ieee80211_lost_packet(struct - unsigned long pkt_time = STA_LOST_PKT_TIME; - unsigned int pkt_thr = STA_LOST_PKT_THRESHOLD; - -- /* If driver relies on its own algorithm for station kickout, skip -- * mac80211 packet loss mechanism. -- */ -- if (ieee80211_hw_check(&sta->local->hw, REPORTS_LOW_ACK)) -- return; -- - /* This packet was aggregated but doesn't carry status info */ - if ((info->flags & IEEE80211_TX_CTL_AMPDU) && - !(info->flags & IEEE80211_TX_STAT_AMPDU)) From 21ab20bc64f5608d9341b1878fa1c5a569b471d5 Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Fri, 27 Jan 2023 16:32:31 +0100 Subject: [PATCH 06/53] rules: prepare to use different linkers This explicitely adds the default linker to the target LDFLAGS. No functional change intended. Signed-off-by: Andre Heider --- rules.mk | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/rules.mk b/rules.mk index 58c53705a28..1cedd91aa8d 100644 --- a/rules.mk +++ b/rules.mk @@ -211,6 +211,10 @@ ifndef DUMP endif endif endif + +TARGET_LINKER?=bfd +TARGET_LDFLAGS+= -fuse-ld=$(TARGET_LINKER) + TARGET_PATH_PKG:=$(STAGING_DIR)/host/bin:$(STAGING_DIR_HOSTPKG)/bin:$(TARGET_PATH) ifeq ($(CONFIG_SOFT_FLOAT),y) @@ -252,6 +256,7 @@ TARGET_RANLIB:=$(TARGET_CROSS)gcc-ranlib TARGET_NM:=$(TARGET_CROSS)gcc-nm TARGET_CC:=$(TARGET_CROSS)gcc TARGET_CXX:=$(TARGET_CROSS)g++ +TARGET_LD:=$(TARGET_CROSS)ld.$(TARGET_LINKER) KPATCH:=$(SCRIPT_DIR)/patch-kernel.sh FILECMD:=$(STAGING_DIR_HOST)/bin/file SED:=$(STAGING_DIR_HOST)/bin/sed -i -e @@ -305,7 +310,7 @@ endif TARGET_CONFIGURE_OPTS = \ AR="$(TARGET_AR)" \ AS="$(TARGET_CC) -c $(TARGET_ASFLAGS)" \ - LD=$(TARGET_CROSS)ld \ + LD="$(TARGET_LD)" \ NM="$(TARGET_NM)" \ CC="$(TARGET_CC)" \ GCC="$(TARGET_CC)" \ From ca788d615fbf780b1a1665475ed304de4276f512 Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Fri, 27 Jan 2023 16:33:25 +0100 Subject: [PATCH 07/53] meson: prepare to use different linkers This sets the default linker for cross compilation. No functional change intended. Signed-off-by: Andre Heider --- include/meson.mk | 1 + tools/meson/Makefile | 1 + tools/meson/files/openwrt-cross.txt.in | 2 ++ 3 files changed, 4 insertions(+) diff --git a/include/meson.mk b/include/meson.mk index 7d67dcf298b..74c9d3dd7fa 100644 --- a/include/meson.mk +++ b/include/meson.mk @@ -78,6 +78,7 @@ define Meson/CreateCrossFile $(STAGING_DIR_HOST)/bin/sed \ -e "s|@CC@|$(foreach BIN,$(TARGET_CC),'$(BIN)',)|" \ -e "s|@CXX@|$(foreach BIN,$(TARGET_CXX),'$(BIN)',)|" \ + -e "s|@LD@|$(foreach FLAG,$(TARGET_LINKER),'$(FLAG)',)|" \ -e "s|@AR@|$(TARGET_AR)|" \ -e "s|@STRIP@|$(TARGET_CROSS)strip|" \ -e "s|@NM@|$(TARGET_NM)|" \ diff --git a/tools/meson/Makefile b/tools/meson/Makefile index b115e0802b5..f957bfb49f0 100644 --- a/tools/meson/Makefile +++ b/tools/meson/Makefile @@ -2,6 +2,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=meson PKG_VERSION:=1.1.1 +PKG_RELEASE:=2 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=https://github.com/mesonbuild/meson/releases/download/$(PKG_VERSION) diff --git a/tools/meson/files/openwrt-cross.txt.in b/tools/meson/files/openwrt-cross.txt.in index ec4b027f1b7..ba119150691 100644 --- a/tools/meson/files/openwrt-cross.txt.in +++ b/tools/meson/files/openwrt-cross.txt.in @@ -1,6 +1,8 @@ [binaries] c = [@CC@] +c_ld = [@LD@] cpp = [@CXX@] +cpp_ld = [@LD@] ar = '@AR@' strip = '@STRIP@' nm = '@NM@' From d026b19cdcda50766e1ecc350fdc7c542e0f1c73 Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Sat, 28 Jan 2023 21:16:16 +0100 Subject: [PATCH 08/53] build: replace SSTRIP_ARGS with SSTRIP_DISCARD_TRAILING_ZEROES sstrip only has one functional arg. Make that a bool option, which can easily depend on other knobs then. This is required to be disabled for the mold linker. Signed-off-by: Andre Heider --- config/Config-build.in | 10 ++++------ rules.mk | 2 +- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/config/Config-build.in b/config/Config-build.in index df2d9101ca9..f8d0f8e0bd2 100644 --- a/config/Config-build.in +++ b/config/Config-build.in @@ -182,7 +182,6 @@ menu "Global build settings" help This will install binaries stripped using strip from binutils. - config USE_SSTRIP bool "sstrip" depends on !USE_GLIBC @@ -199,13 +198,12 @@ menu "Global build settings" help Specifies arguments passed to the strip command when stripping binaries. - config SSTRIP_ARGS - string - prompt "Sstrip arguments" + config SSTRIP_DISCARD_TRAILING_ZEROES + bool "Strip trailing zero bytes" depends on USE_SSTRIP - default "-z" + default y help - Specifies arguments passed to the sstrip command when stripping binaries. + Use sstrip's -z option to discard trailing zero bytes config STRIP_KERNEL_EXPORTS bool "Strip unnecessary exports from the kernel image" diff --git a/rules.mk b/rules.mk index 1cedd91aa8d..ca27583d27e 100644 --- a/rules.mk +++ b/rules.mk @@ -330,7 +330,7 @@ else STRIP:=$(TARGET_CROSS)strip $(call qstrip,$(CONFIG_STRIP_ARGS)) else ifneq ($(CONFIG_USE_SSTRIP),) - STRIP:=$(STAGING_DIR_HOST)/bin/sstrip $(call qstrip,$(CONFIG_SSTRIP_ARGS)) + STRIP:=$(STAGING_DIR_HOST)/bin/sstrip $(if $(CONFIG_SSTRIP_DISCARD_TRAILING_ZEROES),-z) endif endif RSTRIP= \ From 65a716bb95baa3b2617bafe6a86173da8cea7933 Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Fri, 27 Jan 2023 17:13:15 +0100 Subject: [PATCH 09/53] config: add a knob to use the mold linker for packages Building it requires gcc >= 10.2 or clang >= 12. Using sstrip with its -z argument can produce non-working binaries, like a segfaulting `getrandom`, so don't allow that combination. Signed-off-by: Andre Heider --- config/Config-build.in | 15 ++++++++++++++- config/check-hostcxx.sh | 12 ++++++++++++ 2 files changed, 26 insertions(+), 1 deletion(-) create mode 100755 config/check-hostcxx.sh diff --git a/config/Config-build.in b/config/Config-build.in index f8d0f8e0bd2..5f9a1be8586 100644 --- a/config/Config-build.in +++ b/config/Config-build.in @@ -159,6 +159,19 @@ menu "Global build settings" Adds LTO flags to the CFLAGS and LDFLAGS. Packages can choose to opt-out via setting PKG_BUILD_FLAGS:=no-lto + config MOLD + depends on (aarch64 || arm || i386 || i686 || m68k || powerpc || powerpc64 || sh4 || x86_64) + depends on !GCC_USE_VERSION_11 + def_bool $(shell, ./config/check-hostcxx.sh 10 2 12) + + config USE_MOLD + bool + prompt "Use the mold linker for all packages" + depends on MOLD + help + Link packages with mold, a modern linker + Packages can opt-out via setting PKG_BUILD_FLAGS:=no-mold + config IPV6 def_bool y @@ -200,7 +213,7 @@ menu "Global build settings" config SSTRIP_DISCARD_TRAILING_ZEROES bool "Strip trailing zero bytes" - depends on USE_SSTRIP + depends on USE_SSTRIP && !USE_MOLD default y help Use sstrip's -z option to discard trailing zero bytes diff --git a/config/check-hostcxx.sh b/config/check-hostcxx.sh new file mode 100755 index 00000000000..442f4cfb408 --- /dev/null +++ b/config/check-hostcxx.sh @@ -0,0 +1,12 @@ +cat << EOF | "$STAGING_DIR_HOST/bin/g++" -c -x c++ -o /dev/null - >/dev/null 2>&1 +#if __clang__ + #if __clang_major__ < $3 + #error "clang too old" + #endif +#else + #if __GNUC__ < $1 || (__GNUC__ == $1 && (__GNUC_MINOR__ < $2)) + #error "gcc too old" + #endif +#endif +EOF +[ $? -eq 0 ] && echo y || echo n From b1fa9e3d2bbbcbb1da522f23ac83d411136b74de Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Fri, 27 Jan 2023 17:53:02 +0100 Subject: [PATCH 10/53] tools: add mold, a modern linker mold is a faster drop-in replacement for existing Unix linkers. A single binary is able to link various targets, which is why this lives in tools/. All toolchain builds then just need to copy the linker over, hence avoiding multiple builds with the same outcome. Signed-off-by: Andre Heider --- tools/Makefile | 2 ++ tools/mold/Makefile | 22 ++++++++++++++++++++++ 2 files changed, 24 insertions(+) create mode 100644 tools/mold/Makefile diff --git a/tools/Makefile b/tools/Makefile index 40c3ec1ab09..bf525d34a05 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -83,6 +83,7 @@ tools-$(if $(CONFIG_BUILD_ALL_HOST_TOOLS)$(CONFIG_TARGET_tegra),y) += cbootimage tools-$(if $(CONFIG_BUILD_ALL_HOST_TOOLS)$(CONFIG_USES_MINOR),y) += kernel2minor tools-$(if $(CONFIG_BUILD_ALL_HOST_TOOLS)$(CONFIG_USE_SPARSE),y) += sparse tools-$(if $(CONFIG_BUILD_ALL_HOST_TOOLS)$(CONFIG_USE_LLVM_BUILD),y) += llvm-bpf +tools-$(if $(CONFIG_BUILD_ALL_HOST_TOOLS)$(CONFIG_USE_MOLD),y) += mold # builddir dependencies $(curdir)/autoconf/compile := $(curdir)/m4/compile @@ -114,6 +115,7 @@ $(curdir)/meson/compile := $(curdir)/ninja/compile $(curdir)/missing-macros/compile := $(curdir)/autoconf/compile $(curdir)/mkimage/compile += $(curdir)/bison/compile $(curdir)/libressl/compile $(curdir)/mklibs/compile := $(curdir)/libtool/compile +$(curdir)/mold/compile := $(curdir)/cmake/compile $(curdir)/zlib/compile $(curdir)/zstd/compile $(curdir)/mpc/compile := $(curdir)/mpfr/compile $(curdir)/gmp/compile $(curdir)/mpfr/compile := $(curdir)/gmp/compile $(curdir)/mtd-utils/compile := $(curdir)/libtool/compile $(curdir)/e2fsprogs/compile $(curdir)/zlib/compile diff --git a/tools/mold/Makefile b/tools/mold/Makefile new file mode 100644 index 00000000000..e8fcecbfed6 --- /dev/null +++ b/tools/mold/Makefile @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-only + +include $(TOPDIR)/rules.mk + +PKG_NAME:=mold +PKG_VERSION:=1.11.0 + +PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz +PKG_SOURCE_URL_FILE:=v$(PKG_VERSION).tar.gz +PKG_SOURCE_URL:=https://github.com/rui314/mold/archive/refs/tags +PKG_HASH:=99318eced81b09a77e4c657011076cc8ec3d4b6867bd324b8677974545bc4d6f + +include $(INCLUDE_DIR)/host-build.mk +include $(INCLUDE_DIR)/cmake.mk + +CMAKE_HOST_OPTIONS += \ + -DMOLD_LTO=ON \ + -DMOLD_MOSTLY_STATIC=ON \ + -DMOLD_USE_SYSTEM_MIMALLOC=OFF \ + -DMOLD_USE_SYSTEM_TBB=OFF + +$(eval $(call HostBuild)) From 3cae2db2d1a4edd06e8b4d1585e0ba3f2848eeda Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Fri, 27 Jan 2023 17:53:02 +0100 Subject: [PATCH 11/53] toolchain: add mold as additional linker Install it as $tripple-ld.mold in order to use -fuse-ld=mold. Signed-off-by: Andre Heider --- toolchain/Makefile | 2 +- toolchain/mold/Makefile | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+), 1 deletion(-) create mode 100644 toolchain/mold/Makefile diff --git a/toolchain/Makefile b/toolchain/Makefile index c0046293c92..09c16f72a78 100644 --- a/toolchain/Makefile +++ b/toolchain/Makefile @@ -27,7 +27,7 @@ curdir:=toolchain # subdirectories to descend into -$(curdir)/builddirs := $(if $(CONFIG_GDB),gdb) $(if $(CONFIG_EXTERNAL_TOOLCHAIN),wrapper,kernel-headers binutils gcc/initial gcc/final $(LIBC) fortify-headers) $(if $(CONFIG_NASM),nasm) +$(curdir)/builddirs := $(if $(CONFIG_GDB),gdb) $(if $(CONFIG_EXTERNAL_TOOLCHAIN),wrapper,kernel-headers binutils gcc/initial gcc/final $(LIBC) fortify-headers) $(if $(CONFIG_NASM),nasm) $(if $(CONFIG_USE_MOLD),mold) # builddir dependencies ifeq ($(CONFIG_EXTERNAL_TOOLCHAIN),) diff --git a/toolchain/mold/Makefile b/toolchain/mold/Makefile new file mode 100644 index 00000000000..a2acba89d3c --- /dev/null +++ b/toolchain/mold/Makefile @@ -0,0 +1,22 @@ +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/toolchain-build.mk + +define Host/Configure +endef + +define Host/Compile +endef + +define Host/Install + $(INSTALL_DIR) $(TOOLCHAIN_DIR)/bin + $(INSTALL_BIN) $(STAGING_DIR_HOST)/bin/mold $(TOOLCHAIN_DIR)/bin/$(REAL_GNU_TARGET_NAME)-ld.mold +endef + +define Host/Clean +endef + +$(eval $(call HostBuild)) From 42ef375cb658d2de0d44a8b1da4df939341b6021 Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Fri, 27 Jan 2023 18:22:43 +0100 Subject: [PATCH 12/53] treewide: opt-out of tree-wide mold usage These use linker scripts, which mold doesn't support. Signed-off-by: Andre Heider --- include/package.mk | 2 +- package/boot/grub2/Makefile | 2 +- package/kernel/lantiq/ltq-ifxos/Makefile | 1 + package/kernel/lantiq/ltq-vdsl-vr11-mei/Makefile | 1 + package/kernel/lantiq/ltq-vdsl-vr11/Makefile | 1 + 5 files changed, 5 insertions(+), 2 deletions(-) diff --git a/include/package.mk b/include/package.mk index c391d320aa2..1762080b9b0 100644 --- a/include/package.mk +++ b/include/package.mk @@ -24,7 +24,7 @@ PKG_JOBS?=$(if $(PKG_BUILD_PARALLEL),$(MAKE_J),-j1) endif PKG_BUILD_FLAGS?= -__unknown_flags=$(filter-out no-iremap no-mips16 gc-sections no-gc-sections lto no-lto,$(PKG_BUILD_FLAGS)) +__unknown_flags=$(filter-out no-iremap no-mips16 gc-sections no-gc-sections lto no-lto no-mold,$(PKG_BUILD_FLAGS)) ifneq ($(__unknown_flags),) $(error unknown PKG_BUILD_FLAGS: $(__unknown_flags)) endif diff --git a/package/boot/grub2/Makefile b/package/boot/grub2/Makefile index 865feee9ad1..44dafe1ef10 100644 --- a/package/boot/grub2/Makefile +++ b/package/boot/grub2/Makefile @@ -25,7 +25,7 @@ ifneq ($(BUILD_VARIANT),none) endif PKG_FLAGS:=nonshared -PKG_BUILD_FLAGS:=no-lto +PKG_BUILD_FLAGS:=no-lto no-mold include $(INCLUDE_DIR)/host-build.mk include $(INCLUDE_DIR)/package.mk diff --git a/package/kernel/lantiq/ltq-ifxos/Makefile b/package/kernel/lantiq/ltq-ifxos/Makefile index d941a9d56ff..97f7ca78ceb 100644 --- a/package/kernel/lantiq/ltq-ifxos/Makefile +++ b/package/kernel/lantiq/ltq-ifxos/Makefile @@ -23,6 +23,7 @@ PKG_LICENSE_FILES:=LICENSE PKG_EXTMOD_SUBDIRS:=src PKG_FIXUP:=autoreconf +PKG_BUILD_FLAGS:=no-mold include $(INCLUDE_DIR)/package.mk diff --git a/package/kernel/lantiq/ltq-vdsl-vr11-mei/Makefile b/package/kernel/lantiq/ltq-vdsl-vr11-mei/Makefile index f2dcf8db84d..7b8a948179b 100644 --- a/package/kernel/lantiq/ltq-vdsl-vr11-mei/Makefile +++ b/package/kernel/lantiq/ltq-vdsl-vr11-mei/Makefile @@ -25,6 +25,7 @@ PKG_EXTMOD_SUBDIRS:=src PKG_FIXUP:=autoreconf PKG_FLAGS:=nonshared +PKG_BUILD_FLAGS:=no-mold include $(INCLUDE_DIR)/package.mk diff --git a/package/kernel/lantiq/ltq-vdsl-vr11/Makefile b/package/kernel/lantiq/ltq-vdsl-vr11/Makefile index 8284cba9a7f..11f96d744a4 100644 --- a/package/kernel/lantiq/ltq-vdsl-vr11/Makefile +++ b/package/kernel/lantiq/ltq-vdsl-vr11/Makefile @@ -23,6 +23,7 @@ PKG_LICENSE:=GPL-2.0 BSD-2-Clause PKG_LICENSE_FILES:=LICENSE PKG_FIXUP:=autoreconf +PKG_BUILD_FLAGS:=no-mold include $(INCLUDE_DIR)/package.mk From 32ed9764462ae04fad5809f857450d4f606ac4c0 Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Fri, 27 Jan 2023 16:35:46 +0100 Subject: [PATCH 13/53] build: add support to use the mold linker for packages If CONFIG_USE_MOLD is set, all target packages will use the mold linker. Except the ones which opted-out via setting PKG_BUILD_FLAGS:=no-mold. Signed-off-by: Andre Heider --- include/package.mk | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/package.mk b/include/package.mk index 1762080b9b0..61a26f0c438 100644 --- a/include/package.mk +++ b/include/package.mk @@ -55,6 +55,11 @@ ifeq ($(call pkg_build_flag,lto,$(if $(CONFIG_USE_LTO),1,0)),1) TARGET_CXXFLAGS+= -flto=auto -fno-fat-lto-objects TARGET_LDFLAGS+= -flto=auto -fuse-linker-plugin endif +ifdef CONFIG_USE_MOLD + ifeq ($(call pkg_build_flag,mold,1),1) + TARGET_LINKER:=mold + endif +endif include $(INCLUDE_DIR)/hardening.mk include $(INCLUDE_DIR)/prereq.mk From 06e64f9b364abe15c27bf0a7225fcac740819668 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Tue, 23 May 2023 15:43:14 +0800 Subject: [PATCH 14/53] kernel: modules: add xdp-sockets-diag support Support for PF_XDP sockets monitoring interface used by the ss tool. Signed-off-by: Tianling Shen --- config/Config-kernel.in | 6 ++++++ package/kernel/linux/modules/netsupport.mk | 16 ++++++++++++++++ .../hack-5.15/901-debloat_sock_diag.patch | 10 ++++++++++ .../generic/hack-6.1/901-debloat_sock_diag.patch | 10 ++++++++++ 4 files changed, 42 insertions(+) diff --git a/config/Config-kernel.in b/config/Config-kernel.in index a770a9d7973..76b0395f373 100644 --- a/config/Config-kernel.in +++ b/config/Config-kernel.in @@ -1107,6 +1107,12 @@ config KERNEL_NET_L3_MASTER_DEV This module provides glue between core networking code and device drivers to support L3 master devices like VRF. +config KERNEL_XDP_SOCKETS + bool "XDP sockets support" + help + XDP sockets allows a channel between XDP programs and + userspace applications. + config KERNEL_WIRELESS_EXT def_bool n diff --git a/package/kernel/linux/modules/netsupport.mk b/package/kernel/linux/modules/netsupport.mk index cb85c46b785..2475828bdeb 100644 --- a/package/kernel/linux/modules/netsupport.mk +++ b/package/kernel/linux/modules/netsupport.mk @@ -1434,6 +1434,22 @@ endef $(eval $(call KernelPackage,inet-diag)) +define KernelPackage/xdp-sockets-diag + SUBMENU:=$(NETWORK_SUPPORT_MENU) + TITLE:=PF_XDP sockets monitoring interface support for ss utility + DEPENDS:=@KERNEL_XDP_SOCKETS + KCONFIG:=CONFIG_XDP_SOCKETS_DIAG + FILES:=$(LINUX_DIR)/net/xdp/xsk_diag.ko + AUTOLOAD:=$(call AutoLoad,31,xsk_diag) +endef + +define KernelPackage/xdp-sockets-diag/description + Support for PF_XDP sockets monitoring interface used by the ss tool +endef + +$(eval $(call KernelPackage,xdp-sockets-diag)) + + define KernelPackage/wireguard SUBMENU:=$(NETWORK_SUPPORT_MENU) TITLE:=WireGuard secure network tunnel diff --git a/target/linux/generic/hack-5.15/901-debloat_sock_diag.patch b/target/linux/generic/hack-5.15/901-debloat_sock_diag.patch index ac502bdd16d..1f3802aa5b3 100644 --- a/target/linux/generic/hack-5.15/901-debloat_sock_diag.patch +++ b/target/linux/generic/hack-5.15/901-debloat_sock_diag.patch @@ -160,3 +160,13 @@ Signed-off-by: Felix Fietkau default n help Support for UNIX socket monitoring interface used by the ss tool. +--- a/net/xdp/Kconfig ++++ b/net/xdp/Kconfig +@@ -10,6 +10,7 @@ config XDP_SOCKETS + config XDP_SOCKETS_DIAG + tristate "XDP sockets: monitoring interface" + depends on XDP_SOCKETS ++ select SOCK_DIAG + default n + help + Support for PF_XDP sockets monitoring interface used by the ss tool. diff --git a/target/linux/generic/hack-6.1/901-debloat_sock_diag.patch b/target/linux/generic/hack-6.1/901-debloat_sock_diag.patch index 582a48cb182..88e2edd289f 100644 --- a/target/linux/generic/hack-6.1/901-debloat_sock_diag.patch +++ b/target/linux/generic/hack-6.1/901-debloat_sock_diag.patch @@ -162,3 +162,13 @@ Signed-off-by: Felix Fietkau default n help Support for UNIX socket monitoring interface used by the ss tool. +--- a/net/xdp/Kconfig ++++ b/net/xdp/Kconfig +@@ -10,6 +10,7 @@ config XDP_SOCKETS + config XDP_SOCKETS_DIAG + tristate "XDP sockets: monitoring interface" + depends on XDP_SOCKETS ++ select SOCK_DIAG + default n + help + Support for PF_XDP sockets monitoring interface used by the ss tool. From b8b49066140eb810474531a48ee3807caa6a694c Mon Sep 17 00:00:00 2001 From: John Audia Date: Wed, 28 Jun 2023 06:20:03 -0400 Subject: [PATCH 15/53] kernel: bump 6.1 to 6.1.36 All patches automatically rebased. Acknowledgment to @john-tho for the changes to fs.mk to accommodate new paths introduced in https://github.com/gregkh/linux/commit/29429a1f5871dbe54ee0da81bb12db8567f15379 Build system: x86_64 Build-tested: bcm2711/RPi4B Run-tested: bcm2711/RPi4B Signed-off-by: John Audia --- include/kernel-6.1 | 4 ++-- package/kernel/linux/modules/fs.mk | 17 +++++++++---- ...oup-Disable-cgroup-memory-by-default.patch | 8 +++---- ...-t-prevent-IRQ-usage-of-output-GPIOs.patch | 4 ++-- ...t-dsa-mt7530-use-external-PCS-driver.patch | 24 +++++++++---------- ...a-mt7530-refactor-SGMII-PCS-creation.patch | 4 ++-- ...mt7530-use-unlocked-regmap-accessors.patch | 6 ++--- ...se-regmap-to-access-switch-register-.patch | 14 +++++------ ...ove-SGMII-PCS-creation-to-mt7530_pro.patch | 6 ++--- ...t-dsa-mt7530-introduce-mutex-helpers.patch | 12 +++++----- ...ove-p5_intf_modes-function-to-mt7530.patch | 2 +- ...ntroduce-mt7530_probe_common-helper-.patch | 6 ++--- ...ntroduce-mt7530_remove_common-helper.patch | 4 ++-- ...t7530-introduce-separate-MDIO-driver.patch | 14 +++++------ ...ntroduce-driver-for-MT7988-built-in-.patch | 20 ++++++++-------- ...-dsa-mt7530-fix-support-for-MT7531BE.patch | 8 +++---- .../hack-6.1/901-debloat_sock_diag.patch | 2 +- .../generic/hack-6.1/902-debloat_proc.patch | 2 +- ...e-all-MACs-are-powered-down-before-r.patch | 2 +- ...gister-OF-node-for-internal-MDIO-bus.patch | 4 ++-- 20 files changed, 85 insertions(+), 78 deletions(-) diff --git a/include/kernel-6.1 b/include/kernel-6.1 index bc84e23dad7..2748562eba4 100644 --- a/include/kernel-6.1 +++ b/include/kernel-6.1 @@ -1,2 +1,2 @@ -LINUX_VERSION-6.1 = .35 -LINUX_KERNEL_HASH-6.1.35 = be368143bc5d0dc73dd3e8c6191630c1620520379baf6f47c16116b2c0bc26ac \ No newline at end of file +LINUX_VERSION-6.1 = .36 +LINUX_KERNEL_HASH-6.1.36 = d8ca0e300f30b9ff70c6e1497c638a1dac1407f45d3655e9c62c6e45a08afe6b \ No newline at end of file diff --git a/package/kernel/linux/modules/fs.mk b/package/kernel/linux/modules/fs.mk index 5fb9a2b7d64..f2acaa74398 100644 --- a/package/kernel/linux/modules/fs.mk +++ b/package/kernel/linux/modules/fs.mk @@ -87,10 +87,14 @@ define KernelPackage/fs-smbfs-common SUBMENU:=$(FS_MENU) TITLE:=SMBFS common dependencies support HIDDEN:=1 - KCONFIG:=CONFIG_SMBFS_COMMON + KCONFIG:=\ + CONFIG_SMBFS_COMMON@lt6.1 \ + CONFIG_SMBFS@ge6.1 FILES:= \ - $(LINUX_DIR)/fs/smbfs_common/cifs_arc4.ko \ - $(LINUX_DIR)/fs/smbfs_common/cifs_md4.ko + $(LINUX_DIR)/fs/smbfs_common/cifs_arc4.ko@lt6.1 \ + $(LINUX_DIR)/fs/smbfs_common/cifs_md4.ko@lt6.1 \ + $(LINUX_DIR)/fs/smb/common/cifs_arc4.ko@ge6.1 \ + $(LINUX_DIR)/fs/smb/common/cifs_md4.ko@ge6.1 endef define KernelPackage/fs-smbfs-common/description @@ -108,7 +112,8 @@ define KernelPackage/fs-cifs CONFIG_CIFS_DFS_UPCALL=n \ CONFIG_CIFS_UPCALL=n FILES:= \ - $(LINUX_DIR)/fs/cifs/cifs.ko + $(LINUX_DIR)/fs/cifs/cifs.ko@lt6.1 \ + $(LINUX_DIR)/fs/smb/client/cifs.ko@ge6.1 AUTOLOAD:=$(call AutoLoad,30,cifs) $(call AddDepends/nls) DEPENDS+= \ @@ -373,7 +378,9 @@ define KernelPackage/fs-ksmbd CONFIG_SMB_SERVER_SMBDIRECT=n \ CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=n \ CONFIG_SMB_SERVER_KERBEROS5=n - FILES:=$(LINUX_DIR)/fs/ksmbd/ksmbd.ko + FILES:= \ + $(LINUX_DIR)/fs/ksmbd/ksmbd.ko@lt6.1 \ + $(LINUX_DIR)/fs/smb/server/ksmbd.ko@ge6.1 AUTOLOAD:=$(call AutoLoad,41,ksmbd) endef diff --git a/target/linux/bcm27xx/patches-6.1/950-0084-cgroup-Disable-cgroup-memory-by-default.patch b/target/linux/bcm27xx/patches-6.1/950-0084-cgroup-Disable-cgroup-memory-by-default.patch index d437cccb3c7..f97882c163c 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0084-cgroup-Disable-cgroup-memory-by-default.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0084-cgroup-Disable-cgroup-memory-by-default.patch @@ -17,7 +17,7 @@ Signed-off-by: Phil Elwell --- a/kernel/cgroup/cgroup.c +++ b/kernel/cgroup/cgroup.c -@@ -6046,6 +6046,9 @@ int __init cgroup_init_early(void) +@@ -6060,6 +6060,9 @@ int __init cgroup_init_early(void) return 0; } @@ -27,7 +27,7 @@ Signed-off-by: Phil Elwell /** * cgroup_init - cgroup initialization * -@@ -6079,6 +6082,12 @@ int __init cgroup_init(void) +@@ -6093,6 +6096,12 @@ int __init cgroup_init(void) cgroup_unlock(); @@ -40,7 +40,7 @@ Signed-off-by: Phil Elwell for_each_subsys(ss, ssid) { if (ss->early_init) { struct cgroup_subsys_state *css = -@@ -6716,6 +6725,10 @@ static int __init cgroup_disable(char *s +@@ -6730,6 +6739,10 @@ static int __init cgroup_disable(char *s strcmp(token, ss->legacy_name)) continue; @@ -51,7 +51,7 @@ Signed-off-by: Phil Elwell static_branch_disable(cgroup_subsys_enabled_key[i]); pr_info("Disabling %s control group subsystem\n", ss->name); -@@ -6734,6 +6747,31 @@ static int __init cgroup_disable(char *s +@@ -6748,6 +6761,31 @@ static int __init cgroup_disable(char *s } __setup("cgroup_disable=", cgroup_disable); diff --git a/target/linux/bcm27xx/patches-6.1/950-0239-gpiolib-Don-t-prevent-IRQ-usage-of-output-GPIOs.patch b/target/linux/bcm27xx/patches-6.1/950-0239-gpiolib-Don-t-prevent-IRQ-usage-of-output-GPIOs.patch index 617a0025166..3b2b6d688a1 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0239-gpiolib-Don-t-prevent-IRQ-usage-of-output-GPIOs.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0239-gpiolib-Don-t-prevent-IRQ-usage-of-output-GPIOs.patch @@ -26,7 +26,7 @@ Signed-off-by: Phil Elwell /* Device and char device-related information */ static DEFINE_IDA(gpio_ida); static dev_t gpio_devt; -@@ -2414,8 +2416,8 @@ int gpiod_direction_output(struct gpio_d +@@ -2423,8 +2425,8 @@ int gpiod_direction_output(struct gpio_d value = !!value; /* GPIOs used for enabled IRQs shall not be set as output */ @@ -37,7 +37,7 @@ Signed-off-by: Phil Elwell gpiod_err(desc, "%s: tried to set a GPIO tied to an IRQ as output\n", __func__); -@@ -3293,8 +3295,8 @@ int gpiochip_lock_as_irq(struct gpio_chi +@@ -3302,8 +3304,8 @@ int gpiochip_lock_as_irq(struct gpio_chi } /* To be valid for IRQ the line needs to be input or open drain */ diff --git a/target/linux/generic/backport-6.1/788-v6.3-net-dsa-mt7530-use-external-PCS-driver.patch b/target/linux/generic/backport-6.1/788-v6.3-net-dsa-mt7530-use-external-PCS-driver.patch index be97c8ac3c2..aa781dc7b68 100644 --- a/target/linux/generic/backport-6.1/788-v6.3-net-dsa-mt7530-use-external-PCS-driver.patch +++ b/target/linux/generic/backport-6.1/788-v6.3-net-dsa-mt7530-use-external-PCS-driver.patch @@ -81,7 +81,7 @@ Tested-by: Frank Wunderlich #include #include #include -@@ -2597,128 +2598,11 @@ static int mt7531_rgmii_setup(struct mt7 +@@ -2611,128 +2612,11 @@ static int mt7531_rgmii_setup(struct mt7 return 0; } @@ -210,7 +210,7 @@ Tested-by: Frank Wunderlich static int mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface) -@@ -2741,11 +2625,11 @@ mt7531_mac_config(struct dsa_switch *ds, +@@ -2755,11 +2639,11 @@ mt7531_mac_config(struct dsa_switch *ds, phydev = dp->slave->phydev; return mt7531_rgmii_setup(priv, port, interface, phydev); case PHY_INTERFACE_MODE_SGMII: @@ -224,7 +224,7 @@ Tested-by: Frank Wunderlich default: return -EINVAL; } -@@ -2770,11 +2654,11 @@ mt753x_phylink_mac_select_pcs(struct dsa +@@ -2784,11 +2668,11 @@ mt753x_phylink_mac_select_pcs(struct dsa switch (interface) { case PHY_INTERFACE_MODE_TRGMII: @@ -238,7 +238,7 @@ Tested-by: Frank Wunderlich default: return NULL; } -@@ -3015,86 +2899,6 @@ static void mt7530_pcs_get_state(struct +@@ -3029,86 +2913,6 @@ static void mt7530_pcs_get_state(struct state->pause |= MLO_PAUSE_TX; } @@ -325,7 +325,7 @@ Tested-by: Frank Wunderlich static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int mode, phy_interface_t interface, const unsigned long *advertising, -@@ -3114,18 +2918,57 @@ static const struct phylink_pcs_ops mt75 +@@ -3128,18 +2932,57 @@ static const struct phylink_pcs_ops mt75 .pcs_an_restart = mt7530_pcs_an_restart, }; @@ -389,7 +389,7 @@ Tested-by: Frank Wunderlich int i, ret; /* Initialise the PCS devices */ -@@ -3133,8 +2976,6 @@ mt753x_setup(struct dsa_switch *ds) +@@ -3147,8 +2990,6 @@ mt753x_setup(struct dsa_switch *ds) priv->pcs[i].pcs.ops = priv->info->pcs_ops; priv->pcs[i].priv = priv; priv->pcs[i].port = i; @@ -398,7 +398,7 @@ Tested-by: Frank Wunderlich } ret = priv->info->sw_setup(ds); -@@ -3149,6 +2990,16 @@ mt753x_setup(struct dsa_switch *ds) +@@ -3163,6 +3004,16 @@ mt753x_setup(struct dsa_switch *ds) if (ret && priv->irq) mt7530_free_irq_common(priv); @@ -415,7 +415,7 @@ Tested-by: Frank Wunderlich return ret; } -@@ -3240,7 +3091,7 @@ static const struct mt753x_info mt753x_t +@@ -3254,7 +3105,7 @@ static const struct mt753x_info mt753x_t }, [ID_MT7531] = { .id = ID_MT7531, @@ -424,7 +424,7 @@ Tested-by: Frank Wunderlich .sw_setup = mt7531_setup, .phy_read = mt7531_ind_phy_read, .phy_write = mt7531_ind_phy_write, -@@ -3348,7 +3199,7 @@ static void +@@ -3362,7 +3213,7 @@ static void mt7530_remove(struct mdio_device *mdiodev) { struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); @@ -433,7 +433,7 @@ Tested-by: Frank Wunderlich if (!priv) return; -@@ -3367,6 +3218,10 @@ mt7530_remove(struct mdio_device *mdiode +@@ -3381,6 +3232,10 @@ mt7530_remove(struct mdio_device *mdiode mt7530_free_irq(priv); dsa_unregister_switch(priv->ds); @@ -446,7 +446,7 @@ Tested-by: Frank Wunderlich --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h -@@ -364,47 +364,8 @@ enum mt7530_vlan_port_acc_frm { +@@ -369,47 +369,8 @@ enum mt7530_vlan_port_acc_frm { CCR_TX_OCT_CNT_BAD) /* MT7531 SGMII register group */ @@ -496,7 +496,7 @@ Tested-by: Frank Wunderlich /* Register for system reset */ #define MT7530_SYS_CTRL 0x7000 -@@ -703,13 +664,13 @@ struct mt7530_fdb { +@@ -708,13 +669,13 @@ struct mt7530_fdb { * @pm: The matrix used to show all connections with the port. * @pvid: The VLAN specified is to be considered a PVID at ingress. Any * untagged frames will be assigned to the related VLAN. diff --git a/target/linux/generic/backport-6.1/790-v6.4-0002-net-dsa-mt7530-refactor-SGMII-PCS-creation.patch b/target/linux/generic/backport-6.1/790-v6.4-0002-net-dsa-mt7530-refactor-SGMII-PCS-creation.patch index 4f255abc5bc..0e15cce2497 100644 --- a/target/linux/generic/backport-6.1/790-v6.4-0002-net-dsa-mt7530-refactor-SGMII-PCS-creation.patch +++ b/target/linux/generic/backport-6.1/790-v6.4-0002-net-dsa-mt7530-refactor-SGMII-PCS-creation.patch @@ -18,7 +18,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2950,26 +2950,56 @@ static const struct regmap_bus mt7531_re +@@ -2964,26 +2964,56 @@ static const struct regmap_bus mt7531_re .reg_update_bits = mt7530_regmap_update_bits, }; @@ -88,7 +88,7 @@ Signed-off-by: David S. Miller int i, ret; /* Initialise the PCS devices */ -@@ -2991,15 +3021,11 @@ mt753x_setup(struct dsa_switch *ds) +@@ -3005,15 +3035,11 @@ mt753x_setup(struct dsa_switch *ds) if (ret && priv->irq) mt7530_free_irq_common(priv); diff --git a/target/linux/generic/backport-6.1/790-v6.4-0003-net-dsa-mt7530-use-unlocked-regmap-accessors.patch b/target/linux/generic/backport-6.1/790-v6.4-0003-net-dsa-mt7530-use-unlocked-regmap-accessors.patch index 77ac3f3f268..a40f3b8f3b9 100644 --- a/target/linux/generic/backport-6.1/790-v6.4-0003-net-dsa-mt7530-use-unlocked-regmap-accessors.patch +++ b/target/linux/generic/backport-6.1/790-v6.4-0003-net-dsa-mt7530-use-unlocked-regmap-accessors.patch @@ -19,7 +19,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2923,7 +2923,7 @@ static int mt7530_regmap_read(void *cont +@@ -2937,7 +2937,7 @@ static int mt7530_regmap_read(void *cont { struct mt7530_priv *priv = context; @@ -28,7 +28,7 @@ Signed-off-by: David S. Miller return 0; }; -@@ -2931,23 +2931,25 @@ static int mt7530_regmap_write(void *con +@@ -2945,23 +2945,25 @@ static int mt7530_regmap_write(void *con { struct mt7530_priv *priv = context; @@ -62,7 +62,7 @@ Signed-off-by: David S. Miller }; static int -@@ -2973,6 +2975,9 @@ mt7531_create_sgmii(struct mt7530_priv * +@@ -2987,6 +2989,9 @@ mt7531_create_sgmii(struct mt7530_priv * mt7531_pcs_config[i]->reg_stride = 4; mt7531_pcs_config[i]->reg_base = MT7531_SGMII_REG_BASE(5 + i); mt7531_pcs_config[i]->max_register = 0x17c; diff --git a/target/linux/generic/backport-6.1/790-v6.4-0004-net-dsa-mt7530-use-regmap-to-access-switch-register-.patch b/target/linux/generic/backport-6.1/790-v6.4-0004-net-dsa-mt7530-use-regmap-to-access-switch-register-.patch index 6e3e8b09b96..ae17d17d175 100644 --- a/target/linux/generic/backport-6.1/790-v6.4-0004-net-dsa-mt7530-use-regmap-to-access-switch-register-.patch +++ b/target/linux/generic/backport-6.1/790-v6.4-0004-net-dsa-mt7530-use-regmap-to-access-switch-register-.patch @@ -133,7 +133,7 @@ Signed-off-by: David S. Miller } static void -@@ -2919,22 +2940,6 @@ static const struct phylink_pcs_ops mt75 +@@ -2933,22 +2954,6 @@ static const struct phylink_pcs_ops mt75 .pcs_an_restart = mt7530_pcs_an_restart, }; @@ -156,7 +156,7 @@ Signed-off-by: David S. Miller static void mt7530_mdio_regmap_lock(void *mdio_lock) { -@@ -2947,7 +2952,7 @@ mt7530_mdio_regmap_unlock(void *mdio_loc +@@ -2961,7 +2966,7 @@ mt7530_mdio_regmap_unlock(void *mdio_loc mutex_unlock(mdio_lock); } @@ -165,7 +165,7 @@ Signed-off-by: David S. Miller .reg_write = mt7530_regmap_write, .reg_read = mt7530_regmap_read, }; -@@ -2980,7 +2985,7 @@ mt7531_create_sgmii(struct mt7530_priv * +@@ -2994,7 +2999,7 @@ mt7531_create_sgmii(struct mt7530_priv * mt7531_pcs_config[i]->lock_arg = &priv->bus->mdio_lock; regmap = devm_regmap_init(priv->dev, @@ -174,7 +174,7 @@ Signed-off-by: David S. Miller mt7531_pcs_config[i]); if (IS_ERR(regmap)) { ret = PTR_ERR(regmap); -@@ -3145,6 +3150,7 @@ MODULE_DEVICE_TABLE(of, mt7530_of_match) +@@ -3159,6 +3164,7 @@ MODULE_DEVICE_TABLE(of, mt7530_of_match) static int mt7530_probe(struct mdio_device *mdiodev) { @@ -182,7 +182,7 @@ Signed-off-by: David S. Miller struct mt7530_priv *priv; struct device_node *dn; -@@ -3224,6 +3230,21 @@ mt7530_probe(struct mdio_device *mdiodev +@@ -3238,6 +3244,21 @@ mt7530_probe(struct mdio_device *mdiodev mutex_init(&priv->reg_mutex); dev_set_drvdata(&mdiodev->dev, priv); @@ -206,7 +206,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h -@@ -747,6 +747,7 @@ struct mt753x_info { +@@ -752,6 +752,7 @@ struct mt753x_info { * @dev: The device pointer * @ds: The pointer to the dsa core structure * @bus: The bus used for the device and built-in PHY @@ -214,7 +214,7 @@ Signed-off-by: David S. Miller * @rstc: The pointer to reset control used by MCM * @core_pwr: The power supplied into the core * @io_pwr: The power supplied into the I/O -@@ -767,6 +768,7 @@ struct mt7530_priv { +@@ -772,6 +773,7 @@ struct mt7530_priv { struct device *dev; struct dsa_switch *ds; struct mii_bus *bus; diff --git a/target/linux/generic/backport-6.1/790-v6.4-0005-net-dsa-mt7530-move-SGMII-PCS-creation-to-mt7530_pro.patch b/target/linux/generic/backport-6.1/790-v6.4-0005-net-dsa-mt7530-move-SGMII-PCS-creation-to-mt7530_pro.patch index a02702fd687..bbee3d22da2 100644 --- a/target/linux/generic/backport-6.1/790-v6.4-0005-net-dsa-mt7530-move-SGMII-PCS-creation-to-mt7530_pro.patch +++ b/target/linux/generic/backport-6.1/790-v6.4-0005-net-dsa-mt7530-move-SGMII-PCS-creation-to-mt7530_pro.patch @@ -18,7 +18,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -3031,12 +3031,6 @@ mt753x_setup(struct dsa_switch *ds) +@@ -3045,12 +3045,6 @@ mt753x_setup(struct dsa_switch *ds) if (ret && priv->irq) mt7530_free_irq_common(priv); @@ -31,7 +31,7 @@ Signed-off-by: David S. Miller return ret; } -@@ -3153,6 +3147,7 @@ mt7530_probe(struct mdio_device *mdiodev +@@ -3167,6 +3161,7 @@ mt7530_probe(struct mdio_device *mdiodev static struct regmap_config *regmap_config; struct mt7530_priv *priv; struct device_node *dn; @@ -39,7 +39,7 @@ Signed-off-by: David S. Miller dn = mdiodev->dev.of_node; -@@ -3245,6 +3240,12 @@ mt7530_probe(struct mdio_device *mdiodev +@@ -3259,6 +3254,12 @@ mt7530_probe(struct mdio_device *mdiodev if (IS_ERR(priv->regmap)) return PTR_ERR(priv->regmap); diff --git a/target/linux/generic/backport-6.1/790-v6.4-0006-net-dsa-mt7530-introduce-mutex-helpers.patch b/target/linux/generic/backport-6.1/790-v6.4-0006-net-dsa-mt7530-introduce-mutex-helpers.patch index 98122caf090..13de0a12f2f 100644 --- a/target/linux/generic/backport-6.1/790-v6.4-0006-net-dsa-mt7530-introduce-mutex-helpers.patch +++ b/target/linux/generic/backport-6.1/790-v6.4-0006-net-dsa-mt7530-introduce-mutex-helpers.patch @@ -214,7 +214,7 @@ Signed-off-by: David S. Miller return ret; } -@@ -1109,7 +1109,6 @@ static int +@@ -1121,7 +1121,6 @@ static int mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) { struct mt7530_priv *priv = ds->priv; @@ -222,7 +222,7 @@ Signed-off-by: David S. Miller int length; u32 val; -@@ -1120,7 +1119,7 @@ mt7530_port_change_mtu(struct dsa_switch +@@ -1132,7 +1131,7 @@ mt7530_port_change_mtu(struct dsa_switch if (!dsa_is_cpu_port(ds, port)) return 0; @@ -231,7 +231,7 @@ Signed-off-by: David S. Miller val = mt7530_mii_read(priv, MT7530_GMACCR); val &= ~MAX_RX_PKT_LEN_MASK; -@@ -1141,7 +1140,7 @@ mt7530_port_change_mtu(struct dsa_switch +@@ -1153,7 +1152,7 @@ mt7530_port_change_mtu(struct dsa_switch mt7530_mii_write(priv, MT7530_GMACCR, val); @@ -240,7 +240,7 @@ Signed-off-by: David S. Miller return 0; } -@@ -1942,10 +1941,10 @@ mt7530_irq_thread_fn(int irq, void *dev_ +@@ -1954,10 +1953,10 @@ mt7530_irq_thread_fn(int irq, void *dev_ u32 val; int p; @@ -253,7 +253,7 @@ Signed-off-by: David S. Miller for (p = 0; p < MT7530_NUM_PHYS; p++) { if (BIT(p) & val) { -@@ -1981,7 +1980,7 @@ mt7530_irq_bus_lock(struct irq_data *d) +@@ -1993,7 +1992,7 @@ mt7530_irq_bus_lock(struct irq_data *d) { struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); @@ -262,7 +262,7 @@ Signed-off-by: David S. Miller } static void -@@ -1990,7 +1989,7 @@ mt7530_irq_bus_sync_unlock(struct irq_da +@@ -2002,7 +2001,7 @@ mt7530_irq_bus_sync_unlock(struct irq_da struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); diff --git a/target/linux/generic/backport-6.1/790-v6.4-0007-net-dsa-mt7530-move-p5_intf_modes-function-to-mt7530.patch b/target/linux/generic/backport-6.1/790-v6.4-0007-net-dsa-mt7530-move-p5_intf_modes-function-to-mt7530.patch index 5065d735232..f46f753b218 100644 --- a/target/linux/generic/backport-6.1/790-v6.4-0007-net-dsa-mt7530-move-p5_intf_modes-function-to-mt7530.patch +++ b/target/linux/generic/backport-6.1/790-v6.4-0007-net-dsa-mt7530-move-p5_intf_modes-function-to-mt7530.patch @@ -48,7 +48,7 @@ Signed-off-by: David S. Miller struct mt7530_priv *priv = ds->priv; --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h -@@ -682,24 +682,6 @@ enum p5_interface_select { +@@ -687,24 +687,6 @@ enum p5_interface_select { P5_INTF_SEL_GMAC5_SGMII, }; diff --git a/target/linux/generic/backport-6.1/790-v6.4-0008-net-dsa-mt7530-introduce-mt7530_probe_common-helper-.patch b/target/linux/generic/backport-6.1/790-v6.4-0008-net-dsa-mt7530-introduce-mt7530_probe_common-helper-.patch index 761aa1d9797..89f39a93852 100644 --- a/target/linux/generic/backport-6.1/790-v6.4-0008-net-dsa-mt7530-introduce-mt7530_probe_common-helper-.patch +++ b/target/linux/generic/backport-6.1/790-v6.4-0008-net-dsa-mt7530-introduce-mt7530_probe_common-helper-.patch @@ -17,7 +17,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -3159,44 +3159,21 @@ static const struct of_device_id mt7530_ +@@ -3173,44 +3173,21 @@ static const struct of_device_id mt7530_ MODULE_DEVICE_TABLE(of, mt7530_of_match); static int @@ -67,7 +67,7 @@ Signed-off-by: David S. Miller if (!priv->info) return -EINVAL; -@@ -3210,23 +3187,53 @@ mt7530_probe(struct mdio_device *mdiodev +@@ -3224,23 +3201,53 @@ mt7530_probe(struct mdio_device *mdiodev return -EINVAL; priv->id = priv->info->id; @@ -131,7 +131,7 @@ Signed-off-by: David S. Miller priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset", GPIOD_OUT_LOW); if (IS_ERR(priv->reset)) { -@@ -3235,12 +3242,15 @@ mt7530_probe(struct mdio_device *mdiodev +@@ -3249,12 +3256,15 @@ mt7530_probe(struct mdio_device *mdiodev } } diff --git a/target/linux/generic/backport-6.1/790-v6.4-0009-net-dsa-mt7530-introduce-mt7530_remove_common-helper.patch b/target/linux/generic/backport-6.1/790-v6.4-0009-net-dsa-mt7530-introduce-mt7530_remove_common-helper.patch index d3c2a7e2c9b..654d9a88ebf 100644 --- a/target/linux/generic/backport-6.1/790-v6.4-0009-net-dsa-mt7530-introduce-mt7530_remove_common-helper.patch +++ b/target/linux/generic/backport-6.1/790-v6.4-0009-net-dsa-mt7530-introduce-mt7530_remove_common-helper.patch @@ -17,7 +17,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -3277,6 +3277,17 @@ mt7530_probe(struct mdio_device *mdiodev +@@ -3291,6 +3291,17 @@ mt7530_probe(struct mdio_device *mdiodev } static void @@ -35,7 +35,7 @@ Signed-off-by: David S. Miller mt7530_remove(struct mdio_device *mdiodev) { struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); -@@ -3295,15 +3306,10 @@ mt7530_remove(struct mdio_device *mdiode +@@ -3309,15 +3320,10 @@ mt7530_remove(struct mdio_device *mdiode dev_err(priv->dev, "Failed to disable io pwr: %d\n", ret); diff --git a/target/linux/generic/backport-6.1/790-v6.4-0010-net-dsa-mt7530-introduce-separate-MDIO-driver.patch b/target/linux/generic/backport-6.1/790-v6.4-0010-net-dsa-mt7530-introduce-separate-MDIO-driver.patch index 55378ca016b..219a96731a6 100644 --- a/target/linux/generic/backport-6.1/790-v6.4-0010-net-dsa-mt7530-introduce-separate-MDIO-driver.patch +++ b/target/linux/generic/backport-6.1/790-v6.4-0010-net-dsa-mt7530-introduce-separate-MDIO-driver.patch @@ -416,7 +416,7 @@ Signed-off-by: David S. Miller static u32 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) { -@@ -2957,72 +2908,6 @@ static const struct phylink_pcs_ops mt75 +@@ -2971,72 +2922,6 @@ static const struct phylink_pcs_ops mt75 .pcs_an_restart = mt7530_pcs_an_restart, }; @@ -489,7 +489,7 @@ Signed-off-by: David S. Miller static int mt753x_setup(struct dsa_switch *ds) { -@@ -3081,7 +2966,7 @@ static int mt753x_set_mac_eee(struct dsa +@@ -3095,7 +2980,7 @@ static int mt753x_set_mac_eee(struct dsa return 0; } @@ -498,7 +498,7 @@ Signed-off-by: David S. Miller .get_tag_protocol = mtk_get_tag_protocol, .setup = mt753x_setup, .get_strings = mt7530_get_strings, -@@ -3115,8 +3000,9 @@ static const struct dsa_switch_ops mt753 +@@ -3129,8 +3014,9 @@ static const struct dsa_switch_ops mt753 .get_mac_eee = mt753x_get_mac_eee, .set_mac_eee = mt753x_set_mac_eee, }; @@ -509,7 +509,7 @@ Signed-off-by: David S. Miller [ID_MT7621] = { .id = ID_MT7621, .pcs_ops = &mt7530_pcs_ops, -@@ -3149,16 +3035,9 @@ static const struct mt753x_info mt753x_t +@@ -3163,16 +3049,9 @@ static const struct mt753x_info mt753x_t .mac_port_config = mt7531_mac_config, }, }; @@ -528,7 +528,7 @@ Signed-off-by: David S. Miller mt7530_probe_common(struct mt7530_priv *priv) { struct device *dev = priv->dev; -@@ -3195,88 +3074,9 @@ mt7530_probe_common(struct mt7530_priv * +@@ -3209,88 +3088,9 @@ mt7530_probe_common(struct mt7530_priv * return 0; } @@ -619,7 +619,7 @@ Signed-off-by: David S. Miller mt7530_remove_common(struct mt7530_priv *priv) { if (priv->irq) -@@ -3286,55 +3086,7 @@ mt7530_remove_common(struct mt7530_priv +@@ -3300,55 +3100,7 @@ mt7530_remove_common(struct mt7530_priv mutex_destroy(&priv->reg_mutex); } @@ -678,7 +678,7 @@ Signed-off-by: David S. Miller MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h -@@ -807,4 +807,10 @@ static inline void INIT_MT7530_DUMMY_POL +@@ -812,4 +812,10 @@ static inline void INIT_MT7530_DUMMY_POL p->reg = reg; } diff --git a/target/linux/generic/backport-6.1/790-v6.4-0012-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch b/target/linux/generic/backport-6.1/790-v6.4-0012-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch index aeaf9f84678..4dac4464fee 100644 --- a/target/linux/generic/backport-6.1/790-v6.4-0012-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch +++ b/target/linux/generic/backport-6.1/790-v6.4-0012-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch @@ -184,7 +184,7 @@ Signed-off-by: David S. Miller +MODULE_LICENSE("GPL"); --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -1989,6 +1989,47 @@ static const struct irq_domain_ops mt753 +@@ -2001,6 +2001,47 @@ static const struct irq_domain_ops mt753 }; static void @@ -232,7 +232,7 @@ Signed-off-by: David S. Miller mt7530_setup_mdio_irq(struct mt7530_priv *priv) { struct dsa_switch *ds = priv->ds; -@@ -2022,8 +2063,15 @@ mt7530_setup_irq(struct mt7530_priv *pri +@@ -2034,8 +2075,15 @@ mt7530_setup_irq(struct mt7530_priv *pri return priv->irq ? : -EINVAL; } @@ -250,7 +250,7 @@ Signed-off-by: David S. Miller if (!priv->irq_domain) { dev_err(dev, "failed to create IRQ domain\n"); return -ENOMEM; -@@ -2520,6 +2568,25 @@ static void mt7531_mac_port_get_caps(str +@@ -2534,6 +2582,25 @@ static void mt7531_mac_port_get_caps(str } } @@ -276,7 +276,7 @@ Signed-off-by: David S. Miller static int mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state) { -@@ -2596,6 +2663,17 @@ static bool mt753x_is_mac_port(u32 port) +@@ -2610,6 +2677,17 @@ static bool mt753x_is_mac_port(u32 port) } static int @@ -294,7 +294,7 @@ Signed-off-by: David S. Miller mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface) { -@@ -2665,7 +2743,8 @@ mt753x_phylink_mac_config(struct dsa_swi +@@ -2679,7 +2757,8 @@ mt753x_phylink_mac_config(struct dsa_swi switch (port) { case 0 ... 4: /* Internal phy */ @@ -304,7 +304,7 @@ Signed-off-by: David S. Miller goto unsupported; break; case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ -@@ -2743,7 +2822,8 @@ static void mt753x_phylink_mac_link_up(s +@@ -2757,7 +2836,8 @@ static void mt753x_phylink_mac_link_up(s /* MT753x MAC works in 1G full duplex mode for all up-clocked * variants. */ @@ -314,7 +314,7 @@ Signed-off-by: David S. Miller (phy_interface_mode_is_8023z(interface))) { speed = SPEED_1000; duplex = DUPLEX_FULL; -@@ -2823,6 +2903,21 @@ mt7531_cpu_port_config(struct dsa_switch +@@ -2837,6 +2917,21 @@ mt7531_cpu_port_config(struct dsa_switch return 0; } @@ -336,7 +336,7 @@ Signed-off-by: David S. Miller static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, struct phylink_config *config) { -@@ -2968,6 +3063,27 @@ static int mt753x_set_mac_eee(struct dsa +@@ -2982,6 +3077,27 @@ static int mt753x_set_mac_eee(struct dsa return 0; } @@ -364,7 +364,7 @@ Signed-off-by: David S. Miller const struct dsa_switch_ops mt7530_switch_ops = { .get_tag_protocol = mtk_get_tag_protocol, .setup = mt753x_setup, -@@ -3036,6 +3152,17 @@ const struct mt753x_info mt753x_table[] +@@ -3050,6 +3166,17 @@ const struct mt753x_info mt753x_table[] .mac_port_get_caps = mt7531_mac_port_get_caps, .mac_port_config = mt7531_mac_config, }, @@ -407,7 +407,7 @@ Signed-off-by: David S. Miller MT7531_MIRROR_MASK : MIRROR_MASK) /* Registers for BPDU and PAE frame control*/ -@@ -295,9 +296,8 @@ enum mt7530_vlan_port_acc_frm { +@@ -300,9 +301,8 @@ enum mt7530_vlan_port_acc_frm { MT7531_FORCE_DPX | \ MT7531_FORCE_RX_FC | \ MT7531_FORCE_TX_FC) diff --git a/target/linux/generic/backport-6.1/790-v6.4-0013-net-dsa-mt7530-fix-support-for-MT7531BE.patch b/target/linux/generic/backport-6.1/790-v6.4-0013-net-dsa-mt7530-fix-support-for-MT7531BE.patch index 074472f6dcb..4e127f19709 100644 --- a/target/linux/generic/backport-6.1/790-v6.4-0013-net-dsa-mt7530-fix-support-for-MT7531BE.patch +++ b/target/linux/generic/backport-6.1/790-v6.4-0013-net-dsa-mt7530-fix-support-for-MT7531BE.patch @@ -73,7 +73,7 @@ Signed-off-by: Jakub Kicinski } --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -3030,6 +3030,12 @@ mt753x_setup(struct dsa_switch *ds) +@@ -3044,6 +3044,12 @@ mt753x_setup(struct dsa_switch *ds) if (ret && priv->irq) mt7530_free_irq_common(priv); @@ -88,7 +88,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h -@@ -741,10 +741,10 @@ struct mt753x_info { +@@ -746,10 +746,10 @@ struct mt753x_info { * registers * @p6_interface Holding the current port 6 interface * @p5_intf_sel: Holding the current port 5 interface select @@ -100,7 +100,7 @@ Signed-off-by: Jakub Kicinski */ struct mt7530_priv { struct device *dev; -@@ -763,7 +763,6 @@ struct mt7530_priv { +@@ -768,7 +768,6 @@ struct mt7530_priv { unsigned int p5_intf_sel; u8 mirror_rx; u8 mirror_tx; @@ -108,7 +108,7 @@ Signed-off-by: Jakub Kicinski struct mt7530_port ports[MT7530_NUM_PORTS]; struct mt753x_pcs pcs[MT7530_NUM_PORTS]; /* protect among processes for registers access*/ -@@ -771,6 +770,7 @@ struct mt7530_priv { +@@ -776,6 +775,7 @@ struct mt7530_priv { int irq; struct irq_domain *irq_domain; u32 irq_enable; diff --git a/target/linux/generic/hack-6.1/901-debloat_sock_diag.patch b/target/linux/generic/hack-6.1/901-debloat_sock_diag.patch index 88e2edd289f..b93fe2b725d 100644 --- a/target/linux/generic/hack-6.1/901-debloat_sock_diag.patch +++ b/target/linux/generic/hack-6.1/901-debloat_sock_diag.patch @@ -79,7 +79,7 @@ Signed-off-by: Felix Fietkau INDIRECT_CALLABLE_DECLARE(struct dst_entry *ip6_dst_check(struct dst_entry *, u32)); INDIRECT_CALLABLE_DECLARE(struct dst_entry *ipv4_dst_check(struct dst_entry *, -@@ -2174,9 +2188,11 @@ static void __sk_free(struct sock *sk) +@@ -2168,9 +2182,11 @@ static void __sk_free(struct sock *sk) if (likely(sk->sk_net_refcnt)) sock_inuse_add(sock_net(sk), -1); diff --git a/target/linux/generic/hack-6.1/902-debloat_proc.patch b/target/linux/generic/hack-6.1/902-debloat_proc.patch index bac3d4af827..5722ac97b1e 100644 --- a/target/linux/generic/hack-6.1/902-debloat_proc.patch +++ b/target/linux/generic/hack-6.1/902-debloat_proc.patch @@ -330,7 +330,7 @@ Signed-off-by: Felix Fietkau --- a/net/core/sock.c +++ b/net/core/sock.c -@@ -4088,6 +4088,8 @@ static __net_initdata struct pernet_oper +@@ -4082,6 +4082,8 @@ static __net_initdata struct pernet_oper static int __init proto_init(void) { diff --git a/target/linux/generic/pending-6.1/723-net-mt7531-ensure-all-MACs-are-powered-down-before-r.patch b/target/linux/generic/pending-6.1/723-net-mt7531-ensure-all-MACs-are-powered-down-before-r.patch index 00a43e3e551..6540819d47a 100644 --- a/target/linux/generic/pending-6.1/723-net-mt7531-ensure-all-MACs-are-powered-down-before-r.patch +++ b/target/linux/generic/pending-6.1/723-net-mt7531-ensure-all-MACs-are-powered-down-before-r.patch @@ -15,7 +15,7 @@ Signed-off-by: Alexander Couzens --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2236,6 +2236,10 @@ mt7530_setup(struct dsa_switch *ds) +@@ -2248,6 +2248,10 @@ mt7530_setup(struct dsa_switch *ds) return -ENODEV; } diff --git a/target/linux/generic/pending-6.1/795-mt7530-register-OF-node-for-internal-MDIO-bus.patch b/target/linux/generic/pending-6.1/795-mt7530-register-OF-node-for-internal-MDIO-bus.patch index 26f40d9f87b..d4e0d4107b5 100644 --- a/target/linux/generic/pending-6.1/795-mt7530-register-OF-node-for-internal-MDIO-bus.patch +++ b/target/linux/generic/pending-6.1/795-mt7530-register-OF-node-for-internal-MDIO-bus.patch @@ -16,7 +16,7 @@ Signed-off-by: David Bauer --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2126,10 +2126,13 @@ mt7530_setup_mdio(struct mt7530_priv *pr +@@ -2138,10 +2138,13 @@ mt7530_setup_mdio(struct mt7530_priv *pr { struct dsa_switch *ds = priv->ds; struct device *dev = priv->dev; @@ -30,7 +30,7 @@ Signed-off-by: David Bauer bus = devm_mdiobus_alloc(dev); if (!bus) return -ENOMEM; -@@ -2146,7 +2149,9 @@ mt7530_setup_mdio(struct mt7530_priv *pr +@@ -2158,7 +2161,9 @@ mt7530_setup_mdio(struct mt7530_priv *pr if (priv->irq) mt7530_setup_mdio_irq(priv); From 79a82d7e8734bf9e5b7cd12efcda0f18b4ba378a Mon Sep 17 00:00:00 2001 From: John Audia Date: Sat, 1 Jul 2023 10:50:36 -0400 Subject: [PATCH 16/53] kernel: bump 6.1 to 6.1.37 Manually rebased: generic/hack-6.1/220-arm-gc_sections.patch armsr/patches-6.1/221-armsr-disable_gc_sections_armv7.patch All other patches automatically rebased. Signed-off-by: John Audia --- include/kernel-6.1 | 4 ++-- .../patches-6.1/221-armsr-disable_gc_sections_armv7.patch | 4 ++-- .../patches-6.1/202-mips-bmips-tweak-Kconfig-options.patch | 4 ++-- .../bmips/patches-6.1/600-mips-bmips-add-pci-support.patch | 2 +- .../020-v6.3-10-UPSTREAM-mm-add-vma_has_recency.patch | 2 +- target/linux/generic/hack-6.1/220-arm-gc_sections.patch | 4 ++-- .../linux/generic/pending-6.1/300-mips_expose_boot_raw.patch | 4 ++-- .../0060-ARM-mach-qcom-fix-support-for-ipq806x.patch | 4 ++-- .../0067-generic-Mangle-bootloader-s-kernel-arguments.patch | 2 +- .../ipq806x/patches-6.1/900-arm-add-cmdline-override.patch | 2 +- 10 files changed, 16 insertions(+), 16 deletions(-) diff --git a/include/kernel-6.1 b/include/kernel-6.1 index 2748562eba4..5a672efd323 100644 --- a/include/kernel-6.1 +++ b/include/kernel-6.1 @@ -1,2 +1,2 @@ -LINUX_VERSION-6.1 = .36 -LINUX_KERNEL_HASH-6.1.36 = d8ca0e300f30b9ff70c6e1497c638a1dac1407f45d3655e9c62c6e45a08afe6b \ No newline at end of file +LINUX_VERSION-6.1 = .37 +LINUX_KERNEL_HASH-6.1.37 = 46cad712d261a23c8e483a3b79b6a84b9a5f731a8921c9127df35ae35cef1e80 \ No newline at end of file diff --git a/target/linux/armsr/patches-6.1/221-armsr-disable_gc_sections_armv7.patch b/target/linux/armsr/patches-6.1/221-armsr-disable_gc_sections_armv7.patch index cb124c1cf8f..ef8493fa0d8 100644 --- a/target/linux/armsr/patches-6.1/221-armsr-disable_gc_sections_armv7.patch +++ b/target/linux/armsr/patches-6.1/221-armsr-disable_gc_sections_armv7.patch @@ -13,10 +13,10 @@ Signed-off-by: Mathew McBride --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig -@@ -122,7 +122,6 @@ config ARM - select HAVE_UID16 +@@ -123,7 +123,6 @@ config ARM select HAVE_VIRT_CPU_ACCOUNTING_GEN select IRQ_FORCED_THREADING + select LOCK_MM_AND_FIND_VMA - select HAVE_LD_DEAD_CODE_DATA_ELIMINATION select MODULES_USE_ELF_REL select NEED_DMA_MAP_STATE diff --git a/target/linux/bmips/patches-6.1/202-mips-bmips-tweak-Kconfig-options.patch b/target/linux/bmips/patches-6.1/202-mips-bmips-tweak-Kconfig-options.patch index 1c4a478148f..36f8beb89f1 100644 --- a/target/linux/bmips/patches-6.1/202-mips-bmips-tweak-Kconfig-options.patch +++ b/target/linux/bmips/patches-6.1/202-mips-bmips-tweak-Kconfig-options.patch @@ -13,7 +13,7 @@ Signed-off-by: Álvaro Fernández Rojas --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig -@@ -273,19 +273,13 @@ config BMIPS_GENERIC +@@ -274,19 +274,13 @@ config BMIPS_GENERIC select SYNC_R4K select COMMON_CLK select BCM6345_L1_IRQ @@ -33,7 +33,7 @@ Signed-off-by: Álvaro Fernández Rojas select SWAP_IO_SPACE select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN -@@ -295,6 +289,7 @@ config BMIPS_GENERIC +@@ -296,6 +290,7 @@ config BMIPS_GENERIC select HAVE_PCI select PCI_DRIVERS_GENERIC select FW_CFE diff --git a/target/linux/bmips/patches-6.1/600-mips-bmips-add-pci-support.patch b/target/linux/bmips/patches-6.1/600-mips-bmips-add-pci-support.patch index 66e8db4d010..e5c22bb17fd 100644 --- a/target/linux/bmips/patches-6.1/600-mips-bmips-add-pci-support.patch +++ b/target/linux/bmips/patches-6.1/600-mips-bmips-add-pci-support.patch @@ -14,7 +14,7 @@ Signed-off-by: Álvaro Fernández Rojas --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig -@@ -287,7 +287,6 @@ config BMIPS_GENERIC +@@ -288,7 +288,6 @@ config BMIPS_GENERIC select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN select HARDIRQS_SW_RESEND select HAVE_PCI diff --git a/target/linux/generic/backport-6.1/020-v6.3-10-UPSTREAM-mm-add-vma_has_recency.patch b/target/linux/generic/backport-6.1/020-v6.3-10-UPSTREAM-mm-add-vma_has_recency.patch index b5051d71a47..69078629055 100644 --- a/target/linux/generic/backport-6.1/020-v6.3-10-UPSTREAM-mm-add-vma_has_recency.patch +++ b/target/linux/generic/backport-6.1/020-v6.3-10-UPSTREAM-mm-add-vma_has_recency.patch @@ -87,7 +87,7 @@ Signed-off-by: T.J. Mercier mark_page_accessed(page); } rss[mm_counter(page)]--; -@@ -5170,8 +5169,8 @@ static inline void mm_account_fault(stru +@@ -5182,8 +5181,8 @@ static inline void mm_account_fault(stru #ifdef CONFIG_LRU_GEN static void lru_gen_enter_fault(struct vm_area_struct *vma) { diff --git a/target/linux/generic/hack-6.1/220-arm-gc_sections.patch b/target/linux/generic/hack-6.1/220-arm-gc_sections.patch index 483118138e2..b644739768d 100644 --- a/target/linux/generic/hack-6.1/220-arm-gc_sections.patch +++ b/target/linux/generic/hack-6.1/220-arm-gc_sections.patch @@ -12,10 +12,10 @@ Signed-off-by: Gabor Juhos --- --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig -@@ -122,6 +122,7 @@ config ARM - select HAVE_UID16 +@@ -123,6 +123,7 @@ config ARM select HAVE_VIRT_CPU_ACCOUNTING_GEN select IRQ_FORCED_THREADING + select LOCK_MM_AND_FIND_VMA + select HAVE_LD_DEAD_CODE_DATA_ELIMINATION select MODULES_USE_ELF_REL select NEED_DMA_MAP_STATE diff --git a/target/linux/generic/pending-6.1/300-mips_expose_boot_raw.patch b/target/linux/generic/pending-6.1/300-mips_expose_boot_raw.patch index 82576d644d7..9e571a6d875 100644 --- a/target/linux/generic/pending-6.1/300-mips_expose_boot_raw.patch +++ b/target/linux/generic/pending-6.1/300-mips_expose_boot_raw.patch @@ -9,7 +9,7 @@ Acked-by: Rob Landley --- --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig -@@ -1033,9 +1033,6 @@ config FW_ARC +@@ -1034,9 +1034,6 @@ config FW_ARC config ARCH_MAY_HAVE_PC_FDC bool @@ -19,7 +19,7 @@ Acked-by: Rob Landley config CEVT_BCM1480 bool -@@ -3090,6 +3087,18 @@ choice +@@ -3091,6 +3088,18 @@ choice bool "Extend builtin kernel arguments with bootloader arguments" endchoice diff --git a/target/linux/ipq806x/patches-6.1/0060-ARM-mach-qcom-fix-support-for-ipq806x.patch b/target/linux/ipq806x/patches-6.1/0060-ARM-mach-qcom-fix-support-for-ipq806x.patch index 384eee6215b..40c45626106 100644 --- a/target/linux/ipq806x/patches-6.1/0060-ARM-mach-qcom-fix-support-for-ipq806x.patch +++ b/target/linux/ipq806x/patches-6.1/0060-ARM-mach-qcom-fix-support-for-ipq806x.patch @@ -21,7 +21,7 @@ Signed-off-by: Christian Marangi --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig -@@ -283,6 +283,7 @@ config PHYS_OFFSET +@@ -284,6 +284,7 @@ config PHYS_OFFSET default 0x30000000 if ARCH_S3C24XX default 0xa0000000 if ARCH_IOP32X || ARCH_PXA default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 @@ -29,7 +29,7 @@ Signed-off-by: Christian Marangi default 0 help Please provide the physical address corresponding to the -@@ -1702,7 +1703,7 @@ config CRASH_DUMP +@@ -1703,7 +1704,7 @@ config CRASH_DUMP config AUTO_ZRELADDR bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM diff --git a/target/linux/ipq806x/patches-6.1/0067-generic-Mangle-bootloader-s-kernel-arguments.patch b/target/linux/ipq806x/patches-6.1/0067-generic-Mangle-bootloader-s-kernel-arguments.patch index e40b43b968d..15365322fb1 100644 --- a/target/linux/ipq806x/patches-6.1/0067-generic-Mangle-bootloader-s-kernel-arguments.patch +++ b/target/linux/ipq806x/patches-6.1/0067-generic-Mangle-bootloader-s-kernel-arguments.patch @@ -22,7 +22,7 @@ Signed-off-by: Adrian Panella --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig -@@ -1586,6 +1586,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN +@@ -1587,6 +1587,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN The command-line arguments provided by the boot loader will be appended to the the device tree bootargs property. diff --git a/target/linux/ipq806x/patches-6.1/900-arm-add-cmdline-override.patch b/target/linux/ipq806x/patches-6.1/900-arm-add-cmdline-override.patch index 6361cfcbd91..e07947f4b48 100644 --- a/target/linux/ipq806x/patches-6.1/900-arm-add-cmdline-override.patch +++ b/target/linux/ipq806x/patches-6.1/900-arm-add-cmdline-override.patch @@ -1,6 +1,6 @@ --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig -@@ -1599,6 +1599,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGL +@@ -1600,6 +1600,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGL endchoice From a20735da211930a50330725d5f0b29f81b2a0b9c Mon Sep 17 00:00:00 2001 From: John Audia Date: Mon, 3 Jul 2023 05:31:33 -0400 Subject: [PATCH 17/53] kernel: add CONFIG_LOCK_MM_AND_FIND_VMA 6.1.37 introduces a new symbol[1] 1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/diff/arch/x86/Kconfig?id=v6.1.37&id2=v6.1.36 Signed-off-by: John Audia --- target/linux/generic/config-6.1 | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/generic/config-6.1 b/target/linux/generic/config-6.1 index 8bf9d4a3d85..c88e106aa5a 100644 --- a/target/linux/generic/config-6.1 +++ b/target/linux/generic/config-6.1 @@ -3316,6 +3316,7 @@ CONFIG_LOCKDEP_STACK_TRACE_BITS=19 CONFIG_LOCKDEP_STACK_TRACE_HASH_BITS=14 CONFIG_LOCKDEP_SUPPORT=y CONFIG_LOCKD_V4=y +CONFIG_LOCK_MM_AND_FIND_VMA=y # CONFIG_LOCKUP_DETECTOR is not set # CONFIG_LOCK_EVENT_COUNTS is not set # CONFIG_LOCK_STAT is not set From c22931b653633f368569f638258b41df7943f14a Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Thu, 6 Jul 2023 21:01:06 +0200 Subject: [PATCH 18/53] kernel-headers: install isa-rev.h on mips to fix lzma-lader on linux 6.1 Since kernel 5.17+ the mips asm.h includes isa-rev.h, which itself was added 4.17. Without it, lzma-loader will fail to build: make[3] -C target/linux compile make[5]: warning: jobserver unavailable: using -j1. Add '+' to parent make rule. In file included from head.S:22: .../staging_dir/toolchain-mips_mips32_gcc-12.3.0_musl/include/asm/asm.h:22:10: fatal error: asm/isa-rev.h: No such file or directory 22 | #include | ^~~~~~~~~~~~~~~ compilation terminated. make[6]: *** [Makefile:64: head.o] Error 1 make[5]: *** [Makefile:345: compile] Error 2 make[4]: *** [Makefile:24: compile] Error 2 make[3]: *** [Makefile:11: compile] Error 2 ERROR: target/linux failed to build. So add the file to the files to install. We can do that unconditionally, since the oldest supported kernel 5.15 already includes it, even it if does not need it. Signed-off-by: Jonas Gorski --- toolchain/kernel-headers/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/toolchain/kernel-headers/Makefile b/toolchain/kernel-headers/Makefile index eea0ffbde07..c1a8710a4fb 100644 --- a/toolchain/kernel-headers/Makefile +++ b/toolchain/kernel-headers/Makefile @@ -68,6 +68,7 @@ ifneq ($(CONFIG_mips)$(CONFIG_mipsel),) $(HOST_BUILD_DIR)/arch/mips/include/asm/asm.h \ $(HOST_BUILD_DIR)/arch/mips/include/asm/regdef.h \ $(HOST_BUILD_DIR)/arch/mips/include/asm/asm-eva.h \ + $(HOST_BUILD_DIR)/arch/mips/include/asm/isa-rev.h \ $(BUILD_DIR_TOOLCHAIN)/linux-dev/include/asm/ endef endif From 02c1acbfba431f48ec23946a6cd51c9a7e03f724 Mon Sep 17 00:00:00 2001 From: Koen Vandeputte Date: Tue, 6 Jun 2023 18:03:42 +0200 Subject: [PATCH 19/53] kernel: add missing symbols in 5.15 Found these while playing with video pci media adapter support Signed-off-by: Koen Vandeputte --- target/linux/generic/config-5.15 | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/target/linux/generic/config-5.15 b/target/linux/generic/config-5.15 index a7308ede9d8..a2770f2d5f6 100644 --- a/target/linux/generic/config-5.15 +++ b/target/linux/generic/config-5.15 @@ -1684,8 +1684,10 @@ CONFIG_DUMMY_CONSOLE_ROWS=25 # CONFIG_DVB_ATBM8830 is not set # CONFIG_DVB_AU8522_DTV is not set # CONFIG_DVB_AU8522_V4L is not set +# CONFIG_DVB_B2C2_FLEXCOP_PCI is not set # CONFIG_DVB_B2C2_FLEXCOP_USB is not set # CONFIG_DVB_BCM3510 is not set +# CONFIG_DVB_BUDGET_CORE is not set # CONFIG_DVB_CORE is not set # CONFIG_DVB_CX22700 is not set # CONFIG_DVB_CX22702 is not set @@ -1698,6 +1700,7 @@ CONFIG_DUMMY_CONSOLE_ROWS=25 # CONFIG_DVB_CXD2820R is not set # CONFIG_DVB_CXD2841ER is not set # CONFIG_DVB_CXD2880 is not set +# CONFIG_DVB_DDBRIDGE is not set # CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set # CONFIG_DVB_DIB3000MB is not set # CONFIG_DVB_DIB3000MC is not set @@ -1744,12 +1747,17 @@ CONFIG_DVB_MAX_ADAPTERS=16 # CONFIG_DVB_MXL5XX is not set # CONFIG_DVB_MXL692 is not set # CONFIG_DVB_NET is not set +# CONFIG_DVB_NETUP_UNIDVB is not set +# CONFIG_DVB_NGENE is not set # CONFIG_DVB_NXT200X is not set # CONFIG_DVB_NXT6000 is not set # CONFIG_DVB_OR51132 is not set # CONFIG_DVB_OR51211 is not set # CONFIG_DVB_PLATFORM_DRIVERS is not set # CONFIG_DVB_PLL is not set +# CONFIG_DVB_PLUTO2 is not set +# CONFIG_DVB_PT1 is not set +# CONFIG_DVB_PT3 is not set # CONFIG_DVB_RTL2830 is not set # CONFIG_DVB_RTL2832 is not set # CONFIG_DVB_RTL2832_SDR is not set @@ -7241,12 +7249,14 @@ CONFIG_VHOST_MENU=y # CONFIG_VIDEO_CADENCE is not set # CONFIG_VIDEO_CAFE_CCIC is not set # CONFIG_VIDEO_CCS is not set +# CONFIG_VIDEO_COBALT is not set # CONFIG_VIDEO_CODA is not set # CONFIG_VIDEO_CS3308 is not set # CONFIG_VIDEO_CS5345 is not set # CONFIG_VIDEO_CS53L32A is not set # CONFIG_VIDEO_CX231XX is not set # CONFIG_VIDEO_CX2341X is not set +# CONFIG_VIDEO_CX25821 is not set # CONFIG_VIDEO_CX25840 is not set # CONFIG_VIDEO_CX88 is not set # CONFIG_VIDEO_DEV is not set @@ -7279,6 +7289,7 @@ CONFIG_VHOST_MENU=y # CONFIG_VIDEO_IMX477 is not set # CONFIG_VIDEO_IMX8_JPEG is not set # CONFIG_VIDEO_IMX_PXP is not set +# CONFIG_VIDEO_IPU3_CIO2 is not set # CONFIG_VIDEO_IRS1125 is not set # CONFIG_VIDEO_IR_I2C is not set # CONFIG_VIDEO_IVTV is not set @@ -7348,10 +7359,12 @@ CONFIG_VHOST_MENU=y # CONFIG_VIDEO_SAA711X is not set # CONFIG_VIDEO_SAA7127 is not set # CONFIG_VIDEO_SAA7134 is not set +# CONFIG_VIDEO_SAA7164 is not set # CONFIG_VIDEO_SAA717X is not set # CONFIG_VIDEO_SAA7185 is not set # CONFIG_VIDEO_SH_MOBILE_CEU is not set # CONFIG_VIDEO_SMIAPP is not set +# CONFIG_VIDEO_SOLO6X10 is not set # CONFIG_VIDEO_SONY_BTF_MPX is not set # CONFIG_VIDEO_SR030PC30 is not set # CONFIG_VIDEO_STK1160_COMMON is not set @@ -7372,6 +7385,8 @@ CONFIG_VHOST_MENU=y # CONFIG_VIDEO_TVP5150 is not set # CONFIG_VIDEO_TVP7002 is not set # CONFIG_VIDEO_TW2804 is not set +# CONFIG_VIDEO_TW5864 is not set +# CONFIG_VIDEO_TW68 is not set # CONFIG_VIDEO_TW9903 is not set # CONFIG_VIDEO_TW9906 is not set # CONFIG_VIDEO_TW9910 is not set From 0a0b1fd15907285b6172d7cdcc5196211f43330e Mon Sep 17 00:00:00 2001 From: Koen Vandeputte Date: Thu, 8 Jun 2023 09:43:41 +0200 Subject: [PATCH 20/53] kernel: add missing symbols in 6.1 Found these while playing with video pci media adapter support Signed-off-by: Koen Vandeputte --- target/linux/generic/config-6.1 | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/target/linux/generic/config-6.1 b/target/linux/generic/config-6.1 index c88e106aa5a..4d7ef7b2bdd 100644 --- a/target/linux/generic/config-6.1 +++ b/target/linux/generic/config-6.1 @@ -1773,6 +1773,7 @@ CONFIG_DUMMY_CONSOLE_ROWS=25 # CONFIG_DVB_ATBM8830 is not set # CONFIG_DVB_AU8522_DTV is not set # CONFIG_DVB_AU8522_V4L is not set +# CONFIG_DVB_B2C2_FLEXCOP_PCI is not set # CONFIG_DVB_B2C2_FLEXCOP_USB is not set # CONFIG_DVB_BCM3510 is not set # CONFIG_DVB_CORE is not set @@ -1787,6 +1788,7 @@ CONFIG_DUMMY_CONSOLE_ROWS=25 # CONFIG_DVB_CXD2820R is not set # CONFIG_DVB_CXD2841ER is not set # CONFIG_DVB_CXD2880 is not set +# CONFIG_DVB_DDBRIDGE is not set # CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set # CONFIG_DVB_DIB3000MB is not set # CONFIG_DVB_DIB3000MC is not set @@ -1833,12 +1835,17 @@ CONFIG_DVB_MAX_ADAPTERS=16 # CONFIG_DVB_MXL5XX is not set # CONFIG_DVB_MXL692 is not set # CONFIG_DVB_NET is not set +# CONFIG_DVB_NETUP_UNIDVB is not set +# CONFIG_DVB_NGENE is not set # CONFIG_DVB_NXT200X is not set # CONFIG_DVB_NXT6000 is not set # CONFIG_DVB_OR51132 is not set # CONFIG_DVB_OR51211 is not set # CONFIG_DVB_PLATFORM_DRIVERS is not set # CONFIG_DVB_PLL is not set +# CONFIG_DVB_PLUTO2 is not set +# CONFIG_DVB_PT1 is not set +# CONFIG_DVB_PT3 is not set # CONFIG_DVB_RTL2830 is not set # CONFIG_DVB_RTL2832 is not set # CONFIG_DVB_RTL2832_SDR is not set @@ -7494,12 +7501,14 @@ CONFIG_VHOST_MENU=y # CONFIG_VIDEO_CADENCE_CSI2TX is not set # CONFIG_VIDEO_CAFE_CCIC is not set # CONFIG_VIDEO_CCS is not set +# CONFIG_VIDEO_COBALT is not set # CONFIG_VIDEO_CODA is not set # CONFIG_VIDEO_CS3308 is not set # CONFIG_VIDEO_CS5345 is not set # CONFIG_VIDEO_CS53L32A is not set # CONFIG_VIDEO_CX231XX is not set # CONFIG_VIDEO_CX2341X is not set +# CONFIG_VIDEO_CX25821 is not set # CONFIG_VIDEO_CX25840 is not set # CONFIG_VIDEO_CX88 is not set # CONFIG_VIDEO_DEV is not set @@ -7607,10 +7616,12 @@ CONFIG_VHOST_MENU=y # CONFIG_VIDEO_SAA711X is not set # CONFIG_VIDEO_SAA7127 is not set # CONFIG_VIDEO_SAA7134 is not set +# CONFIG_VIDEO_SAA7164 is not set # CONFIG_VIDEO_SAA717X is not set # CONFIG_VIDEO_SAA7185 is not set # CONFIG_VIDEO_SH_MOBILE_CEU is not set # CONFIG_VIDEO_SMIAPP is not set +# CONFIG_VIDEO_SOLO6X10 is not set # CONFIG_VIDEO_SONY_BTF_MPX is not set # CONFIG_VIDEO_SR030PC30 is not set # CONFIG_VIDEO_STK1160_COMMON is not set @@ -7631,6 +7642,8 @@ CONFIG_VHOST_MENU=y # CONFIG_VIDEO_TVP5150 is not set # CONFIG_VIDEO_TVP7002 is not set # CONFIG_VIDEO_TW2804 is not set +# CONFIG_VIDEO_TW5864 is not set +# CONFIG_VIDEO_TW68 is not set # CONFIG_VIDEO_TW9903 is not set # CONFIG_VIDEO_TW9906 is not set # CONFIG_VIDEO_TW9910 is not set From 0295a29f1d2bfcd973261ee69970e109adb60baf Mon Sep 17 00:00:00 2001 From: Koen Vandeputte Date: Wed, 8 Feb 2023 16:26:36 +0100 Subject: [PATCH 21/53] kernel: add support for mem2mem devices This allows addition of devices which use these kernel modules. This also adds a package for handling dma within video2buf. These are only build when selected by a caller Signed-off-by: Koen Vandeputte --- package/kernel/linux/modules/video.mk | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/package/kernel/linux/modules/video.mk b/package/kernel/linux/modules/video.mk index f1e61f33a57..d6bacbbf12e 100644 --- a/package/kernel/linux/modules/video.mk +++ b/package/kernel/linux/modules/video.mk @@ -10,6 +10,7 @@ VIDEO_MENU:=Video Support V4L2_DIR=v4l2-core V4L2_USB_DIR=usb +V4L2_MEM2MEM_DIR=platform # # Video Display @@ -1044,3 +1045,25 @@ define KernelPackage/video-gspca-konica/description endef $(eval $(call KernelPackage,video-gspca-konica)) + +# +# Video Processing +# + +define KernelPackage/video-mem2mem + SUBMENU:=$(VIDEO_MENU) + TITLE:=Memory 2 Memory device support + HIDDEN:=1 + DEPENDS:=+kmod-video-videobuf2 + KCONFIG:= CONFIG_V4L_MEM2MEM_DRIVERS=y + FILES:= $(LINUX_DIR)/drivers/media/$(V4L2_DIR)/v4l2-mem2mem.ko + AUTOLOAD:=$(call AutoLoad,66,v4l2-mem2mem) + $(call AddDepends/video) +endef + +define KernelPackage/video-mem2mem/description + Memory 2 memory device support +endef + +$(eval $(call KernelPackage,video-mem2mem)) + From f1a9240f0b6c3a5e167c7624ab781bca9a1b6010 Mon Sep 17 00:00:00 2001 From: Koen Vandeputte Date: Wed, 8 Feb 2023 16:29:19 +0100 Subject: [PATCH 22/53] kernel: add support for videobuf-dma This adds support for videobuf2-dma driver. This module contains following flavors: - Contiguous - Scatter/Gather Drivers using this can enable 1 of the, or both, depending on their needs. Due to this, a FILES catch-all is required for the videobuf-dma objects as depending on requirements, only 1 of them could get generated. Signed-off-by: Koen Vandeputte --- package/kernel/linux/modules/video.mk | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/package/kernel/linux/modules/video.mk b/package/kernel/linux/modules/video.mk index d6bacbbf12e..68a1d32e76e 100644 --- a/package/kernel/linux/modules/video.mk +++ b/package/kernel/linux/modules/video.mk @@ -1067,3 +1067,21 @@ endef $(eval $(call KernelPackage,video-mem2mem)) +define KernelPackage/video-dma + SUBMENU:=$(VIDEO_MENU) + TITLE:=Video DMA support + HIDDEN:=1 + DEPENDS:=+kmod-video-videobuf2 + KCONFIG:= \ + CONFIG_VIDEOBUF2_DMA_CONTIG \ + CONFIG_VIDEOBUF2_DMA_SG + FILES:= $(LINUX_DIR)/drivers/media/common/videobuf2/videobuf2-dma-*.ko + AUTOLOAD:=$(call AutoLoad,66,videobuf2-dma-contig videobuf2-dma-sg) + $(call AddDepends/video) +endef + +define KernelPackage/video-dma/description + Video DMA support +endef + +$(eval $(call KernelPackage,video-dma)) From 7a726297a7bad1a71e17dcebf0849f0da0468d40 Mon Sep 17 00:00:00 2001 From: Koen Vandeputte Date: Wed, 5 Jul 2023 13:19:28 +0200 Subject: [PATCH 23/53] kernel: add support for imx vpu This adds support for the Video Processing Unit IP block which is present in certain i.MX SOC's. The vpu used in imx6 is the coda960 which supports: - h264 enc - h264 dec - jpeg enc - jpeg dec Please note that the required firmware needs to be added by yourself as it's not available currently in linux-firmware upstream. The firmware package can be found on the internet and it will decompress itself exposing all binaries after accepting the EULA. The binaries should be placed at exactly these paths: - /lib/firmware/vpu_fw_imx6d.bin - /lib/firmware/vpu_fw_imx6q.bin Following output will be printed at boottime if all is well: [ 9.769638] coda 2040000.vpu: Firmware code revision: 46076 [ 9.775277] coda 2040000.vpu: Initialized CODA960. [ 9.780082] coda 2040000.vpu: Firmware version: 3.1.1 [ 9.785312] coda 2040000.vpu: coda-jpeg-encoder registered as video0 [ 9.791859] coda 2040000.vpu: coda-jpeg-decoder registered as video1 [ 9.798375] coda 2040000.vpu: coda-video-encoder registered as video2 [ 9.805013] coda 2040000.vpu: coda-video-decoder registered as video3 gstreamer will automatically detect and use all encoders/decoders. Please note that a FILES catch-all is required for the videobuf-dma objects as some modules enabling this could require (and thus generating) only 1 of them. Signed-off-by: Koen Vandeputte --- package/kernel/linux/modules/video.mk | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/package/kernel/linux/modules/video.mk b/package/kernel/linux/modules/video.mk index 68a1d32e76e..7dfeec9d913 100644 --- a/package/kernel/linux/modules/video.mk +++ b/package/kernel/linux/modules/video.mk @@ -1085,3 +1085,23 @@ define KernelPackage/video-dma/description endef $(eval $(call KernelPackage,video-dma)) + +define KernelPackage/video-coda + TITLE:=i.MX VPU support + DEPENDS:=@(TARGET_imx&&!TARGET_imx_cortexa7) +kmod-video-mem2mem +kmod-video-dma + KCONFIG:= \ + CONFIG_VIDEO_CODA \ + CONFIG_VIDEO_IMX_VDOA + FILES:= \ + $(LINUX_DIR)/drivers/media/$(V4L2_MEM2MEM_DIR)/coda/coda-vpu.ko \ + $(LINUX_DIR)/drivers/media/$(V4L2_MEM2MEM_DIR)/coda/imx-vdoa.ko \ + $(LINUX_DIR)/drivers/media/$(V4L2_DIR)/v4l2-jpeg.ko + AUTOLOAD:=$(call AutoProbe,coda-vpu imx-vdoa v4l2-jpeg) + $(call AddDepends/video) +endef + +define KernelPackage/video-coda/description + The i.MX Video Processing Unit (VPU) kernel module +endef + +$(eval $(call KernelPackage,video-coda)) From a9a872b9d4ccf0d79381d20e114742439606132f Mon Sep 17 00:00:00 2001 From: Koen Vandeputte Date: Mon, 26 Jun 2023 17:23:07 +0200 Subject: [PATCH 24/53] kernel: add support for imx pxp This adds support for the i.MX Pixel Pipeline IP block which is available on some imx6 flavours [1] This allows to use hardware offloading for operations like: - Colour conversion - Scaling - Rotation [1] https://en.wikipedia.org/wiki/I.MX#i.MX_6_series Signed-off-by: Koen Vandeputte --- package/kernel/linux/modules/video.mk | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/package/kernel/linux/modules/video.mk b/package/kernel/linux/modules/video.mk index 7dfeec9d913..d06ee3926bd 100644 --- a/package/kernel/linux/modules/video.mk +++ b/package/kernel/linux/modules/video.mk @@ -1105,3 +1105,20 @@ define KernelPackage/video-coda/description endef $(eval $(call KernelPackage,video-coda)) + +define KernelPackage/video-pxp + TITLE:=i.MX PXP support + DEPENDS:=@TARGET_imx +kmod-video-mem2mem +kmod-video-dma + KCONFIG:= CONFIG_VIDEO_IMX_PXP + FILES:= $(LINUX_DIR)/drivers/media/$(V4L2_MEM2MEM_DIR)/imx-pxp.ko + AUTOLOAD:=$(call AutoProbe,imx-pxp) + $(call AddDepends/video) +endef + +define KernelPackage/video-pxp/description + The i.MX Pixel Pipeline (PXP) kernel module + This enables hardware accelerated support for image + Colour Conversion, Scaling and Rotation +endef + +$(eval $(call KernelPackage,video-pxp)) From bc91784f26b2816c949ad4b102930ccd449e2881 Mon Sep 17 00:00:00 2001 From: Koen Vandeputte Date: Wed, 7 Jun 2023 11:58:52 +0200 Subject: [PATCH 25/53] kernel: add support for tw686x frame grabbers Adds support for Intersil/Techwell tw686x frame grabbers. By default, this module uses MEMCPY to transfer data. Let's switch to "Contiguous DMA" which is the fastest performing method available. [ 10.074349] tw6869: PCI 0000:07:00.0, IRQ 33, MMIO 0x1200000 (contig mode) [ 10.081381] tw686x 0000:07:00.0: enabling device (0140 -> 0142) Signed-off-by: Koen Vandeputte --- package/kernel/linux/modules/video.mk | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/package/kernel/linux/modules/video.mk b/package/kernel/linux/modules/video.mk index d06ee3926bd..e8a2d479ee0 100644 --- a/package/kernel/linux/modules/video.mk +++ b/package/kernel/linux/modules/video.mk @@ -439,6 +439,10 @@ $(AddDepends/video) CONFIG_MEDIA_CAMERA_SUPPORT=y endef +define AddDepends/framegrabber +$(AddDepends/video) + KCONFIG+=CONFIG_MEDIA_PCI_SUPPORT=y +endef define KernelPackage/video-videobuf2 TITLE:=videobuf2 lib @@ -1122,3 +1126,19 @@ define KernelPackage/video-pxp/description endef $(eval $(call KernelPackage,video-pxp)) + +define KernelPackage/video-tw686x + TITLE:=TW686x support + DEPENDS:=@PCIE_SUPPORT +kmod-video-dma +kmod-sound-core + KCONFIG:= CONFIG_VIDEO_TW686X + FILES:= $(LINUX_DIR)/drivers/media/pci/tw686x/tw686x.ko + AUTOLOAD:=$(call AutoProbe,tw686x) + MODPARAMS.tw686x:=dma_mode=contig + $(call AddDepends/framegrabber) +endef + +define KernelPackage/video-tw686x/description + The Intersil/Techwell TW686x kernel module +endef + +$(eval $(call KernelPackage,video-tw686x)) From e386b279fdab758f75160636bca5385dae202aee Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Thu, 6 Jul 2023 20:55:17 +0200 Subject: [PATCH 26/53] generic: 6.1: fix uImage.FIT partitions on mtdblock and ubiblock When refreshing the hack patches for Linux 6.1 the part of the uImage.FIT partition parser patch which takes care of allowing mtdblock and ubiblock devices to have partitions has been dropped, supposedly by accident. Re-add a that part to the patch, so devices using a uImage.FIT filesystem sub-image as rootfs can work with Linux 6.1. Fixes: 19a246bb65 ("generic: 6.1: manually refresh hack patches") Signed-off-by: Daniel Golle --- .../410-block-fit-partition-parser.patch | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/target/linux/generic/hack-6.1/410-block-fit-partition-parser.patch b/target/linux/generic/hack-6.1/410-block-fit-partition-parser.patch index 0384dad85e5..1258f64722a 100644 --- a/target/linux/generic/hack-6.1/410-block-fit-partition-parser.patch +++ b/target/linux/generic/hack-6.1/410-block-fit-partition-parser.patch @@ -179,6 +179,32 @@ Subject: [PATCH] kernel: add block fit partition parser {0, NULL}, }; +--- a/drivers/mtd/mtd_blkdevs.c ++++ b/drivers/mtd/mtd_blkdevs.c +@@ -359,7 +359,9 @@ int add_mtd_blktrans_dev(struct mtd_blkt + } else { + snprintf(gd->disk_name, sizeof(gd->disk_name), + "%s%d", tr->name, new->devnum); +- gd->flags |= GENHD_FL_NO_PART; ++ ++ if (!IS_ENABLED(CONFIG_FIT_PARTITION) || mtd_type_is_nand(new->mtd)) ++ gd->flags |= GENHD_FL_NO_PART; + } + + set_capacity(gd, ((u64)new->size * tr->blksize) >> 9); +--- a/drivers/mtd/ubi/block.c ++++ b/drivers/mtd/ubi/block.c +@@ -431,7 +431,9 @@ int ubiblock_create(struct ubi_volume_in + ret = -ENODEV; + goto out_cleanup_disk; + } +- gd->flags |= GENHD_FL_NO_PART; ++ if (!IS_ENABLED(CONFIG_FIT_PARTITION)) ++ gd->flags |= GENHD_FL_NO_PART; ++ + gd->private_data = dev; + sprintf(gd->disk_name, "ubiblock%d_%d", dev->ubi_num, dev->vol_id); + set_capacity(gd, disk_capacity); --- a/include/linux/msdos_partition.h +++ b/include/linux/msdos_partition.h @@ -31,6 +31,7 @@ enum msdos_sys_ind { From 0c5605b70c7853eff73e5a6d7dfb4b650e0b4420 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sun, 18 Jun 2023 03:22:51 +0200 Subject: [PATCH 27/53] mediatek: prepare old rtk switch driver for use with Linux 6.1 The old RealTek RTL8367S switch driver which is used for some MT7622 devices needs to be modified to no longer free the GPIO after reset has completed. This is due to Linux 5.19 removing devm_gpio_free via commit 2b038e786f83 ("gpiolib: devres: Get rid of unused devm_gpio_free()") Signed-off-by: Daniel Golle --- .../files/drivers/net/phy/rtk/rtl8367s_mdio.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s_mdio.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s_mdio.c index ae958e89672..08d2b57d438 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s_mdio.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s_mdio.c @@ -71,16 +71,10 @@ unsigned int mii_mgr_write(unsigned int phy_addr,unsigned int phy_register,unsig static int rtl8367s_hw_reset(void) { struct rtk_gsw *gsw = _gsw; - int ret; if (gsw->reset_pin < 0) return 0; - ret = devm_gpio_request(gsw->dev, gsw->reset_pin, "mediatek,reset-pin"); - - if (ret) - printk("fail to devm_gpio_request\n"); - gpio_direction_output(gsw->reset_pin, 0); usleep_range(1000, 1100); @@ -89,10 +83,7 @@ static int rtl8367s_hw_reset(void) mdelay(500); - devm_gpio_free(gsw->dev, gsw->reset_pin); - return 0; - } static int rtl8367s_vlan_config(int want_at_p0) @@ -235,6 +226,7 @@ static int rtk_gsw_probe(struct platform_device *pdev) struct mii_bus *mdio_bus; struct rtk_gsw *gsw; const char *pm; + int ret; mdio = of_parse_phandle(np, "mediatek,mdio", 0); @@ -256,6 +248,11 @@ static int rtk_gsw_probe(struct platform_device *pdev) gsw->bus = mdio_bus; gsw->reset_pin = of_get_named_gpio(np, "mediatek,reset-pin", 0); + if (gsw->reset_pin >= 0) { + ret = devm_gpio_request(gsw->dev, gsw->reset_pin, "mediatek,reset-pin"); + if (ret) + printk("fail to devm_gpio_request\n"); + } _gsw = gsw; From d85438f454bb9d2698bda8548ddb5783cb24c368 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Tue, 27 Jun 2023 02:06:47 +0200 Subject: [PATCH 28/53] mediatek: copy patches and files for Linux 6.1 First step only copies patches-5.15 and files-5.15 to patches-6.1 and files-6.1 respectively. Signed-off-by: Daniel Golle --- .../arch/arm64/boot/dts/mediatek/mt7981.dtsi | 775 +++++++++ .../mt7986a-bananapi-bpi-r3-emmc.dtso | 29 + .../mt7986a-bananapi-bpi-r3-nand.dtso | 55 + .../mediatek/mt7986a-bananapi-bpi-r3-nor.dtso | 63 + .../mediatek/mt7986a-bananapi-bpi-r3-sd.dtso | 23 + .../dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 499 ++++++ .../dts/mediatek/mt7986a-rfb-spim-nand.dts | 52 + .../dts/mediatek/mt7986a-rfb-spim-nor.dts | 51 + .../arm64/boot/dts/mediatek/mt7986a-rfb.dtsi | 389 +++++ .../arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 633 +++++++ .../arm64/boot/dts/mediatek/mt7986b-rfb.dts | 194 +++ .../arch/arm64/boot/dts/mediatek/mt7986b.dtsi | 15 + .../mediatek/mt7988a-dsa-10g-spim-nand.dts | 200 +++ .../dts/mediatek/mt7988a-rfb-spim-nand.dtsi | 70 + .../arm64/boot/dts/mediatek/mt7988a-rfb.dtsi | 175 ++ .../arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 853 +++++++++ .../drivers/clk/mediatek/clk-mt7981-apmixed.c | 102 ++ .../drivers/clk/mediatek/clk-mt7981-eth.c | 139 ++ .../clk/mediatek/clk-mt7981-infracfg.c | 235 +++ .../clk/mediatek/clk-mt7981-topckgen.c | 450 +++++ .../drivers/clk/mediatek/clk-mt7986-apmixed.c | 100 ++ .../drivers/clk/mediatek/clk-mt7986-eth.c | 132 ++ .../clk/mediatek/clk-mt7986-infracfg.c | 224 +++ .../clk/mediatek/clk-mt7986-topckgen.c | 342 ++++ .../drivers/clk/mediatek/clk-mt7988-apmixed.c | 113 ++ .../drivers/clk/mediatek/clk-mt7988-eth.c | 299 ++++ .../clk/mediatek/clk-mt7988-infracfg.c | 399 +++++ .../clk/mediatek/clk-mt7988-topckgen.c | 522 ++++++ .../drivers/net/phy/mediatek-2p5ge.c | 262 +++ .../drivers/net/phy/mediatek-ge-soc.c | 1263 ++++++++++++++ .../drivers/pinctrl/mediatek/pinctrl-mt7981.c | 1048 +++++++++++ .../drivers/pinctrl/mediatek/pinctrl-mt7986.c | 1003 +++++++++++ .../drivers/pinctrl/mediatek/pinctrl-mt7988.c | 1281 ++++++++++++++ .../dt-bindings/clock/mediatek,mt7981-clk.h | 215 +++ .../dt-bindings/clock/mediatek,mt7988-clk.h | 276 +++ .../include/dt-bindings/clock/mt7986-clk.h | 169 ++ .../include/dt-bindings/reset/mt7986-resets.h | 55 + .../100-dts-update-mt7622-rfb1.patch | 119 ++ .../101-dts-update-mt7629-rfb.patch | 60 + .../103-mt7623-enable-arch-timer.patch | 20 + .../patches-6.1/104-mt7622-add-snor-irq.patch | 10 + .../105-dts-mt7622-enable-pstore.patch | 25 + .../110-dts-fix-bpi2-console.patch | 10 + .../111-dts-fix-bpi64-console.patch | 11 + .../112-dts-fix-bpi64-lan-names.patch | 37 + .../113-dts-fix-bpi64-leds-and-buttons.patch | 56 + .../114-dts-bpi64-disable-rtc.patch | 21 + .../115-dts-bpi64-add-snand-support.patch | 50 + ...-infrastructure-to-support-hardware-.patch | 214 +++ ...ew-helper-to-retrieve-the-ECC-contex.patch | 31 + ...vide-a-helper-to-retrieve-a-pileline.patch | 73 + ...mem-Introduce-a-capability-structure.patch | 71 + ...ck-the-controller-extra-capabilities.patch | 51 + ...l-the-spi_mem_dtr_supports_op-helper.patch | 111 ++ ...an-ecc-parameter-to-the-spi_mem_op-s.patch | 72 + ...lay-a-little-bit-the-dirmap-creation.patch | 50 + ...te-direct-mapping-descriptors-for-EC.patch | 98 ++ ...nd-make-mtk_ecc.c-a-separated-module.patch | 1383 +++++++++++++++ ...ver-for-MTK-SPI-NAND-Flash-Interface.patch | 1537 +++++++++++++++++ ...-also-parse-nand-ecc-engine-if-avail.patch | 30 + ...dts-mediatek-add-mtk-snfi-for-mt7622.patch | 35 + .../121-hack-spi-nand-1b-bbm.patch | 20 + .../130-dts-mt7629-add-snand-support.patch | 94 + .../131-dts-mt7622-add-snand-support.patch | 68 + ...dts-fix-wmac-support-for-mt7622-rfb1.patch | 18 + ...s-mt7623-eip97-inside-secure-support.patch | 24 + .../160-dts-mt7623-bpi-r2-earlycon.patch | 11 + ...1-dts-mt7623-bpi-r2-mmc-device-order.patch | 11 + .../162-dts-mt7623-bpi-r2-led-aliases.patch | 29 + ...163-dts-mt7623-bpi-r2-ethernet-alias.patch | 10 + ...arm-dts-mt7623-add-musb-device-nodes.patch | 69 + ...80-dts-mt7622-bpi-r64-add-mt7531-irq.patch | 13 + ...-dts-mediatek-mt7622-fix-GICv2-range.patch | 106 ++ ...mt7622-specify-the-L2-cache-topology.patch | 132 ++ ...2-specify-the-number-of-DMA-requests.patch | 122 ++ .../193-dts-mt7623-thermal_zone_fix.patch | 48 + .../194-dts-mt7968a-add-ramoops.patch | 17 + ...i-r3-leds-port-names-and-wifi-eeprom.patch | 196 +++ ...-phy-phy-mtk-tphy-Add-hifsys-support.patch | 66 + ...-mediatek-add-support-for-MT7986-SoC.patch | 26 + ...k-Add-API-for-clock-resource-recycle.patch | 28 + ...lk-mediatek-add-mt7986-clock-support.patch | 39 + ...-spi-mediatek-add-mt7986-spi-support.patch | 917 ++++++++++ ...lk-mediatek-add-mt7981-clock-support.patch | 39 + ...-mediatek-add-support-for-MT7981-SoC.patch | 26 + ...-mediatek-add-support-for-MT7988-SoC.patch | 26 + ...k-mediatek-Add-pcw-chg-shift-control.patch | 24 + ...lk-mediatek-add-mt7988-clock-support.patch | 31 + ...-mediatek-add-support-for-MT7986-SoC.patch | 44 + .../330-snand-mtk-bmt-support.patch | 34 + .../331-mt7622-rfb1-enable-bmt.patch | 10 + ...Add-support-for-the-Fidelix-FM35X1GA.patch | 122 ++ ...-Cleanup-variables-and-error-handlin.patch | 166 ++ ...ufreq-mediatek-Remove-unused-headers.patch | 25 + ...ediatek-Enable-clocks-and-regulators.patch | 117 ++ ...diatek-Use-device-print-to-show-logs.patch | 161 ++ ...freq-mediatek-Replace-old_-with-pre_.patch | 201 +++ ...k-Record-previous-target-vproc-value.patch | 64 + ...ediatek-Make-sram-regulator-optional.patch | 30 + ...-Fix-NULL-pointer-dereference-in-med.patch | 32 + ...-Move-voltage-limits-to-platform-dat.patch | 227 +++ ...-Refine-mtk_cpufreq_voltage_tracking.patch | 255 +++ ...ediatek-Add-opp-notification-support.patch | 184 ++ ...-Fix-potential-deadlock-problem-in-m.patch | 43 + ...freq-mediatek-Link-CCI-device-to-CPU.patch | 188 ++ ...freq-mediatek-Add-support-for-MT8186.patch | 42 + ...-Handle-sram-regulator-probe-deferra.patch | 35 + ...-fix-error-return-code-in-mtk_cpu_dv.patch | 29 + ...mediatek-fix-passing-zero-to-PTR_ERR.patch | 47 + ...-fix-KP-caused-by-handler-usage-afte.patch | 149 ++ ...-raise-proc-sram-max-voltage-for-MT8.patch | 55 + ...-Raise-proc-and-sram-max-voltage-for.patch | 58 + ...freq-mediatek-Add-support-for-MT7988.patch | 41 + ...-correct-voltages-for-MT7622-and-MT7.patch | 53 + ...ypto-add-eip97-inside-secure-support.patch | 27 + ...01-crypto-fix-eip97-cache-incoherent.patch | 26 + .../405-mt7986-trng-add-rng-support.patch | 41 + .../patches-6.1/410-bt-mtk-serial-fix.patch | 33 + ...or-add-support-for-Winbond-W25Q512JV.patch | 28 + ...xx-Move-chip_config-to-driver-s-priv.patch | 130 ++ ...-Add-support-for-dynamic-calibration.patch | 236 +++ ...ers-spi-mem-Add-spi-calibration-hook.patch | 41 + ...xx-Add-controller-s-calibration-para.patch | 43 + ...and-Add-calibration-support-for-spin.patch | 81 + ...nor-Add-calibration-support-for-spi-.patch | 57 + .../500-gsw-rtl8367s-mt7622-support.patch | 25 + ...ek-Split-PCIe-node-for-MT2712-and-MT.patch | 332 ++++ ...ert-PERST-for-100ms-for-power-and-cl.patch | 34 + ...s-mediatek-add-mt7622-pcie-slot-node.patch | 28 + ...dts-mediatek-Update-mt7629-PCIe-node.patch | 203 +++ ...diatek-fix-clearing-interrupt-status.patch | 23 + ...pers-to-extract-clause-45-regad-and-.patch | 53 + ..._eth_soc-implement-Clause-45-MDIO-ac.patch | 128 ++ ...ediatek-add-support-for-coherent-DMA.patch | 82 + .../721-dts-mt7622-mediatek-fix-300mhz.patch | 27 + .../722-remove-300Hz-to-prevent-freeze.patch | 25 + ...er-for-MediaTek-SoC-built-in-GE-PHYs.patch | 82 + ...et-phy-hack-mxl-gpy-disable-sgmii-an.patch | 166 ++ ...phy-add-driver-for-MediaTek-2.5G-PHY.patch | 39 + ...k-tphy-Add-PCIe-2-lane-efuse-support.patch | 225 +++ ...-add-auto-load-valid-check-mechanism.patch | 149 ++ .../804-pwm-add-mt7986-support.patch | 23 + ...mtk-use-function-pointer-for-raw_to_.patch | 56 + ...ek-add-support-for-MT7986-and-MT7981.patch | 240 +++ ...-pwm-mediatek-Add-support-for-MT7981.patch | 122 ++ ...dings-pinctrl-mt8195-add-rsel-define.patch | 33 + ...-moore-check-if-pin_desc-is-valid-be.patch | 93 + ...inctrl-mediatek-support-rsel-feature.patch | 457 +++++ ...-add-a-check-for-error-in-mtk_pincon.patch | 31 + ...-Fix-EINT-pins-input-debounce-time-c.patch | 297 ++++ ...mediatek-Export-debounce-time-tables.patch | 37 + ...-extend-pinctrl-moore-to-support-new.patch | 129 ++ ...dd-bindings-for-Richtek-RT5190A-PMIC.patch | 180 ++ ...a-Add-support-for-Richtek-RT5190A-PM.patch | 562 ++++++ ...et-the-handshake-signal-between-i2c-.patch | 74 + ...p-i2c-dma-register-when-a-timeout-oc.patch | 102 ++ ...d-i2c-compatible-for-Mediatek-MT8186.patch | 45 + ...modify-bus-speed-calculation-formula.patch | 132 ++ ...mediatek-remove-redundant-null-check.patch | 41 + ...18-i2c-mt65xx-Simplify-with-clk-bulk.patch | 234 +++ ...d-i2c-compatible-for-Mediatek-MT8168.patch | 46 + ...imize-master_xfer-and-avoid-circular.patch | 101 ++ ...-an-error-handling-path-in-mtk_i2c_p.patch | 48 + ...diatek-add-i2c-compatible-for-MT8188.patch | 82 + ...move-drivers-from-strlcpy-to-strscpy.patch | 579 +++++++ ...v6.2-i2c-mediatek-add-mt7986-support.patch | 44 + ...evm_platform_get_and_ioremap_resourc.patch | 42 + ...t65xx-drop-of_match_ptr-for-ID-table.patch | 33 + ...-mediatek-add-support-for-MT7981-SoC.patch | 47 + ...mt7622-bpi-r64-aliases-for-dtoverlay.patch | 65 + .../901-arm-add-cmdline-override.patch | 54 + .../910-dts-mt7622-bpi-r64-wifi-eeprom.patch | 31 + ...g-mtk-add-disable_wdt_extrst-support.patch | 50 + ...t-mt7986-Add-toprgu-reset-controller.patch | 49 + ...3-change-driver-name-to-mtk-pcie-gen.patch | 20 + .../930-spi-mt65xx-enable-sel-clk.patch | 29 + ..._wed-rename-mtk_wed_get_memory_regio.patch | 44 + ...986-move-cpuboot-in-a-dedicated-node.patch | 66 + ..._wed-move-cpuboot-in-a-dedicated-dts.patch | 89 + ...tk_wed-move-ilm-a-dedicated-dts-node.patch | 91 + ...tk_wed-move-dlm-a-dedicated-dts-node.patch | 57 + ...-mt7986-move-ilm-in-a-dedicated-node.patch | 83 + ...-mt7986-move-dlm-in-a-dedicated-node.patch | 81 + 183 files changed, 28585 insertions(+) create mode 100644 target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi create mode 100644 target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso create mode 100644 target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso create mode 100644 target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso create mode 100644 target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso create mode 100644 target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts create mode 100644 target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts create mode 100644 target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts create mode 100644 target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi create mode 100644 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mode 100644 target/linux/mediatek/patches-6.1/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi new file mode 100644 index 00000000000..3629a6f6dda --- /dev/null +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi @@ -0,0 +1,775 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2020 MediaTek Inc. + * Author: Sam.Shih + * Author: Jianhui Zhao + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + compatible = "mediatek,mt7981"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x1>; + }; + }; + + pwm: pwm@10048000 { + compatible = "mediatek,mt7981-pwm"; + reg = <0 0x10048000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&infracfg CLK_INFRA_PWM_STA>, + <&infracfg CLK_INFRA_PWM_HCK>, + <&infracfg CLK_INFRA_PWM1_CK>, + <&infracfg CLK_INFRA_PWM2_CK>, + <&infracfg CLK_INFRA_PWM3_CK>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + /* cooling level (0, 1, 2, 3) : (0% duty, 50% duty, 75% duty, 100% duty) */ + cooling-levels = <0 128 192 255>; + #cooling-cells = <2>; + status = "disabled"; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + thermal-sensors = <&thermal 0>; + trips { + cpu_trip_crit: crit { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu_trip_hot: hot { + temperature = <120000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_trip_active_high: active-high { + temperature = <115000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_med: active-med { + temperature = <85000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_low: active-low { + temperature = <60000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + cpu-active-high { + /* active: set fan to cooling level 3 */ + cooling-device = <&fan 3 3>; + trip = <&cpu_trip_active_high>; + }; + + cpu-active-med { + /* active: set fan to cooling level 2 */ + cooling-device = <&fan 2 2>; + trip = <&cpu_trip_active_med>; + }; + + cpu-active-low { + /* passive: set fan to cooling level 1 */ + cooling-device = <&fan 1 1>; + trip = <&cpu_trip_active_low>; + }; + }; + }; + }; + + thermal: thermal@1100c800 { + #thermal-sensor-cells = <1>; + compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal"; + reg = <0 0x1100c800 0 0x800>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_THERM_CK>, + <&infracfg CLK_INFRA_ADC_26M_CK>; + clock-names = "therm", "auxadc"; + mediatek,auxadc = <&auxadc>; + mediatek,apmixedsys = <&apmixedsys>; + nvmem-cells = <&thermal_calibration>; + nvmem-cell-names = "calibration-data"; + }; + + auxadc: adc@1100d000 { + compatible = "mediatek,mt7981-auxadc", + "mediatek,mt7986-auxadc", + "mediatek,mt7622-auxadc"; + reg = <0 0x1100d000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_ADC_26M_CK>, + <&infracfg CLK_INFRA_ADC_FRC_CK>; + clock-names = "main", "32k"; + #io-channel-cells = <1>; + }; + + wdma: wdma@15104800 { + compatible = "mediatek,wed-wdma"; + reg = <0 0x15104800 0 0x400>, + <0 0x15104c00 0 0x400>; + }; + + ap2woccif: ap2woccif@151a5000 { + compatible = "mediatek,ap2woccif"; + reg = <0 0x151a5000 0 0x1000>, + <0 0x151ad000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = , + ; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 64 KiB reserved for ramoops/pstore */ + ramoops@42ff0000 { + compatible = "ramoops"; + reg = <0 0x42ff0000 0 0x10000>; + record-size = <0x1000>; + }; + + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@43000000 { + reg = <0 0x43000000 0 0x30000>; + no-map; + }; + + wmcpu_emi: wmcpu-reserved@47c80000 { + reg = <0 0x47c80000 0 0x100000>; + no-map; + }; + + wo_emi0: wo-emi@47d80000 { + reg = <0 0x47d80000 0 0x40000>; + no-map; + }; + + wo_data: wo-data@47dc0000 { + reg = <0 0x47dc0000 0 0x240000>; + no-map; + }; + + wo_ilm0: wo-ilm@151e0000 { + reg = <0 0x151e0000 0 0x8000>; + no-map; + }; + + wo_dlm0: wo-dlm@151e8000 { + reg = <0 0x151e8000 0 0x2000>; + no-map; + }; + + wo_boot: wo-boot@15194000 { + reg = <0 0x15194000 0 0x1000>; + no-map; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + trng { + compatible = "mediatek,mt7981-rng"; + }; + + clk40m: oscillator@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + clock-output-names = "clkxtal"; + }; + + infracfg: infracfg@10001000 { + compatible = "mediatek,mt7981-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + topckgen: topckgen@1001B000 { + compatible = "mediatek,mt7981-topckgen", "syscon"; + reg = <0 0x1001B000 0 0x1000>; + #clock-cells = <1>; + }; + + apmixedsys: apmixedsys@1001E000 { + compatible = "mediatek,mt7981-apmixedsys", "mediatek,mt7986-apmixedsys", "syscon"; + reg = <0 0x1001E000 0 0x1000>; + #clock-cells = <1>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + clock-frequency = <13000000>; + interrupts = , + , + , + ; + + }; + + watchdog: watchdog@1001c000 { + compatible = "mediatek,mt7986-wdt", + "mediatek,mt6589-wdt"; + reg = <0 0x1001c000 0 0x1000>; + interrupts = ; + #reset-cells = <1>; + status = "disabled"; + }; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x40000>, /* GICD */ + <0 0x0c080000 0 0x200000>; /* GICR */ + + interrupts = ; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_UART0_SEL>, + <&infracfg CLK_INFRA_UART0_CK>; + clock-names = "baud", "bus"; + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_UART0_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>, + <&topckgen CLK_TOP_UART_SEL>; + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x400>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_UART1_SEL>, + <&infracfg CLK_INFRA_UART1_CK>; + clock-names = "baud", "bus"; + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_UART1_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>, + <&topckgen CLK_TOP_UART_SEL>; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x400>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_UART2_SEL>, + <&infracfg CLK_INFRA_UART2_CK>; + clock-names = "baud", "bus"; + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_UART2_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>, + <&topckgen CLK_TOP_UART_SEL>; + status = "disabled"; + }; + + i2c0: i2c@11007000 { + compatible = "mediatek,mt7981-i2c"; + reg = <0 0x11007000 0 0x1000>, + <0 0x10217080 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_INFRA_I2C0_CK>, + <&infracfg CLK_INFRA_AP_DMA_CK>, + <&infracfg CLK_INFRA_I2C_MCK_CK>, + <&infracfg CLK_INFRA_I2C_PCK_CK>; + clock-names = "main", "dma", "arb", "pmic"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pcie: pcie@11280000 { + compatible = "mediatek,mt7981-pcie", + "mediatek,mt7986-pcie"; + device_type = "pci"; + reg = <0 0x11280000 0 0x4000>; + reg-names = "pcie-mac"; + #address-cells = <3>; + #size-cells = <2>; + interrupts = ; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x20000000 + 0x0 0x20000000 0 0x10000000>; + status = "disabled"; + + clocks = <&infracfg CLK_INFRA_IPCIE_CK>, + <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, + <&infracfg CLK_INFRA_IPCIER_CK>, + <&infracfg CLK_INFRA_IPCIEB_CK>; + + phys = <&u3port0 PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + pcie_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + crypto: crypto@10320000 { + compatible = "inside-secure,safexcel-eip97"; + reg = <0 0x10320000 0 0x40000>; + interrupts = , + , + , + ; + interrupt-names = "ring0", "ring1", "ring2", "ring3"; + clocks = <&topckgen CLK_TOP_EIP97B>; + clock-names = "top_eip97_ck"; + assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>; + }; + + pio: pinctrl@11d00000 { + compatible = "mediatek,mt7981-pinctrl"; + reg = <0 0x11d00000 0 0x1000>, + <0 0x11c00000 0 0x1000>, + <0 0x11c10000 0 0x1000>, + <0 0x11d20000 0 0x1000>, + <0 0x11e00000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11f00000 0 0x1000>, + <0 0x11f10000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_rt", "iocfg_rm", + "iocfg_rb", "iocfg_lb", "iocfg_bl", + "iocfg_tm", "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 56>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + + mdio_pins: mdc-mdio-pins { + mux { + function = "eth"; + groups = "smi_mdc_mdio"; + }; + }; + + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0"; + }; + }; + + wifi_dbdc_pins: wifi-dbdc-pins { + mux { + function = "eth"; + groups = "wf0_mode1"; + }; + conf { + pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4", + "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6", + "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10", + "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ", + "WF_CBA_RESETB", "WF_DIG_RESETB"; + drive-strength = <4>; + }; + }; + }; + + ethsys: syscon@15000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mediatek,mt7981-ethsys", + "mediatek,mt7986-ethsys", + "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + wed: wed@15010000 { + compatible = "mediatek,mt7981-wed", + "mediatek,mt7986-wed", + "syscon"; + reg = <0 0x15010000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, + <&wo_data>, <&wo_boot>; + memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", + "wo-data", "wo-boot"; + mediatek,wo-ccif = <&wo_ccif0>; + }; + + eth: ethernet@15100000 { + compatible = "mediatek,mt7981-eth"; + reg = <0 0x15100000 0 0x80000>; + interrupts = , + , + , + ; + clocks = <ðsys CLK_ETH_FE_EN>, + <ðsys CLK_ETH_GP2_EN>, + <ðsys CLK_ETH_GP1_EN>, + <ðsys CLK_ETH_WOCPU0_EN>, + <&sgmiisys0 CLK_SGM0_TX_EN>, + <&sgmiisys0 CLK_SGM0_RX_EN>, + <&sgmiisys0 CLK_SGM0_CK0_EN>, + <&sgmiisys0 CLK_SGM0_CDR_CK0_EN>, + <&sgmiisys1 CLK_SGM1_TX_EN>, + <&sgmiisys1 CLK_SGM1_RX_EN>, + <&sgmiisys1 CLK_SGM1_CK1_EN>, + <&sgmiisys1 CLK_SGM1_CDR_CK1_EN>, + <&topckgen CLK_TOP_SGM_REG>, + <&topckgen CLK_TOP_NETSYS_SEL>, + <&topckgen CLK_TOP_NETSYS_500M_SEL>; + clock-names = "fe", "gp2", "gp1", "wocpu0", + "sgmii_tx250m", "sgmii_rx250m", + "sgmii_cdr_ref", "sgmii_cdr_fb", + "sgmii2_tx250m", "sgmii2_rx250m", + "sgmii2_cdr_ref", "sgmii2_cdr_fb", + "sgmii_ck", "netsys0", "netsys1"; + assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, + <&topckgen CLK_TOP_SGM_325M_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>, + <&topckgen CLK_TOP_CB_SGM_325M>; + mediatek,ethsys = <ðsys>; + mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; + mediatek,infracfg = <&topmisc>; + mediatek,wed = <&wed>; + #reset-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + mdio_bus: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + int_gbe_phy: ethernet-phy@0 { + reg = <0>; + compatible = "ethernet-phy-ieee802.3-c22"; + phy-mode = "gmii"; + phy-is-integrated; + nvmem-cells = <&phy_calibration>; + nvmem-cell-names = "phy-cal-data"; + }; + }; + }; + + wo_ccif0: syscon@151a5000 { + compatible = "mediatek,mt7986-wo-ccif", "syscon"; + reg = <0 0x151a5000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + sgmiisys0: syscon@10060000 { + compatible = "mediatek,mt7981-sgmiisys_0", "mediatek,mt7986-sgmiisys_0", "syscon"; + reg = <0 0x10060000 0 0x1000>; + mediatek,pnswap; + #clock-cells = <1>; + }; + + sgmiisys1: syscon@10070000 { + compatible = "mediatek,mt7981-sgmiisys_1", "mediatek,mt7986-sgmiisys_1", "syscon"; + reg = <0 0x10070000 0 0x1000>; + #clock-cells = <1>; + }; + + topmisc: topmisc@11d10000 { + compatible = "mediatek,mt7981-topmisc", "syscon"; + reg = <0 0x11d10000 0 0x10000>; + #clock-cells = <1>; + }; + + snand: snfi@11005000 { + compatible = "mediatek,mt7986-snand"; + reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>; + reg-names = "nfi", "ecc"; + interrupts = ; + clocks = <&infracfg CLK_INFRA_SPINFI1_CK>, + <&infracfg CLK_INFRA_NFI1_CK>, + <&infracfg CLK_INFRA_NFI_HCK_CK>; + clock-names = "pad_clk", "nfi_clk", "nfi_hclk"; + assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>, + <&topckgen CLK_TOP_NFI1X_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>, + <&topckgen CLK_TOP_CB_M_D8>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt7986-mmc", + "mediatek,mt7981-mmc"; + reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_MSDC_CK>, + <&infracfg CLK_INFRA_MSDC_HCK_CK>, + <&infracfg CLK_INFRA_MSDC_66M_CK>, + <&infracfg CLK_INFRA_MSDC_133M_CK>; + assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>, + <&topckgen CLK_TOP_EMMC_400M_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>, + <&topckgen CLK_TOP_CB_NET2_D2>; + clock-names = "source", "hclk", "axi_cg", "ahb_cg"; + status = "disabled"; + }; + + wed_pcie: wed_pcie@10003000 { + compatible = "mediatek,wed_pcie"; + reg = <0 0x10003000 0 0x10>; + }; + + spi0: spi@1100a000 { + compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100a000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_CB_M_D2>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI0_CK>, + <&infracfg CLK_INFRA_SPI0_HCK_CK>; + + clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; + status = "disabled"; + }; + + spi1: spi@1100b000 { + compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100b000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_CB_M_D2>, + <&topckgen CLK_TOP_SPIM_MST_SEL>, + <&infracfg CLK_INFRA_SPI1_CK>, + <&infracfg CLK_INFRA_SPI1_HCK_CK>; + clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; + status = "disabled"; + }; + + spi2: spi@11009000 { + compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11009000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_CB_M_D2>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI2_CK>, + <&infracfg CLK_INFRA_SPI2_HCK_CK>; + clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; + status = "disabled"; + }; + + consys: consys@10000000 { + compatible = "mediatek,mt7981-consys"; + reg = <0 0x10000000 0 0x8600000>; + memory-region = <&wmcpu_emi>; + }; + + xhci: usb@11200000 { + compatible = "mediatek,mt7986-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x2e00>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>, + <&infracfg CLK_INFRA_IUSB_CK>, + <&infracfg CLK_INFRA_IUSB_133_CK>, + <&infracfg CLK_INFRA_IUSB_66M_CK>, + <&topckgen CLK_TOP_U2U3_XHCI_SEL>; + clock-names = "sys_ck", + "ref_ck", + "mcu_ck", + "dma_ck", + "xhci_ck"; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>; + vusb33-supply = <®_3p3v>; + status = "disabled"; + }; + + usb_phy: usb-phy@11e10000 { + compatible = "mediatek,mt7981", + "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11e10000 0x1700>; + status = "disabled"; + + u2port0: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>; + clock-names = "ref"; + #phy-cells = <1>; + }; + + u3port0: usb-phy@700 { + reg = <0x700 0x900>; + clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>; + clock-names = "ref"; + #phy-cells = <1>; + mediatek,syscon-type = <&topmisc 0x218 0>; + status = "okay"; + }; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + efuse: efuse@11f20000 { + compatible = "mediatek,mt7981-efuse", + "mediatek,efuse"; + reg = <0 0x11f20000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + + thermal_calibration: thermal-calib@274 { + reg = <0x274 0xc>; + }; + + phy_calibration: phy-calib@8dc { + reg = <0x8dc 0x10>; + }; + + comb_rx_imp_p0: usb3-rx-imp@8c8 { + reg = <0x8c8 1>; + bits = <0 5>; + }; + + comb_tx_imp_p0: usb3-tx-imp@8c8 { + reg = <0x8c8 2>; + bits = <5 5>; + }; + + comb_intr_p0: usb3-intr@8c9 { + reg = <0x8c9 1>; + bits = <2 6>; + }; + }; + + afe: audio-controller@11210000 { + compatible = "mediatek,mt79xx-audio"; + reg = <0 0x11210000 0 0x9000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>, + <&infracfg CLK_INFRA_AUD_26M_CK>, + <&infracfg CLK_INFRA_AUD_L_CK>, + <&infracfg CLK_INFRA_AUD_AUD_CK>, + <&infracfg CLK_INFRA_AUD_EG2_CK>, + <&topckgen CLK_TOP_AUD_SEL>; + clock-names = "aud_bus_ck", + "aud_26m_ck", + "aud_l_ck", + "aud_aud_ck", + "aud_eg2_ck", + "aud_sel"; + assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>, + <&topckgen CLK_TOP_A1SYS_SEL>, + <&topckgen CLK_TOP_AUD_L_SEL>, + <&topckgen CLK_TOP_A_TUNER_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>, + <&topckgen CLK_TOP_APLL2_D4>, + <&topckgen CLK_TOP_CB_APLL2_196M>, + <&topckgen CLK_TOP_APLL2_D4>; + status = "disabled"; + }; + + ice: ice_debug { + compatible = "mediatek,mt7981-ice_debug", + "mediatek,mt2701-ice_debug"; + clocks = <&infracfg CLK_INFRA_DBG_CK>; + clock-names = "ice_dbg"; + }; + + wifi: wifi@18000000 { + compatible = "mediatek,mt7981-wmac"; + resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; + reset-names = "consys"; + pinctrl-0 = <&wifi_dbdc_pins>; + pinctrl-names = "dbdc"; + clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>, + <&topckgen CLK_TOP_AP2CNN_HOST_SEL>; + clock-names = "mcu", "ap2conn"; + reg = <0 0x18000000 0 0x1000000>, + <0 0x10003000 0 0x1000>, + <0 0x11d10000 0 0x1000>; + interrupts = , + , + , + ; + memory-region = <&wmcpu_emi>; + status = "disabled"; + }; +}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso new file mode 100644 index 00000000000..779dc6782bb --- /dev/null +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; + + fragment@0 { + target-path = "/soc/mmc@11230000"; + __overlay__ { + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + hs400-ds-delay = <0x14014>; + non-removable; + no-sd; + no-sdio; + status = "okay"; + }; + }; +}; + diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso new file mode 100644 index 00000000000..15ee8c568f3 --- /dev/null +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Authors: Daniel Golle + * Frank Wunderlich + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; + + fragment@0 { + target-path = "/soc/spi@1100a000"; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + spi_nand: spi_nand@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <10000000>; + spi-tx-buswidth = <4>; + spi-rx-buswidth = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bl2"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@80000 { + label = "reserved"; + reg = <0x80000 0x300000>; + }; + + partition@380000 { + label = "fip"; + reg = <0x380000 0x200000>; + read-only; + }; + + partition@580000 { + label = "ubi"; + reg = <0x580000 0x7a80000>; + }; + }; + }; + }; + }; +}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso new file mode 100644 index 00000000000..e48881be4ed --- /dev/null +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Authors: Daniel Golle + * Frank Wunderlich + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; + + fragment@0 { + target-path = "/soc/spi@1100a000"; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bl2"; + reg = <0x0 0x40000>; + read-only; + }; + + partition@40000 { + label = "u-boot-env"; + reg = <0x40000 0x40000>; + }; + + partition@80000 { + label = "reserved2"; + reg = <0x80000 0x80000>; + }; + + partition@100000 { + label = "fip"; + reg = <0x100000 0x80000>; + read-only; + }; + + partition@180000 { + label = "recovery"; + reg = <0x180000 0xa80000>; + }; + + partition@c00000 { + label = "fit"; + reg = <0xc00000 0x1400000>; + }; + }; + }; + }; + }; +}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso new file mode 100644 index 00000000000..f623bce075c --- /dev/null +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; + + fragment@0 { + target-path = "/soc/mmc@11230000"; + __overlay__ { + bus-width = <4>; + max-frequency = <52000000>; + cap-sd-highspeed; + status = "okay"; + }; + }; +}; + diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts new file mode 100644 index 00000000000..af4a4309bda --- /dev/null +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts @@ -0,0 +1,499 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Authors: Sam.Shih + * Frank Wunderlich + * Daniel Golle + */ + +/dts-v1/; +#include +#include +#include +#include + +#include "mt7986a.dtsi" + +/ { + model = "Bananapi BPI-R3"; + chassis-type = "embedded"; + compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; + + aliases { + serial0 = &uart0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + dcin: regulator-12vd { + compatible = "regulator-fixed"; + regulator-name = "12vd"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-boot-on; + regulator-always-on; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + /* cooling level (0, 1, 2) - pwm inverted */ + cooling-levels = <255 96 0>; + pwms = <&pwm 0 10000 0>; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset-key { + label = "reset"; + linux,code = ; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + + wps-key { + label = "wps"; + linux,code = ; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + }; + + /* i2c of the left SFP cage (wan) */ + i2c_sfp1: i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* i2c of the right SFP cage (lan) */ + i2c_sfp2: i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + leds { + compatible = "gpio-leds"; + + green_led: led-0 { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&pio 69 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + blue_led: led-1 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 86 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1.8vd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + vin-supply = <&dcin>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3.3vd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + vin-supply = <&dcin>; + }; + + /* left SFP cage (wan) */ + sfp1: sfp-1 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp1>; + los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; + }; + + /* right SFP cage (lan) */ + sfp2: sfp-2 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp2>; + los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>; + }; +}; + +&cpu_thermal { + cooling-maps { + cpu-active-high { + /* active: set fan to cooling level 2 */ + cooling-device = <&fan 2 2>; + trip = <&cpu_trip_active_high>; + }; + + cpu-active-low { + /* active: set fan to cooling level 1 */ + cooling-device = <&fan 1 1>; + trip = <&cpu_trip_active_low>; + }; + + cpu-passive { + /* passive: set fan to cooling level 0 */ + cooling-device = <&fan 0 0>; + trip = <&cpu_trip_passive>; + }; + }; +}; + +&crypto { + status = "okay"; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; + sfp = <&sfp1>; + managed = "in-band-status"; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&mdio { + switch: switch@31 { + compatible = "mediatek,mt7531"; + reg = <31>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + }; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins>; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pio { + i2c_pins: i2c-pins { + mux { + function = "i2c"; + groups = "i2c"; + }; + }; + + mmc0_pins_default: mmc0-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + bias-pull-up = ; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + bias-pull-down = ; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + bias-pull-down = ; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + bias-pull-up = ; /* pull-up 10K */ + }; + }; + + mmc0_pins_uhs: mmc0-uhs-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + bias-pull-up = ; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + bias-pull-down = ; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + bias-pull-down = ; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + bias-pull-up = ; /* pull-up 10K */ + }; + }; + + pcie_pins: pcie-pins { + mux { + function = "pcie"; + groups = "pcie_clk", "pcie_pereset"; + }; + }; + + pwm_pins: pwm-pins { + mux { + function = "pwm"; + groups = "pwm0", "pwm1_0"; + }; + }; + + spi_flash_pins: spi-flash-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + + spic_pins: spic-pins { + mux { + function = "spi"; + groups = "spi1_0"; + }; + }; + + uart1_pins: uart1-pins { + mux { + function = "uart"; + groups = "uart1_rx_tx"; + }; + }; + + uart2_pins: uart2-pins { + mux { + function = "uart"; + groups = "uart2_0_rx_tx"; + }; + }; + + wf_2g_5g_pins: wf-2g-5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + wf_dbdc_pins: wf-dbdc-pins { + mux { + function = "wifi"; + groups = "wf_dbdc"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + wf_led_pins: wf-led-pins { + mux { + function = "led"; + groups = "wifi_led"; + }; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spic_pins>; + status = "okay"; +}; + +&ssusb { + status = "okay"; +}; + +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "wan"; + }; + + port@1 { + reg = <1>; + label = "lan0"; + }; + + port@2 { + reg = <2>; + label = "lan1"; + }; + + port@3 { + reg = <3>; + label = "lan2"; + }; + + port@4 { + reg = <4>; + label = "lan3"; + }; + + port5: port@5 { + reg = <5>; + label = "lan4"; + phy-mode = "2500base-x"; + sfp = <&sfp2>; + managed = "in-band-status"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; +}; + +&trng { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&wifi { + status = "okay"; + pinctrl-names = "default", "dbdc"; + pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>; + pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>; + + led { + led-active-low; + }; +}; + diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts new file mode 100644 index 00000000000..83a37150cf0 --- /dev/null +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ + +#include "mt7986a-rfb.dtsi" + +/ { + compatible = "mediatek,mt7986a-rfb-snand"; +}; + +&spi0 { + status = "okay"; + + spi_nand: spi_nand@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + reg = <1>; + spi-max-frequency = <10000000>; + spi-tx-buswidth = <4>; + spi-rx-buswidth = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "BL2"; + reg = <0x00000 0x0100000>; + read-only; + }; + partition@100000 { + label = "u-boot-env"; + reg = <0x0100000 0x0080000>; + }; + factory: partition@180000 { + label = "Factory"; + reg = <0x180000 0x0200000>; + }; + partition@380000 { + label = "FIP"; + reg = <0x380000 0x0200000>; + }; + partition@580000 { + label = "ubi"; + reg = <0x580000 0x4000000>; + }; + }; + }; +}; + +&wifi { + mediatek,mtd-eeprom = <&factory 0>; +}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts new file mode 100644 index 00000000000..868365a9942 --- /dev/null +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ + +#include "mt7986a-rfb.dtsi" + +/ { + compatible = "mediatek,mt7986a-rfb-snor"; +}; + +&spi0 { + status = "okay"; + + spi_nor: spi_nor@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-tx-buswidth = <4>; + spi-rx-buswidth = <4>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@00000 { + label = "BL2"; + reg = <0x00000 0x0040000>; + }; + partition@40000 { + label = "u-boot-env"; + reg = <0x40000 0x0010000>; + }; + factory: partition@50000 { + label = "Factory"; + reg = <0x50000 0x00B0000>; + }; + partition@100000 { + label = "FIP"; + reg = <0x100000 0x0080000>; + }; + partition@180000 { + label = "firmware"; + reg = <0x180000 0xE00000>; + }; + }; + }; +}; + +&wifi { + mediatek,mtd-eeprom = <&factory 0>; +}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi new file mode 100644 index 00000000000..1ab56e37f74 --- /dev/null +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi @@ -0,0 +1,389 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +#include "mt7986a.dtsi" + +/ { + model = "MediaTek MT7986a RFB"; + compatible = "mediatek,mt7986a-rfb"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0 0x40000000 0 0x40000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&wifi { + status = "okay"; + pinctrl-names = "default", "dbdc"; + pinctrl-0 = <&wf_2g_5g_pins>; + pinctrl-1 = <&wf_dbdc_pins>; +}; + +&mdio { + phy5: phy@5 { + compatible = "ethernet-phy-id67c9.de0a"; + reg = <5>; + + reset-gpios = <&pio 6 1>; + reset-deassert-us = <20000>; + }; + + phy6: phy@6 { + compatible = "ethernet-phy-id67c9.de0a"; + reg = <6>; + }; + + switch: switch@0 { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 5 0>; + }; +}; + +&crypto { + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + hs400-ds-delay = <0x14014>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pio { + mmc0_pins_default: mmc0-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + }; + + mmc0_pins_uhs: mmc0-uhs-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + }; + + pcie_pins: pcie-pins { + mux { + function = "pcie"; + groups = "pcie_clk", "pcie_wake", "pcie_pereset"; + }; + }; + + spic_pins_g2: spic-pins-29-to-32 { + mux { + function = "spi"; + groups = "spi1_2"; + }; + }; + + spi_flash_pins: spi-flash-pins-33-to-38 { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + conf-pu { + pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; + drive-strength = <8>; + mediatek,pull-up-adv = <0>; /* bias-disable */ + }; + conf-pd { + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; + drive-strength = <8>; + mediatek,pull-down-adv = <0>; /* bias-disable */ + }; + }; + + uart1_pins: uart1-pins { + mux { + function = "uart"; + groups = "uart1"; + }; + }; + + uart2_pins: uart2-pins { + mux { + function = "uart"; + groups = "uart2"; + }; + }; + + wf_2g_5g_pins: wf_2g_5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + wf_dbdc_pins: wf_dbdc-pins { + mux { + function = "wifi"; + groups = "wf_dbdc"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + cs-gpios = <0>, <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spic_pins_g2>; + status = "okay"; + + proslic_spi: proslic_spi@0 { + compatible = "silabs,proslic_spi"; + reg = <0>; + spi-max-frequency = <10000000>; + spi-cpha = <1>; + spi-cpol = <1>; + channel_count = <1>; + debug_level = <4>; /* 1 = TRC, 2 = DBG, 4 = ERR */ + reset_gpio = <&pio 7 0>; + ig,enable-spi = <1>; /* 1: Enable, 0: Disable */ + }; +}; + +&gmac1 { + phy-mode = "2500base-x"; + phy-connection-type = "2500base-x"; + phy-handle = <&phy6>; +}; + +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@5 { + reg = <5>; + label = "lan6"; + + phy-mode = "2500base-x"; + phy-handle = <&phy5>; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; +}; + +&ssusb { + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a.dtsi new file mode 100644 index 00000000000..68539ea788d --- /dev/null +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -0,0 +1,633 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih + */ + +#include +#include +#include +#include +#include + +/ { + compatible = "mediatek,mt7986a"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + clk40m: oscillator-40m { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + #clock-cells = <0>; + clock-output-names = "clkxtal"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x0>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x1>; + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x2>; + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + enable-method = "psci"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + #cooling-cells = <2>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@43000000 { + reg = <0 0x43000000 0 0x30000>; + no-map; + }; + + wmcpu_emi: wmcpu-reserved@4fc00000 { + no-map; + reg = <0 0x4fc00000 0 0x00100000>; + }; + + wo_emi0: wo-emi@4fd00000 { + reg = <0 0x4fd00000 0 0x40000>; + no-map; + }; + + wo_emi1: wo-emi@4fd40000 { + reg = <0 0x4fd40000 0 0x40000>; + no-map; + }; + + wo_ilm0: wo-ilm@151e0000 { + reg = <0 0x151e0000 0 0x8000>; + no-map; + }; + + wo_ilm1: wo-ilm@151f0000 { + reg = <0 0x151f0000 0 0x8000>; + no-map; + }; + + wo_data: wo-data@4fd80000 { + reg = <0 0x4fd80000 0 0x240000>; + no-map; + }; + + wo_dlm0: wo-dlm@151e8000 { + reg = <0 0x151e8000 0 0x2000>; + no-map; + }; + + wo_dlm1: wo-dlm@151f8000 { + reg = <0 0x151f8000 0 0x2000>; + no-map; + }; + + wo_boot: wo-boot@15194000 { + reg = <0 0x15194000 0 0x1000>; + no-map; + }; + + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x10000>, /* GICD */ + <0 0x0c080000 0 0x80000>, /* GICR */ + <0 0x0c400000 0 0x2000>, /* GICC */ + <0 0x0c410000 0 0x1000>, /* GICH */ + <0 0x0c420000 0 0x2000>; /* GICV */ + interrupts = ; + }; + + infracfg: infracfg@10001000 { + compatible = "mediatek,mt7986-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + wed_pcie: wed-pcie@10003000 { + compatible = "mediatek,mt7986-wed-pcie", + "syscon"; + reg = <0 0x10003000 0 0x10>; + }; + + topckgen: topckgen@1001b000 { + compatible = "mediatek,mt7986-topckgen", "syscon"; + reg = <0 0x1001B000 0 0x1000>; + #clock-cells = <1>; + }; + + watchdog: watchdog@1001c000 { + compatible = "mediatek,mt7986-wdt"; + reg = <0 0x1001c000 0 0x1000>; + interrupts = ; + #reset-cells = <1>; + status = "disabled"; + }; + + apmixedsys: apmixedsys@1001e000 { + compatible = "mediatek,mt7986-apmixedsys"; + reg = <0 0x1001E000 0 0x1000>; + #clock-cells = <1>; + }; + + pio: pinctrl@1001f000 { + compatible = "mediatek,mt7986a-pinctrl"; + reg = <0 0x1001f000 0 0x1000>, + <0 0x11c30000 0 0x1000>, + <0 0x11c40000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11e30000 0 0x1000>, + <0 0x11f00000 0 0x1000>, + <0 0x11f10000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt", + "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 100>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + }; + + sgmiisys0: syscon@10060000 { + compatible = "mediatek,mt7986-sgmiisys_0", + "syscon"; + reg = <0 0x10060000 0 0x1000>; + #clock-cells = <1>; + }; + + sgmiisys1: syscon@10070000 { + compatible = "mediatek,mt7986-sgmiisys_1", + "syscon"; + reg = <0 0x10070000 0 0x1000>; + #clock-cells = <1>; + }; + + trng: rng@1020f000 { + compatible = "mediatek,mt7986-rng", + "mediatek,mt7623-rng"; + reg = <0 0x1020f000 0 0x100>; + clocks = <&infracfg CLK_INFRA_TRNG_CK>; + clock-names = "rng"; + status = "disabled"; + }; + + crypto: crypto@10320000 { + compatible = "inside-secure,safexcel-eip97"; + reg = <0 0x10320000 0 0x40000>; + interrupts = , + , + , + ; + interrupt-names = "ring0", "ring1", "ring2", "ring3"; + clocks = <&infracfg CLK_INFRA_EIP97_CK>; + clock-names = "infra_eip97_ck"; + assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>; + assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>; + status = "disabled"; + }; + + pwm: pwm@10048000 { + compatible = "mediatek,mt7986-pwm"; + reg = <0 0x10048000 0 0x1000>; + #clock-cells = <1>; + #pwm-cells = <2>; + interrupts = ; + clocks = <&topckgen CLK_TOP_PWM_SEL>, + <&infracfg CLK_INFRA_PWM_STA>, + <&infracfg CLK_INFRA_PWM1_CK>, + <&infracfg CLK_INFRA_PWM2_CK>; + clock-names = "top", "main", "pwm1", "pwm2"; + status = "disabled"; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt7986-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_UART0_SEL>, + <&infracfg CLK_INFRA_UART0_CK>; + clock-names = "baud", "bus"; + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_UART0_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, + <&topckgen CLK_TOP_UART_SEL>; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt7986-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x400>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_UART1_SEL>, + <&infracfg CLK_INFRA_UART1_CK>; + clock-names = "baud", "bus"; + assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt7986-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x400>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_UART2_SEL>, + <&infracfg CLK_INFRA_UART2_CK>; + clock-names = "baud", "bus"; + assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>; + status = "disabled"; + }; + + i2c0: i2c@11008000 { + compatible = "mediatek,mt7986-i2c"; + reg = <0 0x11008000 0 0x90>, + <0 0x10217080 0 0x80>; + interrupts = ; + clock-div = <5>; + clocks = <&infracfg CLK_INFRA_I2C0_CK>, + <&infracfg CLK_INFRA_AP_DMA_CK>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@1100a000 { + compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100a000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MPLL_D2>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI0_CK>, + <&infracfg CLK_INFRA_SPI0_HCK_CK>; + clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; + status = "disabled"; + }; + + spi1: spi@1100b000 { + compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100b000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MPLL_D2>, + <&topckgen CLK_TOP_SPIM_MST_SEL>, + <&infracfg CLK_INFRA_SPI1_CK>, + <&infracfg CLK_INFRA_SPI1_HCK_CK>; + clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; + status = "disabled"; + }; + + auxadc: adc@1100d000 { + compatible = "mediatek,mt7986-auxadc"; + reg = <0 0x1100d000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_ADC_26M_CK>; + clock-names = "main"; + #io-channel-cells = <1>; + status = "disabled"; + }; + + ssusb: usb@11200000 { + compatible = "mediatek,mt7986-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x2e00>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>, + <&infracfg CLK_INFRA_IUSB_CK>, + <&infracfg CLK_INFRA_IUSB_133_CK>, + <&infracfg CLK_INFRA_IUSB_66M_CK>, + <&topckgen CLK_TOP_U2U3_XHCI_SEL>; + clock-names = "sys_ck", + "ref_ck", + "mcu_ck", + "dma_ck", + "xhci_ck"; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>, + <&u2port1 PHY_TYPE_USB2>; + status = "disabled"; + }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt7986-mmc"; + reg = <0 0x11230000 0 0x1000>, + <0 0x11c20000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>, + <&infracfg CLK_INFRA_MSDC_HCK_CK>, + <&infracfg CLK_INFRA_MSDC_CK>, + <&infracfg CLK_INFRA_MSDC_133M_CK>, + <&infracfg CLK_INFRA_MSDC_66M_CK>; + clock-names = "source", "hclk", "source_cg", "bus_clk", + "sys_cg"; + status = "disabled"; + }; + + thermal: thermal@1100c800 { + #thermal-sensor-cells = <1>; + compatible = "mediatek,mt7986-thermal"; + reg = <0 0x1100c800 0 0x800>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_THERM_CK>, + <&infracfg CLK_INFRA_ADC_26M_CK>, + <&infracfg CLK_INFRA_ADC_FRC_CK>; + clock-names = "therm", "auxadc", "adc_32k"; + mediatek,auxadc = <&auxadc>; + mediatek,apmixedsys = <&apmixedsys>; + nvmem-cells = <&thermal_calibration>; + nvmem-cell-names = "calibration-data"; + }; + + pcie: pcie@11280000 { + compatible = "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x00 0x11280000 0x00 0x4000>; + reg-names = "pcie-mac"; + interrupts = ; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0x00 0x20000000 0x00 + 0x20000000 0x00 0x10000000>; + clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, + <&infracfg CLK_INFRA_IPCIE_CK>, + <&infracfg CLK_INFRA_IPCIER_CK>, + <&infracfg CLK_INFRA_IPCIEB_CK>; + clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; + status = "disabled"; + + phys = <&pcie_port PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + pcie_intc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + pcie_phy: t-phy@11c00000 { + compatible = "mediatek,mt7986-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + pcie_port: pcie-phy@11c00000 { + reg = <0 0x11c00000 0 0x20000>; + clocks = <&clk40m>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + + efuse: efuse@11d00000 { + compatible = "mediatek,mt7986-efuse", "mediatek,efuse"; + reg = <0 0x11d00000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + thermal_calibration: calib@274 { + reg = <0x274 0xc>; + }; + }; + + usb_phy: t-phy@11e10000 { + compatible = "mediatek,mt7986-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11e10000 0x1700>; + status = "disabled"; + + u2port0: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>, + <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>; + clock-names = "ref", "da_ref"; + #phy-cells = <1>; + }; + + u3port0: usb-phy@700 { + reg = <0x700 0x900>; + clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>; + clock-names = "ref"; + #phy-cells = <1>; + }; + + u2port1: usb-phy@1000 { + reg = <0x1000 0x700>; + clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>, + <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>; + clock-names = "ref", "da_ref"; + #phy-cells = <1>; + }; + }; + + ethsys: syscon@15000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mediatek,mt7986-ethsys", + "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + wed0: wed@15010000 { + compatible = "mediatek,mt7986-wed", + "syscon"; + reg = <0 0x15010000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, + <&wo_data>, <&wo_boot>; + memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", + "wo-data", "wo-boot"; + mediatek,wo-ccif = <&wo_ccif0>; + }; + + wed1: wed@15011000 { + compatible = "mediatek,mt7986-wed", + "syscon"; + reg = <0 0x15011000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>, + <&wo_data>, <&wo_boot>; + memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", + "wo-data", "wo-boot"; + mediatek,wo-ccif = <&wo_ccif1>; + }; + + wo_ccif0: syscon@151a5000 { + compatible = "mediatek,mt7986-wo-ccif", "syscon"; + reg = <0 0x151a5000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + wo_ccif1: syscon@151ad000 { + compatible = "mediatek,mt7986-wo-ccif", "syscon"; + reg = <0 0x151ad000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + eth: ethernet@15100000 { + compatible = "mediatek,mt7986-eth"; + reg = <0 0x15100000 0 0x80000>; + interrupts = , + , + , + ; + clocks = <ðsys CLK_ETH_FE_EN>, + <ðsys CLK_ETH_GP2_EN>, + <ðsys CLK_ETH_GP1_EN>, + <ðsys CLK_ETH_WOCPU1_EN>, + <ðsys CLK_ETH_WOCPU0_EN>, + <&sgmiisys0 CLK_SGMII0_TX250M_EN>, + <&sgmiisys0 CLK_SGMII0_RX250M_EN>, + <&sgmiisys0 CLK_SGMII0_CDR_REF>, + <&sgmiisys0 CLK_SGMII0_CDR_FB>, + <&sgmiisys1 CLK_SGMII1_TX250M_EN>, + <&sgmiisys1 CLK_SGMII1_RX250M_EN>, + <&sgmiisys1 CLK_SGMII1_CDR_REF>, + <&sgmiisys1 CLK_SGMII1_CDR_FB>, + <&topckgen CLK_TOP_NETSYS_SEL>, + <&topckgen CLK_TOP_NETSYS_500M_SEL>; + clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0", + "sgmii_tx250m", "sgmii_rx250m", + "sgmii_cdr_ref", "sgmii_cdr_fb", + "sgmii2_tx250m", "sgmii2_rx250m", + "sgmii2_cdr_ref", "sgmii2_cdr_fb", + "netsys0", "netsys1"; + assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, + <&topckgen CLK_TOP_SGM_325M_SEL>; + assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, + <&apmixedsys CLK_APMIXED_SGMPLL>; + mediatek,ethsys = <ðsys>; + mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; + mediatek,wed-pcie = <&wed_pcie>; + mediatek,wed = <&wed0>, <&wed1>; + #reset-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + wifi: wifi@18000000 { + compatible = "mediatek,mt7986-wmac"; + resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; + reset-names = "consys"; + clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>, + <&topckgen CLK_TOP_AP2CNN_HOST_SEL>; + clock-names = "mcu", "ap2conn"; + reg = <0 0x18000000 0 0x1000000>, + <0 0x10003000 0 0x1000>, + <0 0x11d10000 0 0x1000>; + interrupts = , + , + , + ; + memory-region = <&wmcpu_emi>; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + thermal-sensors = <&thermal 0>; + + trips { + cpu_trip_active_high: active-high { + temperature = <115000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_low: active-low { + temperature = <85000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_passive: passive { + temperature = <40000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + }; + }; +}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts new file mode 100644 index 00000000000..83d51916717 --- /dev/null +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +#include "mt7986b.dtsi" + +/ { + model = "MediaTek MT7986b RFB"; + compatible = "mediatek,mt7986b-rfb"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0 0x40000000 0 0x40000000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&ssusb { + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; + +&wifi { + status = "okay"; + pinctrl-names = "default", "dbdc"; + pinctrl-0 = <&wf_2g_5g_pins>; + pinctrl-1 = <&wf_dbdc_pins>; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + phy5: phy@5 { + compatible = "ethernet-phy-id67c9.de0a"; + reg = <5>; + reset-gpios = <&pio 6 1>; + reset-deassert-us = <20000>; + phy-mode = "2500base-x"; + }; + + phy6: phy@6 { + compatible = "ethernet-phy-id67c9.de0a"; + reg = <6>; + phy-mode = "2500base-x"; + }; + + switch@0 { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 5 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan0"; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan3"; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; + }; +}; + +&crypto { + status = "okay"; +}; + +&pio { + wf_2g_5g_pins: wf_2g_5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + wf_dbdc_pins: wf_dbdc-pins { + mux { + function = "wifi"; + groups = "wf_dbdc"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; +}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986b.dtsi b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986b.dtsi new file mode 100644 index 00000000000..db5189664c2 --- /dev/null +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986b.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih + */ + +#include "mt7986a.dtsi" +/ { + compatible = "mediatek,mt7986b"; +}; + +&pio { + compatible = "mediatek,mt7986b-pinctrl"; + gpio-ranges = <&pio 0 0 41>, <&pio 66 66 35>; +}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts new file mode 100644 index 00000000000..98dbf8d6913 --- /dev/null +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +#include "mt7988a-rfb-spim-nand.dtsi" +#include + +/ { + model = "MediaTek MT7988A DSA 10G SPIM-NAND RFB"; + compatible = "mediatek,mt7988a-dsa-10g-spim-snand", + "mediatek,mt7988a-rfb-snand", + "mediatek,mt7988"; + + chosen { + bootargs = "console=ttyS0,115200n1 loglevel=8 \ + earlycon=uart8250,mmio32,0x11000000 \ + pci=pcie_bus_perf"; + }; + + memory { + reg = <0 0x40000000 0 0x40000000>; + }; +}; + +ð { + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "internal"; + + fixed-link { + speed = <10000>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "internal"; + phy-connection-type = "internal"; + phy = <&phy15>; + }; + + gmac2: mac@2 { + compatible = "mediatek,eth-mac"; + reg = <2>; + phy-mode = "10gbase-kr"; + phy-connection-type = "10gbase-kr"; + phy = <&phy8>; + }; + + mdio0: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + /* external Aquantia AQR113C */ + phy0: ethernet-phy@0 { + reg = <0>; + compatible = "ethernet-phy-ieee802.3-c45"; + reset-gpios = <&pio 72 1>; + reset-assert-us = <100000>; + reset-deassert-us = <221000>; + }; + + /* external Aquantia AQR113C */ + phy8: ethernet-phy@8 { + reg = <8>; + compatible = "ethernet-phy-ieee802.3-c45"; + reset-gpios = <&pio 71 1>; + reset-assert-us = <100000>; + reset-deassert-us = <221000>; + }; + + /* external Maxlinear GPY211C */ + phy5: ethernet-phy@5 { + reg = <5>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "2500base-x"; + }; + + /* external Maxlinear GPY211C */ + phy13: ethernet-phy@13 { + reg = <13>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "2500base-x"; + }; + + /* internal 2.5G PHY */ + phy15: ethernet-phy@15 { + reg = <15>; + pinctrl-names = "i2p5gbe-led"; + pinctrl-0 = <&i2p5gbe_led0_pins>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "internal"; + }; + }; +}; + +&switch { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan0"; + phy-mode = "internal"; + phy-handle = <&gsw_phy0>; + }; + + port@1 { + reg = <1>; + label = "lan1"; + phy-mode = "internal"; + phy-handle = <&gsw_phy1>; + }; + + port@2 { + reg = <2>; + label = "lan2"; + phy-mode = "internal"; + phy-handle = <&gsw_phy2>; + }; + + port@3 { + reg = <3>; + label = "lan3"; + phy-mode = "internal"; + phy-handle = <&gsw_phy3>; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "internal"; + + fixed-link { + speed = <10000>; + full-duplex; + pause; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + gsw_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id03a2.9481"; + reg = <0>; + phy-mode = "internal"; + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe0_led0_pins>; + nvmem-cells = <&phy_calibration_p0>; + nvmem-cell-names = "phy-cal-data"; + }; + + gsw_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id03a2.9481"; + reg = <1>; + phy-mode = "internal"; + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe1_led0_pins>; + nvmem-cells = <&phy_calibration_p1>; + nvmem-cell-names = "phy-cal-data"; + }; + + gsw_phy2: ethernet-phy@2 { + compatible = "ethernet-phy-id03a2.9481"; + reg = <2>; + phy-mode = "internal"; + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe2_led0_pins>; + nvmem-cells = <&phy_calibration_p2>; + nvmem-cell-names = "phy-cal-data"; + }; + + gsw_phy3: ethernet-phy@3 { + compatible = "ethernet-phy-id03a2.9481"; + reg = <3>; + phy-mode = "internal"; + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe3_led0_pins>; + nvmem-cells = <&phy_calibration_p3>; + nvmem-cell-names = "phy-cal-data"; + }; + }; +}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtsi b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtsi new file mode 100644 index 00000000000..e4c05712509 --- /dev/null +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtsi @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +#include "mt7988a-rfb.dtsi" + +&pio { + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + status = "okay"; + + spi_nand: spi_nand@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-tx-buswidth = <4>; + spi-rx-buswidth = <4>; + }; + +}; + +&spi_nand { + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <64>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "BL2"; + reg = <0x00000 0x0100000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env"; + reg = <0x0100000 0x0080000>; + }; + + factory: partition@180000 { + label = "Factory"; + reg = <0x180000 0x0400000>; + }; + + partition@580000 { + label = "FIP"; + reg = <0x580000 0x0200000>; + }; + + partition@780000 { + label = "ubi"; + reg = <0x780000 0x7080000>; + }; + }; +}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dtsi b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dtsi new file mode 100644 index 00000000000..423b3860c6c --- /dev/null +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dtsi @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +#include "mt7988a.dtsi" +#include + +&cpu0 { + proc-supply = <&rt5190_buck3>; +}; + +&cpu1 { + proc-supply = <&rt5190_buck3>; +}; + +&cpu2 { + proc-supply = <&rt5190_buck3>; +}; + +&cpu3 { + proc-supply = <&rt5190_buck3>; +}; + +&cci { + proc-supply = <&rt5190_buck3>; +}; + +ð { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + + rt5190a_64: rt5190a@64 { + compatible = "richtek,rt5190a"; + reg = <0x64>; + /*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/ + vin2-supply = <&rt5190_buck1>; + vin3-supply = <&rt5190_buck1>; + vin4-supply = <&rt5190_buck1>; + + regulators { + rt5190_buck1: buck1 { + regulator-name = "rt5190a-buck1"; + regulator-min-microvolt = <5090000>; + regulator-max-microvolt = <5090000>; + regulator-allowed-modes = + ; + regulator-boot-on; + regulator-always-on; + }; + buck2 { + regulator-name = "vcore"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + rt5190_buck3: buck3 { + regulator-name = "vproc"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + }; + buck4 { + regulator-name = "rt5190a-buck4"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-allowed-modes = + ; + regulator-boot-on; + regulator-always-on; + }; + ldo { + regulator-name = "rt5190a-ldo"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>; + status = "okay"; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins>; + status = "okay"; +}; + +&pcie2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_pins>; + status = "disabled"; +}; + +&pcie3 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_pins>; + status = "okay"; +}; + +&ssusb0 { + status = "okay"; +}; + +&ssusb1 { + status = "okay"; +}; + +&tphy { + status = "okay"; +}; + +&pio { + pcie0_pins: pcie0-pins { + mux { + function = "pcie"; + groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", + "pcie_wake_n0_0"; + }; + }; + + pcie1_pins: pcie1-pins { + mux { + function = "pcie"; + groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", + "pcie_wake_n1_0"; + }; + }; + + pcie2_pins: pcie2-pins { + mux { + function = "pcie"; + groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", + "pcie_wake_n2_0"; + }; + }; + + pcie3_pins: pcie3-pins { + mux { + function = "pcie"; + groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", + "pcie_wake_n3_0"; + }; + }; +}; + +&spi0 { + status = "disabled"; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&xphy { + status = "okay"; +}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi new file mode 100644 index 00000000000..13ad39500d1 --- /dev/null +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -0,0 +1,853 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 MediaTek Inc. + * Author: Sam.Shih + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + compatible = "mediatek,mt7988"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + clk40m: oscillator@0 { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + #clock-cells = <0>; + clock-output-names = "clkxtal"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + enable-method = "psci"; + reg = <0x0>; + clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, + <&topckgen CLK_TOP_XTAL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + mediatek,cci = <&cci>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + enable-method = "psci"; + reg = <0x1>; + clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, + <&topckgen CLK_TOP_XTAL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + mediatek,cci = <&cci>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + enable-method = "psci"; + reg = <0x2>; + clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, + <&topckgen CLK_TOP_XTAL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + mediatek,cci = <&cci>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + enable-method = "psci"; + reg = <0x3>; + clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, + <&topckgen CLK_TOP_XTAL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + mediatek,cci = <&cci>; + }; + + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + opp00 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <850000>; + }; + opp01 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <850000>; + }; + opp02 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <850000>; + }; + opp03 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <900000>; + }; + }; + }; + + cci: cci { + compatible = "mediatek,mt7988-cci", + "mediatek,mt8183-cci"; + clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>, + <&topckgen CLK_TOP_XTAL>; + clock-names = "cci", "intermediate"; + operating-points-v2 = <&cci_opp>; + }; + + cci_opp: opp_table_cci { + compatible = "operating-points-v2"; + opp-shared; + opp00 { + opp-hz = /bits/ 64 <480000000>; + opp-microvolt = <850000>; + }; + opp01 { + opp-hz = /bits/ 64 <660000000>; + opp-microvolt = <850000>; + }; + opp02 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <850000>; + }; + opp03 { + opp-hz = /bits/ 64 <1080000000>; + opp-microvolt = <900000>; + }; + }; + + pmu { + compatible = "arm,cortex-a73-pmu"; + interrupt-parent = <&gic>; + interrupt = ; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@43000000 { + reg = <0 0x43000000 0 0x30000>; + no-map; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x40000>, /* GICD */ + <0 0x0c080000 0 0x200000>, /* GICR */ + <0 0x0c400000 0 0x2000>, /* GICC */ + <0 0x0c410000 0 0x1000>, /* GICH */ + <0 0x0c420000 0 0x2000>; /* GICV */ + + interrupts = ; + }; + + phyfw: phy-firmware@f000000 { + compatible = "mediatek,2p5gphy-fw"; + reg = <0 0x0f000000 0 0x8000>, + <0 0x0f100000 0 0x20000>, + <0 0x0f0f0000 0 0x200>; + }; + + infracfg: infracfg@10001000 { + compatible = "mediatek,mt7988-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + topckgen: topckgen@1001b000 { + compatible = "mediatek,mt7988-topckgen", "syscon"; + reg = <0 0x1001b000 0 0x1000>; + #clock-cells = <1>; + }; + + watchdog: watchdog@1001c000 { + compatible = "mediatek,mt7988-wdt", + "mediatek,mt6589-wdt", + "syscon"; + reg = <0 0x1001c000 0 0x1000>; + interrupts = ; + #reset-cells = <1>; + }; + + apmixedsys: apmixedsys@1001e000 { + compatible = "mediatek,mt7988-apmixedsys"; + reg = <0 0x1001e000 0 0x1000>; + #clock-cells = <1>; + }; + + pio: pinctrl@1001f000 { + compatible = "mediatek,mt7988-pinctrl"; + reg = <0 0x1001f000 0 0x1000>, + <0 0x11c10000 0 0x1000>, + <0 0x11d00000 0 0x1000>, + <0 0x11d20000 0 0x1000>, + <0 0x11e00000 0 0x1000>, + <0 0x11f00000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio_base", "iocfg_tr_base", + "iocfg_br_base", "iocfg_rb_base", + "iocfg_lb_base", "iocfg_tl_base", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 83>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + + mdio0_pins: mdio0-pins { + mux { + function = "eth"; + groups = "mdc_mdio0"; + }; + + conf { + groups = "mdc_mdio0"; + drive-strength = ; + }; + }; + + i2c0_pins: i2c0-pins-g0 { + mux { + function = "i2c"; + groups = "i2c0_1"; + }; + }; + + i2c1_pins: i2c1-pins-g0 { + mux { + function = "i2c"; + groups = "i2c1_0"; + }; + }; + + i2c2_pins: i2c2-pins-g0 { + mux { + function = "i2c"; + groups = "i2c2_1"; + }; + }; + + gbe0_led0_pins: gbe0-pins { + mux { + function = "led"; + groups = "gbe0_led0"; + }; + }; + + gbe1_led0_pins: gbe1-pins { + mux { + function = "led"; + groups = "gbe1_led0"; + }; + }; + + gbe2_led0_pins: gbe2-pins { + mux { + function = "led"; + groups = "gbe2_led0"; + }; + }; + + gbe3_led0_pins: gbe3-pins { + mux { + function = "led"; + groups = "gbe3_led0"; + }; + }; + + i2p5gbe_led0_pins: 2p5gbe-pins { + mux { + function = "led"; + groups = "2p5gbe_led0"; + }; + }; + }; + + boottrap: boottrap@1001f6f0 { + compatible = "mediatek,boottrap"; + reg = <0 0x1001f6f0 0 0x4>; + }; + + sgmiisys0: syscon@10060000 { + compatible = "mediatek,mt7988-sgmiisys", + "mediatek,mt7988-sgmiisys_0", + "syscon"; + reg = <0 0x10060000 0 0x1000>; + #clock-cells = <1>; + }; + + sgmiisys1: syscon@10070000 { + compatible = "mediatek,mt7988-sgmiisys", + "mediatek,mt7988-sgmiisys_1", + "syscon"; + reg = <0 0x10070000 0 0x1000>; + #clock-cells = <1>; + }; + + usxgmiisys0: usxgmiisys@10080000 { + compatible = "mediatek,mt7988-usxgmiisys", + "mediatek,mt7988-usxgmiisys_0", + "syscon"; + reg = <0 0x10080000 0 0x1000>; + #clock-cells = <1>; + }; + + usxgmiisys1: usxgmiisys@10081000 { + compatible = "mediatek,mt7988-usxgmiisys", + "mediatek,mt7988-usxgmiisys_1", + "syscon"; + reg = <0 0x10081000 0 0x1000>; + #clock-cells = <1>; + }; + + xfi_pextp0: xfi_pextp@11f20000 { + compatible = "mediatek,mt7988-xfi_pextp", + "mediatek,mt7988-xfi_pextp_0", + "syscon"; + reg = <0 0x11f20000 0 0x10000>; + #clock-cells = <1>; + }; + + xfi_pextp1: xfi_pextp@11f30000 { + compatible = "mediatek,mt7988-xfi_pextp", + "mediatek,mt7988-xfi_pextp_1", + "syscon"; + reg = <0 0x11f30000 0 0x10000>; + #clock-cells = <1>; + }; + + xfi_pll: xfi_pll@11f40000 { + compatible = "mediatek,mt7988-xfi_pll", "syscon"; + reg = <0 0x11f40000 0 0x1000>; + #clock-cells = <1>; + }; + + mcusys: mcusys@100e0000 { + compatible = "mediatek,mt7988-mcusys", "syscon"; + reg = <0 0x100e0000 0 0x1000>; + #clock-cells = <1>; + }; + + uart0: serial@11000000 { + compatible = "mediatek,mt7986-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11000000 0 0x100>; + interrupts = ; + /* + * 8250-mtk driver don't control "baud" clock since commit + * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks + * still need to be passed to the driver to prevent probe fail + */ + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_52M_UART0_CK>; + clock-names = "baud", "bus"; + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_MUX_UART0_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, + <&topckgen CLK_TOP_UART_SEL>; + status = "disabled"; + }; + + i2c0: i2c@11003000 { + compatible = "mediatek,mt7988-i2c", + "mediatek,mt7981-i2c"; + reg = <0 0x11003000 0 0x1000>, + <0 0x10217080 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_INFRA_I2C_BCK>, + <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@11004000 { + compatible = "mediatek,mt7988-i2c", + "mediatek,mt7981-i2c"; + reg = <0 0x11004000 0 0x1000>, + <0 0x10217100 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_INFRA_I2C_BCK>, + <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@11005000 { + compatible = "mediatek,mt7988-i2c", + "mediatek,mt7981-i2c"; + reg = <0 0x11005000 0 0x1000>, + <0 0x10217180 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_INFRA_I2C_BCK>, + <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@11007000 { + compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm"; + reg = <0 0x11007000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MPLL_D2>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_104M_SPI0>, + <&infracfg CLK_INFRA_66M_SPI0_HCK>; + clock-names = "parent-clk", "sel-clk", "spi-clk", + "spi-hclk"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + pcie2: pcie@11280000 { + compatible = "mediatek,mt7988-pcie", + "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0 0x11280000 0 0x2000>; + reg-names = "pcie-mac"; + linux,pci-domain = <3>; + interrupts = ; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0x00 0x20000000 0x00 + 0x20000000 0x00 0x00200000>, + <0x82000000 0x00 0x20200000 0x00 + 0x20200000 0x00 0x07e00000>; + clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>, + <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>, + <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>, + <&infracfg CLK_INFRA_133M_PCIE_CK_P2>; + clock-names = "pl_250m", "tl_26m", "peri_26m", + "top_133m"; + status = "disabled"; + + phys = <&xphyu3port0 PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc2 0>, + <0 0 0 2 &pcie_intc2 1>, + <0 0 0 3 &pcie_intc2 2>, + <0 0 0 4 &pcie_intc2 3>; + pcie_intc2: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + pcie3: pcie@11290000 { + compatible = "mediatek,mt7988-pcie", + "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0 0x11290000 0 0x2000>; + reg-names = "pcie-mac"; + linux,pci-domain = <2>; + interrupts = ; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0x00 0x28000000 0x00 + 0x28000000 0x00 0x00200000>, + <0x82000000 0x00 0x28200000 0x00 + 0x28200000 0x00 0x07e00000>; + clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>, + <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>, + <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>, + <&infracfg CLK_INFRA_133M_PCIE_CK_P3>; + clock-names = "pl_250m", "tl_26m", "peri_26m", + "top_133m"; + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc3 0>, + <0 0 0 2 &pcie_intc3 1>, + <0 0 0 3 &pcie_intc3 2>, + <0 0 0 4 &pcie_intc3 3>; + pcie_intc3: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + pcie0: pcie@11300000 { + compatible = "mediatek,mt7988-pcie", + "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0 0x11300000 0 0x2000>; + reg-names = "pcie-mac"; + linux,pci-domain = <0>; + interrupts = ; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0x00 0x30000000 0x00 + 0x30000000 0x00 0x00200000>, + <0x82000000 0x00 0x30200000 0x00 + 0x30200000 0x00 0x07e00000>; + clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>, + <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>, + <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>, + <&infracfg CLK_INFRA_133M_PCIE_CK_P0>; + clock-names = "pl_250m", "tl_26m", "peri_26m", + "top_133m"; + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + pcie_intc0: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + pcie1: pcie@11310000 { + compatible = "mediatek,mt7988-pcie", + "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0 0x11310000 0 0x2000>; + reg-names = "pcie-mac"; + linux,pci-domain = <1>; + interrupts = ; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0x00 0x38000000 0x00 + 0x38000000 0x00 0x00200000>, + <0x82000000 0x00 0x38200000 0x00 + 0x38200000 0x00 0x07e00000>; + clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>, + <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>, + <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>, + <&infracfg CLK_INFRA_133M_PCIE_CK_P1>; + clock-names = "pl_250m", "tl_26m", "peri_26m", + "top_133m"; + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + pcie_intc1: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + ssusb0: usb@11190000 { + compatible = "mediatek,mt7988-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11190000 0 0x2e00>, + <0 0x11193e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&xphyu2port0 PHY_TYPE_USB2>, + <&xphyu3port0 PHY_TYPE_USB3>; + clocks = <&infracfg CLK_INFRA_USB_SYS>, + <&infracfg CLK_INFRA_USB_XHCI>, + <&infracfg CLK_INFRA_USB_REF>, + <&infracfg CLK_INFRA_66M_USB_HCK>, + <&infracfg CLK_INFRA_133M_USB_HCK>; + clock-names = "sys_ck", + "xhci_ck", + "ref_ck", + "mcu_ck", + "dma_ck"; + #address-cells = <2>; + #size-cells = <2>; + mediatek,p0_speed_fixup; + status = "disabled"; + }; + + ssusb1: usb@11200000 { + compatible = "mediatek,mt7988-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x2e00>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&tphyu2port0 PHY_TYPE_USB2>, + <&tphyu3port0 PHY_TYPE_USB3>; + clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>, + <&infracfg CLK_INFRA_USB_XHCI_CK_P1>, + <&infracfg CLK_INFRA_USB_CK_P1>, + <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>, + <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>; + clock-names = "sys_ck", + "xhci_ck", + "ref_ck", + "mcu_ck", + "dma_ck"; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + }; + + tphy: tphy@11c50000 { + compatible = "mediatek,mt7988", + "mediatek,generic-tphy-v2"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + tphyu2port0: usb-phy@11c50000 { + reg = <0 0x11c50000 0 0x700>; + clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>; + clock-names = "ref"; + #phy-cells = <1>; + }; + tphyu3port0: usb-phy@11c50700 { + reg = <0 0x11c50700 0 0x900>; + clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>; + clock-names = "ref"; + #phy-cells = <1>; + mediatek,usb3-pll-ssc-delta; + mediatek,usb3-pll-ssc-delta1; + }; + }; + + topmisc: topmisc@11d10000 { + compatible = "mediatek,mt7988-topmisc", "syscon", + "mediatek,mt7988-power-controller"; + reg = <0 0x11d10000 0 0x10000>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + xphy: xphy@11e10000 { + compatible = "mediatek,mt7988", + "mediatek,xsphy"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + xphyu2port0: usb-phy@11e10000 { + reg = <0 0x11e10000 0 0x400>; + clocks = <&infracfg CLK_INFRA_USB_UTMI>; + clock-names = "ref"; + #phy-cells = <1>; + }; + + xphyu3port0: usb-phy@11e13000 { + reg = <0 0x11e13400 0 0x500>; + clocks = <&infracfg CLK_INFRA_USB_PIPE>; + clock-names = "ref"; + #phy-cells = <1>; + mediatek,syscon-type = <&topmisc 0x218 0>; + }; + }; + + efuse: efuse@11f50000 { + compatible = "mediatek,efuse"; + reg = <0 0x11f50000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + lvts_calibration: calib@918 { + reg = <0x918 0x28>; + }; + phy_calibration_p0: calib@940 { + reg = <0x940 0x10>; + }; + phy_calibration_p1: calib@954 { + reg = <0x954 0x10>; + }; + phy_calibration_p2: calib@968 { + reg = <0x968 0x10>; + }; + phy_calibration_p3: calib@97c { + reg = <0x97c 0x10>; + }; + cpufreq_calibration: calib@278 { + reg = <0x278 0x1>; + }; + }; + + ethsys: syscon@15000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mediatek,mt7988-ethsys", "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + switch: switch@15020000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mediatek,mt7988-switch"; + reg = <0 0x15020000 0 0x8000>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + resets = <ðrst 0>; + }; + + ethwarp: syscon@15031000 { + compatible = "mediatek,mt7988-ethwarp", "syscon", "simple-mfd"; + reg = <0 0x15031000 0 0x1000>; + #clock-cells = <1>; + + ethrst: reset-controller { + compatible = "ti,syscon-reset"; + #reset-cells = <1>; + ti,reset-bits = < + 0x8 9 0x8 9 0 0 (ASSERT_SET | DEASSERT_CLEAR | STATUS_NONE) + >; + }; + }; + + eth: ethernet@15100000 { + compatible = "mediatek,mt7988-eth"; + reg = <0 0x15100000 0 0x80000>, + <0 0x15400000 0 0x380000>; + interrupts = , + , + , + ; + clocks = <ðsys CLK_ETHDMA_XGP1_EN>, + <ðsys CLK_ETHDMA_XGP2_EN>, + <ðsys CLK_ETHDMA_XGP3_EN>, + <ðsys CLK_ETHDMA_FE_EN>, + <ðsys CLK_ETHDMA_GP2_EN>, + <ðsys CLK_ETHDMA_GP1_EN>, + <ðsys CLK_ETHDMA_GP3_EN>, + <ðsys CLK_ETHDMA_ESW_EN>, + <ðsys CLK_ETHDMA_CRYPT0_EN>, + <&sgmiisys0 CLK_SGM0_TX_EN>, + <&sgmiisys0 CLK_SGM0_RX_EN>, + <&sgmiisys1 CLK_SGM1_TX_EN>, + <&sgmiisys1 CLK_SGM1_RX_EN>, + <ðwarp CLK_ETHWARP_WOCPU2_EN>, + <ðwarp CLK_ETHWARP_WOCPU1_EN>, + <ðwarp CLK_ETHWARP_WOCPU0_EN>, + <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>, + <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>, + <&topckgen CLK_TOP_SGM_0_SEL>, + <&topckgen CLK_TOP_SGM_1_SEL>, + <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>, + <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>, + <&topckgen CLK_TOP_ETH_GMII_SEL>, + <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>, + <&topckgen CLK_TOP_ETH_SYS_200M_SEL>, + <&topckgen CLK_TOP_ETH_SYS_SEL>, + <&topckgen CLK_TOP_ETH_XGMII_SEL>, + <&topckgen CLK_TOP_ETH_MII_SEL>, + <&topckgen CLK_TOP_NETSYS_SEL>, + <&topckgen CLK_TOP_NETSYS_500M_SEL>, + <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>, + <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>, + <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>, + <&topckgen CLK_TOP_NETSYS_WARP_SEL>; + clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1", + "gp3", "esw", "crypto", "sgmii_tx250m", + "sgmii_rx250m", "sgmii2_tx250m", "sgmii2_rx250m", + "ethwarp_wocpu2", "ethwarp_wocpu1", + "ethwarp_wocpu0", "top_usxgmii0_sel", + "top_usxgmii1_sel", "top_sgm0_sel", + "top_sgm1_sel", "top_xfi_phy0_xtal_sel", + "top_xfi_phy1_xtal_sel", "top_eth_gmii_sel", + "top_eth_refck_50m_sel", "top_eth_sys_200m_sel", + "top_eth_sys_sel", "top_eth_xgmii_sel", + "top_eth_mii_sel", "top_netsys_sel", + "top_netsys_500m_sel", "top_netsys_pao_2x_sel", + "top_netsys_sync_250m_sel", + "top_netsys_ppefb_250m_sel", + "top_netsys_warp_sel"; + assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, + <&topckgen CLK_TOP_NETSYS_GSW_SEL>, + <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>, + <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>, + <&topckgen CLK_TOP_SGM_0_SEL>, + <&topckgen CLK_TOP_SGM_1_SEL>; + assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, + <&topckgen CLK_TOP_NET1PLL_D4>, + <&topckgen CLK_TOP_NET1PLL_D8_D4>, + <&topckgen CLK_TOP_NET1PLL_D8_D4>, + <&apmixedsys CLK_APMIXED_SGMPLL>, + <&apmixedsys CLK_APMIXED_SGMPLL>; + mediatek,ethsys = <ðsys>; + mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; + mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>; + mediatek,xfi_pextp = <&xfi_pextp0>, <&xfi_pextp1>; + mediatek,xfi_pll = <&xfi_pll>; + mediatek,infracfg = <&topmisc>; + mediatek,toprgu = <&watchdog>; + #reset-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; +}; diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7981-apmixed.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7981-apmixed.c new file mode 100644 index 00000000000..1647021de88 --- /dev/null +++ b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7981-apmixed.c @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Sam Shih + * Author: Wenzhen Yu + * Author: Jianhui Zhao + * Author: Daniel Golle + */ + +#include +#include +#include +#include +#include +#include "clk-mtk.h" +#include "clk-gate.h" +#include "clk-mux.h" + +#include +#include + +#define MT7981_PLL_FMAX (2500UL * MHZ) +#define CON0_MT7981_RST_BAR BIT(27) + +#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ + _div_table, _parent_name) \ + { \ + .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \ + .en_mask = _en_mask, .flags = _flags, \ + .rst_bar_mask = CON0_MT7981_RST_BAR, .fmax = MT7981_PLL_FMAX, \ + .pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \ + .tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg, \ + .pcw_shift = _pcw_shift, .div_table = _div_table, \ + .parent_name = _parent_name, \ + } + +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ + _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) \ + PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL, \ + "clkxtal") + +static const struct mtk_pll_data plls[] = { + PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, PLL_AO, + 32, 0x0200, 4, 0, 0x0204, 0), + PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32, + 0x0210, 4, 0, 0x0214, 0), + PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32, + 0x0220, 4, 0, 0x0224, 0), + PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023C, 0x00000001, 0, 32, + 0x0230, 4, 0, 0x0234, 0), + PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024C, 0x00000001, 0, 32, + 0x0240, 4, 0, 0x0244, 0), + PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025C, 0x00000001, 0, 32, + 0x0250, 4, 0, 0x0254, 0), + PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32, + 0x0260, 4, 0, 0x0264, 0), + PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32, + 0x0278, 4, 0, 0x027C, 0), +}; + +static const struct of_device_id of_match_clk_mt7981_apmixed[] = { + { .compatible = "mediatek,mt7981-apmixedsys", }, + {} +}; + +static int clk_mt7981_apmixed_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + int r; + + clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls)); + if (!clk_data) + return -ENOMEM; + + mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + + clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) { + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); + goto free_apmixed_data; + } + return r; + +free_apmixed_data: + mtk_free_clk_data(clk_data); + return r; +} + +static struct platform_driver clk_mt7981_apmixed_drv = { + .probe = clk_mt7981_apmixed_probe, + .driver = { + .name = "clk-mt7981-apmixed", + .of_match_table = of_match_clk_mt7981_apmixed, + }, +}; +builtin_platform_driver(clk_mt7981_apmixed_drv); diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7981-eth.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7981-eth.c new file mode 100644 index 00000000000..4aba657aa6f --- /dev/null +++ b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7981-eth.c @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Sam Shih + * Author: Wenzhen Yu + * Author: Jianhui Zhao + * Author: Daniel Golle + */ + +#include +#include +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +static const struct mtk_gate_regs sgmii0_cg_regs = { + .set_ofs = 0xE4, + .clr_ofs = 0xE4, + .sta_ofs = 0xE4, +}; + +#define GATE_SGMII0(_id, _name, _parent, _shift) { \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &sgmii0_cg_regs, \ + .shift = _shift, \ + .ops = &mtk_clk_gate_ops_no_setclr_inv, \ + } + +static const struct mtk_gate sgmii0_clks[] __initconst = { + GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "usb_tx250m", 2), + GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "usb_eq_rx250m", 3), + GATE_SGMII0(CLK_SGM0_CK0_EN, "sgm0_ck0_en", "usb_ln0", 4), + GATE_SGMII0(CLK_SGM0_CDR_CK0_EN, "sgm0_cdr_ck0_en", "usb_cdr", 5), +}; + +static const struct mtk_gate_regs sgmii1_cg_regs = { + .set_ofs = 0xE4, + .clr_ofs = 0xE4, + .sta_ofs = 0xE4, +}; + +#define GATE_SGMII1(_id, _name, _parent, _shift) { \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &sgmii1_cg_regs, \ + .shift = _shift, \ + .ops = &mtk_clk_gate_ops_no_setclr_inv, \ + } + +static const struct mtk_gate sgmii1_clks[] __initconst = { + GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "usb_tx250m", 2), + GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "usb_eq_rx250m", 3), + GATE_SGMII1(CLK_SGM1_CK1_EN, "sgm1_ck1_en", "usb_ln0", 4), + GATE_SGMII1(CLK_SGM1_CDR_CK1_EN, "sgm1_cdr_ck1_en", "usb_cdr", 5), +}; + +static const struct mtk_gate_regs eth_cg_regs = { + .set_ofs = 0x30, + .clr_ofs = 0x30, + .sta_ofs = 0x30, +}; + +#define GATE_ETH(_id, _name, _parent, _shift) { \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = ð_cg_regs, \ + .shift = _shift, \ + .ops = &mtk_clk_gate_ops_no_setclr_inv, \ + } + +static const struct mtk_gate eth_clks[] __initconst = { + GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x", 6), + GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m", 7), + GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m", 8), + GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_wed_mcu", 15), +}; + +static void __init mtk_sgmiisys_0_init(struct device_node *node) +{ + struct clk_onecell_data *clk_data; + int r; + + clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks)); + + mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks), + clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); +} +CLK_OF_DECLARE(mtk_sgmiisys_0, "mediatek,mt7981-sgmiisys_0", + mtk_sgmiisys_0_init); + +static void __init mtk_sgmiisys_1_init(struct device_node *node) +{ + struct clk_onecell_data *clk_data; + int r; + + clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks)); + + mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks), + clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + + if (r) + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); +} +CLK_OF_DECLARE(mtk_sgmiisys_1, "mediatek,mt7981-sgmiisys_1", + mtk_sgmiisys_1_init); + +static void __init mtk_ethsys_init(struct device_node *node) +{ + struct clk_onecell_data *clk_data; + int r; + + clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks)); + + mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + + if (r) + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); +} +CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt7981-ethsys", mtk_ethsys_init); diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7981-infracfg.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7981-infracfg.c new file mode 100644 index 00000000000..8416829e358 --- /dev/null +++ b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7981-infracfg.c @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Sam Shih + * Author: Wenzhen Yu + * Author: Jianhui Zhao + * Author: Daniel Golle + */ + +#include +#include +#include +#include +#include +#include "clk-mtk.h" +#include "clk-gate.h" +#include "clk-mux.h" + +#include +#include + +static DEFINE_SPINLOCK(mt7981_clk_lock); + +static const struct mtk_fixed_factor infra_divs[] = { + FACTOR(CLK_INFRA_66M_MCK, "infra_66m_mck", "sysaxi_sel", 1, 2), +}; + +static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel", + "uart_sel" }; + +static const char *const infra_spi0_parents[] __initconst = { "i2c_sel", + "spi_sel" }; + +static const char *const infra_spi1_parents[] __initconst = { "i2c_sel", + "spim_mst_sel" }; + +static const char *const infra_pwm1_parents[] __initconst = { "pwm_sel" }; + +static const char *const infra_pwm_bsel_parents[] __initconst = { + "cb_rtc_32p7k", "csw_f26m_sel", "infra_66m_mck", "pwm_sel" +}; + +static const char *const infra_pcie_parents[] __initconst = { + "cb_rtc_32p7k", "csw_f26m_sel", "cb_cksq_40m", "pextp_tl_ck_sel" +}; + +static const struct mtk_mux infra_muxes[] = { + /* MODULE_CLK_SEL_0 */ + MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel", + infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1, + -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel", + infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1, + -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel", + infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1, + -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel", + infra_spi0_parents, 0x0018, 0x0010, 0x0014, 4, 1, + -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel", + infra_spi1_parents, 0x0018, 0x0010, 0x0014, 5, 1, + -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI2_SEL, "infra_spi2_sel", + infra_spi0_parents, 0x0018, 0x0010, 0x0014, 6, 1, + -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel", + infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 9, 1, + -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel", + infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 11, 1, + -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM3_SEL, "infra_pwm3_sel", + infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 15, 1, + -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel", + infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13, + 2, -1, -1, -1), + /* MODULE_CLK_SEL_1 */ + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel", + infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2, + -1, -1, -1), +}; + +static const struct mtk_gate_regs infra0_cg_regs = { + .set_ofs = 0x40, + .clr_ofs = 0x44, + .sta_ofs = 0x48, +}; + +static const struct mtk_gate_regs infra1_cg_regs = { + .set_ofs = 0x50, + .clr_ofs = 0x54, + .sta_ofs = 0x58, +}; + +static const struct mtk_gate_regs infra2_cg_regs = { + .set_ofs = 0x60, + .clr_ofs = 0x64, + .sta_ofs = 0x68, +}; + +#define GATE_INFRA0(_id, _name, _parent, _shift) \ + { \ + .id = _id, .name = _name, .parent_name = _parent, \ + .regs = &infra0_cg_regs, .shift = _shift, \ + .ops = &mtk_clk_gate_ops_setclr, \ + } + +#define GATE_INFRA1(_id, _name, _parent, _shift) \ + { \ + .id = _id, .name = _name, .parent_name = _parent, \ + .regs = &infra1_cg_regs, .shift = _shift, \ + .ops = &mtk_clk_gate_ops_setclr, \ + } + +#define GATE_INFRA2(_id, _name, _parent, _shift) \ + { \ + .id = _id, .name = _name, .parent_name = _parent, \ + .regs = &infra2_cg_regs, .shift = _shift, \ + .ops = &mtk_clk_gate_ops_setclr, \ + } + +static const struct mtk_gate infra_clks[] = { + /* INFRA0 */ + GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_66m_mck", 0), + GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_66m_mck", 1), + GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2), + GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3), + GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4), + GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi", 6), + + GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi", 8), + GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9), + GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l", 10), + GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys", 11), + GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner", 13), + GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel", + 14), + GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_66m_mck", 15), + GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_66m_mck", 16), + GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_66m_mck", 24), + GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25), + GATE_INFRA0(CLK_INFRA_PWM3_CK, "infra_pwm3", "infra_pwm3_sel", 27), + /* INFRA1 */ + GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0), + GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_bck", 1), + GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2), + GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3), + GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4), + GATE_INFRA1(CLK_INFRA_SPI2_CK, "infra_spi2", "infra_spi2_sel", 6), + GATE_INFRA1(CLK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", "infra_66m_mck", 7), + GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x", 8), + GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_bck", 9), + GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_66m_mck", 10), + GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11), + GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12), + GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_66m_mck", + 13), + GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_66m_mck", + 14), + GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "cb_rtc_32k", 15), + GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_400m", 16), + GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_208m", 17), + GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi", 18), + GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "sysaxi", 19), + GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20), + GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m", 21), + GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x", 23), + GATE_INFRA1(CLK_INFRA_I2C_MCK_CK, "infra_i2c_mck", "sysaxi", 25), + GATE_INFRA1(CLK_INFRA_I2C_PCK_CK, "infra_i2c_pck", "infra_66m_mck", 26), + /* INFRA2 */ + GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi", 0), + GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "sysaxi", 1), + GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys", 2), + GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_ref", 3), + GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl", 12), + GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "cb_cksq_40m", + 13), + GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m", 14), + GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi", 15), +}; + +static int clk_mt7981_infracfg_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + int r; + void __iomem *base; + int nr = ARRAY_SIZE(infra_divs) + ARRAY_SIZE(infra_muxes) + + ARRAY_SIZE(infra_clks); + + base = of_iomap(node, 0); + if (!base) { + pr_err("%s(): ioremap failed\n", __func__); + return -ENOMEM; + } + + clk_data = mtk_alloc_clk_data(nr); + + if (!clk_data) + return -ENOMEM; + + mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data); + mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node, + &mt7981_clk_lock, clk_data); + mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), + clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) { + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); + goto free_infracfg_data; + } + return r; + +free_infracfg_data: + mtk_free_clk_data(clk_data); + return r; +} + +static const struct of_device_id of_match_clk_mt7981_infracfg[] = { + { .compatible = "mediatek,mt7981-infracfg", }, + {} +}; + +static struct platform_driver clk_mt7981_infracfg_drv = { + .probe = clk_mt7981_infracfg_probe, + .driver = { + .name = "clk-mt7981-infracfg", + .of_match_table = of_match_clk_mt7981_infracfg, + }, +}; +builtin_platform_driver(clk_mt7981_infracfg_drv); diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7981-topckgen.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7981-topckgen.c new file mode 100644 index 00000000000..ce6dc186726 --- /dev/null +++ b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7981-topckgen.c @@ -0,0 +1,450 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Sam Shih + * Author: Wenzhen Yu + * Author: Jianhui Zhao + */ + + +#include +#include +#include +#include +#include +#include "clk-mtk.h" +#include "clk-gate.h" +#include "clk-mux.h" + +#include +#include + +static DEFINE_SPINLOCK(mt7981_clk_lock); + +static const struct mtk_fixed_factor top_divs[] = { + FACTOR(CLK_TOP_CB_CKSQ_40M, "cb_cksq_40m", "clkxtal", 1, 1), + FACTOR(CLK_TOP_CB_M_416M, "cb_m_416m", "mpll", 1, 1), + FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", "mpll", 1, 2), + FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", "mpll", 1, 3), + FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", "mpll", 1, 2), + FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", "mpll", 1, 4), + FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", "mpll", 1, 8), + FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", "mpll", 1, 16), + FACTOR(CLK_TOP_CB_MM_720M, "cb_mm_720m", "mmpll", 1, 1), + FACTOR(CLK_TOP_CB_MM_D2, "cb_mm_d2", "mmpll", 1, 2), + FACTOR(CLK_TOP_CB_MM_D3, "cb_mm_d3", "mmpll", 1, 3), + FACTOR(CLK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", "mmpll", 1, 15), + FACTOR(CLK_TOP_CB_MM_D4, "cb_mm_d4", "mmpll", 1, 4), + FACTOR(CLK_TOP_CB_MM_D6, "cb_mm_d6", "mmpll", 1, 6), + FACTOR(CLK_TOP_MM_D6_D2, "mm_d6_d2", "mmpll", 1, 12), + FACTOR(CLK_TOP_CB_MM_D8, "cb_mm_d8", "mmpll", 1, 8), + FACTOR(CLK_TOP_CB_APLL2_196M, "cb_apll2_196m", "apll2", 1, 1), + FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2), + FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4), + FACTOR(CLK_TOP_NET1_2500M, "net1_2500m", "net1pll", 1, 1), + FACTOR(CLK_TOP_CB_NET1_D4, "cb_net1_d4", "net1pll", 1, 4), + FACTOR(CLK_TOP_CB_NET1_D5, "cb_net1_d5", "net1pll", 1, 5), + FACTOR(CLK_TOP_NET1_D5_D2, "net1_d5_d2", "net1pll", 1, 10), + FACTOR(CLK_TOP_NET1_D5_D4, "net1_d5_d4", "net1pll", 1, 20), + FACTOR(CLK_TOP_CB_NET1_D8, "cb_net1_d8", "net1pll", 1, 8), + FACTOR(CLK_TOP_NET1_D8_D2, "net1_d8_d2", "net1pll", 1, 16), + FACTOR(CLK_TOP_NET1_D8_D4, "net1_d8_d4", "net1pll", 1, 32), + FACTOR(CLK_TOP_CB_NET2_800M, "cb_net2_800m", "net2pll", 1, 1), + FACTOR(CLK_TOP_CB_NET2_D2, "cb_net2_d2", "net2pll", 1, 2), + FACTOR(CLK_TOP_CB_NET2_D4, "cb_net2_d4", "net2pll", 1, 4), + FACTOR(CLK_TOP_NET2_D4_D2, "net2_d4_d2", "net2pll", 1, 8), + FACTOR(CLK_TOP_NET2_D4_D4, "net2_d4_d4", "net2pll", 1, 16), + FACTOR(CLK_TOP_CB_NET2_D6, "cb_net2_d6", "net2pll", 1, 6), + FACTOR(CLK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", "wedmcupll", 1, 1), + FACTOR(CLK_TOP_CB_SGM_325M, "cb_sgm_325m", "sgmpll", 1, 1), + FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", "cb_cksq_40m", 1, 2), + FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", "cb_cksq_40m", 1, 1250), + FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", "cb_cksq_40m", 1, 1220), + FACTOR(CLK_TOP_USB_TX250M, "usb_tx250m", "cb_cksq_40m", 1, 1), + FACTOR(CLK_TOP_FAUD, "faud", "aud_sel", 1, 1), + FACTOR(CLK_TOP_NFI1X, "nfi1x", "nfi1x_sel", 1, 1), + FACTOR(CLK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", "cb_cksq_40m", 1, 1), + FACTOR(CLK_TOP_USB_CDR_CK, "usb_cdr", "cb_cksq_40m", 1, 1), + FACTOR(CLK_TOP_USB_LN0_CK, "usb_ln0", "cb_cksq_40m", 1, 1), + FACTOR(CLK_TOP_SPINFI_BCK, "spinfi_bck", "spinfi_sel", 1, 1), + FACTOR(CLK_TOP_SPI, "spi", "spi_sel", 1, 1), + FACTOR(CLK_TOP_SPIM_MST, "spim_mst", "spim_mst_sel", 1, 1), + FACTOR(CLK_TOP_UART_BCK, "uart_bck", "uart_sel", 1, 1), + FACTOR(CLK_TOP_PWM_BCK, "pwm_bck", "pwm_sel", 1, 1), + FACTOR(CLK_TOP_I2C_BCK, "i2c_bck", "i2c_sel", 1, 1), + FACTOR(CLK_TOP_PEXTP_TL, "pextp_tl", "pextp_tl_ck_sel", 1, 1), + FACTOR(CLK_TOP_EMMC_208M, "emmc_208m", "emmc_208m_sel", 1, 1), + FACTOR(CLK_TOP_EMMC_400M, "emmc_400m", "emmc_400m_sel", 1, 1), + FACTOR(CLK_TOP_DRAMC_REF, "dramc_ref", "dramc_sel", 1, 1), + FACTOR(CLK_TOP_DRAMC_MD32, "dramc_md32", "dramc_md32_sel", 1, 1), + FACTOR(CLK_TOP_SYSAXI, "sysaxi", "sysaxi_sel", 1, 1), + FACTOR(CLK_TOP_SYSAPB, "sysapb", "sysapb_sel", 1, 1), + FACTOR(CLK_TOP_ARM_DB_MAIN, "arm_db_main", "arm_db_main_sel", 1, 1), + FACTOR(CLK_TOP_AP2CNN_HOST, "ap2cnn_host", "ap2cnn_host_sel", 1, 1), + FACTOR(CLK_TOP_NETSYS, "netsys", "netsys_sel", 1, 1), + FACTOR(CLK_TOP_NETSYS_500M, "netsys_500m", "netsys_500m_sel", 1, 1), + FACTOR(CLK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", "netsys_mcu_sel", 1, 1), + FACTOR(CLK_TOP_NETSYS_2X, "netsys_2x", "netsys_2x_sel", 1, 1), + FACTOR(CLK_TOP_SGM_325M, "sgm_325m", "sgm_325m_sel", 1, 1), + FACTOR(CLK_TOP_SGM_REG, "sgm_reg", "sgm_reg_sel", 1, 1), + FACTOR(CLK_TOP_F26M, "csw_f26m", "csw_f26m_sel", 1, 1), + FACTOR(CLK_TOP_EIP97B, "eip97b", "eip97b_sel", 1, 1), + FACTOR(CLK_TOP_USB3_PHY, "usb3_phy", "usb3_phy_sel", 1, 1), + FACTOR(CLK_TOP_AUD, "aud", "faud", 1, 1), + FACTOR(CLK_TOP_A1SYS, "a1sys", "a1sys_sel", 1, 1), + FACTOR(CLK_TOP_AUD_L, "aud_l", "aud_l_sel", 1, 1), + FACTOR(CLK_TOP_A_TUNER, "a_tuner", "a_tuner_sel", 1, 1), + FACTOR(CLK_TOP_U2U3_REF, "u2u3_ref", "u2u3_sel", 1, 1), + FACTOR(CLK_TOP_U2U3_SYS, "u2u3_sys", "u2u3_sys_sel", 1, 1), + FACTOR(CLK_TOP_U2U3_XHCI, "u2u3_xhci", "u2u3_xhci_sel", 1, 1), + FACTOR(CLK_TOP_USB_FRMCNT, "usb_frmcnt", "usb_frmcnt_sel", 1, 1), +}; + +static const char * const nfi1x_parents[] __initconst = { + "cb_cksq_40m", + "cb_mm_d4", + "net1_d8_d2", + "cb_net2_d6", + "cb_m_d4", + "cb_mm_d8", + "net1_d8_d4", + "cb_m_d8" +}; + +static const char * const spinfi_parents[] __initconst = { + "cksq_40m_d2", + "cb_cksq_40m", + "net1_d5_d4", + "cb_m_d4", + "cb_mm_d8", + "net1_d8_d4", + "mm_d6_d2", + "cb_m_d8" +}; + +static const char * const spi_parents[] __initconst = { + "cb_cksq_40m", + "cb_m_d2", + "cb_mm_d4", + "net1_d8_d2", + "cb_net2_d6", + "net1_d5_d4", + "cb_m_d4", + "net1_d8_d4" +}; + +static const char * const uart_parents[] __initconst = { + "cb_cksq_40m", + "cb_m_d8", + "m_d8_d2" +}; + +static const char * const pwm_parents[] __initconst = { + "cb_cksq_40m", + "net1_d8_d2", + "net1_d5_d4", + "cb_m_d4", + "m_d8_d2", + "cb_rtc_32k" +}; + +static const char * const i2c_parents[] __initconst = { + "cb_cksq_40m", + "net1_d5_d4", + "cb_m_d4", + "net1_d8_d4" +}; + +static const char * const pextp_tl_ck_parents[] __initconst = { + "cb_cksq_40m", + "net1_d5_d4", + "cb_m_d4", + "cb_rtc_32k" +}; + +static const char * const emmc_208m_parents[] __initconst = { + "cb_cksq_40m", + "cb_m_d2", + "cb_net2_d4", + "cb_apll2_196m", + "cb_mm_d4", + "net1_d8_d2", + "cb_mm_d6" +}; + +static const char * const emmc_400m_parents[] __initconst = { + "cb_cksq_40m", + "cb_net2_d2", + "cb_mm_d2", + "cb_net2_d2" +}; + +static const char * const csw_f26m_parents[] __initconst = { + "cksq_40m_d2", + "m_d8_d2" +}; + +static const char * const dramc_md32_parents[] __initconst = { + "cb_cksq_40m", + "cb_m_d2", + "cb_wedmcu_208m" +}; + +static const char * const sysaxi_parents[] __initconst = { + "cb_cksq_40m", + "net1_d8_d2" +}; + +static const char * const sysapb_parents[] __initconst = { + "cb_cksq_40m", + "m_d3_d2" +}; + +static const char * const arm_db_main_parents[] __initconst = { + "cb_cksq_40m", + "cb_net2_d6" +}; + +static const char * const ap2cnn_host_parents[] __initconst = { + "cb_cksq_40m", + "net1_d8_d4" +}; + +static const char * const netsys_parents[] __initconst = { + "cb_cksq_40m", + "cb_mm_d2" +}; + +static const char * const netsys_500m_parents[] __initconst = { + "cb_cksq_40m", + "cb_net1_d5" +}; + +static const char * const netsys_mcu_parents[] __initconst = { + "cb_cksq_40m", + "cb_mm_720m", + "cb_net1_d4", + "cb_net1_d5", + "cb_m_416m" +}; + +static const char * const netsys_2x_parents[] __initconst = { + "cb_cksq_40m", + "cb_net2_800m", + "cb_mm_720m" +}; + +static const char * const sgm_325m_parents[] __initconst = { + "cb_cksq_40m", + "cb_sgm_325m" +}; + +static const char * const sgm_reg_parents[] __initconst = { + "cb_cksq_40m", + "cb_net2_d4" +}; + +static const char * const eip97b_parents[] __initconst = { + "cb_cksq_40m", + "cb_net1_d5", + "cb_m_416m", + "cb_mm_d2", + "net1_d5_d2" +}; + +static const char * const aud_parents[] __initconst = { + "cb_cksq_40m", + "cb_apll2_196m" +}; + +static const char * const a1sys_parents[] __initconst = { + "cb_cksq_40m", + "apll2_d4" +}; + +static const char * const aud_l_parents[] __initconst = { + "cb_cksq_40m", + "cb_apll2_196m", + "m_d8_d2" +}; + +static const char * const a_tuner_parents[] __initconst = { + "cb_cksq_40m", + "apll2_d4", + "m_d8_d2" +}; + +static const char * const u2u3_parents[] __initconst = { + "cb_cksq_40m", + "m_d8_d2" +}; + +static const char * const u2u3_sys_parents[] __initconst = { + "cb_cksq_40m", + "net1_d5_d4" +}; + +static const char * const usb_frmcnt_parents[] __initconst = { + "cb_cksq_40m", + "cb_mm_d3_d5" +}; + +static const struct mtk_mux top_muxes[] = { + /* CLK_CFG_0 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, + 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, + 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, + 0x000, 0x004, 0x008, 16, 3, 23, 0x1C0, 2), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, + 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3), + /* CLK_CFG_1 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, + 0x010, 0x014, 0x018, 0, 2, 7, 0x1C0, 4), + MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, + 0x010, 0x014, 0x018, 8, 3, 15, 0x1C0, 5), + MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, + 0x010, 0x014, 0x018, 16, 2, 23, 0x1C0, 6), + MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", + pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 31, + 0x1C0, 7), + /* CLK_CFG_2 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel", + emmc_208m_parents, 0x020, 0x024, 0x028, 0, 3, 7, + 0x1C0, 8), + MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", + emmc_400m_parents, 0x020, 0x024, 0x028, 8, 2, 15, + 0x1C0, 9), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel", + csw_f26m_parents, 0x020, 0x024, 0x028, 16, 1, 23, + 0x1C0, 10, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", + csw_f26m_parents, 0x020, 0x024, 0x028, 24, 1, + 31, 0x1C0, 11, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), + /* CLK_CFG_3 */ + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", + dramc_md32_parents, 0x030, 0x034, 0x038, 0, 2, + 7, 0x1C0, 12, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", + sysaxi_parents, 0x030, 0x034, 0x038, 8, 1, 15, + 0x1C0, 13, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", + sysapb_parents, 0x030, 0x034, 0x038, 16, 1, + 23, 0x1C0, 14, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", + arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, 31, + 0x1C0, 15), + /* CLK_CFG_4 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", + ap2cnn_host_parents, 0x040, 0x044, 0x048, 0, 1, 7, + 0x1C0, 16), + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, + 0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17), + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", + netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1, 23, + 0x1C0, 18), + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", + netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31, + 0x1C0, 19), + /* CLK_CFG_5 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", + netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7, + 0x1C0, 20), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", + sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15, + 0x1C0, 21), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, + 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22), + MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents, + 0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23), + /* CLK_CFG_6 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel", + csw_f26m_parents, 0x060, 0x064, 0x068, 0, 1, + 7, 0x1C0, 24), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x060, + 0x064, 0x068, 8, 1, 15, 0x1C0, 25), + MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, + 0x060, 0x064, 0x068, 16, 1, 23, 0x1C0, 26), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, + 0x060, 0x064, 0x068, 24, 2, 31, 0x1C0, 27), + /* CLK_CFG_7 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", + a_tuner_parents, 0x070, 0x074, 0x078, 0, 2, 7, + 0x1C0, 28), + MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x070, + 0x074, 0x078, 8, 1, 15, 0x1C0, 29), + MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", + u2u3_sys_parents, 0x070, 0x074, 0x078, 16, 1, 23, + 0x1C0, 30), + MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", + u2u3_sys_parents, 0x070, 0x074, 0x078, 24, 1, 31, + 0x1C4, 0), + /* CLK_CFG_8 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", + usb_frmcnt_parents, 0x080, 0x084, 0x088, 0, 1, 7, + 0x1C4, 1), +}; + +static struct mtk_composite top_aud_divs[] = { + DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud", + 0x0420, 0, 0x0420, 8, 8), +}; + +static int clk_mt7981_topckgen_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + int r; + void __iomem *base; + int nr = ARRAY_SIZE(top_divs) + ARRAY_SIZE(top_muxes) + + ARRAY_SIZE(top_aud_divs); + + base = of_iomap(node, 0); + if (!base) { + pr_err("%s(): ioremap failed\n", __func__); + return -ENOMEM; + } + + clk_data = mtk_alloc_clk_data(nr); + if (!clk_data) + return -ENOMEM; + + mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); + mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node, + &mt7981_clk_lock, clk_data); + mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs), base, + &mt7981_clk_lock, clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + + if (r) { + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); + goto free_topckgen_data; + } + return r; + +free_topckgen_data: + mtk_free_clk_data(clk_data); + return r; +} + +static const struct of_device_id of_match_clk_mt7981_topckgen[] = { + { .compatible = "mediatek,mt7981-topckgen", }, + {} +}; + +static struct platform_driver clk_mt7981_topckgen_drv = { + .probe = clk_mt7981_topckgen_probe, + .driver = { + .name = "clk-mt7981-topckgen", + .of_match_table = of_match_clk_mt7981_topckgen, + }, +}; +builtin_platform_driver(clk_mt7981_topckgen_drv); diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7986-apmixed.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7986-apmixed.c new file mode 100644 index 00000000000..76c8ebdeae9 --- /dev/null +++ b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7986-apmixed.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-1.0 +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Sam Shih + * Author: Wenzhen Yu + */ + +#include +#include +#include +#include +#include +#include "clk-mtk.h" +#include "clk-gate.h" +#include "clk-mux.h" + +#include +#include + +#define MT7986_PLL_FMAX (2500UL * MHZ) +#define CON0_MT7986_RST_BAR BIT(27) + +#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ + _div_table, _parent_name) \ + { \ + .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \ + .en_mask = _en_mask, .flags = _flags, \ + .rst_bar_mask = CON0_MT7986_RST_BAR, .fmax = MT7986_PLL_FMAX, \ + .pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \ + .tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg, \ + .pcw_shift = _pcw_shift, .div_table = _div_table, \ + .parent_name = _parent_name, \ + } + +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ + _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) \ + PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL, \ + "clkxtal") + +static const struct mtk_pll_data plls[] = { + PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, 0, 32, + 0x0200, 4, 0, 0x0204, 0), + PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32, + 0x0210, 4, 0, 0x0214, 0), + PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32, + 0x0220, 4, 0, 0x0224, 0), + PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023c, 0x00000001, 0, 32, + 0x0230, 4, 0, 0x0234, 0), + PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024c, 0x00000001, 0, + 32, 0x0240, 4, 0, 0x0244, 0), + PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025c, 0x00000001, 0, 32, + 0x0250, 4, 0, 0x0254, 0), + PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32, 0x0260, + 4, 0, 0x0264, 0), + PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32, + 0x0278, 4, 0, 0x027c, 0), +}; + +static const struct of_device_id of_match_clk_mt7986_apmixed[] = { + { .compatible = "mediatek,mt7986-apmixedsys", }, + {} +}; + +static int clk_mt7986_apmixed_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + int r; + + clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls)); + if (!clk_data) + return -ENOMEM; + + mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + + clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) { + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); + goto free_apmixed_data; + } + return r; + +free_apmixed_data: + mtk_free_clk_data(clk_data); + return r; +} + +static struct platform_driver clk_mt7986_apmixed_drv = { + .probe = clk_mt7986_apmixed_probe, + .driver = { + .name = "clk-mt7986-apmixed", + .of_match_table = of_match_clk_mt7986_apmixed, + }, +}; +builtin_platform_driver(clk_mt7986_apmixed_drv); diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7986-eth.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7986-eth.c new file mode 100644 index 00000000000..ed2e7b20098 --- /dev/null +++ b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7986-eth.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Sam Shih + * Author: Wenzhen Yu + */ + +#include +#include +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +static const struct mtk_gate_regs sgmii0_cg_regs = { + .set_ofs = 0xe4, + .clr_ofs = 0xe4, + .sta_ofs = 0xe4, +}; + +#define GATE_SGMII0(_id, _name, _parent, _shift) \ + { \ + .id = _id, .name = _name, .parent_name = _parent, \ + .regs = &sgmii0_cg_regs, .shift = _shift, \ + .ops = &mtk_clk_gate_ops_no_setclr_inv, \ + } + +static const struct mtk_gate sgmii0_clks[] __initconst = { + GATE_SGMII0(CLK_SGMII0_TX250M_EN, "sgmii0_tx250m_en", "top_xtal", 2), + GATE_SGMII0(CLK_SGMII0_RX250M_EN, "sgmii0_rx250m_en", "top_xtal", 3), + GATE_SGMII0(CLK_SGMII0_CDR_REF, "sgmii0_cdr_ref", "top_xtal", 4), + GATE_SGMII0(CLK_SGMII0_CDR_FB, "sgmii0_cdr_fb", "top_xtal", 5), +}; + +static const struct mtk_gate_regs sgmii1_cg_regs = { + .set_ofs = 0xe4, + .clr_ofs = 0xe4, + .sta_ofs = 0xe4, +}; + +#define GATE_SGMII1(_id, _name, _parent, _shift) \ + { \ + .id = _id, .name = _name, .parent_name = _parent, \ + .regs = &sgmii1_cg_regs, .shift = _shift, \ + .ops = &mtk_clk_gate_ops_no_setclr_inv, \ + } + +static const struct mtk_gate sgmii1_clks[] __initconst = { + GATE_SGMII1(CLK_SGMII1_TX250M_EN, "sgmii1_tx250m_en", "top_xtal", 2), + GATE_SGMII1(CLK_SGMII1_RX250M_EN, "sgmii1_rx250m_en", "top_xtal", 3), + GATE_SGMII1(CLK_SGMII1_CDR_REF, "sgmii1_cdr_ref", "top_xtal", 4), + GATE_SGMII1(CLK_SGMII1_CDR_FB, "sgmii1_cdr_fb", "top_xtal", 5), +}; + +static const struct mtk_gate_regs eth_cg_regs = { + .set_ofs = 0x30, + .clr_ofs = 0x30, + .sta_ofs = 0x30, +}; + +#define GATE_ETH(_id, _name, _parent, _shift) \ + { \ + .id = _id, .name = _name, .parent_name = _parent, \ + .regs = ð_cg_regs, .shift = _shift, \ + .ops = &mtk_clk_gate_ops_no_setclr_inv, \ + } + +static const struct mtk_gate eth_clks[] __initconst = { + GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x_sel", 6), + GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m_sel", 7), + GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m_sel", 8), + GATE_ETH(CLK_ETH_WOCPU1_EN, "eth_wocpu1_en", "netsys_mcu_sel", 14), + GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_mcu_sel", 15), +}; + +static void __init mtk_sgmiisys_0_init(struct device_node *node) +{ + struct clk_onecell_data *clk_data; + int r; + + clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks)); + + mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks), + clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); +} +CLK_OF_DECLARE(mtk_sgmiisys_0, "mediatek,mt7986-sgmiisys_0", + mtk_sgmiisys_0_init); + +static void __init mtk_sgmiisys_1_init(struct device_node *node) +{ + struct clk_onecell_data *clk_data; + int r; + + clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks)); + + mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks), + clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + + if (r) + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); +} +CLK_OF_DECLARE(mtk_sgmiisys_1, "mediatek,mt7986-sgmiisys_1", + mtk_sgmiisys_1_init); + +static void __init mtk_ethsys_init(struct device_node *node) +{ + struct clk_onecell_data *clk_data; + int r; + + clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks)); + + mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + + if (r) + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); +} +CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt7986-ethsys", mtk_ethsys_init); diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7986-infracfg.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7986-infracfg.c new file mode 100644 index 00000000000..82279dfcf57 --- /dev/null +++ b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7986-infracfg.c @@ -0,0 +1,224 @@ +// SPDX-License-Identifier: GPL-1.0 +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Sam Shih + * Author: Wenzhen Yu + */ + +#include +#include +#include +#include +#include +#include "clk-mtk.h" +#include "clk-gate.h" +#include "clk-mux.h" + +#include +#include + +static DEFINE_SPINLOCK(mt7986_clk_lock); + +static const struct mtk_fixed_factor infra_divs[] = { + FACTOR(CLK_INFRA_SYSAXI_D2, "infra_sysaxi_d2", "sysaxi_sel", 1, 2), +}; + +static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel", + "uart_sel" }; + +static const char *const infra_spi_parents[] __initconst = { "i2c_sel", + "spi_sel" }; + +static const char *const infra_pwm_bsel_parents[] __initconst = { + "top_rtc_32p7k", "csw_f26m_sel", "infra_sysaxi_d2", "pwm_sel" +}; + +static const char *const infra_pcie_parents[] __initconst = { + "top_rtc_32p7k", "csw_f26m_sel", "top_xtal", "pextp_tl_ck_sel" +}; + +static const struct mtk_mux infra_muxes[] = { + /* MODULE_CLK_SEL_0 */ + MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel", + infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1, + -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel", + infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1, + -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel", + infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1, + -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel", + infra_spi_parents, 0x0018, 0x0010, 0x0014, 4, 1, + -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel", + infra_spi_parents, 0x0018, 0x0010, 0x0014, 5, 1, + -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel", + infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 9, + 2, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel", + infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 11, + 2, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel", + infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13, + 2, -1, -1, -1), + /* MODULE_CLK_SEL_1 */ + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel", + infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2, + -1, -1, -1), +}; + +static const struct mtk_gate_regs infra0_cg_regs = { + .set_ofs = 0x40, + .clr_ofs = 0x44, + .sta_ofs = 0x48, +}; + +static const struct mtk_gate_regs infra1_cg_regs = { + .set_ofs = 0x50, + .clr_ofs = 0x54, + .sta_ofs = 0x58, +}; + +static const struct mtk_gate_regs infra2_cg_regs = { + .set_ofs = 0x60, + .clr_ofs = 0x64, + .sta_ofs = 0x68, +}; + +#define GATE_INFRA0(_id, _name, _parent, _shift) \ + { \ + .id = _id, .name = _name, .parent_name = _parent, \ + .regs = &infra0_cg_regs, .shift = _shift, \ + .ops = &mtk_clk_gate_ops_setclr, \ + } + +#define GATE_INFRA1(_id, _name, _parent, _shift) \ + { \ + .id = _id, .name = _name, .parent_name = _parent, \ + .regs = &infra1_cg_regs, .shift = _shift, \ + .ops = &mtk_clk_gate_ops_setclr, \ + } + +#define GATE_INFRA2(_id, _name, _parent, _shift) \ + { \ + .id = _id, .name = _name, .parent_name = _parent, \ + .regs = &infra2_cg_regs, .shift = _shift, \ + .ops = &mtk_clk_gate_ops_setclr, \ + } + +static const struct mtk_gate infra_clks[] = { + /* INFRA0 */ + GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_sysaxi_d2", 0), + GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_sysaxi_d2", 1), + GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2), + GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3), + GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4), + GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi_sel", 6), + GATE_INFRA0(CLK_INFRA_EIP97_CK, "infra_eip97", "eip_b_sel", 7), + GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi_sel", 8), + GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9), + GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l_sel", 10), + GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys_sel", 11), + GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner_sel", 13), + GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel", + 14), + GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_sysaxi_d2", 15), + GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_sysaxi_d2", 16), + GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_sysaxi_d2", 24), + GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25), + GATE_INFRA0(CLK_INFRA_TRNG_CK, "infra_trng", "sysaxi_sel", 26), + /* INFRA1 */ + GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0), + GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_sel", 1), + GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2), + GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3), + GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4), + GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x_sel", 8), + GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_sel", 9), + GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_sysaxi_d2", + 10), + GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11), + GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12), + GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_sysaxi_d2", + 13), + GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_sysaxi_d2", + 14), + GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "top_rtc_32k", 15), + GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_416m_sel", 16), + GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_250m_sel", + 17), + GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi_sel", + 18), + GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "infra_sysaxi_d2", + 19), + GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20), + GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m_sel", 21), + GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x_sel", 23), + /* INFRA2 */ + GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi_sel", 0), + GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "infra_sysaxi_d2", + 1), + GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys_sel", 2), + GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_sel", 3), + GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl_ck_sel", 12), + GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "top_xtal", + 13), + GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m_sel", 14), + GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi_sel", 15), +}; + +static int clk_mt7986_infracfg_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + int r; + void __iomem *base; + int nr = ARRAY_SIZE(infra_divs) + ARRAY_SIZE(infra_muxes) + + ARRAY_SIZE(infra_clks); + + base = of_iomap(node, 0); + if (!base) { + pr_err("%s(): ioremap failed\n", __func__); + return -ENOMEM; + } + + clk_data = mtk_alloc_clk_data(nr); + + if (!clk_data) + return -ENOMEM; + + mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data); + mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node, + &mt7986_clk_lock, clk_data); + mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), + clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) { + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); + goto free_infracfg_data; + } + return r; + +free_infracfg_data: + mtk_free_clk_data(clk_data); + return r; + +} + +static const struct of_device_id of_match_clk_mt7986_infracfg[] = { + { .compatible = "mediatek,mt7986-infracfg", }, + {} +}; + +static struct platform_driver clk_mt7986_infracfg_drv = { + .probe = clk_mt7986_infracfg_probe, + .driver = { + .name = "clk-mt7986-infracfg", + .of_match_table = of_match_clk_mt7986_infracfg, + }, +}; +builtin_platform_driver(clk_mt7986_infracfg_drv); diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7986-topckgen.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7986-topckgen.c new file mode 100644 index 00000000000..8550e2be777 --- /dev/null +++ b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7986-topckgen.c @@ -0,0 +1,342 @@ +// SPDX-License-Identifier: GPL-1.0 +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Sam Shih + * Author: Wenzhen Yu + */ + +#include +#include +#include +#include +#include +#include "clk-mtk.h" +#include "clk-gate.h" +#include "clk-mux.h" + +#include +#include + +static DEFINE_SPINLOCK(mt7986_clk_lock); + +static const struct mtk_fixed_clk top_fixed_clks[] = { + FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000), + FIXED_CLK(CLK_TOP_JTAG, "top_jtag", "clkxtal", 50000000), +}; + +static const struct mtk_fixed_factor top_divs[] = { + /* XTAL */ + FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2), + FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250), + FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220), + /* MPLL */ + FACTOR(CLK_TOP_MPLL_D2, "top_mpll_d2", "mpll", 1, 2), + FACTOR(CLK_TOP_MPLL_D4, "top_mpll_d4", "mpll", 1, 4), + FACTOR(CLK_TOP_MPLL_D8, "top_mpll_d8", "mpll", 1, 8), + FACTOR(CLK_TOP_MPLL_D8_D2, "top_mpll_d8_d2", "mpll", 1, 16), + FACTOR(CLK_TOP_MPLL_D3_D2, "top_mpll_d3_d2", "mpll", 1, 6), + /* MMPLL */ + FACTOR(CLK_TOP_MMPLL_D2, "top_mmpll_d2", "mmpll", 1, 2), + FACTOR(CLK_TOP_MMPLL_D4, "top_mmpll_d4", "mmpll", 1, 4), + FACTOR(CLK_TOP_MMPLL_D8, "top_mmpll_d8", "mmpll", 1, 8), + FACTOR(CLK_TOP_MMPLL_D8_D2, "top_mmpll_d8_d2", "mmpll", 1, 16), + FACTOR(CLK_TOP_MMPLL_D3_D8, "top_mmpll_d3_d8", "mmpll", 1, 24), + FACTOR(CLK_TOP_MMPLL_U2PHY, "top_mmpll_u2phy", "mmpll", 1, 30), + /* APLL2 */ + FACTOR(CLK_TOP_APLL2_D4, "top_apll2_d4", "apll2", 1, 4), + /* NET1PLL */ + FACTOR(CLK_TOP_NET1PLL_D4, "top_net1pll_d4", "net1pll", 1, 4), + FACTOR(CLK_TOP_NET1PLL_D5, "top_net1pll_d5", "net1pll", 1, 5), + FACTOR(CLK_TOP_NET1PLL_D5_D2, "top_net1pll_d5_d2", "net1pll", 1, 10), + FACTOR(CLK_TOP_NET1PLL_D5_D4, "top_net1pll_d5_d4", "net1pll", 1, 20), + FACTOR(CLK_TOP_NET1PLL_D8_D2, "top_net1pll_d8_d2", "net1pll", 1, 16), + FACTOR(CLK_TOP_NET1PLL_D8_D4, "top_net1pll_d8_d4", "net1pll", 1, 32), + /* NET2PLL */ + FACTOR(CLK_TOP_NET2PLL_D4, "top_net2pll_d4", "net2pll", 1, 4), + FACTOR(CLK_TOP_NET2PLL_D4_D2, "top_net2pll_d4_d2", "net2pll", 1, 8), + FACTOR(CLK_TOP_NET2PLL_D3_D2, "top_net2pll_d3_d2", "net2pll", 1, 2), + /* WEDMCUPLL */ + FACTOR(CLK_TOP_WEDMCUPLL_D5_D2, "top_wedmcupll_d5_d2", "wedmcupll", 1, + 10), +}; + +static const char *const nfi1x_parents[] __initconst = { "top_xtal", + "top_mmpll_d8", + "top_net1pll_d8_d2", + "top_net2pll_d3_d2", + "top_mpll_d4", + "top_mmpll_d8_d2", + "top_wedmcupll_d5_d2", + "top_mpll_d8" }; + +static const char *const spinfi_parents[] __initconst = { + "top_xtal_d2", "top_xtal", "top_net1pll_d5_d4", + "top_mpll_d4", "top_mmpll_d8_d2", "top_wedmcupll_d5_d2", + "top_mmpll_d3_d8", "top_mpll_d8" +}; + +static const char *const spi_parents[] __initconst = { + "top_xtal", "top_mpll_d2", "top_mmpll_d8", + "top_net1pll_d8_d2", "top_net2pll_d3_d2", "top_net1pll_d5_d4", + "top_mpll_d4", "top_wedmcupll_d5_d2" +}; + +static const char *const uart_parents[] __initconst = { "top_xtal", + "top_mpll_d8", + "top_mpll_d8_d2" }; + +static const char *const pwm_parents[] __initconst = { + "top_xtal", "top_net1pll_d8_d2", "top_net1pll_d5_d4", "top_mpll_d4" +}; + +static const char *const i2c_parents[] __initconst = { + "top_xtal", "top_net1pll_d5_d4", "top_mpll_d4", "top_net1pll_d8_d4" +}; + +static const char *const pextp_tl_ck_parents[] __initconst = { + "top_xtal", "top_net1pll_d5_d4", "top_net2pll_d4_d2", "top_rtc_32k" +}; + +static const char *const emmc_250m_parents[] __initconst = { + "top_xtal", "top_net1pll_d5_d2" +}; + +static const char *const emmc_416m_parents[] __initconst = { "top_xtal", + "mpll" }; + +static const char *const f_26m_adc_parents[] __initconst = { "top_xtal", + "top_mpll_d8_d2" }; + +static const char *const dramc_md32_parents[] __initconst = { "top_xtal", + "top_mpll_d2" }; + +static const char *const sysaxi_parents[] __initconst = { "top_xtal", + "top_net1pll_d8_d2", + "top_net2pll_d4" }; + +static const char *const sysapb_parents[] __initconst = { "top_xtal", + "top_mpll_d3_d2", + "top_net2pll_d4_d2" }; + +static const char *const arm_db_main_parents[] __initconst = { + "top_xtal", "top_net2pll_d3_d2" +}; + +static const char *const arm_db_jtsel_parents[] __initconst = { "top_jtag", + "top_xtal" }; + +static const char *const netsys_parents[] __initconst = { "top_xtal", + "top_mmpll_d4" }; + +static const char *const netsys_500m_parents[] __initconst = { + "top_xtal", "top_net1pll_d5" +}; + +static const char *const netsys_mcu_parents[] __initconst = { + "top_xtal", "wedmcupll", "top_mmpll_d2", "top_net1pll_d4", + "top_net1pll_d5" +}; + +static const char *const netsys_2x_parents[] __initconst = { + "top_xtal", "net2pll", "wedmcupll", "top_mmpll_d2" +}; + +static const char *const sgm_325m_parents[] __initconst = { "top_xtal", + "sgmpll" }; + +static const char *const sgm_reg_parents[] __initconst = { + "top_xtal", "top_net1pll_d8_d4" +}; + +static const char *const a1sys_parents[] __initconst = { "top_xtal", + "top_apll2_d4" }; + +static const char *const conn_mcusys_parents[] __initconst = { "top_xtal", + "top_mmpll_d2" }; + +static const char *const eip_b_parents[] __initconst = { "top_xtal", + "net2pll" }; + +static const char *const aud_l_parents[] __initconst = { "top_xtal", "apll2", + "top_mpll_d8_d2" }; + +static const char *const a_tuner_parents[] __initconst = { "top_xtal", + "top_apll2_d4", + "top_mpll_d8_d2" }; + +static const char *const u2u3_sys_parents[] __initconst = { + "top_xtal", "top_net1pll_d5_d4" +}; + +static const char *const da_u2_refsel_parents[] __initconst = { + "top_xtal", "top_mmpll_u2phy" +}; + +static const struct mtk_mux top_muxes[] = { + /* CLK_CFG_0 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, + 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, + 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000, + 0x004, 0x008, 16, 3, 23, 0x1C0, 2), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, + 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3), + /* CLK_CFG_1 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010, + 0x014, 0x018, 0, 2, 7, 0x1C0, 4), + MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010, + 0x014, 0x018, 8, 2, 15, 0x1C0, 5), + MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010, + 0x014, 0x018, 16, 2, 23, 0x1C0, 6), + MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", + pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, + 31, 0x1C0, 7), + /* CLK_CFG_2 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", + emmc_250m_parents, 0x020, 0x024, 0x028, 0, 1, 7, + 0x1C0, 8), + MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_416M_SEL, "emmc_416m_sel", + emmc_416m_parents, 0x020, 0x024, 0x028, 8, 1, 15, + 0x1C0, 9), + MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel", + f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23, + 0x1C0, 10), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents, + 0x020, 0x024, 0x028, 24, 1, 31, 0x1C0, 11), + /* CLK_CFG_3 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", + dramc_md32_parents, 0x030, 0x034, 0x038, 0, 1, 7, + 0x1C0, 12), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, + 0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, + 0x030, 0x034, 0x038, 16, 2, 23, 0x1C0, 14), + MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", + arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, + 31, 0x1C0, 15), + /* CLK_CFG_4 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_JTSEL, "arm_db_jtsel", + arm_db_jtsel_parents, 0x040, 0x044, 0x048, 0, 1, 7, + 0x1C0, 16), + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, + 0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17), + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", + netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1, + 23, 0x1C0, 18), + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", + netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31, + 0x1C0, 19), + /* CLK_CFG_5 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", + netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7, + 0x1C0, 20), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", + sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15, + 0x1C0, 21), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", + sgm_reg_parents, 0x050, 0x054, 0x058, 16, 1, 23, + 0x1C0, 22), + MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, + 0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23), + /* CLK_CFG_6 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_CONN_MCUSYS_SEL, "conn_mcusys_sel", + conn_mcusys_parents, 0x060, 0x064, 0x068, 0, 1, 7, + 0x1C0, 24), + MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP_B_SEL, "eip_b_sel", eip_b_parents, + 0x060, 0x064, 0x068, 8, 1, 15, 0x1C0, 25), + MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_PHY_SEL, "pcie_phy_sel", + f_26m_adc_parents, 0x060, 0x064, 0x068, 16, 1, 23, + 0x1C0, 26), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel", + f_26m_adc_parents, 0x060, 0x064, 0x068, 24, 1, 31, + 0x1C0, 27), + /* CLK_CFG_7 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_F26M_SEL, "csw_f26m_sel", + f_26m_adc_parents, 0x070, 0x074, 0x078, 0, 1, 7, + 0x1C0, 28), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, + 0x070, 0x074, 0x078, 8, 2, 15, 0x1C0, 29), + MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", + a_tuner_parents, 0x070, 0x074, 0x078, 16, 2, 23, + 0x1C0, 30), + MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", f_26m_adc_parents, + 0x070, 0x074, 0x078, 24, 1, 31, 0x1C4, 0), + /* CLK_CFG_8 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", + u2u3_sys_parents, 0x080, 0x084, 0x088, 0, 1, 7, + 0x1C4, 1), + MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", + u2u3_sys_parents, 0x080, 0x084, 0x088, 8, 1, 15, + 0x1C4, 2), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_U2_REFSEL, "da_u2_refsel", + da_u2_refsel_parents, 0x080, 0x084, 0x088, 16, 1, + 23, 0x1C4, 3), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_U2_CK_1P_SEL, "da_u2_ck_1p_sel", + da_u2_refsel_parents, 0x080, 0x084, 0x088, 24, 1, + 31, 0x1C4, 4), + /* CLK_CFG_9 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", + sgm_reg_parents, 0x090, 0x094, 0x098, 0, 1, 7, + 0x1C4, 5), +}; + +static int clk_mt7986_topckgen_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + int r; + void __iomem *base; + int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) + + ARRAY_SIZE(top_muxes); + + base = of_iomap(node, 0); + if (!base) { + pr_err("%s(): ioremap failed\n", __func__); + return -ENOMEM; + } + + clk_data = mtk_alloc_clk_data(nr); + if (!clk_data) + return -ENOMEM; + + mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), + clk_data); + mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); + mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node, + &mt7986_clk_lock, clk_data); + + clk_prepare_enable(clk_data->clks[CLK_TOP_SYSAXI_SEL]); + clk_prepare_enable(clk_data->clks[CLK_TOP_SYSAPB_SEL]); + clk_prepare_enable(clk_data->clks[CLK_TOP_DRAMC_SEL]); + clk_prepare_enable(clk_data->clks[CLK_TOP_DRAMC_MD32_SEL]); + clk_prepare_enable(clk_data->clks[CLK_TOP_F26M_SEL]); + clk_prepare_enable(clk_data->clks[CLK_TOP_SGM_REG_SEL]); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + + if (r) { + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); + goto free_topckgen_data; + } + return r; + +free_topckgen_data: + mtk_free_clk_data(clk_data); + return r; +} + +static const struct of_device_id of_match_clk_mt7986_topckgen[] = { + { .compatible = "mediatek,mt7986-topckgen", }, + {} +}; + +static struct platform_driver clk_mt7986_topckgen_drv = { + .probe = clk_mt7986_topckgen_probe, + .driver = { + .name = "clk-mt7986-topckgen", + .of_match_table = of_match_clk_mt7986_topckgen, + }, +}; +builtin_platform_driver(clk_mt7986_topckgen_drv); diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-apmixed.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-apmixed.c new file mode 100644 index 00000000000..587b70767eb --- /dev/null +++ b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-apmixed.c @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 MediaTek Inc. + * Author: Sam Shih + * Author: Xiufeng Li + */ + +#include +#include +#include +#include +#include +#include "clk-mtk.h" +#include "clk-gate.h" +#include "clk-mux.h" +#include + +#define MT7988_PLL_FMAX (2500UL * MHZ) +#define MT7988_PCW_CHG_SHIFT 2 + +#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \ + _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ + _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, \ + _div_table) \ + { \ + .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \ + .en_mask = _en_mask, .flags = _flags, \ + .rst_bar_mask = BIT(_rst_bar_mask), .fmax = MT7988_PLL_FMAX, \ + .pcwbits = _pcwbits, .pd_reg = _pd_reg, \ + .pd_shift = _pd_shift, .tuner_reg = _tuner_reg, \ + .tuner_en_reg = _tuner_en_reg, .tuner_en_bit = _tuner_en_bit, \ + .pcw_reg = _pcw_reg, .pcw_shift = _pcw_shift, \ + .pcw_chg_reg = _pcw_chg_reg, \ + .pcw_chg_shift = MT7988_PCW_CHG_SHIFT, \ + .div_table = _div_table, .parent_name = "clkxtal", \ + } + +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \ + _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ + _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg) \ + PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \ + _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ + _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, NULL) + +static const struct mtk_pll_data plls[] = { + PLL(CLK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0, + 0, 32, 0x0104, 4, 0, 0, 0, 0x0108, 0, 0x0104), + PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR, + 23, 32, 0x0114, 4, 0, 0, 0, 0x0118, 0, 0x0114), + PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001, + HAVE_RST_BAR, 23, 32, 0x0124, 4, 0, 0, 0, 0x0128, 0, 0x0124), + PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32, + 0x0134, 4, 0x0704, 0x0700, 1, 0x0138, 0, 0x0134), + PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001, + HAVE_RST_BAR, 23, 32, 0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144), + PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0154, 0x0160, 0xff000001, + (HAVE_RST_BAR | PLL_AO), 23, 32, 0x0154, 4, 0, 0, 0, 0x0158, 0, + 0x0154), + PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0, + 0, 32, 0x0164, 4, 0, 0, 0, 0x0168, 0, 0x0164), + PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32, + 0x0174, 4, 0, 0, 0, 0x0178, 0, 0x0174), + PLL(CLK_APMIXED_ARM_B, "arm_b", 0x0204, 0x0210, 0xff000001, + (HAVE_RST_BAR | PLL_AO), 23, 32, 0x0204, 4, 0, 0, 0, 0x0208, 0, + 0x0204), + PLL(CLK_APMIXED_CCIPLL2_B, "ccipll2_b", 0x0214, 0x0220, 0xff000001, + HAVE_RST_BAR, 23, 32, 0x0214, 4, 0, 0, 0, 0x0218, 0, 0x0214), + PLL(CLK_APMIXED_USXGMIIPLL, "usxgmiipll", 0x0304, 0x0310, 0xff000001, + HAVE_RST_BAR, 23, 32, 0x0304, 4, 0, 0, 0, 0x0308, 0, 0x0304), + PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0314, 0x0320, 0x00000001, 0, 0, + 32, 0x0314, 4, 0, 0, 0, 0x0318, 0, 0x0314), +}; + +static const struct of_device_id of_match_clk_mt7988_apmixed[] = { + { + .compatible = "mediatek,mt7988-apmixedsys", + }, + {} +}; + +static int clk_mt7988_apmixed_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + int r; + + clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls)); + if (!clk_data) + return -ENOMEM; + + mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) { + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); + goto free_apmixed_data; + } + return r; + +free_apmixed_data: + mtk_free_clk_data(clk_data); + return r; +} + +static struct platform_driver clk_mt7988_apmixed_drv = { + .probe = clk_mt7988_apmixed_probe, + .driver = { + .name = "clk-mt7988-apmixed", + .of_match_table = of_match_clk_mt7988_apmixed, + }, +}; +builtin_platform_driver(clk_mt7988_apmixed_drv); diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-eth.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-eth.c new file mode 100644 index 00000000000..341d0f73fd3 --- /dev/null +++ b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-eth.c @@ -0,0 +1,299 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 MediaTek Inc. + * Author: Sam Shih + * Author: Xiufeng Li + */ + +#include +#include +#include +#include +#include +#include "clk-mtk.h" +#include "clk-gate.h" +#include + +static const struct mtk_gate_regs ethdma_cg_regs = { + .set_ofs = 0x30, + .clr_ofs = 0x30, + .sta_ofs = 0x30, +}; + +#define GATE_ETHDMA(_id, _name, _parent, _shift) \ + { \ + .id = _id, .name = _name, .parent_name = _parent, \ + .regs = ðdma_cg_regs, .shift = _shift, \ + .ops = &mtk_clk_gate_ops_no_setclr_inv, \ + } + +static const struct mtk_gate ethdma_clks[] = { + GATE_ETHDMA(CLK_ETHDMA_XGP1_EN, "ethdma_xgp1_en", "top_xtal", 0), + GATE_ETHDMA(CLK_ETHDMA_XGP2_EN, "ethdma_xgp2_en", "top_xtal", 1), + GATE_ETHDMA(CLK_ETHDMA_XGP3_EN, "ethdma_xgp3_en", "top_xtal", 2), + GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", "netsys_2x_sel", 6), + GATE_ETHDMA(CLK_ETHDMA_GP2_EN, "ethdma_gp2_en", "top_xtal", 7), + GATE_ETHDMA(CLK_ETHDMA_GP1_EN, "ethdma_gp1_en", "top_xtal", 8), + GATE_ETHDMA(CLK_ETHDMA_GP3_EN, "ethdma_gp3_en", "top_xtal", 10), + GATE_ETHDMA(CLK_ETHDMA_ESW_EN, "ethdma_esw_en", "netsys_gsw_sel", 16), + GATE_ETHDMA(CLK_ETHDMA_CRYPT0_EN, "ethdma_crypt0_en", "eip197_sel", + 29), +}; + +static int clk_mt7988_ethsys_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + int r; + void __iomem *base; + + base = of_iomap(node, 0); + if (!base) { + pr_err("%s(): ioremap failed\n", __func__); + return -ENOMEM; + } + + clk_data = mtk_alloc_clk_data(ARRAY_SIZE(ethdma_clks)); + + if (!clk_data) + return -ENOMEM; + + mtk_clk_register_gates(node, ethdma_clks, ARRAY_SIZE(ethdma_clks), + clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) { + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); + goto free_data; + } + return r; + +free_data: + mtk_free_clk_data(clk_data); + return r; +} + +static const struct mtk_gate_regs sgmii0_cg_regs = { + .set_ofs = 0xe4, + .clr_ofs = 0xe4, + .sta_ofs = 0xe4, +}; + +#define GATE_SGMII0(_id, _name, _parent, _shift) \ + { \ + .id = _id, .name = _name, .parent_name = _parent, \ + .regs = &sgmii0_cg_regs, .shift = _shift, \ + .ops = &mtk_clk_gate_ops_no_setclr_inv, \ + } + +static const struct mtk_gate sgmii0_clks[] = { + GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "top_xtal", 2), + GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "top_xtal", 3), +}; + +static int clk_mt7988_sgmii0_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + int r; + void __iomem *base; + + base = of_iomap(node, 0); + if (!base) { + pr_err("%s(): ioremap failed\n", __func__); + return -ENOMEM; + } + + clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks)); + + if (!clk_data) + return -ENOMEM; + + mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks), + clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) { + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); + goto free_data; + } + return r; + +free_data: + mtk_free_clk_data(clk_data); + return r; +} + +static const struct mtk_gate_regs sgmii1_cg_regs = { + .set_ofs = 0xe4, + .clr_ofs = 0xe4, + .sta_ofs = 0xe4, +}; + +#define GATE_SGMII1(_id, _name, _parent, _shift) \ + { \ + .id = _id, .name = _name, .parent_name = _parent, \ + .regs = &sgmii1_cg_regs, .shift = _shift, \ + .ops = &mtk_clk_gate_ops_no_setclr_inv, \ + } + +static const struct mtk_gate sgmii1_clks[] = { + GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "top_xtal", 2), + GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "top_xtal", 3), +}; + +static int clk_mt7988_sgmii1_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + int r; + void __iomem *base; + + base = of_iomap(node, 0); + if (!base) { + pr_err("%s(): ioremap failed\n", __func__); + return -ENOMEM; + } + + clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks)); + + if (!clk_data) + return -ENOMEM; + + mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks), + clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) { + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); + goto free_data; + } + return r; + +free_data: + mtk_free_clk_data(clk_data); + return r; +} + +static const struct mtk_gate_regs ethwarp_cg_regs = { + .set_ofs = 0x14, + .clr_ofs = 0x14, + .sta_ofs = 0x14, +}; + +#define GATE_ETHWARP(_id, _name, _parent, _shift) \ + { \ + .id = _id, .name = _name, .parent_name = _parent, \ + .regs = ðwarp_cg_regs, .shift = _shift, \ + .ops = &mtk_clk_gate_ops_no_setclr_inv, \ + } + +static const struct mtk_gate ethwarp_clks[] = { + GATE_ETHWARP(CLK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en", + "netsys_mcu_sel", 13), + GATE_ETHWARP(CLK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en", + "netsys_mcu_sel", 14), + GATE_ETHWARP(CLK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en", + "netsys_mcu_sel", 15), +}; + +static int clk_mt7988_ethwarp_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + int r; + void __iomem *base; + + base = of_iomap(node, 0); + if (!base) { + pr_err("%s(): ioremap failed\n", __func__); + return -ENOMEM; + } + + clk_data = mtk_alloc_clk_data(ARRAY_SIZE(ethwarp_clks)); + + if (!clk_data) + return -ENOMEM; + + mtk_clk_register_gates(node, ethwarp_clks, ARRAY_SIZE(ethwarp_clks), + clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) { + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); + goto free_data; + } + return r; + +free_data: + mtk_free_clk_data(clk_data); + return r; +} + +static const struct of_device_id of_match_clk_mt7988_ethsys[] = { + { + .compatible = "mediatek,mt7988-ethsys", + }, + {} +}; + +static struct platform_driver clk_mt7988_ethsys_drv = { + .probe = clk_mt7988_ethsys_probe, + .driver = { + .name = "clk-mt7988-ethsys", + .of_match_table = of_match_clk_mt7988_ethsys, + }, +}; +builtin_platform_driver(clk_mt7988_ethsys_drv); + +static const struct of_device_id of_match_clk_mt7988_sgmii0[] = { + { + .compatible = "mediatek,mt7988-sgmiisys_0", + }, + {} +}; + +static struct platform_driver clk_mt7988_sgmii0_drv = { + .probe = clk_mt7988_sgmii0_probe, + .driver = { + .name = "clk-mt7988-sgmiisys_0", + .of_match_table = of_match_clk_mt7988_sgmii0, + }, +}; +builtin_platform_driver(clk_mt7988_sgmii0_drv); + +static const struct of_device_id of_match_clk_mt7988_sgmii1[] = { + { + .compatible = "mediatek,mt7988-sgmiisys_1", + }, + {} +}; + +static struct platform_driver clk_mt7988_sgmii1_drv = { + .probe = clk_mt7988_sgmii1_probe, + .driver = { + .name = "clk-mt7988-sgmiisys_1", + .of_match_table = of_match_clk_mt7988_sgmii1, + }, +}; +builtin_platform_driver(clk_mt7988_sgmii1_drv); + +static const struct of_device_id of_match_clk_mt7988_ethwarp[] = { + { + .compatible = "mediatek,mt7988-ethwarp", + }, + {} +}; + +static struct platform_driver clk_mt7988_ethwarp_drv = { + .probe = clk_mt7988_ethwarp_probe, + .driver = { + .name = "clk-mt7988-ethwarp", + .of_match_table = of_match_clk_mt7988_ethwarp, + }, +}; +builtin_platform_driver(clk_mt7988_ethwarp_drv); \ No newline at end of file diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-infracfg.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-infracfg.c new file mode 100644 index 00000000000..77e25383b6e --- /dev/null +++ b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-infracfg.c @@ -0,0 +1,399 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 MediaTek Inc. + * Author: Sam Shih + * Author: Xiufeng Li + */ + +#include +#include +#include +#include +#include +#include "clk-mtk.h" +#include "clk-gate.h" +#include "clk-mux.h" +#include + +static DEFINE_SPINLOCK(mt7988_clk_lock); + +static const char *const infra_mux_uart0_parents[] __initconst = { + "csw_infra_f26m_sel", "uart_sel" +}; + +static const char *const infra_mux_uart1_parents[] __initconst = { + "csw_infra_f26m_sel", "uart_sel" +}; + +static const char *const infra_mux_uart2_parents[] __initconst = { + "csw_infra_f26m_sel", "uart_sel" +}; + +static const char *const infra_mux_spi0_parents[] __initconst = { "i2c_sel", + "spi_sel" }; + +static const char *const infra_mux_spi1_parents[] __initconst = { + "i2c_sel", "spim_mst_sel" +}; + +static const char *const infra_pwm_bck_parents[] __initconst = { + "top_rtc_32p7k", "csw_infra_f26m_sel", "sysaxi_sel", "pwm_sel" +}; + +static const char *const infra_pcie_gfmux_tl_ck_o_p0_parents[] __initconst = { + "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", + "pextp_tl_sel" +}; + +static const char *const infra_pcie_gfmux_tl_ck_o_p1_parents[] __initconst = { + "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", + "pextp_tl_p1_sel" +}; + +static const char *const infra_pcie_gfmux_tl_ck_o_p2_parents[] __initconst = { + "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", + "pextp_tl_p2_sel" +}; + +static const char *const infra_pcie_gfmux_tl_ck_o_p3_parents[] __initconst = { + "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", + "pextp_tl_p3_sel" +}; + +static const struct mtk_mux infra_muxes[] = { + /* MODULE_CLK_SEL_0 */ + MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel", + infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, + 0, 1, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel", + infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, + 1, 1, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel", + infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, + 2, 1, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", + infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 4, + 1, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", + infra_mux_spi1_parents, 0x0018, 0x0010, 0x0014, 5, + 1, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel", + infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 6, + 1, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel", + infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 14, + 2, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel", + infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 16, + 2, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel", + infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 18, + 2, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel", + infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 20, + 2, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel", + infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 22, + 2, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel", + infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 24, + 2, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel", + infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 26, + 2, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel", + infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 28, + 2, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel", + infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 30, + 2, -1, -1, -1), + /* MODULE_CLK_SEL_1 */ + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, + "infra_pcie_gfmux_tl_o_p0_sel", + infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028, + 0x0020, 0x0024, 0, 2, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, + "infra_pcie_gfmux_tl_o_p1_sel", + infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028, + 0x0020, 0x0024, 2, 2, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, + "infra_pcie_gfmux_tl_o_p2_sel", + infra_pcie_gfmux_tl_ck_o_p2_parents, 0x0028, + 0x0020, 0x0024, 4, 2, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, + "infra_pcie_gfmux_tl_o_p3_sel", + infra_pcie_gfmux_tl_ck_o_p3_parents, 0x0028, + 0x0020, 0x0024, 6, 2, -1, -1, -1), +}; + +static const struct mtk_gate_regs infra0_cg_regs = { + .set_ofs = 0x10, + .clr_ofs = 0x14, + .sta_ofs = 0x18, +}; + +static const struct mtk_gate_regs infra1_cg_regs = { + .set_ofs = 0x40, + .clr_ofs = 0x44, + .sta_ofs = 0x48, +}; + +static const struct mtk_gate_regs infra2_cg_regs = { + .set_ofs = 0x50, + .clr_ofs = 0x54, + .sta_ofs = 0x58, +}; + +static const struct mtk_gate_regs infra3_cg_regs = { + .set_ofs = 0x60, + .clr_ofs = 0x64, + .sta_ofs = 0x68, +}; + +#define GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, _flags) \ + { \ + .id = _id, .name = _name, .parent_name = _parent, \ + .regs = &infra0_cg_regs, .shift = _shift, \ + .ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \ + } + +#define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flags) \ + { \ + .id = _id, .name = _name, .parent_name = _parent, \ + .regs = &infra1_cg_regs, .shift = _shift, \ + .ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \ + } + +#define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flags) \ + { \ + .id = _id, .name = _name, .parent_name = _parent, \ + .regs = &infra2_cg_regs, .shift = _shift, \ + .ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \ + } + +#define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flags) \ + { \ + .id = _id, .name = _name, .parent_name = _parent, \ + .regs = &infra3_cg_regs, .shift = _shift, \ + .ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \ + } + +#define GATE_INFRA0(_id, _name, _parent, _shift) \ + GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, 0) + +#define GATE_INFRA1(_id, _name, _parent, _shift) \ + GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0) + +#define GATE_INFRA2(_id, _name, _parent, _shift) \ + GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, 0) + +#define GATE_INFRA3(_id, _name, _parent, _shift) \ + GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0) + +static const struct mtk_gate infra_clks[] = { + /* INFRA0 */ + GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P0, + "infra_pcie_peri_ck_26m_ck_p0", "csw_infra_f26m_sel", 7), + GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1, + "infra_pcie_peri_ck_26m_ck_p1", "csw_infra_f26m_sel", 8), + GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2, + "infra_pcie_peri_ck_26m_ck_p2", "csw_infra_f26m_sel", 9), + GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3, + "infra_pcie_peri_ck_26m_ck_p3", "csw_infra_f26m_sel", 10), + /* INFRA1 */ + GATE_INFRA1(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck", + "sysaxi_sel", 0), + GATE_INFRA1(CLK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck", + "sysaxi_sel", 1), + GATE_INFRA1(CLK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck", + "infra_pwm_sel", 2), + GATE_INFRA1(CLK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1", + "infra_pwm_ck1_sel", 3), + GATE_INFRA1(CLK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2", + "infra_pwm_ck2_sel", 4), + GATE_INFRA1(CLK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3", + "infra_pwm_ck3_sel", 5), + GATE_INFRA1(CLK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4", + "infra_pwm_ck4_sel", 6), + GATE_INFRA1(CLK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5", + "infra_pwm_ck5_sel", 7), + GATE_INFRA1(CLK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6", + "infra_pwm_ck6_sel", 8), + GATE_INFRA1(CLK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7", + "infra_pwm_ck7_sel", 9), + GATE_INFRA1(CLK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8", + "infra_pwm_ck8_sel", 10), + GATE_INFRA1(CLK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck", + "sysaxi_sel", 12), + GATE_INFRA1(CLK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck", + "sysaxi_sel", 13), + GATE_INFRA1(CLK_INFRA_AUD_26M, "infra_f_faud_26m", + "csw_infra_f26m_sel", 14), + GATE_INFRA1(CLK_INFRA_AUD_L, "infra_f_faud_l", "aud_l_sel", 15), + GATE_INFRA1(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", "a1sys_sel", 16), + GATE_INFRA1(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", "a_tuner_sel", 18), + GATE_INFRA1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", + "csw_infra_f26m_sel", 19, CLK_IS_CRITICAL), + // JTAG + GATE_INFRA1_FLAGS(CLK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm", + "sysaxi_sel", 20, CLK_IS_CRITICAL), + GATE_INFRA1(CLK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck", + "sysaxi_sel", 21), + GATE_INFRA1(CLK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck", + "sysaxi_sel", 29), + GATE_INFRA1(CLK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m", + "csw_infra_f26m_sel", 30), + /* INFRA2 */ + GATE_INFRA2(CLK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system", + "csw_infra_f26m_sel", 0), + GATE_INFRA2(CLK_INFRA_I2C_BCK, "infra_i2c_bck", "i2c_sel", 1), + GATE_INFRA2(CLK_INFRA_52M_UART0_CK, "infra_f_52m_uart0", + "infra_mux_uart0_sel", 3), + GATE_INFRA2(CLK_INFRA_52M_UART1_CK, "infra_f_52m_uart1", + "infra_mux_uart1_sel", 4), + GATE_INFRA2(CLK_INFRA_52M_UART2_CK, "infra_f_52m_uart2", + "infra_mux_uart2_sel", 5), + GATE_INFRA2(CLK_INFRA_NFI, "infra_f_fnfi", "nfi1x_sel", 9), + GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10), + GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", + "sysaxi_sel", 11, CLK_IS_CRITICAL), + GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", + "infra_mux_spi0_sel", 12, CLK_IS_CRITICAL), + GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1", + "infra_mux_spi1_sel", 13), + GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck", + "infra_mux_spi2_sel", 14), + GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", + "sysaxi_sel", 15, CLK_IS_CRITICAL), + GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck", + "sysaxi_sel", 16), + GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck", + "sysaxi_sel", 17), + GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", + "sysaxi_sel", 18), + GATE_INFRA2(CLK_INFRA_RTC, "infra_f_frtc", "top_rtc_32k", 19), + GATE_INFRA2(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck", + "csw_infra_f26m_sel", 20), + GATE_INFRA2(CLK_INFRA_RC_ADC, "infra_f_frc_adc", "infra_f_26m_adc_bck", + 21), + GATE_INFRA2(CLK_INFRA_MSDC400, "infra_f_fmsdc400", "emmc_400m_sel", + 22), + GATE_INFRA2(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", "emmc_250m_sel", + 23), + GATE_INFRA2(CLK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck", + "sysaxi_sel", 24), + GATE_INFRA2(CLK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck", + "sysaxi_sel", 25), + GATE_INFRA2(CLK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck", + "sysaxi_sel", 26), + GATE_INFRA2(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", "nfi1x_sel", 27), + GATE_INFRA2(CLK_INFRA_I2C_X16W_MCK_CK_P1, + "infra_hf_i2c_x16w_mck_ck_p1", "sysaxi_sel", 29), + GATE_INFRA2(CLK_INFRA_I2C_X16W_PCK_CK_P1, + "infra_hf_i2c_x16w_pck_ck_p1", "sysaxi_sel", 31), + /* INFRA3 */ + GATE_INFRA3(CLK_INFRA_133M_USB_HCK, "infra_133m_usb_hck", "sysaxi_sel", + 0), + GATE_INFRA3(CLK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1", + "sysaxi_sel", 1), + GATE_INFRA3(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", "sysaxi_sel", + 2), + GATE_INFRA3(CLK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1", + "sysaxi_sel", 3), + GATE_INFRA3(CLK_INFRA_USB_SYS, "infra_usb_sys", "usb_sys_sel", 4), + GATE_INFRA3(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1", + "usb_sys_p1_sel", 5), + GATE_INFRA3(CLK_INFRA_USB_REF, "infra_usb_ref", "top_xtal", 6), + GATE_INFRA3(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", "top_xtal", 7), + GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt", + "usb_frmcnt_sel", 8, CLK_IS_CRITICAL), + GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1", + "usb_frmcnt_p1_sel", 9, CLK_IS_CRITICAL), + GATE_INFRA3(CLK_INFRA_USB_PIPE, "infra_usb_pipe", "sspxtp_sel", 10), + GATE_INFRA3(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", + "usb_phy_sel", 11), + GATE_INFRA3(CLK_INFRA_USB_UTMI, "infra_usb_utmi", "top_xtal", 12), + GATE_INFRA3(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1", + "top_xtal", 13), + GATE_INFRA3(CLK_INFRA_USB_XHCI, "infra_usb_xhci", "usb_xhci_sel", 14), + GATE_INFRA3(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1", + "usb_xhci_p1_sel", 15), + GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0", + "infra_pcie_gfmux_tl_o_p0_sel", 20), + GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1", + "infra_pcie_gfmux_tl_o_p1_sel", 21), + GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2", + "infra_pcie_gfmux_tl_o_p2_sel", 22), + GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3", + "infra_pcie_gfmux_tl_o_p3_sel", 23), + GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0", + "top_xtal", 24), + GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1", + "top_xtal", 25), + GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2", + "top_xtal", 26), + GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3", + "top_xtal", 27), + GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0", + "sysaxi_sel", 28), + GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1", + "sysaxi_sel", 29), + GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2", + "sysaxi_sel", 30), + GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", + "sysaxi_sel", 31), +}; + +static int clk_mt7988_infracfg_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + int r; + void __iomem *base; + int nr = ARRAY_SIZE(infra_muxes) + ARRAY_SIZE(infra_clks); + + base = of_iomap(node, 0); + if (!base) { + pr_err("%s(): ioremap failed\n", __func__); + return -ENOMEM; + } + + clk_data = mtk_alloc_clk_data(nr); + + if (!clk_data) + return -ENOMEM; + + mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node, + &mt7988_clk_lock, clk_data); + + mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), + clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) { + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); + goto free_infracfg_data; + } + return r; + +free_infracfg_data: + mtk_free_clk_data(clk_data); + return r; +} + +static const struct of_device_id of_match_clk_mt7988_infracfg[] = { + { + .compatible = "mediatek,mt7988-infracfg", + }, + {} +}; + +static struct platform_driver clk_mt7988_infracfg_drv = { + .probe = clk_mt7988_infracfg_probe, + .driver = { + .name = "clk-mt7988-infracfg", + .of_match_table = of_match_clk_mt7988_infracfg, + }, +}; +builtin_platform_driver(clk_mt7988_infracfg_drv); diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-topckgen.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-topckgen.c new file mode 100644 index 00000000000..917302b6df6 --- /dev/null +++ b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-topckgen.c @@ -0,0 +1,522 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 MediaTek Inc. + * Author: Sam Shih + * Author: Xiufeng Li + */ + +#include +#include +#include +#include +#include +#include "clk-mtk.h" +#include "clk-gate.h" +#include "clk-mux.h" +#include + +static DEFINE_SPINLOCK(mt7988_clk_lock); + +static const struct mtk_fixed_clk top_fixed_clks[] = { + FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000), +}; + +static const struct mtk_fixed_factor top_divs[] = { + FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2), + FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250), + FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220), + FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", "mpll", 1, 2), + FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", "mpll", 1, 2), + FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", "mpll", 1, 4), + FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", "mpll", 1, 8), + FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", "mpll", 1, 16), + FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2), + FACTOR(CLK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", "mmpll", 1, 15), + FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4), + FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll", 1, 12), + FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", "mmpll", 1, 8), + FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4), + FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", "net1pll", 1, 4), + FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", "net1pll", 1, 5), + FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", "net1pll", 1, 10), + FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", "net1pll", 1, 20), + FACTOR(CLK_TOP_NET1PLL_D8, "net1pll_d8", "net1pll", 1, 8), + FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", "net1pll", 1, 16), + FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", "net1pll", 1, 32), + FACTOR(CLK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", "net1pll", 1, 64), + FACTOR(CLK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", "net1pll", 1, 128), + FACTOR(CLK_TOP_NET2PLL_D2, "net2pll_d2", "net2pll", 1, 2), + FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", "net2pll", 1, 4), + FACTOR(CLK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", "net2pll", 1, 16), + FACTOR(CLK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", "net2pll", 1, 32), + FACTOR(CLK_TOP_NET2PLL_D6, "net2pll_d6", "net2pll", 1, 6), + FACTOR(CLK_TOP_NET2PLL_D8, "net2pll_d8", "net2pll", 1, 8), +}; + +static const char *const netsys_parents[] = { "top_xtal", "net2pll_d2", + "mmpll_d2" }; + +static const char *const netsys_500m_parents[] = { "top_xtal", "net1pll_d5", + "net1pll_d5_d2" }; + +static const char *const netsys_2x_parents[] = { "top_xtal", "net2pll", + "mmpll" }; + +static const char *const netsys_gsw_parents[] = { "top_xtal", "net1pll_d4", + "net1pll_d5" }; + +static const char *const eth_gmii_parents[] = { "top_xtal", "net1pll_d5_d4" }; + +static const char *const netsys_mcu_parents[] = { "top_xtal", "net2pll", + "mmpll", "net1pll_d4", + "net1pll_d5", "mpll" }; + +static const char *const eip197_parents[] = { "top_xtal", "netsyspll", + "net2pll", "mmpll", + "net1pll_d4", "net1pll_d5" }; + +static const char *const axi_infra_parents[] = { "top_xtal", "net1pll_d8_d2" }; + +static const char *const uart_parents[] = { "top_xtal", "mpll_d8", + "mpll_d8_d2" }; + +static const char *const emmc_250m_parents[] = { "top_xtal", "net1pll_d5_d2", + "mmpll_d4" }; + +static const char *const emmc_400m_parents[] = { "top_xtal", "msdcpll", + "mmpll_d2", "mpll_d2", + "mmpll_d4", "net1pll_d8_d2" }; + +static const char *const spi_parents[] = { "top_xtal", "mpll_d2", + "mmpll_d4", "net1pll_d8_d2", + "net2pll_d6", "net1pll_d5_d4", + "mpll_d4", "net1pll_d8_d4" }; + +static const char *const nfi1x_parents[] = { "top_xtal", "mmpll_d4", + "net1pll_d8_d2", "net2pll_d6", + "mpll_d4", "mmpll_d8", + "net1pll_d8_d4", "mpll_d8" }; + +static const char *const spinfi_parents[] = { "top_xtal_d2", "top_xtal", + "net1pll_d5_d4", "mpll_d4", + "mmpll_d8", "net1pll_d8_d4", + "mmpll_d6_d2", "mpll_d8" }; + +static const char *const pwm_parents[] = { "top_xtal", "net1pll_d8_d2", + "net1pll_d5_d4", "mpll_d4", + "mpll_d8_d2", "top_rtc_32k" }; + +static const char *const i2c_parents[] = { "top_xtal", "net1pll_d5_d4", + "mpll_d4", "net1pll_d8_d4" }; + +static const char *const pcie_mbist_250m_parents[] = { "top_xtal", + "net1pll_d5_d2" }; + +static const char *const pextp_tl_ck_parents[] = { "top_xtal", "net2pll_d6", + "mmpll_d8", "mpll_d8_d2", + "top_rtc_32k" }; + +static const char *const usb_frmcnt_parents[] = { "top_xtal", "mmpll_d3_d5" }; + +static const char *const aud_parents[] = { "top_xtal", "apll2" }; + +static const char *const a1sys_parents[] = { "top_xtal", "apll2_d4" }; + +static const char *const aud_l_parents[] = { "top_xtal", "apll2", + "mpll_d8_d2" }; + +static const char *const sspxtp_parents[] = { "top_xtal_d2", "mpll_d8_d2" }; + +static const char *const usxgmii_sbus_0_parents[] = { "top_xtal", + "net1pll_d8_d4" }; + +static const char *const sgm_0_parents[] = { "top_xtal", "sgmpll" }; + +static const char *const sysapb_parents[] = { "top_xtal", "mpll_d3_d2" }; + +static const char *const eth_refck_50m_parents[] = { "top_xtal", + "net2pll_d4_d4" }; + +static const char *const eth_sys_200m_parents[] = { "top_xtal", "net2pll_d4" }; + +static const char *const eth_xgmii_parents[] = { "top_xtal_d2", + "net1pll_d8_d8", + "net1pll_d8_d16" }; + +static const char *const bus_tops_parents[] = { "top_xtal", "net1pll_d5", + "net2pll_d2" }; + +static const char *const npu_tops_parents[] = { "top_xtal", "net2pll" }; + +static const char *const dramc_md32_parents[] = { "top_xtal", "mpll_d2", + "wedmcupll" }; + +static const char *const da_xtp_glb_p0_parents[] = { "top_xtal", + "net2pll_d8" }; + +static const char *const mcusys_backup_625m_parents[] = { "top_xtal", + "net1pll_d4" }; + +static const char *const macsec_parents[] = { "top_xtal", "sgmpll", + "net1pll_d8" }; + +static const char *const netsys_tops_400m_parents[] = { "top_xtal", + "net2pll_d2" }; + +static const char *const eth_mii_parents[] = { "top_xtal_d2", + "net2pll_d4_d8" }; + +static const struct mtk_mux top_muxes[] = { + /* CLK_CFG_0 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, + 0x000, 0x004, 0x008, 0, 2, 7, 0x1c0, 0), + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", + netsys_500m_parents, 0x000, 0x004, 0x008, 8, 2, + 15, 0x1C0, 1), + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", + netsys_2x_parents, 0x000, 0x004, 0x008, 16, 2, 23, + 0x1C0, 2), + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", + netsys_gsw_parents, 0x000, 0x004, 0x008, 24, 2, + 31, 0x1C0, 3), + /* CLK_CFG_1 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", + eth_gmii_parents, 0x010, 0x014, 0x018, 0, 1, 7, + 0x1C0, 4), + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", + netsys_mcu_parents, 0x010, 0x014, 0x018, 8, 3, 15, + 0x1C0, 5), + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel", + netsys_mcu_parents, 0x010, 0x014, 0x018, 16, 3, + 23, 0x1C0, 6), + MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, + 0x010, 0x014, 0x018, 24, 3, 31, 0x1c0, 7), + /* CLK_CFG_2 */ + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel", + axi_infra_parents, 0x020, 0x024, 0x028, 0, + 1, 7, 0x1C0, 8, CLK_IS_CRITICAL), + MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x020, + 0x024, 0x028, 8, 2, 15, 0x1c0, 9), + MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", + emmc_250m_parents, 0x020, 0x024, 0x028, 16, 2, 23, + 0x1C0, 10), + MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", + emmc_400m_parents, 0x020, 0x024, 0x028, 24, 3, 31, + 0x1C0, 11), + /* CLK_CFG_3 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x030, + 0x034, 0x038, 0, 3, 7, 0x1c0, 12), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, + 0x030, 0x034, 0x038, 8, 3, 15, 0x1c0, 13), + MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, + 0x030, 0x034, 0x038, 16, 3, 23, 0x1c0, 14), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, + 0x030, 0x034, 0x038, 24, 3, 31, 0x1c0, 15), + /* CLK_CFG_4 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x040, + 0x044, 0x048, 0, 3, 7, 0x1c0, 16), + MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x040, + 0x044, 0x048, 8, 2, 15, 0x1c0, 17), + MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_MBIST_250M_SEL, + "pcie_mbist_250m_sel", pcie_mbist_250m_parents, + 0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18), + MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_sel", + pextp_tl_ck_parents, 0x040, 0x044, 0x048, 24, 3, + 31, 0x1C0, 19), + /* CLK_CFG_5 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_p1_sel", + pextp_tl_ck_parents, 0x050, 0x054, 0x058, 0, 3, 7, + 0x1C0, 20), + MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_p2_sel", + pextp_tl_ck_parents, 0x050, 0x054, 0x058, 8, 3, + 15, 0x1C0, 21), + MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_p3_sel", + pextp_tl_ck_parents, 0x050, 0x054, 0x058, 16, 3, + 23, 0x1C0, 22), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_SEL, "usb_sys_sel", + eth_gmii_parents, 0x050, 0x054, 0x058, 24, 1, 31, + 0x1C0, 23), + /* CLK_CFG_6 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", + eth_gmii_parents, 0x060, 0x064, 0x068, 0, 1, 7, + 0x1C0, 24), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_SEL, "usb_xhci_sel", + eth_gmii_parents, 0x060, 0x064, 0x068, 8, 1, 15, + 0x1C0, 25), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", + eth_gmii_parents, 0x060, 0x064, 0x068, 16, 1, 23, + 0x1C0, 26), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", + usb_frmcnt_parents, 0x060, 0x064, 0x068, 24, 1, + 31, 0x1C0, 27), + /* CLK_CFG_7 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel", + usb_frmcnt_parents, 0x070, 0x074, 0x078, 0, 1, 7, + 0x1C0, 28), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x070, + 0x074, 0x078, 8, 1, 15, 0x1c0, 29), + MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, + 0x070, 0x074, 0x078, 16, 1, 23, 0x1c0, 30), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, + 0x070, 0x074, 0x078, 24, 2, 31, 0x1c4, 0), + /* CLK_CFG_8 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, + 0x080, 0x084, 0x088, 0, 1, 7, 0x1c4, 1), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, + 0x080, 0x084, 0x088, 8, 1, 15, 0x1c4, 2), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_PHY_SEL, "usb_phy_sel", + sspxtp_parents, 0x080, 0x084, 0x088, 16, 1, 23, + 0x1c4, 3), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel", + usxgmii_sbus_0_parents, 0x080, 0x084, 0x088, 24, + 1, 31, 0x1C4, 4), + /* CLK_CFG_9 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel", + usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, 0, 1, + 7, 0x1C4, 5), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, + 0x090, 0x094, 0x098, 8, 1, 15, 0x1c4, 6), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", + usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, + 16, 1, 23, 0x1C4, 7, CLK_IS_CRITICAL), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, + 0x090, 0x094, 0x098, 24, 1, 31, 0x1c4, 8), + /* CLK_CFG_10 */ + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", + usxgmii_sbus_0_parents, 0x0a0, 0x0a4, 0x0a8, + 0, 1, 7, 0x1C4, 9, CLK_IS_CRITICAL), + MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", + sspxtp_parents, 0x0a0, 0x0a4, 0x0a8, 8, 1, 15, + 0x1C4, 10), + MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", + sspxtp_parents, 0x0a0, 0x0a4, 0x0a8, 16, 1, 23, + 0x1C4, 11), + /* CLK_CFG_11 */ + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", + axi_infra_parents, 0x0a0, 0x0a4, 0x0a8, 24, + 1, 31, 0x1C4, 12, CLK_IS_CRITICAL), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", + sysapb_parents, 0x0b0, 0x0b4, 0x0b8, 0, 1, + 7, 0x1c4, 13, CLK_IS_CRITICAL), + MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel", + eth_refck_50m_parents, 0x0b0, 0x0b4, 0x0b8, 8, 1, + 15, 0x1C4, 14), + MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel", + eth_sys_200m_parents, 0x0b0, 0x0b4, 0x0b8, 16, 1, + 23, 0x1C4, 15), + MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel", + pcie_mbist_250m_parents, 0x0b0, 0x0b4, 0x0b8, 24, + 1, 31, 0x1C4, 16), + /* CLK_CFG_12 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", + eth_xgmii_parents, 0x0c0, 0x0c4, 0x0c8, 0, 2, 7, + 0x1C4, 17), + MUX_GATE_CLR_SET_UPD(CLK_TOP_BUS_TOPS_SEL, "bus_tops_sel", + bus_tops_parents, 0x0c0, 0x0c4, 0x0c8, 8, 2, 15, + 0x1C4, 18), + MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_TOPS_SEL, "npu_tops_sel", + npu_tops_parents, 0x0c0, 0x0c4, 0x0c8, 16, 1, 23, + 0x1C4, 19), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", + sspxtp_parents, 0x0c0, 0x0c4, 0x0c8, 24, 1, + 31, 0x1C4, 20, CLK_IS_CRITICAL), + /* CLK_CFG_13 */ + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", + dramc_md32_parents, 0x0d0, 0x0d4, 0x0d8, 0, + 2, 7, 0x1C4, 21, CLK_IS_CRITICAL), + MUX_GATE_CLR_SET_UPD_FLAGS( + CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents, + 0x0d0, 0x0d4, 0x0d8, 8, 1, 15, 0x1C4, 22, CLK_IS_CRITICAL), + MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", + sspxtp_parents, 0x0d0, 0x0d4, 0x0d8, 16, 1, 23, + 0x1C4, 23), + MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", + sspxtp_parents, 0x0d0, 0x0d4, 0x0d8, 24, 1, 31, + 0x1C4, 24), + /* CLK_CFG_14 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", + sspxtp_parents, 0x0e0, 0x0e4, 0x0e8, 0, 1, 7, + 0x1C4, 25), + MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", + sspxtp_parents, 0x0e0, 0x0e4, 0x0e8, 8, 1, 15, + 0x1C4, 26), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel", + da_xtp_glb_p0_parents, 0x0e0, 0x0e4, 0x0e8, 16, 1, + 23, 0x1C4, 27), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel", + da_xtp_glb_p0_parents, 0x0e0, 0x0e4, 0x0e8, 24, 1, + 31, 0x1C4, 28), + /* CLK_CFG_15 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel", + da_xtp_glb_p0_parents, 0x0f0, 0x0f4, 0x0f8, 0, 1, + 7, 0x1C4, 29), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel", + da_xtp_glb_p0_parents, 0x0f0, 0x0f4, 0x0f8, 8, 1, + 15, 0x1C4, 30), + MUX_GATE_CLR_SET_UPD(CLK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0x0F0, + 0x0f4, 0x0f8, 16, 1, 23, 0x1c8, 0), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_SEL, "da_sel", sspxtp_parents, 0x0f0, + 0x0f4, 0x0f8, 24, 1, 31, 0x1C8, 1), + /* CLK_CFG_16 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, + 0x0100, 0x104, 0x108, 0, 1, 7, 0x1c8, 2), + MUX_GATE_CLR_SET_UPD(CLK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", + sspxtp_parents, 0x0100, 0x104, 0x108, 8, 1, 15, + 0x1C8, 3), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MCUSYS_BACKUP_625M_SEL, + "mcusys_backup_625m_sel", + mcusys_backup_625m_parents, 0x0100, 0x104, 0x108, + 16, 1, 23, 0x1C8, 4), + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SYNC_250M_SEL, + "netsys_sync_250m_sel", pcie_mbist_250m_parents, + 0x0100, 0x104, 0x108, 24, 1, 31, 0x1c8, 5), + /* CLK_CFG_17 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, + 0x0110, 0x114, 0x118, 0, 2, 7, 0x1c8, 6), + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_TOPS_400M_SEL, + "netsys_tops_400m_sel", netsys_tops_400m_parents, + 0x0110, 0x114, 0x118, 8, 1, 15, 0x1c8, 7), + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PPEFB_250M_SEL, + "netsys_ppefb_250m_sel", pcie_mbist_250m_parents, + 0x0110, 0x114, 0x118, 16, 1, 23, 0x1c8, 8), + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", + netsys_parents, 0x0110, 0x114, 0x118, 24, 2, 31, + 0x1C8, 9), + /* CLK_CFG_18 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_MII_SEL, "eth_mii_sel", + eth_mii_parents, 0x0120, 0x124, 0x128, 0, 1, 7, + 0x1c8, 10), + MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_SEL, "ck_npu_sel", netsys_2x_parents, + 0x0120, 0x124, 0x128, 8, 2, 15, 0x1c8, 11), +}; + +static const struct mtk_composite top_aud_divs[] = { + DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud_sel", 0x0420, 0, 0x0420, + 8, 8), +}; + +static int clk_mt7988_topckgen_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + int r; + void __iomem *base; + int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) + + ARRAY_SIZE(top_muxes) + ARRAY_SIZE(top_aud_divs); + + base = of_iomap(node, 0); + if (!base) { + pr_err("%s(): ioremap failed\n", __func__); + return -ENOMEM; + } + + clk_data = mtk_alloc_clk_data(nr); + if (!clk_data) + return -ENOMEM; + + mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), + clk_data); + + mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); + + mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node, + &mt7988_clk_lock, clk_data); + + mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs), + base, &mt7988_clk_lock, clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + + if (r) { + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); + goto free_topckgen_data; + } + return r; + +free_topckgen_data: + mtk_free_clk_data(clk_data); + return r; +} + +static const char *const mcu_bus_div_parents[] = { "top_xtal", "ccipll2_b", + "net1pll_d4" }; + +static const char *const mcu_arm_div_parents[] = { "top_xtal", "arm_b", + "net1pll_d4" }; + +static struct mtk_composite mcu_muxes[] = { + /* bus_pll_divider_cfg */ + MUX_GATE_FLAGS(CLK_MCU_BUS_DIV_SEL, "mcu_bus_div_sel", + mcu_bus_div_parents, 0x7C0, 9, 2, -1, CLK_IS_CRITICAL), + /* mp2_pll_divider_cfg */ + MUX_GATE_FLAGS(CLK_MCU_ARM_DIV_SEL, "mcu_arm_div_sel", + mcu_arm_div_parents, 0x7A8, 9, 2, -1, CLK_IS_CRITICAL), +}; + +static int clk_mt7988_mcusys_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + int r; + void __iomem *base; + int nr = ARRAY_SIZE(mcu_muxes); + + base = of_iomap(node, 0); + if (!base) { + pr_err("%s(): ioremap failed\n", __func__); + return -ENOMEM; + } + + clk_data = mtk_alloc_clk_data(nr); + if (!clk_data) + return -ENOMEM; + + mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base, + &mt7988_clk_lock, clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + + if (r) { + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); + goto free_mcusys_data; + } + return r; + +free_mcusys_data: + mtk_free_clk_data(clk_data); + return r; +} + +static const struct of_device_id of_match_clk_mt7988_topckgen[] = { + { + .compatible = "mediatek,mt7988-topckgen", + }, + {} +}; + +static struct platform_driver clk_mt7988_topckgen_drv = { + .probe = clk_mt7988_topckgen_probe, + .driver = { + .name = "clk-mt7988-topckgen", + .of_match_table = of_match_clk_mt7988_topckgen, + }, +}; +builtin_platform_driver(clk_mt7988_topckgen_drv); + +static const struct of_device_id of_match_clk_mt7988_mcusys[] = { + { + .compatible = "mediatek,mt7988-mcusys", + }, + {} +}; + +static struct platform_driver clk_mt7988_mcusys_drv = { + .probe = clk_mt7988_mcusys_probe, + .driver = { + .name = "clk-mt7988-mcusys", + .of_match_table = of_match_clk_mt7988_mcusys, + }, +}; +builtin_platform_driver(clk_mt7988_mcusys_drv); \ No newline at end of file diff --git a/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-2p5ge.c b/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-2p5ge.c new file mode 100644 index 00000000000..c12e6b8eb6f --- /dev/null +++ b/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-2p5ge.c @@ -0,0 +1,262 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include +#include +#include +#include +#include +#include +#include +#include + +#define MEDAITEK_2P5GE_PHY_DMB_FW "mediatek/mediatek-2p5ge-phy-dmb.bin" +#define MEDIATEK_2P5GE_PHY_PMB_FW "mediatek/mediatek-2p5ge-phy-pmb.bin" + +#define MD32_EN_CFG 0x18 +#define MD32_EN BIT(0) + +#define BASE100T_STATUS_EXTEND 0x10 +#define BASE1000T_STATUS_EXTEND 0x11 +#define EXTEND_CTRL_AND_STATUS 0x16 + +#define PHY_AUX_CTRL_STATUS 0x1d +#define PHY_AUX_DPX_MASK GENMASK(5, 5) +#define PHY_AUX_SPEED_MASK GENMASK(4, 2) + +/* Registers on MDIO_MMD_VEND1 */ +#define MTK_PHY_LINK_STATUS_MISC 0xa2 +#define MTK_PHY_FDX_ENABLE BIT(5) + +/* Registers on MDIO_MMD_VEND2 */ +#define MTK_PHY_LED0_ON_CTRL 0x24 +#define MTK_PHY_LED0_ON_LINK1000 BIT(0) +#define MTK_PHY_LED0_ON_LINK100 BIT(1) +#define MTK_PHY_LED0_ON_LINK10 BIT(2) +#define MTK_PHY_LED0_ON_LINK2500 BIT(7) +#define MTK_PHY_LED0_POLARITY BIT(14) + +#define MTK_PHY_LED1_ON_CTRL 0x26 +#define MTK_PHY_LED1_ON_FDX BIT(4) +#define MTK_PHY_LED1_ON_HDX BIT(5) +#define MTK_PHY_LED1_POLARITY BIT(14) + +enum { + PHY_AUX_SPD_10 = 0, + PHY_AUX_SPD_100, + PHY_AUX_SPD_1000, + PHY_AUX_SPD_2500, +}; + +static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev) +{ + int ret; + int i; + const struct firmware *fw; + struct device *dev = &phydev->mdio.dev; + struct device_node *np; + void __iomem *dmb_addr; + void __iomem *pmb_addr; + void __iomem *mcucsr_base; + u16 reg; + struct pinctrl *pinctrl; + + np = of_find_compatible_node(NULL, NULL, "mediatek,2p5gphy-fw"); + if (!np) + return -ENOENT; + + dmb_addr = of_iomap(np, 0); + if (!dmb_addr) + return -ENOMEM; + pmb_addr = of_iomap(np, 1); + if (!pmb_addr) + return -ENOMEM; + mcucsr_base = of_iomap(np, 2); + if (!mcucsr_base) + return -ENOMEM; + + ret = request_firmware(&fw, MEDAITEK_2P5GE_PHY_DMB_FW, dev); + if (ret) { + dev_err(dev, "failed to load firmware: %s, ret: %d\n", + MEDAITEK_2P5GE_PHY_DMB_FW, ret); + return ret; + } + for (i = 0; i < fw->size - 1; i += 4) + writel(*((uint32_t *)(fw->data + i)), dmb_addr + i); + release_firmware(fw); + + ret = request_firmware(&fw, MEDIATEK_2P5GE_PHY_PMB_FW, dev); + if (ret) { + dev_err(dev, "failed to load firmware: %s, ret: %d\n", + MEDIATEK_2P5GE_PHY_PMB_FW, ret); + return ret; + } + for (i = 0; i < fw->size - 1; i += 4) + writel(*((uint32_t *)(fw->data + i)), pmb_addr + i); + release_firmware(fw); + + reg = readw(mcucsr_base + MD32_EN_CFG); + writew(reg | MD32_EN, mcucsr_base + MD32_EN_CFG); + dev_dbg(dev, "Firmware loading/trigger ok.\n"); + + /* Setup LED */ + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, + MTK_PHY_LED0_POLARITY); + + phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, + MTK_PHY_LED0_ON_LINK10 | + MTK_PHY_LED0_ON_LINK100 | + MTK_PHY_LED0_ON_LINK1000 | + MTK_PHY_LED0_ON_LINK2500); + + phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL, + MTK_PHY_LED1_ON_FDX | MTK_PHY_LED1_ON_HDX); + + pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "i2p5gbe-led"); + if (IS_ERR(pinctrl)) { + dev_err(&phydev->mdio.dev, "Fail to set LED pins!\n"); + return PTR_ERR(pinctrl); + } + + return 0; +} + +static int mt798x_2p5ge_phy_config_aneg(struct phy_device *phydev) +{ + bool changed = false; + u32 adv; + int ret; + + if (phydev->autoneg == AUTONEG_DISABLE) { + /* Configure half duplex with genphy_setup_forced, + * because genphy_c45_pma_setup_forced does not support. + */ + return phydev->duplex != DUPLEX_FULL + ? genphy_setup_forced(phydev) + : genphy_c45_pma_setup_forced(phydev); + } + + ret = genphy_c45_an_config_aneg(phydev); + if (ret < 0) + return ret; + if (ret > 0) + changed = true; + + adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); + ret = phy_modify_changed(phydev, MII_CTRL1000, + ADVERTISE_1000FULL | ADVERTISE_1000HALF, + adv); + if (ret < 0) + return ret; + if (ret > 0) + changed = true; + + return genphy_c45_check_and_restart_aneg(phydev, changed); +} + +static int mt798x_2p5ge_phy_get_features(struct phy_device *phydev) +{ + int ret; + + ret = genphy_read_abilities(phydev); + if (ret) + return ret; + + /* We don't support HDX at MAC layer on mt798x. + * So mask phy's HDX capabilities, too. + */ + linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, + phydev->supported); + linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, + phydev->supported); + linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, + phydev->supported); + linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, + phydev->supported); + linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); + + return 0; +} + +static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev) +{ + int ret; + + ret = genphy_update_link(phydev); + if (ret) + return ret; + + phydev->speed = SPEED_UNKNOWN; + phydev->duplex = DUPLEX_UNKNOWN; + phydev->pause = 0; + phydev->asym_pause = 0; + + if (!phydev->link) + return 0; + + if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) { + ret = genphy_c45_read_lpa(phydev); + if (ret < 0) + return ret; + + /* Read the link partner's 1G advertisement */ + ret = phy_read(phydev, MII_STAT1000); + if (ret < 0) + return ret; + mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret); + } else if (phydev->autoneg == AUTONEG_DISABLE) { + linkmode_zero(phydev->lp_advertising); + } + + ret = phy_read(phydev, PHY_AUX_CTRL_STATUS); + if (ret < 0) + return ret; + + switch (FIELD_GET(PHY_AUX_SPEED_MASK, ret)) { + case PHY_AUX_SPD_10: + phydev->speed = SPEED_10; + break; + case PHY_AUX_SPD_100: + phydev->speed = SPEED_100; + break; + case PHY_AUX_SPD_1000: + phydev->speed = SPEED_1000; + break; + case PHY_AUX_SPD_2500: + phydev->speed = SPEED_2500; + phydev->duplex = DUPLEX_FULL; /* 2.5G must be FDX */ + break; + } + + ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LINK_STATUS_MISC); + if (ret < 0) + return ret; + + phydev->duplex = (ret & MTK_PHY_FDX_ENABLE) ? DUPLEX_FULL : DUPLEX_HALF; + + return 0; +} + +static struct phy_driver mtk_gephy_driver[] = { + { + PHY_ID_MATCH_EXACT(0x00339c11), + .name = "MediaTek MT798x 2.5GbE PHY", + .config_init = mt798x_2p5ge_phy_config_init, + .config_aneg = mt798x_2p5ge_phy_config_aneg, + .get_features = mt798x_2p5ge_phy_get_features, + .read_status = mt798x_2p5ge_phy_read_status, + }, +}; + +module_phy_driver(mtk_gephy_driver); + +static struct mdio_device_id __maybe_unused mtk_2p5ge_phy_tbl[] = { + { PHY_ID_MATCH_VENDOR(0x00339c00) }, + { } +}; + +MODULE_DESCRIPTION("MediaTek 2.5Gb Ethernet PHY driver"); +MODULE_AUTHOR("SkyLake Huang "); +MODULE_LICENSE("GPL"); + +MODULE_DEVICE_TABLE(mdio, mtk_2p5ge_phy_tbl); +MODULE_FIRMWARE(MEDAITEK_2P5GE_PHY_DMB_FW); +MODULE_FIRMWARE(MEDIATEK_2P5GE_PHY_PMB_FW); diff --git a/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-ge-soc.c b/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-ge-soc.c new file mode 100644 index 00000000000..e48502ac3fd --- /dev/null +++ b/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-ge-soc.c @@ -0,0 +1,1263 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include +#include +#include +#include +#include +#include +#include + +#define MTK_GPHY_ID_MT7981 0x03a29461 +#define MTK_GPHY_ID_MT7988 0x03a29481 + +#define MTK_EXT_PAGE_ACCESS 0x1f +#define MTK_PHY_PAGE_STANDARD 0x0000 +#define MTK_PHY_PAGE_EXTENDED_3 0x0003 + +#define MTK_PHY_LPI_REG_14 0x14 +#define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0) + +#define MTK_PHY_LPI_REG_1c 0x1c +#define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8) + +#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 +#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 + +#define ANALOG_INTERNAL_OPERATION_MAX_US 20 +#define TXRESERVE_MIN 0 +#define TXRESERVE_MAX 7 + +#define MTK_PHY_ANARG_RG 0x10 +#define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8) + +/* Registers on MDIO_MMD_VEND1 */ +#define MTK_PHY_TXVLD_DA_RG 0x12 +#define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10) +#define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0) + +#define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16 +#define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10) +#define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0) + +#define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17 +#define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8) +#define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0) + +#define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18 +#define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8) +#define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0) + +#define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19 +#define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8) +#define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0) + +#define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20 +#define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8) +#define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0) + +#define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21 +#define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8) +#define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0) + +#define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22 +#define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8) +#define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0) + +#define MTK_PHY_RXADC_CTRL_RG7 0xc6 +#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8) + +#define MTK_PHY_RXADC_CTRL_RG9 0xc8 +#define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12) +#define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8) +#define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4) +#define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0) + +#define MTK_PHY_LDO_OUTPUT_V 0xd7 + +#define MTK_PHY_RG_ANA_CAL_RG0 0xdb +#define MTK_PHY_RG_CAL_CKINV BIT(12) +#define MTK_PHY_RG_ANA_CALEN BIT(8) +#define MTK_PHY_RG_ZCALEN_A BIT(0) + +#define MTK_PHY_RG_ANA_CAL_RG1 0xdc +#define MTK_PHY_RG_ZCALEN_B BIT(12) +#define MTK_PHY_RG_ZCALEN_C BIT(8) +#define MTK_PHY_RG_ZCALEN_D BIT(4) +#define MTK_PHY_RG_TXVOS_CALEN BIT(0) + +#define MTK_PHY_RG_ANA_CAL_RG5 0xe0 +#define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8) + +#define MTK_PHY_RG_TX_FILTER 0xfe + +#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120 +#define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8) +#define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0) + +#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122 +#define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0) + +#define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144 +#define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5) + +#define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172 +#define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8) +#define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0) + +#define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173 +#define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8) +#define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0) + +#define MTK_PHY_RG_AD_CAL_COMP 0x17a +#define MTK_PHY_AD_CAL_COMP_OUT_SHIFT (8) + +#define MTK_PHY_RG_AD_CAL_CLK 0x17b +#define MTK_PHY_DA_CAL_CLK BIT(0) + +#define MTK_PHY_RG_AD_CALIN 0x17c +#define MTK_PHY_DA_CALIN_FLAG BIT(0) + +#define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d +#define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0) + +#define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e +#define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0) + +#define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f +#define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0) + +#define MTK_PHY_RG_DASN_DAC_IN0_D 0x180 +#define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0) + +#define MTK_PHY_RG_DASN_DAC_IN1_A 0x181 +#define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0) + +#define MTK_PHY_RG_DASN_DAC_IN1_B 0x182 +#define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0) + +#define MTK_PHY_RG_DASN_DAC_IN1_C 0x183 +#define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0) + +#define MTK_PHY_RG_DASN_DAC_IN1_D 0x184 +#define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0) + +#define MTK_PHY_RG_DEV1E_REG19b 0x19b +#define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8) + +#define MTK_PHY_RG_LP_IIR2_K1_L 0x22a +#define MTK_PHY_RG_LP_IIR2_K1_U 0x22b +#define MTK_PHY_RG_LP_IIR2_K2_L 0x22c +#define MTK_PHY_RG_LP_IIR2_K2_U 0x22d +#define MTK_PHY_RG_LP_IIR2_K3_L 0x22e +#define MTK_PHY_RG_LP_IIR2_K3_U 0x22f +#define MTK_PHY_RG_LP_IIR2_K4_L 0x230 +#define MTK_PHY_RG_LP_IIR2_K4_U 0x231 +#define MTK_PHY_RG_LP_IIR2_K5_L 0x232 +#define MTK_PHY_RG_LP_IIR2_K5_U 0x233 + +#define MTK_PHY_RG_DEV1E_REG234 0x234 +#define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0) +#define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4) +#define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12) + +#define MTK_PHY_RG_LPF_CNT_VAL 0x235 + +#define MTK_PHY_RG_DEV1E_REG238 0x238 +#define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0) +#define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12) + +#define MTK_PHY_RG_DEV1E_REG239 0x239 +#define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0) +#define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12) + +#define MTK_PHY_RG_DEV1E_REG27C 0x27c +#define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8) +#define MTK_PHY_RG_DEV1E_REG27D 0x27d +#define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0) + +#define MTK_PHY_RG_DEV1E_REG2C7 0x2c7 +#define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0) +#define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8) + +#define MTK_PHY_RG_DEV1E_REG2D1 0x2d1 +#define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0) +#define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8) +#define MTK_PHY_LPI_TR_READY BIT(9) +#define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10) + +#define MTK_PHY_RG_DEV1E_REG323 0x323 +#define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0) +#define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4) + +#define MTK_PHY_RG_DEV1E_REG324 0x324 +#define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0) +#define MTK_PHY_SMI_DET_MAX_EN BIT(8) + +#define MTK_PHY_RG_DEV1E_REG326 0x326 +#define MTK_PHY_LPI_MODE_SD_ON BIT(0) +#define MTK_PHY_RESET_RANDUPD_CNT BIT(1) +#define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2) +#define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4) +#define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5) + +#define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502 +#define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503 + +#define MTK_PHY_DA_TX_R50_PAIR_A 0x53d +#define MTK_PHY_DA_TX_R50_PAIR_B 0x53e +#define MTK_PHY_DA_TX_R50_PAIR_C 0x53f +#define MTK_PHY_DA_TX_R50_PAIR_D 0x540 + +/* Registers on MDIO_MMD_VEND2 */ +#define MTK_PHY_LED0_ON_CTRL 0x24 +#define MTK_PHY_LED0_ON_MASK GENMASK(6, 0) +#define MTK_PHY_LED0_ON_LINK1000 BIT(0) +#define MTK_PHY_LED0_ON_LINK100 BIT(1) +#define MTK_PHY_LED0_ON_LINK10 BIT(2) +#define MTK_PHY_LED0_ON_LINKDOWN BIT(3) +#define MTK_PHY_LED0_ON_FDX BIT(4) /* Full duplex */ +#define MTK_PHY_LED0_ON_HDX BIT(5) /* Half duplex */ +#define MTK_PHY_LED0_FORCE_ON BIT(6) +#define MTK_PHY_LED0_POLARITY BIT(14) +#define MTK_PHY_LED0_ENABLE BIT(15) + +#define MTK_PHY_LED0_BLINK_CTRL 0x25 +#define MTK_PHY_LED0_1000TX BIT(0) +#define MTK_PHY_LED0_1000RX BIT(1) +#define MTK_PHY_LED0_100TX BIT(2) +#define MTK_PHY_LED0_100RX BIT(3) +#define MTK_PHY_LED0_10TX BIT(4) +#define MTK_PHY_LED0_10RX BIT(5) +#define MTK_PHY_LED0_COLLISION BIT(6) +#define MTK_PHY_LED0_RX_CRC_ERR BIT(7) +#define MTK_PHY_LED0_RX_IDLE_ERR BIT(8) +#define MTK_PHY_LED0_FORCE_BLINK BIT(9) + +#define MTK_PHY_LED1_ON_CTRL 0x26 +#define MTK_PHY_LED1_ON_MASK GENMASK(6, 0) +#define MTK_PHY_LED1_ON_LINK1000 BIT(0) +#define MTK_PHY_LED1_ON_LINK100 BIT(1) +#define MTK_PHY_LED1_ON_LINK10 BIT(2) +#define MTK_PHY_LED1_ON_LINKDOWN BIT(3) +#define MTK_PHY_LED1_ON_FDX BIT(4) /* Full duplex */ +#define MTK_PHY_LED1_ON_HDX BIT(5) /* Half duplex */ +#define MTK_PHY_LED1_FORCE_ON BIT(6) +#define MTK_PHY_LED1_POLARITY BIT(14) +#define MTK_PHY_LED1_ENABLE BIT(15) + +#define MTK_PHY_LED1_BLINK_CTRL 0x27 +#define MTK_PHY_LED1_1000TX BIT(0) +#define MTK_PHY_LED1_1000RX BIT(1) +#define MTK_PHY_LED1_100TX BIT(2) +#define MTK_PHY_LED1_100RX BIT(3) +#define MTK_PHY_LED1_10TX BIT(4) +#define MTK_PHY_LED1_10RX BIT(5) +#define MTK_PHY_LED1_COLLISION BIT(6) +#define MTK_PHY_LED1_RX_CRC_ERR BIT(7) +#define MTK_PHY_LED1_RX_IDLE_ERR BIT(8) +#define MTK_PHY_LED1_FORCE_BLINK BIT(9) + +#define MTK_PHY_RG_BG_RASEL 0x115 +#define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0) + +/* These macro privides efuse parsing for internal phy. */ +#define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0)) +#define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0)) +#define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0)) +#define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0)) +#define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0)) + +#define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0)) +#define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0)) +#define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0)) +#define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0)) +#define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0)) + +#define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0)) +#define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0)) + +#define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0)) +#define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0)) + +enum { + NO_PAIR, + PAIR_A, + PAIR_B, + PAIR_C, + PAIR_D, +}; + +enum { + GPHY_PORT0, + GPHY_PORT1, + GPHY_PORT2, + GPHY_PORT3, +}; + +enum calibration_mode { + EFUSE_K, + SW_K +}; + +enum CAL_ITEM { + REXT, + TX_OFFSET, + TX_AMP, + TX_R50, + TX_VCM +}; + +enum CAL_MODE { + EFUSE_M, + SW_M +}; + +struct mtk_socphy_shared_priv { + u32 boottrap; +}; + +static int mtk_socphy_read_page(struct phy_device *phydev) +{ + return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); +} + +static int mtk_socphy_write_page(struct phy_device *phydev, int page) +{ + return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); +} + +/* One calibration cycle consists of: + * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high + * until AD_CAL_COMP is ready to output calibration result. + * 2.Wait until DA_CAL_CLK is available. + * 3.Fetch AD_CAL_COMP_OUT. + */ +static int cal_cycle(struct phy_device *phydev, int devad, + u32 regnum, u16 mask, u16 cal_val) +{ + int reg_val; + int ret; + + phy_modify_mmd(phydev, devad, regnum, + mask, cal_val); + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, + MTK_PHY_DA_CALIN_FLAG); + + ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, + MTK_PHY_RG_AD_CAL_CLK, reg_val, + reg_val & MTK_PHY_DA_CAL_CLK, 500, + ANALOG_INTERNAL_OPERATION_MAX_US, false); + if (ret) { + phydev_err(phydev, "Calibration cycle timeout\n"); + return ret; + } + + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, + MTK_PHY_DA_CALIN_FLAG); + ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >> + MTK_PHY_AD_CAL_COMP_OUT_SHIFT; + phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); + + return ret; +} + +static int rext_fill_result(struct phy_device *phydev, u16 *buf) +{ + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, + MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8); + phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL, + MTK_PHY_RG_BG_RASEL_MASK, buf[1]); + + return 0; +} + +static int rext_cal_efuse(struct phy_device *phydev, u32 *buf) +{ + u16 rext_cal_val[2]; + + rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]); + rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]); + rext_fill_result(phydev, rext_cal_val); + + return 0; +} + +static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf) +{ + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, + MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8); + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, + MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]); + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, + MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8); + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, + MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]); + + return 0; +} + +static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf) +{ + u16 tx_offset_cal_val[4]; + + tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]); + tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]); + tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]); + tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]); + + tx_offset_fill_result(phydev, tx_offset_cal_val); + + return 0; +} + +static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf) +{ + int i; + int bias[16] = {}; + const int vals_9461[16] = { 7, 1, 4, 7, + 7, 1, 4, 7, + 7, 1, 4, 7, + 7, 1, 4, 7 }; + const int vals_9481[16] = { 10, 6, 6, 10, + 10, 6, 6, 10, + 10, 6, 6, 10, + 10, 6, 6, 10 }; + switch (phydev->drv->phy_id) { + case MTK_GPHY_ID_MT7981: + /* We add some calibration to efuse values + * due to board level influence. + * GBE: +7, TBT: +1, HBT: +4, TST: +7 + */ + memcpy(bias, (const void *)vals_9461, sizeof(bias)); + break; + case MTK_GPHY_ID_MT7988: + memcpy(bias, (const void *)vals_9481, sizeof(bias)); + break; + } + + /* Prevent overflow */ + for (i = 0; i < 12; i++) { + if (buf[i >> 2] + bias[i] > 63) { + buf[i >> 2] = 63; + bias[i] = 0; + } + } + + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, + MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10); + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, + MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]); + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, + MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10); + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, + MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]); + + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, + MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, (buf[1] + bias[4]) << 8); + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, + MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, buf[1] + bias[5]); + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, + MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8); + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, + MTK_PHY_DA_TX_I2MPB_B_TST_MASK, buf[1] + bias[7]); + + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, + MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, (buf[2] + bias[8]) << 8); + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, + MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, buf[2] + bias[9]); + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, + MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, (buf[2] + bias[10]) << 8); + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, + MTK_PHY_DA_TX_I2MPB_C_TST_MASK, buf[2] + bias[11]); + + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, + MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8); + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, + MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, buf[3] + bias[13]); + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, + MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, (buf[3] + bias[14]) << 8); + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, + MTK_PHY_DA_TX_I2MPB_D_TST_MASK, buf[3] + bias[15]); + + return 0; +} + +static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf) +{ + u16 tx_amp_cal_val[4]; + + tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]); + tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]); + tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]); + tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]); + tx_amp_fill_result(phydev, tx_amp_cal_val); + + return 0; +} + +static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val, + u8 txg_calen_x) +{ + int bias = 0; + u16 reg, val; + + if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988) + bias = -2; + + val = clamp_val(bias + tx_r50_cal_val, 0, 63); + + switch (txg_calen_x) { + case PAIR_A: + reg = MTK_PHY_DA_TX_R50_PAIR_A; + break; + case PAIR_B: + reg = MTK_PHY_DA_TX_R50_PAIR_B; + break; + case PAIR_C: + reg = MTK_PHY_DA_TX_R50_PAIR_C; + break; + case PAIR_D: + reg = MTK_PHY_DA_TX_R50_PAIR_D; + break; + default: + return -EINVAL; + } + + phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8); + + return 0; +} + +static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf, + u8 txg_calen_x) +{ + u16 tx_r50_cal_val; + + switch (txg_calen_x) { + case PAIR_A: + tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]); + break; + case PAIR_B: + tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]); + break; + case PAIR_C: + tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]); + break; + case PAIR_D: + tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]); + break; + default: + return -EINVAL; + } + tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x); + + return 0; +} + +static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x) +{ + u8 lower_idx, upper_idx, txreserve_val; + u8 lower_ret, upper_ret; + int ret; + + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, + MTK_PHY_RG_ANA_CALEN); + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, + MTK_PHY_RG_CAL_CKINV); + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, + MTK_PHY_RG_TXVOS_CALEN); + + switch (rg_txreserve_x) { + case PAIR_A: + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, + MTK_PHY_RG_DASN_DAC_IN0_A, + MTK_PHY_DASN_DAC_IN0_A_MASK); + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, + MTK_PHY_RG_DASN_DAC_IN1_A, + MTK_PHY_DASN_DAC_IN1_A_MASK); + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, + MTK_PHY_RG_ANA_CAL_RG0, + MTK_PHY_RG_ZCALEN_A); + break; + case PAIR_B: + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, + MTK_PHY_RG_DASN_DAC_IN0_B, + MTK_PHY_DASN_DAC_IN0_B_MASK); + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, + MTK_PHY_RG_DASN_DAC_IN1_B, + MTK_PHY_DASN_DAC_IN1_B_MASK); + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, + MTK_PHY_RG_ANA_CAL_RG1, + MTK_PHY_RG_ZCALEN_B); + break; + case PAIR_C: + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, + MTK_PHY_RG_DASN_DAC_IN0_C, + MTK_PHY_DASN_DAC_IN0_C_MASK); + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, + MTK_PHY_RG_DASN_DAC_IN1_C, + MTK_PHY_DASN_DAC_IN1_C_MASK); + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, + MTK_PHY_RG_ANA_CAL_RG1, + MTK_PHY_RG_ZCALEN_C); + break; + case PAIR_D: + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, + MTK_PHY_RG_DASN_DAC_IN0_D, + MTK_PHY_DASN_DAC_IN0_D_MASK); + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, + MTK_PHY_RG_DASN_DAC_IN1_D, + MTK_PHY_DASN_DAC_IN1_D_MASK); + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, + MTK_PHY_RG_ANA_CAL_RG1, + MTK_PHY_RG_ZCALEN_D); + break; + default: + ret = -EINVAL; + goto restore; + } + + lower_idx = TXRESERVE_MIN; + upper_idx = TXRESERVE_MAX; + + phydev_dbg(phydev, "Start TX-VCM SW cal.\n"); + while ((upper_idx - lower_idx) > 1) { + txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2); + ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, + MTK_PHY_DA_RX_PSBN_TBT_MASK | + MTK_PHY_DA_RX_PSBN_HBT_MASK | + MTK_PHY_DA_RX_PSBN_GBE_MASK | + MTK_PHY_DA_RX_PSBN_LP_MASK, + txreserve_val << 12 | txreserve_val << 8 | + txreserve_val << 4 | txreserve_val); + if (ret == 1) { + upper_idx = txreserve_val; + upper_ret = ret; + } else if (ret == 0) { + lower_idx = txreserve_val; + lower_ret = ret; + } else { + goto restore; + } + } + + if (lower_idx == TXRESERVE_MIN) { + lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1, + MTK_PHY_RXADC_CTRL_RG9, + MTK_PHY_DA_RX_PSBN_TBT_MASK | + MTK_PHY_DA_RX_PSBN_HBT_MASK | + MTK_PHY_DA_RX_PSBN_GBE_MASK | + MTK_PHY_DA_RX_PSBN_LP_MASK, + lower_idx << 12 | lower_idx << 8 | + lower_idx << 4 | lower_idx); + ret = lower_ret; + } else if (upper_idx == TXRESERVE_MAX) { + upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1, + MTK_PHY_RXADC_CTRL_RG9, + MTK_PHY_DA_RX_PSBN_TBT_MASK | + MTK_PHY_DA_RX_PSBN_HBT_MASK | + MTK_PHY_DA_RX_PSBN_GBE_MASK | + MTK_PHY_DA_RX_PSBN_LP_MASK, + upper_idx << 12 | upper_idx << 8 | + upper_idx << 4 | upper_idx); + ret = upper_ret; + } + if (ret < 0) + goto restore; + + /* We calibrate TX-VCM in different logic. Check upper index and then + * lower index. If this calibration is valid, apply lower index's result. + */ + ret = upper_ret - lower_ret; + if (ret == 1) { + ret = 0; + /* Make sure we use upper_idx in our calibration system */ + cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, + MTK_PHY_DA_RX_PSBN_TBT_MASK | + MTK_PHY_DA_RX_PSBN_HBT_MASK | + MTK_PHY_DA_RX_PSBN_GBE_MASK | + MTK_PHY_DA_RX_PSBN_LP_MASK, + upper_idx << 12 | upper_idx << 8 | + upper_idx << 4 | upper_idx); + phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx); + } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 && + lower_ret == 1) { + ret = 0; + cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, + MTK_PHY_DA_RX_PSBN_TBT_MASK | + MTK_PHY_DA_RX_PSBN_HBT_MASK | + MTK_PHY_DA_RX_PSBN_GBE_MASK | + MTK_PHY_DA_RX_PSBN_LP_MASK, + lower_idx << 12 | lower_idx << 8 | + lower_idx << 4 | lower_idx); + phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n", + lower_idx); + } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 && + lower_ret == 0) { + ret = 0; + phydev_warn(phydev, "TX-VCM SW cal result at high margin 0x%x\n", + upper_idx); + } else { + ret = -EINVAL; + } + +restore: + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, + MTK_PHY_RG_ANA_CALEN); + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, + MTK_PHY_RG_TXVOS_CALEN); + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, + MTK_PHY_RG_ZCALEN_A); + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, + MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C | + MTK_PHY_RG_ZCALEN_D); + + return ret; +} + +static void mt798x_phy_common_finetune(struct phy_device *phydev) +{ + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); + /* EnabRandUpdTrig = 1 */ + __phy_write(phydev, 0x11, 0x2f00); + __phy_write(phydev, 0x12, 0xe); + __phy_write(phydev, 0x10, 0x8fb0); + + /* NormMseLoThresh = 85 */ + __phy_write(phydev, 0x11, 0x55a0); + __phy_write(phydev, 0x12, 0x0); + __phy_write(phydev, 0x10, 0x83aa); + + /* TrFreeze = 0 */ + __phy_write(phydev, 0x11, 0x0); + __phy_write(phydev, 0x12, 0x0); + __phy_write(phydev, 0x10, 0x9686); + + /* SSTrKp1000Slv = 5 */ + __phy_write(phydev, 0x11, 0xbaef); + __phy_write(phydev, 0x12, 0x2e); + __phy_write(phydev, 0x10, 0x968c); + + /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2, + * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2 + */ + __phy_write(phydev, 0x11, 0xd10a); + __phy_write(phydev, 0x12, 0x34); + __phy_write(phydev, 0x10, 0x8f82); + + /* VcoSlicerThreshBitsHigh */ + __phy_write(phydev, 0x11, 0x5555); + __phy_write(phydev, 0x12, 0x55); + __phy_write(phydev, 0x10, 0x8ec0); + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); + + /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/ + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, + MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK, + BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); + + /* rg_tr_lpf_cnt_val = 512 */ + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200); + + /* IIR2 related */ + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82); + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0); + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103); + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0); + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82); + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0); + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177); + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3); + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82); + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe); + + /* FFE peaking */ + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C, + MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8); + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D, + MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e); + + /* Disable LDO pump */ + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0); + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0); + /* Adjust LDO output voltage */ + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222); +} + +static void mt7981_phy_finetune(struct phy_device *phydev) +{ + u16 val[8] = { 0x01ce, 0x01c1, + 0x020f, 0x0202, + 0x03d0, 0x03c0, + 0x0013, 0x0005 }; + int i, k; + + /* 100M eye finetune: + * Keep middle level of TX MLT3 shapper as default. + * Only change TX MLT3 overshoot level here. + */ + for (k = 0, i = 1; i < 12; i++) { + if (i % 3 == 0) + continue; + phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]); + } + + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); + /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */ + __phy_write(phydev, 0x11, 0xc71); + __phy_write(phydev, 0x12, 0xc); + __phy_write(phydev, 0x10, 0x8fae); + + /* ResetSyncOffset = 6 */ + __phy_write(phydev, 0x11, 0x600); + __phy_write(phydev, 0x12, 0x0); + __phy_write(phydev, 0x10, 0x8fc0); + + /* VgaDecRate = 1 */ + __phy_write(phydev, 0x11, 0x4c2a); + __phy_write(phydev, 0x12, 0x3e); + __phy_write(phydev, 0x10, 0x8fa4); + + /* FfeUpdGainForce = 4 */ + __phy_write(phydev, 0x11, 0x240); + __phy_write(phydev, 0x12, 0x0); + __phy_write(phydev, 0x10, 0x9680); + + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); +} + +static void mt7988_phy_finetune(struct phy_device *phydev) +{ + u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182, + 0x020d, 0x0206, 0x0384, 0x03d0, + 0x03c6, 0x030a, 0x0011, 0x0005 }; + int i; + + /* Set default MLT3 shaper first */ + for (i = 0; i < 12; i++) + phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]); + + /* TCT finetune */ + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5); + + /* Disable TX power saving */ + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, + MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8); + + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); + + /* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */ + __phy_write(phydev, 0x11, 0x671); + __phy_write(phydev, 0x12, 0xc); + __phy_write(phydev, 0x10, 0x8fae); + + /* ResetSyncOffset = 5 */ + __phy_write(phydev, 0x11, 0x500); + __phy_write(phydev, 0x12, 0x0); + __phy_write(phydev, 0x10, 0x8fc0); + + /* VgaDecRate is 1 at default on mt7988 */ + + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); + + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30); + /* TxClkOffset = 2 */ + __phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK, + FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2)); + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); +} + +static void mt798x_phy_eee(struct phy_device *phydev) +{ + phy_modify_mmd(phydev, MDIO_MMD_VEND1, + MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120, + MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK | + MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, + FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) | + FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14)); + + phy_modify_mmd(phydev, MDIO_MMD_VEND1, + MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, + MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, + FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, + 0xff)); + + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, + MTK_PHY_RG_TESTMUX_ADC_CTRL, + MTK_PHY_RG_TXEN_DIG_MASK); + + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, + MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY); + + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, + MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN); + + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238, + MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK | + MTK_PHY_LPI_SLV_SEND_TX_EN, + FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120)); + + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239, + MTK_PHY_LPI_SEND_LOC_TIMER_MASK | + MTK_PHY_LPI_TXPCS_LOC_RCV, + FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117)); + + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7, + MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK, + FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) | + FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13)); + + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1, + MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, + FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, + 0x33) | + MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY | + MTK_PHY_LPI_VCO_EEE_STG0_EN); + + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323, + MTK_PHY_EEE_WAKE_MAS_INT_DC | + MTK_PHY_EEE_WAKE_SLV_INT_DC); + + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324, + MTK_PHY_SMI_DETCNT_MAX_MASK, + FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) | + MTK_PHY_SMI_DET_MAX_EN); + + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326, + MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT | + MTK_PHY_TREC_UPDATE_ENAB_CLR | + MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF | + MTK_PHY_TR_READY_SKIP_AFE_WAKEUP); + + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); + /* Regsigdet_sel_1000 = 0 */ + __phy_write(phydev, 0x11, 0xb); + __phy_write(phydev, 0x12, 0x0); + __phy_write(phydev, 0x10, 0x9690); + + /* REG_EEE_st2TrKf1000 = 3 */ + __phy_write(phydev, 0x11, 0x114f); + __phy_write(phydev, 0x12, 0x2); + __phy_write(phydev, 0x10, 0x969a); + + /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */ + __phy_write(phydev, 0x11, 0x3028); + __phy_write(phydev, 0x12, 0x0); + __phy_write(phydev, 0x10, 0x969e); + + /* RegEEE_slv_wake_int_timer_tar = 8 */ + __phy_write(phydev, 0x11, 0x5010); + __phy_write(phydev, 0x12, 0x0); + __phy_write(phydev, 0x10, 0x96a0); + + /* RegEEE_trfreeze_timer2 = 586 */ + __phy_write(phydev, 0x11, 0x24a); + __phy_write(phydev, 0x12, 0x0); + __phy_write(phydev, 0x10, 0x96a8); + + /* RegEEE100Stg1_tar = 16 */ + __phy_write(phydev, 0x11, 0x3210); + __phy_write(phydev, 0x12, 0x0); + __phy_write(phydev, 0x10, 0x96b8); + + /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */ + __phy_write(phydev, 0x11, 0x1463); + __phy_write(phydev, 0x12, 0x0); + __phy_write(phydev, 0x10, 0x96ca); + + /* DfeTailEnableVgaThresh1000 = 27 */ + __phy_write(phydev, 0x11, 0x36); + __phy_write(phydev, 0x12, 0x0); + __phy_write(phydev, 0x10, 0x8f80); + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); + + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3); + __phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000_MASK, + FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c)); + + __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK, + FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc)); + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); + + phy_modify_mmd(phydev, MDIO_MMD_VEND1, + MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, + MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, + FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff)); +} + +static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item, + u8 start_pair, u8 end_pair) +{ + u8 pair_n; + int ret; + + for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { + /* TX_OFFSET & TX_AMP have no SW calibration. */ + switch (cal_item) { + case TX_VCM: + ret = tx_vcm_cal_sw(phydev, pair_n); + break; + default: + return -EINVAL; + } + if (ret) + return ret; + } + return 0; +} + +static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item, + u8 start_pair, u8 end_pair, u32 *buf) +{ + u8 pair_n; + int ret; + + for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { + /* TX_VCM has no efuse calibration. */ + switch (cal_item) { + case REXT: + ret = rext_cal_efuse(phydev, buf); + break; + case TX_OFFSET: + ret = tx_offset_cal_efuse(phydev, buf); + break; + case TX_AMP: + ret = tx_amp_cal_efuse(phydev, buf); + break; + case TX_R50: + ret = tx_r50_cal_efuse(phydev, buf, pair_n); + break; + default: + return -EINVAL; + } + if (ret) + return ret; + } + + return 0; +} + +static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item, + enum CAL_MODE cal_mode, u8 start_pair, + u8 end_pair, u32 *buf) +{ + int ret; + + switch (cal_mode) { + case EFUSE_M: + ret = cal_efuse(phydev, cal_item, start_pair, + end_pair, buf); + break; + case SW_M: + ret = cal_sw(phydev, cal_item, start_pair, end_pair); + break; + default: + return -EINVAL; + } + + if (ret) { + phydev_err(phydev, "cal %d failed\n", cal_item); + return -EIO; + } + + return 0; +} + +static int mt798x_phy_calibration(struct phy_device *phydev) +{ + int ret = 0; + u32 *buf; + size_t len; + struct nvmem_cell *cell; + + cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data"); + if (IS_ERR(cell)) { + if (PTR_ERR(cell) == -EPROBE_DEFER) + return PTR_ERR(cell); + return 0; + } + + buf = (u32 *)nvmem_cell_read(cell, &len); + if (IS_ERR(buf)) + return PTR_ERR(buf); + nvmem_cell_put(cell); + + if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) { + phydev_err(phydev, "invalid efuse data\n"); + ret = -EINVAL; + goto out; + } + + ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf); + if (ret) + goto out; + ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf); + if (ret) + goto out; + ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf); + if (ret) + goto out; + ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf); + if (ret) + goto out; + ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf); + if (ret) + goto out; + +out: + kfree(buf); + return ret; +} + +static int mt798x_phy_config_init(struct phy_device *phydev) +{ + switch (phydev->drv->phy_id) { + case MTK_GPHY_ID_MT7981: + mt7981_phy_finetune(phydev); + break; + case MTK_GPHY_ID_MT7988: + mt7988_phy_finetune(phydev); + break; + } + + mt798x_phy_common_finetune(phydev); + mt798x_phy_eee(phydev); + + return mt798x_phy_calibration(phydev); +} + +static int mt7988_phy_setup_led(struct phy_device *phydev) +{ + struct mtk_socphy_shared_priv *priv = phydev->shared->priv; + int port = phydev->mdio.addr; + u32 reg = priv->boottrap; + struct pinctrl *pinctrl; + + phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, + MTK_PHY_LED0_ENABLE | MTK_PHY_LED0_POLARITY | + MTK_PHY_LED0_ON_LINK10 | + MTK_PHY_LED0_ON_LINK100 | + MTK_PHY_LED0_ON_LINK1000); + phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL, + MTK_PHY_LED1_ENABLE | MTK_PHY_LED1_POLARITY | + MTK_PHY_LED1_ON_LINK10 | + MTK_PHY_LED1_ON_LINK100 | + MTK_PHY_LED1_ON_LINK1000); + + if ((port == GPHY_PORT0 && reg & BIT(8)) || + (port == GPHY_PORT1 && reg & BIT(9)) || + (port == GPHY_PORT2 && reg & BIT(10)) || + (port == GPHY_PORT3 && reg & BIT(11))) { + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, + MTK_PHY_LED0_POLARITY); + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL, + MTK_PHY_LED1_POLARITY); + } + + phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_BLINK_CTRL, + MTK_PHY_LED0_1000TX | MTK_PHY_LED0_1000RX | + MTK_PHY_LED0_100TX | MTK_PHY_LED0_100RX | + MTK_PHY_LED0_10TX | MTK_PHY_LED0_10RX); + phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_BLINK_CTRL, + MTK_PHY_LED1_1000TX | MTK_PHY_LED1_1000RX | + MTK_PHY_LED1_100TX | MTK_PHY_LED1_100RX | + MTK_PHY_LED1_10TX | MTK_PHY_LED1_10RX); + + pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led"); + if (IS_ERR(pinctrl)) { + dev_err(&phydev->mdio.bus->dev, "Failed to setup LED pins\n"); + return PTR_ERR(pinctrl); + } + + return 0; +} + +static int mt7988_phy_probe_shared(struct phy_device *phydev) +{ + struct mtk_socphy_shared_priv *priv = phydev->shared->priv; + void __iomem *boottrap; + struct device_node *np; + u32 reg; + + np = of_find_compatible_node(NULL, NULL, "mediatek,boottrap"); + if (!np) + return -ENOENT; + + boottrap = of_iomap(np, 0); + if (!boottrap) + return -ENOMEM; + + reg = readl(boottrap); + iounmap(boottrap); + + priv->boottrap = reg; + + return 0; +} + +static int mt7981_phy_probe(struct phy_device *phydev) +{ + return mt798x_phy_calibration(phydev); +} + +static int mt7988_phy_probe(struct phy_device *phydev) +{ + int err; + + err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0, + sizeof(struct mtk_socphy_shared_priv)); + if (err) + return err; + + if (phy_package_probe_once(phydev)) { + err = mt7988_phy_probe_shared(phydev); + if (err) + return err; + } + + mt7988_phy_setup_led(phydev); + + return mt798x_phy_calibration(phydev); +} + +static struct phy_driver mtk_socphy_driver[] = { + { + PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), + .name = "MediaTek MT7981 PHY", + .config_init = mt798x_phy_config_init, + .config_intr = genphy_no_config_intr, + .handle_interrupt = genphy_handle_interrupt_no_ack, + .probe = mt7981_phy_probe, + .suspend = genphy_suspend, + .resume = genphy_resume, + .read_page = mtk_socphy_read_page, + .write_page = mtk_socphy_write_page, + }, + { + PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988), + .name = "MediaTek MT7988 PHY", + .config_init = mt798x_phy_config_init, + .config_intr = genphy_no_config_intr, + .handle_interrupt = genphy_handle_interrupt_no_ack, + .probe = mt7988_phy_probe, + .suspend = genphy_suspend, + .resume = genphy_resume, + .read_page = mtk_socphy_read_page, + .write_page = mtk_socphy_write_page, + }, +}; + +module_phy_driver(mtk_socphy_driver); + +static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = { + { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) }, + { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) }, + { } +}; + +MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver"); +MODULE_AUTHOR("Daniel Golle "); +MODULE_AUTHOR("SkyLake Huang "); +MODULE_LICENSE("GPL"); + +MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl); diff --git a/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7981.c b/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7981.c new file mode 100644 index 00000000000..18abc578001 --- /dev/null +++ b/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7981.c @@ -0,0 +1,1048 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * The MT7981 driver based on Linux generic pinctrl binding. + * + * Copyright (C) 2020 MediaTek Inc. + * Author: Sam Shih + */ + +#include "pinctrl-moore.h" + +#define MT7981_PIN(_number, _name) \ + MTK_PIN(_number, _name, 0, _number, DRV_GRP4) + +#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, 0) + +#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, 1) + +static const struct mtk_pin_field_calc mt7981_pin_mode_range[] = { + PIN_FIELD(0, 56, 0x300, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt7981_pin_dir_range[] = { + PIN_FIELD(0, 56, 0x0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7981_pin_di_range[] = { + PIN_FIELD(0, 56, 0x200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7981_pin_do_range[] = { + PIN_FIELD(0, 56, 0x100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7981_pin_ies_range[] = { + PIN_FIELD_BASE(0, 0, 1, 0x10, 0x10, 1, 1), + PIN_FIELD_BASE(1, 1, 1, 0x10, 0x10, 0, 1), + PIN_FIELD_BASE(2, 2, 5, 0x20, 0x10, 6, 1), + PIN_FIELD_BASE(3, 3, 4, 0x20, 0x10, 6, 1), + PIN_FIELD_BASE(4, 4, 4, 0x20, 0x10, 2, 1), + PIN_FIELD_BASE(5, 5, 4, 0x20, 0x10, 1, 1), + PIN_FIELD_BASE(6, 6, 4, 0x20, 0x10, 3, 1), + PIN_FIELD_BASE(7, 7, 4, 0x20, 0x10, 0, 1), + PIN_FIELD_BASE(8, 8, 4, 0x20, 0x10, 4, 1), + + PIN_FIELD_BASE(9, 9, 5, 0x20, 0x10, 9, 1), + PIN_FIELD_BASE(10, 10, 5, 0x20, 0x10, 8, 1), + PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1), + PIN_FIELD_BASE(12, 12, 5, 0x20, 0x10, 7, 1), + PIN_FIELD_BASE(13, 13, 5, 0x20, 0x10, 11, 1), + + PIN_FIELD_BASE(14, 14, 4, 0x20, 0x10, 8, 1), + + PIN_FIELD_BASE(15, 15, 2, 0x20, 0x10, 0, 1), + PIN_FIELD_BASE(16, 16, 2, 0x20, 0x10, 1, 1), + PIN_FIELD_BASE(17, 17, 2, 0x20, 0x10, 5, 1), + PIN_FIELD_BASE(18, 18, 2, 0x20, 0x10, 4, 1), + PIN_FIELD_BASE(19, 19, 2, 0x20, 0x10, 2, 1), + PIN_FIELD_BASE(20, 20, 2, 0x20, 0x10, 3, 1), + PIN_FIELD_BASE(21, 21, 2, 0x20, 0x10, 6, 1), + PIN_FIELD_BASE(22, 22, 2, 0x20, 0x10, 7, 1), + PIN_FIELD_BASE(23, 23, 2, 0x20, 0x10, 10, 1), + PIN_FIELD_BASE(24, 24, 2, 0x20, 0x10, 9, 1), + PIN_FIELD_BASE(25, 25, 2, 0x20, 0x10, 8, 1), + + PIN_FIELD_BASE(26, 26, 5, 0x20, 0x10, 0, 1), + PIN_FIELD_BASE(27, 27, 5, 0x20, 0x10, 4, 1), + PIN_FIELD_BASE(28, 28, 5, 0x20, 0x10, 3, 1), + PIN_FIELD_BASE(29, 29, 5, 0x20, 0x10, 1, 1), + PIN_FIELD_BASE(30, 30, 5, 0x20, 0x10, 2, 1), + PIN_FIELD_BASE(31, 31, 5, 0x20, 0x10, 5, 1), + + PIN_FIELD_BASE(32, 32, 1, 0x10, 0x10, 2, 1), + PIN_FIELD_BASE(33, 33, 1, 0x10, 0x10, 3, 1), + + PIN_FIELD_BASE(34, 34, 4, 0x20, 0x10, 5, 1), + PIN_FIELD_BASE(35, 35, 4, 0x20, 0x10, 7, 1), + + PIN_FIELD_BASE(36, 36, 3, 0x10, 0x10, 2, 1), + PIN_FIELD_BASE(37, 37, 3, 0x10, 0x10, 3, 1), + PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 0, 1), + PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 1, 1), + + PIN_FIELD_BASE(40, 40, 7, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(41, 41, 7, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, 7, 0x30, 0x10, 9, 1), + PIN_FIELD_BASE(43, 43, 7, 0x30, 0x10, 7, 1), + PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1), + PIN_FIELD_BASE(45, 45, 7, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(46, 46, 7, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(47, 47, 7, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(48, 48, 7, 0x30, 0x10, 6, 1), + PIN_FIELD_BASE(49, 49, 7, 0x30, 0x10, 2, 1), + + PIN_FIELD_BASE(50, 50, 6, 0x10, 0x10, 0, 1), + PIN_FIELD_BASE(51, 51, 6, 0x10, 0x10, 2, 1), + PIN_FIELD_BASE(52, 52, 6, 0x10, 0x10, 3, 1), + PIN_FIELD_BASE(53, 53, 6, 0x10, 0x10, 4, 1), + PIN_FIELD_BASE(54, 54, 6, 0x10, 0x10, 5, 1), + PIN_FIELD_BASE(55, 55, 6, 0x10, 0x10, 6, 1), + PIN_FIELD_BASE(56, 56, 6, 0x10, 0x10, 1, 1), +}; + +static const struct mtk_pin_field_calc mt7981_pin_smt_range[] = { + PIN_FIELD_BASE(0, 0, 1, 0x60, 0x10, 1, 1), + PIN_FIELD_BASE(1, 1, 1, 0x60, 0x10, 0, 1), + PIN_FIELD_BASE(2, 2, 5, 0x90, 0x10, 6, 1), + PIN_FIELD_BASE(3, 3, 4, 0x80, 0x10, 6, 1), + PIN_FIELD_BASE(4, 4, 4, 0x80, 0x10, 2, 1), + PIN_FIELD_BASE(5, 5, 4, 0x80, 0x10, 1, 1), + PIN_FIELD_BASE(6, 6, 4, 0x80, 0x10, 3, 1), + PIN_FIELD_BASE(7, 7, 4, 0x80, 0x10, 0, 1), + PIN_FIELD_BASE(8, 8, 4, 0x80, 0x10, 4, 1), + + PIN_FIELD_BASE(9, 9, 5, 0x90, 0x10, 9, 1), + PIN_FIELD_BASE(10, 10, 5, 0x90, 0x10, 8, 1), + PIN_FIELD_BASE(11, 11, 5, 0x90, 0x10, 10, 1), + PIN_FIELD_BASE(12, 12, 5, 0x90, 0x10, 7, 1), + PIN_FIELD_BASE(13, 13, 5, 0x90, 0x10, 11, 1), + + PIN_FIELD_BASE(14, 14, 4, 0x80, 0x10, 8, 1), + + PIN_FIELD_BASE(15, 15, 2, 0x90, 0x10, 0, 1), + PIN_FIELD_BASE(16, 16, 2, 0x90, 0x10, 1, 1), + PIN_FIELD_BASE(17, 17, 2, 0x90, 0x10, 5, 1), + PIN_FIELD_BASE(18, 18, 2, 0x90, 0x10, 4, 1), + PIN_FIELD_BASE(19, 19, 2, 0x90, 0x10, 2, 1), + PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1), + PIN_FIELD_BASE(21, 21, 2, 0x90, 0x10, 6, 1), + PIN_FIELD_BASE(22, 22, 2, 0x90, 0x10, 7, 1), + PIN_FIELD_BASE(23, 23, 2, 0x90, 0x10, 10, 1), + PIN_FIELD_BASE(24, 24, 2, 0x90, 0x10, 9, 1), + PIN_FIELD_BASE(25, 25, 2, 0x90, 0x10, 8, 1), + + PIN_FIELD_BASE(26, 26, 5, 0x90, 0x10, 0, 1), + PIN_FIELD_BASE(27, 27, 5, 0x90, 0x10, 4, 1), + PIN_FIELD_BASE(28, 28, 5, 0x90, 0x10, 3, 1), + PIN_FIELD_BASE(29, 29, 5, 0x90, 0x10, 1, 1), + PIN_FIELD_BASE(30, 30, 5, 0x90, 0x10, 2, 1), + PIN_FIELD_BASE(31, 31, 5, 0x90, 0x10, 5, 1), + + PIN_FIELD_BASE(32, 32, 1, 0x60, 0x10, 2, 1), + PIN_FIELD_BASE(33, 33, 1, 0x60, 0x10, 3, 1), + + PIN_FIELD_BASE(34, 34, 4, 0x80, 0x10, 5, 1), + PIN_FIELD_BASE(35, 35, 4, 0x80, 0x10, 7, 1), + + PIN_FIELD_BASE(36, 36, 3, 0x60, 0x10, 2, 1), + PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 3, 1), + PIN_FIELD_BASE(38, 38, 3, 0x60, 0x10, 0, 1), + PIN_FIELD_BASE(39, 39, 3, 0x60, 0x10, 1, 1), + + PIN_FIELD_BASE(40, 40, 7, 0x70, 0x10, 1, 1), + PIN_FIELD_BASE(41, 41, 7, 0x70, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, 7, 0x70, 0x10, 9, 1), + PIN_FIELD_BASE(43, 43, 7, 0x70, 0x10, 7, 1), + PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1), + PIN_FIELD_BASE(45, 45, 7, 0x70, 0x10, 3, 1), + PIN_FIELD_BASE(46, 46, 7, 0x70, 0x10, 4, 1), + PIN_FIELD_BASE(47, 47, 7, 0x70, 0x10, 5, 1), + PIN_FIELD_BASE(48, 48, 7, 0x70, 0x10, 6, 1), + PIN_FIELD_BASE(49, 49, 7, 0x70, 0x10, 2, 1), + + PIN_FIELD_BASE(50, 50, 6, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(51, 51, 6, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(52, 52, 6, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(53, 53, 6, 0x50, 0x10, 4, 1), + PIN_FIELD_BASE(54, 54, 6, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(55, 55, 6, 0x50, 0x10, 6, 1), + PIN_FIELD_BASE(56, 56, 6, 0x50, 0x10, 1, 1), +}; + +static const struct mtk_pin_field_calc mt7981_pin_pu_range[] = { + PIN_FIELD_BASE(40, 40, 7, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(41, 41, 7, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, 7, 0x50, 0x10, 9, 1), + PIN_FIELD_BASE(43, 43, 7, 0x50, 0x10, 7, 1), + PIN_FIELD_BASE(44, 44, 7, 0x50, 0x10, 8, 1), + PIN_FIELD_BASE(45, 45, 7, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(46, 46, 7, 0x50, 0x10, 4, 1), + PIN_FIELD_BASE(47, 47, 7, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(48, 48, 7, 0x50, 0x10, 6, 1), + PIN_FIELD_BASE(49, 49, 7, 0x50, 0x10, 2, 1), + + PIN_FIELD_BASE(50, 50, 6, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(51, 51, 6, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(52, 52, 6, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(53, 53, 6, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(54, 54, 6, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(55, 55, 6, 0x30, 0x10, 6, 1), + PIN_FIELD_BASE(56, 56, 6, 0x30, 0x10, 1, 1), +}; + +static const struct mtk_pin_field_calc mt7981_pin_pd_range[] = { + PIN_FIELD_BASE(40, 40, 7, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(41, 41, 7, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, 7, 0x40, 0x10, 9, 1), + PIN_FIELD_BASE(43, 43, 7, 0x40, 0x10, 7, 1), + PIN_FIELD_BASE(44, 44, 7, 0x40, 0x10, 8, 1), + PIN_FIELD_BASE(45, 45, 7, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(46, 46, 7, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(47, 47, 7, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(48, 48, 7, 0x40, 0x10, 6, 1), + PIN_FIELD_BASE(49, 49, 7, 0x40, 0x10, 2, 1), + + PIN_FIELD_BASE(50, 50, 6, 0x20, 0x10, 0, 1), + PIN_FIELD_BASE(51, 51, 6, 0x20, 0x10, 2, 1), + PIN_FIELD_BASE(52, 52, 6, 0x20, 0x10, 3, 1), + PIN_FIELD_BASE(53, 53, 6, 0x20, 0x10, 4, 1), + PIN_FIELD_BASE(54, 54, 6, 0x20, 0x10, 5, 1), + PIN_FIELD_BASE(55, 55, 6, 0x20, 0x10, 6, 1), + PIN_FIELD_BASE(56, 56, 6, 0x20, 0x10, 1, 1), +}; + +static const struct mtk_pin_field_calc mt7981_pin_drv_range[] = { + PIN_FIELD_BASE(0, 0, 1, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(1, 1, 1, 0x00, 0x10, 0, 3), + + PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 18, 3), + + PIN_FIELD_BASE(3, 3, 4, 0x00, 0x10, 18, 1), + PIN_FIELD_BASE(4, 4, 4, 0x00, 0x10, 6, 1), + PIN_FIELD_BASE(5, 5, 4, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(6, 6, 4, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 12, 3), + + PIN_FIELD_BASE(9, 9, 5, 0x00, 0x10, 27, 3), + PIN_FIELD_BASE(10, 10, 5, 0x00, 0x10, 24, 3), + PIN_FIELD_BASE(11, 11, 5, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(12, 12, 5, 0x00, 0x10, 21, 3), + PIN_FIELD_BASE(13, 13, 5, 0x00, 0x10, 3, 3), + + PIN_FIELD_BASE(14, 14, 4, 0x00, 0x10, 27, 3), + + PIN_FIELD_BASE(15, 15, 2, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(16, 16, 2, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(17, 17, 2, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(18, 18, 2, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(19, 19, 2, 0x00, 0x10, 6, 3), + PIN_FIELD_BASE(20, 20, 2, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(21, 21, 2, 0x00, 0x10, 18, 3), + PIN_FIELD_BASE(22, 22, 2, 0x00, 0x10, 21, 3), + PIN_FIELD_BASE(23, 23, 2, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(24, 24, 2, 0x00, 0x10, 27, 3), + PIN_FIELD_BASE(25, 25, 2, 0x00, 0x10, 24, 3), + + PIN_FIELD_BASE(26, 26, 5, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(27, 27, 5, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(28, 28, 5, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(29, 29, 5, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(30, 30, 5, 0x00, 0x10, 6, 3), + PIN_FIELD_BASE(31, 31, 5, 0x00, 0x10, 15, 3), + + PIN_FIELD_BASE(32, 32, 1, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(33, 33, 1, 0x00, 0x10, 12, 3), + + PIN_FIELD_BASE(34, 34, 4, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(35, 35, 4, 0x00, 0x10, 21, 3), + + PIN_FIELD_BASE(36, 36, 3, 0x00, 0x10, 6, 3), + PIN_FIELD_BASE(37, 37, 3, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(38, 38, 3, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(39, 39, 3, 0x00, 0x10, 3, 3), + + PIN_FIELD_BASE(40, 40, 7, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(41, 41, 7, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(42, 42, 7, 0x00, 0x10, 27, 3), + PIN_FIELD_BASE(43, 43, 7, 0x00, 0x10, 21, 3), + PIN_FIELD_BASE(44, 44, 7, 0x00, 0x10, 24, 3), + PIN_FIELD_BASE(45, 45, 7, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(46, 46, 7, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(47, 47, 7, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(48, 48, 7, 0x00, 0x10, 18, 3), + PIN_FIELD_BASE(49, 49, 7, 0x00, 0x10, 6, 3), + + PIN_FIELD_BASE(50, 50, 6, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(51, 51, 6, 0x00, 0x10, 6, 3), + PIN_FIELD_BASE(52, 52, 6, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(53, 53, 6, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(54, 54, 6, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(55, 55, 6, 0x00, 0x10, 18, 3), + PIN_FIELD_BASE(56, 56, 6, 0x00, 0x10, 3, 3), +}; + +static const struct mtk_pin_field_calc mt7981_pin_pupd_range[] = { + PIN_FIELD_BASE(0, 0, 1, 0x20, 0x10, 1, 1), + PIN_FIELD_BASE(1, 1, 1, 0x20, 0x10, 0, 1), + PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 6, 1), + PIN_FIELD_BASE(3, 3, 4, 0x30, 0x10, 6, 1), + PIN_FIELD_BASE(4, 4, 4, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(5, 5, 4, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(6, 6, 4, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 4, 1), + + PIN_FIELD_BASE(9, 9, 5, 0x30, 0x10, 9, 1), + PIN_FIELD_BASE(10, 10, 5, 0x30, 0x10, 8, 1), + PIN_FIELD_BASE(11, 11, 5, 0x30, 0x10, 10, 1), + PIN_FIELD_BASE(12, 12, 5, 0x30, 0x10, 7, 1), + PIN_FIELD_BASE(13, 13, 5, 0x30, 0x10, 11, 1), + + PIN_FIELD_BASE(14, 14, 4, 0x30, 0x10, 8, 1), + + PIN_FIELD_BASE(15, 15, 2, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(16, 16, 2, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(17, 17, 2, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(18, 18, 2, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(19, 19, 2, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1), + PIN_FIELD_BASE(21, 21, 2, 0x30, 0x10, 6, 1), + PIN_FIELD_BASE(22, 22, 2, 0x30, 0x10, 7, 1), + PIN_FIELD_BASE(23, 23, 2, 0x30, 0x10, 10, 1), + PIN_FIELD_BASE(24, 24, 2, 0x30, 0x10, 9, 1), + PIN_FIELD_BASE(25, 25, 2, 0x30, 0x10, 8, 1), + + PIN_FIELD_BASE(26, 26, 5, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(27, 27, 5, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(28, 28, 5, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(29, 29, 5, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(30, 30, 5, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(31, 31, 5, 0x30, 0x10, 5, 1), + + PIN_FIELD_BASE(32, 32, 1, 0x20, 0x10, 2, 1), + PIN_FIELD_BASE(33, 33, 1, 0x20, 0x10, 3, 1), + + PIN_FIELD_BASE(34, 34, 4, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(35, 35, 4, 0x30, 0x10, 7, 1), + + PIN_FIELD_BASE(36, 36, 3, 0x20, 0x10, 2, 1), + PIN_FIELD_BASE(37, 37, 3, 0x20, 0x10, 3, 1), + PIN_FIELD_BASE(38, 38, 3, 0x20, 0x10, 0, 1), + PIN_FIELD_BASE(39, 39, 3, 0x20, 0x10, 1, 1), +}; + +static const struct mtk_pin_field_calc mt7981_pin_r0_range[] = { + PIN_FIELD_BASE(0, 0, 1, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(1, 1, 1, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(2, 2, 5, 0x40, 0x10, 6, 1), + PIN_FIELD_BASE(3, 3, 4, 0x40, 0x10, 6, 1), + PIN_FIELD_BASE(4, 4, 4, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(5, 5, 4, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(6, 6, 4, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1), + + PIN_FIELD_BASE(9, 9, 5, 0x40, 0x10, 9, 1), + PIN_FIELD_BASE(10, 10, 5, 0x40, 0x10, 8, 1), + PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1), + PIN_FIELD_BASE(12, 12, 5, 0x40, 0x10, 7, 1), + PIN_FIELD_BASE(13, 13, 5, 0x40, 0x10, 11, 1), + + PIN_FIELD_BASE(14, 14, 4, 0x40, 0x10, 8, 1), + + PIN_FIELD_BASE(15, 15, 2, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(16, 16, 2, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(17, 17, 2, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(18, 18, 2, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(19, 19, 2, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(20, 20, 2, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(21, 21, 2, 0x40, 0x10, 6, 1), + PIN_FIELD_BASE(22, 22, 2, 0x40, 0x10, 7, 1), + PIN_FIELD_BASE(23, 23, 2, 0x40, 0x10, 10, 1), + PIN_FIELD_BASE(24, 24, 2, 0x40, 0x10, 9, 1), + PIN_FIELD_BASE(25, 25, 2, 0x40, 0x10, 8, 1), + + PIN_FIELD_BASE(26, 26, 5, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(27, 27, 5, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(28, 28, 5, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(29, 29, 5, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(30, 30, 5, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(31, 31, 5, 0x40, 0x10, 5, 1), + + PIN_FIELD_BASE(32, 32, 1, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(33, 33, 1, 0x30, 0x10, 3, 1), + + PIN_FIELD_BASE(34, 34, 4, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(35, 35, 4, 0x40, 0x10, 7, 1), + + PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(38, 38, 3, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(39, 39, 3, 0x30, 0x10, 1, 1), +}; + +static const struct mtk_pin_field_calc mt7981_pin_r1_range[] = { + PIN_FIELD_BASE(0, 0, 1, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(1, 1, 1, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 6, 1), + PIN_FIELD_BASE(3, 3, 4, 0x50, 0x10, 6, 1), + PIN_FIELD_BASE(4, 4, 4, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(5, 5, 4, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(6, 6, 4, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(7, 7, 4, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(8, 8, 4, 0x50, 0x10, 4, 1), + + PIN_FIELD_BASE(9, 9, 5, 0x50, 0x10, 9, 1), + PIN_FIELD_BASE(10, 10, 5, 0x50, 0x10, 8, 1), + PIN_FIELD_BASE(11, 11, 5, 0x50, 0x10, 10, 1), + PIN_FIELD_BASE(12, 12, 5, 0x50, 0x10, 7, 1), + PIN_FIELD_BASE(13, 13, 5, 0x50, 0x10, 11, 1), + + PIN_FIELD_BASE(14, 14, 4, 0x50, 0x10, 8, 1), + + PIN_FIELD_BASE(15, 15, 2, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(16, 16, 2, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(17, 17, 2, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(18, 18, 2, 0x50, 0x10, 4, 1), + PIN_FIELD_BASE(19, 19, 2, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(20, 20, 2, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(21, 21, 2, 0x50, 0x10, 6, 1), + PIN_FIELD_BASE(22, 22, 2, 0x50, 0x10, 7, 1), + PIN_FIELD_BASE(23, 23, 2, 0x50, 0x10, 10, 1), + PIN_FIELD_BASE(24, 24, 2, 0x50, 0x10, 9, 1), + PIN_FIELD_BASE(25, 25, 2, 0x50, 0x10, 8, 1), + + PIN_FIELD_BASE(26, 26, 5, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(27, 27, 5, 0x50, 0x10, 4, 1), + PIN_FIELD_BASE(28, 28, 5, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(29, 29, 5, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(30, 30, 5, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(31, 31, 5, 0x50, 0x10, 5, 1), + + PIN_FIELD_BASE(32, 32, 1, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(33, 33, 1, 0x40, 0x10, 3, 1), + + PIN_FIELD_BASE(34, 34, 4, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(35, 35, 4, 0x50, 0x10, 7, 1), + + PIN_FIELD_BASE(36, 36, 3, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(37, 37, 3, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(38, 38, 3, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(39, 39, 3, 0x40, 0x10, 1, 1), +}; + +static const unsigned int mt7981_pull_type[] = { + MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/ + MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/ + MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/ + MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/ + MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/ + MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/ + MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/ + MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/ + MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/ + MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/ + MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/ + MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/ + MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/ + MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/ + MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/ + MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/ + MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/ + MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/ + MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/ + MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/ + MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/ + MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/ + MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/ + MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/ + MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/ + MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/ + MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/ + MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/ + MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/ + MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/ + MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/ + MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/ + MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/ + MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/ + MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/ + MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/ + MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/ + MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/ + MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/ + MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/ + MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/ + MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/ + MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/ + MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/ + MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/ + MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/ + MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/ + MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/ + MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/ + MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/ + MTK_PULL_PU_PD_TYPE,/*100*/ +}; + +static const struct mtk_pin_reg_calc mt7981_reg_cals[] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7981_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7981_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7981_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7981_pin_do_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7981_pin_smt_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7981_pin_ies_range), + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7981_pin_pu_range), + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7981_pin_pd_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7981_pin_drv_range), + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7981_pin_pupd_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7981_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7981_pin_r1_range), +}; + +static const struct mtk_pin_desc mt7981_pins[] = { + MT7981_PIN(0, "GPIO_WPS"), + MT7981_PIN(1, "GPIO_RESET"), + MT7981_PIN(2, "SYS_WATCHDOG"), + MT7981_PIN(3, "PCIE_PERESET_N"), + MT7981_PIN(4, "JTAG_JTDO"), + MT7981_PIN(5, "JTAG_JTDI"), + MT7981_PIN(6, "JTAG_JTMS"), + MT7981_PIN(7, "JTAG_JTCLK"), + MT7981_PIN(8, "JTAG_JTRST_N"), + MT7981_PIN(9, "WO_JTAG_JTDO"), + MT7981_PIN(10, "WO_JTAG_JTDI"), + MT7981_PIN(11, "WO_JTAG_JTMS"), + MT7981_PIN(12, "WO_JTAG_JTCLK"), + MT7981_PIN(13, "WO_JTAG_JTRST_N"), + MT7981_PIN(14, "USB_VBUS"), + MT7981_PIN(15, "PWM0"), + MT7981_PIN(16, "SPI0_CLK"), + MT7981_PIN(17, "SPI0_MOSI"), + MT7981_PIN(18, "SPI0_MISO"), + MT7981_PIN(19, "SPI0_CS"), + MT7981_PIN(20, "SPI0_HOLD"), + MT7981_PIN(21, "SPI0_WP"), + MT7981_PIN(22, "SPI1_CLK"), + MT7981_PIN(23, "SPI1_MOSI"), + MT7981_PIN(24, "SPI1_MISO"), + MT7981_PIN(25, "SPI1_CS"), + MT7981_PIN(26, "SPI2_CLK"), + MT7981_PIN(27, "SPI2_MOSI"), + MT7981_PIN(28, "SPI2_MISO"), + MT7981_PIN(29, "SPI2_CS"), + MT7981_PIN(30, "SPI2_HOLD"), + MT7981_PIN(31, "SPI2_WP"), + MT7981_PIN(32, "UART0_RXD"), + MT7981_PIN(33, "UART0_TXD"), + MT7981_PIN(34, "PCIE_CLK_REQ"), + MT7981_PIN(35, "PCIE_WAKE_N"), + MT7981_PIN(36, "SMI_MDC"), + MT7981_PIN(37, "SMI_MDIO"), + MT7981_PIN(38, "GBE_INT"), + MT7981_PIN(39, "GBE_RESET"), + MT7981_PIN(40, "WF_DIG_RESETB"), + MT7981_PIN(41, "WF_CBA_RESETB"), + MT7981_PIN(42, "WF_XO_REQ"), + MT7981_PIN(43, "WF_TOP_CLK"), + MT7981_PIN(44, "WF_TOP_DATA"), + MT7981_PIN(45, "WF_HB1"), + MT7981_PIN(46, "WF_HB2"), + MT7981_PIN(47, "WF_HB3"), + MT7981_PIN(48, "WF_HB4"), + MT7981_PIN(49, "WF_HB0"), + MT7981_PIN(50, "WF_HB0_B"), + MT7981_PIN(51, "WF_HB5"), + MT7981_PIN(52, "WF_HB6"), + MT7981_PIN(53, "WF_HB7"), + MT7981_PIN(54, "WF_HB8"), + MT7981_PIN(55, "WF_HB9"), + MT7981_PIN(56, "WF_HB10"), +}; + +/* List all groups consisting of these pins dedicated to the enablement of + * certain hardware block and the corresponding mode for all of the pins. + * The hardware probably has multiple combinations of these pinouts. + */ + +/* WA_AICE */ +static int mt7981_wa_aice1_pins[] = { 0, 1, }; +static int mt7981_wa_aice1_funcs[] = { 2, 2, }; + +static int mt7981_wa_aice2_pins[] = { 0, 1, }; +static int mt7981_wa_aice2_funcs[] = { 3, 3, }; + +static int mt7981_wa_aice3_pins[] = { 28, 29, }; +static int mt7981_wa_aice3_funcs[] = { 3, 3, }; + +static int mt7981_wm_aice1_pins[] = { 9, 10, }; +static int mt7981_wm_aice1_funcs[] = { 2, 2, }; + +static int mt7981_wm_aice2_pins[] = { 30, 31, }; +static int mt7981_wm_aice2_funcs[] = { 5, 5, }; + +/* WM_UART */ +static int mt7981_wm_uart_0_pins[] = { 0, 1, }; +static int mt7981_wm_uart_0_funcs[] = { 5, 5, }; + +static int mt7981_wm_uart_1_pins[] = { 20, 21, }; +static int mt7981_wm_uart_1_funcs[] = { 4, 4, }; + +static int mt7981_wm_uart_2_pins[] = { 30, 31, }; +static int mt7981_wm_uart_2_funcs[] = { 3, 3, }; + +/* DFD */ +static int mt7981_dfd_pins[] = { 0, 1, 4, 5, }; +static int mt7981_dfd_funcs[] = { 5, 5, 6, 6, }; + +/* SYS_WATCHDOG */ +static int mt7981_watchdog_pins[] = { 2, }; +static int mt7981_watchdog_funcs[] = { 1, }; + +static int mt7981_watchdog1_pins[] = { 13, }; +static int mt7981_watchdog1_funcs[] = { 5, }; + +/* PCIE_PERESET_N */ +static int mt7981_pcie_pereset_pins[] = { 3, }; +static int mt7981_pcie_pereset_funcs[] = { 1, }; + +/* JTAG */ +static int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, }; +static int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, }; + +/* WM_JTAG */ +static int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, }; +static int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, }; + +static int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, }; +static int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; + +/* WO0_JTAG */ +static int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, }; +static int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, }; + +static int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, }; +static int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; + +/* UART2 */ +static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, }; +static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, }; + +/* GBE_LED0 */ +static int mt7981_gbe_led0_pins[] = { 8, }; +static int mt7981_gbe_led0_funcs[] = { 3, }; + +/* PTA_EXT */ +static int mt7981_pta_ext_0_pins[] = { 4, 5, 6, }; +static int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, }; + +static int mt7981_pta_ext_1_pins[] = { 22, 23, 24, }; +static int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, }; + +/* PWM2 */ +static int mt7981_pwm2_pins[] = { 7, }; +static int mt7981_pwm2_funcs[] = { 4, }; + +/* NET_WO0_UART_TXD */ +static int mt7981_net_wo0_uart_txd_0_pins[] = { 8, }; +static int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, }; + +static int mt7981_net_wo0_uart_txd_1_pins[] = { 14, }; +static int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, }; + +static int mt7981_net_wo0_uart_txd_2_pins[] = { 15, }; +static int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, }; + +/* SPI1 */ +static int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, }; +static int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, }; + +/* I2C */ +static int mt7981_i2c0_0_pins[] = { 6, 7, }; +static int mt7981_i2c0_0_funcs[] = { 6, 6, }; + +static int mt7981_i2c0_1_pins[] = { 30, 31, }; +static int mt7981_i2c0_1_funcs[] = { 4, 4, }; + +static int mt7981_i2c0_2_pins[] = { 36, 37, }; +static int mt7981_i2c0_2_funcs[] = { 2, 2, }; + +static int mt7981_u2_phy_i2c_pins[] = { 30, 31, }; +static int mt7981_u2_phy_i2c_funcs[] = { 6, 6, }; + +static int mt7981_u3_phy_i2c_pins[] = { 32, 33, }; +static int mt7981_u3_phy_i2c_funcs[] = { 3, 3, }; + +static int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, }; +static int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, }; + +static int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, }; +static int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, }; + +/* DFD_NTRST */ +static int mt7981_dfd_ntrst_pins[] = { 8, }; +static int mt7981_dfd_ntrst_funcs[] = { 6, }; + +/* PWM0 */ +static int mt7981_pwm0_0_pins[] = { 13, }; +static int mt7981_pwm0_0_funcs[] = { 2, }; + +static int mt7981_pwm0_1_pins[] = { 15, }; +static int mt7981_pwm0_1_funcs[] = { 1, }; + +/* PWM1 */ +static int mt7981_pwm1_0_pins[] = { 14, }; +static int mt7981_pwm1_0_funcs[] = { 2, }; + +static int mt7981_pwm1_1_pins[] = { 15, }; +static int mt7981_pwm1_1_funcs[] = { 3, }; + +/* GBE_LED1 */ +static int mt7981_gbe_led1_pins[] = { 13, }; +static int mt7981_gbe_led1_funcs[] = { 3, }; + +/* PCM */ +static int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 }; +static int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, }; + +/* UDI */ +static int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, }; +static int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, }; + +/* DRV_VBUS */ +static int mt7981_drv_vbus_pins[] = { 14, }; +static int mt7981_drv_vbus_funcs[] = { 1, }; + +/* EMMC */ +static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, }; +static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; + +/* SNFI */ +static int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, }; +static int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, }; + +/* SPI0 */ +static int mt7981_spi0_pins[] = { 16, 17, 18, 19, }; +static int mt7981_spi0_funcs[] = { 1, 1, 1, 1, }; + +/* SPI0 */ +static int mt7981_spi0_wp_hold_pins[] = { 20, 21, }; +static int mt7981_spi0_wp_hold_funcs[] = { 1, 1, }; + +/* SPI1 */ +static int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, }; +static int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, }; + +/* SPI2 */ +static int mt7981_spi2_pins[] = { 26, 27, 28, 29, }; +static int mt7981_spi2_funcs[] = { 1, 1, 1, 1, }; + +/* SPI2 */ +static int mt7981_spi2_wp_hold_pins[] = { 30, 31, }; +static int mt7981_spi2_wp_hold_funcs[] = { 1, 1, }; + +/* UART1 */ +static int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, }; +static int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, }; + +static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, }; +static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, }; + +/* UART2 */ +static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, }; +static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, }; + +/* UART0 */ +static int mt7981_uart0_pins[] = { 32, 33, }; +static int mt7981_uart0_funcs[] = { 1, 1, }; + +/* PCIE_CLK_REQ */ +static int mt7981_pcie_clk_pins[] = { 34, }; +static int mt7981_pcie_clk_funcs[] = { 2, }; + +/* PCIE_WAKE_N */ +static int mt7981_pcie_wake_pins[] = { 35, }; +static int mt7981_pcie_wake_funcs[] = { 2, }; + +/* MDC_MDIO */ +static int mt7981_smi_mdc_mdio_pins[] = { 36, 37, }; +static int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, }; + +static int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, }; +static int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, }; + +/* WF0_MODE1 */ +static int mt7981_wf0_mode1_pins[] = { 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56 }; +static int mt7981_wf0_mode1_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; + +/* WF0_MODE3 */ +static int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 }; +static int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 }; + +/* WF2G_LED */ +static int mt7981_wf2g_led0_pins[] = { 30, }; +static int mt7981_wf2g_led0_funcs[] = { 2, }; + +static int mt7981_wf2g_led1_pins[] = { 34, }; +static int mt7981_wf2g_led1_funcs[] = { 1, }; + +/* WF5G_LED */ +static int mt7981_wf5g_led0_pins[] = { 31, }; +static int mt7981_wf5g_led0_funcs[] = { 2, }; + +static int mt7981_wf5g_led1_pins[] = { 35, }; +static int mt7981_wf5g_led1_funcs[] = { 1, }; + +/* MT7531_INT */ +static int mt7981_mt7531_int_pins[] = { 38, }; +static int mt7981_mt7531_int_funcs[] = { 1, }; + +/* ANT_SEL */ +static int mt7981_ant_sel_pins[] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 }; +static int mt7981_ant_sel_funcs[] = { 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 }; + +static const struct group_desc mt7981_groups[] = { + /* @GPIO(0,1): WA_AICE(2) */ + PINCTRL_PIN_GROUP("wa_aice1", mt7981_wa_aice1), + /* @GPIO(0,1): WA_AICE(3) */ + PINCTRL_PIN_GROUP("wa_aice2", mt7981_wa_aice2), + /* @GPIO(0,1): WM_UART(5) */ + PINCTRL_PIN_GROUP("wm_uart_0", mt7981_wm_uart_0), + /* @GPIO(0,1,4,5): DFD(6) */ + PINCTRL_PIN_GROUP("dfd", mt7981_dfd), + /* @GPIO(2): SYS_WATCHDOG(1) */ + PINCTRL_PIN_GROUP("watchdog", mt7981_watchdog), + /* @GPIO(3): PCIE_PERESET_N(1) */ + PINCTRL_PIN_GROUP("pcie_pereset", mt7981_pcie_pereset), + /* @GPIO(4,8) JTAG(1) */ + PINCTRL_PIN_GROUP("jtag", mt7981_jtag), + /* @GPIO(4,8) WM_JTAG(2) */ + PINCTRL_PIN_GROUP("wm_jtag_0", mt7981_wm_jtag_0), + /* @GPIO(9,13) WO0_JTAG(1) */ + PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0), + /* @GPIO(4,7) WM_JTAG(3) */ + PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0), + /* @GPIO(8) GBE_LED0(3) */ + PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0), + /* @GPIO(4,6) PTA_EXT(4) */ + PINCTRL_PIN_GROUP("pta_ext_0", mt7981_pta_ext_0), + /* @GPIO(7) PWM2(4) */ + PINCTRL_PIN_GROUP("pwm2", mt7981_pwm2), + /* @GPIO(8) NET_WO0_UART_TXD(4) */ + PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7981_net_wo0_uart_txd_0), + /* @GPIO(4,7) SPI1(5) */ + PINCTRL_PIN_GROUP("spi1_0", mt7981_spi1_0), + /* @GPIO(6,7) I2C(5) */ + PINCTRL_PIN_GROUP("i2c0_0", mt7981_i2c0_0), + /* @GPIO(0,1,4,5): DFD_NTRST(6) */ + PINCTRL_PIN_GROUP("dfd_ntrst", mt7981_dfd_ntrst), + /* @GPIO(9,10): WM_AICE(2) */ + PINCTRL_PIN_GROUP("wm_aice1", mt7981_wm_aice1), + /* @GPIO(13): PWM0(2) */ + PINCTRL_PIN_GROUP("pwm0_0", mt7981_pwm0_0), + /* @GPIO(15): PWM0(1) */ + PINCTRL_PIN_GROUP("pwm0_1", mt7981_pwm0_1), + /* @GPIO(14): PWM1(2) */ + PINCTRL_PIN_GROUP("pwm1_0", mt7981_pwm1_0), + /* @GPIO(15): PWM1(3) */ + PINCTRL_PIN_GROUP("pwm1_1", mt7981_pwm1_1), + /* @GPIO(14) NET_WO0_UART_TXD(3) */ + PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7981_net_wo0_uart_txd_1), + /* @GPIO(15) NET_WO0_UART_TXD(4) */ + PINCTRL_PIN_GROUP("net_wo0_uart_txd_2", mt7981_net_wo0_uart_txd_2), + /* @GPIO(13) GBE_LED0(3) */ + PINCTRL_PIN_GROUP("gbe_led1", mt7981_gbe_led1), + /* @GPIO(9,13) PCM(4) */ + PINCTRL_PIN_GROUP("pcm", mt7981_pcm), + /* @GPIO(13): SYS_WATCHDOG1(5) */ + PINCTRL_PIN_GROUP("watchdog1", mt7981_watchdog1), + /* @GPIO(9,13) UDI(4) */ + PINCTRL_PIN_GROUP("udi", mt7981_udi), + /* @GPIO(14) DRV_VBUS(1) */ + PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus), + /* @GPIO(15,25): EMMC(2) */ + PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45), + /* @GPIO(16,21): SNFI(3) */ + PINCTRL_PIN_GROUP("snfi", mt7981_snfi), + /* @GPIO(16,19): SPI0(1) */ + PINCTRL_PIN_GROUP("spi0", mt7981_spi0), + /* @GPIO(20,21): SPI0(1) */ + PINCTRL_PIN_GROUP("spi0_wp_hold", mt7981_spi0_wp_hold), + /* @GPIO(22,25) SPI1(1) */ + PINCTRL_PIN_GROUP("spi1_1", mt7981_spi1_1), + /* @GPIO(26,29): SPI2(1) */ + PINCTRL_PIN_GROUP("spi2", mt7981_spi2), + /* @GPIO(30,31): SPI0(1) */ + PINCTRL_PIN_GROUP("spi2_wp_hold", mt7981_spi2_wp_hold), + /* @GPIO(16,19): UART1(4) */ + PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0), + /* @GPIO(26,29): UART1(2) */ + PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1), + /* @GPIO(22,25): UART1(3) */ + PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1), + /* @GPIO(22,24) PTA_EXT(4) */ + PINCTRL_PIN_GROUP("pta_ext_1", mt7981_pta_ext_1), + /* @GPIO(20,21): WM_UART(4) */ + PINCTRL_PIN_GROUP("wm_aurt_1", mt7981_wm_uart_1), + /* @GPIO(30,31): WM_UART(3) */ + PINCTRL_PIN_GROUP("wm_aurt_2", mt7981_wm_uart_2), + /* @GPIO(20,24) WM_JTAG(5) */ + PINCTRL_PIN_GROUP("wm_jtag_1", mt7981_wm_jtag_1), + /* @GPIO(25,29) WO0_JTAG(5) */ + PINCTRL_PIN_GROUP("wo0_jtag_1", mt7981_wo0_jtag_1), + /* @GPIO(28,29): WA_AICE(3) */ + PINCTRL_PIN_GROUP("wa_aice3", mt7981_wa_aice3), + /* @GPIO(30,31): WM_AICE(5) */ + PINCTRL_PIN_GROUP("wm_aice2", mt7981_wm_aice2), + /* @GPIO(30,31): I2C(4) */ + PINCTRL_PIN_GROUP("i2c0_1", mt7981_i2c0_1), + /* @GPIO(30,31): I2C(6) */ + PINCTRL_PIN_GROUP("u2_phy_i2c", mt7981_u2_phy_i2c), + /* @GPIO(32,33): I2C(1) */ + PINCTRL_PIN_GROUP("uart0", mt7981_uart0), + /* @GPIO(32,33): I2C(2) */ + PINCTRL_PIN_GROUP("sgmii1_phy_i2c", mt7981_sgmii1_phy_i2c), + /* @GPIO(32,33): I2C(3) */ + PINCTRL_PIN_GROUP("u3_phy_i2c", mt7981_u3_phy_i2c), + /* @GPIO(32,33): I2C(5) */ + PINCTRL_PIN_GROUP("sgmii0_phy_i2c", mt7981_sgmii0_phy_i2c), + /* @GPIO(34): PCIE_CLK_REQ(2) */ + PINCTRL_PIN_GROUP("pcie_clk", mt7981_pcie_clk), + /* @GPIO(35): PCIE_WAKE_N(2) */ + PINCTRL_PIN_GROUP("pcie_wake", mt7981_pcie_wake), + /* @GPIO(36,37): I2C(2) */ + PINCTRL_PIN_GROUP("i2c0_2", mt7981_i2c0_2), + /* @GPIO(36,37): MDC_MDIO(1) */ + PINCTRL_PIN_GROUP("smi_mdc_mdio", mt7981_smi_mdc_mdio), + /* @GPIO(36,37): MDC_MDIO(3) */ + PINCTRL_PIN_GROUP("gbe_ext_mdc_mdio", mt7981_gbe_ext_mdc_mdio), + /* @GPIO(69,85): WF0_MODE1(1) */ + PINCTRL_PIN_GROUP("wf0_mode1", mt7981_wf0_mode1), + /* @GPIO(74,80): WF0_MODE3(3) */ + PINCTRL_PIN_GROUP("wf0_mode3", mt7981_wf0_mode3), + /* @GPIO(30): WF2G_LED(2) */ + PINCTRL_PIN_GROUP("wf2g_led0", mt7981_wf2g_led0), + /* @GPIO(34): WF2G_LED(1) */ + PINCTRL_PIN_GROUP("wf2g_led1", mt7981_wf2g_led1), + /* @GPIO(31): WF5G_LED(2) */ + PINCTRL_PIN_GROUP("wf5g_led0", mt7981_wf5g_led0), + /* @GPIO(35): WF5G_LED(1) */ + PINCTRL_PIN_GROUP("wf5g_led1", mt7981_wf5g_led1), + /* @GPIO(38): MT7531_INT(1) */ + PINCTRL_PIN_GROUP("mt7531_int", mt7981_mt7531_int), + /* @GPIO(14,15,26,17,18,19,20,21,22,23,24,25,34,35): ANT_SEL(1) */ + PINCTRL_PIN_GROUP("ant_sel", mt7981_ant_sel), +}; + +/* Joint those groups owning the same capability in user point of view which + * allows that people tend to use through the device tree. + */ +static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1", + "wa_aice3", "wm_aice1_2", }; +static const char *mt7981_uart_groups[] = { "wm_uart_0", "uart2_0", + "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2", + "uart1_0", "uart1_1", "uart2_1", "wm_aurt_1", "wm_aurt_2", "uart0", }; +static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", }; +static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", }; +static const char *mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", "pcie_wake", }; +static const char *mt7981_jtag_groups[] = { "jtag", "wm_jtag_0", "wo0_jtag_0", + "wo0_jtag_1", "wm_jtag_1", }; +static const char *mt7981_led_groups[] = { "gbe_led0", "gbe_led1", "wf2g_led0", + "wf2g_led1", "wf5g_led0", "wf5g_led1", }; +static const char *mt7981_pta_groups[] = { "pta_ext_0", "pta_ext_1", }; +static const char *mt7981_pwm_groups[] = { "pwm2", "pwm0_0", "pwm0_1", + "pwm1_0", "pwm1_1", }; +static const char *mt7981_spi_groups[] = { "spi1_0", "spi0", "spi0_wp_hold", "spi1_1", "spi2", + "spi2_wp_hold", }; +static const char *mt7981_i2c_groups[] = { "i2c0_0", "i2c0_1", "u2_phy_i2c", + "sgmii1_phy_i2c", "u3_phy_i2c", "sgmii0_phy_i2c", "i2c0_2", }; +static const char *mt7981_pcm_groups[] = { "pcm", }; +static const char *mt7981_udi_groups[] = { "udi", }; +static const char *mt7981_usb_groups[] = { "drv_vbus", }; +static const char *mt7981_flash_groups[] = { "emmc_45", "snfi", }; +static const char *mt7981_ethernet_groups[] = { "smi_mdc_mdio", "gbe_ext_mdc_mdio", + "wf0_mode1", "wf0_mode3", "mt7531_int", }; +static const char *mt7981_ant_groups[] = { "ant_sel", }; + +static const struct function_desc mt7981_functions[] = { + {"wa_aice", mt7981_wa_aice_groups, ARRAY_SIZE(mt7981_wa_aice_groups)}, + {"dfd", mt7981_dfd_groups, ARRAY_SIZE(mt7981_dfd_groups)}, + {"jtag", mt7981_jtag_groups, ARRAY_SIZE(mt7981_jtag_groups)}, + {"pta", mt7981_pta_groups, ARRAY_SIZE(mt7981_pta_groups)}, + {"pcm", mt7981_pcm_groups, ARRAY_SIZE(mt7981_pcm_groups)}, + {"udi", mt7981_udi_groups, ARRAY_SIZE(mt7981_udi_groups)}, + {"usb", mt7981_usb_groups, ARRAY_SIZE(mt7981_usb_groups)}, + {"ant", mt7981_ant_groups, ARRAY_SIZE(mt7981_ant_groups)}, + {"eth", mt7981_ethernet_groups, ARRAY_SIZE(mt7981_ethernet_groups)}, + {"i2c", mt7981_i2c_groups, ARRAY_SIZE(mt7981_i2c_groups)}, + {"led", mt7981_led_groups, ARRAY_SIZE(mt7981_led_groups)}, + {"pwm", mt7981_pwm_groups, ARRAY_SIZE(mt7981_pwm_groups)}, + {"spi", mt7981_spi_groups, ARRAY_SIZE(mt7981_spi_groups)}, + {"uart", mt7981_uart_groups, ARRAY_SIZE(mt7981_uart_groups)}, + {"watchdog", mt7981_wdt_groups, ARRAY_SIZE(mt7981_wdt_groups)}, + {"flash", mt7981_flash_groups, ARRAY_SIZE(mt7981_flash_groups)}, + {"pcie", mt7981_pcie_groups, ARRAY_SIZE(mt7981_pcie_groups)}, +}; + +static const struct mtk_eint_hw mt7981_eint_hw = { + .port_mask = 7, + .ports = 7, + .ap_num = ARRAY_SIZE(mt7981_pins), + .db_cnt = 16, +}; + +static const char * const mt7981_pinctrl_register_base_names[] = { + "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb", + "iocfg_lb", "iocfg_bl", "iocfg_tm", "iocfg_tl", +}; + +static struct mtk_pin_soc mt7981_data = { + .reg_cal = mt7981_reg_cals, + .pins = mt7981_pins, + .npins = ARRAY_SIZE(mt7981_pins), + .grps = mt7981_groups, + .ngrps = ARRAY_SIZE(mt7981_groups), + .funcs = mt7981_functions, + .nfuncs = ARRAY_SIZE(mt7981_functions), + .eint_hw = &mt7981_eint_hw, + .gpio_m = 0, + .ies_present = false, + .base_names = mt7981_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names), + .pull_type = mt7981_pull_type, + .bias_set_combo = mtk_pinconf_bias_set_combo, + .bias_get_combo = mtk_pinconf_bias_get_combo, + .drive_set = mtk_pinconf_drive_set_rev1, + .drive_get = mtk_pinconf_drive_get_rev1, + .adv_pull_get = mtk_pinconf_adv_pull_get, + .adv_pull_set = mtk_pinconf_adv_pull_set, +}; + +static const struct of_device_id mt7981_pinctrl_of_match[] = { + { .compatible = "mediatek,mt7981-pinctrl", }, + {} +}; + +static int mt7981_pinctrl_probe(struct platform_device *pdev) +{ + return mtk_moore_pinctrl_probe(pdev, &mt7981_data); +} + +static struct platform_driver mt7981_pinctrl_driver = { + .driver = { + .name = "mt7981-pinctrl", + .of_match_table = mt7981_pinctrl_of_match, + }, + .probe = mt7981_pinctrl_probe, +}; + +static int __init mt7981_pinctrl_init(void) +{ + return platform_driver_register(&mt7981_pinctrl_driver); +} +arch_initcall(mt7981_pinctrl_init); diff --git a/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7986.c b/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7986.c new file mode 100644 index 00000000000..aa0ccd67f4f --- /dev/null +++ b/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7986.c @@ -0,0 +1,1003 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * The MT7986 driver based on Linux generic pinctrl binding. + * + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam Shih + */ + +#include "pinctrl-moore.h" + +#define MT7986_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4) +#define MT7986_NOT_BALLOUT_PIN(_number) { .number = _number, .name = NULL } + +#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, 0) + +/** + * enum - Locking variants of the iocfg bases + * + * MT7986 have multiple bases to program pin configuration listed as the below: + * iocfg_rt:0x11c30000, iocfg_rb:0x11c40000, iocfg_lt:0x11e20000, + * iocfg_lb:0x11e30000, iocfg_tr:0x11f00000, iocfg_tl:0x11f10000, + * _i_based could be used to indicate what base the pin should be mapped into. + * + * Each iocfg register base control different group of pads on the SoC + * + * + * chip carrier + * + * A B C D E F G H + * +------------------------+ + * 8 | o o o o o o o o | + * 7 | o o o o o o o o | + * 6 | o o o o o o o o | + * 5 | o o o o o o o o | + * 4 | o o o o o o o o | + * 3 | o o o o o o o o | + * 2 | o o o o o o o o | + * 1 | o o o o o o o o | + * +------------------------+ + * + * inside Chip carrier + * + * A B C D E F G H + * +------------------------+ + * 8 | | + * 7 | TL TR | + * 6 | +---------+ | + * 5 | LT | | RT | + * 4 | | | | + * 3 | LB | | RB | + * 2 | +---------+ | + * 1 | | + * +------------------------+ + * + */ + +enum { + GPIO_BASE, + IOCFG_RT_BASE, + IOCFG_RB_BASE, + IOCFG_LT_BASE, + IOCFG_LB_BASE, + IOCFG_TR_BASE, + IOCFG_TL_BASE, +}; + +static const char *const mt7986_pinctrl_register_base_names[] = { + "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt", "iocfg_lb", "iocfg_tr", + "iocfg_tl", +}; + +static const struct mtk_pin_field_calc mt7986_pin_mode_range[] = { + PIN_FIELD(0, 100, 0x300, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt7986_pin_dir_range[] = { + PIN_FIELD(0, 100, 0x0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7986_pin_di_range[] = { + PIN_FIELD(0, 100, 0x200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7986_pin_do_range[] = { + PIN_FIELD(0, 100, 0x100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7986_pin_ies_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x40, 0x10, 17, 1), + PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x20, 0x10, 10, 1), + PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x20, 0x10, 0, 1), + PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x20, 0x10, 0, 1), + PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x40, 0x10, 8, 1), + PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x30, 0x10, 12, 1), + PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x30, 0x10, 18, 1), + PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x30, 0x10, 17, 1), + PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x30, 0x10, 15, 1), + PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x30, 0x10, 19, 1), + PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x30, 0x10, 23, 1), + PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x30, 0x10, 22, 1), + PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x30, 0x10, 21, 1), + PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x20, 0x10, 4, 1), + PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x20, 0x10, 8, 1), + PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x20, 0x10, 7, 1), + PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x20, 0x10, 5, 1), + PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x20, 0x10, 9, 1), + PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x40, 0x10, 18, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x40, 0x10, 12, 1), + PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x40, 0x10, 22, 1), + PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x40, 0x10, 20, 1), + PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x40, 0x10, 26, 1), + PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x40, 0x10, 24, 1), + PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x30, 0x10, 10, 1), + PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x40, 0x10, 15, 1), + PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x40, 0x10, 14, 1), + PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x40, 0x10, 13, 1), + PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x40, 0x10, 16, 1), + PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x20, 0x10, 2, 1), + PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x30, 0x10, 16, 1), + PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x30, 0x10, 14, 1), + PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x30, 0x10, 6, 1), + PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x30, 0x10, 9, 1), + PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x30, 0x10, 14, 1), + PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x30, 0x10, 12, 1), + PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x30, 0x10, 8, 1), +}; + +static const struct mtk_pin_field_calc mt7986_pin_smt_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0xf0, 0x10, 17, 1), + PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x90, 0x10, 10, 1), + PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x90, 0x10, 0, 1), + PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0xf0, 0x10, 0, 1), + PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x90, 0x10, 0, 1), + PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0xf0, 0x10, 8, 1), + PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0xf0, 0x10, 2, 1), + PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0xc0, 0x10, 12, 1), + PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0xc0, 0x10, 18, 1), + PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0xc0, 0x10, 17, 1), + PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0xc0, 0x10, 15, 1), + PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0xc0, 0x10, 19, 1), + PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0xc0, 0x10, 23, 1), + PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0xc0, 0x10, 22, 1), + PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0xc0, 0x10, 21, 1), + PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x90, 0x10, 4, 1), + PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x90, 0x10, 8, 1), + PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x90, 0x10, 7, 1), + PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x90, 0x10, 5, 1), + PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x90, 0x10, 9, 1), + PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0xf0, 0x10, 18, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0xf0, 0x10, 12, 1), + PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0xf0, 0x10, 22, 1), + PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0xf0, 0x10, 20, 1), + PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0xf0, 0x10, 26, 1), + PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0xf0, 0x10, 24, 1), + PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0xc0, 0x10, 2, 1), + PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0xc0, 0x10, 1, 1), + PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0xc0, 0x10, 0, 1), + PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0xc0, 0x10, 10, 1), + PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0xf0, 0x10, 15, 1), + PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0xf0, 0x10, 14, 1), + PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0xf0, 0x10, 13, 1), + PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0xf0, 0x10, 16, 1), + PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x90, 0x10, 2, 1), + PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x80, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x80, 0x10, 0, 1), + PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x80, 0x10, 16, 1), + PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x80, 0x10, 14, 1), + PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x80, 0x10, 4, 1), + PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x80, 0x10, 6, 1), + PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x80, 0x10, 2, 1), + PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x80, 0x10, 9, 1), + PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x80, 0x10, 5, 1), + PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x70, 0x10, 1, 1), + PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x70, 0x10, 0, 1), + PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x70, 0x10, 14, 1), + PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x70, 0x10, 12, 1), + PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x70, 0x10, 4, 1), + PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x70, 0x10, 2, 1), + PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x70, 0x10, 8, 1), +}; + +static const struct mtk_pin_field_calc mt7986_pin_pu_range[] = { + PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x50, 0x10, 16, 1), + PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x50, 0x10, 14, 1), + PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x50, 0x10, 4, 1), + PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x50, 0x10, 6, 1), + PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x50, 0x10, 9, 1), + PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x50, 0x10, 14, 1), + PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x50, 0x10, 12, 1), + PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x50, 0x10, 4, 1), + PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x50, 0x10, 8, 1), +}; + +static const struct mtk_pin_field_calc mt7986_pin_pd_range[] = { + PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x40, 0x10, 16, 1), + PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x40, 0x10, 14, 1), + PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x40, 0x10, 6, 1), + PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x40, 0x10, 9, 1), + PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x40, 0x10, 14, 1), + PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x40, 0x10, 12, 1), + PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x40, 0x10, 8, 1), +}; + +static const struct mtk_pin_field_calc mt7986_pin_drv_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x10, 0x10, 21, 3), + PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x10, 0x10, 0, 3), + PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x00, 0x10, 0, 1), + PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0x00, 0x10, 21, 3), + PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(11, 12, IOCFG_RB_BASE, 0x00, 0x10, 24, 3), + PIN_FIELD_BASE(13, 14, IOCFG_RB_BASE, 0x10, 0x10, 0, 3), + PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x10, 0x10, 6, 3), + PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x10, 0x10, 24, 3), + PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x10, 0x10, 21, 3), + PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x10, 0x10, 15, 3), + PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0x10, 0x10, 27, 3), + PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0x20, 0x10, 0, 3), + PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x20, 0x10, 9, 3), + PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x20, 0x10, 6, 3), + PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x20, 0x10, 3, 3), + PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x00, 0x10, 24, 3), + PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x00, 0x10, 21, 3), + PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x00, 0x10, 27, 3), + PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x10, 0x10, 27, 3), + PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x20, 0x10, 0, 3), + PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x10, 0x10, 6, 3), + PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x20, 0x10, 9, 3), + PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x20, 0x10, 3, 3), + PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x20, 0x10, 21, 3), + PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x20, 0x10, 15, 3), + PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x00, 0x10, 6, 3), + PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x10, 0x10, 0, 3), + PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x10, 0x10, 15, 3), + PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x10, 0x10, 12, 3), + PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x10, 0x10, 9, 3), + PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x10, 0x10, 18, 3), + PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x00, 0x10, 2, 3), + PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x10, 0x10, 18, 3), + PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x10, 0x10, 12, 3), + PIN_FIELD_BASE(74, 77, IOCFG_TR_BASE, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x00, 0x10, 6, 3), + PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x00, 0x10, 27, 3), + PIN_FIELD_BASE(81, 84, IOCFG_TR_BASE, 0x10, 0x10, 0, 3), + PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x10, 0x10, 12, 3), + PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x10, 0x10, 6, 3), + PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x00, 0x10, 6, 3), + PIN_FIELD_BASE(97, 98, IOCFG_TL_BASE, 0x00, 0x10, 24, 3), + PIN_FIELD_BASE(99, 100, IOCFG_TL_BASE, 0x10, 0x10, 2, 3), +}; + +static const struct mtk_pin_field_calc mt7986_pin_pupd_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x60, 0x10, 17, 1), + PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x30, 0x10, 10, 1), + PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x60, 0x10, 0, 1), + PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x60, 0x10, 8, 1), + PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x60, 0x10, 2, 1), + PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x40, 0x10, 12, 1), + PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x40, 0x10, 18, 1), + PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x40, 0x10, 17, 1), + PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x40, 0x10, 15, 1), + PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x40, 0x10, 19, 1), + PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x40, 0x10, 23, 1), + PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x40, 0x10, 22, 1), + PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x40, 0x10, 21, 1), + PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x30, 0x10, 8, 1), + PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x30, 0x10, 7, 1), + PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x30, 0x10, 9, 1), + PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x60, 0x10, 18, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x60, 0x10, 12, 1), + PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x60, 0x10, 23, 1), + PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x60, 0x10, 21, 1), + PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x60, 0x10, 27, 1), + PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x60, 0x10, 25, 1), + PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x40, 0x10, 10, 1), + PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x60, 0x10, 15, 1), + PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x60, 0x10, 14, 1), + PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x60, 0x10, 13, 1), + PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x60, 0x10, 16, 1), + PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x40, 0x10, 2, 1), +}; + +static const struct mtk_pin_field_calc mt7986_pin_r0_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x70, 0x10, 17, 1), + PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x40, 0x10, 10, 1), + PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x70, 0x10, 0, 1), + PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x70, 0x10, 8, 1), + PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x70, 0x10, 2, 1), + PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x50, 0x10, 12, 1), + PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x50, 0x10, 18, 1), + PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x50, 0x10, 17, 1), + PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x50, 0x10, 15, 1), + PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x50, 0x10, 19, 1), + PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x50, 0x10, 23, 1), + PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x50, 0x10, 22, 1), + PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x50, 0x10, 21, 1), + PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x40, 0x10, 8, 1), + PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x40, 0x10, 7, 1), + PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x40, 0x10, 9, 1), + PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x70, 0x10, 18, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x70, 0x10, 12, 1), + PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x70, 0x10, 23, 1), + PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x70, 0x10, 21, 1), + PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x70, 0x10, 27, 1), + PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x70, 0x10, 25, 1), + PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x50, 0x10, 10, 1), + PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x70, 0x10, 15, 1), + PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x70, 0x10, 14, 1), + PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x70, 0x10, 13, 1), + PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x70, 0x10, 16, 1), + PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x50, 0x10, 2, 1), +}; + +static const struct mtk_pin_field_calc mt7986_pin_r1_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x80, 0x10, 17, 1), + PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x50, 0x10, 10, 1), + PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x60, 0x10, 0, 1), + PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x80, 0x10, 0, 1), + PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x80, 0x10, 8, 1), + PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x80, 0x10, 2, 1), + PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x60, 0x10, 12, 1), + PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x60, 0x10, 18, 1), + PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x60, 0x10, 17, 1), + PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x60, 0x10, 15, 1), + PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x60, 0x10, 19, 1), + PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x60, 0x10, 23, 1), + PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x60, 0x10, 22, 1), + PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x60, 0x10, 21, 1), + PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x50, 0x10, 4, 1), + PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x50, 0x10, 8, 1), + PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x50, 0x10, 7, 1), + PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x50, 0x10, 9, 1), + PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x80, 0x10, 18, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x80, 0x10, 12, 1), + PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x80, 0x10, 23, 1), + PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x80, 0x10, 21, 1), + PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x80, 0x10, 27, 1), + PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x80, 0x10, 25, 1), + PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x60, 0x10, 2, 1), + PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x60, 0x10, 1, 1), + PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x60, 0x10, 0, 1), + PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x60, 0x10, 10, 1), + PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x80, 0x10, 15, 1), + PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x80, 0x10, 14, 1), + PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x80, 0x10, 13, 1), + PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x80, 0x10, 16, 1), + PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x60, 0x10, 2, 1), +}; + +static const unsigned int mt7986_pull_type[] = { + MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/ + MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/ + MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/ + MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/ + MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/ + MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/ + MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/ + MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/ + MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/ + MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/ + MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/ + MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/ + MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/ + MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/ + MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/ + MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/ + MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/ + MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/ + MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/ + MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/ + MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/ + MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/ + MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/ + MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/ + MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/ + MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/ + MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/ + MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/ + MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/ + MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/ + MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/ + MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/ + MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/ + MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/ + MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/ + MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/ + MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/ + MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/ + MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/ + MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/ + MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/ + MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/ + MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/ + MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/ + MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/ + MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/ + MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/ + MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/ + MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/ + MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/ + MTK_PULL_PU_PD_TYPE,/*100*/ +}; + +static const struct mtk_pin_reg_calc mt7986_reg_cals[] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7986_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7986_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7986_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7986_pin_do_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7986_pin_smt_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7986_pin_ies_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7986_pin_drv_range), + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7986_pin_pu_range), + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7986_pin_pd_range), + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7986_pin_pupd_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7986_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7986_pin_r1_range), +}; + +static const struct mtk_pin_desc mt7986a_pins[] = { + MT7986_PIN(0, "SYS_WATCHDOG"), + MT7986_PIN(1, "WF2G_LED"), + MT7986_PIN(2, "WF5G_LED"), + MT7986_PIN(3, "I2C_SCL"), + MT7986_PIN(4, "I2C_SDA"), + MT7986_PIN(5, "GPIO_0"), + MT7986_PIN(6, "GPIO_1"), + MT7986_PIN(7, "GPIO_2"), + MT7986_PIN(8, "GPIO_3"), + MT7986_PIN(9, "GPIO_4"), + MT7986_PIN(10, "GPIO_5"), + MT7986_PIN(11, "GPIO_6"), + MT7986_PIN(12, "GPIO_7"), + MT7986_PIN(13, "GPIO_8"), + MT7986_PIN(14, "GPIO_9"), + MT7986_PIN(15, "GPIO_10"), + MT7986_PIN(16, "GPIO_11"), + MT7986_PIN(17, "GPIO_12"), + MT7986_PIN(18, "GPIO_13"), + MT7986_PIN(19, "GPIO_14"), + MT7986_PIN(20, "GPIO_15"), + MT7986_PIN(21, "PWM0"), + MT7986_PIN(22, "PWM1"), + MT7986_PIN(23, "SPI0_CLK"), + MT7986_PIN(24, "SPI0_MOSI"), + MT7986_PIN(25, "SPI0_MISO"), + MT7986_PIN(26, "SPI0_CS"), + MT7986_PIN(27, "SPI0_HOLD"), + MT7986_PIN(28, "SPI0_WP"), + MT7986_PIN(29, "SPI1_CLK"), + MT7986_PIN(30, "SPI1_MOSI"), + MT7986_PIN(31, "SPI1_MISO"), + MT7986_PIN(32, "SPI1_CS"), + MT7986_PIN(33, "SPI2_CLK"), + MT7986_PIN(34, "SPI2_MOSI"), + MT7986_PIN(35, "SPI2_MISO"), + MT7986_PIN(36, "SPI2_CS"), + MT7986_PIN(37, "SPI2_HOLD"), + MT7986_PIN(38, "SPI2_WP"), + MT7986_PIN(39, "UART0_RXD"), + MT7986_PIN(40, "UART0_TXD"), + MT7986_PIN(41, "PCIE_PERESET_N"), + MT7986_PIN(42, "UART1_RXD"), + MT7986_PIN(43, "UART1_TXD"), + MT7986_PIN(44, "UART1_CTS"), + MT7986_PIN(45, "UART1_RTS"), + MT7986_PIN(46, "UART2_RXD"), + MT7986_PIN(47, "UART2_TXD"), + MT7986_PIN(48, "UART2_CTS"), + MT7986_PIN(49, "UART2_RTS"), + MT7986_PIN(50, "EMMC_DATA_0"), + MT7986_PIN(51, "EMMC_DATA_1"), + MT7986_PIN(52, "EMMC_DATA_2"), + MT7986_PIN(53, "EMMC_DATA_3"), + MT7986_PIN(54, "EMMC_DATA_4"), + MT7986_PIN(55, "EMMC_DATA_5"), + MT7986_PIN(56, "EMMC_DATA_6"), + MT7986_PIN(57, "EMMC_DATA_7"), + MT7986_PIN(58, "EMMC_CMD"), + MT7986_PIN(59, "EMMC_CK"), + MT7986_PIN(60, "EMMC_DSL"), + MT7986_PIN(61, "EMMC_RSTB"), + MT7986_PIN(62, "PCM_DTX"), + MT7986_PIN(63, "PCM_DRX"), + MT7986_PIN(64, "PCM_CLK"), + MT7986_PIN(65, "PCM_FS"), + MT7986_PIN(66, "MT7531_INT"), + MT7986_PIN(67, "SMI_MDC"), + MT7986_PIN(68, "SMI_MDIO"), + MT7986_PIN(69, "WF0_DIG_RESETB"), + MT7986_PIN(70, "WF0_CBA_RESETB"), + MT7986_PIN(71, "WF0_XO_REQ"), + MT7986_PIN(72, "WF0_TOP_CLK"), + MT7986_PIN(73, "WF0_TOP_DATA"), + MT7986_PIN(74, "WF0_HB1"), + MT7986_PIN(75, "WF0_HB2"), + MT7986_PIN(76, "WF0_HB3"), + MT7986_PIN(77, "WF0_HB4"), + MT7986_PIN(78, "WF0_HB0"), + MT7986_PIN(79, "WF0_HB0_B"), + MT7986_PIN(80, "WF0_HB5"), + MT7986_PIN(81, "WF0_HB6"), + MT7986_PIN(82, "WF0_HB7"), + MT7986_PIN(83, "WF0_HB8"), + MT7986_PIN(84, "WF0_HB9"), + MT7986_PIN(85, "WF0_HB10"), + MT7986_PIN(86, "WF1_DIG_RESETB"), + MT7986_PIN(87, "WF1_CBA_RESETB"), + MT7986_PIN(88, "WF1_XO_REQ"), + MT7986_PIN(89, "WF1_TOP_CLK"), + MT7986_PIN(90, "WF1_TOP_DATA"), + MT7986_PIN(91, "WF1_HB1"), + MT7986_PIN(92, "WF1_HB2"), + MT7986_PIN(93, "WF1_HB3"), + MT7986_PIN(94, "WF1_HB4"), + MT7986_PIN(95, "WF1_HB0"), + MT7986_PIN(96, "WF1_HB0_B"), + MT7986_PIN(97, "WF1_HB5"), + MT7986_PIN(98, "WF1_HB6"), + MT7986_PIN(99, "WF1_HB7"), + MT7986_PIN(100, "WF1_HB8"), +}; + +static const struct mtk_pin_desc mt7986b_pins[] = { + MT7986_PIN(0, "SYS_WATCHDOG"), + MT7986_PIN(1, "WF2G_LED"), + MT7986_PIN(2, "WF5G_LED"), + MT7986_PIN(3, "I2C_SCL"), + MT7986_PIN(4, "I2C_SDA"), + MT7986_PIN(5, "GPIO_0"), + MT7986_PIN(6, "GPIO_1"), + MT7986_PIN(7, "GPIO_2"), + MT7986_PIN(8, "GPIO_3"), + MT7986_PIN(9, "GPIO_4"), + MT7986_PIN(10, "GPIO_5"), + MT7986_PIN(11, "GPIO_6"), + MT7986_PIN(12, "GPIO_7"), + MT7986_PIN(13, "GPIO_8"), + MT7986_PIN(14, "GPIO_9"), + MT7986_PIN(15, "GPIO_10"), + MT7986_PIN(16, "GPIO_11"), + MT7986_PIN(17, "GPIO_12"), + MT7986_PIN(18, "GPIO_13"), + MT7986_PIN(19, "GPIO_14"), + MT7986_PIN(20, "GPIO_15"), + MT7986_PIN(21, "PWM0"), + MT7986_PIN(22, "PWM1"), + MT7986_PIN(23, "SPI0_CLK"), + MT7986_PIN(24, "SPI0_MOSI"), + MT7986_PIN(25, "SPI0_MISO"), + MT7986_PIN(26, "SPI0_CS"), + MT7986_PIN(27, "SPI0_HOLD"), + MT7986_PIN(28, "SPI0_WP"), + MT7986_PIN(29, "SPI1_CLK"), + MT7986_PIN(30, "SPI1_MOSI"), + MT7986_PIN(31, "SPI1_MISO"), + MT7986_PIN(32, "SPI1_CS"), + MT7986_PIN(33, "SPI2_CLK"), + MT7986_PIN(34, "SPI2_MOSI"), + MT7986_PIN(35, "SPI2_MISO"), + MT7986_PIN(36, "SPI2_CS"), + MT7986_PIN(37, "SPI2_HOLD"), + MT7986_PIN(38, "SPI2_WP"), + MT7986_PIN(39, "UART0_RXD"), + MT7986_PIN(40, "UART0_TXD"), + MT7986_NOT_BALLOUT_PIN(41), + MT7986_NOT_BALLOUT_PIN(42), + MT7986_NOT_BALLOUT_PIN(43), + MT7986_NOT_BALLOUT_PIN(44), + MT7986_NOT_BALLOUT_PIN(45), + MT7986_NOT_BALLOUT_PIN(46), + MT7986_NOT_BALLOUT_PIN(47), + MT7986_NOT_BALLOUT_PIN(48), + MT7986_NOT_BALLOUT_PIN(49), + MT7986_NOT_BALLOUT_PIN(50), + MT7986_NOT_BALLOUT_PIN(51), + MT7986_NOT_BALLOUT_PIN(52), + MT7986_NOT_BALLOUT_PIN(53), + MT7986_NOT_BALLOUT_PIN(54), + MT7986_NOT_BALLOUT_PIN(55), + MT7986_NOT_BALLOUT_PIN(56), + MT7986_NOT_BALLOUT_PIN(57), + MT7986_NOT_BALLOUT_PIN(58), + MT7986_NOT_BALLOUT_PIN(59), + MT7986_NOT_BALLOUT_PIN(60), + MT7986_NOT_BALLOUT_PIN(61), + MT7986_NOT_BALLOUT_PIN(62), + MT7986_NOT_BALLOUT_PIN(63), + MT7986_NOT_BALLOUT_PIN(64), + MT7986_NOT_BALLOUT_PIN(65), + MT7986_PIN(66, "MT7531_INT"), + MT7986_PIN(67, "SMI_MDC"), + MT7986_PIN(68, "SMI_MDIO"), + MT7986_PIN(69, "WF0_DIG_RESETB"), + MT7986_PIN(70, "WF0_CBA_RESETB"), + MT7986_PIN(71, "WF0_XO_REQ"), + MT7986_PIN(72, "WF0_TOP_CLK"), + MT7986_PIN(73, "WF0_TOP_DATA"), + MT7986_PIN(74, "WF0_HB1"), + MT7986_PIN(75, "WF0_HB2"), + MT7986_PIN(76, "WF0_HB3"), + MT7986_PIN(77, "WF0_HB4"), + MT7986_PIN(78, "WF0_HB0"), + MT7986_PIN(79, "WF0_HB0_B"), + MT7986_PIN(80, "WF0_HB5"), + MT7986_PIN(81, "WF0_HB6"), + MT7986_PIN(82, "WF0_HB7"), + MT7986_PIN(83, "WF0_HB8"), + MT7986_PIN(84, "WF0_HB9"), + MT7986_PIN(85, "WF0_HB10"), + MT7986_PIN(86, "WF1_DIG_RESETB"), + MT7986_PIN(87, "WF1_CBA_RESETB"), + MT7986_PIN(88, "WF1_XO_REQ"), + MT7986_PIN(89, "WF1_TOP_CLK"), + MT7986_PIN(90, "WF1_TOP_DATA"), + MT7986_PIN(91, "WF1_HB1"), + MT7986_PIN(92, "WF1_HB2"), + MT7986_PIN(93, "WF1_HB3"), + MT7986_PIN(94, "WF1_HB4"), + MT7986_PIN(95, "WF1_HB0"), + MT7986_PIN(96, "WF1_HB0_B"), + MT7986_PIN(97, "WF1_HB5"), + MT7986_PIN(98, "WF1_HB6"), + MT7986_PIN(99, "WF1_HB7"), + MT7986_PIN(100, "WF1_HB8"), +}; + +/* List all groups consisting of these pins dedicated to the enablement of + * certain hardware block and the corresponding mode for all of the pins. + * The hardware probably has multiple combinations of these pinouts. + */ + +static int mt7986_watchdog_pins[] = { 0, }; +static int mt7986_watchdog_funcs[] = { 1, }; + +static int mt7986_wifi_led_pins[] = { 1, 2, }; +static int mt7986_wifi_led_funcs[] = { 1, 1, }; + +static int mt7986_i2c_pins[] = { 3, 4, }; +static int mt7986_i2c_funcs[] = { 1, 1, }; + +static int mt7986_uart1_0_pins[] = { 7, 8, 9, 10, }; +static int mt7986_uart1_0_funcs[] = { 3, 3, 3, 3, }; + +static int mt7986_spi1_0_pins[] = { 11, 12, 13, 14, }; +static int mt7986_spi1_0_funcs[] = { 3, 3, 3, 3, }; + +static int mt7986_pwm1_1_pins[] = { 20, }; +static int mt7986_pwm1_1_funcs[] = { 2, }; + +static int mt7986_pwm0_pins[] = { 21, }; +static int mt7986_pwm0_funcs[] = { 1, }; + +static int mt7986_pwm1_0_pins[] = { 22, }; +static int mt7986_pwm1_0_funcs[] = { 1, }; + +static int mt7986_emmc_45_pins[] = { + 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, }; +static int mt7986_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; + +static int mt7986_snfi_pins[] = { 23, 24, 25, 26, 27, 28, }; +static int mt7986_snfi_funcs[] = { 1, 1, 1, 1, 1, 1, }; + +static int mt7986_spi1_1_pins[] = { 23, 24, 25, 26, }; +static int mt7986_spi1_1_funcs[] = { 3, 3, 3, 3, }; + +static int mt7986_uart1_1_pins[] = { 23, 24, 25, 26, }; +static int mt7986_uart1_1_funcs[] = { 4, 4, 4, 4, }; + +static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, }; +static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, }; + +static int mt7986_uart1_2_rx_tx_pins[] = { 29, 30, }; +static int mt7986_uart1_2_rx_tx_funcs[] = { 3, 3, }; + +static int mt7986_uart1_2_cts_rts_pins[] = { 31, 32, }; +static int mt7986_uart1_2_cts_rts_funcs[] = { 3, 3, }; + +static int mt7986_uart2_0_rx_tx_pins[] = { 29, 30, }; +static int mt7986_uart2_0_rx_tx_funcs[] = { 4, 4, }; + +static int mt7986_uart2_0_cts_rts_pins[] = { 31, 32, }; +static int mt7986_uart2_0_cts_rts_funcs[] = { 4, 4, }; + +static int mt7986_spi0_pins[] = { 33, 34, 35, 36, }; +static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, }; + +static int mt7986_spi0_wp_hold_pins[] = { 37, 38, }; +static int mt7986_spi0_wp_hold_funcs[] = { 1, 1, }; + +static int mt7986_uart2_1_pins[] = { 33, 34, 35, 36, }; +static int mt7986_uart2_1_funcs[] = { 3, 3, 3, 3, }; + +static int mt7986_uart1_3_rx_tx_pins[] = { 35, 36, }; +static int mt7986_uart1_3_rx_tx_funcs[] = { 2, 2, }; + +static int mt7986_uart1_3_cts_rts_pins[] = { 37, 38, }; +static int mt7986_uart1_3_cts_rts_funcs[] = { 2, 2, }; + +static int mt7986_spi1_3_pins[] = { 33, 34, 35, 36, }; +static int mt7986_spi1_3_funcs[] = { 4, 4, 4, 4, }; + +static int mt7986_uart0_pins[] = { 39, 40, }; +static int mt7986_uart0_funcs[] = { 1, 1, }; + +static int mt7986_pcie_reset_pins[] = { 41, }; +static int mt7986_pcie_reset_funcs[] = { 1, }; + +static int mt7986_uart1_pins[] = { 42, 43, 44, 45, }; +static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, }; + +static int mt7986_uart1_rx_tx_pins[] = { 42, 43, }; +static int mt7986_uart1_rx_tx_funcs[] = { 1, 1, }; + +static int mt7986_uart1_cts_rts_pins[] = { 44, 45, }; +static int mt7986_uart1_cts_rts_funcs[] = { 1, 1, }; + +static int mt7986_uart2_pins[] = { 46, 47, 48, 49, }; +static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, }; + +static int mt7986_emmc_51_pins[] = { + 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, }; +static int mt7986_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; + +static int mt7986_pcm_pins[] = { 62, 63, 64, 65, }; +static int mt7986_pcm_funcs[] = { 1, 1, 1, 1, }; + +static int mt7986_i2s_pins[] = { 62, 63, 64, 65, }; +static int mt7986_i2s_funcs[] = { 1, 1, 1, 1, }; + +static int mt7986_switch_int_pins[] = { 66, }; +static int mt7986_switch_int_funcs[] = { 1, }; + +static int mt7986_mdc_mdio_pins[] = { 67, 68, }; +static int mt7986_mdc_mdio_funcs[] = { 1, 1, }; + +static int mt7986_wf_2g_pins[] = {74, 75, 76, 77, 78, 79, 80, 81, 82, 83, }; +static int mt7986_wf_2g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; + +static int mt7986_wf_5g_pins[] = {91, 92, 93, 94, 95, 96, 97, 98, 99, 100, }; +static int mt7986_wf_5g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; + +static int mt7986_wf_dbdc_pins[] = { + 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, }; +static int mt7986_wf_dbdc_funcs[] = { + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; + +static int mt7986_pcie_clk_pins[] = { 9, }; +static int mt7986_pcie_clk_funcs[] = { 1, }; + +static int mt7986_pcie_wake_pins[] = { 10, }; +static int mt7986_pcie_wake_funcs[] = { 1, }; + +static const struct group_desc mt7986_groups[] = { + PINCTRL_PIN_GROUP("watchdog", mt7986_watchdog), + PINCTRL_PIN_GROUP("wifi_led", mt7986_wifi_led), + PINCTRL_PIN_GROUP("i2c", mt7986_i2c), + PINCTRL_PIN_GROUP("uart1_0", mt7986_uart1_0), + PINCTRL_PIN_GROUP("uart1_rx_tx", mt7986_uart1_rx_tx), + PINCTRL_PIN_GROUP("uart1_cts_rts", mt7986_uart1_cts_rts), + PINCTRL_PIN_GROUP("pcie_clk", mt7986_pcie_clk), + PINCTRL_PIN_GROUP("pcie_wake", mt7986_pcie_wake), + PINCTRL_PIN_GROUP("spi1_0", mt7986_spi1_0), + PINCTRL_PIN_GROUP("pwm1_1", mt7986_pwm1_1), + PINCTRL_PIN_GROUP("pwm0", mt7986_pwm0), + PINCTRL_PIN_GROUP("pwm1_0", mt7986_pwm1_0), + PINCTRL_PIN_GROUP("emmc_45", mt7986_emmc_45), + PINCTRL_PIN_GROUP("snfi", mt7986_snfi), + PINCTRL_PIN_GROUP("spi1_1", mt7986_spi1_1), + PINCTRL_PIN_GROUP("uart1_1", mt7986_uart1_1), + PINCTRL_PIN_GROUP("spi1_2", mt7986_spi1_2), + PINCTRL_PIN_GROUP("uart1_2_rx_tx", mt7986_uart1_2_rx_tx), + PINCTRL_PIN_GROUP("uart1_2_cts_rts", mt7986_uart1_2_cts_rts), + PINCTRL_PIN_GROUP("uart2_0_rx_tx", mt7986_uart2_0_rx_tx), + PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7986_uart2_0_cts_rts), + PINCTRL_PIN_GROUP("spi0", mt7986_spi0), + PINCTRL_PIN_GROUP("spi0_wp_hold", mt7986_spi0_wp_hold), + PINCTRL_PIN_GROUP("uart2_1", mt7986_uart2_1), + PINCTRL_PIN_GROUP("uart1_3_rx_tx", mt7986_uart1_3_rx_tx), + PINCTRL_PIN_GROUP("uart1_3_cts_rts", mt7986_uart1_3_cts_rts), + PINCTRL_PIN_GROUP("spi1_3", mt7986_spi1_3), + PINCTRL_PIN_GROUP("uart0", mt7986_uart0), + PINCTRL_PIN_GROUP("switch_int", mt7986_switch_int), + PINCTRL_PIN_GROUP("mdc_mdio", mt7986_mdc_mdio), + PINCTRL_PIN_GROUP("pcie_pereset", mt7986_pcie_reset), + PINCTRL_PIN_GROUP("uart1", mt7986_uart1), + PINCTRL_PIN_GROUP("uart2", mt7986_uart2), + PINCTRL_PIN_GROUP("emmc_51", mt7986_emmc_51), + PINCTRL_PIN_GROUP("pcm", mt7986_pcm), + PINCTRL_PIN_GROUP("i2s", mt7986_i2s), + PINCTRL_PIN_GROUP("wf_2g", mt7986_wf_2g), + PINCTRL_PIN_GROUP("wf_5g", mt7986_wf_5g), + PINCTRL_PIN_GROUP("wf_dbdc", mt7986_wf_dbdc), +}; + +/* Joint those groups owning the same capability in user point of view which + * allows that people tend to use through the device tree. + */ + +static const char *mt7986_audio_groups[] = { "pcm", "i2s" }; +static const char *mt7986_emmc_groups[] = { + "emmc_45", "emmc_51", }; +static const char *mt7986_ethernet_groups[] = { + "switch_int", "mdc_mdio", }; +static const char *mt7986_i2c_groups[] = { "i2c", }; +static const char *mt7986_led_groups[] = { "wifi_led", }; +static const char *mt7986_flash_groups[] = { "snfi", }; +static const char *mt7986_pcie_groups[] = { + "pcie_clk", "pcie_wake", "pcie_pereset" }; +static const char *mt7986_pwm_groups[] = { "pwm0", "pwm1_0", "pwm1_1", }; +static const char *mt7986_spi_groups[] = { + "spi0", "spi0_wp_hold", "spi1_0", "spi1_1", "spi1_2", "spi1_3", }; +static const char *mt7986_uart_groups[] = { + "uart1_0", "uart1_1", "uart1_rx_tx", "uart1_cts_rts", + "uart1_2_rx_tx", "uart1_2_cts_rts", + "uart1_3_rx_tx", "uart1_3_cts_rts", "uart2_0_rx_tx", "uart2_0_cts_rts", + "uart2_0", "uart2_1", "uart0", "uart1", "uart2", +}; +static const char *mt7986_wdt_groups[] = { "watchdog", }; +static const char *mt7986_wf_groups[] = { "wf_2g", "wf_5g", "wf_dbdc", }; + +static const struct function_desc mt7986_functions[] = { + {"audio", mt7986_audio_groups, ARRAY_SIZE(mt7986_audio_groups)}, + {"emmc", mt7986_emmc_groups, ARRAY_SIZE(mt7986_emmc_groups)}, + {"eth", mt7986_ethernet_groups, ARRAY_SIZE(mt7986_ethernet_groups)}, + {"i2c", mt7986_i2c_groups, ARRAY_SIZE(mt7986_i2c_groups)}, + {"led", mt7986_led_groups, ARRAY_SIZE(mt7986_led_groups)}, + {"flash", mt7986_flash_groups, ARRAY_SIZE(mt7986_flash_groups)}, + {"pcie", mt7986_pcie_groups, ARRAY_SIZE(mt7986_pcie_groups)}, + {"pwm", mt7986_pwm_groups, ARRAY_SIZE(mt7986_pwm_groups)}, + {"spi", mt7986_spi_groups, ARRAY_SIZE(mt7986_spi_groups)}, + {"uart", mt7986_uart_groups, ARRAY_SIZE(mt7986_uart_groups)}, + {"watchdog", mt7986_wdt_groups, ARRAY_SIZE(mt7986_wdt_groups)}, + {"wifi", mt7986_wf_groups, ARRAY_SIZE(mt7986_wf_groups)}, +}; + +static const struct mtk_eint_hw mt7986a_eint_hw = { + .port_mask = 7, + .ports = 7, + .ap_num = ARRAY_SIZE(mt7986a_pins), + .db_cnt = 16, + .db_time = debounce_time_mt6765, +}; + +static const struct mtk_eint_hw mt7986b_eint_hw = { + .port_mask = 7, + .ports = 7, + .ap_num = ARRAY_SIZE(mt7986b_pins), + .db_cnt = 16, + .db_time = debounce_time_mt6765, +}; + +static struct mtk_pin_soc mt7986a_data = { + .reg_cal = mt7986_reg_cals, + .pins = mt7986a_pins, + .npins = ARRAY_SIZE(mt7986a_pins), + .grps = mt7986_groups, + .ngrps = ARRAY_SIZE(mt7986_groups), + .funcs = mt7986_functions, + .nfuncs = ARRAY_SIZE(mt7986_functions), + .eint_hw = &mt7986a_eint_hw, + .gpio_m = 0, + .ies_present = false, + .base_names = mt7986_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), + .pull_type = mt7986_pull_type, + .bias_set_combo = mtk_pinconf_bias_set_combo, + .bias_get_combo = mtk_pinconf_bias_get_combo, + .drive_set = mtk_pinconf_drive_set_rev1, + .drive_get = mtk_pinconf_drive_get_rev1, + .adv_pull_get = mtk_pinconf_adv_pull_get, + .adv_pull_set = mtk_pinconf_adv_pull_set, +}; + +static struct mtk_pin_soc mt7986b_data = { + .reg_cal = mt7986_reg_cals, + .pins = mt7986b_pins, + .npins = ARRAY_SIZE(mt7986b_pins), + .grps = mt7986_groups, + .ngrps = ARRAY_SIZE(mt7986_groups), + .funcs = mt7986_functions, + .nfuncs = ARRAY_SIZE(mt7986_functions), + .eint_hw = &mt7986b_eint_hw, + .gpio_m = 0, + .ies_present = false, + .base_names = mt7986_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), + .pull_type = mt7986_pull_type, + .bias_set_combo = mtk_pinconf_bias_set_combo, + .bias_get_combo = mtk_pinconf_bias_get_combo, + .drive_set = mtk_pinconf_drive_set_rev1, + .drive_get = mtk_pinconf_drive_get_rev1, + .adv_pull_get = mtk_pinconf_adv_pull_get, + .adv_pull_set = mtk_pinconf_adv_pull_set, +}; + +static const struct of_device_id mt7986a_pinctrl_of_match[] = { + {.compatible = "mediatek,mt7986a-pinctrl",}, + {} +}; + +static const struct of_device_id mt7986b_pinctrl_of_match[] = { + {.compatible = "mediatek,mt7986b-pinctrl",}, + {} +}; + +static int mt7986a_pinctrl_probe(struct platform_device *pdev) +{ + return mtk_moore_pinctrl_probe(pdev, &mt7986a_data); +} + +static int mt7986b_pinctrl_probe(struct platform_device *pdev) +{ + return mtk_moore_pinctrl_probe(pdev, &mt7986b_data); +} + +static struct platform_driver mt7986a_pinctrl_driver = { + .driver = { + .name = "mt7986a-pinctrl", + .of_match_table = mt7986a_pinctrl_of_match, + }, + .probe = mt7986a_pinctrl_probe, +}; + +static struct platform_driver mt7986b_pinctrl_driver = { + .driver = { + .name = "mt7986b-pinctrl", + .of_match_table = mt7986b_pinctrl_of_match, + }, + .probe = mt7986b_pinctrl_probe, +}; + +static int __init mt7986a_pinctrl_init(void) +{ + return platform_driver_register(&mt7986a_pinctrl_driver); +} + +static int __init mt7986b_pinctrl_init(void) +{ + return platform_driver_register(&mt7986b_pinctrl_driver); +} + +arch_initcall(mt7986a_pinctrl_init); +arch_initcall(mt7986b_pinctrl_init); diff --git a/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c b/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c new file mode 100644 index 00000000000..80a7e19f7a2 --- /dev/null +++ b/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c @@ -0,0 +1,1281 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * The MT7988 driver based on Linux generic pinctrl binding. + * + * Copyright (C) 2020 MediaTek Inc. + * Author: Sam Shih + */ + +#include "pinctrl-moore.h" + +enum MT7988_PINCTRL_REG_PAGE { + GPIO_BASE, + IOCFG_TR_BASE, + IOCFG_BR_BASE, + IOCFG_RB_BASE, + IOCFG_LB_BASE, + IOCFG_TL_BASE, +}; + +#define MT7988_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4) + +#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, 0) + +#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, 1) + +static const struct mtk_pin_field_calc mt7988_pin_mode_range[] = { + PIN_FIELD(0, 83, 0x300, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt7988_pin_dir_range[] = { + PIN_FIELD(0, 83, 0x0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7988_pin_di_range[] = { + PIN_FIELD(0, 83, 0x200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7988_pin_do_range[] = { + PIN_FIELD(0, 83, 0x100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = { + PIN_FIELD_BASE(0, 1, 5, 0x30, 0x10, 13, 1), + PIN_FIELD_BASE(2, 3, 5, 0x30, 0x10, 11, 1), + PIN_FIELD_BASE(4, 4, 5, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(5, 6, 5, 0x30, 0x10, 9, 1), + PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 8, 1), + PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 6, 1), + PIN_FIELD_BASE(9, 9, 4, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(10, 10, 4, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(11, 11, 1, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(12, 12, 1, 0x40, 0x10, 21, 1), + PIN_FIELD_BASE(13, 14, 1, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(15, 16, 5, 0x30, 0x10, 7, 1), + PIN_FIELD_BASE(17, 18, 5, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(19, 19, 4, 0x30, 0x10, 7, 1), + PIN_FIELD_BASE(20, 20, 4, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(21, 21, 3, 0x50, 0x10, 17, 1), + PIN_FIELD_BASE(22, 22, 3, 0x50, 0x10, 23, 1), + PIN_FIELD_BASE(23, 23, 3, 0x50, 0x10, 20, 1), + PIN_FIELD_BASE(24, 24, 3, 0x50, 0x10, 19, 1), + PIN_FIELD_BASE(25, 26, 3, 0x50, 0x10, 21, 1), + PIN_FIELD_BASE(27, 27, 3, 0x50, 0x10, 18, 1), + PIN_FIELD_BASE(28, 30, 3, 0x50, 0x10, 25, 1), + PIN_FIELD_BASE(31, 31, 3, 0x50, 0x10, 24, 1), + PIN_FIELD_BASE(32, 32, 3, 0x50, 0x10, 28, 1), + PIN_FIELD_BASE(33, 33, 3, 0x60, 0x10, 0, 1), + PIN_FIELD_BASE(34, 34, 3, 0x50, 0x10, 31, 1), + PIN_FIELD_BASE(35, 36, 3, 0x50, 0x10, 29, 1), + PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, 3, 0x50, 0x10, 11, 1), + PIN_FIELD_BASE(39, 39, 3, 0x50, 0x10, 10, 1), + PIN_FIELD_BASE(40, 41, 3, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, 3, 0x50, 0x10, 9, 1), + PIN_FIELD_BASE(43, 43, 3, 0x50, 0x10, 8, 1), + PIN_FIELD_BASE(44, 44, 3, 0x50, 0x10, 7, 1), + PIN_FIELD_BASE(45, 45, 3, 0x50, 0x10, 6, 1), + PIN_FIELD_BASE(46, 46, 3, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(47, 47, 3, 0x50, 0x10, 4, 1), + PIN_FIELD_BASE(48, 48, 3, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(49, 49, 3, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(50, 50, 3, 0x50, 0x10, 15, 1), + PIN_FIELD_BASE(51, 53, 3, 0x50, 0x10, 12, 1), + PIN_FIELD_BASE(54, 54, 3, 0x50, 0x10, 16, 1), + PIN_FIELD_BASE(55, 56, 1, 0x40, 0x10, 14, 1), + PIN_FIELD_BASE(57, 57, 1, 0x40, 0x10, 13, 1), + PIN_FIELD_BASE(58, 60, 1, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(61, 61, 1, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(62, 62, 1, 0x40, 0x10, 7, 1), + PIN_FIELD_BASE(63, 63, 1, 0x40, 0x10, 20, 1), + PIN_FIELD_BASE(64, 68, 1, 0x40, 0x10, 8, 1), + PIN_FIELD_BASE(69, 70, 5, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(71, 72, 5, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(73, 73, 4, 0x30, 0x10, 10, 1), + PIN_FIELD_BASE(74, 74, 4, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(75, 75, 4, 0x30, 0x10, 11, 1), + PIN_FIELD_BASE(76, 76, 4, 0x30, 0x10, 9, 1), + PIN_FIELD_BASE(77, 77, 4, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(78, 78, 4, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(79, 79, 4, 0x30, 0x10, 12, 1), + PIN_FIELD_BASE(80, 81, 1, 0x40, 0x10, 18, 1), + PIN_FIELD_BASE(82, 83, 1, 0x40, 0x10, 16, 1), +}; + +static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = { + PIN_FIELD_BASE(0, 1, 5, 0xc0, 0x10, 13, 1), + PIN_FIELD_BASE(2, 3, 5, 0xc0, 0x10, 11, 1), + PIN_FIELD_BASE(4, 4, 5, 0xc0, 0x10, 0, 1), + PIN_FIELD_BASE(5, 6, 5, 0xc0, 0x10, 9, 1), + PIN_FIELD_BASE(7, 7, 4, 0xb0, 0x10, 8, 1), + PIN_FIELD_BASE(8, 8, 4, 0xb0, 0x10, 6, 1), + PIN_FIELD_BASE(9, 9, 4, 0xb0, 0x10, 5, 1), + PIN_FIELD_BASE(10, 10, 4, 0xb0, 0x10, 3, 1), + PIN_FIELD_BASE(11, 11, 1, 0xe0, 0x10, 0, 1), + PIN_FIELD_BASE(12, 12, 1, 0xe0, 0x10, 21, 1), + PIN_FIELD_BASE(13, 14, 1, 0xe0, 0x10, 1, 1), + PIN_FIELD_BASE(15, 16, 5, 0xc0, 0x10, 7, 1), + PIN_FIELD_BASE(17, 18, 5, 0xc0, 0x10, 3, 1), + PIN_FIELD_BASE(19, 19, 4, 0xb0, 0x10, 7, 1), + PIN_FIELD_BASE(20, 20, 4, 0xb0, 0x10, 4, 1), + PIN_FIELD_BASE(21, 21, 3, 0x140, 0x10, 17, 1), + PIN_FIELD_BASE(22, 22, 3, 0x140, 0x10, 23, 1), + PIN_FIELD_BASE(23, 23, 3, 0x140, 0x10, 20, 1), + PIN_FIELD_BASE(24, 24, 3, 0x140, 0x10, 19, 1), + PIN_FIELD_BASE(25, 26, 3, 0x140, 0x10, 21, 1), + PIN_FIELD_BASE(27, 27, 3, 0x140, 0x10, 18, 1), + PIN_FIELD_BASE(28, 30, 3, 0x140, 0x10, 25, 1), + PIN_FIELD_BASE(31, 31, 3, 0x140, 0x10, 24, 1), + PIN_FIELD_BASE(32, 32, 3, 0x140, 0x10, 28, 1), + PIN_FIELD_BASE(33, 33, 3, 0x150, 0x10, 0, 1), + PIN_FIELD_BASE(34, 34, 3, 0x140, 0x10, 31, 1), + PIN_FIELD_BASE(35, 36, 3, 0x140, 0x10, 29, 1), + PIN_FIELD_BASE(37, 37, 3, 0x150, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, 3, 0x140, 0x10, 11, 1), + PIN_FIELD_BASE(39, 39, 3, 0x140, 0x10, 10, 1), + PIN_FIELD_BASE(40, 41, 3, 0x140, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, 3, 0x140, 0x10, 9, 1), + PIN_FIELD_BASE(43, 43, 3, 0x140, 0x10, 8, 1), + PIN_FIELD_BASE(44, 44, 3, 0x140, 0x10, 7, 1), + PIN_FIELD_BASE(45, 45, 3, 0x140, 0x10, 6, 1), + PIN_FIELD_BASE(46, 46, 3, 0x140, 0x10, 5, 1), + PIN_FIELD_BASE(47, 47, 3, 0x140, 0x10, 4, 1), + PIN_FIELD_BASE(48, 48, 3, 0x140, 0x10, 3, 1), + PIN_FIELD_BASE(49, 49, 3, 0x140, 0x10, 2, 1), + PIN_FIELD_BASE(50, 50, 3, 0x140, 0x10, 15, 1), + PIN_FIELD_BASE(51, 53, 3, 0x140, 0x10, 12, 1), + PIN_FIELD_BASE(54, 54, 3, 0x140, 0x10, 16, 1), + PIN_FIELD_BASE(55, 56, 1, 0xe0, 0x10, 14, 1), + PIN_FIELD_BASE(57, 57, 1, 0xe0, 0x10, 13, 1), + PIN_FIELD_BASE(58, 60, 1, 0xe0, 0x10, 4, 1), + PIN_FIELD_BASE(61, 61, 1, 0xe0, 0x10, 3, 1), + PIN_FIELD_BASE(62, 62, 1, 0xe0, 0x10, 7, 1), + PIN_FIELD_BASE(63, 63, 1, 0xe0, 0x10, 20, 1), + PIN_FIELD_BASE(64, 68, 1, 0xe0, 0x10, 8, 1), + PIN_FIELD_BASE(69, 70, 5, 0xc0, 0x10, 1, 1), + PIN_FIELD_BASE(71, 72, 5, 0xc0, 0x10, 5, 1), + PIN_FIELD_BASE(73, 73, 4, 0xb0, 0x10, 10, 1), + PIN_FIELD_BASE(74, 74, 4, 0xb0, 0x10, 1, 1), + PIN_FIELD_BASE(75, 75, 4, 0xb0, 0x10, 11, 1), + PIN_FIELD_BASE(76, 76, 4, 0xb0, 0x10, 9, 1), + PIN_FIELD_BASE(77, 77, 4, 0xb0, 0x10, 2, 1), + PIN_FIELD_BASE(78, 78, 4, 0xb0, 0x10, 0, 1), + PIN_FIELD_BASE(79, 79, 4, 0xb0, 0x10, 12, 1), + PIN_FIELD_BASE(80, 81, 1, 0xe0, 0x10, 18, 1), + PIN_FIELD_BASE(82, 83, 1, 0xe0, 0x10, 16, 1), +}; + +static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = { + PIN_FIELD_BASE(7, 7, 4, 0x60, 0x10, 5, 1), + PIN_FIELD_BASE(8, 8, 4, 0x60, 0x10, 4, 1), + PIN_FIELD_BASE(9, 9, 4, 0x60, 0x10, 3, 1), + PIN_FIELD_BASE(10, 10, 4, 0x60, 0x10, 2, 1), + PIN_FIELD_BASE(13, 14, 1, 0x70, 0x10, 0, 1), + PIN_FIELD_BASE(63, 63, 1, 0x70, 0x10, 2, 1), + PIN_FIELD_BASE(75, 75, 4, 0x60, 0x10, 7, 1), + PIN_FIELD_BASE(76, 76, 4, 0x60, 0x10, 6, 1), + PIN_FIELD_BASE(77, 77, 4, 0x60, 0x10, 1, 1), + PIN_FIELD_BASE(78, 78, 4, 0x60, 0x10, 0, 1), + PIN_FIELD_BASE(79, 79, 4, 0x60, 0x10, 8, 1), +}; + +static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = { + PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(9, 9, 4, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(10, 10, 4, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(13, 14, 1, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(15, 16, 5, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(17, 18, 5, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(63, 63, 1, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(71, 72, 5, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(75, 75, 4, 0x40, 0x10, 7, 1), + PIN_FIELD_BASE(76, 76, 4, 0x40, 0x10, 6, 1), + PIN_FIELD_BASE(77, 77, 4, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(78, 78, 4, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(79, 79, 4, 0x40, 0x10, 8, 1), +}; + +static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = { + PIN_FIELD_BASE(0, 1, 5, 0x00, 0x10, 21, 3), + PIN_FIELD_BASE(2, 3, 5, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(4, 4, 5, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(5, 6, 5, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 24, 3), + PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 28, 3), + PIN_FIELD_BASE(9, 9, 4, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(10, 10, 4, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(11, 11, 1, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(12, 12, 1, 0x20, 0x10, 3, 3), + PIN_FIELD_BASE(13, 14, 1, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(19, 19, 4, 0x00, 0x10, 21, 3), + PIN_FIELD_BASE(20, 20, 4, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(21, 21, 3, 0x10, 0x10, 21, 3), + PIN_FIELD_BASE(22, 22, 3, 0x20, 0x10, 9, 3), + PIN_FIELD_BASE(23, 23, 3, 0x20, 0x10, 0, 3), + PIN_FIELD_BASE(24, 24, 3, 0x10, 0x10, 27, 3), + PIN_FIELD_BASE(25, 26, 3, 0x20, 0x10, 3, 3), + PIN_FIELD_BASE(27, 27, 3, 0x10, 0x10, 24, 3), + PIN_FIELD_BASE(28, 30, 3, 0x20, 0x10, 15, 3), + PIN_FIELD_BASE(31, 31, 3, 0x20, 0x10, 12, 3), + PIN_FIELD_BASE(32, 32, 3, 0x20, 0x10, 24, 3), + PIN_FIELD_BASE(33, 33, 3, 0x30, 0x10, 6, 3), + PIN_FIELD_BASE(34, 34, 3, 0x30, 0x10, 3, 3), + PIN_FIELD_BASE(35, 35, 3, 0x20, 0x10, 27, 3), + PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 0, 3), + PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 9, 3), + PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 3, 3), + PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 0, 3), + PIN_FIELD_BASE(40, 41, 3, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(42, 42, 3, 0x00, 0x10, 27, 3), + PIN_FIELD_BASE(43, 43, 3, 0x00, 0x10, 24, 3), + PIN_FIELD_BASE(44, 44, 3, 0x00, 0x10, 21, 3), + PIN_FIELD_BASE(45, 45, 3, 0x00, 0x10, 18, 3), + PIN_FIELD_BASE(46, 46, 3, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(47, 47, 3, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(48, 48, 3, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(49, 49, 3, 0x00, 0x10, 6, 3), + PIN_FIELD_BASE(50, 50, 3, 0x10, 0x10, 15, 3), + PIN_FIELD_BASE(51, 53, 3, 0x10, 0x10, 6, 3), + PIN_FIELD_BASE(54, 54, 3, 0x10, 0x10, 18, 3), + PIN_FIELD_BASE(55, 56, 1, 0x10, 0x10, 12, 3), + PIN_FIELD_BASE(57, 57, 1, 0x10, 0x10, 9, 3), + PIN_FIELD_BASE(58, 60, 1, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(61, 61, 1, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(62, 62, 1, 0x00, 0x10, 21, 3), + PIN_FIELD_BASE(63, 63, 1, 0x20, 0x10, 0, 3), + PIN_FIELD_BASE(64, 65, 1, 0x00, 0x10, 24, 3), + PIN_FIELD_BASE(66, 68, 1, 0x10, 0x10, 0, 3), + PIN_FIELD_BASE(69, 70, 5, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(73, 73, 4, 0x10, 0x10, 0, 3), + PIN_FIELD_BASE(74, 74, 4, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(75, 75, 4, 0x10, 0x10, 3, 3), + PIN_FIELD_BASE(76, 76, 4, 0x00, 0x10, 27, 3), + PIN_FIELD_BASE(77, 77, 4, 0x00, 0x10, 6, 3), + PIN_FIELD_BASE(78, 78, 4, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(79, 79, 4, 0x10, 0x10, 6, 3), + PIN_FIELD_BASE(80, 81, 1, 0x10, 0x10, 24, 3), + PIN_FIELD_BASE(82, 83, 1, 0x10, 0x10, 18, 3), +}; + +static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = { + PIN_FIELD_BASE(0, 1, 5, 0x50, 0x10, 7, 1), + PIN_FIELD_BASE(2, 3, 5, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(4, 4, 5, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(5, 6, 5, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(11, 11, 1, 0x60, 0x10, 0, 1), + PIN_FIELD_BASE(12, 12, 1, 0x60, 0x10, 18, 1), + PIN_FIELD_BASE(19, 19, 4, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(20, 20, 4, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(21, 21, 3, 0x70, 0x10, 17, 1), + PIN_FIELD_BASE(22, 22, 3, 0x70, 0x10, 23, 1), + PIN_FIELD_BASE(23, 23, 3, 0x70, 0x10, 20, 1), + PIN_FIELD_BASE(24, 24, 3, 0x70, 0x10, 19, 1), + PIN_FIELD_BASE(25, 26, 3, 0x70, 0x10, 21, 1), + PIN_FIELD_BASE(27, 27, 3, 0x70, 0x10, 18, 1), + PIN_FIELD_BASE(28, 30, 3, 0x70, 0x10, 25, 1), + PIN_FIELD_BASE(31, 31, 3, 0x70, 0x10, 24, 1), + PIN_FIELD_BASE(32, 32, 3, 0x70, 0x10, 28, 1), + PIN_FIELD_BASE(33, 33, 3, 0x80, 0x10, 0, 1), + PIN_FIELD_BASE(34, 34, 3, 0x70, 0x10, 31, 1), + PIN_FIELD_BASE(35, 36, 3, 0x70, 0x10, 29, 1), + PIN_FIELD_BASE(37, 37, 3, 0x80, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, 3, 0x70, 0x10, 11, 1), + PIN_FIELD_BASE(39, 39, 3, 0x70, 0x10, 10, 1), + PIN_FIELD_BASE(40, 41, 3, 0x70, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, 3, 0x70, 0x10, 9, 1), + PIN_FIELD_BASE(43, 43, 3, 0x70, 0x10, 8, 1), + PIN_FIELD_BASE(44, 44, 3, 0x70, 0x10, 7, 1), + PIN_FIELD_BASE(45, 45, 3, 0x70, 0x10, 6, 1), + PIN_FIELD_BASE(46, 46, 3, 0x70, 0x10, 5, 1), + PIN_FIELD_BASE(47, 47, 3, 0x70, 0x10, 4, 1), + PIN_FIELD_BASE(48, 48, 3, 0x70, 0x10, 3, 1), + PIN_FIELD_BASE(49, 49, 3, 0x70, 0x10, 2, 1), + PIN_FIELD_BASE(50, 50, 3, 0x70, 0x10, 15, 1), + PIN_FIELD_BASE(51, 53, 3, 0x70, 0x10, 12, 1), + PIN_FIELD_BASE(54, 54, 3, 0x70, 0x10, 16, 1), + PIN_FIELD_BASE(55, 56, 1, 0x60, 0x10, 12, 1), + PIN_FIELD_BASE(57, 57, 1, 0x60, 0x10, 11, 1), + PIN_FIELD_BASE(58, 60, 1, 0x60, 0x10, 2, 1), + PIN_FIELD_BASE(61, 61, 1, 0x60, 0x10, 1, 1), + PIN_FIELD_BASE(62, 62, 1, 0x60, 0x10, 5, 1), + PIN_FIELD_BASE(64, 68, 1, 0x60, 0x10, 6, 1), + PIN_FIELD_BASE(69, 70, 5, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(73, 73, 4, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(74, 74, 4, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(80, 81, 1, 0x60, 0x10, 16, 1), + PIN_FIELD_BASE(82, 83, 1, 0x60, 0x10, 14, 1), +}; + +static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = { + PIN_FIELD_BASE(0, 1, 5, 0x60, 0x10, 7, 1), + PIN_FIELD_BASE(2, 3, 5, 0x60, 0x10, 5, 1), + PIN_FIELD_BASE(4, 4, 5, 0x60, 0x10, 0, 1), + PIN_FIELD_BASE(5, 6, 5, 0x60, 0x10, 3, 1), + PIN_FIELD_BASE(11, 11, 1, 0x80, 0x10, 0, 1), + PIN_FIELD_BASE(12, 12, 1, 0x80, 0x10, 18, 1), + PIN_FIELD_BASE(19, 19, 4, 0x70, 0x10, 2, 1), + PIN_FIELD_BASE(20, 20, 4, 0x70, 0x10, 1, 1), + PIN_FIELD_BASE(21, 21, 3, 0x90, 0x10, 17, 1), + PIN_FIELD_BASE(22, 22, 3, 0x90, 0x10, 23, 1), + PIN_FIELD_BASE(23, 23, 3, 0x90, 0x10, 20, 1), + PIN_FIELD_BASE(24, 24, 3, 0x90, 0x10, 19, 1), + PIN_FIELD_BASE(25, 26, 3, 0x90, 0x10, 21, 1), + PIN_FIELD_BASE(27, 27, 3, 0x90, 0x10, 18, 1), + PIN_FIELD_BASE(28, 30, 3, 0x90, 0x10, 25, 1), + PIN_FIELD_BASE(31, 31, 3, 0x90, 0x10, 24, 1), + PIN_FIELD_BASE(32, 32, 3, 0x90, 0x10, 28, 1), + PIN_FIELD_BASE(33, 33, 3, 0xa0, 0x10, 0, 1), + PIN_FIELD_BASE(34, 34, 3, 0x90, 0x10, 31, 1), + PIN_FIELD_BASE(35, 36, 3, 0x90, 0x10, 29, 1), + PIN_FIELD_BASE(37, 37, 3, 0xa0, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, 3, 0x90, 0x10, 11, 1), + PIN_FIELD_BASE(39, 39, 3, 0x90, 0x10, 10, 1), + PIN_FIELD_BASE(40, 41, 3, 0x90, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, 3, 0x90, 0x10, 9, 1), + PIN_FIELD_BASE(43, 43, 3, 0x90, 0x10, 8, 1), + PIN_FIELD_BASE(44, 44, 3, 0x90, 0x10, 7, 1), + PIN_FIELD_BASE(45, 45, 3, 0x90, 0x10, 6, 1), + PIN_FIELD_BASE(46, 46, 3, 0x90, 0x10, 5, 1), + PIN_FIELD_BASE(47, 47, 3, 0x90, 0x10, 4, 1), + PIN_FIELD_BASE(48, 48, 3, 0x90, 0x10, 3, 1), + PIN_FIELD_BASE(49, 49, 3, 0x90, 0x10, 2, 1), + PIN_FIELD_BASE(50, 50, 3, 0x90, 0x10, 15, 1), + PIN_FIELD_BASE(51, 53, 3, 0x90, 0x10, 12, 1), + PIN_FIELD_BASE(54, 54, 3, 0x90, 0x10, 16, 1), + PIN_FIELD_BASE(55, 56, 1, 0x80, 0x10, 12, 1), + PIN_FIELD_BASE(57, 57, 1, 0x80, 0x10, 11, 1), + PIN_FIELD_BASE(58, 60, 1, 0x80, 0x10, 2, 1), + PIN_FIELD_BASE(61, 61, 1, 0x80, 0x10, 1, 1), + PIN_FIELD_BASE(62, 62, 1, 0x80, 0x10, 5, 1), + PIN_FIELD_BASE(64, 68, 1, 0x80, 0x10, 6, 1), + PIN_FIELD_BASE(69, 70, 5, 0x60, 0x10, 1, 1), + PIN_FIELD_BASE(73, 73, 4, 0x70, 0x10, 3, 1), + PIN_FIELD_BASE(74, 74, 4, 0x70, 0x10, 0, 1), + PIN_FIELD_BASE(80, 81, 1, 0x80, 0x10, 16, 1), + PIN_FIELD_BASE(82, 83, 1, 0x80, 0x10, 14, 1), +}; + +static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = { + PIN_FIELD_BASE(0, 1, 5, 0x70, 0x10, 7, 1), + PIN_FIELD_BASE(2, 3, 5, 0x70, 0x10, 5, 1), + PIN_FIELD_BASE(4, 4, 5, 0x70, 0x10, 0, 1), + PIN_FIELD_BASE(5, 6, 5, 0x70, 0x10, 3, 1), + PIN_FIELD_BASE(11, 11, 1, 0x90, 0x10, 0, 1), + PIN_FIELD_BASE(12, 12, 1, 0x90, 0x10, 18, 1), + PIN_FIELD_BASE(19, 19, 4, 0x80, 0x10, 2, 1), + PIN_FIELD_BASE(20, 20, 4, 0x80, 0x10, 1, 1), + PIN_FIELD_BASE(21, 21, 3, 0xb0, 0x10, 17, 1), + PIN_FIELD_BASE(22, 22, 3, 0xb0, 0x10, 23, 1), + PIN_FIELD_BASE(23, 23, 3, 0xb0, 0x10, 20, 1), + PIN_FIELD_BASE(24, 24, 3, 0xb0, 0x10, 19, 1), + PIN_FIELD_BASE(25, 26, 3, 0xb0, 0x10, 21, 1), + PIN_FIELD_BASE(27, 27, 3, 0xb0, 0x10, 18, 1), + PIN_FIELD_BASE(28, 30, 3, 0xb0, 0x10, 25, 1), + PIN_FIELD_BASE(31, 31, 3, 0xb0, 0x10, 24, 1), + PIN_FIELD_BASE(32, 32, 3, 0xb0, 0x10, 28, 1), + PIN_FIELD_BASE(33, 33, 3, 0xc0, 0x10, 0, 1), + PIN_FIELD_BASE(34, 34, 3, 0xb0, 0x10, 31, 1), + PIN_FIELD_BASE(35, 36, 3, 0xb0, 0x10, 29, 1), + PIN_FIELD_BASE(37, 37, 3, 0xc0, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, 3, 0xb0, 0x10, 11, 1), + PIN_FIELD_BASE(39, 39, 3, 0xb0, 0x10, 10, 1), + PIN_FIELD_BASE(40, 41, 3, 0xb0, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, 3, 0xb0, 0x10, 9, 1), + PIN_FIELD_BASE(43, 43, 3, 0xb0, 0x10, 8, 1), + PIN_FIELD_BASE(44, 44, 3, 0xb0, 0x10, 7, 1), + PIN_FIELD_BASE(45, 45, 3, 0xb0, 0x10, 6, 1), + PIN_FIELD_BASE(46, 46, 3, 0xb0, 0x10, 5, 1), + PIN_FIELD_BASE(47, 47, 3, 0xb0, 0x10, 4, 1), + PIN_FIELD_BASE(48, 48, 3, 0xb0, 0x10, 3, 1), + PIN_FIELD_BASE(49, 49, 3, 0xb0, 0x10, 2, 1), + PIN_FIELD_BASE(50, 50, 3, 0xb0, 0x10, 15, 1), + PIN_FIELD_BASE(51, 53, 3, 0xb0, 0x10, 12, 1), + PIN_FIELD_BASE(54, 54, 3, 0xb0, 0x10, 16, 1), + PIN_FIELD_BASE(55, 56, 1, 0x90, 0x10, 12, 1), + PIN_FIELD_BASE(57, 57, 1, 0x90, 0x10, 11, 1), + PIN_FIELD_BASE(58, 60, 1, 0x90, 0x10, 2, 1), + PIN_FIELD_BASE(61, 61, 1, 0x90, 0x10, 1, 1), + PIN_FIELD_BASE(62, 62, 1, 0x90, 0x10, 5, 1), + PIN_FIELD_BASE(64, 68, 1, 0x90, 0x10, 6, 1), + PIN_FIELD_BASE(69, 70, 5, 0x70, 0x10, 1, 1), + PIN_FIELD_BASE(73, 73, 4, 0x80, 0x10, 3, 1), + PIN_FIELD_BASE(74, 74, 4, 0x80, 0x10, 0, 1), + PIN_FIELD_BASE(80, 81, 1, 0x90, 0x10, 16, 1), + PIN_FIELD_BASE(82, 83, 1, 0x90, 0x10, 14, 1), +}; + +static const struct mtk_pin_reg_calc mt7988_reg_cals[] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7988_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7988_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7988_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7988_pin_do_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7988_pin_smt_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7988_pin_ies_range), + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7988_pin_pu_range), + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7988_pin_pd_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7988_pin_drv_range), + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7988_pin_pupd_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7988_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7988_pin_r1_range), +}; + +static const struct mtk_pin_desc mt7988_pins[] = { + MT7988_PIN(0, "UART2_RXD"), + MT7988_PIN(1, "UART2_TXD"), + MT7988_PIN(2, "UART2_CTS"), + MT7988_PIN(3, "UART2_RTS"), + MT7988_PIN(4, "GPIO_A"), + MT7988_PIN(5, "SMI_0_MDC"), + MT7988_PIN(6, "SMI_0_MDIO"), + MT7988_PIN(7, "PCIE30_2L_0_WAKE_N"), + MT7988_PIN(8, "PCIE30_2L_0_CLKREQ_N"), + MT7988_PIN(9, "PCIE30_1L_1_WAKE_N"), + MT7988_PIN(10, "PCIE30_1L_1_CLKREQ_N"), + MT7988_PIN(11, "GPIO_P"), + MT7988_PIN(12, "WATCHDOG"), + MT7988_PIN(13, "GPIO_RESET"), + MT7988_PIN(14, "GPIO_WPS"), + MT7988_PIN(15, "PMIC_I2C_SCL"), + MT7988_PIN(16, "PMIC_I2C_SDA"), + MT7988_PIN(17, "I2C_1_SCL"), + MT7988_PIN(18, "I2C_1_SDA"), + MT7988_PIN(19, "PCIE30_2L_0_PRESET_N"), + MT7988_PIN(20, "PCIE30_1L_1_PRESET_N"), + MT7988_PIN(21, "PWMD1"), + MT7988_PIN(22, "SPI0_WP"), + MT7988_PIN(23, "SPI0_HOLD"), + MT7988_PIN(24, "SPI0_CSB"), + MT7988_PIN(25, "SPI0_MISO"), + MT7988_PIN(26, "SPI0_MOSI"), + MT7988_PIN(27, "SPI0_CLK"), + MT7988_PIN(28, "SPI1_CSB"), + MT7988_PIN(29, "SPI1_MISO"), + MT7988_PIN(30, "SPI1_MOSI"), + MT7988_PIN(31, "SPI1_CLK"), + MT7988_PIN(32, "SPI2_CLK"), + MT7988_PIN(33, "SPI2_MOSI"), + MT7988_PIN(34, "SPI2_MISO"), + MT7988_PIN(35, "SPI2_CSB"), + MT7988_PIN(36, "SPI2_HOLD"), + MT7988_PIN(37, "SPI2_WP"), + MT7988_PIN(38, "EMMC_RSTB"), + MT7988_PIN(39, "EMMC_DSL"), + MT7988_PIN(40, "EMMC_CK"), + MT7988_PIN(41, "EMMC_CMD"), + MT7988_PIN(42, "EMMC_DATA_7"), + MT7988_PIN(43, "EMMC_DATA_6"), + MT7988_PIN(44, "EMMC_DATA_5"), + MT7988_PIN(45, "EMMC_DATA_4"), + MT7988_PIN(46, "EMMC_DATA_3"), + MT7988_PIN(47, "EMMC_DATA_2"), + MT7988_PIN(48, "EMMC_DATA_1"), + MT7988_PIN(49, "EMMC_DATA_0"), + MT7988_PIN(50, "PCM_FS_I2S_LRCK"), + MT7988_PIN(51, "PCM_CLK_I2S_BCLK"), + MT7988_PIN(52, "PCM_DRX_I2S_DIN"), + MT7988_PIN(53, "PCM_DTX_I2S_DOUT"), + MT7988_PIN(54, "PCM_MCK_I2S_MCLK"), + MT7988_PIN(55, "UART0_RXD"), + MT7988_PIN(56, "UART0_TXD"), + MT7988_PIN(57, "PWMD0"), + MT7988_PIN(58, "JTAG_JTDI"), + MT7988_PIN(59, "JTAG_JTDO"), + MT7988_PIN(60, "JTAG_JTMS"), + MT7988_PIN(61, "JTAG_JTCLK"), + MT7988_PIN(62, "JTAG_JTRST_N"), + MT7988_PIN(63, "USB_DRV_VBUS_P1"), + MT7988_PIN(64, "LED_A"), + MT7988_PIN(65, "LED_B"), + MT7988_PIN(66, "LED_C"), + MT7988_PIN(67, "LED_D"), + MT7988_PIN(68, "LED_E"), + MT7988_PIN(69, "GPIO_B"), + MT7988_PIN(70, "GPIO_C"), + MT7988_PIN(71, "I2C_2_SCL"), + MT7988_PIN(72, "I2C_2_SDA"), + MT7988_PIN(73, "PCIE30_2L_1_PRESET_N"), + MT7988_PIN(74, "PCIE30_1L_0_PRESET_N"), + MT7988_PIN(75, "PCIE30_2L_1_WAKE_N"), + MT7988_PIN(76, "PCIE30_2L_1_CLKREQ_N"), + MT7988_PIN(77, "PCIE30_1L_0_WAKE_N"), + MT7988_PIN(78, "PCIE30_1L_0_CLKREQ_N"), + MT7988_PIN(79, "USB_DRV_VBUS_P0"), + MT7988_PIN(80, "UART1_RXD"), + MT7988_PIN(81, "UART1_TXD"), + MT7988_PIN(82, "UART1_CTS"), + MT7988_PIN(83, "UART1_RTS"), +}; + +/* jtag */ +static int mt7988_tops_jtag0_0_pins[] = { 0, 1, 2, 3, 4 }; +static int mt7988_tops_jtag0_0_funcs[] = { 2, 2, 2, 2, 2 }; + +static int mt7988_wo0_jtag_pins[] = { 50, 51, 52, 53, 54 }; +static int mt7988_wo0_jtag_funcs[] = { 3, 3, 3, 3, 3 }; + +static int mt7988_wo1_jtag_pins[] = { 50, 51, 52, 53, 54 }; +static int mt7988_wo1_jtag_funcs[] = { 4, 4, 4, 4, 4 }; + +static int mt7988_wo2_jtag_pins[] = { 50, 51, 52, 53, 54 }; +static int mt7988_wo2_jtag_funcs[] = { 5, 5, 5, 5, 5 }; + +static int mt7988_jtag_pins[] = { 58, 59, 60, 61, 62 }; +static int mt7988_jtag_funcs[] = { 1, 1, 1, 1, 1 }; + +static int mt7988_tops_jtag0_1_pins[] = { 58, 59, 60, 61, 62 }; +static int mt7988_tops_jtag0_1_funcs[] = { 4, 4, 4, 4, 4 }; + +/* int_usxgmii */ +static int mt7988_int_usxgmii_pins[] = { 2, 3 }; +static int mt7988_int_usxgmii_funcs[] = { 3, 3 }; + +/* pwm */ +static int mt7988_pwm0_pins[] = { 57 }; +static int mt7988_pwm0_funcs[] = { 1 }; + +static int mt7988_pwm1_pins[] = { 21 }; +static int mt7988_pwm1_funcs[] = { 1 }; + +static int mt7988_pwm2_pins[] = { 80 }; +static int mt7988_pwm2_funcs[] = { 2 }; + +static int mt7988_pwm3_pins[] = { 81 }; +static int mt7988_pwm3_funcs[] = { 2 }; + +static int mt7988_pwm4_pins[] = { 82 }; +static int mt7988_pwm4_funcs[] = { 2 }; + +static int mt7988_pwm5_pins[] = { 83 }; +static int mt7988_pwm5_funcs[] = { 2 }; + +static int mt7988_pwm6_pins[] = { 69 }; +static int mt7988_pwm6_funcs[] = { 3 }; + +static int mt7988_pwm7_pins[] = { 70 }; +static int mt7988_pwm7_funcs[] = { 3 }; + +/* dfd */ +static int mt7988_dfd_pins[] = { 0, 1, 2, 3, 4 }; +static int mt7988_dfd_funcs[] = { 4, 4, 4, 4, 4 }; + +/* i2c */ +static int mt7988_xfi_phy0_i2c0_pins[] = { 0, 1 }; +static int mt7988_xfi_phy0_i2c0_funcs[] = { 5, 5 }; + +static int mt7988_xfi_phy1_i2c0_pins[] = { 0, 1 }; +static int mt7988_xfi_phy1_i2c0_funcs[] = { 6, 6 }; + +static int mt7988_xfi_phy_pll_i2c0_pins[] = { 3, 4 }; +static int mt7988_xfi_phy_pll_i2c0_funcs[] = { 5, 5 }; + +static int mt7988_xfi_phy_pll_i2c1_pins[] = { 3, 4 }; +static int mt7988_xfi_phy_pll_i2c1_funcs[] = { 6, 6 }; + +static int mt7988_i2c0_0_pins[] = { 5, 6 }; +static int mt7988_i2c0_0_funcs[] = { 2, 2 }; + +static int mt7988_i2c1_sfp_pins[] = { 5, 6 }; +static int mt7988_i2c1_sfp_funcs[] = { 4, 4 }; + +static int mt7988_xfi_pextp_phy0_i2c_pins[] = { 5, 6 }; +static int mt7988_xfi_pextp_phy0_i2c_funcs[] = { 5, 5 }; + +static int mt7988_xfi_pextp_phy1_i2c_pins[] = { 5, 6 }; +static int mt7988_xfi_pextp_phy1_i2c_funcs[] = { 6, 6 }; + +static int mt7988_i2c0_1_pins[] = { 15, 16 }; +static int mt7988_i2c0_1_funcs[] = { 1, 1 }; + +static int mt7988_u30_phy_i2c0_pins[] = { 15, 16 }; +static int mt7988_u30_phy_i2c0_funcs[] = { 2, 2 }; + +static int mt7988_u32_phy_i2c0_pins[] = { 15, 16 }; +static int mt7988_u32_phy_i2c0_funcs[] = { 3, 3 }; + +static int mt7988_xfi_phy0_i2c1_pins[] = { 15, 16 }; +static int mt7988_xfi_phy0_i2c1_funcs[] = { 5, 5 }; + +static int mt7988_xfi_phy1_i2c1_pins[] = { 15, 16 }; +static int mt7988_xfi_phy1_i2c1_funcs[] = { 6, 6 }; + +static int mt7988_xfi_phy_pll_i2c2_pins[] = { 15, 16 }; +static int mt7988_xfi_phy_pll_i2c2_funcs[] = { 7, 7 }; + +static int mt7988_i2c1_0_pins[] = { 17, 18 }; +static int mt7988_i2c1_0_funcs[] = { 1, 1 }; + +static int mt7988_u30_phy_i2c1_pins[] = { 17, 18 }; +static int mt7988_u30_phy_i2c1_funcs[] = { 2, 2 }; + +static int mt7988_u32_phy_i2c1_pins[] = { 17, 18 }; +static int mt7988_u32_phy_i2c1_funcs[] = { 3, 3 }; + +static int mt7988_xfi_phy_pll_i2c3_pins[] = { 17, 18 }; +static int mt7988_xfi_phy_pll_i2c3_funcs[] = { 4, 4 }; + +static int mt7988_sgmii0_i2c_pins[] = { 17, 18 }; +static int mt7988_sgmii0_i2c_funcs[] = { 5, 5 }; + +static int mt7988_sgmii1_i2c_pins[] = { 17, 18 }; +static int mt7988_sgmii1_i2c_funcs[] = { 6, 6 }; + +static int mt7988_i2c1_2_pins[] = { 69, 70 }; +static int mt7988_i2c1_2_funcs[] = { 2, 2 }; + +static int mt7988_i2c2_0_pins[] = { 69, 70 }; +static int mt7988_i2c2_0_funcs[] = { 4, 4 }; + +static int mt7988_i2c2_1_pins[] = { 71, 72 }; +static int mt7988_i2c2_1_funcs[] = { 1, 1 }; + +/* eth */ +static int mt7988_mdc_mdio0_pins[] = { 5, 6 }; +static int mt7988_mdc_mdio0_funcs[] = { 1, 1 }; + +static int mt7988_2p5g_ext_mdio_pins[] = { 28, 29 }; +static int mt7988_2p5g_ext_mdio_funcs[] = { 6, 6 }; + +static int mt7988_gbe_ext_mdio_pins[] = { 30, 31 }; +static int mt7988_gbe_ext_mdio_funcs[] = { 6, 6 }; + +static int mt7988_mdc_mdio1_pins[] = { 69, 70 }; +static int mt7988_mdc_mdio1_funcs[] = { 1, 1 }; + +/* pcie */ +static int mt7988_pcie_wake_n0_0_pins[] = { 7 }; +static int mt7988_pcie_wake_n0_0_funcs[] = { 1 }; + +static int mt7988_pcie_clk_req_n0_0_pins[] = { 8 }; +static int mt7988_pcie_clk_req_n0_0_funcs[] = { 1 }; + +static int mt7988_pcie_wake_n3_0_pins[] = { 9 }; +static int mt7988_pcie_wake_n3_0_funcs[] = { 1 }; + +static int mt7988_pcie_clk_req_n3_pins[] = { 10 }; +static int mt7988_pcie_clk_req_n3_funcs[] = { 1 }; + +static int mt7988_pcie_clk_req_n0_1_pins[] = { 10 }; +static int mt7988_pcie_clk_req_n0_1_funcs[] = { 2 }; + +static int mt7988_pcie_p0_phy_i2c_pins[] = { 7, 8 }; +static int mt7988_pcie_p0_phy_i2c_funcs[] = { 3, 3 }; + +static int mt7988_pcie_p1_phy_i2c_pins[] = { 7, 8 }; +static int mt7988_pcie_p1_phy_i2c_funcs[] = { 4, 4 }; + +static int mt7988_pcie_p3_phy_i2c_pins[] = { 9, 10 }; +static int mt7988_pcie_p3_phy_i2c_funcs[] = { 4, 4 }; + +static int mt7988_pcie_p2_phy_i2c_pins[] = { 7, 8 }; +static int mt7988_pcie_p2_phy_i2c_funcs[] = { 5, 5 }; + +static int mt7988_ckm_phy_i2c_pins[] = { 9, 10 }; +static int mt7988_ckm_phy_i2c_funcs[] = { 5, 5 }; + +static int mt7988_pcie_wake_n0_1_pins[] = { 13 }; +static int mt7988_pcie_wake_n0_1_funcs[] = { 2 }; + +static int mt7988_pcie_wake_n3_1_pins[] = { 14 }; +static int mt7988_pcie_wake_n3_1_funcs[] = { 2 }; + +static int mt7988_pcie_2l_0_pereset_pins[] = { 19 }; +static int mt7988_pcie_2l_0_pereset_funcs[] = { 1 }; + +static int mt7988_pcie_1l_1_pereset_pins[] = { 20 }; +static int mt7988_pcie_1l_1_pereset_funcs[] = { 1 }; + +static int mt7988_pcie_clk_req_n2_1_pins[] = { 63 }; +static int mt7988_pcie_clk_req_n2_1_funcs[] = { 2 }; + +static int mt7988_pcie_2l_1_pereset_pins[] = { 73 }; +static int mt7988_pcie_2l_1_pereset_funcs[] = { 1 }; + +static int mt7988_pcie_1l_0_pereset_pins[] = { 74 }; +static int mt7988_pcie_1l_0_pereset_funcs[] = { 1 }; + +static int mt7988_pcie_wake_n1_0_pins[] = { 75 }; +static int mt7988_pcie_wake_n1_0_funcs[] = { 1 }; + +static int mt7988_pcie_clk_req_n1_pins[] = { 76 }; +static int mt7988_pcie_clk_req_n1_funcs[] = { 1 }; + +static int mt7988_pcie_wake_n2_0_pins[] = { 77 }; +static int mt7988_pcie_wake_n2_0_funcs[] = { 1 }; + +static int mt7988_pcie_clk_req_n2_0_pins[] = { 78 }; +static int mt7988_pcie_clk_req_n2_0_funcs[] = { 1 }; + +static int mt7988_pcie_wake_n2_1_pins[] = { 79 }; +static int mt7988_pcie_wake_n2_1_funcs[] = { 2 }; + +/* pmic */ +static int mt7988_pmic_pins[] = { 11 }; +static int mt7988_pmic_funcs[] = { 1 }; + +/* watchdog */ +static int mt7988_watchdog_pins[] = { 12 }; +static int mt7988_watchdog_funcs[] = { 1 }; + +/* spi */ +static int mt7988_spi0_wp_hold_pins[] = { 22, 23 }; +static int mt7988_spi0_wp_hold_funcs[] = { 1, 1 }; + +static int mt7988_spi0_pins[] = { 24, 25, 26, 27 }; +static int mt7988_spi0_funcs[] = { 1, 1, 1, 1 }; + +static int mt7988_spi1_pins[] = { 28, 29, 30, 31 }; +static int mt7988_spi1_funcs[] = { 1, 1, 1, 1 }; + +static int mt7988_spi2_pins[] = { 32, 33, 34, 35 }; +static int mt7988_spi2_funcs[] = { 1, 1, 1, 1 }; + +static int mt7988_spi2_wp_hold_pins[] = { 36, 37 }; +static int mt7988_spi2_wp_hold_funcs[] = { 1, 1 }; + +/* flash */ +static int mt7988_snfi_pins[] = { 22, 23, 24, 25, 26, 27 }; +static int mt7988_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 }; + +static int mt7988_emmc_45_pins[] = { + 21, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37 +}; +static int mt7988_emmc_45_funcs[] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 }; + +static int mt7988_sdcard_pins[] = { 32, 33, 34, 35, 36, 37 }; +static int mt7988_sdcard_funcs[] = { 5, 5, 5, 5, 5, 5 }; + +static int mt7988_emmc_51_pins[] = { 38, 39, 40, 41, 42, 43, + 44, 45, 46, 47, 48, 49 }; +static int mt7988_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; + +/* uart */ +static int mt7988_uart2_pins[] = { 0, 1, 2, 3 }; +static int mt7988_uart2_funcs[] = { 1, 1, 1, 1 }; + +static int mt7988_tops_uart0_0_pins[] = { 22, 23 }; +static int mt7988_tops_uart0_0_funcs[] = { 3, 3 }; + +static int mt7988_uart2_0_pins[] = { 28, 29, 30, 31 }; +static int mt7988_uart2_0_funcs[] = { 2, 2, 2, 2 }; + +static int mt7988_uart1_0_pins[] = { 32, 33, 34, 35 }; +static int mt7988_uart1_0_funcs[] = { 2, 2, 2, 2 }; + +static int mt7988_uart2_1_pins[] = { 32, 33, 34, 35 }; +static int mt7988_uart2_1_funcs[] = { 3, 3, 3, 3 }; + +static int mt7988_net_wo0_uart_txd_0_pins[] = { 28 }; +static int mt7988_net_wo0_uart_txd_0_funcs[] = { 3 }; + +static int mt7988_net_wo1_uart_txd_0_pins[] = { 29 }; +static int mt7988_net_wo1_uart_txd_0_funcs[] = { 3 }; + +static int mt7988_net_wo2_uart_txd_0_pins[] = { 30 }; +static int mt7988_net_wo2_uart_txd_0_funcs[] = { 3 }; + +static int mt7988_tops_uart1_0_pins[] = { 28, 29 }; +static int mt7988_tops_uart1_0_funcs[] = { 4, 4 }; + +static int mt7988_tops_uart0_1_pins[] = { 30, 31 }; +static int mt7988_tops_uart0_1_funcs[] = { 4, 4 }; + +static int mt7988_tops_uart1_1_pins[] = { 36, 37 }; +static int mt7988_tops_uart1_1_funcs[] = { 3, 3 }; + +static int mt7988_uart0_pins[] = { 55, 56 }; +static int mt7988_uart0_funcs[] = { 1, 1 }; + +static int mt7988_tops_uart0_2_pins[] = { 55, 56 }; +static int mt7988_tops_uart0_2_funcs[] = { 2, 2 }; + +static int mt7988_uart2_2_pins[] = { 50, 51, 52, 53 }; +static int mt7988_uart2_2_funcs[] = { 2, 2, 2, 2 }; + +static int mt7988_uart1_1_pins[] = { 58, 59, 60, 61 }; +static int mt7988_uart1_1_funcs[] = { 2, 2, 2, 2 }; + +static int mt7988_uart2_3_pins[] = { 58, 59, 60, 61 }; +static int mt7988_uart2_3_funcs[] = { 3, 3, 3, 3 }; + +static int mt7988_uart1_2_pins[] = { 80, 81, 82, 83 }; +static int mt7988_uart1_2_funcs[] = { 1, 1, 1, 1 }; + +static int mt7988_tops_uart1_2_pins[] = { 80, 81 }; +static int mt7988_tops_uart1_2_funcs[] = { + 4, + 4, +}; + +static int mt7988_net_wo0_uart_txd_1_pins[] = { 80 }; +static int mt7988_net_wo0_uart_txd_1_funcs[] = { 3 }; + +static int mt7988_net_wo1_uart_txd_1_pins[] = { 81 }; +static int mt7988_net_wo1_uart_txd_1_funcs[] = { 3 }; + +static int mt7988_net_wo2_uart_txd_1_pins[] = { 82 }; +static int mt7988_net_wo2_uart_txd_1_funcs[] = { 3 }; + +/* udi */ +static int mt7988_udi_pins[] = { 32, 33, 34, 35, 36 }; +static int mt7988_udi_funcs[] = { 4, 4, 4, 4, 4 }; + +/* i2s */ +static int mt7988_i2s_pins[] = { 50, 51, 52, 53, 54 }; +static int mt7988_i2s_funcs[] = { 1, 1, 1, 1, 1 }; + +/* pcm */ +static int mt7988_pcm_pins[] = { 50, 51, 52, 53 }; +static int mt7988_pcm_funcs[] = { 1, 1, 1, 1 }; + +/* led */ +static int mt7988_gbe0_led1_pins[] = { 58 }; +static int mt7988_gbe0_led1_funcs[] = { 6 }; +static int mt7988_gbe1_led1_pins[] = { 59 }; +static int mt7988_gbe1_led1_funcs[] = { 6 }; +static int mt7988_gbe2_led1_pins[] = { 60 }; +static int mt7988_gbe2_led1_funcs[] = { 6 }; +static int mt7988_gbe3_led1_pins[] = { 61 }; +static int mt7988_gbe3_led1_funcs[] = { 6 }; + +static int mt7988_2p5gbe_led1_pins[] = { 62 }; +static int mt7988_2p5gbe_led1_funcs[] = { 6 }; + +static int mt7988_gbe0_led0_pins[] = { 64 }; +static int mt7988_gbe0_led0_funcs[] = { 1 }; +static int mt7988_gbe1_led0_pins[] = { 65 }; +static int mt7988_gbe1_led0_funcs[] = { 1 }; +static int mt7988_gbe2_led0_pins[] = { 66 }; +static int mt7988_gbe2_led0_funcs[] = { 1 }; +static int mt7988_gbe3_led0_pins[] = { 67 }; +static int mt7988_gbe3_led0_funcs[] = { 1 }; + +static int mt7988_2p5gbe_led0_pins[] = { 68 }; +static int mt7988_2p5gbe_led0_funcs[] = { 1 }; + +/* usb */ +static int mt7988_drv_vbus_p1_pins[] = { 63 }; +static int mt7988_drv_vbus_p1_funcs[] = { 1 }; + +static int mt7988_drv_vbus_pins[] = { 79 }; +static int mt7988_drv_vbus_funcs[] = { 1 }; + +static const struct group_desc mt7988_groups[] = { + /* @GPIO(0,1,2,3): uart2 */ + PINCTRL_PIN_GROUP("uart2", mt7988_uart2), + /* @GPIO(0,1,2,3,4): tops_jtag0_0 */ + PINCTRL_PIN_GROUP("tops_jtag0_0", mt7988_tops_jtag0_0), + /* @GPIO(2,3): int_usxgmii */ + PINCTRL_PIN_GROUP("int_usxgmii", mt7988_int_usxgmii), + /* @GPIO(0,1,2,3,4): dfd */ + PINCTRL_PIN_GROUP("dfd", mt7988_dfd), + /* @GPIO(0,1): xfi_phy0_i2c0 */ + PINCTRL_PIN_GROUP("xfi_phy0_i2c0", mt7988_xfi_phy0_i2c0), + /* @GPIO(0,1): xfi_phy1_i2c0 */ + PINCTRL_PIN_GROUP("xfi_phy1_i2c0", mt7988_xfi_phy1_i2c0), + /* @GPIO(3,4): xfi_phy_pll_i2c0 */ + PINCTRL_PIN_GROUP("xfi_phy_pll_i2c0", mt7988_xfi_phy_pll_i2c0), + /* @GPIO(3,4): xfi_phy_pll_i2c1 */ + PINCTRL_PIN_GROUP("xfi_phy_pll_i2c1", mt7988_xfi_phy_pll_i2c1), + /* @GPIO(5,6) i2c0_0 */ + PINCTRL_PIN_GROUP("i2c0_0", mt7988_i2c0_0), + /* @GPIO(5,6) i2c1_sfp */ + PINCTRL_PIN_GROUP("i2c1_sfp", mt7988_i2c1_sfp), + /* @GPIO(5,6) xfi_pextp_phy0_i2c */ + PINCTRL_PIN_GROUP("xfi_pextp_phy0_i2c", mt7988_xfi_pextp_phy0_i2c), + /* @GPIO(5,6) xfi_pextp_phy1_i2c */ + PINCTRL_PIN_GROUP("xfi_pextp_phy1_i2c", mt7988_xfi_pextp_phy1_i2c), + /* @GPIO(5,6) mdc_mdio0 */ + PINCTRL_PIN_GROUP("mdc_mdio0", mt7988_mdc_mdio0), + /* @GPIO(7): pcie_wake_n0_0 */ + PINCTRL_PIN_GROUP("pcie_wake_n0_0", mt7988_pcie_wake_n0_0), + /* @GPIO(8): pcie_clk_req_n0_0 */ + PINCTRL_PIN_GROUP("pcie_clk_req_n0_0", mt7988_pcie_clk_req_n0_0), + /* @GPIO(9): pcie_wake_n3_0 */ + PINCTRL_PIN_GROUP("pcie_wake_n3_0", mt7988_pcie_wake_n3_0), + /* @GPIO(10): pcie_clk_req_n3 */ + PINCTRL_PIN_GROUP("pcie_clk_req_n3", mt7988_pcie_clk_req_n3), + /* @GPIO(10): pcie_clk_req_n0_1 */ + PINCTRL_PIN_GROUP("pcie_clk_req_n0_1", mt7988_pcie_clk_req_n0_1), + /* @GPIO(7,8) pcie_p0_phy_i2c */ + PINCTRL_PIN_GROUP("pcie_p0_phy_i2c", mt7988_pcie_p0_phy_i2c), + /* @GPIO(7,8) pcie_p1_phy_i2c */ + PINCTRL_PIN_GROUP("pcie_p1_phy_i2c", mt7988_pcie_p1_phy_i2c), + /* @GPIO(7,8) pcie_p2_phy_i2c */ + PINCTRL_PIN_GROUP("pcie_p2_phy_i2c", mt7988_pcie_p2_phy_i2c), + /* @GPIO(9,10) pcie_p3_phy_i2c */ + PINCTRL_PIN_GROUP("pcie_p3_phy_i2c", mt7988_pcie_p3_phy_i2c), + /* @GPIO(9,10) ckm_phy_i2c */ + PINCTRL_PIN_GROUP("ckm_phy_i2c", mt7988_ckm_phy_i2c), + /* @GPIO(11): pmic */ + PINCTRL_PIN_GROUP("pcie_pmic", mt7988_pmic), + /* @GPIO(12): watchdog */ + PINCTRL_PIN_GROUP("watchdog", mt7988_watchdog), + /* @GPIO(13): pcie_wake_n0_1 */ + PINCTRL_PIN_GROUP("pcie_wake_n0_1", mt7988_pcie_wake_n0_1), + /* @GPIO(14): pcie_wake_n3_1 */ + PINCTRL_PIN_GROUP("pcie_wake_n3_1", mt7988_pcie_wake_n3_1), + /* @GPIO(15,16) i2c0_1 */ + PINCTRL_PIN_GROUP("i2c0_1", mt7988_i2c0_1), + /* @GPIO(15,16) u30_phy_i2c0 */ + PINCTRL_PIN_GROUP("u30_phy_i2c0", mt7988_u30_phy_i2c0), + /* @GPIO(15,16) u32_phy_i2c0 */ + PINCTRL_PIN_GROUP("u32_phy_i2c0", mt7988_u32_phy_i2c0), + /* @GPIO(15,16) xfi_phy0_i2c1 */ + PINCTRL_PIN_GROUP("xfi_phy0_i2c1", mt7988_xfi_phy0_i2c1), + /* @GPIO(15,16) xfi_phy1_i2c1 */ + PINCTRL_PIN_GROUP("xfi_phy1_i2c1", mt7988_xfi_phy1_i2c1), + /* @GPIO(15,16) xfi_phy_pll_i2c2 */ + PINCTRL_PIN_GROUP("xfi_phy_pll_i2c2", mt7988_xfi_phy_pll_i2c2), + /* @GPIO(17,18) i2c1_0 */ + PINCTRL_PIN_GROUP("i2c1_0", mt7988_i2c1_0), + /* @GPIO(17,18) u30_phy_i2c1 */ + PINCTRL_PIN_GROUP("u30_phy_i2c1", mt7988_u30_phy_i2c1), + /* @GPIO(17,18) u32_phy_i2c1 */ + PINCTRL_PIN_GROUP("u32_phy_i2c1", mt7988_u32_phy_i2c1), + /* @GPIO(17,18) xfi_phy_pll_i2c3 */ + PINCTRL_PIN_GROUP("xfi_phy_pll_i2c3", mt7988_xfi_phy_pll_i2c3), + /* @GPIO(17,18) sgmii0_i2c */ + PINCTRL_PIN_GROUP("sgmii0_i2c", mt7988_sgmii0_i2c), + /* @GPIO(17,18) sgmii1_i2c */ + PINCTRL_PIN_GROUP("sgmii1_i2c", mt7988_sgmii1_i2c), + /* @GPIO(19): pcie_2l_0_pereset */ + PINCTRL_PIN_GROUP("pcie_2l_0_pereset", mt7988_pcie_2l_0_pereset), + /* @GPIO(20): pcie_1l_1_pereset */ + PINCTRL_PIN_GROUP("pcie_1l_1_pereset", mt7988_pcie_1l_1_pereset), + /* @GPIO(21): pwm1 */ + PINCTRL_PIN_GROUP("pwm1", mt7988_pwm1), + /* @GPIO(22,23) spi0_wp_hold */ + PINCTRL_PIN_GROUP("spi0_wp_hold", mt7988_spi0_wp_hold), + /* @GPIO(24,25,26,27) spi0 */ + PINCTRL_PIN_GROUP("spi0", mt7988_spi0), + /* @GPIO(28,29,30,31) spi1 */ + PINCTRL_PIN_GROUP("spi1", mt7988_spi1), + /* @GPIO(32,33,34,35) spi2 */ + PINCTRL_PIN_GROUP("spi2", mt7988_spi2), + /* @GPIO(36,37) spi2_wp_hold */ + PINCTRL_PIN_GROUP("spi2_wp_hold", mt7988_spi2_wp_hold), + /* @GPIO(22,23,24,25,26,27) snfi */ + PINCTRL_PIN_GROUP("snfi", mt7988_snfi), + /* @GPIO(22,23) tops_uart0_0 */ + PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart0_0), + /* @GPIO(28,29,30,31) uart2_0 */ + PINCTRL_PIN_GROUP("uart2_0", mt7988_uart2_0), + /* @GPIO(32,33,34,35) uart1_0 */ + PINCTRL_PIN_GROUP("uart1_0", mt7988_uart1_0), + /* @GPIO(32,33,34,35) uart2_1 */ + PINCTRL_PIN_GROUP("uart2_1", mt7988_uart2_1), + /* @GPIO(28) net_wo0_uart_txd_0 */ + PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0), + /* @GPIO(29) net_wo1_uart_txd_0 */ + PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0), + /* @GPIO(30) net_wo2_uart_txd_0 */ + PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0), + /* @GPIO(28,29) tops_uart1_0 */ + PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart1_0), + /* @GPIO(30,31) tops_uart0_1 */ + PINCTRL_PIN_GROUP("tops_uart0_1", mt7988_tops_uart0_1), + /* @GPIO(36,37) tops_uart1_1 */ + PINCTRL_PIN_GROUP("tops_uart1_1", mt7988_tops_uart1_1), + /* @GPIO(32,33,34,35,36) udi */ + PINCTRL_PIN_GROUP("udi", mt7988_udi), + /* @GPIO(21,28,29,30,31,32,33,34,35,36,37) emmc_45 */ + PINCTRL_PIN_GROUP("emmc_45", mt7988_emmc_45), + /* @GPIO(32,33,34,35,36,37) sdcard */ + PINCTRL_PIN_GROUP("sdcard", mt7988_sdcard), + /* @GPIO(38,39,40,41,42,43,44,45,46,47,48,49) emmc_51 */ + PINCTRL_PIN_GROUP("emmc_51", mt7988_emmc_51), + /* @GPIO(28,29) 2p5g_ext_mdio */ + PINCTRL_PIN_GROUP("2p5g_ext_mdio", mt7988_2p5g_ext_mdio), + /* @GPIO(30,31) gbe_ext_mdio */ + PINCTRL_PIN_GROUP("gbe_ext_mdio", mt7988_gbe_ext_mdio), + /* @GPIO(50,51,52,53,54) i2s */ + PINCTRL_PIN_GROUP("i2s", mt7988_i2s), + /* @GPIO(50,51,52,53) pcm */ + PINCTRL_PIN_GROUP("pcm", mt7988_pcm), + /* @GPIO(55,56) uart0 */ + PINCTRL_PIN_GROUP("uart0", mt7988_uart0), + /* @GPIO(55,56) tops_uart0_2 */ + PINCTRL_PIN_GROUP("tops_uart0_2", mt7988_tops_uart0_2), + /* @GPIO(50,51,52,53) uart2_2 */ + PINCTRL_PIN_GROUP("uart2_2", mt7988_uart2_2), + /* @GPIO(50,51,52,53,54) wo0_jtag */ + PINCTRL_PIN_GROUP("wo0_jtag", mt7988_wo0_jtag), + /* @GPIO(50,51,52,53,54) wo1-wo1_jtag */ + PINCTRL_PIN_GROUP("wo1_jtag", mt7988_wo1_jtag), + /* @GPIO(50,51,52,53,54) wo2_jtag */ + PINCTRL_PIN_GROUP("wo2_jtag", mt7988_wo2_jtag), + /* @GPIO(57) pwm0 */ + PINCTRL_PIN_GROUP("pwm0", mt7988_pwm0), + /* @GPIO(58,59,60,61,62) jtag */ + PINCTRL_PIN_GROUP("jtag", mt7988_jtag), + /* @GPIO(58,59,60,61,62) tops_jtag0_1 */ + PINCTRL_PIN_GROUP("tops_jtag0_1", mt7988_tops_jtag0_1), + /* @GPIO(58,59,60,61) uart2_3 */ + PINCTRL_PIN_GROUP("uart2_3", mt7988_uart2_3), + /* @GPIO(58,59,60,61) uart1_1 */ + PINCTRL_PIN_GROUP("uart1_1", mt7988_uart1_1), + /* @GPIO(58,59,60,61) gbe_led1 */ + PINCTRL_PIN_GROUP("gbe0_led1", mt7988_gbe0_led1), + PINCTRL_PIN_GROUP("gbe1_led1", mt7988_gbe1_led1), + PINCTRL_PIN_GROUP("gbe2_led1", mt7988_gbe2_led1), + PINCTRL_PIN_GROUP("gbe3_led1", mt7988_gbe3_led1), + /* @GPIO(62) 2p5gbe_led1 */ + PINCTRL_PIN_GROUP("2p5gbe_led1", mt7988_2p5gbe_led1), + /* @GPIO(64,65,66,67) gbe_led0 */ + PINCTRL_PIN_GROUP("gbe0_led0", mt7988_gbe0_led0), + PINCTRL_PIN_GROUP("gbe1_led0", mt7988_gbe1_led0), + PINCTRL_PIN_GROUP("gbe2_led0", mt7988_gbe2_led0), + PINCTRL_PIN_GROUP("gbe3_led0", mt7988_gbe3_led0), + /* @GPIO(68) 2p5gbe_led0 */ + PINCTRL_PIN_GROUP("2p5gbe_led0", mt7988_2p5gbe_led0), + /* @GPIO(63) drv_vbus_p1 */ + PINCTRL_PIN_GROUP("drv_vbus_p1", mt7988_drv_vbus_p1), + /* @GPIO(63) pcie_clk_req_n2_1 */ + PINCTRL_PIN_GROUP("pcie_clk_req_n2_1", mt7988_pcie_clk_req_n2_1), + /* @GPIO(69, 70) mdc_mdio1 */ + PINCTRL_PIN_GROUP("mdc_mdio1", mt7988_mdc_mdio1), + /* @GPIO(69, 70) i2c1_2 */ + PINCTRL_PIN_GROUP("i2c1_2", mt7988_i2c1_2), + /* @GPIO(69) pwm6 */ + PINCTRL_PIN_GROUP("pwm6", mt7988_pwm6), + /* @GPIO(70) pwm7 */ + PINCTRL_PIN_GROUP("pwm7", mt7988_pwm7), + /* @GPIO(69,70) i2c2_0 */ + PINCTRL_PIN_GROUP("i2c2_0", mt7988_i2c2_0), + /* @GPIO(71,72) i2c2_1 */ + PINCTRL_PIN_GROUP("i2c2_1", mt7988_i2c2_1), + /* @GPIO(73) pcie_2l_1_pereset */ + PINCTRL_PIN_GROUP("pcie_2l_1_pereset", mt7988_pcie_2l_1_pereset), + /* @GPIO(74) pcie_1l_0_pereset */ + PINCTRL_PIN_GROUP("pcie_1l_0_pereset", mt7988_pcie_1l_0_pereset), + /* @GPIO(75) pcie_wake_n1_0 */ + PINCTRL_PIN_GROUP("pcie_wake_n1_0", mt7988_pcie_wake_n1_0), + /* @GPIO(76) pcie_clk_req_n1 */ + PINCTRL_PIN_GROUP("pcie_clk_req_n1", mt7988_pcie_clk_req_n1), + /* @GPIO(77) pcie_wake_n2_0 */ + PINCTRL_PIN_GROUP("pcie_wake_n2_0", mt7988_pcie_wake_n2_0), + /* @GPIO(78) pcie_clk_req_n2_0 */ + PINCTRL_PIN_GROUP("pcie_clk_req_n2_0", mt7988_pcie_clk_req_n2_0), + /* @GPIO(79) drv_vbus */ + PINCTRL_PIN_GROUP("drv_vbus", mt7988_drv_vbus), + /* @GPIO(79) pcie_wake_n2_1 */ + PINCTRL_PIN_GROUP("pcie_wake_n2_1", mt7988_pcie_wake_n2_1), + /* @GPIO(80,81,82,83) uart1_2 */ + PINCTRL_PIN_GROUP("uart1_2", mt7988_uart1_2), + /* @GPIO(80) pwm2 */ + PINCTRL_PIN_GROUP("pwm2", mt7988_pwm2), + /* @GPIO(81) pwm3 */ + PINCTRL_PIN_GROUP("pwm3", mt7988_pwm3), + /* @GPIO(82) pwm4 */ + PINCTRL_PIN_GROUP("pwm4", mt7988_pwm4), + /* @GPIO(83) pwm5 */ + PINCTRL_PIN_GROUP("pwm5", mt7988_pwm5), + /* @GPIO(80) net_wo0_uart_txd_0 */ + PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0), + /* @GPIO(81) net_wo1_uart_txd_0 */ + PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0), + /* @GPIO(82) net_wo2_uart_txd_0 */ + PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0), + /* @GPIO(80,81) tops_uart1_2 */ + PINCTRL_PIN_GROUP("tops_uart1_2", mt7988_tops_uart1_2), + /* @GPIO(80) net_wo0_uart_txd_1 */ + PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7988_net_wo0_uart_txd_1), + /* @GPIO(81) net_wo1_uart_txd_1 */ + PINCTRL_PIN_GROUP("net_wo1_uart_txd_1", mt7988_net_wo1_uart_txd_1), + /* @GPIO(82) net_wo2_uart_txd_1 */ + PINCTRL_PIN_GROUP("net_wo2_uart_txd_1", mt7988_net_wo2_uart_txd_1), +}; + +/* Joint those groups owning the same capability in user point of view which + * allows that people tend to use through the device tree. + */ +static const char *mt7988_jtag_groups[] = { + "tops_jtag0_0", "wo0_jtag", "wo1_jtag", + "wo2_jtag", "jtag", "tops_jtag0_1", +}; +static const char *mt7988_int_usxgmii_groups[] = { + "int_usxgmii", +}; +static const char *mt7988_pwm_groups[] = { + "pwm0", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5", "pwm6", "pwm7" +}; +static const char *mt7988_dfd_groups[] = { + "dfd", +}; +static const char *mt7988_i2c_groups[] = { + "xfi_phy0_i2c0", + "xfi_phy1_i2c0", + "xfi_phy_pll_i2c0", + "xfi_phy_pll_i2c1", + "i2c0_0", + "i2c1_sfp", + "xfi_pextp_phy0_i2c", + "xfi_pextp_phy1_i2c", + "i2c0_1", + "u30_phy_i2c0", + "u32_phy_i2c0", + "xfi_phy0_i2c1", + "xfi_phy1_i2c1", + "xfi_phy_pll_i2c2", + "i2c1_0", + "u30_phy_i2c1", + "u32_phy_i2c1", + "xfi_phy_pll_i2c3", + "sgmii0_i2c", + "sgmii1_i2c", + "i2c1_2", + "i2c2_0", + "i2c2_1", +}; +static const char *mt7988_ethernet_groups[] = { + "mdc_mdio0", + "2p5g_ext_mdio", + "gbe_ext_mdio", + "mdc_mdio1", +}; +static const char *mt7988_pcie_groups[] = { + "pcie_wake_n0_0", "pcie_clk_req_n0_0", "pcie_wake_n3_0", + "pcie_clk_req_n3", "pcie_p0_phy_i2c", "pcie_p1_phy_i2c", + "pcie_p3_phy_i2c", "pcie_p2_phy_i2c", "ckm_phy_i2c", + "pcie_wake_n0_1", "pcie_wake_n3_1", "pcie_2l_0_pereset", + "pcie_1l_1_pereset", "pcie_clk_req_n2_1", "pcie_2l_1_pereset", + "pcie_1l_0_pereset", "pcie_wake_n1_0", "pcie_clk_req_n1", + "pcie_wake_n2_0", "pcie_clk_req_n2_0", "pcie_wake_n2_1", + "pcie_clk_req_n0_1" +}; +static const char *mt7988_pmic_groups[] = { + "pmic", +}; +static const char *mt7988_wdt_groups[] = { + "watchdog", +}; +static const char *mt7988_spi_groups[] = { + "spi0", "spi0_wp_hold", "spi1", "spi2", "spi2_wp_hold", +}; +static const char *mt7988_flash_groups[] = { "emmc_45", "sdcard", "snfi", + "emmc_51" }; +static const char *mt7988_uart_groups[] = { + "uart2", + "tops_uart0_0", + "uart2_0", + "uart1_0", + "uart2_1", + "net_wo0_uart_txd_0", + "net_wo1_uart_txd_0", + "net_wo2_uart_txd_0", + "tops_uart1_0", + "ops_uart0_1", + "ops_uart1_1", + "uart0", + "tops_uart0_2", + "uart1_1", + "uart2_3", + "uart1_2", + "tops_uart1_2", + "net_wo0_uart_txd_1", + "net_wo1_uart_txd_1", + "net_wo2_uart_txd_1", +}; +static const char *mt7988_udi_groups[] = { + "udi", +}; +static const char *mt7988_audio_groups[] = { + "i2s", "pcm", +}; +static const char *mt7988_led_groups[] = { + "gbe0_led1", "gbe1_led1", "gbe2_led1", "gbe3_led1", "2p5gbe_led1", + "gbe0_led0", "gbe1_led0", "gbe2_led0", "gbe3_led0", "2p5gbe_led0", + "wf5g_led0", "wf5g_led1", +}; +static const char *mt7988_usb_groups[] = { + "drv_vbus", + "drv_vbus_p1", +}; + +static const struct function_desc mt7988_functions[] = { + { "audio", mt7988_audio_groups, ARRAY_SIZE(mt7988_audio_groups) }, + { "jtag", mt7988_jtag_groups, ARRAY_SIZE(mt7988_jtag_groups) }, + { "int_usxgmii", mt7988_int_usxgmii_groups, + ARRAY_SIZE(mt7988_int_usxgmii_groups) }, + { "pwm", mt7988_pwm_groups, ARRAY_SIZE(mt7988_pwm_groups) }, + { "dfd", mt7988_dfd_groups, ARRAY_SIZE(mt7988_dfd_groups) }, + { "i2c", mt7988_i2c_groups, ARRAY_SIZE(mt7988_i2c_groups) }, + { "eth", mt7988_ethernet_groups, ARRAY_SIZE(mt7988_ethernet_groups) }, + { "pcie", mt7988_pcie_groups, ARRAY_SIZE(mt7988_pcie_groups) }, + { "pmic", mt7988_pmic_groups, ARRAY_SIZE(mt7988_pmic_groups) }, + { "watchdog", mt7988_wdt_groups, ARRAY_SIZE(mt7988_wdt_groups) }, + { "spi", mt7988_spi_groups, ARRAY_SIZE(mt7988_spi_groups) }, + { "flash", mt7988_flash_groups, ARRAY_SIZE(mt7988_flash_groups) }, + { "uart", mt7988_uart_groups, ARRAY_SIZE(mt7988_uart_groups) }, + { "udi", mt7988_udi_groups, ARRAY_SIZE(mt7988_udi_groups) }, + { "usb", mt7988_usb_groups, ARRAY_SIZE(mt7988_usb_groups) }, + { "led", mt7988_led_groups, ARRAY_SIZE(mt7988_led_groups) }, +}; + +static const struct mtk_eint_hw mt7988_eint_hw = { + .port_mask = 7, + .ports = 7, + .ap_num = ARRAY_SIZE(mt7988_pins), + .db_cnt = 16, +}; + +static const char *mt7988_pinctrl_register_base_names[] = { + "gpio_base", "iocfg_tr_base", "iocfg_br_base", + "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base", +}; + +static struct mtk_pin_soc mt7988_data = { + .reg_cal = mt7988_reg_cals, + .pins = mt7988_pins, + .npins = ARRAY_SIZE(mt7988_pins), + .grps = mt7988_groups, + .ngrps = ARRAY_SIZE(mt7988_groups), + .funcs = mt7988_functions, + .nfuncs = ARRAY_SIZE(mt7988_functions), + .eint_hw = &mt7988_eint_hw, + .gpio_m = 0, + .ies_present = false, + .base_names = mt7988_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt7988_pinctrl_register_base_names), + .bias_disable_set = mtk_pinconf_bias_disable_set, + .bias_disable_get = mtk_pinconf_bias_disable_get, + .bias_set = mtk_pinconf_bias_set, + .bias_get = mtk_pinconf_bias_get, + .drive_set = mtk_pinconf_drive_set_rev1, + .drive_get = mtk_pinconf_drive_get_rev1, + .adv_pull_get = mtk_pinconf_adv_pull_get, + .adv_pull_set = mtk_pinconf_adv_pull_set, +}; + +static const struct of_device_id mt7988_pinctrl_of_match[] = { + { + .compatible = "mediatek,mt7988-pinctrl", + }, + {} +}; + +static int mt7988_pinctrl_probe(struct platform_device *pdev) +{ + return mtk_moore_pinctrl_probe(pdev, &mt7988_data); +} + +static struct platform_driver mt7988_pinctrl_driver = { + .driver = { + .name = "mt7988-pinctrl", + .of_match_table = mt7988_pinctrl_of_match, + }, + .probe = mt7988_pinctrl_probe, +}; + +static int __init mt7988_pinctrl_init(void) +{ + return platform_driver_register(&mt7988_pinctrl_driver); +} +arch_initcall(mt7988_pinctrl_init); diff --git a/target/linux/mediatek/files-6.1/include/dt-bindings/clock/mediatek,mt7981-clk.h b/target/linux/mediatek/files-6.1/include/dt-bindings/clock/mediatek,mt7981-clk.h new file mode 100644 index 00000000000..192f8cefb58 --- /dev/null +++ b/target/linux/mediatek/files-6.1/include/dt-bindings/clock/mediatek,mt7981-clk.h @@ -0,0 +1,215 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Wenzhen.Yu + * Author: Jianhui Zhao + * Author: Daniel Golle + */ + +#ifndef _DT_BINDINGS_CLK_MT7981_H +#define _DT_BINDINGS_CLK_MT7981_H + +/* TOPCKGEN */ +#define CLK_TOP_CB_CKSQ_40M 0 +#define CLK_TOP_CB_M_416M 1 +#define CLK_TOP_CB_M_D2 2 +#define CLK_TOP_CB_M_D3 3 +#define CLK_TOP_M_D3_D2 4 +#define CLK_TOP_CB_M_D4 5 +#define CLK_TOP_CB_M_D8 6 +#define CLK_TOP_M_D8_D2 7 +#define CLK_TOP_CB_MM_720M 8 +#define CLK_TOP_CB_MM_D2 9 +#define CLK_TOP_CB_MM_D3 10 +#define CLK_TOP_CB_MM_D3_D5 11 +#define CLK_TOP_CB_MM_D4 12 +#define CLK_TOP_CB_MM_D6 13 +#define CLK_TOP_MM_D6_D2 14 +#define CLK_TOP_CB_MM_D8 15 +#define CLK_TOP_CB_APLL2_196M 16 +#define CLK_TOP_APLL2_D2 17 +#define CLK_TOP_APLL2_D4 18 +#define CLK_TOP_NET1_2500M 19 +#define CLK_TOP_CB_NET1_D4 20 +#define CLK_TOP_CB_NET1_D5 21 +#define CLK_TOP_NET1_D5_D2 22 +#define CLK_TOP_NET1_D5_D4 23 +#define CLK_TOP_CB_NET1_D8 24 +#define CLK_TOP_NET1_D8_D2 25 +#define CLK_TOP_NET1_D8_D4 26 +#define CLK_TOP_CB_NET2_800M 27 +#define CLK_TOP_CB_NET2_D2 28 +#define CLK_TOP_CB_NET2_D4 29 +#define CLK_TOP_NET2_D4_D2 30 +#define CLK_TOP_NET2_D4_D4 31 +#define CLK_TOP_CB_NET2_D6 32 +#define CLK_TOP_CB_WEDMCU_208M 33 +#define CLK_TOP_CB_SGM_325M 34 +#define CLK_TOP_CKSQ_40M_D2 35 +#define CLK_TOP_CB_RTC_32K 36 +#define CLK_TOP_CB_RTC_32P7K 37 +#define CLK_TOP_USB_TX250M 38 +#define CLK_TOP_FAUD 39 +#define CLK_TOP_NFI1X 40 +#define CLK_TOP_USB_EQ_RX250M 41 +#define CLK_TOP_USB_CDR_CK 42 +#define CLK_TOP_USB_LN0_CK 43 +#define CLK_TOP_SPINFI_BCK 44 +#define CLK_TOP_SPI 45 +#define CLK_TOP_SPIM_MST 46 +#define CLK_TOP_UART_BCK 47 +#define CLK_TOP_PWM_BCK 48 +#define CLK_TOP_I2C_BCK 49 +#define CLK_TOP_PEXTP_TL 50 +#define CLK_TOP_EMMC_208M 51 +#define CLK_TOP_EMMC_400M 52 +#define CLK_TOP_DRAMC_REF 53 +#define CLK_TOP_DRAMC_MD32 54 +#define CLK_TOP_SYSAXI 55 +#define CLK_TOP_SYSAPB 56 +#define CLK_TOP_ARM_DB_MAIN 57 +#define CLK_TOP_AP2CNN_HOST 58 +#define CLK_TOP_NETSYS 59 +#define CLK_TOP_NETSYS_500M 60 +#define CLK_TOP_NETSYS_WED_MCU 61 +#define CLK_TOP_NETSYS_2X 62 +#define CLK_TOP_SGM_325M 63 +#define CLK_TOP_SGM_REG 64 +#define CLK_TOP_F26M 65 +#define CLK_TOP_EIP97B 66 +#define CLK_TOP_USB3_PHY 67 +#define CLK_TOP_AUD 68 +#define CLK_TOP_A1SYS 69 +#define CLK_TOP_AUD_L 70 +#define CLK_TOP_A_TUNER 71 +#define CLK_TOP_U2U3_REF 72 +#define CLK_TOP_U2U3_SYS 73 +#define CLK_TOP_U2U3_XHCI 74 +#define CLK_TOP_USB_FRMCNT 75 +#define CLK_TOP_NFI1X_SEL 76 +#define CLK_TOP_SPINFI_SEL 77 +#define CLK_TOP_SPI_SEL 78 +#define CLK_TOP_SPIM_MST_SEL 79 +#define CLK_TOP_UART_SEL 80 +#define CLK_TOP_PWM_SEL 81 +#define CLK_TOP_I2C_SEL 82 +#define CLK_TOP_PEXTP_TL_SEL 83 +#define CLK_TOP_EMMC_208M_SEL 84 +#define CLK_TOP_EMMC_400M_SEL 85 +#define CLK_TOP_F26M_SEL 86 +#define CLK_TOP_DRAMC_SEL 87 +#define CLK_TOP_DRAMC_MD32_SEL 88 +#define CLK_TOP_SYSAXI_SEL 89 +#define CLK_TOP_SYSAPB_SEL 90 +#define CLK_TOP_ARM_DB_MAIN_SEL 91 +#define CLK_TOP_AP2CNN_HOST_SEL 92 +#define CLK_TOP_NETSYS_SEL 93 +#define CLK_TOP_NETSYS_500M_SEL 94 +#define CLK_TOP_NETSYS_MCU_SEL 95 +#define CLK_TOP_NETSYS_2X_SEL 96 +#define CLK_TOP_SGM_325M_SEL 97 +#define CLK_TOP_SGM_REG_SEL 98 +#define CLK_TOP_EIP97B_SEL 99 +#define CLK_TOP_USB3_PHY_SEL 100 +#define CLK_TOP_AUD_SEL 101 +#define CLK_TOP_A1SYS_SEL 102 +#define CLK_TOP_AUD_L_SEL 103 +#define CLK_TOP_A_TUNER_SEL 104 +#define CLK_TOP_U2U3_SEL 105 +#define CLK_TOP_U2U3_SYS_SEL 106 +#define CLK_TOP_U2U3_XHCI_SEL 107 +#define CLK_TOP_USB_FRMCNT_SEL 108 +#define CLK_TOP_AUD_I2S_M 109 + +/* INFRACFG */ +#define CLK_INFRA_66M_MCK 0 +#define CLK_INFRA_UART0_SEL 1 +#define CLK_INFRA_UART1_SEL 2 +#define CLK_INFRA_UART2_SEL 3 +#define CLK_INFRA_SPI0_SEL 4 +#define CLK_INFRA_SPI1_SEL 5 +#define CLK_INFRA_SPI2_SEL 6 +#define CLK_INFRA_PWM1_SEL 7 +#define CLK_INFRA_PWM2_SEL 8 +#define CLK_INFRA_PWM3_SEL 9 +#define CLK_INFRA_PWM_BSEL 10 +#define CLK_INFRA_PCIE_SEL 11 +#define CLK_INFRA_GPT_STA 12 +#define CLK_INFRA_PWM_HCK 13 +#define CLK_INFRA_PWM_STA 14 +#define CLK_INFRA_PWM1_CK 15 +#define CLK_INFRA_PWM2_CK 16 +#define CLK_INFRA_PWM3_CK 17 +#define CLK_INFRA_CQ_DMA_CK 18 +#define CLK_INFRA_AUD_BUS_CK 19 +#define CLK_INFRA_AUD_26M_CK 20 +#define CLK_INFRA_AUD_L_CK 21 +#define CLK_INFRA_AUD_AUD_CK 22 +#define CLK_INFRA_AUD_EG2_CK 23 +#define CLK_INFRA_DRAMC_26M_CK 24 +#define CLK_INFRA_DBG_CK 25 +#define CLK_INFRA_AP_DMA_CK 26 +#define CLK_INFRA_SEJ_CK 27 +#define CLK_INFRA_SEJ_13M_CK 28 +#define CLK_INFRA_THERM_CK 29 +#define CLK_INFRA_I2C0_CK 30 +#define CLK_INFRA_UART0_CK 31 +#define CLK_INFRA_UART1_CK 32 +#define CLK_INFRA_UART2_CK 33 +#define CLK_INFRA_SPI2_CK 34 +#define CLK_INFRA_SPI2_HCK_CK 35 +#define CLK_INFRA_NFI1_CK 36 +#define CLK_INFRA_SPINFI1_CK 37 +#define CLK_INFRA_NFI_HCK_CK 38 +#define CLK_INFRA_SPI0_CK 39 +#define CLK_INFRA_SPI1_CK 40 +#define CLK_INFRA_SPI0_HCK_CK 41 +#define CLK_INFRA_SPI1_HCK_CK 42 +#define CLK_INFRA_FRTC_CK 43 +#define CLK_INFRA_MSDC_CK 44 +#define CLK_INFRA_MSDC_HCK_CK 45 +#define CLK_INFRA_MSDC_133M_CK 46 +#define CLK_INFRA_MSDC_66M_CK 47 +#define CLK_INFRA_ADC_26M_CK 48 +#define CLK_INFRA_ADC_FRC_CK 49 +#define CLK_INFRA_FBIST2FPC_CK 50 +#define CLK_INFRA_I2C_MCK_CK 51 +#define CLK_INFRA_I2C_PCK_CK 52 +#define CLK_INFRA_IUSB_133_CK 53 +#define CLK_INFRA_IUSB_66M_CK 54 +#define CLK_INFRA_IUSB_SYS_CK 55 +#define CLK_INFRA_IUSB_CK 56 +#define CLK_INFRA_IPCIE_CK 57 +#define CLK_INFRA_IPCIE_PIPE_CK 58 +#define CLK_INFRA_IPCIER_CK 59 +#define CLK_INFRA_IPCIEB_CK 60 + +/* APMIXEDSYS */ +#define CLK_APMIXED_ARMPLL 0 +#define CLK_APMIXED_NET2PLL 1 +#define CLK_APMIXED_MMPLL 2 +#define CLK_APMIXED_SGMPLL 3 +#define CLK_APMIXED_WEDMCUPLL 4 +#define CLK_APMIXED_NET1PLL 5 +#define CLK_APMIXED_MPLL 6 +#define CLK_APMIXED_APLL2 7 + +/* SGMIISYS_0 */ +#define CLK_SGM0_TX_EN 0 +#define CLK_SGM0_RX_EN 1 +#define CLK_SGM0_CK0_EN 2 +#define CLK_SGM0_CDR_CK0_EN 3 + +/* SGMIISYS_1 */ +#define CLK_SGM1_TX_EN 0 +#define CLK_SGM1_RX_EN 1 +#define CLK_SGM1_CK1_EN 2 +#define CLK_SGM1_CDR_CK1_EN 3 + +/* ETHSYS */ +#define CLK_ETH_FE_EN 0 +#define CLK_ETH_GP2_EN 1 +#define CLK_ETH_GP1_EN 2 +#define CLK_ETH_WOCPU0_EN 3 + +#endif /* _DT_BINDINGS_CLK_MT7981_H */ diff --git a/target/linux/mediatek/files-6.1/include/dt-bindings/clock/mediatek,mt7988-clk.h b/target/linux/mediatek/files-6.1/include/dt-bindings/clock/mediatek,mt7988-clk.h new file mode 100644 index 00000000000..77cfea4a8ea --- /dev/null +++ b/target/linux/mediatek/files-6.1/include/dt-bindings/clock/mediatek,mt7988-clk.h @@ -0,0 +1,276 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023 MediaTek Inc. + * Author: Sam Shih + * Author: Xiufeng Li + */ + +#ifndef _DT_BINDINGS_CLK_MT7988_H +#define _DT_BINDINGS_CLK_MT7988_H + +/* APMIXEDSYS */ + +#define CLK_APMIXED_NETSYSPLL 0 +#define CLK_APMIXED_MPLL 1 +#define CLK_APMIXED_MMPLL 2 +#define CLK_APMIXED_APLL2 3 +#define CLK_APMIXED_NET1PLL 4 +#define CLK_APMIXED_NET2PLL 5 +#define CLK_APMIXED_WEDMCUPLL 6 +#define CLK_APMIXED_SGMPLL 7 +#define CLK_APMIXED_ARM_B 8 +#define CLK_APMIXED_CCIPLL2_B 9 +#define CLK_APMIXED_USXGMIIPLL 10 +#define CLK_APMIXED_MSDCPLL 11 + +/* TOPCKGEN */ + +#define CLK_TOP_XTAL 0 +#define CLK_TOP_XTAL_D2 1 +#define CLK_TOP_RTC_32K 2 +#define CLK_TOP_RTC_32P7K 3 +#define CLK_TOP_MPLL_D2 4 +#define CLK_TOP_MPLL_D3_D2 5 +#define CLK_TOP_MPLL_D4 6 +#define CLK_TOP_MPLL_D8 7 +#define CLK_TOP_MPLL_D8_D2 8 +#define CLK_TOP_MMPLL_D2 9 +#define CLK_TOP_MMPLL_D3_D5 10 +#define CLK_TOP_MMPLL_D4 11 +#define CLK_TOP_MMPLL_D6_D2 12 +#define CLK_TOP_MMPLL_D8 13 +#define CLK_TOP_APLL2_D4 14 +#define CLK_TOP_NET1PLL_D4 15 +#define CLK_TOP_NET1PLL_D5 16 +#define CLK_TOP_NET1PLL_D5_D2 17 +#define CLK_TOP_NET1PLL_D5_D4 18 +#define CLK_TOP_NET1PLL_D8 19 +#define CLK_TOP_NET1PLL_D8_D2 20 +#define CLK_TOP_NET1PLL_D8_D4 21 +#define CLK_TOP_NET1PLL_D8_D8 22 +#define CLK_TOP_NET1PLL_D8_D16 23 +#define CLK_TOP_NET2PLL_D2 24 +#define CLK_TOP_NET2PLL_D4 25 +#define CLK_TOP_NET2PLL_D4_D4 26 +#define CLK_TOP_NET2PLL_D4_D8 27 +#define CLK_TOP_NET2PLL_D6 28 +#define CLK_TOP_NET2PLL_D8 29 +#define CLK_TOP_NETSYS_SEL 30 +#define CLK_TOP_NETSYS_500M_SEL 31 +#define CLK_TOP_NETSYS_2X_SEL 32 +#define CLK_TOP_NETSYS_GSW_SEL 33 +#define CLK_TOP_ETH_GMII_SEL 34 +#define CLK_TOP_NETSYS_MCU_SEL 35 +#define CLK_TOP_NETSYS_PAO_2X_SEL 36 +#define CLK_TOP_EIP197_SEL 37 +#define CLK_TOP_AXI_INFRA_SEL 38 +#define CLK_TOP_UART_SEL 39 +#define CLK_TOP_EMMC_250M_SEL 40 +#define CLK_TOP_EMMC_400M_SEL 41 +#define CLK_TOP_SPI_SEL 42 +#define CLK_TOP_SPIM_MST_SEL 43 +#define CLK_TOP_NFI1X_SEL 44 +#define CLK_TOP_SPINFI_SEL 45 +#define CLK_TOP_PWM_SEL 46 +#define CLK_TOP_I2C_SEL 47 +#define CLK_TOP_PCIE_MBIST_250M_SEL 48 +#define CLK_TOP_PEXTP_TL_SEL 49 +#define CLK_TOP_PEXTP_TL_P1_SEL 50 +#define CLK_TOP_PEXTP_TL_P2_SEL 51 +#define CLK_TOP_PEXTP_TL_P3_SEL 52 +#define CLK_TOP_USB_SYS_SEL 53 +#define CLK_TOP_USB_SYS_P1_SEL 54 +#define CLK_TOP_USB_XHCI_SEL 55 +#define CLK_TOP_USB_XHCI_P1_SEL 56 +#define CLK_TOP_USB_FRMCNT_SEL 57 +#define CLK_TOP_USB_FRMCNT_P1_SEL 58 +#define CLK_TOP_AUD_SEL 59 +#define CLK_TOP_A1SYS_SEL 60 +#define CLK_TOP_AUD_L_SEL 61 +#define CLK_TOP_A_TUNER_SEL 62 +#define CLK_TOP_SSPXTP_SEL 63 +#define CLK_TOP_USB_PHY_SEL 64 +#define CLK_TOP_USXGMII_SBUS_0_SEL 65 +#define CLK_TOP_USXGMII_SBUS_1_SEL 66 +#define CLK_TOP_SGM_0_SEL 67 +#define CLK_TOP_SGM_SBUS_0_SEL 68 +#define CLK_TOP_SGM_1_SEL 69 +#define CLK_TOP_SGM_SBUS_1_SEL 70 +#define CLK_TOP_XFI_PHY_0_XTAL_SEL 71 +#define CLK_TOP_XFI_PHY_1_XTAL_SEL 72 +#define CLK_TOP_SYSAXI_SEL 73 +#define CLK_TOP_SYSAPB_SEL 74 +#define CLK_TOP_ETH_REFCK_50M_SEL 75 +#define CLK_TOP_ETH_SYS_200M_SEL 76 +#define CLK_TOP_ETH_SYS_SEL 77 +#define CLK_TOP_ETH_XGMII_SEL 78 +#define CLK_TOP_BUS_TOPS_SEL 79 +#define CLK_TOP_NPU_TOPS_SEL 80 +#define CLK_TOP_DRAMC_SEL 81 +#define CLK_TOP_DRAMC_MD32_SEL 82 +#define CLK_TOP_INFRA_F26M_SEL 83 +#define CLK_TOP_PEXTP_P0_SEL 84 +#define CLK_TOP_PEXTP_P1_SEL 85 +#define CLK_TOP_PEXTP_P2_SEL 86 +#define CLK_TOP_PEXTP_P3_SEL 87 +#define CLK_TOP_DA_XTP_GLB_P0_SEL 88 +#define CLK_TOP_DA_XTP_GLB_P1_SEL 89 +#define CLK_TOP_DA_XTP_GLB_P2_SEL 90 +#define CLK_TOP_DA_XTP_GLB_P3_SEL 91 +#define CLK_TOP_CKM_SEL 92 +#define CLK_TOP_DA_SEL 93 +#define CLK_TOP_PEXTP_SEL 94 +#define CLK_TOP_TOPS_P2_26M_SEL 95 +#define CLK_TOP_MCUSYS_BACKUP_625M_SEL 96 +#define CLK_TOP_NETSYS_SYNC_250M_SEL 97 +#define CLK_TOP_MACSEC_SEL 98 +#define CLK_TOP_NETSYS_TOPS_400M_SEL 99 +#define CLK_TOP_NETSYS_PPEFB_250M_SEL 100 +#define CLK_TOP_NETSYS_WARP_SEL 101 +#define CLK_TOP_ETH_MII_SEL 102 +#define CLK_TOP_NPU_SEL 103 +#define CLK_TOP_AUD_I2S_M 104 + +/* MCUSYS */ + +#define CLK_MCU_BUS_DIV_SEL 0 +#define CLK_MCU_ARM_DIV_SEL 1 + +/* INFRACFG_AO */ + +#define CLK_INFRA_MUX_UART0_SEL 0 +#define CLK_INFRA_MUX_UART1_SEL 1 +#define CLK_INFRA_MUX_UART2_SEL 2 +#define CLK_INFRA_MUX_SPI0_SEL 3 +#define CLK_INFRA_MUX_SPI1_SEL 4 +#define CLK_INFRA_MUX_SPI2_SEL 5 +#define CLK_INFRA_PWM_SEL 6 +#define CLK_INFRA_PWM_CK1_SEL 7 +#define CLK_INFRA_PWM_CK2_SEL 8 +#define CLK_INFRA_PWM_CK3_SEL 9 +#define CLK_INFRA_PWM_CK4_SEL 10 +#define CLK_INFRA_PWM_CK5_SEL 11 +#define CLK_INFRA_PWM_CK6_SEL 12 +#define CLK_INFRA_PWM_CK7_SEL 13 +#define CLK_INFRA_PWM_CK8_SEL 14 +#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15 +#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16 +#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17 +#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18 + +/* INFRACFG */ + +#define CLK_INFRA_PCIE_PERI_26M_CK_P0 19 +#define CLK_INFRA_PCIE_PERI_26M_CK_P1 20 +#define CLK_INFRA_PCIE_PERI_26M_CK_P2 21 +#define CLK_INFRA_PCIE_PERI_26M_CK_P3 22 +#define CLK_INFRA_66M_GPT_BCK 23 +#define CLK_INFRA_66M_PWM_HCK 24 +#define CLK_INFRA_66M_PWM_BCK 25 +#define CLK_INFRA_66M_PWM_CK1 26 +#define CLK_INFRA_66M_PWM_CK2 27 +#define CLK_INFRA_66M_PWM_CK3 28 +#define CLK_INFRA_66M_PWM_CK4 29 +#define CLK_INFRA_66M_PWM_CK5 30 +#define CLK_INFRA_66M_PWM_CK6 31 +#define CLK_INFRA_66M_PWM_CK7 32 +#define CLK_INFRA_66M_PWM_CK8 33 +#define CLK_INFRA_133M_CQDMA_BCK 34 +#define CLK_INFRA_66M_AUD_SLV_BCK 35 +#define CLK_INFRA_AUD_26M 36 +#define CLK_INFRA_AUD_L 37 +#define CLK_INFRA_AUD_AUD 38 +#define CLK_INFRA_AUD_EG2 39 +#define CLK_INFRA_DRAMC_F26M 40 +#define CLK_INFRA_133M_DBG_ACKM 41 +#define CLK_INFRA_66M_AP_DMA_BCK 42 +#define CLK_INFRA_66M_SEJ_BCK 43 +#define CLK_INFRA_PRE_CK_SEJ_F13M 44 +#define CLK_INFRA_26M_THERM_SYSTEM 45 +#define CLK_INFRA_I2C_BCK 46 +#define CLK_INFRA_52M_UART0_CK 47 +#define CLK_INFRA_52M_UART1_CK 48 +#define CLK_INFRA_52M_UART2_CK 49 +#define CLK_INFRA_NFI 50 +#define CLK_INFRA_SPINFI 51 +#define CLK_INFRA_66M_NFI_HCK 52 +#define CLK_INFRA_104M_SPI0 53 +#define CLK_INFRA_104M_SPI1 54 +#define CLK_INFRA_104M_SPI2_BCK 55 +#define CLK_INFRA_66M_SPI0_HCK 56 +#define CLK_INFRA_66M_SPI1_HCK 57 +#define CLK_INFRA_66M_SPI2_HCK 58 +#define CLK_INFRA_66M_FLASHIF_AXI 59 +#define CLK_INFRA_RTC 60 +#define CLK_INFRA_26M_ADC_BCK 61 +#define CLK_INFRA_RC_ADC 62 +#define CLK_INFRA_MSDC400 63 +#define CLK_INFRA_MSDC2_HCK 64 +#define CLK_INFRA_133M_MSDC_0_HCK 65 +#define CLK_INFRA_66M_MSDC_0_HCK 66 +#define CLK_INFRA_133M_CPUM_BCK 67 +#define CLK_INFRA_BIST2FPC 68 +#define CLK_INFRA_I2C_X16W_MCK_CK_P1 69 +#define CLK_INFRA_I2C_X16W_PCK_CK_P1 70 +#define CLK_INFRA_133M_USB_HCK 71 +#define CLK_INFRA_133M_USB_HCK_CK_P1 72 +#define CLK_INFRA_66M_USB_HCK 73 +#define CLK_INFRA_66M_USB_HCK_CK_P1 74 +#define CLK_INFRA_USB_SYS 75 +#define CLK_INFRA_USB_SYS_CK_P1 76 +#define CLK_INFRA_USB_REF 77 +#define CLK_INFRA_USB_CK_P1 78 +#define CLK_INFRA_USB_FRMCNT 79 +#define CLK_INFRA_USB_FRMCNT_CK_P1 80 +#define CLK_INFRA_USB_PIPE 81 +#define CLK_INFRA_USB_PIPE_CK_P1 82 +#define CLK_INFRA_USB_UTMI 83 +#define CLK_INFRA_USB_UTMI_CK_P1 84 +#define CLK_INFRA_USB_XHCI 85 +#define CLK_INFRA_USB_XHCI_CK_P1 86 +#define CLK_INFRA_PCIE_GFMUX_TL_P0 87 +#define CLK_INFRA_PCIE_GFMUX_TL_P1 88 +#define CLK_INFRA_PCIE_GFMUX_TL_P2 89 +#define CLK_INFRA_PCIE_GFMUX_TL_P3 90 +#define CLK_INFRA_PCIE_PIPE_P0 91 +#define CLK_INFRA_PCIE_PIPE_P1 92 +#define CLK_INFRA_PCIE_PIPE_P2 93 +#define CLK_INFRA_PCIE_PIPE_P3 94 +#define CLK_INFRA_133M_PCIE_CK_P0 95 +#define CLK_INFRA_133M_PCIE_CK_P1 96 +#define CLK_INFRA_133M_PCIE_CK_P2 97 +#define CLK_INFRA_133M_PCIE_CK_P3 98 + +/* ETHDMA */ + +#define CLK_ETHDMA_XGP1_EN 0 +#define CLK_ETHDMA_XGP2_EN 1 +#define CLK_ETHDMA_XGP3_EN 2 +#define CLK_ETHDMA_FE_EN 3 +#define CLK_ETHDMA_GP2_EN 4 +#define CLK_ETHDMA_GP1_EN 5 +#define CLK_ETHDMA_GP3_EN 6 +#define CLK_ETHDMA_ESW_EN 7 +#define CLK_ETHDMA_CRYPT0_EN 8 +#define CLK_ETHDMA_NR_CLK 9 + +/* SGMIISYS_0 */ + +#define CLK_SGM0_TX_EN 0 +#define CLK_SGM0_RX_EN 1 +#define CLK_SGMII0_NR_CLK 2 + +/* SGMIISYS_1 */ + +#define CLK_SGM1_TX_EN 0 +#define CLK_SGM1_RX_EN 1 +#define CLK_SGMII1_NR_CLK 2 + +/* ETHWARP */ + +#define CLK_ETHWARP_WOCPU2_EN 0 +#define CLK_ETHWARP_WOCPU1_EN 1 +#define CLK_ETHWARP_WOCPU0_EN 2 +#define CLK_ETHWARP_NR_CLK 3 + +#endif /* _DT_BINDINGS_CLK_MT7988_H */ diff --git a/target/linux/mediatek/files-6.1/include/dt-bindings/clock/mt7986-clk.h b/target/linux/mediatek/files-6.1/include/dt-bindings/clock/mt7986-clk.h new file mode 100644 index 00000000000..5a9b169324b --- /dev/null +++ b/target/linux/mediatek/files-6.1/include/dt-bindings/clock/mt7986-clk.h @@ -0,0 +1,169 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Sam Shih + */ + +#ifndef _DT_BINDINGS_CLK_MT7986_H +#define _DT_BINDINGS_CLK_MT7986_H + +/* APMIXEDSYS */ + +#define CLK_APMIXED_ARMPLL 0 +#define CLK_APMIXED_NET2PLL 1 +#define CLK_APMIXED_MMPLL 2 +#define CLK_APMIXED_SGMPLL 3 +#define CLK_APMIXED_WEDMCUPLL 4 +#define CLK_APMIXED_NET1PLL 5 +#define CLK_APMIXED_MPLL 6 +#define CLK_APMIXED_APLL2 7 + +/* TOPCKGEN */ + +#define CLK_TOP_XTAL 0 +#define CLK_TOP_XTAL_D2 1 +#define CLK_TOP_RTC_32K 2 +#define CLK_TOP_RTC_32P7K 3 +#define CLK_TOP_MPLL_D2 4 +#define CLK_TOP_MPLL_D4 5 +#define CLK_TOP_MPLL_D8 6 +#define CLK_TOP_MPLL_D8_D2 7 +#define CLK_TOP_MPLL_D3_D2 8 +#define CLK_TOP_MMPLL_D2 9 +#define CLK_TOP_MMPLL_D4 10 +#define CLK_TOP_MMPLL_D8 11 +#define CLK_TOP_MMPLL_D8_D2 12 +#define CLK_TOP_MMPLL_D3_D8 13 +#define CLK_TOP_MMPLL_U2PHY 14 +#define CLK_TOP_APLL2_D4 15 +#define CLK_TOP_NET1PLL_D4 16 +#define CLK_TOP_NET1PLL_D5 17 +#define CLK_TOP_NET1PLL_D5_D2 18 +#define CLK_TOP_NET1PLL_D5_D4 19 +#define CLK_TOP_NET1PLL_D8_D2 20 +#define CLK_TOP_NET1PLL_D8_D4 21 +#define CLK_TOP_NET2PLL_D4 22 +#define CLK_TOP_NET2PLL_D4_D2 23 +#define CLK_TOP_NET2PLL_D3_D2 24 +#define CLK_TOP_WEDMCUPLL_D5_D2 25 +#define CLK_TOP_NFI1X_SEL 26 +#define CLK_TOP_SPINFI_SEL 27 +#define CLK_TOP_SPI_SEL 28 +#define CLK_TOP_SPIM_MST_SEL 29 +#define CLK_TOP_UART_SEL 30 +#define CLK_TOP_PWM_SEL 31 +#define CLK_TOP_I2C_SEL 32 +#define CLK_TOP_PEXTP_TL_SEL 33 +#define CLK_TOP_EMMC_250M_SEL 34 +#define CLK_TOP_EMMC_416M_SEL 35 +#define CLK_TOP_F_26M_ADC_SEL 36 +#define CLK_TOP_DRAMC_SEL 37 +#define CLK_TOP_DRAMC_MD32_SEL 38 +#define CLK_TOP_SYSAXI_SEL 39 +#define CLK_TOP_SYSAPB_SEL 40 +#define CLK_TOP_ARM_DB_MAIN_SEL 41 +#define CLK_TOP_ARM_DB_JTSEL 42 +#define CLK_TOP_NETSYS_SEL 43 +#define CLK_TOP_NETSYS_500M_SEL 44 +#define CLK_TOP_NETSYS_MCU_SEL 45 +#define CLK_TOP_NETSYS_2X_SEL 46 +#define CLK_TOP_SGM_325M_SEL 47 +#define CLK_TOP_SGM_REG_SEL 48 +#define CLK_TOP_A1SYS_SEL 49 +#define CLK_TOP_CONN_MCUSYS_SEL 50 +#define CLK_TOP_EIP_B_SEL 51 +#define CLK_TOP_PCIE_PHY_SEL 52 +#define CLK_TOP_USB3_PHY_SEL 53 +#define CLK_TOP_F26M_SEL 54 +#define CLK_TOP_AUD_L_SEL 55 +#define CLK_TOP_A_TUNER_SEL 56 +#define CLK_TOP_U2U3_SEL 57 +#define CLK_TOP_U2U3_SYS_SEL 58 +#define CLK_TOP_U2U3_XHCI_SEL 59 +#define CLK_TOP_DA_U2_REFSEL 60 +#define CLK_TOP_DA_U2_CK_1P_SEL 61 +#define CLK_TOP_AP2CNN_HOST_SEL 62 +#define CLK_TOP_JTAG 63 + +/* INFRACFG */ + +#define CLK_INFRA_SYSAXI_D2 0 +#define CLK_INFRA_UART0_SEL 1 +#define CLK_INFRA_UART1_SEL 2 +#define CLK_INFRA_UART2_SEL 3 +#define CLK_INFRA_SPI0_SEL 4 +#define CLK_INFRA_SPI1_SEL 5 +#define CLK_INFRA_PWM1_SEL 6 +#define CLK_INFRA_PWM2_SEL 7 +#define CLK_INFRA_PWM_BSEL 8 +#define CLK_INFRA_PCIE_SEL 9 +#define CLK_INFRA_GPT_STA 10 +#define CLK_INFRA_PWM_HCK 11 +#define CLK_INFRA_PWM_STA 12 +#define CLK_INFRA_PWM1_CK 13 +#define CLK_INFRA_PWM2_CK 14 +#define CLK_INFRA_CQ_DMA_CK 15 +#define CLK_INFRA_EIP97_CK 16 +#define CLK_INFRA_AUD_BUS_CK 17 +#define CLK_INFRA_AUD_26M_CK 18 +#define CLK_INFRA_AUD_L_CK 19 +#define CLK_INFRA_AUD_AUD_CK 20 +#define CLK_INFRA_AUD_EG2_CK 21 +#define CLK_INFRA_DRAMC_26M_CK 22 +#define CLK_INFRA_DBG_CK 23 +#define CLK_INFRA_AP_DMA_CK 24 +#define CLK_INFRA_SEJ_CK 25 +#define CLK_INFRA_SEJ_13M_CK 26 +#define CLK_INFRA_THERM_CK 27 +#define CLK_INFRA_I2C0_CK 28 +#define CLK_INFRA_UART0_CK 29 +#define CLK_INFRA_UART1_CK 30 +#define CLK_INFRA_UART2_CK 31 +#define CLK_INFRA_NFI1_CK 32 +#define CLK_INFRA_SPINFI1_CK 33 +#define CLK_INFRA_NFI_HCK_CK 34 +#define CLK_INFRA_SPI0_CK 35 +#define CLK_INFRA_SPI1_CK 36 +#define CLK_INFRA_SPI0_HCK_CK 37 +#define CLK_INFRA_SPI1_HCK_CK 38 +#define CLK_INFRA_FRTC_CK 39 +#define CLK_INFRA_MSDC_CK 40 +#define CLK_INFRA_MSDC_HCK_CK 41 +#define CLK_INFRA_MSDC_133M_CK 42 +#define CLK_INFRA_MSDC_66M_CK 43 +#define CLK_INFRA_ADC_26M_CK 44 +#define CLK_INFRA_ADC_FRC_CK 45 +#define CLK_INFRA_FBIST2FPC_CK 46 +#define CLK_INFRA_IUSB_133_CK 47 +#define CLK_INFRA_IUSB_66M_CK 48 +#define CLK_INFRA_IUSB_SYS_CK 49 +#define CLK_INFRA_IUSB_CK 50 +#define CLK_INFRA_IPCIE_CK 51 +#define CLK_INFRA_IPCIE_PIPE_CK 52 +#define CLK_INFRA_IPCIER_CK 53 +#define CLK_INFRA_IPCIEB_CK 54 +#define CLK_INFRA_TRNG_CK 55 + +/* SGMIISYS_0 */ + +#define CLK_SGMII0_TX250M_EN 0 +#define CLK_SGMII0_RX250M_EN 1 +#define CLK_SGMII0_CDR_REF 2 +#define CLK_SGMII0_CDR_FB 3 + +/* SGMIISYS_1 */ + +#define CLK_SGMII1_TX250M_EN 0 +#define CLK_SGMII1_RX250M_EN 1 +#define CLK_SGMII1_CDR_REF 2 +#define CLK_SGMII1_CDR_FB 3 + +/* ETHSYS */ + +#define CLK_ETH_FE_EN 0 +#define CLK_ETH_GP2_EN 1 +#define CLK_ETH_GP1_EN 2 +#define CLK_ETH_WOCPU1_EN 3 +#define CLK_ETH_WOCPU0_EN 4 + +#endif /* _DT_BINDINGS_CLK_MT7986_H */ diff --git a/target/linux/mediatek/files-6.1/include/dt-bindings/reset/mt7986-resets.h b/target/linux/mediatek/files-6.1/include/dt-bindings/reset/mt7986-resets.h new file mode 100644 index 00000000000..af3d16c8119 --- /dev/null +++ b/target/linux/mediatek/files-6.1/include/dt-bindings/reset/mt7986-resets.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Sam Shih + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7986 +#define _DT_BINDINGS_RESET_CONTROLLER_MT7986 + +/* INFRACFG resets */ +#define MT7986_INFRACFG_PEXTP_MAC_SW_RST 6 +#define MT7986_INFRACFG_SSUSB_SW_RST 7 +#define MT7986_INFRACFG_EIP97_SW_RST 8 +#define MT7986_INFRACFG_AUDIO_SW_RST 13 +#define MT7986_INFRACFG_CQ_DMA_SW_RST 14 + +#define MT7986_INFRACFG_TRNG_SW_RST 17 +#define MT7986_INFRACFG_AP_DMA_SW_RST 32 +#define MT7986_INFRACFG_I2C_SW_RST 33 +#define MT7986_INFRACFG_NFI_SW_RST 34 +#define MT7986_INFRACFG_SPI0_SW_RST 35 +#define MT7986_INFRACFG_SPI1_SW_RST 36 +#define MT7986_INFRACFG_UART0_SW_RST 37 +#define MT7986_INFRACFG_UART1_SW_RST 38 +#define MT7986_INFRACFG_UART2_SW_RST 39 +#define MT7986_INFRACFG_AUXADC_SW_RST 43 + +#define MT7986_INFRACFG_APXGPT_SW_RST 66 +#define MT7986_INFRACFG_PWM_SW_RST 68 + +#define MT7986_INFRACFG_SW_RST_NUM 69 + +/* TOPRGU resets */ +#define MT7986_TOPRGU_APMIXEDSYS_SW_RST 0 +#define MT7986_TOPRGU_SGMII0_SW_RST 1 +#define MT7986_TOPRGU_SGMII1_SW_RST 2 +#define MT7986_TOPRGU_INFRA_SW_RST 3 +#define MT7986_TOPRGU_U2PHY_SW_RST 5 +#define MT7986_TOPRGU_PCIE_SW_RST 6 +#define MT7986_TOPRGU_SSUSB_SW_RST 7 +#define MT7986_TOPRGU_ETHDMA_SW_RST 20 +#define MT7986_TOPRGU_CONSYS_SW_RST 23 + +#define MT7986_TOPRGU_SW_RST_NUM 24 + +/* ETHSYS Subsystem resets */ +#define MT7986_ETHSYS_FE_SW_RST 6 +#define MT7986_ETHSYS_PMTR_SW_RST 8 +#define MT7986_ETHSYS_GMAC_SW_RST 23 +#define MT7986_ETHSYS_PPE0_SW_RST 30 +#define MT7986_ETHSYS_PPE1_SW_RST 31 + +#define MT7986_ETHSYS_SW_RST_NUM 32 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7986 */ diff --git a/target/linux/mediatek/patches-6.1/100-dts-update-mt7622-rfb1.patch b/target/linux/mediatek/patches-6.1/100-dts-update-mt7622-rfb1.patch new file mode 100644 index 00000000000..7224a9882c0 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/100-dts-update-mt7622-rfb1.patch @@ -0,0 +1,119 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +@@ -1,7 +1,6 @@ + /* +- * Copyright (c) 2017 MediaTek Inc. +- * Author: Ming Huang +- * Sean Wang ++ * Copyright (c) 2018 MediaTek Inc. ++ * Author: Ryder Lee + * + * SPDX-License-Identifier: (GPL-2.0 OR MIT) + */ +@@ -23,7 +22,7 @@ + + chosen { + stdout-path = "serial0:115200n8"; +- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512"; ++ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512"; + }; + + cpus { +@@ -40,23 +39,22 @@ + + gpio-keys { + compatible = "gpio-keys"; +- poll-interval = <100>; + + factory { + label = "factory"; + linux,code = ; +- gpios = <&pio 0 0>; ++ gpios = <&pio 0 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "wps"; + linux,code = ; +- gpios = <&pio 102 0>; ++ gpios = <&pio 102 GPIO_ACTIVE_LOW>; + }; + }; + + memory { +- reg = <0 0x40000000 0 0x20000000>; ++ reg = <0 0x40000000 0 0x40000000>; + }; + + reg_1p8v: regulator-1p8v { +@@ -132,22 +130,22 @@ + + port@0 { + reg = <0>; +- label = "lan0"; ++ label = "lan1"; + }; + + port@1 { + reg = <1>; +- label = "lan1"; ++ label = "lan2"; + }; + + port@2 { + reg = <2>; +- label = "lan2"; ++ label = "lan3"; + }; + + port@3 { + reg = <3>; +- label = "lan3"; ++ label = "lan4"; + }; + + port@4 { +@@ -236,15 +234,28 @@ + + &pcie { + pinctrl-names = "default"; +- pinctrl-0 = <&pcie0_pins>; ++ pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>; + status = "okay"; + + pcie@0,0 { + status = "okay"; + }; ++ ++ pcie@1,0 { ++ status = "okay"; ++ }; + }; + + &pio { ++ /* Attention: GPIO 90 is used to switch between PCIe@1,0 and ++ * SATA functions. i.e. output-high: PCIe, output-low: SATA ++ */ ++ asm_sel { ++ gpio-hog; ++ gpios = <90 GPIO_ACTIVE_HIGH>; ++ output-high; ++ }; ++ + /* eMMC is shared pin with parallel NAND */ + emmc_pins_default: emmc-pins-default { + mux { +@@ -521,11 +532,11 @@ + }; + + &sata { +- status = "okay"; ++ status = "disabled"; + }; + + &sata_phy { +- status = "okay"; ++ status = "disabled"; + }; + + &spi0 { diff --git a/target/linux/mediatek/patches-6.1/101-dts-update-mt7629-rfb.patch b/target/linux/mediatek/patches-6.1/101-dts-update-mt7629-rfb.patch new file mode 100644 index 00000000000..254b5f9eb72 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/101-dts-update-mt7629-rfb.patch @@ -0,0 +1,60 @@ +--- a/arch/arm/boot/dts/mt7629-rfb.dts ++++ b/arch/arm/boot/dts/mt7629-rfb.dts +@@ -18,6 +18,7 @@ + + chosen { + stdout-path = "serial0:115200n8"; ++ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8"; + }; + + gpio-keys { +@@ -70,6 +71,10 @@ + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; ++ ++ nvmem-cells = <&macaddr_factory_2a>; ++ nvmem-cell-names = "mac-address"; ++ + fixed-link { + speed = <2500>; + full-duplex; +@@ -82,6 +87,9 @@ + reg = <1>; + phy-mode = "gmii"; + phy-handle = <&phy0>; ++ ++ nvmem-cells = <&macaddr_factory_24>; ++ nvmem-cell-names = "mac-address"; + }; + + mdio: mdio-bus { +@@ -133,8 +141,9 @@ + }; + + partition@b0000 { +- label = "kernel"; ++ label = "firmware"; + reg = <0xb0000 0xb50000>; ++ compatible = "denx,fit"; + }; + }; + }; +@@ -272,3 +281,17 @@ + pinctrl-0 = <&watchdog_pins>; + status = "okay"; + }; ++ ++&factory { ++ compatible = "nvmem-cells"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ macaddr_factory_24: macaddr@24 { ++ reg = <0x24 0x6>; ++ }; ++ ++ macaddr_factory_2a: macaddr@2a { ++ reg = <0x2a 0x6>; ++ }; ++}; diff --git a/target/linux/mediatek/patches-6.1/103-mt7623-enable-arch-timer.patch b/target/linux/mediatek/patches-6.1/103-mt7623-enable-arch-timer.patch new file mode 100644 index 00000000000..04df7b927b1 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/103-mt7623-enable-arch-timer.patch @@ -0,0 +1,20 @@ +From d6a596012150960f0f3a214d31bbac4b607dbd1e Mon Sep 17 00:00:00 2001 +From: Chuanhong Guo +Date: Fri, 29 Apr 2022 10:40:56 +0800 +Subject: [PATCH] arm: mediatek: select arch timer for mt7623 + +Signed-off-by: Chuanhong Guo +--- + arch/arm/mach-mediatek/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm/mach-mediatek/Kconfig ++++ b/arch/arm/mach-mediatek/Kconfig +@@ -26,6 +26,7 @@ config MACH_MT6592 + config MACH_MT7623 + bool "MediaTek MT7623 SoCs support" + default ARCH_MEDIATEK ++ select HAVE_ARM_ARCH_TIMER + + config MACH_MT7629 + bool "MediaTek MT7629 SoCs support" diff --git a/target/linux/mediatek/patches-6.1/104-mt7622-add-snor-irq.patch b/target/linux/mediatek/patches-6.1/104-mt7622-add-snor-irq.patch new file mode 100644 index 00000000000..79b051147a3 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/104-mt7622-add-snor-irq.patch @@ -0,0 +1,10 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -559,6 +559,7 @@ + compatible = "mediatek,mt7622-nor", + "mediatek,mt8173-nor"; + reg = <0 0x11014000 0 0xe0>; ++ interrupts = ; + clocks = <&pericfg CLK_PERI_FLASH_PD>, + <&topckgen CLK_TOP_FLASH_SEL>; + clock-names = "spi", "sf"; diff --git a/target/linux/mediatek/patches-6.1/105-dts-mt7622-enable-pstore.patch b/target/linux/mediatek/patches-6.1/105-dts-mt7622-enable-pstore.patch new file mode 100644 index 00000000000..da42c07728a --- /dev/null +++ b/target/linux/mediatek/patches-6.1/105-dts-mt7622-enable-pstore.patch @@ -0,0 +1,25 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -111,7 +111,7 @@ + }; + + psci { +- compatible = "arm,psci-0.2"; ++ compatible = "arm,psci-1.0"; + method = "smc"; + }; + +@@ -127,6 +127,13 @@ + #size-cells = <2>; + ranges; + ++ /* 64 KiB reserved for ramoops/pstore */ ++ ramoops@42ff0000 { ++ compatible = "ramoops"; ++ reg = <0 0x42ff0000 0 0x10000>; ++ record-size = <0x1000>; ++ }; ++ + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@43000000 { + reg = <0 0x43000000 0 0x30000>; diff --git a/target/linux/mediatek/patches-6.1/110-dts-fix-bpi2-console.patch b/target/linux/mediatek/patches-6.1/110-dts-fix-bpi2-console.patch new file mode 100644 index 00000000000..8dc53d2985f --- /dev/null +++ b/target/linux/mediatek/patches-6.1/110-dts-fix-bpi2-console.patch @@ -0,0 +1,10 @@ +--- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts ++++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts +@@ -19,6 +19,7 @@ + + chosen { + stdout-path = "serial2:115200n8"; ++ bootargs = "console=ttyS2,115200n8 console=tty1"; + }; + + connector { diff --git a/target/linux/mediatek/patches-6.1/111-dts-fix-bpi64-console.patch b/target/linux/mediatek/patches-6.1/111-dts-fix-bpi64-console.patch new file mode 100644 index 00000000000..07a2eae2454 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/111-dts-fix-bpi64-console.patch @@ -0,0 +1,11 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +@@ -22,7 +22,7 @@ + + chosen { + stdout-path = "serial0:115200n8"; +- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512"; ++ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512"; + }; + + cpus { diff --git a/target/linux/mediatek/patches-6.1/112-dts-fix-bpi64-lan-names.patch b/target/linux/mediatek/patches-6.1/112-dts-fix-bpi64-lan-names.patch new file mode 100644 index 00000000000..6ce85efde98 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/112-dts-fix-bpi64-lan-names.patch @@ -0,0 +1,37 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +@@ -18,6 +18,7 @@ + + aliases { + serial0 = &uart0; ++ ethernet0 = &gmac0; + }; + + chosen { +@@ -160,22 +161,22 @@ + + port@1 { + reg = <1>; +- label = "lan0"; ++ label = "lan1"; + }; + + port@2 { + reg = <2>; +- label = "lan1"; ++ label = "lan2"; + }; + + port@3 { + reg = <3>; +- label = "lan2"; ++ label = "lan3"; + }; + + port@4 { + reg = <4>; +- label = "lan3"; ++ label = "lan4"; + }; + + port@6 { diff --git a/target/linux/mediatek/patches-6.1/113-dts-fix-bpi64-leds-and-buttons.patch b/target/linux/mediatek/patches-6.1/113-dts-fix-bpi64-leds-and-buttons.patch new file mode 100644 index 00000000000..f88dbc71955 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/113-dts-fix-bpi64-leds-and-buttons.patch @@ -0,0 +1,56 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +@@ -19,6 +19,10 @@ + aliases { + serial0 = &uart0; + ethernet0 = &gmac0; ++ led-boot = &led_system_green; ++ led-failsafe = &led_system_blue; ++ led-running = &led_system_green; ++ led-upgrade = &led_system_blue; + }; + + chosen { +@@ -42,8 +46,8 @@ + compatible = "gpio-keys"; + + factory { +- label = "factory"; +- linux,code = ; ++ label = "reset"; ++ linux,code = ; + gpios = <&pio 0 GPIO_ACTIVE_HIGH>; + }; + +@@ -57,17 +61,25 @@ + leds { + compatible = "gpio-leds"; + +- green { +- label = "bpi-r64:pio:green"; +- gpios = <&pio 89 GPIO_ACTIVE_HIGH>; ++ led_system_blue: blue { ++ label = "bpi-r64:pio:blue"; ++ gpios = <&pio 85 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + +- red { +- label = "bpi-r64:pio:red"; +- gpios = <&pio 88 GPIO_ACTIVE_HIGH>; ++ led_system_green: green { ++ label = "bpi-r64:pio:green"; ++ gpios = <&pio 89 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; ++ ++/* ++ * red { ++ * label = "bpi-r64:pio:red"; ++ * gpios = <&pio 88 GPIO_ACTIVE_HIGH>; ++ * default-state = "off"; ++ * }; ++ */ + }; + + memory { diff --git a/target/linux/mediatek/patches-6.1/114-dts-bpi64-disable-rtc.patch b/target/linux/mediatek/patches-6.1/114-dts-bpi64-disable-rtc.patch new file mode 100644 index 00000000000..1f41142aacf --- /dev/null +++ b/target/linux/mediatek/patches-6.1/114-dts-bpi64-disable-rtc.patch @@ -0,0 +1,21 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +@@ -564,12 +564,16 @@ + status = "okay"; + }; + ++&rtc { ++ status = "disabled"; ++}; ++ + &sata { +- status = "disable"; ++ status = "disabled"; + }; + + &sata_phy { +- status = "disable"; ++ status = "disabled"; + }; + + &spi0 { diff --git a/target/linux/mediatek/patches-6.1/115-dts-bpi64-add-snand-support.patch b/target/linux/mediatek/patches-6.1/115-dts-bpi64-add-snand-support.patch new file mode 100644 index 00000000000..34539a5d101 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/115-dts-bpi64-add-snand-support.patch @@ -0,0 +1,50 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +@@ -259,14 +259,42 @@ + status = "disabled"; + }; + +-&nor_flash { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi_nor_pins>; +- status = "disabled"; ++&bch { ++ status = "okay"; ++}; + ++&snfi { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&serial_nand_pins>; ++ status = "okay"; + flash@0 { +- compatible = "jedec,spi-nor"; ++ compatible = "spi-nand"; + reg = <0>; ++ spi-tx-bus-width = <4>; ++ spi-rx-bus-width = <4>; ++ nand-ecc-engine = <&snfi>; ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "bl2"; ++ reg = <0x0 0x80000>; ++ read-only; ++ }; ++ ++ partition@80000 { ++ label = "fip"; ++ reg = <0x80000 0x200000>; ++ read-only; ++ }; ++ ++ partition@280000 { ++ label = "ubi"; ++ reg = <0x280000 0x7d80000>; ++ }; ++ }; + }; + }; + diff --git a/target/linux/mediatek/patches-6.1/120-01-v5.18-mtd-nand-ecc-Add-infrastructure-to-support-hardware-.patch b/target/linux/mediatek/patches-6.1/120-01-v5.18-mtd-nand-ecc-Add-infrastructure-to-support-hardware-.patch new file mode 100644 index 00000000000..7fb62e7403c --- /dev/null +++ b/target/linux/mediatek/patches-6.1/120-01-v5.18-mtd-nand-ecc-Add-infrastructure-to-support-hardware-.patch @@ -0,0 +1,214 @@ +From ad4944aa0b02cb043afe20bc2a018c161e65c992 Mon Sep 17 00:00:00 2001 +From: Miquel Raynal +Date: Thu, 16 Dec 2021 12:16:38 +0100 +Subject: [PATCH 01/15] mtd: nand: ecc: Add infrastructure to support hardware + engines + +Add the necessary helpers to register/unregister hardware ECC engines +that will be called from ECC engine drivers. + +Also add helpers to get the right engine from the user +perspective. Keep a reference of the in use ECC engine in order to +prevent modules to be unloaded. Put the reference when the engine gets +retired. + +A static list of hardware (only) ECC engines is setup to keep track of +the registered engines. + +Signed-off-by: Miquel Raynal +Link: https://lore.kernel.org/linux-mtd/20211216111654.238086-13-miquel.raynal@bootlin.com +(cherry picked from commit 96489c1c0b53131b0e1ec33e2060538379ad6152) +--- + drivers/mtd/nand/core.c | 10 +++-- + drivers/mtd/nand/ecc.c | 88 ++++++++++++++++++++++++++++++++++++++++ + include/linux/mtd/nand.h | 28 +++++++++++++ + 3 files changed, 123 insertions(+), 3 deletions(-) + +--- a/drivers/mtd/nand/core.c ++++ b/drivers/mtd/nand/core.c +@@ -232,7 +232,9 @@ static int nanddev_get_ecc_engine(struct + nand->ecc.engine = nand_ecc_get_on_die_hw_engine(nand); + break; + case NAND_ECC_ENGINE_TYPE_ON_HOST: +- pr_err("On-host hardware ECC engines not supported yet\n"); ++ nand->ecc.engine = nand_ecc_get_on_host_hw_engine(nand); ++ if (PTR_ERR(nand->ecc.engine) == -EPROBE_DEFER) ++ return -EPROBE_DEFER; + break; + default: + pr_err("Missing ECC engine type\n"); +@@ -252,7 +254,7 @@ static int nanddev_put_ecc_engine(struct + { + switch (nand->ecc.ctx.conf.engine_type) { + case NAND_ECC_ENGINE_TYPE_ON_HOST: +- pr_err("On-host hardware ECC engines not supported yet\n"); ++ nand_ecc_put_on_host_hw_engine(nand); + break; + case NAND_ECC_ENGINE_TYPE_NONE: + case NAND_ECC_ENGINE_TYPE_SOFT: +@@ -297,7 +299,9 @@ int nanddev_ecc_engine_init(struct nand_ + /* Look for the ECC engine to use */ + ret = nanddev_get_ecc_engine(nand); + if (ret) { +- pr_err("No ECC engine found\n"); ++ if (ret != -EPROBE_DEFER) ++ pr_err("No ECC engine found\n"); ++ + return ret; + } + +--- a/drivers/mtd/nand/ecc.c ++++ b/drivers/mtd/nand/ecc.c +@@ -96,6 +96,12 @@ + #include + #include + #include ++#include ++#include ++#include ++ ++static LIST_HEAD(on_host_hw_engines); ++static DEFINE_MUTEX(on_host_hw_engines_mutex); + + /** + * nand_ecc_init_ctx - Init the ECC engine context +@@ -611,6 +617,88 @@ struct nand_ecc_engine *nand_ecc_get_on_ + } + EXPORT_SYMBOL(nand_ecc_get_on_die_hw_engine); + ++int nand_ecc_register_on_host_hw_engine(struct nand_ecc_engine *engine) ++{ ++ struct nand_ecc_engine *item; ++ ++ if (!engine) ++ return -EINVAL; ++ ++ /* Prevent multiple registrations of one engine */ ++ list_for_each_entry(item, &on_host_hw_engines, node) ++ if (item == engine) ++ return 0; ++ ++ mutex_lock(&on_host_hw_engines_mutex); ++ list_add_tail(&engine->node, &on_host_hw_engines); ++ mutex_unlock(&on_host_hw_engines_mutex); ++ ++ return 0; ++} ++EXPORT_SYMBOL(nand_ecc_register_on_host_hw_engine); ++ ++int nand_ecc_unregister_on_host_hw_engine(struct nand_ecc_engine *engine) ++{ ++ if (!engine) ++ return -EINVAL; ++ ++ mutex_lock(&on_host_hw_engines_mutex); ++ list_del(&engine->node); ++ mutex_unlock(&on_host_hw_engines_mutex); ++ ++ return 0; ++} ++EXPORT_SYMBOL(nand_ecc_unregister_on_host_hw_engine); ++ ++static struct nand_ecc_engine *nand_ecc_match_on_host_hw_engine(struct device *dev) ++{ ++ struct nand_ecc_engine *item; ++ ++ list_for_each_entry(item, &on_host_hw_engines, node) ++ if (item->dev == dev) ++ return item; ++ ++ return NULL; ++} ++ ++struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand) ++{ ++ struct nand_ecc_engine *engine = NULL; ++ struct device *dev = &nand->mtd.dev; ++ struct platform_device *pdev; ++ struct device_node *np; ++ ++ if (list_empty(&on_host_hw_engines)) ++ return NULL; ++ ++ /* Check for an explicit nand-ecc-engine property */ ++ np = of_parse_phandle(dev->of_node, "nand-ecc-engine", 0); ++ if (np) { ++ pdev = of_find_device_by_node(np); ++ if (!pdev) ++ return ERR_PTR(-EPROBE_DEFER); ++ ++ engine = nand_ecc_match_on_host_hw_engine(&pdev->dev); ++ platform_device_put(pdev); ++ of_node_put(np); ++ ++ if (!engine) ++ return ERR_PTR(-EPROBE_DEFER); ++ } ++ ++ if (engine) ++ get_device(engine->dev); ++ ++ return engine; ++} ++EXPORT_SYMBOL(nand_ecc_get_on_host_hw_engine); ++ ++void nand_ecc_put_on_host_hw_engine(struct nand_device *nand) ++{ ++ put_device(nand->ecc.engine->dev); ++} ++EXPORT_SYMBOL(nand_ecc_put_on_host_hw_engine); ++ + MODULE_LICENSE("GPL"); + MODULE_AUTHOR("Miquel Raynal "); + MODULE_DESCRIPTION("Generic ECC engine"); +--- a/include/linux/mtd/nand.h ++++ b/include/linux/mtd/nand.h +@@ -264,11 +264,35 @@ struct nand_ecc_engine_ops { + }; + + /** ++ * enum nand_ecc_engine_integration - How the NAND ECC engine is integrated ++ * @NAND_ECC_ENGINE_INTEGRATION_INVALID: Invalid value ++ * @NAND_ECC_ENGINE_INTEGRATION_PIPELINED: Pipelined engine, performs on-the-fly ++ * correction, does not need to copy ++ * data around ++ * @NAND_ECC_ENGINE_INTEGRATION_EXTERNAL: External engine, needs to bring the ++ * data into its own area before use ++ */ ++enum nand_ecc_engine_integration { ++ NAND_ECC_ENGINE_INTEGRATION_INVALID, ++ NAND_ECC_ENGINE_INTEGRATION_PIPELINED, ++ NAND_ECC_ENGINE_INTEGRATION_EXTERNAL, ++}; ++ ++/** + * struct nand_ecc_engine - ECC engine abstraction for NAND devices ++ * @dev: Host device ++ * @node: Private field for registration time + * @ops: ECC engine operations ++ * @integration: How the engine is integrated with the host ++ * (only relevant on %NAND_ECC_ENGINE_TYPE_ON_HOST engines) ++ * @priv: Private data + */ + struct nand_ecc_engine { ++ struct device *dev; ++ struct list_head node; + struct nand_ecc_engine_ops *ops; ++ enum nand_ecc_engine_integration integration; ++ void *priv; + }; + + void of_get_nand_ecc_user_config(struct nand_device *nand); +@@ -279,8 +303,12 @@ int nand_ecc_prepare_io_req(struct nand_ + int nand_ecc_finish_io_req(struct nand_device *nand, + struct nand_page_io_req *req); + bool nand_ecc_is_strong_enough(struct nand_device *nand); ++int nand_ecc_register_on_host_hw_engine(struct nand_ecc_engine *engine); ++int nand_ecc_unregister_on_host_hw_engine(struct nand_ecc_engine *engine); + struct nand_ecc_engine *nand_ecc_get_sw_engine(struct nand_device *nand); + struct nand_ecc_engine *nand_ecc_get_on_die_hw_engine(struct nand_device *nand); ++struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand); ++void nand_ecc_put_on_host_hw_engine(struct nand_device *nand); + + #if IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING) + struct nand_ecc_engine *nand_ecc_sw_hamming_get_engine(void); diff --git a/target/linux/mediatek/patches-6.1/120-02-v5.18-mtd-nand-Add-a-new-helper-to-retrieve-the-ECC-contex.patch b/target/linux/mediatek/patches-6.1/120-02-v5.18-mtd-nand-Add-a-new-helper-to-retrieve-the-ECC-contex.patch new file mode 100644 index 00000000000..61a39ee0e59 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/120-02-v5.18-mtd-nand-Add-a-new-helper-to-retrieve-the-ECC-contex.patch @@ -0,0 +1,31 @@ +From 840b2f8dd2d0579e517140e1f9bbc482eaf4ed07 Mon Sep 17 00:00:00 2001 +From: Miquel Raynal +Date: Thu, 16 Dec 2021 12:16:39 +0100 +Subject: [PATCH 02/15] mtd: nand: Add a new helper to retrieve the ECC context + +Introduce nand_to_ecc_ctx() which will allow to easily jump to the +private pointer of an ECC context given a NAND device. This is very +handy, from the prepare or finish ECC hook, to get the internal context +out of the NAND device object. + +Signed-off-by: Miquel Raynal +Link: https://lore.kernel.org/linux-mtd/20211216111654.238086-14-miquel.raynal@bootlin.com +(cherry picked from commit cda32a618debd3fad8e42757b198719ae180f8f4) +--- + include/linux/mtd/nand.h | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/include/linux/mtd/nand.h ++++ b/include/linux/mtd/nand.h +@@ -990,6 +990,11 @@ int nanddev_markbad(struct nand_device * + int nanddev_ecc_engine_init(struct nand_device *nand); + void nanddev_ecc_engine_cleanup(struct nand_device *nand); + ++static inline void *nand_to_ecc_ctx(struct nand_device *nand) ++{ ++ return nand->ecc.ctx.priv; ++} ++ + /* BBT related functions */ + enum nand_bbt_block_status { + NAND_BBT_BLOCK_STATUS_UNKNOWN, diff --git a/target/linux/mediatek/patches-6.1/120-03-v5.18-mtd-nand-ecc-Provide-a-helper-to-retrieve-a-pileline.patch b/target/linux/mediatek/patches-6.1/120-03-v5.18-mtd-nand-ecc-Provide-a-helper-to-retrieve-a-pileline.patch new file mode 100644 index 00000000000..29b62880abd --- /dev/null +++ b/target/linux/mediatek/patches-6.1/120-03-v5.18-mtd-nand-ecc-Provide-a-helper-to-retrieve-a-pileline.patch @@ -0,0 +1,73 @@ +From 784866bc4f9f25e0494b77750f95af2a2619e498 Mon Sep 17 00:00:00 2001 +From: Miquel Raynal +Date: Thu, 16 Dec 2021 12:16:41 +0100 +Subject: [PATCH 03/15] mtd: nand: ecc: Provide a helper to retrieve a + pilelined engine device + +In a pipelined engine situation, we might either have the host which +internally has support for error correction, or have it using an +external hardware block for this purpose. In the former case, the host +is also the ECC engine. In the latter case, it is not. In order to get +the right pointers on the right devices (for example: in order to devm_* +allocate variables), let's introduce this helper which can safely be +called by pipelined ECC engines in order to retrieve the right device +structure. + +Signed-off-by: Miquel Raynal +Link: https://lore.kernel.org/linux-mtd/20211216111654.238086-16-miquel.raynal@bootlin.com +(cherry picked from commit 5145abeb0649acf810a32e63bd762e617a9b3309) +--- + drivers/mtd/nand/ecc.c | 31 +++++++++++++++++++++++++++++++ + include/linux/mtd/nand.h | 1 + + 2 files changed, 32 insertions(+) + +--- a/drivers/mtd/nand/ecc.c ++++ b/drivers/mtd/nand/ecc.c +@@ -699,6 +699,37 @@ void nand_ecc_put_on_host_hw_engine(stru + } + EXPORT_SYMBOL(nand_ecc_put_on_host_hw_engine); + ++/* ++ * In the case of a pipelined engine, the device registering the ECC ++ * engine is not necessarily the ECC engine itself but may be a host controller. ++ * It is then useful to provide a helper to retrieve the right device object ++ * which actually represents the ECC engine. ++ */ ++struct device *nand_ecc_get_engine_dev(struct device *host) ++{ ++ struct platform_device *ecc_pdev; ++ struct device_node *np; ++ ++ /* ++ * If the device node contains this property, it means we need to follow ++ * it in order to get the right ECC engine device we are looking for. ++ */ ++ np = of_parse_phandle(host->of_node, "nand-ecc-engine", 0); ++ if (!np) ++ return host; ++ ++ ecc_pdev = of_find_device_by_node(np); ++ if (!ecc_pdev) { ++ of_node_put(np); ++ return NULL; ++ } ++ ++ platform_device_put(ecc_pdev); ++ of_node_put(np); ++ ++ return &ecc_pdev->dev; ++} ++ + MODULE_LICENSE("GPL"); + MODULE_AUTHOR("Miquel Raynal "); + MODULE_DESCRIPTION("Generic ECC engine"); +--- a/include/linux/mtd/nand.h ++++ b/include/linux/mtd/nand.h +@@ -309,6 +309,7 @@ struct nand_ecc_engine *nand_ecc_get_sw_ + struct nand_ecc_engine *nand_ecc_get_on_die_hw_engine(struct nand_device *nand); + struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand); + void nand_ecc_put_on_host_hw_engine(struct nand_device *nand); ++struct device *nand_ecc_get_engine_dev(struct device *host); + + #if IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING) + struct nand_ecc_engine *nand_ecc_sw_hamming_get_engine(void); diff --git a/target/linux/mediatek/patches-6.1/120-04-v5.18-spi-spi-mem-Introduce-a-capability-structure.patch b/target/linux/mediatek/patches-6.1/120-04-v5.18-spi-spi-mem-Introduce-a-capability-structure.patch new file mode 100644 index 00000000000..1e7f572dd66 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/120-04-v5.18-spi-spi-mem-Introduce-a-capability-structure.patch @@ -0,0 +1,71 @@ +From 3e45577e70cbf8fdc5c13033114989794a3797d5 Mon Sep 17 00:00:00 2001 +From: Miquel Raynal +Date: Thu, 27 Jan 2022 10:17:56 +0100 +Subject: [PATCH 04/15] spi: spi-mem: Introduce a capability structure + +Create a spi_controller_mem_caps structure and put it within the +spi_controller structure close to the spi_controller_mem_ops +strucure. So far the only field in this structure is the support for dtr +operations, but soon we will add another parameter. + +Also create a helper to parse the capabilities and check if the +requested capability has been set or not. + +Signed-off-by: Miquel Raynal +Reviewed-by: Pratyush Yadav +Reviewed-by: Boris Brezillon +Reviewed-by: Tudor Ambarus +Reviewed-by: Mark Brown +Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-2-miquel.raynal@bootlin.com +(cherry picked from commit 4a3cc7fb6e63bcfdedec25364738f1493345bd20) +--- + include/linux/spi/spi-mem.h | 11 +++++++++++ + include/linux/spi/spi.h | 3 +++ + 2 files changed, 14 insertions(+) + +--- a/include/linux/spi/spi-mem.h ++++ b/include/linux/spi/spi-mem.h +@@ -286,6 +286,17 @@ struct spi_controller_mem_ops { + }; + + /** ++ * struct spi_controller_mem_caps - SPI memory controller capabilities ++ * @dtr: Supports DTR operations ++ */ ++struct spi_controller_mem_caps { ++ bool dtr; ++}; ++ ++#define spi_mem_controller_is_capable(ctlr, cap) \ ++ ((ctlr)->mem_caps && (ctlr)->mem_caps->cap) ++ ++/** + * struct spi_mem_driver - SPI memory driver + * @spidrv: inherit from a SPI driver + * @probe: probe a SPI memory. Usually where detection/initialization takes +--- a/include/linux/spi/spi.h ++++ b/include/linux/spi/spi.h +@@ -23,6 +23,7 @@ struct software_node; + struct spi_controller; + struct spi_transfer; + struct spi_controller_mem_ops; ++struct spi_controller_mem_caps; + + /* + * INTERFACES between SPI master-side drivers and SPI slave protocol handlers, +@@ -419,6 +420,7 @@ extern struct spi_device *spi_new_ancill + * @mem_ops: optimized/dedicated operations for interactions with SPI memory. + * This field is optional and should only be implemented if the + * controller has native support for memory like operations. ++ * @mem_caps: controller capabilities for the handling of memory operations. + * @unprepare_message: undo any work done by prepare_message(). + * @slave_abort: abort the ongoing transfer request on an SPI slave controller + * @cs_gpios: LEGACY: array of GPIO descs to use as chip select lines; one per +@@ -643,6 +645,7 @@ struct spi_controller { + + /* Optimized handlers for SPI memory-like operations. */ + const struct spi_controller_mem_ops *mem_ops; ++ const struct spi_controller_mem_caps *mem_caps; + + /* gpio chip select */ + int *cs_gpios; diff --git a/target/linux/mediatek/patches-6.1/120-05-v5.18-spi-spi-mem-Check-the-controller-extra-capabilities.patch b/target/linux/mediatek/patches-6.1/120-05-v5.18-spi-spi-mem-Check-the-controller-extra-capabilities.patch new file mode 100644 index 00000000000..9f01fdb8353 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/120-05-v5.18-spi-spi-mem-Check-the-controller-extra-capabilities.patch @@ -0,0 +1,51 @@ +From c9cae7e1e5c87d0aa76b7bededa5191a0c8cf25a Mon Sep 17 00:00:00 2001 +From: Miquel Raynal +Date: Thu, 27 Jan 2022 10:17:57 +0100 +Subject: [PATCH 05/15] spi: spi-mem: Check the controller extra capabilities + +Controllers can now provide a spi-mem capabilities structure. Let's make +use of it in spi_mem_controller_default_supports_op(). As we want to +check for DTR operations as well as normal operations in a single +helper, let's pull the necessary checks from spi_mem_dtr_supports_op() +for now. + +However, because no controller provide these extra capabilities, this +change has no effect so far. + +Signed-off-by: Miquel Raynal +Reviewed-by: Pratyush Yadav +Reviewed-by: Boris Brezillon +Reviewed-by: Tudor Ambarus +Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-3-miquel.raynal@bootlin.com +(cherry picked from commit cb7e96ee81edaa48c67d84c14df2cbe464391c37) +--- + drivers/spi/spi-mem.c | 17 +++++++++++++---- + 1 file changed, 13 insertions(+), 4 deletions(-) + +--- a/drivers/spi/spi-mem.c ++++ b/drivers/spi/spi-mem.c +@@ -173,11 +173,20 @@ EXPORT_SYMBOL_GPL(spi_mem_dtr_supports_o + bool spi_mem_default_supports_op(struct spi_mem *mem, + const struct spi_mem_op *op) + { +- if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr) +- return false; ++ struct spi_controller *ctlr = mem->spi->controller; ++ bool op_is_dtr = ++ op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr; + +- if (op->cmd.nbytes != 1) +- return false; ++ if (op_is_dtr) { ++ if (!spi_mem_controller_is_capable(ctlr, dtr)) ++ return false; ++ ++ if (op->cmd.nbytes != 2) ++ return false; ++ } else { ++ if (op->cmd.nbytes != 1) ++ return false; ++ } + + return spi_mem_check_buswidth(mem, op); + } diff --git a/target/linux/mediatek/patches-6.1/120-06-v5.18-spi-spi-mem-Kill-the-spi_mem_dtr_supports_op-helper.patch b/target/linux/mediatek/patches-6.1/120-06-v5.18-spi-spi-mem-Kill-the-spi_mem_dtr_supports_op-helper.patch new file mode 100644 index 00000000000..c313a455b60 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/120-06-v5.18-spi-spi-mem-Kill-the-spi_mem_dtr_supports_op-helper.patch @@ -0,0 +1,111 @@ +From 2e5fba82e4aeb72d71230eef2541881615aaf7cf Mon Sep 17 00:00:00 2001 +From: Miquel Raynal +Date: Thu, 27 Jan 2022 10:18:00 +0100 +Subject: [PATCH 06/15] spi: spi-mem: Kill the spi_mem_dtr_supports_op() helper + +Now that spi_mem_default_supports_op() has access to the static +controller capabilities (relating to memory operations), and now that +these capabilities have been filled by the relevant controllers, there +is no need for a specific helper checking only DTR operations, so let's +just kill spi_mem_dtr_supports_op() and simply use +spi_mem_default_supports_op() instead. + +Signed-off-by: Miquel Raynal +Reviewed-by: Pratyush Yadav +Reviewed-by: Boris Brezillon +Reviewed-by: Tudor Ambarus +Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-6-miquel.raynal@bootlin.com +(cherry picked from commit 9a15efc5d5e6b5beaed0883e5bdcd0b1384c1b20) +--- + drivers/spi/spi-cadence-quadspi.c | 5 +---- + drivers/spi/spi-mem.c | 10 ---------- + drivers/spi/spi-mxic.c | 10 +--------- + include/linux/spi/spi-mem.h | 11 ----------- + 4 files changed, 2 insertions(+), 34 deletions(-) + +--- a/drivers/spi/spi-cadence-quadspi.c ++++ b/drivers/spi/spi-cadence-quadspi.c +@@ -1249,10 +1249,7 @@ static bool cqspi_supports_mem_op(struct + return false; + } + +- if (all_true) +- return spi_mem_dtr_supports_op(mem, op); +- else +- return spi_mem_default_supports_op(mem, op); ++ return spi_mem_default_supports_op(mem, op); + } + + static int cqspi_of_get_flash_pdata(struct platform_device *pdev, +--- a/drivers/spi/spi-mem.c ++++ b/drivers/spi/spi-mem.c +@@ -160,16 +160,6 @@ static bool spi_mem_check_buswidth(struc + return true; + } + +-bool spi_mem_dtr_supports_op(struct spi_mem *mem, +- const struct spi_mem_op *op) +-{ +- if (op->cmd.nbytes != 2) +- return false; +- +- return spi_mem_check_buswidth(mem, op); +-} +-EXPORT_SYMBOL_GPL(spi_mem_dtr_supports_op); +- + bool spi_mem_default_supports_op(struct spi_mem *mem, + const struct spi_mem_op *op) + { +--- a/drivers/spi/spi-mxic.c ++++ b/drivers/spi/spi-mxic.c +@@ -331,8 +331,6 @@ static int mxic_spi_data_xfer(struct mxi + static bool mxic_spi_mem_supports_op(struct spi_mem *mem, + const struct spi_mem_op *op) + { +- bool all_false; +- + if (op->data.buswidth > 8 || op->addr.buswidth > 8 || + op->dummy.buswidth > 8 || op->cmd.buswidth > 8) + return false; +@@ -344,13 +342,7 @@ static bool mxic_spi_mem_supports_op(str + if (op->addr.nbytes > 7) + return false; + +- all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr && +- !op->data.dtr; +- +- if (all_false) +- return spi_mem_default_supports_op(mem, op); +- else +- return spi_mem_dtr_supports_op(mem, op); ++ return spi_mem_default_supports_op(mem, op); + } + + static int mxic_spi_mem_exec_op(struct spi_mem *mem, +--- a/include/linux/spi/spi-mem.h ++++ b/include/linux/spi/spi-mem.h +@@ -330,10 +330,6 @@ void spi_controller_dma_unmap_mem_op_dat + + bool spi_mem_default_supports_op(struct spi_mem *mem, + const struct spi_mem_op *op); +- +-bool spi_mem_dtr_supports_op(struct spi_mem *mem, +- const struct spi_mem_op *op); +- + #else + static inline int + spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr, +@@ -356,13 +352,6 @@ bool spi_mem_default_supports_op(struct + { + return false; + } +- +-static inline +-bool spi_mem_dtr_supports_op(struct spi_mem *mem, +- const struct spi_mem_op *op) +-{ +- return false; +-} + #endif /* CONFIG_SPI_MEM */ + + int spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op); diff --git a/target/linux/mediatek/patches-6.1/120-07-v5.18-spi-spi-mem-Add-an-ecc-parameter-to-the-spi_mem_op-s.patch b/target/linux/mediatek/patches-6.1/120-07-v5.18-spi-spi-mem-Add-an-ecc-parameter-to-the-spi_mem_op-s.patch new file mode 100644 index 00000000000..6d7e47650b2 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/120-07-v5.18-spi-spi-mem-Add-an-ecc-parameter-to-the-spi_mem_op-s.patch @@ -0,0 +1,72 @@ +From 9e7eb0ea442ecb1c3fe443289e288694f10c5148 Mon Sep 17 00:00:00 2001 +From: Miquel Raynal +Date: Thu, 27 Jan 2022 10:18:01 +0100 +Subject: [PATCH 07/15] spi: spi-mem: Add an ecc parameter to the spi_mem_op + structure + +Soon the SPI-NAND core will need a way to request a SPI controller to +enable ECC support for a given operation. This is because of the +pipelined integration of certain ECC engines, which are directly managed +by the SPI controller itself. + +Introduce a spi_mem_op additional field for this purpose: ecc. + +So far this field is left unset and checked to be false by all +the SPI controller drivers in their ->supports_op() hook, as they all +call spi_mem_default_supports_op(). + +Signed-off-by: Miquel Raynal +Acked-by: Pratyush Yadav +Reviewed-by: Boris Brezillon +Reviewed-by: Tudor Ambarus +Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-7-miquel.raynal@bootlin.com +(cherry picked from commit a433c2cbd75ab76f277364f44e76f32c7df306e7) +--- + drivers/spi/spi-mem.c | 5 +++++ + include/linux/spi/spi-mem.h | 4 ++++ + 2 files changed, 9 insertions(+) + +--- a/drivers/spi/spi-mem.c ++++ b/drivers/spi/spi-mem.c +@@ -178,6 +178,11 @@ bool spi_mem_default_supports_op(struct + return false; + } + ++ if (op->data.ecc) { ++ if (!spi_mem_controller_is_capable(ctlr, ecc)) ++ return false; ++ } ++ + return spi_mem_check_buswidth(mem, op); + } + EXPORT_SYMBOL_GPL(spi_mem_default_supports_op); +--- a/include/linux/spi/spi-mem.h ++++ b/include/linux/spi/spi-mem.h +@@ -89,6 +89,7 @@ enum spi_mem_data_dir { + * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not + * @data.buswidth: number of IO lanes used to send/receive the data + * @data.dtr: whether the data should be sent in DTR mode or not ++ * @data.ecc: whether error correction is required or not + * @data.dir: direction of the transfer + * @data.nbytes: number of data bytes to send/receive. Can be zero if the + * operation does not involve transferring data +@@ -119,6 +120,7 @@ struct spi_mem_op { + struct { + u8 buswidth; + u8 dtr : 1; ++ u8 ecc : 1; + enum spi_mem_data_dir dir; + unsigned int nbytes; + union { +@@ -288,9 +290,11 @@ struct spi_controller_mem_ops { + /** + * struct spi_controller_mem_caps - SPI memory controller capabilities + * @dtr: Supports DTR operations ++ * @ecc: Supports operations with error correction + */ + struct spi_controller_mem_caps { + bool dtr; ++ bool ecc; + }; + + #define spi_mem_controller_is_capable(ctlr, cap) \ diff --git a/target/linux/mediatek/patches-6.1/120-08-v5.18-mtd-spinand-Delay-a-little-bit-the-dirmap-creation.patch b/target/linux/mediatek/patches-6.1/120-08-v5.18-mtd-spinand-Delay-a-little-bit-the-dirmap-creation.patch new file mode 100644 index 00000000000..87c7b7cd297 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/120-08-v5.18-mtd-spinand-Delay-a-little-bit-the-dirmap-creation.patch @@ -0,0 +1,50 @@ +From 94ef3c35b935a63f6c156957c92f6cf33c9a8dae Mon Sep 17 00:00:00 2001 +From: Miquel Raynal +Date: Thu, 27 Jan 2022 10:18:02 +0100 +Subject: [PATCH 08/15] mtd: spinand: Delay a little bit the dirmap creation + +As we will soon tweak the dirmap creation to act a little bit +differently depending on the picked ECC engine, we need to initialize +dirmaps after ECC engines. This should not have any effect as dirmaps +are not yet used at this point. + +Signed-off-by: Miquel Raynal +Reviewed-by: Boris Brezillon +Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-8-miquel.raynal@bootlin.com +(cherry picked from commit dc4c2cbf0be2d4a8e2a65013ea2815bb2c8ba949) +--- + drivers/mtd/nand/spi/core.c | 16 ++++++++-------- + 1 file changed, 8 insertions(+), 8 deletions(-) + +--- a/drivers/mtd/nand/spi/core.c ++++ b/drivers/mtd/nand/spi/core.c +@@ -1221,14 +1221,6 @@ static int spinand_init(struct spinand_d + if (ret) + goto err_free_bufs; + +- ret = spinand_create_dirmaps(spinand); +- if (ret) { +- dev_err(dev, +- "Failed to create direct mappings for read/write operations (err = %d)\n", +- ret); +- goto err_manuf_cleanup; +- } +- + ret = nanddev_init(nand, &spinand_ops, THIS_MODULE); + if (ret) + goto err_manuf_cleanup; +@@ -1263,6 +1255,14 @@ static int spinand_init(struct spinand_d + mtd->ecc_strength = nanddev_get_ecc_conf(nand)->strength; + mtd->ecc_step_size = nanddev_get_ecc_conf(nand)->step_size; + ++ ret = spinand_create_dirmaps(spinand); ++ if (ret) { ++ dev_err(dev, ++ "Failed to create direct mappings for read/write operations (err = %d)\n", ++ ret); ++ goto err_cleanup_ecc_engine; ++ } ++ + return 0; + + err_cleanup_ecc_engine: diff --git a/target/linux/mediatek/patches-6.1/120-09-v5.18-mtd-spinand-Create-direct-mapping-descriptors-for-EC.patch b/target/linux/mediatek/patches-6.1/120-09-v5.18-mtd-spinand-Create-direct-mapping-descriptors-for-EC.patch new file mode 100644 index 00000000000..35912cd2cd6 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/120-09-v5.18-mtd-spinand-Create-direct-mapping-descriptors-for-EC.patch @@ -0,0 +1,98 @@ +From eb4a2d282c3c5752211d69be6dff2674119e5583 Mon Sep 17 00:00:00 2001 +From: Miquel Raynal +Date: Thu, 27 Jan 2022 10:18:03 +0100 +Subject: [PATCH 09/15] mtd: spinand: Create direct mapping descriptors for ECC + operations + +In order for pipelined ECC engines to be able to enable/disable the ECC +engine only when needed and avoid races when future parallel-operations +will be supported, we need to provide the information about the use of +the ECC engine in the direct mapping hooks. As direct mapping +configurations are meant to be static, it is best to create two new +mappings: one for regular 'raw' accesses and one for accesses involving +correction. It is up to the driver to use or not the new ECC enable +boolean contained in the spi-mem operation. + +As dirmaps are not free (they consume a few pages of MMIO address space) +and because these extra entries are only meant to be used by pipelined +engines, let's limit their use to this specific type of engine and save +a bit of memory with all the other setups. + +Signed-off-by: Miquel Raynal +Reviewed-by: Boris Brezillon +Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-9-miquel.raynal@bootlin.com +(cherry picked from commit f9d7c7265bcff7d9a17425a8cddf702e8fe159c2) +--- + drivers/mtd/nand/spi/core.c | 35 +++++++++++++++++++++++++++++++++-- + include/linux/mtd/spinand.h | 2 ++ + 2 files changed, 35 insertions(+), 2 deletions(-) + +--- a/drivers/mtd/nand/spi/core.c ++++ b/drivers/mtd/nand/spi/core.c +@@ -381,7 +381,10 @@ static int spinand_read_from_cache_op(st + } + } + +- rdesc = spinand->dirmaps[req->pos.plane].rdesc; ++ if (req->mode == MTD_OPS_RAW) ++ rdesc = spinand->dirmaps[req->pos.plane].rdesc; ++ else ++ rdesc = spinand->dirmaps[req->pos.plane].rdesc_ecc; + + while (nbytes) { + ret = spi_mem_dirmap_read(rdesc, column, nbytes, buf); +@@ -452,7 +455,10 @@ static int spinand_write_to_cache_op(str + req->ooblen); + } + +- wdesc = spinand->dirmaps[req->pos.plane].wdesc; ++ if (req->mode == MTD_OPS_RAW) ++ wdesc = spinand->dirmaps[req->pos.plane].wdesc; ++ else ++ wdesc = spinand->dirmaps[req->pos.plane].wdesc_ecc; + + while (nbytes) { + ret = spi_mem_dirmap_write(wdesc, column, nbytes, buf); +@@ -875,6 +881,31 @@ static int spinand_create_dirmap(struct + + spinand->dirmaps[plane].rdesc = desc; + ++ if (nand->ecc.engine->integration != NAND_ECC_ENGINE_INTEGRATION_PIPELINED) { ++ spinand->dirmaps[plane].wdesc_ecc = spinand->dirmaps[plane].wdesc; ++ spinand->dirmaps[plane].rdesc_ecc = spinand->dirmaps[plane].rdesc; ++ ++ return 0; ++ } ++ ++ info.op_tmpl = *spinand->op_templates.update_cache; ++ info.op_tmpl.data.ecc = true; ++ desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev, ++ spinand->spimem, &info); ++ if (IS_ERR(desc)) ++ return PTR_ERR(desc); ++ ++ spinand->dirmaps[plane].wdesc_ecc = desc; ++ ++ info.op_tmpl = *spinand->op_templates.read_cache; ++ info.op_tmpl.data.ecc = true; ++ desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev, ++ spinand->spimem, &info); ++ if (IS_ERR(desc)) ++ return PTR_ERR(desc); ++ ++ spinand->dirmaps[plane].rdesc_ecc = desc; ++ + return 0; + } + +--- a/include/linux/mtd/spinand.h ++++ b/include/linux/mtd/spinand.h +@@ -392,6 +392,8 @@ struct spinand_info { + struct spinand_dirmap { + struct spi_mem_dirmap_desc *wdesc; + struct spi_mem_dirmap_desc *rdesc; ++ struct spi_mem_dirmap_desc *wdesc_ecc; ++ struct spi_mem_dirmap_desc *rdesc_ecc; + }; + + /** diff --git a/target/linux/mediatek/patches-6.1/120-11-v5.19-mtd-nand-make-mtk_ecc.c-a-separated-module.patch b/target/linux/mediatek/patches-6.1/120-11-v5.19-mtd-nand-make-mtk_ecc.c-a-separated-module.patch new file mode 100644 index 00000000000..fd9098eae96 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/120-11-v5.19-mtd-nand-make-mtk_ecc.c-a-separated-module.patch @@ -0,0 +1,1383 @@ +From ebb9653d4a87c64fb679e4c339e867556dada719 Mon Sep 17 00:00:00 2001 +From: Chuanhong Guo +Date: Tue, 22 Mar 2022 18:44:21 +0800 +Subject: [PATCH 11/15] mtd: nand: make mtk_ecc.c a separated module + +this code will be used in mediatek snfi spi-mem controller with +pipelined ECC engine. + +Signed-off-by: Chuanhong Guo +(cherry picked from commit 316f47cec4ce5b81aa8006de202d8769c117a52d) +--- + drivers/mtd/nand/Kconfig | 7 +++++++ + drivers/mtd/nand/Makefile | 1 + + drivers/mtd/nand/{raw/mtk_ecc.c => ecc-mtk.c} | 3 +-- + drivers/mtd/nand/raw/Kconfig | 1 + + drivers/mtd/nand/raw/Makefile | 2 +- + drivers/mtd/nand/raw/mtk_nand.c | 2 +- + .../nand/raw/mtk_ecc.h => include/linux/mtd/nand-ecc-mtk.h | 0 + 7 files changed, 12 insertions(+), 4 deletions(-) + rename drivers/mtd/nand/{raw/mtk_ecc.c => ecc-mtk.c} (99%) + rename drivers/mtd/nand/raw/mtk_ecc.h => include/linux/mtd/nand-ecc-mtk.h (100%) + +--- a/drivers/mtd/nand/Kconfig ++++ b/drivers/mtd/nand/Kconfig +@@ -50,6 +50,13 @@ config MTD_NAND_MTK_BMT + bool "Support MediaTek NAND Bad-block Management Table" + default n + ++config MTD_NAND_ECC_MEDIATEK ++ tristate "Mediatek hardware ECC engine" ++ depends on HAS_IOMEM ++ select MTD_NAND_ECC ++ help ++ This enables support for the hardware ECC engine from Mediatek. ++ + endmenu + + endmenu +--- a/drivers/mtd/nand/Makefile ++++ b/drivers/mtd/nand/Makefile +@@ -3,6 +3,7 @@ + nandcore-objs := core.o bbt.o + obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o + obj-$(CONFIG_MTD_NAND_MTK_BMT) += mtk_bmt.o mtk_bmt_v2.o mtk_bmt_bbt.o mtk_bmt_nmbm.o ++obj-$(CONFIG_MTD_NAND_ECC_MEDIATEK) += ecc-mtk.o + + obj-y += onenand/ + obj-y += raw/ +--- a/drivers/mtd/nand/raw/mtk_ecc.c ++++ /dev/null +@@ -1,599 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR MIT +-/* +- * MTK ECC controller driver. +- * Copyright (C) 2016 MediaTek Inc. +- * Authors: Xiaolei Li +- * Jorge Ramirez-Ortiz +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include "mtk_ecc.h" +- +-#define ECC_IDLE_MASK BIT(0) +-#define ECC_IRQ_EN BIT(0) +-#define ECC_PG_IRQ_SEL BIT(1) +-#define ECC_OP_ENABLE (1) +-#define ECC_OP_DISABLE (0) +- +-#define ECC_ENCCON (0x00) +-#define ECC_ENCCNFG (0x04) +-#define ECC_MS_SHIFT (16) +-#define ECC_ENCDIADDR (0x08) +-#define ECC_ENCIDLE (0x0C) +-#define ECC_DECCON (0x100) +-#define ECC_DECCNFG (0x104) +-#define DEC_EMPTY_EN BIT(31) +-#define DEC_CNFG_CORRECT (0x3 << 12) +-#define ECC_DECIDLE (0x10C) +-#define ECC_DECENUM0 (0x114) +- +-#define ECC_TIMEOUT (500000) +- +-#define ECC_IDLE_REG(op) ((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE) +-#define ECC_CTL_REG(op) ((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON) +- +-struct mtk_ecc_caps { +- u32 err_mask; +- u32 err_shift; +- const u8 *ecc_strength; +- const u32 *ecc_regs; +- u8 num_ecc_strength; +- u8 ecc_mode_shift; +- u32 parity_bits; +- int pg_irq_sel; +-}; +- +-struct mtk_ecc { +- struct device *dev; +- const struct mtk_ecc_caps *caps; +- void __iomem *regs; +- struct clk *clk; +- +- struct completion done; +- struct mutex lock; +- u32 sectors; +- +- u8 *eccdata; +-}; +- +-/* ecc strength that each IP supports */ +-static const u8 ecc_strength_mt2701[] = { +- 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, +- 40, 44, 48, 52, 56, 60 +-}; +- +-static const u8 ecc_strength_mt2712[] = { +- 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, +- 40, 44, 48, 52, 56, 60, 68, 72, 80 +-}; +- +-static const u8 ecc_strength_mt7622[] = { +- 4, 6, 8, 10, 12 +-}; +- +-enum mtk_ecc_regs { +- ECC_ENCPAR00, +- ECC_ENCIRQ_EN, +- ECC_ENCIRQ_STA, +- ECC_DECDONE, +- ECC_DECIRQ_EN, +- ECC_DECIRQ_STA, +-}; +- +-static int mt2701_ecc_regs[] = { +- [ECC_ENCPAR00] = 0x10, +- [ECC_ENCIRQ_EN] = 0x80, +- [ECC_ENCIRQ_STA] = 0x84, +- [ECC_DECDONE] = 0x124, +- [ECC_DECIRQ_EN] = 0x200, +- [ECC_DECIRQ_STA] = 0x204, +-}; +- +-static int mt2712_ecc_regs[] = { +- [ECC_ENCPAR00] = 0x300, +- [ECC_ENCIRQ_EN] = 0x80, +- [ECC_ENCIRQ_STA] = 0x84, +- [ECC_DECDONE] = 0x124, +- [ECC_DECIRQ_EN] = 0x200, +- [ECC_DECIRQ_STA] = 0x204, +-}; +- +-static int mt7622_ecc_regs[] = { +- [ECC_ENCPAR00] = 0x10, +- [ECC_ENCIRQ_EN] = 0x30, +- [ECC_ENCIRQ_STA] = 0x34, +- [ECC_DECDONE] = 0x11c, +- [ECC_DECIRQ_EN] = 0x140, +- [ECC_DECIRQ_STA] = 0x144, +-}; +- +-static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc, +- enum mtk_ecc_operation op) +-{ +- struct device *dev = ecc->dev; +- u32 val; +- int ret; +- +- ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val, +- val & ECC_IDLE_MASK, +- 10, ECC_TIMEOUT); +- if (ret) +- dev_warn(dev, "%s NOT idle\n", +- op == ECC_ENCODE ? "encoder" : "decoder"); +-} +- +-static irqreturn_t mtk_ecc_irq(int irq, void *id) +-{ +- struct mtk_ecc *ecc = id; +- u32 dec, enc; +- +- dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]) +- & ECC_IRQ_EN; +- if (dec) { +- dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]); +- if (dec & ecc->sectors) { +- /* +- * Clear decode IRQ status once again to ensure that +- * there will be no extra IRQ. +- */ +- readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]); +- ecc->sectors = 0; +- complete(&ecc->done); +- } else { +- return IRQ_HANDLED; +- } +- } else { +- enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA]) +- & ECC_IRQ_EN; +- if (enc) +- complete(&ecc->done); +- else +- return IRQ_NONE; +- } +- +- return IRQ_HANDLED; +-} +- +-static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config) +-{ +- u32 ecc_bit, dec_sz, enc_sz; +- u32 reg, i; +- +- for (i = 0; i < ecc->caps->num_ecc_strength; i++) { +- if (ecc->caps->ecc_strength[i] == config->strength) +- break; +- } +- +- if (i == ecc->caps->num_ecc_strength) { +- dev_err(ecc->dev, "invalid ecc strength %d\n", +- config->strength); +- return -EINVAL; +- } +- +- ecc_bit = i; +- +- if (config->op == ECC_ENCODE) { +- /* configure ECC encoder (in bits) */ +- enc_sz = config->len << 3; +- +- reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift); +- reg |= (enc_sz << ECC_MS_SHIFT); +- writel(reg, ecc->regs + ECC_ENCCNFG); +- +- if (config->mode != ECC_NFI_MODE) +- writel(lower_32_bits(config->addr), +- ecc->regs + ECC_ENCDIADDR); +- +- } else { +- /* configure ECC decoder (in bits) */ +- dec_sz = (config->len << 3) + +- config->strength * ecc->caps->parity_bits; +- +- reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift); +- reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT; +- reg |= DEC_EMPTY_EN; +- writel(reg, ecc->regs + ECC_DECCNFG); +- +- if (config->sectors) +- ecc->sectors = 1 << (config->sectors - 1); +- } +- +- return 0; +-} +- +-void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats, +- int sectors) +-{ +- u32 offset, i, err; +- u32 bitflips = 0; +- +- stats->corrected = 0; +- stats->failed = 0; +- +- for (i = 0; i < sectors; i++) { +- offset = (i >> 2) << 2; +- err = readl(ecc->regs + ECC_DECENUM0 + offset); +- err = err >> ((i % 4) * ecc->caps->err_shift); +- err &= ecc->caps->err_mask; +- if (err == ecc->caps->err_mask) { +- /* uncorrectable errors */ +- stats->failed++; +- continue; +- } +- +- stats->corrected += err; +- bitflips = max_t(u32, bitflips, err); +- } +- +- stats->bitflips = bitflips; +-} +-EXPORT_SYMBOL(mtk_ecc_get_stats); +- +-void mtk_ecc_release(struct mtk_ecc *ecc) +-{ +- clk_disable_unprepare(ecc->clk); +- put_device(ecc->dev); +-} +-EXPORT_SYMBOL(mtk_ecc_release); +- +-static void mtk_ecc_hw_init(struct mtk_ecc *ecc) +-{ +- mtk_ecc_wait_idle(ecc, ECC_ENCODE); +- writew(ECC_OP_DISABLE, ecc->regs + ECC_ENCCON); +- +- mtk_ecc_wait_idle(ecc, ECC_DECODE); +- writel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON); +-} +- +-static struct mtk_ecc *mtk_ecc_get(struct device_node *np) +-{ +- struct platform_device *pdev; +- struct mtk_ecc *ecc; +- +- pdev = of_find_device_by_node(np); +- if (!pdev) +- return ERR_PTR(-EPROBE_DEFER); +- +- ecc = platform_get_drvdata(pdev); +- if (!ecc) { +- put_device(&pdev->dev); +- return ERR_PTR(-EPROBE_DEFER); +- } +- +- clk_prepare_enable(ecc->clk); +- mtk_ecc_hw_init(ecc); +- +- return ecc; +-} +- +-struct mtk_ecc *of_mtk_ecc_get(struct device_node *of_node) +-{ +- struct mtk_ecc *ecc = NULL; +- struct device_node *np; +- +- np = of_parse_phandle(of_node, "ecc-engine", 0); +- if (np) { +- ecc = mtk_ecc_get(np); +- of_node_put(np); +- } +- +- return ecc; +-} +-EXPORT_SYMBOL(of_mtk_ecc_get); +- +-int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config) +-{ +- enum mtk_ecc_operation op = config->op; +- u16 reg_val; +- int ret; +- +- ret = mutex_lock_interruptible(&ecc->lock); +- if (ret) { +- dev_err(ecc->dev, "interrupted when attempting to lock\n"); +- return ret; +- } +- +- mtk_ecc_wait_idle(ecc, op); +- +- ret = mtk_ecc_config(ecc, config); +- if (ret) { +- mutex_unlock(&ecc->lock); +- return ret; +- } +- +- if (config->mode != ECC_NFI_MODE || op != ECC_ENCODE) { +- init_completion(&ecc->done); +- reg_val = ECC_IRQ_EN; +- /* +- * For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it +- * means this chip can only generate one ecc irq during page +- * read / write. If is 0, generate one ecc irq each ecc step. +- */ +- if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE) +- reg_val |= ECC_PG_IRQ_SEL; +- if (op == ECC_ENCODE) +- writew(reg_val, ecc->regs + +- ecc->caps->ecc_regs[ECC_ENCIRQ_EN]); +- else +- writew(reg_val, ecc->regs + +- ecc->caps->ecc_regs[ECC_DECIRQ_EN]); +- } +- +- writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op)); +- +- return 0; +-} +-EXPORT_SYMBOL(mtk_ecc_enable); +- +-void mtk_ecc_disable(struct mtk_ecc *ecc) +-{ +- enum mtk_ecc_operation op = ECC_ENCODE; +- +- /* find out the running operation */ +- if (readw(ecc->regs + ECC_CTL_REG(op)) != ECC_OP_ENABLE) +- op = ECC_DECODE; +- +- /* disable it */ +- mtk_ecc_wait_idle(ecc, op); +- if (op == ECC_DECODE) { +- /* +- * Clear decode IRQ status in case there is a timeout to wait +- * decode IRQ. +- */ +- readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]); +- writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]); +- } else { +- writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]); +- } +- +- writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op)); +- +- mutex_unlock(&ecc->lock); +-} +-EXPORT_SYMBOL(mtk_ecc_disable); +- +-int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op) +-{ +- int ret; +- +- ret = wait_for_completion_timeout(&ecc->done, msecs_to_jiffies(500)); +- if (!ret) { +- dev_err(ecc->dev, "%s timeout - interrupt did not arrive)\n", +- (op == ECC_ENCODE) ? "encoder" : "decoder"); +- return -ETIMEDOUT; +- } +- +- return 0; +-} +-EXPORT_SYMBOL(mtk_ecc_wait_done); +- +-int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config, +- u8 *data, u32 bytes) +-{ +- dma_addr_t addr; +- u32 len; +- int ret; +- +- addr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE); +- ret = dma_mapping_error(ecc->dev, addr); +- if (ret) { +- dev_err(ecc->dev, "dma mapping error\n"); +- return -EINVAL; +- } +- +- config->op = ECC_ENCODE; +- config->addr = addr; +- ret = mtk_ecc_enable(ecc, config); +- if (ret) { +- dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE); +- return ret; +- } +- +- ret = mtk_ecc_wait_done(ecc, ECC_ENCODE); +- if (ret) +- goto timeout; +- +- mtk_ecc_wait_idle(ecc, ECC_ENCODE); +- +- /* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */ +- len = (config->strength * ecc->caps->parity_bits + 7) >> 3; +- +- /* write the parity bytes generated by the ECC back to temp buffer */ +- __ioread32_copy(ecc->eccdata, +- ecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00], +- round_up(len, 4)); +- +- /* copy into possibly unaligned OOB region with actual length */ +- memcpy(data + bytes, ecc->eccdata, len); +-timeout: +- +- dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE); +- mtk_ecc_disable(ecc); +- +- return ret; +-} +-EXPORT_SYMBOL(mtk_ecc_encode); +- +-void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p) +-{ +- const u8 *ecc_strength = ecc->caps->ecc_strength; +- int i; +- +- for (i = 0; i < ecc->caps->num_ecc_strength; i++) { +- if (*p <= ecc_strength[i]) { +- if (!i) +- *p = ecc_strength[i]; +- else if (*p != ecc_strength[i]) +- *p = ecc_strength[i - 1]; +- return; +- } +- } +- +- *p = ecc_strength[ecc->caps->num_ecc_strength - 1]; +-} +-EXPORT_SYMBOL(mtk_ecc_adjust_strength); +- +-unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc) +-{ +- return ecc->caps->parity_bits; +-} +-EXPORT_SYMBOL(mtk_ecc_get_parity_bits); +- +-static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = { +- .err_mask = 0x3f, +- .err_shift = 8, +- .ecc_strength = ecc_strength_mt2701, +- .ecc_regs = mt2701_ecc_regs, +- .num_ecc_strength = 20, +- .ecc_mode_shift = 5, +- .parity_bits = 14, +- .pg_irq_sel = 0, +-}; +- +-static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = { +- .err_mask = 0x7f, +- .err_shift = 8, +- .ecc_strength = ecc_strength_mt2712, +- .ecc_regs = mt2712_ecc_regs, +- .num_ecc_strength = 23, +- .ecc_mode_shift = 5, +- .parity_bits = 14, +- .pg_irq_sel = 1, +-}; +- +-static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = { +- .err_mask = 0x1f, +- .err_shift = 5, +- .ecc_strength = ecc_strength_mt7622, +- .ecc_regs = mt7622_ecc_regs, +- .num_ecc_strength = 5, +- .ecc_mode_shift = 4, +- .parity_bits = 13, +- .pg_irq_sel = 0, +-}; +- +-static const struct of_device_id mtk_ecc_dt_match[] = { +- { +- .compatible = "mediatek,mt2701-ecc", +- .data = &mtk_ecc_caps_mt2701, +- }, { +- .compatible = "mediatek,mt2712-ecc", +- .data = &mtk_ecc_caps_mt2712, +- }, { +- .compatible = "mediatek,mt7622-ecc", +- .data = &mtk_ecc_caps_mt7622, +- }, +- {}, +-}; +- +-static int mtk_ecc_probe(struct platform_device *pdev) +-{ +- struct device *dev = &pdev->dev; +- struct mtk_ecc *ecc; +- struct resource *res; +- u32 max_eccdata_size; +- int irq, ret; +- +- ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL); +- if (!ecc) +- return -ENOMEM; +- +- ecc->caps = of_device_get_match_data(dev); +- +- max_eccdata_size = ecc->caps->num_ecc_strength - 1; +- max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size]; +- max_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3; +- max_eccdata_size = round_up(max_eccdata_size, 4); +- ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL); +- if (!ecc->eccdata) +- return -ENOMEM; +- +- res = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- ecc->regs = devm_ioremap_resource(dev, res); +- if (IS_ERR(ecc->regs)) +- return PTR_ERR(ecc->regs); +- +- ecc->clk = devm_clk_get(dev, NULL); +- if (IS_ERR(ecc->clk)) { +- dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(ecc->clk)); +- return PTR_ERR(ecc->clk); +- } +- +- irq = platform_get_irq(pdev, 0); +- if (irq < 0) +- return irq; +- +- ret = dma_set_mask(dev, DMA_BIT_MASK(32)); +- if (ret) { +- dev_err(dev, "failed to set DMA mask\n"); +- return ret; +- } +- +- ret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, "mtk-ecc", ecc); +- if (ret) { +- dev_err(dev, "failed to request irq\n"); +- return -EINVAL; +- } +- +- ecc->dev = dev; +- mutex_init(&ecc->lock); +- platform_set_drvdata(pdev, ecc); +- dev_info(dev, "probed\n"); +- +- return 0; +-} +- +-#ifdef CONFIG_PM_SLEEP +-static int mtk_ecc_suspend(struct device *dev) +-{ +- struct mtk_ecc *ecc = dev_get_drvdata(dev); +- +- clk_disable_unprepare(ecc->clk); +- +- return 0; +-} +- +-static int mtk_ecc_resume(struct device *dev) +-{ +- struct mtk_ecc *ecc = dev_get_drvdata(dev); +- int ret; +- +- ret = clk_prepare_enable(ecc->clk); +- if (ret) { +- dev_err(dev, "failed to enable clk\n"); +- return ret; +- } +- +- return 0; +-} +- +-static SIMPLE_DEV_PM_OPS(mtk_ecc_pm_ops, mtk_ecc_suspend, mtk_ecc_resume); +-#endif +- +-MODULE_DEVICE_TABLE(of, mtk_ecc_dt_match); +- +-static struct platform_driver mtk_ecc_driver = { +- .probe = mtk_ecc_probe, +- .driver = { +- .name = "mtk-ecc", +- .of_match_table = of_match_ptr(mtk_ecc_dt_match), +-#ifdef CONFIG_PM_SLEEP +- .pm = &mtk_ecc_pm_ops, +-#endif +- }, +-}; +- +-module_platform_driver(mtk_ecc_driver); +- +-MODULE_AUTHOR("Xiaolei Li "); +-MODULE_DESCRIPTION("MTK Nand ECC Driver"); +-MODULE_LICENSE("Dual MIT/GPL"); +--- /dev/null ++++ b/drivers/mtd/nand/ecc-mtk.c +@@ -0,0 +1,598 @@ ++// SPDX-License-Identifier: GPL-2.0 OR MIT ++/* ++ * MTK ECC controller driver. ++ * Copyright (C) 2016 MediaTek Inc. ++ * Authors: Xiaolei Li ++ * Jorge Ramirez-Ortiz ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define ECC_IDLE_MASK BIT(0) ++#define ECC_IRQ_EN BIT(0) ++#define ECC_PG_IRQ_SEL BIT(1) ++#define ECC_OP_ENABLE (1) ++#define ECC_OP_DISABLE (0) ++ ++#define ECC_ENCCON (0x00) ++#define ECC_ENCCNFG (0x04) ++#define ECC_MS_SHIFT (16) ++#define ECC_ENCDIADDR (0x08) ++#define ECC_ENCIDLE (0x0C) ++#define ECC_DECCON (0x100) ++#define ECC_DECCNFG (0x104) ++#define DEC_EMPTY_EN BIT(31) ++#define DEC_CNFG_CORRECT (0x3 << 12) ++#define ECC_DECIDLE (0x10C) ++#define ECC_DECENUM0 (0x114) ++ ++#define ECC_TIMEOUT (500000) ++ ++#define ECC_IDLE_REG(op) ((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE) ++#define ECC_CTL_REG(op) ((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON) ++ ++struct mtk_ecc_caps { ++ u32 err_mask; ++ u32 err_shift; ++ const u8 *ecc_strength; ++ const u32 *ecc_regs; ++ u8 num_ecc_strength; ++ u8 ecc_mode_shift; ++ u32 parity_bits; ++ int pg_irq_sel; ++}; ++ ++struct mtk_ecc { ++ struct device *dev; ++ const struct mtk_ecc_caps *caps; ++ void __iomem *regs; ++ struct clk *clk; ++ ++ struct completion done; ++ struct mutex lock; ++ u32 sectors; ++ ++ u8 *eccdata; ++}; ++ ++/* ecc strength that each IP supports */ ++static const u8 ecc_strength_mt2701[] = { ++ 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, ++ 40, 44, 48, 52, 56, 60 ++}; ++ ++static const u8 ecc_strength_mt2712[] = { ++ 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, ++ 40, 44, 48, 52, 56, 60, 68, 72, 80 ++}; ++ ++static const u8 ecc_strength_mt7622[] = { ++ 4, 6, 8, 10, 12 ++}; ++ ++enum mtk_ecc_regs { ++ ECC_ENCPAR00, ++ ECC_ENCIRQ_EN, ++ ECC_ENCIRQ_STA, ++ ECC_DECDONE, ++ ECC_DECIRQ_EN, ++ ECC_DECIRQ_STA, ++}; ++ ++static int mt2701_ecc_regs[] = { ++ [ECC_ENCPAR00] = 0x10, ++ [ECC_ENCIRQ_EN] = 0x80, ++ [ECC_ENCIRQ_STA] = 0x84, ++ [ECC_DECDONE] = 0x124, ++ [ECC_DECIRQ_EN] = 0x200, ++ [ECC_DECIRQ_STA] = 0x204, ++}; ++ ++static int mt2712_ecc_regs[] = { ++ [ECC_ENCPAR00] = 0x300, ++ [ECC_ENCIRQ_EN] = 0x80, ++ [ECC_ENCIRQ_STA] = 0x84, ++ [ECC_DECDONE] = 0x124, ++ [ECC_DECIRQ_EN] = 0x200, ++ [ECC_DECIRQ_STA] = 0x204, ++}; ++ ++static int mt7622_ecc_regs[] = { ++ [ECC_ENCPAR00] = 0x10, ++ [ECC_ENCIRQ_EN] = 0x30, ++ [ECC_ENCIRQ_STA] = 0x34, ++ [ECC_DECDONE] = 0x11c, ++ [ECC_DECIRQ_EN] = 0x140, ++ [ECC_DECIRQ_STA] = 0x144, ++}; ++ ++static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc, ++ enum mtk_ecc_operation op) ++{ ++ struct device *dev = ecc->dev; ++ u32 val; ++ int ret; ++ ++ ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val, ++ val & ECC_IDLE_MASK, ++ 10, ECC_TIMEOUT); ++ if (ret) ++ dev_warn(dev, "%s NOT idle\n", ++ op == ECC_ENCODE ? "encoder" : "decoder"); ++} ++ ++static irqreturn_t mtk_ecc_irq(int irq, void *id) ++{ ++ struct mtk_ecc *ecc = id; ++ u32 dec, enc; ++ ++ dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]) ++ & ECC_IRQ_EN; ++ if (dec) { ++ dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]); ++ if (dec & ecc->sectors) { ++ /* ++ * Clear decode IRQ status once again to ensure that ++ * there will be no extra IRQ. ++ */ ++ readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]); ++ ecc->sectors = 0; ++ complete(&ecc->done); ++ } else { ++ return IRQ_HANDLED; ++ } ++ } else { ++ enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA]) ++ & ECC_IRQ_EN; ++ if (enc) ++ complete(&ecc->done); ++ else ++ return IRQ_NONE; ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config) ++{ ++ u32 ecc_bit, dec_sz, enc_sz; ++ u32 reg, i; ++ ++ for (i = 0; i < ecc->caps->num_ecc_strength; i++) { ++ if (ecc->caps->ecc_strength[i] == config->strength) ++ break; ++ } ++ ++ if (i == ecc->caps->num_ecc_strength) { ++ dev_err(ecc->dev, "invalid ecc strength %d\n", ++ config->strength); ++ return -EINVAL; ++ } ++ ++ ecc_bit = i; ++ ++ if (config->op == ECC_ENCODE) { ++ /* configure ECC encoder (in bits) */ ++ enc_sz = config->len << 3; ++ ++ reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift); ++ reg |= (enc_sz << ECC_MS_SHIFT); ++ writel(reg, ecc->regs + ECC_ENCCNFG); ++ ++ if (config->mode != ECC_NFI_MODE) ++ writel(lower_32_bits(config->addr), ++ ecc->regs + ECC_ENCDIADDR); ++ ++ } else { ++ /* configure ECC decoder (in bits) */ ++ dec_sz = (config->len << 3) + ++ config->strength * ecc->caps->parity_bits; ++ ++ reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift); ++ reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT; ++ reg |= DEC_EMPTY_EN; ++ writel(reg, ecc->regs + ECC_DECCNFG); ++ ++ if (config->sectors) ++ ecc->sectors = 1 << (config->sectors - 1); ++ } ++ ++ return 0; ++} ++ ++void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats, ++ int sectors) ++{ ++ u32 offset, i, err; ++ u32 bitflips = 0; ++ ++ stats->corrected = 0; ++ stats->failed = 0; ++ ++ for (i = 0; i < sectors; i++) { ++ offset = (i >> 2) << 2; ++ err = readl(ecc->regs + ECC_DECENUM0 + offset); ++ err = err >> ((i % 4) * ecc->caps->err_shift); ++ err &= ecc->caps->err_mask; ++ if (err == ecc->caps->err_mask) { ++ /* uncorrectable errors */ ++ stats->failed++; ++ continue; ++ } ++ ++ stats->corrected += err; ++ bitflips = max_t(u32, bitflips, err); ++ } ++ ++ stats->bitflips = bitflips; ++} ++EXPORT_SYMBOL(mtk_ecc_get_stats); ++ ++void mtk_ecc_release(struct mtk_ecc *ecc) ++{ ++ clk_disable_unprepare(ecc->clk); ++ put_device(ecc->dev); ++} ++EXPORT_SYMBOL(mtk_ecc_release); ++ ++static void mtk_ecc_hw_init(struct mtk_ecc *ecc) ++{ ++ mtk_ecc_wait_idle(ecc, ECC_ENCODE); ++ writew(ECC_OP_DISABLE, ecc->regs + ECC_ENCCON); ++ ++ mtk_ecc_wait_idle(ecc, ECC_DECODE); ++ writel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON); ++} ++ ++static struct mtk_ecc *mtk_ecc_get(struct device_node *np) ++{ ++ struct platform_device *pdev; ++ struct mtk_ecc *ecc; ++ ++ pdev = of_find_device_by_node(np); ++ if (!pdev) ++ return ERR_PTR(-EPROBE_DEFER); ++ ++ ecc = platform_get_drvdata(pdev); ++ if (!ecc) { ++ put_device(&pdev->dev); ++ return ERR_PTR(-EPROBE_DEFER); ++ } ++ ++ clk_prepare_enable(ecc->clk); ++ mtk_ecc_hw_init(ecc); ++ ++ return ecc; ++} ++ ++struct mtk_ecc *of_mtk_ecc_get(struct device_node *of_node) ++{ ++ struct mtk_ecc *ecc = NULL; ++ struct device_node *np; ++ ++ np = of_parse_phandle(of_node, "ecc-engine", 0); ++ if (np) { ++ ecc = mtk_ecc_get(np); ++ of_node_put(np); ++ } ++ ++ return ecc; ++} ++EXPORT_SYMBOL(of_mtk_ecc_get); ++ ++int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config) ++{ ++ enum mtk_ecc_operation op = config->op; ++ u16 reg_val; ++ int ret; ++ ++ ret = mutex_lock_interruptible(&ecc->lock); ++ if (ret) { ++ dev_err(ecc->dev, "interrupted when attempting to lock\n"); ++ return ret; ++ } ++ ++ mtk_ecc_wait_idle(ecc, op); ++ ++ ret = mtk_ecc_config(ecc, config); ++ if (ret) { ++ mutex_unlock(&ecc->lock); ++ return ret; ++ } ++ ++ if (config->mode != ECC_NFI_MODE || op != ECC_ENCODE) { ++ init_completion(&ecc->done); ++ reg_val = ECC_IRQ_EN; ++ /* ++ * For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it ++ * means this chip can only generate one ecc irq during page ++ * read / write. If is 0, generate one ecc irq each ecc step. ++ */ ++ if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE) ++ reg_val |= ECC_PG_IRQ_SEL; ++ if (op == ECC_ENCODE) ++ writew(reg_val, ecc->regs + ++ ecc->caps->ecc_regs[ECC_ENCIRQ_EN]); ++ else ++ writew(reg_val, ecc->regs + ++ ecc->caps->ecc_regs[ECC_DECIRQ_EN]); ++ } ++ ++ writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op)); ++ ++ return 0; ++} ++EXPORT_SYMBOL(mtk_ecc_enable); ++ ++void mtk_ecc_disable(struct mtk_ecc *ecc) ++{ ++ enum mtk_ecc_operation op = ECC_ENCODE; ++ ++ /* find out the running operation */ ++ if (readw(ecc->regs + ECC_CTL_REG(op)) != ECC_OP_ENABLE) ++ op = ECC_DECODE; ++ ++ /* disable it */ ++ mtk_ecc_wait_idle(ecc, op); ++ if (op == ECC_DECODE) { ++ /* ++ * Clear decode IRQ status in case there is a timeout to wait ++ * decode IRQ. ++ */ ++ readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]); ++ writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]); ++ } else { ++ writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]); ++ } ++ ++ writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op)); ++ ++ mutex_unlock(&ecc->lock); ++} ++EXPORT_SYMBOL(mtk_ecc_disable); ++ ++int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op) ++{ ++ int ret; ++ ++ ret = wait_for_completion_timeout(&ecc->done, msecs_to_jiffies(500)); ++ if (!ret) { ++ dev_err(ecc->dev, "%s timeout - interrupt did not arrive)\n", ++ (op == ECC_ENCODE) ? "encoder" : "decoder"); ++ return -ETIMEDOUT; ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL(mtk_ecc_wait_done); ++ ++int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config, ++ u8 *data, u32 bytes) ++{ ++ dma_addr_t addr; ++ u32 len; ++ int ret; ++ ++ addr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE); ++ ret = dma_mapping_error(ecc->dev, addr); ++ if (ret) { ++ dev_err(ecc->dev, "dma mapping error\n"); ++ return -EINVAL; ++ } ++ ++ config->op = ECC_ENCODE; ++ config->addr = addr; ++ ret = mtk_ecc_enable(ecc, config); ++ if (ret) { ++ dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE); ++ return ret; ++ } ++ ++ ret = mtk_ecc_wait_done(ecc, ECC_ENCODE); ++ if (ret) ++ goto timeout; ++ ++ mtk_ecc_wait_idle(ecc, ECC_ENCODE); ++ ++ /* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */ ++ len = (config->strength * ecc->caps->parity_bits + 7) >> 3; ++ ++ /* write the parity bytes generated by the ECC back to temp buffer */ ++ __ioread32_copy(ecc->eccdata, ++ ecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00], ++ round_up(len, 4)); ++ ++ /* copy into possibly unaligned OOB region with actual length */ ++ memcpy(data + bytes, ecc->eccdata, len); ++timeout: ++ ++ dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE); ++ mtk_ecc_disable(ecc); ++ ++ return ret; ++} ++EXPORT_SYMBOL(mtk_ecc_encode); ++ ++void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p) ++{ ++ const u8 *ecc_strength = ecc->caps->ecc_strength; ++ int i; ++ ++ for (i = 0; i < ecc->caps->num_ecc_strength; i++) { ++ if (*p <= ecc_strength[i]) { ++ if (!i) ++ *p = ecc_strength[i]; ++ else if (*p != ecc_strength[i]) ++ *p = ecc_strength[i - 1]; ++ return; ++ } ++ } ++ ++ *p = ecc_strength[ecc->caps->num_ecc_strength - 1]; ++} ++EXPORT_SYMBOL(mtk_ecc_adjust_strength); ++ ++unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc) ++{ ++ return ecc->caps->parity_bits; ++} ++EXPORT_SYMBOL(mtk_ecc_get_parity_bits); ++ ++static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = { ++ .err_mask = 0x3f, ++ .err_shift = 8, ++ .ecc_strength = ecc_strength_mt2701, ++ .ecc_regs = mt2701_ecc_regs, ++ .num_ecc_strength = 20, ++ .ecc_mode_shift = 5, ++ .parity_bits = 14, ++ .pg_irq_sel = 0, ++}; ++ ++static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = { ++ .err_mask = 0x7f, ++ .err_shift = 8, ++ .ecc_strength = ecc_strength_mt2712, ++ .ecc_regs = mt2712_ecc_regs, ++ .num_ecc_strength = 23, ++ .ecc_mode_shift = 5, ++ .parity_bits = 14, ++ .pg_irq_sel = 1, ++}; ++ ++static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = { ++ .err_mask = 0x1f, ++ .err_shift = 5, ++ .ecc_strength = ecc_strength_mt7622, ++ .ecc_regs = mt7622_ecc_regs, ++ .num_ecc_strength = 5, ++ .ecc_mode_shift = 4, ++ .parity_bits = 13, ++ .pg_irq_sel = 0, ++}; ++ ++static const struct of_device_id mtk_ecc_dt_match[] = { ++ { ++ .compatible = "mediatek,mt2701-ecc", ++ .data = &mtk_ecc_caps_mt2701, ++ }, { ++ .compatible = "mediatek,mt2712-ecc", ++ .data = &mtk_ecc_caps_mt2712, ++ }, { ++ .compatible = "mediatek,mt7622-ecc", ++ .data = &mtk_ecc_caps_mt7622, ++ }, ++ {}, ++}; ++ ++static int mtk_ecc_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct mtk_ecc *ecc; ++ struct resource *res; ++ u32 max_eccdata_size; ++ int irq, ret; ++ ++ ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL); ++ if (!ecc) ++ return -ENOMEM; ++ ++ ecc->caps = of_device_get_match_data(dev); ++ ++ max_eccdata_size = ecc->caps->num_ecc_strength - 1; ++ max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size]; ++ max_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3; ++ max_eccdata_size = round_up(max_eccdata_size, 4); ++ ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL); ++ if (!ecc->eccdata) ++ return -ENOMEM; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ecc->regs = devm_ioremap_resource(dev, res); ++ if (IS_ERR(ecc->regs)) ++ return PTR_ERR(ecc->regs); ++ ++ ecc->clk = devm_clk_get(dev, NULL); ++ if (IS_ERR(ecc->clk)) { ++ dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(ecc->clk)); ++ return PTR_ERR(ecc->clk); ++ } ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) ++ return irq; ++ ++ ret = dma_set_mask(dev, DMA_BIT_MASK(32)); ++ if (ret) { ++ dev_err(dev, "failed to set DMA mask\n"); ++ return ret; ++ } ++ ++ ret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, "mtk-ecc", ecc); ++ if (ret) { ++ dev_err(dev, "failed to request irq\n"); ++ return -EINVAL; ++ } ++ ++ ecc->dev = dev; ++ mutex_init(&ecc->lock); ++ platform_set_drvdata(pdev, ecc); ++ dev_info(dev, "probed\n"); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM_SLEEP ++static int mtk_ecc_suspend(struct device *dev) ++{ ++ struct mtk_ecc *ecc = dev_get_drvdata(dev); ++ ++ clk_disable_unprepare(ecc->clk); ++ ++ return 0; ++} ++ ++static int mtk_ecc_resume(struct device *dev) ++{ ++ struct mtk_ecc *ecc = dev_get_drvdata(dev); ++ int ret; ++ ++ ret = clk_prepare_enable(ecc->clk); ++ if (ret) { ++ dev_err(dev, "failed to enable clk\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static SIMPLE_DEV_PM_OPS(mtk_ecc_pm_ops, mtk_ecc_suspend, mtk_ecc_resume); ++#endif ++ ++MODULE_DEVICE_TABLE(of, mtk_ecc_dt_match); ++ ++static struct platform_driver mtk_ecc_driver = { ++ .probe = mtk_ecc_probe, ++ .driver = { ++ .name = "mtk-ecc", ++ .of_match_table = of_match_ptr(mtk_ecc_dt_match), ++#ifdef CONFIG_PM_SLEEP ++ .pm = &mtk_ecc_pm_ops, ++#endif ++ }, ++}; ++ ++module_platform_driver(mtk_ecc_driver); ++ ++MODULE_AUTHOR("Xiaolei Li "); ++MODULE_DESCRIPTION("MTK Nand ECC Driver"); ++MODULE_LICENSE("Dual MIT/GPL"); +--- a/drivers/mtd/nand/raw/Kconfig ++++ b/drivers/mtd/nand/raw/Kconfig +@@ -360,6 +360,7 @@ config MTD_NAND_QCOM + + config MTD_NAND_MTK + tristate "MTK NAND controller" ++ depends on MTD_NAND_ECC_MEDIATEK + depends on ARCH_MEDIATEK || COMPILE_TEST + depends on HAS_IOMEM + help +--- a/drivers/mtd/nand/raw/Makefile ++++ b/drivers/mtd/nand/raw/Makefile +@@ -48,7 +48,7 @@ obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_n + obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o + obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/ + obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o +-obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o ++obj-$(CONFIG_MTD_NAND_MTK) += mtk_nand.o + obj-$(CONFIG_MTD_NAND_MXIC) += mxic_nand.o + obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o + obj-$(CONFIG_MTD_NAND_STM32_FMC2) += stm32_fmc2_nand.o +--- a/drivers/mtd/nand/raw/mtk_nand.c ++++ b/drivers/mtd/nand/raw/mtk_nand.c +@@ -17,7 +17,7 @@ + #include + #include + #include +-#include "mtk_ecc.h" ++#include + + /* NAND controller register definition */ + #define NFI_CNFG (0x00) +--- a/drivers/mtd/nand/raw/mtk_ecc.h ++++ /dev/null +@@ -1,47 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +-/* +- * MTK SDG1 ECC controller +- * +- * Copyright (c) 2016 Mediatek +- * Authors: Xiaolei Li +- * Jorge Ramirez-Ortiz +- */ +- +-#ifndef __DRIVERS_MTD_NAND_MTK_ECC_H__ +-#define __DRIVERS_MTD_NAND_MTK_ECC_H__ +- +-#include +- +-enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1}; +-enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE}; +- +-struct device_node; +-struct mtk_ecc; +- +-struct mtk_ecc_stats { +- u32 corrected; +- u32 bitflips; +- u32 failed; +-}; +- +-struct mtk_ecc_config { +- enum mtk_ecc_operation op; +- enum mtk_ecc_mode mode; +- dma_addr_t addr; +- u32 strength; +- u32 sectors; +- u32 len; +-}; +- +-int mtk_ecc_encode(struct mtk_ecc *, struct mtk_ecc_config *, u8 *, u32); +-void mtk_ecc_get_stats(struct mtk_ecc *, struct mtk_ecc_stats *, int); +-int mtk_ecc_wait_done(struct mtk_ecc *, enum mtk_ecc_operation); +-int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *); +-void mtk_ecc_disable(struct mtk_ecc *); +-void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p); +-unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc); +- +-struct mtk_ecc *of_mtk_ecc_get(struct device_node *); +-void mtk_ecc_release(struct mtk_ecc *); +- +-#endif +--- /dev/null ++++ b/include/linux/mtd/nand-ecc-mtk.h +@@ -0,0 +1,47 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR MIT */ ++/* ++ * MTK SDG1 ECC controller ++ * ++ * Copyright (c) 2016 Mediatek ++ * Authors: Xiaolei Li ++ * Jorge Ramirez-Ortiz ++ */ ++ ++#ifndef __DRIVERS_MTD_NAND_MTK_ECC_H__ ++#define __DRIVERS_MTD_NAND_MTK_ECC_H__ ++ ++#include ++ ++enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1}; ++enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE}; ++ ++struct device_node; ++struct mtk_ecc; ++ ++struct mtk_ecc_stats { ++ u32 corrected; ++ u32 bitflips; ++ u32 failed; ++}; ++ ++struct mtk_ecc_config { ++ enum mtk_ecc_operation op; ++ enum mtk_ecc_mode mode; ++ dma_addr_t addr; ++ u32 strength; ++ u32 sectors; ++ u32 len; ++}; ++ ++int mtk_ecc_encode(struct mtk_ecc *, struct mtk_ecc_config *, u8 *, u32); ++void mtk_ecc_get_stats(struct mtk_ecc *, struct mtk_ecc_stats *, int); ++int mtk_ecc_wait_done(struct mtk_ecc *, enum mtk_ecc_operation); ++int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *); ++void mtk_ecc_disable(struct mtk_ecc *); ++void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p); ++unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc); ++ ++struct mtk_ecc *of_mtk_ecc_get(struct device_node *); ++void mtk_ecc_release(struct mtk_ecc *); ++ ++#endif diff --git a/target/linux/mediatek/patches-6.1/120-12-v5.19-spi-add-driver-for-MTK-SPI-NAND-Flash-Interface.patch b/target/linux/mediatek/patches-6.1/120-12-v5.19-spi-add-driver-for-MTK-SPI-NAND-Flash-Interface.patch new file mode 100644 index 00000000000..ed209050123 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/120-12-v5.19-spi-add-driver-for-MTK-SPI-NAND-Flash-Interface.patch @@ -0,0 +1,1537 @@ +From 8170bafa8936e9fbfdce992932a63bd20eca3bc3 Mon Sep 17 00:00:00 2001 +From: Chuanhong Guo +Date: Sat, 2 Apr 2022 10:16:11 +0800 +Subject: [PATCH v6 2/5] spi: add driver for MTK SPI NAND Flash Interface + +This driver implements support for the SPI-NAND mode of MTK NAND Flash +Interface as a SPI-MEM controller with pipelined ECC capability. + +Signed-off-by: Chuanhong Guo +Tested-by: Daniel Golle +--- +Change since v1: + fix CI warnings + +Changes since v2: + use streamed DMA api to avoid an extra memory copy during read + make ECC engine config a per-nand context + take user-requested ECC strength into account + +Change since v3: none +Changes since v4: + fix missing OOB write + print page format with dev_dbg + replace uint*_t copied from vendor driver with u* + +Changes since v5: + add missing nfi mode register configuration in probe + fix an off-by-one bug in mtk_snand_mac_io + + drivers/spi/Kconfig | 10 + + drivers/spi/Makefile | 1 + + drivers/spi/spi-mtk-snfi.c | 1470 ++++++++++++++++++++++++++++++++++++ + 3 files changed, 1481 insertions(+) + create mode 100644 drivers/spi/spi-mtk-snfi.c + +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -529,6 +529,16 @@ config SPI_MTK_NOR + SPI interface as well as several SPI NOR specific instructions + via SPI MEM interface. + ++config SPI_MTK_SNFI ++ tristate "MediaTek SPI NAND Flash Interface" ++ depends on ARCH_MEDIATEK || COMPILE_TEST ++ depends on MTD_NAND_ECC_MEDIATEK ++ help ++ This enables support for SPI-NAND mode on the MediaTek NAND ++ Flash Interface found on MediaTek ARM SoCs. This controller ++ is implemented as a SPI-MEM controller with pipelined ECC ++ capcability. ++ + config SPI_NPCM_FIU + tristate "Nuvoton NPCM FLASH Interface Unit" + depends on ARCH_NPCM || COMPILE_TEST +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -71,6 +71,7 @@ obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52x + obj-$(CONFIG_SPI_MT65XX) += spi-mt65xx.o + obj-$(CONFIG_SPI_MT7621) += spi-mt7621.o + obj-$(CONFIG_SPI_MTK_NOR) += spi-mtk-nor.o ++obj-$(CONFIG_SPI_MTK_SNFI) += spi-mtk-snfi.o + obj-$(CONFIG_SPI_MXIC) += spi-mxic.o + obj-$(CONFIG_SPI_MXS) += spi-mxs.o + obj-$(CONFIG_SPI_NPCM_FIU) += spi-npcm-fiu.o +--- /dev/null ++++ b/drivers/spi/spi-mtk-snfi.c +@@ -0,0 +1,1470 @@ ++// SPDX-License-Identifier: GPL-2.0 ++// ++// Driver for the SPI-NAND mode of Mediatek NAND Flash Interface ++// ++// Copyright (c) 2022 Chuanhong Guo ++// ++// This driver is based on the SPI-NAND mtd driver from Mediatek SDK: ++// ++// Copyright (C) 2020 MediaTek Inc. ++// Author: Weijie Gao ++// ++// This controller organize the page data as several interleaved sectors ++// like the following: (sizeof(FDM + ECC) = snf->nfi_cfg.spare_size) ++// +---------+------+------+---------+------+------+-----+ ++// | Sector1 | FDM1 | ECC1 | Sector2 | FDM2 | ECC2 | ... | ++// +---------+------+------+---------+------+------+-----+ ++// With auto-format turned on, DMA only returns this part: ++// +---------+---------+-----+ ++// | Sector1 | Sector2 | ... | ++// +---------+---------+-----+ ++// The FDM data will be filled to the registers, and ECC parity data isn't ++// accessible. ++// With auto-format off, all ((Sector+FDM+ECC)*nsectors) will be read over DMA ++// in it's original order shown in the first table. ECC can't be turned on when ++// auto-format is off. ++// ++// However, Linux SPI-NAND driver expects the data returned as: ++// +------+-----+ ++// | Page | OOB | ++// +------+-----+ ++// where the page data is continuously stored instead of interleaved. ++// So we assume all instructions matching the page_op template between ECC ++// prepare_io_req and finish_io_req are for page cache r/w. ++// Here's how this spi-mem driver operates when reading: ++// 1. Always set snf->autofmt = true in prepare_io_req (even when ECC is off). ++// 2. Perform page ops and let the controller fill the DMA bounce buffer with ++// de-interleaved sector data and set FDM registers. ++// 3. Return the data as: ++// +---------+---------+-----+------+------+-----+ ++// | Sector1 | Sector2 | ... | FDM1 | FDM2 | ... | ++// +---------+---------+-----+------+------+-----+ ++// 4. For other matching spi_mem ops outside a prepare/finish_io_req pair, ++// read the data with auto-format off into the bounce buffer and copy ++// needed data to the buffer specified in the request. ++// ++// Write requests operates in a similar manner. ++// As a limitation of this strategy, we won't be able to access any ECC parity ++// data at all in Linux. ++// ++// Here's the bad block mark situation on MTK chips: ++// In older chips like mt7622, MTK uses the first FDM byte in the first sector ++// as the bad block mark. After de-interleaving, this byte appears at [pagesize] ++// in the returned data, which is the BBM position expected by kernel. However, ++// the conventional bad block mark is the first byte of the OOB, which is part ++// of the last sector data in the interleaved layout. Instead of fixing their ++// hardware, MTK decided to address this inconsistency in software. On these ++// later chips, the BootROM expects the following: ++// 1. The [pagesize] byte on a nand page is used as BBM, which will appear at ++// (page_size - (nsectors - 1) * spare_size) in the DMA buffer. ++// 2. The original byte stored at that position in the DMA buffer will be stored ++// as the first byte of the FDM section in the last sector. ++// We can't disagree with the BootROM, so after de-interleaving, we need to ++// perform the following swaps in read: ++// 1. Store the BBM at [page_size - (nsectors - 1) * spare_size] to [page_size], ++// which is the expected BBM position by kernel. ++// 2. Store the page data byte at [pagesize + (nsectors-1) * fdm] back to ++// [page_size - (nsectors - 1) * spare_size] ++// Similarly, when writing, we need to perform swaps in the other direction. ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++// NFI registers ++#define NFI_CNFG 0x000 ++#define CNFG_OP_MODE_S 12 ++#define CNFG_OP_MODE_CUST 6 ++#define CNFG_OP_MODE_PROGRAM 3 ++#define CNFG_AUTO_FMT_EN BIT(9) ++#define CNFG_HW_ECC_EN BIT(8) ++#define CNFG_DMA_BURST_EN BIT(2) ++#define CNFG_READ_MODE BIT(1) ++#define CNFG_DMA_MODE BIT(0) ++ ++#define NFI_PAGEFMT 0x0004 ++#define NFI_SPARE_SIZE_LS_S 16 ++#define NFI_FDM_ECC_NUM_S 12 ++#define NFI_FDM_NUM_S 8 ++#define NFI_SPARE_SIZE_S 4 ++#define NFI_SEC_SEL_512 BIT(2) ++#define NFI_PAGE_SIZE_S 0 ++#define NFI_PAGE_SIZE_512_2K 0 ++#define NFI_PAGE_SIZE_2K_4K 1 ++#define NFI_PAGE_SIZE_4K_8K 2 ++#define NFI_PAGE_SIZE_8K_16K 3 ++ ++#define NFI_CON 0x008 ++#define CON_SEC_NUM_S 12 ++#define CON_BWR BIT(9) ++#define CON_BRD BIT(8) ++#define CON_NFI_RST BIT(1) ++#define CON_FIFO_FLUSH BIT(0) ++ ++#define NFI_INTR_EN 0x010 ++#define NFI_INTR_STA 0x014 ++#define NFI_IRQ_INTR_EN BIT(31) ++#define NFI_IRQ_CUS_READ BIT(8) ++#define NFI_IRQ_CUS_PG BIT(7) ++ ++#define NFI_CMD 0x020 ++#define NFI_CMD_DUMMY_READ 0x00 ++#define NFI_CMD_DUMMY_WRITE 0x80 ++ ++#define NFI_STRDATA 0x040 ++#define STR_DATA BIT(0) ++ ++#define NFI_STA 0x060 ++#define NFI_NAND_FSM GENMASK(28, 24) ++#define NFI_FSM GENMASK(19, 16) ++#define READ_EMPTY BIT(12) ++ ++#define NFI_FIFOSTA 0x064 ++#define FIFO_WR_REMAIN_S 8 ++#define FIFO_RD_REMAIN_S 0 ++ ++#define NFI_ADDRCNTR 0x070 ++#define SEC_CNTR GENMASK(16, 12) ++#define SEC_CNTR_S 12 ++#define NFI_SEC_CNTR(val) (((val)&SEC_CNTR) >> SEC_CNTR_S) ++ ++#define NFI_STRADDR 0x080 ++ ++#define NFI_BYTELEN 0x084 ++#define BUS_SEC_CNTR(val) (((val)&SEC_CNTR) >> SEC_CNTR_S) ++ ++#define NFI_FDM0L 0x0a0 ++#define NFI_FDM0M 0x0a4 ++#define NFI_FDML(n) (NFI_FDM0L + (n)*8) ++#define NFI_FDMM(n) (NFI_FDM0M + (n)*8) ++ ++#define NFI_DEBUG_CON1 0x220 ++#define WBUF_EN BIT(2) ++ ++#define NFI_MASTERSTA 0x224 ++#define MAS_ADDR GENMASK(11, 9) ++#define MAS_RD GENMASK(8, 6) ++#define MAS_WR GENMASK(5, 3) ++#define MAS_RDDLY GENMASK(2, 0) ++#define NFI_MASTERSTA_MASK_7622 (MAS_ADDR | MAS_RD | MAS_WR | MAS_RDDLY) ++ ++// SNFI registers ++#define SNF_MAC_CTL 0x500 ++#define MAC_XIO_SEL BIT(4) ++#define SF_MAC_EN BIT(3) ++#define SF_TRIG BIT(2) ++#define WIP_READY BIT(1) ++#define WIP BIT(0) ++ ++#define SNF_MAC_OUTL 0x504 ++#define SNF_MAC_INL 0x508 ++ ++#define SNF_RD_CTL2 0x510 ++#define DATA_READ_DUMMY_S 8 ++#define DATA_READ_MAX_DUMMY 0xf ++#define DATA_READ_CMD_S 0 ++ ++#define SNF_RD_CTL3 0x514 ++ ++#define SNF_PG_CTL1 0x524 ++#define PG_LOAD_CMD_S 8 ++ ++#define SNF_PG_CTL2 0x528 ++ ++#define SNF_MISC_CTL 0x538 ++#define SW_RST BIT(28) ++#define FIFO_RD_LTC_S 25 ++#define PG_LOAD_X4_EN BIT(20) ++#define DATA_READ_MODE_S 16 ++#define DATA_READ_MODE GENMASK(18, 16) ++#define DATA_READ_MODE_X1 0 ++#define DATA_READ_MODE_X2 1 ++#define DATA_READ_MODE_X4 2 ++#define DATA_READ_MODE_DUAL 5 ++#define DATA_READ_MODE_QUAD 6 ++#define PG_LOAD_CUSTOM_EN BIT(7) ++#define DATARD_CUSTOM_EN BIT(6) ++#define CS_DESELECT_CYC_S 0 ++ ++#define SNF_MISC_CTL2 0x53c ++#define PROGRAM_LOAD_BYTE_NUM_S 16 ++#define READ_DATA_BYTE_NUM_S 11 ++ ++#define SNF_DLY_CTL3 0x548 ++#define SFCK_SAM_DLY_S 0 ++ ++#define SNF_STA_CTL1 0x550 ++#define CUS_PG_DONE BIT(28) ++#define CUS_READ_DONE BIT(27) ++#define SPI_STATE_S 0 ++#define SPI_STATE GENMASK(3, 0) ++ ++#define SNF_CFG 0x55c ++#define SPI_MODE BIT(0) ++ ++#define SNF_GPRAM 0x800 ++#define SNF_GPRAM_SIZE 0xa0 ++ ++#define SNFI_POLL_INTERVAL 1000000 ++ ++static const u8 mt7622_spare_sizes[] = { 16, 26, 27, 28 }; ++ ++struct mtk_snand_caps { ++ u16 sector_size; ++ u16 max_sectors; ++ u16 fdm_size; ++ u16 fdm_ecc_size; ++ u16 fifo_size; ++ ++ bool bbm_swap; ++ bool empty_page_check; ++ u32 mastersta_mask; ++ ++ const u8 *spare_sizes; ++ u32 num_spare_size; ++}; ++ ++static const struct mtk_snand_caps mt7622_snand_caps = { ++ .sector_size = 512, ++ .max_sectors = 8, ++ .fdm_size = 8, ++ .fdm_ecc_size = 1, ++ .fifo_size = 32, ++ .bbm_swap = false, ++ .empty_page_check = false, ++ .mastersta_mask = NFI_MASTERSTA_MASK_7622, ++ .spare_sizes = mt7622_spare_sizes, ++ .num_spare_size = ARRAY_SIZE(mt7622_spare_sizes) ++}; ++ ++static const struct mtk_snand_caps mt7629_snand_caps = { ++ .sector_size = 512, ++ .max_sectors = 8, ++ .fdm_size = 8, ++ .fdm_ecc_size = 1, ++ .fifo_size = 32, ++ .bbm_swap = true, ++ .empty_page_check = false, ++ .mastersta_mask = NFI_MASTERSTA_MASK_7622, ++ .spare_sizes = mt7622_spare_sizes, ++ .num_spare_size = ARRAY_SIZE(mt7622_spare_sizes) ++}; ++ ++struct mtk_snand_conf { ++ size_t page_size; ++ size_t oob_size; ++ u8 nsectors; ++ u8 spare_size; ++}; ++ ++struct mtk_snand { ++ struct spi_controller *ctlr; ++ struct device *dev; ++ struct clk *nfi_clk; ++ struct clk *pad_clk; ++ void __iomem *nfi_base; ++ int irq; ++ struct completion op_done; ++ const struct mtk_snand_caps *caps; ++ struct mtk_ecc_config *ecc_cfg; ++ struct mtk_ecc *ecc; ++ struct mtk_snand_conf nfi_cfg; ++ struct mtk_ecc_stats ecc_stats; ++ struct nand_ecc_engine ecc_eng; ++ bool autofmt; ++ u8 *buf; ++ size_t buf_len; ++}; ++ ++static struct mtk_snand *nand_to_mtk_snand(struct nand_device *nand) ++{ ++ struct nand_ecc_engine *eng = nand->ecc.engine; ++ ++ return container_of(eng, struct mtk_snand, ecc_eng); ++} ++ ++static inline int snand_prepare_bouncebuf(struct mtk_snand *snf, size_t size) ++{ ++ if (snf->buf_len >= size) ++ return 0; ++ kfree(snf->buf); ++ snf->buf = kmalloc(size, GFP_KERNEL); ++ if (!snf->buf) ++ return -ENOMEM; ++ snf->buf_len = size; ++ memset(snf->buf, 0xff, snf->buf_len); ++ return 0; ++} ++ ++static inline u32 nfi_read32(struct mtk_snand *snf, u32 reg) ++{ ++ return readl(snf->nfi_base + reg); ++} ++ ++static inline void nfi_write32(struct mtk_snand *snf, u32 reg, u32 val) ++{ ++ writel(val, snf->nfi_base + reg); ++} ++ ++static inline void nfi_write16(struct mtk_snand *snf, u32 reg, u16 val) ++{ ++ writew(val, snf->nfi_base + reg); ++} ++ ++static inline void nfi_rmw32(struct mtk_snand *snf, u32 reg, u32 clr, u32 set) ++{ ++ u32 val; ++ ++ val = readl(snf->nfi_base + reg); ++ val &= ~clr; ++ val |= set; ++ writel(val, snf->nfi_base + reg); ++} ++ ++static void nfi_read_data(struct mtk_snand *snf, u32 reg, u8 *data, u32 len) ++{ ++ u32 i, val = 0, es = sizeof(u32); ++ ++ for (i = reg; i < reg + len; i++) { ++ if (i == reg || i % es == 0) ++ val = nfi_read32(snf, i & ~(es - 1)); ++ ++ *data++ = (u8)(val >> (8 * (i % es))); ++ } ++} ++ ++static int mtk_nfi_reset(struct mtk_snand *snf) ++{ ++ u32 val, fifo_mask; ++ int ret; ++ ++ nfi_write32(snf, NFI_CON, CON_FIFO_FLUSH | CON_NFI_RST); ++ ++ ret = readw_poll_timeout(snf->nfi_base + NFI_MASTERSTA, val, ++ !(val & snf->caps->mastersta_mask), 0, ++ SNFI_POLL_INTERVAL); ++ if (ret) { ++ dev_err(snf->dev, "NFI master is still busy after reset\n"); ++ return ret; ++ } ++ ++ ret = readl_poll_timeout(snf->nfi_base + NFI_STA, val, ++ !(val & (NFI_FSM | NFI_NAND_FSM)), 0, ++ SNFI_POLL_INTERVAL); ++ if (ret) { ++ dev_err(snf->dev, "Failed to reset NFI\n"); ++ return ret; ++ } ++ ++ fifo_mask = ((snf->caps->fifo_size - 1) << FIFO_RD_REMAIN_S) | ++ ((snf->caps->fifo_size - 1) << FIFO_WR_REMAIN_S); ++ ret = readw_poll_timeout(snf->nfi_base + NFI_FIFOSTA, val, ++ !(val & fifo_mask), 0, SNFI_POLL_INTERVAL); ++ if (ret) { ++ dev_err(snf->dev, "NFI FIFOs are not empty\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int mtk_snand_mac_reset(struct mtk_snand *snf) ++{ ++ int ret; ++ u32 val; ++ ++ nfi_rmw32(snf, SNF_MISC_CTL, 0, SW_RST); ++ ++ ret = readl_poll_timeout(snf->nfi_base + SNF_STA_CTL1, val, ++ !(val & SPI_STATE), 0, SNFI_POLL_INTERVAL); ++ if (ret) ++ dev_err(snf->dev, "Failed to reset SNFI MAC\n"); ++ ++ nfi_write32(snf, SNF_MISC_CTL, ++ (2 << FIFO_RD_LTC_S) | (10 << CS_DESELECT_CYC_S)); ++ ++ return ret; ++} ++ ++static int mtk_snand_mac_trigger(struct mtk_snand *snf, u32 outlen, u32 inlen) ++{ ++ int ret; ++ u32 val; ++ ++ nfi_write32(snf, SNF_MAC_CTL, SF_MAC_EN); ++ nfi_write32(snf, SNF_MAC_OUTL, outlen); ++ nfi_write32(snf, SNF_MAC_INL, inlen); ++ ++ nfi_write32(snf, SNF_MAC_CTL, SF_MAC_EN | SF_TRIG); ++ ++ ret = readl_poll_timeout(snf->nfi_base + SNF_MAC_CTL, val, ++ val & WIP_READY, 0, SNFI_POLL_INTERVAL); ++ if (ret) { ++ dev_err(snf->dev, "Timed out waiting for WIP_READY\n"); ++ goto cleanup; ++ } ++ ++ ret = readl_poll_timeout(snf->nfi_base + SNF_MAC_CTL, val, !(val & WIP), ++ 0, SNFI_POLL_INTERVAL); ++ if (ret) ++ dev_err(snf->dev, "Timed out waiting for WIP cleared\n"); ++ ++cleanup: ++ nfi_write32(snf, SNF_MAC_CTL, 0); ++ ++ return ret; ++} ++ ++static int mtk_snand_mac_io(struct mtk_snand *snf, const struct spi_mem_op *op) ++{ ++ u32 rx_len = 0; ++ u32 reg_offs = 0; ++ u32 val = 0; ++ const u8 *tx_buf = NULL; ++ u8 *rx_buf = NULL; ++ int i, ret; ++ u8 b; ++ ++ if (op->data.dir == SPI_MEM_DATA_IN) { ++ rx_len = op->data.nbytes; ++ rx_buf = op->data.buf.in; ++ } else { ++ tx_buf = op->data.buf.out; ++ } ++ ++ mtk_snand_mac_reset(snf); ++ ++ for (i = 0; i < op->cmd.nbytes; i++, reg_offs++) { ++ b = (op->cmd.opcode >> ((op->cmd.nbytes - i - 1) * 8)) & 0xff; ++ val |= b << (8 * (reg_offs % 4)); ++ if (reg_offs % 4 == 3) { ++ nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val); ++ val = 0; ++ } ++ } ++ ++ for (i = 0; i < op->addr.nbytes; i++, reg_offs++) { ++ b = (op->addr.val >> ((op->addr.nbytes - i - 1) * 8)) & 0xff; ++ val |= b << (8 * (reg_offs % 4)); ++ if (reg_offs % 4 == 3) { ++ nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val); ++ val = 0; ++ } ++ } ++ ++ for (i = 0; i < op->dummy.nbytes; i++, reg_offs++) { ++ if (reg_offs % 4 == 3) { ++ nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val); ++ val = 0; ++ } ++ } ++ ++ if (op->data.dir == SPI_MEM_DATA_OUT) { ++ for (i = 0; i < op->data.nbytes; i++, reg_offs++) { ++ val |= tx_buf[i] << (8 * (reg_offs % 4)); ++ if (reg_offs % 4 == 3) { ++ nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val); ++ val = 0; ++ } ++ } ++ } ++ ++ if (reg_offs % 4) ++ nfi_write32(snf, SNF_GPRAM + (reg_offs & ~3), val); ++ ++ for (i = 0; i < reg_offs; i += 4) ++ dev_dbg(snf->dev, "%d: %08X", i, ++ nfi_read32(snf, SNF_GPRAM + i)); ++ ++ dev_dbg(snf->dev, "SNF TX: %u RX: %u", reg_offs, rx_len); ++ ++ ret = mtk_snand_mac_trigger(snf, reg_offs, rx_len); ++ if (ret) ++ return ret; ++ ++ if (!rx_len) ++ return 0; ++ ++ nfi_read_data(snf, SNF_GPRAM + reg_offs, rx_buf, rx_len); ++ return 0; ++} ++ ++static int mtk_snand_setup_pagefmt(struct mtk_snand *snf, u32 page_size, ++ u32 oob_size) ++{ ++ int spare_idx = -1; ++ u32 spare_size, spare_size_shift, pagesize_idx; ++ u32 sector_size_512; ++ u8 nsectors; ++ int i; ++ ++ // skip if it's already configured as required. ++ if (snf->nfi_cfg.page_size == page_size && ++ snf->nfi_cfg.oob_size == oob_size) ++ return 0; ++ ++ nsectors = page_size / snf->caps->sector_size; ++ if (nsectors > snf->caps->max_sectors) { ++ dev_err(snf->dev, "too many sectors required.\n"); ++ goto err; ++ } ++ ++ if (snf->caps->sector_size == 512) { ++ sector_size_512 = NFI_SEC_SEL_512; ++ spare_size_shift = NFI_SPARE_SIZE_S; ++ } else { ++ sector_size_512 = 0; ++ spare_size_shift = NFI_SPARE_SIZE_LS_S; ++ } ++ ++ switch (page_size) { ++ case SZ_512: ++ pagesize_idx = NFI_PAGE_SIZE_512_2K; ++ break; ++ case SZ_2K: ++ if (snf->caps->sector_size == 512) ++ pagesize_idx = NFI_PAGE_SIZE_2K_4K; ++ else ++ pagesize_idx = NFI_PAGE_SIZE_512_2K; ++ break; ++ case SZ_4K: ++ if (snf->caps->sector_size == 512) ++ pagesize_idx = NFI_PAGE_SIZE_4K_8K; ++ else ++ pagesize_idx = NFI_PAGE_SIZE_2K_4K; ++ break; ++ case SZ_8K: ++ if (snf->caps->sector_size == 512) ++ pagesize_idx = NFI_PAGE_SIZE_8K_16K; ++ else ++ pagesize_idx = NFI_PAGE_SIZE_4K_8K; ++ break; ++ case SZ_16K: ++ pagesize_idx = NFI_PAGE_SIZE_8K_16K; ++ break; ++ default: ++ dev_err(snf->dev, "unsupported page size.\n"); ++ goto err; ++ } ++ ++ spare_size = oob_size / nsectors; ++ // If we're using the 1KB sector size, HW will automatically double the ++ // spare size. We should only use half of the value in this case. ++ if (snf->caps->sector_size == 1024) ++ spare_size /= 2; ++ ++ for (i = snf->caps->num_spare_size - 1; i >= 0; i--) { ++ if (snf->caps->spare_sizes[i] <= spare_size) { ++ spare_size = snf->caps->spare_sizes[i]; ++ if (snf->caps->sector_size == 1024) ++ spare_size *= 2; ++ spare_idx = i; ++ break; ++ } ++ } ++ ++ if (spare_idx < 0) { ++ dev_err(snf->dev, "unsupported spare size: %u\n", spare_size); ++ goto err; ++ } ++ ++ nfi_write32(snf, NFI_PAGEFMT, ++ (snf->caps->fdm_ecc_size << NFI_FDM_ECC_NUM_S) | ++ (snf->caps->fdm_size << NFI_FDM_NUM_S) | ++ (spare_idx << spare_size_shift) | ++ (pagesize_idx << NFI_PAGE_SIZE_S) | ++ sector_size_512); ++ ++ snf->nfi_cfg.page_size = page_size; ++ snf->nfi_cfg.oob_size = oob_size; ++ snf->nfi_cfg.nsectors = nsectors; ++ snf->nfi_cfg.spare_size = spare_size; ++ ++ dev_dbg(snf->dev, "page format: (%u + %u) * %u\n", ++ snf->caps->sector_size, spare_size, nsectors); ++ return snand_prepare_bouncebuf(snf, page_size + oob_size); ++err: ++ dev_err(snf->dev, "page size %u + %u is not supported\n", page_size, ++ oob_size); ++ return -EOPNOTSUPP; ++} ++ ++static int mtk_snand_ooblayout_ecc(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *oobecc) ++{ ++ // ECC area is not accessible ++ return -ERANGE; ++} ++ ++static int mtk_snand_ooblayout_free(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *oobfree) ++{ ++ struct nand_device *nand = mtd_to_nanddev(mtd); ++ struct mtk_snand *ms = nand_to_mtk_snand(nand); ++ ++ if (section >= ms->nfi_cfg.nsectors) ++ return -ERANGE; ++ ++ oobfree->length = ms->caps->fdm_size - 1; ++ oobfree->offset = section * ms->caps->fdm_size + 1; ++ return 0; ++} ++ ++static const struct mtd_ooblayout_ops mtk_snand_ooblayout = { ++ .ecc = mtk_snand_ooblayout_ecc, ++ .free = mtk_snand_ooblayout_free, ++}; ++ ++static int mtk_snand_ecc_init_ctx(struct nand_device *nand) ++{ ++ struct mtk_snand *snf = nand_to_mtk_snand(nand); ++ struct nand_ecc_props *conf = &nand->ecc.ctx.conf; ++ struct nand_ecc_props *reqs = &nand->ecc.requirements; ++ struct nand_ecc_props *user = &nand->ecc.user_conf; ++ struct mtd_info *mtd = nanddev_to_mtd(nand); ++ int step_size = 0, strength = 0, desired_correction = 0, steps; ++ bool ecc_user = false; ++ int ret; ++ u32 parity_bits, max_ecc_bytes; ++ struct mtk_ecc_config *ecc_cfg; ++ ++ ret = mtk_snand_setup_pagefmt(snf, nand->memorg.pagesize, ++ nand->memorg.oobsize); ++ if (ret) ++ return ret; ++ ++ ecc_cfg = kzalloc(sizeof(*ecc_cfg), GFP_KERNEL); ++ if (!ecc_cfg) ++ return -ENOMEM; ++ ++ nand->ecc.ctx.priv = ecc_cfg; ++ ++ if (user->step_size && user->strength) { ++ step_size = user->step_size; ++ strength = user->strength; ++ ecc_user = true; ++ } else if (reqs->step_size && reqs->strength) { ++ step_size = reqs->step_size; ++ strength = reqs->strength; ++ } ++ ++ if (step_size && strength) { ++ steps = mtd->writesize / step_size; ++ desired_correction = steps * strength; ++ strength = desired_correction / snf->nfi_cfg.nsectors; ++ } ++ ++ ecc_cfg->mode = ECC_NFI_MODE; ++ ecc_cfg->sectors = snf->nfi_cfg.nsectors; ++ ecc_cfg->len = snf->caps->sector_size + snf->caps->fdm_ecc_size; ++ ++ // calculate the max possible strength under current page format ++ parity_bits = mtk_ecc_get_parity_bits(snf->ecc); ++ max_ecc_bytes = snf->nfi_cfg.spare_size - snf->caps->fdm_size; ++ ecc_cfg->strength = max_ecc_bytes * 8 / parity_bits; ++ mtk_ecc_adjust_strength(snf->ecc, &ecc_cfg->strength); ++ ++ // if there's a user requested strength, find the minimum strength that ++ // meets the requirement. Otherwise use the maximum strength which is ++ // expected by BootROM. ++ if (ecc_user && strength) { ++ u32 s_next = ecc_cfg->strength - 1; ++ ++ while (1) { ++ mtk_ecc_adjust_strength(snf->ecc, &s_next); ++ if (s_next >= ecc_cfg->strength) ++ break; ++ if (s_next < strength) ++ break; ++ s_next = ecc_cfg->strength - 1; ++ } ++ } ++ ++ mtd_set_ooblayout(mtd, &mtk_snand_ooblayout); ++ ++ conf->step_size = snf->caps->sector_size; ++ conf->strength = ecc_cfg->strength; ++ ++ if (ecc_cfg->strength < strength) ++ dev_warn(snf->dev, "unable to fulfill ECC of %u bits.\n", ++ strength); ++ dev_info(snf->dev, "ECC strength: %u bits per %u bytes\n", ++ ecc_cfg->strength, snf->caps->sector_size); ++ ++ return 0; ++} ++ ++static void mtk_snand_ecc_cleanup_ctx(struct nand_device *nand) ++{ ++ struct mtk_ecc_config *ecc_cfg = nand_to_ecc_ctx(nand); ++ ++ kfree(ecc_cfg); ++} ++ ++static int mtk_snand_ecc_prepare_io_req(struct nand_device *nand, ++ struct nand_page_io_req *req) ++{ ++ struct mtk_snand *snf = nand_to_mtk_snand(nand); ++ struct mtk_ecc_config *ecc_cfg = nand_to_ecc_ctx(nand); ++ int ret; ++ ++ ret = mtk_snand_setup_pagefmt(snf, nand->memorg.pagesize, ++ nand->memorg.oobsize); ++ if (ret) ++ return ret; ++ snf->autofmt = true; ++ snf->ecc_cfg = ecc_cfg; ++ return 0; ++} ++ ++static int mtk_snand_ecc_finish_io_req(struct nand_device *nand, ++ struct nand_page_io_req *req) ++{ ++ struct mtk_snand *snf = nand_to_mtk_snand(nand); ++ struct mtd_info *mtd = nanddev_to_mtd(nand); ++ ++ snf->ecc_cfg = NULL; ++ snf->autofmt = false; ++ if ((req->mode == MTD_OPS_RAW) || (req->type != NAND_PAGE_READ)) ++ return 0; ++ ++ if (snf->ecc_stats.failed) ++ mtd->ecc_stats.failed += snf->ecc_stats.failed; ++ mtd->ecc_stats.corrected += snf->ecc_stats.corrected; ++ return snf->ecc_stats.failed ? -EBADMSG : snf->ecc_stats.bitflips; ++} ++ ++static struct nand_ecc_engine_ops mtk_snfi_ecc_engine_ops = { ++ .init_ctx = mtk_snand_ecc_init_ctx, ++ .cleanup_ctx = mtk_snand_ecc_cleanup_ctx, ++ .prepare_io_req = mtk_snand_ecc_prepare_io_req, ++ .finish_io_req = mtk_snand_ecc_finish_io_req, ++}; ++ ++static void mtk_snand_read_fdm(struct mtk_snand *snf, u8 *buf) ++{ ++ u32 vall, valm; ++ u8 *oobptr = buf; ++ int i, j; ++ ++ for (i = 0; i < snf->nfi_cfg.nsectors; i++) { ++ vall = nfi_read32(snf, NFI_FDML(i)); ++ valm = nfi_read32(snf, NFI_FDMM(i)); ++ ++ for (j = 0; j < snf->caps->fdm_size; j++) ++ oobptr[j] = (j >= 4 ? valm : vall) >> ((j % 4) * 8); ++ ++ oobptr += snf->caps->fdm_size; ++ } ++} ++ ++static void mtk_snand_write_fdm(struct mtk_snand *snf, const u8 *buf) ++{ ++ u32 fdm_size = snf->caps->fdm_size; ++ const u8 *oobptr = buf; ++ u32 vall, valm; ++ int i, j; ++ ++ for (i = 0; i < snf->nfi_cfg.nsectors; i++) { ++ vall = 0; ++ valm = 0; ++ ++ for (j = 0; j < 8; j++) { ++ if (j < 4) ++ vall |= (j < fdm_size ? oobptr[j] : 0xff) ++ << (j * 8); ++ else ++ valm |= (j < fdm_size ? oobptr[j] : 0xff) ++ << ((j - 4) * 8); ++ } ++ ++ nfi_write32(snf, NFI_FDML(i), vall); ++ nfi_write32(snf, NFI_FDMM(i), valm); ++ ++ oobptr += fdm_size; ++ } ++} ++ ++static void mtk_snand_bm_swap(struct mtk_snand *snf, u8 *buf) ++{ ++ u32 buf_bbm_pos, fdm_bbm_pos; ++ ++ if (!snf->caps->bbm_swap || snf->nfi_cfg.nsectors == 1) ++ return; ++ ++ // swap [pagesize] byte on nand with the first fdm byte ++ // in the last sector. ++ buf_bbm_pos = snf->nfi_cfg.page_size - ++ (snf->nfi_cfg.nsectors - 1) * snf->nfi_cfg.spare_size; ++ fdm_bbm_pos = snf->nfi_cfg.page_size + ++ (snf->nfi_cfg.nsectors - 1) * snf->caps->fdm_size; ++ ++ swap(snf->buf[fdm_bbm_pos], buf[buf_bbm_pos]); ++} ++ ++static void mtk_snand_fdm_bm_swap(struct mtk_snand *snf) ++{ ++ u32 fdm_bbm_pos1, fdm_bbm_pos2; ++ ++ if (!snf->caps->bbm_swap || snf->nfi_cfg.nsectors == 1) ++ return; ++ ++ // swap the first fdm byte in the first and the last sector. ++ fdm_bbm_pos1 = snf->nfi_cfg.page_size; ++ fdm_bbm_pos2 = snf->nfi_cfg.page_size + ++ (snf->nfi_cfg.nsectors - 1) * snf->caps->fdm_size; ++ swap(snf->buf[fdm_bbm_pos1], snf->buf[fdm_bbm_pos2]); ++} ++ ++static int mtk_snand_read_page_cache(struct mtk_snand *snf, ++ const struct spi_mem_op *op) ++{ ++ u8 *buf = snf->buf; ++ u8 *buf_fdm = buf + snf->nfi_cfg.page_size; ++ // the address part to be sent by the controller ++ u32 op_addr = op->addr.val; ++ // where to start copying data from bounce buffer ++ u32 rd_offset = 0; ++ u32 dummy_clk = (op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth); ++ u32 op_mode = 0; ++ u32 dma_len = snf->buf_len; ++ int ret = 0; ++ u32 rd_mode, rd_bytes, val; ++ dma_addr_t buf_dma; ++ ++ if (snf->autofmt) { ++ u32 last_bit; ++ u32 mask; ++ ++ dma_len = snf->nfi_cfg.page_size; ++ op_mode = CNFG_AUTO_FMT_EN; ++ if (op->data.ecc) ++ op_mode |= CNFG_HW_ECC_EN; ++ // extract the plane bit: ++ // Find the highest bit set in (pagesize+oobsize). ++ // Bits higher than that in op->addr are kept and sent over SPI ++ // Lower bits are used as an offset for copying data from DMA ++ // bounce buffer. ++ last_bit = fls(snf->nfi_cfg.page_size + snf->nfi_cfg.oob_size); ++ mask = (1 << last_bit) - 1; ++ rd_offset = op_addr & mask; ++ op_addr &= ~mask; ++ ++ // check if we can dma to the caller memory ++ if (rd_offset == 0 && op->data.nbytes >= snf->nfi_cfg.page_size) ++ buf = op->data.buf.in; ++ } ++ mtk_snand_mac_reset(snf); ++ mtk_nfi_reset(snf); ++ ++ // command and dummy cycles ++ nfi_write32(snf, SNF_RD_CTL2, ++ (dummy_clk << DATA_READ_DUMMY_S) | ++ (op->cmd.opcode << DATA_READ_CMD_S)); ++ ++ // read address ++ nfi_write32(snf, SNF_RD_CTL3, op_addr); ++ ++ // Set read op_mode ++ if (op->data.buswidth == 4) ++ rd_mode = op->addr.buswidth == 4 ? DATA_READ_MODE_QUAD : ++ DATA_READ_MODE_X4; ++ else if (op->data.buswidth == 2) ++ rd_mode = op->addr.buswidth == 2 ? DATA_READ_MODE_DUAL : ++ DATA_READ_MODE_X2; ++ else ++ rd_mode = DATA_READ_MODE_X1; ++ rd_mode <<= DATA_READ_MODE_S; ++ nfi_rmw32(snf, SNF_MISC_CTL, DATA_READ_MODE, ++ rd_mode | DATARD_CUSTOM_EN); ++ ++ // Set bytes to read ++ rd_bytes = (snf->nfi_cfg.spare_size + snf->caps->sector_size) * ++ snf->nfi_cfg.nsectors; ++ nfi_write32(snf, SNF_MISC_CTL2, ++ (rd_bytes << PROGRAM_LOAD_BYTE_NUM_S) | rd_bytes); ++ ++ // NFI read prepare ++ nfi_write16(snf, NFI_CNFG, ++ (CNFG_OP_MODE_CUST << CNFG_OP_MODE_S) | CNFG_DMA_BURST_EN | ++ CNFG_READ_MODE | CNFG_DMA_MODE | op_mode); ++ ++ nfi_write32(snf, NFI_CON, (snf->nfi_cfg.nsectors << CON_SEC_NUM_S)); ++ ++ buf_dma = dma_map_single(snf->dev, buf, dma_len, DMA_FROM_DEVICE); ++ if (dma_mapping_error(snf->dev, buf_dma)) { ++ dev_err(snf->dev, "DMA mapping failed.\n"); ++ goto cleanup; ++ } ++ nfi_write32(snf, NFI_STRADDR, buf_dma); ++ if (op->data.ecc) { ++ snf->ecc_cfg->op = ECC_DECODE; ++ ret = mtk_ecc_enable(snf->ecc, snf->ecc_cfg); ++ if (ret) ++ goto cleanup_dma; ++ } ++ // Prepare for custom read interrupt ++ nfi_write32(snf, NFI_INTR_EN, NFI_IRQ_INTR_EN | NFI_IRQ_CUS_READ); ++ reinit_completion(&snf->op_done); ++ ++ // Trigger NFI into custom mode ++ nfi_write16(snf, NFI_CMD, NFI_CMD_DUMMY_READ); ++ ++ // Start DMA read ++ nfi_rmw32(snf, NFI_CON, 0, CON_BRD); ++ nfi_write16(snf, NFI_STRDATA, STR_DATA); ++ ++ if (!wait_for_completion_timeout( ++ &snf->op_done, usecs_to_jiffies(SNFI_POLL_INTERVAL))) { ++ dev_err(snf->dev, "DMA timed out for reading from cache.\n"); ++ ret = -ETIMEDOUT; ++ goto cleanup; ++ } ++ ++ // Wait for BUS_SEC_CNTR returning expected value ++ ret = readl_poll_timeout(snf->nfi_base + NFI_BYTELEN, val, ++ BUS_SEC_CNTR(val) >= snf->nfi_cfg.nsectors, 0, ++ SNFI_POLL_INTERVAL); ++ if (ret) { ++ dev_err(snf->dev, "Timed out waiting for BUS_SEC_CNTR\n"); ++ goto cleanup2; ++ } ++ ++ // Wait for bus becoming idle ++ ret = readl_poll_timeout(snf->nfi_base + NFI_MASTERSTA, val, ++ !(val & snf->caps->mastersta_mask), 0, ++ SNFI_POLL_INTERVAL); ++ if (ret) { ++ dev_err(snf->dev, "Timed out waiting for bus becoming idle\n"); ++ goto cleanup2; ++ } ++ ++ if (op->data.ecc) { ++ ret = mtk_ecc_wait_done(snf->ecc, ECC_DECODE); ++ if (ret) { ++ dev_err(snf->dev, "wait ecc done timeout\n"); ++ goto cleanup2; ++ } ++ // save status before disabling ecc ++ mtk_ecc_get_stats(snf->ecc, &snf->ecc_stats, ++ snf->nfi_cfg.nsectors); ++ } ++ ++ dma_unmap_single(snf->dev, buf_dma, dma_len, DMA_FROM_DEVICE); ++ ++ if (snf->autofmt) { ++ mtk_snand_read_fdm(snf, buf_fdm); ++ if (snf->caps->bbm_swap) { ++ mtk_snand_bm_swap(snf, buf); ++ mtk_snand_fdm_bm_swap(snf); ++ } ++ } ++ ++ // copy data back ++ if (nfi_read32(snf, NFI_STA) & READ_EMPTY) { ++ memset(op->data.buf.in, 0xff, op->data.nbytes); ++ snf->ecc_stats.bitflips = 0; ++ snf->ecc_stats.failed = 0; ++ snf->ecc_stats.corrected = 0; ++ } else { ++ if (buf == op->data.buf.in) { ++ u32 cap_len = snf->buf_len - snf->nfi_cfg.page_size; ++ u32 req_left = op->data.nbytes - snf->nfi_cfg.page_size; ++ ++ if (req_left) ++ memcpy(op->data.buf.in + snf->nfi_cfg.page_size, ++ buf_fdm, ++ cap_len < req_left ? cap_len : req_left); ++ } else if (rd_offset < snf->buf_len) { ++ u32 cap_len = snf->buf_len - rd_offset; ++ ++ if (op->data.nbytes < cap_len) ++ cap_len = op->data.nbytes; ++ memcpy(op->data.buf.in, snf->buf + rd_offset, cap_len); ++ } ++ } ++cleanup2: ++ if (op->data.ecc) ++ mtk_ecc_disable(snf->ecc); ++cleanup_dma: ++ // unmap dma only if any error happens. (otherwise it's done before ++ // data copying) ++ if (ret) ++ dma_unmap_single(snf->dev, buf_dma, dma_len, DMA_FROM_DEVICE); ++cleanup: ++ // Stop read ++ nfi_write32(snf, NFI_CON, 0); ++ nfi_write16(snf, NFI_CNFG, 0); ++ ++ // Clear SNF done flag ++ nfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_READ_DONE); ++ nfi_write32(snf, SNF_STA_CTL1, 0); ++ ++ // Disable interrupt ++ nfi_read32(snf, NFI_INTR_STA); ++ nfi_write32(snf, NFI_INTR_EN, 0); ++ ++ nfi_rmw32(snf, SNF_MISC_CTL, DATARD_CUSTOM_EN, 0); ++ return ret; ++} ++ ++static int mtk_snand_write_page_cache(struct mtk_snand *snf, ++ const struct spi_mem_op *op) ++{ ++ // the address part to be sent by the controller ++ u32 op_addr = op->addr.val; ++ // where to start copying data from bounce buffer ++ u32 wr_offset = 0; ++ u32 op_mode = 0; ++ int ret = 0; ++ u32 wr_mode = 0; ++ u32 dma_len = snf->buf_len; ++ u32 wr_bytes, val; ++ size_t cap_len; ++ dma_addr_t buf_dma; ++ ++ if (snf->autofmt) { ++ u32 last_bit; ++ u32 mask; ++ ++ dma_len = snf->nfi_cfg.page_size; ++ op_mode = CNFG_AUTO_FMT_EN; ++ if (op->data.ecc) ++ op_mode |= CNFG_HW_ECC_EN; ++ ++ last_bit = fls(snf->nfi_cfg.page_size + snf->nfi_cfg.oob_size); ++ mask = (1 << last_bit) - 1; ++ wr_offset = op_addr & mask; ++ op_addr &= ~mask; ++ } ++ mtk_snand_mac_reset(snf); ++ mtk_nfi_reset(snf); ++ ++ if (wr_offset) ++ memset(snf->buf, 0xff, wr_offset); ++ ++ cap_len = snf->buf_len - wr_offset; ++ if (op->data.nbytes < cap_len) ++ cap_len = op->data.nbytes; ++ memcpy(snf->buf + wr_offset, op->data.buf.out, cap_len); ++ if (snf->autofmt) { ++ if (snf->caps->bbm_swap) { ++ mtk_snand_fdm_bm_swap(snf); ++ mtk_snand_bm_swap(snf, snf->buf); ++ } ++ mtk_snand_write_fdm(snf, snf->buf + snf->nfi_cfg.page_size); ++ } ++ ++ // Command ++ nfi_write32(snf, SNF_PG_CTL1, (op->cmd.opcode << PG_LOAD_CMD_S)); ++ ++ // write address ++ nfi_write32(snf, SNF_PG_CTL2, op_addr); ++ ++ // Set read op_mode ++ if (op->data.buswidth == 4) ++ wr_mode = PG_LOAD_X4_EN; ++ ++ nfi_rmw32(snf, SNF_MISC_CTL, PG_LOAD_X4_EN, ++ wr_mode | PG_LOAD_CUSTOM_EN); ++ ++ // Set bytes to write ++ wr_bytes = (snf->nfi_cfg.spare_size + snf->caps->sector_size) * ++ snf->nfi_cfg.nsectors; ++ nfi_write32(snf, SNF_MISC_CTL2, ++ (wr_bytes << PROGRAM_LOAD_BYTE_NUM_S) | wr_bytes); ++ ++ // NFI write prepare ++ nfi_write16(snf, NFI_CNFG, ++ (CNFG_OP_MODE_PROGRAM << CNFG_OP_MODE_S) | ++ CNFG_DMA_BURST_EN | CNFG_DMA_MODE | op_mode); ++ ++ nfi_write32(snf, NFI_CON, (snf->nfi_cfg.nsectors << CON_SEC_NUM_S)); ++ buf_dma = dma_map_single(snf->dev, snf->buf, dma_len, DMA_TO_DEVICE); ++ if (dma_mapping_error(snf->dev, buf_dma)) { ++ dev_err(snf->dev, "DMA mapping failed.\n"); ++ goto cleanup; ++ } ++ nfi_write32(snf, NFI_STRADDR, buf_dma); ++ if (op->data.ecc) { ++ snf->ecc_cfg->op = ECC_ENCODE; ++ ret = mtk_ecc_enable(snf->ecc, snf->ecc_cfg); ++ if (ret) ++ goto cleanup_dma; ++ } ++ // Prepare for custom write interrupt ++ nfi_write32(snf, NFI_INTR_EN, NFI_IRQ_INTR_EN | NFI_IRQ_CUS_PG); ++ reinit_completion(&snf->op_done); ++ ; ++ ++ // Trigger NFI into custom mode ++ nfi_write16(snf, NFI_CMD, NFI_CMD_DUMMY_WRITE); ++ ++ // Start DMA write ++ nfi_rmw32(snf, NFI_CON, 0, CON_BWR); ++ nfi_write16(snf, NFI_STRDATA, STR_DATA); ++ ++ if (!wait_for_completion_timeout( ++ &snf->op_done, usecs_to_jiffies(SNFI_POLL_INTERVAL))) { ++ dev_err(snf->dev, "DMA timed out for program load.\n"); ++ ret = -ETIMEDOUT; ++ goto cleanup_ecc; ++ } ++ ++ // Wait for NFI_SEC_CNTR returning expected value ++ ret = readl_poll_timeout(snf->nfi_base + NFI_ADDRCNTR, val, ++ NFI_SEC_CNTR(val) >= snf->nfi_cfg.nsectors, 0, ++ SNFI_POLL_INTERVAL); ++ if (ret) ++ dev_err(snf->dev, "Timed out waiting for NFI_SEC_CNTR\n"); ++ ++cleanup_ecc: ++ if (op->data.ecc) ++ mtk_ecc_disable(snf->ecc); ++cleanup_dma: ++ dma_unmap_single(snf->dev, buf_dma, dma_len, DMA_TO_DEVICE); ++cleanup: ++ // Stop write ++ nfi_write32(snf, NFI_CON, 0); ++ nfi_write16(snf, NFI_CNFG, 0); ++ ++ // Clear SNF done flag ++ nfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_PG_DONE); ++ nfi_write32(snf, SNF_STA_CTL1, 0); ++ ++ // Disable interrupt ++ nfi_read32(snf, NFI_INTR_STA); ++ nfi_write32(snf, NFI_INTR_EN, 0); ++ ++ nfi_rmw32(snf, SNF_MISC_CTL, PG_LOAD_CUSTOM_EN, 0); ++ ++ return ret; ++} ++ ++/** ++ * mtk_snand_is_page_ops() - check if the op is a controller supported page op. ++ * @op spi-mem op to check ++ * ++ * Check whether op can be executed with read_from_cache or program_load ++ * mode in the controller. ++ * This controller can execute typical Read From Cache and Program Load ++ * instructions found on SPI-NAND with 2-byte address. ++ * DTR and cmd buswidth & nbytes should be checked before calling this. ++ * ++ * Return: true if the op matches the instruction template ++ */ ++static bool mtk_snand_is_page_ops(const struct spi_mem_op *op) ++{ ++ if (op->addr.nbytes != 2) ++ return false; ++ ++ if (op->addr.buswidth != 1 && op->addr.buswidth != 2 && ++ op->addr.buswidth != 4) ++ return false; ++ ++ // match read from page instructions ++ if (op->data.dir == SPI_MEM_DATA_IN) { ++ // check dummy cycle first ++ if (op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth > ++ DATA_READ_MAX_DUMMY) ++ return false; ++ // quad io / quad out ++ if ((op->addr.buswidth == 4 || op->addr.buswidth == 1) && ++ op->data.buswidth == 4) ++ return true; ++ ++ // dual io / dual out ++ if ((op->addr.buswidth == 2 || op->addr.buswidth == 1) && ++ op->data.buswidth == 2) ++ return true; ++ ++ // standard spi ++ if (op->addr.buswidth == 1 && op->data.buswidth == 1) ++ return true; ++ } else if (op->data.dir == SPI_MEM_DATA_OUT) { ++ // check dummy cycle first ++ if (op->dummy.nbytes) ++ return false; ++ // program load quad out ++ if (op->addr.buswidth == 1 && op->data.buswidth == 4) ++ return true; ++ // standard spi ++ if (op->addr.buswidth == 1 && op->data.buswidth == 1) ++ return true; ++ } ++ return false; ++} ++ ++static bool mtk_snand_supports_op(struct spi_mem *mem, ++ const struct spi_mem_op *op) ++{ ++ if (!spi_mem_default_supports_op(mem, op)) ++ return false; ++ if (op->cmd.nbytes != 1 || op->cmd.buswidth != 1) ++ return false; ++ if (mtk_snand_is_page_ops(op)) ++ return true; ++ return ((op->addr.nbytes == 0 || op->addr.buswidth == 1) && ++ (op->dummy.nbytes == 0 || op->dummy.buswidth == 1) && ++ (op->data.nbytes == 0 || op->data.buswidth == 1)); ++} ++ ++static int mtk_snand_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) ++{ ++ struct mtk_snand *ms = spi_controller_get_devdata(mem->spi->master); ++ // page ops transfer size must be exactly ((sector_size + spare_size) * ++ // nsectors). Limit the op size if the caller requests more than that. ++ // exec_op will read more than needed and discard the leftover if the ++ // caller requests less data. ++ if (mtk_snand_is_page_ops(op)) { ++ size_t l; ++ // skip adjust_op_size for page ops ++ if (ms->autofmt) ++ return 0; ++ l = ms->caps->sector_size + ms->nfi_cfg.spare_size; ++ l *= ms->nfi_cfg.nsectors; ++ if (op->data.nbytes > l) ++ op->data.nbytes = l; ++ } else { ++ size_t hl = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes; ++ ++ if (hl >= SNF_GPRAM_SIZE) ++ return -EOPNOTSUPP; ++ if (op->data.nbytes > SNF_GPRAM_SIZE - hl) ++ op->data.nbytes = SNF_GPRAM_SIZE - hl; ++ } ++ return 0; ++} ++ ++static int mtk_snand_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) ++{ ++ struct mtk_snand *ms = spi_controller_get_devdata(mem->spi->master); ++ ++ dev_dbg(ms->dev, "OP %02x ADDR %08llX@%d:%u DATA %d:%u", op->cmd.opcode, ++ op->addr.val, op->addr.buswidth, op->addr.nbytes, ++ op->data.buswidth, op->data.nbytes); ++ if (mtk_snand_is_page_ops(op)) { ++ if (op->data.dir == SPI_MEM_DATA_IN) ++ return mtk_snand_read_page_cache(ms, op); ++ else ++ return mtk_snand_write_page_cache(ms, op); ++ } else { ++ return mtk_snand_mac_io(ms, op); ++ } ++} ++ ++static const struct spi_controller_mem_ops mtk_snand_mem_ops = { ++ .adjust_op_size = mtk_snand_adjust_op_size, ++ .supports_op = mtk_snand_supports_op, ++ .exec_op = mtk_snand_exec_op, ++}; ++ ++static const struct spi_controller_mem_caps mtk_snand_mem_caps = { ++ .ecc = true, ++}; ++ ++static irqreturn_t mtk_snand_irq(int irq, void *id) ++{ ++ struct mtk_snand *snf = id; ++ u32 sta, ien; ++ ++ sta = nfi_read32(snf, NFI_INTR_STA); ++ ien = nfi_read32(snf, NFI_INTR_EN); ++ ++ if (!(sta & ien)) ++ return IRQ_NONE; ++ ++ nfi_write32(snf, NFI_INTR_EN, 0); ++ complete(&snf->op_done); ++ return IRQ_HANDLED; ++} ++ ++static const struct of_device_id mtk_snand_ids[] = { ++ { .compatible = "mediatek,mt7622-snand", .data = &mt7622_snand_caps }, ++ { .compatible = "mediatek,mt7629-snand", .data = &mt7629_snand_caps }, ++ {}, ++}; ++ ++MODULE_DEVICE_TABLE(of, mtk_snand_ids); ++ ++static int mtk_snand_enable_clk(struct mtk_snand *ms) ++{ ++ int ret; ++ ++ ret = clk_prepare_enable(ms->nfi_clk); ++ if (ret) { ++ dev_err(ms->dev, "unable to enable nfi clk\n"); ++ return ret; ++ } ++ ret = clk_prepare_enable(ms->pad_clk); ++ if (ret) { ++ dev_err(ms->dev, "unable to enable pad clk\n"); ++ goto err1; ++ } ++ return 0; ++err1: ++ clk_disable_unprepare(ms->nfi_clk); ++ return ret; ++} ++ ++static void mtk_snand_disable_clk(struct mtk_snand *ms) ++{ ++ clk_disable_unprepare(ms->pad_clk); ++ clk_disable_unprepare(ms->nfi_clk); ++} ++ ++static int mtk_snand_probe(struct platform_device *pdev) ++{ ++ struct device_node *np = pdev->dev.of_node; ++ const struct of_device_id *dev_id; ++ struct spi_controller *ctlr; ++ struct mtk_snand *ms; ++ int ret; ++ ++ dev_id = of_match_node(mtk_snand_ids, np); ++ if (!dev_id) ++ return -EINVAL; ++ ++ ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*ms)); ++ if (!ctlr) ++ return -ENOMEM; ++ platform_set_drvdata(pdev, ctlr); ++ ++ ms = spi_controller_get_devdata(ctlr); ++ ++ ms->ctlr = ctlr; ++ ms->caps = dev_id->data; ++ ++ ms->ecc = of_mtk_ecc_get(np); ++ if (IS_ERR(ms->ecc)) ++ return PTR_ERR(ms->ecc); ++ else if (!ms->ecc) ++ return -ENODEV; ++ ++ ms->nfi_base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(ms->nfi_base)) { ++ ret = PTR_ERR(ms->nfi_base); ++ goto release_ecc; ++ } ++ ++ ms->dev = &pdev->dev; ++ ++ ms->nfi_clk = devm_clk_get(&pdev->dev, "nfi_clk"); ++ if (IS_ERR(ms->nfi_clk)) { ++ ret = PTR_ERR(ms->nfi_clk); ++ dev_err(&pdev->dev, "unable to get nfi_clk, err = %d\n", ret); ++ goto release_ecc; ++ } ++ ++ ms->pad_clk = devm_clk_get(&pdev->dev, "pad_clk"); ++ if (IS_ERR(ms->pad_clk)) { ++ ret = PTR_ERR(ms->pad_clk); ++ dev_err(&pdev->dev, "unable to get pad_clk, err = %d\n", ret); ++ goto release_ecc; ++ } ++ ++ ret = mtk_snand_enable_clk(ms); ++ if (ret) ++ goto release_ecc; ++ ++ init_completion(&ms->op_done); ++ ++ ms->irq = platform_get_irq(pdev, 0); ++ if (ms->irq < 0) { ++ ret = ms->irq; ++ goto disable_clk; ++ } ++ ret = devm_request_irq(ms->dev, ms->irq, mtk_snand_irq, 0x0, ++ "mtk-snand", ms); ++ if (ret) { ++ dev_err(ms->dev, "failed to request snfi irq\n"); ++ goto disable_clk; ++ } ++ ++ ret = dma_set_mask(ms->dev, DMA_BIT_MASK(32)); ++ if (ret) { ++ dev_err(ms->dev, "failed to set dma mask\n"); ++ goto disable_clk; ++ } ++ ++ // switch to SNFI mode ++ nfi_write32(ms, SNF_CFG, SPI_MODE); ++ ++ // setup an initial page format for ops matching page_cache_op template ++ // before ECC is called. ++ ret = mtk_snand_setup_pagefmt(ms, ms->caps->sector_size, ++ ms->caps->spare_sizes[0]); ++ if (ret) { ++ dev_err(ms->dev, "failed to set initial page format\n"); ++ goto disable_clk; ++ } ++ ++ // setup ECC engine ++ ms->ecc_eng.dev = &pdev->dev; ++ ms->ecc_eng.integration = NAND_ECC_ENGINE_INTEGRATION_PIPELINED; ++ ms->ecc_eng.ops = &mtk_snfi_ecc_engine_ops; ++ ms->ecc_eng.priv = ms; ++ ++ ret = nand_ecc_register_on_host_hw_engine(&ms->ecc_eng); ++ if (ret) { ++ dev_err(&pdev->dev, "failed to register ecc engine.\n"); ++ goto disable_clk; ++ } ++ ++ ctlr->num_chipselect = 1; ++ ctlr->mem_ops = &mtk_snand_mem_ops; ++ ctlr->mem_caps = &mtk_snand_mem_caps; ++ ctlr->bits_per_word_mask = SPI_BPW_MASK(8); ++ ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD; ++ ctlr->dev.of_node = pdev->dev.of_node; ++ ret = spi_register_controller(ctlr); ++ if (ret) { ++ dev_err(&pdev->dev, "spi_register_controller failed.\n"); ++ goto disable_clk; ++ } ++ ++ return 0; ++disable_clk: ++ mtk_snand_disable_clk(ms); ++release_ecc: ++ mtk_ecc_release(ms->ecc); ++ return ret; ++} ++ ++static int mtk_snand_remove(struct platform_device *pdev) ++{ ++ struct spi_controller *ctlr = platform_get_drvdata(pdev); ++ struct mtk_snand *ms = spi_controller_get_devdata(ctlr); ++ ++ spi_unregister_controller(ctlr); ++ mtk_snand_disable_clk(ms); ++ mtk_ecc_release(ms->ecc); ++ kfree(ms->buf); ++ return 0; ++} ++ ++static struct platform_driver mtk_snand_driver = { ++ .probe = mtk_snand_probe, ++ .remove = mtk_snand_remove, ++ .driver = { ++ .name = "mtk-snand", ++ .of_match_table = mtk_snand_ids, ++ }, ++}; ++ ++module_platform_driver(mtk_snand_driver); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Chuanhong Guo "); ++MODULE_DESCRIPTION("MeidaTek SPI-NAND Flash Controller Driver"); diff --git a/target/linux/mediatek/patches-6.1/120-13-v5.19-mtd-nand-mtk-ecc-also-parse-nand-ecc-engine-if-avail.patch b/target/linux/mediatek/patches-6.1/120-13-v5.19-mtd-nand-mtk-ecc-also-parse-nand-ecc-engine-if-avail.patch new file mode 100644 index 00000000000..01d9d12088c --- /dev/null +++ b/target/linux/mediatek/patches-6.1/120-13-v5.19-mtd-nand-mtk-ecc-also-parse-nand-ecc-engine-if-avail.patch @@ -0,0 +1,30 @@ +From 433b76fa0f3ca2865841abc21538dd8077ca3edd Mon Sep 17 00:00:00 2001 +From: Chuanhong Guo +Date: Mon, 4 Apr 2022 00:05:38 +0800 +Subject: [PATCH 13/15] mtd: nand: mtk-ecc: also parse nand-ecc-engine if + available + +The recently added ECC engine support introduced a generic property +named nand-ecc-engine for ecc engine phandle. This patch adds support +for this new property. + +Signed-off-by: Chuanhong Guo +(cherry picked from commit a41f25feb6e47c1c4d8d3279ae990ccbd8dfab54) +--- + drivers/mtd/nand/ecc-mtk.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +--- a/drivers/mtd/nand/ecc-mtk.c ++++ b/drivers/mtd/nand/ecc-mtk.c +@@ -279,7 +279,10 @@ struct mtk_ecc *of_mtk_ecc_get(struct de + struct mtk_ecc *ecc = NULL; + struct device_node *np; + +- np = of_parse_phandle(of_node, "ecc-engine", 0); ++ np = of_parse_phandle(of_node, "nand-ecc-engine", 0); ++ /* for backward compatibility */ ++ if (!np) ++ np = of_parse_phandle(of_node, "ecc-engine", 0); + if (np) { + ecc = mtk_ecc_get(np); + of_node_put(np); diff --git a/target/linux/mediatek/patches-6.1/120-14-v5.19-arm64-dts-mediatek-add-mtk-snfi-for-mt7622.patch b/target/linux/mediatek/patches-6.1/120-14-v5.19-arm64-dts-mediatek-add-mtk-snfi-for-mt7622.patch new file mode 100644 index 00000000000..15d26713723 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/120-14-v5.19-arm64-dts-mediatek-add-mtk-snfi-for-mt7622.patch @@ -0,0 +1,35 @@ +From 9ba7c246063ae43baf2e53ccc8c8b5f8d025aaaa Mon Sep 17 00:00:00 2001 +From: Chuanhong Guo +Date: Sun, 3 Apr 2022 10:19:29 +0800 +Subject: [PATCH 15/15] arm64: dts: mediatek: add mtk-snfi for mt7622 + +This patch adds a device-tree node for the MTK SPI-NAND Flash Interface +for MT7622 device tree. + +Signed-off-by: Chuanhong Guo +(cherry picked from commit 2e022641709011ef0843d0416b0f264b5fc217af) +--- + arch/arm64/boot/dts/mediatek/mt7622.dtsi | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -553,6 +553,18 @@ + status = "disabled"; + }; + ++ snfi: spi@1100d000 { ++ compatible = "mediatek,mt7622-snand"; ++ reg = <0 0x1100d000 0 0x1000>; ++ interrupts = ; ++ clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>; ++ clock-names = "nfi_clk", "pad_clk"; ++ nand-ecc-engine = <&bch>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + bch: ecc@1100e000 { + compatible = "mediatek,mt7622-ecc"; + reg = <0 0x1100e000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.1/121-hack-spi-nand-1b-bbm.patch b/target/linux/mediatek/patches-6.1/121-hack-spi-nand-1b-bbm.patch new file mode 100644 index 00000000000..ff5521c44ea --- /dev/null +++ b/target/linux/mediatek/patches-6.1/121-hack-spi-nand-1b-bbm.patch @@ -0,0 +1,20 @@ +--- a/drivers/mtd/nand/spi/core.c ++++ b/drivers/mtd/nand/spi/core.c +@@ -724,7 +724,7 @@ static int spinand_mtd_write(struct mtd_ + static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos) + { + struct spinand_device *spinand = nand_to_spinand(nand); +- u8 marker[2] = { }; ++ u8 marker[1] = { }; + struct nand_page_io_req req = { + .pos = *pos, + .ooblen = sizeof(marker), +@@ -735,7 +735,7 @@ static bool spinand_isbad(struct nand_de + + spinand_select_target(spinand, pos->target); + spinand_read_page(spinand, &req); +- if (marker[0] != 0xff || marker[1] != 0xff) ++ if (marker[0] != 0xff) + return true; + + return false; diff --git a/target/linux/mediatek/patches-6.1/130-dts-mt7629-add-snand-support.patch b/target/linux/mediatek/patches-6.1/130-dts-mt7629-add-snand-support.patch new file mode 100644 index 00000000000..be0018a3837 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/130-dts-mt7629-add-snand-support.patch @@ -0,0 +1,94 @@ +From c813fbe806257c574240770ef716fbee19f7dbfa Mon Sep 17 00:00:00 2001 +From: Xiangsheng Hou +Date: Thu, 6 Jun 2019 16:29:04 +0800 +Subject: [PATCH] spi: spi-mem: Mediatek: Add SPI Nand support for MT7629 + +Signed-off-by: Xiangsheng Hou +--- + arch/arm/boot/dts/mt7629-rfb.dts | 45 ++++++++++++++++++++++++++++++++ + arch/arm/boot/dts/mt7629.dtsi | 22 ++++++++++++++++ + 3 files changed, 79 insertions(+) + +--- a/arch/arm/boot/dts/mt7629.dtsi ++++ b/arch/arm/boot/dts/mt7629.dtsi +@@ -272,6 +272,27 @@ + status = "disabled"; + }; + ++ snfi: spi@1100d000 { ++ compatible = "mediatek,mt7629-snand"; ++ reg = <0x1100d000 0x1000>; ++ interrupts = ; ++ clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>; ++ clock-names = "nfi_clk", "pad_clk"; ++ nand-ecc-engine = <&bch>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ bch: ecc@1100e000 { ++ compatible = "mediatek,mt7622-ecc"; ++ reg = <0x1100e000 0x1000>; ++ interrupts = ; ++ clocks = <&pericfg CLK_PERI_NFIECC_PD>; ++ clock-names = "nfiecc_clk"; ++ status = "disabled"; ++ }; ++ + spi: spi@1100a000 { + compatible = "mediatek,mt7629-spi", + "mediatek,mt7622-spi"; +--- a/arch/arm/boot/dts/mt7629-rfb.dts ++++ b/arch/arm/boot/dts/mt7629-rfb.dts +@@ -254,6 +254,50 @@ + }; + }; + ++&bch { ++ status = "okay"; ++}; ++ ++&snfi { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&serial_nand_pins>; ++ status = "okay"; ++ flash@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-tx-bus-width = <4>; ++ spi-rx-bus-width = <4>; ++ nand-ecc-engine = <&snfi>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "Bootloader"; ++ reg = <0x00000 0x0100000>; ++ read-only; ++ }; ++ ++ partition@100000 { ++ label = "Config"; ++ reg = <0x100000 0x0040000>; ++ }; ++ ++ partition@140000 { ++ label = "factory"; ++ reg = <0x140000 0x0080000>; ++ }; ++ ++ partition@1c0000 { ++ label = "firmware"; ++ reg = <0x1c0000 0x1000000>; ++ }; ++ }; ++ }; ++}; ++ + &spi { + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins>; diff --git a/target/linux/mediatek/patches-6.1/131-dts-mt7622-add-snand-support.patch b/target/linux/mediatek/patches-6.1/131-dts-mt7622-add-snand-support.patch new file mode 100644 index 00000000000..134e5997e25 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/131-dts-mt7622-add-snand-support.patch @@ -0,0 +1,68 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +@@ -539,6 +539,65 @@ + status = "disabled"; + }; + ++&bch { ++ status = "okay"; ++}; ++ ++&snfi { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&serial_nand_pins>; ++ status = "okay"; ++ flash@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-tx-bus-width = <4>; ++ spi-rx-bus-width = <4>; ++ nand-ecc-engine = <&snfi>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "Preloader"; ++ reg = <0x00000 0x0080000>; ++ read-only; ++ }; ++ ++ partition@80000 { ++ label = "ATF"; ++ reg = <0x80000 0x0040000>; ++ }; ++ ++ partition@c0000 { ++ label = "Bootloader"; ++ reg = <0xc0000 0x0080000>; ++ }; ++ ++ partition@140000 { ++ label = "Config"; ++ reg = <0x140000 0x0080000>; ++ }; ++ ++ partition@1c0000 { ++ label = "Factory"; ++ reg = <0x1c0000 0x0100000>; ++ }; ++ ++ partition@200000 { ++ label = "firmware"; ++ reg = <0x2c0000 0x2000000>; ++ }; ++ ++ partition@2200000 { ++ label = "User_data"; ++ reg = <0x22c0000 0x4000000>; ++ }; ++ }; ++ }; ++}; ++ + &spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spic0_pins>; diff --git a/target/linux/mediatek/patches-6.1/140-dts-fix-wmac-support-for-mt7622-rfb1.patch b/target/linux/mediatek/patches-6.1/140-dts-fix-wmac-support-for-mt7622-rfb1.patch new file mode 100644 index 00000000000..8e6935b4344 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/140-dts-fix-wmac-support-for-mt7622-rfb1.patch @@ -0,0 +1,18 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +@@ -580,7 +580,7 @@ + reg = <0x140000 0x0080000>; + }; + +- partition@1c0000 { ++ factory: partition@1c0000 { + label = "Factory"; + reg = <0x1c0000 0x0100000>; + }; +@@ -641,5 +641,6 @@ + &wmac { + pinctrl-names = "default"; + pinctrl-0 = <&wmac_pins>; ++ mediatek,mtd-eeprom = <&factory 0x0000>; + status = "okay"; + }; diff --git a/target/linux/mediatek/patches-6.1/150-dts-mt7623-eip97-inside-secure-support.patch b/target/linux/mediatek/patches-6.1/150-dts-mt7623-eip97-inside-secure-support.patch new file mode 100644 index 00000000000..5b63bf4226b --- /dev/null +++ b/target/linux/mediatek/patches-6.1/150-dts-mt7623-eip97-inside-secure-support.patch @@ -0,0 +1,24 @@ +--- a/arch/arm/boot/dts/mt7623.dtsi ++++ b/arch/arm/boot/dts/mt7623.dtsi +@@ -951,17 +951,15 @@ + }; + + crypto: crypto@1b240000 { +- compatible = "mediatek,eip97-crypto"; ++ compatible = "inside-secure,safexcel-eip97"; + reg = <0 0x1b240000 0 0x20000>; + interrupts = , + , + , +- , +- ; ++ ; ++ interrupt-names = "ring0", "ring1", "ring2", "ring3"; + clocks = <ðsys CLK_ETHSYS_CRYPTO>; +- clock-names = "cryp"; +- power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; +- status = "disabled"; ++ status = "okay"; + }; + + bdpsys: syscon@1c000000 { diff --git a/target/linux/mediatek/patches-6.1/160-dts-mt7623-bpi-r2-earlycon.patch b/target/linux/mediatek/patches-6.1/160-dts-mt7623-bpi-r2-earlycon.patch new file mode 100644 index 00000000000..091cffc3c07 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/160-dts-mt7623-bpi-r2-earlycon.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts ++++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts +@@ -19,7 +19,7 @@ + + chosen { + stdout-path = "serial2:115200n8"; +- bootargs = "console=ttyS2,115200n8 console=tty1"; ++ bootargs = "earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1"; + }; + + connector { diff --git a/target/linux/mediatek/patches-6.1/161-dts-mt7623-bpi-r2-mmc-device-order.patch b/target/linux/mediatek/patches-6.1/161-dts-mt7623-bpi-r2-mmc-device-order.patch new file mode 100644 index 00000000000..d1bafc15260 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/161-dts-mt7623-bpi-r2-mmc-device-order.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts ++++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts +@@ -15,6 +15,8 @@ + + aliases { + serial2 = &uart2; ++ mmc0 = &mmc0; ++ mmc1 = &mmc1; + }; + + chosen { diff --git a/target/linux/mediatek/patches-6.1/162-dts-mt7623-bpi-r2-led-aliases.patch b/target/linux/mediatek/patches-6.1/162-dts-mt7623-bpi-r2-led-aliases.patch new file mode 100644 index 00000000000..f6745add5b3 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/162-dts-mt7623-bpi-r2-led-aliases.patch @@ -0,0 +1,29 @@ +--- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts ++++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts +@@ -17,6 +17,10 @@ + serial2 = &uart2; + mmc0 = &mmc0; + mmc1 = &mmc1; ++ led-boot = &led_system_green; ++ led-failsafe = &led_system_blue; ++ led-running = &led_system_green; ++ led-upgrade = &led_system_blue; + }; + + chosen { +@@ -112,13 +116,13 @@ + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_a>; + +- blue { ++ led_system_blue: blue { + label = "bpi-r2:pio:blue"; + gpios = <&pio 240 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + +- green { ++ led_system_green: green { + label = "bpi-r2:pio:green"; + gpios = <&pio 241 GPIO_ACTIVE_LOW>; + default-state = "off"; diff --git a/target/linux/mediatek/patches-6.1/163-dts-mt7623-bpi-r2-ethernet-alias.patch b/target/linux/mediatek/patches-6.1/163-dts-mt7623-bpi-r2-ethernet-alias.patch new file mode 100644 index 00000000000..b1dd75a4140 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/163-dts-mt7623-bpi-r2-ethernet-alias.patch @@ -0,0 +1,10 @@ +--- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts ++++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts +@@ -15,6 +15,7 @@ + + aliases { + serial2 = &uart2; ++ ethernet0 = &gmac0; + mmc0 = &mmc0; + mmc1 = &mmc1; + led-boot = &led_system_green; diff --git a/target/linux/mediatek/patches-6.1/173-arm-dts-mt7623-add-musb-device-nodes.patch b/target/linux/mediatek/patches-6.1/173-arm-dts-mt7623-add-musb-device-nodes.patch new file mode 100644 index 00000000000..ba1d1fe202b --- /dev/null +++ b/target/linux/mediatek/patches-6.1/173-arm-dts-mt7623-add-musb-device-nodes.patch @@ -0,0 +1,69 @@ +From 21d106f15262f5a2ef7531636e0703ee61c33c61 Mon Sep 17 00:00:00 2001 +From: Sungbo Eo +Date: Sun, 8 Aug 2021 21:38:40 +0900 +Subject: [PATCH 2/2] arm: dts: mt7623: add musb device nodes + +MT7623 has an musb controller that is compatible with the one from MT2701. + +Signed-off-by: Sungbo Eo +--- + arch/arm/boot/dts/mt7623.dtsi | 34 ++++++++++++++++++++++++++++++++++ + arch/arm/boot/dts/mt7623a.dtsi | 4 ++++ + 2 files changed, 38 insertions(+) + +--- a/arch/arm/boot/dts/mt7623.dtsi ++++ b/arch/arm/boot/dts/mt7623.dtsi +@@ -585,6 +585,40 @@ + status = "disabled"; + }; + ++ usb0: usb@11200000 { ++ compatible = "mediatek,mt7623-musb", ++ "mediatek,mtk-musb"; ++ reg = <0 0x11200000 0 0x1000>; ++ interrupts = ; ++ interrupt-names = "mc"; ++ phys = <&u2port2 PHY_TYPE_USB2>; ++ dr_mode = "otg"; ++ clocks = <&pericfg CLK_PERI_USB0>, ++ <&pericfg CLK_PERI_USB0_MCU>, ++ <&pericfg CLK_PERI_USB_SLV>; ++ clock-names = "main","mcu","univpll"; ++ power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; ++ status = "disabled"; ++ }; ++ ++ u2phy1: t-phy@11210000 { ++ compatible = "mediatek,mt7623-tphy", ++ "mediatek,generic-tphy-v1"; ++ reg = <0 0x11210000 0 0x0800>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ status = "disabled"; ++ ++ u2port2: usb-phy@11210800 { ++ reg = <0 0x11210800 0 0x0100>; ++ clocks = <&topckgen CLK_TOP_USB_PHY48M>; ++ clock-names = "ref"; ++ #phy-cells = <1>; ++ status = "okay"; ++ }; ++ }; ++ + audsys: clock-controller@11220000 { + compatible = "mediatek,mt7623-audsys", + "mediatek,mt2701-audsys", +--- a/arch/arm/boot/dts/mt7623a.dtsi ++++ b/arch/arm/boot/dts/mt7623a.dtsi +@@ -35,6 +35,10 @@ + clock-names = "ethif"; + }; + ++&usb0 { ++ power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>; ++}; ++ + &usb1 { + power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>; + }; diff --git a/target/linux/mediatek/patches-6.1/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch b/target/linux/mediatek/patches-6.1/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch new file mode 100644 index 00000000000..80ceb490d4e --- /dev/null +++ b/target/linux/mediatek/patches-6.1/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch @@ -0,0 +1,13 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +@@ -160,6 +160,10 @@ + switch@0 { + compatible = "mediatek,mt7531"; + reg = <0>; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ interrupt-parent = <&pio>; ++ interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; + reset-gpios = <&pio 54 0>; + + ports { diff --git a/target/linux/mediatek/patches-6.1/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch b/target/linux/mediatek/patches-6.1/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch new file mode 100644 index 00000000000..39a9770d98f --- /dev/null +++ b/target/linux/mediatek/patches-6.1/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch @@ -0,0 +1,106 @@ +From patchwork Tue Apr 26 19:51:36 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Daniel Golle +X-Patchwork-Id: 12827872 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from bombadil.infradead.org (bombadil.infradead.org + [198.137.202.133]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.lore.kernel.org (Postfix) with ESMTPS id BACF3C433EF + for ; + Tue, 26 Apr 2022 19:53:05 +0000 (UTC) +DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; + d=lists.infradead.org; s=bombadil.20210309; h=Sender: + Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: + List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Subject:Cc:To: + From:Date:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: + Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: + List-Owner; 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+ interrupt-parent = <&gic>; + reg = <0 0x10310000 0 0x1000>, +- <0 0x10320000 0 0x1000>, ++ <0 0x1032f000 0 0x2000>, + <0 0x10340000 0 0x2000>, + <0 0x10360000 0 0x2000>; + }; diff --git a/target/linux/mediatek/patches-6.1/191-v5.19-arm64-dts-mt7622-specify-the-L2-cache-topology.patch b/target/linux/mediatek/patches-6.1/191-v5.19-arm64-dts-mt7622-specify-the-L2-cache-topology.patch new file mode 100644 index 00000000000..8851fefbb3a --- /dev/null +++ b/target/linux/mediatek/patches-6.1/191-v5.19-arm64-dts-mt7622-specify-the-L2-cache-topology.patch @@ -0,0 +1,132 @@ +From patchwork Thu Apr 28 22:57:55 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Rui Salvaterra +X-Patchwork-Id: 12831311 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from bombadil.infradead.org (bombadil.infradead.org + [198.137.202.133]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.lore.kernel.org (Postfix) with ESMTPS id 49367C433EF + for ; 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+ Thu, 28 Apr 2022 15:58:06 -0700 (PDT) +From: Rui Salvaterra +To: linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, + linux-kernel@vger.kernel.org +Cc: matthias.bgg@gmail.com, ryder.lee@mediatek.com, daniel@makrotopia.org, + Rui Salvaterra +Subject: [PATCH] arm64: dts: mt7622: specify the L2 cache topology +Date: Thu, 28 Apr 2022 23:57:55 +0100 +Message-Id: <20220428225755.785153-1-rsalvaterra@gmail.com> +X-Mailer: git-send-email 2.36.0 +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220428_155811_895571_B63D2806 +X-CRM114-Status: GOOD ( 10.27 ) +X-BeenThere: linux-arm-kernel@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +List-Unsubscribe: + , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: + , + +Sender: "linux-arm-kernel" +Errors-To: + linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org + +On an MT7622 system, the kernel complains of not being able to detect the cache +hierarchy of CPU 0. Specify the shared L2 cache node in the device tree, in +order to fix this. + +Signed-off-by: Rui Salvaterra +--- + arch/arm64/boot/dts/mediatek/mt7622.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -80,6 +80,7 @@ + enable-method = "psci"; + clock-frequency = <1300000000>; + cci-control-port = <&cci_control2>; ++ next-level-cache = <&L2>; + }; + + cpu1: cpu@1 { +@@ -94,6 +95,12 @@ + enable-method = "psci"; + clock-frequency = <1300000000>; + cci-control-port = <&cci_control2>; ++ next-level-cache = <&L2>; ++ }; ++ ++ L2: l2-cache { ++ compatible = "cache"; ++ cache-level = <2>; + }; + }; + diff --git a/target/linux/mediatek/patches-6.1/192-v5.19-arm64-dts-mt7622-specify-the-number-of-DMA-requests.patch b/target/linux/mediatek/patches-6.1/192-v5.19-arm64-dts-mt7622-specify-the-number-of-DMA-requests.patch new file mode 100644 index 00000000000..4fef9aea22d --- /dev/null +++ b/target/linux/mediatek/patches-6.1/192-v5.19-arm64-dts-mt7622-specify-the-number-of-DMA-requests.patch @@ -0,0 +1,122 @@ +From patchwork Fri Apr 29 08:42:25 2022 +Content-Type: text/plain; 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+ Fri, 29 Apr 2022 01:42:32 -0700 (PDT) +Received: from crystalwell.adg.lan (a109-49-0-175.cpe.netcabo.pt. + [109.49.0.175]) by smtp.gmail.com with ESMTPSA id + el10-20020a170907284a00b006f3ef214e32sm429064ejc.152.2022.04.29.01.42.31 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Fri, 29 Apr 2022 01:42:31 -0700 (PDT) +From: Rui Salvaterra +To: linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, + linux-kernel@vger.kernel.org +Cc: matthias.bgg@gmail.com, ryder.lee@mediatek.com, daniel@makrotopia.org, + Rui Salvaterra +Subject: [PATCH] arm64: dts: mt7622: specify the number of DMA requests +Date: Fri, 29 Apr 2022 09:42:25 +0100 +Message-Id: <20220429084225.298213-1-rsalvaterra@gmail.com> +X-Mailer: git-send-email 2.36.0 +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220429_014236_944696_097D1E73 +X-CRM114-Status: UNSURE ( 8.85 ) +X-CRM114-Notice: Please train this message. +X-BeenThere: linux-arm-kernel@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +List-Unsubscribe: + , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: + , + +Sender: "linux-arm-kernel" +Errors-To: + linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org + +The MT7622 device tree never bothered to specify the number of virtual DMA +channels for the HSDMA controller, always falling back to the default value of +3. Make this value explicit, in order to avoid the following dmesg notification: + +mtk_hsdma 1b007000.dma-controller: Using 3 as missing dma-requests property + +Signed-off-by: Rui Salvaterra +--- + arch/arm64/boot/dts/mediatek/mt7622.dtsi | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -942,6 +942,7 @@ + clock-names = "hsdma"; + power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>; + #dma-cells = <1>; ++ dma-requests = <3>; + }; + + pcie_mirror: pcie-mirror@10000400 { diff --git a/target/linux/mediatek/patches-6.1/193-dts-mt7623-thermal_zone_fix.patch b/target/linux/mediatek/patches-6.1/193-dts-mt7623-thermal_zone_fix.patch new file mode 100644 index 00000000000..1cfb53d6208 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/193-dts-mt7623-thermal_zone_fix.patch @@ -0,0 +1,48 @@ +From 824d56e753a588fcfd650db1822e34a02a48bb77 Mon Sep 17 00:00:00 2001 +From: Bruno Umuarama +Date: Thu, 13 Oct 2022 21:18:21 +0000 +Subject: [PATCH] mediatek: mt7623: fix thermal zone +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Raising the temperatures for passive and active trips. @VA1DER +proposed at issue 9396 to remove passive trip. This commit relates to +his suggestion. + +Without this patch. the CPU will be throttled all the way down to 98MHz +if the temperature rises even a degree above the trip point, and it was +further discovered that if the internal temperature of the device is +above the first trip point temperature when it boots then it will start +in a throttled state and even +$ echo disabled > /sys/class/thermal/thermal_zone0/mode +will have no effect. + +The patch increases the passive trip point and active cooling map. The +throttling temperature will then be at 77°C and 82°C, which is still a +low enough temperature for ARM devices to not be in the real danger +zone, and gives some operational headroom. + +Signed-off-by: Bruno Umuarama +--- + arch/arm/boot/dts/mt7623.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm/boot/dts/mt7623.dtsi ++++ b/arch/arm/boot/dts/mt7623.dtsi +@@ -160,13 +160,13 @@ + + trips { + cpu_passive: cpu-passive { +- temperature = <57000>; ++ temperature = <77000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_active: cpu-active { +- temperature = <67000>; ++ temperature = <82000>; + hysteresis = <2000>; + type = "active"; + }; diff --git a/target/linux/mediatek/patches-6.1/194-dts-mt7968a-add-ramoops.patch b/target/linux/mediatek/patches-6.1/194-dts-mt7968a-add-ramoops.patch new file mode 100644 index 00000000000..161c1e75168 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/194-dts-mt7968a-add-ramoops.patch @@ -0,0 +1,17 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +@@ -68,6 +68,14 @@ + #address-cells = <2>; + #size-cells = <2>; + ranges; ++ ++ /* 64 KiB reserved for ramoops/pstore */ ++ ramoops@42ff0000 { ++ compatible = "ramoops"; ++ reg = <0 0x42ff0000 0 0x10000>; ++ record-size = <0x1000>; ++ }; ++ + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@43000000 { + reg = <0 0x43000000 0 0x30000>; diff --git a/target/linux/mediatek/patches-6.1/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch b/target/linux/mediatek/patches-6.1/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch new file mode 100644 index 00000000000..7126da788be --- /dev/null +++ b/target/linux/mediatek/patches-6.1/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch @@ -0,0 +1,196 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts +@@ -23,6 +23,10 @@ + serial0 = &uart0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; ++ led-boot = &green_led; ++ led-failsafe = &green_led; ++ led-running = &green_led; ++ led-upgrade = &blue_led; + }; + + chosen { +@@ -417,27 +421,27 @@ + + port@1 { + reg = <1>; +- label = "lan0"; ++ label = "lan1"; + }; + + port@2 { + reg = <2>; +- label = "lan1"; ++ label = "lan2"; + }; + + port@3 { + reg = <3>; +- label = "lan2"; ++ label = "lan3"; + }; + + port@4 { + reg = <4>; +- label = "lan3"; ++ label = "lan4"; + }; + + port5: port@5 { + reg = <5>; +- label = "lan4"; ++ label = "sfp2"; + phy-mode = "2500base-x"; + sfp = <&sfp2>; + managed = "in-band-status"; +@@ -488,9 +492,137 @@ + + &wifi { + status = "okay"; +- pinctrl-names = "default", "dbdc"; ++ pinctrl-names = "default"; + pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>; +- pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>; ++ ++ mediatek,eeprom-data = <0x86790900 0x000c4326 0x60000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x01000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000800 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x24649090 0x00280000 0x05100000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00021e00 0x021e0002 0x1e00021e 0x00022800 0x02280002 0x28000228 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00008080 0x8080fdf7 ++ 0x0903150d 0x80808080 0x80808080 0x05050d0d 0x1313c6c6 0xc3c3c200 0x00c200c2 0x00008182 ++ 0x8585c2c2 0x82828282 0x858500c2 0xc2000081 0x82858587 0x87c2c200 0x81818285 0x858787c2 ++ 0xc2000081 0x82858587 0x87c2c200 0x00818285 0x858787c2 0xc2000081 0x82858587 0x87c4c4c2 ++ 0xc100c300 0xc3c3c100 0x818383c3 0xc3c3c100 0x81838300 0xc2c2c2c0 0x81828484 0x000000c3 ++ 0xc3c3c100 0x81838386 0x86c3c3c3 0xc1008183 0x838686c2 0xc2c2c081 0x82848486 0x86c3c3c3 ++ 0xc1008183 0x838686c3 0xc3c3c100 0x81838386 0x86c3c3c3 0xc1008183 0x83868622 0x28002228 ++ 0x00222800 0x22280000 0xdddddddd 0xdddddddd 0xddbbbbbb 0xccccccdd 0xdddddddd 0xdddddddd ++ 0xeeeeeecc 0xccccdddd 0xdddddddd 0x004a5662 0x0000004a 0x56620000 0x004a5662 0x0000004a ++ 0x56620000 0x88888888 0x33333326 0x26262626 0x26262600 0x33333326 0x26262626 0x26262600 ++ 0x33333326 0x26262626 0x26262600 0x33333326 0x26262626 0x26262600 0x00000000 0xf0f0cc00 ++ 0x00000000 0x0000aaaa 0xaabbbbbb 0xcccccccc 0xccccbbbb 0xbbbbbbbb 0xbbbbbbaa 0xaaaabbbb ++ 0xbbaaaaaa 0x999999aa 0xaaaabbbb 0xbbcccccc 0x00000000 0x0000aaaa 0xaa000000 0xbbbbbbbb ++ 0xbbbbaaaa 0xaa999999 0xaaaaaaaa 0xaaaaaaaa 0xaaaaaaaa 0xaaaaaaaa 0xaaaabbbb 0xbbbbbbbb ++ 0x00000000 0x00000000 0x00000000 0x99999999 0x9999aaaa 0xaaaaaaaa 0x999999aa 0xaaaaaaaa ++ 0xaaaaaaaa 0xaaaaaaaa 0xaaaabbbb 0xbbbbbbbb 0x00000000 0x0000eeee 0xeeffffff 0xcccccccc ++ 0xccccdddd 0xddbbbbbb 0xccccccbb 0xbbbbbbbb 0xbbbbbbbb 0xbbbbbbbb 0xbbbbcccc 0xccdddddd ++ 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 ++ 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 ++ 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e ++ 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 ++ 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 ++ 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e ++ 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 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0x00000000 0x00000024 0xbe570000 0x00000000 0x000800f8 0xfe000600 ++ 0xf8fd0007 0x00f9fe00 0xf500f0f4 0x00000000 0x00000000 0x0000002d 0xd6610000 0x00000000 ++ 0x000400f7 0xfc000500 0xf7fc0005 0x00f7fc00 0xf900f5f8 0x00000000 0x00000000 0x00000026 ++ 0xd96e0000 0x00000000 0x000400f7 0xf9000600 0xf5f70005 0x00f5f800 0xf900f4f7 0x00000000 ++ 0x00000000 0x0000001b 0xce690000 0x00000000 0x000300f8 0xf8000600 0xf6f60004 0x00f6f700 ++ 0xf900f4f7 0x00000000 0x00000000 0x00000018 0xd8720000 0x00000000 0x00000000 0x02404002 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 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0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x000000a4 0xce000000 0x0000b684 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>; + + led { + led-active-low; +--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso +@@ -55,6 +55,7 @@ + partition@c00000 { + label = "fit"; + reg = <0xc00000 0x1400000>; ++ compatible = "denx,fit"; + }; + }; + }; diff --git a/target/linux/mediatek/patches-6.1/200-phy-phy-mtk-tphy-Add-hifsys-support.patch b/target/linux/mediatek/patches-6.1/200-phy-phy-mtk-tphy-Add-hifsys-support.patch new file mode 100644 index 00000000000..cfb0556d1ef --- /dev/null +++ b/target/linux/mediatek/patches-6.1/200-phy-phy-mtk-tphy-Add-hifsys-support.patch @@ -0,0 +1,66 @@ +From 28f9a5e2a3f5441ab5594669ed82da11e32277a9 Mon Sep 17 00:00:00 2001 +From: Kristian Evensen +Date: Mon, 30 Apr 2018 14:38:01 +0200 +Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support + +--- + drivers/phy/mediatek/phy-mtk-tphy.c | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +--- a/drivers/phy/mediatek/phy-mtk-tphy.c ++++ b/drivers/phy/mediatek/phy-mtk-tphy.c +@@ -18,6 +18,8 @@ + #include + #include + #include ++#include ++#include + + /* version V1 sub-banks offset base address */ + /* banks shared by multiple phys */ +@@ -311,6 +313,9 @@ + + #define TPHY_CLKS_CNT 2 + ++#define HIF_SYSCFG1 0x14 ++#define HIF_SYSCFG1_PHY2_MASK (0x3 << 20) ++ + enum mtk_phy_version { + MTK_PHY_V1 = 1, + MTK_PHY_V2, +@@ -377,6 +382,7 @@ struct mtk_tphy { + void __iomem *sif_base; /* only shared sif */ + const struct mtk_phy_pdata *pdata; + struct mtk_phy_instance **phys; ++ struct regmap *hif; + int nphys; + int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */ + int src_coef; /* coefficient for slew rate calibrate */ +@@ -730,6 +736,10 @@ static void pcie_phy_instance_init(struc + if (tphy->pdata->version != MTK_PHY_V1) + return; + ++ if (tphy->hif) ++ regmap_update_bits(tphy->hif, HIF_SYSCFG1, ++ HIF_SYSCFG1_PHY2_MASK, 0); ++ + tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0); + tmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H); + tmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2); +@@ -1437,6 +1447,16 @@ static int mtk_tphy_probe(struct platfor + &tphy->src_coef); + } + ++ if (of_find_property(np, "mediatek,phy-switch", NULL)) { ++ tphy->hif = syscon_regmap_lookup_by_phandle(np, ++ "mediatek,phy-switch"); ++ if (IS_ERR(tphy->hif)) { ++ dev_err(&pdev->dev, ++ "missing \"mediatek,phy-switch\" phandle\n"); ++ return PTR_ERR(tphy->hif); ++ } ++ } ++ + port = 0; + for_each_child_of_node(np, child_np) { + struct mtk_phy_instance *instance; diff --git a/target/linux/mediatek/patches-6.1/210-v6.1-pinctrl-mediatek-add-support-for-MT7986-SoC.patch b/target/linux/mediatek/patches-6.1/210-v6.1-pinctrl-mediatek-add-support-for-MT7986-SoC.patch new file mode 100644 index 00000000000..0761e1da180 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/210-v6.1-pinctrl-mediatek-add-support-for-MT7986-SoC.patch @@ -0,0 +1,26 @@ +--- a/drivers/pinctrl/mediatek/Kconfig ++++ b/drivers/pinctrl/mediatek/Kconfig +@@ -120,6 +120,13 @@ config PINCTRL_MT7622 + default ARM64 && ARCH_MEDIATEK + select PINCTRL_MTK_MOORE + ++config PINCTRL_MT7986 ++ bool "Mediatek MT7986 pin control" ++ depends on OF ++ depends on ARM64 || COMPILE_TEST ++ default ARM64 && ARCH_MEDIATEK ++ select PINCTRL_MTK_MOORE ++ + config PINCTRL_MT8167 + bool "Mediatek MT8167 pin control" + depends on OF +--- a/drivers/pinctrl/mediatek/Makefile ++++ b/drivers/pinctrl/mediatek/Makefile +@@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_MT6797) += pinctrl- + obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o + obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o + obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o ++obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o + obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o + obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o + obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o diff --git a/target/linux/mediatek/patches-6.1/211-v5.16-clk-mediatek-Add-API-for-clock-resource-recycle.patch b/target/linux/mediatek/patches-6.1/211-v5.16-clk-mediatek-Add-API-for-clock-resource-recycle.patch new file mode 100644 index 00000000000..15de8aa3d49 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/211-v5.16-clk-mediatek-Add-API-for-clock-resource-recycle.patch @@ -0,0 +1,28 @@ +--- a/drivers/clk/mediatek/clk-mtk.c ++++ b/drivers/clk/mediatek/clk-mtk.c +@@ -43,6 +43,15 @@ err_out: + return NULL; + } + ++void mtk_free_clk_data(struct clk_onecell_data *clk_data) ++{ ++ if (!clk_data) ++ return; ++ ++ kfree(clk_data->clks); ++ kfree(clk_data); ++} ++ + void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, + int num, struct clk_onecell_data *clk_data) + { +--- a/drivers/clk/mediatek/clk-mtk.h ++++ b/drivers/clk/mediatek/clk-mtk.h +@@ -202,6 +202,7 @@ void mtk_clk_register_dividers(const str + struct clk_onecell_data *clk_data); + + struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num); ++void mtk_free_clk_data(struct clk_onecell_data *clk_data); + + #define HAVE_RST_BAR BIT(0) + #define PLL_AO BIT(1) diff --git a/target/linux/mediatek/patches-6.1/212-v5.17-clk-mediatek-add-mt7986-clock-support.patch b/target/linux/mediatek/patches-6.1/212-v5.17-clk-mediatek-add-mt7986-clock-support.patch new file mode 100644 index 00000000000..8e2365a498e --- /dev/null +++ b/target/linux/mediatek/patches-6.1/212-v5.17-clk-mediatek-add-mt7986-clock-support.patch @@ -0,0 +1,39 @@ +--- a/drivers/clk/mediatek/Kconfig ++++ b/drivers/clk/mediatek/Kconfig +@@ -344,6 +344,23 @@ config COMMON_CLK_MT7629_HIFSYS + This driver supports MediaTek MT7629 HIFSYS clocks providing + to PCI-E and USB. + ++config COMMON_CLK_MT7986 ++ bool "Clock driver for MediaTek MT7986" ++ depends on ARCH_MEDIATEK || COMPILE_TEST ++ select COMMON_CLK_MEDIATEK ++ default ARCH_MEDIATEK ++ help ++ This driver supports MediaTek MT7986 basic clocks and clocks ++ required for various periperals found on MediaTek. ++ ++config COMMON_CLK_MT7986_ETHSYS ++ bool "Clock driver for MediaTek MT7986 ETHSYS" ++ depends on COMMON_CLK_MT7986 ++ default COMMON_CLK_MT7986 ++ help ++ This driver add support for clocks for Ethernet and SGMII ++ required on MediaTek MT7986 SoC. ++ + config COMMON_CLK_MT8135 + bool "Clock driver for MediaTek MT8135" + depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST +--- a/drivers/clk/mediatek/Makefile ++++ b/drivers/clk/mediatek/Makefile +@@ -46,6 +46,10 @@ obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) + + obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o + obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o + obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o ++obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-apmixed.o ++obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o ++obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o ++obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o + obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o + obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167.o + obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o diff --git a/target/linux/mediatek/patches-6.1/213-spi-mediatek-add-mt7986-spi-support.patch b/target/linux/mediatek/patches-6.1/213-spi-mediatek-add-mt7986-spi-support.patch new file mode 100644 index 00000000000..04da1765f37 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/213-spi-mediatek-add-mt7986-spi-support.patch @@ -0,0 +1,917 @@ +From 7d99750f96fc6904d54affebdc8c9b0bfae1e9e8 Mon Sep 17 00:00:00 2001 +From: Sam Shih +Date: Sun, 17 Apr 2022 11:40:22 +0800 +Subject: [PATCH] spi: mediatek: backport document and driver to support mt7986 + spi design + +this patch add the support of ipm design and upgrade devicetree binding + +The patch is comming from following threads +- https://lore.kernel.org/all/20220315032411.2826-1-leilk.liu@mediatek.com/ +- https://lore.kernel.org/all/20220401071616.8874-1-leilk.liu@mediatek.com/ + +Signed-off-by: Sam Shih +--- + .../bindings/spi/mediatek,spi-mt65xx.yaml | 111 ++++ + drivers/spi/spi-mt65xx.c | 509 ++++++++++++++++-- + 2 files changed, 572 insertions(+), 48 deletions(-) + create mode 100644 Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml + +--- /dev/null ++++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml +@@ -0,0 +1,111 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/spi/mediatek,spi-mt65xx.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: SPI Bus controller for MediaTek ARM SoCs ++ ++maintainers: ++ - Leilk Liu ++ ++allOf: ++ - $ref: "/schemas/spi/spi-controller.yaml#" ++ ++properties: ++ compatible: ++ oneOf: ++ - items: ++ - enum: ++ - mediatek,mt7629-spi ++ - const: mediatek,mt7622-spi ++ - items: ++ - enum: ++ - mediatek,mt8516-spi ++ - const: mediatek,mt2712-spi ++ - items: ++ - enum: ++ - mediatek,mt6779-spi ++ - mediatek,mt8186-spi ++ - mediatek,mt8192-spi ++ - mediatek,mt8195-spi ++ - const: mediatek,mt6765-spi ++ - items: ++ - enum: ++ - mediatek,mt7986-spi-ipm ++ - const: mediatek,spi-ipm ++ - items: ++ - enum: ++ - mediatek,mt2701-spi ++ - mediatek,mt2712-spi ++ - mediatek,mt6589-spi ++ - mediatek,mt6765-spi ++ - mediatek,mt6893-spi ++ - mediatek,mt7622-spi ++ - mediatek,mt8135-spi ++ - mediatek,mt8173-spi ++ - mediatek,mt8183-spi ++ ++ reg: ++ maxItems: 1 ++ ++ interrupts: ++ maxItems: 1 ++ ++ clocks: ++ minItems: 3 ++ items: ++ - description: clock used for the parent clock ++ - description: clock used for the muxes clock ++ - description: clock used for the clock gate ++ - description: clock used for the AHB bus, this clock is optional ++ ++ clock-names: ++ minItems: 3 ++ items: ++ - const: parent-clk ++ - const: sel-clk ++ - const: spi-clk ++ - const: hclk ++ ++ mediatek,pad-select: ++ $ref: /schemas/types.yaml#/definitions/uint32-array ++ minItems: 1 ++ maxItems: 4 ++ items: ++ enum: [0, 1, 2, 3] ++ description: ++ specify which pins group(ck/mi/mo/cs) spi controller used. ++ This is an array. ++ ++required: ++ - compatible ++ - reg ++ - interrupts ++ - clocks ++ - clock-names ++ - '#address-cells' ++ - '#size-cells' ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ #include ++ #include ++ ++ spi@1100a000 { ++ compatible = "mediatek,mt8173-spi"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x1100a000 0x1000>; ++ interrupts = ; ++ clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, ++ <&topckgen CLK_TOP_SPI_SEL>, ++ <&pericfg CLK_PERI_SPI0>; ++ clock-names = "parent-clk", "sel-clk", "spi-clk"; ++ cs-gpios = <&pio 105 GPIO_ACTIVE_LOW>, <&pio 72 GPIO_ACTIVE_LOW>; ++ mediatek,pad-select = <1>, <0>; ++ }; +--- a/drivers/spi/spi-mt65xx.c ++++ b/drivers/spi/spi-mt65xx.c +@@ -12,11 +12,12 @@ + #include + #include + #include +-#include ++#include + #include + #include + #include + #include ++#include + #include + + #define SPI_CFG0_REG 0x0000 +@@ -31,6 +32,7 @@ + #define SPI_CFG2_REG 0x0028 + #define SPI_TX_SRC_REG_64 0x002c + #define SPI_RX_DST_REG_64 0x0030 ++#define SPI_CFG3_IPM_REG 0x0040 + + #define SPI_CFG0_SCK_HIGH_OFFSET 0 + #define SPI_CFG0_SCK_LOW_OFFSET 8 +@@ -51,6 +53,7 @@ + #define SPI_CFG1_CS_IDLE_MASK 0xff + #define SPI_CFG1_PACKET_LOOP_MASK 0xff00 + #define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000 ++#define SPI_CFG1_IPM_PACKET_LENGTH_MASK GENMASK(31, 16) + #define SPI_CFG2_SCK_HIGH_OFFSET 0 + #define SPI_CFG2_SCK_LOW_OFFSET 16 + +@@ -71,6 +74,24 @@ + #define SPI_CMD_TX_ENDIAN BIT(15) + #define SPI_CMD_FINISH_IE BIT(16) + #define SPI_CMD_PAUSE_IE BIT(17) ++#define SPI_CMD_IPM_NONIDLE_MODE BIT(19) ++#define SPI_CMD_IPM_SPIM_LOOP BIT(21) ++#define SPI_CMD_IPM_GET_TICKDLY_OFFSET 22 ++ ++#define SPI_CMD_IPM_GET_TICKDLY_MASK GENMASK(24, 22) ++ ++#define PIN_MODE_CFG(x) ((x) / 2) ++ ++#define SPI_CFG3_IPM_HALF_DUPLEX_DIR BIT(2) ++#define SPI_CFG3_IPM_HALF_DUPLEX_EN BIT(3) ++#define SPI_CFG3_IPM_XMODE_EN BIT(4) ++#define SPI_CFG3_IPM_NODATA_FLAG BIT(5) ++#define SPI_CFG3_IPM_CMD_BYTELEN_OFFSET 8 ++#define SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET 12 ++ ++#define SPI_CFG3_IPM_CMD_PIN_MODE_MASK GENMASK(1, 0) ++#define SPI_CFG3_IPM_CMD_BYTELEN_MASK GENMASK(11, 8) ++#define SPI_CFG3_IPM_ADDR_BYTELEN_MASK GENMASK(15, 12) + + #define MT8173_SPI_MAX_PAD_SEL 3 + +@@ -81,6 +102,9 @@ + + #define MTK_SPI_MAX_FIFO_SIZE 32U + #define MTK_SPI_PACKET_SIZE 1024 ++#define MTK_SPI_IPM_PACKET_SIZE SZ_64K ++#define MTK_SPI_IPM_PACKET_LOOP SZ_256 ++ + #define MTK_SPI_32BITS_MASK (0xffffffff) + + #define DMA_ADDR_EXT_BITS (36) +@@ -96,6 +120,8 @@ struct mtk_spi_compatible { + bool dma_ext; + /* some IC no need unprepare SPI clk */ + bool no_need_unprepare; ++ /* IPM design adjust and extend register to support more features */ ++ bool ipm_design; + }; + + struct mtk_spi { +@@ -103,7 +129,7 @@ struct mtk_spi { + u32 state; + int pad_num; + u32 *pad_sel; +- struct clk *parent_clk, *sel_clk, *spi_clk; ++ struct clk *parent_clk, *sel_clk, *spi_clk, *spi_hclk; + struct spi_transfer *cur_transfer; + u32 xfer_len; + u32 num_xfered; +@@ -111,6 +137,11 @@ struct mtk_spi { + u32 tx_sgl_len, rx_sgl_len; + const struct mtk_spi_compatible *dev_comp; + u32 spi_clk_hz; ++ struct completion spimem_done; ++ bool use_spimem; ++ struct device *dev; ++ dma_addr_t tx_dma; ++ dma_addr_t rx_dma; + }; + + static const struct mtk_spi_compatible mtk_common_compat; +@@ -119,6 +150,12 @@ static const struct mtk_spi_compatible m + .must_tx = true, + }; + ++static const struct mtk_spi_compatible mtk_ipm_compat = { ++ .enhance_timing = true, ++ .dma_ext = true, ++ .ipm_design = true, ++}; ++ + static const struct mtk_spi_compatible mt6765_compat = { + .need_pad_sel = true, + .must_tx = true, +@@ -160,6 +197,9 @@ static const struct mtk_chip_config mtk_ + }; + + static const struct of_device_id mtk_spi_of_match[] = { ++ { .compatible = "mediatek,spi-ipm", ++ .data = (void *)&mtk_ipm_compat, ++ }, + { .compatible = "mediatek,mt2701-spi", + .data = (void *)&mtk_common_compat, + }, +@@ -278,12 +318,11 @@ static int mtk_spi_set_hw_cs_timing(stru + return 0; + } + +-static int mtk_spi_prepare_message(struct spi_master *master, +- struct spi_message *msg) ++static int mtk_spi_hw_init(struct spi_master *master, ++ struct spi_device *spi) + { + u16 cpha, cpol; + u32 reg_val; +- struct spi_device *spi = msg->spi; + struct mtk_chip_config *chip_config = spi->controller_data; + struct mtk_spi *mdata = spi_master_get_devdata(master); + +@@ -291,6 +330,15 @@ static int mtk_spi_prepare_message(struc + cpol = spi->mode & SPI_CPOL ? 1 : 0; + + reg_val = readl(mdata->base + SPI_CMD_REG); ++ if (mdata->dev_comp->ipm_design) { ++ /* SPI transfer without idle time until packet length done */ ++ reg_val |= SPI_CMD_IPM_NONIDLE_MODE; ++ if (spi->mode & SPI_LOOP) ++ reg_val |= SPI_CMD_IPM_SPIM_LOOP; ++ else ++ reg_val &= ~SPI_CMD_IPM_SPIM_LOOP; ++ } ++ + if (cpha) + reg_val |= SPI_CMD_CPHA; + else +@@ -348,23 +396,39 @@ static int mtk_spi_prepare_message(struc + mdata->base + SPI_PAD_SEL_REG); + + /* tick delay */ +- reg_val = readl(mdata->base + SPI_CFG1_REG); + if (mdata->dev_comp->enhance_timing) { +- reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK; +- reg_val |= ((chip_config->tick_delay & 0x7) +- << SPI_CFG1_GET_TICK_DLY_OFFSET); ++ if (mdata->dev_comp->ipm_design) { ++ reg_val = readl(mdata->base + SPI_CMD_REG); ++ reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK; ++ reg_val |= ((chip_config->tick_delay & 0x7) ++ << SPI_CMD_IPM_GET_TICKDLY_OFFSET); ++ writel(reg_val, mdata->base + SPI_CMD_REG); ++ } else { ++ reg_val = readl(mdata->base + SPI_CFG1_REG); ++ reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK; ++ reg_val |= ((chip_config->tick_delay & 0x7) ++ << SPI_CFG1_GET_TICK_DLY_OFFSET); ++ writel(reg_val, mdata->base + SPI_CFG1_REG); ++ } + } else { ++ reg_val = readl(mdata->base + SPI_CFG1_REG); + reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1; + reg_val |= ((chip_config->tick_delay & 0x3) + << SPI_CFG1_GET_TICK_DLY_OFFSET_V1); ++ writel(reg_val, mdata->base + SPI_CFG1_REG); + } +- writel(reg_val, mdata->base + SPI_CFG1_REG); + + /* set hw cs timing */ + mtk_spi_set_hw_cs_timing(spi); + return 0; + } + ++static int mtk_spi_prepare_message(struct spi_master *master, ++ struct spi_message *msg) ++{ ++ return mtk_spi_hw_init(master, msg->spi); ++} ++ + static void mtk_spi_set_cs(struct spi_device *spi, bool enable) + { + u32 reg_val; +@@ -386,13 +450,13 @@ static void mtk_spi_set_cs(struct spi_de + } + + static void mtk_spi_prepare_transfer(struct spi_master *master, +- struct spi_transfer *xfer) ++ u32 speed_hz) + { + u32 div, sck_time, reg_val; + struct mtk_spi *mdata = spi_master_get_devdata(master); + +- if (xfer->speed_hz < mdata->spi_clk_hz / 2) +- div = DIV_ROUND_UP(mdata->spi_clk_hz, xfer->speed_hz); ++ if (speed_hz < mdata->spi_clk_hz / 2) ++ div = DIV_ROUND_UP(mdata->spi_clk_hz, speed_hz); + else + div = 1; + +@@ -423,12 +487,24 @@ static void mtk_spi_setup_packet(struct + u32 packet_size, packet_loop, reg_val; + struct mtk_spi *mdata = spi_master_get_devdata(master); + +- packet_size = min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE); ++ if (mdata->dev_comp->ipm_design) ++ packet_size = min_t(u32, ++ mdata->xfer_len, ++ MTK_SPI_IPM_PACKET_SIZE); ++ else ++ packet_size = min_t(u32, ++ mdata->xfer_len, ++ MTK_SPI_PACKET_SIZE); ++ + packet_loop = mdata->xfer_len / packet_size; + + reg_val = readl(mdata->base + SPI_CFG1_REG); +- reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK); ++ if (mdata->dev_comp->ipm_design) ++ reg_val &= ~SPI_CFG1_IPM_PACKET_LENGTH_MASK; ++ else ++ reg_val &= ~SPI_CFG1_PACKET_LENGTH_MASK; + reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET; ++ reg_val &= ~SPI_CFG1_PACKET_LOOP_MASK; + reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET; + writel(reg_val, mdata->base + SPI_CFG1_REG); + } +@@ -523,7 +599,7 @@ static int mtk_spi_fifo_transfer(struct + mdata->cur_transfer = xfer; + mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len); + mdata->num_xfered = 0; +- mtk_spi_prepare_transfer(master, xfer); ++ mtk_spi_prepare_transfer(master, xfer->speed_hz); + mtk_spi_setup_packet(master); + + if (xfer->tx_buf) { +@@ -556,7 +632,7 @@ static int mtk_spi_dma_transfer(struct s + mdata->cur_transfer = xfer; + mdata->num_xfered = 0; + +- mtk_spi_prepare_transfer(master, xfer); ++ mtk_spi_prepare_transfer(master, xfer->speed_hz); + + cmd = readl(mdata->base + SPI_CMD_REG); + if (xfer->tx_buf) +@@ -591,6 +667,19 @@ static int mtk_spi_transfer_one(struct s + struct spi_device *spi, + struct spi_transfer *xfer) + { ++ struct mtk_spi *mdata = spi_master_get_devdata(spi->master); ++ u32 reg_val = 0; ++ ++ /* prepare xfer direction and duplex mode */ ++ if (mdata->dev_comp->ipm_design) { ++ if (!xfer->tx_buf || !xfer->rx_buf) { ++ reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN; ++ if (xfer->rx_buf) ++ reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR; ++ } ++ writel(reg_val, mdata->base + SPI_CFG3_IPM_REG); ++ } ++ + if (master->can_dma(master, spi, xfer)) + return mtk_spi_dma_transfer(master, spi, xfer); + else +@@ -614,8 +703,9 @@ static int mtk_spi_setup(struct spi_devi + if (!spi->controller_data) + spi->controller_data = (void *)&mtk_default_chip_info; + +- if (mdata->dev_comp->need_pad_sel && gpio_is_valid(spi->cs_gpio)) +- gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); ++ if (mdata->dev_comp->need_pad_sel && spi->cs_gpiod) ++ /* CS de-asserted, gpiolib will handle inversion */ ++ gpiod_direction_output(spi->cs_gpiod, 0); + + return 0; + } +@@ -633,6 +723,12 @@ static irqreturn_t mtk_spi_interrupt(int + else + mdata->state = MTK_SPI_IDLE; + ++ /* SPI-MEM ops */ ++ if (mdata->use_spimem) { ++ complete(&mdata->spimem_done); ++ return IRQ_HANDLED; ++ } ++ + if (!master->can_dma(master, NULL, trans)) { + if (trans->rx_buf) { + cnt = mdata->xfer_len / 4; +@@ -716,6 +812,274 @@ static irqreturn_t mtk_spi_interrupt(int + return IRQ_HANDLED; + } + ++static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem, ++ struct spi_mem_op *op) ++{ ++ int opcode_len; ++ ++ if (op->data.dir != SPI_MEM_NO_DATA) { ++ opcode_len = 1 + op->addr.nbytes + op->dummy.nbytes; ++ if (opcode_len + op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) { ++ op->data.nbytes = MTK_SPI_IPM_PACKET_SIZE - opcode_len; ++ /* force data buffer dma-aligned. */ ++ op->data.nbytes -= op->data.nbytes % 4; ++ } ++ } ++ ++ return 0; ++} ++ ++static bool mtk_spi_mem_supports_op(struct spi_mem *mem, ++ const struct spi_mem_op *op) ++{ ++ if (!spi_mem_default_supports_op(mem, op)) ++ return false; ++ ++ if (op->addr.nbytes && op->dummy.nbytes && ++ op->addr.buswidth != op->dummy.buswidth) ++ return false; ++ ++ if (op->addr.nbytes + op->dummy.nbytes > 16) ++ return false; ++ ++ if (op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) { ++ if (op->data.nbytes / MTK_SPI_IPM_PACKET_SIZE > ++ MTK_SPI_IPM_PACKET_LOOP || ++ op->data.nbytes % MTK_SPI_IPM_PACKET_SIZE != 0) ++ return false; ++ } ++ ++ return true; ++} ++ ++static void mtk_spi_mem_setup_dma_xfer(struct spi_master *master, ++ const struct spi_mem_op *op) ++{ ++ struct mtk_spi *mdata = spi_master_get_devdata(master); ++ ++ writel((u32)(mdata->tx_dma & MTK_SPI_32BITS_MASK), ++ mdata->base + SPI_TX_SRC_REG); ++#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT ++ if (mdata->dev_comp->dma_ext) ++ writel((u32)(mdata->tx_dma >> 32), ++ mdata->base + SPI_TX_SRC_REG_64); ++#endif ++ ++ if (op->data.dir == SPI_MEM_DATA_IN) { ++ writel((u32)(mdata->rx_dma & MTK_SPI_32BITS_MASK), ++ mdata->base + SPI_RX_DST_REG); ++#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT ++ if (mdata->dev_comp->dma_ext) ++ writel((u32)(mdata->rx_dma >> 32), ++ mdata->base + SPI_RX_DST_REG_64); ++#endif ++ } ++} ++ ++static int mtk_spi_transfer_wait(struct spi_mem *mem, ++ const struct spi_mem_op *op) ++{ ++ struct mtk_spi *mdata = spi_master_get_devdata(mem->spi->master); ++ /* ++ * For each byte we wait for 8 cycles of the SPI clock. ++ * Since speed is defined in Hz and we want milliseconds, ++ * so it should be 8 * 1000. ++ */ ++ u64 ms = 8000LL; ++ ++ if (op->data.dir == SPI_MEM_NO_DATA) ++ ms *= 32; /* prevent we may get 0 for short transfers. */ ++ else ++ ms *= op->data.nbytes; ++ ms = div_u64(ms, mem->spi->max_speed_hz); ++ ms += ms + 1000; /* 1s tolerance */ ++ ++ if (ms > UINT_MAX) ++ ms = UINT_MAX; ++ ++ if (!wait_for_completion_timeout(&mdata->spimem_done, ++ msecs_to_jiffies(ms))) { ++ dev_err(mdata->dev, "spi-mem transfer timeout\n"); ++ return -ETIMEDOUT; ++ } ++ ++ return 0; ++} ++ ++static int mtk_spi_mem_exec_op(struct spi_mem *mem, ++ const struct spi_mem_op *op) ++{ ++ struct mtk_spi *mdata = spi_master_get_devdata(mem->spi->master); ++ u32 reg_val, nio, tx_size; ++ char *tx_tmp_buf, *rx_tmp_buf; ++ int ret = 0; ++ ++ mdata->use_spimem = true; ++ reinit_completion(&mdata->spimem_done); ++ ++ mtk_spi_reset(mdata); ++ mtk_spi_hw_init(mem->spi->master, mem->spi); ++ mtk_spi_prepare_transfer(mem->spi->master, mem->spi->max_speed_hz); ++ ++ reg_val = readl(mdata->base + SPI_CFG3_IPM_REG); ++ /* opcode byte len */ ++ reg_val &= ~SPI_CFG3_IPM_CMD_BYTELEN_MASK; ++ reg_val |= 1 << SPI_CFG3_IPM_CMD_BYTELEN_OFFSET; ++ ++ /* addr & dummy byte len */ ++ reg_val &= ~SPI_CFG3_IPM_ADDR_BYTELEN_MASK; ++ if (op->addr.nbytes || op->dummy.nbytes) ++ reg_val |= (op->addr.nbytes + op->dummy.nbytes) << ++ SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET; ++ ++ /* data byte len */ ++ if (op->data.dir == SPI_MEM_NO_DATA) { ++ reg_val |= SPI_CFG3_IPM_NODATA_FLAG; ++ writel(0, mdata->base + SPI_CFG1_REG); ++ } else { ++ reg_val &= ~SPI_CFG3_IPM_NODATA_FLAG; ++ mdata->xfer_len = op->data.nbytes; ++ mtk_spi_setup_packet(mem->spi->master); ++ } ++ ++ if (op->addr.nbytes || op->dummy.nbytes) { ++ if (op->addr.buswidth == 1 || op->dummy.buswidth == 1) ++ reg_val |= SPI_CFG3_IPM_XMODE_EN; ++ else ++ reg_val &= ~SPI_CFG3_IPM_XMODE_EN; ++ } ++ ++ if (op->addr.buswidth == 2 || ++ op->dummy.buswidth == 2 || ++ op->data.buswidth == 2) ++ nio = 2; ++ else if (op->addr.buswidth == 4 || ++ op->dummy.buswidth == 4 || ++ op->data.buswidth == 4) ++ nio = 4; ++ else ++ nio = 1; ++ ++ reg_val &= ~SPI_CFG3_IPM_CMD_PIN_MODE_MASK; ++ reg_val |= PIN_MODE_CFG(nio); ++ ++ reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN; ++ if (op->data.dir == SPI_MEM_DATA_IN) ++ reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR; ++ else ++ reg_val &= ~SPI_CFG3_IPM_HALF_DUPLEX_DIR; ++ writel(reg_val, mdata->base + SPI_CFG3_IPM_REG); ++ ++ tx_size = 1 + op->addr.nbytes + op->dummy.nbytes; ++ if (op->data.dir == SPI_MEM_DATA_OUT) ++ tx_size += op->data.nbytes; ++ ++ tx_size = max_t(u32, tx_size, 32); ++ ++ tx_tmp_buf = kzalloc(tx_size, GFP_KERNEL | GFP_DMA); ++ if (!tx_tmp_buf) { ++ mdata->use_spimem = false; ++ return -ENOMEM; ++ } ++ ++ tx_tmp_buf[0] = op->cmd.opcode; ++ ++ if (op->addr.nbytes) { ++ int i; ++ ++ for (i = 0; i < op->addr.nbytes; i++) ++ tx_tmp_buf[i + 1] = op->addr.val >> ++ (8 * (op->addr.nbytes - i - 1)); ++ } ++ ++ if (op->dummy.nbytes) ++ memset(tx_tmp_buf + op->addr.nbytes + 1, ++ 0xff, ++ op->dummy.nbytes); ++ ++ if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) ++ memcpy(tx_tmp_buf + op->dummy.nbytes + op->addr.nbytes + 1, ++ op->data.buf.out, ++ op->data.nbytes); ++ ++ mdata->tx_dma = dma_map_single(mdata->dev, tx_tmp_buf, ++ tx_size, DMA_TO_DEVICE); ++ if (dma_mapping_error(mdata->dev, mdata->tx_dma)) { ++ ret = -ENOMEM; ++ goto err_exit; ++ } ++ ++ if (op->data.dir == SPI_MEM_DATA_IN) { ++ if (!IS_ALIGNED((size_t)op->data.buf.in, 4)) { ++ rx_tmp_buf = kzalloc(op->data.nbytes, ++ GFP_KERNEL | GFP_DMA); ++ if (!rx_tmp_buf) { ++ ret = -ENOMEM; ++ goto unmap_tx_dma; ++ } ++ } else { ++ rx_tmp_buf = op->data.buf.in; ++ } ++ ++ mdata->rx_dma = dma_map_single(mdata->dev, ++ rx_tmp_buf, ++ op->data.nbytes, ++ DMA_FROM_DEVICE); ++ if (dma_mapping_error(mdata->dev, mdata->rx_dma)) { ++ ret = -ENOMEM; ++ goto kfree_rx_tmp_buf; ++ } ++ } ++ ++ reg_val = readl(mdata->base + SPI_CMD_REG); ++ reg_val |= SPI_CMD_TX_DMA; ++ if (op->data.dir == SPI_MEM_DATA_IN) ++ reg_val |= SPI_CMD_RX_DMA; ++ writel(reg_val, mdata->base + SPI_CMD_REG); ++ ++ mtk_spi_mem_setup_dma_xfer(mem->spi->master, op); ++ ++ mtk_spi_enable_transfer(mem->spi->master); ++ ++ /* Wait for the interrupt. */ ++ ret = mtk_spi_transfer_wait(mem, op); ++ if (ret) ++ goto unmap_rx_dma; ++ ++ /* spi disable dma */ ++ reg_val = readl(mdata->base + SPI_CMD_REG); ++ reg_val &= ~SPI_CMD_TX_DMA; ++ if (op->data.dir == SPI_MEM_DATA_IN) ++ reg_val &= ~SPI_CMD_RX_DMA; ++ writel(reg_val, mdata->base + SPI_CMD_REG); ++ ++unmap_rx_dma: ++ if (op->data.dir == SPI_MEM_DATA_IN) { ++ dma_unmap_single(mdata->dev, mdata->rx_dma, ++ op->data.nbytes, DMA_FROM_DEVICE); ++ if (!IS_ALIGNED((size_t)op->data.buf.in, 4)) ++ memcpy(op->data.buf.in, rx_tmp_buf, op->data.nbytes); ++ } ++kfree_rx_tmp_buf: ++ if (op->data.dir == SPI_MEM_DATA_IN && ++ !IS_ALIGNED((size_t)op->data.buf.in, 4)) ++ kfree(rx_tmp_buf); ++unmap_tx_dma: ++ dma_unmap_single(mdata->dev, mdata->tx_dma, ++ tx_size, DMA_TO_DEVICE); ++err_exit: ++ kfree(tx_tmp_buf); ++ mdata->use_spimem = false; ++ ++ return ret; ++} ++ ++static const struct spi_controller_mem_ops mtk_spi_mem_ops = { ++ .adjust_op_size = mtk_spi_mem_adjust_op_size, ++ .supports_op = mtk_spi_mem_supports_op, ++ .exec_op = mtk_spi_mem_exec_op, ++}; ++ + static int mtk_spi_probe(struct platform_device *pdev) + { + struct spi_master *master; +@@ -739,6 +1103,7 @@ static int mtk_spi_probe(struct platform + master->can_dma = mtk_spi_can_dma; + master->setup = mtk_spi_setup; + master->set_cs_timing = mtk_spi_set_hw_cs_timing; ++ master->use_gpio_descriptors = true; + + of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node); + if (!of_id) { +@@ -755,6 +1120,14 @@ static int mtk_spi_probe(struct platform + + if (mdata->dev_comp->must_tx) + master->flags = SPI_MASTER_MUST_TX; ++ if (mdata->dev_comp->ipm_design) ++ master->mode_bits |= SPI_LOOP; ++ ++ if (mdata->dev_comp->ipm_design) { ++ mdata->dev = &pdev->dev; ++ master->mem_ops = &mtk_spi_mem_ops; ++ init_completion(&mdata->spimem_done); ++ } + + if (mdata->dev_comp->need_pad_sel) { + mdata->pad_num = of_property_count_u32_elems( +@@ -831,25 +1204,40 @@ static int mtk_spi_probe(struct platform + goto err_put_master; + } + ++ mdata->spi_hclk = devm_clk_get_optional(&pdev->dev, "hclk"); ++ if (IS_ERR(mdata->spi_hclk)) { ++ ret = PTR_ERR(mdata->spi_hclk); ++ dev_err(&pdev->dev, "failed to get hclk: %d\n", ret); ++ goto err_put_master; ++ } ++ ++ ret = clk_prepare_enable(mdata->spi_hclk); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "failed to enable hclk (%d)\n", ret); ++ goto err_put_master; ++ } ++ + ret = clk_prepare_enable(mdata->spi_clk); + if (ret < 0) { + dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret); +- goto err_put_master; ++ goto err_disable_spi_hclk; + } + + ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk); + if (ret < 0) { + dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret); +- clk_disable_unprepare(mdata->spi_clk); +- goto err_put_master; ++ goto err_disable_spi_clk; + } + + mdata->spi_clk_hz = clk_get_rate(mdata->spi_clk); + +- if (mdata->dev_comp->no_need_unprepare) ++ if (mdata->dev_comp->no_need_unprepare) { + clk_disable(mdata->spi_clk); +- else ++ clk_disable(mdata->spi_hclk); ++ } else { + clk_disable_unprepare(mdata->spi_clk); ++ clk_disable_unprepare(mdata->spi_hclk); ++ } + + pm_runtime_enable(&pdev->dev); + +@@ -862,25 +1250,12 @@ static int mtk_spi_probe(struct platform + goto err_disable_runtime_pm; + } + +- if (!master->cs_gpios && master->num_chipselect > 1) { ++ if (!master->cs_gpiods && master->num_chipselect > 1) { + dev_err(&pdev->dev, + "cs_gpios not specified and num_chipselect > 1\n"); + ret = -EINVAL; + goto err_disable_runtime_pm; + } +- +- if (master->cs_gpios) { +- for (i = 0; i < master->num_chipselect; i++) { +- ret = devm_gpio_request(&pdev->dev, +- master->cs_gpios[i], +- dev_name(&pdev->dev)); +- if (ret) { +- dev_err(&pdev->dev, +- "can't get CS GPIO %i\n", i); +- goto err_disable_runtime_pm; +- } +- } +- } + } + + if (mdata->dev_comp->dma_ext) +@@ -902,6 +1277,10 @@ static int mtk_spi_probe(struct platform + + err_disable_runtime_pm: + pm_runtime_disable(&pdev->dev); ++err_disable_spi_clk: ++ clk_disable_unprepare(mdata->spi_clk); ++err_disable_spi_hclk: ++ clk_disable_unprepare(mdata->spi_hclk); + err_put_master: + spi_master_put(master); + +@@ -920,8 +1299,10 @@ static int mtk_spi_remove(struct platfor + + mtk_spi_reset(mdata); + +- if (mdata->dev_comp->no_need_unprepare) ++ if (mdata->dev_comp->no_need_unprepare) { + clk_unprepare(mdata->spi_clk); ++ clk_unprepare(mdata->spi_hclk); ++ } + + pm_runtime_put_noidle(&pdev->dev); + pm_runtime_disable(&pdev->dev); +@@ -940,8 +1321,10 @@ static int mtk_spi_suspend(struct device + if (ret) + return ret; + +- if (!pm_runtime_suspended(dev)) ++ if (!pm_runtime_suspended(dev)) { + clk_disable_unprepare(mdata->spi_clk); ++ clk_disable_unprepare(mdata->spi_hclk); ++ } + + return ret; + } +@@ -958,11 +1341,20 @@ static int mtk_spi_resume(struct device + dev_err(dev, "failed to enable spi_clk (%d)\n", ret); + return ret; + } ++ ++ ret = clk_prepare_enable(mdata->spi_hclk); ++ if (ret < 0) { ++ dev_err(dev, "failed to enable spi_hclk (%d)\n", ret); ++ clk_disable_unprepare(mdata->spi_clk); ++ return ret; ++ } + } + + ret = spi_master_resume(master); +- if (ret < 0) ++ if (ret < 0) { + clk_disable_unprepare(mdata->spi_clk); ++ clk_disable_unprepare(mdata->spi_hclk); ++ } + + return ret; + } +@@ -974,10 +1366,13 @@ static int mtk_spi_runtime_suspend(struc + struct spi_master *master = dev_get_drvdata(dev); + struct mtk_spi *mdata = spi_master_get_devdata(master); + +- if (mdata->dev_comp->no_need_unprepare) ++ if (mdata->dev_comp->no_need_unprepare) { + clk_disable(mdata->spi_clk); +- else ++ clk_disable(mdata->spi_hclk); ++ } else { + clk_disable_unprepare(mdata->spi_clk); ++ clk_disable_unprepare(mdata->spi_hclk); ++ } + + return 0; + } +@@ -988,13 +1383,31 @@ static int mtk_spi_runtime_resume(struct + struct mtk_spi *mdata = spi_master_get_devdata(master); + int ret; + +- if (mdata->dev_comp->no_need_unprepare) ++ if (mdata->dev_comp->no_need_unprepare) { + ret = clk_enable(mdata->spi_clk); +- else ++ if (ret < 0) { ++ dev_err(dev, "failed to enable spi_clk (%d)\n", ret); ++ return ret; ++ } ++ ret = clk_enable(mdata->spi_hclk); ++ if (ret < 0) { ++ dev_err(dev, "failed to enable spi_hclk (%d)\n", ret); ++ clk_disable(mdata->spi_clk); ++ return ret; ++ } ++ } else { + ret = clk_prepare_enable(mdata->spi_clk); +- if (ret < 0) { +- dev_err(dev, "failed to enable spi_clk (%d)\n", ret); +- return ret; ++ if (ret < 0) { ++ dev_err(dev, "failed to prepare_enable spi_clk (%d)\n", ret); ++ return ret; ++ } ++ ++ ret = clk_prepare_enable(mdata->spi_hclk); ++ if (ret < 0) { ++ dev_err(dev, "failed to prepare_enable spi_hclk (%d)\n", ret); ++ clk_disable_unprepare(mdata->spi_clk); ++ return ret; ++ } + } + + return 0; diff --git a/target/linux/mediatek/patches-6.1/214-v6.3-clk-mediatek-add-mt7981-clock-support.patch b/target/linux/mediatek/patches-6.1/214-v6.3-clk-mediatek-add-mt7981-clock-support.patch new file mode 100644 index 00000000000..631eb04092d --- /dev/null +++ b/target/linux/mediatek/patches-6.1/214-v6.3-clk-mediatek-add-mt7981-clock-support.patch @@ -0,0 +1,39 @@ +--- a/drivers/clk/mediatek/Kconfig ++++ b/drivers/clk/mediatek/Kconfig +@@ -344,6 +344,23 @@ config COMMON_CLK_MT7629_HIFSYS + This driver supports MediaTek MT7629 HIFSYS clocks providing + to PCI-E and USB. + ++config COMMON_CLK_MT7981 ++ bool "Clock driver for MediaTek MT7981" ++ depends on ARCH_MEDIATEK || COMPILE_TEST ++ select COMMON_CLK_MEDIATEK ++ default ARCH_MEDIATEK ++ help ++ This driver supports MediaTek MT7981 basic clocks and clocks ++ required for various periperals found on MediaTek. ++ ++config COMMON_CLK_MT7981_ETHSYS ++ bool "Clock driver for MediaTek MT7981 ETHSYS" ++ depends on COMMON_CLK_MT7981 ++ default COMMON_CLK_MT7981 ++ help ++ This driver add support for clocks for Ethernet and SGMII ++ required on MediaTek MT7981 SoC. ++ + config COMMON_CLK_MT7986 + bool "Clock driver for MediaTek MT7986" + depends on ARCH_MEDIATEK || COMPILE_TEST +--- a/drivers/clk/mediatek/Makefile ++++ b/drivers/clk/mediatek/Makefile +@@ -46,6 +46,10 @@ obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) + + obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o + obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o + obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o ++obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-apmixed.o ++obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-topckgen.o ++obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-infracfg.o ++obj-$(CONFIG_COMMON_CLK_MT7981_ETHSYS) += clk-mt7981-eth.o + obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-apmixed.o + obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o + obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o diff --git a/target/linux/mediatek/patches-6.1/215-v6.3-pinctrl-mediatek-add-support-for-MT7981-SoC.patch b/target/linux/mediatek/patches-6.1/215-v6.3-pinctrl-mediatek-add-support-for-MT7981-SoC.patch new file mode 100644 index 00000000000..ae99685df4c --- /dev/null +++ b/target/linux/mediatek/patches-6.1/215-v6.3-pinctrl-mediatek-add-support-for-MT7981-SoC.patch @@ -0,0 +1,26 @@ +--- a/drivers/pinctrl/mediatek/Kconfig ++++ b/drivers/pinctrl/mediatek/Kconfig +@@ -120,6 +120,13 @@ config PINCTRL_MT7622 + default ARM64 && ARCH_MEDIATEK + select PINCTRL_MTK_MOORE + ++config PINCTRL_MT7981 ++ bool "Mediatek MT7981 pin control" ++ depends on OF ++ depends on ARM64 || COMPILE_TEST ++ default ARM64 && ARCH_MEDIATEK ++ select PINCTRL_MTK_MOORE ++ + config PINCTRL_MT7986 + bool "Mediatek MT7986 pin control" + depends on OF +--- a/drivers/pinctrl/mediatek/Makefile ++++ b/drivers/pinctrl/mediatek/Makefile +@@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_MT6797) += pinctrl- + obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o + obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o + obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o ++obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7981.o + obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o + obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o + obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o diff --git a/target/linux/mediatek/patches-6.1/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch b/target/linux/mediatek/patches-6.1/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch new file mode 100644 index 00000000000..cbee45bc1f8 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch @@ -0,0 +1,26 @@ +--- a/drivers/pinctrl/mediatek/Kconfig ++++ b/drivers/pinctrl/mediatek/Kconfig +@@ -134,6 +134,13 @@ config PINCTRL_MT7986 + default ARM64 && ARCH_MEDIATEK + select PINCTRL_MTK_MOORE + ++config PINCTRL_MT7988 ++ bool "Mediatek MT7988 pin control" ++ depends on OF ++ depends on ARM64 || COMPILE_TEST ++ default ARCH_MEDIATEK ++ select PINCTRL_MTK_MOORE ++ + config PINCTRL_MT8167 + bool "Mediatek MT8167 pin control" + depends on OF +--- a/drivers/pinctrl/mediatek/Makefile ++++ b/drivers/pinctrl/mediatek/Makefile +@@ -19,6 +19,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl- + obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o + obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7981.o + obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o ++obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o + obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o + obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o + obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o diff --git a/target/linux/mediatek/patches-6.1/241-clk-mediatek-Add-pcw-chg-shift-control.patch b/target/linux/mediatek/patches-6.1/241-clk-mediatek-Add-pcw-chg-shift-control.patch new file mode 100644 index 00000000000..23a5b7c911a --- /dev/null +++ b/target/linux/mediatek/patches-6.1/241-clk-mediatek-Add-pcw-chg-shift-control.patch @@ -0,0 +1,24 @@ +--- a/drivers/clk/mediatek/clk-mtk.h ++++ b/drivers/clk/mediatek/clk-mtk.h +@@ -233,6 +233,7 @@ struct mtk_pll_data { + u32 pcw_reg; + int pcw_shift; + u32 pcw_chg_reg; ++ int pcw_chg_shift; + const struct mtk_pll_div_table *div_table; + const char *parent_name; + u32 en_reg; +--- a/drivers/clk/mediatek/clk-pll.c ++++ b/drivers/clk/mediatek/clk-pll.c +@@ -137,7 +137,10 @@ static void mtk_pll_set_rate_regs(struct + pll->data->pcw_shift); + val |= pcw << pll->data->pcw_shift; + writel(val, pll->pcw_addr); +- chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK; ++ if (pll->data->pcw_chg_shift) ++ chg = readl(pll->pcw_chg_addr) | BIT(pll->data->pcw_chg_shift); ++ else ++ chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK; + writel(chg, pll->pcw_chg_addr); + if (pll->tuner_addr) + writel(val + 1, pll->tuner_addr); diff --git a/target/linux/mediatek/patches-6.1/242-clk-mediatek-add-mt7988-clock-support.patch b/target/linux/mediatek/patches-6.1/242-clk-mediatek-add-mt7988-clock-support.patch new file mode 100644 index 00000000000..bf9146352a6 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/242-clk-mediatek-add-mt7988-clock-support.patch @@ -0,0 +1,31 @@ +--- a/drivers/clk/mediatek/Kconfig ++++ b/drivers/clk/mediatek/Kconfig +@@ -378,6 +378,15 @@ config COMMON_CLK_MT7986_ETHSYS + This driver add support for clocks for Ethernet and SGMII + required on MediaTek MT7986 SoC. + ++config COMMON_CLK_MT7988 ++ bool "Clock driver for MediaTek MT7988" ++ depends on ARCH_MEDIATEK || COMPILE_TEST ++ select COMMON_CLK_MEDIATEK ++ default ARCH_MEDIATEK ++ help ++ This driver supports MediaTek MT7988 basic clocks and clocks ++ required for various periperals found on MediaTek. ++ + config COMMON_CLK_MT8135 + bool "Clock driver for MediaTek MT8135" + depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST +--- a/drivers/clk/mediatek/Makefile ++++ b/drivers/clk/mediatek/Makefile +@@ -54,6 +54,10 @@ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-m + obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o + obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o + obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o ++obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-apmixed.o ++obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-topckgen.o ++obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-infracfg.o ++obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-eth.o + obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o + obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167.o + obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o diff --git a/target/linux/mediatek/patches-6.1/320-mmc-mediatek-add-support-for-MT7986-SoC.patch b/target/linux/mediatek/patches-6.1/320-mmc-mediatek-add-support-for-MT7986-SoC.patch new file mode 100644 index 00000000000..56ffa73c00c --- /dev/null +++ b/target/linux/mediatek/patches-6.1/320-mmc-mediatek-add-support-for-MT7986-SoC.patch @@ -0,0 +1,44 @@ +From 1a7963e9843f6f1e4b02a30926d20b314c03e4df Mon Sep 17 00:00:00 2001 +From: Sam Shih +Date: Sat, 25 Jun 2022 02:10:13 +0800 +Subject: [PATCH] mmc: mediatek: add support for MT7986 SoC + +Adding mt7986 own characteristics and of_device_id to have support +of MT7986 SoC. + +Signed-off-by: Sam Shih +Change-Id: I07cf8406cbe8c1a7114b304f35fc3e689e512e5a +--- + drivers/mmc/host/mtk-sd.c | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +--- a/drivers/mmc/host/mtk-sd.c ++++ b/drivers/mmc/host/mtk-sd.c +@@ -540,6 +540,19 @@ static const struct mtk_mmc_compatible m + .support_64g = false, + }; + ++static const struct mtk_mmc_compatible mt7986_compat = { ++ .clk_div_bits = 12, ++ .recheck_sdio_irq = true, ++ .hs400_tune = false, ++ .pad_tune_reg = MSDC_PAD_TUNE0, ++ .async_fifo = true, ++ .data_tune = true, ++ .busy_check = true, ++ .stop_clk_fix = true, ++ .enhance_rx = true, ++ .support_64g = true, ++}; ++ + static const struct mtk_mmc_compatible mt8516_compat = { + .clk_div_bits = 12, + .recheck_sdio_irq = true, +@@ -584,6 +597,7 @@ static const struct of_device_id msdc_of + { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, + { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, + { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, ++ { .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat}, + { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, + { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, + { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat}, diff --git a/target/linux/mediatek/patches-6.1/330-snand-mtk-bmt-support.patch b/target/linux/mediatek/patches-6.1/330-snand-mtk-bmt-support.patch new file mode 100644 index 00000000000..6814e5f5e98 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/330-snand-mtk-bmt-support.patch @@ -0,0 +1,34 @@ +--- a/drivers/mtd/nand/spi/core.c ++++ b/drivers/mtd/nand/spi/core.c +@@ -19,6 +19,7 @@ + #include + #include + #include ++#include + + static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val) + { +@@ -1343,6 +1344,7 @@ static int spinand_probe(struct spi_mem + if (ret) + return ret; + ++ mtk_bmt_attach(mtd); + ret = mtd_device_register(mtd, NULL, 0); + if (ret) + goto err_spinand_cleanup; +@@ -1350,6 +1352,7 @@ static int spinand_probe(struct spi_mem + return 0; + + err_spinand_cleanup: ++ mtk_bmt_detach(mtd); + spinand_cleanup(spinand); + + return ret; +@@ -1368,6 +1371,7 @@ static int spinand_remove(struct spi_mem + if (ret) + return ret; + ++ mtk_bmt_detach(mtd); + spinand_cleanup(spinand); + + return 0; diff --git a/target/linux/mediatek/patches-6.1/331-mt7622-rfb1-enable-bmt.patch b/target/linux/mediatek/patches-6.1/331-mt7622-rfb1-enable-bmt.patch new file mode 100644 index 00000000000..9c1a8f284ab --- /dev/null +++ b/target/linux/mediatek/patches-6.1/331-mt7622-rfb1-enable-bmt.patch @@ -0,0 +1,10 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +@@ -553,6 +553,7 @@ + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + nand-ecc-engine = <&snfi>; ++ mediatek,bmt-v2; + + partitions { + compatible = "fixed-partitions"; diff --git a/target/linux/mediatek/patches-6.1/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch b/target/linux/mediatek/patches-6.1/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch new file mode 100644 index 00000000000..6baa32879bf --- /dev/null +++ b/target/linux/mediatek/patches-6.1/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch @@ -0,0 +1,122 @@ +From 5f49a5c9b16330e0df8f639310e4715dcad71947 Mon Sep 17 00:00:00 2001 +From: Davide Fioravanti +Date: Fri, 8 Jan 2021 15:35:24 +0100 +Subject: [PATCH] mtd: spinand: Add support for the Fidelix FM35X1GA + +Datasheet: http://www.hobos.com.cn/upload/datasheet/DS35X1GAXXX_100_rev00.pdf + +Signed-off-by: Davide Fioravanti +--- + drivers/mtd/nand/spi/Makefile | 2 +- + drivers/mtd/nand/spi/core.c | 1 + + drivers/mtd/nand/spi/fidelix.c | 76 ++++++++++++++++++++++++++++++++++ + include/linux/mtd/spinand.h | 1 + + 4 files changed, 79 insertions(+), 1 deletion(-) + create mode 100644 drivers/mtd/nand/spi/fidelix.c + +--- a/drivers/mtd/nand/spi/Makefile ++++ b/drivers/mtd/nand/spi/Makefile +@@ -1,3 +1,3 @@ + # SPDX-License-Identifier: GPL-2.0 +-spinand-objs := core.o esmt.o etron.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o ++spinand-objs := core.o esmt.o etron.o fidelix.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o + obj-$(CONFIG_MTD_SPI_NAND) += spinand.o +--- a/drivers/mtd/nand/spi/core.c ++++ b/drivers/mtd/nand/spi/core.c +@@ -939,6 +939,7 @@ static const struct nand_ops spinand_ops + + static const struct spinand_manufacturer *spinand_manufacturers[] = { + &esmt_c8_spinand_manufacturer, ++ &fidelix_spinand_manufacturer, + &gigadevice_spinand_manufacturer, + &etron_spinand_manufacturer, + ¯onix_spinand_manufacturer, +--- /dev/null ++++ b/drivers/mtd/nand/spi/fidelix.c +@@ -0,0 +1,76 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2020 Davide Fioravanti ++ */ ++ ++#include ++#include ++#include ++ ++#define SPINAND_MFR_FIDELIX 0xE5 ++#define FIDELIX_ECCSR_MASK 0x0F ++ ++static SPINAND_OP_VARIANTS(read_cache_variants, ++ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); ++ ++static SPINAND_OP_VARIANTS(write_cache_variants, ++ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), ++ SPINAND_PROG_LOAD(true, 0, NULL, 0)); ++ ++static SPINAND_OP_VARIANTS(update_cache_variants, ++ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), ++ SPINAND_PROG_LOAD(false, 0, NULL, 0)); ++ ++static int fm35x1ga_ooblayout_ecc(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section > 3) ++ return -ERANGE; ++ ++ region->offset = (16 * section) + 8; ++ region->length = 8; ++ ++ return 0; ++} ++ ++static int fm35x1ga_ooblayout_free(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section > 3) ++ return -ERANGE; ++ ++ region->offset = (16 * section) + 2; ++ region->length = 6; ++ ++ return 0; ++} ++ ++static const struct mtd_ooblayout_ops fm35x1ga_ooblayout = { ++ .ecc = fm35x1ga_ooblayout_ecc, ++ .free = fm35x1ga_ooblayout_free, ++}; ++ ++static const struct spinand_info fidelix_spinand_table[] = { ++ SPINAND_INFO("FM35X1GA", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x71), ++ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), ++ NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&fm35x1ga_ooblayout, NULL)), ++}; ++ ++static const struct spinand_manufacturer_ops fidelix_spinand_manuf_ops = { ++}; ++ ++const struct spinand_manufacturer fidelix_spinand_manufacturer = { ++ .id = SPINAND_MFR_FIDELIX, ++ .name = "Fidelix", ++ .chips = fidelix_spinand_table, ++ .nchips = ARRAY_SIZE(fidelix_spinand_table), ++ .ops = &fidelix_spinand_manuf_ops, ++}; +--- a/include/linux/mtd/spinand.h ++++ b/include/linux/mtd/spinand.h +@@ -262,6 +262,7 @@ struct spinand_manufacturer { + /* SPI NAND manufacturers */ + extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer; + extern const struct spinand_manufacturer etron_spinand_manufacturer; ++extern const struct spinand_manufacturer fidelix_spinand_manufacturer; + extern const struct spinand_manufacturer gigadevice_spinand_manufacturer; + extern const struct spinand_manufacturer macronix_spinand_manufacturer; + extern const struct spinand_manufacturer micron_spinand_manufacturer; diff --git a/target/linux/mediatek/patches-6.1/350-01-cpufreq-mediatek-Cleanup-variables-and-error-handlin.patch b/target/linux/mediatek/patches-6.1/350-01-cpufreq-mediatek-Cleanup-variables-and-error-handlin.patch new file mode 100644 index 00000000000..8fad64a5702 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/350-01-cpufreq-mediatek-Cleanup-variables-and-error-handlin.patch @@ -0,0 +1,166 @@ +From 7a768326fdba542144833b9198a6d0edab52fad2 Mon Sep 17 00:00:00 2001 +From: Jia-Wei Chang +Date: Fri, 8 Apr 2022 12:58:56 +0800 +Subject: [PATCH 01/21] cpufreq: mediatek: Cleanup variables and error handling + in mtk_cpu_dvfs_info_init() + +- Remove several unnecessary varaibles in mtk_cpu_dvfs_info_init(). +- Unify error message format and use dev_err_probe() if possible. + +Signed-off-by: Jia-Wei Chang +Signed-off-by: Rex-BC Chen +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Viresh Kumar +--- + drivers/cpufreq/mediatek-cpufreq.c | 89 ++++++++++++------------------ + 1 file changed, 34 insertions(+), 55 deletions(-) + +--- a/drivers/cpufreq/mediatek-cpufreq.c ++++ b/drivers/cpufreq/mediatek-cpufreq.c +@@ -302,96 +302,75 @@ static int mtk_cpufreq_set_target(struct + static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) + { + struct device *cpu_dev; +- struct regulator *proc_reg = ERR_PTR(-ENODEV); +- struct regulator *sram_reg = ERR_PTR(-ENODEV); +- struct clk *cpu_clk = ERR_PTR(-ENODEV); +- struct clk *inter_clk = ERR_PTR(-ENODEV); + struct dev_pm_opp *opp; + unsigned long rate; + int ret; + + cpu_dev = get_cpu_device(cpu); + if (!cpu_dev) { +- pr_err("failed to get cpu%d device\n", cpu); ++ dev_err(cpu_dev, "failed to get cpu%d device\n", cpu); + return -ENODEV; + } ++ info->cpu_dev = cpu_dev; + +- cpu_clk = clk_get(cpu_dev, "cpu"); +- if (IS_ERR(cpu_clk)) { +- if (PTR_ERR(cpu_clk) == -EPROBE_DEFER) +- pr_warn("cpu clk for cpu%d not ready, retry.\n", cpu); +- else +- pr_err("failed to get cpu clk for cpu%d\n", cpu); +- +- ret = PTR_ERR(cpu_clk); +- return ret; +- } +- +- inter_clk = clk_get(cpu_dev, "intermediate"); +- if (IS_ERR(inter_clk)) { +- if (PTR_ERR(inter_clk) == -EPROBE_DEFER) +- pr_warn("intermediate clk for cpu%d not ready, retry.\n", +- cpu); +- else +- pr_err("failed to get intermediate clk for cpu%d\n", +- cpu); ++ info->cpu_clk = clk_get(cpu_dev, "cpu"); ++ if (IS_ERR(info->cpu_clk)) { ++ ret = PTR_ERR(info->cpu_clk); ++ return dev_err_probe(cpu_dev, ret, ++ "cpu%d: failed to get cpu clk\n", cpu); ++ } + +- ret = PTR_ERR(inter_clk); ++ info->inter_clk = clk_get(cpu_dev, "intermediate"); ++ if (IS_ERR(info->inter_clk)) { ++ ret = PTR_ERR(info->inter_clk); ++ dev_err_probe(cpu_dev, ret, ++ "cpu%d: failed to get intermediate clk\n", cpu); + goto out_free_resources; + } + +- proc_reg = regulator_get_optional(cpu_dev, "proc"); +- if (IS_ERR(proc_reg)) { +- if (PTR_ERR(proc_reg) == -EPROBE_DEFER) +- pr_warn("proc regulator for cpu%d not ready, retry.\n", +- cpu); +- else +- pr_err("failed to get proc regulator for cpu%d\n", +- cpu); +- +- ret = PTR_ERR(proc_reg); ++ info->proc_reg = regulator_get_optional(cpu_dev, "proc"); ++ if (IS_ERR(info->proc_reg)) { ++ ret = PTR_ERR(info->proc_reg); ++ dev_err_probe(cpu_dev, ret, ++ "cpu%d: failed to get proc regulator\n", cpu); + goto out_free_resources; + } + + /* Both presence and absence of sram regulator are valid cases. */ +- sram_reg = regulator_get_exclusive(cpu_dev, "sram"); ++ info->sram_reg = regulator_get_exclusive(cpu_dev, "sram"); ++ if (IS_ERR(info->sram_reg)) ++ info->sram_reg = NULL; + + /* Get OPP-sharing information from "operating-points-v2" bindings */ + ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, &info->cpus); + if (ret) { +- pr_err("failed to get OPP-sharing information for cpu%d\n", +- cpu); ++ dev_err(cpu_dev, ++ "cpu%d: failed to get OPP-sharing information\n", cpu); + goto out_free_resources; + } + + ret = dev_pm_opp_of_cpumask_add_table(&info->cpus); + if (ret) { +- pr_warn("no OPP table for cpu%d\n", cpu); ++ dev_warn(cpu_dev, "cpu%d: no OPP table\n", cpu); + goto out_free_resources; + } + + /* Search a safe voltage for intermediate frequency. */ +- rate = clk_get_rate(inter_clk); ++ rate = clk_get_rate(info->inter_clk); + opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate); + if (IS_ERR(opp)) { +- pr_err("failed to get intermediate opp for cpu%d\n", cpu); ++ dev_err(cpu_dev, "cpu%d: failed to get intermediate opp\n", cpu); + ret = PTR_ERR(opp); + goto out_free_opp_table; + } + info->intermediate_voltage = dev_pm_opp_get_voltage(opp); + dev_pm_opp_put(opp); + +- info->cpu_dev = cpu_dev; +- info->proc_reg = proc_reg; +- info->sram_reg = IS_ERR(sram_reg) ? NULL : sram_reg; +- info->cpu_clk = cpu_clk; +- info->inter_clk = inter_clk; +- + /* + * If SRAM regulator is present, software "voltage tracking" is needed + * for this CPU power domain. + */ +- info->need_voltage_tracking = !IS_ERR(sram_reg); ++ info->need_voltage_tracking = (info->sram_reg != NULL); + + return 0; + +@@ -399,14 +378,14 @@ out_free_opp_table: + dev_pm_opp_of_cpumask_remove_table(&info->cpus); + + out_free_resources: +- if (!IS_ERR(proc_reg)) +- regulator_put(proc_reg); +- if (!IS_ERR(sram_reg)) +- regulator_put(sram_reg); +- if (!IS_ERR(cpu_clk)) +- clk_put(cpu_clk); +- if (!IS_ERR(inter_clk)) +- clk_put(inter_clk); ++ if (!IS_ERR(info->proc_reg)) ++ regulator_put(info->proc_reg); ++ if (!IS_ERR(info->sram_reg)) ++ regulator_put(info->sram_reg); ++ if (!IS_ERR(info->cpu_clk)) ++ clk_put(info->cpu_clk); ++ if (!IS_ERR(info->inter_clk)) ++ clk_put(info->inter_clk); + + return ret; + } diff --git a/target/linux/mediatek/patches-6.1/350-02-cpufreq-mediatek-Remove-unused-headers.patch b/target/linux/mediatek/patches-6.1/350-02-cpufreq-mediatek-Remove-unused-headers.patch new file mode 100644 index 00000000000..eebeeb09028 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/350-02-cpufreq-mediatek-Remove-unused-headers.patch @@ -0,0 +1,25 @@ +From 756104b856d4bc3121420af3ced342f5fc2b2123 Mon Sep 17 00:00:00 2001 +From: Jia-Wei Chang +Date: Fri, 8 Apr 2022 12:58:57 +0800 +Subject: [PATCH 02/21] cpufreq: mediatek: Remove unused headers + +Remove unused headers. + +Signed-off-by: Jia-Wei Chang +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Viresh Kumar +--- + drivers/cpufreq/mediatek-cpufreq.c | 2 -- + 1 file changed, 2 deletions(-) + +--- a/drivers/cpufreq/mediatek-cpufreq.c ++++ b/drivers/cpufreq/mediatek-cpufreq.c +@@ -13,8 +13,6 @@ + #include + #include + #include +-#include +-#include + + #define MIN_VOLT_SHIFT (100000) + #define MAX_VOLT_SHIFT (200000) diff --git a/target/linux/mediatek/patches-6.1/350-03-cpufreq-mediatek-Enable-clocks-and-regulators.patch b/target/linux/mediatek/patches-6.1/350-03-cpufreq-mediatek-Enable-clocks-and-regulators.patch new file mode 100644 index 00000000000..c97d5fc3d91 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/350-03-cpufreq-mediatek-Enable-clocks-and-regulators.patch @@ -0,0 +1,117 @@ +From 342d5545e9f40496db9ae0d31c2427dd5f369a43 Mon Sep 17 00:00:00 2001 +From: Jia-Wei Chang +Date: Fri, 8 Apr 2022 12:58:58 +0800 +Subject: [PATCH 03/21] cpufreq: mediatek: Enable clocks and regulators + +We need to enable regulators so that the max and min requested values will +be recorded. +The intermediate clock is not always enabled by CCF in different projects, +so we should enable it in the cpufreq driver. + +Signed-off-by: Andrew-sh.Cheng +Signed-off-by: Jia-Wei Chang +Signed-off-by: Rex-BC Chen +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Viresh Kumar +--- + drivers/cpufreq/mediatek-cpufreq.c | 50 +++++++++++++++++++++++++++--- + 1 file changed, 45 insertions(+), 5 deletions(-) + +--- a/drivers/cpufreq/mediatek-cpufreq.c ++++ b/drivers/cpufreq/mediatek-cpufreq.c +@@ -334,10 +334,23 @@ static int mtk_cpu_dvfs_info_init(struct + goto out_free_resources; + } + ++ ret = regulator_enable(info->proc_reg); ++ if (ret) { ++ dev_warn(cpu_dev, "cpu%d: failed to enable vproc\n", cpu); ++ goto out_free_resources; ++ } ++ + /* Both presence and absence of sram regulator are valid cases. */ + info->sram_reg = regulator_get_exclusive(cpu_dev, "sram"); + if (IS_ERR(info->sram_reg)) + info->sram_reg = NULL; ++ else { ++ ret = regulator_enable(info->sram_reg); ++ if (ret) { ++ dev_warn(cpu_dev, "cpu%d: failed to enable vsram\n", cpu); ++ goto out_free_resources; ++ } ++ } + + /* Get OPP-sharing information from "operating-points-v2" bindings */ + ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, &info->cpus); +@@ -353,13 +366,21 @@ static int mtk_cpu_dvfs_info_init(struct + goto out_free_resources; + } + ++ ret = clk_prepare_enable(info->cpu_clk); ++ if (ret) ++ goto out_free_opp_table; ++ ++ ret = clk_prepare_enable(info->inter_clk); ++ if (ret) ++ goto out_disable_mux_clock; ++ + /* Search a safe voltage for intermediate frequency. */ + rate = clk_get_rate(info->inter_clk); + opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate); + if (IS_ERR(opp)) { + dev_err(cpu_dev, "cpu%d: failed to get intermediate opp\n", cpu); + ret = PTR_ERR(opp); +- goto out_free_opp_table; ++ goto out_disable_inter_clock; + } + info->intermediate_voltage = dev_pm_opp_get_voltage(opp); + dev_pm_opp_put(opp); +@@ -372,10 +393,21 @@ static int mtk_cpu_dvfs_info_init(struct + + return 0; + ++out_disable_inter_clock: ++ clk_disable_unprepare(info->inter_clk); ++ ++out_disable_mux_clock: ++ clk_disable_unprepare(info->cpu_clk); ++ + out_free_opp_table: + dev_pm_opp_of_cpumask_remove_table(&info->cpus); + + out_free_resources: ++ if (regulator_is_enabled(info->proc_reg)) ++ regulator_disable(info->proc_reg); ++ if (info->sram_reg && regulator_is_enabled(info->sram_reg)) ++ regulator_disable(info->sram_reg); ++ + if (!IS_ERR(info->proc_reg)) + regulator_put(info->proc_reg); + if (!IS_ERR(info->sram_reg)) +@@ -390,14 +422,22 @@ out_free_resources: + + static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info) + { +- if (!IS_ERR(info->proc_reg)) ++ if (!IS_ERR(info->proc_reg)) { ++ regulator_disable(info->proc_reg); + regulator_put(info->proc_reg); +- if (!IS_ERR(info->sram_reg)) ++ } ++ if (!IS_ERR(info->sram_reg)) { ++ regulator_disable(info->sram_reg); + regulator_put(info->sram_reg); +- if (!IS_ERR(info->cpu_clk)) ++ } ++ if (!IS_ERR(info->cpu_clk)) { ++ clk_disable_unprepare(info->cpu_clk); + clk_put(info->cpu_clk); +- if (!IS_ERR(info->inter_clk)) ++ } ++ if (!IS_ERR(info->inter_clk)) { ++ clk_disable_unprepare(info->inter_clk); + clk_put(info->inter_clk); ++ } + + dev_pm_opp_of_cpumask_remove_table(&info->cpus); + } diff --git a/target/linux/mediatek/patches-6.1/350-04-cpufreq-mediatek-Use-device-print-to-show-logs.patch b/target/linux/mediatek/patches-6.1/350-04-cpufreq-mediatek-Use-device-print-to-show-logs.patch new file mode 100644 index 00000000000..18e1da728a8 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/350-04-cpufreq-mediatek-Use-device-print-to-show-logs.patch @@ -0,0 +1,161 @@ +From a02e2b359141035d2d6999940bc1b9f83ec88587 Mon Sep 17 00:00:00 2001 +From: Rex-BC Chen +Date: Fri, 22 Apr 2022 15:52:27 +0800 +Subject: [PATCH 04/21] cpufreq: mediatek: Use device print to show logs + +- Replace pr_* with dev_* to show logs. +- Remove usage of __func__. + +Signed-off-by: Rex-BC Chen +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Viresh Kumar +--- + drivers/cpufreq/mediatek-cpufreq.c | 54 ++++++++++++++++-------------- + 1 file changed, 28 insertions(+), 26 deletions(-) + +--- a/drivers/cpufreq/mediatek-cpufreq.c ++++ b/drivers/cpufreq/mediatek-cpufreq.c +@@ -67,7 +67,8 @@ static int mtk_cpufreq_voltage_tracking( + + old_vproc = regulator_get_voltage(proc_reg); + if (old_vproc < 0) { +- pr_err("%s: invalid Vproc value: %d\n", __func__, old_vproc); ++ dev_err(info->cpu_dev, ++ "invalid Vproc value: %d\n", old_vproc); + return old_vproc; + } + /* Vsram should not exceed the maximum allowed voltage of SoC. */ +@@ -83,14 +84,14 @@ static int mtk_cpufreq_voltage_tracking( + do { + old_vsram = regulator_get_voltage(sram_reg); + if (old_vsram < 0) { +- pr_err("%s: invalid Vsram value: %d\n", +- __func__, old_vsram); ++ dev_err(info->cpu_dev, ++ "invalid Vsram value: %d\n", old_vsram); + return old_vsram; + } + old_vproc = regulator_get_voltage(proc_reg); + if (old_vproc < 0) { +- pr_err("%s: invalid Vproc value: %d\n", +- __func__, old_vproc); ++ dev_err(info->cpu_dev, ++ "invalid Vproc value: %d\n", old_vproc); + return old_vproc; + } + +@@ -138,14 +139,14 @@ static int mtk_cpufreq_voltage_tracking( + do { + old_vproc = regulator_get_voltage(proc_reg); + if (old_vproc < 0) { +- pr_err("%s: invalid Vproc value: %d\n", +- __func__, old_vproc); ++ dev_err(info->cpu_dev, ++ "invalid Vproc value: %d\n", old_vproc); + return old_vproc; + } + old_vsram = regulator_get_voltage(sram_reg); + if (old_vsram < 0) { +- pr_err("%s: invalid Vsram value: %d\n", +- __func__, old_vsram); ++ dev_err(info->cpu_dev, ++ "invalid Vsram value: %d\n", old_vsram); + return old_vsram; + } + +@@ -216,7 +217,7 @@ static int mtk_cpufreq_set_target(struct + old_freq_hz = clk_get_rate(cpu_clk); + old_vproc = regulator_get_voltage(info->proc_reg); + if (old_vproc < 0) { +- pr_err("%s: invalid Vproc value: %d\n", __func__, old_vproc); ++ dev_err(cpu_dev, "invalid Vproc value: %d\n", old_vproc); + return old_vproc; + } + +@@ -224,8 +225,8 @@ static int mtk_cpufreq_set_target(struct + + opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz); + if (IS_ERR(opp)) { +- pr_err("cpu%d: failed to find OPP for %ld\n", +- policy->cpu, freq_hz); ++ dev_err(cpu_dev, "cpu%d: failed to find OPP for %ld\n", ++ policy->cpu, freq_hz); + return PTR_ERR(opp); + } + vproc = dev_pm_opp_get_voltage(opp); +@@ -239,8 +240,8 @@ static int mtk_cpufreq_set_target(struct + if (old_vproc < target_vproc) { + ret = mtk_cpufreq_set_voltage(info, target_vproc); + if (ret) { +- pr_err("cpu%d: failed to scale up voltage!\n", +- policy->cpu); ++ dev_err(cpu_dev, ++ "cpu%d: failed to scale up voltage!\n", policy->cpu); + mtk_cpufreq_set_voltage(info, old_vproc); + return ret; + } +@@ -249,8 +250,8 @@ static int mtk_cpufreq_set_target(struct + /* Reparent the CPU clock to intermediate clock. */ + ret = clk_set_parent(cpu_clk, info->inter_clk); + if (ret) { +- pr_err("cpu%d: failed to re-parent cpu clock!\n", +- policy->cpu); ++ dev_err(cpu_dev, ++ "cpu%d: failed to re-parent cpu clock!\n", policy->cpu); + mtk_cpufreq_set_voltage(info, old_vproc); + WARN_ON(1); + return ret; +@@ -259,8 +260,8 @@ static int mtk_cpufreq_set_target(struct + /* Set the original PLL to target rate. */ + ret = clk_set_rate(armpll, freq_hz); + if (ret) { +- pr_err("cpu%d: failed to scale cpu clock rate!\n", +- policy->cpu); ++ dev_err(cpu_dev, ++ "cpu%d: failed to scale cpu clock rate!\n", policy->cpu); + clk_set_parent(cpu_clk, armpll); + mtk_cpufreq_set_voltage(info, old_vproc); + return ret; +@@ -269,8 +270,8 @@ static int mtk_cpufreq_set_target(struct + /* Set parent of CPU clock back to the original PLL. */ + ret = clk_set_parent(cpu_clk, armpll); + if (ret) { +- pr_err("cpu%d: failed to re-parent cpu clock!\n", +- policy->cpu); ++ dev_err(cpu_dev, ++ "cpu%d: failed to re-parent cpu clock!\n", policy->cpu); + mtk_cpufreq_set_voltage(info, inter_vproc); + WARN_ON(1); + return ret; +@@ -283,8 +284,8 @@ static int mtk_cpufreq_set_target(struct + if (vproc < inter_vproc || vproc < old_vproc) { + ret = mtk_cpufreq_set_voltage(info, vproc); + if (ret) { +- pr_err("cpu%d: failed to scale down voltage!\n", +- policy->cpu); ++ dev_err(cpu_dev, ++ "cpu%d: failed to scale down voltage!\n", policy->cpu); + clk_set_parent(cpu_clk, info->inter_clk); + clk_set_rate(armpll, old_freq_hz); + clk_set_parent(cpu_clk, armpll); +@@ -450,15 +451,16 @@ static int mtk_cpufreq_init(struct cpufr + + info = mtk_cpu_dvfs_info_lookup(policy->cpu); + if (!info) { +- pr_err("dvfs info for cpu%d is not initialized.\n", +- policy->cpu); ++ dev_err(info->cpu_dev, ++ "dvfs info for cpu%d is not initialized.\n", policy->cpu); + return -EINVAL; + } + + ret = dev_pm_opp_init_cpufreq_table(info->cpu_dev, &freq_table); + if (ret) { +- pr_err("failed to init cpufreq table for cpu%d: %d\n", +- policy->cpu, ret); ++ dev_err(info->cpu_dev, ++ "failed to init cpufreq table for cpu%d: %d\n", ++ policy->cpu, ret); + return ret; + } + diff --git a/target/linux/mediatek/patches-6.1/350-05-cpufreq-mediatek-Replace-old_-with-pre_.patch b/target/linux/mediatek/patches-6.1/350-05-cpufreq-mediatek-Replace-old_-with-pre_.patch new file mode 100644 index 00000000000..8506f4e4776 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/350-05-cpufreq-mediatek-Replace-old_-with-pre_.patch @@ -0,0 +1,201 @@ +From 35832d9f9c5c1da01420d962dc56e7e61d104829 Mon Sep 17 00:00:00 2001 +From: Rex-BC Chen +Date: Fri, 22 Apr 2022 15:52:28 +0800 +Subject: [PATCH 05/21] cpufreq: mediatek: Replace old_* with pre_* + +To make driver more readable, replace old_* with pre_*. + +Signed-off-by: Rex-BC Chen +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Viresh Kumar +--- + drivers/cpufreq/mediatek-cpufreq.c | 84 +++++++++++++++--------------- + 1 file changed, 42 insertions(+), 42 deletions(-) + +--- a/drivers/cpufreq/mediatek-cpufreq.c ++++ b/drivers/cpufreq/mediatek-cpufreq.c +@@ -63,18 +63,18 @@ static int mtk_cpufreq_voltage_tracking( + { + struct regulator *proc_reg = info->proc_reg; + struct regulator *sram_reg = info->sram_reg; +- int old_vproc, old_vsram, new_vsram, vsram, vproc, ret; ++ int pre_vproc, pre_vsram, new_vsram, vsram, vproc, ret; + +- old_vproc = regulator_get_voltage(proc_reg); +- if (old_vproc < 0) { ++ pre_vproc = regulator_get_voltage(proc_reg); ++ if (pre_vproc < 0) { + dev_err(info->cpu_dev, +- "invalid Vproc value: %d\n", old_vproc); +- return old_vproc; ++ "invalid Vproc value: %d\n", pre_vproc); ++ return pre_vproc; + } + /* Vsram should not exceed the maximum allowed voltage of SoC. */ + new_vsram = min(new_vproc + MIN_VOLT_SHIFT, MAX_VOLT_LIMIT); + +- if (old_vproc < new_vproc) { ++ if (pre_vproc < new_vproc) { + /* + * When scaling up voltages, Vsram and Vproc scale up step + * by step. At each step, set Vsram to (Vproc + 200mV) first, +@@ -82,20 +82,20 @@ static int mtk_cpufreq_voltage_tracking( + * Keep doing it until Vsram and Vproc hit target voltages. + */ + do { +- old_vsram = regulator_get_voltage(sram_reg); +- if (old_vsram < 0) { ++ pre_vsram = regulator_get_voltage(sram_reg); ++ if (pre_vsram < 0) { + dev_err(info->cpu_dev, +- "invalid Vsram value: %d\n", old_vsram); +- return old_vsram; ++ "invalid Vsram value: %d\n", pre_vsram); ++ return pre_vsram; + } +- old_vproc = regulator_get_voltage(proc_reg); +- if (old_vproc < 0) { ++ pre_vproc = regulator_get_voltage(proc_reg); ++ if (pre_vproc < 0) { + dev_err(info->cpu_dev, +- "invalid Vproc value: %d\n", old_vproc); +- return old_vproc; ++ "invalid Vproc value: %d\n", pre_vproc); ++ return pre_vproc; + } + +- vsram = min(new_vsram, old_vproc + MAX_VOLT_SHIFT); ++ vsram = min(new_vsram, pre_vproc + MAX_VOLT_SHIFT); + + if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) { + vsram = MAX_VOLT_LIMIT; +@@ -124,12 +124,12 @@ static int mtk_cpufreq_voltage_tracking( + ret = regulator_set_voltage(proc_reg, vproc, + vproc + VOLT_TOL); + if (ret) { +- regulator_set_voltage(sram_reg, old_vsram, +- old_vsram); ++ regulator_set_voltage(sram_reg, pre_vsram, ++ pre_vsram); + return ret; + } + } while (vproc < new_vproc || vsram < new_vsram); +- } else if (old_vproc > new_vproc) { ++ } else if (pre_vproc > new_vproc) { + /* + * When scaling down voltages, Vsram and Vproc scale down step + * by step. At each step, set Vproc to (Vsram - 200mV) first, +@@ -137,20 +137,20 @@ static int mtk_cpufreq_voltage_tracking( + * Keep doing it until Vsram and Vproc hit target voltages. + */ + do { +- old_vproc = regulator_get_voltage(proc_reg); +- if (old_vproc < 0) { ++ pre_vproc = regulator_get_voltage(proc_reg); ++ if (pre_vproc < 0) { + dev_err(info->cpu_dev, +- "invalid Vproc value: %d\n", old_vproc); +- return old_vproc; ++ "invalid Vproc value: %d\n", pre_vproc); ++ return pre_vproc; + } +- old_vsram = regulator_get_voltage(sram_reg); +- if (old_vsram < 0) { ++ pre_vsram = regulator_get_voltage(sram_reg); ++ if (pre_vsram < 0) { + dev_err(info->cpu_dev, +- "invalid Vsram value: %d\n", old_vsram); +- return old_vsram; ++ "invalid Vsram value: %d\n", pre_vsram); ++ return pre_vsram; + } + +- vproc = max(new_vproc, old_vsram - MAX_VOLT_SHIFT); ++ vproc = max(new_vproc, pre_vsram - MAX_VOLT_SHIFT); + ret = regulator_set_voltage(proc_reg, vproc, + vproc + VOLT_TOL); + if (ret) +@@ -180,8 +180,8 @@ static int mtk_cpufreq_voltage_tracking( + } + + if (ret) { +- regulator_set_voltage(proc_reg, old_vproc, +- old_vproc); ++ regulator_set_voltage(proc_reg, pre_vproc, ++ pre_vproc); + return ret; + } + } while (vproc > new_vproc + VOLT_TOL || +@@ -209,16 +209,16 @@ static int mtk_cpufreq_set_target(struct + struct mtk_cpu_dvfs_info *info = policy->driver_data; + struct device *cpu_dev = info->cpu_dev; + struct dev_pm_opp *opp; +- long freq_hz, old_freq_hz; +- int vproc, old_vproc, inter_vproc, target_vproc, ret; ++ long freq_hz, pre_freq_hz; ++ int vproc, pre_vproc, inter_vproc, target_vproc, ret; + + inter_vproc = info->intermediate_voltage; + +- old_freq_hz = clk_get_rate(cpu_clk); +- old_vproc = regulator_get_voltage(info->proc_reg); +- if (old_vproc < 0) { +- dev_err(cpu_dev, "invalid Vproc value: %d\n", old_vproc); +- return old_vproc; ++ pre_freq_hz = clk_get_rate(cpu_clk); ++ pre_vproc = regulator_get_voltage(info->proc_reg); ++ if (pre_vproc < 0) { ++ dev_err(cpu_dev, "invalid Vproc value: %d\n", pre_vproc); ++ return pre_vproc; + } + + freq_hz = freq_table[index].frequency * 1000; +@@ -237,12 +237,12 @@ static int mtk_cpufreq_set_target(struct + * current voltage, scale up voltage first. + */ + target_vproc = (inter_vproc > vproc) ? inter_vproc : vproc; +- if (old_vproc < target_vproc) { ++ if (pre_vproc < target_vproc) { + ret = mtk_cpufreq_set_voltage(info, target_vproc); + if (ret) { + dev_err(cpu_dev, + "cpu%d: failed to scale up voltage!\n", policy->cpu); +- mtk_cpufreq_set_voltage(info, old_vproc); ++ mtk_cpufreq_set_voltage(info, pre_vproc); + return ret; + } + } +@@ -252,7 +252,7 @@ static int mtk_cpufreq_set_target(struct + if (ret) { + dev_err(cpu_dev, + "cpu%d: failed to re-parent cpu clock!\n", policy->cpu); +- mtk_cpufreq_set_voltage(info, old_vproc); ++ mtk_cpufreq_set_voltage(info, pre_vproc); + WARN_ON(1); + return ret; + } +@@ -263,7 +263,7 @@ static int mtk_cpufreq_set_target(struct + dev_err(cpu_dev, + "cpu%d: failed to scale cpu clock rate!\n", policy->cpu); + clk_set_parent(cpu_clk, armpll); +- mtk_cpufreq_set_voltage(info, old_vproc); ++ mtk_cpufreq_set_voltage(info, pre_vproc); + return ret; + } + +@@ -281,13 +281,13 @@ static int mtk_cpufreq_set_target(struct + * If the new voltage is lower than the intermediate voltage or the + * original voltage, scale down to the new voltage. + */ +- if (vproc < inter_vproc || vproc < old_vproc) { ++ if (vproc < inter_vproc || vproc < pre_vproc) { + ret = mtk_cpufreq_set_voltage(info, vproc); + if (ret) { + dev_err(cpu_dev, + "cpu%d: failed to scale down voltage!\n", policy->cpu); + clk_set_parent(cpu_clk, info->inter_clk); +- clk_set_rate(armpll, old_freq_hz); ++ clk_set_rate(armpll, pre_freq_hz); + clk_set_parent(cpu_clk, armpll); + return ret; + } diff --git a/target/linux/mediatek/patches-6.1/350-06-cpufreq-mediatek-Record-previous-target-vproc-value.patch b/target/linux/mediatek/patches-6.1/350-06-cpufreq-mediatek-Record-previous-target-vproc-value.patch new file mode 100644 index 00000000000..94e6617d267 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/350-06-cpufreq-mediatek-Record-previous-target-vproc-value.patch @@ -0,0 +1,64 @@ +From 34737eb8d0daa0d4183f10286a2f55d8788066bc Mon Sep 17 00:00:00 2001 +From: Jia-Wei Chang +Date: Fri, 22 Apr 2022 15:52:29 +0800 +Subject: [PATCH 06/21] cpufreq: mediatek: Record previous target vproc value + +We found the buck voltage may not be exactly the same with what we set +because CPU may share the same buck with other module. +Therefore, we need to record the previous desired value instead of reading +it from regulators. + +Signed-off-by: Andrew-sh.Cheng +Signed-off-by: Jia-Wei Chang +Signed-off-by: Rex-BC Chen +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Viresh Kumar +--- + drivers/cpufreq/mediatek-cpufreq.c | 20 ++++++++++++++++---- + 1 file changed, 16 insertions(+), 4 deletions(-) + +--- a/drivers/cpufreq/mediatek-cpufreq.c ++++ b/drivers/cpufreq/mediatek-cpufreq.c +@@ -40,6 +40,7 @@ struct mtk_cpu_dvfs_info { + struct list_head list_head; + int intermediate_voltage; + bool need_voltage_tracking; ++ int pre_vproc; + }; + + static struct platform_device *cpufreq_pdev; +@@ -193,11 +194,17 @@ static int mtk_cpufreq_voltage_tracking( + + static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc) + { ++ int ret; ++ + if (info->need_voltage_tracking) +- return mtk_cpufreq_voltage_tracking(info, vproc); ++ ret = mtk_cpufreq_voltage_tracking(info, vproc); + else +- return regulator_set_voltage(info->proc_reg, vproc, +- vproc + VOLT_TOL); ++ ret = regulator_set_voltage(info->proc_reg, vproc, ++ MAX_VOLT_LIMIT); ++ if (!ret) ++ info->pre_vproc = vproc; ++ ++ return ret; + } + + static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, +@@ -215,7 +222,12 @@ static int mtk_cpufreq_set_target(struct + inter_vproc = info->intermediate_voltage; + + pre_freq_hz = clk_get_rate(cpu_clk); +- pre_vproc = regulator_get_voltage(info->proc_reg); ++ ++ if (unlikely(info->pre_vproc <= 0)) ++ pre_vproc = regulator_get_voltage(info->proc_reg); ++ else ++ pre_vproc = info->pre_vproc; ++ + if (pre_vproc < 0) { + dev_err(cpu_dev, "invalid Vproc value: %d\n", pre_vproc); + return pre_vproc; diff --git a/target/linux/mediatek/patches-6.1/350-07-cpufreq-mediatek-Make-sram-regulator-optional.patch b/target/linux/mediatek/patches-6.1/350-07-cpufreq-mediatek-Make-sram-regulator-optional.patch new file mode 100644 index 00000000000..4b74873b158 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/350-07-cpufreq-mediatek-Make-sram-regulator-optional.patch @@ -0,0 +1,30 @@ +From f6114c2bc563a8050e9dc874ad87e1448865f031 Mon Sep 17 00:00:00 2001 +From: Jia-Wei Chang +Date: Fri, 22 Apr 2022 15:52:33 +0800 +Subject: [PATCH 07/21] cpufreq: mediatek: Make sram regulator optional + +For some MediaTek SoCs, like MT8186, it's possible that the sram regulator +is shared between CPU and CCI. +We hope regulator framework can return error for error handling rather +than a dummy handler from regulator_get api. +Therefore, we choose to use regulator_get_optional. + +Signed-off-by: Jia-Wei Chang +Signed-off-by: Rex-BC Chen +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Viresh Kumar +--- + drivers/cpufreq/mediatek-cpufreq.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/cpufreq/mediatek-cpufreq.c ++++ b/drivers/cpufreq/mediatek-cpufreq.c +@@ -354,7 +354,7 @@ static int mtk_cpu_dvfs_info_init(struct + } + + /* Both presence and absence of sram regulator are valid cases. */ +- info->sram_reg = regulator_get_exclusive(cpu_dev, "sram"); ++ info->sram_reg = regulator_get_optional(cpu_dev, "sram"); + if (IS_ERR(info->sram_reg)) + info->sram_reg = NULL; + else { diff --git a/target/linux/mediatek/patches-6.1/350-08-cpufreq-mediatek-Fix-NULL-pointer-dereference-in-med.patch b/target/linux/mediatek/patches-6.1/350-08-cpufreq-mediatek-Fix-NULL-pointer-dereference-in-med.patch new file mode 100644 index 00000000000..f2f572a753f --- /dev/null +++ b/target/linux/mediatek/patches-6.1/350-08-cpufreq-mediatek-Fix-NULL-pointer-dereference-in-med.patch @@ -0,0 +1,32 @@ +From fa7030d8ad4638acfd9e0fac84a20716d031dc95 Mon Sep 17 00:00:00 2001 +From: Wan Jiabing +Date: Tue, 26 Apr 2022 19:17:14 +0800 +Subject: [PATCH 08/21] cpufreq: mediatek: Fix NULL pointer dereference in + mediatek-cpufreq + +Fix following coccicheck error: +drivers/cpufreq/mediatek-cpufreq.c:464:16-23: ERROR: info is NULL but dereferenced. + +Use pr_err instead of dev_err to avoid dereferring a NULL pointer. + +Fixes: f52b16ba9fe4 ("cpufreq: mediatek: Use device print to show logs") +Signed-off-by: Wan Jiabing +Reviewed-by: Matthias Brugger +Signed-off-by: Viresh Kumar +--- + drivers/cpufreq/mediatek-cpufreq.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/cpufreq/mediatek-cpufreq.c ++++ b/drivers/cpufreq/mediatek-cpufreq.c +@@ -463,8 +463,8 @@ static int mtk_cpufreq_init(struct cpufr + + info = mtk_cpu_dvfs_info_lookup(policy->cpu); + if (!info) { +- dev_err(info->cpu_dev, +- "dvfs info for cpu%d is not initialized.\n", policy->cpu); ++ pr_err("dvfs info for cpu%d is not initialized.\n", ++ policy->cpu); + return -EINVAL; + } + diff --git a/target/linux/mediatek/patches-6.1/350-09-cpufreq-mediatek-Move-voltage-limits-to-platform-dat.patch b/target/linux/mediatek/patches-6.1/350-09-cpufreq-mediatek-Move-voltage-limits-to-platform-dat.patch new file mode 100644 index 00000000000..23b319648dc --- /dev/null +++ b/target/linux/mediatek/patches-6.1/350-09-cpufreq-mediatek-Move-voltage-limits-to-platform-dat.patch @@ -0,0 +1,227 @@ +From be2354b064e6bafbbad599ae2e10569ba4f7d5a6 Mon Sep 17 00:00:00 2001 +From: Rex-BC Chen +Date: Thu, 5 May 2022 19:52:19 +0800 +Subject: [PATCH 09/21] cpufreq: mediatek: Move voltage limits to platform data + +Voltages and shifts are defined as macros originally. +There are different requirements of these values for each MediaTek SoCs. +Therefore, we add the platform data and move these values into it. + +Signed-off-by: Jia-Wei Chang +Signed-off-by: Rex-BC Chen +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Viresh Kumar +--- + drivers/cpufreq/mediatek-cpufreq.c | 84 +++++++++++++++++++++--------- + 1 file changed, 58 insertions(+), 26 deletions(-) + +--- a/drivers/cpufreq/mediatek-cpufreq.c ++++ b/drivers/cpufreq/mediatek-cpufreq.c +@@ -10,15 +10,21 @@ + #include + #include + #include ++#include + #include + #include + #include + +-#define MIN_VOLT_SHIFT (100000) +-#define MAX_VOLT_SHIFT (200000) +-#define MAX_VOLT_LIMIT (1150000) + #define VOLT_TOL (10000) + ++struct mtk_cpufreq_platform_data { ++ int min_volt_shift; ++ int max_volt_shift; ++ int proc_max_volt; ++ int sram_min_volt; ++ int sram_max_volt; ++}; ++ + /* + * The struct mtk_cpu_dvfs_info holds necessary information for doing CPU DVFS + * on each CPU power/clock domain of Mediatek SoCs. Each CPU cluster in +@@ -41,6 +47,7 @@ struct mtk_cpu_dvfs_info { + int intermediate_voltage; + bool need_voltage_tracking; + int pre_vproc; ++ const struct mtk_cpufreq_platform_data *soc_data; + }; + + static struct platform_device *cpufreq_pdev; +@@ -62,6 +69,7 @@ static struct mtk_cpu_dvfs_info *mtk_cpu + static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, + int new_vproc) + { ++ const struct mtk_cpufreq_platform_data *soc_data = info->soc_data; + struct regulator *proc_reg = info->proc_reg; + struct regulator *sram_reg = info->sram_reg; + int pre_vproc, pre_vsram, new_vsram, vsram, vproc, ret; +@@ -73,7 +81,8 @@ static int mtk_cpufreq_voltage_tracking( + return pre_vproc; + } + /* Vsram should not exceed the maximum allowed voltage of SoC. */ +- new_vsram = min(new_vproc + MIN_VOLT_SHIFT, MAX_VOLT_LIMIT); ++ new_vsram = min(new_vproc + soc_data->min_volt_shift, ++ soc_data->sram_max_volt); + + if (pre_vproc < new_vproc) { + /* +@@ -96,10 +105,11 @@ static int mtk_cpufreq_voltage_tracking( + return pre_vproc; + } + +- vsram = min(new_vsram, pre_vproc + MAX_VOLT_SHIFT); ++ vsram = min(new_vsram, ++ pre_vproc + soc_data->min_volt_shift); + +- if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) { +- vsram = MAX_VOLT_LIMIT; ++ if (vsram + VOLT_TOL >= soc_data->sram_max_volt) { ++ vsram = soc_data->sram_max_volt; + + /* + * If the target Vsram hits the maximum voltage, +@@ -117,7 +127,7 @@ static int mtk_cpufreq_voltage_tracking( + ret = regulator_set_voltage(sram_reg, vsram, + vsram + VOLT_TOL); + +- vproc = vsram - MIN_VOLT_SHIFT; ++ vproc = vsram - soc_data->min_volt_shift; + } + if (ret) + return ret; +@@ -151,7 +161,8 @@ static int mtk_cpufreq_voltage_tracking( + return pre_vsram; + } + +- vproc = max(new_vproc, pre_vsram - MAX_VOLT_SHIFT); ++ vproc = max(new_vproc, ++ pre_vsram - soc_data->max_volt_shift); + ret = regulator_set_voltage(proc_reg, vproc, + vproc + VOLT_TOL); + if (ret) +@@ -160,10 +171,11 @@ static int mtk_cpufreq_voltage_tracking( + if (vproc == new_vproc) + vsram = new_vsram; + else +- vsram = max(new_vsram, vproc + MIN_VOLT_SHIFT); ++ vsram = max(new_vsram, ++ vproc + soc_data->min_volt_shift); + +- if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) { +- vsram = MAX_VOLT_LIMIT; ++ if (vsram + VOLT_TOL >= soc_data->sram_max_volt) { ++ vsram = soc_data->sram_max_volt; + + /* + * If the target Vsram hits the maximum voltage, +@@ -194,13 +206,14 @@ static int mtk_cpufreq_voltage_tracking( + + static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc) + { ++ const struct mtk_cpufreq_platform_data *soc_data = info->soc_data; + int ret; + + if (info->need_voltage_tracking) + ret = mtk_cpufreq_voltage_tracking(info, vproc); + else + ret = regulator_set_voltage(info->proc_reg, vproc, +- MAX_VOLT_LIMIT); ++ soc_data->proc_max_volt); + if (!ret) + info->pre_vproc = vproc; + +@@ -509,9 +522,17 @@ static struct cpufreq_driver mtk_cpufreq + + static int mtk_cpufreq_probe(struct platform_device *pdev) + { ++ const struct mtk_cpufreq_platform_data *data; + struct mtk_cpu_dvfs_info *info, *tmp; + int cpu, ret; + ++ data = dev_get_platdata(&pdev->dev); ++ if (!data) { ++ dev_err(&pdev->dev, ++ "failed to get mtk cpufreq platform data\n"); ++ return -ENODEV; ++ } ++ + for_each_possible_cpu(cpu) { + info = mtk_cpu_dvfs_info_lookup(cpu); + if (info) +@@ -523,6 +544,7 @@ static int mtk_cpufreq_probe(struct plat + goto release_dvfs_info_list; + } + ++ info->soc_data = data; + ret = mtk_cpu_dvfs_info_init(info, cpu); + if (ret) { + dev_err(&pdev->dev, +@@ -558,20 +580,27 @@ static struct platform_driver mtk_cpufre + .probe = mtk_cpufreq_probe, + }; + ++static const struct mtk_cpufreq_platform_data mt2701_platform_data = { ++ .min_volt_shift = 100000, ++ .max_volt_shift = 200000, ++ .proc_max_volt = 1150000, ++ .sram_min_volt = 0, ++ .sram_max_volt = 1150000, ++}; ++ + /* List of machines supported by this driver */ + static const struct of_device_id mtk_cpufreq_machines[] __initconst = { +- { .compatible = "mediatek,mt2701", }, +- { .compatible = "mediatek,mt2712", }, +- { .compatible = "mediatek,mt7622", }, +- { .compatible = "mediatek,mt7623", }, +- { .compatible = "mediatek,mt8167", }, +- { .compatible = "mediatek,mt817x", }, +- { .compatible = "mediatek,mt8173", }, +- { .compatible = "mediatek,mt8176", }, +- { .compatible = "mediatek,mt8183", }, +- { .compatible = "mediatek,mt8365", }, +- { .compatible = "mediatek,mt8516", }, +- ++ { .compatible = "mediatek,mt2701", .data = &mt2701_platform_data }, ++ { .compatible = "mediatek,mt2712", .data = &mt2701_platform_data }, ++ { .compatible = "mediatek,mt7622", .data = &mt2701_platform_data }, ++ { .compatible = "mediatek,mt7623", .data = &mt2701_platform_data }, ++ { .compatible = "mediatek,mt8167", .data = &mt2701_platform_data }, ++ { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data }, ++ { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data }, ++ { .compatible = "mediatek,mt8176", .data = &mt2701_platform_data }, ++ { .compatible = "mediatek,mt8183", .data = &mt2701_platform_data }, ++ { .compatible = "mediatek,mt8365", .data = &mt2701_platform_data }, ++ { .compatible = "mediatek,mt8516", .data = &mt2701_platform_data }, + { } + }; + MODULE_DEVICE_TABLE(of, mtk_cpufreq_machines); +@@ -580,6 +609,7 @@ static int __init mtk_cpufreq_driver_ini + { + struct device_node *np; + const struct of_device_id *match; ++ const struct mtk_cpufreq_platform_data *data; + int err; + + np = of_find_node_by_path("/"); +@@ -592,6 +622,7 @@ static int __init mtk_cpufreq_driver_ini + pr_debug("Machine is not compatible with mtk-cpufreq\n"); + return -ENODEV; + } ++ data = match->data; + + err = platform_driver_register(&mtk_cpufreq_platdrv); + if (err) +@@ -603,7 +634,8 @@ static int __init mtk_cpufreq_driver_ini + * and the device registration codes are put here to handle defer + * probing. + */ +- cpufreq_pdev = platform_device_register_simple("mtk-cpufreq", -1, NULL, 0); ++ cpufreq_pdev = platform_device_register_data(NULL, "mtk-cpufreq", -1, ++ data, sizeof(*data)); + if (IS_ERR(cpufreq_pdev)) { + pr_err("failed to register mtk-cpufreq platform device\n"); + platform_driver_unregister(&mtk_cpufreq_platdrv); diff --git a/target/linux/mediatek/patches-6.1/350-10-cpufreq-mediatek-Refine-mtk_cpufreq_voltage_tracking.patch b/target/linux/mediatek/patches-6.1/350-10-cpufreq-mediatek-Refine-mtk_cpufreq_voltage_tracking.patch new file mode 100644 index 00000000000..0ba9471ffa7 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/350-10-cpufreq-mediatek-Refine-mtk_cpufreq_voltage_tracking.patch @@ -0,0 +1,255 @@ +From 944b041c91f1e1cd762c39c1222f078550149486 Mon Sep 17 00:00:00 2001 +From: Jia-Wei Chang +Date: Thu, 5 May 2022 19:52:20 +0800 +Subject: [PATCH 10/21] cpufreq: mediatek: Refine + mtk_cpufreq_voltage_tracking() + +Because the difference of sram and proc should in a range of min_volt_shift +and max_volt_shift. We need to adjust the sram and proc step by step. + +We replace VOLT_TOL (voltage tolerance) with the platform data and update the +logic to determine the voltage boundary and invoking regulator_set_voltage. + +- Use 'sram_min_volt' and 'sram_max_volt' to determine the voltage boundary + of sram regulator. +- Use (sram_min_volt - min_volt_shift) and 'proc_max_volt' to determine the + voltage boundary of vproc regulator. + +Moreover, to prevent infinite loop when tracking voltage, we calculate the +maximum value for each platform data. +We assume min voltage is 0 and tracking target voltage using +min_volt_shift for each iteration. +The retry_max is 3 times of expeted iteration count. + +Signed-off-by: Jia-Wei Chang +Signed-off-by: Rex-BC Chen +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Viresh Kumar +--- + drivers/cpufreq/mediatek-cpufreq.c | 147 ++++++++++------------------- + 1 file changed, 51 insertions(+), 96 deletions(-) + +--- a/drivers/cpufreq/mediatek-cpufreq.c ++++ b/drivers/cpufreq/mediatek-cpufreq.c +@@ -8,6 +8,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -15,8 +16,6 @@ + #include + #include + +-#define VOLT_TOL (10000) +- + struct mtk_cpufreq_platform_data { + int min_volt_shift; + int max_volt_shift; +@@ -48,6 +47,7 @@ struct mtk_cpu_dvfs_info { + bool need_voltage_tracking; + int pre_vproc; + const struct mtk_cpufreq_platform_data *soc_data; ++ int vtrack_max; + }; + + static struct platform_device *cpufreq_pdev; +@@ -73,6 +73,7 @@ static int mtk_cpufreq_voltage_tracking( + struct regulator *proc_reg = info->proc_reg; + struct regulator *sram_reg = info->sram_reg; + int pre_vproc, pre_vsram, new_vsram, vsram, vproc, ret; ++ int retry = info->vtrack_max; + + pre_vproc = regulator_get_voltage(proc_reg); + if (pre_vproc < 0) { +@@ -80,91 +81,44 @@ static int mtk_cpufreq_voltage_tracking( + "invalid Vproc value: %d\n", pre_vproc); + return pre_vproc; + } +- /* Vsram should not exceed the maximum allowed voltage of SoC. */ +- new_vsram = min(new_vproc + soc_data->min_volt_shift, +- soc_data->sram_max_volt); +- +- if (pre_vproc < new_vproc) { +- /* +- * When scaling up voltages, Vsram and Vproc scale up step +- * by step. At each step, set Vsram to (Vproc + 200mV) first, +- * then set Vproc to (Vsram - 100mV). +- * Keep doing it until Vsram and Vproc hit target voltages. +- */ +- do { +- pre_vsram = regulator_get_voltage(sram_reg); +- if (pre_vsram < 0) { +- dev_err(info->cpu_dev, +- "invalid Vsram value: %d\n", pre_vsram); +- return pre_vsram; +- } +- pre_vproc = regulator_get_voltage(proc_reg); +- if (pre_vproc < 0) { +- dev_err(info->cpu_dev, +- "invalid Vproc value: %d\n", pre_vproc); +- return pre_vproc; +- } + +- vsram = min(new_vsram, +- pre_vproc + soc_data->min_volt_shift); ++ pre_vsram = regulator_get_voltage(sram_reg); ++ if (pre_vsram < 0) { ++ dev_err(info->cpu_dev, "invalid Vsram value: %d\n", pre_vsram); ++ return pre_vsram; ++ } + +- if (vsram + VOLT_TOL >= soc_data->sram_max_volt) { +- vsram = soc_data->sram_max_volt; ++ new_vsram = clamp(new_vproc + soc_data->min_volt_shift, ++ soc_data->sram_min_volt, soc_data->sram_max_volt); ++ ++ do { ++ if (pre_vproc <= new_vproc) { ++ vsram = clamp(pre_vproc + soc_data->max_volt_shift, ++ soc_data->sram_min_volt, new_vsram); ++ ret = regulator_set_voltage(sram_reg, vsram, ++ soc_data->sram_max_volt); + +- /* +- * If the target Vsram hits the maximum voltage, +- * try to set the exact voltage value first. +- */ +- ret = regulator_set_voltage(sram_reg, vsram, +- vsram); +- if (ret) +- ret = regulator_set_voltage(sram_reg, +- vsram - VOLT_TOL, +- vsram); ++ if (ret) ++ return ret; + ++ if (vsram == soc_data->sram_max_volt || ++ new_vsram == soc_data->sram_min_volt) + vproc = new_vproc; +- } else { +- ret = regulator_set_voltage(sram_reg, vsram, +- vsram + VOLT_TOL); +- ++ else + vproc = vsram - soc_data->min_volt_shift; +- } +- if (ret) +- return ret; + + ret = regulator_set_voltage(proc_reg, vproc, +- vproc + VOLT_TOL); ++ soc_data->proc_max_volt); + if (ret) { + regulator_set_voltage(sram_reg, pre_vsram, +- pre_vsram); ++ soc_data->sram_max_volt); + return ret; + } +- } while (vproc < new_vproc || vsram < new_vsram); +- } else if (pre_vproc > new_vproc) { +- /* +- * When scaling down voltages, Vsram and Vproc scale down step +- * by step. At each step, set Vproc to (Vsram - 200mV) first, +- * then set Vproc to (Vproc + 100mV). +- * Keep doing it until Vsram and Vproc hit target voltages. +- */ +- do { +- pre_vproc = regulator_get_voltage(proc_reg); +- if (pre_vproc < 0) { +- dev_err(info->cpu_dev, +- "invalid Vproc value: %d\n", pre_vproc); +- return pre_vproc; +- } +- pre_vsram = regulator_get_voltage(sram_reg); +- if (pre_vsram < 0) { +- dev_err(info->cpu_dev, +- "invalid Vsram value: %d\n", pre_vsram); +- return pre_vsram; +- } +- ++ } else if (pre_vproc > new_vproc) { + vproc = max(new_vproc, + pre_vsram - soc_data->max_volt_shift); + ret = regulator_set_voltage(proc_reg, vproc, +- vproc + VOLT_TOL); ++ soc_data->proc_max_volt); + if (ret) + return ret; + +@@ -174,32 +128,24 @@ static int mtk_cpufreq_voltage_tracking( + vsram = max(new_vsram, + vproc + soc_data->min_volt_shift); + +- if (vsram + VOLT_TOL >= soc_data->sram_max_volt) { +- vsram = soc_data->sram_max_volt; +- +- /* +- * If the target Vsram hits the maximum voltage, +- * try to set the exact voltage value first. +- */ +- ret = regulator_set_voltage(sram_reg, vsram, +- vsram); +- if (ret) +- ret = regulator_set_voltage(sram_reg, +- vsram - VOLT_TOL, +- vsram); +- } else { +- ret = regulator_set_voltage(sram_reg, vsram, +- vsram + VOLT_TOL); +- } +- ++ ret = regulator_set_voltage(sram_reg, vsram, ++ soc_data->sram_max_volt); + if (ret) { + regulator_set_voltage(proc_reg, pre_vproc, +- pre_vproc); ++ soc_data->proc_max_volt); + return ret; + } +- } while (vproc > new_vproc + VOLT_TOL || +- vsram > new_vsram + VOLT_TOL); +- } ++ } ++ ++ pre_vproc = vproc; ++ pre_vsram = vsram; ++ ++ if (--retry < 0) { ++ dev_err(info->cpu_dev, ++ "over loop count, failed to set voltage\n"); ++ return -EINVAL; ++ } ++ } while (vproc != new_vproc || vsram != new_vsram); + + return 0; + } +@@ -261,8 +207,8 @@ static int mtk_cpufreq_set_target(struct + * If the new voltage or the intermediate voltage is higher than the + * current voltage, scale up voltage first. + */ +- target_vproc = (inter_vproc > vproc) ? inter_vproc : vproc; +- if (pre_vproc < target_vproc) { ++ target_vproc = max(inter_vproc, vproc); ++ if (pre_vproc <= target_vproc) { + ret = mtk_cpufreq_set_voltage(info, target_vproc); + if (ret) { + dev_err(cpu_dev, +@@ -417,6 +363,15 @@ static int mtk_cpu_dvfs_info_init(struct + */ + info->need_voltage_tracking = (info->sram_reg != NULL); + ++ /* ++ * We assume min voltage is 0 and tracking target voltage using ++ * min_volt_shift for each iteration. ++ * The vtrack_max is 3 times of expeted iteration count. ++ */ ++ info->vtrack_max = 3 * DIV_ROUND_UP(max(info->soc_data->sram_max_volt, ++ info->soc_data->proc_max_volt), ++ info->soc_data->min_volt_shift); ++ + return 0; + + out_disable_inter_clock: diff --git a/target/linux/mediatek/patches-6.1/350-11-cpufreq-mediatek-Add-opp-notification-support.patch b/target/linux/mediatek/patches-6.1/350-11-cpufreq-mediatek-Add-opp-notification-support.patch new file mode 100644 index 00000000000..2cb99b907a6 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/350-11-cpufreq-mediatek-Add-opp-notification-support.patch @@ -0,0 +1,184 @@ +From 01be227eff7e5fc01f7c8de8f6daddd5fb17ddd1 Mon Sep 17 00:00:00 2001 +From: Rex-BC Chen +Date: Thu, 5 May 2022 19:52:21 +0800 +Subject: [PATCH 11/21] cpufreq: mediatek: Add opp notification support + +From this opp notifier, cpufreq should listen to opp notification and do +proper actions when receiving events of disable and voltage adjustment. + +One of the user for this opp notifier is MediaTek SVS. +The MediaTek Smart Voltage Scaling (SVS) is a hardware which calculates +suitable SVS bank voltages to OPP voltage table. + +Signed-off-by: Andrew-sh.Cheng +Signed-off-by: Jia-Wei Chang +Signed-off-by: Rex-BC Chen +Reviewed-by: AngeloGioacchino Del Regno +[ Viresh: Renamed opp_freq as current_freq and moved its initialization ] +Signed-off-by: Viresh Kumar +--- + drivers/cpufreq/mediatek-cpufreq.c | 90 +++++++++++++++++++++++++++--- + 1 file changed, 82 insertions(+), 8 deletions(-) + +--- a/drivers/cpufreq/mediatek-cpufreq.c ++++ b/drivers/cpufreq/mediatek-cpufreq.c +@@ -46,6 +46,11 @@ struct mtk_cpu_dvfs_info { + int intermediate_voltage; + bool need_voltage_tracking; + int pre_vproc; ++ /* Avoid race condition for regulators between notify and policy */ ++ struct mutex reg_lock; ++ struct notifier_block opp_nb; ++ unsigned int opp_cpu; ++ unsigned long current_freq; + const struct mtk_cpufreq_platform_data *soc_data; + int vtrack_max; + }; +@@ -182,6 +187,8 @@ static int mtk_cpufreq_set_target(struct + + pre_freq_hz = clk_get_rate(cpu_clk); + ++ mutex_lock(&info->reg_lock); ++ + if (unlikely(info->pre_vproc <= 0)) + pre_vproc = regulator_get_voltage(info->proc_reg); + else +@@ -214,7 +221,7 @@ static int mtk_cpufreq_set_target(struct + dev_err(cpu_dev, + "cpu%d: failed to scale up voltage!\n", policy->cpu); + mtk_cpufreq_set_voltage(info, pre_vproc); +- return ret; ++ goto out; + } + } + +@@ -224,8 +231,7 @@ static int mtk_cpufreq_set_target(struct + dev_err(cpu_dev, + "cpu%d: failed to re-parent cpu clock!\n", policy->cpu); + mtk_cpufreq_set_voltage(info, pre_vproc); +- WARN_ON(1); +- return ret; ++ goto out; + } + + /* Set the original PLL to target rate. */ +@@ -235,7 +241,7 @@ static int mtk_cpufreq_set_target(struct + "cpu%d: failed to scale cpu clock rate!\n", policy->cpu); + clk_set_parent(cpu_clk, armpll); + mtk_cpufreq_set_voltage(info, pre_vproc); +- return ret; ++ goto out; + } + + /* Set parent of CPU clock back to the original PLL. */ +@@ -244,8 +250,7 @@ static int mtk_cpufreq_set_target(struct + dev_err(cpu_dev, + "cpu%d: failed to re-parent cpu clock!\n", policy->cpu); + mtk_cpufreq_set_voltage(info, inter_vproc); +- WARN_ON(1); +- return ret; ++ goto out; + } + + /* +@@ -260,15 +265,72 @@ static int mtk_cpufreq_set_target(struct + clk_set_parent(cpu_clk, info->inter_clk); + clk_set_rate(armpll, pre_freq_hz); + clk_set_parent(cpu_clk, armpll); +- return ret; ++ goto out; + } + } + +- return 0; ++ info->current_freq = freq_hz; ++ ++out: ++ mutex_unlock(&info->reg_lock); ++ ++ return ret; + } + + #define DYNAMIC_POWER "dynamic-power-coefficient" + ++static int mtk_cpufreq_opp_notifier(struct notifier_block *nb, ++ unsigned long event, void *data) ++{ ++ struct dev_pm_opp *opp = data; ++ struct dev_pm_opp *new_opp; ++ struct mtk_cpu_dvfs_info *info; ++ unsigned long freq, volt; ++ struct cpufreq_policy *policy; ++ int ret = 0; ++ ++ info = container_of(nb, struct mtk_cpu_dvfs_info, opp_nb); ++ ++ if (event == OPP_EVENT_ADJUST_VOLTAGE) { ++ freq = dev_pm_opp_get_freq(opp); ++ ++ mutex_lock(&info->reg_lock); ++ if (info->current_freq == freq) { ++ volt = dev_pm_opp_get_voltage(opp); ++ ret = mtk_cpufreq_set_voltage(info, volt); ++ if (ret) ++ dev_err(info->cpu_dev, ++ "failed to scale voltage: %d\n", ret); ++ } ++ mutex_unlock(&info->reg_lock); ++ } else if (event == OPP_EVENT_DISABLE) { ++ freq = dev_pm_opp_get_freq(opp); ++ ++ /* case of current opp item is disabled */ ++ if (info->current_freq == freq) { ++ freq = 1; ++ new_opp = dev_pm_opp_find_freq_ceil(info->cpu_dev, ++ &freq); ++ if (IS_ERR(new_opp)) { ++ dev_err(info->cpu_dev, ++ "all opp items are disabled\n"); ++ ret = PTR_ERR(new_opp); ++ return notifier_from_errno(ret); ++ } ++ ++ dev_pm_opp_put(new_opp); ++ policy = cpufreq_cpu_get(info->opp_cpu); ++ if (policy) { ++ cpufreq_driver_target(policy, freq / 1000, ++ CPUFREQ_RELATION_L); ++ cpufreq_cpu_put(policy); ++ } ++ } ++ } ++ ++ return notifier_from_errno(ret); ++} ++ + static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) + { + struct device *cpu_dev; +@@ -357,6 +419,17 @@ static int mtk_cpu_dvfs_info_init(struct + info->intermediate_voltage = dev_pm_opp_get_voltage(opp); + dev_pm_opp_put(opp); + ++ mutex_init(&info->reg_lock); ++ info->current_freq = clk_get_rate(info->cpu_clk); ++ ++ info->opp_cpu = cpu; ++ info->opp_nb.notifier_call = mtk_cpufreq_opp_notifier; ++ ret = dev_pm_opp_register_notifier(cpu_dev, &info->opp_nb); ++ if (ret) { ++ dev_err(cpu_dev, "cpu%d: failed to register opp notifier\n", cpu); ++ goto out_disable_inter_clock; ++ } ++ + /* + * If SRAM regulator is present, software "voltage tracking" is needed + * for this CPU power domain. +@@ -421,6 +494,7 @@ static void mtk_cpu_dvfs_info_release(st + } + + dev_pm_opp_of_cpumask_remove_table(&info->cpus); ++ dev_pm_opp_unregister_notifier(info->cpu_dev, &info->opp_nb); + } + + static int mtk_cpufreq_init(struct cpufreq_policy *policy) diff --git a/target/linux/mediatek/patches-6.1/350-12-cpufreq-mediatek-Fix-potential-deadlock-problem-in-m.patch b/target/linux/mediatek/patches-6.1/350-12-cpufreq-mediatek-Fix-potential-deadlock-problem-in-m.patch new file mode 100644 index 00000000000..76bd795c004 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/350-12-cpufreq-mediatek-Fix-potential-deadlock-problem-in-m.patch @@ -0,0 +1,43 @@ +From 6a1bd7cf4ed7a1948f564aaf16d34b7352c0029b Mon Sep 17 00:00:00 2001 +From: Wan Jiabing +Date: Tue, 10 May 2022 17:05:31 +0800 +Subject: [PATCH 12/21] cpufreq: mediatek: Fix potential deadlock problem in + mtk_cpufreq_set_target + +Fix following coccichek error: +./drivers/cpufreq/mediatek-cpufreq.c:199:2-8: preceding lock on line +./drivers/cpufreq/mediatek-cpufreq.c:208:2-8: preceding lock on line + +mutex_lock is acquired but not released before return. +Use 'goto out' to help releasing the mutex_lock. + +Fixes: c210063b40ac ("cpufreq: mediatek: Add opp notification support") +Signed-off-by: Wan Jiabing +Reviewed-by: Rex-BC Chen +Signed-off-by: Viresh Kumar +--- + drivers/cpufreq/mediatek-cpufreq.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +--- a/drivers/cpufreq/mediatek-cpufreq.c ++++ b/drivers/cpufreq/mediatek-cpufreq.c +@@ -196,7 +196,8 @@ static int mtk_cpufreq_set_target(struct + + if (pre_vproc < 0) { + dev_err(cpu_dev, "invalid Vproc value: %d\n", pre_vproc); +- return pre_vproc; ++ ret = pre_vproc; ++ goto out; + } + + freq_hz = freq_table[index].frequency * 1000; +@@ -205,7 +206,8 @@ static int mtk_cpufreq_set_target(struct + if (IS_ERR(opp)) { + dev_err(cpu_dev, "cpu%d: failed to find OPP for %ld\n", + policy->cpu, freq_hz); +- return PTR_ERR(opp); ++ ret = PTR_ERR(opp); ++ goto out; + } + vproc = dev_pm_opp_get_voltage(opp); + dev_pm_opp_put(opp); diff --git a/target/linux/mediatek/patches-6.1/350-13-cpufreq-mediatek-Link-CCI-device-to-CPU.patch b/target/linux/mediatek/patches-6.1/350-13-cpufreq-mediatek-Link-CCI-device-to-CPU.patch new file mode 100644 index 00000000000..eeaa466c326 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/350-13-cpufreq-mediatek-Link-CCI-device-to-CPU.patch @@ -0,0 +1,188 @@ +From 15aaf74fb734a3e69b10d00b97b322711b81e222 Mon Sep 17 00:00:00 2001 +From: Rex-BC Chen +Date: Thu, 5 May 2022 19:52:22 +0800 +Subject: [PATCH 13/21] cpufreq: mediatek: Link CCI device to CPU + +In some MediaTek SoCs, like MT8183, CPU and CCI share the same power +supplies. Cpufreq needs to check if CCI devfreq exists and wait until +CCI devfreq ready before scaling frequency. + +Before CCI devfreq is ready, we record the voltage when booting to +kernel and use the max(cpu target voltage, booting voltage) to +prevent cpufreq adjust to the lower voltage which will cause the CCI +crash because of high frequency and low voltage. + +- Add is_ccifreq_ready() to link CCI device to CPI, and CPU will start + DVFS when CCI is ready. +- Add platform data for MT8183. + +Signed-off-by: Jia-Wei Chang +Signed-off-by: Rex-BC Chen +Reviewed-by: AngeloGioacchino Del Regno +Reviewed-by: Kevin Hilman +Signed-off-by: Viresh Kumar +--- + drivers/cpufreq/mediatek-cpufreq.c | 82 +++++++++++++++++++++++++++++- + 1 file changed, 81 insertions(+), 1 deletion(-) + +--- a/drivers/cpufreq/mediatek-cpufreq.c ++++ b/drivers/cpufreq/mediatek-cpufreq.c +@@ -22,6 +22,7 @@ struct mtk_cpufreq_platform_data { + int proc_max_volt; + int sram_min_volt; + int sram_max_volt; ++ bool ccifreq_supported; + }; + + /* +@@ -38,6 +39,7 @@ struct mtk_cpufreq_platform_data { + struct mtk_cpu_dvfs_info { + struct cpumask cpus; + struct device *cpu_dev; ++ struct device *cci_dev; + struct regulator *proc_reg; + struct regulator *sram_reg; + struct clk *cpu_clk; +@@ -45,6 +47,7 @@ struct mtk_cpu_dvfs_info { + struct list_head list_head; + int intermediate_voltage; + bool need_voltage_tracking; ++ int vproc_on_boot; + int pre_vproc; + /* Avoid race condition for regulators between notify and policy */ + struct mutex reg_lock; +@@ -53,6 +56,7 @@ struct mtk_cpu_dvfs_info { + unsigned long current_freq; + const struct mtk_cpufreq_platform_data *soc_data; + int vtrack_max; ++ bool ccifreq_bound; + }; + + static struct platform_device *cpufreq_pdev; +@@ -171,6 +175,28 @@ static int mtk_cpufreq_set_voltage(struc + return ret; + } + ++static bool is_ccifreq_ready(struct mtk_cpu_dvfs_info *info) ++{ ++ struct device_link *sup_link; ++ ++ if (info->ccifreq_bound) ++ return true; ++ ++ sup_link = device_link_add(info->cpu_dev, info->cci_dev, ++ DL_FLAG_AUTOREMOVE_CONSUMER); ++ if (!sup_link) { ++ dev_err(info->cpu_dev, "cpu%d: sup_link is NULL\n", info->opp_cpu); ++ return false; ++ } ++ ++ if (sup_link->supplier->links.status != DL_DEV_DRIVER_BOUND) ++ return false; ++ ++ info->ccifreq_bound = true; ++ ++ return true; ++} ++ + static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, + unsigned int index) + { +@@ -213,6 +239,14 @@ static int mtk_cpufreq_set_target(struct + dev_pm_opp_put(opp); + + /* ++ * If MediaTek cci is supported but is not ready, we will use the value ++ * of max(target cpu voltage, booting voltage) to prevent high freqeuncy ++ * low voltage crash. ++ */ ++ if (info->soc_data->ccifreq_supported && !is_ccifreq_ready(info)) ++ vproc = max(vproc, info->vproc_on_boot); ++ ++ /* + * If the new voltage or the intermediate voltage is higher than the + * current voltage, scale up voltage first. + */ +@@ -333,6 +367,23 @@ static int mtk_cpufreq_opp_notifier(stru + return notifier_from_errno(ret); + } + ++static struct device *of_get_cci(struct device *cpu_dev) ++{ ++ struct device_node *np; ++ struct platform_device *pdev; ++ ++ np = of_parse_phandle(cpu_dev->of_node, "mediatek,cci", 0); ++ if (IS_ERR_OR_NULL(np)) ++ return NULL; ++ ++ pdev = of_find_device_by_node(np); ++ of_node_put(np); ++ if (IS_ERR_OR_NULL(pdev)) ++ return NULL; ++ ++ return &pdev->dev; ++} ++ + static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) + { + struct device *cpu_dev; +@@ -347,6 +398,16 @@ static int mtk_cpu_dvfs_info_init(struct + } + info->cpu_dev = cpu_dev; + ++ info->ccifreq_bound = false; ++ if (info->soc_data->ccifreq_supported) { ++ info->cci_dev = of_get_cci(info->cpu_dev); ++ if (IS_ERR_OR_NULL(info->cci_dev)) { ++ ret = PTR_ERR(info->cci_dev); ++ dev_err(cpu_dev, "cpu%d: failed to get cci device\n", cpu); ++ return -ENODEV; ++ } ++ } ++ + info->cpu_clk = clk_get(cpu_dev, "cpu"); + if (IS_ERR(info->cpu_clk)) { + ret = PTR_ERR(info->cpu_clk); +@@ -410,6 +471,15 @@ static int mtk_cpu_dvfs_info_init(struct + if (ret) + goto out_disable_mux_clock; + ++ if (info->soc_data->ccifreq_supported) { ++ info->vproc_on_boot = regulator_get_voltage(info->proc_reg); ++ if (info->vproc_on_boot < 0) { ++ dev_err(info->cpu_dev, ++ "invalid Vproc value: %d\n", info->vproc_on_boot); ++ goto out_disable_inter_clock; ++ } ++ } ++ + /* Search a safe voltage for intermediate frequency. */ + rate = clk_get_rate(info->inter_clk); + opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate); +@@ -617,6 +687,16 @@ static const struct mtk_cpufreq_platform + .proc_max_volt = 1150000, + .sram_min_volt = 0, + .sram_max_volt = 1150000, ++ .ccifreq_supported = false, ++}; ++ ++static const struct mtk_cpufreq_platform_data mt8183_platform_data = { ++ .min_volt_shift = 100000, ++ .max_volt_shift = 200000, ++ .proc_max_volt = 1150000, ++ .sram_min_volt = 0, ++ .sram_max_volt = 1150000, ++ .ccifreq_supported = true, + }; + + /* List of machines supported by this driver */ +@@ -629,7 +709,7 @@ static const struct of_device_id mtk_cpu + { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt8176", .data = &mt2701_platform_data }, +- { .compatible = "mediatek,mt8183", .data = &mt2701_platform_data }, ++ { .compatible = "mediatek,mt8183", .data = &mt8183_platform_data }, + { .compatible = "mediatek,mt8365", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt8516", .data = &mt2701_platform_data }, + { } diff --git a/target/linux/mediatek/patches-6.1/350-14-cpufreq-mediatek-Add-support-for-MT8186.patch b/target/linux/mediatek/patches-6.1/350-14-cpufreq-mediatek-Add-support-for-MT8186.patch new file mode 100644 index 00000000000..31000cfbe05 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/350-14-cpufreq-mediatek-Add-support-for-MT8186.patch @@ -0,0 +1,42 @@ +From b6be0baa6615afc65c3963adab674e36af1d4d5f Mon Sep 17 00:00:00 2001 +From: Jia-Wei Chang +Date: Thu, 5 May 2022 19:52:23 +0800 +Subject: [PATCH 14/21] cpufreq: mediatek: Add support for MT8186 + +The platform data of MT8186 is different from previous MediaTek SoCs, +so we add a new compatible and platform data for it. + +Signed-off-by: Jia-Wei Chang +Signed-off-by: Rex-BC Chen +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Viresh Kumar +--- + drivers/cpufreq/mediatek-cpufreq.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/drivers/cpufreq/mediatek-cpufreq.c ++++ b/drivers/cpufreq/mediatek-cpufreq.c +@@ -699,6 +699,15 @@ static const struct mtk_cpufreq_platform + .ccifreq_supported = true, + }; + ++static const struct mtk_cpufreq_platform_data mt8186_platform_data = { ++ .min_volt_shift = 100000, ++ .max_volt_shift = 250000, ++ .proc_max_volt = 1118750, ++ .sram_min_volt = 850000, ++ .sram_max_volt = 1118750, ++ .ccifreq_supported = true, ++}; ++ + /* List of machines supported by this driver */ + static const struct of_device_id mtk_cpufreq_machines[] __initconst = { + { .compatible = "mediatek,mt2701", .data = &mt2701_platform_data }, +@@ -710,6 +719,7 @@ static const struct of_device_id mtk_cpu + { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt8176", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt8183", .data = &mt8183_platform_data }, ++ { .compatible = "mediatek,mt8186", .data = &mt8186_platform_data }, + { .compatible = "mediatek,mt8365", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt8516", .data = &mt2701_platform_data }, + { } diff --git a/target/linux/mediatek/patches-6.1/350-15-cpufreq-mediatek-Handle-sram-regulator-probe-deferra.patch b/target/linux/mediatek/patches-6.1/350-15-cpufreq-mediatek-Handle-sram-regulator-probe-deferra.patch new file mode 100644 index 00000000000..c0137894c93 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/350-15-cpufreq-mediatek-Handle-sram-regulator-probe-deferra.patch @@ -0,0 +1,35 @@ +From 75d19b24aa3203d6c78e4c431c2cc07157ce12fe Mon Sep 17 00:00:00 2001 +From: AngeloGioacchino Del Regno +Date: Wed, 13 Jul 2022 13:15:36 +0200 +Subject: [PATCH 15/21] cpufreq: mediatek: Handle sram regulator probe deferral + +If the regulator_get_optional() call for the SRAM regulator returns +a probe deferral, we must bail out and retry probing later: failing +to do this will produce unstabilities on platforms requiring the +handling for this regulator. + +Fixes: ffa7bdf7f344 ("cpufreq: mediatek: Make sram regulator optional") +Signed-off-by: AngeloGioacchino Del Regno +Signed-off-by: Viresh Kumar +--- + drivers/cpufreq/mediatek-cpufreq.c | 8 ++++++-- + 1 file changed, 6 insertions(+), 2 deletions(-) + +--- a/drivers/cpufreq/mediatek-cpufreq.c ++++ b/drivers/cpufreq/mediatek-cpufreq.c +@@ -439,9 +439,13 @@ static int mtk_cpu_dvfs_info_init(struct + + /* Both presence and absence of sram regulator are valid cases. */ + info->sram_reg = regulator_get_optional(cpu_dev, "sram"); +- if (IS_ERR(info->sram_reg)) ++ if (IS_ERR(info->sram_reg)) { ++ ret = PTR_ERR(info->sram_reg); ++ if (ret == -EPROBE_DEFER) ++ goto out_free_resources; ++ + info->sram_reg = NULL; +- else { ++ } else { + ret = regulator_enable(info->sram_reg); + if (ret) { + dev_warn(cpu_dev, "cpu%d: failed to enable vsram\n", cpu); diff --git a/target/linux/mediatek/patches-6.1/350-16-cpufreq-mediatek-fix-error-return-code-in-mtk_cpu_dv.patch b/target/linux/mediatek/patches-6.1/350-16-cpufreq-mediatek-fix-error-return-code-in-mtk_cpu_dv.patch new file mode 100644 index 00000000000..45c4477ff1a --- /dev/null +++ b/target/linux/mediatek/patches-6.1/350-16-cpufreq-mediatek-fix-error-return-code-in-mtk_cpu_dv.patch @@ -0,0 +1,29 @@ +From dd1174c21dacacd6c0129c1dabc5decad35c02c2 Mon Sep 17 00:00:00 2001 +From: Yang Yingliang +Date: Tue, 17 May 2022 21:34:50 +0800 +Subject: [PATCH 16/21] cpufreq: mediatek: fix error return code in + mtk_cpu_dvfs_info_init() + +If regulator_get_voltage() fails, it should return the error code in +mtk_cpu_dvfs_info_init(). + +Fixes: 0daa47325bae ("cpufreq: mediatek: Link CCI device to CPU") +Reported-by: Hulk Robot +Signed-off-by: Yang Yingliang +Reviewed-by: AngeloGioacchino Del Regno +Reviewed-by: Rex-BC Chen +Signed-off-by: Viresh Kumar +--- + drivers/cpufreq/mediatek-cpufreq.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/cpufreq/mediatek-cpufreq.c ++++ b/drivers/cpufreq/mediatek-cpufreq.c +@@ -478,6 +478,7 @@ static int mtk_cpu_dvfs_info_init(struct + if (info->soc_data->ccifreq_supported) { + info->vproc_on_boot = regulator_get_voltage(info->proc_reg); + if (info->vproc_on_boot < 0) { ++ ret = info->vproc_on_boot; + dev_err(info->cpu_dev, + "invalid Vproc value: %d\n", info->vproc_on_boot); + goto out_disable_inter_clock; diff --git a/target/linux/mediatek/patches-6.1/350-17-cpufreq-mediatek-fix-passing-zero-to-PTR_ERR.patch b/target/linux/mediatek/patches-6.1/350-17-cpufreq-mediatek-fix-passing-zero-to-PTR_ERR.patch new file mode 100644 index 00000000000..557d02b822b --- /dev/null +++ b/target/linux/mediatek/patches-6.1/350-17-cpufreq-mediatek-fix-passing-zero-to-PTR_ERR.patch @@ -0,0 +1,47 @@ +From 230a74d459244411db91bfd678f17fcf7aedfcd0 Mon Sep 17 00:00:00 2001 +From: Jia-Wei Chang +Date: Fri, 24 Mar 2023 18:11:27 +0800 +Subject: [PATCH 17/21] cpufreq: mediatek: fix passing zero to 'PTR_ERR' + +In order to prevent passing zero to 'PTR_ERR' in +mtk_cpu_dvfs_info_init(), we fix the return value of of_get_cci() using +error pointer by explicitly casting error number. + +Signed-off-by: Jia-Wei Chang +Fixes: 0daa47325bae ("cpufreq: mediatek: Link CCI device to CPU") +Reported-by: Dan Carpenter +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Viresh Kumar +--- + drivers/cpufreq/mediatek-cpufreq.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +--- a/drivers/cpufreq/mediatek-cpufreq.c ++++ b/drivers/cpufreq/mediatek-cpufreq.c +@@ -373,13 +373,13 @@ static struct device *of_get_cci(struct + struct platform_device *pdev; + + np = of_parse_phandle(cpu_dev->of_node, "mediatek,cci", 0); +- if (IS_ERR_OR_NULL(np)) +- return NULL; ++ if (!np) ++ return ERR_PTR(-ENODEV); + + pdev = of_find_device_by_node(np); + of_node_put(np); +- if (IS_ERR_OR_NULL(pdev)) +- return NULL; ++ if (!pdev) ++ return ERR_PTR(-ENODEV); + + return &pdev->dev; + } +@@ -401,7 +401,7 @@ static int mtk_cpu_dvfs_info_init(struct + info->ccifreq_bound = false; + if (info->soc_data->ccifreq_supported) { + info->cci_dev = of_get_cci(info->cpu_dev); +- if (IS_ERR_OR_NULL(info->cci_dev)) { ++ if (IS_ERR(info->cci_dev)) { + ret = PTR_ERR(info->cci_dev); + dev_err(cpu_dev, "cpu%d: failed to get cci device\n", cpu); + return -ENODEV; diff --git a/target/linux/mediatek/patches-6.1/350-18-cpufreq-mediatek-fix-KP-caused-by-handler-usage-afte.patch b/target/linux/mediatek/patches-6.1/350-18-cpufreq-mediatek-fix-KP-caused-by-handler-usage-afte.patch new file mode 100644 index 00000000000..61531d38ad2 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/350-18-cpufreq-mediatek-fix-KP-caused-by-handler-usage-afte.patch @@ -0,0 +1,149 @@ +From fced531b7c7e18192e7982637c8e8f20c29aad64 Mon Sep 17 00:00:00 2001 +From: Jia-Wei Chang +Date: Fri, 24 Mar 2023 18:11:28 +0800 +Subject: [PATCH 18/21] cpufreq: mediatek: fix KP caused by handler usage after + regulator_put/clk_put + +Any kind of failure in mtk_cpu_dvfs_info_init() will lead to calling +regulator_put() or clk_put() and the KP will occur since the regulator/clk +handlers are used after released in mtk_cpu_dvfs_info_release(). + +To prevent the usage after regulator_put()/clk_put(), the regulator/clk +handlers are addressed in a way of "Free the Last Thing Style". + +Signed-off-by: Jia-Wei Chang +Fixes: 4b9ceb757bbb ("cpufreq: mediatek: Enable clocks and regulators") +Suggested-by: AngeloGioacchino Del Regno +Suggested-by: Dan Carpenter +Signed-off-by: Viresh Kumar +--- + drivers/cpufreq/mediatek-cpufreq.c | 62 +++++++++++++++--------------- + 1 file changed, 30 insertions(+), 32 deletions(-) + +--- a/drivers/cpufreq/mediatek-cpufreq.c ++++ b/drivers/cpufreq/mediatek-cpufreq.c +@@ -420,7 +420,7 @@ static int mtk_cpu_dvfs_info_init(struct + ret = PTR_ERR(info->inter_clk); + dev_err_probe(cpu_dev, ret, + "cpu%d: failed to get intermediate clk\n", cpu); +- goto out_free_resources; ++ goto out_free_mux_clock; + } + + info->proc_reg = regulator_get_optional(cpu_dev, "proc"); +@@ -428,13 +428,13 @@ static int mtk_cpu_dvfs_info_init(struct + ret = PTR_ERR(info->proc_reg); + dev_err_probe(cpu_dev, ret, + "cpu%d: failed to get proc regulator\n", cpu); +- goto out_free_resources; ++ goto out_free_inter_clock; + } + + ret = regulator_enable(info->proc_reg); + if (ret) { + dev_warn(cpu_dev, "cpu%d: failed to enable vproc\n", cpu); +- goto out_free_resources; ++ goto out_free_proc_reg; + } + + /* Both presence and absence of sram regulator are valid cases. */ +@@ -442,14 +442,14 @@ static int mtk_cpu_dvfs_info_init(struct + if (IS_ERR(info->sram_reg)) { + ret = PTR_ERR(info->sram_reg); + if (ret == -EPROBE_DEFER) +- goto out_free_resources; ++ goto out_disable_proc_reg; + + info->sram_reg = NULL; + } else { + ret = regulator_enable(info->sram_reg); + if (ret) { + dev_warn(cpu_dev, "cpu%d: failed to enable vsram\n", cpu); +- goto out_free_resources; ++ goto out_free_sram_reg; + } + } + +@@ -458,13 +458,13 @@ static int mtk_cpu_dvfs_info_init(struct + if (ret) { + dev_err(cpu_dev, + "cpu%d: failed to get OPP-sharing information\n", cpu); +- goto out_free_resources; ++ goto out_disable_sram_reg; + } + + ret = dev_pm_opp_of_cpumask_add_table(&info->cpus); + if (ret) { + dev_warn(cpu_dev, "cpu%d: no OPP table\n", cpu); +- goto out_free_resources; ++ goto out_disable_sram_reg; + } + + ret = clk_prepare_enable(info->cpu_clk); +@@ -533,43 +533,41 @@ out_disable_mux_clock: + out_free_opp_table: + dev_pm_opp_of_cpumask_remove_table(&info->cpus); + +-out_free_resources: +- if (regulator_is_enabled(info->proc_reg)) +- regulator_disable(info->proc_reg); +- if (info->sram_reg && regulator_is_enabled(info->sram_reg)) ++out_disable_sram_reg: ++ if (info->sram_reg) + regulator_disable(info->sram_reg); + +- if (!IS_ERR(info->proc_reg)) +- regulator_put(info->proc_reg); +- if (!IS_ERR(info->sram_reg)) ++out_free_sram_reg: ++ if (info->sram_reg) + regulator_put(info->sram_reg); +- if (!IS_ERR(info->cpu_clk)) +- clk_put(info->cpu_clk); +- if (!IS_ERR(info->inter_clk)) +- clk_put(info->inter_clk); ++ ++out_disable_proc_reg: ++ regulator_disable(info->proc_reg); ++ ++out_free_proc_reg: ++ regulator_put(info->proc_reg); ++ ++out_free_inter_clock: ++ clk_put(info->inter_clk); ++ ++out_free_mux_clock: ++ clk_put(info->cpu_clk); + + return ret; + } + + static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info) + { +- if (!IS_ERR(info->proc_reg)) { +- regulator_disable(info->proc_reg); +- regulator_put(info->proc_reg); +- } +- if (!IS_ERR(info->sram_reg)) { ++ regulator_disable(info->proc_reg); ++ regulator_put(info->proc_reg); ++ if (info->sram_reg) { + regulator_disable(info->sram_reg); + regulator_put(info->sram_reg); + } +- if (!IS_ERR(info->cpu_clk)) { +- clk_disable_unprepare(info->cpu_clk); +- clk_put(info->cpu_clk); +- } +- if (!IS_ERR(info->inter_clk)) { +- clk_disable_unprepare(info->inter_clk); +- clk_put(info->inter_clk); +- } +- ++ clk_disable_unprepare(info->cpu_clk); ++ clk_put(info->cpu_clk); ++ clk_disable_unprepare(info->inter_clk); ++ clk_put(info->inter_clk); + dev_pm_opp_of_cpumask_remove_table(&info->cpus); + dev_pm_opp_unregister_notifier(info->cpu_dev, &info->opp_nb); + } diff --git a/target/linux/mediatek/patches-6.1/350-19-cpufreq-mediatek-raise-proc-sram-max-voltage-for-MT8.patch b/target/linux/mediatek/patches-6.1/350-19-cpufreq-mediatek-raise-proc-sram-max-voltage-for-MT8.patch new file mode 100644 index 00000000000..2b7d229f1c5 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/350-19-cpufreq-mediatek-raise-proc-sram-max-voltage-for-MT8.patch @@ -0,0 +1,55 @@ +From 24bc42a2d44cb821818717a5c607270921ec5d20 Mon Sep 17 00:00:00 2001 +From: Jia-Wei Chang +Date: Fri, 24 Mar 2023 18:11:29 +0800 +Subject: [PATCH 19/21] cpufreq: mediatek: raise proc/sram max voltage for + MT8516 + +Since the upper boundary of proc/sram voltage of MT8516 is 1300 mV, +which is greater than the value of MT2701 1150 mV, we fix it by adding +the corresponding platform data and specify proc/sram_max_volt to +support MT8516. + +Signed-off-by: Jia-Wei Chang +Fixes: ead858bd128d ("cpufreq: mediatek: Move voltage limits to platform data") +Fixes: 6a17b3876bc8 ("cpufreq: mediatek: Refine mtk_cpufreq_voltage_tracking()") +Reported-by: Nick Hainke +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Viresh Kumar +--- + drivers/cpufreq/mediatek-cpufreq.c | 13 +++++++++++-- + 1 file changed, 11 insertions(+), 2 deletions(-) + +--- a/drivers/cpufreq/mediatek-cpufreq.c ++++ b/drivers/cpufreq/mediatek-cpufreq.c +@@ -711,20 +711,29 @@ static const struct mtk_cpufreq_platform + .ccifreq_supported = true, + }; + ++static const struct mtk_cpufreq_platform_data mt8516_platform_data = { ++ .min_volt_shift = 100000, ++ .max_volt_shift = 200000, ++ .proc_max_volt = 1310000, ++ .sram_min_volt = 0, ++ .sram_max_volt = 1310000, ++ .ccifreq_supported = false, ++}; ++ + /* List of machines supported by this driver */ + static const struct of_device_id mtk_cpufreq_machines[] __initconst = { + { .compatible = "mediatek,mt2701", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt2712", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt7622", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt7623", .data = &mt2701_platform_data }, +- { .compatible = "mediatek,mt8167", .data = &mt2701_platform_data }, ++ { .compatible = "mediatek,mt8167", .data = &mt8516_platform_data }, + { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt8176", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt8183", .data = &mt8183_platform_data }, + { .compatible = "mediatek,mt8186", .data = &mt8186_platform_data }, + { .compatible = "mediatek,mt8365", .data = &mt2701_platform_data }, +- { .compatible = "mediatek,mt8516", .data = &mt2701_platform_data }, ++ { .compatible = "mediatek,mt8516", .data = &mt8516_platform_data }, + { } + }; + MODULE_DEVICE_TABLE(of, mtk_cpufreq_machines); diff --git a/target/linux/mediatek/patches-6.1/350-20-cpufreq-mediatek-Raise-proc-and-sram-max-voltage-for.patch b/target/linux/mediatek/patches-6.1/350-20-cpufreq-mediatek-Raise-proc-and-sram-max-voltage-for.patch new file mode 100644 index 00000000000..2de8eb6394c --- /dev/null +++ b/target/linux/mediatek/patches-6.1/350-20-cpufreq-mediatek-Raise-proc-and-sram-max-voltage-for.patch @@ -0,0 +1,58 @@ +From fe6ef09358dc0cfead9d383a8676fbe7a40fcef7 Mon Sep 17 00:00:00 2001 +From: AngeloGioacchino Del Regno +Date: Fri, 24 Mar 2023 18:11:30 +0800 +Subject: [PATCH 20/21] cpufreq: mediatek: Raise proc and sram max voltage for + MT7622/7623 + +During the addition of SRAM voltage tracking for CCI scaling, this +driver got some voltage limits set for the vtrack algorithm: these +were moved to platform data first, then enforced in a later commit +6a17b3876bc8 ("cpufreq: mediatek: Refine mtk_cpufreq_voltage_tracking()") +using these as max values for the regulator_set_voltage() calls. + +In this case, the vsram/vproc constraints for MT7622 and MT7623 +were supposed to be the same as MT2701 (and a number of other SoCs), +but that turned out to be a mistake because the aforementioned two +SoCs' maximum voltage for both VPROC and VPROC_SRAM is 1.36V. + +Fix that by adding new platform data for MT7622/7623 declaring the +right {proc,sram}_max_volt parameter. + +Fixes: ead858bd128d ("cpufreq: mediatek: Move voltage limits to platform data") +Fixes: 6a17b3876bc8 ("cpufreq: mediatek: Refine mtk_cpufreq_voltage_tracking()") +Signed-off-by: AngeloGioacchino Del Regno +Signed-off-by: Jia-Wei Chang +Signed-off-by: Viresh Kumar +--- + drivers/cpufreq/mediatek-cpufreq.c | 13 +++++++++++-- + 1 file changed, 11 insertions(+), 2 deletions(-) + +--- a/drivers/cpufreq/mediatek-cpufreq.c ++++ b/drivers/cpufreq/mediatek-cpufreq.c +@@ -693,6 +693,15 @@ static const struct mtk_cpufreq_platform + .ccifreq_supported = false, + }; + ++static const struct mtk_cpufreq_platform_data mt7622_platform_data = { ++ .min_volt_shift = 100000, ++ .max_volt_shift = 200000, ++ .proc_max_volt = 1360000, ++ .sram_min_volt = 0, ++ .sram_max_volt = 1360000, ++ .ccifreq_supported = false, ++}; ++ + static const struct mtk_cpufreq_platform_data mt8183_platform_data = { + .min_volt_shift = 100000, + .max_volt_shift = 200000, +@@ -724,8 +733,8 @@ static const struct mtk_cpufreq_platform + static const struct of_device_id mtk_cpufreq_machines[] __initconst = { + { .compatible = "mediatek,mt2701", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt2712", .data = &mt2701_platform_data }, +- { .compatible = "mediatek,mt7622", .data = &mt2701_platform_data }, +- { .compatible = "mediatek,mt7623", .data = &mt2701_platform_data }, ++ { .compatible = "mediatek,mt7622", .data = &mt7622_platform_data }, ++ { .compatible = "mediatek,mt7623", .data = &mt7622_platform_data }, + { .compatible = "mediatek,mt8167", .data = &mt8516_platform_data }, + { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data }, diff --git a/target/linux/mediatek/patches-6.1/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch b/target/linux/mediatek/patches-6.1/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch new file mode 100644 index 00000000000..6acd3d607fb --- /dev/null +++ b/target/linux/mediatek/patches-6.1/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch @@ -0,0 +1,41 @@ +From 4983a1517e7ddbc6f53fc07607e4ebeb51412843 Mon Sep 17 00:00:00 2001 +From: Sam Shih +Date: Tue, 28 Feb 2023 19:59:22 +0800 +Subject: [PATCH 21/21] cpufreq: mediatek: Add support for MT7988 + +This add cpufreq support for mediatek MT7988 SoC. + +The platform data of MT7988 is different from previous MediaTek SoCs, +so we add a new compatible and platform data for it. + +Signed-off-by: Sam Shih +--- + drivers/cpufreq/mediatek-cpufreq.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/drivers/cpufreq/mediatek-cpufreq.c ++++ b/drivers/cpufreq/mediatek-cpufreq.c +@@ -702,6 +702,15 @@ static const struct mtk_cpufreq_platform + .ccifreq_supported = false, + }; + ++static const struct mtk_cpufreq_platform_data mt7988_platform_data = { ++ .min_volt_shift = 100000, ++ .max_volt_shift = 200000, ++ .proc_max_volt = 900000, ++ .sram_min_volt = 0, ++ .sram_max_volt = 1150000, ++ .ccifreq_supported = true, ++}; ++ + static const struct mtk_cpufreq_platform_data mt8183_platform_data = { + .min_volt_shift = 100000, + .max_volt_shift = 200000, +@@ -735,6 +744,7 @@ static const struct of_device_id mtk_cpu + { .compatible = "mediatek,mt2712", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt7622", .data = &mt7622_platform_data }, + { .compatible = "mediatek,mt7623", .data = &mt7622_platform_data }, ++ { .compatible = "mediatek,mt7988", .data = &mt7988_platform_data }, + { .compatible = "mediatek,mt8167", .data = &mt8516_platform_data }, + { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data }, diff --git a/target/linux/mediatek/patches-6.1/351-cpufreq-mediatek-correct-voltages-for-MT7622-and-MT7.patch b/target/linux/mediatek/patches-6.1/351-cpufreq-mediatek-correct-voltages-for-MT7622-and-MT7.patch new file mode 100644 index 00000000000..6ab05b897c3 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/351-cpufreq-mediatek-correct-voltages-for-MT7622-and-MT7.patch @@ -0,0 +1,53 @@ +From e7697814c142c99f470c3458d49e41b25a575f23 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Fri, 26 May 2023 10:31:40 +0100 +Subject: [PATCH] cpufreq: mediatek: correct voltages for MT7622 and MT7623 + +The MT6380 regulator typically used together with MT7622 does not +support the current maximum processor and SRAM voltage in the cpufreq +driver (1360000uV). +For MT7622 limit processor and SRAM supply voltages to 1350000uV to +avoid having the tracking algorithm request unsupported voltages from +the regulator. + +On MT7623 there is no separate SRAM supply and the maximum voltage used +is 1300000uV. Create dedicated platform data for MT7623 to cover that +case as well. + +Fixes: 0883426fd07e3 ("cpufreq: mediatek: Raise proc and sram max voltage for MT7622/7623") +Suggested-by: Jia-wei Chang +Signed-off-by: Daniel Golle +--- + drivers/cpufreq/mediatek-cpufreq.c | 13 ++++++++++--- + 1 file changed, 10 insertions(+), 3 deletions(-) + +--- a/drivers/cpufreq/mediatek-cpufreq.c ++++ b/drivers/cpufreq/mediatek-cpufreq.c +@@ -696,9 +696,16 @@ static const struct mtk_cpufreq_platform + static const struct mtk_cpufreq_platform_data mt7622_platform_data = { + .min_volt_shift = 100000, + .max_volt_shift = 200000, +- .proc_max_volt = 1360000, ++ .proc_max_volt = 1350000, + .sram_min_volt = 0, +- .sram_max_volt = 1360000, ++ .sram_max_volt = 1350000, ++ .ccifreq_supported = false, ++}; ++ ++static const struct mtk_cpufreq_platform_data mt7623_platform_data = { ++ .min_volt_shift = 100000, ++ .max_volt_shift = 200000, ++ .proc_max_volt = 1300000, + .ccifreq_supported = false, + }; + +@@ -743,7 +750,7 @@ static const struct of_device_id mtk_cpu + { .compatible = "mediatek,mt2701", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt2712", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt7622", .data = &mt7622_platform_data }, +- { .compatible = "mediatek,mt7623", .data = &mt7622_platform_data }, ++ { .compatible = "mediatek,mt7623", .data = &mt7623_platform_data }, + { .compatible = "mediatek,mt7988", .data = &mt7988_platform_data }, + { .compatible = "mediatek,mt8167", .data = &mt8516_platform_data }, + { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data }, diff --git a/target/linux/mediatek/patches-6.1/400-crypto-add-eip97-inside-secure-support.patch b/target/linux/mediatek/patches-6.1/400-crypto-add-eip97-inside-secure-support.patch new file mode 100644 index 00000000000..25ca9485e41 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/400-crypto-add-eip97-inside-secure-support.patch @@ -0,0 +1,27 @@ +--- a/drivers/crypto/inside-secure/safexcel.c ++++ b/drivers/crypto/inside-secure/safexcel.c +@@ -600,6 +600,14 @@ static int safexcel_hw_init(struct safex + val |= EIP197_MST_CTRL_TX_MAX_CMD(5); + writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL); + } ++ /* ++ * Set maximum number of TX commands to 2^4 = 16 for EIP97 HW2.1/HW2.3 ++ */ ++ else { ++ val = 0; ++ val |= EIP97_MST_CTRL_TX_MAX_CMD(4); ++ writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL); ++ } + + /* Configure wr/rd cache values */ + writel(EIP197_MST_CTRL_RD_CACHE(RD_CACHE_4BITS) | +--- a/drivers/crypto/inside-secure/safexcel.h ++++ b/drivers/crypto/inside-secure/safexcel.h +@@ -315,6 +315,7 @@ + #define EIP197_MST_CTRL_RD_CACHE(n) (((n) & 0xf) << 0) + #define EIP197_MST_CTRL_WD_CACHE(n) (((n) & 0xf) << 4) + #define EIP197_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 20) ++#define EIP97_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 4) + #define EIP197_MST_CTRL_BYTE_SWAP BIT(24) + #define EIP197_MST_CTRL_NO_BYTE_SWAP BIT(25) + #define EIP197_MST_CTRL_BYTE_SWAP_BITS GENMASK(25, 24) diff --git a/target/linux/mediatek/patches-6.1/401-crypto-fix-eip97-cache-incoherent.patch b/target/linux/mediatek/patches-6.1/401-crypto-fix-eip97-cache-incoherent.patch new file mode 100644 index 00000000000..186c66f6878 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/401-crypto-fix-eip97-cache-incoherent.patch @@ -0,0 +1,26 @@ +--- a/drivers/crypto/inside-secure/safexcel.h ++++ b/drivers/crypto/inside-secure/safexcel.h +@@ -737,6 +737,9 @@ enum safexcel_eip_version { + /* Priority we use for advertising our algorithms */ + #define SAFEXCEL_CRA_PRIORITY 300 + ++/* System cache line size */ ++#define SYSTEM_CACHELINE_SIZE 64 ++ + /* SM3 digest result for zero length message */ + #define EIP197_SM3_ZEROM_HASH "\x1A\xB2\x1D\x83\x55\xCF\xA1\x7F" \ + "\x8E\x61\x19\x48\x31\xE8\x1A\x8F" \ +--- a/drivers/crypto/inside-secure/safexcel_hash.c ++++ b/drivers/crypto/inside-secure/safexcel_hash.c +@@ -55,9 +55,9 @@ struct safexcel_ahash_req { + u8 block_sz; /* block size, only set once */ + u8 digest_sz; /* output digest size, only set once */ + __le32 state[SHA3_512_BLOCK_SIZE / +- sizeof(__le32)] __aligned(sizeof(__le32)); ++ sizeof(__le32)] __aligned(SYSTEM_CACHELINE_SIZE); + +- u64 len; ++ u64 len __aligned(SYSTEM_CACHELINE_SIZE); + u64 processed; + + u8 cache[HASH_CACHE_SIZE] __aligned(sizeof(u32)); diff --git a/target/linux/mediatek/patches-6.1/405-mt7986-trng-add-rng-support.patch b/target/linux/mediatek/patches-6.1/405-mt7986-trng-add-rng-support.patch new file mode 100644 index 00000000000..332f17bae73 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/405-mt7986-trng-add-rng-support.patch @@ -0,0 +1,41 @@ +From f6ba5e17bee38f8ffe118c47fbfef3cf90eb87ff Mon Sep 17 00:00:00 2001 +From: "Mingming.Su" +Date: Wed, 30 Jun 2021 16:59:32 +0800 +Subject: [PATCH] mt7986: trng: add rng support + +1. Add trng compatible name for MT7986 +2. Fix mtk_rng_wait_ready() function + +Signed-off-by: Mingming.Su +--- + drivers/char/hw_random/mtk-rng.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/drivers/char/hw_random/mtk-rng.c ++++ b/drivers/char/hw_random/mtk-rng.c +@@ -22,7 +22,7 @@ + #define RNG_AUTOSUSPEND_TIMEOUT 100 + + #define USEC_POLL 2 +-#define TIMEOUT_POLL 20 ++#define TIMEOUT_POLL 60 + + #define RNG_CTRL 0x00 + #define RNG_EN BIT(0) +@@ -77,7 +77,7 @@ static bool mtk_rng_wait_ready(struct hw + readl_poll_timeout_atomic(priv->base + RNG_CTRL, ready, + ready & RNG_READY, USEC_POLL, + TIMEOUT_POLL); +- return !!ready; ++ return !!(ready & RNG_READY); + } + + static int mtk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait) +@@ -179,6 +179,7 @@ static const struct dev_pm_ops mtk_rng_p + #endif /* CONFIG_PM */ + + static const struct of_device_id mtk_rng_match[] = { ++ { .compatible = "mediatek,mt7986-rng" }, + { .compatible = "mediatek,mt7623-rng" }, + {}, + }; diff --git a/target/linux/mediatek/patches-6.1/410-bt-mtk-serial-fix.patch b/target/linux/mediatek/patches-6.1/410-bt-mtk-serial-fix.patch new file mode 100644 index 00000000000..3f4597c65d6 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/410-bt-mtk-serial-fix.patch @@ -0,0 +1,33 @@ +--- a/drivers/tty/serial/8250/8250.h ++++ b/drivers/tty/serial/8250/8250.h +@@ -85,6 +85,7 @@ struct serial8250_config { + #define UART_CAP_MINI BIT(17) /* Mini UART on BCM283X family lacks: + * STOP PARITY EPAR SPAR WLEN5 WLEN6 + */ ++#define UART_CAP_NMOD (1 << 18) /* UART doesn't do termios */ + + #define UART_BUG_QUOT BIT(0) /* UART has buggy quot LSB */ + #define UART_BUG_TXEN BIT(1) /* UART has buggy TX IIR status */ +--- a/drivers/tty/serial/8250/8250_port.c ++++ b/drivers/tty/serial/8250/8250_port.c +@@ -289,7 +289,7 @@ static const struct serial8250_config ua + .tx_loadsz = 16, + .fcr = UART_FCR_ENABLE_FIFO | + UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, +- .flags = UART_CAP_FIFO, ++ .flags = UART_CAP_FIFO | UART_CAP_NMOD, + }, + [PORT_NPCM] = { + .name = "Nuvoton 16550", +@@ -2766,6 +2766,11 @@ serial8250_do_set_termios(struct uart_po + unsigned long flags; + unsigned int baud, quot, frac = 0; + ++ if (up->capabilities & UART_CAP_NMOD) { ++ termios->c_cflag = 0; ++ return; ++ } ++ + if (up->capabilities & UART_CAP_MINI) { + termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR); + if ((termios->c_cflag & CSIZE) == CS5 || diff --git a/target/linux/mediatek/patches-6.1/420-mtd-spi-nor-add-support-for-Winbond-W25Q512JV.patch b/target/linux/mediatek/patches-6.1/420-mtd-spi-nor-add-support-for-Winbond-W25Q512JV.patch new file mode 100644 index 00000000000..cc9e9c55e36 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/420-mtd-spi-nor-add-support-for-Winbond-W25Q512JV.patch @@ -0,0 +1,28 @@ +From: David Bauer +To: linux-mtd@lists.infradead.org +Subject: [PATCH] mtd: spi-nor: add support for Winbond W25Q512JV +Date: Sat, 13 Feb 2021 16:10:47 +0100 + +The Winbond W25Q512JV is a 512mb SPI-NOR chip. It supports 4K +sectors as well as block protection and Dual-/Quad-read. + +Tested on: Ubiquiti UniFi 6 LR + +Signed-off-by: David Bauer +--- + drivers/mtd/spi-nor/winbond.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/mtd/spi-nor/winbond.c ++++ b/drivers/mtd/spi-nor/winbond.c +@@ -98,6 +98,10 @@ static const struct flash_info winbond_p + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { "w25q256jw", INFO(0xef6019, 0, 64 * 1024, 512, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, ++ { "w25q512jv", INFO(0xef4020, 0, 64 * 1024, 1024, ++ SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ | ++ SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | ++ SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) }, + { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024, + SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) }, + { "w25q512jvq", INFO(0xef4020, 0, 64 * 1024, 1024, diff --git a/target/linux/mediatek/patches-6.1/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch b/target/linux/mediatek/patches-6.1/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch new file mode 100644 index 00000000000..a57ee253938 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch @@ -0,0 +1,130 @@ +From bfd3acc428085742d754a6d328d1a93ebf9451df Mon Sep 17 00:00:00 2001 +From: "SkyLake.Huang" +Date: Thu, 23 Jun 2022 18:29:51 +0800 +Subject: [PATCH 1/6] drivers: spi-mt65xx: Move chip_config to driver's private + data + +Signed-off-by: SkyLake.Huang +--- + drivers/spi/spi-mt65xx.c | 29 +++++++++--------------- + include/linux/platform_data/spi-mt65xx.h | 17 -------------- + 2 files changed, 11 insertions(+), 35 deletions(-) + delete mode 100644 include/linux/platform_data/spi-mt65xx.h + +--- a/drivers/spi/spi-mt65xx.c ++++ b/drivers/spi/spi-mt65xx.c +@@ -14,7 +14,6 @@ + #include + #include + #include +-#include + #include + #include + #include +@@ -142,6 +141,8 @@ struct mtk_spi { + struct device *dev; + dma_addr_t tx_dma; + dma_addr_t rx_dma; ++ u32 sample_sel; ++ u32 get_tick_dly; + }; + + static const struct mtk_spi_compatible mtk_common_compat; +@@ -187,15 +188,6 @@ static const struct mtk_spi_compatible m + .no_need_unprepare = true, + }; + +-/* +- * A piece of default chip info unless the platform +- * supplies it. +- */ +-static const struct mtk_chip_config mtk_default_chip_info = { +- .sample_sel = 0, +- .tick_delay = 0, +-}; +- + static const struct of_device_id mtk_spi_of_match[] = { + { .compatible = "mediatek,spi-ipm", + .data = (void *)&mtk_ipm_compat, +@@ -323,7 +315,6 @@ static int mtk_spi_hw_init(struct spi_ma + { + u16 cpha, cpol; + u32 reg_val; +- struct mtk_chip_config *chip_config = spi->controller_data; + struct mtk_spi *mdata = spi_master_get_devdata(master); + + cpha = spi->mode & SPI_CPHA ? 1 : 0; +@@ -373,7 +364,7 @@ static int mtk_spi_hw_init(struct spi_ma + else + reg_val &= ~SPI_CMD_CS_POL; + +- if (chip_config->sample_sel) ++ if (mdata->sample_sel) + reg_val |= SPI_CMD_SAMPLE_SEL; + else + reg_val &= ~SPI_CMD_SAMPLE_SEL; +@@ -400,20 +391,20 @@ static int mtk_spi_hw_init(struct spi_ma + if (mdata->dev_comp->ipm_design) { + reg_val = readl(mdata->base + SPI_CMD_REG); + reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK; +- reg_val |= ((chip_config->tick_delay & 0x7) ++ reg_val |= ((mdata->get_tick_dly & 0x7) + << SPI_CMD_IPM_GET_TICKDLY_OFFSET); + writel(reg_val, mdata->base + SPI_CMD_REG); + } else { + reg_val = readl(mdata->base + SPI_CFG1_REG); + reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK; +- reg_val |= ((chip_config->tick_delay & 0x7) ++ reg_val |= ((mdata->get_tick_dly & 0x7) + << SPI_CFG1_GET_TICK_DLY_OFFSET); + writel(reg_val, mdata->base + SPI_CFG1_REG); + } + } else { + reg_val = readl(mdata->base + SPI_CFG1_REG); + reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1; +- reg_val |= ((chip_config->tick_delay & 0x3) ++ reg_val |= ((mdata->get_tick_dly & 0x3) + << SPI_CFG1_GET_TICK_DLY_OFFSET_V1); + writel(reg_val, mdata->base + SPI_CFG1_REG); + } +@@ -700,9 +691,6 @@ static int mtk_spi_setup(struct spi_devi + { + struct mtk_spi *mdata = spi_master_get_devdata(spi->master); + +- if (!spi->controller_data) +- spi->controller_data = (void *)&mtk_default_chip_info; +- + if (mdata->dev_comp->need_pad_sel && spi->cs_gpiod) + /* CS de-asserted, gpiolib will handle inversion */ + gpiod_direction_output(spi->cs_gpiod, 0); +@@ -1115,6 +1103,10 @@ static int mtk_spi_probe(struct platform + mdata = spi_master_get_devdata(master); + mdata->dev_comp = of_id->data; + ++ /* Set device configs to default first. Calibrate it later. */ ++ mdata->sample_sel = 0; ++ mdata->get_tick_dly = 2; ++ + if (mdata->dev_comp->enhance_timing) + master->mode_bits |= SPI_CS_HIGH; + +--- a/include/linux/platform_data/spi-mt65xx.h ++++ /dev/null +@@ -1,17 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * MTK SPI bus driver definitions +- * +- * Copyright (c) 2015 MediaTek Inc. +- * Author: Leilk Liu +- */ +- +-#ifndef ____LINUX_PLATFORM_DATA_SPI_MTK_H +-#define ____LINUX_PLATFORM_DATA_SPI_MTK_H +- +-/* Board specific platform_data */ +-struct mtk_chip_config { +- u32 sample_sel; +- u32 tick_delay; +-}; +-#endif diff --git a/target/linux/mediatek/patches-6.1/432-drivers-spi-Add-support-for-dynamic-calibration.patch b/target/linux/mediatek/patches-6.1/432-drivers-spi-Add-support-for-dynamic-calibration.patch new file mode 100644 index 00000000000..4c980e9438d --- /dev/null +++ b/target/linux/mediatek/patches-6.1/432-drivers-spi-Add-support-for-dynamic-calibration.patch @@ -0,0 +1,236 @@ +From 2ade0172154e50c8a2bfd8634c6eff943cffea29 Mon Sep 17 00:00:00 2001 +From: "SkyLake.Huang" +Date: Thu, 23 Jun 2022 18:35:52 +0800 +Subject: [PATCH 2/6] drivers: spi: Add support for dynamic calibration + +Signed-off-by: SkyLake.Huang +--- + drivers/spi/spi.c | 137 ++++++++++++++++++++++++++++++++++++++++ + include/linux/spi/spi.h | 42 ++++++++++++ + 2 files changed, 179 insertions(+) + +--- a/drivers/spi/spi.c ++++ b/drivers/spi/spi.c +@@ -1234,6 +1234,70 @@ static int spi_transfer_wait(struct spi_ + return 0; + } + ++int spi_do_calibration(struct spi_controller *ctlr, struct spi_device *spi, ++ int (*cal_read)(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen), void *drv_priv) ++{ ++ int datalen = ctlr->cal_rule->datalen; ++ int addrlen = ctlr->cal_rule->addrlen; ++ u8 *buf; ++ int ret; ++ int i; ++ struct list_head *cal_head, *listptr; ++ struct spi_cal_target *target; ++ ++ /* Calculate calibration result */ ++ int hit_val, total_hit, origin; ++ bool hit; ++ ++ /* Make sure we can start calibration */ ++ if(!ctlr->cal_target || !ctlr->cal_rule || !ctlr->append_caldata) ++ return 0; ++ ++ buf = kzalloc(datalen * sizeof(u8), GFP_KERNEL); ++ if(!buf) ++ return -ENOMEM; ++ ++ ret = ctlr->append_caldata(ctlr); ++ if (ret) ++ goto cal_end; ++ ++ cal_head = ctlr->cal_target; ++ list_for_each(listptr, cal_head) { ++ target = list_entry(listptr, struct spi_cal_target, list); ++ ++ hit = false; ++ hit_val = 0; ++ total_hit = 0; ++ origin = *target->cal_item; ++ ++ for(i=target->cal_min; i<=target->cal_max; i+=target->step) { ++ *target->cal_item = i; ++ ret = (*cal_read)(drv_priv, ctlr->cal_rule->addr, addrlen, buf, datalen); ++ if(ret) ++ break; ++ dev_dbg(&spi->dev, "controller cal item value: 0x%x\n", i); ++ if(memcmp(ctlr->cal_rule->match_data, buf, datalen * sizeof(u8)) == 0) { ++ hit = true; ++ hit_val += i; ++ total_hit++; ++ dev_dbg(&spi->dev, "golden data matches data read!\n"); ++ } ++ } ++ if(hit) { ++ *target->cal_item = DIV_ROUND_CLOSEST(hit_val, total_hit); ++ dev_info(&spi->dev, "calibration result: 0x%x", *target->cal_item); ++ } else { ++ *target->cal_item = origin; ++ dev_warn(&spi->dev, "calibration failed, fallback to default: 0x%x", origin); ++ } ++ } ++ ++cal_end: ++ kfree(buf); ++ return ret? ret: 0; ++} ++EXPORT_SYMBOL_GPL(spi_do_calibration); ++ + static void _spi_transfer_delay_ns(u32 ns) + { + if (!ns) +@@ -2021,6 +2085,75 @@ void spi_flush_queue(struct spi_controll + /*-------------------------------------------------------------------------*/ + + #if defined(CONFIG_OF) ++static inline void alloc_cal_data(struct list_head **cal_target, ++ struct spi_cal_rule **cal_rule, bool enable) ++{ ++ if(enable) { ++ *cal_target = kmalloc(sizeof(struct list_head), GFP_KERNEL); ++ INIT_LIST_HEAD(*cal_target); ++ *cal_rule = kmalloc(sizeof(struct spi_cal_rule), GFP_KERNEL); ++ } else { ++ kfree(*cal_target); ++ kfree(*cal_rule); ++ } ++} ++ ++static int of_spi_parse_cal_dt(struct spi_controller *ctlr, struct spi_device *spi, ++ struct device_node *nc) ++{ ++ u32 value; ++ int rc; ++ const char *cal_mode; ++ ++ rc = of_property_read_bool(nc, "spi-cal-enable"); ++ if (rc) ++ alloc_cal_data(&ctlr->cal_target, &ctlr->cal_rule, true); ++ else ++ return 0; ++ ++ rc = of_property_read_string(nc, "spi-cal-mode", &cal_mode); ++ if(!rc) { ++ if(strcmp("read-data", cal_mode) == 0){ ++ ctlr->cal_rule->mode = SPI_CAL_READ_DATA; ++ } else if(strcmp("read-pp", cal_mode) == 0) { ++ ctlr->cal_rule->mode = SPI_CAL_READ_PP; ++ return 0; ++ } else if(strcmp("read-sfdp", cal_mode) == 0){ ++ ctlr->cal_rule->mode = SPI_CAL_READ_SFDP; ++ return 0; ++ } ++ } else ++ goto err; ++ ++ ctlr->cal_rule->datalen = 0; ++ rc = of_property_read_u32(nc, "spi-cal-datalen", &value); ++ if(!rc && value > 0) { ++ ctlr->cal_rule->datalen = value; ++ ++ ctlr->cal_rule->match_data = kzalloc(value * sizeof(u8), GFP_KERNEL); ++ rc = of_property_read_u8_array(nc, "spi-cal-data", ++ ctlr->cal_rule->match_data, value); ++ if(rc) ++ kfree(ctlr->cal_rule->match_data); ++ } ++ ++ rc = of_property_read_u32(nc, "spi-cal-addrlen", &value); ++ if(!rc && value > 0) { ++ ctlr->cal_rule->addrlen = value; ++ ++ ctlr->cal_rule->addr = kzalloc(value * sizeof(u32), GFP_KERNEL); ++ rc = of_property_read_u32_array(nc, "spi-cal-addr", ++ ctlr->cal_rule->addr, value); ++ if(rc) ++ kfree(ctlr->cal_rule->addr); ++ } ++ return 0; ++ ++err: ++ alloc_cal_data(&ctlr->cal_target, &ctlr->cal_rule, false); ++ return 0; ++} ++ + static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi, + struct device_node *nc) + { +@@ -2139,6 +2272,10 @@ of_register_spi_device(struct spi_contro + if (rc) + goto err_out; + ++ rc = of_spi_parse_cal_dt(ctlr, spi, nc); ++ if (rc) ++ goto err_out; ++ + /* Store a pointer to the node in the device structure */ + of_node_get(nc); + spi->dev.of_node = nc; +--- a/include/linux/spi/spi.h ++++ b/include/linux/spi/spi.h +@@ -290,6 +290,40 @@ struct spi_driver { + struct device_driver driver; + }; + ++enum { ++ SPI_CAL_READ_DATA = 0, ++ SPI_CAL_READ_PP = 1, /* only for SPI-NAND */ ++ SPI_CAL_READ_SFDP = 2, /* only for SPI-NOR */ ++}; ++ ++struct nand_addr { ++ unsigned int lun; ++ unsigned int plane; ++ unsigned int eraseblock; ++ unsigned int page; ++ unsigned int dataoffs; ++}; ++ ++/** ++ * Read calibration rule from device dts node. ++ * Once calibration result matches the rule, we regard is as success. ++ */ ++struct spi_cal_rule { ++ int datalen; ++ u8 *match_data; ++ int addrlen; ++ u32 *addr; ++ int mode; ++}; ++ ++struct spi_cal_target { ++ u32 *cal_item; ++ int cal_min; /* min of cal_item */ ++ int cal_max; /* max of cal_item */ ++ int step; /* Increase/decrease cal_item */ ++ struct list_head list; ++}; ++ + static inline struct spi_driver *to_spi_driver(struct device_driver *drv) + { + return drv ? container_of(drv, struct spi_driver, driver) : NULL; +@@ -665,6 +699,11 @@ struct spi_controller { + void *dummy_rx; + void *dummy_tx; + ++ /* For calibration */ ++ int (*append_caldata)(struct spi_controller *ctlr); ++ struct list_head *cal_target; ++ struct spi_cal_rule *cal_rule; ++ + int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs); + + /* +@@ -1477,6 +1516,9 @@ spi_register_board_info(struct spi_board + { return 0; } + #endif + ++extern int spi_do_calibration(struct spi_controller *ctlr, ++ struct spi_device *spi, int (*cal_read)(void *, u32 *, int, u8 *, int), void *drv_priv); ++ + /* If you're hotplugging an adapter with devices (parport, usb, etc) + * use spi_new_device() to describe each device. You can also call + * spi_unregister_device() to start making that device vanish, but diff --git a/target/linux/mediatek/patches-6.1/433-drivers-spi-mem-Add-spi-calibration-hook.patch b/target/linux/mediatek/patches-6.1/433-drivers-spi-mem-Add-spi-calibration-hook.patch new file mode 100644 index 00000000000..aaacab01312 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/433-drivers-spi-mem-Add-spi-calibration-hook.patch @@ -0,0 +1,41 @@ +From 06640a5da2973318c06e516da16a5b579622e7c5 Mon Sep 17 00:00:00 2001 +From: "SkyLake.Huang" +Date: Thu, 23 Jun 2022 18:37:55 +0800 +Subject: [PATCH 3/6] drivers: spi-mem: Add spi calibration hook + +Signed-off-by: SkyLake.Huang +--- + drivers/spi/spi-mem.c | 8 ++++++++ + include/linux/spi/spi-mem.h | 4 ++++ + 2 files changed, 12 insertions(+) + +--- a/drivers/spi/spi-mem.c ++++ b/drivers/spi/spi-mem.c +@@ -410,6 +410,14 @@ int spi_mem_exec_op(struct spi_mem *mem, + } + EXPORT_SYMBOL_GPL(spi_mem_exec_op); + ++int spi_mem_do_calibration(struct spi_mem *mem, ++ int (*cal_read)(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen), ++ void *priv) ++{ ++ return spi_do_calibration(mem->spi->controller, mem->spi, cal_read, priv); ++} ++EXPORT_SYMBOL_GPL(spi_mem_do_calibration); ++ + /** + * spi_mem_get_name() - Return the SPI mem device name to be used by the + * upper layer if necessary +--- a/include/linux/spi/spi-mem.h ++++ b/include/linux/spi/spi-mem.h +@@ -366,6 +366,10 @@ bool spi_mem_supports_op(struct spi_mem + int spi_mem_exec_op(struct spi_mem *mem, + const struct spi_mem_op *op); + ++int spi_mem_do_calibration(struct spi_mem *mem, ++ int (*cal_read)(void *, u32 *, int, u8 *, int), ++ void *priv); ++ + const char *spi_mem_get_name(struct spi_mem *mem); + + struct spi_mem_dirmap_desc * diff --git a/target/linux/mediatek/patches-6.1/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch b/target/linux/mediatek/patches-6.1/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch new file mode 100644 index 00000000000..a64d6229819 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch @@ -0,0 +1,43 @@ +From d278c7a0bf730318a7ccf8d0a8b434c813e23fd0 Mon Sep 17 00:00:00 2001 +From: "SkyLake.Huang" +Date: Thu, 23 Jun 2022 18:39:03 +0800 +Subject: [PATCH 4/6] drivers: spi-mt65xx: Add controller's calibration + paramter + +Signed-off-by: SkyLake.Huang +--- + drivers/spi/spi-mt65xx.c | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +--- a/drivers/spi/spi-mt65xx.c ++++ b/drivers/spi/spi-mt65xx.c +@@ -800,6 +800,21 @@ static irqreturn_t mtk_spi_interrupt(int + return IRQ_HANDLED; + } + ++static int mtk_spi_append_caldata(struct spi_controller *ctlr) ++{ ++ struct spi_cal_target *cal_target = kmalloc(sizeof(*cal_target), GFP_KERNEL); ++ struct mtk_spi *mdata = spi_master_get_devdata(ctlr); ++ ++ cal_target->cal_item = &mdata->get_tick_dly; ++ cal_target->cal_min = 0; ++ cal_target->cal_max = 7; ++ cal_target->step = 1; ++ ++ list_add(&cal_target->list, ctlr->cal_target); ++ ++ return 0; ++} ++ + static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem, + struct spi_mem_op *op) + { +@@ -1092,6 +1107,7 @@ static int mtk_spi_probe(struct platform + master->setup = mtk_spi_setup; + master->set_cs_timing = mtk_spi_set_hw_cs_timing; + master->use_gpio_descriptors = true; ++ master->append_caldata = mtk_spi_append_caldata; + + of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node); + if (!of_id) { diff --git a/target/linux/mediatek/patches-6.1/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch b/target/linux/mediatek/patches-6.1/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch new file mode 100644 index 00000000000..e2684eebb74 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch @@ -0,0 +1,81 @@ +From 7670ec4a14891a1a182b98a9c403ffbf6b49e4b1 Mon Sep 17 00:00:00 2001 +From: "SkyLake.Huang" +Date: Thu, 23 Jun 2022 18:39:56 +0800 +Subject: [PATCH 5/6] drivers: mtd: spinand: Add calibration support for + spinand + +Signed-off-by: SkyLake.Huang +--- + drivers/mtd/nand/spi/core.c | 54 +++++++++++++++++++++++++++++++++++++ + 1 file changed, 54 insertions(+) + +--- a/drivers/mtd/nand/spi/core.c ++++ b/drivers/mtd/nand/spi/core.c +@@ -977,6 +977,56 @@ static int spinand_manufacturer_match(st + return -ENOTSUPP; + } + ++int spinand_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen) { ++ struct spinand_device *spinand = (struct spinand_device *)priv; ++ struct device *dev = &spinand->spimem->spi->dev; ++ struct spi_mem_op op = SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, buf, readlen); ++ struct nand_pos pos; ++ struct nand_page_io_req req; ++ u8 status; ++ int ret; ++ ++ if(addrlen != sizeof(struct nand_addr)/sizeof(unsigned int)) { ++ dev_err(dev, "Must provide correct addr(length) for spinand calibration\n"); ++ return -EINVAL; ++ } ++ ++ ret = spinand_reset_op(spinand); ++ if (ret) ++ return ret; ++ ++ /* We should store our golden data in first target because ++ * we can't switch target at this moment. ++ */ ++ pos = (struct nand_pos){ ++ .target = 0, ++ .lun = *addr, ++ .plane = *(addr+1), ++ .eraseblock = *(addr+2), ++ .page = *(addr+3), ++ }; ++ ++ req = (struct nand_page_io_req){ ++ .pos = pos, ++ .dataoffs = *(addr+4), ++ .datalen = readlen, ++ .databuf.in = buf, ++ .mode = MTD_OPS_AUTO_OOB, ++ }; ++ ++ ret = spinand_load_page_op(spinand, &req); ++ if (ret) ++ return ret; ++ ++ ret = spinand_wait(spinand, &status); ++ if (ret < 0) ++ return ret; ++ ++ ret = spi_mem_exec_op(spinand->spimem, &op); ++ ++ return 0; ++} ++ + static int spinand_id_detect(struct spinand_device *spinand) + { + u8 *id = spinand->id.data; +@@ -1227,6 +1277,10 @@ static int spinand_init(struct spinand_d + if (!spinand->scratchbuf) + return -ENOMEM; + ++ ret = spi_mem_do_calibration(spinand->spimem, spinand_cal_read, spinand); ++ if (ret) ++ dev_err(dev, "Failed to calibrate SPI-NAND (err = %d)\n", ret); ++ + ret = spinand_detect(spinand); + if (ret) + goto err_free_bufs; diff --git a/target/linux/mediatek/patches-6.1/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch b/target/linux/mediatek/patches-6.1/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch new file mode 100644 index 00000000000..25a7cd38614 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch @@ -0,0 +1,57 @@ +From f3fe3b15eca7908eaac57f9b8387a5dbc45ec5b2 Mon Sep 17 00:00:00 2001 +From: "SkyLake.Huang" +Date: Thu, 23 Jun 2022 18:40:59 +0800 +Subject: [PATCH 6/6] drivers: mtd: spi-nor: Add calibration support for + spi-nor + +Signed-off-by: SkyLake.Huang +--- + drivers/mtd/nand/spi/core.c | 5 ++++- + drivers/mtd/spi-nor/core.c | 15 +++++++++++++++ + 2 files changed, 19 insertions(+), 1 deletion(-) + +--- a/drivers/mtd/nand/spi/core.c ++++ b/drivers/mtd/nand/spi/core.c +@@ -1018,7 +1018,10 @@ int spinand_cal_read(void *priv, u32 *ad + if (ret) + return ret; + +- ret = spinand_wait(spinand, &status); ++ ret = spinand_wait(spinand, ++ SPINAND_READ_INITIAL_DELAY_US, ++ SPINAND_READ_POLL_DELAY_US, ++ &status); + if (ret < 0) + return ret; + +--- a/drivers/mtd/spi-nor/core.c ++++ b/drivers/mtd/spi-nor/core.c +@@ -3060,6 +3060,18 @@ static void spi_nor_debugfs_init(struct + info->id_len, info->id); + } + ++static int spi_nor_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen) ++{ ++ struct spi_nor *nor = (struct spi_nor *)priv; ++ ++ nor->reg_proto = SNOR_PROTO_1_1_1; ++ nor->read_proto = SNOR_PROTO_1_1_1; ++ nor->read_opcode = SPINOR_OP_READ; ++ nor->read_dummy = 0; ++ ++ return nor->controller_ops->read(nor, *addr, readlen, buf); ++} ++ + static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor, + const char *name) + { +@@ -3133,6 +3145,9 @@ int spi_nor_scan(struct spi_nor *nor, co + if (!nor->bouncebuf) + return -ENOMEM; + ++ if(nor->spimem) ++ spi_mem_do_calibration(nor->spimem, spi_nor_cal_read, nor); ++ + info = spi_nor_get_flash_info(nor, name); + if (IS_ERR(info)) + return PTR_ERR(info); diff --git a/target/linux/mediatek/patches-6.1/500-gsw-rtl8367s-mt7622-support.patch b/target/linux/mediatek/patches-6.1/500-gsw-rtl8367s-mt7622-support.patch new file mode 100644 index 00000000000..b8964f4e765 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/500-gsw-rtl8367s-mt7622-support.patch @@ -0,0 +1,25 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -367,6 +367,12 @@ config ROCKCHIP_PHY + help + Currently supports the integrated Ethernet PHY. + ++config RTL8367S_GSW ++ tristate "rtl8367 Gigabit Switch support for mt7622" ++ depends on NET_VENDOR_MEDIATEK ++ help ++ This driver supports rtl8367s in mt7622 ++ + config SMSC_PHY + tristate "SMSC PHYs" + help +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -95,6 +95,7 @@ obj-$(CONFIG_QSEMI_PHY) += qsemi.o + obj-$(CONFIG_REALTEK_PHY) += realtek.o + obj-$(CONFIG_RENESAS_PHY) += uPD60620.o + obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o ++obj-$(CONFIG_RTL8367S_GSW) += rtk/ + obj-$(CONFIG_SMSC_PHY) += smsc.o + obj-$(CONFIG_STE10XP) += ste10Xp.o + obj-$(CONFIG_TERANETICS_PHY) += teranetics.o diff --git a/target/linux/mediatek/patches-6.1/600-v5.16-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-and-MT.patch b/target/linux/mediatek/patches-6.1/600-v5.16-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-and-MT.patch new file mode 100644 index 00000000000..6a84ff47db1 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/600-v5.16-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-and-MT.patch @@ -0,0 +1,332 @@ +From: Chuanjia Liu +Date: Mon, 23 Aug 2021 11:27:59 +0800 +Subject: [PATCH] arm64: dts: mediatek: Split PCIe node for MT2712 and MT7622 + +There are two independent PCIe controllers in MT2712 and MT7622 +platform. Each of them should contain an independent MSI domain. + +In old dts architecture, MSI domain will be inherited from the root +bridge, and all of the devices will share the same MSI domain. +Hence that, the PCIe devices will not work properly if the irq number +which required is more than 32. + +Split the PCIe node for MT2712 and MT7622 platform to comply with +the hardware design and fix MSI issue. + +Signed-off-by: Chuanjia Liu +Acked-by: Ryder Lee +Link: https://lore.kernel.org/r/20210823032800.1660-6-chuanjia.liu@mediatek.com +Signed-off-by: Matthias Brugger +--- + +--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +@@ -915,64 +915,67 @@ + }; + }; + +- pcie: pcie@11700000 { ++ pcie1: pcie@112ff000 { + compatible = "mediatek,mt2712-pcie"; + device_type = "pci"; +- reg = <0 0x11700000 0 0x1000>, +- <0 0x112ff000 0 0x1000>; +- reg-names = "port0", "port1"; ++ reg = <0 0x112ff000 0 0x1000>; ++ reg-names = "port1"; ++ linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; +- interrupts = , +- ; +- clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, +- <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, +- <&pericfg CLK_PERI_PCIE0>, ++ interrupts = ; ++ interrupt-names = "pcie_irq"; ++ clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, + <&pericfg CLK_PERI_PCIE1>; +- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1"; +- phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>; +- phy-names = "pcie-phy0", "pcie-phy1"; ++ clock-names = "sys_ck1", "ahb_ck1"; ++ phys = <&u3port1 PHY_TYPE_PCIE>; ++ phy-names = "pcie-phy1"; + bus-range = <0x00 0xff>; +- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; ++ ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>; ++ status = "disabled"; + +- pcie0: pcie@0,0 { +- device_type = "pci"; +- status = "disabled"; +- reg = <0x0000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie_intc1 0>, ++ <0 0 0 2 &pcie_intc1 1>, ++ <0 0 0 3 &pcie_intc1 2>, ++ <0 0 0 4 &pcie_intc1 3>; ++ pcie_intc1: interrupt-controller { ++ interrupt-controller; ++ #address-cells = <0>; + #interrupt-cells = <1>; +- ranges; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0 0 0 1 &pcie_intc0 0>, +- <0 0 0 2 &pcie_intc0 1>, +- <0 0 0 3 &pcie_intc0 2>, +- <0 0 0 4 &pcie_intc0 3>; +- pcie_intc0: interrupt-controller { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- }; + }; ++ }; ++ ++ pcie0: pcie@11700000 { ++ compatible = "mediatek,mt2712-pcie"; ++ device_type = "pci"; ++ reg = <0 0x11700000 0 0x1000>; ++ reg-names = "port0"; ++ linux,pci-domain = <0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ interrupts = ; ++ interrupt-names = "pcie_irq"; ++ clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, ++ <&pericfg CLK_PERI_PCIE0>; ++ clock-names = "sys_ck0", "ahb_ck0"; ++ phys = <&u3port0 PHY_TYPE_PCIE>; ++ phy-names = "pcie-phy0"; ++ bus-range = <0x00 0xff>; ++ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; ++ status = "disabled"; + +- pcie1: pcie@1,0 { +- device_type = "pci"; +- status = "disabled"; +- reg = <0x0800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie_intc0 0>, ++ <0 0 0 2 &pcie_intc0 1>, ++ <0 0 0 3 &pcie_intc0 2>, ++ <0 0 0 4 &pcie_intc0 3>; ++ pcie_intc0: interrupt-controller { ++ interrupt-controller; ++ #address-cells = <0>; + #interrupt-cells = <1>; +- ranges; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0 0 0 1 &pcie_intc1 0>, +- <0 0 0 2 &pcie_intc1 1>, +- <0 0 0 3 &pcie_intc1 2>, +- <0 0 0 4 &pcie_intc1 3>; +- pcie_intc1: interrupt-controller { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- }; + }; + }; + +--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +@@ -302,18 +302,16 @@ + }; + }; + +-&pcie { ++&pcie0 { + pinctrl-names = "default"; +- pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>; ++ pinctrl-0 = <&pcie0_pins>; + status = "okay"; ++}; + +- pcie@0,0 { +- status = "okay"; +- }; +- +- pcie@1,0 { +- status = "okay"; +- }; ++&pcie1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie1_pins>; ++ status = "okay"; + }; + + &pio { +--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +@@ -232,18 +232,16 @@ + }; + }; + +-&pcie { ++&pcie0 { + pinctrl-names = "default"; +- pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>; ++ pinctrl-0 = <&pcie0_pins>; + status = "okay"; ++}; + +- pcie@0,0 { +- status = "okay"; +- }; +- +- pcie@1,0 { +- status = "okay"; +- }; ++&pcie1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie1_pins>; ++ status = "okay"; + }; + + &pio { +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -809,75 +809,83 @@ + #reset-cells = <1>; + }; + +- pcie: pcie@1a140000 { ++ pciecfg: pciecfg@1a140000 { ++ compatible = "mediatek,generic-pciecfg", "syscon"; ++ reg = <0 0x1a140000 0 0x1000>; ++ }; ++ ++ pcie0: pcie@1a143000 { + compatible = "mediatek,mt7622-pcie"; + device_type = "pci"; +- reg = <0 0x1a140000 0 0x1000>, +- <0 0x1a143000 0 0x1000>, +- <0 0x1a145000 0 0x1000>; +- reg-names = "subsys", "port0", "port1"; ++ reg = <0 0x1a143000 0 0x1000>; ++ reg-names = "port0"; ++ linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupts = , +- ; ++ interrupts = ; ++ interrupt-names = "pcie_irq"; + clocks = <&pciesys CLK_PCIE_P0_MAC_EN>, +- <&pciesys CLK_PCIE_P1_MAC_EN>, +- <&pciesys CLK_PCIE_P0_AHB_EN>, + <&pciesys CLK_PCIE_P0_AHB_EN>, + <&pciesys CLK_PCIE_P0_AUX_EN>, +- <&pciesys CLK_PCIE_P1_AUX_EN>, + <&pciesys CLK_PCIE_P0_AXI_EN>, +- <&pciesys CLK_PCIE_P1_AXI_EN>, + <&pciesys CLK_PCIE_P0_OBFF_EN>, +- <&pciesys CLK_PCIE_P1_OBFF_EN>, +- <&pciesys CLK_PCIE_P0_PIPE_EN>, +- <&pciesys CLK_PCIE_P1_PIPE_EN>; +- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1", +- "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1", +- "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1"; ++ <&pciesys CLK_PCIE_P0_PIPE_EN>; ++ clock-names = "sys_ck0", "ahb_ck0", "aux_ck0", ++ "axi_ck0", "obff_ck0", "pipe_ck0"; ++ + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; + bus-range = <0x00 0xff>; +- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; ++ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; + status = "disabled"; + +- pcie0: pcie@0,0 { +- reg = <0x0000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie_intc0 0>, ++ <0 0 0 2 &pcie_intc0 1>, ++ <0 0 0 3 &pcie_intc0 2>, ++ <0 0 0 4 &pcie_intc0 3>; ++ pcie_intc0: interrupt-controller { ++ interrupt-controller; ++ #address-cells = <0>; + #interrupt-cells = <1>; +- ranges; +- status = "disabled"; +- +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0 0 0 1 &pcie_intc0 0>, +- <0 0 0 2 &pcie_intc0 1>, +- <0 0 0 3 &pcie_intc0 2>, +- <0 0 0 4 &pcie_intc0 3>; +- pcie_intc0: interrupt-controller { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- }; + }; ++ }; + +- pcie1: pcie@1,0 { +- reg = <0x0800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges; +- status = "disabled"; ++ pcie1: pcie@1a145000 { ++ compatible = "mediatek,mt7622-pcie"; ++ device_type = "pci"; ++ reg = <0 0x1a145000 0 0x1000>; ++ reg-names = "port1"; ++ linux,pci-domain = <1>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ interrupts = ; ++ interrupt-names = "pcie_irq"; ++ clocks = <&pciesys CLK_PCIE_P1_MAC_EN>, ++ /* designer has connect RC1 with p0_ahb clock */ ++ <&pciesys CLK_PCIE_P0_AHB_EN>, ++ <&pciesys CLK_PCIE_P1_AUX_EN>, ++ <&pciesys CLK_PCIE_P1_AXI_EN>, ++ <&pciesys CLK_PCIE_P1_OBFF_EN>, ++ <&pciesys CLK_PCIE_P1_PIPE_EN>; ++ clock-names = "sys_ck1", "ahb_ck1", "aux_ck1", ++ "axi_ck1", "obff_ck1", "pipe_ck1"; ++ ++ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; ++ bus-range = <0x00 0xff>; ++ ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; ++ status = "disabled"; + +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0 0 0 1 &pcie_intc1 0>, +- <0 0 0 2 &pcie_intc1 1>, +- <0 0 0 3 &pcie_intc1 2>, +- <0 0 0 4 &pcie_intc1 3>; +- pcie_intc1: interrupt-controller { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- }; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie_intc1 0>, ++ <0 0 0 2 &pcie_intc1 1>, ++ <0 0 0 3 &pcie_intc1 2>, ++ <0 0 0 4 &pcie_intc1 3>; ++ pcie_intc1: interrupt-controller { ++ interrupt-controller; ++ #address-cells = <0>; ++ #interrupt-cells = <1>; + }; + }; + diff --git a/target/linux/mediatek/patches-6.1/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch b/target/linux/mediatek/patches-6.1/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch new file mode 100644 index 00000000000..ff482272108 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch @@ -0,0 +1,34 @@ +From: qizhong cheng +Date: Mon, 27 Dec 2021 21:31:10 +0800 +Subject: [PATCH] PCI: mediatek: Assert PERST# for 100ms for power and clock to + stabilize +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Described in PCIe CEM specification sections 2.2 (PERST# Signal) and +2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should +be delayed 100ms (TPVPERL) for the power and clock to become stable. + +Link: https://lore.kernel.org/r/20211227133110.14500-1-qizhong.cheng@mediatek.com +Signed-off-by: qizhong cheng +Signed-off-by: Lorenzo Pieralisi +Acked-by: Pali Rohár +--- + +--- a/drivers/pci/controller/pcie-mediatek.c ++++ b/drivers/pci/controller/pcie-mediatek.c +@@ -702,6 +702,13 @@ static int mtk_pcie_startup_port_v2(stru + */ + writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); + ++ /* ++ * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and ++ * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should ++ * be delayed 100ms (TPVPERL) for the power and clock to become stable. ++ */ ++ msleep(100); ++ + /* De-assert PHY, PE, PIPE, MAC and configuration reset */ + val = readl(port->base + PCIE_RST_CTRL); + val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | diff --git a/target/linux/mediatek/patches-6.1/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch b/target/linux/mediatek/patches-6.1/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch new file mode 100644 index 00000000000..bf479ab53b2 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch @@ -0,0 +1,28 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -849,6 +849,12 @@ + #address-cells = <0>; + #interrupt-cells = <1>; + }; ++ ++ slot0: pcie@0,0 { ++ reg = <0x0000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ }; + }; + + pcie1: pcie@1a145000 { +@@ -887,6 +893,12 @@ + #address-cells = <0>; + #interrupt-cells = <1>; + }; ++ ++ slot1: pcie@1,0 { ++ reg = <0x0800 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ }; + }; + + sata: sata@1a200000 { diff --git a/target/linux/mediatek/patches-6.1/603-v5.16-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch b/target/linux/mediatek/patches-6.1/603-v5.16-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch new file mode 100644 index 00000000000..252ef080f59 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/603-v5.16-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch @@ -0,0 +1,203 @@ +From patchwork Thu May 28 06:16:48 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Chuanjia Liu +X-Patchwork-Id: 11574797 +Return-Path: + +Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org + [172.30.200.123]) + by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 30A5E1392 + for ; + Thu, 28 May 2020 06:29:05 +0000 (UTC) +Received: from bombadil.infradead.org (bombadil.infradead.org + [198.137.202.133]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by mail.kernel.org (Postfix) with ESMTPS id 08B6320721 + for ; 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Thu, 28 May 2020 14:18:52 +0800 +From: +To: , , +Subject: [PATCH v2 4/4] ARM: dts: mediatek: Update mt7629 PCIe node +Date: Thu, 28 May 2020 14:16:48 +0800 +Message-ID: <20200528061648.32078-5-chuanjia.liu@mediatek.com> +X-Mailer: git-send-email 2.18.0 +In-Reply-To: <20200528061648.32078-1-chuanjia.liu@mediatek.com> +References: <20200528061648.32078-1-chuanjia.liu@mediatek.com> +MIME-Version: 1.0 +X-MTK: N +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20200527_232901_719172_E5A99C62 +X-CRM114-Status: GOOD ( 11.61 ) +X-Spam-Score: -0.2 (/) +X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: + Content analysis details: (-0.2 points) + pts rule name description + ---- ---------------------- + -------------------------------------------------- + -0.0 SPF_PASS SPF: sender matches SPF record + 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record + 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 + encoding + -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from + author's domain + 0.1 DKIM_SIGNED Message has a DKIM or DK signature, + not necessarily + valid + -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature + -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from + envelope-from domain + 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay + lines +X-BeenThere: linux-mediatek@lists.infradead.org +X-Mailman-Version: 2.1.29 +Precedence: list +List-Id: +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Cc: devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com, + srv_heupstream@mediatek.com, "chuanjia.liu" , + linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, + jianjun.wang@mediatek.com, linux-mediatek@lists.infradead.org, + yong.wu@mediatek.com, bhelgaas@google.com, + linux-arm-kernel@lists.infradead.org, amurray@thegoodpenguin.co.uk +Sender: "Linux-mediatek" +Errors-To: + linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org + +From: "chuanjia.liu" + +Remove unused property and add pciecfg node. + +Signed-off-by: chuanjia.liu +--- + arch/arm/boot/dts/mt7629-rfb.dts | 3 ++- + arch/arm/boot/dts/mt7629.dtsi | 23 +++++++++++++---------- + 2 files changed, 15 insertions(+), 11 deletions(-) + +--- a/arch/arm/boot/dts/mt7629-rfb.dts ++++ b/arch/arm/boot/dts/mt7629-rfb.dts +@@ -149,9 +149,10 @@ + }; + }; + +-&pcie { ++&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; ++ status = "okay"; + }; + + &pciephy1 { +--- a/arch/arm/boot/dts/mt7629.dtsi ++++ b/arch/arm/boot/dts/mt7629.dtsi +@@ -382,16 +382,21 @@ + #reset-cells = <1>; + }; + +- pcie: pcie@1a140000 { ++ pciecfg: pciecfg@1a140000 { ++ compatible = "mediatek,mt7629-pciecfg", "syscon"; ++ reg = <0x1a140000 0x1000>; ++ }; ++ ++ pcie1: pcie@1a145000 { + compatible = "mediatek,mt7629-pcie"; + device_type = "pci"; +- reg = <0x1a140000 0x1000>, +- <0x1a145000 0x1000>; +- reg-names = "subsys","port1"; ++ reg = <0x1a145000 0x1000>; ++ reg-names = "port1"; ++ mediatek,pcie-cfg = <&pciecfg>; + #address-cells = <3>; + #size-cells = <2>; +- interrupts = , +- ; ++ interrupts = ; ++ interrupt-names = "pcie_irq"; + clocks = <&pciesys CLK_PCIE_P1_MAC_EN>, + <&pciesys CLK_PCIE_P0_AHB_EN>, + <&pciesys CLK_PCIE_P1_AUX_EN>, +@@ -412,21 +417,19 @@ + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>; ++ status = "disabled"; + +- pcie1: pcie@1,0 { +- device_type = "pci"; ++ slot1: pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; +- num-lanes = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; +- + pcie_intc1: interrupt-controller { + interrupt-controller; + #address-cells = <0>; diff --git a/target/linux/mediatek/patches-6.1/610-pcie-mediatek-fix-clearing-interrupt-status.patch b/target/linux/mediatek/patches-6.1/610-pcie-mediatek-fix-clearing-interrupt-status.patch new file mode 100644 index 00000000000..2bebfddf5c6 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/610-pcie-mediatek-fix-clearing-interrupt-status.patch @@ -0,0 +1,23 @@ +From: Felix Fietkau +Date: Fri, 4 Sep 2020 18:33:27 +0200 +Subject: [PATCH] pcie-mediatek: fix clearing interrupt status + +Clearing the status needs to happen after running the handler, otherwise +we will get an extra spurious interrupt after the cause has been cleared + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/pci/controller/pcie-mediatek.c ++++ b/drivers/pci/controller/pcie-mediatek.c +@@ -614,9 +614,9 @@ static void mtk_pcie_intr_handler(struct + if (status & INTX_MASK) { + for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) { + /* Clear the INTx */ +- writel(1 << bit, port->base + PCIE_INT_STATUS); + generic_handle_domain_irq(port->irq_domain, + bit - INTX_SHIFT); ++ writel(1 << bit, port->base + PCIE_INT_STATUS); + } + } + diff --git a/target/linux/mediatek/patches-6.1/702-v5.17-net-mdio-add-helpers-to-extract-clause-45-regad-and-.patch b/target/linux/mediatek/patches-6.1/702-v5.17-net-mdio-add-helpers-to-extract-clause-45-regad-and-.patch new file mode 100644 index 00000000000..da33aaa72f3 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/702-v5.17-net-mdio-add-helpers-to-extract-clause-45-regad-and-.patch @@ -0,0 +1,53 @@ +From c6af53f038aa32cec12e8a305ba07c7ef168f1b0 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Tue, 4 Jan 2022 12:07:00 +0000 +Subject: [PATCH 2/3] net: mdio: add helpers to extract clause 45 regad and + devad fields + +Add a couple of helpers and definitions to extract the clause 45 regad +and devad fields from the regnum passed into MDIO drivers. + +Tested-by: Daniel Golle +Reviewed-by: Andrew Lunn +Signed-off-by: Russell King (Oracle) +Signed-off-by: Daniel Golle +Signed-off-by: David S. Miller +--- + include/linux/mdio.h | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/include/linux/mdio.h ++++ b/include/linux/mdio.h +@@ -7,6 +7,7 @@ + #define __LINUX_MDIO_H__ + + #include ++#include + #include + + /* Or MII_ADDR_C45 into regnum for read/write on mii_bus to enable the 21 bit +@@ -14,6 +15,7 @@ + */ + #define MII_ADDR_C45 (1<<30) + #define MII_DEVADDR_C45_SHIFT 16 ++#define MII_DEVADDR_C45_MASK GENMASK(20, 16) + #define MII_REGADDR_C45_MASK GENMASK(15, 0) + + struct gpio_desc; +@@ -355,6 +357,16 @@ static inline u32 mdiobus_c45_addr(int d + return MII_ADDR_C45 | devad << MII_DEVADDR_C45_SHIFT | regnum; + } + ++static inline u16 mdiobus_c45_regad(u32 regnum) ++{ ++ return FIELD_GET(MII_REGADDR_C45_MASK, regnum); ++} ++ ++static inline u16 mdiobus_c45_devad(u32 regnum) ++{ ++ return FIELD_GET(MII_DEVADDR_C45_MASK, regnum); ++} ++ + static inline int __mdiobus_c45_read(struct mii_bus *bus, int prtad, int devad, + u16 regnum) + { diff --git a/target/linux/mediatek/patches-6.1/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch b/target/linux/mediatek/patches-6.1/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch new file mode 100644 index 00000000000..84718d300b5 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch @@ -0,0 +1,128 @@ +From e2e7f6e29c99a1c6afc0e0aa4b9ea80302d28720 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Tue, 4 Jan 2022 12:07:46 +0000 +Subject: [PATCH 3/3] net: ethernet: mtk_eth_soc: implement Clause 45 MDIO + access + +Implement read and write access to IEEE 802.3 Clause 45 Ethernet +phy registers while making use of new mdiobus_c45_regad and +mdiobus_c45_devad helpers. + +Tested on the Ubiquiti UniFi 6 LR access point featuring +MediaTek MT7622BV WiSoC with Aquantia AQR112C. + +Signed-off-by: Daniel Golle +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 70 +++++++++++++++++---- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 3 + + 2 files changed, 60 insertions(+), 13 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -323,13 +323,35 @@ static int _mtk_mdio_write(struct mtk_et + if (ret < 0) + return ret; + +- mtk_w32(eth, PHY_IAC_ACCESS | +- PHY_IAC_START_C22 | +- PHY_IAC_CMD_WRITE | +- PHY_IAC_REG(phy_reg) | +- PHY_IAC_ADDR(phy_addr) | +- PHY_IAC_DATA(write_data), +- MTK_PHY_IAC); ++ if (phy_reg & MII_ADDR_C45) { ++ mtk_w32(eth, PHY_IAC_ACCESS | ++ PHY_IAC_START_C45 | ++ PHY_IAC_CMD_C45_ADDR | ++ PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | ++ PHY_IAC_ADDR(phy_addr) | ++ PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)), ++ MTK_PHY_IAC); ++ ++ ret = mtk_mdio_busy_wait(eth); ++ if (ret < 0) ++ return ret; ++ ++ mtk_w32(eth, PHY_IAC_ACCESS | ++ PHY_IAC_START_C45 | ++ PHY_IAC_CMD_WRITE | ++ PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | ++ PHY_IAC_ADDR(phy_addr) | ++ PHY_IAC_DATA(write_data), ++ MTK_PHY_IAC); ++ } else { ++ mtk_w32(eth, PHY_IAC_ACCESS | ++ PHY_IAC_START_C22 | ++ PHY_IAC_CMD_WRITE | ++ PHY_IAC_REG(phy_reg) | ++ PHY_IAC_ADDR(phy_addr) | ++ PHY_IAC_DATA(write_data), ++ MTK_PHY_IAC); ++ } + + ret = mtk_mdio_busy_wait(eth); + if (ret < 0) +@@ -346,12 +368,33 @@ static int _mtk_mdio_read(struct mtk_eth + if (ret < 0) + return ret; + +- mtk_w32(eth, PHY_IAC_ACCESS | +- PHY_IAC_START_C22 | +- PHY_IAC_CMD_C22_READ | +- PHY_IAC_REG(phy_reg) | +- PHY_IAC_ADDR(phy_addr), +- MTK_PHY_IAC); ++ if (phy_reg & MII_ADDR_C45) { ++ mtk_w32(eth, PHY_IAC_ACCESS | ++ PHY_IAC_START_C45 | ++ PHY_IAC_CMD_C45_ADDR | ++ PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | ++ PHY_IAC_ADDR(phy_addr) | ++ PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)), ++ MTK_PHY_IAC); ++ ++ ret = mtk_mdio_busy_wait(eth); ++ if (ret < 0) ++ return ret; ++ ++ mtk_w32(eth, PHY_IAC_ACCESS | ++ PHY_IAC_START_C45 | ++ PHY_IAC_CMD_C45_READ | ++ PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | ++ PHY_IAC_ADDR(phy_addr), ++ MTK_PHY_IAC); ++ } else { ++ mtk_w32(eth, PHY_IAC_ACCESS | ++ PHY_IAC_START_C22 | ++ PHY_IAC_CMD_C22_READ | ++ PHY_IAC_REG(phy_reg) | ++ PHY_IAC_ADDR(phy_addr), ++ MTK_PHY_IAC); ++ } + + ret = mtk_mdio_busy_wait(eth); + if (ret < 0) +@@ -1013,6 +1056,7 @@ static int mtk_mdio_init(struct mtk_eth + eth->mii_bus->name = "mdio"; + eth->mii_bus->read = mtk_mdio_read; + eth->mii_bus->write = mtk_mdio_write; ++ eth->mii_bus->probe_capabilities = MDIOBUS_C22_C45; + eth->mii_bus->priv = eth; + eth->mii_bus->parent = eth->dev; + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -382,9 +382,12 @@ + #define PHY_IAC_ADDR_MASK GENMASK(24, 20) + #define PHY_IAC_ADDR(x) FIELD_PREP(PHY_IAC_ADDR_MASK, (x)) + #define PHY_IAC_CMD_MASK GENMASK(19, 18) ++#define PHY_IAC_CMD_C45_ADDR FIELD_PREP(PHY_IAC_CMD_MASK, 0) + #define PHY_IAC_CMD_WRITE FIELD_PREP(PHY_IAC_CMD_MASK, 1) + #define PHY_IAC_CMD_C22_READ FIELD_PREP(PHY_IAC_CMD_MASK, 2) ++#define PHY_IAC_CMD_C45_READ FIELD_PREP(PHY_IAC_CMD_MASK, 3) + #define PHY_IAC_START_MASK GENMASK(17, 16) ++#define PHY_IAC_START_C45 FIELD_PREP(PHY_IAC_START_MASK, 0) + #define PHY_IAC_START_C22 FIELD_PREP(PHY_IAC_START_MASK, 1) + #define PHY_IAC_DATA_MASK GENMASK(15, 0) + #define PHY_IAC_DATA(x) FIELD_PREP(PHY_IAC_DATA_MASK, (x)) diff --git a/target/linux/mediatek/patches-6.1/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch b/target/linux/mediatek/patches-6.1/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch new file mode 100644 index 00000000000..de64eda8277 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch @@ -0,0 +1,82 @@ +From: Felix Fietkau +Date: Fri, 4 Sep 2020 18:42:42 +0200 +Subject: [PATCH] pci: pcie-mediatek: add support for coherent DMA + +It improves performance by eliminating the need for a cache flush for DMA on +attached devices + +Signed-off-by: Felix Fietkau +--- + +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -837,6 +837,9 @@ + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; + status = "disabled"; ++ dma-coherent; ++ mediatek,hifsys = <&hifsys>; ++ mediatek,cci-control = <&cci_control2>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; +@@ -881,6 +884,9 @@ + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; + status = "disabled"; ++ dma-coherent; ++ mediatek,hifsys = <&hifsys>; ++ mediatek,cci-control = <&cci_control2>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; +--- a/drivers/pci/controller/pcie-mediatek.c ++++ b/drivers/pci/controller/pcie-mediatek.c +@@ -20,6 +20,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -139,6 +140,11 @@ + #define PCIE_LINK_STATUS_V2 0x804 + #define PCIE_PORT_LINKUP_V2 BIT(10) + ++/* DMA channel mapping */ ++#define HIFSYS_DMA_AG_MAP 0x008 ++#define HIFSYS_DMA_AG_MAP_PCIE0 BIT(0) ++#define HIFSYS_DMA_AG_MAP_PCIE1 BIT(1) ++ + struct mtk_pcie_port; + + /** +@@ -1054,6 +1060,27 @@ static int mtk_pcie_setup(struct mtk_pci + struct mtk_pcie_port *port, *tmp; + int err, slot; + ++ if (of_dma_is_coherent(node)) { ++ struct regmap *con; ++ u32 mask; ++ ++ con = syscon_regmap_lookup_by_phandle(node, ++ "mediatek,cci-control"); ++ /* enable CPU/bus coherency */ ++ if (!IS_ERR(con)) ++ regmap_write(con, 0, 3); ++ ++ con = syscon_regmap_lookup_by_phandle(node, ++ "mediatek,hifsys"); ++ if (IS_ERR(con)) { ++ dev_err(dev, "missing hifsys node\n"); ++ return PTR_ERR(con); ++ } ++ ++ mask = HIFSYS_DMA_AG_MAP_PCIE0 | HIFSYS_DMA_AG_MAP_PCIE1; ++ regmap_update_bits(con, HIFSYS_DMA_AG_MAP, mask, mask); ++ } ++ + slot = of_get_pci_domain_nr(dev->of_node); + if (slot < 0) { + for_each_available_child_of_node(node, child) { diff --git a/target/linux/mediatek/patches-6.1/721-dts-mt7622-mediatek-fix-300mhz.patch b/target/linux/mediatek/patches-6.1/721-dts-mt7622-mediatek-fix-300mhz.patch new file mode 100644 index 00000000000..f9a5fdbd0d8 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/721-dts-mt7622-mediatek-fix-300mhz.patch @@ -0,0 +1,27 @@ +From: Jip de Beer +Date: Sun, 9 Jan 2022 13:14:04 +0100 +Subject: [PATCH] mediatek mt7622: fix 300mhz typo in dts + +The lowest frequency should be 300MHz, since that is the label +assigned to the OPP in the mt7622.dtsi device tree, while there is one +missing zero in the actual value. + +To be clear, the lowest frequency should be 300MHz instead of 30MHz. + +As mentioned @dangowrt on the OpenWrt forum there is no benefit in +leaving 30MHz as the lowest frequency. + +Signed-off-by: Jip de Beer +Signed-off-by: Fritz D. Ansel +--- +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -24,7 +24,7 @@ + compatible = "operating-points-v2"; + opp-shared; + opp-300000000 { +- opp-hz = /bits/ 64 <30000000>; ++ opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <950000>; + }; + diff --git a/target/linux/mediatek/patches-6.1/722-remove-300Hz-to-prevent-freeze.patch b/target/linux/mediatek/patches-6.1/722-remove-300Hz-to-prevent-freeze.patch new file mode 100644 index 00000000000..52069496ca8 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/722-remove-300Hz-to-prevent-freeze.patch @@ -0,0 +1,25 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -23,11 +23,17 @@ + cpu_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; +- opp-300000000 { +- opp-hz = /bits/ 64 <300000000>; +- opp-microvolt = <950000>; +- }; +- ++ /* Due to the bug described at the link below, remove the 300 MHz clock to avoid a low ++ * voltage condition that can cause a hang when rebooting the RT3200/E8450. ++ * ++ * https://forum.openwrt.org/t/belkin-rt3200-linksys-e8450-wifi-ax-discussion/94302/1490 ++ * ++ * opp-300000000 { ++ * opp-hz = /bits/ 64 <300000000>; ++ * opp-microvolt = <950000>; ++ * }; ++ * ++ */ + opp-437500000 { + opp-hz = /bits/ 64 <437500000>; + opp-microvolt = <1000000>; diff --git a/target/linux/mediatek/patches-6.1/730-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch b/target/linux/mediatek/patches-6.1/730-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch new file mode 100644 index 00000000000..6af9e843357 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/730-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch @@ -0,0 +1,82 @@ +From 60ed9eb9605656c19ca402b7bd3f47552e901601 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Mon, 13 Feb 2023 02:33:14 +0000 +Subject: [PATCH] net: phy: add driver for MediaTek SoC built-in GE PHYs + +Some of MediaTek's Filogic SoCs come with built-in gigabit Ethernet +PHYs which require calibration data from the SoC's efuse. +Despite the similar design the driver doesn't share any code with the +existing mediatek-ge.c, so add support for these PHYs by introducing a +new driver for only MediaTek's ARM64 SoCs. + +Signed-off-by: Daniel Golle +--- + MAINTAINERS | 9 + + drivers/net/phy/Kconfig | 12 + + drivers/net/phy/Makefile | 1 + + drivers/net/phy/mediatek-ge-soc.c | 1263 +++++++++++++++++++++++++++++ + drivers/net/phy/mediatek-ge.c | 3 +- + 5 files changed, 1287 insertions(+), 1 deletion(-) + create mode 100644 drivers/net/phy/mediatek-ge-soc.c + +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -11797,6 +11797,15 @@ S: Maintained + F: drivers/net/pcs/pcs-mtk-lynxi.c + F: include/linux/pcs/pcs-mtk-lynxi.h + ++MEDIATEK ETHERNET PHY DRIVERS ++M: Daniel Golle ++M: Qingfang Deng ++M: SkyLake Huang ++L: netdev@vger.kernel.org ++S: Maintained ++F: drivers/net/phy/mediatek-ge-soc.c ++F: drivers/net/phy/mediatek-ge.c ++ + MEDIATEK I2C CONTROLLER DRIVER + M: Qii Wang + L: linux-i2c@vger.kernel.org +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -293,6 +293,18 @@ config MEDIATEK_GE_PHY + help + Supports the MediaTek Gigabit Ethernet PHYs. + ++config MEDIATEK_GE_SOC_PHY ++ tristate "MediaTek SoC Ethernet PHYs" ++ depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST ++ select NVMEM_MTK_EFUSE ++ help ++ Supports MediaTek SoC built-in Gigabit Ethernet PHYs. ++ ++ Include support for built-in Ethernet PHYs which are present in ++ the MT7981 and MT7988 SoCs. These PHYs need calibration data ++ present in the SoCs efuse and will dynamically calibrate VCM ++ (common-mode voltage) during startup. ++ + config MICREL_PHY + tristate "Micrel PHYs" + help +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -81,6 +81,7 @@ obj-$(CONFIG_MARVELL_PHY) += marvell.o + obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o + obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o + obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o ++obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mediatek-ge-soc.o + obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o + obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o + obj-$(CONFIG_MICREL_PHY) += micrel.o +--- a/drivers/net/phy/mediatek-ge.c ++++ b/drivers/net/phy/mediatek-ge.c +@@ -136,7 +136,8 @@ static struct phy_driver mtk_gephy_drive + module_phy_driver(mtk_gephy_driver); + + static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = { +- { PHY_ID_MATCH_VENDOR(0x03a29400) }, ++ { PHY_ID_MATCH_EXACT(0x03a29441) }, ++ { PHY_ID_MATCH_EXACT(0x03a29412) }, + { } + }; + diff --git a/target/linux/mediatek/patches-6.1/731-net-phy-hack-mxl-gpy-disable-sgmii-an.patch b/target/linux/mediatek/patches-6.1/731-net-phy-hack-mxl-gpy-disable-sgmii-an.patch new file mode 100644 index 00000000000..2e39ca3c26a --- /dev/null +++ b/target/linux/mediatek/patches-6.1/731-net-phy-hack-mxl-gpy-disable-sgmii-an.patch @@ -0,0 +1,166 @@ +--- a/drivers/net/phy/mxl-gpy.c ++++ b/drivers/net/phy/mxl-gpy.c +@@ -126,6 +126,12 @@ static int gpy_config_init(struct phy_de + if (ret < 0) + return ret; + ++ /* Disable SGMII auto-negotiation */ ++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, ++ VSPEC1_SGMII_CTRL_ANEN, 0); ++ if (ret < 0) ++ return ret; ++ + return gpy_led_write(phydev); + } + +@@ -151,65 +157,6 @@ static int gpy_probe(struct phy_device * + return 0; + } + +-static bool gpy_sgmii_need_reaneg(struct phy_device *phydev) +-{ +- int fw_ver, fw_type, fw_minor; +- size_t i; +- +- fw_ver = phy_read(phydev, PHY_FWV); +- if (fw_ver < 0) +- return true; +- +- fw_type = FIELD_GET(PHY_FWV_TYPE_MASK, fw_ver); +- fw_minor = FIELD_GET(PHY_FWV_MINOR_MASK, fw_ver); +- +- for (i = 0; i < ARRAY_SIZE(ver_need_sgmii_reaneg); i++) { +- if (fw_type != ver_need_sgmii_reaneg[i].type) +- continue; +- if (fw_minor < ver_need_sgmii_reaneg[i].minor) +- return true; +- break; +- } +- +- return false; +-} +- +-static bool gpy_2500basex_chk(struct phy_device *phydev) +-{ +- int ret; +- +- ret = phy_read(phydev, PHY_MIISTAT); +- if (ret < 0) { +- phydev_err(phydev, "Error: MDIO register access failed: %d\n", +- ret); +- return false; +- } +- +- if (!(ret & PHY_MIISTAT_LS) || +- FIELD_GET(PHY_MIISTAT_SPD_MASK, ret) != PHY_MIISTAT_SPD_2500) +- return false; +- +- phydev->speed = SPEED_2500; +- phydev->interface = PHY_INTERFACE_MODE_2500BASEX; +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, +- VSPEC1_SGMII_CTRL_ANEN, 0); +- return true; +-} +- +-static bool gpy_sgmii_aneg_en(struct phy_device *phydev) +-{ +- int ret; +- +- ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL); +- if (ret < 0) { +- phydev_err(phydev, "Error: MMD register access failed: %d\n", +- ret); +- return true; +- } +- +- return (ret & VSPEC1_SGMII_CTRL_ANEN) ? true : false; +-} +- + static int gpy_config_aneg(struct phy_device *phydev) + { + bool changed = false; +@@ -248,53 +195,11 @@ static int gpy_config_aneg(struct phy_de + phydev->interface == PHY_INTERFACE_MODE_INTERNAL) + return 0; + +- /* No need to trigger re-ANEG if link speed is 2.5G or SGMII ANEG is +- * disabled. +- */ +- if (!gpy_sgmii_need_reaneg(phydev) || gpy_2500basex_chk(phydev) || +- !gpy_sgmii_aneg_en(phydev)) +- return 0; +- +- /* There is a design constraint in GPY2xx device where SGMII AN is +- * only triggered when there is change of speed. If, PHY link +- * partner`s speed is still same even after PHY TPI is down and up +- * again, SGMII AN is not triggered and hence no new in-band message +- * from GPY to MAC side SGMII. +- * This could cause an issue during power up, when PHY is up prior to +- * MAC. At this condition, once MAC side SGMII is up, MAC side SGMII +- * wouldn`t receive new in-band message from GPY with correct link +- * status, speed and duplex info. +- * +- * 1) If PHY is already up and TPI link status is still down (such as +- * hard reboot), TPI link status is polled for 4 seconds before +- * retriggerring SGMII AN. +- * 2) If PHY is already up and TPI link status is also up (such as soft +- * reboot), polling of TPI link status is not needed and SGMII AN is +- * immediately retriggered. +- * 3) Other conditions such as PHY is down, speed change etc, skip +- * retriggering SGMII AN. Note: in case of speed change, GPY FW will +- * initiate SGMII AN. +- */ +- +- if (phydev->state != PHY_UP) +- return 0; +- +- ret = phy_read_poll_timeout(phydev, MII_BMSR, ret, ret & BMSR_LSTATUS, +- 20000, 4000000, false); +- if (ret == -ETIMEDOUT) +- return 0; +- else if (ret < 0) +- return ret; +- +- /* Trigger SGMII AN. */ +- return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, +- VSPEC1_SGMII_CTRL_ANRS, VSPEC1_SGMII_CTRL_ANRS); ++ return 0; + } + + static void gpy_update_interface(struct phy_device *phydev) + { +- int ret; +- + /* Interface mode is fixed for USXGMII and integrated PHY */ + if (phydev->interface == PHY_INTERFACE_MODE_USXGMII || + phydev->interface == PHY_INTERFACE_MODE_INTERNAL) +@@ -306,29 +211,11 @@ static void gpy_update_interface(struct + switch (phydev->speed) { + case SPEED_2500: + phydev->interface = PHY_INTERFACE_MODE_2500BASEX; +- ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, +- VSPEC1_SGMII_CTRL_ANEN, 0); +- if (ret < 0) +- phydev_err(phydev, +- "Error: Disable of SGMII ANEG failed: %d\n", +- ret); + break; + case SPEED_1000: + case SPEED_100: + case SPEED_10: + phydev->interface = PHY_INTERFACE_MODE_SGMII; +- if (gpy_sgmii_aneg_en(phydev)) +- break; +- /* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed +- * if ANEG is disabled (in 2500-BaseX mode). +- */ +- ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, +- VSPEC1_SGMII_ANEN_ANRS, +- VSPEC1_SGMII_ANEN_ANRS); +- if (ret < 0) +- phydev_err(phydev, +- "Error: Enable of SGMII ANEG failed: %d\n", +- ret); + break; + } + } diff --git a/target/linux/mediatek/patches-6.1/732-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch b/target/linux/mediatek/patches-6.1/732-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch new file mode 100644 index 00000000000..7151eb35cc0 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/732-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch @@ -0,0 +1,39 @@ +From 128dc09b0af36772062142ce9e85b19c84ac789a Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Tue, 28 Feb 2023 17:53:37 +0000 +Subject: [PATCH] net: phy: add driver for MediaTek 2.5G PHY + +Signed-off-by: Daniel Golle +--- + drivers/net/phy/Kconfig | 7 ++ + drivers/net/phy/Makefile | 1 + + drivers/net/phy/mediatek-2p5ge.c | 220 +++++++++++++++++++++++++++++++ + 3 files changed, 226 insertions(+) + create mode 100644 drivers/net/phy/mediatek-2p5ge.c + +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -305,6 +305,13 @@ config MEDIATEK_GE_SOC_PHY + present in the SoCs efuse and will dynamically calibrate VCM + (common-mode voltage) during startup. + ++config MEDIATEK_2P5G_PHY ++ tristate "MediaTek 2.5G Ethernet PHY" ++ depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST ++ default NET_MEDIATEK_SOC ++ help ++ Supports the MediaTek 2.5G Ethernet PHY. ++ + config MICREL_PHY + tristate "Micrel PHYs" + help +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -80,6 +80,7 @@ obj-$(CONFIG_MARVELL_10G_PHY) += marvell + obj-$(CONFIG_MARVELL_PHY) += marvell.o + obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o + obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o ++obj-$(CONFIG_MEDIATEK_2P5G_PHY) += mediatek-2p5ge.o + obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o + obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mediatek-ge-soc.o + obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o diff --git a/target/linux/mediatek/patches-6.1/801-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch b/target/linux/mediatek/patches-6.1/801-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch new file mode 100644 index 00000000000..691a7c0398e --- /dev/null +++ b/target/linux/mediatek/patches-6.1/801-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch @@ -0,0 +1,225 @@ +From 41ffe32e7ec23f592e21c508b5108899ad393059 Mon Sep 17 00:00:00 2001 +From: Zhanyong Wang +Date: Tue, 25 Jan 2022 16:50:47 +0800 +Subject: [PATCH 4/5] phy: phy-mtk-tphy: Add PCIe 2 lane efuse support + +Add PCIe 2 lane efuse support in tphy driver. + +Signed-off-by: Jie Yang +Signed-off-by: Zhanyong Wang +--- + drivers/phy/mediatek/phy-mtk-tphy.c | 140 ++++++++++++++++++++++++++++ + 1 file changed, 140 insertions(+) + +--- a/drivers/phy/mediatek/phy-mtk-tphy.c ++++ b/drivers/phy/mediatek/phy-mtk-tphy.c +@@ -44,6 +44,15 @@ + #define SSUSB_SIFSLV_V2_U3PHYD 0x200 + #define SSUSB_SIFSLV_V2_U3PHYA 0x400 + ++/* version V4 sub-banks offset base address */ ++/* pcie phy banks */ ++#define SSUSB_SIFSLV_V4_SPLLC 0x000 ++#define SSUSB_SIFSLV_V4_CHIP 0x100 ++#define SSUSB_SIFSLV_V4_U3PHYD 0x900 ++#define SSUSB_SIFSLV_V4_U3PHYA 0xb00 ++ ++#define SSUSB_LN1_OFFSET 0x10000 ++ + #define U3P_MISC_REG1 0x04 + #define MR1_EFUSE_AUTO_LOAD_DIS BIT(6) + +@@ -320,6 +329,7 @@ enum mtk_phy_version { + MTK_PHY_V1 = 1, + MTK_PHY_V2, + MTK_PHY_V3, ++ MTK_PHY_V4, + }; + + struct mtk_phy_pdata { +@@ -369,6 +379,9 @@ struct mtk_phy_instance { + u32 efuse_intr; + u32 efuse_tx_imp; + u32 efuse_rx_imp; ++ u32 efuse_intr_ln1; ++ u32 efuse_tx_imp_ln1; ++ u32 efuse_rx_imp_ln1; + int eye_src; + int eye_vrt; + int eye_term; +@@ -946,6 +959,36 @@ static void phy_v2_banks_init(struct mtk + } + } + ++static void phy_v4_banks_init(struct mtk_tphy *tphy, ++ struct mtk_phy_instance *instance) ++{ ++ struct u2phy_banks *u2_banks = &instance->u2_banks; ++ struct u3phy_banks *u3_banks = &instance->u3_banks; ++ ++ switch (instance->type) { ++ case PHY_TYPE_USB2: ++ u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC; ++ u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ; ++ u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM; ++ break; ++ case PHY_TYPE_USB3: ++ u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC; ++ u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP; ++ u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD; ++ u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA; ++ break; ++ case PHY_TYPE_PCIE: ++ u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V4_SPLLC; ++ u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V4_CHIP; ++ u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V4_U3PHYD; ++ u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V4_U3PHYA; ++ break; ++ default: ++ dev_err(tphy->dev, "incompatible PHY type\n"); ++ return; ++ } ++} ++ + static void phy_parse_property(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) + { +@@ -1144,6 +1187,40 @@ static int phy_efuse_get(struct mtk_tphy + + dev_dbg(dev, "u3 efuse - intr %x, rx_imp %x, tx_imp %x\n", + instance->efuse_intr, instance->efuse_rx_imp,instance->efuse_tx_imp); ++ ++ if (tphy->pdata->version != MTK_PHY_V4) ++ break; ++ ++ ret = nvmem_cell_read_variable_le_u32(dev, "intr_ln1", &instance->efuse_intr_ln1); ++ if (ret) { ++ dev_err(dev, "fail to get u3 lane1 intr efuse, %d\n", ret); ++ break; ++ } ++ ++ ret = nvmem_cell_read_variable_le_u32(dev, "rx_imp_ln1", &instance->efuse_rx_imp_ln1); ++ if (ret) { ++ dev_err(dev, "fail to get u3 lane1 rx_imp efuse, %d\n", ret); ++ break; ++ } ++ ++ ret = nvmem_cell_read_variable_le_u32(dev, "tx_imp_ln1", &instance->efuse_tx_imp_ln1); ++ if (ret) { ++ dev_err(dev, "fail to get u3 lane1 tx_imp efuse, %d\n", ret); ++ break; ++ } ++ ++ /* no efuse, ignore it */ ++ if (!instance->efuse_intr_ln1 && ++ !instance->efuse_rx_imp_ln1 && ++ !instance->efuse_tx_imp_ln1) { ++ dev_warn(dev, "no u3 lane1 efuse, but dts enable it\n"); ++ instance->efuse_sw_en = 0; ++ break; ++ } ++ ++ dev_info(dev, "u3 lane1 efuse - intr %x, rx_imp %x, tx_imp %x\n", ++ instance->efuse_intr_ln1, instance->efuse_rx_imp_ln1, ++ instance->efuse_tx_imp_ln1); + break; + default: + dev_err(dev, "no sw efuse for type %d\n", instance->type); +@@ -1175,6 +1252,31 @@ static void phy_efuse_set(struct mtk_phy + writel(tmp, u2_banks->com + U3P_USBPHYACR1); + break; + case PHY_TYPE_USB3: ++ tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV); ++ tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS; ++ writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV); ++ ++ tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0); ++ tmp &= ~P3D_RG_TX_IMPEL; ++ tmp |= P3D_RG_TX_IMPEL_VAL(instance->efuse_tx_imp); ++ tmp |= P3D_RG_FORCE_TX_IMPEL; ++ writel(tmp, u3_banks->phyd + U3P_U3_PHYD_IMPCAL0); ++ ++ tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1); ++ tmp &= ~P3D_RG_RX_IMPEL; ++ tmp |= P3D_RG_RX_IMPEL_VAL(instance->efuse_rx_imp); ++ tmp |= P3D_RG_FORCE_RX_IMPEL; ++ writel(tmp, u3_banks->phyd + U3P_U3_PHYD_IMPCAL1); ++ ++ tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0); ++ tmp &= ~P3A_RG_IEXT_INTR; ++ tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr); ++ writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0); ++ pr_err("%s set efuse, tx_imp %x, rx_imp %x intr %x\n", ++ __func__, instance->efuse_tx_imp, ++ instance->efuse_rx_imp, instance->efuse_intr); ++ ++ break; + case PHY_TYPE_PCIE: + tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV); + tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS; +@@ -1196,6 +1298,34 @@ static void phy_efuse_set(struct mtk_phy + tmp &= ~P3A_RG_IEXT_INTR; + tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0); ++ if (!instance->efuse_intr_ln1 && ++ !instance->efuse_rx_imp_ln1 && ++ !instance->efuse_tx_imp_ln1) ++ break; ++ ++ tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV); ++ tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS; ++ writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV); ++ ++ tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL0); ++ tmp &= ~P3D_RG_TX_IMPEL; ++ tmp |= P3D_RG_TX_IMPEL_VAL(instance->efuse_tx_imp_ln1); ++ tmp |= P3D_RG_FORCE_TX_IMPEL; ++ writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL0); ++ ++ tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL1); ++ tmp &= ~P3D_RG_RX_IMPEL; ++ tmp |= P3D_RG_RX_IMPEL_VAL(instance->efuse_rx_imp_ln1); ++ tmp |= P3D_RG_FORCE_RX_IMPEL; ++ writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL1); ++ ++ tmp = readl(u3_banks->phya + SSUSB_LN1_OFFSET + U3P_U3_PHYA_REG0); ++ tmp &= ~P3A_RG_IEXT_INTR; ++ tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr_ln1); ++ writel(tmp, u3_banks->phya + SSUSB_LN1_OFFSET + U3P_U3_PHYA_REG0); ++ dev_info(dev, "%s set LN1 efuse, tx_imp %x, rx_imp %x intr %x\n", ++ __func__, instance->efuse_tx_imp_ln1, ++ instance->efuse_rx_imp_ln1, instance->efuse_intr_ln1); + break; + default: + dev_warn(dev, "no sw efuse for type %d\n", instance->type); +@@ -1335,6 +1465,9 @@ static struct phy *mtk_phy_xlate(struct + case MTK_PHY_V3: + phy_v2_banks_init(tphy, instance); + break; ++ case MTK_PHY_V4: ++ phy_v4_banks_init(tphy, instance); ++ break; + default: + dev_err(dev, "phy version is not supported\n"); + return ERR_PTR(-EINVAL); +@@ -1375,6 +1508,12 @@ static const struct mtk_phy_pdata tphy_v + .version = MTK_PHY_V3, + }; + ++static const struct mtk_phy_pdata tphy_v4_pdata = { ++ .avoid_rx_sen_degradation = false, ++ .sw_efuse_supported = true, ++ .version = MTK_PHY_V4, ++}; ++ + static const struct mtk_phy_pdata mt8173_pdata = { + .avoid_rx_sen_degradation = true, + .version = MTK_PHY_V1, +@@ -1394,6 +1533,7 @@ static const struct of_device_id mtk_tph + { .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata }, + { .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata }, + { .compatible = "mediatek,generic-tphy-v3", .data = &tphy_v3_pdata }, ++ { .compatible = "mediatek,generic-tphy-v4", .data = &tphy_v4_pdata }, + { }, + }; + MODULE_DEVICE_TABLE(of, mtk_tphy_id_table); diff --git a/target/linux/mediatek/patches-6.1/802-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch b/target/linux/mediatek/patches-6.1/802-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch new file mode 100644 index 00000000000..3b8285bf479 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/802-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch @@ -0,0 +1,149 @@ +From 1d5819e90f2ef6dead11809744372a9863227a92 Mon Sep 17 00:00:00 2001 +From: Zhanyong Wang +Date: Tue, 25 Jan 2022 19:03:34 +0800 +Subject: [PATCH 5/5] phy: phy-mtk-tphy: add auto-load-valid check mechanism + support + +add auto-load-valid check mechanism support + +Signed-off-by: Zhanyong Wang +--- + drivers/phy/mediatek/phy-mtk-tphy.c | 67 +++++++++++++++++++++++++++-- + 1 file changed, 64 insertions(+), 3 deletions(-) + +--- a/drivers/phy/mediatek/phy-mtk-tphy.c ++++ b/drivers/phy/mediatek/phy-mtk-tphy.c +@@ -376,9 +376,13 @@ struct mtk_phy_instance { + u32 type_sw_reg; + u32 type_sw_index; + u32 efuse_sw_en; ++ bool efuse_alv_en; ++ u32 efuse_autoloadvalid; + u32 efuse_intr; + u32 efuse_tx_imp; + u32 efuse_rx_imp; ++ bool efuse_alv_ln1_en; ++ u32 efuse_ln1_autoloadvalid; + u32 efuse_intr_ln1; + u32 efuse_tx_imp_ln1; + u32 efuse_rx_imp_ln1; +@@ -1126,6 +1130,7 @@ static int phy_efuse_get(struct mtk_tphy + { + struct device *dev = &instance->phy->dev; + int ret = 0; ++ bool alv = false; + + /* tphy v1 doesn't support sw efuse, skip it */ + if (!tphy->pdata->sw_efuse_supported) { +@@ -1140,6 +1145,20 @@ static int phy_efuse_get(struct mtk_tphy + + switch (instance->type) { + case PHY_TYPE_USB2: ++ alv = of_property_read_bool(dev->of_node, "auto_load_valid"); ++ if (alv) { ++ instance->efuse_alv_en = alv; ++ ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid", ++ &instance->efuse_autoloadvalid); ++ if (ret) { ++ dev_err(dev, "fail to get u2 alv efuse, %d\n", ret); ++ break; ++ } ++ dev_info(dev, ++ "u2 auto load valid efuse: ENABLE with value: %u\n", ++ instance->efuse_autoloadvalid); ++ } ++ + ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr); + if (ret) { + dev_err(dev, "fail to get u2 intr efuse, %d\n", ret); +@@ -1158,6 +1177,20 @@ static int phy_efuse_get(struct mtk_tphy + + case PHY_TYPE_USB3: + case PHY_TYPE_PCIE: ++ alv = of_property_read_bool(dev->of_node, "auto_load_valid"); ++ if (alv) { ++ instance->efuse_alv_en = alv; ++ ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid", ++ &instance->efuse_autoloadvalid); ++ if (ret) { ++ dev_err(dev, "fail to get u3(pcei) alv efuse, %d\n", ret); ++ break; ++ } ++ dev_info(dev, ++ "u3 auto load valid efuse: ENABLE with value: %u\n", ++ instance->efuse_autoloadvalid); ++ } ++ + ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr); + if (ret) { + dev_err(dev, "fail to get u3 intr efuse, %d\n", ret); +@@ -1191,6 +1224,20 @@ static int phy_efuse_get(struct mtk_tphy + if (tphy->pdata->version != MTK_PHY_V4) + break; + ++ alv = of_property_read_bool(dev->of_node, "auto_load_valid_ln1"); ++ if (alv) { ++ instance->efuse_alv_ln1_en = alv; ++ ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid_ln1", ++ &instance->efuse_ln1_autoloadvalid); ++ if (ret) { ++ dev_err(dev, "fail to get pcie auto_load_valid efuse, %d\n", ret); ++ break; ++ } ++ dev_info(dev, ++ "pcie auto load valid efuse: ENABLE with value: %u\n", ++ instance->efuse_ln1_autoloadvalid); ++ } ++ + ret = nvmem_cell_read_variable_le_u32(dev, "intr_ln1", &instance->efuse_intr_ln1); + if (ret) { + dev_err(dev, "fail to get u3 lane1 intr efuse, %d\n", ret); +@@ -1242,6 +1289,10 @@ static void phy_efuse_set(struct mtk_phy + + switch (instance->type) { + case PHY_TYPE_USB2: ++ if (instance->efuse_alv_en && ++ instance->efuse_autoloadvalid == 1) ++ break; ++ + tmp = readl(u2_banks->misc + U3P_MISC_REG1); + tmp |= MR1_EFUSE_AUTO_LOAD_DIS; + writel(tmp, u2_banks->misc + U3P_MISC_REG1); +@@ -1252,6 +1303,10 @@ static void phy_efuse_set(struct mtk_phy + writel(tmp, u2_banks->com + U3P_USBPHYACR1); + break; + case PHY_TYPE_USB3: ++ if (instance->efuse_alv_en && ++ instance->efuse_autoloadvalid == 1) ++ break; ++ + tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV); + tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS; + writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV); +@@ -1278,6 +1333,10 @@ static void phy_efuse_set(struct mtk_phy + + break; + case PHY_TYPE_PCIE: ++ if (instance->efuse_alv_en && ++ instance->efuse_autoloadvalid == 1) ++ break; ++ + tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV); + tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS; + writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV); +@@ -1298,9 +1357,12 @@ static void phy_efuse_set(struct mtk_phy + tmp &= ~P3A_RG_IEXT_INTR; + tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0); +- if (!instance->efuse_intr_ln1 && +- !instance->efuse_rx_imp_ln1 && +- !instance->efuse_tx_imp_ln1) ++ ++ if ((!instance->efuse_intr_ln1 && ++ !instance->efuse_rx_imp_ln1 && ++ !instance->efuse_tx_imp_ln1) || ++ (instance->efuse_alv_ln1_en && ++ instance->efuse_ln1_autoloadvalid == 1)) + break; + + tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV); diff --git a/target/linux/mediatek/patches-6.1/804-pwm-add-mt7986-support.patch b/target/linux/mediatek/patches-6.1/804-pwm-add-mt7986-support.patch new file mode 100644 index 00000000000..7a10dac051c --- /dev/null +++ b/target/linux/mediatek/patches-6.1/804-pwm-add-mt7986-support.patch @@ -0,0 +1,23 @@ +--- a/drivers/pwm/pwm-mediatek.c ++++ b/drivers/pwm/pwm-mediatek.c +@@ -302,6 +302,12 @@ static const struct pwm_mediatek_of_data + .has_ck_26m_sel = true, + }; + ++static const struct pwm_mediatek_of_data mt7986_pwm_data = { ++ .num_pwms = 2, ++ .pwm45_fixup = false, ++ .has_ck_26m_sel = true, ++}; ++ + static const struct pwm_mediatek_of_data mt8516_pwm_data = { + .num_pwms = 5, + .pwm45_fixup = false, +@@ -314,6 +320,7 @@ static const struct of_device_id pwm_med + { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data }, + { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data }, + { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data }, ++ { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data }, + { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data }, + { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data }, + { }, diff --git a/target/linux/mediatek/patches-6.1/805-v6.2-thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch b/target/linux/mediatek/patches-6.1/805-v6.2-thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch new file mode 100644 index 00000000000..b142b22eb8d --- /dev/null +++ b/target/linux/mediatek/patches-6.1/805-v6.2-thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch @@ -0,0 +1,56 @@ +From 69c17529e8418da3eec703dde31e1b01e5b0f7e8 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Wed, 18 Jan 2023 02:48:41 +0000 +Subject: [PATCH 1/2] thermal/drivers/mtk: use function pointer for + raw_to_mcelsius + +Instead of having if-else logic selecting either raw_to_mcelsius_v1 or +raw_to_mcelsius_v2 in mtk_thermal_bank_temperature introduce a function +pointer raw_to_mcelsius to struct mtk_thermal which is initialized in the +probe function. + +Signed-off-by: Daniel Golle +--- + drivers/thermal/mtk_thermal.c | 17 ++++++++++------- + 1 file changed, 10 insertions(+), 7 deletions(-) + +--- a/drivers/thermal/mtk_thermal.c ++++ b/drivers/thermal/mtk_thermal.c +@@ -292,6 +292,8 @@ struct mtk_thermal { + + const struct mtk_thermal_data *conf; + struct mtk_thermal_bank banks[MAX_NUM_ZONES]; ++ ++ int (*raw_to_mcelsius)(struct mtk_thermal *mt, int sensno, s32 raw); + }; + + /* MT8183 thermal sensor data */ +@@ -656,13 +658,9 @@ static int mtk_thermal_bank_temperature( + for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) { + raw = readl(mt->thermal_base + conf->msr[i]); + +- if (mt->conf->version == MTK_THERMAL_V1) { +- temp = raw_to_mcelsius_v1( +- mt, conf->bank_data[bank->id].sensors[i], raw); +- } else { +- temp = raw_to_mcelsius_v2( +- mt, conf->bank_data[bank->id].sensors[i], raw); +- } ++ temp = mt->raw_to_mcelsius( ++ mt, conf->bank_data[bank->id].sensors[i], raw); ++ + + /* + * The first read of a sensor often contains very high bogus +@@ -1085,6 +1083,11 @@ static int mtk_thermal_probe(struct plat + mtk_thermal_release_periodic_ts(mt, auxadc_base); + } + ++ if (mt->conf->version == MTK_THERMAL_V1) ++ mt->raw_to_mcelsius = raw_to_mcelsius_v1; ++ else ++ mt->raw_to_mcelsius = raw_to_mcelsius_v2; ++ + for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++) + for (i = 0; i < mt->conf->num_banks; i++) + mtk_thermal_init_bank(mt, i, apmixed_phys_base, diff --git a/target/linux/mediatek/patches-6.1/806-v6.2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch b/target/linux/mediatek/patches-6.1/806-v6.2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch new file mode 100644 index 00000000000..3ac2e7fc28c --- /dev/null +++ b/target/linux/mediatek/patches-6.1/806-v6.2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch @@ -0,0 +1,240 @@ +From aa957c759b1182aee00cc35178667f849f941b42 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Wed, 30 Nov 2022 13:19:39 +0000 +Subject: [PATCH 2/2] thermal: mediatek: add support for MT7986 and MT7981 + +Add support for V3 generation thermal found in MT7986 and MT7981 SoCs. +Brings code to assign values from efuse as well as new function to +convert raw temperature to millidegree celsius, as found in MediaTek's +SDK sources (but cleaned up and de-duplicated) + +[1]: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/baf36c7eef477aae1f8f2653b6c29e2caf48475b +Signed-off-by: Daniel Golle +--- + drivers/thermal/mtk_thermal.c | 137 ++++++++++++++++++++++++++++++++-- + 1 file changed, 132 insertions(+), 5 deletions(-) + +--- a/drivers/thermal/mtk_thermal.c ++++ b/drivers/thermal/mtk_thermal.c +@@ -150,6 +150,20 @@ + #define CALIB_BUF1_VALID_V2(x) (((x) >> 4) & 0x1) + #define CALIB_BUF1_O_SLOPE_SIGN_V2(x) (((x) >> 3) & 0x1) + ++/* ++ * Layout of the fuses providing the calibration data ++ * These macros can be used for MT7981 and MT7986. ++ */ ++#define CALIB_BUF0_ADC_GE_V3(x) (((x) >> 0) & 0x3ff) ++#define CALIB_BUF0_DEGC_CALI_V3(x) (((x) >> 20) & 0x3f) ++#define CALIB_BUF0_O_SLOPE_V3(x) (((x) >> 26) & 0x3f) ++#define CALIB_BUF1_VTS_TS1_V3(x) (((x) >> 0) & 0x1ff) ++#define CALIB_BUF1_VTS_TS2_V3(x) (((x) >> 21) & 0x1ff) ++#define CALIB_BUF1_VTS_TSABB_V3(x) (((x) >> 9) & 0x1ff) ++#define CALIB_BUF1_VALID_V3(x) (((x) >> 18) & 0x1) ++#define CALIB_BUF1_O_SLOPE_SIGN_V3(x) (((x) >> 19) & 0x1) ++#define CALIB_BUF1_ID_V3(x) (((x) >> 20) & 0x1) ++ + enum { + VTS1, + VTS2, +@@ -163,6 +177,7 @@ enum { + enum mtk_thermal_version { + MTK_THERMAL_V1 = 1, + MTK_THERMAL_V2, ++ MTK_THERMAL_V3, + }; + + /* MT2701 thermal sensors */ +@@ -245,6 +260,27 @@ enum mtk_thermal_version { + /* The calibration coefficient of sensor */ + #define MT8183_CALIBRATION 153 + ++/* AUXADC channel 11 is used for the temperature sensors */ ++#define MT7986_TEMP_AUXADC_CHANNEL 11 ++ ++/* The total number of temperature sensors in the MT7986 */ ++#define MT7986_NUM_SENSORS 1 ++ ++/* The number of banks in the MT7986 */ ++#define MT7986_NUM_ZONES 1 ++ ++/* The number of sensing points per bank */ ++#define MT7986_NUM_SENSORS_PER_ZONE 1 ++ ++/* MT7986 thermal sensors */ ++#define MT7986_TS1 0 ++ ++/* The number of controller in the MT7986 */ ++#define MT7986_NUM_CONTROLLER 1 ++ ++/* The calibration coefficient of sensor */ ++#define MT7986_CALIBRATION 165 ++ + struct mtk_thermal; + + struct thermal_bank_cfg { +@@ -388,6 +424,14 @@ static const int mt7622_mux_values[MT762 + static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 }; + static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, }; + ++/* MT7986 thermal sensor data */ ++static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, }; ++static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, }; ++static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, }; ++static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, }; ++static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 }; ++static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, }; ++ + /* + * The MT8173 thermal controller has four banks. Each bank can read up to + * four temperature sensors simultaneously. The MT8173 has a total of 5 +@@ -551,6 +595,30 @@ static const struct mtk_thermal_data mt8 + .version = MTK_THERMAL_V1, + }; + ++/* ++ * MT7986 uses AUXADC Channel 11 for raw data access. ++ */ ++static const struct mtk_thermal_data mt7986_thermal_data = { ++ .auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL, ++ .num_banks = MT7986_NUM_ZONES, ++ .num_sensors = MT7986_NUM_SENSORS, ++ .vts_index = mt7986_vts_index, ++ .cali_val = MT7986_CALIBRATION, ++ .num_controller = MT7986_NUM_CONTROLLER, ++ .controller_offset = mt7986_tc_offset, ++ .need_switch_bank = true, ++ .bank_data = { ++ { ++ .num_sensors = 1, ++ .sensors = mt7986_bank_data, ++ }, ++ }, ++ .msr = mt7986_msr, ++ .adcpnp = mt7986_adcpnp, ++ .sensor_mux_values = mt7986_mux_values, ++ .version = MTK_THERMAL_V3, ++}; ++ + /** + * raw_to_mcelsius - convert a raw ADC value to mcelsius + * @mt: The thermal controller +@@ -605,6 +673,22 @@ static int raw_to_mcelsius_v2(struct mtk + return (format_2 - tmp) * 100; + } + ++static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw) ++{ ++ s32 tmp; ++ ++ if (raw == 0) ++ return 0; ++ ++ raw &= 0xfff; ++ tmp = 100000 * 15 / 16 * 10000; ++ tmp /= 4096 - 512 + mt->adc_ge; ++ tmp /= 1490; ++ tmp *= raw - mt->vts[sensno] - 2900; ++ ++ return mt->degc_cali * 500 - tmp; ++} ++ + /** + * mtk_thermal_get_bank - get bank + * @bank: The bank +@@ -885,6 +969,25 @@ static int mtk_thermal_extract_efuse_v2( + return 0; + } + ++static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf) ++{ ++ if (!CALIB_BUF1_VALID_V3(buf[1])) ++ return -EINVAL; ++ ++ mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]); ++ mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]); ++ mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]); ++ mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]); ++ mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]); ++ mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]); ++ mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]); ++ ++ if (CALIB_BUF1_ID_V3(buf[1]) == 0) ++ mt->o_slope = 0; ++ ++ return 0; ++} ++ + static int mtk_thermal_get_calibration_data(struct device *dev, + struct mtk_thermal *mt) + { +@@ -895,6 +998,7 @@ static int mtk_thermal_get_calibration_d + + /* Start with default values */ + mt->adc_ge = 512; ++ mt->adc_oe = 512; + for (i = 0; i < mt->conf->num_sensors; i++) + mt->vts[i] = 260; + mt->degc_cali = 40; +@@ -920,10 +1024,20 @@ static int mtk_thermal_get_calibration_d + goto out; + } + +- if (mt->conf->version == MTK_THERMAL_V1) ++ switch (mt->conf->version) { ++ case MTK_THERMAL_V1: + ret = mtk_thermal_extract_efuse_v1(mt, buf); +- else ++ break; ++ case MTK_THERMAL_V2: + ret = mtk_thermal_extract_efuse_v2(mt, buf); ++ break; ++ case MTK_THERMAL_V3: ++ ret = mtk_thermal_extract_efuse_v3(mt, buf); ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } + + if (ret) { + dev_info(dev, "Device not calibrated, using default calibration values\n"); +@@ -954,6 +1068,10 @@ static const struct of_device_id mtk_the + .data = (void *)&mt7622_thermal_data, + }, + { ++ .compatible = "mediatek,mt7986-thermal", ++ .data = (void *)&mt7986_thermal_data, ++ }, ++ { + .compatible = "mediatek,mt8183-thermal", + .data = (void *)&mt8183_thermal_data, + }, { +@@ -1078,15 +1196,24 @@ static int mtk_thermal_probe(struct plat + goto err_disable_clk_auxadc; + } + +- if (mt->conf->version == MTK_THERMAL_V2) { ++ if (mt->conf->version != MTK_THERMAL_V1) { + mtk_thermal_turn_on_buffer(apmixed_base); + mtk_thermal_release_periodic_ts(mt, auxadc_base); + } + +- if (mt->conf->version == MTK_THERMAL_V1) ++ switch (mt->conf->version) { ++ case MTK_THERMAL_V1: + mt->raw_to_mcelsius = raw_to_mcelsius_v1; +- else ++ break; ++ case MTK_THERMAL_V2: + mt->raw_to_mcelsius = raw_to_mcelsius_v2; ++ break; ++ case MTK_THERMAL_V3: ++ mt->raw_to_mcelsius = raw_to_mcelsius_v3; ++ break; ++ default: ++ break; ++ } + + for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++) + for (i = 0; i < mt->conf->num_banks; i++) diff --git a/target/linux/mediatek/patches-6.1/811-pwm-mediatek-Add-support-for-MT7981.patch b/target/linux/mediatek/patches-6.1/811-pwm-mediatek-Add-support-for-MT7981.patch new file mode 100644 index 00000000000..8f27462cbdc --- /dev/null +++ b/target/linux/mediatek/patches-6.1/811-pwm-mediatek-Add-support-for-MT7981.patch @@ -0,0 +1,122 @@ +From 73d20ebc21c562fbe79d02fa0fa38e095e716fa9 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Wed, 19 Apr 2023 20:25:51 +0100 +Subject: [PATCH] pwm: mediatek: Add support for MT7981 + +The PWM unit on MT7981 uses different register offsets than previous +MediaTek PWM units. Add support for these new offsets and add support +for PWM on MT7981 which has 3 PWM channels, one of them is typically +used for a temperature controlled fan. + +Signed-off-by: Daniel Golle +--- + drivers/pwm/pwm-mediatek.c | 41 ++++++++++++++++++++++++++++++-------- + 1 file changed, 33 insertions(+), 8 deletions(-) + +--- a/drivers/pwm/pwm-mediatek.c ++++ b/drivers/pwm/pwm-mediatek.c +@@ -38,6 +38,7 @@ struct pwm_mediatek_of_data { + unsigned int num_pwms; + bool pwm45_fixup; + bool has_ck_26m_sel; ++ const unsigned int *reg_offset; + }; + + /** +@@ -59,10 +60,14 @@ struct pwm_mediatek_chip { + const struct pwm_mediatek_of_data *soc; + }; + +-static const unsigned int pwm_mediatek_reg_offset[] = { ++static const unsigned int mtk_pwm_reg_offset_v1[] = { + 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220 + }; + ++static const unsigned int mtk_pwm_reg_offset_v2[] = { ++ 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240 ++}; ++ + static inline struct pwm_mediatek_chip * + to_pwm_mediatek_chip(struct pwm_chip *chip) + { +@@ -111,7 +116,7 @@ static inline void pwm_mediatek_writel(s + unsigned int num, unsigned int offset, + u32 value) + { +- writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset); ++ writel(value, chip->regs + chip->soc->reg_offset[num] + offset); + } + + static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm, +@@ -270,48 +275,63 @@ static const struct pwm_mediatek_of_data + .num_pwms = 8, + .pwm45_fixup = false, + .has_ck_26m_sel = false, ++ .reg_offset = mtk_pwm_reg_offset_v1, + }; + + static const struct pwm_mediatek_of_data mt7622_pwm_data = { + .num_pwms = 6, + .pwm45_fixup = false, + .has_ck_26m_sel = true, ++ .reg_offset = mtk_pwm_reg_offset_v1, + }; + + static const struct pwm_mediatek_of_data mt7623_pwm_data = { + .num_pwms = 5, + .pwm45_fixup = true, + .has_ck_26m_sel = false, ++ .reg_offset = mtk_pwm_reg_offset_v1, + }; + + static const struct pwm_mediatek_of_data mt7628_pwm_data = { + .num_pwms = 4, + .pwm45_fixup = true, + .has_ck_26m_sel = false, ++ .reg_offset = mtk_pwm_reg_offset_v1, + }; + + static const struct pwm_mediatek_of_data mt7629_pwm_data = { + .num_pwms = 1, + .pwm45_fixup = false, + .has_ck_26m_sel = false, ++ .reg_offset = mtk_pwm_reg_offset_v1, + }; + + static const struct pwm_mediatek_of_data mt8183_pwm_data = { + .num_pwms = 4, + .pwm45_fixup = false, + .has_ck_26m_sel = true, ++ .reg_offset = mtk_pwm_reg_offset_v1, ++}; ++ ++static const struct pwm_mediatek_of_data mt7981_pwm_data = { ++ .num_pwms = 3, ++ .pwm45_fixup = false, ++ .has_ck_26m_sel = true, ++ .reg_offset = mtk_pwm_reg_offset_v2, + }; + + static const struct pwm_mediatek_of_data mt7986_pwm_data = { + .num_pwms = 2, + .pwm45_fixup = false, + .has_ck_26m_sel = true, ++ .reg_offset = mtk_pwm_reg_offset_v1, + }; + + static const struct pwm_mediatek_of_data mt8516_pwm_data = { + .num_pwms = 5, + .pwm45_fixup = false, + .has_ck_26m_sel = true, ++ .reg_offset = mtk_pwm_reg_offset_v1, + }; + + static const struct of_device_id pwm_mediatek_of_match[] = { +@@ -320,6 +340,7 @@ static const struct of_device_id pwm_med + { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data }, + { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data }, + { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data }, ++ { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data }, + { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data }, + { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data }, + { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data }, diff --git a/target/linux/mediatek/patches-6.1/820-v5.16-dt-bindings-pinctrl-mt8195-add-rsel-define.patch b/target/linux/mediatek/patches-6.1/820-v5.16-dt-bindings-pinctrl-mt8195-add-rsel-define.patch new file mode 100644 index 00000000000..f2be737146e --- /dev/null +++ b/target/linux/mediatek/patches-6.1/820-v5.16-dt-bindings-pinctrl-mt8195-add-rsel-define.patch @@ -0,0 +1,33 @@ +From 26564c44357e19d03c124550bbd0b5851e6638c2 Mon Sep 17 00:00:00 2001 +From: Zhiyong Tao +Date: Fri, 24 Sep 2021 16:06:28 +0800 +Subject: [PATCH] dt-bindings: pinctrl: mt8195: add rsel define + +This patch adds rsel define for mt8195. + +Signed-off-by: Zhiyong Tao +Acked-by: Rob Herring +Link: https://lore.kernel.org/r/20210924080632.28410-2-zhiyong.tao@mediatek.com +Signed-off-by: Linus Walleij +--- + include/dt-bindings/pinctrl/mt65xx.h | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/include/dt-bindings/pinctrl/mt65xx.h ++++ b/include/dt-bindings/pinctrl/mt65xx.h +@@ -16,6 +16,15 @@ + #define MTK_PUPD_SET_R1R0_10 102 + #define MTK_PUPD_SET_R1R0_11 103 + ++#define MTK_PULL_SET_RSEL_000 200 ++#define MTK_PULL_SET_RSEL_001 201 ++#define MTK_PULL_SET_RSEL_010 202 ++#define MTK_PULL_SET_RSEL_011 203 ++#define MTK_PULL_SET_RSEL_100 204 ++#define MTK_PULL_SET_RSEL_101 205 ++#define MTK_PULL_SET_RSEL_110 206 ++#define MTK_PULL_SET_RSEL_111 207 ++ + #define MTK_DRIVE_2mA 2 + #define MTK_DRIVE_4mA 4 + #define MTK_DRIVE_6mA 6 diff --git a/target/linux/mediatek/patches-6.1/821-v5.16-pinctrl-mediatek-moore-check-if-pin_desc-is-valid-be.patch b/target/linux/mediatek/patches-6.1/821-v5.16-pinctrl-mediatek-moore-check-if-pin_desc-is-valid-be.patch new file mode 100644 index 00000000000..aa9f879e3aa --- /dev/null +++ b/target/linux/mediatek/patches-6.1/821-v5.16-pinctrl-mediatek-moore-check-if-pin_desc-is-valid-be.patch @@ -0,0 +1,93 @@ +From d8b94c9ff96c2024a527086d850eb0b314337ff9 Mon Sep 17 00:00:00 2001 +From: Sam Shih +Date: Tue, 14 Sep 2021 16:51:32 +0800 +Subject: [PATCH] pinctrl: mediatek: moore: check if pin_desc is valid before + use + +Certain SoC are missing the middle part gpios in consecutive pins, +it's better to check if mtk_pin_desc is a valid pin for the extensibility + +Signed-off-by: Sam Shih +Acked-by: Sean Wang +Link: https://lore.kernel.org/r/20210914085137.31761-5-sam.shih@mediatek.com +Signed-off-by: Linus Walleij +--- + drivers/pinctrl/mediatek/pinctrl-moore.c | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +--- a/drivers/pinctrl/mediatek/pinctrl-moore.c ++++ b/drivers/pinctrl/mediatek/pinctrl-moore.c +@@ -60,6 +60,8 @@ static int mtk_pinmux_set_mux(struct pin + int pin = grp->pins[i]; + + desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; ++ if (!desc->name) ++ return -ENOTSUPP; + + mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, + pin_modes[i]); +@@ -76,6 +78,8 @@ static int mtk_pinmux_gpio_request_enabl + const struct mtk_pin_desc *desc; + + desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; ++ if (!desc->name) ++ return -ENOTSUPP; + + return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, + hw->soc->gpio_m); +@@ -89,6 +93,8 @@ static int mtk_pinmux_gpio_set_direction + const struct mtk_pin_desc *desc; + + desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; ++ if (!desc->name) ++ return -ENOTSUPP; + + /* hardware would take 0 as input direction */ + return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input); +@@ -103,6 +109,8 @@ static int mtk_pinconf_get(struct pinctr + const struct mtk_pin_desc *desc; + + desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; ++ if (!desc->name) ++ return -ENOTSUPP; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: +@@ -218,6 +226,8 @@ static int mtk_pinconf_set(struct pinctr + int cfg, err = 0; + + desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; ++ if (!desc->name) ++ return -ENOTSUPP; + + for (cfg = 0; cfg < num_configs; cfg++) { + param = pinconf_to_config_param(configs[cfg]); +@@ -435,6 +445,8 @@ static int mtk_gpio_get(struct gpio_chip + int value, err; + + desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; ++ if (!desc->name) ++ return -ENOTSUPP; + + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value); + if (err) +@@ -449,6 +461,10 @@ static void mtk_gpio_set(struct gpio_chi + const struct mtk_pin_desc *desc; + + desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; ++ if (!desc->name) { ++ dev_err(hw->dev, "Failed to set gpio %d\n", gpio); ++ return; ++ } + + mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value); + } +@@ -490,6 +506,8 @@ static int mtk_gpio_set_config(struct gp + u32 debounce; + + desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset]; ++ if (!desc->name) ++ return -ENOTSUPP; + + if (!hw->eint || + pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE || diff --git a/target/linux/mediatek/patches-6.1/822-v5.16-pinctrl-mediatek-support-rsel-feature.patch b/target/linux/mediatek/patches-6.1/822-v5.16-pinctrl-mediatek-support-rsel-feature.patch new file mode 100644 index 00000000000..0f5c0495fef --- /dev/null +++ b/target/linux/mediatek/patches-6.1/822-v5.16-pinctrl-mediatek-support-rsel-feature.patch @@ -0,0 +1,457 @@ +From fb34a9ae383ae26326d4889fd2513e49f1019b88 Mon Sep 17 00:00:00 2001 +From: Zhiyong Tao +Date: Fri, 24 Sep 2021 16:06:31 +0800 +Subject: [PATCH] pinctrl: mediatek: support rsel feature + +This patch supports rsel(resistance selection) feature for I2C pins. +It provides more resistance selection solution in different ICs. +It provides rsel define and si unit solution by identifying +"mediatek,rsel_resistance_in_si_unit" property in pio dtsi node. + +Signed-off-by: Zhiyong Tao +Reviewed-by: Chen-Yu Tsai +Link: https://lore.kernel.org/r/20210924080632.28410-5-zhiyong.tao@mediatek.com +Signed-off-by: Linus Walleij +--- + .../pinctrl/mediatek/pinctrl-mtk-common-v2.c | 231 +++++++++++++++--- + .../pinctrl/mediatek/pinctrl-mtk-common-v2.h | 46 ++++ + drivers/pinctrl/mediatek/pinctrl-paris.c | 60 +++-- + 3 files changed, 289 insertions(+), 48 deletions(-) + +--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c +@@ -665,6 +665,181 @@ out: + return err; + } + ++static int mtk_hw_pin_rsel_lookup(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, ++ u32 pullup, u32 arg, u32 *rsel_val) ++{ ++ const struct mtk_pin_rsel *rsel; ++ int check; ++ bool found = false; ++ ++ rsel = hw->soc->pin_rsel; ++ ++ for (check = 0; check <= hw->soc->npin_rsel - 1; check++) { ++ if (desc->number >= rsel[check].s_pin && ++ desc->number <= rsel[check].e_pin) { ++ if (pullup) { ++ if (rsel[check].up_rsel == arg) { ++ found = true; ++ *rsel_val = rsel[check].rsel_index; ++ break; ++ } ++ } else { ++ if (rsel[check].down_rsel == arg) { ++ found = true; ++ *rsel_val = rsel[check].rsel_index; ++ break; ++ } ++ } ++ } ++ } ++ ++ if (!found) { ++ dev_err(hw->dev, "Not support rsel value %d Ohm for pin = %d (%s)\n", ++ arg, desc->number, desc->name); ++ return -ENOTSUPP; ++ } ++ ++ return 0; ++} ++ ++static int mtk_pinconf_bias_set_rsel(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, ++ u32 pullup, u32 arg) ++{ ++ int err, rsel_val; ++ ++ if (hw->rsel_si_unit) { ++ /* find pin rsel_index from pin_rsel array*/ ++ err = mtk_hw_pin_rsel_lookup(hw, desc, pullup, arg, &rsel_val); ++ if (err) ++ goto out; ++ } else { ++ if (arg < MTK_PULL_SET_RSEL_000 || ++ arg > MTK_PULL_SET_RSEL_111) { ++ err = -EINVAL; ++ goto out; ++ } ++ ++ rsel_val = arg - MTK_PULL_SET_RSEL_000; ++ } ++ ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_RSEL, rsel_val); ++ if (err) ++ goto out; ++ ++ err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, MTK_ENABLE); ++ ++out: ++ return err; ++} ++ ++int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, ++ u32 pullup, u32 arg) ++{ ++ int err = -ENOTSUPP; ++ u32 try_all_type; ++ ++ if (hw->soc->pull_type) ++ try_all_type = hw->soc->pull_type[desc->number]; ++ else ++ try_all_type = MTK_PULL_TYPE_MASK; ++ ++ if (try_all_type & MTK_PULL_RSEL_TYPE) { ++ err = mtk_pinconf_bias_set_rsel(hw, desc, pullup, arg); ++ if (!err) ++ return err; ++ } ++ ++ if (try_all_type & MTK_PULL_PU_PD_TYPE) { ++ err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg); ++ if (!err) ++ return err; ++ } ++ ++ if (try_all_type & MTK_PULL_PULLSEL_TYPE) { ++ err = mtk_pinconf_bias_set_pullsel_pullen(hw, desc, ++ pullup, arg); ++ if (!err) ++ return err; ++ } ++ ++ if (try_all_type & MTK_PULL_PUPD_R1R0_TYPE) ++ err = mtk_pinconf_bias_set_pupd_r1_r0(hw, desc, pullup, arg); ++ ++ if (err) ++ dev_err(hw->dev, "Invalid pull argument\n"); ++ ++ return err; ++} ++EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_combo); ++ ++static int mtk_rsel_get_si_unit(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, ++ u32 pullup, u32 rsel_val, u32 *si_unit) ++{ ++ const struct mtk_pin_rsel *rsel; ++ int check; ++ ++ rsel = hw->soc->pin_rsel; ++ ++ for (check = 0; check <= hw->soc->npin_rsel - 1; check++) { ++ if (desc->number >= rsel[check].s_pin && ++ desc->number <= rsel[check].e_pin) { ++ if (rsel_val == rsel[check].rsel_index) { ++ if (pullup) ++ *si_unit = rsel[check].up_rsel; ++ else ++ *si_unit = rsel[check].down_rsel; ++ break; ++ } ++ } ++ } ++ ++ return 0; ++} ++ ++static int mtk_pinconf_bias_get_rsel(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, ++ u32 *pullup, u32 *enable) ++{ ++ int pu, pd, rsel, err; ++ ++ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_RSEL, &rsel); ++ if (err) ++ goto out; ++ ++ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &pu); ++ if (err) ++ goto out; ++ ++ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd); ++ ++ if (pu == 0 && pd == 0) { ++ *pullup = 0; ++ *enable = MTK_DISABLE; ++ } else if (pu == 1 && pd == 0) { ++ *pullup = 1; ++ if (hw->rsel_si_unit) ++ mtk_rsel_get_si_unit(hw, desc, *pullup, rsel, enable); ++ else ++ *enable = rsel + MTK_PULL_SET_RSEL_000; ++ } else if (pu == 0 && pd == 1) { ++ *pullup = 0; ++ if (hw->rsel_si_unit) ++ mtk_rsel_get_si_unit(hw, desc, *pullup, rsel, enable); ++ else ++ *enable = rsel + MTK_PULL_SET_RSEL_000; ++ } else { ++ err = -EINVAL; ++ goto out; ++ } ++ ++out: ++ return err; ++} ++ + static int mtk_pinconf_bias_get_pu_pd(struct mtk_pinctrl *hw, + const struct mtk_pin_desc *desc, + u32 *pullup, u32 *enable) +@@ -746,44 +921,40 @@ out: + return err; + } + +-int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw, +- const struct mtk_pin_desc *desc, +- u32 pullup, u32 arg) +-{ +- int err; +- +- err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg); +- if (!err) +- goto out; +- +- err = mtk_pinconf_bias_set_pullsel_pullen(hw, desc, pullup, arg); +- if (!err) +- goto out; +- +- err = mtk_pinconf_bias_set_pupd_r1_r0(hw, desc, pullup, arg); +- +-out: +- return err; +-} +-EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_combo); +- + int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw, + const struct mtk_pin_desc *desc, + u32 *pullup, u32 *enable) + { +- int err; ++ int err = -ENOTSUPP; ++ u32 try_all_type; + +- err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable); +- if (!err) +- goto out; ++ if (hw->soc->pull_type) ++ try_all_type = hw->soc->pull_type[desc->number]; ++ else ++ try_all_type = MTK_PULL_TYPE_MASK; + +- err = mtk_pinconf_bias_get_pullsel_pullen(hw, desc, pullup, enable); +- if (!err) +- goto out; ++ if (try_all_type & MTK_PULL_RSEL_TYPE) { ++ err = mtk_pinconf_bias_get_rsel(hw, desc, pullup, enable); ++ if (!err) ++ return err; ++ } ++ ++ if (try_all_type & MTK_PULL_PU_PD_TYPE) { ++ err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable); ++ if (!err) ++ return err; ++ } ++ ++ if (try_all_type & MTK_PULL_PULLSEL_TYPE) { ++ err = mtk_pinconf_bias_get_pullsel_pullen(hw, desc, ++ pullup, enable); ++ if (!err) ++ return err; ++ } + +- err = mtk_pinconf_bias_get_pupd_r1_r0(hw, desc, pullup, enable); ++ if (try_all_type & MTK_PULL_PUPD_R1R0_TYPE) ++ err = mtk_pinconf_bias_get_pupd_r1_r0(hw, desc, pullup, enable); + +-out: + return err; + } + EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_combo); +--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h ++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h +@@ -17,6 +17,22 @@ + #define MTK_ENABLE 1 + #define MTK_PULLDOWN 0 + #define MTK_PULLUP 1 ++#define MTK_PULL_PU_PD_TYPE BIT(0) ++#define MTK_PULL_PULLSEL_TYPE BIT(1) ++#define MTK_PULL_PUPD_R1R0_TYPE BIT(2) ++/* MTK_PULL_RSEL_TYPE can select resistance and can be ++ * turned on/off itself. But it can't be selected pull up/down ++ */ ++#define MTK_PULL_RSEL_TYPE BIT(3) ++/* MTK_PULL_PU_PD_RSEL_TYPE is a type which is controlled by ++ * MTK_PULL_PU_PD_TYPE and MTK_PULL_RSEL_TYPE. ++ */ ++#define MTK_PULL_PU_PD_RSEL_TYPE (MTK_PULL_PU_PD_TYPE \ ++ | MTK_PULL_RSEL_TYPE) ++#define MTK_PULL_TYPE_MASK (MTK_PULL_PU_PD_TYPE |\ ++ MTK_PULL_PULLSEL_TYPE |\ ++ MTK_PULL_PUPD_R1R0_TYPE |\ ++ MTK_PULL_RSEL_TYPE) + + #define EINT_NA U16_MAX + #define NO_EINT_SUPPORT EINT_NA +@@ -42,6 +58,14 @@ + PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, 1) + ++#define PIN_RSEL(_s_pin, _e_pin, _rsel_index, _up_resl, _down_rsel) { \ ++ .s_pin = _s_pin, \ ++ .e_pin = _e_pin, \ ++ .rsel_index = _rsel_index, \ ++ .up_rsel = _up_resl, \ ++ .down_rsel = _down_rsel, \ ++ } ++ + /* List these attributes which could be modified for the pin */ + enum { + PINCTRL_PIN_REG_MODE, +@@ -67,6 +91,7 @@ enum { + PINCTRL_PIN_REG_DRV_E0, + PINCTRL_PIN_REG_DRV_E1, + PINCTRL_PIN_REG_DRV_ADV, ++ PINCTRL_PIN_REG_RSEL, + PINCTRL_PIN_REG_MAX, + }; + +@@ -129,6 +154,22 @@ struct mtk_pin_field_calc { + u8 fixed; + }; + ++/** ++ * struct mtk_pin_rsel - the structure that provides bias resistance selection. ++ * @s_pin: the start pin within the rsel range ++ * @e_pin: the end pin within the rsel range ++ * @rsel_index: the rsel bias resistance index ++ * @up_rsel: the pullup rsel bias resistance value ++ * @down_rsel: the pulldown rsel bias resistance value ++ */ ++struct mtk_pin_rsel { ++ u16 s_pin; ++ u16 e_pin; ++ u16 rsel_index; ++ u32 up_rsel; ++ u32 down_rsel; ++}; ++ + /* struct mtk_pin_reg_calc - the structure that holds all ranges used to + * determine which register the pin would make use of + * for certain pin attribute. +@@ -206,6 +247,9 @@ struct mtk_pin_soc { + bool ies_present; + const char * const *base_names; + unsigned int nbase_names; ++ const unsigned int *pull_type; ++ const struct mtk_pin_rsel *pin_rsel; ++ unsigned int npin_rsel; + + /* Specific pinconfig operations */ + int (*bias_disable_set)(struct mtk_pinctrl *hw, +@@ -254,6 +298,8 @@ struct mtk_pinctrl { + const char **grp_names; + /* lock pin's register resource to avoid multiple threads issue*/ + spinlock_t lock; ++ /* identify rsel setting by si unit or rsel define in dts node */ ++ bool rsel_si_unit; + }; + + void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set); +--- a/drivers/pinctrl/mediatek/pinctrl-paris.c ++++ b/drivers/pinctrl/mediatek/pinctrl-paris.c +@@ -574,8 +574,9 @@ static int mtk_hw_get_value_wrap(struct + ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw, + unsigned int gpio, char *buf, unsigned int buf_len) + { +- int pinmux, pullup = 0, pullen = 0, len = 0, r1 = -1, r0 = -1; ++ int pinmux, pullup = 0, pullen = 0, len = 0, r1 = -1, r0 = -1, rsel = -1; + const struct mtk_pin_desc *desc; ++ u32 try_all_type; + + if (gpio >= hw->soc->npins) + return -EINVAL; +@@ -589,24 +590,39 @@ ssize_t mtk_pctrl_show_one_pin(struct mt + pinmux -= hw->soc->nfuncs; + + mtk_pinconf_bias_get_combo(hw, desc, &pullup, &pullen); +- if (pullen == MTK_PUPD_SET_R1R0_00) { +- pullen = 0; +- r1 = 0; +- r0 = 0; +- } else if (pullen == MTK_PUPD_SET_R1R0_01) { +- pullen = 1; +- r1 = 0; +- r0 = 1; +- } else if (pullen == MTK_PUPD_SET_R1R0_10) { +- pullen = 1; +- r1 = 1; +- r0 = 0; +- } else if (pullen == MTK_PUPD_SET_R1R0_11) { ++ ++ if (hw->soc->pull_type) ++ try_all_type = hw->soc->pull_type[desc->number]; ++ ++ if (hw->rsel_si_unit && (try_all_type & MTK_PULL_RSEL_TYPE)) { ++ rsel = pullen; + pullen = 1; +- r1 = 1; +- r0 = 1; +- } else if (pullen != MTK_DISABLE && pullen != MTK_ENABLE) { +- pullen = 0; ++ } else { ++ /* Case for: R1R0 */ ++ if (pullen == MTK_PUPD_SET_R1R0_00) { ++ pullen = 0; ++ r1 = 0; ++ r0 = 0; ++ } else if (pullen == MTK_PUPD_SET_R1R0_01) { ++ pullen = 1; ++ r1 = 0; ++ r0 = 1; ++ } else if (pullen == MTK_PUPD_SET_R1R0_10) { ++ pullen = 1; ++ r1 = 1; ++ r0 = 0; ++ } else if (pullen == MTK_PUPD_SET_R1R0_11) { ++ pullen = 1; ++ r1 = 1; ++ r0 = 1; ++ } ++ ++ /* Case for: RSEL */ ++ if (pullen >= MTK_PULL_SET_RSEL_000 && ++ pullen <= MTK_PULL_SET_RSEL_111) { ++ rsel = pullen - MTK_PULL_SET_RSEL_000; ++ pullen = 1; ++ } + } + len += scnprintf(buf + len, buf_len - len, + "%03d: %1d%1d%1d%1d%02d%1d%1d%1d%1d", +@@ -624,6 +640,8 @@ ssize_t mtk_pctrl_show_one_pin(struct mt + if (r1 != -1) { + len += scnprintf(buf + len, buf_len - len, " (%1d %1d)\n", + r1, r0); ++ } else if (rsel != -1) { ++ len += scnprintf(buf + len, buf_len - len, " (%1d)\n", rsel); + } else { + len += scnprintf(buf + len, buf_len - len, "\n"); + } +@@ -966,6 +984,12 @@ int mtk_paris_pinctrl_probe(struct platf + + hw->nbase = hw->soc->nbase_names; + ++ if (of_find_property(hw->dev->of_node, ++ "mediatek,rsel_resistance_in_si_unit", NULL)) ++ hw->rsel_si_unit = true; ++ else ++ hw->rsel_si_unit = false; ++ + spin_lock_init(&hw->lock); + + err = mtk_pctrl_build_state(pdev); diff --git a/target/linux/mediatek/patches-6.1/823-v5.17-pinctrl-mediatek-add-a-check-for-error-in-mtk_pincon.patch b/target/linux/mediatek/patches-6.1/823-v5.17-pinctrl-mediatek-add-a-check-for-error-in-mtk_pincon.patch new file mode 100644 index 00000000000..6752b4093b4 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/823-v5.17-pinctrl-mediatek-add-a-check-for-error-in-mtk_pincon.patch @@ -0,0 +1,31 @@ +From 9f9d17c228c89e38ed612500126daf626270be9a Mon Sep 17 00:00:00 2001 +From: Dan Carpenter +Date: Sat, 27 Nov 2021 17:08:36 +0300 +Subject: [PATCH] pinctrl: mediatek: add a check for error in + mtk_pinconf_bias_get_rsel() + +All the other mtk_hw_get_value() calls have a check for "if (err)" so +we can add one here as well. This silences a Smatch warning: + + drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c:819 mtk_pinconf_bias_get_rsel() + error: uninitialized symbol 'pd'. + +Fixes: fb34a9ae383a ("pinctrl: mediatek: support rsel feature") +Signed-off-by: Dan Carpenter +Link: https://lore.kernel.org/r/20211127140836.GB24002@kili +Signed-off-by: Linus Walleij +--- + drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c +@@ -815,6 +815,8 @@ static int mtk_pinconf_bias_get_rsel(str + goto out; + + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd); ++ if (err) ++ goto out; + + if (pu == 0 && pd == 0) { + *pullup = 0; diff --git a/target/linux/mediatek/patches-6.1/824-v6.1-pinctrl-mediatek-Fix-EINT-pins-input-debounce-time-c.patch b/target/linux/mediatek/patches-6.1/824-v6.1-pinctrl-mediatek-Fix-EINT-pins-input-debounce-time-c.patch new file mode 100644 index 00000000000..47a29fbdba4 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/824-v6.1-pinctrl-mediatek-Fix-EINT-pins-input-debounce-time-c.patch @@ -0,0 +1,297 @@ +From e1ff91f9d2303cd4e706cc908bfca21cd17b9927 Mon Sep 17 00:00:00 2001 +From: AngeloGioacchino Del Regno +Date: Fri, 11 Nov 2022 10:41:06 +0100 +Subject: [PATCH] pinctrl: mediatek: Fix EINT pins input debounce time + configuration + +The External Interrupt Controller (EINTC) on all of the supported +MediaTek SoCs does support input debouncing, but not all of them +index the debounce time values (DBNC_SETTING registers) the same way. + +Before this change, in some cases, as an example, requesting a debounce +time of 16 milliseconds would mistakenly set the relative DBNC_SETTING +register to 0x2, resulting in a way shorter debounce time of 500uS. + +To fix the aforementioned issue, define three different debounce_time +arrays, reflecting the correct register index for each value and for +each register index variant, and make sure that each SoC pinctrl +driver uses the right one. + +Signed-off-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20221111094106.18486-1-angelogioacchino.delregno@collabora.com +Signed-off-by: Linus Walleij +--- + drivers/pinctrl/mediatek/mtk-eint.c | 31 +++++++++++++++++++---- + drivers/pinctrl/mediatek/mtk-eint.h | 6 +++++ + drivers/pinctrl/mediatek/pinctrl-mt2701.c | 1 + + drivers/pinctrl/mediatek/pinctrl-mt2712.c | 1 + + drivers/pinctrl/mediatek/pinctrl-mt6765.c | 1 + + drivers/pinctrl/mediatek/pinctrl-mt6779.c | 1 + + drivers/pinctrl/mediatek/pinctrl-mt7622.c | 1 + + drivers/pinctrl/mediatek/pinctrl-mt7623.c | 1 + + drivers/pinctrl/mediatek/pinctrl-mt7629.c | 1 + + drivers/pinctrl/mediatek/pinctrl-mt8127.c | 1 + + drivers/pinctrl/mediatek/pinctrl-mt8135.c | 1 + + drivers/pinctrl/mediatek/pinctrl-mt8167.c | 1 + + drivers/pinctrl/mediatek/pinctrl-mt8173.c | 1 + + drivers/pinctrl/mediatek/pinctrl-mt8183.c | 1 + + drivers/pinctrl/mediatek/pinctrl-mt8192.c | 1 + + drivers/pinctrl/mediatek/pinctrl-mt8195.c | 1 + + drivers/pinctrl/mediatek/pinctrl-mt8365.c | 1 + + drivers/pinctrl/mediatek/pinctrl-mt8516.c | 1 + + 22 files changed, 53 insertions(+), 5 deletions(-) + +--- a/drivers/pinctrl/mediatek/mtk-eint.c ++++ b/drivers/pinctrl/mediatek/mtk-eint.c +@@ -24,6 +24,7 @@ + #define MTK_EINT_EDGE_SENSITIVE 0 + #define MTK_EINT_LEVEL_SENSITIVE 1 + #define MTK_EINT_DBNC_SET_DBNC_BITS 4 ++#define MTK_EINT_DBNC_MAX 16 + #define MTK_EINT_DBNC_RST_BIT (0x1 << 1) + #define MTK_EINT_DBNC_SET_EN (0x1 << 0) + +@@ -48,6 +49,18 @@ static const struct mtk_eint_regs mtk_ge + .dbnc_clr = 0x700, + }; + ++const unsigned int debounce_time_mt2701[] = { ++ 500, 1000, 16000, 32000, 64000, 128000, 256000, 0 ++}; ++ ++const unsigned int debounce_time_mt6765[] = { ++ 125, 250, 500, 1000, 16000, 32000, 64000, 128000, 256000, 512000, 0 ++}; ++ ++const unsigned int debounce_time_mt6795[] = { ++ 500, 1000, 16000, 32000, 64000, 128000, 256000, 512000, 0 ++}; ++ + static void __iomem *mtk_eint_get_offset(struct mtk_eint *eint, + unsigned int eint_num, + unsigned int offset) +@@ -407,10 +420,11 @@ int mtk_eint_set_debounce(struct mtk_ein + int virq, eint_offset; + unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask, + dbnc; +- static const unsigned int debounce_time[] = {500, 1000, 16000, 32000, +- 64000, 128000, 256000}; + struct irq_data *d; + ++ if (!eint->hw->db_time) ++ return -EOPNOTSUPP; ++ + virq = irq_find_mapping(eint->domain, eint_num); + eint_offset = (eint_num % 4) * 8; + d = irq_get_irq_data(virq); +@@ -421,9 +435,9 @@ int mtk_eint_set_debounce(struct mtk_ein + if (!mtk_eint_can_en_debounce(eint, eint_num)) + return -EINVAL; + +- dbnc = ARRAY_SIZE(debounce_time); +- for (i = 0; i < ARRAY_SIZE(debounce_time); i++) { +- if (debounce <= debounce_time[i]) { ++ dbnc = eint->num_db_time; ++ for (i = 0; i < eint->num_db_time; i++) { ++ if (debounce <= eint->hw->db_time[i]) { + dbnc = i; + break; + } +@@ -497,6 +511,13 @@ int mtk_eint_do_init(struct mtk_eint *ei + if (!eint->domain) + return -ENOMEM; + ++ if (eint->hw->db_time) { ++ for (i = 0; i < MTK_EINT_DBNC_MAX; i++) ++ if (eint->hw->db_time[i] == 0) ++ break; ++ eint->num_db_time = i; ++ } ++ + mtk_eint_hw_init(eint); + for (i = 0; i < eint->hw->ap_num; i++) { + int virq = irq_create_mapping(eint->domain, i); +--- a/drivers/pinctrl/mediatek/mtk-eint.h ++++ b/drivers/pinctrl/mediatek/mtk-eint.h +@@ -37,8 +37,13 @@ struct mtk_eint_hw { + u8 ports; + unsigned int ap_num; + unsigned int db_cnt; ++ const unsigned int *db_time; + }; + ++extern const unsigned int debounce_time_mt2701[]; ++extern const unsigned int debounce_time_mt6765[]; ++extern const unsigned int debounce_time_mt6795[]; ++ + struct mtk_eint; + + struct mtk_eint_xt { +@@ -62,6 +67,7 @@ struct mtk_eint { + /* Used to fit into various EINT device */ + const struct mtk_eint_hw *hw; + const struct mtk_eint_regs *regs; ++ u16 num_db_time; + + /* Used to fit into various pinctrl device */ + void *pctl; +--- a/drivers/pinctrl/mediatek/pinctrl-mt2701.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c +@@ -531,6 +531,7 @@ static const struct mtk_pinctrl_devdata + .ports = 6, + .ap_num = 169, + .db_cnt = 16, ++ .db_time = debounce_time_mt2701, + }, + }; + +--- a/drivers/pinctrl/mediatek/pinctrl-mt2712.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt2712.c +@@ -584,6 +584,7 @@ static const struct mtk_pinctrl_devdata + .ports = 8, + .ap_num = 229, + .db_cnt = 40, ++ .db_time = debounce_time_mt2701, + }, + }; + +--- a/drivers/pinctrl/mediatek/pinctrl-mt6765.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt6765.c +@@ -1062,6 +1062,7 @@ static const struct mtk_eint_hw mt6765_e + .ports = 6, + .ap_num = 160, + .db_cnt = 13, ++ .db_time = debounce_time_mt6765, + }; + + static const struct mtk_pin_soc mt6765_data = { +--- a/drivers/pinctrl/mediatek/pinctrl-mt6779.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt6779.c +@@ -737,6 +737,7 @@ static const struct mtk_eint_hw mt6779_e + .ports = 6, + .ap_num = 195, + .db_cnt = 13, ++ .db_time = debounce_time_mt2701, + }; + + static const struct mtk_pin_soc mt6779_data = { +--- a/drivers/pinctrl/mediatek/pinctrl-mt7622.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c +@@ -846,6 +846,7 @@ static const struct mtk_eint_hw mt7622_e + .ports = 7, + .ap_num = ARRAY_SIZE(mt7622_pins), + .db_cnt = 20, ++ .db_time = debounce_time_mt6765, + }; + + static const struct mtk_pin_soc mt7622_data = { +--- a/drivers/pinctrl/mediatek/pinctrl-mt7623.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c +@@ -1369,6 +1369,7 @@ static const struct mtk_eint_hw mt7623_e + .ports = 6, + .ap_num = 169, + .db_cnt = 20, ++ .db_time = debounce_time_mt2701, + }; + + static struct mtk_pin_soc mt7623_data = { +--- a/drivers/pinctrl/mediatek/pinctrl-mt7629.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt7629.c +@@ -402,6 +402,7 @@ static const struct mtk_eint_hw mt7629_e + .ports = 7, + .ap_num = ARRAY_SIZE(mt7629_pins), + .db_cnt = 16, ++ .db_time = debounce_time_mt2701, + }; + + static struct mtk_pin_soc mt7629_data = { +--- a/drivers/pinctrl/mediatek/pinctrl-mt8127.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt8127.c +@@ -300,6 +300,7 @@ static const struct mtk_pinctrl_devdata + .ports = 6, + .ap_num = 143, + .db_cnt = 16, ++ .db_time = debounce_time_mt2701, + }, + }; + +--- a/drivers/pinctrl/mediatek/pinctrl-mt8135.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c +@@ -313,6 +313,7 @@ static const struct mtk_pinctrl_devdata + .ports = 6, + .ap_num = 192, + .db_cnt = 16, ++ .db_time = debounce_time_mt2701, + }, + }; + +--- a/drivers/pinctrl/mediatek/pinctrl-mt8167.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt8167.c +@@ -332,6 +332,7 @@ static const struct mtk_pinctrl_devdata + .ports = 6, + .ap_num = 169, + .db_cnt = 64, ++ .db_time = debounce_time_mt6795, + }, + }; + +--- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c +@@ -340,6 +340,7 @@ static const struct mtk_pinctrl_devdata + .ports = 6, + .ap_num = 224, + .db_cnt = 16, ++ .db_time = debounce_time_mt2701, + }, + }; + +--- a/drivers/pinctrl/mediatek/pinctrl-mt8183.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt8183.c +@@ -545,6 +545,7 @@ static const struct mtk_eint_hw mt8183_e + .ports = 6, + .ap_num = 212, + .db_cnt = 13, ++ .db_time = debounce_time_mt6765, + }; + + static const struct mtk_pin_soc mt8183_data = { +--- a/drivers/pinctrl/mediatek/pinctrl-mt8192.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt8192.c +@@ -1339,6 +1339,7 @@ static const struct mtk_eint_hw mt8192_e + .ports = 7, + .ap_num = 224, + .db_cnt = 32, ++ .db_time = debounce_time_mt6765, + }; + + static const struct mtk_pin_reg_calc mt8192_reg_cals[PINCTRL_PIN_REG_MAX] = { +--- a/drivers/pinctrl/mediatek/pinctrl-mt8195.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt8195.c +@@ -805,6 +805,7 @@ static const struct mtk_eint_hw mt8195_e + .ports = 7, + .ap_num = 225, + .db_cnt = 32, ++ .db_time = debounce_time_mt6765, + }; + + static const struct mtk_pin_soc mt8195_data = { +--- a/drivers/pinctrl/mediatek/pinctrl-mt8365.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt8365.c +@@ -466,6 +466,7 @@ static const struct mtk_pinctrl_devdata + .ports = 5, + .ap_num = 160, + .db_cnt = 160, ++ .db_time = debounce_time_mt6765, + }, + }; + +--- a/drivers/pinctrl/mediatek/pinctrl-mt8516.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c +@@ -332,6 +332,7 @@ static const struct mtk_pinctrl_devdata + .ports = 6, + .ap_num = 169, + .db_cnt = 64, ++ .db_time = debounce_time_mt6795, + }, + }; + diff --git a/target/linux/mediatek/patches-6.1/825-v6.1-pinctrl-mediatek-Export-debounce-time-tables.patch b/target/linux/mediatek/patches-6.1/825-v6.1-pinctrl-mediatek-Export-debounce-time-tables.patch new file mode 100644 index 00000000000..92f4e842e8a --- /dev/null +++ b/target/linux/mediatek/patches-6.1/825-v6.1-pinctrl-mediatek-Export-debounce-time-tables.patch @@ -0,0 +1,37 @@ +From 2e35b25dd8e666b8619355fc3defb1b246a5dc02 Mon Sep 17 00:00:00 2001 +From: Linus Walleij +Date: Tue, 15 Nov 2022 09:11:07 +0100 +Subject: [PATCH] pinctrl: mediatek: Export debounce time tables + +The kernel test robot complains that in certain combinations +when building the Mediatek drivers as modules we lack some +debounce table symbols, so export them. + +Reported-by: kernel test robot +Fixes: e1ff91f9d230 ("pinctrl: mediatek: Fix EINT pins input debounce time configuration") +Cc: AngeloGioacchino Del Regno +Signed-off-by: Linus Walleij +--- + drivers/pinctrl/mediatek/mtk-eint.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/pinctrl/mediatek/mtk-eint.c ++++ b/drivers/pinctrl/mediatek/mtk-eint.c +@@ -52,14 +52,17 @@ static const struct mtk_eint_regs mtk_ge + const unsigned int debounce_time_mt2701[] = { + 500, 1000, 16000, 32000, 64000, 128000, 256000, 0 + }; ++EXPORT_SYMBOL_GPL(debounce_time_mt2701); + + const unsigned int debounce_time_mt6765[] = { + 125, 250, 500, 1000, 16000, 32000, 64000, 128000, 256000, 512000, 0 + }; ++EXPORT_SYMBOL_GPL(debounce_time_mt6765); + + const unsigned int debounce_time_mt6795[] = { + 500, 1000, 16000, 32000, 64000, 128000, 256000, 512000, 0 + }; ++EXPORT_SYMBOL_GPL(debounce_time_mt6795); + + static void __iomem *mtk_eint_get_offset(struct mtk_eint *eint, + unsigned int eint_num, diff --git a/target/linux/mediatek/patches-6.1/826-v6.2-pinctrl-mediatek-extend-pinctrl-moore-to-support-new.patch b/target/linux/mediatek/patches-6.1/826-v6.2-pinctrl-mediatek-extend-pinctrl-moore-to-support-new.patch new file mode 100644 index 00000000000..f130fdbc566 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/826-v6.2-pinctrl-mediatek-extend-pinctrl-moore-to-support-new.patch @@ -0,0 +1,129 @@ +From fae82621ac33e2a4a96220c56e90d1ec6237d394 Mon Sep 17 00:00:00 2001 +From: Sam Shih +Date: Sun, 6 Nov 2022 09:01:12 +0100 +Subject: [PATCH] pinctrl: mediatek: extend pinctrl-moore to support new bias + functions + +Commit fb34a9ae383a ("pinctrl: mediatek: support rsel feature") +introduced SoC specify 'pull_type' attribute to mtk_pinconf_bias_set_combo +and mtk_pinconf_bias_get_combo, and make the functions able to support +almost all Mediatek SoCs that use pinctrl-mtk-common-v2.c. + +This patch enables pinctrl_moore to support these functions. + +Signed-off-by: Sam Shih +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20221106080114.7426-6-linux@fw-web.de +Signed-off-by: Linus Walleij +--- + drivers/pinctrl/mediatek/pinctrl-moore.c | 49 ++++++++++++++++++++---- + 1 file changed, 42 insertions(+), 7 deletions(-) + +--- a/drivers/pinctrl/mediatek/pinctrl-moore.c ++++ b/drivers/pinctrl/mediatek/pinctrl-moore.c +@@ -8,6 +8,7 @@ + * + */ + ++#include + #include + #include "pinctrl-moore.h" + +@@ -105,7 +106,7 @@ static int mtk_pinconf_get(struct pinctr + { + struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); + u32 param = pinconf_to_config_param(*config); +- int val, val2, err, reg, ret = 1; ++ int val, val2, err, pullup, reg, ret = 1; + const struct mtk_pin_desc *desc; + + desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; +@@ -114,7 +115,13 @@ static int mtk_pinconf_get(struct pinctr + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: +- if (hw->soc->bias_disable_get) { ++ if (hw->soc->bias_get_combo) { ++ err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret); ++ if (err) ++ return err; ++ if (ret != MTK_PUPD_SET_R1R0_00 && ret != MTK_DISABLE) ++ return -EINVAL; ++ } else if (hw->soc->bias_disable_get) { + err = hw->soc->bias_disable_get(hw, desc, &ret); + if (err) + return err; +@@ -123,7 +130,15 @@ static int mtk_pinconf_get(struct pinctr + } + break; + case PIN_CONFIG_BIAS_PULL_UP: +- if (hw->soc->bias_get) { ++ if (hw->soc->bias_get_combo) { ++ err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret); ++ if (err) ++ return err; ++ if (ret == MTK_PUPD_SET_R1R0_00 || ret == MTK_DISABLE) ++ return -EINVAL; ++ if (!pullup) ++ return -EINVAL; ++ } else if (hw->soc->bias_get) { + err = hw->soc->bias_get(hw, desc, 1, &ret); + if (err) + return err; +@@ -132,7 +147,15 @@ static int mtk_pinconf_get(struct pinctr + } + break; + case PIN_CONFIG_BIAS_PULL_DOWN: +- if (hw->soc->bias_get) { ++ if (hw->soc->bias_get_combo) { ++ err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret); ++ if (err) ++ return err; ++ if (ret == MTK_PUPD_SET_R1R0_00 || ret == MTK_DISABLE) ++ return -EINVAL; ++ if (pullup) ++ return -EINVAL; ++ } else if (hw->soc->bias_get) { + err = hw->soc->bias_get(hw, desc, 0, &ret); + if (err) + return err; +@@ -235,7 +258,11 @@ static int mtk_pinconf_set(struct pinctr + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: +- if (hw->soc->bias_disable_set) { ++ if (hw->soc->bias_set_combo) { ++ err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE); ++ if (err) ++ return err; ++ } else if (hw->soc->bias_disable_set) { + err = hw->soc->bias_disable_set(hw, desc); + if (err) + return err; +@@ -244,7 +271,11 @@ static int mtk_pinconf_set(struct pinctr + } + break; + case PIN_CONFIG_BIAS_PULL_UP: +- if (hw->soc->bias_set) { ++ if (hw->soc->bias_set_combo) { ++ err = hw->soc->bias_set_combo(hw, desc, 1, arg); ++ if (err) ++ return err; ++ } else if (hw->soc->bias_set) { + err = hw->soc->bias_set(hw, desc, 1); + if (err) + return err; +@@ -253,7 +284,11 @@ static int mtk_pinconf_set(struct pinctr + } + break; + case PIN_CONFIG_BIAS_PULL_DOWN: +- if (hw->soc->bias_set) { ++ if (hw->soc->bias_set_combo) { ++ err = hw->soc->bias_set_combo(hw, desc, 0, arg); ++ if (err) ++ return err; ++ } else if (hw->soc->bias_set) { + err = hw->soc->bias_set(hw, desc, 0); + if (err) + return err; diff --git a/target/linux/mediatek/patches-6.1/830-v5.18-regulator-Add-bindings-for-Richtek-RT5190A-PMIC.patch b/target/linux/mediatek/patches-6.1/830-v5.18-regulator-Add-bindings-for-Richtek-RT5190A-PMIC.patch new file mode 100644 index 00000000000..30891d34872 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/830-v5.18-regulator-Add-bindings-for-Richtek-RT5190A-PMIC.patch @@ -0,0 +1,180 @@ +From b77e70f6b8f2cc62fba847f3008a430a09ef275d Mon Sep 17 00:00:00 2001 +From: ChiYuan Huang +Date: Wed, 9 Mar 2022 16:01:42 +0800 +Subject: [PATCH 1/2] regulator: Add bindings for Richtek RT5190A PMIC + +Add bindings for Richtek RT5190A PMIC. + +Signed-off-by: ChiYuan Huang +Reviewed-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/1646812903-32496-2-git-send-email-u0084500@gmail.com +Signed-off-by: Mark Brown +--- + .../regulator/richtek,rt5190a-regulator.yaml | 141 ++++++++++++++++++ + .../regulator/richtek,rt5190a-regulator.h | 15 ++ + 2 files changed, 156 insertions(+) + create mode 100644 Documentation/devicetree/bindings/regulator/richtek,rt5190a-regulator.yaml + create mode 100644 include/dt-bindings/regulator/richtek,rt5190a-regulator.h + +--- /dev/null ++++ b/Documentation/devicetree/bindings/regulator/richtek,rt5190a-regulator.yaml +@@ -0,0 +1,141 @@ ++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/regulator/richtek,rt5190a-regulator.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Richtek RT5190A PMIC Regulator ++ ++maintainers: ++ - ChiYuan Huang ++ ++description: | ++ The RT5190A integrates 1 channel buck controller, 3 channels high efficiency ++ synchronous buck converters, 1 LDO, I2C control interface and peripherial ++ logical control. ++ ++ It also supports mute AC OFF depop sound and quick setting storage while ++ input power is removed. ++ ++properties: ++ compatible: ++ enum: ++ - richtek,rt5190a ++ ++ reg: ++ maxItems: 1 ++ ++ interrupts: ++ maxItems: 1 ++ ++ vin2-supply: ++ description: phandle to buck2 input voltage. ++ ++ vin3-supply: ++ description: phandle to buck3 input voltage. ++ ++ vin4-supply: ++ description: phandle to buck4 input voltage. ++ ++ vinldo-supply: ++ description: phandle to ldo input voltage ++ ++ richtek,mute-enable: ++ description: | ++ The mute function uses 'mutein', 'muteout', and 'vdet' pins as the control ++ signal. When enabled, The normal behavior is to bypass the 'mutein' signal ++ 'muteout'. But if the power source removal is detected from 'vdet', ++ whatever the 'mutein' signal is, it will pull down the 'muteout' to force ++ speakers mute. this function is commonly used to prevent the speaker pop ++ noise during AC power turned off in the modern TV system design. ++ type: boolean ++ ++ regulators: ++ type: object ++ ++ patternProperties: ++ "^buck[1-4]$|^ldo$": ++ type: object ++ $ref: regulator.yaml# ++ description: | ++ regulator description for buck1 and buck4. ++ ++ properties: ++ regulator-allowed-modes: ++ description: | ++ buck operating mode, only buck1/4 support mode operating. ++ 0: auto mode ++ 1: force pwm mode ++ items: ++ enum: [0, 1] ++ ++ richtek,latchup-enable: ++ type: boolean ++ description: | ++ If specified, undervolt protection mode changes from the default ++ hiccup to latchup. ++ ++ unevaluatedProperties: false ++ ++ additionalProperties: false ++ ++required: ++ - compatible ++ - reg ++ - regulators ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ ++ i2c { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ pmic@64 { ++ compatible = "richtek,rt5190a"; ++ reg = <0x64>; ++ interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>; ++ vin2-supply = <&rt5190_buck1>; ++ vin3-supply = <&rt5190_buck1>; ++ vin4-supply = <&rt5190_buck1>; ++ ++ regulators { ++ rt5190_buck1: buck1 { ++ regulator-name = "rt5190a-buck1"; ++ regulator-min-microvolt = <5090000>; ++ regulator-max-microvolt = <5090000>; ++ regulator-allowed-modes = ; ++ regulator-boot-on; ++ }; ++ buck2 { ++ regulator-name = "rt5190a-buck2"; ++ regulator-min-microvolt = <600000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-boot-on; ++ }; ++ buck3 { ++ regulator-name = "rt5190a-buck3"; ++ regulator-min-microvolt = <600000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-boot-on; ++ }; ++ buck4 { ++ regulator-name = "rt5190a-buck4"; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <850000>; ++ regulator-allowed-modes = ; ++ regulator-boot-on; ++ }; ++ ldo { ++ regulator-name = "rt5190a-ldo"; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-boot-on; ++ }; ++ }; ++ }; ++ }; +--- /dev/null ++++ b/include/dt-bindings/regulator/richtek,rt5190a-regulator.h +@@ -0,0 +1,15 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++ ++#ifndef __DT_BINDINGS_RICHTEK_RT5190A_REGULATOR_H__ ++#define __DT_BINDINGS_RICHTEK_RT5190A_REGULATOR_H__ ++ ++/* ++ * BUCK/LDO mode constants which may be used in devicetree properties ++ * (eg. regulator-allowed-modes). ++ * See the manufacturer's datasheet for more information on these modes. ++ */ ++ ++#define RT5190A_OPMODE_AUTO 0 ++#define RT5190A_OPMODE_FPWM 1 ++ ++#endif diff --git a/target/linux/mediatek/patches-6.1/831-v5.18-regulator-rt5190a-Add-support-for-Richtek-RT5190A-PM.patch b/target/linux/mediatek/patches-6.1/831-v5.18-regulator-rt5190a-Add-support-for-Richtek-RT5190A-PM.patch new file mode 100644 index 00000000000..0e0f099e505 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/831-v5.18-regulator-rt5190a-Add-support-for-Richtek-RT5190A-PM.patch @@ -0,0 +1,562 @@ +From 760423dfad53877b468490758fe7ea968ded9402 Mon Sep 17 00:00:00 2001 +From: ChiYuan Huang +Date: Wed, 9 Mar 2022 16:01:43 +0800 +Subject: [PATCH 2/2] regulator: rt5190a: Add support for Richtek RT5190A PMIC + +Add support for Richtek RT5190A PMIC. + +Signed-off-by: ChiYuan Huang +Link: https://lore.kernel.org/r/1646812903-32496-3-git-send-email-u0084500@gmail.com +Signed-off-by: Mark Brown +--- + drivers/regulator/Kconfig | 10 + + drivers/regulator/Makefile | 1 + + drivers/regulator/rt5190a-regulator.c | 513 ++++++++++++++++++++++++++ + 3 files changed, 524 insertions(+) + create mode 100644 drivers/regulator/rt5190a-regulator.c + +--- a/drivers/regulator/Kconfig ++++ b/drivers/regulator/Kconfig +@@ -1037,6 +1037,16 @@ config REGULATOR_RT5033 + RT5033 PMIC. The device supports multiple regulators like + current source, LDO and Buck. + ++config REGULATOR_RT5190A ++ tristate "Richtek RT5190A PMIC" ++ depends on I2C ++ select REGMAP_I2C ++ help ++ This adds support for voltage regulator in Richtek RT5190A PMIC. ++ It integratas 1 channel buck controller, 3 channels high efficiency ++ buck converters, 1 LDO, mute AC OFF depop function, with the general ++ I2C control interface. ++ + config REGULATOR_RT6160 + tristate "Richtek RT6160 BuckBoost voltage regulator" + depends on I2C +--- a/drivers/regulator/Makefile ++++ b/drivers/regulator/Makefile +@@ -125,6 +125,7 @@ obj-$(CONFIG_REGULATOR_ROHM) += rohm-reg + obj-$(CONFIG_REGULATOR_RT4801) += rt4801-regulator.o + obj-$(CONFIG_REGULATOR_RT4831) += rt4831-regulator.o + obj-$(CONFIG_REGULATOR_RT5033) += rt5033-regulator.o ++obj-$(CONFIG_REGULATOR_RT5190A) += rt5190a-regulator.o + obj-$(CONFIG_REGULATOR_RT6160) += rt6160-regulator.o + obj-$(CONFIG_REGULATOR_RT6245) += rt6245-regulator.o + obj-$(CONFIG_REGULATOR_RTMV20) += rtmv20-regulator.o +--- /dev/null ++++ b/drivers/regulator/rt5190a-regulator.c +@@ -0,0 +1,513 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define RT5190A_REG_MANUFACTURE 0x00 ++#define RT5190A_REG_BUCK2VSEL 0x04 ++#define RT5190A_REG_BUCK3VSEL 0x05 ++#define RT5190A_REG_DCDCCNTL 0x06 ++#define RT5190A_REG_ENABLE 0x07 ++#define RT5190A_REG_DISCHARGE 0x09 ++#define RT5190A_REG_PROTMODE 0x0A ++#define RT5190A_REG_MUTECNTL 0x0B ++#define RT5190A_REG_PGSTAT 0x0F ++#define RT5190A_REG_OVINT 0x10 ++#define RT5190A_REG_HOTDIEMASK 0x17 ++ ++#define RT5190A_VSEL_MASK GENMASK(6, 0) ++#define RT5190A_RID_BITMASK(rid) BIT(rid + 1) ++#define RT5190A_BUCK1_DISCHG_MASK GENMASK(1, 0) ++#define RT5190A_BUCK1_DISCHG_ONVAL 0x01 ++#define RT5190A_OVERVOLT_MASK GENMASK(7, 0) ++#define RT5190A_UNDERVOLT_MASK GENMASK(15, 8) ++#define RT5190A_CH234OT_MASK BIT(29) ++#define RT5190A_CHIPOT_MASK BIT(28) ++ ++#define RT5190A_BUCK23_MINUV 600000 ++#define RT5190A_BUCK23_MAXUV 1400000 ++#define RT5190A_BUCK23_STEPUV 10000 ++#define RT5190A_BUCK23_STEPNUM ((1400000 - 600000) / 10000 + 1) ++ ++enum { ++ RT5190A_IDX_BUCK1 = 0, ++ RT5190A_IDX_BUCK2, ++ RT5190A_IDX_BUCK3, ++ RT5190A_IDX_BUCK4, ++ RT5190A_IDX_LDO, ++ RT5190A_MAX_IDX ++}; ++ ++struct rt5190a_priv { ++ struct device *dev; ++ struct regmap *regmap; ++ struct regulator_desc rdesc[RT5190A_MAX_IDX]; ++ struct regulator_dev *rdev[RT5190A_MAX_IDX]; ++}; ++ ++static int rt5190a_get_error_flags(struct regulator_dev *rdev, ++ unsigned int *flags) ++{ ++ struct regmap *regmap = rdev_get_regmap(rdev); ++ int rid = rdev_get_id(rdev); ++ unsigned int pgood_stat; ++ int ret; ++ ++ ret = regmap_read(regmap, RT5190A_REG_PGSTAT, &pgood_stat); ++ if (ret) ++ return ret; ++ ++ if (!(pgood_stat & RT5190A_RID_BITMASK(rid))) ++ *flags = REGULATOR_ERROR_FAIL; ++ else ++ *flags = 0; ++ ++ return 0; ++} ++ ++static int rt5190a_fixed_buck_set_mode(struct regulator_dev *rdev, ++ unsigned int mode) ++{ ++ struct regmap *regmap = rdev_get_regmap(rdev); ++ int rid = rdev_get_id(rdev); ++ unsigned int mask = RT5190A_RID_BITMASK(rid), val; ++ ++ switch (mode) { ++ case REGULATOR_MODE_FAST: ++ val = mask; ++ break; ++ case REGULATOR_MODE_NORMAL: ++ val = 0; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return regmap_update_bits(regmap, RT5190A_REG_DCDCCNTL, mask, val); ++} ++ ++static unsigned int rt5190a_fixed_buck_get_mode(struct regulator_dev *rdev) ++{ ++ struct regmap *regmap = rdev_get_regmap(rdev); ++ int rid = rdev_get_id(rdev); ++ unsigned int val; ++ int ret; ++ ++ ret = regmap_read(regmap, RT5190A_REG_DCDCCNTL, &val); ++ if (ret) { ++ dev_err(&rdev->dev, "Failed to get mode [%d]\n", ret); ++ return ret; ++ } ++ ++ if (val & RT5190A_RID_BITMASK(rid)) ++ return REGULATOR_MODE_FAST; ++ ++ return REGULATOR_MODE_NORMAL; ++} ++ ++static const struct regulator_ops rt5190a_ranged_buck_ops = { ++ .enable = regulator_enable_regmap, ++ .disable = regulator_disable_regmap, ++ .is_enabled = regulator_is_enabled_regmap, ++ .set_voltage_sel = regulator_set_voltage_sel_regmap, ++ .get_voltage_sel = regulator_get_voltage_sel_regmap, ++ .list_voltage = regulator_list_voltage_linear, ++ .set_active_discharge = regulator_set_active_discharge_regmap, ++ .get_error_flags = rt5190a_get_error_flags, ++}; ++ ++static const struct regulator_ops rt5190a_fixed_buck_ops = { ++ .enable = regulator_enable_regmap, ++ .disable = regulator_disable_regmap, ++ .is_enabled = regulator_is_enabled_regmap, ++ .set_active_discharge = regulator_set_active_discharge_regmap, ++ .set_mode = rt5190a_fixed_buck_set_mode, ++ .get_mode = rt5190a_fixed_buck_get_mode, ++ .get_error_flags = rt5190a_get_error_flags, ++}; ++ ++static const struct regulator_ops rt5190a_fixed_ldo_ops = { ++ .enable = regulator_enable_regmap, ++ .disable = regulator_disable_regmap, ++ .is_enabled = regulator_is_enabled_regmap, ++ .set_active_discharge = regulator_set_active_discharge_regmap, ++ .get_error_flags = rt5190a_get_error_flags, ++}; ++ ++static irqreturn_t rt5190a_irq_handler(int irq, void *data) ++{ ++ struct rt5190a_priv *priv = data; ++ __le32 raws; ++ unsigned int events, fields; ++ static const struct { ++ unsigned int bitmask; ++ unsigned int report; ++ } event_tbl[] = { ++ { RT5190A_OVERVOLT_MASK, REGULATOR_ERROR_REGULATION_OUT }, ++ { RT5190A_UNDERVOLT_MASK, REGULATOR_ERROR_UNDER_VOLTAGE } ++ }; ++ int i, j, ret; ++ ++ ret = regmap_raw_read(priv->regmap, RT5190A_REG_OVINT, &raws, ++ sizeof(raws)); ++ if (ret) { ++ dev_err(priv->dev, "Failed to read events\n"); ++ return IRQ_NONE; ++ } ++ ++ events = le32_to_cpu(raws); ++ ++ ret = regmap_raw_write(priv->regmap, RT5190A_REG_OVINT, &raws, ++ sizeof(raws)); ++ if (ret) ++ dev_err(priv->dev, "Failed to write-clear events\n"); ++ ++ /* Handle OV,UV events */ ++ for (i = 0; i < ARRAY_SIZE(event_tbl); i++) { ++ fields = events & event_tbl[i].bitmask; ++ fields >>= ffs(event_tbl[i].bitmask) - 1; ++ ++ for (j = 0; j < RT5190A_MAX_IDX; j++) { ++ if (!(fields & RT5190A_RID_BITMASK(j))) ++ continue; ++ ++ regulator_notifier_call_chain(priv->rdev[j], ++ event_tbl[i].report, ++ NULL); ++ } ++ } ++ ++ /* Handle CH234 OT event */ ++ if (events & RT5190A_CH234OT_MASK) { ++ for (j = RT5190A_IDX_BUCK2; j < RT5190A_IDX_LDO; j++) { ++ regulator_notifier_call_chain(priv->rdev[j], ++ REGULATOR_ERROR_OVER_TEMP, ++ NULL); ++ } ++ } ++ ++ /* Warning if CHIP OT occur */ ++ if (events & RT5190A_CHIPOT_MASK) ++ dev_warn(priv->dev, "CHIP overheat\n"); ++ ++ return IRQ_HANDLED; ++} ++ ++static unsigned int rt5190a_of_map_mode(unsigned int mode) ++{ ++ switch (mode) { ++ case RT5190A_OPMODE_AUTO: ++ return REGULATOR_MODE_NORMAL; ++ case RT5190A_OPMODE_FPWM: ++ return REGULATOR_MODE_FAST; ++ default: ++ return REGULATOR_MODE_INVALID; ++ } ++} ++ ++static int rt5190a_of_parse_cb(struct rt5190a_priv *priv, int rid, ++ struct of_regulator_match *match) ++{ ++ struct regulator_desc *desc = priv->rdesc + rid; ++ struct regulator_init_data *init_data = match->init_data; ++ struct device_node *np = match->of_node; ++ bool latchup_enable; ++ unsigned int mask = RT5190A_RID_BITMASK(rid), val; ++ ++ switch (rid) { ++ case RT5190A_IDX_BUCK1: ++ case RT5190A_IDX_BUCK4: ++ case RT5190A_IDX_LDO: ++ init_data->constraints.apply_uV = 0; ++ ++ if (init_data->constraints.min_uV == ++ init_data->constraints.max_uV) ++ desc->fixed_uV = init_data->constraints.min_uV; ++ else { ++ dev_err(priv->dev, ++ "Variable voltage for fixed regulator\n"); ++ return -EINVAL; ++ } ++ break; ++ default: ++ break; ++ } ++ ++ latchup_enable = of_property_read_bool(np, "richtek,latchup-enable"); ++ ++ /* latchup: 0, default hiccup: 1 */ ++ val = !latchup_enable ? mask : 0; ++ ++ return regmap_update_bits(priv->regmap, RT5190A_REG_PROTMODE, mask, val); ++} ++ ++static void rt5190a_fillin_regulator_desc(struct regulator_desc *desc, int rid) ++{ ++ static const char * const regu_name[] = { "buck1", "buck2", ++ "buck3", "buck4", ++ "ldo" }; ++ static const char * const supply[] = { NULL, "vin2", "vin3", "vin4", ++ "vinldo" }; ++ ++ desc->name = regu_name[rid]; ++ desc->supply_name = supply[rid]; ++ desc->owner = THIS_MODULE; ++ desc->type = REGULATOR_VOLTAGE; ++ desc->id = rid; ++ desc->enable_reg = RT5190A_REG_ENABLE; ++ desc->enable_mask = RT5190A_RID_BITMASK(rid); ++ desc->active_discharge_reg = RT5190A_REG_DISCHARGE; ++ desc->active_discharge_mask = RT5190A_RID_BITMASK(rid); ++ desc->active_discharge_on = RT5190A_RID_BITMASK(rid); ++ ++ switch (rid) { ++ case RT5190A_IDX_BUCK1: ++ desc->active_discharge_mask = RT5190A_BUCK1_DISCHG_MASK; ++ desc->active_discharge_on = RT5190A_BUCK1_DISCHG_ONVAL; ++ desc->n_voltages = 1; ++ desc->ops = &rt5190a_fixed_buck_ops; ++ desc->of_map_mode = rt5190a_of_map_mode; ++ break; ++ case RT5190A_IDX_BUCK2: ++ desc->vsel_reg = RT5190A_REG_BUCK2VSEL; ++ desc->vsel_mask = RT5190A_VSEL_MASK; ++ desc->min_uV = RT5190A_BUCK23_MINUV; ++ desc->uV_step = RT5190A_BUCK23_STEPUV; ++ desc->n_voltages = RT5190A_BUCK23_STEPNUM; ++ desc->ops = &rt5190a_ranged_buck_ops; ++ break; ++ case RT5190A_IDX_BUCK3: ++ desc->vsel_reg = RT5190A_REG_BUCK3VSEL; ++ desc->vsel_mask = RT5190A_VSEL_MASK; ++ desc->min_uV = RT5190A_BUCK23_MINUV; ++ desc->uV_step = RT5190A_BUCK23_STEPUV; ++ desc->n_voltages = RT5190A_BUCK23_STEPNUM; ++ desc->ops = &rt5190a_ranged_buck_ops; ++ break; ++ case RT5190A_IDX_BUCK4: ++ desc->n_voltages = 1; ++ desc->ops = &rt5190a_fixed_buck_ops; ++ desc->of_map_mode = rt5190a_of_map_mode; ++ break; ++ case RT5190A_IDX_LDO: ++ desc->n_voltages = 1; ++ desc->ops = &rt5190a_fixed_ldo_ops; ++ break; ++ } ++} ++ ++static struct of_regulator_match rt5190a_regulator_match[] = { ++ { .name = "buck1", }, ++ { .name = "buck2", }, ++ { .name = "buck3", }, ++ { .name = "buck4", }, ++ { .name = "ldo", } ++}; ++ ++static int rt5190a_parse_regulator_dt_data(struct rt5190a_priv *priv) ++{ ++ struct device_node *regulator_np; ++ struct regulator_desc *reg_desc; ++ struct of_regulator_match *match; ++ int i, ret; ++ ++ for (i = 0; i < RT5190A_MAX_IDX; i++) { ++ reg_desc = priv->rdesc + i; ++ match = rt5190a_regulator_match + i; ++ ++ rt5190a_fillin_regulator_desc(reg_desc, i); ++ ++ match->desc = reg_desc; ++ } ++ ++ regulator_np = of_get_child_by_name(priv->dev->of_node, "regulators"); ++ if (!regulator_np) { ++ dev_err(priv->dev, "Could not find 'regulators' node\n"); ++ return -ENODEV; ++ } ++ ++ ret = of_regulator_match(priv->dev, regulator_np, ++ rt5190a_regulator_match, ++ ARRAY_SIZE(rt5190a_regulator_match)); ++ ++ of_node_put(regulator_np); ++ ++ if (ret < 0) { ++ dev_err(priv->dev, ++ "Error parsing regulator init data: %d\n", ret); ++ return ret; ++ } ++ ++ for (i = 0; i < RT5190A_MAX_IDX; i++) { ++ match = rt5190a_regulator_match + i; ++ ++ ret = rt5190a_of_parse_cb(priv, i, match); ++ if (ret) { ++ dev_err(priv->dev, "Failed in [%d] of_parse_cb\n", i); ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ ++static const struct reg_sequence rt5190a_init_patch[] = { ++ { 0x09, 0x3d, }, ++ { 0x0a, 0x3e, }, ++ { 0x0b, 0x01, }, ++ { 0x10, 0xff, }, ++ { 0x11, 0xff, }, ++ { 0x12, 0xff, }, ++ { 0x13, 0xff, }, ++ { 0x14, 0, }, ++ { 0x15, 0, }, ++ { 0x16, 0x3e, }, ++ { 0x17, 0, } ++}; ++ ++static int rt5190a_device_initialize(struct rt5190a_priv *priv) ++{ ++ bool mute_enable; ++ int ret; ++ ++ ret = regmap_register_patch(priv->regmap, rt5190a_init_patch, ++ ARRAY_SIZE(rt5190a_init_patch)); ++ if (ret) { ++ dev_err(priv->dev, "Failed to do register patch\n"); ++ return ret; ++ } ++ ++ mute_enable = device_property_read_bool(priv->dev, ++ "richtek,mute-enable"); ++ ++ if (mute_enable) { ++ ret = regmap_write(priv->regmap, RT5190A_REG_MUTECNTL, 0x00); ++ if (ret) { ++ dev_err(priv->dev, "Failed to enable mute function\n"); ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ ++static int rt5190a_device_check(struct rt5190a_priv *priv) ++{ ++ u16 devid; ++ int ret; ++ ++ ret = regmap_raw_read(priv->regmap, RT5190A_REG_MANUFACTURE, &devid, ++ sizeof(devid)); ++ if (ret) ++ return ret; ++ ++ if (devid) { ++ dev_err(priv->dev, "Incorrect device id 0x%04x\n", devid); ++ return -ENODEV; ++ } ++ ++ return 0; ++} ++ ++static const struct regmap_config rt5190a_regmap_config = { ++ .reg_bits = 8, ++ .val_bits = 8, ++ .max_register = RT5190A_REG_HOTDIEMASK, ++}; ++ ++static int rt5190a_probe(struct i2c_client *i2c) ++{ ++ struct rt5190a_priv *priv; ++ struct regulator_config cfg = {}; ++ int i, ret; ++ ++ priv = devm_kzalloc(&i2c->dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ priv->dev = &i2c->dev; ++ ++ priv->regmap = devm_regmap_init_i2c(i2c, &rt5190a_regmap_config); ++ if (IS_ERR(priv->regmap)) { ++ dev_err(&i2c->dev, "Failed to allocate regmap\n"); ++ return PTR_ERR(priv->regmap); ++ } ++ ++ ret = rt5190a_device_check(priv); ++ if (ret) { ++ dev_err(&i2c->dev, "Failed to check device %d\n", ret); ++ return ret; ++ } ++ ++ ret = rt5190a_device_initialize(priv); ++ if (ret) { ++ dev_err(&i2c->dev, "Failed to initialize the device\n"); ++ return ret; ++ } ++ ++ ret = rt5190a_parse_regulator_dt_data(priv); ++ if (ret) { ++ dev_err(&i2c->dev, "Failed to parse regulator dt\n"); ++ return ret; ++ } ++ ++ cfg.dev = &i2c->dev; ++ cfg.regmap = priv->regmap; ++ ++ for (i = 0; i < RT5190A_MAX_IDX; i++) { ++ struct regulator_desc *desc = priv->rdesc + i; ++ struct of_regulator_match *match = rt5190a_regulator_match + i; ++ ++ cfg.init_data = match->init_data; ++ cfg.of_node = match->of_node; ++ ++ priv->rdev[i] = devm_regulator_register(&i2c->dev, desc, &cfg); ++ if (IS_ERR(priv->rdev[i])) { ++ dev_err(&i2c->dev, "Failed to register regulator %s\n", ++ desc->name); ++ return PTR_ERR(priv->rdev[i]); ++ } ++ } ++ ++ if (i2c->irq) { ++ ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, ++ rt5190a_irq_handler, ++ IRQF_ONESHOT, ++ dev_name(&i2c->dev), priv); ++ if (ret) { ++ dev_err(&i2c->dev, "Failed to register interrupt\n"); ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ ++static const struct of_device_id __maybe_unused rt5190a_device_table[] = { ++ { .compatible = "richtek,rt5190a", }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, rt5190a_device_table); ++ ++static struct i2c_driver rt5190a_driver = { ++ .driver = { ++ .name = "rt5190a", ++ .of_match_table = rt5190a_device_table, ++ }, ++ .probe_new = rt5190a_probe, ++}; ++module_i2c_driver(rt5190a_driver); ++ ++MODULE_AUTHOR("ChiYuan Huang "); ++MODULE_DESCRIPTION("Richtek RT5190A Regulator Driver"); ++MODULE_LICENSE("GPL v2"); diff --git a/target/linux/mediatek/patches-6.1/840-v5.16-i2c-mediatek-Reset-the-handshake-signal-between-i2c-.patch b/target/linux/mediatek/patches-6.1/840-v5.16-i2c-mediatek-Reset-the-handshake-signal-between-i2c-.patch new file mode 100644 index 00000000000..8b011964098 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/840-v5.16-i2c-mediatek-Reset-the-handshake-signal-between-i2c-.patch @@ -0,0 +1,74 @@ +From 95e4dfbf33dc0a0843ba20db811f7ea271235e1e Mon Sep 17 00:00:00 2001 +From: Kewei Xu +Date: Sun, 10 Oct 2021 15:05:12 +0800 +Subject: [PATCH 01/16] i2c: mediatek: Reset the handshake signal between i2c + and dma + +Due to changes in the hardware design of the handshaking signal +between i2c and dma, it is necessary to reset the handshaking +signal before each transfer to ensure that the multi-msgs can +be transferred correctly. + +Signed-off-by: Kewei Xu +Reviewed-by: Qii Wang +Signed-off-by: Wolfram Sang +--- + drivers/i2c/busses/i2c-mt65xx.c | 26 ++++++++++++++++++++++++++ + 1 file changed, 26 insertions(+) + +--- a/drivers/i2c/busses/i2c-mt65xx.c ++++ b/drivers/i2c/busses/i2c-mt65xx.c +@@ -15,6 +15,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -49,6 +50,8 @@ + #define I2C_RD_TRANAC_VALUE 0x0001 + #define I2C_SCL_MIS_COMP_VALUE 0x0000 + #define I2C_CHN_CLR_FLAG 0x0000 ++#define I2C_RELIABILITY 0x0010 ++#define I2C_DMAACK_ENABLE 0x0008 + + #define I2C_DMA_CON_TX 0x0000 + #define I2C_DMA_CON_RX 0x0001 +@@ -851,6 +854,7 @@ static int mtk_i2c_do_transfer(struct mt + u16 restart_flag = 0; + u16 dma_sync = 0; + u32 reg_4g_mode; ++ u32 reg_dma_reset; + u8 *dma_rd_buf = NULL; + u8 *dma_wr_buf = NULL; + dma_addr_t rpaddr = 0; +@@ -864,6 +868,28 @@ static int mtk_i2c_do_transfer(struct mt + + reinit_completion(&i2c->msg_complete); + ++ if (i2c->dev_comp->apdma_sync && ++ i2c->op != I2C_MASTER_WRRD && num > 1) { ++ mtk_i2c_writew(i2c, 0x00, OFFSET_DEBUGCTRL); ++ writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_WARM_RST, ++ i2c->pdmabase + OFFSET_RST); ++ ++ ret = readw_poll_timeout(i2c->pdmabase + OFFSET_RST, ++ reg_dma_reset, ++ !(reg_dma_reset & I2C_DMA_WARM_RST), ++ 0, 100); ++ if (ret) { ++ dev_err(i2c->dev, "DMA warm reset timeout\n"); ++ return -ETIMEDOUT; ++ } ++ ++ writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); ++ mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST, OFFSET_SOFTRESET); ++ mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET); ++ mtk_i2c_writew(i2c, I2C_RELIABILITY | I2C_DMAACK_ENABLE, ++ OFFSET_DEBUGCTRL); ++ } ++ + control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) & + ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS); + if ((i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) || (left_num >= 1)) diff --git a/target/linux/mediatek/patches-6.1/841-v5.16-i2c-mediatek-Dump-i2c-dma-register-when-a-timeout-oc.patch b/target/linux/mediatek/patches-6.1/841-v5.16-i2c-mediatek-Dump-i2c-dma-register-when-a-timeout-oc.patch new file mode 100644 index 00000000000..a2d2521c772 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/841-v5.16-i2c-mediatek-Dump-i2c-dma-register-when-a-timeout-oc.patch @@ -0,0 +1,102 @@ +From 5b8e29e566e086ef9b5b9ea0d054370a295e1d05 Mon Sep 17 00:00:00 2001 +From: Kewei Xu +Date: Sun, 10 Oct 2021 15:05:13 +0800 +Subject: [PATCH 02/16] i2c: mediatek: Dump i2c/dma register when a timeout + occurs + +When a timeout error occurs in i2c transter, it is usually related +to the i2c/dma IP hardware configuration. Therefore, the purpose of +this patch is to dump the key register values of i2c/dma when a +timeout occurs in i2c for debugging. + +Signed-off-by: Kewei Xu +Reviewed-by: Qii Wang +Signed-off-by: Wolfram Sang +--- + drivers/i2c/busses/i2c-mt65xx.c | 54 +++++++++++++++++++++++++++++++++ + 1 file changed, 54 insertions(+) + +--- a/drivers/i2c/busses/i2c-mt65xx.c ++++ b/drivers/i2c/busses/i2c-mt65xx.c +@@ -130,6 +130,7 @@ enum I2C_REGS_OFFSET { + OFFSET_HS, + OFFSET_SOFTRESET, + OFFSET_DCM_EN, ++ OFFSET_MULTI_DMA, + OFFSET_PATH_DIR, + OFFSET_DEBUGSTAT, + OFFSET_DEBUGCTRL, +@@ -197,6 +198,7 @@ static const u16 mt_i2c_regs_v2[] = { + [OFFSET_TRANSFER_LEN_AUX] = 0x44, + [OFFSET_CLOCK_DIV] = 0x48, + [OFFSET_SOFTRESET] = 0x50, ++ [OFFSET_MULTI_DMA] = 0x8c, + [OFFSET_SCL_MIS_COMP_POINT] = 0x90, + [OFFSET_DEBUGSTAT] = 0xe4, + [OFFSET_DEBUGCTRL] = 0xe8, +@@ -845,6 +847,57 @@ static int mtk_i2c_set_speed(struct mtk_ + return 0; + } + ++static void i2c_dump_register(struct mtk_i2c *i2c) ++{ ++ dev_dbg(i2c->dev, "SLAVE_ADDR: 0x%x, INTR_MASK: 0x%x\n", ++ mtk_i2c_readw(i2c, OFFSET_SLAVE_ADDR), ++ mtk_i2c_readw(i2c, OFFSET_INTR_MASK)); ++ dev_dbg(i2c->dev, "INTR_STAT: 0x%x, CONTROL: 0x%x\n", ++ mtk_i2c_readw(i2c, OFFSET_INTR_STAT), ++ mtk_i2c_readw(i2c, OFFSET_CONTROL)); ++ dev_dbg(i2c->dev, "TRANSFER_LEN: 0x%x, TRANSAC_LEN: 0x%x\n", ++ mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN), ++ mtk_i2c_readw(i2c, OFFSET_TRANSAC_LEN)); ++ dev_dbg(i2c->dev, "DELAY_LEN: 0x%x, HTIMING: 0x%x\n", ++ mtk_i2c_readw(i2c, OFFSET_DELAY_LEN), ++ mtk_i2c_readw(i2c, OFFSET_TIMING)); ++ dev_dbg(i2c->dev, "START: 0x%x, EXT_CONF: 0x%x\n", ++ mtk_i2c_readw(i2c, OFFSET_START), ++ mtk_i2c_readw(i2c, OFFSET_EXT_CONF)); ++ dev_dbg(i2c->dev, "HS: 0x%x, IO_CONFIG: 0x%x\n", ++ mtk_i2c_readw(i2c, OFFSET_HS), ++ mtk_i2c_readw(i2c, OFFSET_IO_CONFIG)); ++ dev_dbg(i2c->dev, "DCM_EN: 0x%x, TRANSFER_LEN_AUX: 0x%x\n", ++ mtk_i2c_readw(i2c, OFFSET_DCM_EN), ++ mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN_AUX)); ++ dev_dbg(i2c->dev, "CLOCK_DIV: 0x%x, FIFO_STAT: 0x%x\n", ++ mtk_i2c_readw(i2c, OFFSET_CLOCK_DIV), ++ mtk_i2c_readw(i2c, OFFSET_FIFO_STAT)); ++ dev_dbg(i2c->dev, "DEBUGCTRL : 0x%x, DEBUGSTAT: 0x%x\n", ++ mtk_i2c_readw(i2c, OFFSET_DEBUGCTRL), ++ mtk_i2c_readw(i2c, OFFSET_DEBUGSTAT)); ++ if (i2c->dev_comp->regs == mt_i2c_regs_v2) { ++ dev_dbg(i2c->dev, "LTIMING: 0x%x, MULTI_DMA: 0x%x\n", ++ mtk_i2c_readw(i2c, OFFSET_LTIMING), ++ mtk_i2c_readw(i2c, OFFSET_MULTI_DMA)); ++ } ++ dev_dbg(i2c->dev, "\nDMA_INT_FLAG: 0x%x, DMA_INT_EN: 0x%x\n", ++ readl(i2c->pdmabase + OFFSET_INT_FLAG), ++ readl(i2c->pdmabase + OFFSET_INT_EN)); ++ dev_dbg(i2c->dev, "DMA_EN: 0x%x, DMA_CON: 0x%x\n", ++ readl(i2c->pdmabase + OFFSET_EN), ++ readl(i2c->pdmabase + OFFSET_CON)); ++ dev_dbg(i2c->dev, "DMA_TX_MEM_ADDR: 0x%x, DMA_RX_MEM_ADDR: 0x%x\n", ++ readl(i2c->pdmabase + OFFSET_TX_MEM_ADDR), ++ readl(i2c->pdmabase + OFFSET_RX_MEM_ADDR)); ++ dev_dbg(i2c->dev, "DMA_TX_LEN: 0x%x, DMA_RX_LEN: 0x%x\n", ++ readl(i2c->pdmabase + OFFSET_TX_LEN), ++ readl(i2c->pdmabase + OFFSET_RX_LEN)); ++ dev_dbg(i2c->dev, "DMA_TX_4G_MODE: 0x%x, DMA_RX_4G_MODE: 0x%x", ++ readl(i2c->pdmabase + OFFSET_TX_4G_MODE), ++ readl(i2c->pdmabase + OFFSET_RX_4G_MODE)); ++} ++ + static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, + int num, int left_num) + { +@@ -1075,6 +1128,7 @@ static int mtk_i2c_do_transfer(struct mt + + if (ret == 0) { + dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr); ++ i2c_dump_register(i2c); + mtk_i2c_init_hw(i2c); + return -ETIMEDOUT; + } diff --git a/target/linux/mediatek/patches-6.1/842-v5.18-i2c-mediatek-Add-i2c-compatible-for-Mediatek-MT8186.patch b/target/linux/mediatek/patches-6.1/842-v5.18-i2c-mediatek-Add-i2c-compatible-for-Mediatek-MT8186.patch new file mode 100644 index 00000000000..184fe94ff80 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/842-v5.18-i2c-mediatek-Add-i2c-compatible-for-Mediatek-MT8186.patch @@ -0,0 +1,45 @@ +From 83630e3c6147bf7bb18a18f3d5a99462464f450b Mon Sep 17 00:00:00 2001 +From: Kewei Xu +Date: Tue, 25 Jan 2022 19:04:13 +0800 +Subject: [PATCH 03/16] i2c: mediatek: Add i2c compatible for Mediatek MT8186 + +Add i2c compatible for MT8186. Compare to MT8192 i2c controller, +MT8186 doesn't need handshake signal witch apdma. + +Signed-off-by: Kewei Xu +Reviewed-by: Qii Wang +Signed-off-by: Wolfram Sang +--- + drivers/i2c/busses/i2c-mt65xx.c | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +--- a/drivers/i2c/busses/i2c-mt65xx.c ++++ b/drivers/i2c/busses/i2c-mt65xx.c +@@ -397,6 +397,19 @@ static const struct mtk_i2c_compatible m + .max_dma_support = 33, + }; + ++static const struct mtk_i2c_compatible mt8186_compat = { ++ .regs = mt_i2c_regs_v2, ++ .pmic_i2c = 0, ++ .dcm = 0, ++ .auto_restart = 1, ++ .aux_len_reg = 1, ++ .timing_adjust = 1, ++ .dma_sync = 0, ++ .ltiming_adjust = 1, ++ .apdma_sync = 0, ++ .max_dma_support = 36, ++}; ++ + static const struct mtk_i2c_compatible mt8192_compat = { + .quirks = &mt8183_i2c_quirks, + .regs = mt_i2c_regs_v2, +@@ -418,6 +431,7 @@ static const struct of_device_id mtk_i2c + { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat }, + { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, + { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat }, ++ { .compatible = "mediatek,mt8186-i2c", .data = &mt8186_compat }, + { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat }, + {} + }; diff --git a/target/linux/mediatek/patches-6.1/843-v5.18-i2c-mediatek-modify-bus-speed-calculation-formula.patch b/target/linux/mediatek/patches-6.1/843-v5.18-i2c-mediatek-modify-bus-speed-calculation-formula.patch new file mode 100644 index 00000000000..0ace4a6701c --- /dev/null +++ b/target/linux/mediatek/patches-6.1/843-v5.18-i2c-mediatek-modify-bus-speed-calculation-formula.patch @@ -0,0 +1,132 @@ +From f606aab3f1a49d723d66e14e545f6ca45005bda6 Mon Sep 17 00:00:00 2001 +From: Kewei Xu +Date: Thu, 17 Feb 2022 20:22:43 +0800 +Subject: [PATCH 04/16] i2c: mediatek: modify bus speed calculation formula + +When clock-div is 0 or greater than 1, the bus speed +calculated by the old speed calculation formula will be +larger than the target speed. So we update the formula. + +Signed-off-by: Kewei Xu +Reviewed-by: AngeloGioacchino Del Regno +Reviewed-by: Qii Wang +Signed-off-by: Wolfram Sang +--- + drivers/i2c/busses/i2c-mt65xx.c | 51 ++++++++++++++++++++++++++------- + 1 file changed, 41 insertions(+), 10 deletions(-) + +--- a/drivers/i2c/busses/i2c-mt65xx.c ++++ b/drivers/i2c/busses/i2c-mt65xx.c +@@ -67,11 +67,12 @@ + + #define MAX_SAMPLE_CNT_DIV 8 + #define MAX_STEP_CNT_DIV 64 +-#define MAX_CLOCK_DIV 256 ++#define MAX_CLOCK_DIV_8BITS 256 ++#define MAX_CLOCK_DIV_5BITS 32 + #define MAX_HS_STEP_CNT_DIV 8 +-#define I2C_STANDARD_MODE_BUFFER (1000 / 2) +-#define I2C_FAST_MODE_BUFFER (300 / 2) +-#define I2C_FAST_MODE_PLUS_BUFFER (20 / 2) ++#define I2C_STANDARD_MODE_BUFFER (1000 / 3) ++#define I2C_FAST_MODE_BUFFER (300 / 3) ++#define I2C_FAST_MODE_PLUS_BUFFER (20 / 3) + + #define I2C_CONTROL_RS (0x1 << 1) + #define I2C_CONTROL_DMA_EN (0x1 << 2) +@@ -604,6 +605,31 @@ static int mtk_i2c_max_step_cnt(unsigned + return MAX_STEP_CNT_DIV; + } + ++static int mtk_i2c_get_clk_div_restri(struct mtk_i2c *i2c, ++ unsigned int sample_cnt) ++{ ++ int clk_div_restri = 0; ++ ++ if (i2c->dev_comp->ltiming_adjust == 0) ++ return 0; ++ ++ if (sample_cnt == 1) { ++ if (i2c->ac_timing.inter_clk_div == 0) ++ clk_div_restri = 0; ++ else ++ clk_div_restri = 1; ++ } else { ++ if (i2c->ac_timing.inter_clk_div == 0) ++ clk_div_restri = -1; ++ else if (i2c->ac_timing.inter_clk_div == 1) ++ clk_div_restri = 0; ++ else ++ clk_div_restri = 1; ++ } ++ ++ return clk_div_restri; ++} ++ + /* + * Check and Calculate i2c ac-timing + * +@@ -732,6 +758,7 @@ static int mtk_i2c_calculate_speed(struc + unsigned int best_mul; + unsigned int cnt_mul; + int ret = -EINVAL; ++ int clk_div_restri = 0; + + if (target_speed > I2C_MAX_HIGH_SPEED_MODE_FREQ) + target_speed = I2C_MAX_HIGH_SPEED_MODE_FREQ; +@@ -749,7 +776,8 @@ static int mtk_i2c_calculate_speed(struc + * optimizing for sample_cnt * step_cnt being minimal + */ + for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) { +- step_cnt = DIV_ROUND_UP(opt_div, sample_cnt); ++ clk_div_restri = mtk_i2c_get_clk_div_restri(i2c, sample_cnt); ++ step_cnt = DIV_ROUND_UP(opt_div + clk_div_restri, sample_cnt); + cnt_mul = step_cnt * sample_cnt; + if (step_cnt > max_step_cnt) + continue; +@@ -763,7 +791,7 @@ static int mtk_i2c_calculate_speed(struc + best_mul = cnt_mul; + base_sample_cnt = sample_cnt; + base_step_cnt = step_cnt; +- if (best_mul == opt_div) ++ if (best_mul == (opt_div + clk_div_restri)) + break; + } + } +@@ -774,7 +802,8 @@ static int mtk_i2c_calculate_speed(struc + sample_cnt = base_sample_cnt; + step_cnt = base_step_cnt; + +- if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) { ++ if ((clk_src / (2 * (sample_cnt * step_cnt - clk_div_restri))) > ++ target_speed) { + /* In this case, hardware can't support such + * low i2c_bus_freq + */ +@@ -803,13 +832,16 @@ static int mtk_i2c_set_speed(struct mtk_ + target_speed = i2c->speed_hz; + parent_clk /= i2c->clk_src_div; + +- if (i2c->dev_comp->timing_adjust) +- max_clk_div = MAX_CLOCK_DIV; ++ if (i2c->dev_comp->timing_adjust && i2c->dev_comp->ltiming_adjust) ++ max_clk_div = MAX_CLOCK_DIV_5BITS; ++ else if (i2c->dev_comp->timing_adjust) ++ max_clk_div = MAX_CLOCK_DIV_8BITS; + else + max_clk_div = 1; + + for (clk_div = 1; clk_div <= max_clk_div; clk_div++) { + clk_src = parent_clk / clk_div; ++ i2c->ac_timing.inter_clk_div = clk_div - 1; + + if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) { + /* Set master code speed register */ +@@ -856,7 +888,6 @@ static int mtk_i2c_set_speed(struct mtk_ + break; + } + +- i2c->ac_timing.inter_clk_div = clk_div - 1; + + return 0; + } diff --git a/target/linux/mediatek/patches-6.1/844-v5.18-i2c-mediatek-remove-redundant-null-check.patch b/target/linux/mediatek/patches-6.1/844-v5.18-i2c-mediatek-remove-redundant-null-check.patch new file mode 100644 index 00000000000..8f3c965a8d4 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/844-v5.18-i2c-mediatek-remove-redundant-null-check.patch @@ -0,0 +1,41 @@ +From eb4a2ae019815946f574cd9f8209e12bdcd8fd34 Mon Sep 17 00:00:00 2001 +From: Xu Wang +Date: Wed, 30 Sep 2020 08:42:33 +0000 +Subject: [PATCH 05/16] i2c: mediatek: remove redundant null check + +Because clk_disable_unprepare already checked NULL clock parameter, +so the additional checks are unnecessary, just remove it + +Signed-off-by: Xu Wang +Reviewed-by: Qii Wang +Signed-off-by: Wolfram Sang +--- + drivers/i2c/busses/i2c-mt65xx.c | 9 +++------ + 1 file changed, 3 insertions(+), 6 deletions(-) + +--- a/drivers/i2c/busses/i2c-mt65xx.c ++++ b/drivers/i2c/busses/i2c-mt65xx.c +@@ -476,8 +476,7 @@ static int mtk_i2c_clock_enable(struct m + return 0; + + err_arb: +- if (i2c->have_pmic) +- clk_disable_unprepare(i2c->clk_pmic); ++ clk_disable_unprepare(i2c->clk_pmic); + err_pmic: + clk_disable_unprepare(i2c->clk_main); + err_main: +@@ -488,11 +487,9 @@ err_main: + + static void mtk_i2c_clock_disable(struct mtk_i2c *i2c) + { +- if (i2c->clk_arb) +- clk_disable_unprepare(i2c->clk_arb); ++ clk_disable_unprepare(i2c->clk_arb); + +- if (i2c->have_pmic) +- clk_disable_unprepare(i2c->clk_pmic); ++ clk_disable_unprepare(i2c->clk_pmic); + + clk_disable_unprepare(i2c->clk_main); + clk_disable_unprepare(i2c->clk_dma); diff --git a/target/linux/mediatek/patches-6.1/845-v5.18-i2c-mt65xx-Simplify-with-clk-bulk.patch b/target/linux/mediatek/patches-6.1/845-v5.18-i2c-mt65xx-Simplify-with-clk-bulk.patch new file mode 100644 index 00000000000..71d083f31a9 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/845-v5.18-i2c-mt65xx-Simplify-with-clk-bulk.patch @@ -0,0 +1,234 @@ +From cc6faa5e0772296d815fd298c231277d47308a6a Mon Sep 17 00:00:00 2001 +From: AngeloGioacchino Del Regno +Date: Thu, 3 Mar 2022 10:15:47 +0100 +Subject: [PATCH 06/16] i2c: mt65xx: Simplify with clk-bulk + +Since depending on the SoC or specific bus functionality some clocks +may be optional, we cannot get the benefit of using devm_clk_bulk_get() +but, by migrating to clk-bulk, we are able to remove the custom functions +mtk_i2c_clock_enable() and mtk_i2c_clock_disable(), increasing common +APIs usage, hence (lightly) decreasing kernel footprint. + +Signed-off-by: AngeloGioacchino Del Regno +Reviewed-by: Qii Wang +Signed-off-by: Wolfram Sang +--- + drivers/i2c/busses/i2c-mt65xx.c | 124 +++++++++++++------------------- + 1 file changed, 51 insertions(+), 73 deletions(-) + +--- a/drivers/i2c/busses/i2c-mt65xx.c ++++ b/drivers/i2c/busses/i2c-mt65xx.c +@@ -86,6 +86,27 @@ + + #define I2C_DRV_NAME "i2c-mt65xx" + ++/** ++ * enum i2c_mt65xx_clks - Clocks enumeration for MT65XX I2C ++ * ++ * @I2C_MT65XX_CLK_MAIN: main clock for i2c bus ++ * @I2C_MT65XX_CLK_DMA: DMA clock for i2c via DMA ++ * @I2C_MT65XX_CLK_PMIC: PMIC clock for i2c from PMIC ++ * @I2C_MT65XX_CLK_ARB: Arbitrator clock for i2c ++ * @I2C_MT65XX_CLK_MAX: Number of supported clocks ++ */ ++enum i2c_mt65xx_clks { ++ I2C_MT65XX_CLK_MAIN = 0, ++ I2C_MT65XX_CLK_DMA, ++ I2C_MT65XX_CLK_PMIC, ++ I2C_MT65XX_CLK_ARB, ++ I2C_MT65XX_CLK_MAX ++}; ++ ++static const char * const i2c_mt65xx_clk_ids[I2C_MT65XX_CLK_MAX] = { ++ "main", "dma", "pmic", "arb" ++}; ++ + enum DMA_REGS_OFFSET { + OFFSET_INT_FLAG = 0x0, + OFFSET_INT_EN = 0x04, +@@ -244,10 +265,7 @@ struct mtk_i2c { + /* set in i2c probe */ + void __iomem *base; /* i2c base addr */ + void __iomem *pdmabase; /* dma base address*/ +- struct clk *clk_main; /* main clock for i2c bus */ +- struct clk *clk_dma; /* DMA clock for i2c via DMA */ +- struct clk *clk_pmic; /* PMIC clock for i2c from PMIC */ +- struct clk *clk_arb; /* Arbitrator clock for i2c */ ++ struct clk_bulk_data clocks[I2C_MT65XX_CLK_MAX]; /* clocks for i2c */ + bool have_pmic; /* can use i2c pins from PMIC */ + bool use_push_pull; /* IO config push-pull mode */ + +@@ -449,52 +467,6 @@ static void mtk_i2c_writew(struct mtk_i2 + writew(val, i2c->base + i2c->dev_comp->regs[reg]); + } + +-static int mtk_i2c_clock_enable(struct mtk_i2c *i2c) +-{ +- int ret; +- +- ret = clk_prepare_enable(i2c->clk_dma); +- if (ret) +- return ret; +- +- ret = clk_prepare_enable(i2c->clk_main); +- if (ret) +- goto err_main; +- +- if (i2c->have_pmic) { +- ret = clk_prepare_enable(i2c->clk_pmic); +- if (ret) +- goto err_pmic; +- } +- +- if (i2c->clk_arb) { +- ret = clk_prepare_enable(i2c->clk_arb); +- if (ret) +- goto err_arb; +- } +- +- return 0; +- +-err_arb: +- clk_disable_unprepare(i2c->clk_pmic); +-err_pmic: +- clk_disable_unprepare(i2c->clk_main); +-err_main: +- clk_disable_unprepare(i2c->clk_dma); +- +- return ret; +-} +- +-static void mtk_i2c_clock_disable(struct mtk_i2c *i2c) +-{ +- clk_disable_unprepare(i2c->clk_arb); +- +- clk_disable_unprepare(i2c->clk_pmic); +- +- clk_disable_unprepare(i2c->clk_main); +- clk_disable_unprepare(i2c->clk_dma); +-} +- + static void mtk_i2c_init_hw(struct mtk_i2c *i2c) + { + u16 control_reg; +@@ -1191,7 +1163,7 @@ static int mtk_i2c_transfer(struct i2c_a + int left_num = num; + struct mtk_i2c *i2c = i2c_get_adapdata(adap); + +- ret = mtk_i2c_clock_enable(i2c); ++ ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks); + if (ret) + return ret; + +@@ -1245,7 +1217,7 @@ static int mtk_i2c_transfer(struct i2c_a + ret = num; + + err_exit: +- mtk_i2c_clock_disable(i2c); ++ clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); + return ret; + } + +@@ -1323,9 +1295,8 @@ static int mtk_i2c_probe(struct platform + { + int ret = 0; + struct mtk_i2c *i2c; +- struct clk *clk; + struct resource *res; +- int irq; ++ int i, irq, speed_clk; + + i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); + if (!i2c) +@@ -1371,35 +1342,42 @@ static int mtk_i2c_probe(struct platform + if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c) + return -EINVAL; + +- i2c->clk_main = devm_clk_get(&pdev->dev, "main"); +- if (IS_ERR(i2c->clk_main)) { ++ /* Fill in clk-bulk IDs */ ++ for (i = 0; i < I2C_MT65XX_CLK_MAX; i++) ++ i2c->clocks[i].id = i2c_mt65xx_clk_ids[i]; ++ ++ /* Get clocks one by one, some may be optional */ ++ i2c->clocks[I2C_MT65XX_CLK_MAIN].clk = devm_clk_get(&pdev->dev, "main"); ++ if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_MAIN].clk)) { + dev_err(&pdev->dev, "cannot get main clock\n"); +- return PTR_ERR(i2c->clk_main); ++ return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_MAIN].clk); + } + +- i2c->clk_dma = devm_clk_get(&pdev->dev, "dma"); +- if (IS_ERR(i2c->clk_dma)) { ++ i2c->clocks[I2C_MT65XX_CLK_DMA].clk = devm_clk_get(&pdev->dev, "dma"); ++ if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_DMA].clk)) { + dev_err(&pdev->dev, "cannot get dma clock\n"); +- return PTR_ERR(i2c->clk_dma); ++ return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_DMA].clk); + } + +- i2c->clk_arb = devm_clk_get(&pdev->dev, "arb"); +- if (IS_ERR(i2c->clk_arb)) +- i2c->clk_arb = NULL; ++ i2c->clocks[I2C_MT65XX_CLK_ARB].clk = devm_clk_get_optional(&pdev->dev, "arb"); ++ if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk)) ++ return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk); + +- clk = i2c->clk_main; + if (i2c->have_pmic) { +- i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic"); +- if (IS_ERR(i2c->clk_pmic)) { ++ i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get(&pdev->dev, "pmic"); ++ if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) { + dev_err(&pdev->dev, "cannot get pmic clock\n"); +- return PTR_ERR(i2c->clk_pmic); ++ return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk); + } +- clk = i2c->clk_pmic; ++ speed_clk = I2C_MT65XX_CLK_PMIC; ++ } else { ++ i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = NULL; ++ speed_clk = I2C_MT65XX_CLK_MAIN; + } + + strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name)); + +- ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk)); ++ ret = mtk_i2c_set_speed(i2c, clk_get_rate(i2c->clocks[speed_clk].clk)); + if (ret) { + dev_err(&pdev->dev, "Failed to set the speed.\n"); + return -EINVAL; +@@ -1414,13 +1392,13 @@ static int mtk_i2c_probe(struct platform + } + } + +- ret = mtk_i2c_clock_enable(i2c); ++ ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks); + if (ret) { + dev_err(&pdev->dev, "clock enable failed!\n"); + return ret; + } + mtk_i2c_init_hw(i2c); +- mtk_i2c_clock_disable(i2c); ++ clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); + + ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq, + IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE, +@@ -1465,7 +1443,7 @@ static int mtk_i2c_resume_noirq(struct d + int ret; + struct mtk_i2c *i2c = dev_get_drvdata(dev); + +- ret = mtk_i2c_clock_enable(i2c); ++ ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks); + if (ret) { + dev_err(dev, "clock enable failed!\n"); + return ret; +@@ -1473,7 +1451,7 @@ static int mtk_i2c_resume_noirq(struct d + + mtk_i2c_init_hw(i2c); + +- mtk_i2c_clock_disable(i2c); ++ clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); + + i2c_mark_adapter_resumed(&i2c->adap); + diff --git a/target/linux/mediatek/patches-6.1/846-v5.18-i2c-mediatek-Add-i2c-compatible-for-Mediatek-MT8168.patch b/target/linux/mediatek/patches-6.1/846-v5.18-i2c-mediatek-Add-i2c-compatible-for-Mediatek-MT8168.patch new file mode 100644 index 00000000000..fe5be94fca4 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/846-v5.18-i2c-mediatek-Add-i2c-compatible-for-Mediatek-MT8168.patch @@ -0,0 +1,46 @@ +From de054c03f90b3ea22bc346fbf78ac716df192b2d Mon Sep 17 00:00:00 2001 +From: Kewei Xu +Date: Mon, 7 Mar 2022 11:36:49 +0800 +Subject: [PATCH 07/16] i2c: mediatek: Add i2c compatible for Mediatek MT8168 + +Add i2c compatible for MT8168. Compare to MT2712 i2c controller, +MT8168 need to synchronize signal with dma. + +Signed-off-by: Kewei Xu +Reviewed-by: AngeloGioacchino Del Regno +Reviewed-by: Qii Wang +Signed-off-by: Wolfram Sang +--- + drivers/i2c/busses/i2c-mt65xx.c | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +--- a/drivers/i2c/busses/i2c-mt65xx.c ++++ b/drivers/i2c/busses/i2c-mt65xx.c +@@ -389,6 +389,19 @@ static const struct mtk_i2c_compatible m + .max_dma_support = 32, + }; + ++static const struct mtk_i2c_compatible mt8168_compat = { ++ .regs = mt_i2c_regs_v1, ++ .pmic_i2c = 0, ++ .dcm = 1, ++ .auto_restart = 1, ++ .aux_len_reg = 1, ++ .timing_adjust = 1, ++ .dma_sync = 1, ++ .ltiming_adjust = 0, ++ .apdma_sync = 0, ++ .max_dma_support = 33, ++}; ++ + static const struct mtk_i2c_compatible mt8173_compat = { + .regs = mt_i2c_regs_v1, + .pmic_i2c = 0, +@@ -448,6 +461,7 @@ static const struct of_device_id mtk_i2c + { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat }, + { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat }, + { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat }, ++ { .compatible = "mediatek,mt8168-i2c", .data = &mt8168_compat }, + { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, + { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat }, + { .compatible = "mediatek,mt8186-i2c", .data = &mt8186_compat }, diff --git a/target/linux/mediatek/patches-6.1/847-v5.19-i2c-mediatek-Optimize-master_xfer-and-avoid-circular.patch b/target/linux/mediatek/patches-6.1/847-v5.19-i2c-mediatek-Optimize-master_xfer-and-avoid-circular.patch new file mode 100644 index 00000000000..5c4ce40765c --- /dev/null +++ b/target/linux/mediatek/patches-6.1/847-v5.19-i2c-mediatek-Optimize-master_xfer-and-avoid-circular.patch @@ -0,0 +1,101 @@ +From 2831f9a53ec3a16012d2d23590e3ebad6084b763 Mon Sep 17 00:00:00 2001 +From: AngeloGioacchino Del Regno +Date: Mon, 11 Apr 2022 15:21:07 +0200 +Subject: [PATCH 08/16] i2c: mediatek: Optimize master_xfer() and avoid + circular locking +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Especially (but not only) during probe, it may happen that multiple +devices are communicating via i2c (or multiple i2c busses) and +sometimes while others are probing asynchronously. +For example, a Cr50 TPM may be filling entropy (or userspace may be +reading random data) while the rt5682 (i2c) codec driver reads/sets +some registers, like while getting/setting a clock's rate, which +happens both during probe and during system operation. + +In this driver, the mtk_i2c_transfer() function (which is the i2c +.master_xfer() callback) was granularly managing the clocks by +performing a clk_bulk_prepare_enable() to start them and its inverse. +This is not only creating possible circular locking dependencies in +the some cases (like former explanation), but it's also suboptimal, +as clk_core prepare/unprepare operations are using mutex locking, +which creates a bit of unwanted overhead (for example, i2c trackpads +will call master_xfer() every few milliseconds!). + +With this commit, we avoid both the circular locking and additional +overhead by changing how we handle the clocks in this driver: +- Prepare the clocks during probe (and PM resume) +- Enable/disable clocks in mtk_i2c_transfer() +- Unprepare the clocks only for driver removal (and PM suspend) + +For the sake of providing a full explanation: during probe, the +clocks are not only prepared but also enabled, as this is needed +for some hardware initialization but, after that, we are disabling +but not unpreparing them, leaving an expected state for the +aforementioned clock handling strategy. + +Signed-off-by: AngeloGioacchino Del Regno +Tested-by: Nícolas F. R. A. Prado +Reviewed-by: Qii Wang +Signed-off-by: Wolfram Sang +--- + drivers/i2c/busses/i2c-mt65xx.c | 11 +++++++---- + 1 file changed, 7 insertions(+), 4 deletions(-) + +--- a/drivers/i2c/busses/i2c-mt65xx.c ++++ b/drivers/i2c/busses/i2c-mt65xx.c +@@ -1177,7 +1177,7 @@ static int mtk_i2c_transfer(struct i2c_a + int left_num = num; + struct mtk_i2c *i2c = i2c_get_adapdata(adap); + +- ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks); ++ ret = clk_bulk_enable(I2C_MT65XX_CLK_MAX, i2c->clocks); + if (ret) + return ret; + +@@ -1231,7 +1231,7 @@ static int mtk_i2c_transfer(struct i2c_a + ret = num; + + err_exit: +- clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); ++ clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks); + return ret; + } + +@@ -1412,7 +1412,7 @@ static int mtk_i2c_probe(struct platform + return ret; + } + mtk_i2c_init_hw(i2c); +- clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); ++ clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks); + + ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq, + IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE, +@@ -1439,6 +1439,8 @@ static int mtk_i2c_remove(struct platfor + + i2c_del_adapter(&i2c->adap); + ++ clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); ++ + return 0; + } + +@@ -1448,6 +1450,7 @@ static int mtk_i2c_suspend_noirq(struct + struct mtk_i2c *i2c = dev_get_drvdata(dev); + + i2c_mark_adapter_suspended(&i2c->adap); ++ clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); + + return 0; + } +@@ -1465,7 +1468,7 @@ static int mtk_i2c_resume_noirq(struct d + + mtk_i2c_init_hw(i2c); + +- clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); ++ clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks); + + i2c_mark_adapter_resumed(&i2c->adap); + diff --git a/target/linux/mediatek/patches-6.1/848-v5.19-i2c-mediatek-Fix-an-error-handling-path-in-mtk_i2c_p.patch b/target/linux/mediatek/patches-6.1/848-v5.19-i2c-mediatek-Fix-an-error-handling-path-in-mtk_i2c_p.patch new file mode 100644 index 00000000000..354f12e2146 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/848-v5.19-i2c-mediatek-Fix-an-error-handling-path-in-mtk_i2c_p.patch @@ -0,0 +1,48 @@ +From 6f3a5814c7aaea4176e0ac8b1ec6dc0a65aa2808 Mon Sep 17 00:00:00 2001 +From: Christophe JAILLET +Date: Sun, 22 May 2022 14:22:07 +0200 +Subject: [PATCH 09/16] i2c: mediatek: Fix an error handling path in + mtk_i2c_probe() + +The clsk are prepared, enabled, then disabled. So if an error occurs after +the disable step, they are still prepared. + +Add an error handling path to unprepare the clks in such a case, as already +done in the .remove function. + +Fixes: 8b4fc246c3ff ("i2c: mediatek: Optimize master_xfer() and avoid circular locking") +Signed-off-by: Christophe JAILLET +Reviewed-by: AngeloGioacchino Del Regno +Reviewed-by: Qii Wang +Signed-off-by: Wolfram Sang +--- + drivers/i2c/busses/i2c-mt65xx.c | 9 +++++++-- + 1 file changed, 7 insertions(+), 2 deletions(-) + +--- a/drivers/i2c/busses/i2c-mt65xx.c ++++ b/drivers/i2c/busses/i2c-mt65xx.c +@@ -1420,17 +1420,22 @@ static int mtk_i2c_probe(struct platform + if (ret < 0) { + dev_err(&pdev->dev, + "Request I2C IRQ %d fail\n", irq); +- return ret; ++ goto err_bulk_unprepare; + } + + i2c_set_adapdata(&i2c->adap, i2c); + ret = i2c_add_adapter(&i2c->adap); + if (ret) +- return ret; ++ goto err_bulk_unprepare; + + platform_set_drvdata(pdev, i2c); + + return 0; ++ ++err_bulk_unprepare: ++ clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); ++ ++ return ret; + } + + static int mtk_i2c_remove(struct platform_device *pdev) diff --git a/target/linux/mediatek/patches-6.1/849-v6.0-i2c-mediatek-add-i2c-compatible-for-MT8188.patch b/target/linux/mediatek/patches-6.1/849-v6.0-i2c-mediatek-add-i2c-compatible-for-MT8188.patch new file mode 100644 index 00000000000..744aa96ed0c --- /dev/null +++ b/target/linux/mediatek/patches-6.1/849-v6.0-i2c-mediatek-add-i2c-compatible-for-MT8188.patch @@ -0,0 +1,82 @@ +From 94c7f8af2c0a399c8aa66f2522b60c5784b5be6c Mon Sep 17 00:00:00 2001 +From: Kewei Xu +Date: Sat, 6 Aug 2022 18:02:49 +0800 +Subject: [PATCH 10/16] i2c: mediatek: add i2c compatible for MT8188 + +Add i2c compatible for MT8188 and added mt_i2c_regs_v3[], since +MT8188 i2c OFFSET_SLAVE_ADDR register changed from 0x04 to 0x94. + +Signed-off-by: Kewei Xu +Reviewed-by: AngeloGioacchino Del Regno +Reviewed-by: Qii Wang +Signed-off-by: Wolfram Sang +--- + drivers/i2c/busses/i2c-mt65xx.c | 43 +++++++++++++++++++++++++++++++++ + 1 file changed, 43 insertions(+) + +--- a/drivers/i2c/busses/i2c-mt65xx.c ++++ b/drivers/i2c/busses/i2c-mt65xx.c +@@ -229,6 +229,35 @@ static const u16 mt_i2c_regs_v2[] = { + [OFFSET_DCM_EN] = 0xf88, + }; + ++static const u16 mt_i2c_regs_v3[] = { ++ [OFFSET_DATA_PORT] = 0x0, ++ [OFFSET_INTR_MASK] = 0x8, ++ [OFFSET_INTR_STAT] = 0xc, ++ [OFFSET_CONTROL] = 0x10, ++ [OFFSET_TRANSFER_LEN] = 0x14, ++ [OFFSET_TRANSAC_LEN] = 0x18, ++ [OFFSET_DELAY_LEN] = 0x1c, ++ [OFFSET_TIMING] = 0x20, ++ [OFFSET_START] = 0x24, ++ [OFFSET_EXT_CONF] = 0x28, ++ [OFFSET_LTIMING] = 0x2c, ++ [OFFSET_HS] = 0x30, ++ [OFFSET_IO_CONFIG] = 0x34, ++ [OFFSET_FIFO_ADDR_CLR] = 0x38, ++ [OFFSET_SDA_TIMING] = 0x3c, ++ [OFFSET_TRANSFER_LEN_AUX] = 0x44, ++ [OFFSET_CLOCK_DIV] = 0x48, ++ [OFFSET_SOFTRESET] = 0x50, ++ [OFFSET_MULTI_DMA] = 0x8c, ++ [OFFSET_SCL_MIS_COMP_POINT] = 0x90, ++ [OFFSET_SLAVE_ADDR] = 0x94, ++ [OFFSET_DEBUGSTAT] = 0xe4, ++ [OFFSET_DEBUGCTRL] = 0xe8, ++ [OFFSET_FIFO_STAT] = 0xf4, ++ [OFFSET_FIFO_THRESH] = 0xf8, ++ [OFFSET_DCM_EN] = 0xf88, ++}; ++ + struct mtk_i2c_compatible { + const struct i2c_adapter_quirks *quirks; + const u16 *regs; +@@ -442,6 +471,19 @@ static const struct mtk_i2c_compatible m + .max_dma_support = 36, + }; + ++static const struct mtk_i2c_compatible mt8188_compat = { ++ .regs = mt_i2c_regs_v3, ++ .pmic_i2c = 0, ++ .dcm = 0, ++ .auto_restart = 1, ++ .aux_len_reg = 1, ++ .timing_adjust = 1, ++ .dma_sync = 0, ++ .ltiming_adjust = 1, ++ .apdma_sync = 1, ++ .max_dma_support = 36, ++}; ++ + static const struct mtk_i2c_compatible mt8192_compat = { + .quirks = &mt8183_i2c_quirks, + .regs = mt_i2c_regs_v2, +@@ -465,6 +507,7 @@ static const struct of_device_id mtk_i2c + { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, + { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat }, + { .compatible = "mediatek,mt8186-i2c", .data = &mt8186_compat }, ++ { .compatible = "mediatek,mt8188-i2c", .data = &mt8188_compat }, + { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat }, + {} + }; diff --git a/target/linux/mediatek/patches-6.1/850-v6.0-i2c-move-drivers-from-strlcpy-to-strscpy.patch b/target/linux/mediatek/patches-6.1/850-v6.0-i2c-move-drivers-from-strlcpy-to-strscpy.patch new file mode 100644 index 00000000000..1520a6cbe6d --- /dev/null +++ b/target/linux/mediatek/patches-6.1/850-v6.0-i2c-move-drivers-from-strlcpy-to-strscpy.patch @@ -0,0 +1,579 @@ +From 2f4ca256a98cc19787b7c861109dd1150a21b0bf Mon Sep 17 00:00:00 2001 +From: Wolfram Sang +Date: Thu, 11 Aug 2022 09:10:30 +0200 +Subject: [PATCH 11/16] i2c: move drivers from strlcpy to strscpy + +Follow the advice of the below link and prefer 'strscpy'. Conversion is +easy because no driver used the return value and has been done with a +simple sed invocation. + +Link: https://lore.kernel.org/r/CAHk-=wgfRnXz0W3D37d01q3JFkr_i_uTL=V6A6G1oUZcprmknw@mail.gmail.com/ +Signed-off-by: Wolfram Sang +Signed-off-by: Wolfram Sang +--- + drivers/i2c/busses/i2c-altera.c | 2 +- + drivers/i2c/busses/i2c-aspeed.c | 2 +- + drivers/i2c/busses/i2c-au1550.c | 2 +- + drivers/i2c/busses/i2c-axxia.c | 2 +- + drivers/i2c/busses/i2c-bcm-kona.c | 2 +- + drivers/i2c/busses/i2c-cbus-gpio.c | 2 +- + drivers/i2c/busses/i2c-cht-wc.c | 2 +- + drivers/i2c/busses/i2c-cros-ec-tunnel.c | 2 +- + drivers/i2c/busses/i2c-davinci.c | 2 +- + drivers/i2c/busses/i2c-digicolor.c | 2 +- + drivers/i2c/busses/i2c-eg20t.c | 2 +- + drivers/i2c/busses/i2c-emev2.c | 2 +- + drivers/i2c/busses/i2c-exynos5.c | 2 +- + drivers/i2c/busses/i2c-gpio.c | 2 +- + drivers/i2c/busses/i2c-highlander.c | 2 +- + drivers/i2c/busses/i2c-hix5hd2.c | 2 +- + drivers/i2c/busses/i2c-i801.c | 4 ++-- + drivers/i2c/busses/i2c-ibm_iic.c | 2 +- + drivers/i2c/busses/i2c-icy.c | 2 +- + drivers/i2c/busses/i2c-imx-lpi2c.c | 2 +- + drivers/i2c/busses/i2c-lpc2k.c | 2 +- + drivers/i2c/busses/i2c-meson.c | 2 +- + drivers/i2c/busses/i2c-mt65xx.c | 2 +- + drivers/i2c/busses/i2c-mt7621.c | 2 +- + drivers/i2c/busses/i2c-mv64xxx.c | 2 +- + drivers/i2c/busses/i2c-mxs.c | 2 +- + drivers/i2c/busses/i2c-nvidia-gpu.c | 2 +- + drivers/i2c/busses/i2c-omap.c | 2 +- + drivers/i2c/busses/i2c-opal.c | 4 ++-- + drivers/i2c/busses/i2c-parport.c | 2 +- + drivers/i2c/busses/i2c-pxa.c | 2 +- + drivers/i2c/busses/i2c-qcom-geni.c | 2 +- + drivers/i2c/busses/i2c-qup.c | 2 +- + drivers/i2c/busses/i2c-rcar.c | 2 +- + drivers/i2c/busses/i2c-riic.c | 2 +- + drivers/i2c/busses/i2c-rk3x.c | 2 +- + drivers/i2c/busses/i2c-s3c2410.c | 2 +- + drivers/i2c/busses/i2c-sh_mobile.c | 2 +- + drivers/i2c/busses/i2c-simtec.c | 2 +- + drivers/i2c/busses/i2c-taos-evm.c | 2 +- + drivers/i2c/busses/i2c-tegra-bpmp.c | 2 +- + drivers/i2c/busses/i2c-tegra.c | 2 +- + drivers/i2c/busses/i2c-uniphier-f.c | 2 +- + drivers/i2c/busses/i2c-uniphier.c | 2 +- + drivers/i2c/busses/i2c-versatile.c | 2 +- + drivers/i2c/busses/i2c-wmt.c | 2 +- + 46 files changed, 48 insertions(+), 48 deletions(-) + +--- a/drivers/i2c/busses/i2c-altera.c ++++ b/drivers/i2c/busses/i2c-altera.c +@@ -447,7 +447,7 @@ static int altr_i2c_probe(struct platfor + mutex_unlock(&idev->isr_mutex); + + i2c_set_adapdata(&idev->adapter, idev); +- strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name)); ++ strscpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name)); + idev->adapter.owner = THIS_MODULE; + idev->adapter.algo = &altr_i2c_algo; + idev->adapter.dev.parent = &pdev->dev; +--- a/drivers/i2c/busses/i2c-aspeed.c ++++ b/drivers/i2c/busses/i2c-aspeed.c +@@ -1024,7 +1024,7 @@ static int aspeed_i2c_probe_bus(struct p + bus->adap.algo = &aspeed_i2c_algo; + bus->adap.dev.parent = &pdev->dev; + bus->adap.dev.of_node = pdev->dev.of_node; +- strlcpy(bus->adap.name, pdev->name, sizeof(bus->adap.name)); ++ strscpy(bus->adap.name, pdev->name, sizeof(bus->adap.name)); + i2c_set_adapdata(&bus->adap, bus); + + bus->dev = &pdev->dev; +--- a/drivers/i2c/busses/i2c-au1550.c ++++ b/drivers/i2c/busses/i2c-au1550.c +@@ -321,7 +321,7 @@ i2c_au1550_probe(struct platform_device + priv->adap.algo = &au1550_algo; + priv->adap.algo_data = priv; + priv->adap.dev.parent = &pdev->dev; +- strlcpy(priv->adap.name, "Au1xxx PSC I2C", sizeof(priv->adap.name)); ++ strscpy(priv->adap.name, "Au1xxx PSC I2C", sizeof(priv->adap.name)); + + /* Now, set up the PSC for SMBus PIO mode. */ + i2c_au1550_setup(priv); +--- a/drivers/i2c/busses/i2c-axxia.c ++++ b/drivers/i2c/busses/i2c-axxia.c +@@ -783,7 +783,7 @@ static int axxia_i2c_probe(struct platfo + } + + i2c_set_adapdata(&idev->adapter, idev); +- strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name)); ++ strscpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name)); + idev->adapter.owner = THIS_MODULE; + idev->adapter.algo = &axxia_i2c_algo; + idev->adapter.bus_recovery_info = &axxia_i2c_recovery_info; +--- a/drivers/i2c/busses/i2c-bcm-kona.c ++++ b/drivers/i2c/busses/i2c-bcm-kona.c +@@ -849,7 +849,7 @@ static int bcm_kona_i2c_probe(struct pla + adap = &dev->adapter; + i2c_set_adapdata(adap, dev); + adap->owner = THIS_MODULE; +- strlcpy(adap->name, "Broadcom I2C adapter", sizeof(adap->name)); ++ strscpy(adap->name, "Broadcom I2C adapter", sizeof(adap->name)); + adap->algo = &bcm_algo; + adap->dev.parent = &pdev->dev; + adap->dev.of_node = pdev->dev.of_node; +--- a/drivers/i2c/busses/i2c-cbus-gpio.c ++++ b/drivers/i2c/busses/i2c-cbus-gpio.c +@@ -245,7 +245,7 @@ static int cbus_i2c_probe(struct platfor + adapter->nr = pdev->id; + adapter->timeout = HZ; + adapter->algo = &cbus_i2c_algo; +- strlcpy(adapter->name, "CBUS I2C adapter", sizeof(adapter->name)); ++ strscpy(adapter->name, "CBUS I2C adapter", sizeof(adapter->name)); + + spin_lock_init(&chost->lock); + chost->dev = &pdev->dev; +--- a/drivers/i2c/busses/i2c-cht-wc.c ++++ b/drivers/i2c/busses/i2c-cht-wc.c +@@ -334,7 +334,7 @@ static int cht_wc_i2c_adap_i2c_probe(str + adap->adapter.class = I2C_CLASS_HWMON; + adap->adapter.algo = &cht_wc_i2c_adap_algo; + adap->adapter.lock_ops = &cht_wc_i2c_adap_lock_ops; +- strlcpy(adap->adapter.name, "PMIC I2C Adapter", ++ strscpy(adap->adapter.name, "PMIC I2C Adapter", + sizeof(adap->adapter.name)); + adap->adapter.dev.parent = &pdev->dev; + +--- a/drivers/i2c/busses/i2c-cros-ec-tunnel.c ++++ b/drivers/i2c/busses/i2c-cros-ec-tunnel.c +@@ -267,7 +267,7 @@ static int ec_i2c_probe(struct platform_ + bus->dev = dev; + + bus->adap.owner = THIS_MODULE; +- strlcpy(bus->adap.name, "cros-ec-i2c-tunnel", sizeof(bus->adap.name)); ++ strscpy(bus->adap.name, "cros-ec-i2c-tunnel", sizeof(bus->adap.name)); + bus->adap.algo = &ec_i2c_algorithm; + bus->adap.algo_data = bus; + bus->adap.dev.parent = &pdev->dev; +--- a/drivers/i2c/busses/i2c-davinci.c ++++ b/drivers/i2c/busses/i2c-davinci.c +@@ -847,7 +847,7 @@ static int davinci_i2c_probe(struct plat + i2c_set_adapdata(adap, dev); + adap->owner = THIS_MODULE; + adap->class = I2C_CLASS_DEPRECATED; +- strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name)); ++ strscpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name)); + adap->algo = &i2c_davinci_algo; + adap->dev.parent = &pdev->dev; + adap->timeout = DAVINCI_I2C_TIMEOUT; +--- a/drivers/i2c/busses/i2c-digicolor.c ++++ b/drivers/i2c/busses/i2c-digicolor.c +@@ -322,7 +322,7 @@ static int dc_i2c_probe(struct platform_ + if (ret < 0) + return ret; + +- strlcpy(i2c->adap.name, "Conexant Digicolor I2C adapter", ++ strscpy(i2c->adap.name, "Conexant Digicolor I2C adapter", + sizeof(i2c->adap.name)); + i2c->adap.owner = THIS_MODULE; + i2c->adap.algo = &dc_i2c_algorithm; +--- a/drivers/i2c/busses/i2c-eg20t.c ++++ b/drivers/i2c/busses/i2c-eg20t.c +@@ -773,7 +773,7 @@ static int pch_i2c_probe(struct pci_dev + + pch_adap->owner = THIS_MODULE; + pch_adap->class = I2C_CLASS_HWMON; +- strlcpy(pch_adap->name, KBUILD_MODNAME, sizeof(pch_adap->name)); ++ strscpy(pch_adap->name, KBUILD_MODNAME, sizeof(pch_adap->name)); + pch_adap->algo = &pch_algorithm; + pch_adap->algo_data = &adap_info->pch_data[i]; + +--- a/drivers/i2c/busses/i2c-emev2.c ++++ b/drivers/i2c/busses/i2c-emev2.c +@@ -371,7 +371,7 @@ static int em_i2c_probe(struct platform_ + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + +- strlcpy(priv->adap.name, "EMEV2 I2C", sizeof(priv->adap.name)); ++ strscpy(priv->adap.name, "EMEV2 I2C", sizeof(priv->adap.name)); + + priv->sclk = devm_clk_get(&pdev->dev, "sclk"); + if (IS_ERR(priv->sclk)) +--- a/drivers/i2c/busses/i2c-exynos5.c ++++ b/drivers/i2c/busses/i2c-exynos5.c +@@ -751,7 +751,7 @@ static int exynos5_i2c_probe(struct plat + if (of_property_read_u32(np, "clock-frequency", &i2c->op_clock)) + i2c->op_clock = I2C_MAX_STANDARD_MODE_FREQ; + +- strlcpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name)); ++ strscpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name)); + i2c->adap.owner = THIS_MODULE; + i2c->adap.algo = &exynos5_i2c_algorithm; + i2c->adap.retries = 3; +--- a/drivers/i2c/busses/i2c-gpio.c ++++ b/drivers/i2c/busses/i2c-gpio.c +@@ -436,7 +436,7 @@ static int i2c_gpio_probe(struct platfor + + adap->owner = THIS_MODULE; + if (np) +- strlcpy(adap->name, dev_name(dev), sizeof(adap->name)); ++ strscpy(adap->name, dev_name(dev), sizeof(adap->name)); + else + snprintf(adap->name, sizeof(adap->name), "i2c-gpio%d", pdev->id); + +--- a/drivers/i2c/busses/i2c-highlander.c ++++ b/drivers/i2c/busses/i2c-highlander.c +@@ -402,7 +402,7 @@ static int highlander_i2c_probe(struct p + i2c_set_adapdata(adap, dev); + adap->owner = THIS_MODULE; + adap->class = I2C_CLASS_HWMON; +- strlcpy(adap->name, "HL FPGA I2C adapter", sizeof(adap->name)); ++ strscpy(adap->name, "HL FPGA I2C adapter", sizeof(adap->name)); + adap->algo = &highlander_i2c_algo; + adap->dev.parent = &pdev->dev; + adap->nr = pdev->id; +--- a/drivers/i2c/busses/i2c-hix5hd2.c ++++ b/drivers/i2c/busses/i2c-hix5hd2.c +@@ -423,7 +423,7 @@ static int hix5hd2_i2c_probe(struct plat + } + clk_prepare_enable(priv->clk); + +- strlcpy(priv->adap.name, "hix5hd2-i2c", sizeof(priv->adap.name)); ++ strscpy(priv->adap.name, "hix5hd2-i2c", sizeof(priv->adap.name)); + priv->dev = &pdev->dev; + priv->adap.owner = THIS_MODULE; + priv->adap.algo = &hix5hd2_i2c_algorithm; +--- a/drivers/i2c/busses/i2c-i801.c ++++ b/drivers/i2c/busses/i2c-i801.c +@@ -1111,7 +1111,7 @@ static void dmi_check_onboard_device(u8 + + memset(&info, 0, sizeof(struct i2c_board_info)); + info.addr = dmi_devices[i].i2c_addr; +- strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); ++ strscpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); + i2c_new_client_device(adap, &info); + break; + } +@@ -1267,7 +1267,7 @@ static void register_dell_lis3lv02d_i2c_ + + memset(&info, 0, sizeof(struct i2c_board_info)); + info.addr = dell_lis3lv02d_devices[i].i2c_addr; +- strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE); ++ strscpy(info.type, "lis3lv02d", I2C_NAME_SIZE); + i2c_new_client_device(&priv->adapter, &info); + } + +--- a/drivers/i2c/busses/i2c-ibm_iic.c ++++ b/drivers/i2c/busses/i2c-ibm_iic.c +@@ -738,7 +738,7 @@ static int iic_probe(struct platform_dev + adap = &dev->adap; + adap->dev.parent = &ofdev->dev; + adap->dev.of_node = of_node_get(np); +- strlcpy(adap->name, "IBM IIC", sizeof(adap->name)); ++ strscpy(adap->name, "IBM IIC", sizeof(adap->name)); + i2c_set_adapdata(adap, dev); + adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; + adap->algo = &iic_algo; +--- a/drivers/i2c/busses/i2c-icy.c ++++ b/drivers/i2c/busses/i2c-icy.c +@@ -141,7 +141,7 @@ static int icy_probe(struct zorro_dev *z + i2c->adapter.owner = THIS_MODULE; + /* i2c->adapter.algo assigned by i2c_pcf_add_bus() */ + i2c->adapter.algo_data = algo_data; +- strlcpy(i2c->adapter.name, "ICY I2C Zorro adapter", ++ strscpy(i2c->adapter.name, "ICY I2C Zorro adapter", + sizeof(i2c->adapter.name)); + + if (!devm_request_mem_region(&z->dev, +--- a/drivers/i2c/busses/i2c-imx-lpi2c.c ++++ b/drivers/i2c/busses/i2c-imx-lpi2c.c +@@ -564,7 +564,7 @@ static int lpi2c_imx_probe(struct platfo + lpi2c_imx->adapter.algo = &lpi2c_imx_algo; + lpi2c_imx->adapter.dev.parent = &pdev->dev; + lpi2c_imx->adapter.dev.of_node = pdev->dev.of_node; +- strlcpy(lpi2c_imx->adapter.name, pdev->name, ++ strscpy(lpi2c_imx->adapter.name, pdev->name, + sizeof(lpi2c_imx->adapter.name)); + + lpi2c_imx->clk = devm_clk_get(&pdev->dev, NULL); +--- a/drivers/i2c/busses/i2c-lpc2k.c ++++ b/drivers/i2c/busses/i2c-lpc2k.c +@@ -417,7 +417,7 @@ static int i2c_lpc2k_probe(struct platfo + + i2c_set_adapdata(&i2c->adap, i2c); + i2c->adap.owner = THIS_MODULE; +- strlcpy(i2c->adap.name, "LPC2K I2C adapter", sizeof(i2c->adap.name)); ++ strscpy(i2c->adap.name, "LPC2K I2C adapter", sizeof(i2c->adap.name)); + i2c->adap.algo = &i2c_lpc2k_algorithm; + i2c->adap.dev.parent = &pdev->dev; + i2c->adap.dev.of_node = pdev->dev.of_node; +--- a/drivers/i2c/busses/i2c-meson.c ++++ b/drivers/i2c/busses/i2c-meson.c +@@ -451,7 +451,7 @@ static int meson_i2c_probe(struct platfo + return ret; + } + +- strlcpy(i2c->adap.name, "Meson I2C adapter", ++ strscpy(i2c->adap.name, "Meson I2C adapter", + sizeof(i2c->adap.name)); + i2c->adap.owner = THIS_MODULE; + i2c->adap.algo = &meson_i2c_algorithm; +--- a/drivers/i2c/busses/i2c-mt65xx.c ++++ b/drivers/i2c/busses/i2c-mt65xx.c +@@ -1432,7 +1432,7 @@ static int mtk_i2c_probe(struct platform + speed_clk = I2C_MT65XX_CLK_MAIN; + } + +- strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name)); ++ strscpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name)); + + ret = mtk_i2c_set_speed(i2c, clk_get_rate(i2c->clocks[speed_clk].clk)); + if (ret) { +--- a/drivers/i2c/busses/i2c-mt7621.c ++++ b/drivers/i2c/busses/i2c-mt7621.c +@@ -315,7 +315,7 @@ static int mtk_i2c_probe(struct platform + adap->dev.parent = &pdev->dev; + i2c_set_adapdata(adap, i2c); + adap->dev.of_node = pdev->dev.of_node; +- strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name)); ++ strscpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name)); + + platform_set_drvdata(pdev, i2c); + +--- a/drivers/i2c/busses/i2c-mv64xxx.c ++++ b/drivers/i2c/busses/i2c-mv64xxx.c +@@ -1000,7 +1000,7 @@ mv64xxx_i2c_probe(struct platform_device + if (IS_ERR(drv_data->reg_base)) + return PTR_ERR(drv_data->reg_base); + +- strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter", ++ strscpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter", + sizeof(drv_data->adapter.name)); + + init_waitqueue_head(&drv_data->waitq); +--- a/drivers/i2c/busses/i2c-mxs.c ++++ b/drivers/i2c/busses/i2c-mxs.c +@@ -838,7 +838,7 @@ static int mxs_i2c_probe(struct platform + return err; + + adap = &i2c->adapter; +- strlcpy(adap->name, "MXS I2C adapter", sizeof(adap->name)); ++ strscpy(adap->name, "MXS I2C adapter", sizeof(adap->name)); + adap->owner = THIS_MODULE; + adap->algo = &mxs_i2c_algo; + adap->quirks = &mxs_i2c_quirks; +--- a/drivers/i2c/busses/i2c-nvidia-gpu.c ++++ b/drivers/i2c/busses/i2c-nvidia-gpu.c +@@ -319,7 +319,7 @@ static int gpu_i2c_probe(struct pci_dev + + i2c_set_adapdata(&i2cd->adapter, i2cd); + i2cd->adapter.owner = THIS_MODULE; +- strlcpy(i2cd->adapter.name, "NVIDIA GPU I2C adapter", ++ strscpy(i2cd->adapter.name, "NVIDIA GPU I2C adapter", + sizeof(i2cd->adapter.name)); + i2cd->adapter.algo = &gpu_i2c_algorithm; + i2cd->adapter.quirks = &gpu_i2c_quirks; +--- a/drivers/i2c/busses/i2c-omap.c ++++ b/drivers/i2c/busses/i2c-omap.c +@@ -1488,7 +1488,7 @@ omap_i2c_probe(struct platform_device *p + i2c_set_adapdata(adap, omap); + adap->owner = THIS_MODULE; + adap->class = I2C_CLASS_DEPRECATED; +- strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name)); ++ strscpy(adap->name, "OMAP I2C adapter", sizeof(adap->name)); + adap->algo = &omap_i2c_algo; + adap->quirks = &omap_i2c_quirks; + adap->dev.parent = &pdev->dev; +--- a/drivers/i2c/busses/i2c-opal.c ++++ b/drivers/i2c/busses/i2c-opal.c +@@ -220,9 +220,9 @@ static int i2c_opal_probe(struct platfor + adapter->dev.of_node = of_node_get(pdev->dev.of_node); + pname = of_get_property(pdev->dev.of_node, "ibm,port-name", NULL); + if (pname) +- strlcpy(adapter->name, pname, sizeof(adapter->name)); ++ strscpy(adapter->name, pname, sizeof(adapter->name)); + else +- strlcpy(adapter->name, "opal", sizeof(adapter->name)); ++ strscpy(adapter->name, "opal", sizeof(adapter->name)); + + platform_set_drvdata(pdev, adapter); + rc = i2c_add_adapter(adapter); +--- a/drivers/i2c/busses/i2c-parport.c ++++ b/drivers/i2c/busses/i2c-parport.c +@@ -308,7 +308,7 @@ static void i2c_parport_attach(struct pa + /* Fill the rest of the structure */ + adapter->adapter.owner = THIS_MODULE; + adapter->adapter.class = I2C_CLASS_HWMON; +- strlcpy(adapter->adapter.name, "Parallel port adapter", ++ strscpy(adapter->adapter.name, "Parallel port adapter", + sizeof(adapter->adapter.name)); + adapter->algo_data = parport_algo_data; + /* Slow down if we can't sense SCL */ +--- a/drivers/i2c/busses/i2c-pxa.c ++++ b/drivers/i2c/busses/i2c-pxa.c +@@ -1403,7 +1403,7 @@ static int i2c_pxa_probe(struct platform + spin_lock_init(&i2c->lock); + init_waitqueue_head(&i2c->wait); + +- strlcpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name)); ++ strscpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name)); + + i2c->clk = devm_clk_get(&dev->dev, NULL); + if (IS_ERR(i2c->clk)) { +--- a/drivers/i2c/busses/i2c-qcom-geni.c ++++ b/drivers/i2c/busses/i2c-qcom-geni.c +@@ -577,7 +577,7 @@ static int geni_i2c_probe(struct platfor + i2c_set_adapdata(&gi2c->adap, gi2c); + gi2c->adap.dev.parent = dev; + gi2c->adap.dev.of_node = dev->of_node; +- strlcpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name)); ++ strscpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name)); + + ret = geni_icc_get(&gi2c->se, "qup-memory"); + if (ret) +--- a/drivers/i2c/busses/i2c-qup.c ++++ b/drivers/i2c/busses/i2c-qup.c +@@ -1878,7 +1878,7 @@ nodma: + qup->adap.dev.of_node = pdev->dev.of_node; + qup->is_last = true; + +- strlcpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name)); ++ strscpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name)); + + pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC); + pm_runtime_use_autosuspend(qup->dev); +--- a/drivers/i2c/busses/i2c-rcar.c ++++ b/drivers/i2c/busses/i2c-rcar.c +@@ -1059,7 +1059,7 @@ static int rcar_i2c_probe(struct platfor + adap->bus_recovery_info = &rcar_i2c_bri; + adap->quirks = &rcar_i2c_quirks; + i2c_set_adapdata(adap, priv); +- strlcpy(adap->name, pdev->name, sizeof(adap->name)); ++ strscpy(adap->name, pdev->name, sizeof(adap->name)); + + /* Init DMA */ + sg_init_table(&priv->sg, 1); +--- a/drivers/i2c/busses/i2c-riic.c ++++ b/drivers/i2c/busses/i2c-riic.c +@@ -447,7 +447,7 @@ static int riic_i2c_probe(struct platfor + + adap = &riic->adapter; + i2c_set_adapdata(adap, riic); +- strlcpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name)); ++ strscpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name)); + adap->owner = THIS_MODULE; + adap->algo = &riic_algo; + adap->dev.parent = &pdev->dev; +--- a/drivers/i2c/busses/i2c-rk3x.c ++++ b/drivers/i2c/busses/i2c-rk3x.c +@@ -1240,7 +1240,7 @@ static int rk3x_i2c_probe(struct platfor + /* use common interface to get I2C timing properties */ + i2c_parse_fw_timings(&pdev->dev, &i2c->t, true); + +- strlcpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name)); ++ strscpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name)); + i2c->adap.owner = THIS_MODULE; + i2c->adap.algo = &rk3x_i2c_algorithm; + i2c->adap.retries = 3; +--- a/drivers/i2c/busses/i2c-s3c2410.c ++++ b/drivers/i2c/busses/i2c-s3c2410.c +@@ -1076,7 +1076,7 @@ static int s3c24xx_i2c_probe(struct plat + else + s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c); + +- strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name)); ++ strscpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name)); + i2c->adap.owner = THIS_MODULE; + i2c->adap.algo = &s3c24xx_i2c_algorithm; + i2c->adap.retries = 2; +--- a/drivers/i2c/busses/i2c-sh_mobile.c ++++ b/drivers/i2c/busses/i2c-sh_mobile.c +@@ -930,7 +930,7 @@ static int sh_mobile_i2c_probe(struct pl + adap->nr = dev->id; + adap->dev.of_node = dev->dev.of_node; + +- strlcpy(adap->name, dev->name, sizeof(adap->name)); ++ strscpy(adap->name, dev->name, sizeof(adap->name)); + + spin_lock_init(&pd->lock); + init_waitqueue_head(&pd->wait); +--- a/drivers/i2c/busses/i2c-simtec.c ++++ b/drivers/i2c/busses/i2c-simtec.c +@@ -99,7 +99,7 @@ static int simtec_i2c_probe(struct platf + pd->adap.algo_data = &pd->bit; + pd->adap.dev.parent = &dev->dev; + +- strlcpy(pd->adap.name, "Simtec I2C", sizeof(pd->adap.name)); ++ strscpy(pd->adap.name, "Simtec I2C", sizeof(pd->adap.name)); + + pd->bit.data = pd; + pd->bit.setsda = simtec_i2c_setsda; +--- a/drivers/i2c/busses/i2c-taos-evm.c ++++ b/drivers/i2c/busses/i2c-taos-evm.c +@@ -239,7 +239,7 @@ static int taos_connect(struct serio *se + dev_err(&serio->dev, "TAOS EVM identification failed\n"); + goto exit_close; + } +- strlcpy(adapter->name, name, sizeof(adapter->name)); ++ strscpy(adapter->name, name, sizeof(adapter->name)); + + /* Turn echo off for better performance */ + taos->state = TAOS_STATE_EOFF; +--- a/drivers/i2c/busses/i2c-tegra-bpmp.c ++++ b/drivers/i2c/busses/i2c-tegra-bpmp.c +@@ -305,7 +305,7 @@ static int tegra_bpmp_i2c_probe(struct p + + i2c_set_adapdata(&i2c->adapter, i2c); + i2c->adapter.owner = THIS_MODULE; +- strlcpy(i2c->adapter.name, "Tegra BPMP I2C adapter", ++ strscpy(i2c->adapter.name, "Tegra BPMP I2C adapter", + sizeof(i2c->adapter.name)); + i2c->adapter.algo = &tegra_bpmp_i2c_algo; + i2c->adapter.dev.parent = &pdev->dev; +--- a/drivers/i2c/busses/i2c-tegra.c ++++ b/drivers/i2c/busses/i2c-tegra.c +@@ -1799,7 +1799,7 @@ static int tegra_i2c_probe(struct platfo + if (i2c_dev->hw->supports_bus_clear) + i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info; + +- strlcpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev), ++ strscpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev), + sizeof(i2c_dev->adapter.name)); + + err = i2c_add_numbered_adapter(&i2c_dev->adapter); +--- a/drivers/i2c/busses/i2c-uniphier-f.c ++++ b/drivers/i2c/busses/i2c-uniphier-f.c +@@ -564,7 +564,7 @@ static int uniphier_fi2c_probe(struct pl + priv->adap.algo = &uniphier_fi2c_algo; + priv->adap.dev.parent = dev; + priv->adap.dev.of_node = dev->of_node; +- strlcpy(priv->adap.name, "UniPhier FI2C", sizeof(priv->adap.name)); ++ strscpy(priv->adap.name, "UniPhier FI2C", sizeof(priv->adap.name)); + priv->adap.bus_recovery_info = &uniphier_fi2c_bus_recovery_info; + i2c_set_adapdata(&priv->adap, priv); + platform_set_drvdata(pdev, priv); +--- a/drivers/i2c/busses/i2c-uniphier.c ++++ b/drivers/i2c/busses/i2c-uniphier.c +@@ -358,7 +358,7 @@ static int uniphier_i2c_probe(struct pla + priv->adap.algo = &uniphier_i2c_algo; + priv->adap.dev.parent = dev; + priv->adap.dev.of_node = dev->of_node; +- strlcpy(priv->adap.name, "UniPhier I2C", sizeof(priv->adap.name)); ++ strscpy(priv->adap.name, "UniPhier I2C", sizeof(priv->adap.name)); + priv->adap.bus_recovery_info = &uniphier_i2c_bus_recovery_info; + i2c_set_adapdata(&priv->adap, priv); + platform_set_drvdata(pdev, priv); +--- a/drivers/i2c/busses/i2c-versatile.c ++++ b/drivers/i2c/busses/i2c-versatile.c +@@ -79,7 +79,7 @@ static int i2c_versatile_probe(struct pl + writel(SCL | SDA, i2c->base + I2C_CONTROLS); + + i2c->adap.owner = THIS_MODULE; +- strlcpy(i2c->adap.name, "Versatile I2C adapter", sizeof(i2c->adap.name)); ++ strscpy(i2c->adap.name, "Versatile I2C adapter", sizeof(i2c->adap.name)); + i2c->adap.algo_data = &i2c->algo; + i2c->adap.dev.parent = &dev->dev; + i2c->adap.dev.of_node = dev->dev.of_node; +--- a/drivers/i2c/busses/i2c-wmt.c ++++ b/drivers/i2c/busses/i2c-wmt.c +@@ -413,7 +413,7 @@ static int wmt_i2c_probe(struct platform + + adap = &i2c_dev->adapter; + i2c_set_adapdata(adap, i2c_dev); +- strlcpy(adap->name, "WMT I2C adapter", sizeof(adap->name)); ++ strscpy(adap->name, "WMT I2C adapter", sizeof(adap->name)); + adap->owner = THIS_MODULE; + adap->algo = &wmt_i2c_algo; + adap->dev.parent = &pdev->dev; diff --git a/target/linux/mediatek/patches-6.1/851-v6.2-i2c-mediatek-add-mt7986-support.patch b/target/linux/mediatek/patches-6.1/851-v6.2-i2c-mediatek-add-mt7986-support.patch new file mode 100644 index 00000000000..4c398c59f93 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/851-v6.2-i2c-mediatek-add-mt7986-support.patch @@ -0,0 +1,44 @@ +From 11f9a0f4e51887ad7b4a2898a368fcd0c2984e89 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Sun, 9 Oct 2022 12:16:31 +0200 +Subject: [PATCH 12/16] i2c: mediatek: add mt7986 support + +Add i2c support for MT7986 SoC. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Wolfram Sang +--- + drivers/i2c/busses/i2c-mt65xx.c | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +--- a/drivers/i2c/busses/i2c-mt65xx.c ++++ b/drivers/i2c/busses/i2c-mt65xx.c +@@ -431,6 +431,19 @@ static const struct mtk_i2c_compatible m + .max_dma_support = 33, + }; + ++static const struct mtk_i2c_compatible mt7986_compat = { ++ .quirks = &mt7622_i2c_quirks, ++ .regs = mt_i2c_regs_v1, ++ .pmic_i2c = 0, ++ .dcm = 1, ++ .auto_restart = 1, ++ .aux_len_reg = 1, ++ .timing_adjust = 0, ++ .dma_sync = 1, ++ .ltiming_adjust = 0, ++ .max_dma_support = 32, ++}; ++ + static const struct mtk_i2c_compatible mt8173_compat = { + .regs = mt_i2c_regs_v1, + .pmic_i2c = 0, +@@ -503,6 +516,7 @@ static const struct of_device_id mtk_i2c + { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat }, + { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat }, + { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat }, ++ { .compatible = "mediatek,mt7986-i2c", .data = &mt7986_compat }, + { .compatible = "mediatek,mt8168-i2c", .data = &mt8168_compat }, + { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, + { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat }, diff --git a/target/linux/mediatek/patches-6.1/852-v6.3-i2c-mt65xx-Use-devm_platform_get_and_ioremap_resourc.patch b/target/linux/mediatek/patches-6.1/852-v6.3-i2c-mt65xx-Use-devm_platform_get_and_ioremap_resourc.patch new file mode 100644 index 00000000000..18c66cdac52 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/852-v6.3-i2c-mt65xx-Use-devm_platform_get_and_ioremap_resourc.patch @@ -0,0 +1,42 @@ +From 98204ccafd45a8a6109ff2d60e2c179b95d92578 Mon Sep 17 00:00:00 2001 +From: ye xingchen +Date: Thu, 19 Jan 2023 17:19:58 +0800 +Subject: [PATCH 13/16] i2c: mt65xx: Use + devm_platform_get_and_ioremap_resource() + +Convert platform_get_resource(), devm_ioremap_resource() to a single +call to devm_platform_get_and_ioremap_resource(), as this is exactly +what this function does. + +Signed-off-by: ye xingchen +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Wolfram Sang +--- + drivers/i2c/busses/i2c-mt65xx.c | 7 ++----- + 1 file changed, 2 insertions(+), 5 deletions(-) + +--- a/drivers/i2c/busses/i2c-mt65xx.c ++++ b/drivers/i2c/busses/i2c-mt65xx.c +@@ -1366,20 +1366,17 @@ static int mtk_i2c_probe(struct platform + { + int ret = 0; + struct mtk_i2c *i2c; +- struct resource *res; + int i, irq, speed_clk; + + i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); + if (!i2c) + return -ENOMEM; + +- res = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- i2c->base = devm_ioremap_resource(&pdev->dev, res); ++ i2c->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); + if (IS_ERR(i2c->base)) + return PTR_ERR(i2c->base); + +- res = platform_get_resource(pdev, IORESOURCE_MEM, 1); +- i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res); ++ i2c->pdmabase = devm_platform_get_and_ioremap_resource(pdev, 1, NULL); + if (IS_ERR(i2c->pdmabase)) + return PTR_ERR(i2c->pdmabase); + diff --git a/target/linux/mediatek/patches-6.1/853-v6.3-i2c-mt65xx-drop-of_match_ptr-for-ID-table.patch b/target/linux/mediatek/patches-6.1/853-v6.3-i2c-mt65xx-drop-of_match_ptr-for-ID-table.patch new file mode 100644 index 00000000000..d000d535226 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/853-v6.3-i2c-mt65xx-drop-of_match_ptr-for-ID-table.patch @@ -0,0 +1,33 @@ +From 8106fa2e0ae6082833fe1df97829c46c0183eaea Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski +Date: Sat, 11 Mar 2023 12:16:54 +0100 +Subject: [PATCH 14/16] i2c: mt65xx: drop of_match_ptr for ID table +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The driver can match only via the DT table so the table should be always +used and the of_match_ptr does not have any sense (this also allows ACPI +matching via PRP0001, even though it might not be relevant here). + + drivers/i2c/busses/i2c-mt65xx.c:514:34: error: ‘mtk_i2c_of_match’ defined but not used [-Werror=unused-const-variable=] + +Signed-off-by: Krzysztof Kozlowski +Reviewed-by: Guenter Roeck +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Wolfram Sang +--- + drivers/i2c/busses/i2c-mt65xx.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/i2c/busses/i2c-mt65xx.c ++++ b/drivers/i2c/busses/i2c-mt65xx.c +@@ -1546,7 +1546,7 @@ static struct platform_driver mtk_i2c_dr + .driver = { + .name = I2C_DRV_NAME, + .pm = &mtk_i2c_pm, +- .of_match_table = of_match_ptr(mtk_i2c_of_match), ++ .of_match_table = mtk_i2c_of_match, + }, + }; + diff --git a/target/linux/mediatek/patches-6.1/854-v6.4-i2c-mediatek-add-support-for-MT7981-SoC.patch b/target/linux/mediatek/patches-6.1/854-v6.4-i2c-mediatek-add-support-for-MT7981-SoC.patch new file mode 100644 index 00000000000..e0973741e29 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/854-v6.4-i2c-mediatek-add-support-for-MT7981-SoC.patch @@ -0,0 +1,47 @@ +From f69f3d662ba3bf999c36d9ac1e684540c4487bc3 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Mon, 10 Apr 2023 17:19:38 +0100 +Subject: [PATCH 15/16] i2c: mediatek: add support for MT7981 SoC + +Add support for the I2C units found in the MediaTek MT7981 and MT7988 +SoCs. Just like other recent MediaTek I2C units that also uses v3 +register offsets (which differ from v2 only by OFFSET_SLAVE_ADDR being +0x94 instead of 0x4). + +Signed-off-by: Daniel Golle +Reviewed-by: AngeloGioacchino Del Regno +Reviewed-by: Alexandre Mergnat +Signed-off-by: Wolfram Sang +--- + drivers/i2c/busses/i2c-mt65xx.c | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +--- a/drivers/i2c/busses/i2c-mt65xx.c ++++ b/drivers/i2c/busses/i2c-mt65xx.c +@@ -431,6 +431,18 @@ static const struct mtk_i2c_compatible m + .max_dma_support = 33, + }; + ++static const struct mtk_i2c_compatible mt7981_compat = { ++ .regs = mt_i2c_regs_v3, ++ .pmic_i2c = 0, ++ .dcm = 0, ++ .auto_restart = 1, ++ .aux_len_reg = 1, ++ .timing_adjust = 1, ++ .dma_sync = 1, ++ .ltiming_adjust = 1, ++ .max_dma_support = 33 ++}; ++ + static const struct mtk_i2c_compatible mt7986_compat = { + .quirks = &mt7622_i2c_quirks, + .regs = mt_i2c_regs_v1, +@@ -516,6 +528,7 @@ static const struct of_device_id mtk_i2c + { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat }, + { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat }, + { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat }, ++ { .compatible = "mediatek,mt7981-i2c", .data = &mt7981_compat }, + { .compatible = "mediatek,mt7986-i2c", .data = &mt7986_compat }, + { .compatible = "mediatek,mt8168-i2c", .data = &mt8168_compat }, + { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, diff --git a/target/linux/mediatek/patches-6.1/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch b/target/linux/mediatek/patches-6.1/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch new file mode 100644 index 00000000000..f779c1e0473 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch @@ -0,0 +1,65 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +@@ -318,7 +318,7 @@ + /* Attention: GPIO 90 is used to switch between PCIe@1,0 and + * SATA functions. i.e. output-high: PCIe, output-low: SATA + */ +- asm_sel { ++ asmsel: asm_sel { + gpio-hog; + gpios = <90 GPIO_ACTIVE_HIGH>; + output-high; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-sata.dtso +@@ -0,0 +1,31 @@ ++/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ ++ ++#include ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "bananapi,bpi-r64", "mediatek,mt7622"; ++ ++ fragment@0 { ++ target = <&asmsel>; ++ __overlay__ { ++ gpios = <90 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&sata>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&sata_phy>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-pcie1.dtso +@@ -0,0 +1,17 @@ ++/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ ++ ++#include ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "bananapi,bpi-r64", "mediatek,mt7622"; ++ ++ fragment@0 { ++ target = <&asmsel>; ++ __overlay__ { ++ gpios = <90 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++}; diff --git a/target/linux/mediatek/patches-6.1/901-arm-add-cmdline-override.patch b/target/linux/mediatek/patches-6.1/901-arm-add-cmdline-override.patch new file mode 100644 index 00000000000..6016128bd4a --- /dev/null +++ b/target/linux/mediatek/patches-6.1/901-arm-add-cmdline-override.patch @@ -0,0 +1,54 @@ +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -1729,6 +1729,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN + + endchoice + ++config CMDLINE_OVERRIDE ++ bool "Use alternative cmdline from device tree" ++ help ++ Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can ++ be used, this is not a good option for kernels that are shared across ++ devices. This setting enables using "chosen/cmdline-override" as the ++ cmdline if it exists in the device tree. ++ + config CMDLINE + string "Default kernel command string" + default "" +--- a/drivers/of/fdt.c ++++ b/drivers/of/fdt.c +@@ -1162,6 +1162,17 @@ int __init early_init_dt_scan_chosen(uns + if (p != NULL && l > 0) + strlcat(data, p, min_t(int, strlen(data) + (int)l, COMMAND_LINE_SIZE)); + ++ /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different ++ * device tree option of chosen/bootargs-override. This is ++ * helpful on boards where u-boot sets bootargs, and is unable ++ * to be modified. ++ */ ++#ifdef CONFIG_CMDLINE_OVERRIDE ++ p = of_get_flat_dt_prop(node, "bootargs-override", &l); ++ if (p != NULL && l > 0) ++ strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE)); ++#endif ++ + /* + * CONFIG_CMDLINE is meant to be a default in case nothing else + * managed to set the command line, unless CONFIG_CMDLINE_FORCE +--- a/arch/arm64/Kconfig ++++ b/arch/arm64/Kconfig +@@ -1942,6 +1942,14 @@ config CMDLINE_FORCE + + endchoice + ++config CMDLINE_OVERRIDE ++ bool "Use alternative cmdline from device tree" ++ help ++ Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can ++ be used, this is not a good option for kernels that are shared across ++ devices. This setting enables using "chosen/cmdline-override" as the ++ cmdline if it exists in the device tree. ++ + config EFI_STUB + bool + diff --git a/target/linux/mediatek/patches-6.1/910-dts-mt7622-bpi-r64-wifi-eeprom.patch b/target/linux/mediatek/patches-6.1/910-dts-mt7622-bpi-r64-wifi-eeprom.patch new file mode 100644 index 00000000000..2a863aecf93 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/910-dts-mt7622-bpi-r64-wifi-eeprom.patch @@ -0,0 +1,31 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +@@ -645,5 +645,28 @@ + }; + + &wmac { ++ mediatek,eeprom-data = <0x22760500 0x0 0x0 0x0 ++ 0x0 0x0 0x0 0x0 ++ 0x0 0x0 0x0 0x0 ++ 0x0 0x44000020 0x0 0x10002000 ++ 0x4400 0x4000000 0x0 0x0 ++ 0x200000b3 0x40b6c3c3 0x26000000 0x41c42600 ++ 0x41c4 0x26000000 0xc0c52600 0x0 ++ 0x0 0x0 0x0 0x0 ++ 0x0 0x0 0x0 0x0 ++ 0x0 0x0 0x0 0x0 ++ 0x0 0x0 0x0 0x0 ++ 0x0 0x0 0x0 0xc6c6 ++ 0xc3c3c2c1 0xc300c3 0x818181 0x83c1c182 ++ 0x83838382 0x0 0x0 0x0 ++ 0x0 0x0 0x0 0x0 ++ 0x84002e00 0x90000087 0x8a000000 0x0 ++ 0x0 0x0 0x0 0x0 ++ 0x0 0x0 0x0 0x0 ++ 0xb000009 0x0 0x0 0x0 ++ 0x0 0x0 0x0 0x0 ++ 0x0 0x0 0x0 0x0 ++ 0x0 0x0 0x0 0x7707>; ++ + status = "okay"; + }; diff --git a/target/linux/mediatek/patches-6.1/920-v5.16-watchdog-mtk-add-disable_wdt_extrst-support.patch b/target/linux/mediatek/patches-6.1/920-v5.16-watchdog-mtk-add-disable_wdt_extrst-support.patch new file mode 100644 index 00000000000..d9379721fb8 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/920-v5.16-watchdog-mtk-add-disable_wdt_extrst-support.patch @@ -0,0 +1,50 @@ +From 59b0f51335644ee603260faaa4298c0115fb7187 Mon Sep 17 00:00:00 2001 +From: Fengquan Chen +Date: Tue, 14 Sep 2021 20:34:54 +0800 +Subject: [PATCH] watchdog: mtk: add disable_wdt_extrst support + +In some cases, we may need watchdog just to trigger an +internal soc reset without sending any output signal. + +Provide a disable_wdt_extrst parameter for configuration. +We can disable or enable it just by configuring dts. + +Signed-off-by: Fengquan Chen +Reviewed-by: Guenter Roeck +Link: https://lore.kernel.org/r/20210914123454.32603-3-Fengquan.Chen@mediatek.com +Signed-off-by: Guenter Roeck +Signed-off-by: Wim Van Sebroeck +--- + drivers/watchdog/mtk_wdt.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/drivers/watchdog/mtk_wdt.c ++++ b/drivers/watchdog/mtk_wdt.c +@@ -65,6 +65,7 @@ struct mtk_wdt_dev { + void __iomem *wdt_base; + spinlock_t lock; /* protects WDT_SWSYSRST reg */ + struct reset_controller_dev rcdev; ++ bool disable_wdt_extrst; + }; + + struct mtk_wdt_data { +@@ -256,6 +257,8 @@ static int mtk_wdt_start(struct watchdog + reg |= (WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN); + else + reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN); ++ if (mtk_wdt->disable_wdt_extrst) ++ reg &= ~WDT_MODE_EXRST_EN; + reg |= (WDT_MODE_EN | WDT_MODE_KEY); + iowrite32(reg, wdt_base + WDT_MODE); + +@@ -381,6 +384,10 @@ static int mtk_wdt_probe(struct platform + if (err) + return err; + } ++ ++ mtk_wdt->disable_wdt_extrst = ++ of_property_read_bool(dev->of_node, "mediatek,disable-extrst"); ++ + return 0; + } + diff --git a/target/linux/mediatek/patches-6.1/921-v5.19-watchdog-mtk_wdt-mt7986-Add-toprgu-reset-controller.patch b/target/linux/mediatek/patches-6.1/921-v5.19-watchdog-mtk_wdt-mt7986-Add-toprgu-reset-controller.patch new file mode 100644 index 00000000000..96fb215f76c --- /dev/null +++ b/target/linux/mediatek/patches-6.1/921-v5.19-watchdog-mtk_wdt-mt7986-Add-toprgu-reset-controller.patch @@ -0,0 +1,49 @@ +From 711a5b25bac95dcd1111521ed71693330e74a926 Mon Sep 17 00:00:00 2001 +From: Sam Shih +Date: Wed, 5 Jan 2022 18:04:56 +0800 +Subject: [PATCH] watchdog: mtk_wdt: mt7986: Add toprgu reset controller + support + +Besides watchdog, the mt7986 toprgu module also provides software reset +functionality for various peripheral subsystems +(eg, ethernet, pcie, and connectivity) + +Signed-off-by: Sam Shih +Reviewed-by: Matthias Brugger +Reviewed-by: Guenter Roeck +Link: https://lore.kernel.org/r/20220105100456.7126-3-sam.shih@mediatek.com +Signed-off-by: Guenter Roeck +Signed-off-by: Wim Van Sebroeck +--- + drivers/watchdog/mtk_wdt.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/drivers/watchdog/mtk_wdt.c ++++ b/drivers/watchdog/mtk_wdt.c +@@ -10,6 +10,7 @@ + */ + + #include ++#include + #include + #include + #include +@@ -76,6 +77,10 @@ static const struct mtk_wdt_data mt2712_ + .toprgu_sw_rst_num = MT2712_TOPRGU_SW_RST_NUM, + }; + ++static const struct mtk_wdt_data mt7986_data = { ++ .toprgu_sw_rst_num = MT7986_TOPRGU_SW_RST_NUM, ++}; ++ + static const struct mtk_wdt_data mt8183_data = { + .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM, + }; +@@ -418,6 +423,7 @@ static int mtk_wdt_resume(struct device + static const struct of_device_id mtk_wdt_dt_ids[] = { + { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data }, + { .compatible = "mediatek,mt6589-wdt" }, ++ { .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data }, + { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data }, + { .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data }, + { .compatible = "mediatek,mt8195-wdt", .data = &mt8195_data }, diff --git a/target/linux/mediatek/patches-6.1/922-v6.1-PCI-mediatek-gen3-change-driver-name-to-mtk-pcie-gen.patch b/target/linux/mediatek/patches-6.1/922-v6.1-PCI-mediatek-gen3-change-driver-name-to-mtk-pcie-gen.patch new file mode 100644 index 00000000000..44aed2207d5 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/922-v6.1-PCI-mediatek-gen3-change-driver-name-to-mtk-pcie-gen.patch @@ -0,0 +1,20 @@ +From: Felix Fietkau +Date: Wed, 4 May 2022 12:03:42 +0200 +Subject: [PATCH] PCI: mediatek-gen3: change driver name to mtk-pcie-gen3 + +This allows it to coexist with the other mtk pcie driver in the same kernel + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/pci/controller/pcie-mediatek-gen3.c ++++ b/drivers/pci/controller/pcie-mediatek-gen3.c +@@ -1025,7 +1025,7 @@ static struct platform_driver mtk_pcie_d + .probe = mtk_pcie_probe, + .remove = mtk_pcie_remove, + .driver = { +- .name = "mtk-pcie", ++ .name = "mtk-pcie-gen3", + .of_match_table = mtk_pcie_of_match, + .pm = &mtk_pcie_pm_ops, + }, diff --git a/target/linux/mediatek/patches-6.1/930-spi-mt65xx-enable-sel-clk.patch b/target/linux/mediatek/patches-6.1/930-spi-mt65xx-enable-sel-clk.patch new file mode 100644 index 00000000000..ebb6c060b54 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/930-spi-mt65xx-enable-sel-clk.patch @@ -0,0 +1,29 @@ +--- a/drivers/spi/spi-mt65xx.c ++++ b/drivers/spi/spi-mt65xx.c +@@ -1231,10 +1231,16 @@ static int mtk_spi_probe(struct platform + goto err_disable_spi_hclk; + } + ++ ret = clk_prepare_enable(mdata->sel_clk); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "failed to enable sel_clk (%d)\n", ret); ++ goto err_disable_spi_clk; ++ } ++ + ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk); + if (ret < 0) { + dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret); +- goto err_disable_spi_clk; ++ goto err_disable_spi_sel_clk; + } + + mdata->spi_clk_hz = clk_get_rate(mdata->spi_clk); +@@ -1285,6 +1291,8 @@ static int mtk_spi_probe(struct platform + + err_disable_runtime_pm: + pm_runtime_disable(&pdev->dev); ++err_disable_spi_sel_clk: ++ clk_disable_unprepare(mdata->sel_clk); + err_disable_spi_clk: + clk_disable_unprepare(mdata->spi_clk); + err_disable_spi_hclk: diff --git a/target/linux/mediatek/patches-6.1/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch b/target/linux/mediatek/patches-6.1/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch new file mode 100644 index 00000000000..2fe565f3b25 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch @@ -0,0 +1,44 @@ +From 3cf212c4ce6cd72c09bc47f35f539ba0afd4d106 Mon Sep 17 00:00:00 2001 +Message-Id: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org> +From: Lorenzo Bianconi +Date: Sun, 12 Mar 2023 16:40:31 +0100 +Subject: [PATCH net-next 1/2] net: ethernet: mtk_wed: rename + mtk_wed_get_memory_region in mtk_wed_get_reserved_memory_region + +This is a preliminary patch to move wed ilm/dlm and cpuboot properties in +dedicated dts nodes. + +Signed-off-by: Lorenzo Bianconi +--- + drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c ++++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c +@@ -215,8 +215,8 @@ int mtk_wed_mcu_msg_update(struct mtk_we + } + + static int +-mtk_wed_get_memory_region(struct mtk_wed_wo *wo, +- struct mtk_wed_wo_memory_region *region) ++mtk_wed_get_reserved_memory_region(struct mtk_wed_wo *wo, ++ struct mtk_wed_wo_memory_region *region) + { + struct reserved_mem *rmem; + struct device_node *np; +@@ -311,13 +311,13 @@ mtk_wed_mcu_load_firmware(struct mtk_wed + + /* load firmware region metadata */ + for (i = 0; i < ARRAY_SIZE(mem_region); i++) { +- ret = mtk_wed_get_memory_region(wo, &mem_region[i]); ++ ret = mtk_wed_get_reserved_memory_region(wo, &mem_region[i]); + if (ret) + return ret; + } + + wo->boot.name = "wo-boot"; +- ret = mtk_wed_get_memory_region(wo, &wo->boot); ++ ret = mtk_wed_get_reserved_memory_region(wo, &wo->boot); + if (ret) + return ret; + diff --git a/target/linux/mediatek/patches-6.1/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch b/target/linux/mediatek/patches-6.1/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch new file mode 100644 index 00000000000..0a58ae953b4 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch @@ -0,0 +1,66 @@ +From 247e566e3459481f1fa98733534bfed767e18b42 Mon Sep 17 00:00:00 2001 +Message-Id: <247e566e3459481f1fa98733534bfed767e18b42.1678620342.git.lorenzo@kernel.org> +From: Lorenzo Bianconi +Date: Sat, 11 Mar 2023 16:32:41 +0100 +Subject: [PATCH net-next] arm64: dts: mt7986: move cpuboot in a dedicated node + +Signed-off-by: Lorenzo Bianconi +--- + arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 21 +++++++++++---------- + 1 file changed, 11 insertions(+), 10 deletions(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +@@ -121,12 +121,6 @@ + reg = <0 0x151f8000 0 0x2000>; + no-map; + }; +- +- wo_boot: wo-boot@15194000 { +- reg = <0 0x15194000 0 0x1000>; +- no-map; +- }; +- + }; + + timer { +@@ -518,10 +512,11 @@ + interrupt-parent = <&gic>; + interrupts = ; + memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, +- <&wo_data>, <&wo_boot>; ++ <&wo_data>; + memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", +- "wo-data", "wo-boot"; ++ "wo-data"; + mediatek,wo-ccif = <&wo_ccif0>; ++ mediatek,wo-cpuboot = <&wo_cpuboot>; + }; + + wed1: wed@15011000 { +@@ -531,10 +526,11 @@ + interrupt-parent = <&gic>; + interrupts = ; + memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>, +- <&wo_data>, <&wo_boot>; ++ <&wo_data>; + memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", +- "wo-data", "wo-boot"; ++ "wo-data"; + mediatek,wo-ccif = <&wo_ccif1>; ++ mediatek,wo-cpuboot = <&wo_cpuboot>; + }; + + wo_ccif0: syscon@151a5000 { +@@ -551,6 +547,11 @@ + interrupts = ; + }; + ++ wo_cpuboot: syscon@15194000 { ++ compatible = "mediatek,mt7986-wo-cpuboot", "syscon"; ++ reg = <0 0x15194000 0 0x1000>; ++ }; ++ + eth: ethernet@15100000 { + compatible = "mediatek,mt7986-eth"; + reg = <0 0x15100000 0 0x80000>; diff --git a/target/linux/mediatek/patches-6.1/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch b/target/linux/mediatek/patches-6.1/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch new file mode 100644 index 00000000000..9de4ffa433e --- /dev/null +++ b/target/linux/mediatek/patches-6.1/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch @@ -0,0 +1,89 @@ +From f292d1bf83ec160bef2532b58aa08f5b71041923 Mon Sep 17 00:00:00 2001 +Message-Id: +In-Reply-To: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org> +References: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org> +From: Lorenzo Bianconi +Date: Sat, 11 Mar 2023 18:13:04 +0100 +Subject: [PATCH net-next 2/2] net: ethernet: mtk_wed: move cpuboot in a + dedicated dts node + +Since the cpuboot memory region is not part of the RAM SoC, move cpuboot +in a deidicated syscon node. +This patch helps to keep backward-compatibility with older version of +uboot codebase where we have a limit of 8 reserved-memory dts child +nodes. +Keep backward-compatibility with older dts version where cpuboot was +defined as reserved-memory child node. + +Signed-off-by: Lorenzo Bianconi +--- + drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 34 +++++++++++++++++---- + drivers/net/ethernet/mediatek/mtk_wed_wo.h | 3 +- + 2 files changed, 30 insertions(+), 7 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c ++++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c +@@ -18,12 +18,23 @@ + + static u32 wo_r32(struct mtk_wed_wo *wo, u32 reg) + { +- return readl(wo->boot.addr + reg); ++ u32 val; ++ ++ if (!wo->boot_regmap) ++ return readl(wo->boot.addr + reg); ++ ++ if (regmap_read(wo->boot_regmap, reg, &val)) ++ val = ~0; ++ ++ return val; + } + + static void wo_w32(struct mtk_wed_wo *wo, u32 reg, u32 val) + { +- writel(val, wo->boot.addr + reg); ++ if (wo->boot_regmap) ++ regmap_write(wo->boot_regmap, reg, val); ++ else ++ writel(val, wo->boot.addr + reg); + } + + static struct sk_buff * +@@ -316,10 +327,21 @@ mtk_wed_mcu_load_firmware(struct mtk_wed + return ret; + } + +- wo->boot.name = "wo-boot"; +- ret = mtk_wed_get_reserved_memory_region(wo, &wo->boot); +- if (ret) +- return ret; ++ wo->boot_regmap = syscon_regmap_lookup_by_phandle(wo->hw->node, ++ "mediatek,wo-cpuboot"); ++ if (IS_ERR(wo->boot_regmap)) { ++ if (wo->boot_regmap != ERR_PTR(-ENODEV)) ++ return PTR_ERR(wo->boot_regmap); ++ ++ /* For backward compatibility, we need to check if cpu_boot ++ * is defined through reserved memory property. ++ */ ++ wo->boot_regmap = NULL; ++ wo->boot.name = "wo-boot"; ++ ret = mtk_wed_get_reserved_memory_region(wo, &wo->boot); ++ if (ret) ++ return ret; ++ } + + /* set dummy cr */ + wed_w32(wo->hw->wed_dev, MTK_WED_SCR0 + 4 * MTK_WED_DUMMY_CR_FWDL, +--- a/drivers/net/ethernet/mediatek/mtk_wed_wo.h ++++ b/drivers/net/ethernet/mediatek/mtk_wed_wo.h +@@ -228,7 +228,8 @@ struct mtk_wed_wo_queue { + + struct mtk_wed_wo { + struct mtk_wed_hw *hw; +- struct mtk_wed_wo_memory_region boot; ++ struct mtk_wed_wo_memory_region boot; /* backward compatibility */ ++ struct regmap *boot_regmap; + + struct mtk_wed_wo_queue q_tx; + struct mtk_wed_wo_queue q_rx; diff --git a/target/linux/mediatek/patches-6.1/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch b/target/linux/mediatek/patches-6.1/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch new file mode 100644 index 00000000000..7b6c5d1e277 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch @@ -0,0 +1,91 @@ +From f3565e6c2276411275e707a5442d3f69cc111273 Mon Sep 17 00:00:00 2001 +Message-Id: +From: Lorenzo Bianconi +Date: Sun, 12 Mar 2023 18:51:47 +0100 +Subject: [PATCH net-next 1/3] net: ethernet: mtk_wed: move ilm a dedicated dts + node + +Since the ilm memory region is not part of the RAM SoC, move ilm in a +deidicated syscon node. +This patch helps to keep backward-compatibility with older version of +uboot codebase where we have a limit of 8 reserved-memory dts child +nodes. +Keep backward-compatibility with older dts version where ilm was defined +as reserved-memory child node. + +Signed-off-by: Lorenzo Bianconi +--- + drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 55 ++++++++++++++++++--- + 1 file changed, 49 insertions(+), 6 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c ++++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c +@@ -300,6 +300,52 @@ next: + } + + static int ++mtk_wed_mcu_load_memory_regions(struct mtk_wed_wo *wo, ++ struct mtk_wed_wo_memory_region *region) ++{ ++ struct device_node *np; ++ int ret; ++ ++ /* firmware EMI memory region */ ++ ret = mtk_wed_get_reserved_memory_region(wo, ++ ®ion[MTK_WED_WO_REGION_EMI]); ++ if (ret) ++ return ret; ++ ++ /* firmware DATA memory region */ ++ ret = mtk_wed_get_reserved_memory_region(wo, ++ ®ion[MTK_WED_WO_REGION_DATA]); ++ if (ret) ++ return ret; ++ ++ np = of_parse_phandle(wo->hw->node, "mediatek,wo-ilm", 0); ++ if (np) { ++ struct mtk_wed_wo_memory_region *ilm_region; ++ struct resource res; ++ ++ ret = of_address_to_resource(np, 0, &res); ++ of_node_put(np); ++ ++ if (ret < 0) ++ return ret; ++ ++ ilm_region = ®ion[MTK_WED_WO_REGION_ILM]; ++ ilm_region->phy_addr = res.start; ++ ilm_region->size = resource_size(&res); ++ ilm_region->addr = devm_ioremap(wo->hw->dev, res.start, ++ resource_size(&res)); ++ ++ return IS_ERR(ilm_region->addr) ? PTR_ERR(ilm_region->addr) : 0; ++ } ++ ++ /* For backward compatibility, we need to check if ILM ++ * node is defined through reserved memory property. ++ */ ++ return mtk_wed_get_reserved_memory_region(wo, ++ ®ion[MTK_WED_WO_REGION_ILM]); ++} ++ ++static int + mtk_wed_mcu_load_firmware(struct mtk_wed_wo *wo) + { + static struct mtk_wed_wo_memory_region mem_region[] = { +@@ -320,12 +366,9 @@ mtk_wed_mcu_load_firmware(struct mtk_wed + u32 val, boot_cr; + int ret, i; + +- /* load firmware region metadata */ +- for (i = 0; i < ARRAY_SIZE(mem_region); i++) { +- ret = mtk_wed_get_reserved_memory_region(wo, &mem_region[i]); +- if (ret) +- return ret; +- } ++ ret = mtk_wed_mcu_load_memory_regions(wo, mem_region); ++ if (ret) ++ return ret; + + wo->boot_regmap = syscon_regmap_lookup_by_phandle(wo->hw->node, + "mediatek,wo-cpuboot"); diff --git a/target/linux/mediatek/patches-6.1/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch b/target/linux/mediatek/patches-6.1/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch new file mode 100644 index 00000000000..a455005504c --- /dev/null +++ b/target/linux/mediatek/patches-6.1/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch @@ -0,0 +1,57 @@ +From b74ba226be2c45091b93bd49192bdd6d2178729e Mon Sep 17 00:00:00 2001 +Message-Id: +In-Reply-To: +References: +From: Lorenzo Bianconi +Date: Mon, 13 Mar 2023 15:45:16 +0100 +Subject: [PATCH net-next 3/3] net: ethernet: mtk_wed: move dlm a dedicated dts + node + +Since the dlm memory region is not part of the RAM SoC, move dlm in a +deidicated syscon node. +This patch helps to keep backward-compatibility with older version of +uboot codebase where we have a limit of 8 reserved-memory dts child +nodes. +Keep backward-compatibility with older dts version where dlm was defined +as reserved-memory child node. + +Signed-off-by: Lorenzo Bianconi +--- + drivers/net/ethernet/mediatek/mtk_wed.c | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + +--- a/drivers/net/ethernet/mediatek/mtk_wed.c ++++ b/drivers/net/ethernet/mediatek/mtk_wed.c +@@ -813,6 +813,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device + struct device_node *np; + int index; + ++ np = of_parse_phandle(dev->hw->node, "mediatek,wo-dlm", 0); ++ if (np) { ++ struct resource res; ++ int ret; ++ ++ ret = of_address_to_resource(np, 0, &res); ++ of_node_put(np); ++ ++ if (ret < 0) ++ return ret; ++ ++ dev->rro.miod_phys = res.start; ++ goto out; ++ } ++ ++ /* For backward compatibility, we need to check if DLM ++ * node is defined through reserved memory property. ++ */ + index = of_property_match_string(dev->hw->node, "memory-region-names", + "wo-dlm"); + if (index < 0) +@@ -829,6 +847,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device + return -ENODEV; + + dev->rro.miod_phys = rmem->base; ++out: + dev->rro.fdbk_phys = MTK_WED_MIOD_COUNT + dev->rro.miod_phys; + + return mtk_wed_rro_ring_alloc(dev, &dev->rro.ring, diff --git a/target/linux/mediatek/patches-6.1/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch b/target/linux/mediatek/patches-6.1/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch new file mode 100644 index 00000000000..36fe9278372 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch @@ -0,0 +1,83 @@ +From 01561065af5bf1d2a4244896d897e3a1eafbcd46 Mon Sep 17 00:00:00 2001 +Message-Id: <01561065af5bf1d2a4244896d897e3a1eafbcd46.1678717704.git.lorenzo@kernel.org> +From: Lorenzo Bianconi +Date: Mon, 13 Mar 2023 15:10:56 +0100 +Subject: [PATCH net-next] arm64: dts: mt7986: move ilm in a dedicated node + +Since the ilm memory region is not part of the RAM SoC, move ilm in a +deidicated syscon node. +This patch helps to keep backward-compatibility with older version of +uboot codebase where we have a limit of 8 reserved-memory dts child +nodes. + +Signed-off-by: Lorenzo Bianconi +--- + arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 34 +++++++++++------------ + 1 file changed, 16 insertions(+), 18 deletions(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +@@ -97,16 +97,6 @@ + no-map; + }; + +- wo_ilm0: wo-ilm@151e0000 { +- reg = <0 0x151e0000 0 0x8000>; +- no-map; +- }; +- +- wo_ilm1: wo-ilm@151f0000 { +- reg = <0 0x151f0000 0 0x8000>; +- no-map; +- }; +- + wo_data: wo-data@4fd80000 { + reg = <0 0x4fd80000 0 0x240000>; + no-map; +@@ -511,11 +501,10 @@ + reg = <0 0x15010000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; +- memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, +- <&wo_data>; +- memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", +- "wo-data"; ++ memory-region = <&wo_emi0>, <&wo_dlm0>, <&wo_data>; ++ memory-region-names = "wo-emi", "wo-dlm", "wo-data"; + mediatek,wo-ccif = <&wo_ccif0>; ++ mediatek,wo-ilm = <&wo_ilm0>; + mediatek,wo-cpuboot = <&wo_cpuboot>; + }; + +@@ -525,11 +514,10 @@ + reg = <0 0x15011000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; +- memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>, +- <&wo_data>; +- memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", +- "wo-data"; ++ memory-region = <&wo_emi1>, <&wo_dlm1>, <&wo_data>; ++ memory-region-names = "wo-emi", "wo-dlm", "wo-data"; + mediatek,wo-ccif = <&wo_ccif1>; ++ mediatek,wo-ilm = <&wo_ilm1>; + mediatek,wo-cpuboot = <&wo_cpuboot>; + }; + +@@ -547,6 +535,16 @@ + interrupts = ; + }; + ++ wo_ilm0: syscon@151e0000 { ++ compatible = "mediatek,mt7986-wo-ilm", "syscon"; ++ reg = <0 0x151e0000 0 0x8000>; ++ }; ++ ++ wo_ilm1: syscon@151f0000 { ++ compatible = "mediatek,mt7986-wo-ilm", "syscon"; ++ reg = <0 0x151f0000 0 0x8000>; ++ }; ++ + wo_cpuboot: syscon@15194000 { + compatible = "mediatek,mt7986-wo-cpuboot", "syscon"; + reg = <0 0x15194000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.1/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch b/target/linux/mediatek/patches-6.1/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch new file mode 100644 index 00000000000..55f17286c60 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch @@ -0,0 +1,81 @@ +From 9f76be683a8ec498563c294bc1cc279468058302 Mon Sep 17 00:00:00 2001 +Message-Id: <9f76be683a8ec498563c294bc1cc279468058302.1678719283.git.lorenzo@kernel.org> +From: Lorenzo Bianconi +Date: Mon, 13 Mar 2023 15:53:30 +0100 +Subject: [PATCH net-next] arm64: dts: mt7986: move dlm in a dedicated node + +Since the dlm memory region is not part of the RAM SoC, move dlm in a +deidicated syscon node. +This patch helps to keep backward-compatibility with older version of +uboot codebase where we have a limit of 8 reserved-memory dts child +nodes. + +Signed-off-by: Lorenzo Bianconi +--- + arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 30 ++++++++++++----------- + 1 file changed, 16 insertions(+), 14 deletions(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +@@ -101,16 +101,6 @@ + reg = <0 0x4fd80000 0 0x240000>; + no-map; + }; +- +- wo_dlm0: wo-dlm@151e8000 { +- reg = <0 0x151e8000 0 0x2000>; +- no-map; +- }; +- +- wo_dlm1: wo-dlm@151f8000 { +- reg = <0 0x151f8000 0 0x2000>; +- no-map; +- }; + }; + + timer { +@@ -501,10 +491,11 @@ + reg = <0 0x15010000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; +- memory-region = <&wo_emi0>, <&wo_dlm0>, <&wo_data>; +- memory-region-names = "wo-emi", "wo-dlm", "wo-data"; ++ memory-region = <&wo_emi0>, <&wo_data>; ++ memory-region-names = "wo-emi", "wo-data"; + mediatek,wo-ccif = <&wo_ccif0>; + mediatek,wo-ilm = <&wo_ilm0>; ++ mediatek,wo-dlm = <&wo_dlm0>; + mediatek,wo-cpuboot = <&wo_cpuboot>; + }; + +@@ -514,10 +505,11 @@ + reg = <0 0x15011000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; +- memory-region = <&wo_emi1>, <&wo_dlm1>, <&wo_data>; +- memory-region-names = "wo-emi", "wo-dlm", "wo-data"; ++ memory-region = <&wo_emi1>, <&wo_data>; ++ memory-region-names = "wo-emi", "wo-data"; + mediatek,wo-ccif = <&wo_ccif1>; + mediatek,wo-ilm = <&wo_ilm1>; ++ mediatek,wo-dlm = <&wo_dlm1>; + mediatek,wo-cpuboot = <&wo_cpuboot>; + }; + +@@ -545,6 +537,16 @@ + reg = <0 0x151f0000 0 0x8000>; + }; + ++ wo_dlm0: syscon@151e8000 { ++ compatible = "mediatek,mt7986-wo-dlm", "syscon"; ++ reg = <0 0x151e8000 0 0x2000>; ++ }; ++ ++ wo_dlm1: syscon@151f8000 { ++ compatible = "mediatek,mt7986-wo-dlm", "syscon"; ++ reg = <0 0x151f8000 0 0x2000>; ++ }; ++ + wo_cpuboot: syscon@15194000 { + compatible = "mediatek,mt7986-wo-cpuboot", "syscon"; + reg = <0 0x15194000 0 0x1000>; From 659f4a13ddcb5b4f112a50d6a26b3aacf72d1a92 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Tue, 27 Jun 2023 02:15:55 +0200 Subject: [PATCH 29/53] mediatek: adapt files and patches for Linux 6.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With Linux 6.1 many of our downstream patches and out-of-tree files can be removed or at least replaced by backported upstream commits. Signed-off-by: Daniel Golle [fix CMDLINE_OVERRIDE for arm64] Signed-off-by: Bjørn Mork --- .../mt7986a-bananapi-bpi-r3-emmc.dtso | 29 - .../mt7986a-bananapi-bpi-r3-nand.dtso | 55 - .../mediatek/mt7986a-bananapi-bpi-r3-nor.dtso | 63 - .../mediatek/mt7986a-bananapi-bpi-r3-sd.dtso | 23 - .../dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 499 ------ .../arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 633 ------- .../arm64/boot/dts/mediatek/mt7986b-rfb.dts | 194 --- .../arch/arm64/boot/dts/mediatek/mt7986b.dtsi | 15 - .../drivers/clk/mediatek/clk-mt7981-apmixed.c | 102 -- .../drivers/clk/mediatek/clk-mt7981-eth.c | 139 -- .../clk/mediatek/clk-mt7981-infracfg.c | 235 --- .../clk/mediatek/clk-mt7981-topckgen.c | 450 ----- .../drivers/clk/mediatek/clk-mt7986-apmixed.c | 100 -- .../drivers/clk/mediatek/clk-mt7986-eth.c | 132 -- .../clk/mediatek/clk-mt7986-infracfg.c | 224 --- .../clk/mediatek/clk-mt7986-topckgen.c | 342 ---- .../drivers/clk/mediatek/clk-mt7988-apmixed.c | 12 +- .../drivers/clk/mediatek/clk-mt7988-eth.c | 222 +-- .../clk/mediatek/clk-mt7988-infracfg.c | 60 +- .../clk/mediatek/clk-mt7988-topckgen.c | 126 +- .../drivers/net/phy/mediatek-ge-soc.c | 1263 -------------- .../drivers/pinctrl/mediatek/pinctrl-mt7981.c | 1048 ----------- .../drivers/pinctrl/mediatek/pinctrl-mt7986.c | 1003 ----------- .../drivers/pinctrl/mediatek/pinctrl-mt7988.c | 35 +- .../dt-bindings/clock/mediatek,mt7981-clk.h | 215 --- .../include/dt-bindings/clock/mt7986-clk.h | 169 -- .../include/dt-bindings/reset/mt7986-resets.h | 55 - ...-overlays-to-built-from-.dtso-named-.patch | 44 + ...ek-mt7986-add-support-for-RX-Wireles.patch | 106 ++ ...s-mt7986-harmonize-device-node-order.patch | 166 ++ ...7986-add-crypto-related-device-nodes.patch | 68 + ...4-v6.2-arm64-dts-mt7986-add-i2c-node.patch | 37 + ...s-mediatek-mt7986-Add-SoC-compatible.patch | 61 + ...-mt7986-add-spi-related-device-nodes.patch | 157 ++ ...-mt7986-add-usb-related-device-nodes.patch | 127 ++ ...-mt7986-add-mmc-related-device-nodes.patch | 160 ++ ...mt7986-add-pcie-related-device-nodes.patch | 118 ++ ...6.3-arm64-dts-mt7986-add-Bananapi-R3.patch | 689 ++++++++ ...ropagate-chassis-type-where-possible.patch | 323 ++++ .../012-v6.5-arm64-dts-mt7986-add-PWM.patch | 38 + ...5-arm64-dts-mt7986-add-PWM-to-BPI-R3.patch | 43 + ...-set-Wifi-Leds-low-active-for-BPI-R3.patch | 27 + ...-use-size-of-reserved-partition-for-.patch | 46 + ...m64-dts-mt7986-add-thermal-and-efuse.patch | 80 + ...5-arm64-dts-mt7986-add-thermal-zones.patch | 51 + ...-add-pwm-fan-and-cooling-maps-to-BPI.patch | 64 + ...-increase-bl2-partition-on-NAND-of-B.patch | 41 + .../100-dts-update-mt7622-rfb1.patch | 38 +- .../101-dts-update-mt7629-rfb.patch | 2 +- .../patches-6.1/104-mt7622-add-snor-irq.patch | 2 +- .../105-dts-mt7622-enable-pstore.patch | 11 +- .../111-dts-fix-bpi64-console.patch | 2 +- .../112-dts-fix-bpi64-lan-names.patch | 4 +- .../113-dts-fix-bpi64-leds-and-buttons.patch | 45 +- .../114-dts-bpi64-disable-rtc.patch | 2 +- .../115-dts-bpi64-add-snand-support.patch | 2 +- ...-infrastructure-to-support-hardware-.patch | 214 --- ...ew-helper-to-retrieve-the-ECC-contex.patch | 31 - ...vide-a-helper-to-retrieve-a-pileline.patch | 73 - ...mem-Introduce-a-capability-structure.patch | 71 - ...ck-the-controller-extra-capabilities.patch | 51 - ...l-the-spi_mem_dtr_supports_op-helper.patch | 111 -- ...an-ecc-parameter-to-the-spi_mem_op-s.patch | 72 - ...lay-a-little-bit-the-dirmap-creation.patch | 50 - ...te-direct-mapping-descriptors-for-EC.patch | 98 -- ...nd-make-mtk_ecc.c-a-separated-module.patch | 1383 --------------- ...ver-for-MTK-SPI-NAND-Flash-Interface.patch | 1537 ----------------- ...-also-parse-nand-ecc-engine-if-avail.patch | 30 - ...dts-mediatek-add-mtk-snfi-for-mt7622.patch | 35 - .../130-dts-mt7629-add-snand-support.patch | 2 +- .../131-dts-mt7622-add-snand-support.patch | 2 +- ...dts-fix-wmac-support-for-mt7622-rfb1.patch | 4 +- ...s-mt7623-eip97-inside-secure-support.patch | 2 +- ...arm-dts-mt7623-add-musb-device-nodes.patch | 69 - ...80-dts-mt7622-bpi-r64-add-mt7531-irq.patch | 2 +- ...-dts-mediatek-mt7622-fix-GICv2-range.patch | 2 +- ...mt7622-specify-the-L2-cache-topology.patch | 132 -- ...2-specify-the-number-of-DMA-requests.patch | 122 -- ...-phy-phy-mtk-tphy-Add-hifsys-support.patch | 20 +- ...-mediatek-add-support-for-MT7986-SoC.patch | 26 - ...llow-configuring-uart-rx-tx-and-rts-.patch | 88 + ...k-Add-API-for-clock-resource-recycle.patch | 28 - ...-add-pull_type-attribute-for-mediate.patch | 100 ++ ...lk-mediatek-add-mt7986-clock-support.patch | 39 - ...-spi-mediatek-add-mt7986-spi-support.patch | 917 ---------- ...lk-mediatek-add-mt7981-clock-support.patch | 39 - ....3-pinctrl-add-mt7981-pinctrl-driver.patch | 1094 ++++++++++++ ...-mediatek-add-support-for-MT7981-SoC.patch | 26 - ...-add-missing-options-to-PINCTRL_MT79.patch | 30 + ...-gate-Propagate-struct-device-with-m.patch | 536 ++++++ ...mux-Propagate-struct-device-where-po.patch | 140 ++ ...-mtk-Propagate-struct-device-for-com.patch | 181 ++ ...-mux-Propagate-struct-device-for-mtk.patch | 103 ++ ...mediatek-clk-mtk-Add-dummy-clock-ops.patch | 74 + ...tch-to-mtk_clk_simple_probe-where-po.patch | 790 +++++++++ ...-clk-mtk-Extend-mtk_clk_simple_probe.patch | 189 ++ ...-mt7986-topckgen-Properly-keep-some-.patch | 97 ++ ...-mt7986-topckgen-Migrate-to-mtk_clk_.patch | 88 + ...986-apmixed-Use-PLL_AO-flag-to-set-c.patch | 38 + ...-clock-mediatek-add-mt7981-clock-IDs.patch | 237 +++ ...lk-mediatek-add-MT7981-clock-support.patch | 932 ++++++++++ ...-mediatek-add-support-for-MT7988-SoC.patch | 6 +- ...k-mediatek-Add-pcw-chg-shift-control.patch | 22 +- ...lk-mediatek-add-mt7988-clock-support.patch | 6 +- ...mediatek-add-support-for-MT7986-SoC.patch} | 29 +- ...d-Inline-Crypto-Engine-clock-control.patch | 57 + ...fix-two-spelling-mistakes-in-comment.patch | 36 + ...d-open-coding-by-using-mmc_op_tuning.patch | 39 + .../330-snand-mtk-bmt-support.patch | 6 +- .../331-mt7622-rfb1-enable-bmt.patch | 2 +- ...Add-support-for-the-Fidelix-FM35X1GA.patch | 14 +- ...-Cleanup-variables-and-error-handlin.patch | 166 -- ...ufreq-mediatek-Remove-unused-headers.patch | 25 - ...ediatek-Enable-clocks-and-regulators.patch | 117 -- ...diatek-Use-device-print-to-show-logs.patch | 161 -- ...freq-mediatek-Replace-old_-with-pre_.patch | 201 --- ...k-Record-previous-target-vproc-value.patch | 64 - ...ediatek-Make-sram-regulator-optional.patch | 30 - ...-Fix-NULL-pointer-dereference-in-med.patch | 32 - ...-Move-voltage-limits-to-platform-dat.patch | 227 --- ...-Refine-mtk_cpufreq_voltage_tracking.patch | 255 --- ...ediatek-Add-opp-notification-support.patch | 184 -- ...-Fix-potential-deadlock-problem-in-m.patch | 43 - ...freq-mediatek-Link-CCI-device-to-CPU.patch | 188 -- ...freq-mediatek-Add-support-for-MT8186.patch | 42 - ...-Handle-sram-regulator-probe-deferra.patch | 35 - ...-fix-error-return-code-in-mtk_cpu_dv.patch | 29 - ...mediatek-fix-passing-zero-to-PTR_ERR.patch | 47 - ...-fix-KP-caused-by-handler-usage-afte.patch | 149 -- ...-raise-proc-sram-max-voltage-for-MT8.patch | 55 - ...-Raise-proc-and-sram-max-voltage-for.patch | 58 - ...05-v6.2-mt7986-trng-add-rng-support.patch} | 8 +- .../patches-6.1/410-bt-mtk-serial-fix.patch | 10 +- ...or-add-support-for-Winbond-W25Q512JV.patch | 28 - ...xx-Move-chip_config-to-driver-s-priv.patch | 16 +- ...-Add-support-for-dynamic-calibration.patch | 12 +- ...ers-spi-mem-Add-spi-calibration-hook.patch | 2 +- ...xx-Add-controller-s-calibration-para.patch | 8 +- ...and-Add-calibration-support-for-spin.patch | 4 +- ...nor-Add-calibration-support-for-spi-.patch | 8 +- .../500-gsw-rtl8367s-mt7622-support.patch | 4 +- ...ek-Split-PCIe-node-for-MT2712-and-MT.patch | 332 ---- ...ert-PERST-for-100ms-for-power-and-cl.patch | 2 +- ...dts-mediatek-Update-mt7629-PCIe-node.patch | 203 --- ...diatek-fix-clearing-interrupt-status.patch | 2 +- ...pers-to-extract-clause-45-regad-and-.patch | 53 - ..._eth_soc-implement-Clause-45-MDIO-ac.patch | 128 -- ...er-for-MediaTek-SoC-built-in-GE-PHYs.patch | 82 - ...er-for-MediaTek-SoC-built-in-GE-PHYs.patch | 1204 +++++++++++++ ...et-phy-hack-mxl-gpy-disable-sgmii-an.patch | 166 -- ...-ge-soc-initialize-MT7988-PHY-LEDs-d.patch | 213 +++ ...-don-t-use-SGMII-AN-if-using-phylink.patch | 63 + ...hy-add-driver-for-MediaTek-2.5G-PHY.patch} | 6 +- ...k-tphy-Add-PCIe-2-lane-efuse-support.patch | 225 --- ...-add-auto-load-valid-check-mechanism.patch | 149 -- .../804-pwm-add-mt7986-support.patch | 6 +- ...mtk-use-function-pointer-for-raw_to_.patch | 2 +- ...ek-add-support-for-MT7986-and-MT7981.patch | 2 +- ...-pwm-mediatek-Add-support-for-MT7981.patch | 122 -- ...dings-pinctrl-mt8195-add-rsel-define.patch | 33 - ...-moore-check-if-pin_desc-is-valid-be.patch | 93 - ...inctrl-mediatek-support-rsel-feature.patch | 457 ----- ...-add-a-check-for-error-in-mtk_pincon.patch | 31 - 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...g-mtk-add-disable_wdt_extrst-support.patch | 50 - ...t-mt7986-Add-toprgu-reset-controller.patch | 49 - ...3-change-driver-name-to-mtk-pcie-gen.patch | 20 - .../930-spi-mt65xx-enable-sel-clk.patch | 29 +- ...tk_wed-move-dlm-a-dedicated-dts-node.patch | 4 +- 186 files changed, 9042 insertions(+), 19597 deletions(-) delete mode 100644 target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso delete mode 100644 target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso delete mode 100644 target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso delete mode 100644 target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso delete mode 100644 target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts delete mode 100644 target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a.dtsi delete mode 100644 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target/linux/mediatek/patches-6.1/004-v6.2-arm64-dts-mt7986-add-i2c-node.patch create mode 100644 target/linux/mediatek/patches-6.1/005-v6.2-arm64-dts-mediatek-mt7986-Add-SoC-compatible.patch create mode 100644 target/linux/mediatek/patches-6.1/006-v6.2-arm64-dts-mt7986-add-spi-related-device-nodes.patch create mode 100644 target/linux/mediatek/patches-6.1/007-v6.3-arm64-dts-mt7986-add-usb-related-device-nodes.patch create mode 100644 target/linux/mediatek/patches-6.1/008-v6.3-arm64-dts-mt7986-add-mmc-related-device-nodes.patch create mode 100644 target/linux/mediatek/patches-6.1/009-v6.3-arm64-dts-mt7986-add-pcie-related-device-nodes.patch create mode 100644 target/linux/mediatek/patches-6.1/010-v6.3-arm64-dts-mt7986-add-Bananapi-R3.patch create mode 100644 target/linux/mediatek/patches-6.1/011-v6.5-arm64-mediatek-Propagate-chassis-type-where-possible.patch create mode 100644 target/linux/mediatek/patches-6.1/012-v6.5-arm64-dts-mt7986-add-PWM.patch create mode 100644 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100644 target/linux/mediatek/patches-6.1/220-v6.3-clk-mediatek-clk-gate-Propagate-struct-device-with-m.patch create mode 100644 target/linux/mediatek/patches-6.1/221-v6.3-clk-mediatek-cpumux-Propagate-struct-device-where-po.patch create mode 100644 target/linux/mediatek/patches-6.1/222-v6.3-clk-mediatek-clk-mtk-Propagate-struct-device-for-com.patch create mode 100644 target/linux/mediatek/patches-6.1/223-v6.3-clk-mediatek-clk-mux-Propagate-struct-device-for-mtk.patch create mode 100644 target/linux/mediatek/patches-6.1/224-v6.3-clk-mediatek-clk-mtk-Add-dummy-clock-ops.patch create mode 100644 target/linux/mediatek/patches-6.1/225-v6.3-clk-mediatek-Switch-to-mtk_clk_simple_probe-where-po.patch create mode 100644 target/linux/mediatek/patches-6.1/226-v6.3-clk-mediatek-clk-mtk-Extend-mtk_clk_simple_probe.patch create mode 100644 target/linux/mediatek/patches-6.1/227-v6.3-clk-mediatek-clk-mt7986-topckgen-Properly-keep-some-.patch create mode 100644 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target/linux/mediatek/patches-6.1/350-01-cpufreq-mediatek-Cleanup-variables-and-error-handlin.patch delete mode 100644 target/linux/mediatek/patches-6.1/350-02-cpufreq-mediatek-Remove-unused-headers.patch delete mode 100644 target/linux/mediatek/patches-6.1/350-03-cpufreq-mediatek-Enable-clocks-and-regulators.patch delete mode 100644 target/linux/mediatek/patches-6.1/350-04-cpufreq-mediatek-Use-device-print-to-show-logs.patch delete mode 100644 target/linux/mediatek/patches-6.1/350-05-cpufreq-mediatek-Replace-old_-with-pre_.patch delete mode 100644 target/linux/mediatek/patches-6.1/350-06-cpufreq-mediatek-Record-previous-target-vproc-value.patch delete mode 100644 target/linux/mediatek/patches-6.1/350-07-cpufreq-mediatek-Make-sram-regulator-optional.patch delete mode 100644 target/linux/mediatek/patches-6.1/350-08-cpufreq-mediatek-Fix-NULL-pointer-dereference-in-med.patch delete mode 100644 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target/linux/mediatek/patches-6.1/825-v6.1-pinctrl-mediatek-Export-debounce-time-tables.patch delete mode 100644 target/linux/mediatek/patches-6.1/830-v5.18-regulator-Add-bindings-for-Richtek-RT5190A-PMIC.patch delete mode 100644 target/linux/mediatek/patches-6.1/831-v5.18-regulator-rt5190a-Add-support-for-Richtek-RT5190A-PM.patch delete mode 100644 target/linux/mediatek/patches-6.1/840-v5.16-i2c-mediatek-Reset-the-handshake-signal-between-i2c-.patch delete mode 100644 target/linux/mediatek/patches-6.1/841-v5.16-i2c-mediatek-Dump-i2c-dma-register-when-a-timeout-oc.patch delete mode 100644 target/linux/mediatek/patches-6.1/842-v5.18-i2c-mediatek-Add-i2c-compatible-for-Mediatek-MT8186.patch delete mode 100644 target/linux/mediatek/patches-6.1/843-v5.18-i2c-mediatek-modify-bus-speed-calculation-formula.patch delete mode 100644 target/linux/mediatek/patches-6.1/844-v5.18-i2c-mediatek-remove-redundant-null-check.patch delete mode 100644 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target/linux/mediatek/patches-6.1/922-v6.1-PCI-mediatek-gen3-change-driver-name-to-mtk-pcie-gen.patch diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso deleted file mode 100644 index 779dc6782bb..00000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2021 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -/ { - compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; - - fragment@0 { - target-path = "/soc/mmc@11230000"; - __overlay__ { - bus-width = <8>; - max-frequency = <200000000>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - hs400-ds-delay = <0x14014>; - non-removable; - no-sd; - no-sdio; - status = "okay"; - }; - }; -}; - diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso deleted file mode 100644 index 15ee8c568f3..00000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso +++ /dev/null @@ -1,55 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -/* - * Authors: Daniel Golle - * Frank Wunderlich - */ - -/dts-v1/; -/plugin/; - -/ { - compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; - - fragment@0 { - target-path = "/soc/spi@1100a000"; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - spi_nand: spi_nand@0 { - compatible = "spi-nand"; - reg = <0>; - spi-max-frequency = <10000000>; - spi-tx-buswidth = <4>; - spi-rx-buswidth = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bl2"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@80000 { - label = "reserved"; - reg = <0x80000 0x300000>; - }; - - partition@380000 { - label = "fip"; - reg = <0x380000 0x200000>; - read-only; - }; - - partition@580000 { - label = "ubi"; - reg = <0x580000 0x7a80000>; - }; - }; - }; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso deleted file mode 100644 index e48881be4ed..00000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -/* - * Authors: Daniel Golle - * Frank Wunderlich - */ - -/dts-v1/; -/plugin/; - -/ { - compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; - - fragment@0 { - target-path = "/soc/spi@1100a000"; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bl2"; - reg = <0x0 0x40000>; - read-only; - }; - - partition@40000 { - label = "u-boot-env"; - reg = <0x40000 0x40000>; - }; - - partition@80000 { - label = "reserved2"; - reg = <0x80000 0x80000>; - }; - - partition@100000 { - label = "fip"; - reg = <0x100000 0x80000>; - read-only; - }; - - partition@180000 { - label = "recovery"; - reg = <0x180000 0xa80000>; - }; - - partition@c00000 { - label = "fit"; - reg = <0xc00000 0x1400000>; - }; - }; - }; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso deleted file mode 100644 index f623bce075c..00000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2021 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -/ { - compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; - - fragment@0 { - target-path = "/soc/mmc@11230000"; - __overlay__ { - bus-width = <4>; - max-frequency = <52000000>; - cap-sd-highspeed; - status = "okay"; - }; - }; -}; - diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts deleted file mode 100644 index af4a4309bda..00000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts +++ /dev/null @@ -1,499 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2021 MediaTek Inc. - * Authors: Sam.Shih - * Frank Wunderlich - * Daniel Golle - */ - -/dts-v1/; -#include -#include -#include -#include - -#include "mt7986a.dtsi" - -/ { - model = "Bananapi BPI-R3"; - chassis-type = "embedded"; - compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; - - aliases { - serial0 = &uart0; - ethernet0 = &gmac0; - ethernet1 = &gmac1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - dcin: regulator-12vd { - compatible = "regulator-fixed"; - regulator-name = "12vd"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-boot-on; - regulator-always-on; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - /* cooling level (0, 1, 2) - pwm inverted */ - cooling-levels = <255 96 0>; - pwms = <&pwm 0 10000 0>; - status = "okay"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - reset-key { - label = "reset"; - linux,code = ; - gpios = <&pio 9 GPIO_ACTIVE_LOW>; - }; - - wps-key { - label = "wps"; - linux,code = ; - gpios = <&pio 10 GPIO_ACTIVE_LOW>; - }; - }; - - /* i2c of the left SFP cage (wan) */ - i2c_sfp1: i2c-gpio-0 { - compatible = "i2c-gpio"; - sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - /* i2c of the right SFP cage (lan) */ - i2c_sfp2: i2c-gpio-1 { - compatible = "i2c-gpio"; - sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - leds { - compatible = "gpio-leds"; - - green_led: led-0 { - color = ; - function = LED_FUNCTION_POWER; - gpios = <&pio 69 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - blue_led: led-1 { - color = ; - function = LED_FUNCTION_STATUS; - gpios = <&pio 86 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1.8vd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - vin-supply = <&dcin>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3.3vd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - vin-supply = <&dcin>; - }; - - /* left SFP cage (wan) */ - sfp1: sfp-1 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp1>; - los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>; - tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>; - tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; - }; - - /* right SFP cage (lan) */ - sfp2: sfp-2 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp2>; - los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>; - tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>; - tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>; - }; -}; - -&cpu_thermal { - cooling-maps { - cpu-active-high { - /* active: set fan to cooling level 2 */ - cooling-device = <&fan 2 2>; - trip = <&cpu_trip_active_high>; - }; - - cpu-active-low { - /* active: set fan to cooling level 1 */ - cooling-device = <&fan 1 1>; - trip = <&cpu_trip_active_low>; - }; - - cpu-passive { - /* passive: set fan to cooling level 0 */ - cooling-device = <&fan 0 0>; - trip = <&cpu_trip_passive>; - }; - }; -}; - -&crypto { - status = "okay"; -}; - -ð { - status = "okay"; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - - gmac1: mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "2500base-x"; - sfp = <&sfp1>; - managed = "in-band-status"; - }; - - mdio: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - }; -}; - -&mdio { - switch: switch@31 { - compatible = "mediatek,mt7531"; - reg = <31>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&pio>; - interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; - reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; - }; -}; - -&mmc0 { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_default>; - pinctrl-1 = <&mmc0_pins_uhs>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c_pins>; - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pins>; - status = "okay"; -}; - -&pcie_phy { - status = "okay"; -}; - -&pio { - i2c_pins: i2c-pins { - mux { - function = "i2c"; - groups = "i2c"; - }; - }; - - mmc0_pins_default: mmc0-pins { - mux { - function = "emmc"; - groups = "emmc_51"; - }; - conf-cmd-dat { - pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", - "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", - "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; - input-enable; - drive-strength = <4>; - bias-pull-up = ; /* pull-up 10K */ - }; - conf-clk { - pins = "EMMC_CK"; - drive-strength = <6>; - bias-pull-down = ; /* pull-down 50K */ - }; - conf-ds { - pins = "EMMC_DSL"; - bias-pull-down = ; /* pull-down 50K */ - }; - conf-rst { - pins = "EMMC_RSTB"; - drive-strength = <4>; - bias-pull-up = ; /* pull-up 10K */ - }; - }; - - mmc0_pins_uhs: mmc0-uhs-pins { - mux { - function = "emmc"; - groups = "emmc_51"; - }; - conf-cmd-dat { - pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", - "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", - "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; - input-enable; - drive-strength = <4>; - bias-pull-up = ; /* pull-up 10K */ - }; - conf-clk { - pins = "EMMC_CK"; - drive-strength = <6>; - bias-pull-down = ; /* pull-down 50K */ - }; - conf-ds { - pins = "EMMC_DSL"; - bias-pull-down = ; /* pull-down 50K */ - }; - conf-rst { - pins = "EMMC_RSTB"; - drive-strength = <4>; - bias-pull-up = ; /* pull-up 10K */ - }; - }; - - pcie_pins: pcie-pins { - mux { - function = "pcie"; - groups = "pcie_clk", "pcie_pereset"; - }; - }; - - pwm_pins: pwm-pins { - mux { - function = "pwm"; - groups = "pwm0", "pwm1_0"; - }; - }; - - spi_flash_pins: spi-flash-pins { - mux { - function = "spi"; - groups = "spi0", "spi0_wp_hold"; - }; - }; - - spic_pins: spic-pins { - mux { - function = "spi"; - groups = "spi1_0"; - }; - }; - - uart1_pins: uart1-pins { - mux { - function = "uart"; - groups = "uart1_rx_tx"; - }; - }; - - uart2_pins: uart2-pins { - mux { - function = "uart"; - groups = "uart2_0_rx_tx"; - }; - }; - - wf_2g_5g_pins: wf-2g-5g-pins { - mux { - function = "wifi"; - groups = "wf_2g", "wf_5g"; - }; - conf { - pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", - "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", - "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", - "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", - "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", - "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", - "WF1_TOP_CLK", "WF1_TOP_DATA"; - drive-strength = <4>; - }; - }; - - wf_dbdc_pins: wf-dbdc-pins { - mux { - function = "wifi"; - groups = "wf_dbdc"; - }; - conf { - pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", - "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", - "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", - "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", - "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", - "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", - "WF1_TOP_CLK", "WF1_TOP_DATA"; - drive-strength = <4>; - }; - }; - - wf_led_pins: wf-led-pins { - mux { - function = "led"; - groups = "wifi_led"; - }; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm_pins>; - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi_flash_pins>; - status = "okay"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spic_pins>; - status = "okay"; -}; - -&ssusb { - status = "okay"; -}; - -&switch { - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "wan"; - }; - - port@1 { - reg = <1>; - label = "lan0"; - }; - - port@2 { - reg = <2>; - label = "lan1"; - }; - - port@3 { - reg = <3>; - label = "lan2"; - }; - - port@4 { - reg = <4>; - label = "lan3"; - }; - - port5: port@5 { - reg = <5>; - label = "lan4"; - phy-mode = "2500base-x"; - sfp = <&sfp2>; - managed = "in-band-status"; - }; - - port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&gmac0>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - }; -}; - -&trng { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; -}; - -&usb_phy { - status = "okay"; -}; - -&watchdog { - status = "okay"; -}; - -&wifi { - status = "okay"; - pinctrl-names = "default", "dbdc"; - pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>; - pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>; - - led { - led-active-low; - }; -}; - diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a.dtsi deleted file mode 100644 index 68539ea788d..00000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ /dev/null @@ -1,633 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2021 MediaTek Inc. - * Author: Sam.Shih - */ - -#include -#include -#include -#include -#include - -/ { - compatible = "mediatek,mt7986a"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - clk40m: oscillator-40m { - compatible = "fixed-clock"; - clock-frequency = <40000000>; - #clock-cells = <0>; - clock-output-names = "clkxtal"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x0>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x1>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x2>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - enable-method = "psci"; - compatible = "arm,cortex-a53"; - reg = <0x3>; - #cooling-cells = <2>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@43000000 { - reg = <0 0x43000000 0 0x30000>; - no-map; - }; - - wmcpu_emi: wmcpu-reserved@4fc00000 { - no-map; - reg = <0 0x4fc00000 0 0x00100000>; - }; - - wo_emi0: wo-emi@4fd00000 { - reg = <0 0x4fd00000 0 0x40000>; - no-map; - }; - - wo_emi1: wo-emi@4fd40000 { - reg = <0 0x4fd40000 0 0x40000>; - no-map; - }; - - wo_ilm0: wo-ilm@151e0000 { - reg = <0 0x151e0000 0 0x8000>; - no-map; - }; - - wo_ilm1: wo-ilm@151f0000 { - reg = <0 0x151f0000 0 0x8000>; - no-map; - }; - - wo_data: wo-data@4fd80000 { - reg = <0 0x4fd80000 0 0x240000>; - no-map; - }; - - wo_dlm0: wo-dlm@151e8000 { - reg = <0 0x151e8000 0 0x2000>; - no-map; - }; - - wo_dlm1: wo-dlm@151f8000 { - reg = <0 0x151f8000 0 0x2000>; - no-map; - }; - - wo_boot: wo-boot@15194000 { - reg = <0 0x15194000 0 0x1000>; - no-map; - }; - - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - ranges; - - gic: interrupt-controller@c000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - interrupt-controller; - reg = <0 0x0c000000 0 0x10000>, /* GICD */ - <0 0x0c080000 0 0x80000>, /* GICR */ - <0 0x0c400000 0 0x2000>, /* GICC */ - <0 0x0c410000 0 0x1000>, /* GICH */ - <0 0x0c420000 0 0x2000>; /* GICV */ - interrupts = ; - }; - - infracfg: infracfg@10001000 { - compatible = "mediatek,mt7986-infracfg", "syscon"; - reg = <0 0x10001000 0 0x1000>; - #clock-cells = <1>; - }; - - wed_pcie: wed-pcie@10003000 { - compatible = "mediatek,mt7986-wed-pcie", - "syscon"; - reg = <0 0x10003000 0 0x10>; - }; - - topckgen: topckgen@1001b000 { - compatible = "mediatek,mt7986-topckgen", "syscon"; - reg = <0 0x1001B000 0 0x1000>; - #clock-cells = <1>; - }; - - watchdog: watchdog@1001c000 { - compatible = "mediatek,mt7986-wdt"; - reg = <0 0x1001c000 0 0x1000>; - interrupts = ; - #reset-cells = <1>; - status = "disabled"; - }; - - apmixedsys: apmixedsys@1001e000 { - compatible = "mediatek,mt7986-apmixedsys"; - reg = <0 0x1001E000 0 0x1000>; - #clock-cells = <1>; - }; - - pio: pinctrl@1001f000 { - compatible = "mediatek,mt7986a-pinctrl"; - reg = <0 0x1001f000 0 0x1000>, - <0 0x11c30000 0 0x1000>, - <0 0x11c40000 0 0x1000>, - <0 0x11e20000 0 0x1000>, - <0 0x11e30000 0 0x1000>, - <0 0x11f00000 0 0x1000>, - <0 0x11f10000 0 0x1000>, - <0 0x1000b000 0 0x1000>; - reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt", - "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pio 0 0 100>; - interrupt-controller; - interrupts = ; - interrupt-parent = <&gic>; - #interrupt-cells = <2>; - }; - - sgmiisys0: syscon@10060000 { - compatible = "mediatek,mt7986-sgmiisys_0", - "syscon"; - reg = <0 0x10060000 0 0x1000>; - #clock-cells = <1>; - }; - - sgmiisys1: syscon@10070000 { - compatible = "mediatek,mt7986-sgmiisys_1", - "syscon"; - reg = <0 0x10070000 0 0x1000>; - #clock-cells = <1>; - }; - - trng: rng@1020f000 { - compatible = "mediatek,mt7986-rng", - "mediatek,mt7623-rng"; - reg = <0 0x1020f000 0 0x100>; - clocks = <&infracfg CLK_INFRA_TRNG_CK>; - clock-names = "rng"; - status = "disabled"; - }; - - crypto: crypto@10320000 { - compatible = "inside-secure,safexcel-eip97"; - reg = <0 0x10320000 0 0x40000>; - interrupts = , - , - , - ; - interrupt-names = "ring0", "ring1", "ring2", "ring3"; - clocks = <&infracfg CLK_INFRA_EIP97_CK>; - clock-names = "infra_eip97_ck"; - assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>; - assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>; - status = "disabled"; - }; - - pwm: pwm@10048000 { - compatible = "mediatek,mt7986-pwm"; - reg = <0 0x10048000 0 0x1000>; - #clock-cells = <1>; - #pwm-cells = <2>; - interrupts = ; - clocks = <&topckgen CLK_TOP_PWM_SEL>, - <&infracfg CLK_INFRA_PWM_STA>, - <&infracfg CLK_INFRA_PWM1_CK>, - <&infracfg CLK_INFRA_PWM2_CK>; - clock-names = "top", "main", "pwm1", "pwm2"; - status = "disabled"; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt7986-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11002000 0 0x400>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_UART0_SEL>, - <&infracfg CLK_INFRA_UART0_CK>; - clock-names = "baud", "bus"; - assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_UART0_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, - <&topckgen CLK_TOP_UART_SEL>; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt7986-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11003000 0 0x400>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_UART1_SEL>, - <&infracfg CLK_INFRA_UART1_CK>; - clock-names = "baud", "bus"; - assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>; - status = "disabled"; - }; - - uart2: serial@11004000 { - compatible = "mediatek,mt7986-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11004000 0 0x400>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_UART2_SEL>, - <&infracfg CLK_INFRA_UART2_CK>; - clock-names = "baud", "bus"; - assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>; - status = "disabled"; - }; - - i2c0: i2c@11008000 { - compatible = "mediatek,mt7986-i2c"; - reg = <0 0x11008000 0 0x90>, - <0 0x10217080 0 0x80>; - interrupts = ; - clock-div = <5>; - clocks = <&infracfg CLK_INFRA_I2C0_CK>, - <&infracfg CLK_INFRA_AP_DMA_CK>; - clock-names = "main", "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@1100a000 { - compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x1100a000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_MPLL_D2>, - <&topckgen CLK_TOP_SPI_SEL>, - <&infracfg CLK_INFRA_SPI0_CK>, - <&infracfg CLK_INFRA_SPI0_HCK_CK>; - clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; - status = "disabled"; - }; - - spi1: spi@1100b000 { - compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x1100b000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_MPLL_D2>, - <&topckgen CLK_TOP_SPIM_MST_SEL>, - <&infracfg CLK_INFRA_SPI1_CK>, - <&infracfg CLK_INFRA_SPI1_HCK_CK>; - clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; - status = "disabled"; - }; - - auxadc: adc@1100d000 { - compatible = "mediatek,mt7986-auxadc"; - reg = <0 0x1100d000 0 0x1000>; - clocks = <&infracfg CLK_INFRA_ADC_26M_CK>; - clock-names = "main"; - #io-channel-cells = <1>; - status = "disabled"; - }; - - ssusb: usb@11200000 { - compatible = "mediatek,mt7986-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x11200000 0 0x2e00>, - <0 0x11203e00 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>, - <&infracfg CLK_INFRA_IUSB_CK>, - <&infracfg CLK_INFRA_IUSB_133_CK>, - <&infracfg CLK_INFRA_IUSB_66M_CK>, - <&topckgen CLK_TOP_U2U3_XHCI_SEL>; - clock-names = "sys_ck", - "ref_ck", - "mcu_ck", - "dma_ck", - "xhci_ck"; - phys = <&u2port0 PHY_TYPE_USB2>, - <&u3port0 PHY_TYPE_USB3>, - <&u2port1 PHY_TYPE_USB2>; - status = "disabled"; - }; - - mmc0: mmc@11230000 { - compatible = "mediatek,mt7986-mmc"; - reg = <0 0x11230000 0 0x1000>, - <0 0x11c20000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>, - <&infracfg CLK_INFRA_MSDC_HCK_CK>, - <&infracfg CLK_INFRA_MSDC_CK>, - <&infracfg CLK_INFRA_MSDC_133M_CK>, - <&infracfg CLK_INFRA_MSDC_66M_CK>; - clock-names = "source", "hclk", "source_cg", "bus_clk", - "sys_cg"; - status = "disabled"; - }; - - thermal: thermal@1100c800 { - #thermal-sensor-cells = <1>; - compatible = "mediatek,mt7986-thermal"; - reg = <0 0x1100c800 0 0x800>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_THERM_CK>, - <&infracfg CLK_INFRA_ADC_26M_CK>, - <&infracfg CLK_INFRA_ADC_FRC_CK>; - clock-names = "therm", "auxadc", "adc_32k"; - mediatek,auxadc = <&auxadc>; - mediatek,apmixedsys = <&apmixedsys>; - nvmem-cells = <&thermal_calibration>; - nvmem-cell-names = "calibration-data"; - }; - - pcie: pcie@11280000 { - compatible = "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - reg = <0x00 0x11280000 0x00 0x4000>; - reg-names = "pcie-mac"; - interrupts = ; - bus-range = <0x00 0xff>; - ranges = <0x82000000 0x00 0x20000000 0x00 - 0x20000000 0x00 0x10000000>; - clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, - <&infracfg CLK_INFRA_IPCIE_CK>, - <&infracfg CLK_INFRA_IPCIER_CK>, - <&infracfg CLK_INFRA_IPCIEB_CK>; - clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; - status = "disabled"; - - phys = <&pcie_port PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &pcie_intc 0>, - <0 0 0 2 &pcie_intc 1>, - <0 0 0 3 &pcie_intc 2>, - <0 0 0 4 &pcie_intc 3>; - pcie_intc: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; - - pcie_phy: t-phy@11c00000 { - compatible = "mediatek,mt7986-tphy", - "mediatek,generic-tphy-v2"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - pcie_port: pcie-phy@11c00000 { - reg = <0 0x11c00000 0 0x20000>; - clocks = <&clk40m>; - clock-names = "ref"; - #phy-cells = <1>; - }; - }; - - efuse: efuse@11d00000 { - compatible = "mediatek,mt7986-efuse", "mediatek,efuse"; - reg = <0 0x11d00000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - thermal_calibration: calib@274 { - reg = <0x274 0xc>; - }; - }; - - usb_phy: t-phy@11e10000 { - compatible = "mediatek,mt7986-tphy", - "mediatek,generic-tphy-v2"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x11e10000 0x1700>; - status = "disabled"; - - u2port0: usb-phy@0 { - reg = <0x0 0x700>; - clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>, - <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>; - clock-names = "ref", "da_ref"; - #phy-cells = <1>; - }; - - u3port0: usb-phy@700 { - reg = <0x700 0x900>; - clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>; - clock-names = "ref"; - #phy-cells = <1>; - }; - - u2port1: usb-phy@1000 { - reg = <0x1000 0x700>; - clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>, - <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>; - clock-names = "ref", "da_ref"; - #phy-cells = <1>; - }; - }; - - ethsys: syscon@15000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mediatek,mt7986-ethsys", - "syscon"; - reg = <0 0x15000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - wed0: wed@15010000 { - compatible = "mediatek,mt7986-wed", - "syscon"; - reg = <0 0x15010000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, - <&wo_data>, <&wo_boot>; - memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", - "wo-data", "wo-boot"; - mediatek,wo-ccif = <&wo_ccif0>; - }; - - wed1: wed@15011000 { - compatible = "mediatek,mt7986-wed", - "syscon"; - reg = <0 0x15011000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>, - <&wo_data>, <&wo_boot>; - memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", - "wo-data", "wo-boot"; - mediatek,wo-ccif = <&wo_ccif1>; - }; - - wo_ccif0: syscon@151a5000 { - compatible = "mediatek,mt7986-wo-ccif", "syscon"; - reg = <0 0x151a5000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - }; - - wo_ccif1: syscon@151ad000 { - compatible = "mediatek,mt7986-wo-ccif", "syscon"; - reg = <0 0x151ad000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - }; - - eth: ethernet@15100000 { - compatible = "mediatek,mt7986-eth"; - reg = <0 0x15100000 0 0x80000>; - interrupts = , - , - , - ; - clocks = <ðsys CLK_ETH_FE_EN>, - <ðsys CLK_ETH_GP2_EN>, - <ðsys CLK_ETH_GP1_EN>, - <ðsys CLK_ETH_WOCPU1_EN>, - <ðsys CLK_ETH_WOCPU0_EN>, - <&sgmiisys0 CLK_SGMII0_TX250M_EN>, - <&sgmiisys0 CLK_SGMII0_RX250M_EN>, - <&sgmiisys0 CLK_SGMII0_CDR_REF>, - <&sgmiisys0 CLK_SGMII0_CDR_FB>, - <&sgmiisys1 CLK_SGMII1_TX250M_EN>, - <&sgmiisys1 CLK_SGMII1_RX250M_EN>, - <&sgmiisys1 CLK_SGMII1_CDR_REF>, - <&sgmiisys1 CLK_SGMII1_CDR_FB>, - <&topckgen CLK_TOP_NETSYS_SEL>, - <&topckgen CLK_TOP_NETSYS_500M_SEL>; - clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0", - "sgmii_tx250m", "sgmii_rx250m", - "sgmii_cdr_ref", "sgmii_cdr_fb", - "sgmii2_tx250m", "sgmii2_rx250m", - "sgmii2_cdr_ref", "sgmii2_cdr_fb", - "netsys0", "netsys1"; - assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, - <&topckgen CLK_TOP_SGM_325M_SEL>; - assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, - <&apmixedsys CLK_APMIXED_SGMPLL>; - mediatek,ethsys = <ðsys>; - mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; - mediatek,wed-pcie = <&wed_pcie>; - mediatek,wed = <&wed0>, <&wed1>; - #reset-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - wifi: wifi@18000000 { - compatible = "mediatek,mt7986-wmac"; - resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; - reset-names = "consys"; - clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>, - <&topckgen CLK_TOP_AP2CNN_HOST_SEL>; - clock-names = "mcu", "ap2conn"; - reg = <0 0x18000000 0 0x1000000>, - <0 0x10003000 0 0x1000>, - <0 0x11d10000 0 0x1000>; - interrupts = , - , - , - ; - memory-region = <&wmcpu_emi>; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <1000>; - thermal-sensors = <&thermal 0>; - - trips { - cpu_trip_active_high: active-high { - temperature = <115000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_active_low: active-low { - temperature = <85000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_passive: passive { - temperature = <40000>; - hysteresis = <2000>; - type = "passive"; - }; - }; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts deleted file mode 100644 index 83d51916717..00000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts +++ /dev/null @@ -1,194 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2021 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -#include "mt7986b.dtsi" - -/ { - model = "MediaTek MT7986b RFB"; - compatible = "mediatek,mt7986b-rfb"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0 0x40000000 0 0x40000000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "fixed-5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&ssusb { - vusb33-supply = <®_3p3v>; - vbus-supply = <®_5v>; - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&usb_phy { - status = "okay"; -}; - -&wifi { - status = "okay"; - pinctrl-names = "default", "dbdc"; - pinctrl-0 = <&wf_2g_5g_pins>; - pinctrl-1 = <&wf_dbdc_pins>; -}; - -ð { - status = "okay"; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - - gmac1: mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - - mdio: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - phy5: phy@5 { - compatible = "ethernet-phy-id67c9.de0a"; - reg = <5>; - reset-gpios = <&pio 6 1>; - reset-deassert-us = <20000>; - phy-mode = "2500base-x"; - }; - - phy6: phy@6 { - compatible = "ethernet-phy-id67c9.de0a"; - reg = <6>; - phy-mode = "2500base-x"; - }; - - switch@0 { - compatible = "mediatek,mt7531"; - reg = <31>; - reset-gpios = <&pio 5 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan0"; - }; - - port@1 { - reg = <1>; - label = "lan1"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan3"; - }; - - port@6 { - reg = <6>; - ethernet = <&gmac0>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - }; - }; - }; -}; - -&crypto { - status = "okay"; -}; - -&pio { - wf_2g_5g_pins: wf_2g_5g-pins { - mux { - function = "wifi"; - groups = "wf_2g", "wf_5g"; - }; - conf { - pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", - "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", - "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", - "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", - "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", - "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", - "WF1_TOP_CLK", "WF1_TOP_DATA"; - drive-strength = <4>; - }; - }; - - wf_dbdc_pins: wf_dbdc-pins { - mux { - function = "wifi"; - groups = "wf_dbdc"; - }; - conf { - pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", - "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", - "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", - "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", - "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", - "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", - "WF1_TOP_CLK", "WF1_TOP_DATA"; - drive-strength = <4>; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986b.dtsi b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986b.dtsi deleted file mode 100644 index db5189664c2..00000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986b.dtsi +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2021 MediaTek Inc. - * Author: Sam.Shih - */ - -#include "mt7986a.dtsi" -/ { - compatible = "mediatek,mt7986b"; -}; - -&pio { - compatible = "mediatek,mt7986b-pinctrl"; - gpio-ranges = <&pio 0 0 41>, <&pio 66 66 35>; -}; diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7981-apmixed.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7981-apmixed.c deleted file mode 100644 index 1647021de88..00000000000 --- a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7981-apmixed.c +++ /dev/null @@ -1,102 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2021 MediaTek Inc. - * Author: Sam Shih - * Author: Wenzhen Yu - * Author: Jianhui Zhao - * Author: Daniel Golle - */ - -#include -#include -#include -#include -#include -#include "clk-mtk.h" -#include "clk-gate.h" -#include "clk-mux.h" - -#include -#include - -#define MT7981_PLL_FMAX (2500UL * MHZ) -#define CON0_MT7981_RST_BAR BIT(27) - -#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ - _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ - _div_table, _parent_name) \ - { \ - .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \ - .en_mask = _en_mask, .flags = _flags, \ - .rst_bar_mask = CON0_MT7981_RST_BAR, .fmax = MT7981_PLL_FMAX, \ - .pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \ - .tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg, \ - .pcw_shift = _pcw_shift, .div_table = _div_table, \ - .parent_name = _parent_name, \ - } - -#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ - _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) \ - PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ - _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL, \ - "clkxtal") - -static const struct mtk_pll_data plls[] = { - PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, PLL_AO, - 32, 0x0200, 4, 0, 0x0204, 0), - PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32, - 0x0210, 4, 0, 0x0214, 0), - PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32, - 0x0220, 4, 0, 0x0224, 0), - PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023C, 0x00000001, 0, 32, - 0x0230, 4, 0, 0x0234, 0), - PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024C, 0x00000001, 0, 32, - 0x0240, 4, 0, 0x0244, 0), - PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025C, 0x00000001, 0, 32, - 0x0250, 4, 0, 0x0254, 0), - PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32, - 0x0260, 4, 0, 0x0264, 0), - PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32, - 0x0278, 4, 0, 0x027C, 0), -}; - -static const struct of_device_id of_match_clk_mt7981_apmixed[] = { - { .compatible = "mediatek,mt7981-apmixedsys", }, - {} -}; - -static int clk_mt7981_apmixed_probe(struct platform_device *pdev) -{ - struct clk_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls)); - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); - - clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_apmixed_data; - } - return r; - -free_apmixed_data: - mtk_free_clk_data(clk_data); - return r; -} - -static struct platform_driver clk_mt7981_apmixed_drv = { - .probe = clk_mt7981_apmixed_probe, - .driver = { - .name = "clk-mt7981-apmixed", - .of_match_table = of_match_clk_mt7981_apmixed, - }, -}; -builtin_platform_driver(clk_mt7981_apmixed_drv); diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7981-eth.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7981-eth.c deleted file mode 100644 index 4aba657aa6f..00000000000 --- a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7981-eth.c +++ /dev/null @@ -1,139 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2021 MediaTek Inc. - * Author: Sam Shih - * Author: Wenzhen Yu - * Author: Jianhui Zhao - * Author: Daniel Golle - */ - -#include -#include -#include -#include -#include - -#include "clk-mtk.h" -#include "clk-gate.h" - -#include - -static const struct mtk_gate_regs sgmii0_cg_regs = { - .set_ofs = 0xE4, - .clr_ofs = 0xE4, - .sta_ofs = 0xE4, -}; - -#define GATE_SGMII0(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &sgmii0_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } - -static const struct mtk_gate sgmii0_clks[] __initconst = { - GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "usb_tx250m", 2), - GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "usb_eq_rx250m", 3), - GATE_SGMII0(CLK_SGM0_CK0_EN, "sgm0_ck0_en", "usb_ln0", 4), - GATE_SGMII0(CLK_SGM0_CDR_CK0_EN, "sgm0_cdr_ck0_en", "usb_cdr", 5), -}; - -static const struct mtk_gate_regs sgmii1_cg_regs = { - .set_ofs = 0xE4, - .clr_ofs = 0xE4, - .sta_ofs = 0xE4, -}; - -#define GATE_SGMII1(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &sgmii1_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } - -static const struct mtk_gate sgmii1_clks[] __initconst = { - GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "usb_tx250m", 2), - GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "usb_eq_rx250m", 3), - GATE_SGMII1(CLK_SGM1_CK1_EN, "sgm1_ck1_en", "usb_ln0", 4), - GATE_SGMII1(CLK_SGM1_CDR_CK1_EN, "sgm1_cdr_ck1_en", "usb_cdr", 5), -}; - -static const struct mtk_gate_regs eth_cg_regs = { - .set_ofs = 0x30, - .clr_ofs = 0x30, - .sta_ofs = 0x30, -}; - -#define GATE_ETH(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = ð_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } - -static const struct mtk_gate eth_clks[] __initconst = { - GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x", 6), - GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m", 7), - GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m", 8), - GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_wed_mcu", 15), -}; - -static void __init mtk_sgmiisys_0_init(struct device_node *node) -{ - struct clk_onecell_data *clk_data; - int r; - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks)); - - mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks), - clk_data); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} -CLK_OF_DECLARE(mtk_sgmiisys_0, "mediatek,mt7981-sgmiisys_0", - mtk_sgmiisys_0_init); - -static void __init mtk_sgmiisys_1_init(struct device_node *node) -{ - struct clk_onecell_data *clk_data; - int r; - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks)); - - mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks), - clk_data); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} -CLK_OF_DECLARE(mtk_sgmiisys_1, "mediatek,mt7981-sgmiisys_1", - mtk_sgmiisys_1_init); - -static void __init mtk_ethsys_init(struct device_node *node) -{ - struct clk_onecell_data *clk_data; - int r; - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks)); - - mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} -CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt7981-ethsys", mtk_ethsys_init); diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7981-infracfg.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7981-infracfg.c deleted file mode 100644 index 8416829e358..00000000000 --- a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7981-infracfg.c +++ /dev/null @@ -1,235 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2021 MediaTek Inc. - * Author: Sam Shih - * Author: Wenzhen Yu - * Author: Jianhui Zhao - * Author: Daniel Golle - */ - -#include -#include -#include -#include -#include -#include "clk-mtk.h" -#include "clk-gate.h" -#include "clk-mux.h" - -#include -#include - -static DEFINE_SPINLOCK(mt7981_clk_lock); - -static const struct mtk_fixed_factor infra_divs[] = { - FACTOR(CLK_INFRA_66M_MCK, "infra_66m_mck", "sysaxi_sel", 1, 2), -}; - -static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel", - "uart_sel" }; - -static const char *const infra_spi0_parents[] __initconst = { "i2c_sel", - "spi_sel" }; - -static const char *const infra_spi1_parents[] __initconst = { "i2c_sel", - "spim_mst_sel" }; - -static const char *const infra_pwm1_parents[] __initconst = { "pwm_sel" }; - -static const char *const infra_pwm_bsel_parents[] __initconst = { - "cb_rtc_32p7k", "csw_f26m_sel", "infra_66m_mck", "pwm_sel" -}; - -static const char *const infra_pcie_parents[] __initconst = { - "cb_rtc_32p7k", "csw_f26m_sel", "cb_cksq_40m", "pextp_tl_ck_sel" -}; - -static const struct mtk_mux infra_muxes[] = { - /* MODULE_CLK_SEL_0 */ - MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel", - infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1, - -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel", - infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1, - -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel", - infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1, - -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel", - infra_spi0_parents, 0x0018, 0x0010, 0x0014, 4, 1, - -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel", - infra_spi1_parents, 0x0018, 0x0010, 0x0014, 5, 1, - -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI2_SEL, "infra_spi2_sel", - infra_spi0_parents, 0x0018, 0x0010, 0x0014, 6, 1, - -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel", - infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 9, 1, - -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel", - infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 11, 1, - -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM3_SEL, "infra_pwm3_sel", - infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 15, 1, - -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel", - infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13, - 2, -1, -1, -1), - /* MODULE_CLK_SEL_1 */ - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel", - infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2, - -1, -1, -1), -}; - -static const struct mtk_gate_regs infra0_cg_regs = { - .set_ofs = 0x40, - .clr_ofs = 0x44, - .sta_ofs = 0x48, -}; - -static const struct mtk_gate_regs infra1_cg_regs = { - .set_ofs = 0x50, - .clr_ofs = 0x54, - .sta_ofs = 0x58, -}; - -static const struct mtk_gate_regs infra2_cg_regs = { - .set_ofs = 0x60, - .clr_ofs = 0x64, - .sta_ofs = 0x68, -}; - -#define GATE_INFRA0(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &infra0_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } - -#define GATE_INFRA1(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &infra1_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } - -#define GATE_INFRA2(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &infra2_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } - -static const struct mtk_gate infra_clks[] = { - /* INFRA0 */ - GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_66m_mck", 0), - GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_66m_mck", 1), - GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2), - GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3), - GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4), - GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi", 6), - - GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi", 8), - GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9), - GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l", 10), - GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys", 11), - GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner", 13), - GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel", - 14), - GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_66m_mck", 15), - GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_66m_mck", 16), - GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_66m_mck", 24), - GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25), - GATE_INFRA0(CLK_INFRA_PWM3_CK, "infra_pwm3", "infra_pwm3_sel", 27), - /* INFRA1 */ - GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0), - GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_bck", 1), - GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2), - GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3), - GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4), - GATE_INFRA1(CLK_INFRA_SPI2_CK, "infra_spi2", "infra_spi2_sel", 6), - GATE_INFRA1(CLK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", "infra_66m_mck", 7), - GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x", 8), - GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_bck", 9), - GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_66m_mck", 10), - GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11), - GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12), - GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_66m_mck", - 13), - GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_66m_mck", - 14), - GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "cb_rtc_32k", 15), - GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_400m", 16), - GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_208m", 17), - GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi", 18), - GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "sysaxi", 19), - GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20), - GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m", 21), - GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x", 23), - GATE_INFRA1(CLK_INFRA_I2C_MCK_CK, "infra_i2c_mck", "sysaxi", 25), - GATE_INFRA1(CLK_INFRA_I2C_PCK_CK, "infra_i2c_pck", "infra_66m_mck", 26), - /* INFRA2 */ - GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi", 0), - GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "sysaxi", 1), - GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys", 2), - GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_ref", 3), - GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl", 12), - GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "cb_cksq_40m", - 13), - GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m", 14), - GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi", 15), -}; - -static int clk_mt7981_infracfg_probe(struct platform_device *pdev) -{ - struct clk_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - void __iomem *base; - int nr = ARRAY_SIZE(infra_divs) + ARRAY_SIZE(infra_muxes) + - ARRAY_SIZE(infra_clks); - - base = of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return -ENOMEM; - } - - clk_data = mtk_alloc_clk_data(nr); - - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data); - mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node, - &mt7981_clk_lock, clk_data); - mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_infracfg_data; - } - return r; - -free_infracfg_data: - mtk_free_clk_data(clk_data); - return r; -} - -static const struct of_device_id of_match_clk_mt7981_infracfg[] = { - { .compatible = "mediatek,mt7981-infracfg", }, - {} -}; - -static struct platform_driver clk_mt7981_infracfg_drv = { - .probe = clk_mt7981_infracfg_probe, - .driver = { - .name = "clk-mt7981-infracfg", - .of_match_table = of_match_clk_mt7981_infracfg, - }, -}; -builtin_platform_driver(clk_mt7981_infracfg_drv); diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7981-topckgen.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7981-topckgen.c deleted file mode 100644 index ce6dc186726..00000000000 --- a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7981-topckgen.c +++ /dev/null @@ -1,450 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2021 MediaTek Inc. - * Author: Sam Shih - * Author: Wenzhen Yu - * Author: Jianhui Zhao - */ - - -#include -#include -#include -#include -#include -#include "clk-mtk.h" -#include "clk-gate.h" -#include "clk-mux.h" - -#include -#include - -static DEFINE_SPINLOCK(mt7981_clk_lock); - -static const struct mtk_fixed_factor top_divs[] = { - FACTOR(CLK_TOP_CB_CKSQ_40M, "cb_cksq_40m", "clkxtal", 1, 1), - FACTOR(CLK_TOP_CB_M_416M, "cb_m_416m", "mpll", 1, 1), - FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", "mpll", 1, 2), - FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", "mpll", 1, 3), - FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", "mpll", 1, 2), - FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", "mpll", 1, 4), - FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", "mpll", 1, 8), - FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", "mpll", 1, 16), - FACTOR(CLK_TOP_CB_MM_720M, "cb_mm_720m", "mmpll", 1, 1), - FACTOR(CLK_TOP_CB_MM_D2, "cb_mm_d2", "mmpll", 1, 2), - FACTOR(CLK_TOP_CB_MM_D3, "cb_mm_d3", "mmpll", 1, 3), - FACTOR(CLK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", "mmpll", 1, 15), - FACTOR(CLK_TOP_CB_MM_D4, "cb_mm_d4", "mmpll", 1, 4), - FACTOR(CLK_TOP_CB_MM_D6, "cb_mm_d6", "mmpll", 1, 6), - FACTOR(CLK_TOP_MM_D6_D2, "mm_d6_d2", "mmpll", 1, 12), - FACTOR(CLK_TOP_CB_MM_D8, "cb_mm_d8", "mmpll", 1, 8), - FACTOR(CLK_TOP_CB_APLL2_196M, "cb_apll2_196m", "apll2", 1, 1), - FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2), - FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4), - FACTOR(CLK_TOP_NET1_2500M, "net1_2500m", "net1pll", 1, 1), - FACTOR(CLK_TOP_CB_NET1_D4, "cb_net1_d4", "net1pll", 1, 4), - FACTOR(CLK_TOP_CB_NET1_D5, "cb_net1_d5", "net1pll", 1, 5), - FACTOR(CLK_TOP_NET1_D5_D2, "net1_d5_d2", "net1pll", 1, 10), - FACTOR(CLK_TOP_NET1_D5_D4, "net1_d5_d4", "net1pll", 1, 20), - FACTOR(CLK_TOP_CB_NET1_D8, "cb_net1_d8", "net1pll", 1, 8), - FACTOR(CLK_TOP_NET1_D8_D2, "net1_d8_d2", "net1pll", 1, 16), - FACTOR(CLK_TOP_NET1_D8_D4, "net1_d8_d4", "net1pll", 1, 32), - FACTOR(CLK_TOP_CB_NET2_800M, "cb_net2_800m", "net2pll", 1, 1), - FACTOR(CLK_TOP_CB_NET2_D2, "cb_net2_d2", "net2pll", 1, 2), - FACTOR(CLK_TOP_CB_NET2_D4, "cb_net2_d4", "net2pll", 1, 4), - FACTOR(CLK_TOP_NET2_D4_D2, "net2_d4_d2", "net2pll", 1, 8), - FACTOR(CLK_TOP_NET2_D4_D4, "net2_d4_d4", "net2pll", 1, 16), - FACTOR(CLK_TOP_CB_NET2_D6, "cb_net2_d6", "net2pll", 1, 6), - FACTOR(CLK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", "wedmcupll", 1, 1), - FACTOR(CLK_TOP_CB_SGM_325M, "cb_sgm_325m", "sgmpll", 1, 1), - FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", "cb_cksq_40m", 1, 2), - FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", "cb_cksq_40m", 1, 1250), - FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", "cb_cksq_40m", 1, 1220), - FACTOR(CLK_TOP_USB_TX250M, "usb_tx250m", "cb_cksq_40m", 1, 1), - FACTOR(CLK_TOP_FAUD, "faud", "aud_sel", 1, 1), - FACTOR(CLK_TOP_NFI1X, "nfi1x", "nfi1x_sel", 1, 1), - FACTOR(CLK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", "cb_cksq_40m", 1, 1), - FACTOR(CLK_TOP_USB_CDR_CK, "usb_cdr", "cb_cksq_40m", 1, 1), - FACTOR(CLK_TOP_USB_LN0_CK, "usb_ln0", "cb_cksq_40m", 1, 1), - FACTOR(CLK_TOP_SPINFI_BCK, "spinfi_bck", "spinfi_sel", 1, 1), - FACTOR(CLK_TOP_SPI, "spi", "spi_sel", 1, 1), - FACTOR(CLK_TOP_SPIM_MST, "spim_mst", "spim_mst_sel", 1, 1), - FACTOR(CLK_TOP_UART_BCK, "uart_bck", "uart_sel", 1, 1), - FACTOR(CLK_TOP_PWM_BCK, "pwm_bck", "pwm_sel", 1, 1), - FACTOR(CLK_TOP_I2C_BCK, "i2c_bck", "i2c_sel", 1, 1), - FACTOR(CLK_TOP_PEXTP_TL, "pextp_tl", "pextp_tl_ck_sel", 1, 1), - FACTOR(CLK_TOP_EMMC_208M, "emmc_208m", "emmc_208m_sel", 1, 1), - FACTOR(CLK_TOP_EMMC_400M, "emmc_400m", "emmc_400m_sel", 1, 1), - FACTOR(CLK_TOP_DRAMC_REF, "dramc_ref", "dramc_sel", 1, 1), - FACTOR(CLK_TOP_DRAMC_MD32, "dramc_md32", "dramc_md32_sel", 1, 1), - FACTOR(CLK_TOP_SYSAXI, "sysaxi", "sysaxi_sel", 1, 1), - FACTOR(CLK_TOP_SYSAPB, "sysapb", "sysapb_sel", 1, 1), - FACTOR(CLK_TOP_ARM_DB_MAIN, "arm_db_main", "arm_db_main_sel", 1, 1), - FACTOR(CLK_TOP_AP2CNN_HOST, "ap2cnn_host", "ap2cnn_host_sel", 1, 1), - FACTOR(CLK_TOP_NETSYS, "netsys", "netsys_sel", 1, 1), - FACTOR(CLK_TOP_NETSYS_500M, "netsys_500m", "netsys_500m_sel", 1, 1), - FACTOR(CLK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", "netsys_mcu_sel", 1, 1), - FACTOR(CLK_TOP_NETSYS_2X, "netsys_2x", "netsys_2x_sel", 1, 1), - FACTOR(CLK_TOP_SGM_325M, "sgm_325m", "sgm_325m_sel", 1, 1), - FACTOR(CLK_TOP_SGM_REG, "sgm_reg", "sgm_reg_sel", 1, 1), - FACTOR(CLK_TOP_F26M, "csw_f26m", "csw_f26m_sel", 1, 1), - FACTOR(CLK_TOP_EIP97B, "eip97b", "eip97b_sel", 1, 1), - FACTOR(CLK_TOP_USB3_PHY, "usb3_phy", "usb3_phy_sel", 1, 1), - FACTOR(CLK_TOP_AUD, "aud", "faud", 1, 1), - FACTOR(CLK_TOP_A1SYS, "a1sys", "a1sys_sel", 1, 1), - FACTOR(CLK_TOP_AUD_L, "aud_l", "aud_l_sel", 1, 1), - FACTOR(CLK_TOP_A_TUNER, "a_tuner", "a_tuner_sel", 1, 1), - FACTOR(CLK_TOP_U2U3_REF, "u2u3_ref", "u2u3_sel", 1, 1), - FACTOR(CLK_TOP_U2U3_SYS, "u2u3_sys", "u2u3_sys_sel", 1, 1), - FACTOR(CLK_TOP_U2U3_XHCI, "u2u3_xhci", "u2u3_xhci_sel", 1, 1), - FACTOR(CLK_TOP_USB_FRMCNT, "usb_frmcnt", "usb_frmcnt_sel", 1, 1), -}; - -static const char * const nfi1x_parents[] __initconst = { - "cb_cksq_40m", - "cb_mm_d4", - "net1_d8_d2", - "cb_net2_d6", - "cb_m_d4", - "cb_mm_d8", - "net1_d8_d4", - "cb_m_d8" -}; - -static const char * const spinfi_parents[] __initconst = { - "cksq_40m_d2", - "cb_cksq_40m", - "net1_d5_d4", - "cb_m_d4", - "cb_mm_d8", - "net1_d8_d4", - "mm_d6_d2", - "cb_m_d8" -}; - -static const char * const spi_parents[] __initconst = { - "cb_cksq_40m", - "cb_m_d2", - "cb_mm_d4", - "net1_d8_d2", - "cb_net2_d6", - "net1_d5_d4", - "cb_m_d4", - "net1_d8_d4" -}; - -static const char * const uart_parents[] __initconst = { - "cb_cksq_40m", - "cb_m_d8", - "m_d8_d2" -}; - -static const char * const pwm_parents[] __initconst = { - "cb_cksq_40m", - "net1_d8_d2", - "net1_d5_d4", - "cb_m_d4", - "m_d8_d2", - "cb_rtc_32k" -}; - -static const char * const i2c_parents[] __initconst = { - "cb_cksq_40m", - "net1_d5_d4", - "cb_m_d4", - "net1_d8_d4" -}; - -static const char * const pextp_tl_ck_parents[] __initconst = { - "cb_cksq_40m", - "net1_d5_d4", - "cb_m_d4", - "cb_rtc_32k" -}; - -static const char * const emmc_208m_parents[] __initconst = { - "cb_cksq_40m", - "cb_m_d2", - "cb_net2_d4", - "cb_apll2_196m", - "cb_mm_d4", - "net1_d8_d2", - "cb_mm_d6" -}; - -static const char * const emmc_400m_parents[] __initconst = { - "cb_cksq_40m", - "cb_net2_d2", - "cb_mm_d2", - "cb_net2_d2" -}; - -static const char * const csw_f26m_parents[] __initconst = { - "cksq_40m_d2", - "m_d8_d2" -}; - -static const char * const dramc_md32_parents[] __initconst = { - "cb_cksq_40m", - "cb_m_d2", - "cb_wedmcu_208m" -}; - -static const char * const sysaxi_parents[] __initconst = { - "cb_cksq_40m", - "net1_d8_d2" -}; - -static const char * const sysapb_parents[] __initconst = { - "cb_cksq_40m", - "m_d3_d2" -}; - -static const char * const arm_db_main_parents[] __initconst = { - "cb_cksq_40m", - "cb_net2_d6" -}; - -static const char * const ap2cnn_host_parents[] __initconst = { - "cb_cksq_40m", - "net1_d8_d4" -}; - -static const char * const netsys_parents[] __initconst = { - "cb_cksq_40m", - "cb_mm_d2" -}; - -static const char * const netsys_500m_parents[] __initconst = { - "cb_cksq_40m", - "cb_net1_d5" -}; - -static const char * const netsys_mcu_parents[] __initconst = { - "cb_cksq_40m", - "cb_mm_720m", - "cb_net1_d4", - "cb_net1_d5", - "cb_m_416m" -}; - -static const char * const netsys_2x_parents[] __initconst = { - "cb_cksq_40m", - "cb_net2_800m", - "cb_mm_720m" -}; - -static const char * const sgm_325m_parents[] __initconst = { - "cb_cksq_40m", - "cb_sgm_325m" -}; - -static const char * const sgm_reg_parents[] __initconst = { - "cb_cksq_40m", - "cb_net2_d4" -}; - -static const char * const eip97b_parents[] __initconst = { - "cb_cksq_40m", - "cb_net1_d5", - "cb_m_416m", - "cb_mm_d2", - "net1_d5_d2" -}; - -static const char * const aud_parents[] __initconst = { - "cb_cksq_40m", - "cb_apll2_196m" -}; - -static const char * const a1sys_parents[] __initconst = { - "cb_cksq_40m", - "apll2_d4" -}; - -static const char * const aud_l_parents[] __initconst = { - "cb_cksq_40m", - "cb_apll2_196m", - "m_d8_d2" -}; - -static const char * const a_tuner_parents[] __initconst = { - "cb_cksq_40m", - "apll2_d4", - "m_d8_d2" -}; - -static const char * const u2u3_parents[] __initconst = { - "cb_cksq_40m", - "m_d8_d2" -}; - -static const char * const u2u3_sys_parents[] __initconst = { - "cb_cksq_40m", - "net1_d5_d4" -}; - -static const char * const usb_frmcnt_parents[] __initconst = { - "cb_cksq_40m", - "cb_mm_d3_d5" -}; - -static const struct mtk_mux top_muxes[] = { - /* CLK_CFG_0 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, - 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, - 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, - 0x000, 0x004, 0x008, 16, 3, 23, 0x1C0, 2), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, - 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3), - /* CLK_CFG_1 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, - 0x010, 0x014, 0x018, 0, 2, 7, 0x1C0, 4), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, - 0x010, 0x014, 0x018, 8, 3, 15, 0x1C0, 5), - MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, - 0x010, 0x014, 0x018, 16, 2, 23, 0x1C0, 6), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", - pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 31, - 0x1C0, 7), - /* CLK_CFG_2 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel", - emmc_208m_parents, 0x020, 0x024, 0x028, 0, 3, 7, - 0x1C0, 8), - MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", - emmc_400m_parents, 0x020, 0x024, 0x028, 8, 2, 15, - 0x1C0, 9), - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel", - csw_f26m_parents, 0x020, 0x024, 0x028, 16, 1, 23, - 0x1C0, 10, - CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", - csw_f26m_parents, 0x020, 0x024, 0x028, 24, 1, - 31, 0x1C0, 11, - CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), - /* CLK_CFG_3 */ - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", - dramc_md32_parents, 0x030, 0x034, 0x038, 0, 2, - 7, 0x1C0, 12, - CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", - sysaxi_parents, 0x030, 0x034, 0x038, 8, 1, 15, - 0x1C0, 13, - CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", - sysapb_parents, 0x030, 0x034, 0x038, 16, 1, - 23, 0x1C0, 14, - CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), - MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", - arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, 31, - 0x1C0, 15), - /* CLK_CFG_4 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", - ap2cnn_host_parents, 0x040, 0x044, 0x048, 0, 1, 7, - 0x1C0, 16), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, - 0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", - netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1, 23, - 0x1C0, 18), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", - netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31, - 0x1C0, 19), - /* CLK_CFG_5 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", - netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7, - 0x1C0, 20), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", - sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15, - 0x1C0, 21), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, - 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22), - MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents, - 0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23), - /* CLK_CFG_6 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel", - csw_f26m_parents, 0x060, 0x064, 0x068, 0, 1, - 7, 0x1C0, 24), - MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x060, - 0x064, 0x068, 8, 1, 15, 0x1C0, 25), - MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, - 0x060, 0x064, 0x068, 16, 1, 23, 0x1C0, 26), - MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, - 0x060, 0x064, 0x068, 24, 2, 31, 0x1C0, 27), - /* CLK_CFG_7 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", - a_tuner_parents, 0x070, 0x074, 0x078, 0, 2, 7, - 0x1C0, 28), - MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x070, - 0x074, 0x078, 8, 1, 15, 0x1C0, 29), - MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", - u2u3_sys_parents, 0x070, 0x074, 0x078, 16, 1, 23, - 0x1C0, 30), - MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", - u2u3_sys_parents, 0x070, 0x074, 0x078, 24, 1, 31, - 0x1C4, 0), - /* CLK_CFG_8 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", - usb_frmcnt_parents, 0x080, 0x084, 0x088, 0, 1, 7, - 0x1C4, 1), -}; - -static struct mtk_composite top_aud_divs[] = { - DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud", - 0x0420, 0, 0x0420, 8, 8), -}; - -static int clk_mt7981_topckgen_probe(struct platform_device *pdev) -{ - struct clk_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - void __iomem *base; - int nr = ARRAY_SIZE(top_divs) + ARRAY_SIZE(top_muxes) + - ARRAY_SIZE(top_aud_divs); - - base = of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return -ENOMEM; - } - - clk_data = mtk_alloc_clk_data(nr); - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); - mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node, - &mt7981_clk_lock, clk_data); - mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs), base, - &mt7981_clk_lock, clk_data); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_topckgen_data; - } - return r; - -free_topckgen_data: - mtk_free_clk_data(clk_data); - return r; -} - -static const struct of_device_id of_match_clk_mt7981_topckgen[] = { - { .compatible = "mediatek,mt7981-topckgen", }, - {} -}; - -static struct platform_driver clk_mt7981_topckgen_drv = { - .probe = clk_mt7981_topckgen_probe, - .driver = { - .name = "clk-mt7981-topckgen", - .of_match_table = of_match_clk_mt7981_topckgen, - }, -}; -builtin_platform_driver(clk_mt7981_topckgen_drv); diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7986-apmixed.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7986-apmixed.c deleted file mode 100644 index 76c8ebdeae9..00000000000 --- a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7986-apmixed.c +++ /dev/null @@ -1,100 +0,0 @@ -// SPDX-License-Identifier: GPL-1.0 -/* - * Copyright (c) 2021 MediaTek Inc. - * Author: Sam Shih - * Author: Wenzhen Yu - */ - -#include -#include -#include -#include -#include -#include "clk-mtk.h" -#include "clk-gate.h" -#include "clk-mux.h" - -#include -#include - -#define MT7986_PLL_FMAX (2500UL * MHZ) -#define CON0_MT7986_RST_BAR BIT(27) - -#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ - _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ - _div_table, _parent_name) \ - { \ - .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \ - .en_mask = _en_mask, .flags = _flags, \ - .rst_bar_mask = CON0_MT7986_RST_BAR, .fmax = MT7986_PLL_FMAX, \ - .pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \ - .tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg, \ - .pcw_shift = _pcw_shift, .div_table = _div_table, \ - .parent_name = _parent_name, \ - } - -#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ - _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) \ - PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ - _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL, \ - "clkxtal") - -static const struct mtk_pll_data plls[] = { - PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, 0, 32, - 0x0200, 4, 0, 0x0204, 0), - PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32, - 0x0210, 4, 0, 0x0214, 0), - PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32, - 0x0220, 4, 0, 0x0224, 0), - PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023c, 0x00000001, 0, 32, - 0x0230, 4, 0, 0x0234, 0), - PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024c, 0x00000001, 0, - 32, 0x0240, 4, 0, 0x0244, 0), - PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025c, 0x00000001, 0, 32, - 0x0250, 4, 0, 0x0254, 0), - PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32, 0x0260, - 4, 0, 0x0264, 0), - PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32, - 0x0278, 4, 0, 0x027c, 0), -}; - -static const struct of_device_id of_match_clk_mt7986_apmixed[] = { - { .compatible = "mediatek,mt7986-apmixedsys", }, - {} -}; - -static int clk_mt7986_apmixed_probe(struct platform_device *pdev) -{ - struct clk_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls)); - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); - - clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_apmixed_data; - } - return r; - -free_apmixed_data: - mtk_free_clk_data(clk_data); - return r; -} - -static struct platform_driver clk_mt7986_apmixed_drv = { - .probe = clk_mt7986_apmixed_probe, - .driver = { - .name = "clk-mt7986-apmixed", - .of_match_table = of_match_clk_mt7986_apmixed, - }, -}; -builtin_platform_driver(clk_mt7986_apmixed_drv); diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7986-eth.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7986-eth.c deleted file mode 100644 index ed2e7b20098..00000000000 --- a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7986-eth.c +++ /dev/null @@ -1,132 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2021 MediaTek Inc. - * Author: Sam Shih - * Author: Wenzhen Yu - */ - -#include -#include -#include -#include -#include - -#include "clk-mtk.h" -#include "clk-gate.h" - -#include - -static const struct mtk_gate_regs sgmii0_cg_regs = { - .set_ofs = 0xe4, - .clr_ofs = 0xe4, - .sta_ofs = 0xe4, -}; - -#define GATE_SGMII0(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &sgmii0_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } - -static const struct mtk_gate sgmii0_clks[] __initconst = { - GATE_SGMII0(CLK_SGMII0_TX250M_EN, "sgmii0_tx250m_en", "top_xtal", 2), - GATE_SGMII0(CLK_SGMII0_RX250M_EN, "sgmii0_rx250m_en", "top_xtal", 3), - GATE_SGMII0(CLK_SGMII0_CDR_REF, "sgmii0_cdr_ref", "top_xtal", 4), - GATE_SGMII0(CLK_SGMII0_CDR_FB, "sgmii0_cdr_fb", "top_xtal", 5), -}; - -static const struct mtk_gate_regs sgmii1_cg_regs = { - .set_ofs = 0xe4, - .clr_ofs = 0xe4, - .sta_ofs = 0xe4, -}; - -#define GATE_SGMII1(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &sgmii1_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } - -static const struct mtk_gate sgmii1_clks[] __initconst = { - GATE_SGMII1(CLK_SGMII1_TX250M_EN, "sgmii1_tx250m_en", "top_xtal", 2), - GATE_SGMII1(CLK_SGMII1_RX250M_EN, "sgmii1_rx250m_en", "top_xtal", 3), - GATE_SGMII1(CLK_SGMII1_CDR_REF, "sgmii1_cdr_ref", "top_xtal", 4), - GATE_SGMII1(CLK_SGMII1_CDR_FB, "sgmii1_cdr_fb", "top_xtal", 5), -}; - -static const struct mtk_gate_regs eth_cg_regs = { - .set_ofs = 0x30, - .clr_ofs = 0x30, - .sta_ofs = 0x30, -}; - -#define GATE_ETH(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = ð_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } - -static const struct mtk_gate eth_clks[] __initconst = { - GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x_sel", 6), - GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m_sel", 7), - GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m_sel", 8), - GATE_ETH(CLK_ETH_WOCPU1_EN, "eth_wocpu1_en", "netsys_mcu_sel", 14), - GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_mcu_sel", 15), -}; - -static void __init mtk_sgmiisys_0_init(struct device_node *node) -{ - struct clk_onecell_data *clk_data; - int r; - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks)); - - mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks), - clk_data); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} -CLK_OF_DECLARE(mtk_sgmiisys_0, "mediatek,mt7986-sgmiisys_0", - mtk_sgmiisys_0_init); - -static void __init mtk_sgmiisys_1_init(struct device_node *node) -{ - struct clk_onecell_data *clk_data; - int r; - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks)); - - mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks), - clk_data); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} -CLK_OF_DECLARE(mtk_sgmiisys_1, "mediatek,mt7986-sgmiisys_1", - mtk_sgmiisys_1_init); - -static void __init mtk_ethsys_init(struct device_node *node) -{ - struct clk_onecell_data *clk_data; - int r; - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks)); - - mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} -CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt7986-ethsys", mtk_ethsys_init); diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7986-infracfg.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7986-infracfg.c deleted file mode 100644 index 82279dfcf57..00000000000 --- a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7986-infracfg.c +++ /dev/null @@ -1,224 +0,0 @@ -// SPDX-License-Identifier: GPL-1.0 -/* - * Copyright (c) 2021 MediaTek Inc. - * Author: Sam Shih - * Author: Wenzhen Yu - */ - -#include -#include -#include -#include -#include -#include "clk-mtk.h" -#include "clk-gate.h" -#include "clk-mux.h" - -#include -#include - -static DEFINE_SPINLOCK(mt7986_clk_lock); - -static const struct mtk_fixed_factor infra_divs[] = { - FACTOR(CLK_INFRA_SYSAXI_D2, "infra_sysaxi_d2", "sysaxi_sel", 1, 2), -}; - -static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel", - "uart_sel" }; - -static const char *const infra_spi_parents[] __initconst = { "i2c_sel", - "spi_sel" }; - -static const char *const infra_pwm_bsel_parents[] __initconst = { - "top_rtc_32p7k", "csw_f26m_sel", "infra_sysaxi_d2", "pwm_sel" -}; - -static const char *const infra_pcie_parents[] __initconst = { - "top_rtc_32p7k", "csw_f26m_sel", "top_xtal", "pextp_tl_ck_sel" -}; - -static const struct mtk_mux infra_muxes[] = { - /* MODULE_CLK_SEL_0 */ - MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel", - infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1, - -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel", - infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1, - -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel", - infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1, - -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel", - infra_spi_parents, 0x0018, 0x0010, 0x0014, 4, 1, - -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel", - infra_spi_parents, 0x0018, 0x0010, 0x0014, 5, 1, - -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel", - infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 9, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel", - infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 11, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel", - infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13, - 2, -1, -1, -1), - /* MODULE_CLK_SEL_1 */ - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel", - infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2, - -1, -1, -1), -}; - -static const struct mtk_gate_regs infra0_cg_regs = { - .set_ofs = 0x40, - .clr_ofs = 0x44, - .sta_ofs = 0x48, -}; - -static const struct mtk_gate_regs infra1_cg_regs = { - .set_ofs = 0x50, - .clr_ofs = 0x54, - .sta_ofs = 0x58, -}; - -static const struct mtk_gate_regs infra2_cg_regs = { - .set_ofs = 0x60, - .clr_ofs = 0x64, - .sta_ofs = 0x68, -}; - -#define GATE_INFRA0(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &infra0_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } - -#define GATE_INFRA1(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &infra1_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } - -#define GATE_INFRA2(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &infra2_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } - -static const struct mtk_gate infra_clks[] = { - /* INFRA0 */ - GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_sysaxi_d2", 0), - GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_sysaxi_d2", 1), - GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2), - GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3), - GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4), - GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi_sel", 6), - GATE_INFRA0(CLK_INFRA_EIP97_CK, "infra_eip97", "eip_b_sel", 7), - GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi_sel", 8), - GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9), - GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l_sel", 10), - GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys_sel", 11), - GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner_sel", 13), - GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel", - 14), - GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_sysaxi_d2", 15), - GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_sysaxi_d2", 16), - GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_sysaxi_d2", 24), - GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25), - GATE_INFRA0(CLK_INFRA_TRNG_CK, "infra_trng", "sysaxi_sel", 26), - /* INFRA1 */ - GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0), - GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_sel", 1), - GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2), - GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3), - GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4), - GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x_sel", 8), - GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_sel", 9), - GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_sysaxi_d2", - 10), - GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11), - GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12), - GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_sysaxi_d2", - 13), - GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_sysaxi_d2", - 14), - GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "top_rtc_32k", 15), - GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_416m_sel", 16), - GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_250m_sel", - 17), - GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi_sel", - 18), - GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "infra_sysaxi_d2", - 19), - GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20), - GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m_sel", 21), - GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x_sel", 23), - /* INFRA2 */ - GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi_sel", 0), - GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "infra_sysaxi_d2", - 1), - GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys_sel", 2), - GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_sel", 3), - GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl_ck_sel", 12), - GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "top_xtal", - 13), - GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m_sel", 14), - GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi_sel", 15), -}; - -static int clk_mt7986_infracfg_probe(struct platform_device *pdev) -{ - struct clk_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - void __iomem *base; - int nr = ARRAY_SIZE(infra_divs) + ARRAY_SIZE(infra_muxes) + - ARRAY_SIZE(infra_clks); - - base = of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return -ENOMEM; - } - - clk_data = mtk_alloc_clk_data(nr); - - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data); - mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node, - &mt7986_clk_lock, clk_data); - mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_infracfg_data; - } - return r; - -free_infracfg_data: - mtk_free_clk_data(clk_data); - return r; - -} - -static const struct of_device_id of_match_clk_mt7986_infracfg[] = { - { .compatible = "mediatek,mt7986-infracfg", }, - {} -}; - -static struct platform_driver clk_mt7986_infracfg_drv = { - .probe = clk_mt7986_infracfg_probe, - .driver = { - .name = "clk-mt7986-infracfg", - .of_match_table = of_match_clk_mt7986_infracfg, - }, -}; -builtin_platform_driver(clk_mt7986_infracfg_drv); diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7986-topckgen.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7986-topckgen.c deleted file mode 100644 index 8550e2be777..00000000000 --- a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7986-topckgen.c +++ /dev/null @@ -1,342 +0,0 @@ -// SPDX-License-Identifier: GPL-1.0 -/* - * Copyright (c) 2021 MediaTek Inc. - * Author: Sam Shih - * Author: Wenzhen Yu - */ - -#include -#include -#include -#include -#include -#include "clk-mtk.h" -#include "clk-gate.h" -#include "clk-mux.h" - -#include -#include - -static DEFINE_SPINLOCK(mt7986_clk_lock); - -static const struct mtk_fixed_clk top_fixed_clks[] = { - FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000), - FIXED_CLK(CLK_TOP_JTAG, "top_jtag", "clkxtal", 50000000), -}; - -static const struct mtk_fixed_factor top_divs[] = { - /* XTAL */ - FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2), - FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250), - FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220), - /* MPLL */ - FACTOR(CLK_TOP_MPLL_D2, "top_mpll_d2", "mpll", 1, 2), - FACTOR(CLK_TOP_MPLL_D4, "top_mpll_d4", "mpll", 1, 4), - FACTOR(CLK_TOP_MPLL_D8, "top_mpll_d8", "mpll", 1, 8), - FACTOR(CLK_TOP_MPLL_D8_D2, "top_mpll_d8_d2", "mpll", 1, 16), - FACTOR(CLK_TOP_MPLL_D3_D2, "top_mpll_d3_d2", "mpll", 1, 6), - /* MMPLL */ - FACTOR(CLK_TOP_MMPLL_D2, "top_mmpll_d2", "mmpll", 1, 2), - FACTOR(CLK_TOP_MMPLL_D4, "top_mmpll_d4", "mmpll", 1, 4), - FACTOR(CLK_TOP_MMPLL_D8, "top_mmpll_d8", "mmpll", 1, 8), - FACTOR(CLK_TOP_MMPLL_D8_D2, "top_mmpll_d8_d2", "mmpll", 1, 16), - FACTOR(CLK_TOP_MMPLL_D3_D8, "top_mmpll_d3_d8", "mmpll", 1, 24), - FACTOR(CLK_TOP_MMPLL_U2PHY, "top_mmpll_u2phy", "mmpll", 1, 30), - /* APLL2 */ - FACTOR(CLK_TOP_APLL2_D4, "top_apll2_d4", "apll2", 1, 4), - /* NET1PLL */ - FACTOR(CLK_TOP_NET1PLL_D4, "top_net1pll_d4", "net1pll", 1, 4), - FACTOR(CLK_TOP_NET1PLL_D5, "top_net1pll_d5", "net1pll", 1, 5), - FACTOR(CLK_TOP_NET1PLL_D5_D2, "top_net1pll_d5_d2", "net1pll", 1, 10), - FACTOR(CLK_TOP_NET1PLL_D5_D4, "top_net1pll_d5_d4", "net1pll", 1, 20), - FACTOR(CLK_TOP_NET1PLL_D8_D2, "top_net1pll_d8_d2", "net1pll", 1, 16), - FACTOR(CLK_TOP_NET1PLL_D8_D4, "top_net1pll_d8_d4", "net1pll", 1, 32), - /* NET2PLL */ - FACTOR(CLK_TOP_NET2PLL_D4, "top_net2pll_d4", "net2pll", 1, 4), - FACTOR(CLK_TOP_NET2PLL_D4_D2, "top_net2pll_d4_d2", "net2pll", 1, 8), - FACTOR(CLK_TOP_NET2PLL_D3_D2, "top_net2pll_d3_d2", "net2pll", 1, 2), - /* WEDMCUPLL */ - FACTOR(CLK_TOP_WEDMCUPLL_D5_D2, "top_wedmcupll_d5_d2", "wedmcupll", 1, - 10), -}; - -static const char *const nfi1x_parents[] __initconst = { "top_xtal", - "top_mmpll_d8", - "top_net1pll_d8_d2", - "top_net2pll_d3_d2", - "top_mpll_d4", - "top_mmpll_d8_d2", - "top_wedmcupll_d5_d2", - "top_mpll_d8" }; - -static const char *const spinfi_parents[] __initconst = { - "top_xtal_d2", "top_xtal", "top_net1pll_d5_d4", - "top_mpll_d4", "top_mmpll_d8_d2", "top_wedmcupll_d5_d2", - "top_mmpll_d3_d8", "top_mpll_d8" -}; - -static const char *const spi_parents[] __initconst = { - "top_xtal", "top_mpll_d2", "top_mmpll_d8", - "top_net1pll_d8_d2", "top_net2pll_d3_d2", "top_net1pll_d5_d4", - "top_mpll_d4", "top_wedmcupll_d5_d2" -}; - -static const char *const uart_parents[] __initconst = { "top_xtal", - "top_mpll_d8", - "top_mpll_d8_d2" }; - -static const char *const pwm_parents[] __initconst = { - "top_xtal", "top_net1pll_d8_d2", "top_net1pll_d5_d4", "top_mpll_d4" -}; - -static const char *const i2c_parents[] __initconst = { - "top_xtal", "top_net1pll_d5_d4", "top_mpll_d4", "top_net1pll_d8_d4" -}; - -static const char *const pextp_tl_ck_parents[] __initconst = { - "top_xtal", "top_net1pll_d5_d4", "top_net2pll_d4_d2", "top_rtc_32k" -}; - -static const char *const emmc_250m_parents[] __initconst = { - "top_xtal", "top_net1pll_d5_d2" -}; - -static const char *const emmc_416m_parents[] __initconst = { "top_xtal", - "mpll" }; - -static const char *const f_26m_adc_parents[] __initconst = { "top_xtal", - "top_mpll_d8_d2" }; - -static const char *const dramc_md32_parents[] __initconst = { "top_xtal", - "top_mpll_d2" }; - -static const char *const sysaxi_parents[] __initconst = { "top_xtal", - "top_net1pll_d8_d2", - "top_net2pll_d4" }; - -static const char *const sysapb_parents[] __initconst = { "top_xtal", - "top_mpll_d3_d2", - "top_net2pll_d4_d2" }; - -static const char *const arm_db_main_parents[] __initconst = { - "top_xtal", "top_net2pll_d3_d2" -}; - -static const char *const arm_db_jtsel_parents[] __initconst = { "top_jtag", - "top_xtal" }; - -static const char *const netsys_parents[] __initconst = { "top_xtal", - "top_mmpll_d4" }; - -static const char *const netsys_500m_parents[] __initconst = { - "top_xtal", "top_net1pll_d5" -}; - -static const char *const netsys_mcu_parents[] __initconst = { - "top_xtal", "wedmcupll", "top_mmpll_d2", "top_net1pll_d4", - "top_net1pll_d5" -}; - -static const char *const netsys_2x_parents[] __initconst = { - "top_xtal", "net2pll", "wedmcupll", "top_mmpll_d2" -}; - -static const char *const sgm_325m_parents[] __initconst = { "top_xtal", - "sgmpll" }; - -static const char *const sgm_reg_parents[] __initconst = { - "top_xtal", "top_net1pll_d8_d4" -}; - -static const char *const a1sys_parents[] __initconst = { "top_xtal", - "top_apll2_d4" }; - -static const char *const conn_mcusys_parents[] __initconst = { "top_xtal", - "top_mmpll_d2" }; - -static const char *const eip_b_parents[] __initconst = { "top_xtal", - "net2pll" }; - -static const char *const aud_l_parents[] __initconst = { "top_xtal", "apll2", - "top_mpll_d8_d2" }; - -static const char *const a_tuner_parents[] __initconst = { "top_xtal", - "top_apll2_d4", - "top_mpll_d8_d2" }; - -static const char *const u2u3_sys_parents[] __initconst = { - "top_xtal", "top_net1pll_d5_d4" -}; - -static const char *const da_u2_refsel_parents[] __initconst = { - "top_xtal", "top_mmpll_u2phy" -}; - -static const struct mtk_mux top_muxes[] = { - /* CLK_CFG_0 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, - 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, - 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000, - 0x004, 0x008, 16, 3, 23, 0x1C0, 2), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, - 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3), - /* CLK_CFG_1 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010, - 0x014, 0x018, 0, 2, 7, 0x1C0, 4), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010, - 0x014, 0x018, 8, 2, 15, 0x1C0, 5), - MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010, - 0x014, 0x018, 16, 2, 23, 0x1C0, 6), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", - pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, - 31, 0x1C0, 7), - /* CLK_CFG_2 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", - emmc_250m_parents, 0x020, 0x024, 0x028, 0, 1, 7, - 0x1C0, 8), - MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_416M_SEL, "emmc_416m_sel", - emmc_416m_parents, 0x020, 0x024, 0x028, 8, 1, 15, - 0x1C0, 9), - MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel", - f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23, - 0x1C0, 10), - MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents, - 0x020, 0x024, 0x028, 24, 1, 31, 0x1C0, 11), - /* CLK_CFG_3 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", - dramc_md32_parents, 0x030, 0x034, 0x038, 0, 1, 7, - 0x1C0, 12), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, - 0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, - 0x030, 0x034, 0x038, 16, 2, 23, 0x1C0, 14), - MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", - arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, - 31, 0x1C0, 15), - /* CLK_CFG_4 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_JTSEL, "arm_db_jtsel", - arm_db_jtsel_parents, 0x040, 0x044, 0x048, 0, 1, 7, - 0x1C0, 16), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, - 0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", - netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1, - 23, 0x1C0, 18), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", - netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31, - 0x1C0, 19), - /* CLK_CFG_5 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", - netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7, - 0x1C0, 20), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", - sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15, - 0x1C0, 21), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", - sgm_reg_parents, 0x050, 0x054, 0x058, 16, 1, 23, - 0x1C0, 22), - MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, - 0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23), - /* CLK_CFG_6 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_CONN_MCUSYS_SEL, "conn_mcusys_sel", - conn_mcusys_parents, 0x060, 0x064, 0x068, 0, 1, 7, - 0x1C0, 24), - MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP_B_SEL, "eip_b_sel", eip_b_parents, - 0x060, 0x064, 0x068, 8, 1, 15, 0x1C0, 25), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_PHY_SEL, "pcie_phy_sel", - f_26m_adc_parents, 0x060, 0x064, 0x068, 16, 1, 23, - 0x1C0, 26), - MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel", - f_26m_adc_parents, 0x060, 0x064, 0x068, 24, 1, 31, - 0x1C0, 27), - /* CLK_CFG_7 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_F26M_SEL, "csw_f26m_sel", - f_26m_adc_parents, 0x070, 0x074, 0x078, 0, 1, 7, - 0x1C0, 28), - MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, - 0x070, 0x074, 0x078, 8, 2, 15, 0x1C0, 29), - MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", - a_tuner_parents, 0x070, 0x074, 0x078, 16, 2, 23, - 0x1C0, 30), - MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", f_26m_adc_parents, - 0x070, 0x074, 0x078, 24, 1, 31, 0x1C4, 0), - /* CLK_CFG_8 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", - u2u3_sys_parents, 0x080, 0x084, 0x088, 0, 1, 7, - 0x1C4, 1), - MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", - u2u3_sys_parents, 0x080, 0x084, 0x088, 8, 1, 15, - 0x1C4, 2), - MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_U2_REFSEL, "da_u2_refsel", - da_u2_refsel_parents, 0x080, 0x084, 0x088, 16, 1, - 23, 0x1C4, 3), - MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_U2_CK_1P_SEL, "da_u2_ck_1p_sel", - da_u2_refsel_parents, 0x080, 0x084, 0x088, 24, 1, - 31, 0x1C4, 4), - /* CLK_CFG_9 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", - sgm_reg_parents, 0x090, 0x094, 0x098, 0, 1, 7, - 0x1C4, 5), -}; - -static int clk_mt7986_topckgen_probe(struct platform_device *pdev) -{ - struct clk_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - void __iomem *base; - int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) + - ARRAY_SIZE(top_muxes); - - base = of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return -ENOMEM; - } - - clk_data = mtk_alloc_clk_data(nr); - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), - clk_data); - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); - mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node, - &mt7986_clk_lock, clk_data); - - clk_prepare_enable(clk_data->clks[CLK_TOP_SYSAXI_SEL]); - clk_prepare_enable(clk_data->clks[CLK_TOP_SYSAPB_SEL]); - clk_prepare_enable(clk_data->clks[CLK_TOP_DRAMC_SEL]); - clk_prepare_enable(clk_data->clks[CLK_TOP_DRAMC_MD32_SEL]); - clk_prepare_enable(clk_data->clks[CLK_TOP_F26M_SEL]); - clk_prepare_enable(clk_data->clks[CLK_TOP_SGM_REG_SEL]); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_topckgen_data; - } - return r; - -free_topckgen_data: - mtk_free_clk_data(clk_data); - return r; -} - -static const struct of_device_id of_match_clk_mt7986_topckgen[] = { - { .compatible = "mediatek,mt7986-topckgen", }, - {} -}; - -static struct platform_driver clk_mt7986_topckgen_drv = { - .probe = clk_mt7986_topckgen_probe, - .driver = { - .name = "clk-mt7986-topckgen", - .of_match_table = of_match_clk_mt7986_topckgen, - }, -}; -builtin_platform_driver(clk_mt7986_topckgen_drv); diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-apmixed.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-apmixed.c index 587b70767eb..3f1edc231e3 100644 --- a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-apmixed.c +++ b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-apmixed.c @@ -13,6 +13,7 @@ #include "clk-mtk.h" #include "clk-gate.h" #include "clk-mux.h" +#include "clk-pll.h" #include #define MT7988_PLL_FMAX (2500UL * MHZ) @@ -72,15 +73,13 @@ static const struct mtk_pll_data plls[] = { }; static const struct of_device_id of_match_clk_mt7988_apmixed[] = { - { - .compatible = "mediatek,mt7988-apmixedsys", - }, - {} + { .compatible = "mediatek,mt7988-apmixedsys", }, + { /* sentinel */ } }; static int clk_mt7988_apmixed_probe(struct platform_device *pdev) { - struct clk_onecell_data *clk_data; + struct clk_hw_onecell_data *clk_data; struct device_node *node = pdev->dev.of_node; int r; @@ -90,7 +89,7 @@ static int clk_mt7988_apmixed_probe(struct platform_device *pdev) mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) { pr_err("%s(): could not register clock provider: %d\n", __func__, r); @@ -111,3 +110,4 @@ static struct platform_driver clk_mt7988_apmixed_drv = { }, }; builtin_platform_driver(clk_mt7988_apmixed_drv); +MODULE_LICENSE("GPL"); diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-eth.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-eth.c index 341d0f73fd3..14b877f8cb0 100644 --- a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-eth.c +++ b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-eth.c @@ -40,39 +40,10 @@ static const struct mtk_gate ethdma_clks[] = { 29), }; -static int clk_mt7988_ethsys_probe(struct platform_device *pdev) -{ - struct clk_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - void __iomem *base; - - base = of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return -ENOMEM; - } - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(ethdma_clks)); - - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_gates(node, ethdma_clks, ARRAY_SIZE(ethdma_clks), - clk_data); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_data; - } - return r; - -free_data: - mtk_free_clk_data(clk_data); - return r; -} +static const struct mtk_clk_desc ethdma_desc = { + .clks = ethdma_clks, + .num_clks = ARRAY_SIZE(ethdma_clks), +}; static const struct mtk_gate_regs sgmii0_cg_regs = { .set_ofs = 0xe4, @@ -92,39 +63,10 @@ static const struct mtk_gate sgmii0_clks[] = { GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "top_xtal", 3), }; -static int clk_mt7988_sgmii0_probe(struct platform_device *pdev) -{ - struct clk_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - void __iomem *base; - - base = of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return -ENOMEM; - } - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks)); - - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks), - clk_data); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_data; - } - return r; - -free_data: - mtk_free_clk_data(clk_data); - return r; -} +static const struct mtk_clk_desc sgmii0_desc = { + .clks = sgmii0_clks, + .num_clks = ARRAY_SIZE(sgmii0_clks), +}; static const struct mtk_gate_regs sgmii1_cg_regs = { .set_ofs = 0xe4, @@ -144,39 +86,10 @@ static const struct mtk_gate sgmii1_clks[] = { GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "top_xtal", 3), }; -static int clk_mt7988_sgmii1_probe(struct platform_device *pdev) -{ - struct clk_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - void __iomem *base; - - base = of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return -ENOMEM; - } - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks)); - - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks), - clk_data); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_data; - } - return r; - -free_data: - mtk_free_clk_data(clk_data); - return r; -} +static const struct mtk_clk_desc sgmii1_desc = { + .clks = sgmii1_clks, + .num_clks = ARRAY_SIZE(sgmii1_clks), +}; static const struct mtk_gate_regs ethwarp_cg_regs = { .set_ofs = 0x14, @@ -200,100 +113,29 @@ static const struct mtk_gate ethwarp_clks[] = { "netsys_mcu_sel", 15), }; -static int clk_mt7988_ethwarp_probe(struct platform_device *pdev) -{ - struct clk_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - void __iomem *base; - - base = of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return -ENOMEM; - } - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(ethwarp_clks)); - - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_gates(node, ethwarp_clks, ARRAY_SIZE(ethwarp_clks), - clk_data); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_data; - } - return r; - -free_data: - mtk_free_clk_data(clk_data); - return r; -} - -static const struct of_device_id of_match_clk_mt7988_ethsys[] = { - { - .compatible = "mediatek,mt7988-ethsys", - }, - {} +static const struct mtk_clk_desc ethwarp_desc = { + .clks = ethwarp_clks, + .num_clks = ARRAY_SIZE(ethwarp_clks), }; -static struct platform_driver clk_mt7988_ethsys_drv = { - .probe = clk_mt7988_ethsys_probe, +static const struct of_device_id of_match_clk_mt7986_eth[] = { + { .compatible = "mediatek,mt7988-ethsys", .data = ðdma_desc }, + { .compatible = "mediatek,mt7988-sgmiisys_0", .data = &sgmii0_desc }, + { .compatible = "mediatek,mt7988-sgmiisys_1", .data = &sgmii1_desc }, + { .compatible = "mediatek,mt7988-ethwarp", .data = ðwarp_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_eth); + +static struct platform_driver clk_mt7988_eth_drv = { .driver = { - .name = "clk-mt7988-ethsys", - .of_match_table = of_match_clk_mt7988_ethsys, + .name = "clk-mt7988-eth", + .of_match_table = of_match_clk_mt7986_eth, }, + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, }; -builtin_platform_driver(clk_mt7988_ethsys_drv); +module_platform_driver(clk_mt7988_eth_drv); -static const struct of_device_id of_match_clk_mt7988_sgmii0[] = { - { - .compatible = "mediatek,mt7988-sgmiisys_0", - }, - {} -}; - -static struct platform_driver clk_mt7988_sgmii0_drv = { - .probe = clk_mt7988_sgmii0_probe, - .driver = { - .name = "clk-mt7988-sgmiisys_0", - .of_match_table = of_match_clk_mt7988_sgmii0, - }, -}; -builtin_platform_driver(clk_mt7988_sgmii0_drv); - -static const struct of_device_id of_match_clk_mt7988_sgmii1[] = { - { - .compatible = "mediatek,mt7988-sgmiisys_1", - }, - {} -}; - -static struct platform_driver clk_mt7988_sgmii1_drv = { - .probe = clk_mt7988_sgmii1_probe, - .driver = { - .name = "clk-mt7988-sgmiisys_1", - .of_match_table = of_match_clk_mt7988_sgmii1, - }, -}; -builtin_platform_driver(clk_mt7988_sgmii1_drv); - -static const struct of_device_id of_match_clk_mt7988_ethwarp[] = { - { - .compatible = "mediatek,mt7988-ethwarp", - }, - {} -}; - -static struct platform_driver clk_mt7988_ethwarp_drv = { - .probe = clk_mt7988_ethwarp_probe, - .driver = { - .name = "clk-mt7988-ethwarp", - .of_match_table = of_match_clk_mt7988_ethwarp, - }, -}; -builtin_platform_driver(clk_mt7988_ethwarp_drv); \ No newline at end of file +MODULE_DESCRIPTION("MediaTek MT7988 Ethernet clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-infracfg.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-infracfg.c index 77e25383b6e..111b516ae56 100644 --- a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-infracfg.c +++ b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-infracfg.c @@ -344,56 +344,26 @@ static const struct mtk_gate infra_clks[] = { "sysaxi_sel", 31), }; -static int clk_mt7988_infracfg_probe(struct platform_device *pdev) -{ - struct clk_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - void __iomem *base; - int nr = ARRAY_SIZE(infra_muxes) + ARRAY_SIZE(infra_clks); - - base = of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return -ENOMEM; - } - - clk_data = mtk_alloc_clk_data(nr); - - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node, - &mt7988_clk_lock, clk_data); - - mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_infracfg_data; - } - return r; - -free_infracfg_data: - mtk_free_clk_data(clk_data); - return r; -} - -static const struct of_device_id of_match_clk_mt7988_infracfg[] = { - { - .compatible = "mediatek,mt7988-infracfg", - }, - {} +static const struct mtk_clk_desc infra_desc = { + .clks = infra_clks, + .num_clks = ARRAY_SIZE(infra_clks), + .mux_clks = infra_muxes, + .num_mux_clks = ARRAY_SIZE(infra_muxes), + .clk_lock = &mt7988_clk_lock, }; +static const struct of_device_id of_match_clk_mt7988_infracfg[] = { + { .compatible = "mediatek,mt7988-infracfg", .data = &infra_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_infracfg); + static struct platform_driver clk_mt7988_infracfg_drv = { - .probe = clk_mt7988_infracfg_probe, .driver = { .name = "clk-mt7988-infracfg", .of_match_table = of_match_clk_mt7988_infracfg, }, + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, }; -builtin_platform_driver(clk_mt7988_infracfg_drv); +module_platform_driver(clk_mt7988_infracfg_drv); diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-topckgen.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-topckgen.c index 917302b6df6..b0745d65089 100644 --- a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-topckgen.c +++ b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-topckgen.c @@ -395,49 +395,17 @@ static const struct mtk_composite top_aud_divs[] = { 8, 8), }; -static int clk_mt7988_topckgen_probe(struct platform_device *pdev) -{ - struct clk_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - void __iomem *base; - int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) + - ARRAY_SIZE(top_muxes) + ARRAY_SIZE(top_aud_divs); - - base = of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return -ENOMEM; - } - - clk_data = mtk_alloc_clk_data(nr); - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), - clk_data); - - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); - - mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node, - &mt7988_clk_lock, clk_data); - - mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs), - base, &mt7988_clk_lock, clk_data); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_topckgen_data; - } - return r; - -free_topckgen_data: - mtk_free_clk_data(clk_data); - return r; -} +static const struct mtk_clk_desc topck_desc = { + .fixed_clks = top_fixed_clks, + .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), + .factor_clks = top_divs, + .num_factor_clks = ARRAY_SIZE(top_divs), + .mux_clks = top_muxes, + .num_mux_clks = ARRAY_SIZE(top_muxes), + .composite_clks = top_aud_divs, + .num_composite_clks = ARRAY_SIZE(top_aud_divs), + .clk_lock = &mt7988_clk_lock, +}; static const char *const mcu_bus_div_parents[] = { "top_xtal", "ccipll2_b", "net1pll_d4" }; @@ -454,69 +422,25 @@ static struct mtk_composite mcu_muxes[] = { mcu_arm_div_parents, 0x7A8, 9, 2, -1, CLK_IS_CRITICAL), }; -static int clk_mt7988_mcusys_probe(struct platform_device *pdev) -{ - struct clk_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - void __iomem *base; - int nr = ARRAY_SIZE(mcu_muxes); - - base = of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return -ENOMEM; - } - - clk_data = mtk_alloc_clk_data(nr); - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base, - &mt7988_clk_lock, clk_data); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_mcusys_data; - } - return r; - -free_mcusys_data: - mtk_free_clk_data(clk_data); - return r; -} - -static const struct of_device_id of_match_clk_mt7988_topckgen[] = { - { - .compatible = "mediatek,mt7988-topckgen", - }, - {} +static const struct mtk_clk_desc mcusys_desc = { + .composite_clks = mcu_muxes, + .num_composite_clks = ARRAY_SIZE(mcu_muxes), }; +static const struct of_device_id of_match_clk_mt7988_topckgen[] = { + { .compatible = "mediatek,mt7988-topckgen", .data = &topck_desc }, + { .compatible = "mediatek,mt7988-mcusys", .data = &mcusys_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_topckgen); + static struct platform_driver clk_mt7988_topckgen_drv = { - .probe = clk_mt7988_topckgen_probe, + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt7988-topckgen", .of_match_table = of_match_clk_mt7988_topckgen, }, }; -builtin_platform_driver(clk_mt7988_topckgen_drv); - -static const struct of_device_id of_match_clk_mt7988_mcusys[] = { - { - .compatible = "mediatek,mt7988-mcusys", - }, - {} -}; - -static struct platform_driver clk_mt7988_mcusys_drv = { - .probe = clk_mt7988_mcusys_probe, - .driver = { - .name = "clk-mt7988-mcusys", - .of_match_table = of_match_clk_mt7988_mcusys, - }, -}; -builtin_platform_driver(clk_mt7988_mcusys_drv); \ No newline at end of file +module_platform_driver(clk_mt7988_topckgen_drv); +MODULE_LICENSE("GPL"); diff --git a/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-ge-soc.c b/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-ge-soc.c deleted file mode 100644 index e48502ac3fd..00000000000 --- a/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-ge-soc.c +++ /dev/null @@ -1,1263 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -#include -#include -#include -#include -#include -#include -#include - -#define MTK_GPHY_ID_MT7981 0x03a29461 -#define MTK_GPHY_ID_MT7988 0x03a29481 - -#define MTK_EXT_PAGE_ACCESS 0x1f -#define MTK_PHY_PAGE_STANDARD 0x0000 -#define MTK_PHY_PAGE_EXTENDED_3 0x0003 - -#define MTK_PHY_LPI_REG_14 0x14 -#define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0) - -#define MTK_PHY_LPI_REG_1c 0x1c -#define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8) - -#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 -#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 - -#define ANALOG_INTERNAL_OPERATION_MAX_US 20 -#define TXRESERVE_MIN 0 -#define TXRESERVE_MAX 7 - -#define MTK_PHY_ANARG_RG 0x10 -#define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8) - -/* Registers on MDIO_MMD_VEND1 */ -#define MTK_PHY_TXVLD_DA_RG 0x12 -#define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10) -#define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0) - -#define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16 -#define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10) -#define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0) - -#define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17 -#define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8) -#define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0) - -#define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18 -#define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8) -#define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0) - -#define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19 -#define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8) -#define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0) - -#define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20 -#define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8) -#define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0) - -#define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21 -#define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8) -#define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0) - -#define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22 -#define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8) -#define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0) - -#define MTK_PHY_RXADC_CTRL_RG7 0xc6 -#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8) - -#define MTK_PHY_RXADC_CTRL_RG9 0xc8 -#define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12) -#define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8) -#define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4) -#define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0) - -#define MTK_PHY_LDO_OUTPUT_V 0xd7 - -#define MTK_PHY_RG_ANA_CAL_RG0 0xdb -#define MTK_PHY_RG_CAL_CKINV BIT(12) -#define MTK_PHY_RG_ANA_CALEN BIT(8) -#define MTK_PHY_RG_ZCALEN_A BIT(0) - -#define MTK_PHY_RG_ANA_CAL_RG1 0xdc -#define MTK_PHY_RG_ZCALEN_B BIT(12) -#define MTK_PHY_RG_ZCALEN_C BIT(8) -#define MTK_PHY_RG_ZCALEN_D BIT(4) -#define MTK_PHY_RG_TXVOS_CALEN BIT(0) - -#define MTK_PHY_RG_ANA_CAL_RG5 0xe0 -#define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8) - -#define MTK_PHY_RG_TX_FILTER 0xfe - -#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120 -#define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8) -#define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0) - -#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122 -#define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0) - -#define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144 -#define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5) - -#define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172 -#define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8) -#define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0) - -#define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173 -#define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8) -#define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0) - -#define MTK_PHY_RG_AD_CAL_COMP 0x17a -#define MTK_PHY_AD_CAL_COMP_OUT_SHIFT (8) - -#define MTK_PHY_RG_AD_CAL_CLK 0x17b -#define MTK_PHY_DA_CAL_CLK BIT(0) - -#define MTK_PHY_RG_AD_CALIN 0x17c -#define MTK_PHY_DA_CALIN_FLAG BIT(0) - -#define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d -#define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0) - -#define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e -#define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0) - -#define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f -#define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0) - -#define MTK_PHY_RG_DASN_DAC_IN0_D 0x180 -#define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0) - -#define MTK_PHY_RG_DASN_DAC_IN1_A 0x181 -#define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0) - -#define MTK_PHY_RG_DASN_DAC_IN1_B 0x182 -#define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0) - -#define MTK_PHY_RG_DASN_DAC_IN1_C 0x183 -#define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0) - -#define MTK_PHY_RG_DASN_DAC_IN1_D 0x184 -#define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0) - -#define MTK_PHY_RG_DEV1E_REG19b 0x19b -#define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8) - -#define MTK_PHY_RG_LP_IIR2_K1_L 0x22a -#define MTK_PHY_RG_LP_IIR2_K1_U 0x22b -#define MTK_PHY_RG_LP_IIR2_K2_L 0x22c -#define MTK_PHY_RG_LP_IIR2_K2_U 0x22d -#define MTK_PHY_RG_LP_IIR2_K3_L 0x22e -#define MTK_PHY_RG_LP_IIR2_K3_U 0x22f -#define MTK_PHY_RG_LP_IIR2_K4_L 0x230 -#define MTK_PHY_RG_LP_IIR2_K4_U 0x231 -#define MTK_PHY_RG_LP_IIR2_K5_L 0x232 -#define MTK_PHY_RG_LP_IIR2_K5_U 0x233 - -#define MTK_PHY_RG_DEV1E_REG234 0x234 -#define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0) -#define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4) -#define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12) - -#define MTK_PHY_RG_LPF_CNT_VAL 0x235 - -#define MTK_PHY_RG_DEV1E_REG238 0x238 -#define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0) -#define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12) - -#define MTK_PHY_RG_DEV1E_REG239 0x239 -#define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0) -#define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12) - -#define MTK_PHY_RG_DEV1E_REG27C 0x27c -#define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8) -#define MTK_PHY_RG_DEV1E_REG27D 0x27d -#define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0) - -#define MTK_PHY_RG_DEV1E_REG2C7 0x2c7 -#define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0) -#define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8) - -#define MTK_PHY_RG_DEV1E_REG2D1 0x2d1 -#define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0) -#define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8) -#define MTK_PHY_LPI_TR_READY BIT(9) -#define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10) - -#define MTK_PHY_RG_DEV1E_REG323 0x323 -#define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0) -#define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4) - -#define MTK_PHY_RG_DEV1E_REG324 0x324 -#define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0) -#define MTK_PHY_SMI_DET_MAX_EN BIT(8) - -#define MTK_PHY_RG_DEV1E_REG326 0x326 -#define MTK_PHY_LPI_MODE_SD_ON BIT(0) -#define MTK_PHY_RESET_RANDUPD_CNT BIT(1) -#define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2) -#define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4) -#define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5) - -#define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502 -#define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503 - -#define MTK_PHY_DA_TX_R50_PAIR_A 0x53d -#define MTK_PHY_DA_TX_R50_PAIR_B 0x53e -#define MTK_PHY_DA_TX_R50_PAIR_C 0x53f -#define MTK_PHY_DA_TX_R50_PAIR_D 0x540 - -/* Registers on MDIO_MMD_VEND2 */ -#define MTK_PHY_LED0_ON_CTRL 0x24 -#define MTK_PHY_LED0_ON_MASK GENMASK(6, 0) -#define MTK_PHY_LED0_ON_LINK1000 BIT(0) -#define MTK_PHY_LED0_ON_LINK100 BIT(1) -#define MTK_PHY_LED0_ON_LINK10 BIT(2) -#define MTK_PHY_LED0_ON_LINKDOWN BIT(3) -#define MTK_PHY_LED0_ON_FDX BIT(4) /* Full duplex */ -#define MTK_PHY_LED0_ON_HDX BIT(5) /* Half duplex */ -#define MTK_PHY_LED0_FORCE_ON BIT(6) -#define MTK_PHY_LED0_POLARITY BIT(14) -#define MTK_PHY_LED0_ENABLE BIT(15) - -#define MTK_PHY_LED0_BLINK_CTRL 0x25 -#define MTK_PHY_LED0_1000TX BIT(0) -#define MTK_PHY_LED0_1000RX BIT(1) -#define MTK_PHY_LED0_100TX BIT(2) -#define MTK_PHY_LED0_100RX BIT(3) -#define MTK_PHY_LED0_10TX BIT(4) -#define MTK_PHY_LED0_10RX BIT(5) -#define MTK_PHY_LED0_COLLISION BIT(6) -#define MTK_PHY_LED0_RX_CRC_ERR BIT(7) -#define MTK_PHY_LED0_RX_IDLE_ERR BIT(8) -#define MTK_PHY_LED0_FORCE_BLINK BIT(9) - -#define MTK_PHY_LED1_ON_CTRL 0x26 -#define MTK_PHY_LED1_ON_MASK GENMASK(6, 0) -#define MTK_PHY_LED1_ON_LINK1000 BIT(0) -#define MTK_PHY_LED1_ON_LINK100 BIT(1) -#define MTK_PHY_LED1_ON_LINK10 BIT(2) -#define MTK_PHY_LED1_ON_LINKDOWN BIT(3) -#define MTK_PHY_LED1_ON_FDX BIT(4) /* Full duplex */ -#define MTK_PHY_LED1_ON_HDX BIT(5) /* Half duplex */ -#define MTK_PHY_LED1_FORCE_ON BIT(6) -#define MTK_PHY_LED1_POLARITY BIT(14) -#define MTK_PHY_LED1_ENABLE BIT(15) - -#define MTK_PHY_LED1_BLINK_CTRL 0x27 -#define MTK_PHY_LED1_1000TX BIT(0) -#define MTK_PHY_LED1_1000RX BIT(1) -#define MTK_PHY_LED1_100TX BIT(2) -#define MTK_PHY_LED1_100RX BIT(3) -#define MTK_PHY_LED1_10TX BIT(4) -#define MTK_PHY_LED1_10RX BIT(5) -#define MTK_PHY_LED1_COLLISION BIT(6) -#define MTK_PHY_LED1_RX_CRC_ERR BIT(7) -#define MTK_PHY_LED1_RX_IDLE_ERR BIT(8) -#define MTK_PHY_LED1_FORCE_BLINK BIT(9) - -#define MTK_PHY_RG_BG_RASEL 0x115 -#define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0) - -/* These macro privides efuse parsing for internal phy. */ -#define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0)) -#define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0)) -#define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0)) -#define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0)) -#define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0)) - -#define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0)) -#define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0)) -#define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0)) -#define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0)) -#define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0)) - -#define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0)) -#define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0)) - -#define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0)) -#define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0)) - -enum { - NO_PAIR, - PAIR_A, - PAIR_B, - PAIR_C, - PAIR_D, -}; - -enum { - GPHY_PORT0, - GPHY_PORT1, - GPHY_PORT2, - GPHY_PORT3, -}; - -enum calibration_mode { - EFUSE_K, - SW_K -}; - -enum CAL_ITEM { - REXT, - TX_OFFSET, - TX_AMP, - TX_R50, - TX_VCM -}; - -enum CAL_MODE { - EFUSE_M, - SW_M -}; - -struct mtk_socphy_shared_priv { - u32 boottrap; -}; - -static int mtk_socphy_read_page(struct phy_device *phydev) -{ - return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); -} - -static int mtk_socphy_write_page(struct phy_device *phydev, int page) -{ - return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); -} - -/* One calibration cycle consists of: - * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high - * until AD_CAL_COMP is ready to output calibration result. - * 2.Wait until DA_CAL_CLK is available. - * 3.Fetch AD_CAL_COMP_OUT. - */ -static int cal_cycle(struct phy_device *phydev, int devad, - u32 regnum, u16 mask, u16 cal_val) -{ - int reg_val; - int ret; - - phy_modify_mmd(phydev, devad, regnum, - mask, cal_val); - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, - MTK_PHY_DA_CALIN_FLAG); - - ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_AD_CAL_CLK, reg_val, - reg_val & MTK_PHY_DA_CAL_CLK, 500, - ANALOG_INTERNAL_OPERATION_MAX_US, false); - if (ret) { - phydev_err(phydev, "Calibration cycle timeout\n"); - return ret; - } - - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, - MTK_PHY_DA_CALIN_FLAG); - ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >> - MTK_PHY_AD_CAL_COMP_OUT_SHIFT; - phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); - - return ret; -} - -static int rext_fill_result(struct phy_device *phydev, u16 *buf) -{ - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, - MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8); - phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL, - MTK_PHY_RG_BG_RASEL_MASK, buf[1]); - - return 0; -} - -static int rext_cal_efuse(struct phy_device *phydev, u32 *buf) -{ - u16 rext_cal_val[2]; - - rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]); - rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]); - rext_fill_result(phydev, rext_cal_val); - - return 0; -} - -static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf) -{ - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, - MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, - MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, - MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, - MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]); - - return 0; -} - -static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf) -{ - u16 tx_offset_cal_val[4]; - - tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]); - tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]); - tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]); - tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]); - - tx_offset_fill_result(phydev, tx_offset_cal_val); - - return 0; -} - -static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf) -{ - int i; - int bias[16] = {}; - const int vals_9461[16] = { 7, 1, 4, 7, - 7, 1, 4, 7, - 7, 1, 4, 7, - 7, 1, 4, 7 }; - const int vals_9481[16] = { 10, 6, 6, 10, - 10, 6, 6, 10, - 10, 6, 6, 10, - 10, 6, 6, 10 }; - switch (phydev->drv->phy_id) { - case MTK_GPHY_ID_MT7981: - /* We add some calibration to efuse values - * due to board level influence. - * GBE: +7, TBT: +1, HBT: +4, TST: +7 - */ - memcpy(bias, (const void *)vals_9461, sizeof(bias)); - break; - case MTK_GPHY_ID_MT7988: - memcpy(bias, (const void *)vals_9481, sizeof(bias)); - break; - } - - /* Prevent overflow */ - for (i = 0; i < 12; i++) { - if (buf[i >> 2] + bias[i] > 63) { - buf[i >> 2] = 63; - bias[i] = 0; - } - } - - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, - MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, - MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, - MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, - MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]); - - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, - MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, (buf[1] + bias[4]) << 8); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, - MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, buf[1] + bias[5]); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, - MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, - MTK_PHY_DA_TX_I2MPB_B_TST_MASK, buf[1] + bias[7]); - - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, - MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, (buf[2] + bias[8]) << 8); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, - MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, buf[2] + bias[9]); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, - MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, (buf[2] + bias[10]) << 8); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, - MTK_PHY_DA_TX_I2MPB_C_TST_MASK, buf[2] + bias[11]); - - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, - MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, - MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, buf[3] + bias[13]); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, - MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, (buf[3] + bias[14]) << 8); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, - MTK_PHY_DA_TX_I2MPB_D_TST_MASK, buf[3] + bias[15]); - - return 0; -} - -static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf) -{ - u16 tx_amp_cal_val[4]; - - tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]); - tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]); - tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]); - tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]); - tx_amp_fill_result(phydev, tx_amp_cal_val); - - return 0; -} - -static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val, - u8 txg_calen_x) -{ - int bias = 0; - u16 reg, val; - - if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988) - bias = -2; - - val = clamp_val(bias + tx_r50_cal_val, 0, 63); - - switch (txg_calen_x) { - case PAIR_A: - reg = MTK_PHY_DA_TX_R50_PAIR_A; - break; - case PAIR_B: - reg = MTK_PHY_DA_TX_R50_PAIR_B; - break; - case PAIR_C: - reg = MTK_PHY_DA_TX_R50_PAIR_C; - break; - case PAIR_D: - reg = MTK_PHY_DA_TX_R50_PAIR_D; - break; - default: - return -EINVAL; - } - - phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8); - - return 0; -} - -static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf, - u8 txg_calen_x) -{ - u16 tx_r50_cal_val; - - switch (txg_calen_x) { - case PAIR_A: - tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]); - break; - case PAIR_B: - tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]); - break; - case PAIR_C: - tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]); - break; - case PAIR_D: - tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]); - break; - default: - return -EINVAL; - } - tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x); - - return 0; -} - -static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x) -{ - u8 lower_idx, upper_idx, txreserve_val; - u8 lower_ret, upper_ret; - int ret; - - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, - MTK_PHY_RG_ANA_CALEN); - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, - MTK_PHY_RG_CAL_CKINV); - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, - MTK_PHY_RG_TXVOS_CALEN); - - switch (rg_txreserve_x) { - case PAIR_A: - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_DASN_DAC_IN0_A, - MTK_PHY_DASN_DAC_IN0_A_MASK); - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_DASN_DAC_IN1_A, - MTK_PHY_DASN_DAC_IN1_A_MASK); - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_ANA_CAL_RG0, - MTK_PHY_RG_ZCALEN_A); - break; - case PAIR_B: - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_DASN_DAC_IN0_B, - MTK_PHY_DASN_DAC_IN0_B_MASK); - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_DASN_DAC_IN1_B, - MTK_PHY_DASN_DAC_IN1_B_MASK); - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_ANA_CAL_RG1, - MTK_PHY_RG_ZCALEN_B); - break; - case PAIR_C: - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_DASN_DAC_IN0_C, - MTK_PHY_DASN_DAC_IN0_C_MASK); - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_DASN_DAC_IN1_C, - MTK_PHY_DASN_DAC_IN1_C_MASK); - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_ANA_CAL_RG1, - MTK_PHY_RG_ZCALEN_C); - break; - case PAIR_D: - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_DASN_DAC_IN0_D, - MTK_PHY_DASN_DAC_IN0_D_MASK); - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_DASN_DAC_IN1_D, - MTK_PHY_DASN_DAC_IN1_D_MASK); - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_ANA_CAL_RG1, - MTK_PHY_RG_ZCALEN_D); - break; - default: - ret = -EINVAL; - goto restore; - } - - lower_idx = TXRESERVE_MIN; - upper_idx = TXRESERVE_MAX; - - phydev_dbg(phydev, "Start TX-VCM SW cal.\n"); - while ((upper_idx - lower_idx) > 1) { - txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2); - ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, - MTK_PHY_DA_RX_PSBN_TBT_MASK | - MTK_PHY_DA_RX_PSBN_HBT_MASK | - MTK_PHY_DA_RX_PSBN_GBE_MASK | - MTK_PHY_DA_RX_PSBN_LP_MASK, - txreserve_val << 12 | txreserve_val << 8 | - txreserve_val << 4 | txreserve_val); - if (ret == 1) { - upper_idx = txreserve_val; - upper_ret = ret; - } else if (ret == 0) { - lower_idx = txreserve_val; - lower_ret = ret; - } else { - goto restore; - } - } - - if (lower_idx == TXRESERVE_MIN) { - lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1, - MTK_PHY_RXADC_CTRL_RG9, - MTK_PHY_DA_RX_PSBN_TBT_MASK | - MTK_PHY_DA_RX_PSBN_HBT_MASK | - MTK_PHY_DA_RX_PSBN_GBE_MASK | - MTK_PHY_DA_RX_PSBN_LP_MASK, - lower_idx << 12 | lower_idx << 8 | - lower_idx << 4 | lower_idx); - ret = lower_ret; - } else if (upper_idx == TXRESERVE_MAX) { - upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1, - MTK_PHY_RXADC_CTRL_RG9, - MTK_PHY_DA_RX_PSBN_TBT_MASK | - MTK_PHY_DA_RX_PSBN_HBT_MASK | - MTK_PHY_DA_RX_PSBN_GBE_MASK | - MTK_PHY_DA_RX_PSBN_LP_MASK, - upper_idx << 12 | upper_idx << 8 | - upper_idx << 4 | upper_idx); - ret = upper_ret; - } - if (ret < 0) - goto restore; - - /* We calibrate TX-VCM in different logic. Check upper index and then - * lower index. If this calibration is valid, apply lower index's result. - */ - ret = upper_ret - lower_ret; - if (ret == 1) { - ret = 0; - /* Make sure we use upper_idx in our calibration system */ - cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, - MTK_PHY_DA_RX_PSBN_TBT_MASK | - MTK_PHY_DA_RX_PSBN_HBT_MASK | - MTK_PHY_DA_RX_PSBN_GBE_MASK | - MTK_PHY_DA_RX_PSBN_LP_MASK, - upper_idx << 12 | upper_idx << 8 | - upper_idx << 4 | upper_idx); - phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx); - } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 && - lower_ret == 1) { - ret = 0; - cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, - MTK_PHY_DA_RX_PSBN_TBT_MASK | - MTK_PHY_DA_RX_PSBN_HBT_MASK | - MTK_PHY_DA_RX_PSBN_GBE_MASK | - MTK_PHY_DA_RX_PSBN_LP_MASK, - lower_idx << 12 | lower_idx << 8 | - lower_idx << 4 | lower_idx); - phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n", - lower_idx); - } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 && - lower_ret == 0) { - ret = 0; - phydev_warn(phydev, "TX-VCM SW cal result at high margin 0x%x\n", - upper_idx); - } else { - ret = -EINVAL; - } - -restore: - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, - MTK_PHY_RG_ANA_CALEN); - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, - MTK_PHY_RG_TXVOS_CALEN); - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, - MTK_PHY_RG_ZCALEN_A); - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, - MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C | - MTK_PHY_RG_ZCALEN_D); - - return ret; -} - -static void mt798x_phy_common_finetune(struct phy_device *phydev) -{ - phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); - /* EnabRandUpdTrig = 1 */ - __phy_write(phydev, 0x11, 0x2f00); - __phy_write(phydev, 0x12, 0xe); - __phy_write(phydev, 0x10, 0x8fb0); - - /* NormMseLoThresh = 85 */ - __phy_write(phydev, 0x11, 0x55a0); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x83aa); - - /* TrFreeze = 0 */ - __phy_write(phydev, 0x11, 0x0); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x9686); - - /* SSTrKp1000Slv = 5 */ - __phy_write(phydev, 0x11, 0xbaef); - __phy_write(phydev, 0x12, 0x2e); - __phy_write(phydev, 0x10, 0x968c); - - /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2, - * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2 - */ - __phy_write(phydev, 0x11, 0xd10a); - __phy_write(phydev, 0x12, 0x34); - __phy_write(phydev, 0x10, 0x8f82); - - /* VcoSlicerThreshBitsHigh */ - __phy_write(phydev, 0x11, 0x5555); - __phy_write(phydev, 0x12, 0x55); - __phy_write(phydev, 0x10, 0x8ec0); - phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); - - /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/ - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, - MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK, - BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); - - /* rg_tr_lpf_cnt_val = 512 */ - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200); - - /* IIR2 related */ - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82); - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0); - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103); - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0); - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82); - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0); - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177); - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3); - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82); - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe); - - /* FFE peaking */ - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C, - MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D, - MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e); - - /* Disable LDO pump */ - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0); - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0); - /* Adjust LDO output voltage */ - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222); -} - -static void mt7981_phy_finetune(struct phy_device *phydev) -{ - u16 val[8] = { 0x01ce, 0x01c1, - 0x020f, 0x0202, - 0x03d0, 0x03c0, - 0x0013, 0x0005 }; - int i, k; - - /* 100M eye finetune: - * Keep middle level of TX MLT3 shapper as default. - * Only change TX MLT3 overshoot level here. - */ - for (k = 0, i = 1; i < 12; i++) { - if (i % 3 == 0) - continue; - phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]); - } - - phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); - /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */ - __phy_write(phydev, 0x11, 0xc71); - __phy_write(phydev, 0x12, 0xc); - __phy_write(phydev, 0x10, 0x8fae); - - /* ResetSyncOffset = 6 */ - __phy_write(phydev, 0x11, 0x600); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x8fc0); - - /* VgaDecRate = 1 */ - __phy_write(phydev, 0x11, 0x4c2a); - __phy_write(phydev, 0x12, 0x3e); - __phy_write(phydev, 0x10, 0x8fa4); - - /* FfeUpdGainForce = 4 */ - __phy_write(phydev, 0x11, 0x240); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x9680); - - phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); -} - -static void mt7988_phy_finetune(struct phy_device *phydev) -{ - u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182, - 0x020d, 0x0206, 0x0384, 0x03d0, - 0x03c6, 0x030a, 0x0011, 0x0005 }; - int i; - - /* Set default MLT3 shaper first */ - for (i = 0; i < 12; i++) - phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]); - - /* TCT finetune */ - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5); - - /* Disable TX power saving */ - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, - MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8); - - phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); - - /* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */ - __phy_write(phydev, 0x11, 0x671); - __phy_write(phydev, 0x12, 0xc); - __phy_write(phydev, 0x10, 0x8fae); - - /* ResetSyncOffset = 5 */ - __phy_write(phydev, 0x11, 0x500); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x8fc0); - - /* VgaDecRate is 1 at default on mt7988 */ - - phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); - - phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30); - /* TxClkOffset = 2 */ - __phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK, - FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2)); - phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); -} - -static void mt798x_phy_eee(struct phy_device *phydev) -{ - phy_modify_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120, - MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK | - MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, - FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) | - FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14)); - - phy_modify_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, - MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, - FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, - 0xff)); - - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_TESTMUX_ADC_CTRL, - MTK_PHY_RG_TXEN_DIG_MASK); - - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY); - - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN); - - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238, - MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK | - MTK_PHY_LPI_SLV_SEND_TX_EN, - FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120)); - - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239, - MTK_PHY_LPI_SEND_LOC_TIMER_MASK | - MTK_PHY_LPI_TXPCS_LOC_RCV, - FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117)); - - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7, - MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK, - FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) | - FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13)); - - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1, - MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, - FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, - 0x33) | - MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY | - MTK_PHY_LPI_VCO_EEE_STG0_EN); - - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323, - MTK_PHY_EEE_WAKE_MAS_INT_DC | - MTK_PHY_EEE_WAKE_SLV_INT_DC); - - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324, - MTK_PHY_SMI_DETCNT_MAX_MASK, - FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) | - MTK_PHY_SMI_DET_MAX_EN); - - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326, - MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT | - MTK_PHY_TREC_UPDATE_ENAB_CLR | - MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF | - MTK_PHY_TR_READY_SKIP_AFE_WAKEUP); - - phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); - /* Regsigdet_sel_1000 = 0 */ - __phy_write(phydev, 0x11, 0xb); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x9690); - - /* REG_EEE_st2TrKf1000 = 3 */ - __phy_write(phydev, 0x11, 0x114f); - __phy_write(phydev, 0x12, 0x2); - __phy_write(phydev, 0x10, 0x969a); - - /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */ - __phy_write(phydev, 0x11, 0x3028); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x969e); - - /* RegEEE_slv_wake_int_timer_tar = 8 */ - __phy_write(phydev, 0x11, 0x5010); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x96a0); - - /* RegEEE_trfreeze_timer2 = 586 */ - __phy_write(phydev, 0x11, 0x24a); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x96a8); - - /* RegEEE100Stg1_tar = 16 */ - __phy_write(phydev, 0x11, 0x3210); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x96b8); - - /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */ - __phy_write(phydev, 0x11, 0x1463); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x96ca); - - /* DfeTailEnableVgaThresh1000 = 27 */ - __phy_write(phydev, 0x11, 0x36); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x8f80); - phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); - - phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3); - __phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000_MASK, - FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c)); - - __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK, - FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc)); - phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); - - phy_modify_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, - MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, - FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff)); -} - -static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item, - u8 start_pair, u8 end_pair) -{ - u8 pair_n; - int ret; - - for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { - /* TX_OFFSET & TX_AMP have no SW calibration. */ - switch (cal_item) { - case TX_VCM: - ret = tx_vcm_cal_sw(phydev, pair_n); - break; - default: - return -EINVAL; - } - if (ret) - return ret; - } - return 0; -} - -static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item, - u8 start_pair, u8 end_pair, u32 *buf) -{ - u8 pair_n; - int ret; - - for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { - /* TX_VCM has no efuse calibration. */ - switch (cal_item) { - case REXT: - ret = rext_cal_efuse(phydev, buf); - break; - case TX_OFFSET: - ret = tx_offset_cal_efuse(phydev, buf); - break; - case TX_AMP: - ret = tx_amp_cal_efuse(phydev, buf); - break; - case TX_R50: - ret = tx_r50_cal_efuse(phydev, buf, pair_n); - break; - default: - return -EINVAL; - } - if (ret) - return ret; - } - - return 0; -} - -static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item, - enum CAL_MODE cal_mode, u8 start_pair, - u8 end_pair, u32 *buf) -{ - int ret; - - switch (cal_mode) { - case EFUSE_M: - ret = cal_efuse(phydev, cal_item, start_pair, - end_pair, buf); - break; - case SW_M: - ret = cal_sw(phydev, cal_item, start_pair, end_pair); - break; - default: - return -EINVAL; - } - - if (ret) { - phydev_err(phydev, "cal %d failed\n", cal_item); - return -EIO; - } - - return 0; -} - -static int mt798x_phy_calibration(struct phy_device *phydev) -{ - int ret = 0; - u32 *buf; - size_t len; - struct nvmem_cell *cell; - - cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data"); - if (IS_ERR(cell)) { - if (PTR_ERR(cell) == -EPROBE_DEFER) - return PTR_ERR(cell); - return 0; - } - - buf = (u32 *)nvmem_cell_read(cell, &len); - if (IS_ERR(buf)) - return PTR_ERR(buf); - nvmem_cell_put(cell); - - if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) { - phydev_err(phydev, "invalid efuse data\n"); - ret = -EINVAL; - goto out; - } - - ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf); - if (ret) - goto out; - ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf); - if (ret) - goto out; - ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf); - if (ret) - goto out; - ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf); - if (ret) - goto out; - ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf); - if (ret) - goto out; - -out: - kfree(buf); - return ret; -} - -static int mt798x_phy_config_init(struct phy_device *phydev) -{ - switch (phydev->drv->phy_id) { - case MTK_GPHY_ID_MT7981: - mt7981_phy_finetune(phydev); - break; - case MTK_GPHY_ID_MT7988: - mt7988_phy_finetune(phydev); - break; - } - - mt798x_phy_common_finetune(phydev); - mt798x_phy_eee(phydev); - - return mt798x_phy_calibration(phydev); -} - -static int mt7988_phy_setup_led(struct phy_device *phydev) -{ - struct mtk_socphy_shared_priv *priv = phydev->shared->priv; - int port = phydev->mdio.addr; - u32 reg = priv->boottrap; - struct pinctrl *pinctrl; - - phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, - MTK_PHY_LED0_ENABLE | MTK_PHY_LED0_POLARITY | - MTK_PHY_LED0_ON_LINK10 | - MTK_PHY_LED0_ON_LINK100 | - MTK_PHY_LED0_ON_LINK1000); - phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL, - MTK_PHY_LED1_ENABLE | MTK_PHY_LED1_POLARITY | - MTK_PHY_LED1_ON_LINK10 | - MTK_PHY_LED1_ON_LINK100 | - MTK_PHY_LED1_ON_LINK1000); - - if ((port == GPHY_PORT0 && reg & BIT(8)) || - (port == GPHY_PORT1 && reg & BIT(9)) || - (port == GPHY_PORT2 && reg & BIT(10)) || - (port == GPHY_PORT3 && reg & BIT(11))) { - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, - MTK_PHY_LED0_POLARITY); - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL, - MTK_PHY_LED1_POLARITY); - } - - phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_BLINK_CTRL, - MTK_PHY_LED0_1000TX | MTK_PHY_LED0_1000RX | - MTK_PHY_LED0_100TX | MTK_PHY_LED0_100RX | - MTK_PHY_LED0_10TX | MTK_PHY_LED0_10RX); - phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_BLINK_CTRL, - MTK_PHY_LED1_1000TX | MTK_PHY_LED1_1000RX | - MTK_PHY_LED1_100TX | MTK_PHY_LED1_100RX | - MTK_PHY_LED1_10TX | MTK_PHY_LED1_10RX); - - pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led"); - if (IS_ERR(pinctrl)) { - dev_err(&phydev->mdio.bus->dev, "Failed to setup LED pins\n"); - return PTR_ERR(pinctrl); - } - - return 0; -} - -static int mt7988_phy_probe_shared(struct phy_device *phydev) -{ - struct mtk_socphy_shared_priv *priv = phydev->shared->priv; - void __iomem *boottrap; - struct device_node *np; - u32 reg; - - np = of_find_compatible_node(NULL, NULL, "mediatek,boottrap"); - if (!np) - return -ENOENT; - - boottrap = of_iomap(np, 0); - if (!boottrap) - return -ENOMEM; - - reg = readl(boottrap); - iounmap(boottrap); - - priv->boottrap = reg; - - return 0; -} - -static int mt7981_phy_probe(struct phy_device *phydev) -{ - return mt798x_phy_calibration(phydev); -} - -static int mt7988_phy_probe(struct phy_device *phydev) -{ - int err; - - err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0, - sizeof(struct mtk_socphy_shared_priv)); - if (err) - return err; - - if (phy_package_probe_once(phydev)) { - err = mt7988_phy_probe_shared(phydev); - if (err) - return err; - } - - mt7988_phy_setup_led(phydev); - - return mt798x_phy_calibration(phydev); -} - -static struct phy_driver mtk_socphy_driver[] = { - { - PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), - .name = "MediaTek MT7981 PHY", - .config_init = mt798x_phy_config_init, - .config_intr = genphy_no_config_intr, - .handle_interrupt = genphy_handle_interrupt_no_ack, - .probe = mt7981_phy_probe, - .suspend = genphy_suspend, - .resume = genphy_resume, - .read_page = mtk_socphy_read_page, - .write_page = mtk_socphy_write_page, - }, - { - PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988), - .name = "MediaTek MT7988 PHY", - .config_init = mt798x_phy_config_init, - .config_intr = genphy_no_config_intr, - .handle_interrupt = genphy_handle_interrupt_no_ack, - .probe = mt7988_phy_probe, - .suspend = genphy_suspend, - .resume = genphy_resume, - .read_page = mtk_socphy_read_page, - .write_page = mtk_socphy_write_page, - }, -}; - -module_phy_driver(mtk_socphy_driver); - -static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = { - { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) }, - { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) }, - { } -}; - -MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver"); -MODULE_AUTHOR("Daniel Golle "); -MODULE_AUTHOR("SkyLake Huang "); -MODULE_LICENSE("GPL"); - -MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl); diff --git a/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7981.c b/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7981.c deleted file mode 100644 index 18abc578001..00000000000 --- a/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7981.c +++ /dev/null @@ -1,1048 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * The MT7981 driver based on Linux generic pinctrl binding. - * - * Copyright (C) 2020 MediaTek Inc. - * Author: Sam Shih - */ - -#include "pinctrl-moore.h" - -#define MT7981_PIN(_number, _name) \ - MTK_PIN(_number, _name, 0, _number, DRV_GRP4) - -#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \ - PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ - _x_bits, 32, 0) - -#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \ - PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ - _x_bits, 32, 1) - -static const struct mtk_pin_field_calc mt7981_pin_mode_range[] = { - PIN_FIELD(0, 56, 0x300, 0x10, 0, 4), -}; - -static const struct mtk_pin_field_calc mt7981_pin_dir_range[] = { - PIN_FIELD(0, 56, 0x0, 0x10, 0, 1), -}; - -static const struct mtk_pin_field_calc mt7981_pin_di_range[] = { - PIN_FIELD(0, 56, 0x200, 0x10, 0, 1), -}; - -static const struct mtk_pin_field_calc mt7981_pin_do_range[] = { - PIN_FIELD(0, 56, 0x100, 0x10, 0, 1), -}; - -static const struct mtk_pin_field_calc mt7981_pin_ies_range[] = { - PIN_FIELD_BASE(0, 0, 1, 0x10, 0x10, 1, 1), - PIN_FIELD_BASE(1, 1, 1, 0x10, 0x10, 0, 1), - PIN_FIELD_BASE(2, 2, 5, 0x20, 0x10, 6, 1), - PIN_FIELD_BASE(3, 3, 4, 0x20, 0x10, 6, 1), - PIN_FIELD_BASE(4, 4, 4, 0x20, 0x10, 2, 1), - PIN_FIELD_BASE(5, 5, 4, 0x20, 0x10, 1, 1), - PIN_FIELD_BASE(6, 6, 4, 0x20, 0x10, 3, 1), - PIN_FIELD_BASE(7, 7, 4, 0x20, 0x10, 0, 1), - PIN_FIELD_BASE(8, 8, 4, 0x20, 0x10, 4, 1), - - PIN_FIELD_BASE(9, 9, 5, 0x20, 0x10, 9, 1), - PIN_FIELD_BASE(10, 10, 5, 0x20, 0x10, 8, 1), - PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1), - PIN_FIELD_BASE(12, 12, 5, 0x20, 0x10, 7, 1), - PIN_FIELD_BASE(13, 13, 5, 0x20, 0x10, 11, 1), - - PIN_FIELD_BASE(14, 14, 4, 0x20, 0x10, 8, 1), - - PIN_FIELD_BASE(15, 15, 2, 0x20, 0x10, 0, 1), - PIN_FIELD_BASE(16, 16, 2, 0x20, 0x10, 1, 1), - PIN_FIELD_BASE(17, 17, 2, 0x20, 0x10, 5, 1), - PIN_FIELD_BASE(18, 18, 2, 0x20, 0x10, 4, 1), - PIN_FIELD_BASE(19, 19, 2, 0x20, 0x10, 2, 1), - PIN_FIELD_BASE(20, 20, 2, 0x20, 0x10, 3, 1), - PIN_FIELD_BASE(21, 21, 2, 0x20, 0x10, 6, 1), - PIN_FIELD_BASE(22, 22, 2, 0x20, 0x10, 7, 1), - PIN_FIELD_BASE(23, 23, 2, 0x20, 0x10, 10, 1), - PIN_FIELD_BASE(24, 24, 2, 0x20, 0x10, 9, 1), - PIN_FIELD_BASE(25, 25, 2, 0x20, 0x10, 8, 1), - - PIN_FIELD_BASE(26, 26, 5, 0x20, 0x10, 0, 1), - PIN_FIELD_BASE(27, 27, 5, 0x20, 0x10, 4, 1), - PIN_FIELD_BASE(28, 28, 5, 0x20, 0x10, 3, 1), - PIN_FIELD_BASE(29, 29, 5, 0x20, 0x10, 1, 1), - PIN_FIELD_BASE(30, 30, 5, 0x20, 0x10, 2, 1), - PIN_FIELD_BASE(31, 31, 5, 0x20, 0x10, 5, 1), - - PIN_FIELD_BASE(32, 32, 1, 0x10, 0x10, 2, 1), - PIN_FIELD_BASE(33, 33, 1, 0x10, 0x10, 3, 1), - - PIN_FIELD_BASE(34, 34, 4, 0x20, 0x10, 5, 1), - PIN_FIELD_BASE(35, 35, 4, 0x20, 0x10, 7, 1), - - PIN_FIELD_BASE(36, 36, 3, 0x10, 0x10, 2, 1), - PIN_FIELD_BASE(37, 37, 3, 0x10, 0x10, 3, 1), - PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 0, 1), - PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 1, 1), - - PIN_FIELD_BASE(40, 40, 7, 0x30, 0x10, 1, 1), - PIN_FIELD_BASE(41, 41, 7, 0x30, 0x10, 0, 1), - PIN_FIELD_BASE(42, 42, 7, 0x30, 0x10, 9, 1), - PIN_FIELD_BASE(43, 43, 7, 0x30, 0x10, 7, 1), - PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1), - PIN_FIELD_BASE(45, 45, 7, 0x30, 0x10, 3, 1), - PIN_FIELD_BASE(46, 46, 7, 0x30, 0x10, 4, 1), - PIN_FIELD_BASE(47, 47, 7, 0x30, 0x10, 5, 1), - PIN_FIELD_BASE(48, 48, 7, 0x30, 0x10, 6, 1), - PIN_FIELD_BASE(49, 49, 7, 0x30, 0x10, 2, 1), - - PIN_FIELD_BASE(50, 50, 6, 0x10, 0x10, 0, 1), - PIN_FIELD_BASE(51, 51, 6, 0x10, 0x10, 2, 1), - PIN_FIELD_BASE(52, 52, 6, 0x10, 0x10, 3, 1), - PIN_FIELD_BASE(53, 53, 6, 0x10, 0x10, 4, 1), - PIN_FIELD_BASE(54, 54, 6, 0x10, 0x10, 5, 1), - PIN_FIELD_BASE(55, 55, 6, 0x10, 0x10, 6, 1), - PIN_FIELD_BASE(56, 56, 6, 0x10, 0x10, 1, 1), -}; - -static const struct mtk_pin_field_calc mt7981_pin_smt_range[] = { - PIN_FIELD_BASE(0, 0, 1, 0x60, 0x10, 1, 1), - PIN_FIELD_BASE(1, 1, 1, 0x60, 0x10, 0, 1), - PIN_FIELD_BASE(2, 2, 5, 0x90, 0x10, 6, 1), - PIN_FIELD_BASE(3, 3, 4, 0x80, 0x10, 6, 1), - PIN_FIELD_BASE(4, 4, 4, 0x80, 0x10, 2, 1), - PIN_FIELD_BASE(5, 5, 4, 0x80, 0x10, 1, 1), - PIN_FIELD_BASE(6, 6, 4, 0x80, 0x10, 3, 1), - PIN_FIELD_BASE(7, 7, 4, 0x80, 0x10, 0, 1), - PIN_FIELD_BASE(8, 8, 4, 0x80, 0x10, 4, 1), - - PIN_FIELD_BASE(9, 9, 5, 0x90, 0x10, 9, 1), - PIN_FIELD_BASE(10, 10, 5, 0x90, 0x10, 8, 1), - PIN_FIELD_BASE(11, 11, 5, 0x90, 0x10, 10, 1), - PIN_FIELD_BASE(12, 12, 5, 0x90, 0x10, 7, 1), - PIN_FIELD_BASE(13, 13, 5, 0x90, 0x10, 11, 1), - - PIN_FIELD_BASE(14, 14, 4, 0x80, 0x10, 8, 1), - - PIN_FIELD_BASE(15, 15, 2, 0x90, 0x10, 0, 1), - PIN_FIELD_BASE(16, 16, 2, 0x90, 0x10, 1, 1), - PIN_FIELD_BASE(17, 17, 2, 0x90, 0x10, 5, 1), - PIN_FIELD_BASE(18, 18, 2, 0x90, 0x10, 4, 1), - PIN_FIELD_BASE(19, 19, 2, 0x90, 0x10, 2, 1), - PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1), - PIN_FIELD_BASE(21, 21, 2, 0x90, 0x10, 6, 1), - PIN_FIELD_BASE(22, 22, 2, 0x90, 0x10, 7, 1), - PIN_FIELD_BASE(23, 23, 2, 0x90, 0x10, 10, 1), - PIN_FIELD_BASE(24, 24, 2, 0x90, 0x10, 9, 1), - PIN_FIELD_BASE(25, 25, 2, 0x90, 0x10, 8, 1), - - PIN_FIELD_BASE(26, 26, 5, 0x90, 0x10, 0, 1), - PIN_FIELD_BASE(27, 27, 5, 0x90, 0x10, 4, 1), - PIN_FIELD_BASE(28, 28, 5, 0x90, 0x10, 3, 1), - PIN_FIELD_BASE(29, 29, 5, 0x90, 0x10, 1, 1), - PIN_FIELD_BASE(30, 30, 5, 0x90, 0x10, 2, 1), - PIN_FIELD_BASE(31, 31, 5, 0x90, 0x10, 5, 1), - - PIN_FIELD_BASE(32, 32, 1, 0x60, 0x10, 2, 1), - PIN_FIELD_BASE(33, 33, 1, 0x60, 0x10, 3, 1), - - PIN_FIELD_BASE(34, 34, 4, 0x80, 0x10, 5, 1), - PIN_FIELD_BASE(35, 35, 4, 0x80, 0x10, 7, 1), - - PIN_FIELD_BASE(36, 36, 3, 0x60, 0x10, 2, 1), - PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 3, 1), - PIN_FIELD_BASE(38, 38, 3, 0x60, 0x10, 0, 1), - PIN_FIELD_BASE(39, 39, 3, 0x60, 0x10, 1, 1), - - PIN_FIELD_BASE(40, 40, 7, 0x70, 0x10, 1, 1), - PIN_FIELD_BASE(41, 41, 7, 0x70, 0x10, 0, 1), - PIN_FIELD_BASE(42, 42, 7, 0x70, 0x10, 9, 1), - PIN_FIELD_BASE(43, 43, 7, 0x70, 0x10, 7, 1), - PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1), - PIN_FIELD_BASE(45, 45, 7, 0x70, 0x10, 3, 1), - PIN_FIELD_BASE(46, 46, 7, 0x70, 0x10, 4, 1), - PIN_FIELD_BASE(47, 47, 7, 0x70, 0x10, 5, 1), - PIN_FIELD_BASE(48, 48, 7, 0x70, 0x10, 6, 1), - PIN_FIELD_BASE(49, 49, 7, 0x70, 0x10, 2, 1), - - PIN_FIELD_BASE(50, 50, 6, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(51, 51, 6, 0x50, 0x10, 2, 1), - PIN_FIELD_BASE(52, 52, 6, 0x50, 0x10, 3, 1), - PIN_FIELD_BASE(53, 53, 6, 0x50, 0x10, 4, 1), - PIN_FIELD_BASE(54, 54, 6, 0x50, 0x10, 5, 1), - PIN_FIELD_BASE(55, 55, 6, 0x50, 0x10, 6, 1), - PIN_FIELD_BASE(56, 56, 6, 0x50, 0x10, 1, 1), -}; - -static const struct mtk_pin_field_calc mt7981_pin_pu_range[] = { - PIN_FIELD_BASE(40, 40, 7, 0x50, 0x10, 1, 1), - PIN_FIELD_BASE(41, 41, 7, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(42, 42, 7, 0x50, 0x10, 9, 1), - PIN_FIELD_BASE(43, 43, 7, 0x50, 0x10, 7, 1), - PIN_FIELD_BASE(44, 44, 7, 0x50, 0x10, 8, 1), - PIN_FIELD_BASE(45, 45, 7, 0x50, 0x10, 3, 1), - PIN_FIELD_BASE(46, 46, 7, 0x50, 0x10, 4, 1), - PIN_FIELD_BASE(47, 47, 7, 0x50, 0x10, 5, 1), - PIN_FIELD_BASE(48, 48, 7, 0x50, 0x10, 6, 1), - PIN_FIELD_BASE(49, 49, 7, 0x50, 0x10, 2, 1), - - PIN_FIELD_BASE(50, 50, 6, 0x30, 0x10, 0, 1), - PIN_FIELD_BASE(51, 51, 6, 0x30, 0x10, 2, 1), - PIN_FIELD_BASE(52, 52, 6, 0x30, 0x10, 3, 1), - PIN_FIELD_BASE(53, 53, 6, 0x30, 0x10, 4, 1), - PIN_FIELD_BASE(54, 54, 6, 0x30, 0x10, 5, 1), - PIN_FIELD_BASE(55, 55, 6, 0x30, 0x10, 6, 1), - PIN_FIELD_BASE(56, 56, 6, 0x30, 0x10, 1, 1), -}; - -static const struct mtk_pin_field_calc mt7981_pin_pd_range[] = { - PIN_FIELD_BASE(40, 40, 7, 0x40, 0x10, 1, 1), - PIN_FIELD_BASE(41, 41, 7, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(42, 42, 7, 0x40, 0x10, 9, 1), - PIN_FIELD_BASE(43, 43, 7, 0x40, 0x10, 7, 1), - PIN_FIELD_BASE(44, 44, 7, 0x40, 0x10, 8, 1), - PIN_FIELD_BASE(45, 45, 7, 0x40, 0x10, 3, 1), - PIN_FIELD_BASE(46, 46, 7, 0x40, 0x10, 4, 1), - PIN_FIELD_BASE(47, 47, 7, 0x40, 0x10, 5, 1), - PIN_FIELD_BASE(48, 48, 7, 0x40, 0x10, 6, 1), - PIN_FIELD_BASE(49, 49, 7, 0x40, 0x10, 2, 1), - - PIN_FIELD_BASE(50, 50, 6, 0x20, 0x10, 0, 1), - PIN_FIELD_BASE(51, 51, 6, 0x20, 0x10, 2, 1), - PIN_FIELD_BASE(52, 52, 6, 0x20, 0x10, 3, 1), - PIN_FIELD_BASE(53, 53, 6, 0x20, 0x10, 4, 1), - PIN_FIELD_BASE(54, 54, 6, 0x20, 0x10, 5, 1), - PIN_FIELD_BASE(55, 55, 6, 0x20, 0x10, 6, 1), - PIN_FIELD_BASE(56, 56, 6, 0x20, 0x10, 1, 1), -}; - -static const struct mtk_pin_field_calc mt7981_pin_drv_range[] = { - PIN_FIELD_BASE(0, 0, 1, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(1, 1, 1, 0x00, 0x10, 0, 3), - - PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 18, 3), - - PIN_FIELD_BASE(3, 3, 4, 0x00, 0x10, 18, 1), - PIN_FIELD_BASE(4, 4, 4, 0x00, 0x10, 6, 1), - PIN_FIELD_BASE(5, 5, 4, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(6, 6, 4, 0x00, 0x10, 9, 3), - PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 12, 3), - - PIN_FIELD_BASE(9, 9, 5, 0x00, 0x10, 27, 3), - PIN_FIELD_BASE(10, 10, 5, 0x00, 0x10, 24, 3), - PIN_FIELD_BASE(11, 11, 5, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(12, 12, 5, 0x00, 0x10, 21, 3), - PIN_FIELD_BASE(13, 13, 5, 0x00, 0x10, 3, 3), - - PIN_FIELD_BASE(14, 14, 4, 0x00, 0x10, 27, 3), - - PIN_FIELD_BASE(15, 15, 2, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(16, 16, 2, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(17, 17, 2, 0x00, 0x10, 15, 3), - PIN_FIELD_BASE(18, 18, 2, 0x00, 0x10, 12, 3), - PIN_FIELD_BASE(19, 19, 2, 0x00, 0x10, 6, 3), - PIN_FIELD_BASE(20, 20, 2, 0x00, 0x10, 9, 3), - PIN_FIELD_BASE(21, 21, 2, 0x00, 0x10, 18, 3), - PIN_FIELD_BASE(22, 22, 2, 0x00, 0x10, 21, 3), - PIN_FIELD_BASE(23, 23, 2, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(24, 24, 2, 0x00, 0x10, 27, 3), - PIN_FIELD_BASE(25, 25, 2, 0x00, 0x10, 24, 3), - - PIN_FIELD_BASE(26, 26, 5, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(27, 27, 5, 0x00, 0x10, 12, 3), - PIN_FIELD_BASE(28, 28, 5, 0x00, 0x10, 9, 3), - PIN_FIELD_BASE(29, 29, 5, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(30, 30, 5, 0x00, 0x10, 6, 3), - PIN_FIELD_BASE(31, 31, 5, 0x00, 0x10, 15, 3), - - PIN_FIELD_BASE(32, 32, 1, 0x00, 0x10, 9, 3), - PIN_FIELD_BASE(33, 33, 1, 0x00, 0x10, 12, 3), - - PIN_FIELD_BASE(34, 34, 4, 0x00, 0x10, 15, 3), - PIN_FIELD_BASE(35, 35, 4, 0x00, 0x10, 21, 3), - - PIN_FIELD_BASE(36, 36, 3, 0x00, 0x10, 6, 3), - PIN_FIELD_BASE(37, 37, 3, 0x00, 0x10, 9, 3), - PIN_FIELD_BASE(38, 38, 3, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(39, 39, 3, 0x00, 0x10, 3, 3), - - PIN_FIELD_BASE(40, 40, 7, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(41, 41, 7, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(42, 42, 7, 0x00, 0x10, 27, 3), - PIN_FIELD_BASE(43, 43, 7, 0x00, 0x10, 21, 3), - PIN_FIELD_BASE(44, 44, 7, 0x00, 0x10, 24, 3), - PIN_FIELD_BASE(45, 45, 7, 0x00, 0x10, 9, 3), - PIN_FIELD_BASE(46, 46, 7, 0x00, 0x10, 12, 3), - PIN_FIELD_BASE(47, 47, 7, 0x00, 0x10, 15, 3), - PIN_FIELD_BASE(48, 48, 7, 0x00, 0x10, 18, 3), - PIN_FIELD_BASE(49, 49, 7, 0x00, 0x10, 6, 3), - - PIN_FIELD_BASE(50, 50, 6, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(51, 51, 6, 0x00, 0x10, 6, 3), - PIN_FIELD_BASE(52, 52, 6, 0x00, 0x10, 9, 3), - PIN_FIELD_BASE(53, 53, 6, 0x00, 0x10, 12, 3), - PIN_FIELD_BASE(54, 54, 6, 0x00, 0x10, 15, 3), - PIN_FIELD_BASE(55, 55, 6, 0x00, 0x10, 18, 3), - PIN_FIELD_BASE(56, 56, 6, 0x00, 0x10, 3, 3), -}; - -static const struct mtk_pin_field_calc mt7981_pin_pupd_range[] = { - PIN_FIELD_BASE(0, 0, 1, 0x20, 0x10, 1, 1), - PIN_FIELD_BASE(1, 1, 1, 0x20, 0x10, 0, 1), - PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 6, 1), - PIN_FIELD_BASE(3, 3, 4, 0x30, 0x10, 6, 1), - PIN_FIELD_BASE(4, 4, 4, 0x30, 0x10, 2, 1), - PIN_FIELD_BASE(5, 5, 4, 0x30, 0x10, 1, 1), - PIN_FIELD_BASE(6, 6, 4, 0x30, 0x10, 3, 1), - PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 0, 1), - PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 4, 1), - - PIN_FIELD_BASE(9, 9, 5, 0x30, 0x10, 9, 1), - PIN_FIELD_BASE(10, 10, 5, 0x30, 0x10, 8, 1), - PIN_FIELD_BASE(11, 11, 5, 0x30, 0x10, 10, 1), - PIN_FIELD_BASE(12, 12, 5, 0x30, 0x10, 7, 1), - PIN_FIELD_BASE(13, 13, 5, 0x30, 0x10, 11, 1), - - PIN_FIELD_BASE(14, 14, 4, 0x30, 0x10, 8, 1), - - PIN_FIELD_BASE(15, 15, 2, 0x30, 0x10, 0, 1), - PIN_FIELD_BASE(16, 16, 2, 0x30, 0x10, 1, 1), - PIN_FIELD_BASE(17, 17, 2, 0x30, 0x10, 5, 1), - PIN_FIELD_BASE(18, 18, 2, 0x30, 0x10, 4, 1), - PIN_FIELD_BASE(19, 19, 2, 0x30, 0x10, 2, 1), - PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1), - PIN_FIELD_BASE(21, 21, 2, 0x30, 0x10, 6, 1), - PIN_FIELD_BASE(22, 22, 2, 0x30, 0x10, 7, 1), - PIN_FIELD_BASE(23, 23, 2, 0x30, 0x10, 10, 1), - PIN_FIELD_BASE(24, 24, 2, 0x30, 0x10, 9, 1), - PIN_FIELD_BASE(25, 25, 2, 0x30, 0x10, 8, 1), - - PIN_FIELD_BASE(26, 26, 5, 0x30, 0x10, 0, 1), - PIN_FIELD_BASE(27, 27, 5, 0x30, 0x10, 4, 1), - PIN_FIELD_BASE(28, 28, 5, 0x30, 0x10, 3, 1), - PIN_FIELD_BASE(29, 29, 5, 0x30, 0x10, 1, 1), - PIN_FIELD_BASE(30, 30, 5, 0x30, 0x10, 2, 1), - PIN_FIELD_BASE(31, 31, 5, 0x30, 0x10, 5, 1), - - PIN_FIELD_BASE(32, 32, 1, 0x20, 0x10, 2, 1), - PIN_FIELD_BASE(33, 33, 1, 0x20, 0x10, 3, 1), - - PIN_FIELD_BASE(34, 34, 4, 0x30, 0x10, 5, 1), - PIN_FIELD_BASE(35, 35, 4, 0x30, 0x10, 7, 1), - - PIN_FIELD_BASE(36, 36, 3, 0x20, 0x10, 2, 1), - PIN_FIELD_BASE(37, 37, 3, 0x20, 0x10, 3, 1), - PIN_FIELD_BASE(38, 38, 3, 0x20, 0x10, 0, 1), - PIN_FIELD_BASE(39, 39, 3, 0x20, 0x10, 1, 1), -}; - -static const struct mtk_pin_field_calc mt7981_pin_r0_range[] = { - PIN_FIELD_BASE(0, 0, 1, 0x30, 0x10, 1, 1), - PIN_FIELD_BASE(1, 1, 1, 0x30, 0x10, 0, 1), - PIN_FIELD_BASE(2, 2, 5, 0x40, 0x10, 6, 1), - PIN_FIELD_BASE(3, 3, 4, 0x40, 0x10, 6, 1), - PIN_FIELD_BASE(4, 4, 4, 0x40, 0x10, 2, 1), - PIN_FIELD_BASE(5, 5, 4, 0x40, 0x10, 1, 1), - PIN_FIELD_BASE(6, 6, 4, 0x40, 0x10, 3, 1), - PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1), - - PIN_FIELD_BASE(9, 9, 5, 0x40, 0x10, 9, 1), - PIN_FIELD_BASE(10, 10, 5, 0x40, 0x10, 8, 1), - PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1), - PIN_FIELD_BASE(12, 12, 5, 0x40, 0x10, 7, 1), - PIN_FIELD_BASE(13, 13, 5, 0x40, 0x10, 11, 1), - - PIN_FIELD_BASE(14, 14, 4, 0x40, 0x10, 8, 1), - - PIN_FIELD_BASE(15, 15, 2, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(16, 16, 2, 0x40, 0x10, 1, 1), - PIN_FIELD_BASE(17, 17, 2, 0x40, 0x10, 5, 1), - PIN_FIELD_BASE(18, 18, 2, 0x40, 0x10, 4, 1), - PIN_FIELD_BASE(19, 19, 2, 0x40, 0x10, 2, 1), - PIN_FIELD_BASE(20, 20, 2, 0x40, 0x10, 3, 1), - PIN_FIELD_BASE(21, 21, 2, 0x40, 0x10, 6, 1), - PIN_FIELD_BASE(22, 22, 2, 0x40, 0x10, 7, 1), - PIN_FIELD_BASE(23, 23, 2, 0x40, 0x10, 10, 1), - PIN_FIELD_BASE(24, 24, 2, 0x40, 0x10, 9, 1), - PIN_FIELD_BASE(25, 25, 2, 0x40, 0x10, 8, 1), - - PIN_FIELD_BASE(26, 26, 5, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(27, 27, 5, 0x40, 0x10, 4, 1), - PIN_FIELD_BASE(28, 28, 5, 0x40, 0x10, 3, 1), - PIN_FIELD_BASE(29, 29, 5, 0x40, 0x10, 1, 1), - PIN_FIELD_BASE(30, 30, 5, 0x40, 0x10, 2, 1), - PIN_FIELD_BASE(31, 31, 5, 0x40, 0x10, 5, 1), - - PIN_FIELD_BASE(32, 32, 1, 0x30, 0x10, 2, 1), - PIN_FIELD_BASE(33, 33, 1, 0x30, 0x10, 3, 1), - - PIN_FIELD_BASE(34, 34, 4, 0x40, 0x10, 5, 1), - PIN_FIELD_BASE(35, 35, 4, 0x40, 0x10, 7, 1), - - PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 2, 1), - PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 3, 1), - PIN_FIELD_BASE(38, 38, 3, 0x30, 0x10, 0, 1), - PIN_FIELD_BASE(39, 39, 3, 0x30, 0x10, 1, 1), -}; - -static const struct mtk_pin_field_calc mt7981_pin_r1_range[] = { - PIN_FIELD_BASE(0, 0, 1, 0x40, 0x10, 1, 1), - PIN_FIELD_BASE(1, 1, 1, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 6, 1), - PIN_FIELD_BASE(3, 3, 4, 0x50, 0x10, 6, 1), - PIN_FIELD_BASE(4, 4, 4, 0x50, 0x10, 2, 1), - PIN_FIELD_BASE(5, 5, 4, 0x50, 0x10, 1, 1), - PIN_FIELD_BASE(6, 6, 4, 0x50, 0x10, 3, 1), - PIN_FIELD_BASE(7, 7, 4, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(8, 8, 4, 0x50, 0x10, 4, 1), - - PIN_FIELD_BASE(9, 9, 5, 0x50, 0x10, 9, 1), - PIN_FIELD_BASE(10, 10, 5, 0x50, 0x10, 8, 1), - PIN_FIELD_BASE(11, 11, 5, 0x50, 0x10, 10, 1), - PIN_FIELD_BASE(12, 12, 5, 0x50, 0x10, 7, 1), - PIN_FIELD_BASE(13, 13, 5, 0x50, 0x10, 11, 1), - - PIN_FIELD_BASE(14, 14, 4, 0x50, 0x10, 8, 1), - - PIN_FIELD_BASE(15, 15, 2, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(16, 16, 2, 0x50, 0x10, 1, 1), - PIN_FIELD_BASE(17, 17, 2, 0x50, 0x10, 5, 1), - PIN_FIELD_BASE(18, 18, 2, 0x50, 0x10, 4, 1), - PIN_FIELD_BASE(19, 19, 2, 0x50, 0x10, 2, 1), - PIN_FIELD_BASE(20, 20, 2, 0x50, 0x10, 3, 1), - PIN_FIELD_BASE(21, 21, 2, 0x50, 0x10, 6, 1), - PIN_FIELD_BASE(22, 22, 2, 0x50, 0x10, 7, 1), - PIN_FIELD_BASE(23, 23, 2, 0x50, 0x10, 10, 1), - PIN_FIELD_BASE(24, 24, 2, 0x50, 0x10, 9, 1), - PIN_FIELD_BASE(25, 25, 2, 0x50, 0x10, 8, 1), - - PIN_FIELD_BASE(26, 26, 5, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(27, 27, 5, 0x50, 0x10, 4, 1), - PIN_FIELD_BASE(28, 28, 5, 0x50, 0x10, 3, 1), - PIN_FIELD_BASE(29, 29, 5, 0x50, 0x10, 1, 1), - PIN_FIELD_BASE(30, 30, 5, 0x50, 0x10, 2, 1), - PIN_FIELD_BASE(31, 31, 5, 0x50, 0x10, 5, 1), - - PIN_FIELD_BASE(32, 32, 1, 0x40, 0x10, 2, 1), - PIN_FIELD_BASE(33, 33, 1, 0x40, 0x10, 3, 1), - - PIN_FIELD_BASE(34, 34, 4, 0x50, 0x10, 5, 1), - PIN_FIELD_BASE(35, 35, 4, 0x50, 0x10, 7, 1), - - PIN_FIELD_BASE(36, 36, 3, 0x40, 0x10, 2, 1), - PIN_FIELD_BASE(37, 37, 3, 0x40, 0x10, 3, 1), - PIN_FIELD_BASE(38, 38, 3, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(39, 39, 3, 0x40, 0x10, 1, 1), -}; - -static const unsigned int mt7981_pull_type[] = { - MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/ - MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/ - MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/ - MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/ - MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/ - MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/ - MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/ - MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/ - MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/ - MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/ - MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/ - MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/ - MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/ - MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/ - MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/ - MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/ - MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/ - MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/ - MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/ - MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/ - MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/ - MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/ - MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/ - MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/ - MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/ - MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/ - MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/ - MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/ - MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/ - MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/ - MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/ - MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/ - MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/ - MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/ - MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/ - MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/ - MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/ - MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/ - MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/ - MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/ - MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/ - MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/ - MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/ - MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/ - MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/ - MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/ - MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/ - MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/ - MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/ - MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/ - MTK_PULL_PU_PD_TYPE,/*100*/ -}; - -static const struct mtk_pin_reg_calc mt7981_reg_cals[] = { - [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7981_pin_mode_range), - [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7981_pin_dir_range), - [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7981_pin_di_range), - [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7981_pin_do_range), - [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7981_pin_smt_range), - [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7981_pin_ies_range), - [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7981_pin_pu_range), - [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7981_pin_pd_range), - [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7981_pin_drv_range), - [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7981_pin_pupd_range), - [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7981_pin_r0_range), - [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7981_pin_r1_range), -}; - -static const struct mtk_pin_desc mt7981_pins[] = { - MT7981_PIN(0, "GPIO_WPS"), - MT7981_PIN(1, "GPIO_RESET"), - MT7981_PIN(2, "SYS_WATCHDOG"), - MT7981_PIN(3, "PCIE_PERESET_N"), - MT7981_PIN(4, "JTAG_JTDO"), - MT7981_PIN(5, "JTAG_JTDI"), - MT7981_PIN(6, "JTAG_JTMS"), - MT7981_PIN(7, "JTAG_JTCLK"), - MT7981_PIN(8, "JTAG_JTRST_N"), - MT7981_PIN(9, "WO_JTAG_JTDO"), - MT7981_PIN(10, "WO_JTAG_JTDI"), - MT7981_PIN(11, "WO_JTAG_JTMS"), - MT7981_PIN(12, "WO_JTAG_JTCLK"), - MT7981_PIN(13, "WO_JTAG_JTRST_N"), - MT7981_PIN(14, "USB_VBUS"), - MT7981_PIN(15, "PWM0"), - MT7981_PIN(16, "SPI0_CLK"), - MT7981_PIN(17, "SPI0_MOSI"), - MT7981_PIN(18, "SPI0_MISO"), - MT7981_PIN(19, "SPI0_CS"), - MT7981_PIN(20, "SPI0_HOLD"), - MT7981_PIN(21, "SPI0_WP"), - MT7981_PIN(22, "SPI1_CLK"), - MT7981_PIN(23, "SPI1_MOSI"), - MT7981_PIN(24, "SPI1_MISO"), - MT7981_PIN(25, "SPI1_CS"), - MT7981_PIN(26, "SPI2_CLK"), - MT7981_PIN(27, "SPI2_MOSI"), - MT7981_PIN(28, "SPI2_MISO"), - MT7981_PIN(29, "SPI2_CS"), - MT7981_PIN(30, "SPI2_HOLD"), - MT7981_PIN(31, "SPI2_WP"), - MT7981_PIN(32, "UART0_RXD"), - MT7981_PIN(33, "UART0_TXD"), - MT7981_PIN(34, "PCIE_CLK_REQ"), - MT7981_PIN(35, "PCIE_WAKE_N"), - MT7981_PIN(36, "SMI_MDC"), - MT7981_PIN(37, "SMI_MDIO"), - MT7981_PIN(38, "GBE_INT"), - MT7981_PIN(39, "GBE_RESET"), - MT7981_PIN(40, "WF_DIG_RESETB"), - MT7981_PIN(41, "WF_CBA_RESETB"), - MT7981_PIN(42, "WF_XO_REQ"), - MT7981_PIN(43, "WF_TOP_CLK"), - MT7981_PIN(44, "WF_TOP_DATA"), - MT7981_PIN(45, "WF_HB1"), - MT7981_PIN(46, "WF_HB2"), - MT7981_PIN(47, "WF_HB3"), - MT7981_PIN(48, "WF_HB4"), - MT7981_PIN(49, "WF_HB0"), - MT7981_PIN(50, "WF_HB0_B"), - MT7981_PIN(51, "WF_HB5"), - MT7981_PIN(52, "WF_HB6"), - MT7981_PIN(53, "WF_HB7"), - MT7981_PIN(54, "WF_HB8"), - MT7981_PIN(55, "WF_HB9"), - MT7981_PIN(56, "WF_HB10"), -}; - -/* List all groups consisting of these pins dedicated to the enablement of - * certain hardware block and the corresponding mode for all of the pins. - * The hardware probably has multiple combinations of these pinouts. - */ - -/* WA_AICE */ -static int mt7981_wa_aice1_pins[] = { 0, 1, }; -static int mt7981_wa_aice1_funcs[] = { 2, 2, }; - -static int mt7981_wa_aice2_pins[] = { 0, 1, }; -static int mt7981_wa_aice2_funcs[] = { 3, 3, }; - -static int mt7981_wa_aice3_pins[] = { 28, 29, }; -static int mt7981_wa_aice3_funcs[] = { 3, 3, }; - -static int mt7981_wm_aice1_pins[] = { 9, 10, }; -static int mt7981_wm_aice1_funcs[] = { 2, 2, }; - -static int mt7981_wm_aice2_pins[] = { 30, 31, }; -static int mt7981_wm_aice2_funcs[] = { 5, 5, }; - -/* WM_UART */ -static int mt7981_wm_uart_0_pins[] = { 0, 1, }; -static int mt7981_wm_uart_0_funcs[] = { 5, 5, }; - -static int mt7981_wm_uart_1_pins[] = { 20, 21, }; -static int mt7981_wm_uart_1_funcs[] = { 4, 4, }; - -static int mt7981_wm_uart_2_pins[] = { 30, 31, }; -static int mt7981_wm_uart_2_funcs[] = { 3, 3, }; - -/* DFD */ -static int mt7981_dfd_pins[] = { 0, 1, 4, 5, }; -static int mt7981_dfd_funcs[] = { 5, 5, 6, 6, }; - -/* SYS_WATCHDOG */ -static int mt7981_watchdog_pins[] = { 2, }; -static int mt7981_watchdog_funcs[] = { 1, }; - -static int mt7981_watchdog1_pins[] = { 13, }; -static int mt7981_watchdog1_funcs[] = { 5, }; - -/* PCIE_PERESET_N */ -static int mt7981_pcie_pereset_pins[] = { 3, }; -static int mt7981_pcie_pereset_funcs[] = { 1, }; - -/* JTAG */ -static int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, }; -static int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, }; - -/* WM_JTAG */ -static int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, }; -static int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, }; - -static int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, }; -static int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; - -/* WO0_JTAG */ -static int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, }; -static int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, }; - -static int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, }; -static int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; - -/* UART2 */ -static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, }; -static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, }; - -/* GBE_LED0 */ -static int mt7981_gbe_led0_pins[] = { 8, }; -static int mt7981_gbe_led0_funcs[] = { 3, }; - -/* PTA_EXT */ -static int mt7981_pta_ext_0_pins[] = { 4, 5, 6, }; -static int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, }; - -static int mt7981_pta_ext_1_pins[] = { 22, 23, 24, }; -static int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, }; - -/* PWM2 */ -static int mt7981_pwm2_pins[] = { 7, }; -static int mt7981_pwm2_funcs[] = { 4, }; - -/* NET_WO0_UART_TXD */ -static int mt7981_net_wo0_uart_txd_0_pins[] = { 8, }; -static int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, }; - -static int mt7981_net_wo0_uart_txd_1_pins[] = { 14, }; -static int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, }; - -static int mt7981_net_wo0_uart_txd_2_pins[] = { 15, }; -static int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, }; - -/* SPI1 */ -static int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, }; -static int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, }; - -/* I2C */ -static int mt7981_i2c0_0_pins[] = { 6, 7, }; -static int mt7981_i2c0_0_funcs[] = { 6, 6, }; - -static int mt7981_i2c0_1_pins[] = { 30, 31, }; -static int mt7981_i2c0_1_funcs[] = { 4, 4, }; - -static int mt7981_i2c0_2_pins[] = { 36, 37, }; -static int mt7981_i2c0_2_funcs[] = { 2, 2, }; - -static int mt7981_u2_phy_i2c_pins[] = { 30, 31, }; -static int mt7981_u2_phy_i2c_funcs[] = { 6, 6, }; - -static int mt7981_u3_phy_i2c_pins[] = { 32, 33, }; -static int mt7981_u3_phy_i2c_funcs[] = { 3, 3, }; - -static int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, }; -static int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, }; - -static int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, }; -static int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, }; - -/* DFD_NTRST */ -static int mt7981_dfd_ntrst_pins[] = { 8, }; -static int mt7981_dfd_ntrst_funcs[] = { 6, }; - -/* PWM0 */ -static int mt7981_pwm0_0_pins[] = { 13, }; -static int mt7981_pwm0_0_funcs[] = { 2, }; - -static int mt7981_pwm0_1_pins[] = { 15, }; -static int mt7981_pwm0_1_funcs[] = { 1, }; - -/* PWM1 */ -static int mt7981_pwm1_0_pins[] = { 14, }; -static int mt7981_pwm1_0_funcs[] = { 2, }; - -static int mt7981_pwm1_1_pins[] = { 15, }; -static int mt7981_pwm1_1_funcs[] = { 3, }; - -/* GBE_LED1 */ -static int mt7981_gbe_led1_pins[] = { 13, }; -static int mt7981_gbe_led1_funcs[] = { 3, }; - -/* PCM */ -static int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 }; -static int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, }; - -/* UDI */ -static int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, }; -static int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, }; - -/* DRV_VBUS */ -static int mt7981_drv_vbus_pins[] = { 14, }; -static int mt7981_drv_vbus_funcs[] = { 1, }; - -/* EMMC */ -static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, }; -static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; - -/* SNFI */ -static int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, }; -static int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, }; - -/* SPI0 */ -static int mt7981_spi0_pins[] = { 16, 17, 18, 19, }; -static int mt7981_spi0_funcs[] = { 1, 1, 1, 1, }; - -/* SPI0 */ -static int mt7981_spi0_wp_hold_pins[] = { 20, 21, }; -static int mt7981_spi0_wp_hold_funcs[] = { 1, 1, }; - -/* SPI1 */ -static int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, }; -static int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, }; - -/* SPI2 */ -static int mt7981_spi2_pins[] = { 26, 27, 28, 29, }; -static int mt7981_spi2_funcs[] = { 1, 1, 1, 1, }; - -/* SPI2 */ -static int mt7981_spi2_wp_hold_pins[] = { 30, 31, }; -static int mt7981_spi2_wp_hold_funcs[] = { 1, 1, }; - -/* UART1 */ -static int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, }; -static int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, }; - -static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, }; -static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, }; - -/* UART2 */ -static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, }; -static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, }; - -/* UART0 */ -static int mt7981_uart0_pins[] = { 32, 33, }; -static int mt7981_uart0_funcs[] = { 1, 1, }; - -/* PCIE_CLK_REQ */ -static int mt7981_pcie_clk_pins[] = { 34, }; -static int mt7981_pcie_clk_funcs[] = { 2, }; - -/* PCIE_WAKE_N */ -static int mt7981_pcie_wake_pins[] = { 35, }; -static int mt7981_pcie_wake_funcs[] = { 2, }; - -/* MDC_MDIO */ -static int mt7981_smi_mdc_mdio_pins[] = { 36, 37, }; -static int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, }; - -static int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, }; -static int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, }; - -/* WF0_MODE1 */ -static int mt7981_wf0_mode1_pins[] = { 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56 }; -static int mt7981_wf0_mode1_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; - -/* WF0_MODE3 */ -static int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 }; -static int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 }; - -/* WF2G_LED */ -static int mt7981_wf2g_led0_pins[] = { 30, }; -static int mt7981_wf2g_led0_funcs[] = { 2, }; - -static int mt7981_wf2g_led1_pins[] = { 34, }; -static int mt7981_wf2g_led1_funcs[] = { 1, }; - -/* WF5G_LED */ -static int mt7981_wf5g_led0_pins[] = { 31, }; -static int mt7981_wf5g_led0_funcs[] = { 2, }; - -static int mt7981_wf5g_led1_pins[] = { 35, }; -static int mt7981_wf5g_led1_funcs[] = { 1, }; - -/* MT7531_INT */ -static int mt7981_mt7531_int_pins[] = { 38, }; -static int mt7981_mt7531_int_funcs[] = { 1, }; - -/* ANT_SEL */ -static int mt7981_ant_sel_pins[] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 }; -static int mt7981_ant_sel_funcs[] = { 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 }; - -static const struct group_desc mt7981_groups[] = { - /* @GPIO(0,1): WA_AICE(2) */ - PINCTRL_PIN_GROUP("wa_aice1", mt7981_wa_aice1), - /* @GPIO(0,1): WA_AICE(3) */ - PINCTRL_PIN_GROUP("wa_aice2", mt7981_wa_aice2), - /* @GPIO(0,1): WM_UART(5) */ - PINCTRL_PIN_GROUP("wm_uart_0", mt7981_wm_uart_0), - /* @GPIO(0,1,4,5): DFD(6) */ - PINCTRL_PIN_GROUP("dfd", mt7981_dfd), - /* @GPIO(2): SYS_WATCHDOG(1) */ - PINCTRL_PIN_GROUP("watchdog", mt7981_watchdog), - /* @GPIO(3): PCIE_PERESET_N(1) */ - PINCTRL_PIN_GROUP("pcie_pereset", mt7981_pcie_pereset), - /* @GPIO(4,8) JTAG(1) */ - PINCTRL_PIN_GROUP("jtag", mt7981_jtag), - /* @GPIO(4,8) WM_JTAG(2) */ - PINCTRL_PIN_GROUP("wm_jtag_0", mt7981_wm_jtag_0), - /* @GPIO(9,13) WO0_JTAG(1) */ - PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0), - /* @GPIO(4,7) WM_JTAG(3) */ - PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0), - /* @GPIO(8) GBE_LED0(3) */ - PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0), - /* @GPIO(4,6) PTA_EXT(4) */ - PINCTRL_PIN_GROUP("pta_ext_0", mt7981_pta_ext_0), - /* @GPIO(7) PWM2(4) */ - PINCTRL_PIN_GROUP("pwm2", mt7981_pwm2), - /* @GPIO(8) NET_WO0_UART_TXD(4) */ - PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7981_net_wo0_uart_txd_0), - /* @GPIO(4,7) SPI1(5) */ - PINCTRL_PIN_GROUP("spi1_0", mt7981_spi1_0), - /* @GPIO(6,7) I2C(5) */ - PINCTRL_PIN_GROUP("i2c0_0", mt7981_i2c0_0), - /* @GPIO(0,1,4,5): DFD_NTRST(6) */ - PINCTRL_PIN_GROUP("dfd_ntrst", mt7981_dfd_ntrst), - /* @GPIO(9,10): WM_AICE(2) */ - PINCTRL_PIN_GROUP("wm_aice1", mt7981_wm_aice1), - /* @GPIO(13): PWM0(2) */ - PINCTRL_PIN_GROUP("pwm0_0", mt7981_pwm0_0), - /* @GPIO(15): PWM0(1) */ - PINCTRL_PIN_GROUP("pwm0_1", mt7981_pwm0_1), - /* @GPIO(14): PWM1(2) */ - PINCTRL_PIN_GROUP("pwm1_0", mt7981_pwm1_0), - /* @GPIO(15): PWM1(3) */ - PINCTRL_PIN_GROUP("pwm1_1", mt7981_pwm1_1), - /* @GPIO(14) NET_WO0_UART_TXD(3) */ - PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7981_net_wo0_uart_txd_1), - /* @GPIO(15) NET_WO0_UART_TXD(4) */ - PINCTRL_PIN_GROUP("net_wo0_uart_txd_2", mt7981_net_wo0_uart_txd_2), - /* @GPIO(13) GBE_LED0(3) */ - PINCTRL_PIN_GROUP("gbe_led1", mt7981_gbe_led1), - /* @GPIO(9,13) PCM(4) */ - PINCTRL_PIN_GROUP("pcm", mt7981_pcm), - /* @GPIO(13): SYS_WATCHDOG1(5) */ - PINCTRL_PIN_GROUP("watchdog1", mt7981_watchdog1), - /* @GPIO(9,13) UDI(4) */ - PINCTRL_PIN_GROUP("udi", mt7981_udi), - /* @GPIO(14) DRV_VBUS(1) */ - PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus), - /* @GPIO(15,25): EMMC(2) */ - PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45), - /* @GPIO(16,21): SNFI(3) */ - PINCTRL_PIN_GROUP("snfi", mt7981_snfi), - /* @GPIO(16,19): SPI0(1) */ - PINCTRL_PIN_GROUP("spi0", mt7981_spi0), - /* @GPIO(20,21): SPI0(1) */ - PINCTRL_PIN_GROUP("spi0_wp_hold", mt7981_spi0_wp_hold), - /* @GPIO(22,25) SPI1(1) */ - PINCTRL_PIN_GROUP("spi1_1", mt7981_spi1_1), - /* @GPIO(26,29): SPI2(1) */ - PINCTRL_PIN_GROUP("spi2", mt7981_spi2), - /* @GPIO(30,31): SPI0(1) */ - PINCTRL_PIN_GROUP("spi2_wp_hold", mt7981_spi2_wp_hold), - /* @GPIO(16,19): UART1(4) */ - PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0), - /* @GPIO(26,29): UART1(2) */ - PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1), - /* @GPIO(22,25): UART1(3) */ - PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1), - /* @GPIO(22,24) PTA_EXT(4) */ - PINCTRL_PIN_GROUP("pta_ext_1", mt7981_pta_ext_1), - /* @GPIO(20,21): WM_UART(4) */ - PINCTRL_PIN_GROUP("wm_aurt_1", mt7981_wm_uart_1), - /* @GPIO(30,31): WM_UART(3) */ - PINCTRL_PIN_GROUP("wm_aurt_2", mt7981_wm_uart_2), - /* @GPIO(20,24) WM_JTAG(5) */ - PINCTRL_PIN_GROUP("wm_jtag_1", mt7981_wm_jtag_1), - /* @GPIO(25,29) WO0_JTAG(5) */ - PINCTRL_PIN_GROUP("wo0_jtag_1", mt7981_wo0_jtag_1), - /* @GPIO(28,29): WA_AICE(3) */ - PINCTRL_PIN_GROUP("wa_aice3", mt7981_wa_aice3), - /* @GPIO(30,31): WM_AICE(5) */ - PINCTRL_PIN_GROUP("wm_aice2", mt7981_wm_aice2), - /* @GPIO(30,31): I2C(4) */ - PINCTRL_PIN_GROUP("i2c0_1", mt7981_i2c0_1), - /* @GPIO(30,31): I2C(6) */ - PINCTRL_PIN_GROUP("u2_phy_i2c", mt7981_u2_phy_i2c), - /* @GPIO(32,33): I2C(1) */ - PINCTRL_PIN_GROUP("uart0", mt7981_uart0), - /* @GPIO(32,33): I2C(2) */ - PINCTRL_PIN_GROUP("sgmii1_phy_i2c", mt7981_sgmii1_phy_i2c), - /* @GPIO(32,33): I2C(3) */ - PINCTRL_PIN_GROUP("u3_phy_i2c", mt7981_u3_phy_i2c), - /* @GPIO(32,33): I2C(5) */ - PINCTRL_PIN_GROUP("sgmii0_phy_i2c", mt7981_sgmii0_phy_i2c), - /* @GPIO(34): PCIE_CLK_REQ(2) */ - PINCTRL_PIN_GROUP("pcie_clk", mt7981_pcie_clk), - /* @GPIO(35): PCIE_WAKE_N(2) */ - PINCTRL_PIN_GROUP("pcie_wake", mt7981_pcie_wake), - /* @GPIO(36,37): I2C(2) */ - PINCTRL_PIN_GROUP("i2c0_2", mt7981_i2c0_2), - /* @GPIO(36,37): MDC_MDIO(1) */ - PINCTRL_PIN_GROUP("smi_mdc_mdio", mt7981_smi_mdc_mdio), - /* @GPIO(36,37): MDC_MDIO(3) */ - PINCTRL_PIN_GROUP("gbe_ext_mdc_mdio", mt7981_gbe_ext_mdc_mdio), - /* @GPIO(69,85): WF0_MODE1(1) */ - PINCTRL_PIN_GROUP("wf0_mode1", mt7981_wf0_mode1), - /* @GPIO(74,80): WF0_MODE3(3) */ - PINCTRL_PIN_GROUP("wf0_mode3", mt7981_wf0_mode3), - /* @GPIO(30): WF2G_LED(2) */ - PINCTRL_PIN_GROUP("wf2g_led0", mt7981_wf2g_led0), - /* @GPIO(34): WF2G_LED(1) */ - PINCTRL_PIN_GROUP("wf2g_led1", mt7981_wf2g_led1), - /* @GPIO(31): WF5G_LED(2) */ - PINCTRL_PIN_GROUP("wf5g_led0", mt7981_wf5g_led0), - /* @GPIO(35): WF5G_LED(1) */ - PINCTRL_PIN_GROUP("wf5g_led1", mt7981_wf5g_led1), - /* @GPIO(38): MT7531_INT(1) */ - PINCTRL_PIN_GROUP("mt7531_int", mt7981_mt7531_int), - /* @GPIO(14,15,26,17,18,19,20,21,22,23,24,25,34,35): ANT_SEL(1) */ - PINCTRL_PIN_GROUP("ant_sel", mt7981_ant_sel), -}; - -/* Joint those groups owning the same capability in user point of view which - * allows that people tend to use through the device tree. - */ -static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1", - "wa_aice3", "wm_aice1_2", }; -static const char *mt7981_uart_groups[] = { "wm_uart_0", "uart2_0", - "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2", - "uart1_0", "uart1_1", "uart2_1", "wm_aurt_1", "wm_aurt_2", "uart0", }; -static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", }; -static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", }; -static const char *mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", "pcie_wake", }; -static const char *mt7981_jtag_groups[] = { "jtag", "wm_jtag_0", "wo0_jtag_0", - "wo0_jtag_1", "wm_jtag_1", }; -static const char *mt7981_led_groups[] = { "gbe_led0", "gbe_led1", "wf2g_led0", - "wf2g_led1", "wf5g_led0", "wf5g_led1", }; -static const char *mt7981_pta_groups[] = { "pta_ext_0", "pta_ext_1", }; -static const char *mt7981_pwm_groups[] = { "pwm2", "pwm0_0", "pwm0_1", - "pwm1_0", "pwm1_1", }; -static const char *mt7981_spi_groups[] = { "spi1_0", "spi0", "spi0_wp_hold", "spi1_1", "spi2", - "spi2_wp_hold", }; -static const char *mt7981_i2c_groups[] = { "i2c0_0", "i2c0_1", "u2_phy_i2c", - "sgmii1_phy_i2c", "u3_phy_i2c", "sgmii0_phy_i2c", "i2c0_2", }; -static const char *mt7981_pcm_groups[] = { "pcm", }; -static const char *mt7981_udi_groups[] = { "udi", }; -static const char *mt7981_usb_groups[] = { "drv_vbus", }; -static const char *mt7981_flash_groups[] = { "emmc_45", "snfi", }; -static const char *mt7981_ethernet_groups[] = { "smi_mdc_mdio", "gbe_ext_mdc_mdio", - "wf0_mode1", "wf0_mode3", "mt7531_int", }; -static const char *mt7981_ant_groups[] = { "ant_sel", }; - -static const struct function_desc mt7981_functions[] = { - {"wa_aice", mt7981_wa_aice_groups, ARRAY_SIZE(mt7981_wa_aice_groups)}, - {"dfd", mt7981_dfd_groups, ARRAY_SIZE(mt7981_dfd_groups)}, - {"jtag", mt7981_jtag_groups, ARRAY_SIZE(mt7981_jtag_groups)}, - {"pta", mt7981_pta_groups, ARRAY_SIZE(mt7981_pta_groups)}, - {"pcm", mt7981_pcm_groups, ARRAY_SIZE(mt7981_pcm_groups)}, - {"udi", mt7981_udi_groups, ARRAY_SIZE(mt7981_udi_groups)}, - {"usb", mt7981_usb_groups, ARRAY_SIZE(mt7981_usb_groups)}, - {"ant", mt7981_ant_groups, ARRAY_SIZE(mt7981_ant_groups)}, - {"eth", mt7981_ethernet_groups, ARRAY_SIZE(mt7981_ethernet_groups)}, - {"i2c", mt7981_i2c_groups, ARRAY_SIZE(mt7981_i2c_groups)}, - {"led", mt7981_led_groups, ARRAY_SIZE(mt7981_led_groups)}, - {"pwm", mt7981_pwm_groups, ARRAY_SIZE(mt7981_pwm_groups)}, - {"spi", mt7981_spi_groups, ARRAY_SIZE(mt7981_spi_groups)}, - {"uart", mt7981_uart_groups, ARRAY_SIZE(mt7981_uart_groups)}, - {"watchdog", mt7981_wdt_groups, ARRAY_SIZE(mt7981_wdt_groups)}, - {"flash", mt7981_flash_groups, ARRAY_SIZE(mt7981_flash_groups)}, - {"pcie", mt7981_pcie_groups, ARRAY_SIZE(mt7981_pcie_groups)}, -}; - -static const struct mtk_eint_hw mt7981_eint_hw = { - .port_mask = 7, - .ports = 7, - .ap_num = ARRAY_SIZE(mt7981_pins), - .db_cnt = 16, -}; - -static const char * const mt7981_pinctrl_register_base_names[] = { - "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb", - "iocfg_lb", "iocfg_bl", "iocfg_tm", "iocfg_tl", -}; - -static struct mtk_pin_soc mt7981_data = { - .reg_cal = mt7981_reg_cals, - .pins = mt7981_pins, - .npins = ARRAY_SIZE(mt7981_pins), - .grps = mt7981_groups, - .ngrps = ARRAY_SIZE(mt7981_groups), - .funcs = mt7981_functions, - .nfuncs = ARRAY_SIZE(mt7981_functions), - .eint_hw = &mt7981_eint_hw, - .gpio_m = 0, - .ies_present = false, - .base_names = mt7981_pinctrl_register_base_names, - .nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names), - .pull_type = mt7981_pull_type, - .bias_set_combo = mtk_pinconf_bias_set_combo, - .bias_get_combo = mtk_pinconf_bias_get_combo, - .drive_set = mtk_pinconf_drive_set_rev1, - .drive_get = mtk_pinconf_drive_get_rev1, - .adv_pull_get = mtk_pinconf_adv_pull_get, - .adv_pull_set = mtk_pinconf_adv_pull_set, -}; - -static const struct of_device_id mt7981_pinctrl_of_match[] = { - { .compatible = "mediatek,mt7981-pinctrl", }, - {} -}; - -static int mt7981_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_moore_pinctrl_probe(pdev, &mt7981_data); -} - -static struct platform_driver mt7981_pinctrl_driver = { - .driver = { - .name = "mt7981-pinctrl", - .of_match_table = mt7981_pinctrl_of_match, - }, - .probe = mt7981_pinctrl_probe, -}; - -static int __init mt7981_pinctrl_init(void) -{ - return platform_driver_register(&mt7981_pinctrl_driver); -} -arch_initcall(mt7981_pinctrl_init); diff --git a/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7986.c b/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7986.c deleted file mode 100644 index aa0ccd67f4f..00000000000 --- a/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7986.c +++ /dev/null @@ -1,1003 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * The MT7986 driver based on Linux generic pinctrl binding. - * - * Copyright (C) 2021 MediaTek Inc. - * Author: Sam Shih - */ - -#include "pinctrl-moore.h" - -#define MT7986_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4) -#define MT7986_NOT_BALLOUT_PIN(_number) { .number = _number, .name = NULL } - -#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ - _x_bits) \ - PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ - _x_bits, 32, 0) - -/** - * enum - Locking variants of the iocfg bases - * - * MT7986 have multiple bases to program pin configuration listed as the below: - * iocfg_rt:0x11c30000, iocfg_rb:0x11c40000, iocfg_lt:0x11e20000, - * iocfg_lb:0x11e30000, iocfg_tr:0x11f00000, iocfg_tl:0x11f10000, - * _i_based could be used to indicate what base the pin should be mapped into. - * - * Each iocfg register base control different group of pads on the SoC - * - * - * chip carrier - * - * A B C D E F G H - * +------------------------+ - * 8 | o o o o o o o o | - * 7 | o o o o o o o o | - * 6 | o o o o o o o o | - * 5 | o o o o o o o o | - * 4 | o o o o o o o o | - * 3 | o o o o o o o o | - * 2 | o o o o o o o o | - * 1 | o o o o o o o o | - * +------------------------+ - * - * inside Chip carrier - * - * A B C D E F G H - * +------------------------+ - * 8 | | - * 7 | TL TR | - * 6 | +---------+ | - * 5 | LT | | RT | - * 4 | | | | - * 3 | LB | | RB | - * 2 | +---------+ | - * 1 | | - * +------------------------+ - * - */ - -enum { - GPIO_BASE, - IOCFG_RT_BASE, - IOCFG_RB_BASE, - IOCFG_LT_BASE, - IOCFG_LB_BASE, - IOCFG_TR_BASE, - IOCFG_TL_BASE, -}; - -static const char *const mt7986_pinctrl_register_base_names[] = { - "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt", "iocfg_lb", "iocfg_tr", - "iocfg_tl", -}; - -static const struct mtk_pin_field_calc mt7986_pin_mode_range[] = { - PIN_FIELD(0, 100, 0x300, 0x10, 0, 4), -}; - -static const struct mtk_pin_field_calc mt7986_pin_dir_range[] = { - PIN_FIELD(0, 100, 0x0, 0x10, 0, 1), -}; - -static const struct mtk_pin_field_calc mt7986_pin_di_range[] = { - PIN_FIELD(0, 100, 0x200, 0x10, 0, 1), -}; - -static const struct mtk_pin_field_calc mt7986_pin_do_range[] = { - PIN_FIELD(0, 100, 0x100, 0x10, 0, 1), -}; - -static const struct mtk_pin_field_calc mt7986_pin_ies_range[] = { - PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x40, 0x10, 17, 1), - PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x20, 0x10, 10, 1), - PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x20, 0x10, 0, 1), - PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x20, 0x10, 0, 1), - PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x40, 0x10, 8, 1), - PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x40, 0x10, 2, 1), - PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x30, 0x10, 12, 1), - PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x30, 0x10, 18, 1), - PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x30, 0x10, 17, 1), - PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x30, 0x10, 15, 1), - PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x30, 0x10, 19, 1), - PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x30, 0x10, 23, 1), - PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x30, 0x10, 22, 1), - PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x30, 0x10, 21, 1), - PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x20, 0x10, 4, 1), - PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x20, 0x10, 8, 1), - PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x20, 0x10, 7, 1), - PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x20, 0x10, 5, 1), - PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x20, 0x10, 9, 1), - PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x40, 0x10, 18, 1), - PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x40, 0x10, 12, 1), - PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x40, 0x10, 22, 1), - PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x40, 0x10, 20, 1), - PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x40, 0x10, 26, 1), - PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x40, 0x10, 24, 1), - PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x30, 0x10, 2, 1), - PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x30, 0x10, 1, 1), - PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x30, 0x10, 0, 1), - PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x30, 0x10, 10, 1), - PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x40, 0x10, 15, 1), - PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x40, 0x10, 14, 1), - PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x40, 0x10, 13, 1), - PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x40, 0x10, 16, 1), - PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x20, 0x10, 2, 1), - PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x30, 0x10, 1, 1), - PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x30, 0x10, 0, 1), - PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x30, 0x10, 16, 1), - PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x30, 0x10, 14, 1), - PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x30, 0x10, 4, 1), - PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x30, 0x10, 6, 1), - PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x30, 0x10, 2, 1), - PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x30, 0x10, 9, 1), - PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x30, 0x10, 5, 1), - PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x30, 0x10, 1, 1), - PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x30, 0x10, 0, 1), - PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x30, 0x10, 14, 1), - PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x30, 0x10, 12, 1), - PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x30, 0x10, 4, 1), - PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x30, 0x10, 2, 1), - PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x30, 0x10, 8, 1), -}; - -static const struct mtk_pin_field_calc mt7986_pin_smt_range[] = { - PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0xf0, 0x10, 17, 1), - PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x90, 0x10, 10, 1), - PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x90, 0x10, 0, 1), - PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0xf0, 0x10, 0, 1), - PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x90, 0x10, 0, 1), - PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0xf0, 0x10, 8, 1), - PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0xf0, 0x10, 2, 1), - PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0xc0, 0x10, 12, 1), - PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0xc0, 0x10, 18, 1), - PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0xc0, 0x10, 17, 1), - PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0xc0, 0x10, 15, 1), - PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0xc0, 0x10, 19, 1), - PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0xc0, 0x10, 23, 1), - PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0xc0, 0x10, 22, 1), - PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0xc0, 0x10, 21, 1), - PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x90, 0x10, 4, 1), - PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x90, 0x10, 8, 1), - PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x90, 0x10, 7, 1), - PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x90, 0x10, 5, 1), - PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x90, 0x10, 9, 1), - PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0xf0, 0x10, 18, 1), - PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0xf0, 0x10, 12, 1), - PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0xf0, 0x10, 22, 1), - PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0xf0, 0x10, 20, 1), - PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0xf0, 0x10, 26, 1), - PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0xf0, 0x10, 24, 1), - PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0xc0, 0x10, 2, 1), - PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0xc0, 0x10, 1, 1), - PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0xc0, 0x10, 0, 1), - PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0xc0, 0x10, 10, 1), - PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0xf0, 0x10, 15, 1), - PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0xf0, 0x10, 14, 1), - PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0xf0, 0x10, 13, 1), - PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0xf0, 0x10, 16, 1), - PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x90, 0x10, 2, 1), - PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x80, 0x10, 1, 1), - PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x80, 0x10, 0, 1), - PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x80, 0x10, 16, 1), - PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x80, 0x10, 14, 1), - PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x80, 0x10, 4, 1), - PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x80, 0x10, 6, 1), - PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x80, 0x10, 2, 1), - PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x80, 0x10, 9, 1), - PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x80, 0x10, 5, 1), - PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x70, 0x10, 1, 1), - PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x70, 0x10, 0, 1), - PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x70, 0x10, 14, 1), - PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x70, 0x10, 12, 1), - PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x70, 0x10, 4, 1), - PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x70, 0x10, 2, 1), - PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x70, 0x10, 8, 1), -}; - -static const struct mtk_pin_field_calc mt7986_pin_pu_range[] = { - PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x50, 0x10, 1, 1), - PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x50, 0x10, 16, 1), - PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x50, 0x10, 14, 1), - PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x50, 0x10, 4, 1), - PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x50, 0x10, 6, 1), - PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x50, 0x10, 2, 1), - PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x50, 0x10, 9, 1), - PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x50, 0x10, 5, 1), - PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x50, 0x10, 1, 1), - PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x50, 0x10, 14, 1), - PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x50, 0x10, 12, 1), - PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x50, 0x10, 4, 1), - PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x50, 0x10, 2, 1), - PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x50, 0x10, 8, 1), -}; - -static const struct mtk_pin_field_calc mt7986_pin_pd_range[] = { - PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x40, 0x10, 1, 1), - PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x40, 0x10, 16, 1), - PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x40, 0x10, 14, 1), - PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x40, 0x10, 4, 1), - PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x40, 0x10, 6, 1), - PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x40, 0x10, 2, 1), - PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x40, 0x10, 9, 1), - PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x40, 0x10, 5, 1), - PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x40, 0x10, 1, 1), - PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x40, 0x10, 14, 1), - PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x40, 0x10, 12, 1), - PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x40, 0x10, 4, 1), - PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x40, 0x10, 2, 1), - PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x40, 0x10, 8, 1), -}; - -static const struct mtk_pin_field_calc mt7986_pin_drv_range[] = { - PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x10, 0x10, 21, 3), - PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x10, 0x10, 0, 3), - PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x00, 0x10, 0, 1), - PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0x00, 0x10, 21, 3), - PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(11, 12, IOCFG_RB_BASE, 0x00, 0x10, 24, 3), - PIN_FIELD_BASE(13, 14, IOCFG_RB_BASE, 0x10, 0x10, 0, 3), - PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x10, 0x10, 6, 3), - PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x10, 0x10, 24, 3), - PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x10, 0x10, 21, 3), - PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x10, 0x10, 15, 3), - PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0x10, 0x10, 27, 3), - PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0x20, 0x10, 0, 3), - PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x20, 0x10, 9, 3), - PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x20, 0x10, 6, 3), - PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x20, 0x10, 3, 3), - PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x00, 0x10, 12, 3), - PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x00, 0x10, 24, 3), - PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x00, 0x10, 21, 3), - PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x00, 0x10, 15, 3), - PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x00, 0x10, 27, 3), - PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x10, 0x10, 27, 3), - PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x20, 0x10, 0, 3), - PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x10, 0x10, 6, 3), - PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x20, 0x10, 9, 3), - PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x20, 0x10, 3, 3), - PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x20, 0x10, 21, 3), - PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x20, 0x10, 15, 3), - PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x00, 0x10, 6, 3), - PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x10, 0x10, 0, 3), - PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x10, 0x10, 15, 3), - PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x10, 0x10, 12, 3), - PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x10, 0x10, 9, 3), - PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x10, 0x10, 18, 3), - PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x00, 0x10, 2, 3), - PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x10, 0x10, 18, 3), - PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x10, 0x10, 12, 3), - PIN_FIELD_BASE(74, 77, IOCFG_TR_BASE, 0x00, 0x10, 15, 3), - PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x00, 0x10, 6, 3), - PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x00, 0x10, 27, 3), - PIN_FIELD_BASE(81, 84, IOCFG_TR_BASE, 0x10, 0x10, 0, 3), - PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x00, 0x10, 12, 3), - PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x10, 0x10, 12, 3), - PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x10, 0x10, 6, 3), - PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x00, 0x10, 12, 3), - PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x00, 0x10, 6, 3), - PIN_FIELD_BASE(97, 98, IOCFG_TL_BASE, 0x00, 0x10, 24, 3), - PIN_FIELD_BASE(99, 100, IOCFG_TL_BASE, 0x10, 0x10, 2, 3), -}; - -static const struct mtk_pin_field_calc mt7986_pin_pupd_range[] = { - PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x60, 0x10, 17, 1), - PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x30, 0x10, 10, 1), - PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x60, 0x10, 0, 1), - PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x30, 0x10, 0, 1), - PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x60, 0x10, 8, 1), - PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x60, 0x10, 2, 1), - PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x40, 0x10, 12, 1), - PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x40, 0x10, 18, 1), - PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x40, 0x10, 17, 1), - PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x40, 0x10, 15, 1), - PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x40, 0x10, 19, 1), - PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x40, 0x10, 23, 1), - PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x40, 0x10, 22, 1), - PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x40, 0x10, 21, 1), - PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x30, 0x10, 4, 1), - PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x30, 0x10, 8, 1), - PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x30, 0x10, 7, 1), - PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x30, 0x10, 5, 1), - PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x30, 0x10, 9, 1), - PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x60, 0x10, 18, 1), - PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x60, 0x10, 12, 1), - PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x60, 0x10, 23, 1), - PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x60, 0x10, 21, 1), - PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x60, 0x10, 27, 1), - PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x60, 0x10, 25, 1), - PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x40, 0x10, 2, 1), - PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x40, 0x10, 1, 1), - PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x40, 0x10, 10, 1), - PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x60, 0x10, 15, 1), - PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x60, 0x10, 14, 1), - PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x60, 0x10, 13, 1), - PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x60, 0x10, 16, 1), - PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x40, 0x10, 2, 1), -}; - -static const struct mtk_pin_field_calc mt7986_pin_r0_range[] = { - PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x70, 0x10, 17, 1), - PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x40, 0x10, 10, 1), - PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x70, 0x10, 0, 1), - PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x70, 0x10, 8, 1), - PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x70, 0x10, 2, 1), - PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x50, 0x10, 12, 1), - PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x50, 0x10, 18, 1), - PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x50, 0x10, 17, 1), - PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x50, 0x10, 15, 1), - PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x50, 0x10, 19, 1), - PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x50, 0x10, 23, 1), - PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x50, 0x10, 22, 1), - PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x50, 0x10, 21, 1), - PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x40, 0x10, 4, 1), - PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x40, 0x10, 8, 1), - PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x40, 0x10, 7, 1), - PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x40, 0x10, 5, 1), - PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x40, 0x10, 9, 1), - PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x70, 0x10, 18, 1), - PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x70, 0x10, 12, 1), - PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x70, 0x10, 23, 1), - PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x70, 0x10, 21, 1), - PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x70, 0x10, 27, 1), - PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x70, 0x10, 25, 1), - PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x50, 0x10, 2, 1), - PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x50, 0x10, 1, 1), - PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x50, 0x10, 10, 1), - PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x70, 0x10, 15, 1), - PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x70, 0x10, 14, 1), - PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x70, 0x10, 13, 1), - PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x70, 0x10, 16, 1), - PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x50, 0x10, 2, 1), -}; - -static const struct mtk_pin_field_calc mt7986_pin_r1_range[] = { - PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x80, 0x10, 17, 1), - PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x50, 0x10, 10, 1), - PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x60, 0x10, 0, 1), - PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x80, 0x10, 0, 1), - PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x80, 0x10, 8, 1), - PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x80, 0x10, 2, 1), - PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x60, 0x10, 12, 1), - PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x60, 0x10, 18, 1), - PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x60, 0x10, 17, 1), - PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x60, 0x10, 15, 1), - PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x60, 0x10, 19, 1), - PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x60, 0x10, 23, 1), - PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x60, 0x10, 22, 1), - PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x60, 0x10, 21, 1), - PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x50, 0x10, 4, 1), - PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x50, 0x10, 8, 1), - PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x50, 0x10, 7, 1), - PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x50, 0x10, 5, 1), - PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x50, 0x10, 9, 1), - PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x80, 0x10, 18, 1), - PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x80, 0x10, 12, 1), - PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x80, 0x10, 23, 1), - PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x80, 0x10, 21, 1), - PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x80, 0x10, 27, 1), - PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x80, 0x10, 25, 1), - PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x60, 0x10, 2, 1), - PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x60, 0x10, 1, 1), - PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x60, 0x10, 0, 1), - PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x60, 0x10, 10, 1), - PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x80, 0x10, 15, 1), - PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x80, 0x10, 14, 1), - PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x80, 0x10, 13, 1), - PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x80, 0x10, 16, 1), - PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x60, 0x10, 2, 1), -}; - -static const unsigned int mt7986_pull_type[] = { - MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/ - MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/ - MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/ - MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/ - MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/ - MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/ - MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/ - MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/ - MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/ - MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/ - MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/ - MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/ - MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/ - MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/ - MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/ - MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/ - MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/ - MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/ - MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/ - MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/ - MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/ - MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/ - MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/ - MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/ - MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/ - MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/ - MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/ - MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/ - MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/ - MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/ - MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/ - MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/ - MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/ - MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/ - MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/ - MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/ - MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/ - MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/ - MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/ - MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/ - MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/ - MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/ - MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/ - MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/ - MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/ - MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/ - MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/ - MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/ - MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/ - MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/ - MTK_PULL_PU_PD_TYPE,/*100*/ -}; - -static const struct mtk_pin_reg_calc mt7986_reg_cals[] = { - [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7986_pin_mode_range), - [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7986_pin_dir_range), - [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7986_pin_di_range), - [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7986_pin_do_range), - [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7986_pin_smt_range), - [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7986_pin_ies_range), - [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7986_pin_drv_range), - [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7986_pin_pu_range), - [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7986_pin_pd_range), - [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7986_pin_pupd_range), - [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7986_pin_r0_range), - [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7986_pin_r1_range), -}; - -static const struct mtk_pin_desc mt7986a_pins[] = { - MT7986_PIN(0, "SYS_WATCHDOG"), - MT7986_PIN(1, "WF2G_LED"), - MT7986_PIN(2, "WF5G_LED"), - MT7986_PIN(3, "I2C_SCL"), - MT7986_PIN(4, "I2C_SDA"), - MT7986_PIN(5, "GPIO_0"), - MT7986_PIN(6, "GPIO_1"), - MT7986_PIN(7, "GPIO_2"), - MT7986_PIN(8, "GPIO_3"), - MT7986_PIN(9, "GPIO_4"), - MT7986_PIN(10, "GPIO_5"), - MT7986_PIN(11, "GPIO_6"), - MT7986_PIN(12, "GPIO_7"), - MT7986_PIN(13, "GPIO_8"), - MT7986_PIN(14, "GPIO_9"), - MT7986_PIN(15, "GPIO_10"), - MT7986_PIN(16, "GPIO_11"), - MT7986_PIN(17, "GPIO_12"), - MT7986_PIN(18, "GPIO_13"), - MT7986_PIN(19, "GPIO_14"), - MT7986_PIN(20, "GPIO_15"), - MT7986_PIN(21, "PWM0"), - MT7986_PIN(22, "PWM1"), - MT7986_PIN(23, "SPI0_CLK"), - MT7986_PIN(24, "SPI0_MOSI"), - MT7986_PIN(25, "SPI0_MISO"), - MT7986_PIN(26, "SPI0_CS"), - MT7986_PIN(27, "SPI0_HOLD"), - MT7986_PIN(28, "SPI0_WP"), - MT7986_PIN(29, "SPI1_CLK"), - MT7986_PIN(30, "SPI1_MOSI"), - MT7986_PIN(31, "SPI1_MISO"), - MT7986_PIN(32, "SPI1_CS"), - MT7986_PIN(33, "SPI2_CLK"), - MT7986_PIN(34, "SPI2_MOSI"), - MT7986_PIN(35, "SPI2_MISO"), - MT7986_PIN(36, "SPI2_CS"), - MT7986_PIN(37, "SPI2_HOLD"), - MT7986_PIN(38, "SPI2_WP"), - MT7986_PIN(39, "UART0_RXD"), - MT7986_PIN(40, "UART0_TXD"), - MT7986_PIN(41, "PCIE_PERESET_N"), - MT7986_PIN(42, "UART1_RXD"), - MT7986_PIN(43, "UART1_TXD"), - MT7986_PIN(44, "UART1_CTS"), - MT7986_PIN(45, "UART1_RTS"), - MT7986_PIN(46, "UART2_RXD"), - MT7986_PIN(47, "UART2_TXD"), - MT7986_PIN(48, "UART2_CTS"), - MT7986_PIN(49, "UART2_RTS"), - MT7986_PIN(50, "EMMC_DATA_0"), - MT7986_PIN(51, "EMMC_DATA_1"), - MT7986_PIN(52, "EMMC_DATA_2"), - MT7986_PIN(53, "EMMC_DATA_3"), - MT7986_PIN(54, "EMMC_DATA_4"), - MT7986_PIN(55, "EMMC_DATA_5"), - MT7986_PIN(56, "EMMC_DATA_6"), - MT7986_PIN(57, "EMMC_DATA_7"), - MT7986_PIN(58, "EMMC_CMD"), - MT7986_PIN(59, "EMMC_CK"), - MT7986_PIN(60, "EMMC_DSL"), - MT7986_PIN(61, "EMMC_RSTB"), - MT7986_PIN(62, "PCM_DTX"), - MT7986_PIN(63, "PCM_DRX"), - MT7986_PIN(64, "PCM_CLK"), - MT7986_PIN(65, "PCM_FS"), - MT7986_PIN(66, "MT7531_INT"), - MT7986_PIN(67, "SMI_MDC"), - MT7986_PIN(68, "SMI_MDIO"), - MT7986_PIN(69, "WF0_DIG_RESETB"), - MT7986_PIN(70, "WF0_CBA_RESETB"), - MT7986_PIN(71, "WF0_XO_REQ"), - MT7986_PIN(72, "WF0_TOP_CLK"), - MT7986_PIN(73, "WF0_TOP_DATA"), - MT7986_PIN(74, "WF0_HB1"), - MT7986_PIN(75, "WF0_HB2"), - MT7986_PIN(76, "WF0_HB3"), - MT7986_PIN(77, "WF0_HB4"), - MT7986_PIN(78, "WF0_HB0"), - MT7986_PIN(79, "WF0_HB0_B"), - MT7986_PIN(80, "WF0_HB5"), - MT7986_PIN(81, "WF0_HB6"), - MT7986_PIN(82, "WF0_HB7"), - MT7986_PIN(83, "WF0_HB8"), - MT7986_PIN(84, "WF0_HB9"), - MT7986_PIN(85, "WF0_HB10"), - MT7986_PIN(86, "WF1_DIG_RESETB"), - MT7986_PIN(87, "WF1_CBA_RESETB"), - MT7986_PIN(88, "WF1_XO_REQ"), - MT7986_PIN(89, "WF1_TOP_CLK"), - MT7986_PIN(90, "WF1_TOP_DATA"), - MT7986_PIN(91, "WF1_HB1"), - MT7986_PIN(92, "WF1_HB2"), - MT7986_PIN(93, "WF1_HB3"), - MT7986_PIN(94, "WF1_HB4"), - MT7986_PIN(95, "WF1_HB0"), - MT7986_PIN(96, "WF1_HB0_B"), - MT7986_PIN(97, "WF1_HB5"), - MT7986_PIN(98, "WF1_HB6"), - MT7986_PIN(99, "WF1_HB7"), - MT7986_PIN(100, "WF1_HB8"), -}; - -static const struct mtk_pin_desc mt7986b_pins[] = { - MT7986_PIN(0, "SYS_WATCHDOG"), - MT7986_PIN(1, "WF2G_LED"), - MT7986_PIN(2, "WF5G_LED"), - MT7986_PIN(3, "I2C_SCL"), - MT7986_PIN(4, "I2C_SDA"), - MT7986_PIN(5, "GPIO_0"), - MT7986_PIN(6, "GPIO_1"), - MT7986_PIN(7, "GPIO_2"), - MT7986_PIN(8, "GPIO_3"), - MT7986_PIN(9, "GPIO_4"), - MT7986_PIN(10, "GPIO_5"), - MT7986_PIN(11, "GPIO_6"), - MT7986_PIN(12, "GPIO_7"), - MT7986_PIN(13, "GPIO_8"), - MT7986_PIN(14, "GPIO_9"), - MT7986_PIN(15, "GPIO_10"), - MT7986_PIN(16, "GPIO_11"), - MT7986_PIN(17, "GPIO_12"), - MT7986_PIN(18, "GPIO_13"), - MT7986_PIN(19, "GPIO_14"), - MT7986_PIN(20, "GPIO_15"), - MT7986_PIN(21, "PWM0"), - MT7986_PIN(22, "PWM1"), - MT7986_PIN(23, "SPI0_CLK"), - MT7986_PIN(24, "SPI0_MOSI"), - MT7986_PIN(25, "SPI0_MISO"), - MT7986_PIN(26, "SPI0_CS"), - MT7986_PIN(27, "SPI0_HOLD"), - MT7986_PIN(28, "SPI0_WP"), - MT7986_PIN(29, "SPI1_CLK"), - MT7986_PIN(30, "SPI1_MOSI"), - MT7986_PIN(31, "SPI1_MISO"), - MT7986_PIN(32, "SPI1_CS"), - MT7986_PIN(33, "SPI2_CLK"), - MT7986_PIN(34, "SPI2_MOSI"), - MT7986_PIN(35, "SPI2_MISO"), - MT7986_PIN(36, "SPI2_CS"), - MT7986_PIN(37, "SPI2_HOLD"), - MT7986_PIN(38, "SPI2_WP"), - MT7986_PIN(39, "UART0_RXD"), - MT7986_PIN(40, "UART0_TXD"), - MT7986_NOT_BALLOUT_PIN(41), - MT7986_NOT_BALLOUT_PIN(42), - MT7986_NOT_BALLOUT_PIN(43), - MT7986_NOT_BALLOUT_PIN(44), - MT7986_NOT_BALLOUT_PIN(45), - MT7986_NOT_BALLOUT_PIN(46), - MT7986_NOT_BALLOUT_PIN(47), - MT7986_NOT_BALLOUT_PIN(48), - MT7986_NOT_BALLOUT_PIN(49), - MT7986_NOT_BALLOUT_PIN(50), - MT7986_NOT_BALLOUT_PIN(51), - MT7986_NOT_BALLOUT_PIN(52), - MT7986_NOT_BALLOUT_PIN(53), - MT7986_NOT_BALLOUT_PIN(54), - MT7986_NOT_BALLOUT_PIN(55), - MT7986_NOT_BALLOUT_PIN(56), - MT7986_NOT_BALLOUT_PIN(57), - MT7986_NOT_BALLOUT_PIN(58), - MT7986_NOT_BALLOUT_PIN(59), - MT7986_NOT_BALLOUT_PIN(60), - MT7986_NOT_BALLOUT_PIN(61), - MT7986_NOT_BALLOUT_PIN(62), - MT7986_NOT_BALLOUT_PIN(63), - MT7986_NOT_BALLOUT_PIN(64), - MT7986_NOT_BALLOUT_PIN(65), - MT7986_PIN(66, "MT7531_INT"), - MT7986_PIN(67, "SMI_MDC"), - MT7986_PIN(68, "SMI_MDIO"), - MT7986_PIN(69, "WF0_DIG_RESETB"), - MT7986_PIN(70, "WF0_CBA_RESETB"), - MT7986_PIN(71, "WF0_XO_REQ"), - MT7986_PIN(72, "WF0_TOP_CLK"), - MT7986_PIN(73, "WF0_TOP_DATA"), - MT7986_PIN(74, "WF0_HB1"), - MT7986_PIN(75, "WF0_HB2"), - MT7986_PIN(76, "WF0_HB3"), - MT7986_PIN(77, "WF0_HB4"), - MT7986_PIN(78, "WF0_HB0"), - MT7986_PIN(79, "WF0_HB0_B"), - MT7986_PIN(80, "WF0_HB5"), - MT7986_PIN(81, "WF0_HB6"), - MT7986_PIN(82, "WF0_HB7"), - MT7986_PIN(83, "WF0_HB8"), - MT7986_PIN(84, "WF0_HB9"), - MT7986_PIN(85, "WF0_HB10"), - MT7986_PIN(86, "WF1_DIG_RESETB"), - MT7986_PIN(87, "WF1_CBA_RESETB"), - MT7986_PIN(88, "WF1_XO_REQ"), - MT7986_PIN(89, "WF1_TOP_CLK"), - MT7986_PIN(90, "WF1_TOP_DATA"), - MT7986_PIN(91, "WF1_HB1"), - MT7986_PIN(92, "WF1_HB2"), - MT7986_PIN(93, "WF1_HB3"), - MT7986_PIN(94, "WF1_HB4"), - MT7986_PIN(95, "WF1_HB0"), - MT7986_PIN(96, "WF1_HB0_B"), - MT7986_PIN(97, "WF1_HB5"), - MT7986_PIN(98, "WF1_HB6"), - MT7986_PIN(99, "WF1_HB7"), - MT7986_PIN(100, "WF1_HB8"), -}; - -/* List all groups consisting of these pins dedicated to the enablement of - * certain hardware block and the corresponding mode for all of the pins. - * The hardware probably has multiple combinations of these pinouts. - */ - -static int mt7986_watchdog_pins[] = { 0, }; -static int mt7986_watchdog_funcs[] = { 1, }; - -static int mt7986_wifi_led_pins[] = { 1, 2, }; -static int mt7986_wifi_led_funcs[] = { 1, 1, }; - -static int mt7986_i2c_pins[] = { 3, 4, }; -static int mt7986_i2c_funcs[] = { 1, 1, }; - -static int mt7986_uart1_0_pins[] = { 7, 8, 9, 10, }; -static int mt7986_uart1_0_funcs[] = { 3, 3, 3, 3, }; - -static int mt7986_spi1_0_pins[] = { 11, 12, 13, 14, }; -static int mt7986_spi1_0_funcs[] = { 3, 3, 3, 3, }; - -static int mt7986_pwm1_1_pins[] = { 20, }; -static int mt7986_pwm1_1_funcs[] = { 2, }; - -static int mt7986_pwm0_pins[] = { 21, }; -static int mt7986_pwm0_funcs[] = { 1, }; - -static int mt7986_pwm1_0_pins[] = { 22, }; -static int mt7986_pwm1_0_funcs[] = { 1, }; - -static int mt7986_emmc_45_pins[] = { - 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, }; -static int mt7986_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; - -static int mt7986_snfi_pins[] = { 23, 24, 25, 26, 27, 28, }; -static int mt7986_snfi_funcs[] = { 1, 1, 1, 1, 1, 1, }; - -static int mt7986_spi1_1_pins[] = { 23, 24, 25, 26, }; -static int mt7986_spi1_1_funcs[] = { 3, 3, 3, 3, }; - -static int mt7986_uart1_1_pins[] = { 23, 24, 25, 26, }; -static int mt7986_uart1_1_funcs[] = { 4, 4, 4, 4, }; - -static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, }; -static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, }; - -static int mt7986_uart1_2_rx_tx_pins[] = { 29, 30, }; -static int mt7986_uart1_2_rx_tx_funcs[] = { 3, 3, }; - -static int mt7986_uart1_2_cts_rts_pins[] = { 31, 32, }; -static int mt7986_uart1_2_cts_rts_funcs[] = { 3, 3, }; - -static int mt7986_uart2_0_rx_tx_pins[] = { 29, 30, }; -static int mt7986_uart2_0_rx_tx_funcs[] = { 4, 4, }; - -static int mt7986_uart2_0_cts_rts_pins[] = { 31, 32, }; -static int mt7986_uart2_0_cts_rts_funcs[] = { 4, 4, }; - -static int mt7986_spi0_pins[] = { 33, 34, 35, 36, }; -static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, }; - -static int mt7986_spi0_wp_hold_pins[] = { 37, 38, }; -static int mt7986_spi0_wp_hold_funcs[] = { 1, 1, }; - -static int mt7986_uart2_1_pins[] = { 33, 34, 35, 36, }; -static int mt7986_uart2_1_funcs[] = { 3, 3, 3, 3, }; - -static int mt7986_uart1_3_rx_tx_pins[] = { 35, 36, }; -static int mt7986_uart1_3_rx_tx_funcs[] = { 2, 2, }; - -static int mt7986_uart1_3_cts_rts_pins[] = { 37, 38, }; -static int mt7986_uart1_3_cts_rts_funcs[] = { 2, 2, }; - -static int mt7986_spi1_3_pins[] = { 33, 34, 35, 36, }; -static int mt7986_spi1_3_funcs[] = { 4, 4, 4, 4, }; - -static int mt7986_uart0_pins[] = { 39, 40, }; -static int mt7986_uart0_funcs[] = { 1, 1, }; - -static int mt7986_pcie_reset_pins[] = { 41, }; -static int mt7986_pcie_reset_funcs[] = { 1, }; - -static int mt7986_uart1_pins[] = { 42, 43, 44, 45, }; -static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, }; - -static int mt7986_uart1_rx_tx_pins[] = { 42, 43, }; -static int mt7986_uart1_rx_tx_funcs[] = { 1, 1, }; - -static int mt7986_uart1_cts_rts_pins[] = { 44, 45, }; -static int mt7986_uart1_cts_rts_funcs[] = { 1, 1, }; - -static int mt7986_uart2_pins[] = { 46, 47, 48, 49, }; -static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, }; - -static int mt7986_emmc_51_pins[] = { - 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, }; -static int mt7986_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; - -static int mt7986_pcm_pins[] = { 62, 63, 64, 65, }; -static int mt7986_pcm_funcs[] = { 1, 1, 1, 1, }; - -static int mt7986_i2s_pins[] = { 62, 63, 64, 65, }; -static int mt7986_i2s_funcs[] = { 1, 1, 1, 1, }; - -static int mt7986_switch_int_pins[] = { 66, }; -static int mt7986_switch_int_funcs[] = { 1, }; - -static int mt7986_mdc_mdio_pins[] = { 67, 68, }; -static int mt7986_mdc_mdio_funcs[] = { 1, 1, }; - -static int mt7986_wf_2g_pins[] = {74, 75, 76, 77, 78, 79, 80, 81, 82, 83, }; -static int mt7986_wf_2g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; - -static int mt7986_wf_5g_pins[] = {91, 92, 93, 94, 95, 96, 97, 98, 99, 100, }; -static int mt7986_wf_5g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; - -static int mt7986_wf_dbdc_pins[] = { - 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, }; -static int mt7986_wf_dbdc_funcs[] = { - 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; - -static int mt7986_pcie_clk_pins[] = { 9, }; -static int mt7986_pcie_clk_funcs[] = { 1, }; - -static int mt7986_pcie_wake_pins[] = { 10, }; -static int mt7986_pcie_wake_funcs[] = { 1, }; - -static const struct group_desc mt7986_groups[] = { - PINCTRL_PIN_GROUP("watchdog", mt7986_watchdog), - PINCTRL_PIN_GROUP("wifi_led", mt7986_wifi_led), - PINCTRL_PIN_GROUP("i2c", mt7986_i2c), - PINCTRL_PIN_GROUP("uart1_0", mt7986_uart1_0), - PINCTRL_PIN_GROUP("uart1_rx_tx", mt7986_uart1_rx_tx), - PINCTRL_PIN_GROUP("uart1_cts_rts", mt7986_uart1_cts_rts), - PINCTRL_PIN_GROUP("pcie_clk", mt7986_pcie_clk), - PINCTRL_PIN_GROUP("pcie_wake", mt7986_pcie_wake), - PINCTRL_PIN_GROUP("spi1_0", mt7986_spi1_0), - PINCTRL_PIN_GROUP("pwm1_1", mt7986_pwm1_1), - PINCTRL_PIN_GROUP("pwm0", mt7986_pwm0), - PINCTRL_PIN_GROUP("pwm1_0", mt7986_pwm1_0), - PINCTRL_PIN_GROUP("emmc_45", mt7986_emmc_45), - PINCTRL_PIN_GROUP("snfi", mt7986_snfi), - PINCTRL_PIN_GROUP("spi1_1", mt7986_spi1_1), - PINCTRL_PIN_GROUP("uart1_1", mt7986_uart1_1), - PINCTRL_PIN_GROUP("spi1_2", mt7986_spi1_2), - PINCTRL_PIN_GROUP("uart1_2_rx_tx", mt7986_uart1_2_rx_tx), - PINCTRL_PIN_GROUP("uart1_2_cts_rts", mt7986_uart1_2_cts_rts), - PINCTRL_PIN_GROUP("uart2_0_rx_tx", mt7986_uart2_0_rx_tx), - PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7986_uart2_0_cts_rts), - PINCTRL_PIN_GROUP("spi0", mt7986_spi0), - PINCTRL_PIN_GROUP("spi0_wp_hold", mt7986_spi0_wp_hold), - PINCTRL_PIN_GROUP("uart2_1", mt7986_uart2_1), - PINCTRL_PIN_GROUP("uart1_3_rx_tx", mt7986_uart1_3_rx_tx), - PINCTRL_PIN_GROUP("uart1_3_cts_rts", mt7986_uart1_3_cts_rts), - PINCTRL_PIN_GROUP("spi1_3", mt7986_spi1_3), - PINCTRL_PIN_GROUP("uart0", mt7986_uart0), - PINCTRL_PIN_GROUP("switch_int", mt7986_switch_int), - PINCTRL_PIN_GROUP("mdc_mdio", mt7986_mdc_mdio), - PINCTRL_PIN_GROUP("pcie_pereset", mt7986_pcie_reset), - PINCTRL_PIN_GROUP("uart1", mt7986_uart1), - PINCTRL_PIN_GROUP("uart2", mt7986_uart2), - PINCTRL_PIN_GROUP("emmc_51", mt7986_emmc_51), - PINCTRL_PIN_GROUP("pcm", mt7986_pcm), - PINCTRL_PIN_GROUP("i2s", mt7986_i2s), - PINCTRL_PIN_GROUP("wf_2g", mt7986_wf_2g), - PINCTRL_PIN_GROUP("wf_5g", mt7986_wf_5g), - PINCTRL_PIN_GROUP("wf_dbdc", mt7986_wf_dbdc), -}; - -/* Joint those groups owning the same capability in user point of view which - * allows that people tend to use through the device tree. - */ - -static const char *mt7986_audio_groups[] = { "pcm", "i2s" }; -static const char *mt7986_emmc_groups[] = { - "emmc_45", "emmc_51", }; -static const char *mt7986_ethernet_groups[] = { - "switch_int", "mdc_mdio", }; -static const char *mt7986_i2c_groups[] = { "i2c", }; -static const char *mt7986_led_groups[] = { "wifi_led", }; -static const char *mt7986_flash_groups[] = { "snfi", }; -static const char *mt7986_pcie_groups[] = { - "pcie_clk", "pcie_wake", "pcie_pereset" }; -static const char *mt7986_pwm_groups[] = { "pwm0", "pwm1_0", "pwm1_1", }; -static const char *mt7986_spi_groups[] = { - "spi0", "spi0_wp_hold", "spi1_0", "spi1_1", "spi1_2", "spi1_3", }; -static const char *mt7986_uart_groups[] = { - "uart1_0", "uart1_1", "uart1_rx_tx", "uart1_cts_rts", - "uart1_2_rx_tx", "uart1_2_cts_rts", - "uart1_3_rx_tx", "uart1_3_cts_rts", "uart2_0_rx_tx", "uart2_0_cts_rts", - "uart2_0", "uart2_1", "uart0", "uart1", "uart2", -}; -static const char *mt7986_wdt_groups[] = { "watchdog", }; -static const char *mt7986_wf_groups[] = { "wf_2g", "wf_5g", "wf_dbdc", }; - -static const struct function_desc mt7986_functions[] = { - {"audio", mt7986_audio_groups, ARRAY_SIZE(mt7986_audio_groups)}, - {"emmc", mt7986_emmc_groups, ARRAY_SIZE(mt7986_emmc_groups)}, - {"eth", mt7986_ethernet_groups, ARRAY_SIZE(mt7986_ethernet_groups)}, - {"i2c", mt7986_i2c_groups, ARRAY_SIZE(mt7986_i2c_groups)}, - {"led", mt7986_led_groups, ARRAY_SIZE(mt7986_led_groups)}, - {"flash", mt7986_flash_groups, ARRAY_SIZE(mt7986_flash_groups)}, - {"pcie", mt7986_pcie_groups, ARRAY_SIZE(mt7986_pcie_groups)}, - {"pwm", mt7986_pwm_groups, ARRAY_SIZE(mt7986_pwm_groups)}, - {"spi", mt7986_spi_groups, ARRAY_SIZE(mt7986_spi_groups)}, - {"uart", mt7986_uart_groups, ARRAY_SIZE(mt7986_uart_groups)}, - {"watchdog", mt7986_wdt_groups, ARRAY_SIZE(mt7986_wdt_groups)}, - {"wifi", mt7986_wf_groups, ARRAY_SIZE(mt7986_wf_groups)}, -}; - -static const struct mtk_eint_hw mt7986a_eint_hw = { - .port_mask = 7, - .ports = 7, - .ap_num = ARRAY_SIZE(mt7986a_pins), - .db_cnt = 16, - .db_time = debounce_time_mt6765, -}; - -static const struct mtk_eint_hw mt7986b_eint_hw = { - .port_mask = 7, - .ports = 7, - .ap_num = ARRAY_SIZE(mt7986b_pins), - .db_cnt = 16, - .db_time = debounce_time_mt6765, -}; - -static struct mtk_pin_soc mt7986a_data = { - .reg_cal = mt7986_reg_cals, - .pins = mt7986a_pins, - .npins = ARRAY_SIZE(mt7986a_pins), - .grps = mt7986_groups, - .ngrps = ARRAY_SIZE(mt7986_groups), - .funcs = mt7986_functions, - .nfuncs = ARRAY_SIZE(mt7986_functions), - .eint_hw = &mt7986a_eint_hw, - .gpio_m = 0, - .ies_present = false, - .base_names = mt7986_pinctrl_register_base_names, - .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), - .pull_type = mt7986_pull_type, - .bias_set_combo = mtk_pinconf_bias_set_combo, - .bias_get_combo = mtk_pinconf_bias_get_combo, - .drive_set = mtk_pinconf_drive_set_rev1, - .drive_get = mtk_pinconf_drive_get_rev1, - .adv_pull_get = mtk_pinconf_adv_pull_get, - .adv_pull_set = mtk_pinconf_adv_pull_set, -}; - -static struct mtk_pin_soc mt7986b_data = { - .reg_cal = mt7986_reg_cals, - .pins = mt7986b_pins, - .npins = ARRAY_SIZE(mt7986b_pins), - .grps = mt7986_groups, - .ngrps = ARRAY_SIZE(mt7986_groups), - .funcs = mt7986_functions, - .nfuncs = ARRAY_SIZE(mt7986_functions), - .eint_hw = &mt7986b_eint_hw, - .gpio_m = 0, - .ies_present = false, - .base_names = mt7986_pinctrl_register_base_names, - .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), - .pull_type = mt7986_pull_type, - .bias_set_combo = mtk_pinconf_bias_set_combo, - .bias_get_combo = mtk_pinconf_bias_get_combo, - .drive_set = mtk_pinconf_drive_set_rev1, - .drive_get = mtk_pinconf_drive_get_rev1, - .adv_pull_get = mtk_pinconf_adv_pull_get, - .adv_pull_set = mtk_pinconf_adv_pull_set, -}; - -static const struct of_device_id mt7986a_pinctrl_of_match[] = { - {.compatible = "mediatek,mt7986a-pinctrl",}, - {} -}; - -static const struct of_device_id mt7986b_pinctrl_of_match[] = { - {.compatible = "mediatek,mt7986b-pinctrl",}, - {} -}; - -static int mt7986a_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_moore_pinctrl_probe(pdev, &mt7986a_data); -} - -static int mt7986b_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_moore_pinctrl_probe(pdev, &mt7986b_data); -} - -static struct platform_driver mt7986a_pinctrl_driver = { - .driver = { - .name = "mt7986a-pinctrl", - .of_match_table = mt7986a_pinctrl_of_match, - }, - .probe = mt7986a_pinctrl_probe, -}; - -static struct platform_driver mt7986b_pinctrl_driver = { - .driver = { - .name = "mt7986b-pinctrl", - .of_match_table = mt7986b_pinctrl_of_match, - }, - .probe = mt7986b_pinctrl_probe, -}; - -static int __init mt7986a_pinctrl_init(void) -{ - return platform_driver_register(&mt7986a_pinctrl_driver); -} - -static int __init mt7986b_pinctrl_init(void) -{ - return platform_driver_register(&mt7986b_pinctrl_driver); -} - -arch_initcall(mt7986a_pinctrl_init); -arch_initcall(mt7986b_pinctrl_init); diff --git a/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c b/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c index 80a7e19f7a2..da0269ed7a2 100644 --- a/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c +++ b/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c @@ -1096,20 +1096,20 @@ static const struct group_desc mt7988_groups[] = { /* Joint those groups owning the same capability in user point of view which * allows that people tend to use through the device tree. */ -static const char *mt7988_jtag_groups[] = { +static const char * const mt7988_jtag_groups[] = { "tops_jtag0_0", "wo0_jtag", "wo1_jtag", "wo2_jtag", "jtag", "tops_jtag0_1", }; -static const char *mt7988_int_usxgmii_groups[] = { +static const char * const mt7988_int_usxgmii_groups[] = { "int_usxgmii", }; -static const char *mt7988_pwm_groups[] = { +static const char * const mt7988_pwm_groups[] = { "pwm0", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5", "pwm6", "pwm7" }; -static const char *mt7988_dfd_groups[] = { +static const char * const mt7988_dfd_groups[] = { "dfd", }; -static const char *mt7988_i2c_groups[] = { +static const char * const mt7988_i2c_groups[] = { "xfi_phy0_i2c0", "xfi_phy1_i2c0", "xfi_phy_pll_i2c0", @@ -1134,13 +1134,13 @@ static const char *mt7988_i2c_groups[] = { "i2c2_0", "i2c2_1", }; -static const char *mt7988_ethernet_groups[] = { +static const char * const mt7988_ethernet_groups[] = { "mdc_mdio0", "2p5g_ext_mdio", "gbe_ext_mdio", "mdc_mdio1", }; -static const char *mt7988_pcie_groups[] = { +static const char * const mt7988_pcie_groups[] = { "pcie_wake_n0_0", "pcie_clk_req_n0_0", "pcie_wake_n3_0", "pcie_clk_req_n3", "pcie_p0_phy_i2c", "pcie_p1_phy_i2c", "pcie_p3_phy_i2c", "pcie_p2_phy_i2c", "ckm_phy_i2c", @@ -1150,18 +1150,18 @@ static const char *mt7988_pcie_groups[] = { "pcie_wake_n2_0", "pcie_clk_req_n2_0", "pcie_wake_n2_1", "pcie_clk_req_n0_1" }; -static const char *mt7988_pmic_groups[] = { +static const char * const mt7988_pmic_groups[] = { "pmic", }; -static const char *mt7988_wdt_groups[] = { +static const char * const mt7988_wdt_groups[] = { "watchdog", }; -static const char *mt7988_spi_groups[] = { +static const char * const mt7988_spi_groups[] = { "spi0", "spi0_wp_hold", "spi1", "spi2", "spi2_wp_hold", }; -static const char *mt7988_flash_groups[] = { "emmc_45", "sdcard", "snfi", +static const char * const mt7988_flash_groups[] = { "emmc_45", "sdcard", "snfi", "emmc_51" }; -static const char *mt7988_uart_groups[] = { +static const char * const mt7988_uart_groups[] = { "uart2", "tops_uart0_0", "uart2_0", @@ -1183,18 +1183,18 @@ static const char *mt7988_uart_groups[] = { "net_wo1_uart_txd_1", "net_wo2_uart_txd_1", }; -static const char *mt7988_udi_groups[] = { +static const char * const mt7988_udi_groups[] = { "udi", }; -static const char *mt7988_audio_groups[] = { +static const char * const mt7988_audio_groups[] = { "i2s", "pcm", }; -static const char *mt7988_led_groups[] = { +static const char * const mt7988_led_groups[] = { "gbe0_led1", "gbe1_led1", "gbe2_led1", "gbe3_led1", "2p5gbe_led1", "gbe0_led0", "gbe1_led0", "gbe2_led0", "gbe3_led0", "2p5gbe_led0", "wf5g_led0", "wf5g_led1", }; -static const char *mt7988_usb_groups[] = { +static const char * const mt7988_usb_groups[] = { "drv_vbus", "drv_vbus_p1", }; @@ -1226,7 +1226,7 @@ static const struct mtk_eint_hw mt7988_eint_hw = { .db_cnt = 16, }; -static const char *mt7988_pinctrl_register_base_names[] = { +static const char * const mt7988_pinctrl_register_base_names[] = { "gpio_base", "iocfg_tr_base", "iocfg_br_base", "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base", }; @@ -1279,3 +1279,4 @@ static int __init mt7988_pinctrl_init(void) return platform_driver_register(&mt7988_pinctrl_driver); } arch_initcall(mt7988_pinctrl_init); + diff --git a/target/linux/mediatek/files-6.1/include/dt-bindings/clock/mediatek,mt7981-clk.h b/target/linux/mediatek/files-6.1/include/dt-bindings/clock/mediatek,mt7981-clk.h deleted file mode 100644 index 192f8cefb58..00000000000 --- a/target/linux/mediatek/files-6.1/include/dt-bindings/clock/mediatek,mt7981-clk.h +++ /dev/null @@ -1,215 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (c) 2021 MediaTek Inc. - * Author: Wenzhen.Yu - * Author: Jianhui Zhao - * Author: Daniel Golle - */ - -#ifndef _DT_BINDINGS_CLK_MT7981_H -#define _DT_BINDINGS_CLK_MT7981_H - -/* TOPCKGEN */ -#define CLK_TOP_CB_CKSQ_40M 0 -#define CLK_TOP_CB_M_416M 1 -#define CLK_TOP_CB_M_D2 2 -#define CLK_TOP_CB_M_D3 3 -#define CLK_TOP_M_D3_D2 4 -#define CLK_TOP_CB_M_D4 5 -#define CLK_TOP_CB_M_D8 6 -#define CLK_TOP_M_D8_D2 7 -#define CLK_TOP_CB_MM_720M 8 -#define CLK_TOP_CB_MM_D2 9 -#define CLK_TOP_CB_MM_D3 10 -#define CLK_TOP_CB_MM_D3_D5 11 -#define CLK_TOP_CB_MM_D4 12 -#define CLK_TOP_CB_MM_D6 13 -#define CLK_TOP_MM_D6_D2 14 -#define CLK_TOP_CB_MM_D8 15 -#define CLK_TOP_CB_APLL2_196M 16 -#define CLK_TOP_APLL2_D2 17 -#define CLK_TOP_APLL2_D4 18 -#define CLK_TOP_NET1_2500M 19 -#define CLK_TOP_CB_NET1_D4 20 -#define CLK_TOP_CB_NET1_D5 21 -#define CLK_TOP_NET1_D5_D2 22 -#define CLK_TOP_NET1_D5_D4 23 -#define CLK_TOP_CB_NET1_D8 24 -#define CLK_TOP_NET1_D8_D2 25 -#define CLK_TOP_NET1_D8_D4 26 -#define CLK_TOP_CB_NET2_800M 27 -#define CLK_TOP_CB_NET2_D2 28 -#define CLK_TOP_CB_NET2_D4 29 -#define CLK_TOP_NET2_D4_D2 30 -#define CLK_TOP_NET2_D4_D4 31 -#define CLK_TOP_CB_NET2_D6 32 -#define CLK_TOP_CB_WEDMCU_208M 33 -#define CLK_TOP_CB_SGM_325M 34 -#define CLK_TOP_CKSQ_40M_D2 35 -#define CLK_TOP_CB_RTC_32K 36 -#define CLK_TOP_CB_RTC_32P7K 37 -#define CLK_TOP_USB_TX250M 38 -#define CLK_TOP_FAUD 39 -#define CLK_TOP_NFI1X 40 -#define CLK_TOP_USB_EQ_RX250M 41 -#define CLK_TOP_USB_CDR_CK 42 -#define CLK_TOP_USB_LN0_CK 43 -#define CLK_TOP_SPINFI_BCK 44 -#define CLK_TOP_SPI 45 -#define CLK_TOP_SPIM_MST 46 -#define CLK_TOP_UART_BCK 47 -#define CLK_TOP_PWM_BCK 48 -#define CLK_TOP_I2C_BCK 49 -#define CLK_TOP_PEXTP_TL 50 -#define CLK_TOP_EMMC_208M 51 -#define CLK_TOP_EMMC_400M 52 -#define CLK_TOP_DRAMC_REF 53 -#define CLK_TOP_DRAMC_MD32 54 -#define CLK_TOP_SYSAXI 55 -#define CLK_TOP_SYSAPB 56 -#define CLK_TOP_ARM_DB_MAIN 57 -#define CLK_TOP_AP2CNN_HOST 58 -#define CLK_TOP_NETSYS 59 -#define CLK_TOP_NETSYS_500M 60 -#define CLK_TOP_NETSYS_WED_MCU 61 -#define CLK_TOP_NETSYS_2X 62 -#define CLK_TOP_SGM_325M 63 -#define CLK_TOP_SGM_REG 64 -#define CLK_TOP_F26M 65 -#define CLK_TOP_EIP97B 66 -#define CLK_TOP_USB3_PHY 67 -#define CLK_TOP_AUD 68 -#define CLK_TOP_A1SYS 69 -#define CLK_TOP_AUD_L 70 -#define CLK_TOP_A_TUNER 71 -#define CLK_TOP_U2U3_REF 72 -#define CLK_TOP_U2U3_SYS 73 -#define CLK_TOP_U2U3_XHCI 74 -#define CLK_TOP_USB_FRMCNT 75 -#define CLK_TOP_NFI1X_SEL 76 -#define CLK_TOP_SPINFI_SEL 77 -#define CLK_TOP_SPI_SEL 78 -#define CLK_TOP_SPIM_MST_SEL 79 -#define CLK_TOP_UART_SEL 80 -#define CLK_TOP_PWM_SEL 81 -#define CLK_TOP_I2C_SEL 82 -#define CLK_TOP_PEXTP_TL_SEL 83 -#define CLK_TOP_EMMC_208M_SEL 84 -#define CLK_TOP_EMMC_400M_SEL 85 -#define CLK_TOP_F26M_SEL 86 -#define CLK_TOP_DRAMC_SEL 87 -#define CLK_TOP_DRAMC_MD32_SEL 88 -#define CLK_TOP_SYSAXI_SEL 89 -#define CLK_TOP_SYSAPB_SEL 90 -#define CLK_TOP_ARM_DB_MAIN_SEL 91 -#define CLK_TOP_AP2CNN_HOST_SEL 92 -#define CLK_TOP_NETSYS_SEL 93 -#define CLK_TOP_NETSYS_500M_SEL 94 -#define CLK_TOP_NETSYS_MCU_SEL 95 -#define CLK_TOP_NETSYS_2X_SEL 96 -#define CLK_TOP_SGM_325M_SEL 97 -#define CLK_TOP_SGM_REG_SEL 98 -#define CLK_TOP_EIP97B_SEL 99 -#define CLK_TOP_USB3_PHY_SEL 100 -#define CLK_TOP_AUD_SEL 101 -#define CLK_TOP_A1SYS_SEL 102 -#define CLK_TOP_AUD_L_SEL 103 -#define CLK_TOP_A_TUNER_SEL 104 -#define CLK_TOP_U2U3_SEL 105 -#define CLK_TOP_U2U3_SYS_SEL 106 -#define CLK_TOP_U2U3_XHCI_SEL 107 -#define CLK_TOP_USB_FRMCNT_SEL 108 -#define CLK_TOP_AUD_I2S_M 109 - -/* INFRACFG */ -#define CLK_INFRA_66M_MCK 0 -#define CLK_INFRA_UART0_SEL 1 -#define CLK_INFRA_UART1_SEL 2 -#define CLK_INFRA_UART2_SEL 3 -#define CLK_INFRA_SPI0_SEL 4 -#define CLK_INFRA_SPI1_SEL 5 -#define CLK_INFRA_SPI2_SEL 6 -#define CLK_INFRA_PWM1_SEL 7 -#define CLK_INFRA_PWM2_SEL 8 -#define CLK_INFRA_PWM3_SEL 9 -#define CLK_INFRA_PWM_BSEL 10 -#define CLK_INFRA_PCIE_SEL 11 -#define CLK_INFRA_GPT_STA 12 -#define CLK_INFRA_PWM_HCK 13 -#define CLK_INFRA_PWM_STA 14 -#define CLK_INFRA_PWM1_CK 15 -#define CLK_INFRA_PWM2_CK 16 -#define CLK_INFRA_PWM3_CK 17 -#define CLK_INFRA_CQ_DMA_CK 18 -#define CLK_INFRA_AUD_BUS_CK 19 -#define CLK_INFRA_AUD_26M_CK 20 -#define CLK_INFRA_AUD_L_CK 21 -#define CLK_INFRA_AUD_AUD_CK 22 -#define CLK_INFRA_AUD_EG2_CK 23 -#define CLK_INFRA_DRAMC_26M_CK 24 -#define CLK_INFRA_DBG_CK 25 -#define CLK_INFRA_AP_DMA_CK 26 -#define CLK_INFRA_SEJ_CK 27 -#define CLK_INFRA_SEJ_13M_CK 28 -#define CLK_INFRA_THERM_CK 29 -#define CLK_INFRA_I2C0_CK 30 -#define CLK_INFRA_UART0_CK 31 -#define CLK_INFRA_UART1_CK 32 -#define CLK_INFRA_UART2_CK 33 -#define CLK_INFRA_SPI2_CK 34 -#define CLK_INFRA_SPI2_HCK_CK 35 -#define CLK_INFRA_NFI1_CK 36 -#define CLK_INFRA_SPINFI1_CK 37 -#define CLK_INFRA_NFI_HCK_CK 38 -#define CLK_INFRA_SPI0_CK 39 -#define CLK_INFRA_SPI1_CK 40 -#define CLK_INFRA_SPI0_HCK_CK 41 -#define CLK_INFRA_SPI1_HCK_CK 42 -#define CLK_INFRA_FRTC_CK 43 -#define CLK_INFRA_MSDC_CK 44 -#define CLK_INFRA_MSDC_HCK_CK 45 -#define CLK_INFRA_MSDC_133M_CK 46 -#define CLK_INFRA_MSDC_66M_CK 47 -#define CLK_INFRA_ADC_26M_CK 48 -#define CLK_INFRA_ADC_FRC_CK 49 -#define CLK_INFRA_FBIST2FPC_CK 50 -#define CLK_INFRA_I2C_MCK_CK 51 -#define CLK_INFRA_I2C_PCK_CK 52 -#define CLK_INFRA_IUSB_133_CK 53 -#define CLK_INFRA_IUSB_66M_CK 54 -#define CLK_INFRA_IUSB_SYS_CK 55 -#define CLK_INFRA_IUSB_CK 56 -#define CLK_INFRA_IPCIE_CK 57 -#define CLK_INFRA_IPCIE_PIPE_CK 58 -#define CLK_INFRA_IPCIER_CK 59 -#define CLK_INFRA_IPCIEB_CK 60 - -/* APMIXEDSYS */ -#define CLK_APMIXED_ARMPLL 0 -#define CLK_APMIXED_NET2PLL 1 -#define CLK_APMIXED_MMPLL 2 -#define CLK_APMIXED_SGMPLL 3 -#define CLK_APMIXED_WEDMCUPLL 4 -#define CLK_APMIXED_NET1PLL 5 -#define CLK_APMIXED_MPLL 6 -#define CLK_APMIXED_APLL2 7 - -/* SGMIISYS_0 */ -#define CLK_SGM0_TX_EN 0 -#define CLK_SGM0_RX_EN 1 -#define CLK_SGM0_CK0_EN 2 -#define CLK_SGM0_CDR_CK0_EN 3 - -/* SGMIISYS_1 */ -#define CLK_SGM1_TX_EN 0 -#define CLK_SGM1_RX_EN 1 -#define CLK_SGM1_CK1_EN 2 -#define CLK_SGM1_CDR_CK1_EN 3 - -/* ETHSYS */ -#define CLK_ETH_FE_EN 0 -#define CLK_ETH_GP2_EN 1 -#define CLK_ETH_GP1_EN 2 -#define CLK_ETH_WOCPU0_EN 3 - -#endif /* _DT_BINDINGS_CLK_MT7981_H */ diff --git a/target/linux/mediatek/files-6.1/include/dt-bindings/clock/mt7986-clk.h b/target/linux/mediatek/files-6.1/include/dt-bindings/clock/mt7986-clk.h deleted file mode 100644 index 5a9b169324b..00000000000 --- a/target/linux/mediatek/files-6.1/include/dt-bindings/clock/mt7986-clk.h +++ /dev/null @@ -1,169 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (c) 2021 MediaTek Inc. - * Author: Sam Shih - */ - -#ifndef _DT_BINDINGS_CLK_MT7986_H -#define _DT_BINDINGS_CLK_MT7986_H - -/* APMIXEDSYS */ - -#define CLK_APMIXED_ARMPLL 0 -#define CLK_APMIXED_NET2PLL 1 -#define CLK_APMIXED_MMPLL 2 -#define CLK_APMIXED_SGMPLL 3 -#define CLK_APMIXED_WEDMCUPLL 4 -#define CLK_APMIXED_NET1PLL 5 -#define CLK_APMIXED_MPLL 6 -#define CLK_APMIXED_APLL2 7 - -/* TOPCKGEN */ - -#define CLK_TOP_XTAL 0 -#define CLK_TOP_XTAL_D2 1 -#define CLK_TOP_RTC_32K 2 -#define CLK_TOP_RTC_32P7K 3 -#define CLK_TOP_MPLL_D2 4 -#define CLK_TOP_MPLL_D4 5 -#define CLK_TOP_MPLL_D8 6 -#define CLK_TOP_MPLL_D8_D2 7 -#define CLK_TOP_MPLL_D3_D2 8 -#define CLK_TOP_MMPLL_D2 9 -#define CLK_TOP_MMPLL_D4 10 -#define CLK_TOP_MMPLL_D8 11 -#define CLK_TOP_MMPLL_D8_D2 12 -#define CLK_TOP_MMPLL_D3_D8 13 -#define CLK_TOP_MMPLL_U2PHY 14 -#define CLK_TOP_APLL2_D4 15 -#define CLK_TOP_NET1PLL_D4 16 -#define CLK_TOP_NET1PLL_D5 17 -#define CLK_TOP_NET1PLL_D5_D2 18 -#define CLK_TOP_NET1PLL_D5_D4 19 -#define CLK_TOP_NET1PLL_D8_D2 20 -#define CLK_TOP_NET1PLL_D8_D4 21 -#define CLK_TOP_NET2PLL_D4 22 -#define CLK_TOP_NET2PLL_D4_D2 23 -#define CLK_TOP_NET2PLL_D3_D2 24 -#define CLK_TOP_WEDMCUPLL_D5_D2 25 -#define CLK_TOP_NFI1X_SEL 26 -#define CLK_TOP_SPINFI_SEL 27 -#define CLK_TOP_SPI_SEL 28 -#define CLK_TOP_SPIM_MST_SEL 29 -#define CLK_TOP_UART_SEL 30 -#define CLK_TOP_PWM_SEL 31 -#define CLK_TOP_I2C_SEL 32 -#define CLK_TOP_PEXTP_TL_SEL 33 -#define CLK_TOP_EMMC_250M_SEL 34 -#define CLK_TOP_EMMC_416M_SEL 35 -#define CLK_TOP_F_26M_ADC_SEL 36 -#define CLK_TOP_DRAMC_SEL 37 -#define CLK_TOP_DRAMC_MD32_SEL 38 -#define CLK_TOP_SYSAXI_SEL 39 -#define CLK_TOP_SYSAPB_SEL 40 -#define CLK_TOP_ARM_DB_MAIN_SEL 41 -#define CLK_TOP_ARM_DB_JTSEL 42 -#define CLK_TOP_NETSYS_SEL 43 -#define CLK_TOP_NETSYS_500M_SEL 44 -#define CLK_TOP_NETSYS_MCU_SEL 45 -#define CLK_TOP_NETSYS_2X_SEL 46 -#define CLK_TOP_SGM_325M_SEL 47 -#define CLK_TOP_SGM_REG_SEL 48 -#define CLK_TOP_A1SYS_SEL 49 -#define CLK_TOP_CONN_MCUSYS_SEL 50 -#define CLK_TOP_EIP_B_SEL 51 -#define CLK_TOP_PCIE_PHY_SEL 52 -#define CLK_TOP_USB3_PHY_SEL 53 -#define CLK_TOP_F26M_SEL 54 -#define CLK_TOP_AUD_L_SEL 55 -#define CLK_TOP_A_TUNER_SEL 56 -#define CLK_TOP_U2U3_SEL 57 -#define CLK_TOP_U2U3_SYS_SEL 58 -#define CLK_TOP_U2U3_XHCI_SEL 59 -#define CLK_TOP_DA_U2_REFSEL 60 -#define CLK_TOP_DA_U2_CK_1P_SEL 61 -#define CLK_TOP_AP2CNN_HOST_SEL 62 -#define CLK_TOP_JTAG 63 - -/* INFRACFG */ - -#define CLK_INFRA_SYSAXI_D2 0 -#define CLK_INFRA_UART0_SEL 1 -#define CLK_INFRA_UART1_SEL 2 -#define CLK_INFRA_UART2_SEL 3 -#define CLK_INFRA_SPI0_SEL 4 -#define CLK_INFRA_SPI1_SEL 5 -#define CLK_INFRA_PWM1_SEL 6 -#define CLK_INFRA_PWM2_SEL 7 -#define CLK_INFRA_PWM_BSEL 8 -#define CLK_INFRA_PCIE_SEL 9 -#define CLK_INFRA_GPT_STA 10 -#define CLK_INFRA_PWM_HCK 11 -#define CLK_INFRA_PWM_STA 12 -#define CLK_INFRA_PWM1_CK 13 -#define CLK_INFRA_PWM2_CK 14 -#define CLK_INFRA_CQ_DMA_CK 15 -#define CLK_INFRA_EIP97_CK 16 -#define CLK_INFRA_AUD_BUS_CK 17 -#define CLK_INFRA_AUD_26M_CK 18 -#define CLK_INFRA_AUD_L_CK 19 -#define CLK_INFRA_AUD_AUD_CK 20 -#define CLK_INFRA_AUD_EG2_CK 21 -#define CLK_INFRA_DRAMC_26M_CK 22 -#define CLK_INFRA_DBG_CK 23 -#define CLK_INFRA_AP_DMA_CK 24 -#define CLK_INFRA_SEJ_CK 25 -#define CLK_INFRA_SEJ_13M_CK 26 -#define CLK_INFRA_THERM_CK 27 -#define CLK_INFRA_I2C0_CK 28 -#define CLK_INFRA_UART0_CK 29 -#define CLK_INFRA_UART1_CK 30 -#define CLK_INFRA_UART2_CK 31 -#define CLK_INFRA_NFI1_CK 32 -#define CLK_INFRA_SPINFI1_CK 33 -#define CLK_INFRA_NFI_HCK_CK 34 -#define CLK_INFRA_SPI0_CK 35 -#define CLK_INFRA_SPI1_CK 36 -#define CLK_INFRA_SPI0_HCK_CK 37 -#define CLK_INFRA_SPI1_HCK_CK 38 -#define CLK_INFRA_FRTC_CK 39 -#define CLK_INFRA_MSDC_CK 40 -#define CLK_INFRA_MSDC_HCK_CK 41 -#define CLK_INFRA_MSDC_133M_CK 42 -#define CLK_INFRA_MSDC_66M_CK 43 -#define CLK_INFRA_ADC_26M_CK 44 -#define CLK_INFRA_ADC_FRC_CK 45 -#define CLK_INFRA_FBIST2FPC_CK 46 -#define CLK_INFRA_IUSB_133_CK 47 -#define CLK_INFRA_IUSB_66M_CK 48 -#define CLK_INFRA_IUSB_SYS_CK 49 -#define CLK_INFRA_IUSB_CK 50 -#define CLK_INFRA_IPCIE_CK 51 -#define CLK_INFRA_IPCIE_PIPE_CK 52 -#define CLK_INFRA_IPCIER_CK 53 -#define CLK_INFRA_IPCIEB_CK 54 -#define CLK_INFRA_TRNG_CK 55 - -/* SGMIISYS_0 */ - -#define CLK_SGMII0_TX250M_EN 0 -#define CLK_SGMII0_RX250M_EN 1 -#define CLK_SGMII0_CDR_REF 2 -#define CLK_SGMII0_CDR_FB 3 - -/* SGMIISYS_1 */ - -#define CLK_SGMII1_TX250M_EN 0 -#define CLK_SGMII1_RX250M_EN 1 -#define CLK_SGMII1_CDR_REF 2 -#define CLK_SGMII1_CDR_FB 3 - -/* ETHSYS */ - -#define CLK_ETH_FE_EN 0 -#define CLK_ETH_GP2_EN 1 -#define CLK_ETH_GP1_EN 2 -#define CLK_ETH_WOCPU1_EN 3 -#define CLK_ETH_WOCPU0_EN 4 - -#endif /* _DT_BINDINGS_CLK_MT7986_H */ diff --git a/target/linux/mediatek/files-6.1/include/dt-bindings/reset/mt7986-resets.h b/target/linux/mediatek/files-6.1/include/dt-bindings/reset/mt7986-resets.h deleted file mode 100644 index af3d16c8119..00000000000 --- a/target/linux/mediatek/files-6.1/include/dt-bindings/reset/mt7986-resets.h +++ /dev/null @@ -1,55 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -/* - * Copyright (c) 2022 MediaTek Inc. - * Author: Sam Shih - */ - -#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7986 -#define _DT_BINDINGS_RESET_CONTROLLER_MT7986 - -/* INFRACFG resets */ -#define MT7986_INFRACFG_PEXTP_MAC_SW_RST 6 -#define MT7986_INFRACFG_SSUSB_SW_RST 7 -#define MT7986_INFRACFG_EIP97_SW_RST 8 -#define MT7986_INFRACFG_AUDIO_SW_RST 13 -#define MT7986_INFRACFG_CQ_DMA_SW_RST 14 - -#define MT7986_INFRACFG_TRNG_SW_RST 17 -#define MT7986_INFRACFG_AP_DMA_SW_RST 32 -#define MT7986_INFRACFG_I2C_SW_RST 33 -#define MT7986_INFRACFG_NFI_SW_RST 34 -#define MT7986_INFRACFG_SPI0_SW_RST 35 -#define MT7986_INFRACFG_SPI1_SW_RST 36 -#define MT7986_INFRACFG_UART0_SW_RST 37 -#define MT7986_INFRACFG_UART1_SW_RST 38 -#define MT7986_INFRACFG_UART2_SW_RST 39 -#define MT7986_INFRACFG_AUXADC_SW_RST 43 - -#define MT7986_INFRACFG_APXGPT_SW_RST 66 -#define MT7986_INFRACFG_PWM_SW_RST 68 - -#define MT7986_INFRACFG_SW_RST_NUM 69 - -/* TOPRGU resets */ -#define MT7986_TOPRGU_APMIXEDSYS_SW_RST 0 -#define MT7986_TOPRGU_SGMII0_SW_RST 1 -#define MT7986_TOPRGU_SGMII1_SW_RST 2 -#define MT7986_TOPRGU_INFRA_SW_RST 3 -#define MT7986_TOPRGU_U2PHY_SW_RST 5 -#define MT7986_TOPRGU_PCIE_SW_RST 6 -#define MT7986_TOPRGU_SSUSB_SW_RST 7 -#define MT7986_TOPRGU_ETHDMA_SW_RST 20 -#define MT7986_TOPRGU_CONSYS_SW_RST 23 - -#define MT7986_TOPRGU_SW_RST_NUM 24 - -/* ETHSYS Subsystem resets */ -#define MT7986_ETHSYS_FE_SW_RST 6 -#define MT7986_ETHSYS_PMTR_SW_RST 8 -#define MT7986_ETHSYS_GMAC_SW_RST 23 -#define MT7986_ETHSYS_PPE0_SW_RST 30 -#define MT7986_ETHSYS_PPE1_SW_RST 31 - -#define MT7986_ETHSYS_SW_RST_NUM 32 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7986 */ diff --git a/target/linux/mediatek/patches-6.1/000-v6.2-kbuild-Allow-DTB-overlays-to-built-from-.dtso-named-.patch b/target/linux/mediatek/patches-6.1/000-v6.2-kbuild-Allow-DTB-overlays-to-built-from-.dtso-named-.patch new file mode 100644 index 00000000000..17c5c6098aa --- /dev/null +++ b/target/linux/mediatek/patches-6.1/000-v6.2-kbuild-Allow-DTB-overlays-to-built-from-.dtso-named-.patch @@ -0,0 +1,44 @@ +From 363547d2191cbc32ca954ba75d72908712398ff2 Mon Sep 17 00:00:00 2001 +From: Andrew Davis +Date: Mon, 24 Oct 2022 12:34:28 -0500 +Subject: [PATCH] kbuild: Allow DTB overlays to built from .dtso named source + files + +Currently DTB Overlays (.dtbo) are build from source files with the same +extension (.dts) as the base DTs (.dtb). This may become confusing and +even lead to wrong results. For example, a composite DTB (created from a +base DTB and a set of overlays) might have the same name as one of the +overlays that create it. + +Different files should be generated from differently named sources. + .dtb <-> .dts + .dtbo <-> .dtso + +We do not remove the ability to compile DTBO files from .dts files here, +only add a new rule allowing the .dtso file name. The current .dts named +overlays can be renamed with time. After all have been renamed we can +remove the other rule. + +Signed-off-by: Andrew Davis +Reviewed-by: Geert Uytterhoeven +Tested-by: Geert Uytterhoeven +Reviewed-by: Frank Rowand +Tested-by: Frank Rowand +Link: https://lore.kernel.org/r/20221024173434.32518-2-afd@ti.com +Signed-off-by: Rob Herring +--- + scripts/Makefile.lib | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/scripts/Makefile.lib ++++ b/scripts/Makefile.lib +@@ -408,6 +408,9 @@ $(obj)/%.dtb: $(src)/%.dts $(DTC) $(DT_T + $(obj)/%.dtbo: $(src)/%.dts $(DTC) FORCE + $(call if_changed_dep,dtc) + ++$(obj)/%.dtbo: $(src)/%.dtso $(DTC) FORCE ++ $(call if_changed_dep,dtc) ++ + dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp) + + # Bzip2 diff --git a/target/linux/mediatek/patches-6.1/001-v6.2-arm64-dts-mediatek-mt7986-add-support-for-RX-Wireles.patch b/target/linux/mediatek/patches-6.1/001-v6.2-arm64-dts-mediatek-mt7986-add-support-for-RX-Wireles.patch new file mode 100644 index 00000000000..970e0f92bb4 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/001-v6.2-arm64-dts-mediatek-mt7986-add-support-for-RX-Wireles.patch @@ -0,0 +1,106 @@ +From 2c4daed9580164522859fa100128be408cc69be2 Mon Sep 17 00:00:00 2001 +From: Lorenzo Bianconi +Date: Sat, 5 Nov 2022 23:36:16 +0100 +Subject: [PATCH 01/19] arm64: dts: mediatek: mt7986: add support for RX + Wireless Ethernet Dispatch + +Similar to TX Wireless Ethernet Dispatch, introduce RX Wireless Ethernet +Dispatch to offload traffic received by the wlan interface to lan/wan +one. + +Co-developed-by: Sujuan Chen +Signed-off-by: Sujuan Chen +Signed-off-by: Lorenzo Bianconi +Signed-off-by: David S. Miller +--- + arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 65 +++++++++++++++++++++++ + 1 file changed, 65 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +@@ -76,6 +76,47 @@ + no-map; + reg = <0 0x4fc00000 0 0x00100000>; + }; ++ ++ wo_emi0: wo-emi@4fd00000 { ++ reg = <0 0x4fd00000 0 0x40000>; ++ no-map; ++ }; ++ ++ wo_emi1: wo-emi@4fd40000 { ++ reg = <0 0x4fd40000 0 0x40000>; ++ no-map; ++ }; ++ ++ wo_ilm0: wo-ilm@151e0000 { ++ reg = <0 0x151e0000 0 0x8000>; ++ no-map; ++ }; ++ ++ wo_ilm1: wo-ilm@151f0000 { ++ reg = <0 0x151f0000 0 0x8000>; ++ no-map; ++ }; ++ ++ wo_data: wo-data@4fd80000 { ++ reg = <0 0x4fd80000 0 0x240000>; ++ no-map; ++ }; ++ ++ wo_dlm0: wo-dlm@151e8000 { ++ reg = <0 0x151e8000 0 0x2000>; ++ no-map; ++ }; ++ ++ wo_dlm1: wo-dlm@151f8000 { ++ reg = <0 0x151f8000 0 0x2000>; ++ no-map; ++ }; ++ ++ wo_boot: wo-boot@15194000 { ++ reg = <0 0x15194000 0 0x1000>; ++ no-map; ++ }; ++ + }; + + timer { +@@ -239,6 +280,11 @@ + reg = <0 0x15010000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; ++ memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, ++ <&wo_data>, <&wo_boot>; ++ memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", ++ "wo-data", "wo-boot"; ++ mediatek,wo-ccif = <&wo_ccif0>; + }; + + wed1: wed@15011000 { +@@ -247,6 +293,25 @@ + reg = <0 0x15011000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; ++ memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>, ++ <&wo_data>, <&wo_boot>; ++ memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", ++ "wo-data", "wo-boot"; ++ mediatek,wo-ccif = <&wo_ccif1>; ++ }; ++ ++ wo_ccif0: syscon@151a5000 { ++ compatible = "mediatek,mt7986-wo-ccif", "syscon"; ++ reg = <0 0x151a5000 0 0x1000>; ++ interrupt-parent = <&gic>; ++ interrupts = ; ++ }; ++ ++ wo_ccif1: syscon@151ad000 { ++ compatible = "mediatek,mt7986-wo-ccif", "syscon"; ++ reg = <0 0x151ad000 0 0x1000>; ++ interrupt-parent = <&gic>; ++ interrupts = ; + }; + + eth: ethernet@15100000 { diff --git a/target/linux/mediatek/patches-6.1/002-v6.2-arm64-dts-mt7986-harmonize-device-node-order.patch b/target/linux/mediatek/patches-6.1/002-v6.2-arm64-dts-mt7986-harmonize-device-node-order.patch new file mode 100644 index 00000000000..b5091687a33 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/002-v6.2-arm64-dts-mt7986-harmonize-device-node-order.patch @@ -0,0 +1,166 @@ +From 438e53828c08cf0e8a65b61cf6ce1e4b6620551a Mon Sep 17 00:00:00 2001 +From: Sam Shih +Date: Sun, 6 Nov 2022 09:50:24 +0100 +Subject: [PATCH 02/19] arm64: dts: mt7986: harmonize device node order + +This arrange device tree nodes in alphabetical order. + +Signed-off-by: Sam Shih +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20221106085034.12582-2-linux@fw-web.de +Signed-off-by: Matthias Brugger +--- + arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 94 ++++++++++---------- + arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 22 ++--- + 2 files changed, 58 insertions(+), 58 deletions(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +@@ -54,6 +54,53 @@ + }; + }; + ++&pio { ++ uart1_pins: uart1-pins { ++ mux { ++ function = "uart"; ++ groups = "uart1"; ++ }; ++ }; ++ ++ uart2_pins: uart2-pins { ++ mux { ++ function = "uart"; ++ groups = "uart2"; ++ }; ++ }; ++ ++ wf_2g_5g_pins: wf-2g-5g-pins { ++ mux { ++ function = "wifi"; ++ groups = "wf_2g", "wf_5g"; ++ }; ++ conf { ++ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", ++ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", ++ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", ++ "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", ++ "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", ++ "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", ++ "WF1_TOP_CLK", "WF1_TOP_DATA"; ++ drive-strength = <4>; ++ }; ++ }; ++ ++ wf_dbdc_pins: wf-dbdc-pins { ++ mux { ++ function = "wifi"; ++ groups = "wf_dbdc"; ++ }; ++ conf { ++ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", ++ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", ++ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", ++ "WF0_TOP_CLK", "WF0_TOP_DATA"; ++ drive-strength = <4>; ++ }; ++ }; ++}; ++ + &switch { + ports { + #address-cells = <1>; +@@ -121,50 +168,3 @@ + pinctrl-0 = <&wf_2g_5g_pins>; + pinctrl-1 = <&wf_dbdc_pins>; + }; +- +-&pio { +- uart1_pins: uart1-pins { +- mux { +- function = "uart"; +- groups = "uart1"; +- }; +- }; +- +- uart2_pins: uart2-pins { +- mux { +- function = "uart"; +- groups = "uart2"; +- }; +- }; +- +- wf_2g_5g_pins: wf-2g-5g-pins { +- mux { +- function = "wifi"; +- groups = "wf_2g", "wf_5g"; +- }; +- conf { +- pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", +- "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", +- "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", +- "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", +- "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", +- "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", +- "WF1_TOP_CLK", "WF1_TOP_DATA"; +- drive-strength = <4>; +- }; +- }; +- +- wf_dbdc_pins: wf-dbdc-pins { +- mux { +- function = "wifi"; +- groups = "wf_dbdc"; +- }; +- conf { +- pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", +- "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", +- "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", +- "WF0_TOP_CLK", "WF0_TOP_DATA"; +- drive-strength = <4>; +- }; +- }; +-}; +--- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts +@@ -25,10 +25,6 @@ + }; + }; + +-&uart0 { +- status = "okay"; +-}; +- + ð { + status = "okay"; + +@@ -99,13 +95,6 @@ + }; + }; + +-&wifi { +- status = "okay"; +- pinctrl-names = "default", "dbdc"; +- pinctrl-0 = <&wf_2g_5g_pins>; +- pinctrl-1 = <&wf_dbdc_pins>; +-}; +- + &pio { + wf_2g_5g_pins: wf-2g-5g-pins { + mux { +@@ -138,3 +127,14 @@ + }; + }; + }; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&wifi { ++ status = "okay"; ++ pinctrl-names = "default", "dbdc"; ++ pinctrl-0 = <&wf_2g_5g_pins>; ++ pinctrl-1 = <&wf_dbdc_pins>; ++}; diff --git a/target/linux/mediatek/patches-6.1/003-v6.2-arm64-dts-mt7986-add-crypto-related-device-nodes.patch b/target/linux/mediatek/patches-6.1/003-v6.2-arm64-dts-mt7986-add-crypto-related-device-nodes.patch new file mode 100644 index 00000000000..5706531a468 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/003-v6.2-arm64-dts-mt7986-add-crypto-related-device-nodes.patch @@ -0,0 +1,68 @@ +From ffb05357b47f06b2b4d1e14ba89169e28feb727b Mon Sep 17 00:00:00 2001 +From: Sam Shih +Date: Sun, 6 Nov 2022 09:50:27 +0100 +Subject: [PATCH 03/19] arm64: dts: mt7986: add crypto related device nodes + +This patch adds crypto engine support for MT7986. + +Signed-off-by: Vic Wu +Signed-off-by: Sam Shih +Signed-off-by: Frank Wunderlich +Link: https://lore.kernel.org/r/20221106085034.12582-5-linux@fw-web.de +Signed-off-by: Matthias Brugger +--- + arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 4 ++++ + arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 15 +++++++++++++++ + arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 4 ++++ + 3 files changed, 23 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +@@ -25,6 +25,10 @@ + }; + }; + ++&crypto { ++ status = "okay"; ++}; ++ + ð { + status = "okay"; + +--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +@@ -223,6 +223,21 @@ + status = "disabled"; + }; + ++ crypto: crypto@10320000 { ++ compatible = "inside-secure,safexcel-eip97"; ++ reg = <0 0x10320000 0 0x40000>; ++ interrupts = , ++ , ++ , ++ ; ++ interrupt-names = "ring0", "ring1", "ring2", "ring3"; ++ clocks = <&infracfg CLK_INFRA_EIP97_CK>; ++ clock-names = "infra_eip97_ck"; ++ assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>; ++ assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>; ++ status = "disabled"; ++ }; ++ + uart0: serial@11002000 { + compatible = "mediatek,mt7986-uart", + "mediatek,mt6577-uart"; +--- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts +@@ -25,6 +25,10 @@ + }; + }; + ++&crypto { ++ status = "okay"; ++}; ++ + ð { + status = "okay"; + diff --git a/target/linux/mediatek/patches-6.1/004-v6.2-arm64-dts-mt7986-add-i2c-node.patch b/target/linux/mediatek/patches-6.1/004-v6.2-arm64-dts-mt7986-add-i2c-node.patch new file mode 100644 index 00000000000..0e5b77a11b3 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/004-v6.2-arm64-dts-mt7986-add-i2c-node.patch @@ -0,0 +1,37 @@ +From b49b7dc404ded1d89cbc568d875009a5c1ed4ef6 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Sun, 6 Nov 2022 09:50:29 +0100 +Subject: [PATCH 04/19] arm64: dts: mt7986: add i2c node + +Add i2c Node to mt7986 devicetree. + +Signed-off-by: Frank Wunderlich +Link: https://lore.kernel.org/r/20221106085034.12582-7-linux@fw-web.de +Signed-off-by: Matthias Brugger +--- + arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +@@ -279,6 +279,20 @@ + status = "disabled"; + }; + ++ i2c0: i2c@11008000 { ++ compatible = "mediatek,mt7986-i2c"; ++ reg = <0 0x11008000 0 0x90>, ++ <0 0x10217080 0 0x80>; ++ interrupts = ; ++ clock-div = <5>; ++ clocks = <&infracfg CLK_INFRA_I2C0_CK>, ++ <&infracfg CLK_INFRA_AP_DMA_CK>; ++ clock-names = "main", "dma"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + ethsys: syscon@15000000 { + #address-cells = <1>; + #size-cells = <1>; diff --git a/target/linux/mediatek/patches-6.1/005-v6.2-arm64-dts-mediatek-mt7986-Add-SoC-compatible.patch b/target/linux/mediatek/patches-6.1/005-v6.2-arm64-dts-mediatek-mt7986-Add-SoC-compatible.patch new file mode 100644 index 00000000000..8201b47df61 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/005-v6.2-arm64-dts-mediatek-mt7986-Add-SoC-compatible.patch @@ -0,0 +1,61 @@ +From 2cd6022800d6da7822e169f3e6f7f790c1431445 Mon Sep 17 00:00:00 2001 +From: Matthias Brugger +Date: Mon, 14 Nov 2022 13:16:53 +0100 +Subject: [PATCH 05/19] arm64: dts: mediatek: mt7986: Add SoC compatible + +Missing SoC compatible in the board file causes dt bindings check. + +Signed-off-by: Matthias Brugger +Link: https://lore.kernel.org/r/20221114121653.14739-1-matthias.bgg@kernel.org +Signed-off-by: Matthias Brugger +--- + arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 2 +- + arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 1 + + arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 2 +- + arch/arm64/boot/dts/mediatek/mt7986b.dtsi | 3 +++ + 4 files changed, 6 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +@@ -9,7 +9,7 @@ + + / { + model = "MediaTek MT7986a RFB"; +- compatible = "mediatek,mt7986a-rfb"; ++ compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a"; + + aliases { + serial0 = &uart0; +--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +@@ -10,6 +10,7 @@ + #include + + / { ++ compatible = "mediatek,mt7986a"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; +--- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts +@@ -9,7 +9,7 @@ + + / { + model = "MediaTek MT7986b RFB"; +- compatible = "mediatek,mt7986b-rfb"; ++ compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b"; + + aliases { + serial0 = &uart0; +--- a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi +@@ -5,6 +5,9 @@ + */ + + #include "mt7986a.dtsi" ++/ { ++ compatible = "mediatek,mt7986b"; ++}; + + &pio { + compatible = "mediatek,mt7986b-pinctrl"; diff --git a/target/linux/mediatek/patches-6.1/006-v6.2-arm64-dts-mt7986-add-spi-related-device-nodes.patch b/target/linux/mediatek/patches-6.1/006-v6.2-arm64-dts-mt7986-add-spi-related-device-nodes.patch new file mode 100644 index 00000000000..b319b166a70 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/006-v6.2-arm64-dts-mt7986-add-spi-related-device-nodes.patch @@ -0,0 +1,157 @@ +From f4029538f063a845dc9aae46cce4cf386e6253a5 Mon Sep 17 00:00:00 2001 +From: Sam Shih +Date: Fri, 18 Nov 2022 20:01:21 +0100 +Subject: [PATCH 06/19] arm64: dts: mt7986: add spi related device nodes + +This patch adds spi support for MT7986. + +Signed-off-by: Sam Shih +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20221118190126.100895-7-linux@fw-web.de +Signed-off-by: Matthias Brugger +--- + arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 35 ++++++++++++++++++++ + arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 28 ++++++++++++++++ + arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 35 ++++++++++++++++++++ + 3 files changed, 98 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +@@ -59,6 +59,20 @@ + }; + + &pio { ++ spi_flash_pins: spi-flash-pins { ++ mux { ++ function = "spi"; ++ groups = "spi0", "spi0_wp_hold"; ++ }; ++ }; ++ ++ spic_pins: spic-pins { ++ mux { ++ function = "spi"; ++ groups = "spi1_2"; ++ }; ++ }; ++ + uart1_pins: uart1-pins { + mux { + function = "uart"; +@@ -105,6 +119,27 @@ + }; + }; + ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi_flash_pins>; ++ cs-gpios = <0>, <0>; ++ status = "okay"; ++ spi_nand: spi_nand@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <10000000>; ++ spi-tx-buswidth = <4>; ++ spi-rx-buswidth = <4>; ++ }; ++}; ++ ++&spi1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spic_pins>; ++ cs-gpios = <0>, <0>; ++ status = "okay"; ++}; ++ + &switch { + ports { + #address-cells = <1>; +--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +@@ -294,6 +294,34 @@ + status = "disabled"; + }; + ++ spi0: spi@1100a000 { ++ compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0 0x1100a000 0 0x100>; ++ interrupts = ; ++ clocks = <&topckgen CLK_TOP_MPLL_D2>, ++ <&topckgen CLK_TOP_SPI_SEL>, ++ <&infracfg CLK_INFRA_SPI0_CK>, ++ <&infracfg CLK_INFRA_SPI0_HCK_CK>; ++ clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; ++ status = "disabled"; ++ }; ++ ++ spi1: spi@1100b000 { ++ compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0 0x1100b000 0 0x100>; ++ interrupts = ; ++ clocks = <&topckgen CLK_TOP_MPLL_D2>, ++ <&topckgen CLK_TOP_SPIM_MST_SEL>, ++ <&infracfg CLK_INFRA_SPI1_CK>, ++ <&infracfg CLK_INFRA_SPI1_HCK_CK>; ++ clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; ++ status = "disabled"; ++ }; ++ + ethsys: syscon@15000000 { + #address-cells = <1>; + #size-cells = <1>; +--- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts +@@ -100,6 +100,20 @@ + }; + + &pio { ++ spi_flash_pins: spi-flash-pins { ++ mux { ++ function = "spi"; ++ groups = "spi0", "spi0_wp_hold"; ++ }; ++ }; ++ ++ spic_pins: spic-pins { ++ mux { ++ function = "spi"; ++ groups = "spi1_2"; ++ }; ++ }; ++ + wf_2g_5g_pins: wf-2g-5g-pins { + mux { + function = "wifi"; +@@ -132,6 +146,27 @@ + }; + }; + ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi_flash_pins>; ++ cs-gpios = <0>, <0>; ++ status = "okay"; ++ spi_nand: spi_nand@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <10000000>; ++ spi-tx-buswidth = <4>; ++ spi-rx-buswidth = <4>; ++ }; ++}; ++ ++&spi1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spic_pins>; ++ cs-gpios = <0>, <0>; ++ status = "okay"; ++}; ++ + &uart0 { + status = "okay"; + }; diff --git a/target/linux/mediatek/patches-6.1/007-v6.3-arm64-dts-mt7986-add-usb-related-device-nodes.patch b/target/linux/mediatek/patches-6.1/007-v6.3-arm64-dts-mt7986-add-usb-related-device-nodes.patch new file mode 100644 index 00000000000..53567c66a0b --- /dev/null +++ b/target/linux/mediatek/patches-6.1/007-v6.3-arm64-dts-mt7986-add-usb-related-device-nodes.patch @@ -0,0 +1,127 @@ +From 9e8e24ab716098e617195ce29b88e84608bf2108 Mon Sep 17 00:00:00 2001 +From: Sam Shih +Date: Fri, 6 Jan 2023 16:28:42 +0100 +Subject: [PATCH 07/19] arm64: dts: mt7986: add usb related device nodes + +This patch adds USB support for MT7986. + +Signed-off-by: Sam Shih +Signed-off-by: Frank Wunderlich +Reviewed-by: Chunfeng Yun +Link: https://lore.kernel.org/r/20230106152845.88717-3-linux@fw-web.de +Signed-off-by: Matthias Brugger +--- + arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 8 +++ + arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 55 ++++++++++++++++++++ + arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 8 +++ + 3 files changed, 71 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +@@ -140,6 +140,10 @@ + status = "okay"; + }; + ++&ssusb { ++ status = "okay"; ++}; ++ + &switch { + ports { + #address-cells = <1>; +@@ -201,6 +205,10 @@ + status = "okay"; + }; + ++&usb_phy { ++ status = "okay"; ++}; ++ + &wifi { + status = "okay"; + pinctrl-names = "default", "dbdc"; +--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +@@ -322,6 +322,61 @@ + status = "disabled"; + }; + ++ ssusb: usb@11200000 { ++ compatible = "mediatek,mt7986-xhci", ++ "mediatek,mtk-xhci"; ++ reg = <0 0x11200000 0 0x2e00>, ++ <0 0x11203e00 0 0x0100>; ++ reg-names = "mac", "ippc"; ++ interrupts = ; ++ clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>, ++ <&infracfg CLK_INFRA_IUSB_CK>, ++ <&infracfg CLK_INFRA_IUSB_133_CK>, ++ <&infracfg CLK_INFRA_IUSB_66M_CK>, ++ <&topckgen CLK_TOP_U2U3_XHCI_SEL>; ++ clock-names = "sys_ck", ++ "ref_ck", ++ "mcu_ck", ++ "dma_ck", ++ "xhci_ck"; ++ phys = <&u2port0 PHY_TYPE_USB2>, ++ <&u3port0 PHY_TYPE_USB3>, ++ <&u2port1 PHY_TYPE_USB2>; ++ status = "disabled"; ++ }; ++ ++ usb_phy: t-phy@11e10000 { ++ compatible = "mediatek,mt7986-tphy", ++ "mediatek,generic-tphy-v2"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0 0x11e10000 0x1700>; ++ status = "disabled"; ++ ++ u2port0: usb-phy@0 { ++ reg = <0x0 0x700>; ++ clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>, ++ <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>; ++ clock-names = "ref", "da_ref"; ++ #phy-cells = <1>; ++ }; ++ ++ u3port0: usb-phy@700 { ++ reg = <0x700 0x900>; ++ clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>; ++ clock-names = "ref"; ++ #phy-cells = <1>; ++ }; ++ ++ u2port1: usb-phy@1000 { ++ reg = <0x1000 0x700>; ++ clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>, ++ <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>; ++ clock-names = "ref", "da_ref"; ++ #phy-cells = <1>; ++ }; ++ }; ++ + ethsys: syscon@15000000 { + #address-cells = <1>; + #size-cells = <1>; +--- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts +@@ -167,10 +167,18 @@ + status = "okay"; + }; + ++&ssusb { ++ status = "okay"; ++}; ++ + &uart0 { + status = "okay"; + }; + ++&usb_phy { ++ status = "okay"; ++}; ++ + &wifi { + status = "okay"; + pinctrl-names = "default", "dbdc"; diff --git a/target/linux/mediatek/patches-6.1/008-v6.3-arm64-dts-mt7986-add-mmc-related-device-nodes.patch b/target/linux/mediatek/patches-6.1/008-v6.3-arm64-dts-mt7986-add-mmc-related-device-nodes.patch new file mode 100644 index 00000000000..9c0a48149d4 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/008-v6.3-arm64-dts-mt7986-add-mmc-related-device-nodes.patch @@ -0,0 +1,160 @@ +From c1744e9e75a6a8abc7c893f349bcbf725b9c0d74 Mon Sep 17 00:00:00 2001 +From: Sam Shih +Date: Fri, 6 Jan 2023 16:28:43 +0100 +Subject: [PATCH 08/19] arm64: dts: mt7986: add mmc related device nodes + +This patch adds mmc support for MT7986. + +Signed-off-by: Sam Shih +Signed-off-by: Frank Wunderlich +Link: https://lore.kernel.org/r/20230106152845.88717-4-linux@fw-web.de +Signed-off-by: Matthias Brugger +--- + arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 96 ++++++++++++++++++++ + arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 15 +++ + 2 files changed, 111 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +@@ -5,6 +5,8 @@ + */ + + /dts-v1/; ++#include ++ + #include "mt7986a.dtsi" + + / { +@@ -23,6 +25,24 @@ + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; ++ ++ reg_1p8v: regulator-1p8v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-1.8V"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ reg_3p3v: regulator-3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-3.3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; + }; + + &crypto { +@@ -58,7 +78,83 @@ + }; + }; + ++&mmc0 { ++ pinctrl-names = "default", "state_uhs"; ++ pinctrl-0 = <&mmc0_pins_default>; ++ pinctrl-1 = <&mmc0_pins_uhs>; ++ bus-width = <8>; ++ max-frequency = <200000000>; ++ cap-mmc-highspeed; ++ mmc-hs200-1_8v; ++ mmc-hs400-1_8v; ++ hs400-ds-delay = <0x14014>; ++ vmmc-supply = <®_3p3v>; ++ vqmmc-supply = <®_1p8v>; ++ non-removable; ++ no-sd; ++ no-sdio; ++ status = "okay"; ++}; ++ + &pio { ++ mmc0_pins_default: mmc0-pins { ++ mux { ++ function = "emmc"; ++ groups = "emmc_51"; ++ }; ++ conf-cmd-dat { ++ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", ++ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", ++ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; ++ input-enable; ++ drive-strength = <4>; ++ bias-pull-up = ; /* pull-up 10K */ ++ }; ++ conf-clk { ++ pins = "EMMC_CK"; ++ drive-strength = <6>; ++ bias-pull-down = ; /* pull-down 50K */ ++ }; ++ conf-ds { ++ pins = "EMMC_DSL"; ++ bias-pull-down = ; /* pull-down 50K */ ++ }; ++ conf-rst { ++ pins = "EMMC_RSTB"; ++ drive-strength = <4>; ++ bias-pull-up = ; /* pull-up 10K */ ++ }; ++ }; ++ ++ mmc0_pins_uhs: mmc0-uhs-pins { ++ mux { ++ function = "emmc"; ++ groups = "emmc_51"; ++ }; ++ conf-cmd-dat { ++ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", ++ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", ++ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; ++ input-enable; ++ drive-strength = <4>; ++ bias-pull-up = ; /* pull-up 10K */ ++ }; ++ conf-clk { ++ pins = "EMMC_CK"; ++ drive-strength = <6>; ++ bias-pull-down = ; /* pull-down 50K */ ++ }; ++ conf-ds { ++ pins = "EMMC_DSL"; ++ bias-pull-down = ; /* pull-down 50K */ ++ }; ++ conf-rst { ++ pins = "EMMC_RSTB"; ++ drive-strength = <4>; ++ bias-pull-up = ; /* pull-up 10K */ ++ }; ++ }; ++ + spi_flash_pins: spi-flash-pins { + mux { + function = "spi"; +--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +@@ -345,6 +345,21 @@ + status = "disabled"; + }; + ++ mmc0: mmc@11230000 { ++ compatible = "mediatek,mt7986-mmc"; ++ reg = <0 0x11230000 0 0x1000>, ++ <0 0x11c20000 0 0x1000>; ++ interrupts = ; ++ clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>, ++ <&infracfg CLK_INFRA_MSDC_HCK_CK>, ++ <&infracfg CLK_INFRA_MSDC_CK>, ++ <&infracfg CLK_INFRA_MSDC_133M_CK>, ++ <&infracfg CLK_INFRA_MSDC_66M_CK>; ++ clock-names = "source", "hclk", "source_cg", "bus_clk", ++ "sys_cg"; ++ status = "disabled"; ++ }; ++ + usb_phy: t-phy@11e10000 { + compatible = "mediatek,mt7986-tphy", + "mediatek,generic-tphy-v2"; diff --git a/target/linux/mediatek/patches-6.1/009-v6.3-arm64-dts-mt7986-add-pcie-related-device-nodes.patch b/target/linux/mediatek/patches-6.1/009-v6.3-arm64-dts-mt7986-add-pcie-related-device-nodes.patch new file mode 100644 index 00000000000..adc63948576 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/009-v6.3-arm64-dts-mt7986-add-pcie-related-device-nodes.patch @@ -0,0 +1,118 @@ +From 87a42ef1d6cf602e4aa40555b4404cad6149a90f Mon Sep 17 00:00:00 2001 +From: Sam Shih +Date: Fri, 6 Jan 2023 16:28:44 +0100 +Subject: [PATCH 09/19] arm64: dts: mt7986: add pcie related device nodes + +This patch adds PCIe support for MT7986. + +Signed-off-by: Jieyy Yang +Signed-off-by: Sam Shih +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20230106152845.88717-5-linux@fw-web.de +Signed-off-by: Matthias Brugger +--- + arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 16 ++++++ + arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 52 ++++++++++++++++++++ + 2 files changed, 68 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +@@ -93,6 +93,15 @@ + non-removable; + no-sd; + no-sdio; ++}; ++ ++&pcie { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_pins>; ++ status = "okay"; ++}; ++ ++&pcie_phy { + status = "okay"; + }; + +@@ -155,6 +164,13 @@ + }; + }; + ++ pcie_pins: pcie-pins { ++ mux { ++ function = "pcie"; ++ groups = "pcie_clk", "pcie_wake", "pcie_pereset"; ++ }; ++ }; ++ + spi_flash_pins: spi-flash-pins { + mux { + function = "spi"; +--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +@@ -8,6 +8,7 @@ + #include + #include + #include ++#include + + / { + compatible = "mediatek,mt7986a"; +@@ -360,6 +361,57 @@ + status = "disabled"; + }; + ++ pcie: pcie@11280000 { ++ compatible = "mediatek,mt7986-pcie", ++ "mediatek,mt8192-pcie"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ reg = <0x00 0x11280000 0x00 0x4000>; ++ reg-names = "pcie-mac"; ++ interrupts = ; ++ bus-range = <0x00 0xff>; ++ ranges = <0x82000000 0x00 0x20000000 0x00 ++ 0x20000000 0x00 0x10000000>; ++ clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, ++ <&infracfg CLK_INFRA_IPCIE_CK>, ++ <&infracfg CLK_INFRA_IPCIER_CK>, ++ <&infracfg CLK_INFRA_IPCIEB_CK>; ++ clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; ++ status = "disabled"; ++ ++ phys = <&pcie_port PHY_TYPE_PCIE>; ++ phy-names = "pcie-phy"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &pcie_intc 0>, ++ <0 0 0 2 &pcie_intc 1>, ++ <0 0 0 3 &pcie_intc 2>, ++ <0 0 0 4 &pcie_intc 3>; ++ pcie_intc: interrupt-controller { ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ ++ pcie_phy: t-phy@11c00000 { ++ compatible = "mediatek,mt7986-tphy", ++ "mediatek,generic-tphy-v2"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ status = "disabled"; ++ ++ pcie_port: pcie-phy@11c00000 { ++ reg = <0 0x11c00000 0 0x20000>; ++ clocks = <&clk40m>; ++ clock-names = "ref"; ++ #phy-cells = <1>; ++ }; ++ }; ++ + usb_phy: t-phy@11e10000 { + compatible = "mediatek,mt7986-tphy", + "mediatek,generic-tphy-v2"; diff --git a/target/linux/mediatek/patches-6.1/010-v6.3-arm64-dts-mt7986-add-Bananapi-R3.patch b/target/linux/mediatek/patches-6.1/010-v6.3-arm64-dts-mt7986-add-Bananapi-R3.patch new file mode 100644 index 00000000000..abe0b6e9bc1 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/010-v6.3-arm64-dts-mt7986-add-Bananapi-R3.patch @@ -0,0 +1,689 @@ +From a751f7412e0098801673b80bc7a4738ae7d710ce Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Fri, 6 Jan 2023 16:28:45 +0100 +Subject: [PATCH 10/19] arm64: dts: mt7986: add Bananapi R3 + +Add support for Bananapi R3 SBC. + +- SD/eMMC support (switching first 4 bits of data-bus with sw6/D) +- SPI-NAND/NOR support (switched CS by sw5/C) +- all rj45 ports and both SFP working (eth1/lan4) +- all USB-Ports + SIM-Slot tested +- i2c and all uarts tested +- wifi tested (with eeprom calibration data) + +The device can boot from all 4 storage options. Both, SPI and MMC, can +be switched using hardware switches on the board, see +https://wiki.banana-pi.org/Banana_Pi_BPI-R3#Jumper_setting + +Signed-off-by: Frank Wunderlich +Link: https://lore.kernel.org/r/20230106152845.88717-6-linux@fw-web.de +Signed-off-by: Matthias Brugger +--- + arch/arm64/boot/dts/mediatek/Makefile | 5 + + .../mt7986a-bananapi-bpi-r3-emmc.dtso | 29 ++ + .../mt7986a-bananapi-bpi-r3-nand.dtso | 55 +++ + .../mediatek/mt7986a-bananapi-bpi-r3-nor.dtso | 68 +++ + .../mediatek/mt7986a-bananapi-bpi-r3-sd.dtso | 23 + + .../dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 450 ++++++++++++++++++ + 6 files changed, 630 insertions(+) + create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso + create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso + create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso + create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso + create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts + +--- a/arch/arm64/boot/dts/mediatek/Makefile ++++ b/arch/arm64/boot/dts/mediatek/Makefile +@@ -7,6 +7,11 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-ev + dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb + dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb + dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3.dtb ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc.dtbo ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo + dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb + dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb + dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso +@@ -0,0 +1,29 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2021 MediaTek Inc. ++ * Author: Sam.Shih ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; ++ ++ fragment@0 { ++ target-path = "/soc/mmc@11230000"; ++ __overlay__ { ++ bus-width = <8>; ++ max-frequency = <200000000>; ++ cap-mmc-highspeed; ++ mmc-hs200-1_8v; ++ mmc-hs400-1_8v; ++ hs400-ds-delay = <0x14014>; ++ non-removable; ++ no-sd; ++ no-sdio; ++ status = "okay"; ++ }; ++ }; ++}; ++ +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso +@@ -0,0 +1,55 @@ ++/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ ++/* ++ * Authors: Daniel Golle ++ * Frank Wunderlich ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; ++ ++ fragment@0 { ++ target-path = "/soc/spi@1100a000"; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi_nand: spi_nand@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <10000000>; ++ spi-tx-buswidth = <4>; ++ spi-rx-buswidth = <4>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "bl2"; ++ reg = <0x0 0x80000>; ++ read-only; ++ }; ++ ++ partition@80000 { ++ label = "reserved"; ++ reg = <0x80000 0x300000>; ++ }; ++ ++ partition@380000 { ++ label = "fip"; ++ reg = <0x380000 0x200000>; ++ read-only; ++ }; ++ ++ partition@580000 { ++ label = "ubi"; ++ reg = <0x580000 0x7a80000>; ++ }; ++ }; ++ }; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso +@@ -0,0 +1,68 @@ ++/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ ++/* ++ * Authors: Daniel Golle ++ * Frank Wunderlich ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; ++ ++ fragment@0 { ++ target-path = "/soc/spi@1100a000"; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <10000000>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "bl2"; ++ reg = <0x0 0x20000>; ++ read-only; ++ }; ++ ++ partition@20000 { ++ label = "reserved"; ++ reg = <0x20000 0x20000>; ++ }; ++ ++ partition@40000 { ++ label = "u-boot-env"; ++ reg = <0x40000 0x40000>; ++ }; ++ ++ partition@80000 { ++ label = "reserved2"; ++ reg = <0x80000 0x80000>; ++ }; ++ ++ partition@100000 { ++ label = "fip"; ++ reg = <0x100000 0x80000>; ++ read-only; ++ }; ++ ++ partition@180000 { ++ label = "recovery"; ++ reg = <0x180000 0xa80000>; ++ }; ++ ++ partition@c00000 { ++ label = "fit"; ++ reg = <0xc00000 0x1400000>; ++ }; ++ }; ++ }; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso +@@ -0,0 +1,23 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2021 MediaTek Inc. ++ * Author: Sam.Shih ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; ++ ++ fragment@0 { ++ target-path = "/soc/mmc@11230000"; ++ __overlay__ { ++ bus-width = <4>; ++ max-frequency = <52000000>; ++ cap-sd-highspeed; ++ status = "okay"; ++ }; ++ }; ++}; ++ +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts +@@ -0,0 +1,450 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2021 MediaTek Inc. ++ * Authors: Sam.Shih ++ * Frank Wunderlich ++ * Daniel Golle ++ */ ++ ++/dts-v1/; ++#include ++#include ++#include ++#include ++ ++#include "mt7986a.dtsi" ++ ++/ { ++ model = "Bananapi BPI-R3"; ++ compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; ++ ++ aliases { ++ serial0 = &uart0; ++ ethernet0 = &gmac0; ++ ethernet1 = &gmac1; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ dcin: regulator-12vd { ++ compatible = "regulator-fixed"; ++ regulator-name = "12vd"; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ ++ reset-key { ++ label = "reset"; ++ linux,code = ; ++ gpios = <&pio 9 GPIO_ACTIVE_LOW>; ++ }; ++ ++ wps-key { ++ label = "wps"; ++ linux,code = ; ++ gpios = <&pio 10 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ /* i2c of the left SFP cage (wan) */ ++ i2c_sfp1: i2c-gpio-0 { ++ compatible = "i2c-gpio"; ++ sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; ++ scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; ++ i2c-gpio,delay-us = <2>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ /* i2c of the right SFP cage (lan) */ ++ i2c_sfp2: i2c-gpio-1 { ++ compatible = "i2c-gpio"; ++ sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; ++ scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; ++ i2c-gpio,delay-us = <2>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ green_led: led-0 { ++ color = ; ++ function = LED_FUNCTION_POWER; ++ gpios = <&pio 69 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; ++ }; ++ ++ blue_led: led-1 { ++ color = ; ++ function = LED_FUNCTION_STATUS; ++ gpios = <&pio 86 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ }; ++ }; ++ ++ reg_1p8v: regulator-1p8v { ++ compatible = "regulator-fixed"; ++ regulator-name = "1.8vd"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ vin-supply = <&dcin>; ++ }; ++ ++ reg_3p3v: regulator-3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "3.3vd"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ vin-supply = <&dcin>; ++ }; ++ ++ /* left SFP cage (wan) */ ++ sfp1: sfp-1 { ++ compatible = "sff,sfp"; ++ i2c-bus = <&i2c_sfp1>; ++ los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>; ++ mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>; ++ tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>; ++ tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ /* right SFP cage (lan) */ ++ sfp2: sfp-2 { ++ compatible = "sff,sfp"; ++ i2c-bus = <&i2c_sfp2>; ++ los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>; ++ mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>; ++ tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>; ++ tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>; ++ }; ++}; ++ ++&crypto { ++ status = "okay"; ++}; ++ ++ð { ++ status = "okay"; ++ ++ gmac0: mac@0 { ++ compatible = "mediatek,eth-mac"; ++ reg = <0>; ++ phy-mode = "2500base-x"; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ pause; ++ }; ++ }; ++ ++ gmac1: mac@1 { ++ compatible = "mediatek,eth-mac"; ++ reg = <1>; ++ phy-mode = "2500base-x"; ++ sfp = <&sfp1>; ++ managed = "in-band-status"; ++ }; ++ ++ mdio: mdio-bus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++}; ++ ++&mdio { ++ switch: switch@31 { ++ compatible = "mediatek,mt7531"; ++ reg = <31>; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ interrupt-parent = <&pio>; ++ interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; ++ reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; ++ }; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default", "state_uhs"; ++ pinctrl-0 = <&mmc0_pins_default>; ++ pinctrl-1 = <&mmc0_pins_uhs>; ++ vmmc-supply = <®_3p3v>; ++ vqmmc-supply = <®_1p8v>; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c_pins>; ++ status = "okay"; ++}; ++ ++&pcie { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_pins>; ++ status = "okay"; ++}; ++ ++&pcie_phy { ++ status = "okay"; ++}; ++ ++&pio { ++ i2c_pins: i2c-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c"; ++ }; ++ }; ++ ++ mmc0_pins_default: mmc0-pins { ++ mux { ++ function = "emmc"; ++ groups = "emmc_51"; ++ }; ++ conf-cmd-dat { ++ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", ++ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", ++ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; ++ input-enable; ++ drive-strength = <4>; ++ bias-pull-up = ; /* pull-up 10K */ ++ }; ++ conf-clk { ++ pins = "EMMC_CK"; ++ drive-strength = <6>; ++ bias-pull-down = ; /* pull-down 50K */ ++ }; ++ conf-ds { ++ pins = "EMMC_DSL"; ++ bias-pull-down = ; /* pull-down 50K */ ++ }; ++ conf-rst { ++ pins = "EMMC_RSTB"; ++ drive-strength = <4>; ++ bias-pull-up = ; /* pull-up 10K */ ++ }; ++ }; ++ ++ mmc0_pins_uhs: mmc0-uhs-pins { ++ mux { ++ function = "emmc"; ++ groups = "emmc_51"; ++ }; ++ conf-cmd-dat { ++ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", ++ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", ++ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; ++ input-enable; ++ drive-strength = <4>; ++ bias-pull-up = ; /* pull-up 10K */ ++ }; ++ conf-clk { ++ pins = "EMMC_CK"; ++ drive-strength = <6>; ++ bias-pull-down = ; /* pull-down 50K */ ++ }; ++ conf-ds { ++ pins = "EMMC_DSL"; ++ bias-pull-down = ; /* pull-down 50K */ ++ }; ++ conf-rst { ++ pins = "EMMC_RSTB"; ++ drive-strength = <4>; ++ bias-pull-up = ; /* pull-up 10K */ ++ }; ++ }; ++ ++ pcie_pins: pcie-pins { ++ mux { ++ function = "pcie"; ++ groups = "pcie_clk", "pcie_pereset"; ++ }; ++ }; ++ ++ spi_flash_pins: spi-flash-pins { ++ mux { ++ function = "spi"; ++ groups = "spi0", "spi0_wp_hold"; ++ }; ++ }; ++ ++ spic_pins: spic-pins { ++ mux { ++ function = "spi"; ++ groups = "spi1_0"; ++ }; ++ }; ++ ++ uart1_pins: uart1-pins { ++ mux { ++ function = "uart"; ++ groups = "uart1_rx_tx"; ++ }; ++ }; ++ ++ uart2_pins: uart2-pins { ++ mux { ++ function = "uart"; ++ groups = "uart2_0_rx_tx"; ++ }; ++ }; ++ ++ wf_2g_5g_pins: wf-2g-5g-pins { ++ mux { ++ function = "wifi"; ++ groups = "wf_2g", "wf_5g"; ++ }; ++ conf { ++ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", ++ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", ++ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", ++ "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", ++ "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", ++ "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", ++ "WF1_TOP_CLK", "WF1_TOP_DATA"; ++ drive-strength = <4>; ++ }; ++ }; ++ ++ wf_dbdc_pins: wf-dbdc-pins { ++ mux { ++ function = "wifi"; ++ groups = "wf_dbdc"; ++ }; ++ conf { ++ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", ++ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", ++ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", ++ "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", ++ "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", ++ "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", ++ "WF1_TOP_CLK", "WF1_TOP_DATA"; ++ drive-strength = <4>; ++ }; ++ }; ++ ++ wf_led_pins: wf-led-pins { ++ mux { ++ function = "led"; ++ groups = "wifi_led"; ++ }; ++ }; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi_flash_pins>; ++ status = "okay"; ++}; ++ ++&spi1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spic_pins>; ++ status = "okay"; ++}; ++ ++&ssusb { ++ status = "okay"; ++}; ++ ++&switch { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ label = "wan"; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ label = "lan0"; ++ }; ++ ++ port@2 { ++ reg = <2>; ++ label = "lan1"; ++ }; ++ ++ port@3 { ++ reg = <3>; ++ label = "lan2"; ++ }; ++ ++ port@4 { ++ reg = <4>; ++ label = "lan3"; ++ }; ++ ++ port5: port@5 { ++ reg = <5>; ++ label = "lan4"; ++ phy-mode = "2500base-x"; ++ sfp = <&sfp2>; ++ managed = "in-band-status"; ++ }; ++ ++ port@6 { ++ reg = <6>; ++ label = "cpu"; ++ ethernet = <&gmac0>; ++ phy-mode = "2500base-x"; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ pause; ++ }; ++ }; ++ }; ++}; ++ ++&trng { ++ status = "okay"; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins>; ++ status = "okay"; ++}; ++ ++&usb_phy { ++ status = "okay"; ++}; ++ ++&watchdog { ++ status = "okay"; ++}; ++ ++&wifi { ++ status = "okay"; ++ pinctrl-names = "default", "dbdc"; ++ pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>; ++ pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>; ++}; ++ diff --git a/target/linux/mediatek/patches-6.1/011-v6.5-arm64-mediatek-Propagate-chassis-type-where-possible.patch b/target/linux/mediatek/patches-6.1/011-v6.5-arm64-mediatek-Propagate-chassis-type-where-possible.patch new file mode 100644 index 00000000000..79038334c4e --- /dev/null +++ b/target/linux/mediatek/patches-6.1/011-v6.5-arm64-mediatek-Propagate-chassis-type-where-possible.patch @@ -0,0 +1,323 @@ +From 4c2d5411f4b101f7aa0fd74f80109e3afd6dc967 Mon Sep 17 00:00:00 2001 +From: AngeloGioacchino Del Regno +Date: Wed, 17 May 2023 12:11:08 +0200 +Subject: [PATCH 11/19] arm64: mediatek: Propagate chassis-type where possible + +The chassis-type string identifies the form-factor of the system: +add this property to all device trees of devices for which the form +factor is known. + +Signed-off-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20230517101108.205654-1-angelogioacchino.delregno@collabora.com +Signed-off-by: Matthias Brugger +--- + arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 1 + + arch/arm64/boot/dts/mediatek/mt6755-evb.dts | 1 + + arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 1 + + arch/arm64/boot/dts/mediatek/mt6795-evb.dts | 1 + + arch/arm64/boot/dts/mediatek/mt6797-evb.dts | 1 + + arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts | 1 + + arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts | 1 + + arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 1 + + arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 1 + + arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 1 + + arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 1 + + arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts | 1 + + arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts | 1 + + arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts | 1 + + arch/arm64/boot/dts/mediatek/mt8173-elm.dts | 1 + + arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 1 + + arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 1 + + arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts | 1 + + arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts | 1 + + .../boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts | 1 + + arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts | 1 + + arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts | 1 + + arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts | 1 + + arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts | 1 + + arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts | 1 + + arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts | 1 + + arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts | 1 + + arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 1 + + 28 files changed, 28 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts ++++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts +@@ -11,6 +11,7 @@ + + / { + model = "MediaTek MT2712 evaluation board"; ++ chassis-type = "embedded"; + compatible = "mediatek,mt2712-evb", "mediatek,mt2712"; + + aliases { +--- a/arch/arm64/boot/dts/mediatek/mt6755-evb.dts ++++ b/arch/arm64/boot/dts/mediatek/mt6755-evb.dts +@@ -9,6 +9,7 @@ + + / { + model = "MediaTek MT6755 EVB"; ++ chassis-type = "embedded"; + compatible = "mediatek,mt6755-evb", "mediatek,mt6755"; + + aliases { +--- a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts ++++ b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts +@@ -10,6 +10,7 @@ + + / { + model = "MediaTek MT6779 EVB"; ++ chassis-type = "embedded"; + compatible = "mediatek,mt6779-evb", "mediatek,mt6779"; + + aliases { +--- a/arch/arm64/boot/dts/mediatek/mt6795-evb.dts ++++ b/arch/arm64/boot/dts/mediatek/mt6795-evb.dts +@@ -9,6 +9,7 @@ + + / { + model = "MediaTek MT6795 Evaluation Board"; ++ chassis-type = "embedded"; + compatible = "mediatek,mt6795-evb", "mediatek,mt6795"; + + aliases { +--- a/arch/arm64/boot/dts/mediatek/mt6797-evb.dts ++++ b/arch/arm64/boot/dts/mediatek/mt6797-evb.dts +@@ -9,6 +9,7 @@ + + / { + model = "MediaTek MT6797 Evaluation Board"; ++ chassis-type = "embedded"; + compatible = "mediatek,mt6797-evb", "mediatek,mt6797"; + + aliases { +--- a/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts ++++ b/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts +@@ -12,6 +12,7 @@ + + / { + model = "Mediatek X20 Development Board"; ++ chassis-type = "embedded"; + compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797"; + + aliases { +--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +@@ -15,6 +15,7 @@ + + / { + model = "Bananapi BPI-R64"; ++ chassis-type = "embedded"; + compatible = "bananapi,bpi-r64", "mediatek,mt7622"; + + aliases { +--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +@@ -15,6 +15,7 @@ + + / { + model = "MediaTek MT7622 RFB1 board"; ++ chassis-type = "embedded"; + compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622"; + + aliases { +--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts +@@ -16,6 +16,7 @@ + + / { + model = "Bananapi BPI-R3"; ++ chassis-type = "embedded"; + compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; + + aliases { +--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +@@ -11,6 +11,7 @@ + + / { + model = "MediaTek MT7986a RFB"; ++ chassis-type = "embedded"; + compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a"; + + aliases { +--- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts +@@ -9,6 +9,7 @@ + + / { + model = "MediaTek MT7986b RFB"; ++ chassis-type = "embedded"; + compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b"; + + aliases { +--- a/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts ++++ b/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts +@@ -11,6 +11,7 @@ + + / { + model = "Pumpkin MT8167"; ++ chassis-type = "embedded"; + compatible = "mediatek,mt8167-pumpkin", "mediatek,mt8167"; + + memory@40000000 { +--- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts ++++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts +@@ -8,6 +8,7 @@ + + / { + model = "Google Hanawl"; ++ chassis-type = "laptop"; + compatible = "google,hana-rev7", "mediatek,mt8173"; + }; + +--- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts ++++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts +@@ -8,6 +8,7 @@ + + / { + model = "Google Hana"; ++ chassis-type = "laptop"; + compatible = "google,hana-rev6", "google,hana-rev5", + "google,hana-rev4", "google,hana-rev3", + "google,hana", "mediatek,mt8173"; +--- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dts ++++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dts +@@ -8,6 +8,7 @@ + + / { + model = "Google Elm"; ++ chassis-type = "laptop"; + compatible = "google,elm-rev8", "google,elm-rev7", "google,elm-rev6", + "google,elm-rev5", "google,elm-rev4", "google,elm-rev3", + "google,elm", "mediatek,mt8173"; +--- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts ++++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts +@@ -10,6 +10,7 @@ + + / { + model = "MediaTek MT8173 evaluation board"; ++ chassis-type = "embedded"; + compatible = "mediatek,mt8173-evb", "mediatek,mt8173"; + + aliases { +--- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts ++++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts +@@ -11,6 +11,7 @@ + + / { + model = "MediaTek MT8183 evaluation board"; ++ chassis-type = "embedded"; + compatible = "mediatek,mt8183-evb", "mediatek,mt8183"; + + aliases { +--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts ++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts +@@ -9,6 +9,7 @@ + + / { + model = "Google burnet board"; ++ chassis-type = "convertible"; + compatible = "google,burnet", "mediatek,mt8183"; + }; + +--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts ++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts +@@ -9,6 +9,7 @@ + + / { + model = "Google damu board"; ++ chassis-type = "convertible"; + compatible = "google,damu", "mediatek,mt8183"; + }; + +--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts ++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts +@@ -9,6 +9,7 @@ + + / { + model = "Google juniper sku16 board"; ++ chassis-type = "convertible"; + compatible = "google,juniper-sku16", "google,juniper", "mediatek,mt8183"; + }; + +--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts ++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts +@@ -9,6 +9,7 @@ + + / { + model = "MediaTek kakadu board sku22"; ++ chassis-type = "tablet"; + compatible = "google,kakadu-rev3-sku22", "google,kakadu-rev2-sku22", + "google,kakadu", "mediatek,mt8183"; + }; +--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts ++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts +@@ -9,6 +9,7 @@ + + / { + model = "MediaTek kakadu board"; ++ chassis-type = "tablet"; + compatible = "google,kakadu-rev3", "google,kakadu-rev2", + "google,kakadu", "mediatek,mt8183"; + }; +--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts ++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts +@@ -12,6 +12,7 @@ + + / { + model = "MediaTek kodama sku16 board"; ++ chassis-type = "tablet"; + compatible = "google,kodama-sku16", "google,kodama", "mediatek,mt8183"; + }; + +--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts ++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts +@@ -12,6 +12,7 @@ + + / { + model = "MediaTek kodama sku272 board"; ++ chassis-type = "tablet"; + compatible = "google,kodama-sku272", "google,kodama", "mediatek,mt8183"; + }; + +--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts ++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts +@@ -12,6 +12,7 @@ + + / { + model = "MediaTek kodama sku288 board"; ++ chassis-type = "tablet"; + compatible = "google,kodama-sku288", "google,kodama", "mediatek,mt8183"; + }; + +--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts ++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts +@@ -14,6 +14,7 @@ + + / { + model = "MediaTek krane sku0 board"; ++ chassis-type = "tablet"; + compatible = "google,krane-sku0", "google,krane", "mediatek,mt8183"; + }; + +--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts ++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts +@@ -14,6 +14,7 @@ + + / { + model = "MediaTek krane sku176 board"; ++ chassis-type = "tablet"; + compatible = "google,krane-sku176", "google,krane", "mediatek,mt8183"; + }; + +--- a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts ++++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts +@@ -7,6 +7,7 @@ + + / { + model = "MediaTek MT8186 evaluation board"; ++ chassis-type = "embedded"; + compatible = "mediatek,mt8186-evb", "mediatek,mt8186"; + + aliases { diff --git a/target/linux/mediatek/patches-6.1/012-v6.5-arm64-dts-mt7986-add-PWM.patch b/target/linux/mediatek/patches-6.1/012-v6.5-arm64-dts-mt7986-add-PWM.patch new file mode 100644 index 00000000000..e8c47945d63 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/012-v6.5-arm64-dts-mt7986-add-PWM.patch @@ -0,0 +1,38 @@ +From 3b92c547e3d4a35c6214b3e7fa1103d0749d83b1 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Fri, 21 Apr 2023 15:20:44 +0200 +Subject: [PATCH 12/19] arm64: dts: mt7986: add PWM + +This adds pwm node to mt7986. + +Signed-off-by: Daniel Golle +Signed-off-by: Frank Wunderlich +Link: https://lore.kernel.org/r/20230421132047.42166-5-linux@fw-web.de +Signed-off-by: Matthias Brugger +--- + arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +@@ -240,6 +240,20 @@ + status = "disabled"; + }; + ++ pwm: pwm@10048000 { ++ compatible = "mediatek,mt7986-pwm"; ++ reg = <0 0x10048000 0 0x1000>; ++ #clock-cells = <1>; ++ #pwm-cells = <2>; ++ interrupts = ; ++ clocks = <&topckgen CLK_TOP_PWM_SEL>, ++ <&infracfg CLK_INFRA_PWM_STA>, ++ <&infracfg CLK_INFRA_PWM1_CK>, ++ <&infracfg CLK_INFRA_PWM2_CK>; ++ clock-names = "top", "main", "pwm1", "pwm2"; ++ status = "disabled"; ++ }; ++ + uart0: serial@11002000 { + compatible = "mediatek,mt7986-uart", + "mediatek,mt6577-uart"; diff --git a/target/linux/mediatek/patches-6.1/013-v6.5-arm64-dts-mt7986-add-PWM-to-BPI-R3.patch b/target/linux/mediatek/patches-6.1/013-v6.5-arm64-dts-mt7986-add-PWM-to-BPI-R3.patch new file mode 100644 index 00000000000..ce908e3d31f --- /dev/null +++ b/target/linux/mediatek/patches-6.1/013-v6.5-arm64-dts-mt7986-add-PWM-to-BPI-R3.patch @@ -0,0 +1,43 @@ +From 35e482bb599df010b4869017ff576dbb7a4d4c2e Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Fri, 21 Apr 2023 15:20:45 +0200 +Subject: [PATCH 13/19] arm64: dts: mt7986: add PWM to BPI-R3 + +Add pwm node and pinctrl to BananaPi R3 devicetree. + +Signed-off-by: Frank Wunderlich +Link: https://lore.kernel.org/r/20230421132047.42166-6-linux@fw-web.de +Signed-off-by: Matthias Brugger +--- + .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts +@@ -275,6 +275,13 @@ + }; + }; + ++ pwm_pins: pwm-pins { ++ mux { ++ function = "pwm"; ++ groups = "pwm0", "pwm1_0"; ++ }; ++ }; ++ + spi_flash_pins: spi-flash-pins { + mux { + function = "spi"; +@@ -345,6 +352,12 @@ + }; + }; + ++&pwm { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm_pins>; ++ status = "okay"; ++}; ++ + &spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; diff --git a/target/linux/mediatek/patches-6.1/014-v6.5-arm64-dts-mt7986-set-Wifi-Leds-low-active-for-BPI-R3.patch b/target/linux/mediatek/patches-6.1/014-v6.5-arm64-dts-mt7986-set-Wifi-Leds-low-active-for-BPI-R3.patch new file mode 100644 index 00000000000..c7b38484f4f --- /dev/null +++ b/target/linux/mediatek/patches-6.1/014-v6.5-arm64-dts-mt7986-set-Wifi-Leds-low-active-for-BPI-R3.patch @@ -0,0 +1,27 @@ +From ccdda5714446db8690505371442f7807f5d7c6fc Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Sun, 5 Feb 2023 18:48:33 +0100 +Subject: [PATCH 14/19] arm64: dts: mt7986: set Wifi Leds low-active for BPI-R3 + +Leds for Wifi are low-active, so add property to devicetree. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20230205174833.107050-1-linux@fw-web.de +Signed-off-by: Matthias Brugger +--- + arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts +@@ -460,5 +460,9 @@ + pinctrl-names = "default", "dbdc"; + pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>; + pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>; ++ ++ led { ++ led-active-low; ++ }; + }; + diff --git a/target/linux/mediatek/patches-6.1/015-v6.5-arm64-dts-mt7986-use-size-of-reserved-partition-for-.patch b/target/linux/mediatek/patches-6.1/015-v6.5-arm64-dts-mt7986-use-size-of-reserved-partition-for-.patch new file mode 100644 index 00000000000..0b84f1463ac --- /dev/null +++ b/target/linux/mediatek/patches-6.1/015-v6.5-arm64-dts-mt7986-use-size-of-reserved-partition-for-.patch @@ -0,0 +1,46 @@ +From 1423b4b780adcf3994e63a5988a62d5d1d509bb1 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Sun, 28 May 2023 13:33:42 +0200 +Subject: [PATCH 15/19] arm64: dts: mt7986: use size of reserved partition for + bl2 + +To store uncompressed bl2 more space is required than partition is +actually defined. + +There is currently no known usage of this reserved partition. +Openwrt uses same partition layout. + +We added same change to u-boot with commit d7bb1099 [1]. + +[1] https://source.denx.de/u-boot/u-boot/-/commit/d7bb109900c1ca754a0198b9afb50e3161ffc21e + +Cc: stable@vger.kernel.org +Fixes: 8e01fb15b815 ("arm64: dts: mt7986: add Bananapi R3") +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Reviewed-by: Daniel Golle +Link: https://lore.kernel.org/r/20230528113343.7649-1-linux@fw-web.de +Signed-off-by: Matthias Brugger +--- + .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso | 7 +------ + 1 file changed, 1 insertion(+), 6 deletions(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso +@@ -27,15 +27,10 @@ + + partition@0 { + label = "bl2"; +- reg = <0x0 0x20000>; ++ reg = <0x0 0x40000>; + read-only; + }; + +- partition@20000 { +- label = "reserved"; +- reg = <0x20000 0x20000>; +- }; +- + partition@40000 { + label = "u-boot-env"; + reg = <0x40000 0x40000>; diff --git a/target/linux/mediatek/patches-6.1/016-v6.5-arm64-dts-mt7986-add-thermal-and-efuse.patch b/target/linux/mediatek/patches-6.1/016-v6.5-arm64-dts-mt7986-add-thermal-and-efuse.patch new file mode 100644 index 00000000000..0d12079d7c6 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/016-v6.5-arm64-dts-mt7986-add-thermal-and-efuse.patch @@ -0,0 +1,80 @@ +From 40a5a767d698ef7a71f8be851ea18b0a7a8b47bd Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Tue, 30 May 2023 22:12:33 +0200 +Subject: [PATCH 16/19] arm64: dts: mt7986: add thermal and efuse + +Add thermal related nodes to mt7986 devicetree. + +Signed-off-by: Daniel Golle +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20230530201235.22330-3-linux@fw-web.de +Signed-off-by: Matthias Brugger +--- + arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 36 ++++++++++++++++++++++- + 1 file changed, 35 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +@@ -337,6 +337,15 @@ + status = "disabled"; + }; + ++ auxadc: adc@1100d000 { ++ compatible = "mediatek,mt7986-auxadc"; ++ reg = <0 0x1100d000 0 0x1000>; ++ clocks = <&infracfg CLK_INFRA_ADC_26M_CK>; ++ clock-names = "main"; ++ #io-channel-cells = <1>; ++ status = "disabled"; ++ }; ++ + ssusb: usb@11200000 { + compatible = "mediatek,mt7986-xhci", + "mediatek,mtk-xhci"; +@@ -375,6 +384,21 @@ + status = "disabled"; + }; + ++ thermal: thermal@1100c800 { ++ #thermal-sensor-cells = <1>; ++ compatible = "mediatek,mt7986-thermal"; ++ reg = <0 0x1100c800 0 0x800>; ++ interrupts = ; ++ clocks = <&infracfg CLK_INFRA_THERM_CK>, ++ <&infracfg CLK_INFRA_ADC_26M_CK>, ++ <&infracfg CLK_INFRA_ADC_FRC_CK>; ++ clock-names = "therm", "auxadc", "adc_32k"; ++ mediatek,auxadc = <&auxadc>; ++ mediatek,apmixedsys = <&apmixedsys>; ++ nvmem-cells = <&thermal_calibration>; ++ nvmem-cell-names = "calibration-data"; ++ }; ++ + pcie: pcie@11280000 { + compatible = "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; +@@ -426,6 +450,17 @@ + }; + }; + ++ efuse: efuse@11d00000 { ++ compatible = "mediatek,mt7986-efuse", "mediatek,efuse"; ++ reg = <0 0x11d00000 0 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ thermal_calibration: calib@274 { ++ reg = <0x274 0xc>; ++ }; ++ }; ++ + usb_phy: t-phy@11e10000 { + compatible = "mediatek,mt7986-tphy", + "mediatek,generic-tphy-v2"; +@@ -567,5 +602,4 @@ + memory-region = <&wmcpu_emi>; + }; + }; +- + }; diff --git a/target/linux/mediatek/patches-6.1/017-v6.5-arm64-dts-mt7986-add-thermal-zones.patch b/target/linux/mediatek/patches-6.1/017-v6.5-arm64-dts-mt7986-add-thermal-zones.patch new file mode 100644 index 00000000000..3fe3e885ebb --- /dev/null +++ b/target/linux/mediatek/patches-6.1/017-v6.5-arm64-dts-mt7986-add-thermal-zones.patch @@ -0,0 +1,51 @@ +From bb78d0cf5117517f1ed296ae71048945d9107675 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Tue, 30 May 2023 22:12:34 +0200 +Subject: [PATCH 17/19] arm64: dts: mt7986: add thermal-zones + +Add thermal-zones to mt7986 devicetree. + +Signed-off-by: Daniel Golle +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20230530201235.22330-4-linux@fw-web.de +Signed-off-by: Matthias Brugger +--- + arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 28 +++++++++++++++++++++++ + 1 file changed, 28 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +@@ -602,4 +602,32 @@ + memory-region = <&wmcpu_emi>; + }; + }; ++ ++ thermal-zones { ++ cpu_thermal: cpu-thermal { ++ polling-delay-passive = <1000>; ++ polling-delay = <1000>; ++ thermal-sensors = <&thermal 0>; ++ ++ trips { ++ cpu_trip_active_high: active-high { ++ temperature = <115000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ ++ cpu_trip_active_low: active-low { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ ++ cpu_trip_passive: passive { ++ temperature = <40000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ }; ++ }; ++ }; + }; diff --git a/target/linux/mediatek/patches-6.1/018-v6.5-arm64-dts-mt7986-add-pwm-fan-and-cooling-maps-to-BPI.patch b/target/linux/mediatek/patches-6.1/018-v6.5-arm64-dts-mt7986-add-pwm-fan-and-cooling-maps-to-BPI.patch new file mode 100644 index 00000000000..ca7d872a1bf --- /dev/null +++ b/target/linux/mediatek/patches-6.1/018-v6.5-arm64-dts-mt7986-add-pwm-fan-and-cooling-maps-to-BPI.patch @@ -0,0 +1,64 @@ +From 5d90603b09e5814ffc38c47e79ccf9bc564f9296 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Tue, 30 May 2023 22:12:35 +0200 +Subject: [PATCH 18/19] arm64: dts: mt7986: add pwm-fan and cooling-maps to + BPI-R3 dts + +Add pwm-fan and cooling-maps to BananaPi-R3 devicetree. + +Signed-off-by: Daniel Golle +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20230530201235.22330-5-linux@fw-web.de +Signed-off-by: Matthias Brugger +--- + .../dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 31 +++++++++++++++++++ + 1 file changed, 31 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts +@@ -38,6 +38,15 @@ + regulator-always-on; + }; + ++ fan: pwm-fan { ++ compatible = "pwm-fan"; ++ #cooling-cells = <2>; ++ /* cooling level (0, 1, 2) - pwm inverted */ ++ cooling-levels = <255 96 0>; ++ pwms = <&pwm 0 10000 0>; ++ status = "okay"; ++ }; ++ + gpio-keys { + compatible = "gpio-keys"; + +@@ -133,6 +142,28 @@ + }; + }; + ++&cpu_thermal { ++ cooling-maps { ++ cpu-active-high { ++ /* active: set fan to cooling level 2 */ ++ cooling-device = <&fan 2 2>; ++ trip = <&cpu_trip_active_high>; ++ }; ++ ++ cpu-active-low { ++ /* active: set fan to cooling level 1 */ ++ cooling-device = <&fan 1 1>; ++ trip = <&cpu_trip_active_low>; ++ }; ++ ++ cpu-passive { ++ /* passive: set fan to cooling level 0 */ ++ cooling-device = <&fan 0 0>; ++ trip = <&cpu_trip_passive>; ++ }; ++ }; ++}; ++ + &crypto { + status = "okay"; + }; diff --git a/target/linux/mediatek/patches-6.1/019-v6.5-arm64-dts-mt7986-increase-bl2-partition-on-NAND-of-B.patch b/target/linux/mediatek/patches-6.1/019-v6.5-arm64-dts-mt7986-increase-bl2-partition-on-NAND-of-B.patch new file mode 100644 index 00000000000..9cc6cad0af5 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/019-v6.5-arm64-dts-mt7986-increase-bl2-partition-on-NAND-of-B.patch @@ -0,0 +1,41 @@ +From 6dd3b939370094eb79529683be84500f3c757404 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Tue, 6 Jun 2023 16:43:20 +0100 +Subject: [PATCH 19/19] arm64: dts: mt7986: increase bl2 partition on NAND of + Bananapi R3 + +The bootrom burned into the MT7986 SoC will try multiple locations on +the SPI-NAND flash to load bl2 in case the bl2 image located at the the +previously attempted offset is corrupt. + +Use 0x100000 instead of 0x80000 as partition size for bl2 on SPI-NAND, +allowing for up to four redundant copies of bl2 (typically sized a +bit less than 0x40000). + +Fixes: 8e01fb15b8157 ("arm64: dts: mt7986: add Bananapi R3") +Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/ZH9UGF99RgzrHZ88@makrotopia.org +Signed-off-by: Matthias Brugger +--- + .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso +@@ -29,13 +29,13 @@ + + partition@0 { + label = "bl2"; +- reg = <0x0 0x80000>; ++ reg = <0x0 0x100000>; + read-only; + }; + +- partition@80000 { ++ partition@100000 { + label = "reserved"; +- reg = <0x80000 0x300000>; ++ reg = <0x100000 0x280000>; + }; + + partition@380000 { diff --git a/target/linux/mediatek/patches-6.1/100-dts-update-mt7622-rfb1.patch b/target/linux/mediatek/patches-6.1/100-dts-update-mt7622-rfb1.patch index 7224a9882c0..1c249c03a68 100644 --- a/target/linux/mediatek/patches-6.1/100-dts-update-mt7622-rfb1.patch +++ b/target/linux/mediatek/patches-6.1/100-dts-update-mt7622-rfb1.patch @@ -10,7 +10,7 @@ * * SPDX-License-Identifier: (GPL-2.0 OR MIT) */ -@@ -23,7 +22,7 @@ +@@ -24,7 +23,7 @@ chosen { stdout-path = "serial0:115200n8"; @@ -19,20 +19,15 @@ }; cpus { -@@ -40,23 +39,22 @@ - - gpio-keys { - compatible = "gpio-keys"; -- poll-interval = <100>; - - factory { +@@ -45,18 +44,18 @@ + key-factory { label = "factory"; linux,code = ; - gpios = <&pio 0 0>; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; }; - wps { + key-wps { label = "wps"; linux,code = ; - gpios = <&pio 102 0>; @@ -46,7 +41,7 @@ }; reg_1p8v: regulator-1p8v { -@@ -132,22 +130,22 @@ +@@ -132,22 +131,22 @@ port@0 { reg = <0>; @@ -73,23 +68,16 @@ }; port@4 { -@@ -236,15 +234,28 @@ - - &pcie { - pinctrl-names = "default"; -- pinctrl-0 = <&pcie0_pins>; -+ pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>; +@@ -240,7 +239,22 @@ status = "okay"; - - pcie@0,0 { - status = "okay"; - }; -+ -+ pcie@1,0 { -+ status = "okay"; -+ }; }; ++&pcie1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie1_pins>; ++ status = "okay"; ++}; ++ &pio { + /* Attention: GPIO 90 is used to switch between PCIe@1,0 and + * SATA functions. i.e. output-high: PCIe, output-low: SATA @@ -103,7 +91,7 @@ /* eMMC is shared pin with parallel NAND */ emmc_pins_default: emmc-pins-default { mux { -@@ -521,11 +532,11 @@ +@@ -517,11 +531,11 @@ }; &sata { diff --git a/target/linux/mediatek/patches-6.1/101-dts-update-mt7629-rfb.patch b/target/linux/mediatek/patches-6.1/101-dts-update-mt7629-rfb.patch index 254b5f9eb72..b1770371b00 100644 --- a/target/linux/mediatek/patches-6.1/101-dts-update-mt7629-rfb.patch +++ b/target/linux/mediatek/patches-6.1/101-dts-update-mt7629-rfb.patch @@ -40,7 +40,7 @@ }; }; }; -@@ -272,3 +281,17 @@ +@@ -273,3 +282,17 @@ pinctrl-0 = <&watchdog_pins>; status = "okay"; }; diff --git a/target/linux/mediatek/patches-6.1/104-mt7622-add-snor-irq.patch b/target/linux/mediatek/patches-6.1/104-mt7622-add-snor-irq.patch index 79b051147a3..0d9c91f44dd 100644 --- a/target/linux/mediatek/patches-6.1/104-mt7622-add-snor-irq.patch +++ b/target/linux/mediatek/patches-6.1/104-mt7622-add-snor-irq.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -559,6 +559,7 @@ +@@ -578,6 +578,7 @@ compatible = "mediatek,mt7622-nor", "mediatek,mt8173-nor"; reg = <0 0x11014000 0 0xe0>; diff --git a/target/linux/mediatek/patches-6.1/105-dts-mt7622-enable-pstore.patch b/target/linux/mediatek/patches-6.1/105-dts-mt7622-enable-pstore.patch index da42c07728a..93da722e724 100644 --- a/target/linux/mediatek/patches-6.1/105-dts-mt7622-enable-pstore.patch +++ b/target/linux/mediatek/patches-6.1/105-dts-mt7622-enable-pstore.patch @@ -1,15 +1,6 @@ --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -111,7 +111,7 @@ - }; - - psci { -- compatible = "arm,psci-0.2"; -+ compatible = "arm,psci-1.0"; - method = "smc"; - }; - -@@ -127,6 +127,13 @@ +@@ -134,6 +134,13 @@ #size-cells = <2>; ranges; diff --git a/target/linux/mediatek/patches-6.1/111-dts-fix-bpi64-console.patch b/target/linux/mediatek/patches-6.1/111-dts-fix-bpi64-console.patch index 07a2eae2454..f77f10cb955 100644 --- a/target/linux/mediatek/patches-6.1/111-dts-fix-bpi64-console.patch +++ b/target/linux/mediatek/patches-6.1/111-dts-fix-bpi64-console.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -22,7 +22,7 @@ +@@ -24,7 +24,7 @@ chosen { stdout-path = "serial0:115200n8"; diff --git a/target/linux/mediatek/patches-6.1/112-dts-fix-bpi64-lan-names.patch b/target/linux/mediatek/patches-6.1/112-dts-fix-bpi64-lan-names.patch index 6ce85efde98..816683e6267 100644 --- a/target/linux/mediatek/patches-6.1/112-dts-fix-bpi64-lan-names.patch +++ b/target/linux/mediatek/patches-6.1/112-dts-fix-bpi64-lan-names.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -18,6 +18,7 @@ +@@ -20,6 +20,7 @@ aliases { serial0 = &uart0; @@ -8,7 +8,7 @@ }; chosen { -@@ -160,22 +161,22 @@ +@@ -164,22 +165,22 @@ port@1 { reg = <1>; diff --git a/target/linux/mediatek/patches-6.1/113-dts-fix-bpi64-leds-and-buttons.patch b/target/linux/mediatek/patches-6.1/113-dts-fix-bpi64-leds-and-buttons.patch index f88dbc71955..bf1912a9163 100644 --- a/target/linux/mediatek/patches-6.1/113-dts-fix-bpi64-leds-and-buttons.patch +++ b/target/linux/mediatek/patches-6.1/113-dts-fix-bpi64-leds-and-buttons.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -19,6 +19,10 @@ +@@ -21,6 +21,10 @@ aliases { serial0 = &uart0; ethernet0 = &gmac0; @@ -11,10 +11,10 @@ }; chosen { -@@ -42,8 +46,8 @@ +@@ -44,8 +48,8 @@ compatible = "gpio-keys"; - factory { + factory-key { - label = "factory"; - linux,code = ; + label = "reset"; @@ -22,35 +22,26 @@ gpios = <&pio 0 GPIO_ACTIVE_HIGH>; }; -@@ -57,17 +61,25 @@ +@@ -59,17 +63,17 @@ leds { compatible = "gpio-leds"; -- green { -- label = "bpi-r64:pio:green"; -- gpios = <&pio 89 GPIO_ACTIVE_HIGH>; -+ led_system_blue: blue { +- led-0 { ++ led_system_green: led-0 { + label = "bpi-r64:pio:green"; + color = ; + gpios = <&pio 89 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + +- led-1 { +- label = "bpi-r64:pio:red"; +- color = ; +- gpios = <&pio 88 GPIO_ACTIVE_HIGH>; ++ led_system_blue: led-1 { + label = "bpi-r64:pio:blue"; ++ color = ; + gpios = <&pio 85 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - -- red { -- label = "bpi-r64:pio:red"; -- gpios = <&pio 88 GPIO_ACTIVE_HIGH>; -+ led_system_green: green { -+ label = "bpi-r64:pio:green"; -+ gpios = <&pio 89 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; -+ -+/* -+ * red { -+ * label = "bpi-r64:pio:red"; -+ * gpios = <&pio 88 GPIO_ACTIVE_HIGH>; -+ * default-state = "off"; -+ * }; -+ */ }; - - memory { diff --git a/target/linux/mediatek/patches-6.1/114-dts-bpi64-disable-rtc.patch b/target/linux/mediatek/patches-6.1/114-dts-bpi64-disable-rtc.patch index 1f41142aacf..3d1b90217f1 100644 --- a/target/linux/mediatek/patches-6.1/114-dts-bpi64-disable-rtc.patch +++ b/target/linux/mediatek/patches-6.1/114-dts-bpi64-disable-rtc.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -564,12 +564,16 @@ +@@ -558,12 +558,16 @@ status = "okay"; }; diff --git a/target/linux/mediatek/patches-6.1/115-dts-bpi64-add-snand-support.patch b/target/linux/mediatek/patches-6.1/115-dts-bpi64-add-snand-support.patch index 34539a5d101..b159a17c4a2 100644 --- a/target/linux/mediatek/patches-6.1/115-dts-bpi64-add-snand-support.patch +++ b/target/linux/mediatek/patches-6.1/115-dts-bpi64-add-snand-support.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -259,14 +259,42 @@ +@@ -255,14 +255,42 @@ status = "disabled"; }; diff --git a/target/linux/mediatek/patches-6.1/120-01-v5.18-mtd-nand-ecc-Add-infrastructure-to-support-hardware-.patch b/target/linux/mediatek/patches-6.1/120-01-v5.18-mtd-nand-ecc-Add-infrastructure-to-support-hardware-.patch deleted file mode 100644 index 7fb62e7403c..00000000000 --- a/target/linux/mediatek/patches-6.1/120-01-v5.18-mtd-nand-ecc-Add-infrastructure-to-support-hardware-.patch +++ /dev/null @@ -1,214 +0,0 @@ -From ad4944aa0b02cb043afe20bc2a018c161e65c992 Mon Sep 17 00:00:00 2001 -From: Miquel Raynal -Date: Thu, 16 Dec 2021 12:16:38 +0100 -Subject: [PATCH 01/15] mtd: nand: ecc: Add infrastructure to support hardware - engines - -Add the necessary helpers to register/unregister hardware ECC engines -that will be called from ECC engine drivers. - -Also add helpers to get the right engine from the user -perspective. Keep a reference of the in use ECC engine in order to -prevent modules to be unloaded. Put the reference when the engine gets -retired. - -A static list of hardware (only) ECC engines is setup to keep track of -the registered engines. - -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20211216111654.238086-13-miquel.raynal@bootlin.com -(cherry picked from commit 96489c1c0b53131b0e1ec33e2060538379ad6152) ---- - drivers/mtd/nand/core.c | 10 +++-- - drivers/mtd/nand/ecc.c | 88 ++++++++++++++++++++++++++++++++++++++++ - include/linux/mtd/nand.h | 28 +++++++++++++ - 3 files changed, 123 insertions(+), 3 deletions(-) - ---- a/drivers/mtd/nand/core.c -+++ b/drivers/mtd/nand/core.c -@@ -232,7 +232,9 @@ static int nanddev_get_ecc_engine(struct - nand->ecc.engine = nand_ecc_get_on_die_hw_engine(nand); - break; - case NAND_ECC_ENGINE_TYPE_ON_HOST: -- pr_err("On-host hardware ECC engines not supported yet\n"); -+ nand->ecc.engine = nand_ecc_get_on_host_hw_engine(nand); -+ if (PTR_ERR(nand->ecc.engine) == -EPROBE_DEFER) -+ return -EPROBE_DEFER; - break; - default: - pr_err("Missing ECC engine type\n"); -@@ -252,7 +254,7 @@ static int nanddev_put_ecc_engine(struct - { - switch (nand->ecc.ctx.conf.engine_type) { - case NAND_ECC_ENGINE_TYPE_ON_HOST: -- pr_err("On-host hardware ECC engines not supported yet\n"); -+ nand_ecc_put_on_host_hw_engine(nand); - break; - case NAND_ECC_ENGINE_TYPE_NONE: - case NAND_ECC_ENGINE_TYPE_SOFT: -@@ -297,7 +299,9 @@ int nanddev_ecc_engine_init(struct nand_ - /* Look for the ECC engine to use */ - ret = nanddev_get_ecc_engine(nand); - if (ret) { -- pr_err("No ECC engine found\n"); -+ if (ret != -EPROBE_DEFER) -+ pr_err("No ECC engine found\n"); -+ - return ret; - } - ---- a/drivers/mtd/nand/ecc.c -+++ b/drivers/mtd/nand/ecc.c -@@ -96,6 +96,12 @@ - #include - #include - #include -+#include -+#include -+#include -+ -+static LIST_HEAD(on_host_hw_engines); -+static DEFINE_MUTEX(on_host_hw_engines_mutex); - - /** - * nand_ecc_init_ctx - Init the ECC engine context -@@ -611,6 +617,88 @@ struct nand_ecc_engine *nand_ecc_get_on_ - } - EXPORT_SYMBOL(nand_ecc_get_on_die_hw_engine); - -+int nand_ecc_register_on_host_hw_engine(struct nand_ecc_engine *engine) -+{ -+ struct nand_ecc_engine *item; -+ -+ if (!engine) -+ return -EINVAL; -+ -+ /* Prevent multiple registrations of one engine */ -+ list_for_each_entry(item, &on_host_hw_engines, node) -+ if (item == engine) -+ return 0; -+ -+ mutex_lock(&on_host_hw_engines_mutex); -+ list_add_tail(&engine->node, &on_host_hw_engines); -+ mutex_unlock(&on_host_hw_engines_mutex); -+ -+ return 0; -+} -+EXPORT_SYMBOL(nand_ecc_register_on_host_hw_engine); -+ -+int nand_ecc_unregister_on_host_hw_engine(struct nand_ecc_engine *engine) -+{ -+ if (!engine) -+ return -EINVAL; -+ -+ mutex_lock(&on_host_hw_engines_mutex); -+ list_del(&engine->node); -+ mutex_unlock(&on_host_hw_engines_mutex); -+ -+ return 0; -+} -+EXPORT_SYMBOL(nand_ecc_unregister_on_host_hw_engine); -+ -+static struct nand_ecc_engine *nand_ecc_match_on_host_hw_engine(struct device *dev) -+{ -+ struct nand_ecc_engine *item; -+ -+ list_for_each_entry(item, &on_host_hw_engines, node) -+ if (item->dev == dev) -+ return item; -+ -+ return NULL; -+} -+ -+struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand) -+{ -+ struct nand_ecc_engine *engine = NULL; -+ struct device *dev = &nand->mtd.dev; -+ struct platform_device *pdev; -+ struct device_node *np; -+ -+ if (list_empty(&on_host_hw_engines)) -+ return NULL; -+ -+ /* Check for an explicit nand-ecc-engine property */ -+ np = of_parse_phandle(dev->of_node, "nand-ecc-engine", 0); -+ if (np) { -+ pdev = of_find_device_by_node(np); -+ if (!pdev) -+ return ERR_PTR(-EPROBE_DEFER); -+ -+ engine = nand_ecc_match_on_host_hw_engine(&pdev->dev); -+ platform_device_put(pdev); -+ of_node_put(np); -+ -+ if (!engine) -+ return ERR_PTR(-EPROBE_DEFER); -+ } -+ -+ if (engine) -+ get_device(engine->dev); -+ -+ return engine; -+} -+EXPORT_SYMBOL(nand_ecc_get_on_host_hw_engine); -+ -+void nand_ecc_put_on_host_hw_engine(struct nand_device *nand) -+{ -+ put_device(nand->ecc.engine->dev); -+} -+EXPORT_SYMBOL(nand_ecc_put_on_host_hw_engine); -+ - MODULE_LICENSE("GPL"); - MODULE_AUTHOR("Miquel Raynal "); - MODULE_DESCRIPTION("Generic ECC engine"); ---- a/include/linux/mtd/nand.h -+++ b/include/linux/mtd/nand.h -@@ -264,11 +264,35 @@ struct nand_ecc_engine_ops { - }; - - /** -+ * enum nand_ecc_engine_integration - How the NAND ECC engine is integrated -+ * @NAND_ECC_ENGINE_INTEGRATION_INVALID: Invalid value -+ * @NAND_ECC_ENGINE_INTEGRATION_PIPELINED: Pipelined engine, performs on-the-fly -+ * correction, does not need to copy -+ * data around -+ * @NAND_ECC_ENGINE_INTEGRATION_EXTERNAL: External engine, needs to bring the -+ * data into its own area before use -+ */ -+enum nand_ecc_engine_integration { -+ NAND_ECC_ENGINE_INTEGRATION_INVALID, -+ NAND_ECC_ENGINE_INTEGRATION_PIPELINED, -+ NAND_ECC_ENGINE_INTEGRATION_EXTERNAL, -+}; -+ -+/** - * struct nand_ecc_engine - ECC engine abstraction for NAND devices -+ * @dev: Host device -+ * @node: Private field for registration time - * @ops: ECC engine operations -+ * @integration: How the engine is integrated with the host -+ * (only relevant on %NAND_ECC_ENGINE_TYPE_ON_HOST engines) -+ * @priv: Private data - */ - struct nand_ecc_engine { -+ struct device *dev; -+ struct list_head node; - struct nand_ecc_engine_ops *ops; -+ enum nand_ecc_engine_integration integration; -+ void *priv; - }; - - void of_get_nand_ecc_user_config(struct nand_device *nand); -@@ -279,8 +303,12 @@ int nand_ecc_prepare_io_req(struct nand_ - int nand_ecc_finish_io_req(struct nand_device *nand, - struct nand_page_io_req *req); - bool nand_ecc_is_strong_enough(struct nand_device *nand); -+int nand_ecc_register_on_host_hw_engine(struct nand_ecc_engine *engine); -+int nand_ecc_unregister_on_host_hw_engine(struct nand_ecc_engine *engine); - struct nand_ecc_engine *nand_ecc_get_sw_engine(struct nand_device *nand); - struct nand_ecc_engine *nand_ecc_get_on_die_hw_engine(struct nand_device *nand); -+struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand); -+void nand_ecc_put_on_host_hw_engine(struct nand_device *nand); - - #if IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING) - struct nand_ecc_engine *nand_ecc_sw_hamming_get_engine(void); diff --git a/target/linux/mediatek/patches-6.1/120-02-v5.18-mtd-nand-Add-a-new-helper-to-retrieve-the-ECC-contex.patch b/target/linux/mediatek/patches-6.1/120-02-v5.18-mtd-nand-Add-a-new-helper-to-retrieve-the-ECC-contex.patch deleted file mode 100644 index 61a39ee0e59..00000000000 --- a/target/linux/mediatek/patches-6.1/120-02-v5.18-mtd-nand-Add-a-new-helper-to-retrieve-the-ECC-contex.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 840b2f8dd2d0579e517140e1f9bbc482eaf4ed07 Mon Sep 17 00:00:00 2001 -From: Miquel Raynal -Date: Thu, 16 Dec 2021 12:16:39 +0100 -Subject: [PATCH 02/15] mtd: nand: Add a new helper to retrieve the ECC context - -Introduce nand_to_ecc_ctx() which will allow to easily jump to the -private pointer of an ECC context given a NAND device. This is very -handy, from the prepare or finish ECC hook, to get the internal context -out of the NAND device object. - -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20211216111654.238086-14-miquel.raynal@bootlin.com -(cherry picked from commit cda32a618debd3fad8e42757b198719ae180f8f4) ---- - include/linux/mtd/nand.h | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/include/linux/mtd/nand.h -+++ b/include/linux/mtd/nand.h -@@ -990,6 +990,11 @@ int nanddev_markbad(struct nand_device * - int nanddev_ecc_engine_init(struct nand_device *nand); - void nanddev_ecc_engine_cleanup(struct nand_device *nand); - -+static inline void *nand_to_ecc_ctx(struct nand_device *nand) -+{ -+ return nand->ecc.ctx.priv; -+} -+ - /* BBT related functions */ - enum nand_bbt_block_status { - NAND_BBT_BLOCK_STATUS_UNKNOWN, diff --git a/target/linux/mediatek/patches-6.1/120-03-v5.18-mtd-nand-ecc-Provide-a-helper-to-retrieve-a-pileline.patch b/target/linux/mediatek/patches-6.1/120-03-v5.18-mtd-nand-ecc-Provide-a-helper-to-retrieve-a-pileline.patch deleted file mode 100644 index 29b62880abd..00000000000 --- a/target/linux/mediatek/patches-6.1/120-03-v5.18-mtd-nand-ecc-Provide-a-helper-to-retrieve-a-pileline.patch +++ /dev/null @@ -1,73 +0,0 @@ -From 784866bc4f9f25e0494b77750f95af2a2619e498 Mon Sep 17 00:00:00 2001 -From: Miquel Raynal -Date: Thu, 16 Dec 2021 12:16:41 +0100 -Subject: [PATCH 03/15] mtd: nand: ecc: Provide a helper to retrieve a - pilelined engine device - -In a pipelined engine situation, we might either have the host which -internally has support for error correction, or have it using an -external hardware block for this purpose. In the former case, the host -is also the ECC engine. In the latter case, it is not. In order to get -the right pointers on the right devices (for example: in order to devm_* -allocate variables), let's introduce this helper which can safely be -called by pipelined ECC engines in order to retrieve the right device -structure. - -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20211216111654.238086-16-miquel.raynal@bootlin.com -(cherry picked from commit 5145abeb0649acf810a32e63bd762e617a9b3309) ---- - drivers/mtd/nand/ecc.c | 31 +++++++++++++++++++++++++++++++ - include/linux/mtd/nand.h | 1 + - 2 files changed, 32 insertions(+) - ---- a/drivers/mtd/nand/ecc.c -+++ b/drivers/mtd/nand/ecc.c -@@ -699,6 +699,37 @@ void nand_ecc_put_on_host_hw_engine(stru - } - EXPORT_SYMBOL(nand_ecc_put_on_host_hw_engine); - -+/* -+ * In the case of a pipelined engine, the device registering the ECC -+ * engine is not necessarily the ECC engine itself but may be a host controller. -+ * It is then useful to provide a helper to retrieve the right device object -+ * which actually represents the ECC engine. -+ */ -+struct device *nand_ecc_get_engine_dev(struct device *host) -+{ -+ struct platform_device *ecc_pdev; -+ struct device_node *np; -+ -+ /* -+ * If the device node contains this property, it means we need to follow -+ * it in order to get the right ECC engine device we are looking for. -+ */ -+ np = of_parse_phandle(host->of_node, "nand-ecc-engine", 0); -+ if (!np) -+ return host; -+ -+ ecc_pdev = of_find_device_by_node(np); -+ if (!ecc_pdev) { -+ of_node_put(np); -+ return NULL; -+ } -+ -+ platform_device_put(ecc_pdev); -+ of_node_put(np); -+ -+ return &ecc_pdev->dev; -+} -+ - MODULE_LICENSE("GPL"); - MODULE_AUTHOR("Miquel Raynal "); - MODULE_DESCRIPTION("Generic ECC engine"); ---- a/include/linux/mtd/nand.h -+++ b/include/linux/mtd/nand.h -@@ -309,6 +309,7 @@ struct nand_ecc_engine *nand_ecc_get_sw_ - struct nand_ecc_engine *nand_ecc_get_on_die_hw_engine(struct nand_device *nand); - struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand); - void nand_ecc_put_on_host_hw_engine(struct nand_device *nand); -+struct device *nand_ecc_get_engine_dev(struct device *host); - - #if IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING) - struct nand_ecc_engine *nand_ecc_sw_hamming_get_engine(void); diff --git a/target/linux/mediatek/patches-6.1/120-04-v5.18-spi-spi-mem-Introduce-a-capability-structure.patch b/target/linux/mediatek/patches-6.1/120-04-v5.18-spi-spi-mem-Introduce-a-capability-structure.patch deleted file mode 100644 index 1e7f572dd66..00000000000 --- a/target/linux/mediatek/patches-6.1/120-04-v5.18-spi-spi-mem-Introduce-a-capability-structure.patch +++ /dev/null @@ -1,71 +0,0 @@ -From 3e45577e70cbf8fdc5c13033114989794a3797d5 Mon Sep 17 00:00:00 2001 -From: Miquel Raynal -Date: Thu, 27 Jan 2022 10:17:56 +0100 -Subject: [PATCH 04/15] spi: spi-mem: Introduce a capability structure - -Create a spi_controller_mem_caps structure and put it within the -spi_controller structure close to the spi_controller_mem_ops -strucure. So far the only field in this structure is the support for dtr -operations, but soon we will add another parameter. - -Also create a helper to parse the capabilities and check if the -requested capability has been set or not. - -Signed-off-by: Miquel Raynal -Reviewed-by: Pratyush Yadav -Reviewed-by: Boris Brezillon -Reviewed-by: Tudor Ambarus -Reviewed-by: Mark Brown -Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-2-miquel.raynal@bootlin.com -(cherry picked from commit 4a3cc7fb6e63bcfdedec25364738f1493345bd20) ---- - include/linux/spi/spi-mem.h | 11 +++++++++++ - include/linux/spi/spi.h | 3 +++ - 2 files changed, 14 insertions(+) - ---- a/include/linux/spi/spi-mem.h -+++ b/include/linux/spi/spi-mem.h -@@ -286,6 +286,17 @@ struct spi_controller_mem_ops { - }; - - /** -+ * struct spi_controller_mem_caps - SPI memory controller capabilities -+ * @dtr: Supports DTR operations -+ */ -+struct spi_controller_mem_caps { -+ bool dtr; -+}; -+ -+#define spi_mem_controller_is_capable(ctlr, cap) \ -+ ((ctlr)->mem_caps && (ctlr)->mem_caps->cap) -+ -+/** - * struct spi_mem_driver - SPI memory driver - * @spidrv: inherit from a SPI driver - * @probe: probe a SPI memory. Usually where detection/initialization takes ---- a/include/linux/spi/spi.h -+++ b/include/linux/spi/spi.h -@@ -23,6 +23,7 @@ struct software_node; - struct spi_controller; - struct spi_transfer; - struct spi_controller_mem_ops; -+struct spi_controller_mem_caps; - - /* - * INTERFACES between SPI master-side drivers and SPI slave protocol handlers, -@@ -419,6 +420,7 @@ extern struct spi_device *spi_new_ancill - * @mem_ops: optimized/dedicated operations for interactions with SPI memory. - * This field is optional and should only be implemented if the - * controller has native support for memory like operations. -+ * @mem_caps: controller capabilities for the handling of memory operations. - * @unprepare_message: undo any work done by prepare_message(). - * @slave_abort: abort the ongoing transfer request on an SPI slave controller - * @cs_gpios: LEGACY: array of GPIO descs to use as chip select lines; one per -@@ -643,6 +645,7 @@ struct spi_controller { - - /* Optimized handlers for SPI memory-like operations. */ - const struct spi_controller_mem_ops *mem_ops; -+ const struct spi_controller_mem_caps *mem_caps; - - /* gpio chip select */ - int *cs_gpios; diff --git a/target/linux/mediatek/patches-6.1/120-05-v5.18-spi-spi-mem-Check-the-controller-extra-capabilities.patch b/target/linux/mediatek/patches-6.1/120-05-v5.18-spi-spi-mem-Check-the-controller-extra-capabilities.patch deleted file mode 100644 index 9f01fdb8353..00000000000 --- a/target/linux/mediatek/patches-6.1/120-05-v5.18-spi-spi-mem-Check-the-controller-extra-capabilities.patch +++ /dev/null @@ -1,51 +0,0 @@ -From c9cae7e1e5c87d0aa76b7bededa5191a0c8cf25a Mon Sep 17 00:00:00 2001 -From: Miquel Raynal -Date: Thu, 27 Jan 2022 10:17:57 +0100 -Subject: [PATCH 05/15] spi: spi-mem: Check the controller extra capabilities - -Controllers can now provide a spi-mem capabilities structure. Let's make -use of it in spi_mem_controller_default_supports_op(). As we want to -check for DTR operations as well as normal operations in a single -helper, let's pull the necessary checks from spi_mem_dtr_supports_op() -for now. - -However, because no controller provide these extra capabilities, this -change has no effect so far. - -Signed-off-by: Miquel Raynal -Reviewed-by: Pratyush Yadav -Reviewed-by: Boris Brezillon -Reviewed-by: Tudor Ambarus -Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-3-miquel.raynal@bootlin.com -(cherry picked from commit cb7e96ee81edaa48c67d84c14df2cbe464391c37) ---- - drivers/spi/spi-mem.c | 17 +++++++++++++---- - 1 file changed, 13 insertions(+), 4 deletions(-) - ---- a/drivers/spi/spi-mem.c -+++ b/drivers/spi/spi-mem.c -@@ -173,11 +173,20 @@ EXPORT_SYMBOL_GPL(spi_mem_dtr_supports_o - bool spi_mem_default_supports_op(struct spi_mem *mem, - const struct spi_mem_op *op) - { -- if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr) -- return false; -+ struct spi_controller *ctlr = mem->spi->controller; -+ bool op_is_dtr = -+ op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr; - -- if (op->cmd.nbytes != 1) -- return false; -+ if (op_is_dtr) { -+ if (!spi_mem_controller_is_capable(ctlr, dtr)) -+ return false; -+ -+ if (op->cmd.nbytes != 2) -+ return false; -+ } else { -+ if (op->cmd.nbytes != 1) -+ return false; -+ } - - return spi_mem_check_buswidth(mem, op); - } diff --git a/target/linux/mediatek/patches-6.1/120-06-v5.18-spi-spi-mem-Kill-the-spi_mem_dtr_supports_op-helper.patch b/target/linux/mediatek/patches-6.1/120-06-v5.18-spi-spi-mem-Kill-the-spi_mem_dtr_supports_op-helper.patch deleted file mode 100644 index c313a455b60..00000000000 --- a/target/linux/mediatek/patches-6.1/120-06-v5.18-spi-spi-mem-Kill-the-spi_mem_dtr_supports_op-helper.patch +++ /dev/null @@ -1,111 +0,0 @@ -From 2e5fba82e4aeb72d71230eef2541881615aaf7cf Mon Sep 17 00:00:00 2001 -From: Miquel Raynal -Date: Thu, 27 Jan 2022 10:18:00 +0100 -Subject: [PATCH 06/15] spi: spi-mem: Kill the spi_mem_dtr_supports_op() helper - -Now that spi_mem_default_supports_op() has access to the static -controller capabilities (relating to memory operations), and now that -these capabilities have been filled by the relevant controllers, there -is no need for a specific helper checking only DTR operations, so let's -just kill spi_mem_dtr_supports_op() and simply use -spi_mem_default_supports_op() instead. - -Signed-off-by: Miquel Raynal -Reviewed-by: Pratyush Yadav -Reviewed-by: Boris Brezillon -Reviewed-by: Tudor Ambarus -Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-6-miquel.raynal@bootlin.com -(cherry picked from commit 9a15efc5d5e6b5beaed0883e5bdcd0b1384c1b20) ---- - drivers/spi/spi-cadence-quadspi.c | 5 +---- - drivers/spi/spi-mem.c | 10 ---------- - drivers/spi/spi-mxic.c | 10 +--------- - include/linux/spi/spi-mem.h | 11 ----------- - 4 files changed, 2 insertions(+), 34 deletions(-) - ---- a/drivers/spi/spi-cadence-quadspi.c -+++ b/drivers/spi/spi-cadence-quadspi.c -@@ -1249,10 +1249,7 @@ static bool cqspi_supports_mem_op(struct - return false; - } - -- if (all_true) -- return spi_mem_dtr_supports_op(mem, op); -- else -- return spi_mem_default_supports_op(mem, op); -+ return spi_mem_default_supports_op(mem, op); - } - - static int cqspi_of_get_flash_pdata(struct platform_device *pdev, ---- a/drivers/spi/spi-mem.c -+++ b/drivers/spi/spi-mem.c -@@ -160,16 +160,6 @@ static bool spi_mem_check_buswidth(struc - return true; - } - --bool spi_mem_dtr_supports_op(struct spi_mem *mem, -- const struct spi_mem_op *op) --{ -- if (op->cmd.nbytes != 2) -- return false; -- -- return spi_mem_check_buswidth(mem, op); --} --EXPORT_SYMBOL_GPL(spi_mem_dtr_supports_op); -- - bool spi_mem_default_supports_op(struct spi_mem *mem, - const struct spi_mem_op *op) - { ---- a/drivers/spi/spi-mxic.c -+++ b/drivers/spi/spi-mxic.c -@@ -331,8 +331,6 @@ static int mxic_spi_data_xfer(struct mxi - static bool mxic_spi_mem_supports_op(struct spi_mem *mem, - const struct spi_mem_op *op) - { -- bool all_false; -- - if (op->data.buswidth > 8 || op->addr.buswidth > 8 || - op->dummy.buswidth > 8 || op->cmd.buswidth > 8) - return false; -@@ -344,13 +342,7 @@ static bool mxic_spi_mem_supports_op(str - if (op->addr.nbytes > 7) - return false; - -- all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr && -- !op->data.dtr; -- -- if (all_false) -- return spi_mem_default_supports_op(mem, op); -- else -- return spi_mem_dtr_supports_op(mem, op); -+ return spi_mem_default_supports_op(mem, op); - } - - static int mxic_spi_mem_exec_op(struct spi_mem *mem, ---- a/include/linux/spi/spi-mem.h -+++ b/include/linux/spi/spi-mem.h -@@ -330,10 +330,6 @@ void spi_controller_dma_unmap_mem_op_dat - - bool spi_mem_default_supports_op(struct spi_mem *mem, - const struct spi_mem_op *op); -- --bool spi_mem_dtr_supports_op(struct spi_mem *mem, -- const struct spi_mem_op *op); -- - #else - static inline int - spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr, -@@ -356,13 +352,6 @@ bool spi_mem_default_supports_op(struct - { - return false; - } -- --static inline --bool spi_mem_dtr_supports_op(struct spi_mem *mem, -- const struct spi_mem_op *op) --{ -- return false; --} - #endif /* CONFIG_SPI_MEM */ - - int spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op); diff --git a/target/linux/mediatek/patches-6.1/120-07-v5.18-spi-spi-mem-Add-an-ecc-parameter-to-the-spi_mem_op-s.patch b/target/linux/mediatek/patches-6.1/120-07-v5.18-spi-spi-mem-Add-an-ecc-parameter-to-the-spi_mem_op-s.patch deleted file mode 100644 index 6d7e47650b2..00000000000 --- a/target/linux/mediatek/patches-6.1/120-07-v5.18-spi-spi-mem-Add-an-ecc-parameter-to-the-spi_mem_op-s.patch +++ /dev/null @@ -1,72 +0,0 @@ -From 9e7eb0ea442ecb1c3fe443289e288694f10c5148 Mon Sep 17 00:00:00 2001 -From: Miquel Raynal -Date: Thu, 27 Jan 2022 10:18:01 +0100 -Subject: [PATCH 07/15] spi: spi-mem: Add an ecc parameter to the spi_mem_op - structure - -Soon the SPI-NAND core will need a way to request a SPI controller to -enable ECC support for a given operation. This is because of the -pipelined integration of certain ECC engines, which are directly managed -by the SPI controller itself. - -Introduce a spi_mem_op additional field for this purpose: ecc. - -So far this field is left unset and checked to be false by all -the SPI controller drivers in their ->supports_op() hook, as they all -call spi_mem_default_supports_op(). - -Signed-off-by: Miquel Raynal -Acked-by: Pratyush Yadav -Reviewed-by: Boris Brezillon -Reviewed-by: Tudor Ambarus -Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-7-miquel.raynal@bootlin.com -(cherry picked from commit a433c2cbd75ab76f277364f44e76f32c7df306e7) ---- - drivers/spi/spi-mem.c | 5 +++++ - include/linux/spi/spi-mem.h | 4 ++++ - 2 files changed, 9 insertions(+) - ---- a/drivers/spi/spi-mem.c -+++ b/drivers/spi/spi-mem.c -@@ -178,6 +178,11 @@ bool spi_mem_default_supports_op(struct - return false; - } - -+ if (op->data.ecc) { -+ if (!spi_mem_controller_is_capable(ctlr, ecc)) -+ return false; -+ } -+ - return spi_mem_check_buswidth(mem, op); - } - EXPORT_SYMBOL_GPL(spi_mem_default_supports_op); ---- a/include/linux/spi/spi-mem.h -+++ b/include/linux/spi/spi-mem.h -@@ -89,6 +89,7 @@ enum spi_mem_data_dir { - * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not - * @data.buswidth: number of IO lanes used to send/receive the data - * @data.dtr: whether the data should be sent in DTR mode or not -+ * @data.ecc: whether error correction is required or not - * @data.dir: direction of the transfer - * @data.nbytes: number of data bytes to send/receive. Can be zero if the - * operation does not involve transferring data -@@ -119,6 +120,7 @@ struct spi_mem_op { - struct { - u8 buswidth; - u8 dtr : 1; -+ u8 ecc : 1; - enum spi_mem_data_dir dir; - unsigned int nbytes; - union { -@@ -288,9 +290,11 @@ struct spi_controller_mem_ops { - /** - * struct spi_controller_mem_caps - SPI memory controller capabilities - * @dtr: Supports DTR operations -+ * @ecc: Supports operations with error correction - */ - struct spi_controller_mem_caps { - bool dtr; -+ bool ecc; - }; - - #define spi_mem_controller_is_capable(ctlr, cap) \ diff --git a/target/linux/mediatek/patches-6.1/120-08-v5.18-mtd-spinand-Delay-a-little-bit-the-dirmap-creation.patch b/target/linux/mediatek/patches-6.1/120-08-v5.18-mtd-spinand-Delay-a-little-bit-the-dirmap-creation.patch deleted file mode 100644 index 87c7b7cd297..00000000000 --- a/target/linux/mediatek/patches-6.1/120-08-v5.18-mtd-spinand-Delay-a-little-bit-the-dirmap-creation.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 94ef3c35b935a63f6c156957c92f6cf33c9a8dae Mon Sep 17 00:00:00 2001 -From: Miquel Raynal -Date: Thu, 27 Jan 2022 10:18:02 +0100 -Subject: [PATCH 08/15] mtd: spinand: Delay a little bit the dirmap creation - -As we will soon tweak the dirmap creation to act a little bit -differently depending on the picked ECC engine, we need to initialize -dirmaps after ECC engines. This should not have any effect as dirmaps -are not yet used at this point. - -Signed-off-by: Miquel Raynal -Reviewed-by: Boris Brezillon -Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-8-miquel.raynal@bootlin.com -(cherry picked from commit dc4c2cbf0be2d4a8e2a65013ea2815bb2c8ba949) ---- - drivers/mtd/nand/spi/core.c | 16 ++++++++-------- - 1 file changed, 8 insertions(+), 8 deletions(-) - ---- a/drivers/mtd/nand/spi/core.c -+++ b/drivers/mtd/nand/spi/core.c -@@ -1221,14 +1221,6 @@ static int spinand_init(struct spinand_d - if (ret) - goto err_free_bufs; - -- ret = spinand_create_dirmaps(spinand); -- if (ret) { -- dev_err(dev, -- "Failed to create direct mappings for read/write operations (err = %d)\n", -- ret); -- goto err_manuf_cleanup; -- } -- - ret = nanddev_init(nand, &spinand_ops, THIS_MODULE); - if (ret) - goto err_manuf_cleanup; -@@ -1263,6 +1255,14 @@ static int spinand_init(struct spinand_d - mtd->ecc_strength = nanddev_get_ecc_conf(nand)->strength; - mtd->ecc_step_size = nanddev_get_ecc_conf(nand)->step_size; - -+ ret = spinand_create_dirmaps(spinand); -+ if (ret) { -+ dev_err(dev, -+ "Failed to create direct mappings for read/write operations (err = %d)\n", -+ ret); -+ goto err_cleanup_ecc_engine; -+ } -+ - return 0; - - err_cleanup_ecc_engine: diff --git a/target/linux/mediatek/patches-6.1/120-09-v5.18-mtd-spinand-Create-direct-mapping-descriptors-for-EC.patch b/target/linux/mediatek/patches-6.1/120-09-v5.18-mtd-spinand-Create-direct-mapping-descriptors-for-EC.patch deleted file mode 100644 index 35912cd2cd6..00000000000 --- a/target/linux/mediatek/patches-6.1/120-09-v5.18-mtd-spinand-Create-direct-mapping-descriptors-for-EC.patch +++ /dev/null @@ -1,98 +0,0 @@ -From eb4a2d282c3c5752211d69be6dff2674119e5583 Mon Sep 17 00:00:00 2001 -From: Miquel Raynal -Date: Thu, 27 Jan 2022 10:18:03 +0100 -Subject: [PATCH 09/15] mtd: spinand: Create direct mapping descriptors for ECC - operations - -In order for pipelined ECC engines to be able to enable/disable the ECC -engine only when needed and avoid races when future parallel-operations -will be supported, we need to provide the information about the use of -the ECC engine in the direct mapping hooks. As direct mapping -configurations are meant to be static, it is best to create two new -mappings: one for regular 'raw' accesses and one for accesses involving -correction. It is up to the driver to use or not the new ECC enable -boolean contained in the spi-mem operation. - -As dirmaps are not free (they consume a few pages of MMIO address space) -and because these extra entries are only meant to be used by pipelined -engines, let's limit their use to this specific type of engine and save -a bit of memory with all the other setups. - -Signed-off-by: Miquel Raynal -Reviewed-by: Boris Brezillon -Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-9-miquel.raynal@bootlin.com -(cherry picked from commit f9d7c7265bcff7d9a17425a8cddf702e8fe159c2) ---- - drivers/mtd/nand/spi/core.c | 35 +++++++++++++++++++++++++++++++++-- - include/linux/mtd/spinand.h | 2 ++ - 2 files changed, 35 insertions(+), 2 deletions(-) - ---- a/drivers/mtd/nand/spi/core.c -+++ b/drivers/mtd/nand/spi/core.c -@@ -381,7 +381,10 @@ static int spinand_read_from_cache_op(st - } - } - -- rdesc = spinand->dirmaps[req->pos.plane].rdesc; -+ if (req->mode == MTD_OPS_RAW) -+ rdesc = spinand->dirmaps[req->pos.plane].rdesc; -+ else -+ rdesc = spinand->dirmaps[req->pos.plane].rdesc_ecc; - - while (nbytes) { - ret = spi_mem_dirmap_read(rdesc, column, nbytes, buf); -@@ -452,7 +455,10 @@ static int spinand_write_to_cache_op(str - req->ooblen); - } - -- wdesc = spinand->dirmaps[req->pos.plane].wdesc; -+ if (req->mode == MTD_OPS_RAW) -+ wdesc = spinand->dirmaps[req->pos.plane].wdesc; -+ else -+ wdesc = spinand->dirmaps[req->pos.plane].wdesc_ecc; - - while (nbytes) { - ret = spi_mem_dirmap_write(wdesc, column, nbytes, buf); -@@ -875,6 +881,31 @@ static int spinand_create_dirmap(struct - - spinand->dirmaps[plane].rdesc = desc; - -+ if (nand->ecc.engine->integration != NAND_ECC_ENGINE_INTEGRATION_PIPELINED) { -+ spinand->dirmaps[plane].wdesc_ecc = spinand->dirmaps[plane].wdesc; -+ spinand->dirmaps[plane].rdesc_ecc = spinand->dirmaps[plane].rdesc; -+ -+ return 0; -+ } -+ -+ info.op_tmpl = *spinand->op_templates.update_cache; -+ info.op_tmpl.data.ecc = true; -+ desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev, -+ spinand->spimem, &info); -+ if (IS_ERR(desc)) -+ return PTR_ERR(desc); -+ -+ spinand->dirmaps[plane].wdesc_ecc = desc; -+ -+ info.op_tmpl = *spinand->op_templates.read_cache; -+ info.op_tmpl.data.ecc = true; -+ desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev, -+ spinand->spimem, &info); -+ if (IS_ERR(desc)) -+ return PTR_ERR(desc); -+ -+ spinand->dirmaps[plane].rdesc_ecc = desc; -+ - return 0; - } - ---- a/include/linux/mtd/spinand.h -+++ b/include/linux/mtd/spinand.h -@@ -392,6 +392,8 @@ struct spinand_info { - struct spinand_dirmap { - struct spi_mem_dirmap_desc *wdesc; - struct spi_mem_dirmap_desc *rdesc; -+ struct spi_mem_dirmap_desc *wdesc_ecc; -+ struct spi_mem_dirmap_desc *rdesc_ecc; - }; - - /** diff --git a/target/linux/mediatek/patches-6.1/120-11-v5.19-mtd-nand-make-mtk_ecc.c-a-separated-module.patch b/target/linux/mediatek/patches-6.1/120-11-v5.19-mtd-nand-make-mtk_ecc.c-a-separated-module.patch deleted file mode 100644 index fd9098eae96..00000000000 --- a/target/linux/mediatek/patches-6.1/120-11-v5.19-mtd-nand-make-mtk_ecc.c-a-separated-module.patch +++ /dev/null @@ -1,1383 +0,0 @@ -From ebb9653d4a87c64fb679e4c339e867556dada719 Mon Sep 17 00:00:00 2001 -From: Chuanhong Guo -Date: Tue, 22 Mar 2022 18:44:21 +0800 -Subject: [PATCH 11/15] mtd: nand: make mtk_ecc.c a separated module - -this code will be used in mediatek snfi spi-mem controller with -pipelined ECC engine. - -Signed-off-by: Chuanhong Guo -(cherry picked from commit 316f47cec4ce5b81aa8006de202d8769c117a52d) ---- - drivers/mtd/nand/Kconfig | 7 +++++++ - drivers/mtd/nand/Makefile | 1 + - drivers/mtd/nand/{raw/mtk_ecc.c => ecc-mtk.c} | 3 +-- - drivers/mtd/nand/raw/Kconfig | 1 + - drivers/mtd/nand/raw/Makefile | 2 +- - drivers/mtd/nand/raw/mtk_nand.c | 2 +- - .../nand/raw/mtk_ecc.h => include/linux/mtd/nand-ecc-mtk.h | 0 - 7 files changed, 12 insertions(+), 4 deletions(-) - rename drivers/mtd/nand/{raw/mtk_ecc.c => ecc-mtk.c} (99%) - rename drivers/mtd/nand/raw/mtk_ecc.h => include/linux/mtd/nand-ecc-mtk.h (100%) - ---- a/drivers/mtd/nand/Kconfig -+++ b/drivers/mtd/nand/Kconfig -@@ -50,6 +50,13 @@ config MTD_NAND_MTK_BMT - bool "Support MediaTek NAND Bad-block Management Table" - default n - -+config MTD_NAND_ECC_MEDIATEK -+ tristate "Mediatek hardware ECC engine" -+ depends on HAS_IOMEM -+ select MTD_NAND_ECC -+ help -+ This enables support for the hardware ECC engine from Mediatek. -+ - endmenu - - endmenu ---- a/drivers/mtd/nand/Makefile -+++ b/drivers/mtd/nand/Makefile -@@ -3,6 +3,7 @@ - nandcore-objs := core.o bbt.o - obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o - obj-$(CONFIG_MTD_NAND_MTK_BMT) += mtk_bmt.o mtk_bmt_v2.o mtk_bmt_bbt.o mtk_bmt_nmbm.o -+obj-$(CONFIG_MTD_NAND_ECC_MEDIATEK) += ecc-mtk.o - - obj-y += onenand/ - obj-y += raw/ ---- a/drivers/mtd/nand/raw/mtk_ecc.c -+++ /dev/null -@@ -1,599 +0,0 @@ --// SPDX-License-Identifier: GPL-2.0 OR MIT --/* -- * MTK ECC controller driver. -- * Copyright (C) 2016 MediaTek Inc. -- * Authors: Xiaolei Li -- * Jorge Ramirez-Ortiz -- */ -- --#include --#include --#include --#include --#include --#include --#include --#include --#include -- --#include "mtk_ecc.h" -- --#define ECC_IDLE_MASK BIT(0) --#define ECC_IRQ_EN BIT(0) --#define ECC_PG_IRQ_SEL BIT(1) --#define ECC_OP_ENABLE (1) --#define ECC_OP_DISABLE (0) -- --#define ECC_ENCCON (0x00) --#define ECC_ENCCNFG (0x04) --#define ECC_MS_SHIFT (16) --#define ECC_ENCDIADDR (0x08) --#define ECC_ENCIDLE (0x0C) --#define ECC_DECCON (0x100) --#define ECC_DECCNFG (0x104) --#define DEC_EMPTY_EN BIT(31) --#define DEC_CNFG_CORRECT (0x3 << 12) --#define ECC_DECIDLE (0x10C) --#define ECC_DECENUM0 (0x114) -- --#define ECC_TIMEOUT (500000) -- --#define ECC_IDLE_REG(op) ((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE) --#define ECC_CTL_REG(op) ((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON) -- --struct mtk_ecc_caps { -- u32 err_mask; -- u32 err_shift; -- const u8 *ecc_strength; -- const u32 *ecc_regs; -- u8 num_ecc_strength; -- u8 ecc_mode_shift; -- u32 parity_bits; -- int pg_irq_sel; --}; -- --struct mtk_ecc { -- struct device *dev; -- const struct mtk_ecc_caps *caps; -- void __iomem *regs; -- struct clk *clk; -- -- struct completion done; -- struct mutex lock; -- u32 sectors; -- -- u8 *eccdata; --}; -- --/* ecc strength that each IP supports */ --static const u8 ecc_strength_mt2701[] = { -- 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, -- 40, 44, 48, 52, 56, 60 --}; -- --static const u8 ecc_strength_mt2712[] = { -- 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, -- 40, 44, 48, 52, 56, 60, 68, 72, 80 --}; -- --static const u8 ecc_strength_mt7622[] = { -- 4, 6, 8, 10, 12 --}; -- --enum mtk_ecc_regs { -- ECC_ENCPAR00, -- ECC_ENCIRQ_EN, -- ECC_ENCIRQ_STA, -- ECC_DECDONE, -- ECC_DECIRQ_EN, -- ECC_DECIRQ_STA, --}; -- --static int mt2701_ecc_regs[] = { -- [ECC_ENCPAR00] = 0x10, -- [ECC_ENCIRQ_EN] = 0x80, -- [ECC_ENCIRQ_STA] = 0x84, -- [ECC_DECDONE] = 0x124, -- [ECC_DECIRQ_EN] = 0x200, -- [ECC_DECIRQ_STA] = 0x204, --}; -- --static int mt2712_ecc_regs[] = { -- [ECC_ENCPAR00] = 0x300, -- [ECC_ENCIRQ_EN] = 0x80, -- [ECC_ENCIRQ_STA] = 0x84, -- [ECC_DECDONE] = 0x124, -- [ECC_DECIRQ_EN] = 0x200, -- [ECC_DECIRQ_STA] = 0x204, --}; -- --static int mt7622_ecc_regs[] = { -- [ECC_ENCPAR00] = 0x10, -- [ECC_ENCIRQ_EN] = 0x30, -- [ECC_ENCIRQ_STA] = 0x34, -- [ECC_DECDONE] = 0x11c, -- [ECC_DECIRQ_EN] = 0x140, -- [ECC_DECIRQ_STA] = 0x144, --}; -- --static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc, -- enum mtk_ecc_operation op) --{ -- struct device *dev = ecc->dev; -- u32 val; -- int ret; -- -- ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val, -- val & ECC_IDLE_MASK, -- 10, ECC_TIMEOUT); -- if (ret) -- dev_warn(dev, "%s NOT idle\n", -- op == ECC_ENCODE ? "encoder" : "decoder"); --} -- --static irqreturn_t mtk_ecc_irq(int irq, void *id) --{ -- struct mtk_ecc *ecc = id; -- u32 dec, enc; -- -- dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]) -- & ECC_IRQ_EN; -- if (dec) { -- dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]); -- if (dec & ecc->sectors) { -- /* -- * Clear decode IRQ status once again to ensure that -- * there will be no extra IRQ. -- */ -- readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]); -- ecc->sectors = 0; -- complete(&ecc->done); -- } else { -- return IRQ_HANDLED; -- } -- } else { -- enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA]) -- & ECC_IRQ_EN; -- if (enc) -- complete(&ecc->done); -- else -- return IRQ_NONE; -- } -- -- return IRQ_HANDLED; --} -- --static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config) --{ -- u32 ecc_bit, dec_sz, enc_sz; -- u32 reg, i; -- -- for (i = 0; i < ecc->caps->num_ecc_strength; i++) { -- if (ecc->caps->ecc_strength[i] == config->strength) -- break; -- } -- -- if (i == ecc->caps->num_ecc_strength) { -- dev_err(ecc->dev, "invalid ecc strength %d\n", -- config->strength); -- return -EINVAL; -- } -- -- ecc_bit = i; -- -- if (config->op == ECC_ENCODE) { -- /* configure ECC encoder (in bits) */ -- enc_sz = config->len << 3; -- -- reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift); -- reg |= (enc_sz << ECC_MS_SHIFT); -- writel(reg, ecc->regs + ECC_ENCCNFG); -- -- if (config->mode != ECC_NFI_MODE) -- writel(lower_32_bits(config->addr), -- ecc->regs + ECC_ENCDIADDR); -- -- } else { -- /* configure ECC decoder (in bits) */ -- dec_sz = (config->len << 3) + -- config->strength * ecc->caps->parity_bits; -- -- reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift); -- reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT; -- reg |= DEC_EMPTY_EN; -- writel(reg, ecc->regs + ECC_DECCNFG); -- -- if (config->sectors) -- ecc->sectors = 1 << (config->sectors - 1); -- } -- -- return 0; --} -- --void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats, -- int sectors) --{ -- u32 offset, i, err; -- u32 bitflips = 0; -- -- stats->corrected = 0; -- stats->failed = 0; -- -- for (i = 0; i < sectors; i++) { -- offset = (i >> 2) << 2; -- err = readl(ecc->regs + ECC_DECENUM0 + offset); -- err = err >> ((i % 4) * ecc->caps->err_shift); -- err &= ecc->caps->err_mask; -- if (err == ecc->caps->err_mask) { -- /* uncorrectable errors */ -- stats->failed++; -- continue; -- } -- -- stats->corrected += err; -- bitflips = max_t(u32, bitflips, err); -- } -- -- stats->bitflips = bitflips; --} --EXPORT_SYMBOL(mtk_ecc_get_stats); -- --void mtk_ecc_release(struct mtk_ecc *ecc) --{ -- clk_disable_unprepare(ecc->clk); -- put_device(ecc->dev); --} --EXPORT_SYMBOL(mtk_ecc_release); -- --static void mtk_ecc_hw_init(struct mtk_ecc *ecc) --{ -- mtk_ecc_wait_idle(ecc, ECC_ENCODE); -- writew(ECC_OP_DISABLE, ecc->regs + ECC_ENCCON); -- -- mtk_ecc_wait_idle(ecc, ECC_DECODE); -- writel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON); --} -- --static struct mtk_ecc *mtk_ecc_get(struct device_node *np) --{ -- struct platform_device *pdev; -- struct mtk_ecc *ecc; -- -- pdev = of_find_device_by_node(np); -- if (!pdev) -- return ERR_PTR(-EPROBE_DEFER); -- -- ecc = platform_get_drvdata(pdev); -- if (!ecc) { -- put_device(&pdev->dev); -- return ERR_PTR(-EPROBE_DEFER); -- } -- -- clk_prepare_enable(ecc->clk); -- mtk_ecc_hw_init(ecc); -- -- return ecc; --} -- --struct mtk_ecc *of_mtk_ecc_get(struct device_node *of_node) --{ -- struct mtk_ecc *ecc = NULL; -- struct device_node *np; -- -- np = of_parse_phandle(of_node, "ecc-engine", 0); -- if (np) { -- ecc = mtk_ecc_get(np); -- of_node_put(np); -- } -- -- return ecc; --} --EXPORT_SYMBOL(of_mtk_ecc_get); -- --int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config) --{ -- enum mtk_ecc_operation op = config->op; -- u16 reg_val; -- int ret; -- -- ret = mutex_lock_interruptible(&ecc->lock); -- if (ret) { -- dev_err(ecc->dev, "interrupted when attempting to lock\n"); -- return ret; -- } -- -- mtk_ecc_wait_idle(ecc, op); -- -- ret = mtk_ecc_config(ecc, config); -- if (ret) { -- mutex_unlock(&ecc->lock); -- return ret; -- } -- -- if (config->mode != ECC_NFI_MODE || op != ECC_ENCODE) { -- init_completion(&ecc->done); -- reg_val = ECC_IRQ_EN; -- /* -- * For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it -- * means this chip can only generate one ecc irq during page -- * read / write. If is 0, generate one ecc irq each ecc step. -- */ -- if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE) -- reg_val |= ECC_PG_IRQ_SEL; -- if (op == ECC_ENCODE) -- writew(reg_val, ecc->regs + -- ecc->caps->ecc_regs[ECC_ENCIRQ_EN]); -- else -- writew(reg_val, ecc->regs + -- ecc->caps->ecc_regs[ECC_DECIRQ_EN]); -- } -- -- writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op)); -- -- return 0; --} --EXPORT_SYMBOL(mtk_ecc_enable); -- --void mtk_ecc_disable(struct mtk_ecc *ecc) --{ -- enum mtk_ecc_operation op = ECC_ENCODE; -- -- /* find out the running operation */ -- if (readw(ecc->regs + ECC_CTL_REG(op)) != ECC_OP_ENABLE) -- op = ECC_DECODE; -- -- /* disable it */ -- mtk_ecc_wait_idle(ecc, op); -- if (op == ECC_DECODE) { -- /* -- * Clear decode IRQ status in case there is a timeout to wait -- * decode IRQ. -- */ -- readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]); -- writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]); -- } else { -- writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]); -- } -- -- writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op)); -- -- mutex_unlock(&ecc->lock); --} --EXPORT_SYMBOL(mtk_ecc_disable); -- --int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op) --{ -- int ret; -- -- ret = wait_for_completion_timeout(&ecc->done, msecs_to_jiffies(500)); -- if (!ret) { -- dev_err(ecc->dev, "%s timeout - interrupt did not arrive)\n", -- (op == ECC_ENCODE) ? "encoder" : "decoder"); -- return -ETIMEDOUT; -- } -- -- return 0; --} --EXPORT_SYMBOL(mtk_ecc_wait_done); -- --int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config, -- u8 *data, u32 bytes) --{ -- dma_addr_t addr; -- u32 len; -- int ret; -- -- addr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE); -- ret = dma_mapping_error(ecc->dev, addr); -- if (ret) { -- dev_err(ecc->dev, "dma mapping error\n"); -- return -EINVAL; -- } -- -- config->op = ECC_ENCODE; -- config->addr = addr; -- ret = mtk_ecc_enable(ecc, config); -- if (ret) { -- dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE); -- return ret; -- } -- -- ret = mtk_ecc_wait_done(ecc, ECC_ENCODE); -- if (ret) -- goto timeout; -- -- mtk_ecc_wait_idle(ecc, ECC_ENCODE); -- -- /* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */ -- len = (config->strength * ecc->caps->parity_bits + 7) >> 3; -- -- /* write the parity bytes generated by the ECC back to temp buffer */ -- __ioread32_copy(ecc->eccdata, -- ecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00], -- round_up(len, 4)); -- -- /* copy into possibly unaligned OOB region with actual length */ -- memcpy(data + bytes, ecc->eccdata, len); --timeout: -- -- dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE); -- mtk_ecc_disable(ecc); -- -- return ret; --} --EXPORT_SYMBOL(mtk_ecc_encode); -- --void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p) --{ -- const u8 *ecc_strength = ecc->caps->ecc_strength; -- int i; -- -- for (i = 0; i < ecc->caps->num_ecc_strength; i++) { -- if (*p <= ecc_strength[i]) { -- if (!i) -- *p = ecc_strength[i]; -- else if (*p != ecc_strength[i]) -- *p = ecc_strength[i - 1]; -- return; -- } -- } -- -- *p = ecc_strength[ecc->caps->num_ecc_strength - 1]; --} --EXPORT_SYMBOL(mtk_ecc_adjust_strength); -- --unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc) --{ -- return ecc->caps->parity_bits; --} --EXPORT_SYMBOL(mtk_ecc_get_parity_bits); -- --static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = { -- .err_mask = 0x3f, -- .err_shift = 8, -- .ecc_strength = ecc_strength_mt2701, -- .ecc_regs = mt2701_ecc_regs, -- .num_ecc_strength = 20, -- .ecc_mode_shift = 5, -- .parity_bits = 14, -- .pg_irq_sel = 0, --}; -- --static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = { -- .err_mask = 0x7f, -- .err_shift = 8, -- .ecc_strength = ecc_strength_mt2712, -- .ecc_regs = mt2712_ecc_regs, -- .num_ecc_strength = 23, -- .ecc_mode_shift = 5, -- .parity_bits = 14, -- .pg_irq_sel = 1, --}; -- --static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = { -- .err_mask = 0x1f, -- .err_shift = 5, -- .ecc_strength = ecc_strength_mt7622, -- .ecc_regs = mt7622_ecc_regs, -- .num_ecc_strength = 5, -- .ecc_mode_shift = 4, -- .parity_bits = 13, -- .pg_irq_sel = 0, --}; -- --static const struct of_device_id mtk_ecc_dt_match[] = { -- { -- .compatible = "mediatek,mt2701-ecc", -- .data = &mtk_ecc_caps_mt2701, -- }, { -- .compatible = "mediatek,mt2712-ecc", -- .data = &mtk_ecc_caps_mt2712, -- }, { -- .compatible = "mediatek,mt7622-ecc", -- .data = &mtk_ecc_caps_mt7622, -- }, -- {}, --}; -- --static int mtk_ecc_probe(struct platform_device *pdev) --{ -- struct device *dev = &pdev->dev; -- struct mtk_ecc *ecc; -- struct resource *res; -- u32 max_eccdata_size; -- int irq, ret; -- -- ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL); -- if (!ecc) -- return -ENOMEM; -- -- ecc->caps = of_device_get_match_data(dev); -- -- max_eccdata_size = ecc->caps->num_ecc_strength - 1; -- max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size]; -- max_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3; -- max_eccdata_size = round_up(max_eccdata_size, 4); -- ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL); -- if (!ecc->eccdata) -- return -ENOMEM; -- -- res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -- ecc->regs = devm_ioremap_resource(dev, res); -- if (IS_ERR(ecc->regs)) -- return PTR_ERR(ecc->regs); -- -- ecc->clk = devm_clk_get(dev, NULL); -- if (IS_ERR(ecc->clk)) { -- dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(ecc->clk)); -- return PTR_ERR(ecc->clk); -- } -- -- irq = platform_get_irq(pdev, 0); -- if (irq < 0) -- return irq; -- -- ret = dma_set_mask(dev, DMA_BIT_MASK(32)); -- if (ret) { -- dev_err(dev, "failed to set DMA mask\n"); -- return ret; -- } -- -- ret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, "mtk-ecc", ecc); -- if (ret) { -- dev_err(dev, "failed to request irq\n"); -- return -EINVAL; -- } -- -- ecc->dev = dev; -- mutex_init(&ecc->lock); -- platform_set_drvdata(pdev, ecc); -- dev_info(dev, "probed\n"); -- -- return 0; --} -- --#ifdef CONFIG_PM_SLEEP --static int mtk_ecc_suspend(struct device *dev) --{ -- struct mtk_ecc *ecc = dev_get_drvdata(dev); -- -- clk_disable_unprepare(ecc->clk); -- -- return 0; --} -- --static int mtk_ecc_resume(struct device *dev) --{ -- struct mtk_ecc *ecc = dev_get_drvdata(dev); -- int ret; -- -- ret = clk_prepare_enable(ecc->clk); -- if (ret) { -- dev_err(dev, "failed to enable clk\n"); -- return ret; -- } -- -- return 0; --} -- --static SIMPLE_DEV_PM_OPS(mtk_ecc_pm_ops, mtk_ecc_suspend, mtk_ecc_resume); --#endif -- --MODULE_DEVICE_TABLE(of, mtk_ecc_dt_match); -- --static struct platform_driver mtk_ecc_driver = { -- .probe = mtk_ecc_probe, -- .driver = { -- .name = "mtk-ecc", -- .of_match_table = of_match_ptr(mtk_ecc_dt_match), --#ifdef CONFIG_PM_SLEEP -- .pm = &mtk_ecc_pm_ops, --#endif -- }, --}; -- --module_platform_driver(mtk_ecc_driver); -- --MODULE_AUTHOR("Xiaolei Li "); --MODULE_DESCRIPTION("MTK Nand ECC Driver"); --MODULE_LICENSE("Dual MIT/GPL"); ---- /dev/null -+++ b/drivers/mtd/nand/ecc-mtk.c -@@ -0,0 +1,598 @@ -+// SPDX-License-Identifier: GPL-2.0 OR MIT -+/* -+ * MTK ECC controller driver. -+ * Copyright (C) 2016 MediaTek Inc. -+ * Authors: Xiaolei Li -+ * Jorge Ramirez-Ortiz -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define ECC_IDLE_MASK BIT(0) -+#define ECC_IRQ_EN BIT(0) -+#define ECC_PG_IRQ_SEL BIT(1) -+#define ECC_OP_ENABLE (1) -+#define ECC_OP_DISABLE (0) -+ -+#define ECC_ENCCON (0x00) -+#define ECC_ENCCNFG (0x04) -+#define ECC_MS_SHIFT (16) -+#define ECC_ENCDIADDR (0x08) -+#define ECC_ENCIDLE (0x0C) -+#define ECC_DECCON (0x100) -+#define ECC_DECCNFG (0x104) -+#define DEC_EMPTY_EN BIT(31) -+#define DEC_CNFG_CORRECT (0x3 << 12) -+#define ECC_DECIDLE (0x10C) -+#define ECC_DECENUM0 (0x114) -+ -+#define ECC_TIMEOUT (500000) -+ -+#define ECC_IDLE_REG(op) ((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE) -+#define ECC_CTL_REG(op) ((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON) -+ -+struct mtk_ecc_caps { -+ u32 err_mask; -+ u32 err_shift; -+ const u8 *ecc_strength; -+ const u32 *ecc_regs; -+ u8 num_ecc_strength; -+ u8 ecc_mode_shift; -+ u32 parity_bits; -+ int pg_irq_sel; -+}; -+ -+struct mtk_ecc { -+ struct device *dev; -+ const struct mtk_ecc_caps *caps; -+ void __iomem *regs; -+ struct clk *clk; -+ -+ struct completion done; -+ struct mutex lock; -+ u32 sectors; -+ -+ u8 *eccdata; -+}; -+ -+/* ecc strength that each IP supports */ -+static const u8 ecc_strength_mt2701[] = { -+ 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, -+ 40, 44, 48, 52, 56, 60 -+}; -+ -+static const u8 ecc_strength_mt2712[] = { -+ 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, -+ 40, 44, 48, 52, 56, 60, 68, 72, 80 -+}; -+ -+static const u8 ecc_strength_mt7622[] = { -+ 4, 6, 8, 10, 12 -+}; -+ -+enum mtk_ecc_regs { -+ ECC_ENCPAR00, -+ ECC_ENCIRQ_EN, -+ ECC_ENCIRQ_STA, -+ ECC_DECDONE, -+ ECC_DECIRQ_EN, -+ ECC_DECIRQ_STA, -+}; -+ -+static int mt2701_ecc_regs[] = { -+ [ECC_ENCPAR00] = 0x10, -+ [ECC_ENCIRQ_EN] = 0x80, -+ [ECC_ENCIRQ_STA] = 0x84, -+ [ECC_DECDONE] = 0x124, -+ [ECC_DECIRQ_EN] = 0x200, -+ [ECC_DECIRQ_STA] = 0x204, -+}; -+ -+static int mt2712_ecc_regs[] = { -+ [ECC_ENCPAR00] = 0x300, -+ [ECC_ENCIRQ_EN] = 0x80, -+ [ECC_ENCIRQ_STA] = 0x84, -+ [ECC_DECDONE] = 0x124, -+ [ECC_DECIRQ_EN] = 0x200, -+ [ECC_DECIRQ_STA] = 0x204, -+}; -+ -+static int mt7622_ecc_regs[] = { -+ [ECC_ENCPAR00] = 0x10, -+ [ECC_ENCIRQ_EN] = 0x30, -+ [ECC_ENCIRQ_STA] = 0x34, -+ [ECC_DECDONE] = 0x11c, -+ [ECC_DECIRQ_EN] = 0x140, -+ [ECC_DECIRQ_STA] = 0x144, -+}; -+ -+static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc, -+ enum mtk_ecc_operation op) -+{ -+ struct device *dev = ecc->dev; -+ u32 val; -+ int ret; -+ -+ ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val, -+ val & ECC_IDLE_MASK, -+ 10, ECC_TIMEOUT); -+ if (ret) -+ dev_warn(dev, "%s NOT idle\n", -+ op == ECC_ENCODE ? "encoder" : "decoder"); -+} -+ -+static irqreturn_t mtk_ecc_irq(int irq, void *id) -+{ -+ struct mtk_ecc *ecc = id; -+ u32 dec, enc; -+ -+ dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]) -+ & ECC_IRQ_EN; -+ if (dec) { -+ dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]); -+ if (dec & ecc->sectors) { -+ /* -+ * Clear decode IRQ status once again to ensure that -+ * there will be no extra IRQ. -+ */ -+ readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]); -+ ecc->sectors = 0; -+ complete(&ecc->done); -+ } else { -+ return IRQ_HANDLED; -+ } -+ } else { -+ enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA]) -+ & ECC_IRQ_EN; -+ if (enc) -+ complete(&ecc->done); -+ else -+ return IRQ_NONE; -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config) -+{ -+ u32 ecc_bit, dec_sz, enc_sz; -+ u32 reg, i; -+ -+ for (i = 0; i < ecc->caps->num_ecc_strength; i++) { -+ if (ecc->caps->ecc_strength[i] == config->strength) -+ break; -+ } -+ -+ if (i == ecc->caps->num_ecc_strength) { -+ dev_err(ecc->dev, "invalid ecc strength %d\n", -+ config->strength); -+ return -EINVAL; -+ } -+ -+ ecc_bit = i; -+ -+ if (config->op == ECC_ENCODE) { -+ /* configure ECC encoder (in bits) */ -+ enc_sz = config->len << 3; -+ -+ reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift); -+ reg |= (enc_sz << ECC_MS_SHIFT); -+ writel(reg, ecc->regs + ECC_ENCCNFG); -+ -+ if (config->mode != ECC_NFI_MODE) -+ writel(lower_32_bits(config->addr), -+ ecc->regs + ECC_ENCDIADDR); -+ -+ } else { -+ /* configure ECC decoder (in bits) */ -+ dec_sz = (config->len << 3) + -+ config->strength * ecc->caps->parity_bits; -+ -+ reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift); -+ reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT; -+ reg |= DEC_EMPTY_EN; -+ writel(reg, ecc->regs + ECC_DECCNFG); -+ -+ if (config->sectors) -+ ecc->sectors = 1 << (config->sectors - 1); -+ } -+ -+ return 0; -+} -+ -+void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats, -+ int sectors) -+{ -+ u32 offset, i, err; -+ u32 bitflips = 0; -+ -+ stats->corrected = 0; -+ stats->failed = 0; -+ -+ for (i = 0; i < sectors; i++) { -+ offset = (i >> 2) << 2; -+ err = readl(ecc->regs + ECC_DECENUM0 + offset); -+ err = err >> ((i % 4) * ecc->caps->err_shift); -+ err &= ecc->caps->err_mask; -+ if (err == ecc->caps->err_mask) { -+ /* uncorrectable errors */ -+ stats->failed++; -+ continue; -+ } -+ -+ stats->corrected += err; -+ bitflips = max_t(u32, bitflips, err); -+ } -+ -+ stats->bitflips = bitflips; -+} -+EXPORT_SYMBOL(mtk_ecc_get_stats); -+ -+void mtk_ecc_release(struct mtk_ecc *ecc) -+{ -+ clk_disable_unprepare(ecc->clk); -+ put_device(ecc->dev); -+} -+EXPORT_SYMBOL(mtk_ecc_release); -+ -+static void mtk_ecc_hw_init(struct mtk_ecc *ecc) -+{ -+ mtk_ecc_wait_idle(ecc, ECC_ENCODE); -+ writew(ECC_OP_DISABLE, ecc->regs + ECC_ENCCON); -+ -+ mtk_ecc_wait_idle(ecc, ECC_DECODE); -+ writel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON); -+} -+ -+static struct mtk_ecc *mtk_ecc_get(struct device_node *np) -+{ -+ struct platform_device *pdev; -+ struct mtk_ecc *ecc; -+ -+ pdev = of_find_device_by_node(np); -+ if (!pdev) -+ return ERR_PTR(-EPROBE_DEFER); -+ -+ ecc = platform_get_drvdata(pdev); -+ if (!ecc) { -+ put_device(&pdev->dev); -+ return ERR_PTR(-EPROBE_DEFER); -+ } -+ -+ clk_prepare_enable(ecc->clk); -+ mtk_ecc_hw_init(ecc); -+ -+ return ecc; -+} -+ -+struct mtk_ecc *of_mtk_ecc_get(struct device_node *of_node) -+{ -+ struct mtk_ecc *ecc = NULL; -+ struct device_node *np; -+ -+ np = of_parse_phandle(of_node, "ecc-engine", 0); -+ if (np) { -+ ecc = mtk_ecc_get(np); -+ of_node_put(np); -+ } -+ -+ return ecc; -+} -+EXPORT_SYMBOL(of_mtk_ecc_get); -+ -+int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config) -+{ -+ enum mtk_ecc_operation op = config->op; -+ u16 reg_val; -+ int ret; -+ -+ ret = mutex_lock_interruptible(&ecc->lock); -+ if (ret) { -+ dev_err(ecc->dev, "interrupted when attempting to lock\n"); -+ return ret; -+ } -+ -+ mtk_ecc_wait_idle(ecc, op); -+ -+ ret = mtk_ecc_config(ecc, config); -+ if (ret) { -+ mutex_unlock(&ecc->lock); -+ return ret; -+ } -+ -+ if (config->mode != ECC_NFI_MODE || op != ECC_ENCODE) { -+ init_completion(&ecc->done); -+ reg_val = ECC_IRQ_EN; -+ /* -+ * For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it -+ * means this chip can only generate one ecc irq during page -+ * read / write. If is 0, generate one ecc irq each ecc step. -+ */ -+ if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE) -+ reg_val |= ECC_PG_IRQ_SEL; -+ if (op == ECC_ENCODE) -+ writew(reg_val, ecc->regs + -+ ecc->caps->ecc_regs[ECC_ENCIRQ_EN]); -+ else -+ writew(reg_val, ecc->regs + -+ ecc->caps->ecc_regs[ECC_DECIRQ_EN]); -+ } -+ -+ writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op)); -+ -+ return 0; -+} -+EXPORT_SYMBOL(mtk_ecc_enable); -+ -+void mtk_ecc_disable(struct mtk_ecc *ecc) -+{ -+ enum mtk_ecc_operation op = ECC_ENCODE; -+ -+ /* find out the running operation */ -+ if (readw(ecc->regs + ECC_CTL_REG(op)) != ECC_OP_ENABLE) -+ op = ECC_DECODE; -+ -+ /* disable it */ -+ mtk_ecc_wait_idle(ecc, op); -+ if (op == ECC_DECODE) { -+ /* -+ * Clear decode IRQ status in case there is a timeout to wait -+ * decode IRQ. -+ */ -+ readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]); -+ writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]); -+ } else { -+ writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]); -+ } -+ -+ writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op)); -+ -+ mutex_unlock(&ecc->lock); -+} -+EXPORT_SYMBOL(mtk_ecc_disable); -+ -+int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op) -+{ -+ int ret; -+ -+ ret = wait_for_completion_timeout(&ecc->done, msecs_to_jiffies(500)); -+ if (!ret) { -+ dev_err(ecc->dev, "%s timeout - interrupt did not arrive)\n", -+ (op == ECC_ENCODE) ? "encoder" : "decoder"); -+ return -ETIMEDOUT; -+ } -+ -+ return 0; -+} -+EXPORT_SYMBOL(mtk_ecc_wait_done); -+ -+int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config, -+ u8 *data, u32 bytes) -+{ -+ dma_addr_t addr; -+ u32 len; -+ int ret; -+ -+ addr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE); -+ ret = dma_mapping_error(ecc->dev, addr); -+ if (ret) { -+ dev_err(ecc->dev, "dma mapping error\n"); -+ return -EINVAL; -+ } -+ -+ config->op = ECC_ENCODE; -+ config->addr = addr; -+ ret = mtk_ecc_enable(ecc, config); -+ if (ret) { -+ dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE); -+ return ret; -+ } -+ -+ ret = mtk_ecc_wait_done(ecc, ECC_ENCODE); -+ if (ret) -+ goto timeout; -+ -+ mtk_ecc_wait_idle(ecc, ECC_ENCODE); -+ -+ /* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */ -+ len = (config->strength * ecc->caps->parity_bits + 7) >> 3; -+ -+ /* write the parity bytes generated by the ECC back to temp buffer */ -+ __ioread32_copy(ecc->eccdata, -+ ecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00], -+ round_up(len, 4)); -+ -+ /* copy into possibly unaligned OOB region with actual length */ -+ memcpy(data + bytes, ecc->eccdata, len); -+timeout: -+ -+ dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE); -+ mtk_ecc_disable(ecc); -+ -+ return ret; -+} -+EXPORT_SYMBOL(mtk_ecc_encode); -+ -+void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p) -+{ -+ const u8 *ecc_strength = ecc->caps->ecc_strength; -+ int i; -+ -+ for (i = 0; i < ecc->caps->num_ecc_strength; i++) { -+ if (*p <= ecc_strength[i]) { -+ if (!i) -+ *p = ecc_strength[i]; -+ else if (*p != ecc_strength[i]) -+ *p = ecc_strength[i - 1]; -+ return; -+ } -+ } -+ -+ *p = ecc_strength[ecc->caps->num_ecc_strength - 1]; -+} -+EXPORT_SYMBOL(mtk_ecc_adjust_strength); -+ -+unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc) -+{ -+ return ecc->caps->parity_bits; -+} -+EXPORT_SYMBOL(mtk_ecc_get_parity_bits); -+ -+static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = { -+ .err_mask = 0x3f, -+ .err_shift = 8, -+ .ecc_strength = ecc_strength_mt2701, -+ .ecc_regs = mt2701_ecc_regs, -+ .num_ecc_strength = 20, -+ .ecc_mode_shift = 5, -+ .parity_bits = 14, -+ .pg_irq_sel = 0, -+}; -+ -+static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = { -+ .err_mask = 0x7f, -+ .err_shift = 8, -+ .ecc_strength = ecc_strength_mt2712, -+ .ecc_regs = mt2712_ecc_regs, -+ .num_ecc_strength = 23, -+ .ecc_mode_shift = 5, -+ .parity_bits = 14, -+ .pg_irq_sel = 1, -+}; -+ -+static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = { -+ .err_mask = 0x1f, -+ .err_shift = 5, -+ .ecc_strength = ecc_strength_mt7622, -+ .ecc_regs = mt7622_ecc_regs, -+ .num_ecc_strength = 5, -+ .ecc_mode_shift = 4, -+ .parity_bits = 13, -+ .pg_irq_sel = 0, -+}; -+ -+static const struct of_device_id mtk_ecc_dt_match[] = { -+ { -+ .compatible = "mediatek,mt2701-ecc", -+ .data = &mtk_ecc_caps_mt2701, -+ }, { -+ .compatible = "mediatek,mt2712-ecc", -+ .data = &mtk_ecc_caps_mt2712, -+ }, { -+ .compatible = "mediatek,mt7622-ecc", -+ .data = &mtk_ecc_caps_mt7622, -+ }, -+ {}, -+}; -+ -+static int mtk_ecc_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct mtk_ecc *ecc; -+ struct resource *res; -+ u32 max_eccdata_size; -+ int irq, ret; -+ -+ ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL); -+ if (!ecc) -+ return -ENOMEM; -+ -+ ecc->caps = of_device_get_match_data(dev); -+ -+ max_eccdata_size = ecc->caps->num_ecc_strength - 1; -+ max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size]; -+ max_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3; -+ max_eccdata_size = round_up(max_eccdata_size, 4); -+ ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL); -+ if (!ecc->eccdata) -+ return -ENOMEM; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ ecc->regs = devm_ioremap_resource(dev, res); -+ if (IS_ERR(ecc->regs)) -+ return PTR_ERR(ecc->regs); -+ -+ ecc->clk = devm_clk_get(dev, NULL); -+ if (IS_ERR(ecc->clk)) { -+ dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(ecc->clk)); -+ return PTR_ERR(ecc->clk); -+ } -+ -+ irq = platform_get_irq(pdev, 0); -+ if (irq < 0) -+ return irq; -+ -+ ret = dma_set_mask(dev, DMA_BIT_MASK(32)); -+ if (ret) { -+ dev_err(dev, "failed to set DMA mask\n"); -+ return ret; -+ } -+ -+ ret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, "mtk-ecc", ecc); -+ if (ret) { -+ dev_err(dev, "failed to request irq\n"); -+ return -EINVAL; -+ } -+ -+ ecc->dev = dev; -+ mutex_init(&ecc->lock); -+ platform_set_drvdata(pdev, ecc); -+ dev_info(dev, "probed\n"); -+ -+ return 0; -+} -+ -+#ifdef CONFIG_PM_SLEEP -+static int mtk_ecc_suspend(struct device *dev) -+{ -+ struct mtk_ecc *ecc = dev_get_drvdata(dev); -+ -+ clk_disable_unprepare(ecc->clk); -+ -+ return 0; -+} -+ -+static int mtk_ecc_resume(struct device *dev) -+{ -+ struct mtk_ecc *ecc = dev_get_drvdata(dev); -+ int ret; -+ -+ ret = clk_prepare_enable(ecc->clk); -+ if (ret) { -+ dev_err(dev, "failed to enable clk\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static SIMPLE_DEV_PM_OPS(mtk_ecc_pm_ops, mtk_ecc_suspend, mtk_ecc_resume); -+#endif -+ -+MODULE_DEVICE_TABLE(of, mtk_ecc_dt_match); -+ -+static struct platform_driver mtk_ecc_driver = { -+ .probe = mtk_ecc_probe, -+ .driver = { -+ .name = "mtk-ecc", -+ .of_match_table = of_match_ptr(mtk_ecc_dt_match), -+#ifdef CONFIG_PM_SLEEP -+ .pm = &mtk_ecc_pm_ops, -+#endif -+ }, -+}; -+ -+module_platform_driver(mtk_ecc_driver); -+ -+MODULE_AUTHOR("Xiaolei Li "); -+MODULE_DESCRIPTION("MTK Nand ECC Driver"); -+MODULE_LICENSE("Dual MIT/GPL"); ---- a/drivers/mtd/nand/raw/Kconfig -+++ b/drivers/mtd/nand/raw/Kconfig -@@ -360,6 +360,7 @@ config MTD_NAND_QCOM - - config MTD_NAND_MTK - tristate "MTK NAND controller" -+ depends on MTD_NAND_ECC_MEDIATEK - depends on ARCH_MEDIATEK || COMPILE_TEST - depends on HAS_IOMEM - help ---- a/drivers/mtd/nand/raw/Makefile -+++ b/drivers/mtd/nand/raw/Makefile -@@ -48,7 +48,7 @@ obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_n - obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o - obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/ - obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o --obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o -+obj-$(CONFIG_MTD_NAND_MTK) += mtk_nand.o - obj-$(CONFIG_MTD_NAND_MXIC) += mxic_nand.o - obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o - obj-$(CONFIG_MTD_NAND_STM32_FMC2) += stm32_fmc2_nand.o ---- a/drivers/mtd/nand/raw/mtk_nand.c -+++ b/drivers/mtd/nand/raw/mtk_nand.c -@@ -17,7 +17,7 @@ - #include - #include - #include --#include "mtk_ecc.h" -+#include - - /* NAND controller register definition */ - #define NFI_CNFG (0x00) ---- a/drivers/mtd/nand/raw/mtk_ecc.h -+++ /dev/null -@@ -1,47 +0,0 @@ --/* SPDX-License-Identifier: GPL-2.0 OR MIT */ --/* -- * MTK SDG1 ECC controller -- * -- * Copyright (c) 2016 Mediatek -- * Authors: Xiaolei Li -- * Jorge Ramirez-Ortiz -- */ -- --#ifndef __DRIVERS_MTD_NAND_MTK_ECC_H__ --#define __DRIVERS_MTD_NAND_MTK_ECC_H__ -- --#include -- --enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1}; --enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE}; -- --struct device_node; --struct mtk_ecc; -- --struct mtk_ecc_stats { -- u32 corrected; -- u32 bitflips; -- u32 failed; --}; -- --struct mtk_ecc_config { -- enum mtk_ecc_operation op; -- enum mtk_ecc_mode mode; -- dma_addr_t addr; -- u32 strength; -- u32 sectors; -- u32 len; --}; -- --int mtk_ecc_encode(struct mtk_ecc *, struct mtk_ecc_config *, u8 *, u32); --void mtk_ecc_get_stats(struct mtk_ecc *, struct mtk_ecc_stats *, int); --int mtk_ecc_wait_done(struct mtk_ecc *, enum mtk_ecc_operation); --int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *); --void mtk_ecc_disable(struct mtk_ecc *); --void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p); --unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc); -- --struct mtk_ecc *of_mtk_ecc_get(struct device_node *); --void mtk_ecc_release(struct mtk_ecc *); -- --#endif ---- /dev/null -+++ b/include/linux/mtd/nand-ecc-mtk.h -@@ -0,0 +1,47 @@ -+/* SPDX-License-Identifier: GPL-2.0 OR MIT */ -+/* -+ * MTK SDG1 ECC controller -+ * -+ * Copyright (c) 2016 Mediatek -+ * Authors: Xiaolei Li -+ * Jorge Ramirez-Ortiz -+ */ -+ -+#ifndef __DRIVERS_MTD_NAND_MTK_ECC_H__ -+#define __DRIVERS_MTD_NAND_MTK_ECC_H__ -+ -+#include -+ -+enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1}; -+enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE}; -+ -+struct device_node; -+struct mtk_ecc; -+ -+struct mtk_ecc_stats { -+ u32 corrected; -+ u32 bitflips; -+ u32 failed; -+}; -+ -+struct mtk_ecc_config { -+ enum mtk_ecc_operation op; -+ enum mtk_ecc_mode mode; -+ dma_addr_t addr; -+ u32 strength; -+ u32 sectors; -+ u32 len; -+}; -+ -+int mtk_ecc_encode(struct mtk_ecc *, struct mtk_ecc_config *, u8 *, u32); -+void mtk_ecc_get_stats(struct mtk_ecc *, struct mtk_ecc_stats *, int); -+int mtk_ecc_wait_done(struct mtk_ecc *, enum mtk_ecc_operation); -+int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *); -+void mtk_ecc_disable(struct mtk_ecc *); -+void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p); -+unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc); -+ -+struct mtk_ecc *of_mtk_ecc_get(struct device_node *); -+void mtk_ecc_release(struct mtk_ecc *); -+ -+#endif diff --git a/target/linux/mediatek/patches-6.1/120-12-v5.19-spi-add-driver-for-MTK-SPI-NAND-Flash-Interface.patch b/target/linux/mediatek/patches-6.1/120-12-v5.19-spi-add-driver-for-MTK-SPI-NAND-Flash-Interface.patch deleted file mode 100644 index ed209050123..00000000000 --- a/target/linux/mediatek/patches-6.1/120-12-v5.19-spi-add-driver-for-MTK-SPI-NAND-Flash-Interface.patch +++ /dev/null @@ -1,1537 +0,0 @@ -From 8170bafa8936e9fbfdce992932a63bd20eca3bc3 Mon Sep 17 00:00:00 2001 -From: Chuanhong Guo -Date: Sat, 2 Apr 2022 10:16:11 +0800 -Subject: [PATCH v6 2/5] spi: add driver for MTK SPI NAND Flash Interface - -This driver implements support for the SPI-NAND mode of MTK NAND Flash -Interface as a SPI-MEM controller with pipelined ECC capability. - -Signed-off-by: Chuanhong Guo -Tested-by: Daniel Golle ---- -Change since v1: - fix CI warnings - -Changes since v2: - use streamed DMA api to avoid an extra memory copy during read - make ECC engine config a per-nand context - take user-requested ECC strength into account - -Change since v3: none -Changes since v4: - fix missing OOB write - print page format with dev_dbg - replace uint*_t copied from vendor driver with u* - -Changes since v5: - add missing nfi mode register configuration in probe - fix an off-by-one bug in mtk_snand_mac_io - - drivers/spi/Kconfig | 10 + - drivers/spi/Makefile | 1 + - drivers/spi/spi-mtk-snfi.c | 1470 ++++++++++++++++++++++++++++++++++++ - 3 files changed, 1481 insertions(+) - create mode 100644 drivers/spi/spi-mtk-snfi.c - ---- a/drivers/spi/Kconfig -+++ b/drivers/spi/Kconfig -@@ -529,6 +529,16 @@ config SPI_MTK_NOR - SPI interface as well as several SPI NOR specific instructions - via SPI MEM interface. - -+config SPI_MTK_SNFI -+ tristate "MediaTek SPI NAND Flash Interface" -+ depends on ARCH_MEDIATEK || COMPILE_TEST -+ depends on MTD_NAND_ECC_MEDIATEK -+ help -+ This enables support for SPI-NAND mode on the MediaTek NAND -+ Flash Interface found on MediaTek ARM SoCs. This controller -+ is implemented as a SPI-MEM controller with pipelined ECC -+ capcability. -+ - config SPI_NPCM_FIU - tristate "Nuvoton NPCM FLASH Interface Unit" - depends on ARCH_NPCM || COMPILE_TEST ---- a/drivers/spi/Makefile -+++ b/drivers/spi/Makefile -@@ -71,6 +71,7 @@ obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52x - obj-$(CONFIG_SPI_MT65XX) += spi-mt65xx.o - obj-$(CONFIG_SPI_MT7621) += spi-mt7621.o - obj-$(CONFIG_SPI_MTK_NOR) += spi-mtk-nor.o -+obj-$(CONFIG_SPI_MTK_SNFI) += spi-mtk-snfi.o - obj-$(CONFIG_SPI_MXIC) += spi-mxic.o - obj-$(CONFIG_SPI_MXS) += spi-mxs.o - obj-$(CONFIG_SPI_NPCM_FIU) += spi-npcm-fiu.o ---- /dev/null -+++ b/drivers/spi/spi-mtk-snfi.c -@@ -0,0 +1,1470 @@ -+// SPDX-License-Identifier: GPL-2.0 -+// -+// Driver for the SPI-NAND mode of Mediatek NAND Flash Interface -+// -+// Copyright (c) 2022 Chuanhong Guo -+// -+// This driver is based on the SPI-NAND mtd driver from Mediatek SDK: -+// -+// Copyright (C) 2020 MediaTek Inc. -+// Author: Weijie Gao -+// -+// This controller organize the page data as several interleaved sectors -+// like the following: (sizeof(FDM + ECC) = snf->nfi_cfg.spare_size) -+// +---------+------+------+---------+------+------+-----+ -+// | Sector1 | FDM1 | ECC1 | Sector2 | FDM2 | ECC2 | ... | -+// +---------+------+------+---------+------+------+-----+ -+// With auto-format turned on, DMA only returns this part: -+// +---------+---------+-----+ -+// | Sector1 | Sector2 | ... | -+// +---------+---------+-----+ -+// The FDM data will be filled to the registers, and ECC parity data isn't -+// accessible. -+// With auto-format off, all ((Sector+FDM+ECC)*nsectors) will be read over DMA -+// in it's original order shown in the first table. ECC can't be turned on when -+// auto-format is off. -+// -+// However, Linux SPI-NAND driver expects the data returned as: -+// +------+-----+ -+// | Page | OOB | -+// +------+-----+ -+// where the page data is continuously stored instead of interleaved. -+// So we assume all instructions matching the page_op template between ECC -+// prepare_io_req and finish_io_req are for page cache r/w. -+// Here's how this spi-mem driver operates when reading: -+// 1. Always set snf->autofmt = true in prepare_io_req (even when ECC is off). -+// 2. Perform page ops and let the controller fill the DMA bounce buffer with -+// de-interleaved sector data and set FDM registers. -+// 3. Return the data as: -+// +---------+---------+-----+------+------+-----+ -+// | Sector1 | Sector2 | ... | FDM1 | FDM2 | ... | -+// +---------+---------+-----+------+------+-----+ -+// 4. For other matching spi_mem ops outside a prepare/finish_io_req pair, -+// read the data with auto-format off into the bounce buffer and copy -+// needed data to the buffer specified in the request. -+// -+// Write requests operates in a similar manner. -+// As a limitation of this strategy, we won't be able to access any ECC parity -+// data at all in Linux. -+// -+// Here's the bad block mark situation on MTK chips: -+// In older chips like mt7622, MTK uses the first FDM byte in the first sector -+// as the bad block mark. After de-interleaving, this byte appears at [pagesize] -+// in the returned data, which is the BBM position expected by kernel. However, -+// the conventional bad block mark is the first byte of the OOB, which is part -+// of the last sector data in the interleaved layout. Instead of fixing their -+// hardware, MTK decided to address this inconsistency in software. On these -+// later chips, the BootROM expects the following: -+// 1. The [pagesize] byte on a nand page is used as BBM, which will appear at -+// (page_size - (nsectors - 1) * spare_size) in the DMA buffer. -+// 2. The original byte stored at that position in the DMA buffer will be stored -+// as the first byte of the FDM section in the last sector. -+// We can't disagree with the BootROM, so after de-interleaving, we need to -+// perform the following swaps in read: -+// 1. Store the BBM at [page_size - (nsectors - 1) * spare_size] to [page_size], -+// which is the expected BBM position by kernel. -+// 2. Store the page data byte at [pagesize + (nsectors-1) * fdm] back to -+// [page_size - (nsectors - 1) * spare_size] -+// Similarly, when writing, we need to perform swaps in the other direction. -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+// NFI registers -+#define NFI_CNFG 0x000 -+#define CNFG_OP_MODE_S 12 -+#define CNFG_OP_MODE_CUST 6 -+#define CNFG_OP_MODE_PROGRAM 3 -+#define CNFG_AUTO_FMT_EN BIT(9) -+#define CNFG_HW_ECC_EN BIT(8) -+#define CNFG_DMA_BURST_EN BIT(2) -+#define CNFG_READ_MODE BIT(1) -+#define CNFG_DMA_MODE BIT(0) -+ -+#define NFI_PAGEFMT 0x0004 -+#define NFI_SPARE_SIZE_LS_S 16 -+#define NFI_FDM_ECC_NUM_S 12 -+#define NFI_FDM_NUM_S 8 -+#define NFI_SPARE_SIZE_S 4 -+#define NFI_SEC_SEL_512 BIT(2) -+#define NFI_PAGE_SIZE_S 0 -+#define NFI_PAGE_SIZE_512_2K 0 -+#define NFI_PAGE_SIZE_2K_4K 1 -+#define NFI_PAGE_SIZE_4K_8K 2 -+#define NFI_PAGE_SIZE_8K_16K 3 -+ -+#define NFI_CON 0x008 -+#define CON_SEC_NUM_S 12 -+#define CON_BWR BIT(9) -+#define CON_BRD BIT(8) -+#define CON_NFI_RST BIT(1) -+#define CON_FIFO_FLUSH BIT(0) -+ -+#define NFI_INTR_EN 0x010 -+#define NFI_INTR_STA 0x014 -+#define NFI_IRQ_INTR_EN BIT(31) -+#define NFI_IRQ_CUS_READ BIT(8) -+#define NFI_IRQ_CUS_PG BIT(7) -+ -+#define NFI_CMD 0x020 -+#define NFI_CMD_DUMMY_READ 0x00 -+#define NFI_CMD_DUMMY_WRITE 0x80 -+ -+#define NFI_STRDATA 0x040 -+#define STR_DATA BIT(0) -+ -+#define NFI_STA 0x060 -+#define NFI_NAND_FSM GENMASK(28, 24) -+#define NFI_FSM GENMASK(19, 16) -+#define READ_EMPTY BIT(12) -+ -+#define NFI_FIFOSTA 0x064 -+#define FIFO_WR_REMAIN_S 8 -+#define FIFO_RD_REMAIN_S 0 -+ -+#define NFI_ADDRCNTR 0x070 -+#define SEC_CNTR GENMASK(16, 12) -+#define SEC_CNTR_S 12 -+#define NFI_SEC_CNTR(val) (((val)&SEC_CNTR) >> SEC_CNTR_S) -+ -+#define NFI_STRADDR 0x080 -+ -+#define NFI_BYTELEN 0x084 -+#define BUS_SEC_CNTR(val) (((val)&SEC_CNTR) >> SEC_CNTR_S) -+ -+#define NFI_FDM0L 0x0a0 -+#define NFI_FDM0M 0x0a4 -+#define NFI_FDML(n) (NFI_FDM0L + (n)*8) -+#define NFI_FDMM(n) (NFI_FDM0M + (n)*8) -+ -+#define NFI_DEBUG_CON1 0x220 -+#define WBUF_EN BIT(2) -+ -+#define NFI_MASTERSTA 0x224 -+#define MAS_ADDR GENMASK(11, 9) -+#define MAS_RD GENMASK(8, 6) -+#define MAS_WR GENMASK(5, 3) -+#define MAS_RDDLY GENMASK(2, 0) -+#define NFI_MASTERSTA_MASK_7622 (MAS_ADDR | MAS_RD | MAS_WR | MAS_RDDLY) -+ -+// SNFI registers -+#define SNF_MAC_CTL 0x500 -+#define MAC_XIO_SEL BIT(4) -+#define SF_MAC_EN BIT(3) -+#define SF_TRIG BIT(2) -+#define WIP_READY BIT(1) -+#define WIP BIT(0) -+ -+#define SNF_MAC_OUTL 0x504 -+#define SNF_MAC_INL 0x508 -+ -+#define SNF_RD_CTL2 0x510 -+#define DATA_READ_DUMMY_S 8 -+#define DATA_READ_MAX_DUMMY 0xf -+#define DATA_READ_CMD_S 0 -+ -+#define SNF_RD_CTL3 0x514 -+ -+#define SNF_PG_CTL1 0x524 -+#define PG_LOAD_CMD_S 8 -+ -+#define SNF_PG_CTL2 0x528 -+ -+#define SNF_MISC_CTL 0x538 -+#define SW_RST BIT(28) -+#define FIFO_RD_LTC_S 25 -+#define PG_LOAD_X4_EN BIT(20) -+#define DATA_READ_MODE_S 16 -+#define DATA_READ_MODE GENMASK(18, 16) -+#define DATA_READ_MODE_X1 0 -+#define DATA_READ_MODE_X2 1 -+#define DATA_READ_MODE_X4 2 -+#define DATA_READ_MODE_DUAL 5 -+#define DATA_READ_MODE_QUAD 6 -+#define PG_LOAD_CUSTOM_EN BIT(7) -+#define DATARD_CUSTOM_EN BIT(6) -+#define CS_DESELECT_CYC_S 0 -+ -+#define SNF_MISC_CTL2 0x53c -+#define PROGRAM_LOAD_BYTE_NUM_S 16 -+#define READ_DATA_BYTE_NUM_S 11 -+ -+#define SNF_DLY_CTL3 0x548 -+#define SFCK_SAM_DLY_S 0 -+ -+#define SNF_STA_CTL1 0x550 -+#define CUS_PG_DONE BIT(28) -+#define CUS_READ_DONE BIT(27) -+#define SPI_STATE_S 0 -+#define SPI_STATE GENMASK(3, 0) -+ -+#define SNF_CFG 0x55c -+#define SPI_MODE BIT(0) -+ -+#define SNF_GPRAM 0x800 -+#define SNF_GPRAM_SIZE 0xa0 -+ -+#define SNFI_POLL_INTERVAL 1000000 -+ -+static const u8 mt7622_spare_sizes[] = { 16, 26, 27, 28 }; -+ -+struct mtk_snand_caps { -+ u16 sector_size; -+ u16 max_sectors; -+ u16 fdm_size; -+ u16 fdm_ecc_size; -+ u16 fifo_size; -+ -+ bool bbm_swap; -+ bool empty_page_check; -+ u32 mastersta_mask; -+ -+ const u8 *spare_sizes; -+ u32 num_spare_size; -+}; -+ -+static const struct mtk_snand_caps mt7622_snand_caps = { -+ .sector_size = 512, -+ .max_sectors = 8, -+ .fdm_size = 8, -+ .fdm_ecc_size = 1, -+ .fifo_size = 32, -+ .bbm_swap = false, -+ .empty_page_check = false, -+ .mastersta_mask = NFI_MASTERSTA_MASK_7622, -+ .spare_sizes = mt7622_spare_sizes, -+ .num_spare_size = ARRAY_SIZE(mt7622_spare_sizes) -+}; -+ -+static const struct mtk_snand_caps mt7629_snand_caps = { -+ .sector_size = 512, -+ .max_sectors = 8, -+ .fdm_size = 8, -+ .fdm_ecc_size = 1, -+ .fifo_size = 32, -+ .bbm_swap = true, -+ .empty_page_check = false, -+ .mastersta_mask = NFI_MASTERSTA_MASK_7622, -+ .spare_sizes = mt7622_spare_sizes, -+ .num_spare_size = ARRAY_SIZE(mt7622_spare_sizes) -+}; -+ -+struct mtk_snand_conf { -+ size_t page_size; -+ size_t oob_size; -+ u8 nsectors; -+ u8 spare_size; -+}; -+ -+struct mtk_snand { -+ struct spi_controller *ctlr; -+ struct device *dev; -+ struct clk *nfi_clk; -+ struct clk *pad_clk; -+ void __iomem *nfi_base; -+ int irq; -+ struct completion op_done; -+ const struct mtk_snand_caps *caps; -+ struct mtk_ecc_config *ecc_cfg; -+ struct mtk_ecc *ecc; -+ struct mtk_snand_conf nfi_cfg; -+ struct mtk_ecc_stats ecc_stats; -+ struct nand_ecc_engine ecc_eng; -+ bool autofmt; -+ u8 *buf; -+ size_t buf_len; -+}; -+ -+static struct mtk_snand *nand_to_mtk_snand(struct nand_device *nand) -+{ -+ struct nand_ecc_engine *eng = nand->ecc.engine; -+ -+ return container_of(eng, struct mtk_snand, ecc_eng); -+} -+ -+static inline int snand_prepare_bouncebuf(struct mtk_snand *snf, size_t size) -+{ -+ if (snf->buf_len >= size) -+ return 0; -+ kfree(snf->buf); -+ snf->buf = kmalloc(size, GFP_KERNEL); -+ if (!snf->buf) -+ return -ENOMEM; -+ snf->buf_len = size; -+ memset(snf->buf, 0xff, snf->buf_len); -+ return 0; -+} -+ -+static inline u32 nfi_read32(struct mtk_snand *snf, u32 reg) -+{ -+ return readl(snf->nfi_base + reg); -+} -+ -+static inline void nfi_write32(struct mtk_snand *snf, u32 reg, u32 val) -+{ -+ writel(val, snf->nfi_base + reg); -+} -+ -+static inline void nfi_write16(struct mtk_snand *snf, u32 reg, u16 val) -+{ -+ writew(val, snf->nfi_base + reg); -+} -+ -+static inline void nfi_rmw32(struct mtk_snand *snf, u32 reg, u32 clr, u32 set) -+{ -+ u32 val; -+ -+ val = readl(snf->nfi_base + reg); -+ val &= ~clr; -+ val |= set; -+ writel(val, snf->nfi_base + reg); -+} -+ -+static void nfi_read_data(struct mtk_snand *snf, u32 reg, u8 *data, u32 len) -+{ -+ u32 i, val = 0, es = sizeof(u32); -+ -+ for (i = reg; i < reg + len; i++) { -+ if (i == reg || i % es == 0) -+ val = nfi_read32(snf, i & ~(es - 1)); -+ -+ *data++ = (u8)(val >> (8 * (i % es))); -+ } -+} -+ -+static int mtk_nfi_reset(struct mtk_snand *snf) -+{ -+ u32 val, fifo_mask; -+ int ret; -+ -+ nfi_write32(snf, NFI_CON, CON_FIFO_FLUSH | CON_NFI_RST); -+ -+ ret = readw_poll_timeout(snf->nfi_base + NFI_MASTERSTA, val, -+ !(val & snf->caps->mastersta_mask), 0, -+ SNFI_POLL_INTERVAL); -+ if (ret) { -+ dev_err(snf->dev, "NFI master is still busy after reset\n"); -+ return ret; -+ } -+ -+ ret = readl_poll_timeout(snf->nfi_base + NFI_STA, val, -+ !(val & (NFI_FSM | NFI_NAND_FSM)), 0, -+ SNFI_POLL_INTERVAL); -+ if (ret) { -+ dev_err(snf->dev, "Failed to reset NFI\n"); -+ return ret; -+ } -+ -+ fifo_mask = ((snf->caps->fifo_size - 1) << FIFO_RD_REMAIN_S) | -+ ((snf->caps->fifo_size - 1) << FIFO_WR_REMAIN_S); -+ ret = readw_poll_timeout(snf->nfi_base + NFI_FIFOSTA, val, -+ !(val & fifo_mask), 0, SNFI_POLL_INTERVAL); -+ if (ret) { -+ dev_err(snf->dev, "NFI FIFOs are not empty\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int mtk_snand_mac_reset(struct mtk_snand *snf) -+{ -+ int ret; -+ u32 val; -+ -+ nfi_rmw32(snf, SNF_MISC_CTL, 0, SW_RST); -+ -+ ret = readl_poll_timeout(snf->nfi_base + SNF_STA_CTL1, val, -+ !(val & SPI_STATE), 0, SNFI_POLL_INTERVAL); -+ if (ret) -+ dev_err(snf->dev, "Failed to reset SNFI MAC\n"); -+ -+ nfi_write32(snf, SNF_MISC_CTL, -+ (2 << FIFO_RD_LTC_S) | (10 << CS_DESELECT_CYC_S)); -+ -+ return ret; -+} -+ -+static int mtk_snand_mac_trigger(struct mtk_snand *snf, u32 outlen, u32 inlen) -+{ -+ int ret; -+ u32 val; -+ -+ nfi_write32(snf, SNF_MAC_CTL, SF_MAC_EN); -+ nfi_write32(snf, SNF_MAC_OUTL, outlen); -+ nfi_write32(snf, SNF_MAC_INL, inlen); -+ -+ nfi_write32(snf, SNF_MAC_CTL, SF_MAC_EN | SF_TRIG); -+ -+ ret = readl_poll_timeout(snf->nfi_base + SNF_MAC_CTL, val, -+ val & WIP_READY, 0, SNFI_POLL_INTERVAL); -+ if (ret) { -+ dev_err(snf->dev, "Timed out waiting for WIP_READY\n"); -+ goto cleanup; -+ } -+ -+ ret = readl_poll_timeout(snf->nfi_base + SNF_MAC_CTL, val, !(val & WIP), -+ 0, SNFI_POLL_INTERVAL); -+ if (ret) -+ dev_err(snf->dev, "Timed out waiting for WIP cleared\n"); -+ -+cleanup: -+ nfi_write32(snf, SNF_MAC_CTL, 0); -+ -+ return ret; -+} -+ -+static int mtk_snand_mac_io(struct mtk_snand *snf, const struct spi_mem_op *op) -+{ -+ u32 rx_len = 0; -+ u32 reg_offs = 0; -+ u32 val = 0; -+ const u8 *tx_buf = NULL; -+ u8 *rx_buf = NULL; -+ int i, ret; -+ u8 b; -+ -+ if (op->data.dir == SPI_MEM_DATA_IN) { -+ rx_len = op->data.nbytes; -+ rx_buf = op->data.buf.in; -+ } else { -+ tx_buf = op->data.buf.out; -+ } -+ -+ mtk_snand_mac_reset(snf); -+ -+ for (i = 0; i < op->cmd.nbytes; i++, reg_offs++) { -+ b = (op->cmd.opcode >> ((op->cmd.nbytes - i - 1) * 8)) & 0xff; -+ val |= b << (8 * (reg_offs % 4)); -+ if (reg_offs % 4 == 3) { -+ nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val); -+ val = 0; -+ } -+ } -+ -+ for (i = 0; i < op->addr.nbytes; i++, reg_offs++) { -+ b = (op->addr.val >> ((op->addr.nbytes - i - 1) * 8)) & 0xff; -+ val |= b << (8 * (reg_offs % 4)); -+ if (reg_offs % 4 == 3) { -+ nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val); -+ val = 0; -+ } -+ } -+ -+ for (i = 0; i < op->dummy.nbytes; i++, reg_offs++) { -+ if (reg_offs % 4 == 3) { -+ nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val); -+ val = 0; -+ } -+ } -+ -+ if (op->data.dir == SPI_MEM_DATA_OUT) { -+ for (i = 0; i < op->data.nbytes; i++, reg_offs++) { -+ val |= tx_buf[i] << (8 * (reg_offs % 4)); -+ if (reg_offs % 4 == 3) { -+ nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val); -+ val = 0; -+ } -+ } -+ } -+ -+ if (reg_offs % 4) -+ nfi_write32(snf, SNF_GPRAM + (reg_offs & ~3), val); -+ -+ for (i = 0; i < reg_offs; i += 4) -+ dev_dbg(snf->dev, "%d: %08X", i, -+ nfi_read32(snf, SNF_GPRAM + i)); -+ -+ dev_dbg(snf->dev, "SNF TX: %u RX: %u", reg_offs, rx_len); -+ -+ ret = mtk_snand_mac_trigger(snf, reg_offs, rx_len); -+ if (ret) -+ return ret; -+ -+ if (!rx_len) -+ return 0; -+ -+ nfi_read_data(snf, SNF_GPRAM + reg_offs, rx_buf, rx_len); -+ return 0; -+} -+ -+static int mtk_snand_setup_pagefmt(struct mtk_snand *snf, u32 page_size, -+ u32 oob_size) -+{ -+ int spare_idx = -1; -+ u32 spare_size, spare_size_shift, pagesize_idx; -+ u32 sector_size_512; -+ u8 nsectors; -+ int i; -+ -+ // skip if it's already configured as required. -+ if (snf->nfi_cfg.page_size == page_size && -+ snf->nfi_cfg.oob_size == oob_size) -+ return 0; -+ -+ nsectors = page_size / snf->caps->sector_size; -+ if (nsectors > snf->caps->max_sectors) { -+ dev_err(snf->dev, "too many sectors required.\n"); -+ goto err; -+ } -+ -+ if (snf->caps->sector_size == 512) { -+ sector_size_512 = NFI_SEC_SEL_512; -+ spare_size_shift = NFI_SPARE_SIZE_S; -+ } else { -+ sector_size_512 = 0; -+ spare_size_shift = NFI_SPARE_SIZE_LS_S; -+ } -+ -+ switch (page_size) { -+ case SZ_512: -+ pagesize_idx = NFI_PAGE_SIZE_512_2K; -+ break; -+ case SZ_2K: -+ if (snf->caps->sector_size == 512) -+ pagesize_idx = NFI_PAGE_SIZE_2K_4K; -+ else -+ pagesize_idx = NFI_PAGE_SIZE_512_2K; -+ break; -+ case SZ_4K: -+ if (snf->caps->sector_size == 512) -+ pagesize_idx = NFI_PAGE_SIZE_4K_8K; -+ else -+ pagesize_idx = NFI_PAGE_SIZE_2K_4K; -+ break; -+ case SZ_8K: -+ if (snf->caps->sector_size == 512) -+ pagesize_idx = NFI_PAGE_SIZE_8K_16K; -+ else -+ pagesize_idx = NFI_PAGE_SIZE_4K_8K; -+ break; -+ case SZ_16K: -+ pagesize_idx = NFI_PAGE_SIZE_8K_16K; -+ break; -+ default: -+ dev_err(snf->dev, "unsupported page size.\n"); -+ goto err; -+ } -+ -+ spare_size = oob_size / nsectors; -+ // If we're using the 1KB sector size, HW will automatically double the -+ // spare size. We should only use half of the value in this case. -+ if (snf->caps->sector_size == 1024) -+ spare_size /= 2; -+ -+ for (i = snf->caps->num_spare_size - 1; i >= 0; i--) { -+ if (snf->caps->spare_sizes[i] <= spare_size) { -+ spare_size = snf->caps->spare_sizes[i]; -+ if (snf->caps->sector_size == 1024) -+ spare_size *= 2; -+ spare_idx = i; -+ break; -+ } -+ } -+ -+ if (spare_idx < 0) { -+ dev_err(snf->dev, "unsupported spare size: %u\n", spare_size); -+ goto err; -+ } -+ -+ nfi_write32(snf, NFI_PAGEFMT, -+ (snf->caps->fdm_ecc_size << NFI_FDM_ECC_NUM_S) | -+ (snf->caps->fdm_size << NFI_FDM_NUM_S) | -+ (spare_idx << spare_size_shift) | -+ (pagesize_idx << NFI_PAGE_SIZE_S) | -+ sector_size_512); -+ -+ snf->nfi_cfg.page_size = page_size; -+ snf->nfi_cfg.oob_size = oob_size; -+ snf->nfi_cfg.nsectors = nsectors; -+ snf->nfi_cfg.spare_size = spare_size; -+ -+ dev_dbg(snf->dev, "page format: (%u + %u) * %u\n", -+ snf->caps->sector_size, spare_size, nsectors); -+ return snand_prepare_bouncebuf(snf, page_size + oob_size); -+err: -+ dev_err(snf->dev, "page size %u + %u is not supported\n", page_size, -+ oob_size); -+ return -EOPNOTSUPP; -+} -+ -+static int mtk_snand_ooblayout_ecc(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *oobecc) -+{ -+ // ECC area is not accessible -+ return -ERANGE; -+} -+ -+static int mtk_snand_ooblayout_free(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *oobfree) -+{ -+ struct nand_device *nand = mtd_to_nanddev(mtd); -+ struct mtk_snand *ms = nand_to_mtk_snand(nand); -+ -+ if (section >= ms->nfi_cfg.nsectors) -+ return -ERANGE; -+ -+ oobfree->length = ms->caps->fdm_size - 1; -+ oobfree->offset = section * ms->caps->fdm_size + 1; -+ return 0; -+} -+ -+static const struct mtd_ooblayout_ops mtk_snand_ooblayout = { -+ .ecc = mtk_snand_ooblayout_ecc, -+ .free = mtk_snand_ooblayout_free, -+}; -+ -+static int mtk_snand_ecc_init_ctx(struct nand_device *nand) -+{ -+ struct mtk_snand *snf = nand_to_mtk_snand(nand); -+ struct nand_ecc_props *conf = &nand->ecc.ctx.conf; -+ struct nand_ecc_props *reqs = &nand->ecc.requirements; -+ struct nand_ecc_props *user = &nand->ecc.user_conf; -+ struct mtd_info *mtd = nanddev_to_mtd(nand); -+ int step_size = 0, strength = 0, desired_correction = 0, steps; -+ bool ecc_user = false; -+ int ret; -+ u32 parity_bits, max_ecc_bytes; -+ struct mtk_ecc_config *ecc_cfg; -+ -+ ret = mtk_snand_setup_pagefmt(snf, nand->memorg.pagesize, -+ nand->memorg.oobsize); -+ if (ret) -+ return ret; -+ -+ ecc_cfg = kzalloc(sizeof(*ecc_cfg), GFP_KERNEL); -+ if (!ecc_cfg) -+ return -ENOMEM; -+ -+ nand->ecc.ctx.priv = ecc_cfg; -+ -+ if (user->step_size && user->strength) { -+ step_size = user->step_size; -+ strength = user->strength; -+ ecc_user = true; -+ } else if (reqs->step_size && reqs->strength) { -+ step_size = reqs->step_size; -+ strength = reqs->strength; -+ } -+ -+ if (step_size && strength) { -+ steps = mtd->writesize / step_size; -+ desired_correction = steps * strength; -+ strength = desired_correction / snf->nfi_cfg.nsectors; -+ } -+ -+ ecc_cfg->mode = ECC_NFI_MODE; -+ ecc_cfg->sectors = snf->nfi_cfg.nsectors; -+ ecc_cfg->len = snf->caps->sector_size + snf->caps->fdm_ecc_size; -+ -+ // calculate the max possible strength under current page format -+ parity_bits = mtk_ecc_get_parity_bits(snf->ecc); -+ max_ecc_bytes = snf->nfi_cfg.spare_size - snf->caps->fdm_size; -+ ecc_cfg->strength = max_ecc_bytes * 8 / parity_bits; -+ mtk_ecc_adjust_strength(snf->ecc, &ecc_cfg->strength); -+ -+ // if there's a user requested strength, find the minimum strength that -+ // meets the requirement. Otherwise use the maximum strength which is -+ // expected by BootROM. -+ if (ecc_user && strength) { -+ u32 s_next = ecc_cfg->strength - 1; -+ -+ while (1) { -+ mtk_ecc_adjust_strength(snf->ecc, &s_next); -+ if (s_next >= ecc_cfg->strength) -+ break; -+ if (s_next < strength) -+ break; -+ s_next = ecc_cfg->strength - 1; -+ } -+ } -+ -+ mtd_set_ooblayout(mtd, &mtk_snand_ooblayout); -+ -+ conf->step_size = snf->caps->sector_size; -+ conf->strength = ecc_cfg->strength; -+ -+ if (ecc_cfg->strength < strength) -+ dev_warn(snf->dev, "unable to fulfill ECC of %u bits.\n", -+ strength); -+ dev_info(snf->dev, "ECC strength: %u bits per %u bytes\n", -+ ecc_cfg->strength, snf->caps->sector_size); -+ -+ return 0; -+} -+ -+static void mtk_snand_ecc_cleanup_ctx(struct nand_device *nand) -+{ -+ struct mtk_ecc_config *ecc_cfg = nand_to_ecc_ctx(nand); -+ -+ kfree(ecc_cfg); -+} -+ -+static int mtk_snand_ecc_prepare_io_req(struct nand_device *nand, -+ struct nand_page_io_req *req) -+{ -+ struct mtk_snand *snf = nand_to_mtk_snand(nand); -+ struct mtk_ecc_config *ecc_cfg = nand_to_ecc_ctx(nand); -+ int ret; -+ -+ ret = mtk_snand_setup_pagefmt(snf, nand->memorg.pagesize, -+ nand->memorg.oobsize); -+ if (ret) -+ return ret; -+ snf->autofmt = true; -+ snf->ecc_cfg = ecc_cfg; -+ return 0; -+} -+ -+static int mtk_snand_ecc_finish_io_req(struct nand_device *nand, -+ struct nand_page_io_req *req) -+{ -+ struct mtk_snand *snf = nand_to_mtk_snand(nand); -+ struct mtd_info *mtd = nanddev_to_mtd(nand); -+ -+ snf->ecc_cfg = NULL; -+ snf->autofmt = false; -+ if ((req->mode == MTD_OPS_RAW) || (req->type != NAND_PAGE_READ)) -+ return 0; -+ -+ if (snf->ecc_stats.failed) -+ mtd->ecc_stats.failed += snf->ecc_stats.failed; -+ mtd->ecc_stats.corrected += snf->ecc_stats.corrected; -+ return snf->ecc_stats.failed ? -EBADMSG : snf->ecc_stats.bitflips; -+} -+ -+static struct nand_ecc_engine_ops mtk_snfi_ecc_engine_ops = { -+ .init_ctx = mtk_snand_ecc_init_ctx, -+ .cleanup_ctx = mtk_snand_ecc_cleanup_ctx, -+ .prepare_io_req = mtk_snand_ecc_prepare_io_req, -+ .finish_io_req = mtk_snand_ecc_finish_io_req, -+}; -+ -+static void mtk_snand_read_fdm(struct mtk_snand *snf, u8 *buf) -+{ -+ u32 vall, valm; -+ u8 *oobptr = buf; -+ int i, j; -+ -+ for (i = 0; i < snf->nfi_cfg.nsectors; i++) { -+ vall = nfi_read32(snf, NFI_FDML(i)); -+ valm = nfi_read32(snf, NFI_FDMM(i)); -+ -+ for (j = 0; j < snf->caps->fdm_size; j++) -+ oobptr[j] = (j >= 4 ? valm : vall) >> ((j % 4) * 8); -+ -+ oobptr += snf->caps->fdm_size; -+ } -+} -+ -+static void mtk_snand_write_fdm(struct mtk_snand *snf, const u8 *buf) -+{ -+ u32 fdm_size = snf->caps->fdm_size; -+ const u8 *oobptr = buf; -+ u32 vall, valm; -+ int i, j; -+ -+ for (i = 0; i < snf->nfi_cfg.nsectors; i++) { -+ vall = 0; -+ valm = 0; -+ -+ for (j = 0; j < 8; j++) { -+ if (j < 4) -+ vall |= (j < fdm_size ? oobptr[j] : 0xff) -+ << (j * 8); -+ else -+ valm |= (j < fdm_size ? oobptr[j] : 0xff) -+ << ((j - 4) * 8); -+ } -+ -+ nfi_write32(snf, NFI_FDML(i), vall); -+ nfi_write32(snf, NFI_FDMM(i), valm); -+ -+ oobptr += fdm_size; -+ } -+} -+ -+static void mtk_snand_bm_swap(struct mtk_snand *snf, u8 *buf) -+{ -+ u32 buf_bbm_pos, fdm_bbm_pos; -+ -+ if (!snf->caps->bbm_swap || snf->nfi_cfg.nsectors == 1) -+ return; -+ -+ // swap [pagesize] byte on nand with the first fdm byte -+ // in the last sector. -+ buf_bbm_pos = snf->nfi_cfg.page_size - -+ (snf->nfi_cfg.nsectors - 1) * snf->nfi_cfg.spare_size; -+ fdm_bbm_pos = snf->nfi_cfg.page_size + -+ (snf->nfi_cfg.nsectors - 1) * snf->caps->fdm_size; -+ -+ swap(snf->buf[fdm_bbm_pos], buf[buf_bbm_pos]); -+} -+ -+static void mtk_snand_fdm_bm_swap(struct mtk_snand *snf) -+{ -+ u32 fdm_bbm_pos1, fdm_bbm_pos2; -+ -+ if (!snf->caps->bbm_swap || snf->nfi_cfg.nsectors == 1) -+ return; -+ -+ // swap the first fdm byte in the first and the last sector. -+ fdm_bbm_pos1 = snf->nfi_cfg.page_size; -+ fdm_bbm_pos2 = snf->nfi_cfg.page_size + -+ (snf->nfi_cfg.nsectors - 1) * snf->caps->fdm_size; -+ swap(snf->buf[fdm_bbm_pos1], snf->buf[fdm_bbm_pos2]); -+} -+ -+static int mtk_snand_read_page_cache(struct mtk_snand *snf, -+ const struct spi_mem_op *op) -+{ -+ u8 *buf = snf->buf; -+ u8 *buf_fdm = buf + snf->nfi_cfg.page_size; -+ // the address part to be sent by the controller -+ u32 op_addr = op->addr.val; -+ // where to start copying data from bounce buffer -+ u32 rd_offset = 0; -+ u32 dummy_clk = (op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth); -+ u32 op_mode = 0; -+ u32 dma_len = snf->buf_len; -+ int ret = 0; -+ u32 rd_mode, rd_bytes, val; -+ dma_addr_t buf_dma; -+ -+ if (snf->autofmt) { -+ u32 last_bit; -+ u32 mask; -+ -+ dma_len = snf->nfi_cfg.page_size; -+ op_mode = CNFG_AUTO_FMT_EN; -+ if (op->data.ecc) -+ op_mode |= CNFG_HW_ECC_EN; -+ // extract the plane bit: -+ // Find the highest bit set in (pagesize+oobsize). -+ // Bits higher than that in op->addr are kept and sent over SPI -+ // Lower bits are used as an offset for copying data from DMA -+ // bounce buffer. -+ last_bit = fls(snf->nfi_cfg.page_size + snf->nfi_cfg.oob_size); -+ mask = (1 << last_bit) - 1; -+ rd_offset = op_addr & mask; -+ op_addr &= ~mask; -+ -+ // check if we can dma to the caller memory -+ if (rd_offset == 0 && op->data.nbytes >= snf->nfi_cfg.page_size) -+ buf = op->data.buf.in; -+ } -+ mtk_snand_mac_reset(snf); -+ mtk_nfi_reset(snf); -+ -+ // command and dummy cycles -+ nfi_write32(snf, SNF_RD_CTL2, -+ (dummy_clk << DATA_READ_DUMMY_S) | -+ (op->cmd.opcode << DATA_READ_CMD_S)); -+ -+ // read address -+ nfi_write32(snf, SNF_RD_CTL3, op_addr); -+ -+ // Set read op_mode -+ if (op->data.buswidth == 4) -+ rd_mode = op->addr.buswidth == 4 ? DATA_READ_MODE_QUAD : -+ DATA_READ_MODE_X4; -+ else if (op->data.buswidth == 2) -+ rd_mode = op->addr.buswidth == 2 ? DATA_READ_MODE_DUAL : -+ DATA_READ_MODE_X2; -+ else -+ rd_mode = DATA_READ_MODE_X1; -+ rd_mode <<= DATA_READ_MODE_S; -+ nfi_rmw32(snf, SNF_MISC_CTL, DATA_READ_MODE, -+ rd_mode | DATARD_CUSTOM_EN); -+ -+ // Set bytes to read -+ rd_bytes = (snf->nfi_cfg.spare_size + snf->caps->sector_size) * -+ snf->nfi_cfg.nsectors; -+ nfi_write32(snf, SNF_MISC_CTL2, -+ (rd_bytes << PROGRAM_LOAD_BYTE_NUM_S) | rd_bytes); -+ -+ // NFI read prepare -+ nfi_write16(snf, NFI_CNFG, -+ (CNFG_OP_MODE_CUST << CNFG_OP_MODE_S) | CNFG_DMA_BURST_EN | -+ CNFG_READ_MODE | CNFG_DMA_MODE | op_mode); -+ -+ nfi_write32(snf, NFI_CON, (snf->nfi_cfg.nsectors << CON_SEC_NUM_S)); -+ -+ buf_dma = dma_map_single(snf->dev, buf, dma_len, DMA_FROM_DEVICE); -+ if (dma_mapping_error(snf->dev, buf_dma)) { -+ dev_err(snf->dev, "DMA mapping failed.\n"); -+ goto cleanup; -+ } -+ nfi_write32(snf, NFI_STRADDR, buf_dma); -+ if (op->data.ecc) { -+ snf->ecc_cfg->op = ECC_DECODE; -+ ret = mtk_ecc_enable(snf->ecc, snf->ecc_cfg); -+ if (ret) -+ goto cleanup_dma; -+ } -+ // Prepare for custom read interrupt -+ nfi_write32(snf, NFI_INTR_EN, NFI_IRQ_INTR_EN | NFI_IRQ_CUS_READ); -+ reinit_completion(&snf->op_done); -+ -+ // Trigger NFI into custom mode -+ nfi_write16(snf, NFI_CMD, NFI_CMD_DUMMY_READ); -+ -+ // Start DMA read -+ nfi_rmw32(snf, NFI_CON, 0, CON_BRD); -+ nfi_write16(snf, NFI_STRDATA, STR_DATA); -+ -+ if (!wait_for_completion_timeout( -+ &snf->op_done, usecs_to_jiffies(SNFI_POLL_INTERVAL))) { -+ dev_err(snf->dev, "DMA timed out for reading from cache.\n"); -+ ret = -ETIMEDOUT; -+ goto cleanup; -+ } -+ -+ // Wait for BUS_SEC_CNTR returning expected value -+ ret = readl_poll_timeout(snf->nfi_base + NFI_BYTELEN, val, -+ BUS_SEC_CNTR(val) >= snf->nfi_cfg.nsectors, 0, -+ SNFI_POLL_INTERVAL); -+ if (ret) { -+ dev_err(snf->dev, "Timed out waiting for BUS_SEC_CNTR\n"); -+ goto cleanup2; -+ } -+ -+ // Wait for bus becoming idle -+ ret = readl_poll_timeout(snf->nfi_base + NFI_MASTERSTA, val, -+ !(val & snf->caps->mastersta_mask), 0, -+ SNFI_POLL_INTERVAL); -+ if (ret) { -+ dev_err(snf->dev, "Timed out waiting for bus becoming idle\n"); -+ goto cleanup2; -+ } -+ -+ if (op->data.ecc) { -+ ret = mtk_ecc_wait_done(snf->ecc, ECC_DECODE); -+ if (ret) { -+ dev_err(snf->dev, "wait ecc done timeout\n"); -+ goto cleanup2; -+ } -+ // save status before disabling ecc -+ mtk_ecc_get_stats(snf->ecc, &snf->ecc_stats, -+ snf->nfi_cfg.nsectors); -+ } -+ -+ dma_unmap_single(snf->dev, buf_dma, dma_len, DMA_FROM_DEVICE); -+ -+ if (snf->autofmt) { -+ mtk_snand_read_fdm(snf, buf_fdm); -+ if (snf->caps->bbm_swap) { -+ mtk_snand_bm_swap(snf, buf); -+ mtk_snand_fdm_bm_swap(snf); -+ } -+ } -+ -+ // copy data back -+ if (nfi_read32(snf, NFI_STA) & READ_EMPTY) { -+ memset(op->data.buf.in, 0xff, op->data.nbytes); -+ snf->ecc_stats.bitflips = 0; -+ snf->ecc_stats.failed = 0; -+ snf->ecc_stats.corrected = 0; -+ } else { -+ if (buf == op->data.buf.in) { -+ u32 cap_len = snf->buf_len - snf->nfi_cfg.page_size; -+ u32 req_left = op->data.nbytes - snf->nfi_cfg.page_size; -+ -+ if (req_left) -+ memcpy(op->data.buf.in + snf->nfi_cfg.page_size, -+ buf_fdm, -+ cap_len < req_left ? cap_len : req_left); -+ } else if (rd_offset < snf->buf_len) { -+ u32 cap_len = snf->buf_len - rd_offset; -+ -+ if (op->data.nbytes < cap_len) -+ cap_len = op->data.nbytes; -+ memcpy(op->data.buf.in, snf->buf + rd_offset, cap_len); -+ } -+ } -+cleanup2: -+ if (op->data.ecc) -+ mtk_ecc_disable(snf->ecc); -+cleanup_dma: -+ // unmap dma only if any error happens. (otherwise it's done before -+ // data copying) -+ if (ret) -+ dma_unmap_single(snf->dev, buf_dma, dma_len, DMA_FROM_DEVICE); -+cleanup: -+ // Stop read -+ nfi_write32(snf, NFI_CON, 0); -+ nfi_write16(snf, NFI_CNFG, 0); -+ -+ // Clear SNF done flag -+ nfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_READ_DONE); -+ nfi_write32(snf, SNF_STA_CTL1, 0); -+ -+ // Disable interrupt -+ nfi_read32(snf, NFI_INTR_STA); -+ nfi_write32(snf, NFI_INTR_EN, 0); -+ -+ nfi_rmw32(snf, SNF_MISC_CTL, DATARD_CUSTOM_EN, 0); -+ return ret; -+} -+ -+static int mtk_snand_write_page_cache(struct mtk_snand *snf, -+ const struct spi_mem_op *op) -+{ -+ // the address part to be sent by the controller -+ u32 op_addr = op->addr.val; -+ // where to start copying data from bounce buffer -+ u32 wr_offset = 0; -+ u32 op_mode = 0; -+ int ret = 0; -+ u32 wr_mode = 0; -+ u32 dma_len = snf->buf_len; -+ u32 wr_bytes, val; -+ size_t cap_len; -+ dma_addr_t buf_dma; -+ -+ if (snf->autofmt) { -+ u32 last_bit; -+ u32 mask; -+ -+ dma_len = snf->nfi_cfg.page_size; -+ op_mode = CNFG_AUTO_FMT_EN; -+ if (op->data.ecc) -+ op_mode |= CNFG_HW_ECC_EN; -+ -+ last_bit = fls(snf->nfi_cfg.page_size + snf->nfi_cfg.oob_size); -+ mask = (1 << last_bit) - 1; -+ wr_offset = op_addr & mask; -+ op_addr &= ~mask; -+ } -+ mtk_snand_mac_reset(snf); -+ mtk_nfi_reset(snf); -+ -+ if (wr_offset) -+ memset(snf->buf, 0xff, wr_offset); -+ -+ cap_len = snf->buf_len - wr_offset; -+ if (op->data.nbytes < cap_len) -+ cap_len = op->data.nbytes; -+ memcpy(snf->buf + wr_offset, op->data.buf.out, cap_len); -+ if (snf->autofmt) { -+ if (snf->caps->bbm_swap) { -+ mtk_snand_fdm_bm_swap(snf); -+ mtk_snand_bm_swap(snf, snf->buf); -+ } -+ mtk_snand_write_fdm(snf, snf->buf + snf->nfi_cfg.page_size); -+ } -+ -+ // Command -+ nfi_write32(snf, SNF_PG_CTL1, (op->cmd.opcode << PG_LOAD_CMD_S)); -+ -+ // write address -+ nfi_write32(snf, SNF_PG_CTL2, op_addr); -+ -+ // Set read op_mode -+ if (op->data.buswidth == 4) -+ wr_mode = PG_LOAD_X4_EN; -+ -+ nfi_rmw32(snf, SNF_MISC_CTL, PG_LOAD_X4_EN, -+ wr_mode | PG_LOAD_CUSTOM_EN); -+ -+ // Set bytes to write -+ wr_bytes = (snf->nfi_cfg.spare_size + snf->caps->sector_size) * -+ snf->nfi_cfg.nsectors; -+ nfi_write32(snf, SNF_MISC_CTL2, -+ (wr_bytes << PROGRAM_LOAD_BYTE_NUM_S) | wr_bytes); -+ -+ // NFI write prepare -+ nfi_write16(snf, NFI_CNFG, -+ (CNFG_OP_MODE_PROGRAM << CNFG_OP_MODE_S) | -+ CNFG_DMA_BURST_EN | CNFG_DMA_MODE | op_mode); -+ -+ nfi_write32(snf, NFI_CON, (snf->nfi_cfg.nsectors << CON_SEC_NUM_S)); -+ buf_dma = dma_map_single(snf->dev, snf->buf, dma_len, DMA_TO_DEVICE); -+ if (dma_mapping_error(snf->dev, buf_dma)) { -+ dev_err(snf->dev, "DMA mapping failed.\n"); -+ goto cleanup; -+ } -+ nfi_write32(snf, NFI_STRADDR, buf_dma); -+ if (op->data.ecc) { -+ snf->ecc_cfg->op = ECC_ENCODE; -+ ret = mtk_ecc_enable(snf->ecc, snf->ecc_cfg); -+ if (ret) -+ goto cleanup_dma; -+ } -+ // Prepare for custom write interrupt -+ nfi_write32(snf, NFI_INTR_EN, NFI_IRQ_INTR_EN | NFI_IRQ_CUS_PG); -+ reinit_completion(&snf->op_done); -+ ; -+ -+ // Trigger NFI into custom mode -+ nfi_write16(snf, NFI_CMD, NFI_CMD_DUMMY_WRITE); -+ -+ // Start DMA write -+ nfi_rmw32(snf, NFI_CON, 0, CON_BWR); -+ nfi_write16(snf, NFI_STRDATA, STR_DATA); -+ -+ if (!wait_for_completion_timeout( -+ &snf->op_done, usecs_to_jiffies(SNFI_POLL_INTERVAL))) { -+ dev_err(snf->dev, "DMA timed out for program load.\n"); -+ ret = -ETIMEDOUT; -+ goto cleanup_ecc; -+ } -+ -+ // Wait for NFI_SEC_CNTR returning expected value -+ ret = readl_poll_timeout(snf->nfi_base + NFI_ADDRCNTR, val, -+ NFI_SEC_CNTR(val) >= snf->nfi_cfg.nsectors, 0, -+ SNFI_POLL_INTERVAL); -+ if (ret) -+ dev_err(snf->dev, "Timed out waiting for NFI_SEC_CNTR\n"); -+ -+cleanup_ecc: -+ if (op->data.ecc) -+ mtk_ecc_disable(snf->ecc); -+cleanup_dma: -+ dma_unmap_single(snf->dev, buf_dma, dma_len, DMA_TO_DEVICE); -+cleanup: -+ // Stop write -+ nfi_write32(snf, NFI_CON, 0); -+ nfi_write16(snf, NFI_CNFG, 0); -+ -+ // Clear SNF done flag -+ nfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_PG_DONE); -+ nfi_write32(snf, SNF_STA_CTL1, 0); -+ -+ // Disable interrupt -+ nfi_read32(snf, NFI_INTR_STA); -+ nfi_write32(snf, NFI_INTR_EN, 0); -+ -+ nfi_rmw32(snf, SNF_MISC_CTL, PG_LOAD_CUSTOM_EN, 0); -+ -+ return ret; -+} -+ -+/** -+ * mtk_snand_is_page_ops() - check if the op is a controller supported page op. -+ * @op spi-mem op to check -+ * -+ * Check whether op can be executed with read_from_cache or program_load -+ * mode in the controller. -+ * This controller can execute typical Read From Cache and Program Load -+ * instructions found on SPI-NAND with 2-byte address. -+ * DTR and cmd buswidth & nbytes should be checked before calling this. -+ * -+ * Return: true if the op matches the instruction template -+ */ -+static bool mtk_snand_is_page_ops(const struct spi_mem_op *op) -+{ -+ if (op->addr.nbytes != 2) -+ return false; -+ -+ if (op->addr.buswidth != 1 && op->addr.buswidth != 2 && -+ op->addr.buswidth != 4) -+ return false; -+ -+ // match read from page instructions -+ if (op->data.dir == SPI_MEM_DATA_IN) { -+ // check dummy cycle first -+ if (op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth > -+ DATA_READ_MAX_DUMMY) -+ return false; -+ // quad io / quad out -+ if ((op->addr.buswidth == 4 || op->addr.buswidth == 1) && -+ op->data.buswidth == 4) -+ return true; -+ -+ // dual io / dual out -+ if ((op->addr.buswidth == 2 || op->addr.buswidth == 1) && -+ op->data.buswidth == 2) -+ return true; -+ -+ // standard spi -+ if (op->addr.buswidth == 1 && op->data.buswidth == 1) -+ return true; -+ } else if (op->data.dir == SPI_MEM_DATA_OUT) { -+ // check dummy cycle first -+ if (op->dummy.nbytes) -+ return false; -+ // program load quad out -+ if (op->addr.buswidth == 1 && op->data.buswidth == 4) -+ return true; -+ // standard spi -+ if (op->addr.buswidth == 1 && op->data.buswidth == 1) -+ return true; -+ } -+ return false; -+} -+ -+static bool mtk_snand_supports_op(struct spi_mem *mem, -+ const struct spi_mem_op *op) -+{ -+ if (!spi_mem_default_supports_op(mem, op)) -+ return false; -+ if (op->cmd.nbytes != 1 || op->cmd.buswidth != 1) -+ return false; -+ if (mtk_snand_is_page_ops(op)) -+ return true; -+ return ((op->addr.nbytes == 0 || op->addr.buswidth == 1) && -+ (op->dummy.nbytes == 0 || op->dummy.buswidth == 1) && -+ (op->data.nbytes == 0 || op->data.buswidth == 1)); -+} -+ -+static int mtk_snand_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) -+{ -+ struct mtk_snand *ms = spi_controller_get_devdata(mem->spi->master); -+ // page ops transfer size must be exactly ((sector_size + spare_size) * -+ // nsectors). Limit the op size if the caller requests more than that. -+ // exec_op will read more than needed and discard the leftover if the -+ // caller requests less data. -+ if (mtk_snand_is_page_ops(op)) { -+ size_t l; -+ // skip adjust_op_size for page ops -+ if (ms->autofmt) -+ return 0; -+ l = ms->caps->sector_size + ms->nfi_cfg.spare_size; -+ l *= ms->nfi_cfg.nsectors; -+ if (op->data.nbytes > l) -+ op->data.nbytes = l; -+ } else { -+ size_t hl = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes; -+ -+ if (hl >= SNF_GPRAM_SIZE) -+ return -EOPNOTSUPP; -+ if (op->data.nbytes > SNF_GPRAM_SIZE - hl) -+ op->data.nbytes = SNF_GPRAM_SIZE - hl; -+ } -+ return 0; -+} -+ -+static int mtk_snand_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) -+{ -+ struct mtk_snand *ms = spi_controller_get_devdata(mem->spi->master); -+ -+ dev_dbg(ms->dev, "OP %02x ADDR %08llX@%d:%u DATA %d:%u", op->cmd.opcode, -+ op->addr.val, op->addr.buswidth, op->addr.nbytes, -+ op->data.buswidth, op->data.nbytes); -+ if (mtk_snand_is_page_ops(op)) { -+ if (op->data.dir == SPI_MEM_DATA_IN) -+ return mtk_snand_read_page_cache(ms, op); -+ else -+ return mtk_snand_write_page_cache(ms, op); -+ } else { -+ return mtk_snand_mac_io(ms, op); -+ } -+} -+ -+static const struct spi_controller_mem_ops mtk_snand_mem_ops = { -+ .adjust_op_size = mtk_snand_adjust_op_size, -+ .supports_op = mtk_snand_supports_op, -+ .exec_op = mtk_snand_exec_op, -+}; -+ -+static const struct spi_controller_mem_caps mtk_snand_mem_caps = { -+ .ecc = true, -+}; -+ -+static irqreturn_t mtk_snand_irq(int irq, void *id) -+{ -+ struct mtk_snand *snf = id; -+ u32 sta, ien; -+ -+ sta = nfi_read32(snf, NFI_INTR_STA); -+ ien = nfi_read32(snf, NFI_INTR_EN); -+ -+ if (!(sta & ien)) -+ return IRQ_NONE; -+ -+ nfi_write32(snf, NFI_INTR_EN, 0); -+ complete(&snf->op_done); -+ return IRQ_HANDLED; -+} -+ -+static const struct of_device_id mtk_snand_ids[] = { -+ { .compatible = "mediatek,mt7622-snand", .data = &mt7622_snand_caps }, -+ { .compatible = "mediatek,mt7629-snand", .data = &mt7629_snand_caps }, -+ {}, -+}; -+ -+MODULE_DEVICE_TABLE(of, mtk_snand_ids); -+ -+static int mtk_snand_enable_clk(struct mtk_snand *ms) -+{ -+ int ret; -+ -+ ret = clk_prepare_enable(ms->nfi_clk); -+ if (ret) { -+ dev_err(ms->dev, "unable to enable nfi clk\n"); -+ return ret; -+ } -+ ret = clk_prepare_enable(ms->pad_clk); -+ if (ret) { -+ dev_err(ms->dev, "unable to enable pad clk\n"); -+ goto err1; -+ } -+ return 0; -+err1: -+ clk_disable_unprepare(ms->nfi_clk); -+ return ret; -+} -+ -+static void mtk_snand_disable_clk(struct mtk_snand *ms) -+{ -+ clk_disable_unprepare(ms->pad_clk); -+ clk_disable_unprepare(ms->nfi_clk); -+} -+ -+static int mtk_snand_probe(struct platform_device *pdev) -+{ -+ struct device_node *np = pdev->dev.of_node; -+ const struct of_device_id *dev_id; -+ struct spi_controller *ctlr; -+ struct mtk_snand *ms; -+ int ret; -+ -+ dev_id = of_match_node(mtk_snand_ids, np); -+ if (!dev_id) -+ return -EINVAL; -+ -+ ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*ms)); -+ if (!ctlr) -+ return -ENOMEM; -+ platform_set_drvdata(pdev, ctlr); -+ -+ ms = spi_controller_get_devdata(ctlr); -+ -+ ms->ctlr = ctlr; -+ ms->caps = dev_id->data; -+ -+ ms->ecc = of_mtk_ecc_get(np); -+ if (IS_ERR(ms->ecc)) -+ return PTR_ERR(ms->ecc); -+ else if (!ms->ecc) -+ return -ENODEV; -+ -+ ms->nfi_base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(ms->nfi_base)) { -+ ret = PTR_ERR(ms->nfi_base); -+ goto release_ecc; -+ } -+ -+ ms->dev = &pdev->dev; -+ -+ ms->nfi_clk = devm_clk_get(&pdev->dev, "nfi_clk"); -+ if (IS_ERR(ms->nfi_clk)) { -+ ret = PTR_ERR(ms->nfi_clk); -+ dev_err(&pdev->dev, "unable to get nfi_clk, err = %d\n", ret); -+ goto release_ecc; -+ } -+ -+ ms->pad_clk = devm_clk_get(&pdev->dev, "pad_clk"); -+ if (IS_ERR(ms->pad_clk)) { -+ ret = PTR_ERR(ms->pad_clk); -+ dev_err(&pdev->dev, "unable to get pad_clk, err = %d\n", ret); -+ goto release_ecc; -+ } -+ -+ ret = mtk_snand_enable_clk(ms); -+ if (ret) -+ goto release_ecc; -+ -+ init_completion(&ms->op_done); -+ -+ ms->irq = platform_get_irq(pdev, 0); -+ if (ms->irq < 0) { -+ ret = ms->irq; -+ goto disable_clk; -+ } -+ ret = devm_request_irq(ms->dev, ms->irq, mtk_snand_irq, 0x0, -+ "mtk-snand", ms); -+ if (ret) { -+ dev_err(ms->dev, "failed to request snfi irq\n"); -+ goto disable_clk; -+ } -+ -+ ret = dma_set_mask(ms->dev, DMA_BIT_MASK(32)); -+ if (ret) { -+ dev_err(ms->dev, "failed to set dma mask\n"); -+ goto disable_clk; -+ } -+ -+ // switch to SNFI mode -+ nfi_write32(ms, SNF_CFG, SPI_MODE); -+ -+ // setup an initial page format for ops matching page_cache_op template -+ // before ECC is called. -+ ret = mtk_snand_setup_pagefmt(ms, ms->caps->sector_size, -+ ms->caps->spare_sizes[0]); -+ if (ret) { -+ dev_err(ms->dev, "failed to set initial page format\n"); -+ goto disable_clk; -+ } -+ -+ // setup ECC engine -+ ms->ecc_eng.dev = &pdev->dev; -+ ms->ecc_eng.integration = NAND_ECC_ENGINE_INTEGRATION_PIPELINED; -+ ms->ecc_eng.ops = &mtk_snfi_ecc_engine_ops; -+ ms->ecc_eng.priv = ms; -+ -+ ret = nand_ecc_register_on_host_hw_engine(&ms->ecc_eng); -+ if (ret) { -+ dev_err(&pdev->dev, "failed to register ecc engine.\n"); -+ goto disable_clk; -+ } -+ -+ ctlr->num_chipselect = 1; -+ ctlr->mem_ops = &mtk_snand_mem_ops; -+ ctlr->mem_caps = &mtk_snand_mem_caps; -+ ctlr->bits_per_word_mask = SPI_BPW_MASK(8); -+ ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD; -+ ctlr->dev.of_node = pdev->dev.of_node; -+ ret = spi_register_controller(ctlr); -+ if (ret) { -+ dev_err(&pdev->dev, "spi_register_controller failed.\n"); -+ goto disable_clk; -+ } -+ -+ return 0; -+disable_clk: -+ mtk_snand_disable_clk(ms); -+release_ecc: -+ mtk_ecc_release(ms->ecc); -+ return ret; -+} -+ -+static int mtk_snand_remove(struct platform_device *pdev) -+{ -+ struct spi_controller *ctlr = platform_get_drvdata(pdev); -+ struct mtk_snand *ms = spi_controller_get_devdata(ctlr); -+ -+ spi_unregister_controller(ctlr); -+ mtk_snand_disable_clk(ms); -+ mtk_ecc_release(ms->ecc); -+ kfree(ms->buf); -+ return 0; -+} -+ -+static struct platform_driver mtk_snand_driver = { -+ .probe = mtk_snand_probe, -+ .remove = mtk_snand_remove, -+ .driver = { -+ .name = "mtk-snand", -+ .of_match_table = mtk_snand_ids, -+ }, -+}; -+ -+module_platform_driver(mtk_snand_driver); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Chuanhong Guo "); -+MODULE_DESCRIPTION("MeidaTek SPI-NAND Flash Controller Driver"); diff --git a/target/linux/mediatek/patches-6.1/120-13-v5.19-mtd-nand-mtk-ecc-also-parse-nand-ecc-engine-if-avail.patch b/target/linux/mediatek/patches-6.1/120-13-v5.19-mtd-nand-mtk-ecc-also-parse-nand-ecc-engine-if-avail.patch deleted file mode 100644 index 01d9d12088c..00000000000 --- a/target/linux/mediatek/patches-6.1/120-13-v5.19-mtd-nand-mtk-ecc-also-parse-nand-ecc-engine-if-avail.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 433b76fa0f3ca2865841abc21538dd8077ca3edd Mon Sep 17 00:00:00 2001 -From: Chuanhong Guo -Date: Mon, 4 Apr 2022 00:05:38 +0800 -Subject: [PATCH 13/15] mtd: nand: mtk-ecc: also parse nand-ecc-engine if - available - -The recently added ECC engine support introduced a generic property -named nand-ecc-engine for ecc engine phandle. This patch adds support -for this new property. - -Signed-off-by: Chuanhong Guo -(cherry picked from commit a41f25feb6e47c1c4d8d3279ae990ccbd8dfab54) ---- - drivers/mtd/nand/ecc-mtk.c | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - ---- a/drivers/mtd/nand/ecc-mtk.c -+++ b/drivers/mtd/nand/ecc-mtk.c -@@ -279,7 +279,10 @@ struct mtk_ecc *of_mtk_ecc_get(struct de - struct mtk_ecc *ecc = NULL; - struct device_node *np; - -- np = of_parse_phandle(of_node, "ecc-engine", 0); -+ np = of_parse_phandle(of_node, "nand-ecc-engine", 0); -+ /* for backward compatibility */ -+ if (!np) -+ np = of_parse_phandle(of_node, "ecc-engine", 0); - if (np) { - ecc = mtk_ecc_get(np); - of_node_put(np); diff --git a/target/linux/mediatek/patches-6.1/120-14-v5.19-arm64-dts-mediatek-add-mtk-snfi-for-mt7622.patch b/target/linux/mediatek/patches-6.1/120-14-v5.19-arm64-dts-mediatek-add-mtk-snfi-for-mt7622.patch deleted file mode 100644 index 15d26713723..00000000000 --- a/target/linux/mediatek/patches-6.1/120-14-v5.19-arm64-dts-mediatek-add-mtk-snfi-for-mt7622.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 9ba7c246063ae43baf2e53ccc8c8b5f8d025aaaa Mon Sep 17 00:00:00 2001 -From: Chuanhong Guo -Date: Sun, 3 Apr 2022 10:19:29 +0800 -Subject: [PATCH 15/15] arm64: dts: mediatek: add mtk-snfi for mt7622 - -This patch adds a device-tree node for the MTK SPI-NAND Flash Interface -for MT7622 device tree. - -Signed-off-by: Chuanhong Guo -(cherry picked from commit 2e022641709011ef0843d0416b0f264b5fc217af) ---- - arch/arm64/boot/dts/mediatek/mt7622.dtsi | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -553,6 +553,18 @@ - status = "disabled"; - }; - -+ snfi: spi@1100d000 { -+ compatible = "mediatek,mt7622-snand"; -+ reg = <0 0x1100d000 0 0x1000>; -+ interrupts = ; -+ clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>; -+ clock-names = "nfi_clk", "pad_clk"; -+ nand-ecc-engine = <&bch>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ - bch: ecc@1100e000 { - compatible = "mediatek,mt7622-ecc"; - reg = <0 0x1100e000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.1/130-dts-mt7629-add-snand-support.patch b/target/linux/mediatek/patches-6.1/130-dts-mt7629-add-snand-support.patch index be0018a3837..82654e683c3 100644 --- a/target/linux/mediatek/patches-6.1/130-dts-mt7629-add-snand-support.patch +++ b/target/linux/mediatek/patches-6.1/130-dts-mt7629-add-snand-support.patch @@ -41,7 +41,7 @@ Signed-off-by: Xiangsheng Hou "mediatek,mt7622-spi"; --- a/arch/arm/boot/dts/mt7629-rfb.dts +++ b/arch/arm/boot/dts/mt7629-rfb.dts -@@ -254,6 +254,50 @@ +@@ -255,6 +255,50 @@ }; }; diff --git a/target/linux/mediatek/patches-6.1/131-dts-mt7622-add-snand-support.patch b/target/linux/mediatek/patches-6.1/131-dts-mt7622-add-snand-support.patch index 134e5997e25..9cfe69ebb6a 100644 --- a/target/linux/mediatek/patches-6.1/131-dts-mt7622-add-snand-support.patch +++ b/target/linux/mediatek/patches-6.1/131-dts-mt7622-add-snand-support.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -539,6 +539,65 @@ +@@ -538,6 +538,65 @@ status = "disabled"; }; diff --git a/target/linux/mediatek/patches-6.1/140-dts-fix-wmac-support-for-mt7622-rfb1.patch b/target/linux/mediatek/patches-6.1/140-dts-fix-wmac-support-for-mt7622-rfb1.patch index 8e6935b4344..b01ce97cf01 100644 --- a/target/linux/mediatek/patches-6.1/140-dts-fix-wmac-support-for-mt7622-rfb1.patch +++ b/target/linux/mediatek/patches-6.1/140-dts-fix-wmac-support-for-mt7622-rfb1.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -580,7 +580,7 @@ +@@ -579,7 +579,7 @@ reg = <0x140000 0x0080000>; }; @@ -9,7 +9,7 @@ label = "Factory"; reg = <0x1c0000 0x0100000>; }; -@@ -641,5 +641,6 @@ +@@ -640,5 +640,6 @@ &wmac { pinctrl-names = "default"; pinctrl-0 = <&wmac_pins>; diff --git a/target/linux/mediatek/patches-6.1/150-dts-mt7623-eip97-inside-secure-support.patch b/target/linux/mediatek/patches-6.1/150-dts-mt7623-eip97-inside-secure-support.patch index 5b63bf4226b..0860a22c37f 100644 --- a/target/linux/mediatek/patches-6.1/150-dts-mt7623-eip97-inside-secure-support.patch +++ b/target/linux/mediatek/patches-6.1/150-dts-mt7623-eip97-inside-secure-support.patch @@ -1,6 +1,6 @@ --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi -@@ -951,17 +951,15 @@ +@@ -984,17 +984,15 @@ }; crypto: crypto@1b240000 { diff --git a/target/linux/mediatek/patches-6.1/173-arm-dts-mt7623-add-musb-device-nodes.patch b/target/linux/mediatek/patches-6.1/173-arm-dts-mt7623-add-musb-device-nodes.patch deleted file mode 100644 index ba1d1fe202b..00000000000 --- a/target/linux/mediatek/patches-6.1/173-arm-dts-mt7623-add-musb-device-nodes.patch +++ /dev/null @@ -1,69 +0,0 @@ -From 21d106f15262f5a2ef7531636e0703ee61c33c61 Mon Sep 17 00:00:00 2001 -From: Sungbo Eo -Date: Sun, 8 Aug 2021 21:38:40 +0900 -Subject: [PATCH 2/2] arm: dts: mt7623: add musb device nodes - -MT7623 has an musb controller that is compatible with the one from MT2701. - -Signed-off-by: Sungbo Eo ---- - arch/arm/boot/dts/mt7623.dtsi | 34 ++++++++++++++++++++++++++++++++++ - arch/arm/boot/dts/mt7623a.dtsi | 4 ++++ - 2 files changed, 38 insertions(+) - ---- a/arch/arm/boot/dts/mt7623.dtsi -+++ b/arch/arm/boot/dts/mt7623.dtsi -@@ -585,6 +585,40 @@ - status = "disabled"; - }; - -+ usb0: usb@11200000 { -+ compatible = "mediatek,mt7623-musb", -+ "mediatek,mtk-musb"; -+ reg = <0 0x11200000 0 0x1000>; -+ interrupts = ; -+ interrupt-names = "mc"; -+ phys = <&u2port2 PHY_TYPE_USB2>; -+ dr_mode = "otg"; -+ clocks = <&pericfg CLK_PERI_USB0>, -+ <&pericfg CLK_PERI_USB0_MCU>, -+ <&pericfg CLK_PERI_USB_SLV>; -+ clock-names = "main","mcu","univpll"; -+ power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; -+ status = "disabled"; -+ }; -+ -+ u2phy1: t-phy@11210000 { -+ compatible = "mediatek,mt7623-tphy", -+ "mediatek,generic-tphy-v1"; -+ reg = <0 0x11210000 0 0x0800>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ status = "disabled"; -+ -+ u2port2: usb-phy@11210800 { -+ reg = <0 0x11210800 0 0x0100>; -+ clocks = <&topckgen CLK_TOP_USB_PHY48M>; -+ clock-names = "ref"; -+ #phy-cells = <1>; -+ status = "okay"; -+ }; -+ }; -+ - audsys: clock-controller@11220000 { - compatible = "mediatek,mt7623-audsys", - "mediatek,mt2701-audsys", ---- a/arch/arm/boot/dts/mt7623a.dtsi -+++ b/arch/arm/boot/dts/mt7623a.dtsi -@@ -35,6 +35,10 @@ - clock-names = "ethif"; - }; - -+&usb0 { -+ power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>; -+}; -+ - &usb1 { - power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>; - }; diff --git a/target/linux/mediatek/patches-6.1/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch b/target/linux/mediatek/patches-6.1/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch index 80ceb490d4e..5a834ac34f8 100644 --- a/target/linux/mediatek/patches-6.1/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch +++ b/target/linux/mediatek/patches-6.1/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -160,6 +160,10 @@ +@@ -156,6 +156,10 @@ switch@0 { compatible = "mediatek,mt7531"; reg = <0>; diff --git a/target/linux/mediatek/patches-6.1/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch b/target/linux/mediatek/patches-6.1/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch index 39a9770d98f..1e04d23a0e9 100644 --- a/target/linux/mediatek/patches-6.1/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch +++ b/target/linux/mediatek/patches-6.1/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch @@ -95,7 +95,7 @@ Signed-off-by: Daniel Golle --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -339,7 +339,7 @@ +@@ -346,7 +346,7 @@ #interrupt-cells = <3>; interrupt-parent = <&gic>; reg = <0 0x10310000 0 0x1000>, diff --git a/target/linux/mediatek/patches-6.1/191-v5.19-arm64-dts-mt7622-specify-the-L2-cache-topology.patch b/target/linux/mediatek/patches-6.1/191-v5.19-arm64-dts-mt7622-specify-the-L2-cache-topology.patch deleted file mode 100644 index 8851fefbb3a..00000000000 --- a/target/linux/mediatek/patches-6.1/191-v5.19-arm64-dts-mt7622-specify-the-L2-cache-topology.patch +++ /dev/null @@ -1,132 +0,0 @@ -From patchwork Thu Apr 28 22:57:55 2022 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Rui Salvaterra -X-Patchwork-Id: 12831311 -Return-Path: - -X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on - aws-us-west-2-korg-lkml-1.web.codeaurora.org -Received: from bombadil.infradead.org (bombadil.infradead.org - [198.137.202.133]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by smtp.lore.kernel.org (Postfix) with ESMTPS id 49367C433EF - for ; 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- Thu, 28 Apr 2022 15:58:06 -0700 (PDT) -From: Rui Salvaterra -To: linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, - linux-kernel@vger.kernel.org -Cc: matthias.bgg@gmail.com, ryder.lee@mediatek.com, daniel@makrotopia.org, - Rui Salvaterra -Subject: [PATCH] arm64: dts: mt7622: specify the L2 cache topology -Date: Thu, 28 Apr 2022 23:57:55 +0100 -Message-Id: <20220428225755.785153-1-rsalvaterra@gmail.com> -X-Mailer: git-send-email 2.36.0 -MIME-Version: 1.0 -X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 -X-CRM114-CacheID: sfid-20220428_155811_895571_B63D2806 -X-CRM114-Status: GOOD ( 10.27 ) -X-BeenThere: linux-arm-kernel@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: -List-Unsubscribe: - , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: - , - -Sender: "linux-arm-kernel" -Errors-To: - linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org - -On an MT7622 system, the kernel complains of not being able to detect the cache -hierarchy of CPU 0. Specify the shared L2 cache node in the device tree, in -order to fix this. - -Signed-off-by: Rui Salvaterra ---- - arch/arm64/boot/dts/mediatek/mt7622.dtsi | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -80,6 +80,7 @@ - enable-method = "psci"; - clock-frequency = <1300000000>; - cci-control-port = <&cci_control2>; -+ next-level-cache = <&L2>; - }; - - cpu1: cpu@1 { -@@ -94,6 +95,12 @@ - enable-method = "psci"; - clock-frequency = <1300000000>; - cci-control-port = <&cci_control2>; -+ next-level-cache = <&L2>; -+ }; -+ -+ L2: l2-cache { -+ compatible = "cache"; -+ cache-level = <2>; - }; - }; - diff --git a/target/linux/mediatek/patches-6.1/192-v5.19-arm64-dts-mt7622-specify-the-number-of-DMA-requests.patch b/target/linux/mediatek/patches-6.1/192-v5.19-arm64-dts-mt7622-specify-the-number-of-DMA-requests.patch deleted file mode 100644 index 4fef9aea22d..00000000000 --- a/target/linux/mediatek/patches-6.1/192-v5.19-arm64-dts-mt7622-specify-the-number-of-DMA-requests.patch +++ /dev/null @@ -1,122 +0,0 @@ -From patchwork Fri Apr 29 08:42:25 2022 -Content-Type: text/plain; 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- Fri, 29 Apr 2022 01:42:32 -0700 (PDT) -Received: from crystalwell.adg.lan (a109-49-0-175.cpe.netcabo.pt. - [109.49.0.175]) by smtp.gmail.com with ESMTPSA id - el10-20020a170907284a00b006f3ef214e32sm429064ejc.152.2022.04.29.01.42.31 - (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); - Fri, 29 Apr 2022 01:42:31 -0700 (PDT) -From: Rui Salvaterra -To: linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, - linux-kernel@vger.kernel.org -Cc: matthias.bgg@gmail.com, ryder.lee@mediatek.com, daniel@makrotopia.org, - Rui Salvaterra -Subject: [PATCH] arm64: dts: mt7622: specify the number of DMA requests -Date: Fri, 29 Apr 2022 09:42:25 +0100 -Message-Id: <20220429084225.298213-1-rsalvaterra@gmail.com> -X-Mailer: git-send-email 2.36.0 -MIME-Version: 1.0 -X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 -X-CRM114-CacheID: sfid-20220429_014236_944696_097D1E73 -X-CRM114-Status: UNSURE ( 8.85 ) -X-CRM114-Notice: Please train this message. -X-BeenThere: linux-arm-kernel@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: -List-Unsubscribe: - , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: - , - -Sender: "linux-arm-kernel" -Errors-To: - linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org - -The MT7622 device tree never bothered to specify the number of virtual DMA -channels for the HSDMA controller, always falling back to the default value of -3. Make this value explicit, in order to avoid the following dmesg notification: - -mtk_hsdma 1b007000.dma-controller: Using 3 as missing dma-requests property - -Signed-off-by: Rui Salvaterra ---- - arch/arm64/boot/dts/mediatek/mt7622.dtsi | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -942,6 +942,7 @@ - clock-names = "hsdma"; - power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>; - #dma-cells = <1>; -+ dma-requests = <3>; - }; - - pcie_mirror: pcie-mirror@10000400 { diff --git a/target/linux/mediatek/patches-6.1/200-phy-phy-mtk-tphy-Add-hifsys-support.patch b/target/linux/mediatek/patches-6.1/200-phy-phy-mtk-tphy-Add-hifsys-support.patch index cfb0556d1ef..6347533aa8f 100644 --- a/target/linux/mediatek/patches-6.1/200-phy-phy-mtk-tphy-Add-hifsys-support.patch +++ b/target/linux/mediatek/patches-6.1/200-phy-phy-mtk-tphy-Add-hifsys-support.patch @@ -9,16 +9,16 @@ Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support --- a/drivers/phy/mediatek/phy-mtk-tphy.c +++ b/drivers/phy/mediatek/phy-mtk-tphy.c -@@ -18,6 +18,8 @@ +@@ -17,6 +17,8 @@ #include #include #include +#include +#include - /* version V1 sub-banks offset base address */ - /* banks shared by multiple phys */ -@@ -311,6 +313,9 @@ + #include "phy-mtk-io.h" + +@@ -264,6 +266,9 @@ #define TPHY_CLKS_CNT 2 @@ -28,7 +28,7 @@ Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support enum mtk_phy_version { MTK_PHY_V1 = 1, MTK_PHY_V2, -@@ -377,6 +382,7 @@ struct mtk_tphy { +@@ -331,6 +336,7 @@ struct mtk_tphy { void __iomem *sif_base; /* only shared sif */ const struct mtk_phy_pdata *pdata; struct mtk_phy_instance **phys; @@ -36,7 +36,7 @@ Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support int nphys; int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */ int src_coef; /* coefficient for slew rate calibrate */ -@@ -730,6 +736,10 @@ static void pcie_phy_instance_init(struc +@@ -596,6 +602,10 @@ static void pcie_phy_instance_init(struc if (tphy->pdata->version != MTK_PHY_V1) return; @@ -44,10 +44,10 @@ Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support + regmap_update_bits(tphy->hif, HIF_SYSCFG1, + HIF_SYSCFG1_PHY2_MASK, 0); + - tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0); - tmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H); - tmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2); -@@ -1437,6 +1447,16 @@ static int mtk_tphy_probe(struct platfor + mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG0, + P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H, + FIELD_PREP(P3A_RG_XTAL_EXT_PE1H, 0x2) | +@@ -1241,6 +1251,16 @@ static int mtk_tphy_probe(struct platfor &tphy->src_coef); } diff --git a/target/linux/mediatek/patches-6.1/210-v6.1-pinctrl-mediatek-add-support-for-MT7986-SoC.patch b/target/linux/mediatek/patches-6.1/210-v6.1-pinctrl-mediatek-add-support-for-MT7986-SoC.patch deleted file mode 100644 index 0761e1da180..00000000000 --- a/target/linux/mediatek/patches-6.1/210-v6.1-pinctrl-mediatek-add-support-for-MT7986-SoC.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/drivers/pinctrl/mediatek/Kconfig -+++ b/drivers/pinctrl/mediatek/Kconfig -@@ -120,6 +120,13 @@ config PINCTRL_MT7622 - default ARM64 && ARCH_MEDIATEK - select PINCTRL_MTK_MOORE - -+config PINCTRL_MT7986 -+ bool "Mediatek MT7986 pin control" -+ depends on OF -+ depends on ARM64 || COMPILE_TEST -+ default ARM64 && ARCH_MEDIATEK -+ select PINCTRL_MTK_MOORE -+ - config PINCTRL_MT8167 - bool "Mediatek MT8167 pin control" - depends on OF ---- a/drivers/pinctrl/mediatek/Makefile -+++ b/drivers/pinctrl/mediatek/Makefile -@@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_MT6797) += pinctrl- - obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o - obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o - obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o -+obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o - obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o - obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o - obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o diff --git a/target/linux/mediatek/patches-6.1/210-v6.2-pinctrl-mt7986-allow-configuring-uart-rx-tx-and-rts-.patch b/target/linux/mediatek/patches-6.1/210-v6.2-pinctrl-mt7986-allow-configuring-uart-rx-tx-and-rts-.patch new file mode 100644 index 00000000000..3e16a533e1b --- /dev/null +++ b/target/linux/mediatek/patches-6.1/210-v6.2-pinctrl-mt7986-allow-configuring-uart-rx-tx-and-rts-.patch @@ -0,0 +1,88 @@ +From f76e8bc416bebb0f7b9f57b1247eae945421c0b9 Mon Sep 17 00:00:00 2001 +From: Sam Shih +Date: Sat, 8 Oct 2022 18:48:06 +0200 +Subject: [PATCH 1/2] pinctrl: mt7986: allow configuring uart rx/tx and rts/cts + separately + +Some mt7986 boards use uart rts/cts pins as gpio, +This patch allows to change rts/cts to gpio mode, but keep +rx/tx as UART function. + +Signed-off-by: Frank Wunderlich +Signed-off-by: Sam Shih +Link: https://lore.kernel.org/r/20221008164807.113590-1-linux@fw-web.de +Signed-off-by: Linus Walleij +--- + drivers/pinctrl/mediatek/pinctrl-mt7986.c | 32 ++++++++++++++++++----- + 1 file changed, 25 insertions(+), 7 deletions(-) + +--- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c +@@ -675,11 +675,17 @@ static int mt7986_uart1_1_funcs[] = { 4, + static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, }; + static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, }; + +-static int mt7986_uart1_2_pins[] = { 29, 30, 31, 32, }; +-static int mt7986_uart1_2_funcs[] = { 3, 3, 3, 3, }; ++static int mt7986_uart1_2_rx_tx_pins[] = { 29, 30, }; ++static int mt7986_uart1_2_rx_tx_funcs[] = { 3, 3, }; + +-static int mt7986_uart2_0_pins[] = { 29, 30, 31, 32, }; +-static int mt7986_uart2_0_funcs[] = { 4, 4, 4, 4, }; ++static int mt7986_uart1_2_cts_rts_pins[] = { 31, 32, }; ++static int mt7986_uart1_2_cts_rts_funcs[] = { 3, 3, }; ++ ++static int mt7986_uart2_0_rx_tx_pins[] = { 29, 30, }; ++static int mt7986_uart2_0_rx_tx_funcs[] = { 4, 4, }; ++ ++static int mt7986_uart2_0_cts_rts_pins[] = { 31, 32, }; ++static int mt7986_uart2_0_cts_rts_funcs[] = { 4, 4, }; + + static int mt7986_spi0_pins[] = { 33, 34, 35, 36, }; + static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, }; +@@ -708,6 +714,12 @@ static int mt7986_pcie_reset_funcs[] = { + static int mt7986_uart1_pins[] = { 42, 43, 44, 45, }; + static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, }; + ++static int mt7986_uart1_rx_tx_pins[] = { 42, 43, }; ++static int mt7986_uart1_rx_tx_funcs[] = { 1, 1, }; ++ ++static int mt7986_uart1_cts_rts_pins[] = { 44, 45, }; ++static int mt7986_uart1_cts_rts_funcs[] = { 1, 1, }; ++ + static int mt7986_uart2_pins[] = { 46, 47, 48, 49, }; + static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, }; + +@@ -749,6 +761,8 @@ static const struct group_desc mt7986_gr + PINCTRL_PIN_GROUP("wifi_led", mt7986_wifi_led), + PINCTRL_PIN_GROUP("i2c", mt7986_i2c), + PINCTRL_PIN_GROUP("uart1_0", mt7986_uart1_0), ++ PINCTRL_PIN_GROUP("uart1_rx_tx", mt7986_uart1_rx_tx), ++ PINCTRL_PIN_GROUP("uart1_cts_rts", mt7986_uart1_cts_rts), + PINCTRL_PIN_GROUP("pcie_clk", mt7986_pcie_clk), + PINCTRL_PIN_GROUP("pcie_wake", mt7986_pcie_wake), + PINCTRL_PIN_GROUP("spi1_0", mt7986_spi1_0), +@@ -760,8 +774,10 @@ static const struct group_desc mt7986_gr + PINCTRL_PIN_GROUP("spi1_1", mt7986_spi1_1), + PINCTRL_PIN_GROUP("uart1_1", mt7986_uart1_1), + PINCTRL_PIN_GROUP("spi1_2", mt7986_spi1_2), +- PINCTRL_PIN_GROUP("uart1_2", mt7986_uart1_2), +- PINCTRL_PIN_GROUP("uart2_0", mt7986_uart2_0), ++ PINCTRL_PIN_GROUP("uart1_2_rx_tx", mt7986_uart1_2_rx_tx), ++ PINCTRL_PIN_GROUP("uart1_2_cts_rts", mt7986_uart1_2_cts_rts), ++ PINCTRL_PIN_GROUP("uart2_0_rx_tx", mt7986_uart2_0_rx_tx), ++ PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7986_uart2_0_cts_rts), + PINCTRL_PIN_GROUP("spi0", mt7986_spi0), + PINCTRL_PIN_GROUP("spi0_wp_hold", mt7986_spi0_wp_hold), + PINCTRL_PIN_GROUP("uart2_1", mt7986_uart2_1), +@@ -800,7 +816,9 @@ static const char *mt7986_pwm_groups[] = + static const char *mt7986_spi_groups[] = { + "spi0", "spi0_wp_hold", "spi1_0", "spi1_1", "spi1_2", "spi1_3", }; + static const char *mt7986_uart_groups[] = { +- "uart1_0", "uart1_1", "uart1_2", "uart1_3_rx_tx", "uart1_3_cts_rts", ++ "uart1_0", "uart1_1", "uart1_rx_tx", "uart1_cts_rts", ++ "uart1_2_rx_tx", "uart1_2_cts_rts", ++ "uart1_3_rx_tx", "uart1_3_cts_rts", "uart2_0_rx_tx", "uart2_0_cts_rts", + "uart2_0", "uart2_1", "uart0", "uart1", "uart2", + }; + static const char *mt7986_wdt_groups[] = { "watchdog", }; diff --git a/target/linux/mediatek/patches-6.1/211-v5.16-clk-mediatek-Add-API-for-clock-resource-recycle.patch b/target/linux/mediatek/patches-6.1/211-v5.16-clk-mediatek-Add-API-for-clock-resource-recycle.patch deleted file mode 100644 index 15de8aa3d49..00000000000 --- a/target/linux/mediatek/patches-6.1/211-v5.16-clk-mediatek-Add-API-for-clock-resource-recycle.patch +++ /dev/null @@ -1,28 +0,0 @@ ---- a/drivers/clk/mediatek/clk-mtk.c -+++ b/drivers/clk/mediatek/clk-mtk.c -@@ -43,6 +43,15 @@ err_out: - return NULL; - } - -+void mtk_free_clk_data(struct clk_onecell_data *clk_data) -+{ -+ if (!clk_data) -+ return; -+ -+ kfree(clk_data->clks); -+ kfree(clk_data); -+} -+ - void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, - int num, struct clk_onecell_data *clk_data) - { ---- a/drivers/clk/mediatek/clk-mtk.h -+++ b/drivers/clk/mediatek/clk-mtk.h -@@ -202,6 +202,7 @@ void mtk_clk_register_dividers(const str - struct clk_onecell_data *clk_data); - - struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num); -+void mtk_free_clk_data(struct clk_onecell_data *clk_data); - - #define HAVE_RST_BAR BIT(0) - #define PLL_AO BIT(1) diff --git a/target/linux/mediatek/patches-6.1/211-v6.2-pinctrl-mediatek-add-pull_type-attribute-for-mediate.patch b/target/linux/mediatek/patches-6.1/211-v6.2-pinctrl-mediatek-add-pull_type-attribute-for-mediate.patch new file mode 100644 index 00000000000..47ded1aeb5f --- /dev/null +++ b/target/linux/mediatek/patches-6.1/211-v6.2-pinctrl-mediatek-add-pull_type-attribute-for-mediate.patch @@ -0,0 +1,100 @@ +From 822d774abbcc66b811e28c68b59b40b964ba5b46 Mon Sep 17 00:00:00 2001 +From: Sam Shih +Date: Sun, 6 Nov 2022 09:01:13 +0100 +Subject: [PATCH 2/2] pinctrl: mediatek: add pull_type attribute for mediatek + MT7986 SoC + +Commit fb34a9ae383a ("pinctrl: mediatek: support rsel feature") +add SoC specify 'pull_type' attribute for bias configuration. + +This patch add pull_type attribute to pinctrl-mt7986.c, and make +bias_set_combo and bias_get_combo available to mediatek MT7986 SoC. + +Signed-off-by: Sam Shih +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20221106080114.7426-7-linux@fw-web.de +Signed-off-by: Linus Walleij +--- + drivers/pinctrl/mediatek/pinctrl-mt7986.c | 56 +++++++++++++++++++++++ + 1 file changed, 56 insertions(+) + +--- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c +@@ -407,6 +407,60 @@ static const struct mtk_pin_field_calc m + PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x60, 0x10, 2, 1), + }; + ++static const unsigned int mt7986_pull_type[] = { ++ MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/ ++ MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/ ++ MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/ ++ MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/ ++ MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/ ++ MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/ ++ MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/ ++ MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/ ++ MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/ ++ MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/ ++ MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/ ++ MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/ ++ MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/ ++ MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/ ++ MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/ ++ MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/ ++ MTK_PULL_PU_PD_TYPE,/*100*/ ++}; ++ + static const struct mtk_pin_reg_calc mt7986_reg_cals[] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7986_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7986_pin_dir_range), +@@ -868,6 +922,7 @@ static struct mtk_pin_soc mt7986a_data = + .ies_present = false, + .base_names = mt7986_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), ++ .pull_type = mt7986_pull_type, + .bias_set_combo = mtk_pinconf_bias_set_combo, + .bias_get_combo = mtk_pinconf_bias_get_combo, + .drive_set = mtk_pinconf_drive_set_rev1, +@@ -889,6 +944,7 @@ static struct mtk_pin_soc mt7986b_data = + .ies_present = false, + .base_names = mt7986_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), ++ .pull_type = mt7986_pull_type, + .bias_set_combo = mtk_pinconf_bias_set_combo, + .bias_get_combo = mtk_pinconf_bias_get_combo, + .drive_set = mtk_pinconf_drive_set_rev1, diff --git a/target/linux/mediatek/patches-6.1/212-v5.17-clk-mediatek-add-mt7986-clock-support.patch b/target/linux/mediatek/patches-6.1/212-v5.17-clk-mediatek-add-mt7986-clock-support.patch deleted file mode 100644 index 8e2365a498e..00000000000 --- a/target/linux/mediatek/patches-6.1/212-v5.17-clk-mediatek-add-mt7986-clock-support.patch +++ /dev/null @@ -1,39 +0,0 @@ ---- a/drivers/clk/mediatek/Kconfig -+++ b/drivers/clk/mediatek/Kconfig -@@ -344,6 +344,23 @@ config COMMON_CLK_MT7629_HIFSYS - This driver supports MediaTek MT7629 HIFSYS clocks providing - to PCI-E and USB. - -+config COMMON_CLK_MT7986 -+ bool "Clock driver for MediaTek MT7986" -+ depends on ARCH_MEDIATEK || COMPILE_TEST -+ select COMMON_CLK_MEDIATEK -+ default ARCH_MEDIATEK -+ help -+ This driver supports MediaTek MT7986 basic clocks and clocks -+ required for various periperals found on MediaTek. -+ -+config COMMON_CLK_MT7986_ETHSYS -+ bool "Clock driver for MediaTek MT7986 ETHSYS" -+ depends on COMMON_CLK_MT7986 -+ default COMMON_CLK_MT7986 -+ help -+ This driver add support for clocks for Ethernet and SGMII -+ required on MediaTek MT7986 SoC. -+ - config COMMON_CLK_MT8135 - bool "Clock driver for MediaTek MT8135" - depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST ---- a/drivers/clk/mediatek/Makefile -+++ b/drivers/clk/mediatek/Makefile -@@ -46,6 +46,10 @@ obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) + - obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o - obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o - obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o -+obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-apmixed.o -+obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o -+obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o -+obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o - obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o - obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167.o - obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o diff --git a/target/linux/mediatek/patches-6.1/213-spi-mediatek-add-mt7986-spi-support.patch b/target/linux/mediatek/patches-6.1/213-spi-mediatek-add-mt7986-spi-support.patch deleted file mode 100644 index 04da1765f37..00000000000 --- a/target/linux/mediatek/patches-6.1/213-spi-mediatek-add-mt7986-spi-support.patch +++ /dev/null @@ -1,917 +0,0 @@ -From 7d99750f96fc6904d54affebdc8c9b0bfae1e9e8 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Sun, 17 Apr 2022 11:40:22 +0800 -Subject: [PATCH] spi: mediatek: backport document and driver to support mt7986 - spi design - -this patch add the support of ipm design and upgrade devicetree binding - -The patch is comming from following threads -- https://lore.kernel.org/all/20220315032411.2826-1-leilk.liu@mediatek.com/ -- https://lore.kernel.org/all/20220401071616.8874-1-leilk.liu@mediatek.com/ - -Signed-off-by: Sam Shih ---- - .../bindings/spi/mediatek,spi-mt65xx.yaml | 111 ++++ - drivers/spi/spi-mt65xx.c | 509 ++++++++++++++++-- - 2 files changed, 572 insertions(+), 48 deletions(-) - create mode 100644 Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml -@@ -0,0 +1,111 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/spi/mediatek,spi-mt65xx.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: SPI Bus controller for MediaTek ARM SoCs -+ -+maintainers: -+ - Leilk Liu -+ -+allOf: -+ - $ref: "/schemas/spi/spi-controller.yaml#" -+ -+properties: -+ compatible: -+ oneOf: -+ - items: -+ - enum: -+ - mediatek,mt7629-spi -+ - const: mediatek,mt7622-spi -+ - items: -+ - enum: -+ - mediatek,mt8516-spi -+ - const: mediatek,mt2712-spi -+ - items: -+ - enum: -+ - mediatek,mt6779-spi -+ - mediatek,mt8186-spi -+ - mediatek,mt8192-spi -+ - mediatek,mt8195-spi -+ - const: mediatek,mt6765-spi -+ - items: -+ - enum: -+ - mediatek,mt7986-spi-ipm -+ - const: mediatek,spi-ipm -+ - items: -+ - enum: -+ - mediatek,mt2701-spi -+ - mediatek,mt2712-spi -+ - mediatek,mt6589-spi -+ - mediatek,mt6765-spi -+ - mediatek,mt6893-spi -+ - mediatek,mt7622-spi -+ - mediatek,mt8135-spi -+ - mediatek,mt8173-spi -+ - mediatek,mt8183-spi -+ -+ reg: -+ maxItems: 1 -+ -+ interrupts: -+ maxItems: 1 -+ -+ clocks: -+ minItems: 3 -+ items: -+ - description: clock used for the parent clock -+ - description: clock used for the muxes clock -+ - description: clock used for the clock gate -+ - description: clock used for the AHB bus, this clock is optional -+ -+ clock-names: -+ minItems: 3 -+ items: -+ - const: parent-clk -+ - const: sel-clk -+ - const: spi-clk -+ - const: hclk -+ -+ mediatek,pad-select: -+ $ref: /schemas/types.yaml#/definitions/uint32-array -+ minItems: 1 -+ maxItems: 4 -+ items: -+ enum: [0, 1, 2, 3] -+ description: -+ specify which pins group(ck/mi/mo/cs) spi controller used. -+ This is an array. -+ -+required: -+ - compatible -+ - reg -+ - interrupts -+ - clocks -+ - clock-names -+ - '#address-cells' -+ - '#size-cells' -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ #include -+ #include -+ #include -+ #include -+ -+ spi@1100a000 { -+ compatible = "mediatek,mt8173-spi"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x1100a000 0x1000>; -+ interrupts = ; -+ clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, -+ <&topckgen CLK_TOP_SPI_SEL>, -+ <&pericfg CLK_PERI_SPI0>; -+ clock-names = "parent-clk", "sel-clk", "spi-clk"; -+ cs-gpios = <&pio 105 GPIO_ACTIVE_LOW>, <&pio 72 GPIO_ACTIVE_LOW>; -+ mediatek,pad-select = <1>, <0>; -+ }; ---- a/drivers/spi/spi-mt65xx.c -+++ b/drivers/spi/spi-mt65xx.c -@@ -12,11 +12,12 @@ - #include - #include - #include --#include -+#include - #include - #include - #include - #include -+#include - #include - - #define SPI_CFG0_REG 0x0000 -@@ -31,6 +32,7 @@ - #define SPI_CFG2_REG 0x0028 - #define SPI_TX_SRC_REG_64 0x002c - #define SPI_RX_DST_REG_64 0x0030 -+#define SPI_CFG3_IPM_REG 0x0040 - - #define SPI_CFG0_SCK_HIGH_OFFSET 0 - #define SPI_CFG0_SCK_LOW_OFFSET 8 -@@ -51,6 +53,7 @@ - #define SPI_CFG1_CS_IDLE_MASK 0xff - #define SPI_CFG1_PACKET_LOOP_MASK 0xff00 - #define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000 -+#define SPI_CFG1_IPM_PACKET_LENGTH_MASK GENMASK(31, 16) - #define SPI_CFG2_SCK_HIGH_OFFSET 0 - #define SPI_CFG2_SCK_LOW_OFFSET 16 - -@@ -71,6 +74,24 @@ - #define SPI_CMD_TX_ENDIAN BIT(15) - #define SPI_CMD_FINISH_IE BIT(16) - #define SPI_CMD_PAUSE_IE BIT(17) -+#define SPI_CMD_IPM_NONIDLE_MODE BIT(19) -+#define SPI_CMD_IPM_SPIM_LOOP BIT(21) -+#define SPI_CMD_IPM_GET_TICKDLY_OFFSET 22 -+ -+#define SPI_CMD_IPM_GET_TICKDLY_MASK GENMASK(24, 22) -+ -+#define PIN_MODE_CFG(x) ((x) / 2) -+ -+#define SPI_CFG3_IPM_HALF_DUPLEX_DIR BIT(2) -+#define SPI_CFG3_IPM_HALF_DUPLEX_EN BIT(3) -+#define SPI_CFG3_IPM_XMODE_EN BIT(4) -+#define SPI_CFG3_IPM_NODATA_FLAG BIT(5) -+#define SPI_CFG3_IPM_CMD_BYTELEN_OFFSET 8 -+#define SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET 12 -+ -+#define SPI_CFG3_IPM_CMD_PIN_MODE_MASK GENMASK(1, 0) -+#define SPI_CFG3_IPM_CMD_BYTELEN_MASK GENMASK(11, 8) -+#define SPI_CFG3_IPM_ADDR_BYTELEN_MASK GENMASK(15, 12) - - #define MT8173_SPI_MAX_PAD_SEL 3 - -@@ -81,6 +102,9 @@ - - #define MTK_SPI_MAX_FIFO_SIZE 32U - #define MTK_SPI_PACKET_SIZE 1024 -+#define MTK_SPI_IPM_PACKET_SIZE SZ_64K -+#define MTK_SPI_IPM_PACKET_LOOP SZ_256 -+ - #define MTK_SPI_32BITS_MASK (0xffffffff) - - #define DMA_ADDR_EXT_BITS (36) -@@ -96,6 +120,8 @@ struct mtk_spi_compatible { - bool dma_ext; - /* some IC no need unprepare SPI clk */ - bool no_need_unprepare; -+ /* IPM design adjust and extend register to support more features */ -+ bool ipm_design; - }; - - struct mtk_spi { -@@ -103,7 +129,7 @@ struct mtk_spi { - u32 state; - int pad_num; - u32 *pad_sel; -- struct clk *parent_clk, *sel_clk, *spi_clk; -+ struct clk *parent_clk, *sel_clk, *spi_clk, *spi_hclk; - struct spi_transfer *cur_transfer; - u32 xfer_len; - u32 num_xfered; -@@ -111,6 +137,11 @@ struct mtk_spi { - u32 tx_sgl_len, rx_sgl_len; - const struct mtk_spi_compatible *dev_comp; - u32 spi_clk_hz; -+ struct completion spimem_done; -+ bool use_spimem; -+ struct device *dev; -+ dma_addr_t tx_dma; -+ dma_addr_t rx_dma; - }; - - static const struct mtk_spi_compatible mtk_common_compat; -@@ -119,6 +150,12 @@ static const struct mtk_spi_compatible m - .must_tx = true, - }; - -+static const struct mtk_spi_compatible mtk_ipm_compat = { -+ .enhance_timing = true, -+ .dma_ext = true, -+ .ipm_design = true, -+}; -+ - static const struct mtk_spi_compatible mt6765_compat = { - .need_pad_sel = true, - .must_tx = true, -@@ -160,6 +197,9 @@ static const struct mtk_chip_config mtk_ - }; - - static const struct of_device_id mtk_spi_of_match[] = { -+ { .compatible = "mediatek,spi-ipm", -+ .data = (void *)&mtk_ipm_compat, -+ }, - { .compatible = "mediatek,mt2701-spi", - .data = (void *)&mtk_common_compat, - }, -@@ -278,12 +318,11 @@ static int mtk_spi_set_hw_cs_timing(stru - return 0; - } - --static int mtk_spi_prepare_message(struct spi_master *master, -- struct spi_message *msg) -+static int mtk_spi_hw_init(struct spi_master *master, -+ struct spi_device *spi) - { - u16 cpha, cpol; - u32 reg_val; -- struct spi_device *spi = msg->spi; - struct mtk_chip_config *chip_config = spi->controller_data; - struct mtk_spi *mdata = spi_master_get_devdata(master); - -@@ -291,6 +330,15 @@ static int mtk_spi_prepare_message(struc - cpol = spi->mode & SPI_CPOL ? 1 : 0; - - reg_val = readl(mdata->base + SPI_CMD_REG); -+ if (mdata->dev_comp->ipm_design) { -+ /* SPI transfer without idle time until packet length done */ -+ reg_val |= SPI_CMD_IPM_NONIDLE_MODE; -+ if (spi->mode & SPI_LOOP) -+ reg_val |= SPI_CMD_IPM_SPIM_LOOP; -+ else -+ reg_val &= ~SPI_CMD_IPM_SPIM_LOOP; -+ } -+ - if (cpha) - reg_val |= SPI_CMD_CPHA; - else -@@ -348,23 +396,39 @@ static int mtk_spi_prepare_message(struc - mdata->base + SPI_PAD_SEL_REG); - - /* tick delay */ -- reg_val = readl(mdata->base + SPI_CFG1_REG); - if (mdata->dev_comp->enhance_timing) { -- reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK; -- reg_val |= ((chip_config->tick_delay & 0x7) -- << SPI_CFG1_GET_TICK_DLY_OFFSET); -+ if (mdata->dev_comp->ipm_design) { -+ reg_val = readl(mdata->base + SPI_CMD_REG); -+ reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK; -+ reg_val |= ((chip_config->tick_delay & 0x7) -+ << SPI_CMD_IPM_GET_TICKDLY_OFFSET); -+ writel(reg_val, mdata->base + SPI_CMD_REG); -+ } else { -+ reg_val = readl(mdata->base + SPI_CFG1_REG); -+ reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK; -+ reg_val |= ((chip_config->tick_delay & 0x7) -+ << SPI_CFG1_GET_TICK_DLY_OFFSET); -+ writel(reg_val, mdata->base + SPI_CFG1_REG); -+ } - } else { -+ reg_val = readl(mdata->base + SPI_CFG1_REG); - reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1; - reg_val |= ((chip_config->tick_delay & 0x3) - << SPI_CFG1_GET_TICK_DLY_OFFSET_V1); -+ writel(reg_val, mdata->base + SPI_CFG1_REG); - } -- writel(reg_val, mdata->base + SPI_CFG1_REG); - - /* set hw cs timing */ - mtk_spi_set_hw_cs_timing(spi); - return 0; - } - -+static int mtk_spi_prepare_message(struct spi_master *master, -+ struct spi_message *msg) -+{ -+ return mtk_spi_hw_init(master, msg->spi); -+} -+ - static void mtk_spi_set_cs(struct spi_device *spi, bool enable) - { - u32 reg_val; -@@ -386,13 +450,13 @@ static void mtk_spi_set_cs(struct spi_de - } - - static void mtk_spi_prepare_transfer(struct spi_master *master, -- struct spi_transfer *xfer) -+ u32 speed_hz) - { - u32 div, sck_time, reg_val; - struct mtk_spi *mdata = spi_master_get_devdata(master); - -- if (xfer->speed_hz < mdata->spi_clk_hz / 2) -- div = DIV_ROUND_UP(mdata->spi_clk_hz, xfer->speed_hz); -+ if (speed_hz < mdata->spi_clk_hz / 2) -+ div = DIV_ROUND_UP(mdata->spi_clk_hz, speed_hz); - else - div = 1; - -@@ -423,12 +487,24 @@ static void mtk_spi_setup_packet(struct - u32 packet_size, packet_loop, reg_val; - struct mtk_spi *mdata = spi_master_get_devdata(master); - -- packet_size = min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE); -+ if (mdata->dev_comp->ipm_design) -+ packet_size = min_t(u32, -+ mdata->xfer_len, -+ MTK_SPI_IPM_PACKET_SIZE); -+ else -+ packet_size = min_t(u32, -+ mdata->xfer_len, -+ MTK_SPI_PACKET_SIZE); -+ - packet_loop = mdata->xfer_len / packet_size; - - reg_val = readl(mdata->base + SPI_CFG1_REG); -- reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK); -+ if (mdata->dev_comp->ipm_design) -+ reg_val &= ~SPI_CFG1_IPM_PACKET_LENGTH_MASK; -+ else -+ reg_val &= ~SPI_CFG1_PACKET_LENGTH_MASK; - reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET; -+ reg_val &= ~SPI_CFG1_PACKET_LOOP_MASK; - reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET; - writel(reg_val, mdata->base + SPI_CFG1_REG); - } -@@ -523,7 +599,7 @@ static int mtk_spi_fifo_transfer(struct - mdata->cur_transfer = xfer; - mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len); - mdata->num_xfered = 0; -- mtk_spi_prepare_transfer(master, xfer); -+ mtk_spi_prepare_transfer(master, xfer->speed_hz); - mtk_spi_setup_packet(master); - - if (xfer->tx_buf) { -@@ -556,7 +632,7 @@ static int mtk_spi_dma_transfer(struct s - mdata->cur_transfer = xfer; - mdata->num_xfered = 0; - -- mtk_spi_prepare_transfer(master, xfer); -+ mtk_spi_prepare_transfer(master, xfer->speed_hz); - - cmd = readl(mdata->base + SPI_CMD_REG); - if (xfer->tx_buf) -@@ -591,6 +667,19 @@ static int mtk_spi_transfer_one(struct s - struct spi_device *spi, - struct spi_transfer *xfer) - { -+ struct mtk_spi *mdata = spi_master_get_devdata(spi->master); -+ u32 reg_val = 0; -+ -+ /* prepare xfer direction and duplex mode */ -+ if (mdata->dev_comp->ipm_design) { -+ if (!xfer->tx_buf || !xfer->rx_buf) { -+ reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN; -+ if (xfer->rx_buf) -+ reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR; -+ } -+ writel(reg_val, mdata->base + SPI_CFG3_IPM_REG); -+ } -+ - if (master->can_dma(master, spi, xfer)) - return mtk_spi_dma_transfer(master, spi, xfer); - else -@@ -614,8 +703,9 @@ static int mtk_spi_setup(struct spi_devi - if (!spi->controller_data) - spi->controller_data = (void *)&mtk_default_chip_info; - -- if (mdata->dev_comp->need_pad_sel && gpio_is_valid(spi->cs_gpio)) -- gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); -+ if (mdata->dev_comp->need_pad_sel && spi->cs_gpiod) -+ /* CS de-asserted, gpiolib will handle inversion */ -+ gpiod_direction_output(spi->cs_gpiod, 0); - - return 0; - } -@@ -633,6 +723,12 @@ static irqreturn_t mtk_spi_interrupt(int - else - mdata->state = MTK_SPI_IDLE; - -+ /* SPI-MEM ops */ -+ if (mdata->use_spimem) { -+ complete(&mdata->spimem_done); -+ return IRQ_HANDLED; -+ } -+ - if (!master->can_dma(master, NULL, trans)) { - if (trans->rx_buf) { - cnt = mdata->xfer_len / 4; -@@ -716,6 +812,274 @@ static irqreturn_t mtk_spi_interrupt(int - return IRQ_HANDLED; - } - -+static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem, -+ struct spi_mem_op *op) -+{ -+ int opcode_len; -+ -+ if (op->data.dir != SPI_MEM_NO_DATA) { -+ opcode_len = 1 + op->addr.nbytes + op->dummy.nbytes; -+ if (opcode_len + op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) { -+ op->data.nbytes = MTK_SPI_IPM_PACKET_SIZE - opcode_len; -+ /* force data buffer dma-aligned. */ -+ op->data.nbytes -= op->data.nbytes % 4; -+ } -+ } -+ -+ return 0; -+} -+ -+static bool mtk_spi_mem_supports_op(struct spi_mem *mem, -+ const struct spi_mem_op *op) -+{ -+ if (!spi_mem_default_supports_op(mem, op)) -+ return false; -+ -+ if (op->addr.nbytes && op->dummy.nbytes && -+ op->addr.buswidth != op->dummy.buswidth) -+ return false; -+ -+ if (op->addr.nbytes + op->dummy.nbytes > 16) -+ return false; -+ -+ if (op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) { -+ if (op->data.nbytes / MTK_SPI_IPM_PACKET_SIZE > -+ MTK_SPI_IPM_PACKET_LOOP || -+ op->data.nbytes % MTK_SPI_IPM_PACKET_SIZE != 0) -+ return false; -+ } -+ -+ return true; -+} -+ -+static void mtk_spi_mem_setup_dma_xfer(struct spi_master *master, -+ const struct spi_mem_op *op) -+{ -+ struct mtk_spi *mdata = spi_master_get_devdata(master); -+ -+ writel((u32)(mdata->tx_dma & MTK_SPI_32BITS_MASK), -+ mdata->base + SPI_TX_SRC_REG); -+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT -+ if (mdata->dev_comp->dma_ext) -+ writel((u32)(mdata->tx_dma >> 32), -+ mdata->base + SPI_TX_SRC_REG_64); -+#endif -+ -+ if (op->data.dir == SPI_MEM_DATA_IN) { -+ writel((u32)(mdata->rx_dma & MTK_SPI_32BITS_MASK), -+ mdata->base + SPI_RX_DST_REG); -+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT -+ if (mdata->dev_comp->dma_ext) -+ writel((u32)(mdata->rx_dma >> 32), -+ mdata->base + SPI_RX_DST_REG_64); -+#endif -+ } -+} -+ -+static int mtk_spi_transfer_wait(struct spi_mem *mem, -+ const struct spi_mem_op *op) -+{ -+ struct mtk_spi *mdata = spi_master_get_devdata(mem->spi->master); -+ /* -+ * For each byte we wait for 8 cycles of the SPI clock. -+ * Since speed is defined in Hz and we want milliseconds, -+ * so it should be 8 * 1000. -+ */ -+ u64 ms = 8000LL; -+ -+ if (op->data.dir == SPI_MEM_NO_DATA) -+ ms *= 32; /* prevent we may get 0 for short transfers. */ -+ else -+ ms *= op->data.nbytes; -+ ms = div_u64(ms, mem->spi->max_speed_hz); -+ ms += ms + 1000; /* 1s tolerance */ -+ -+ if (ms > UINT_MAX) -+ ms = UINT_MAX; -+ -+ if (!wait_for_completion_timeout(&mdata->spimem_done, -+ msecs_to_jiffies(ms))) { -+ dev_err(mdata->dev, "spi-mem transfer timeout\n"); -+ return -ETIMEDOUT; -+ } -+ -+ return 0; -+} -+ -+static int mtk_spi_mem_exec_op(struct spi_mem *mem, -+ const struct spi_mem_op *op) -+{ -+ struct mtk_spi *mdata = spi_master_get_devdata(mem->spi->master); -+ u32 reg_val, nio, tx_size; -+ char *tx_tmp_buf, *rx_tmp_buf; -+ int ret = 0; -+ -+ mdata->use_spimem = true; -+ reinit_completion(&mdata->spimem_done); -+ -+ mtk_spi_reset(mdata); -+ mtk_spi_hw_init(mem->spi->master, mem->spi); -+ mtk_spi_prepare_transfer(mem->spi->master, mem->spi->max_speed_hz); -+ -+ reg_val = readl(mdata->base + SPI_CFG3_IPM_REG); -+ /* opcode byte len */ -+ reg_val &= ~SPI_CFG3_IPM_CMD_BYTELEN_MASK; -+ reg_val |= 1 << SPI_CFG3_IPM_CMD_BYTELEN_OFFSET; -+ -+ /* addr & dummy byte len */ -+ reg_val &= ~SPI_CFG3_IPM_ADDR_BYTELEN_MASK; -+ if (op->addr.nbytes || op->dummy.nbytes) -+ reg_val |= (op->addr.nbytes + op->dummy.nbytes) << -+ SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET; -+ -+ /* data byte len */ -+ if (op->data.dir == SPI_MEM_NO_DATA) { -+ reg_val |= SPI_CFG3_IPM_NODATA_FLAG; -+ writel(0, mdata->base + SPI_CFG1_REG); -+ } else { -+ reg_val &= ~SPI_CFG3_IPM_NODATA_FLAG; -+ mdata->xfer_len = op->data.nbytes; -+ mtk_spi_setup_packet(mem->spi->master); -+ } -+ -+ if (op->addr.nbytes || op->dummy.nbytes) { -+ if (op->addr.buswidth == 1 || op->dummy.buswidth == 1) -+ reg_val |= SPI_CFG3_IPM_XMODE_EN; -+ else -+ reg_val &= ~SPI_CFG3_IPM_XMODE_EN; -+ } -+ -+ if (op->addr.buswidth == 2 || -+ op->dummy.buswidth == 2 || -+ op->data.buswidth == 2) -+ nio = 2; -+ else if (op->addr.buswidth == 4 || -+ op->dummy.buswidth == 4 || -+ op->data.buswidth == 4) -+ nio = 4; -+ else -+ nio = 1; -+ -+ reg_val &= ~SPI_CFG3_IPM_CMD_PIN_MODE_MASK; -+ reg_val |= PIN_MODE_CFG(nio); -+ -+ reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN; -+ if (op->data.dir == SPI_MEM_DATA_IN) -+ reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR; -+ else -+ reg_val &= ~SPI_CFG3_IPM_HALF_DUPLEX_DIR; -+ writel(reg_val, mdata->base + SPI_CFG3_IPM_REG); -+ -+ tx_size = 1 + op->addr.nbytes + op->dummy.nbytes; -+ if (op->data.dir == SPI_MEM_DATA_OUT) -+ tx_size += op->data.nbytes; -+ -+ tx_size = max_t(u32, tx_size, 32); -+ -+ tx_tmp_buf = kzalloc(tx_size, GFP_KERNEL | GFP_DMA); -+ if (!tx_tmp_buf) { -+ mdata->use_spimem = false; -+ return -ENOMEM; -+ } -+ -+ tx_tmp_buf[0] = op->cmd.opcode; -+ -+ if (op->addr.nbytes) { -+ int i; -+ -+ for (i = 0; i < op->addr.nbytes; i++) -+ tx_tmp_buf[i + 1] = op->addr.val >> -+ (8 * (op->addr.nbytes - i - 1)); -+ } -+ -+ if (op->dummy.nbytes) -+ memset(tx_tmp_buf + op->addr.nbytes + 1, -+ 0xff, -+ op->dummy.nbytes); -+ -+ if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) -+ memcpy(tx_tmp_buf + op->dummy.nbytes + op->addr.nbytes + 1, -+ op->data.buf.out, -+ op->data.nbytes); -+ -+ mdata->tx_dma = dma_map_single(mdata->dev, tx_tmp_buf, -+ tx_size, DMA_TO_DEVICE); -+ if (dma_mapping_error(mdata->dev, mdata->tx_dma)) { -+ ret = -ENOMEM; -+ goto err_exit; -+ } -+ -+ if (op->data.dir == SPI_MEM_DATA_IN) { -+ if (!IS_ALIGNED((size_t)op->data.buf.in, 4)) { -+ rx_tmp_buf = kzalloc(op->data.nbytes, -+ GFP_KERNEL | GFP_DMA); -+ if (!rx_tmp_buf) { -+ ret = -ENOMEM; -+ goto unmap_tx_dma; -+ } -+ } else { -+ rx_tmp_buf = op->data.buf.in; -+ } -+ -+ mdata->rx_dma = dma_map_single(mdata->dev, -+ rx_tmp_buf, -+ op->data.nbytes, -+ DMA_FROM_DEVICE); -+ if (dma_mapping_error(mdata->dev, mdata->rx_dma)) { -+ ret = -ENOMEM; -+ goto kfree_rx_tmp_buf; -+ } -+ } -+ -+ reg_val = readl(mdata->base + SPI_CMD_REG); -+ reg_val |= SPI_CMD_TX_DMA; -+ if (op->data.dir == SPI_MEM_DATA_IN) -+ reg_val |= SPI_CMD_RX_DMA; -+ writel(reg_val, mdata->base + SPI_CMD_REG); -+ -+ mtk_spi_mem_setup_dma_xfer(mem->spi->master, op); -+ -+ mtk_spi_enable_transfer(mem->spi->master); -+ -+ /* Wait for the interrupt. */ -+ ret = mtk_spi_transfer_wait(mem, op); -+ if (ret) -+ goto unmap_rx_dma; -+ -+ /* spi disable dma */ -+ reg_val = readl(mdata->base + SPI_CMD_REG); -+ reg_val &= ~SPI_CMD_TX_DMA; -+ if (op->data.dir == SPI_MEM_DATA_IN) -+ reg_val &= ~SPI_CMD_RX_DMA; -+ writel(reg_val, mdata->base + SPI_CMD_REG); -+ -+unmap_rx_dma: -+ if (op->data.dir == SPI_MEM_DATA_IN) { -+ dma_unmap_single(mdata->dev, mdata->rx_dma, -+ op->data.nbytes, DMA_FROM_DEVICE); -+ if (!IS_ALIGNED((size_t)op->data.buf.in, 4)) -+ memcpy(op->data.buf.in, rx_tmp_buf, op->data.nbytes); -+ } -+kfree_rx_tmp_buf: -+ if (op->data.dir == SPI_MEM_DATA_IN && -+ !IS_ALIGNED((size_t)op->data.buf.in, 4)) -+ kfree(rx_tmp_buf); -+unmap_tx_dma: -+ dma_unmap_single(mdata->dev, mdata->tx_dma, -+ tx_size, DMA_TO_DEVICE); -+err_exit: -+ kfree(tx_tmp_buf); -+ mdata->use_spimem = false; -+ -+ return ret; -+} -+ -+static const struct spi_controller_mem_ops mtk_spi_mem_ops = { -+ .adjust_op_size = mtk_spi_mem_adjust_op_size, -+ .supports_op = mtk_spi_mem_supports_op, -+ .exec_op = mtk_spi_mem_exec_op, -+}; -+ - static int mtk_spi_probe(struct platform_device *pdev) - { - struct spi_master *master; -@@ -739,6 +1103,7 @@ static int mtk_spi_probe(struct platform - master->can_dma = mtk_spi_can_dma; - master->setup = mtk_spi_setup; - master->set_cs_timing = mtk_spi_set_hw_cs_timing; -+ master->use_gpio_descriptors = true; - - of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node); - if (!of_id) { -@@ -755,6 +1120,14 @@ static int mtk_spi_probe(struct platform - - if (mdata->dev_comp->must_tx) - master->flags = SPI_MASTER_MUST_TX; -+ if (mdata->dev_comp->ipm_design) -+ master->mode_bits |= SPI_LOOP; -+ -+ if (mdata->dev_comp->ipm_design) { -+ mdata->dev = &pdev->dev; -+ master->mem_ops = &mtk_spi_mem_ops; -+ init_completion(&mdata->spimem_done); -+ } - - if (mdata->dev_comp->need_pad_sel) { - mdata->pad_num = of_property_count_u32_elems( -@@ -831,25 +1204,40 @@ static int mtk_spi_probe(struct platform - goto err_put_master; - } - -+ mdata->spi_hclk = devm_clk_get_optional(&pdev->dev, "hclk"); -+ if (IS_ERR(mdata->spi_hclk)) { -+ ret = PTR_ERR(mdata->spi_hclk); -+ dev_err(&pdev->dev, "failed to get hclk: %d\n", ret); -+ goto err_put_master; -+ } -+ -+ ret = clk_prepare_enable(mdata->spi_hclk); -+ if (ret < 0) { -+ dev_err(&pdev->dev, "failed to enable hclk (%d)\n", ret); -+ goto err_put_master; -+ } -+ - ret = clk_prepare_enable(mdata->spi_clk); - if (ret < 0) { - dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret); -- goto err_put_master; -+ goto err_disable_spi_hclk; - } - - ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk); - if (ret < 0) { - dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret); -- clk_disable_unprepare(mdata->spi_clk); -- goto err_put_master; -+ goto err_disable_spi_clk; - } - - mdata->spi_clk_hz = clk_get_rate(mdata->spi_clk); - -- if (mdata->dev_comp->no_need_unprepare) -+ if (mdata->dev_comp->no_need_unprepare) { - clk_disable(mdata->spi_clk); -- else -+ clk_disable(mdata->spi_hclk); -+ } else { - clk_disable_unprepare(mdata->spi_clk); -+ clk_disable_unprepare(mdata->spi_hclk); -+ } - - pm_runtime_enable(&pdev->dev); - -@@ -862,25 +1250,12 @@ static int mtk_spi_probe(struct platform - goto err_disable_runtime_pm; - } - -- if (!master->cs_gpios && master->num_chipselect > 1) { -+ if (!master->cs_gpiods && master->num_chipselect > 1) { - dev_err(&pdev->dev, - "cs_gpios not specified and num_chipselect > 1\n"); - ret = -EINVAL; - goto err_disable_runtime_pm; - } -- -- if (master->cs_gpios) { -- for (i = 0; i < master->num_chipselect; i++) { -- ret = devm_gpio_request(&pdev->dev, -- master->cs_gpios[i], -- dev_name(&pdev->dev)); -- if (ret) { -- dev_err(&pdev->dev, -- "can't get CS GPIO %i\n", i); -- goto err_disable_runtime_pm; -- } -- } -- } - } - - if (mdata->dev_comp->dma_ext) -@@ -902,6 +1277,10 @@ static int mtk_spi_probe(struct platform - - err_disable_runtime_pm: - pm_runtime_disable(&pdev->dev); -+err_disable_spi_clk: -+ clk_disable_unprepare(mdata->spi_clk); -+err_disable_spi_hclk: -+ clk_disable_unprepare(mdata->spi_hclk); - err_put_master: - spi_master_put(master); - -@@ -920,8 +1299,10 @@ static int mtk_spi_remove(struct platfor - - mtk_spi_reset(mdata); - -- if (mdata->dev_comp->no_need_unprepare) -+ if (mdata->dev_comp->no_need_unprepare) { - clk_unprepare(mdata->spi_clk); -+ clk_unprepare(mdata->spi_hclk); -+ } - - pm_runtime_put_noidle(&pdev->dev); - pm_runtime_disable(&pdev->dev); -@@ -940,8 +1321,10 @@ static int mtk_spi_suspend(struct device - if (ret) - return ret; - -- if (!pm_runtime_suspended(dev)) -+ if (!pm_runtime_suspended(dev)) { - clk_disable_unprepare(mdata->spi_clk); -+ clk_disable_unprepare(mdata->spi_hclk); -+ } - - return ret; - } -@@ -958,11 +1341,20 @@ static int mtk_spi_resume(struct device - dev_err(dev, "failed to enable spi_clk (%d)\n", ret); - return ret; - } -+ -+ ret = clk_prepare_enable(mdata->spi_hclk); -+ if (ret < 0) { -+ dev_err(dev, "failed to enable spi_hclk (%d)\n", ret); -+ clk_disable_unprepare(mdata->spi_clk); -+ return ret; -+ } - } - - ret = spi_master_resume(master); -- if (ret < 0) -+ if (ret < 0) { - clk_disable_unprepare(mdata->spi_clk); -+ clk_disable_unprepare(mdata->spi_hclk); -+ } - - return ret; - } -@@ -974,10 +1366,13 @@ static int mtk_spi_runtime_suspend(struc - struct spi_master *master = dev_get_drvdata(dev); - struct mtk_spi *mdata = spi_master_get_devdata(master); - -- if (mdata->dev_comp->no_need_unprepare) -+ if (mdata->dev_comp->no_need_unprepare) { - clk_disable(mdata->spi_clk); -- else -+ clk_disable(mdata->spi_hclk); -+ } else { - clk_disable_unprepare(mdata->spi_clk); -+ clk_disable_unprepare(mdata->spi_hclk); -+ } - - return 0; - } -@@ -988,13 +1383,31 @@ static int mtk_spi_runtime_resume(struct - struct mtk_spi *mdata = spi_master_get_devdata(master); - int ret; - -- if (mdata->dev_comp->no_need_unprepare) -+ if (mdata->dev_comp->no_need_unprepare) { - ret = clk_enable(mdata->spi_clk); -- else -+ if (ret < 0) { -+ dev_err(dev, "failed to enable spi_clk (%d)\n", ret); -+ return ret; -+ } -+ ret = clk_enable(mdata->spi_hclk); -+ if (ret < 0) { -+ dev_err(dev, "failed to enable spi_hclk (%d)\n", ret); -+ clk_disable(mdata->spi_clk); -+ return ret; -+ } -+ } else { - ret = clk_prepare_enable(mdata->spi_clk); -- if (ret < 0) { -- dev_err(dev, "failed to enable spi_clk (%d)\n", ret); -- return ret; -+ if (ret < 0) { -+ dev_err(dev, "failed to prepare_enable spi_clk (%d)\n", ret); -+ return ret; -+ } -+ -+ ret = clk_prepare_enable(mdata->spi_hclk); -+ if (ret < 0) { -+ dev_err(dev, "failed to prepare_enable spi_hclk (%d)\n", ret); -+ clk_disable_unprepare(mdata->spi_clk); -+ return ret; -+ } - } - - return 0; diff --git a/target/linux/mediatek/patches-6.1/214-v6.3-clk-mediatek-add-mt7981-clock-support.patch b/target/linux/mediatek/patches-6.1/214-v6.3-clk-mediatek-add-mt7981-clock-support.patch deleted file mode 100644 index 631eb04092d..00000000000 --- a/target/linux/mediatek/patches-6.1/214-v6.3-clk-mediatek-add-mt7981-clock-support.patch +++ /dev/null @@ -1,39 +0,0 @@ ---- a/drivers/clk/mediatek/Kconfig -+++ b/drivers/clk/mediatek/Kconfig -@@ -344,6 +344,23 @@ config COMMON_CLK_MT7629_HIFSYS - This driver supports MediaTek MT7629 HIFSYS clocks providing - to PCI-E and USB. - -+config COMMON_CLK_MT7981 -+ bool "Clock driver for MediaTek MT7981" -+ depends on ARCH_MEDIATEK || COMPILE_TEST -+ select COMMON_CLK_MEDIATEK -+ default ARCH_MEDIATEK -+ help -+ This driver supports MediaTek MT7981 basic clocks and clocks -+ required for various periperals found on MediaTek. -+ -+config COMMON_CLK_MT7981_ETHSYS -+ bool "Clock driver for MediaTek MT7981 ETHSYS" -+ depends on COMMON_CLK_MT7981 -+ default COMMON_CLK_MT7981 -+ help -+ This driver add support for clocks for Ethernet and SGMII -+ required on MediaTek MT7981 SoC. -+ - config COMMON_CLK_MT7986 - bool "Clock driver for MediaTek MT7986" - depends on ARCH_MEDIATEK || COMPILE_TEST ---- a/drivers/clk/mediatek/Makefile -+++ b/drivers/clk/mediatek/Makefile -@@ -46,6 +46,10 @@ obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) + - obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o - obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o - obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o -+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-apmixed.o -+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-topckgen.o -+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-infracfg.o -+obj-$(CONFIG_COMMON_CLK_MT7981_ETHSYS) += clk-mt7981-eth.o - obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-apmixed.o - obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o - obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o diff --git a/target/linux/mediatek/patches-6.1/215-v6.3-pinctrl-add-mt7981-pinctrl-driver.patch b/target/linux/mediatek/patches-6.1/215-v6.3-pinctrl-add-mt7981-pinctrl-driver.patch new file mode 100644 index 00000000000..46dfa24b7b7 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/215-v6.3-pinctrl-add-mt7981-pinctrl-driver.patch @@ -0,0 +1,1094 @@ +From 6c83b2d94fcca735cf7d8aa7a55a4957eb404a9d Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Thu, 26 Jan 2023 00:34:56 +0000 +Subject: [PATCH] pinctrl: add mt7981 pinctrl driver + +Add pinctrl driver for the MediaTek MT7981 SoC, based on the driver +which can also be found the SDK. + +Signed-off-by: Daniel Golle +Reviewed-by: Rob Herring +Link: https://lore.kernel.org/r/ef5112946d16cacc67e65e439ba7b52a9950c1bb.1674693008.git.daniel@makrotopia.org +Signed-off-by: Linus Walleij +--- + drivers/pinctrl/mediatek/Kconfig | 5 + + drivers/pinctrl/mediatek/Makefile | 1 + + drivers/pinctrl/mediatek/pinctrl-mt7981.c | 1048 +++++++++++++++++++++ + 3 files changed, 1054 insertions(+) + create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7981.c + +--- a/drivers/pinctrl/mediatek/Kconfig ++++ b/drivers/pinctrl/mediatek/Kconfig +@@ -127,6 +127,11 @@ config PINCTRL_MT7622 + default ARM64 && ARCH_MEDIATEK + select PINCTRL_MTK_MOORE + ++config PINCTRL_MT7981 ++ bool "Mediatek MT7981 pin control" ++ depends on OF ++ select PINCTRL_MTK_MOORE ++ + config PINCTRL_MT7986 + bool "Mediatek MT7986 pin control" + depends on OF +--- a/drivers/pinctrl/mediatek/Makefile ++++ b/drivers/pinctrl/mediatek/Makefile +@@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_MT6797) += pinctrl- + obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o + obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o + obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o ++obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o + obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o + obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o + obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o +--- /dev/null ++++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c +@@ -0,0 +1,1048 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * The MT7981 driver based on Linux generic pinctrl binding. ++ * ++ * Copyright (C) 2020 MediaTek Inc. ++ * Author: Sam Shih ++ */ ++ ++#include "pinctrl-moore.h" ++ ++#define MT7981_PIN(_number, _name) \ ++ MTK_PIN(_number, _name, 0, _number, DRV_GRP4) ++ ++#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \ ++ PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ ++ _x_bits, 32, 0) ++ ++#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \ ++ PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ ++ _x_bits, 32, 1) ++ ++static const struct mtk_pin_field_calc mt7981_pin_mode_range[] = { ++ PIN_FIELD(0, 56, 0x300, 0x10, 0, 4), ++}; ++ ++static const struct mtk_pin_field_calc mt7981_pin_dir_range[] = { ++ PIN_FIELD(0, 56, 0x0, 0x10, 0, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7981_pin_di_range[] = { ++ PIN_FIELD(0, 56, 0x200, 0x10, 0, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7981_pin_do_range[] = { ++ PIN_FIELD(0, 56, 0x100, 0x10, 0, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7981_pin_ies_range[] = { ++ PIN_FIELD_BASE(0, 0, 1, 0x10, 0x10, 1, 1), ++ PIN_FIELD_BASE(1, 1, 1, 0x10, 0x10, 0, 1), ++ PIN_FIELD_BASE(2, 2, 5, 0x20, 0x10, 6, 1), ++ PIN_FIELD_BASE(3, 3, 4, 0x20, 0x10, 6, 1), ++ PIN_FIELD_BASE(4, 4, 4, 0x20, 0x10, 2, 1), ++ PIN_FIELD_BASE(5, 5, 4, 0x20, 0x10, 1, 1), ++ PIN_FIELD_BASE(6, 6, 4, 0x20, 0x10, 3, 1), ++ PIN_FIELD_BASE(7, 7, 4, 0x20, 0x10, 0, 1), ++ PIN_FIELD_BASE(8, 8, 4, 0x20, 0x10, 4, 1), ++ ++ PIN_FIELD_BASE(9, 9, 5, 0x20, 0x10, 9, 1), ++ PIN_FIELD_BASE(10, 10, 5, 0x20, 0x10, 8, 1), ++ PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1), ++ PIN_FIELD_BASE(12, 12, 5, 0x20, 0x10, 7, 1), ++ PIN_FIELD_BASE(13, 13, 5, 0x20, 0x10, 11, 1), ++ ++ PIN_FIELD_BASE(14, 14, 4, 0x20, 0x10, 8, 1), ++ ++ PIN_FIELD_BASE(15, 15, 2, 0x20, 0x10, 0, 1), ++ PIN_FIELD_BASE(16, 16, 2, 0x20, 0x10, 1, 1), ++ PIN_FIELD_BASE(17, 17, 2, 0x20, 0x10, 5, 1), ++ PIN_FIELD_BASE(18, 18, 2, 0x20, 0x10, 4, 1), ++ PIN_FIELD_BASE(19, 19, 2, 0x20, 0x10, 2, 1), ++ PIN_FIELD_BASE(20, 20, 2, 0x20, 0x10, 3, 1), ++ PIN_FIELD_BASE(21, 21, 2, 0x20, 0x10, 6, 1), ++ PIN_FIELD_BASE(22, 22, 2, 0x20, 0x10, 7, 1), ++ PIN_FIELD_BASE(23, 23, 2, 0x20, 0x10, 10, 1), ++ PIN_FIELD_BASE(24, 24, 2, 0x20, 0x10, 9, 1), ++ PIN_FIELD_BASE(25, 25, 2, 0x20, 0x10, 8, 1), ++ ++ PIN_FIELD_BASE(26, 26, 5, 0x20, 0x10, 0, 1), ++ PIN_FIELD_BASE(27, 27, 5, 0x20, 0x10, 4, 1), ++ PIN_FIELD_BASE(28, 28, 5, 0x20, 0x10, 3, 1), ++ PIN_FIELD_BASE(29, 29, 5, 0x20, 0x10, 1, 1), ++ PIN_FIELD_BASE(30, 30, 5, 0x20, 0x10, 2, 1), ++ PIN_FIELD_BASE(31, 31, 5, 0x20, 0x10, 5, 1), ++ ++ PIN_FIELD_BASE(32, 32, 1, 0x10, 0x10, 2, 1), ++ PIN_FIELD_BASE(33, 33, 1, 0x10, 0x10, 3, 1), ++ ++ PIN_FIELD_BASE(34, 34, 4, 0x20, 0x10, 5, 1), ++ PIN_FIELD_BASE(35, 35, 4, 0x20, 0x10, 7, 1), ++ ++ PIN_FIELD_BASE(36, 36, 3, 0x10, 0x10, 2, 1), ++ PIN_FIELD_BASE(37, 37, 3, 0x10, 0x10, 3, 1), ++ PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 0, 1), ++ PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 1, 1), ++ ++ PIN_FIELD_BASE(40, 40, 7, 0x30, 0x10, 1, 1), ++ PIN_FIELD_BASE(41, 41, 7, 0x30, 0x10, 0, 1), ++ PIN_FIELD_BASE(42, 42, 7, 0x30, 0x10, 9, 1), ++ PIN_FIELD_BASE(43, 43, 7, 0x30, 0x10, 7, 1), ++ PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1), ++ PIN_FIELD_BASE(45, 45, 7, 0x30, 0x10, 3, 1), ++ PIN_FIELD_BASE(46, 46, 7, 0x30, 0x10, 4, 1), ++ PIN_FIELD_BASE(47, 47, 7, 0x30, 0x10, 5, 1), ++ PIN_FIELD_BASE(48, 48, 7, 0x30, 0x10, 6, 1), ++ PIN_FIELD_BASE(49, 49, 7, 0x30, 0x10, 2, 1), ++ ++ PIN_FIELD_BASE(50, 50, 6, 0x10, 0x10, 0, 1), ++ PIN_FIELD_BASE(51, 51, 6, 0x10, 0x10, 2, 1), ++ PIN_FIELD_BASE(52, 52, 6, 0x10, 0x10, 3, 1), ++ PIN_FIELD_BASE(53, 53, 6, 0x10, 0x10, 4, 1), ++ PIN_FIELD_BASE(54, 54, 6, 0x10, 0x10, 5, 1), ++ PIN_FIELD_BASE(55, 55, 6, 0x10, 0x10, 6, 1), ++ PIN_FIELD_BASE(56, 56, 6, 0x10, 0x10, 1, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7981_pin_smt_range[] = { ++ PIN_FIELD_BASE(0, 0, 1, 0x60, 0x10, 1, 1), ++ PIN_FIELD_BASE(1, 1, 1, 0x60, 0x10, 0, 1), ++ PIN_FIELD_BASE(2, 2, 5, 0x90, 0x10, 6, 1), ++ PIN_FIELD_BASE(3, 3, 4, 0x80, 0x10, 6, 1), ++ PIN_FIELD_BASE(4, 4, 4, 0x80, 0x10, 2, 1), ++ PIN_FIELD_BASE(5, 5, 4, 0x80, 0x10, 1, 1), ++ PIN_FIELD_BASE(6, 6, 4, 0x80, 0x10, 3, 1), ++ PIN_FIELD_BASE(7, 7, 4, 0x80, 0x10, 0, 1), ++ PIN_FIELD_BASE(8, 8, 4, 0x80, 0x10, 4, 1), ++ ++ PIN_FIELD_BASE(9, 9, 5, 0x90, 0x10, 9, 1), ++ PIN_FIELD_BASE(10, 10, 5, 0x90, 0x10, 8, 1), ++ PIN_FIELD_BASE(11, 11, 5, 0x90, 0x10, 10, 1), ++ PIN_FIELD_BASE(12, 12, 5, 0x90, 0x10, 7, 1), ++ PIN_FIELD_BASE(13, 13, 5, 0x90, 0x10, 11, 1), ++ ++ PIN_FIELD_BASE(14, 14, 4, 0x80, 0x10, 8, 1), ++ ++ PIN_FIELD_BASE(15, 15, 2, 0x90, 0x10, 0, 1), ++ PIN_FIELD_BASE(16, 16, 2, 0x90, 0x10, 1, 1), ++ PIN_FIELD_BASE(17, 17, 2, 0x90, 0x10, 5, 1), ++ PIN_FIELD_BASE(18, 18, 2, 0x90, 0x10, 4, 1), ++ PIN_FIELD_BASE(19, 19, 2, 0x90, 0x10, 2, 1), ++ PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1), ++ PIN_FIELD_BASE(21, 21, 2, 0x90, 0x10, 6, 1), ++ PIN_FIELD_BASE(22, 22, 2, 0x90, 0x10, 7, 1), ++ PIN_FIELD_BASE(23, 23, 2, 0x90, 0x10, 10, 1), ++ PIN_FIELD_BASE(24, 24, 2, 0x90, 0x10, 9, 1), ++ PIN_FIELD_BASE(25, 25, 2, 0x90, 0x10, 8, 1), ++ ++ PIN_FIELD_BASE(26, 26, 5, 0x90, 0x10, 0, 1), ++ PIN_FIELD_BASE(27, 27, 5, 0x90, 0x10, 4, 1), ++ PIN_FIELD_BASE(28, 28, 5, 0x90, 0x10, 3, 1), ++ PIN_FIELD_BASE(29, 29, 5, 0x90, 0x10, 1, 1), ++ PIN_FIELD_BASE(30, 30, 5, 0x90, 0x10, 2, 1), ++ PIN_FIELD_BASE(31, 31, 5, 0x90, 0x10, 5, 1), ++ ++ PIN_FIELD_BASE(32, 32, 1, 0x60, 0x10, 2, 1), ++ PIN_FIELD_BASE(33, 33, 1, 0x60, 0x10, 3, 1), ++ ++ PIN_FIELD_BASE(34, 34, 4, 0x80, 0x10, 5, 1), ++ PIN_FIELD_BASE(35, 35, 4, 0x80, 0x10, 7, 1), ++ ++ PIN_FIELD_BASE(36, 36, 3, 0x60, 0x10, 2, 1), ++ PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 3, 1), ++ PIN_FIELD_BASE(38, 38, 3, 0x60, 0x10, 0, 1), ++ PIN_FIELD_BASE(39, 39, 3, 0x60, 0x10, 1, 1), ++ ++ PIN_FIELD_BASE(40, 40, 7, 0x70, 0x10, 1, 1), ++ PIN_FIELD_BASE(41, 41, 7, 0x70, 0x10, 0, 1), ++ PIN_FIELD_BASE(42, 42, 7, 0x70, 0x10, 9, 1), ++ PIN_FIELD_BASE(43, 43, 7, 0x70, 0x10, 7, 1), ++ PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1), ++ PIN_FIELD_BASE(45, 45, 7, 0x70, 0x10, 3, 1), ++ PIN_FIELD_BASE(46, 46, 7, 0x70, 0x10, 4, 1), ++ PIN_FIELD_BASE(47, 47, 7, 0x70, 0x10, 5, 1), ++ PIN_FIELD_BASE(48, 48, 7, 0x70, 0x10, 6, 1), ++ PIN_FIELD_BASE(49, 49, 7, 0x70, 0x10, 2, 1), ++ ++ PIN_FIELD_BASE(50, 50, 6, 0x50, 0x10, 0, 1), ++ PIN_FIELD_BASE(51, 51, 6, 0x50, 0x10, 2, 1), ++ PIN_FIELD_BASE(52, 52, 6, 0x50, 0x10, 3, 1), ++ PIN_FIELD_BASE(53, 53, 6, 0x50, 0x10, 4, 1), ++ PIN_FIELD_BASE(54, 54, 6, 0x50, 0x10, 5, 1), ++ PIN_FIELD_BASE(55, 55, 6, 0x50, 0x10, 6, 1), ++ PIN_FIELD_BASE(56, 56, 6, 0x50, 0x10, 1, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7981_pin_pu_range[] = { ++ PIN_FIELD_BASE(40, 40, 7, 0x50, 0x10, 1, 1), ++ PIN_FIELD_BASE(41, 41, 7, 0x50, 0x10, 0, 1), ++ PIN_FIELD_BASE(42, 42, 7, 0x50, 0x10, 9, 1), ++ PIN_FIELD_BASE(43, 43, 7, 0x50, 0x10, 7, 1), ++ PIN_FIELD_BASE(44, 44, 7, 0x50, 0x10, 8, 1), ++ PIN_FIELD_BASE(45, 45, 7, 0x50, 0x10, 3, 1), ++ PIN_FIELD_BASE(46, 46, 7, 0x50, 0x10, 4, 1), ++ PIN_FIELD_BASE(47, 47, 7, 0x50, 0x10, 5, 1), ++ PIN_FIELD_BASE(48, 48, 7, 0x50, 0x10, 6, 1), ++ PIN_FIELD_BASE(49, 49, 7, 0x50, 0x10, 2, 1), ++ ++ PIN_FIELD_BASE(50, 50, 6, 0x30, 0x10, 0, 1), ++ PIN_FIELD_BASE(51, 51, 6, 0x30, 0x10, 2, 1), ++ PIN_FIELD_BASE(52, 52, 6, 0x30, 0x10, 3, 1), ++ PIN_FIELD_BASE(53, 53, 6, 0x30, 0x10, 4, 1), ++ PIN_FIELD_BASE(54, 54, 6, 0x30, 0x10, 5, 1), ++ PIN_FIELD_BASE(55, 55, 6, 0x30, 0x10, 6, 1), ++ PIN_FIELD_BASE(56, 56, 6, 0x30, 0x10, 1, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7981_pin_pd_range[] = { ++ PIN_FIELD_BASE(40, 40, 7, 0x40, 0x10, 1, 1), ++ PIN_FIELD_BASE(41, 41, 7, 0x40, 0x10, 0, 1), ++ PIN_FIELD_BASE(42, 42, 7, 0x40, 0x10, 9, 1), ++ PIN_FIELD_BASE(43, 43, 7, 0x40, 0x10, 7, 1), ++ PIN_FIELD_BASE(44, 44, 7, 0x40, 0x10, 8, 1), ++ PIN_FIELD_BASE(45, 45, 7, 0x40, 0x10, 3, 1), ++ PIN_FIELD_BASE(46, 46, 7, 0x40, 0x10, 4, 1), ++ PIN_FIELD_BASE(47, 47, 7, 0x40, 0x10, 5, 1), ++ PIN_FIELD_BASE(48, 48, 7, 0x40, 0x10, 6, 1), ++ PIN_FIELD_BASE(49, 49, 7, 0x40, 0x10, 2, 1), ++ ++ PIN_FIELD_BASE(50, 50, 6, 0x20, 0x10, 0, 1), ++ PIN_FIELD_BASE(51, 51, 6, 0x20, 0x10, 2, 1), ++ PIN_FIELD_BASE(52, 52, 6, 0x20, 0x10, 3, 1), ++ PIN_FIELD_BASE(53, 53, 6, 0x20, 0x10, 4, 1), ++ PIN_FIELD_BASE(54, 54, 6, 0x20, 0x10, 5, 1), ++ PIN_FIELD_BASE(55, 55, 6, 0x20, 0x10, 6, 1), ++ PIN_FIELD_BASE(56, 56, 6, 0x20, 0x10, 1, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7981_pin_drv_range[] = { ++ PIN_FIELD_BASE(0, 0, 1, 0x00, 0x10, 3, 3), ++ PIN_FIELD_BASE(1, 1, 1, 0x00, 0x10, 0, 3), ++ ++ PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 18, 3), ++ ++ PIN_FIELD_BASE(3, 3, 4, 0x00, 0x10, 18, 1), ++ PIN_FIELD_BASE(4, 4, 4, 0x00, 0x10, 6, 1), ++ PIN_FIELD_BASE(5, 5, 4, 0x00, 0x10, 3, 3), ++ PIN_FIELD_BASE(6, 6, 4, 0x00, 0x10, 9, 3), ++ PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 0, 3), ++ PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 12, 3), ++ ++ PIN_FIELD_BASE(9, 9, 5, 0x00, 0x10, 27, 3), ++ PIN_FIELD_BASE(10, 10, 5, 0x00, 0x10, 24, 3), ++ PIN_FIELD_BASE(11, 11, 5, 0x00, 0x10, 0, 3), ++ PIN_FIELD_BASE(12, 12, 5, 0x00, 0x10, 21, 3), ++ PIN_FIELD_BASE(13, 13, 5, 0x00, 0x10, 3, 3), ++ ++ PIN_FIELD_BASE(14, 14, 4, 0x00, 0x10, 27, 3), ++ ++ PIN_FIELD_BASE(15, 15, 2, 0x00, 0x10, 0, 3), ++ PIN_FIELD_BASE(16, 16, 2, 0x00, 0x10, 3, 3), ++ PIN_FIELD_BASE(17, 17, 2, 0x00, 0x10, 15, 3), ++ PIN_FIELD_BASE(18, 18, 2, 0x00, 0x10, 12, 3), ++ PIN_FIELD_BASE(19, 19, 2, 0x00, 0x10, 6, 3), ++ PIN_FIELD_BASE(20, 20, 2, 0x00, 0x10, 9, 3), ++ PIN_FIELD_BASE(21, 21, 2, 0x00, 0x10, 18, 3), ++ PIN_FIELD_BASE(22, 22, 2, 0x00, 0x10, 21, 3), ++ PIN_FIELD_BASE(23, 23, 2, 0x00, 0x10, 0, 3), ++ PIN_FIELD_BASE(24, 24, 2, 0x00, 0x10, 27, 3), ++ PIN_FIELD_BASE(25, 25, 2, 0x00, 0x10, 24, 3), ++ ++ PIN_FIELD_BASE(26, 26, 5, 0x00, 0x10, 0, 3), ++ PIN_FIELD_BASE(27, 27, 5, 0x00, 0x10, 12, 3), ++ PIN_FIELD_BASE(28, 28, 5, 0x00, 0x10, 9, 3), ++ PIN_FIELD_BASE(29, 29, 5, 0x00, 0x10, 3, 3), ++ PIN_FIELD_BASE(30, 30, 5, 0x00, 0x10, 6, 3), ++ PIN_FIELD_BASE(31, 31, 5, 0x00, 0x10, 15, 3), ++ ++ PIN_FIELD_BASE(32, 32, 1, 0x00, 0x10, 9, 3), ++ PIN_FIELD_BASE(33, 33, 1, 0x00, 0x10, 12, 3), ++ ++ PIN_FIELD_BASE(34, 34, 4, 0x00, 0x10, 15, 3), ++ PIN_FIELD_BASE(35, 35, 4, 0x00, 0x10, 21, 3), ++ ++ PIN_FIELD_BASE(36, 36, 3, 0x00, 0x10, 6, 3), ++ PIN_FIELD_BASE(37, 37, 3, 0x00, 0x10, 9, 3), ++ PIN_FIELD_BASE(38, 38, 3, 0x00, 0x10, 0, 3), ++ PIN_FIELD_BASE(39, 39, 3, 0x00, 0x10, 3, 3), ++ ++ PIN_FIELD_BASE(40, 40, 7, 0x00, 0x10, 3, 3), ++ PIN_FIELD_BASE(41, 41, 7, 0x00, 0x10, 0, 3), ++ PIN_FIELD_BASE(42, 42, 7, 0x00, 0x10, 27, 3), ++ PIN_FIELD_BASE(43, 43, 7, 0x00, 0x10, 21, 3), ++ PIN_FIELD_BASE(44, 44, 7, 0x00, 0x10, 24, 3), ++ PIN_FIELD_BASE(45, 45, 7, 0x00, 0x10, 9, 3), ++ PIN_FIELD_BASE(46, 46, 7, 0x00, 0x10, 12, 3), ++ PIN_FIELD_BASE(47, 47, 7, 0x00, 0x10, 15, 3), ++ PIN_FIELD_BASE(48, 48, 7, 0x00, 0x10, 18, 3), ++ PIN_FIELD_BASE(49, 49, 7, 0x00, 0x10, 6, 3), ++ ++ PIN_FIELD_BASE(50, 50, 6, 0x00, 0x10, 0, 3), ++ PIN_FIELD_BASE(51, 51, 6, 0x00, 0x10, 6, 3), ++ PIN_FIELD_BASE(52, 52, 6, 0x00, 0x10, 9, 3), ++ PIN_FIELD_BASE(53, 53, 6, 0x00, 0x10, 12, 3), ++ PIN_FIELD_BASE(54, 54, 6, 0x00, 0x10, 15, 3), ++ PIN_FIELD_BASE(55, 55, 6, 0x00, 0x10, 18, 3), ++ PIN_FIELD_BASE(56, 56, 6, 0x00, 0x10, 3, 3), ++}; ++ ++static const struct mtk_pin_field_calc mt7981_pin_pupd_range[] = { ++ PIN_FIELD_BASE(0, 0, 1, 0x20, 0x10, 1, 1), ++ PIN_FIELD_BASE(1, 1, 1, 0x20, 0x10, 0, 1), ++ PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 6, 1), ++ PIN_FIELD_BASE(3, 3, 4, 0x30, 0x10, 6, 1), ++ PIN_FIELD_BASE(4, 4, 4, 0x30, 0x10, 2, 1), ++ PIN_FIELD_BASE(5, 5, 4, 0x30, 0x10, 1, 1), ++ PIN_FIELD_BASE(6, 6, 4, 0x30, 0x10, 3, 1), ++ PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 0, 1), ++ PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 4, 1), ++ ++ PIN_FIELD_BASE(9, 9, 5, 0x30, 0x10, 9, 1), ++ PIN_FIELD_BASE(10, 10, 5, 0x30, 0x10, 8, 1), ++ PIN_FIELD_BASE(11, 11, 5, 0x30, 0x10, 10, 1), ++ PIN_FIELD_BASE(12, 12, 5, 0x30, 0x10, 7, 1), ++ PIN_FIELD_BASE(13, 13, 5, 0x30, 0x10, 11, 1), ++ ++ PIN_FIELD_BASE(14, 14, 4, 0x30, 0x10, 8, 1), ++ ++ PIN_FIELD_BASE(15, 15, 2, 0x30, 0x10, 0, 1), ++ PIN_FIELD_BASE(16, 16, 2, 0x30, 0x10, 1, 1), ++ PIN_FIELD_BASE(17, 17, 2, 0x30, 0x10, 5, 1), ++ PIN_FIELD_BASE(18, 18, 2, 0x30, 0x10, 4, 1), ++ PIN_FIELD_BASE(19, 19, 2, 0x30, 0x10, 2, 1), ++ PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1), ++ PIN_FIELD_BASE(21, 21, 2, 0x30, 0x10, 6, 1), ++ PIN_FIELD_BASE(22, 22, 2, 0x30, 0x10, 7, 1), ++ PIN_FIELD_BASE(23, 23, 2, 0x30, 0x10, 10, 1), ++ PIN_FIELD_BASE(24, 24, 2, 0x30, 0x10, 9, 1), ++ PIN_FIELD_BASE(25, 25, 2, 0x30, 0x10, 8, 1), ++ ++ PIN_FIELD_BASE(26, 26, 5, 0x30, 0x10, 0, 1), ++ PIN_FIELD_BASE(27, 27, 5, 0x30, 0x10, 4, 1), ++ PIN_FIELD_BASE(28, 28, 5, 0x30, 0x10, 3, 1), ++ PIN_FIELD_BASE(29, 29, 5, 0x30, 0x10, 1, 1), ++ PIN_FIELD_BASE(30, 30, 5, 0x30, 0x10, 2, 1), ++ PIN_FIELD_BASE(31, 31, 5, 0x30, 0x10, 5, 1), ++ ++ PIN_FIELD_BASE(32, 32, 1, 0x20, 0x10, 2, 1), ++ PIN_FIELD_BASE(33, 33, 1, 0x20, 0x10, 3, 1), ++ ++ PIN_FIELD_BASE(34, 34, 4, 0x30, 0x10, 5, 1), ++ PIN_FIELD_BASE(35, 35, 4, 0x30, 0x10, 7, 1), ++ ++ PIN_FIELD_BASE(36, 36, 3, 0x20, 0x10, 2, 1), ++ PIN_FIELD_BASE(37, 37, 3, 0x20, 0x10, 3, 1), ++ PIN_FIELD_BASE(38, 38, 3, 0x20, 0x10, 0, 1), ++ PIN_FIELD_BASE(39, 39, 3, 0x20, 0x10, 1, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7981_pin_r0_range[] = { ++ PIN_FIELD_BASE(0, 0, 1, 0x30, 0x10, 1, 1), ++ PIN_FIELD_BASE(1, 1, 1, 0x30, 0x10, 0, 1), ++ PIN_FIELD_BASE(2, 2, 5, 0x40, 0x10, 6, 1), ++ PIN_FIELD_BASE(3, 3, 4, 0x40, 0x10, 6, 1), ++ PIN_FIELD_BASE(4, 4, 4, 0x40, 0x10, 2, 1), ++ PIN_FIELD_BASE(5, 5, 4, 0x40, 0x10, 1, 1), ++ PIN_FIELD_BASE(6, 6, 4, 0x40, 0x10, 3, 1), ++ PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 0, 1), ++ PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1), ++ ++ PIN_FIELD_BASE(9, 9, 5, 0x40, 0x10, 9, 1), ++ PIN_FIELD_BASE(10, 10, 5, 0x40, 0x10, 8, 1), ++ PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1), ++ PIN_FIELD_BASE(12, 12, 5, 0x40, 0x10, 7, 1), ++ PIN_FIELD_BASE(13, 13, 5, 0x40, 0x10, 11, 1), ++ ++ PIN_FIELD_BASE(14, 14, 4, 0x40, 0x10, 8, 1), ++ ++ PIN_FIELD_BASE(15, 15, 2, 0x40, 0x10, 0, 1), ++ PIN_FIELD_BASE(16, 16, 2, 0x40, 0x10, 1, 1), ++ PIN_FIELD_BASE(17, 17, 2, 0x40, 0x10, 5, 1), ++ PIN_FIELD_BASE(18, 18, 2, 0x40, 0x10, 4, 1), ++ PIN_FIELD_BASE(19, 19, 2, 0x40, 0x10, 2, 1), ++ PIN_FIELD_BASE(20, 20, 2, 0x40, 0x10, 3, 1), ++ PIN_FIELD_BASE(21, 21, 2, 0x40, 0x10, 6, 1), ++ PIN_FIELD_BASE(22, 22, 2, 0x40, 0x10, 7, 1), ++ PIN_FIELD_BASE(23, 23, 2, 0x40, 0x10, 10, 1), ++ PIN_FIELD_BASE(24, 24, 2, 0x40, 0x10, 9, 1), ++ PIN_FIELD_BASE(25, 25, 2, 0x40, 0x10, 8, 1), ++ ++ PIN_FIELD_BASE(26, 26, 5, 0x40, 0x10, 0, 1), ++ PIN_FIELD_BASE(27, 27, 5, 0x40, 0x10, 4, 1), ++ PIN_FIELD_BASE(28, 28, 5, 0x40, 0x10, 3, 1), ++ PIN_FIELD_BASE(29, 29, 5, 0x40, 0x10, 1, 1), ++ PIN_FIELD_BASE(30, 30, 5, 0x40, 0x10, 2, 1), ++ PIN_FIELD_BASE(31, 31, 5, 0x40, 0x10, 5, 1), ++ ++ PIN_FIELD_BASE(32, 32, 1, 0x30, 0x10, 2, 1), ++ PIN_FIELD_BASE(33, 33, 1, 0x30, 0x10, 3, 1), ++ ++ PIN_FIELD_BASE(34, 34, 4, 0x40, 0x10, 5, 1), ++ PIN_FIELD_BASE(35, 35, 4, 0x40, 0x10, 7, 1), ++ ++ PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 2, 1), ++ PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 3, 1), ++ PIN_FIELD_BASE(38, 38, 3, 0x30, 0x10, 0, 1), ++ PIN_FIELD_BASE(39, 39, 3, 0x30, 0x10, 1, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7981_pin_r1_range[] = { ++ PIN_FIELD_BASE(0, 0, 1, 0x40, 0x10, 1, 1), ++ PIN_FIELD_BASE(1, 1, 1, 0x40, 0x10, 0, 1), ++ PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 6, 1), ++ PIN_FIELD_BASE(3, 3, 4, 0x50, 0x10, 6, 1), ++ PIN_FIELD_BASE(4, 4, 4, 0x50, 0x10, 2, 1), ++ PIN_FIELD_BASE(5, 5, 4, 0x50, 0x10, 1, 1), ++ PIN_FIELD_BASE(6, 6, 4, 0x50, 0x10, 3, 1), ++ PIN_FIELD_BASE(7, 7, 4, 0x50, 0x10, 0, 1), ++ PIN_FIELD_BASE(8, 8, 4, 0x50, 0x10, 4, 1), ++ ++ PIN_FIELD_BASE(9, 9, 5, 0x50, 0x10, 9, 1), ++ PIN_FIELD_BASE(10, 10, 5, 0x50, 0x10, 8, 1), ++ PIN_FIELD_BASE(11, 11, 5, 0x50, 0x10, 10, 1), ++ PIN_FIELD_BASE(12, 12, 5, 0x50, 0x10, 7, 1), ++ PIN_FIELD_BASE(13, 13, 5, 0x50, 0x10, 11, 1), ++ ++ PIN_FIELD_BASE(14, 14, 4, 0x50, 0x10, 8, 1), ++ ++ PIN_FIELD_BASE(15, 15, 2, 0x50, 0x10, 0, 1), ++ PIN_FIELD_BASE(16, 16, 2, 0x50, 0x10, 1, 1), ++ PIN_FIELD_BASE(17, 17, 2, 0x50, 0x10, 5, 1), ++ PIN_FIELD_BASE(18, 18, 2, 0x50, 0x10, 4, 1), ++ PIN_FIELD_BASE(19, 19, 2, 0x50, 0x10, 2, 1), ++ PIN_FIELD_BASE(20, 20, 2, 0x50, 0x10, 3, 1), ++ PIN_FIELD_BASE(21, 21, 2, 0x50, 0x10, 6, 1), ++ PIN_FIELD_BASE(22, 22, 2, 0x50, 0x10, 7, 1), ++ PIN_FIELD_BASE(23, 23, 2, 0x50, 0x10, 10, 1), ++ PIN_FIELD_BASE(24, 24, 2, 0x50, 0x10, 9, 1), ++ PIN_FIELD_BASE(25, 25, 2, 0x50, 0x10, 8, 1), ++ ++ PIN_FIELD_BASE(26, 26, 5, 0x50, 0x10, 0, 1), ++ PIN_FIELD_BASE(27, 27, 5, 0x50, 0x10, 4, 1), ++ PIN_FIELD_BASE(28, 28, 5, 0x50, 0x10, 3, 1), ++ PIN_FIELD_BASE(29, 29, 5, 0x50, 0x10, 1, 1), ++ PIN_FIELD_BASE(30, 30, 5, 0x50, 0x10, 2, 1), ++ PIN_FIELD_BASE(31, 31, 5, 0x50, 0x10, 5, 1), ++ ++ PIN_FIELD_BASE(32, 32, 1, 0x40, 0x10, 2, 1), ++ PIN_FIELD_BASE(33, 33, 1, 0x40, 0x10, 3, 1), ++ ++ PIN_FIELD_BASE(34, 34, 4, 0x50, 0x10, 5, 1), ++ PIN_FIELD_BASE(35, 35, 4, 0x50, 0x10, 7, 1), ++ ++ PIN_FIELD_BASE(36, 36, 3, 0x40, 0x10, 2, 1), ++ PIN_FIELD_BASE(37, 37, 3, 0x40, 0x10, 3, 1), ++ PIN_FIELD_BASE(38, 38, 3, 0x40, 0x10, 0, 1), ++ PIN_FIELD_BASE(39, 39, 3, 0x40, 0x10, 1, 1), ++}; ++ ++static const unsigned int mt7981_pull_type[] = { ++ MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/ ++ MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/ ++ MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/ ++ MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/ ++ MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/ ++ MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/ ++ MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/ ++ MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/ ++ MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/ ++ MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/ ++ MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/ ++ MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/ ++ MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/ ++ MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/ ++ MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/ ++ MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/ ++ MTK_PULL_PU_PD_TYPE,/*100*/ ++}; ++ ++static const struct mtk_pin_reg_calc mt7981_reg_cals[] = { ++ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7981_pin_mode_range), ++ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7981_pin_dir_range), ++ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7981_pin_di_range), ++ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7981_pin_do_range), ++ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7981_pin_smt_range), ++ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7981_pin_ies_range), ++ [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7981_pin_pu_range), ++ [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7981_pin_pd_range), ++ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7981_pin_drv_range), ++ [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7981_pin_pupd_range), ++ [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7981_pin_r0_range), ++ [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7981_pin_r1_range), ++}; ++ ++static const struct mtk_pin_desc mt7981_pins[] = { ++ MT7981_PIN(0, "GPIO_WPS"), ++ MT7981_PIN(1, "GPIO_RESET"), ++ MT7981_PIN(2, "SYS_WATCHDOG"), ++ MT7981_PIN(3, "PCIE_PERESET_N"), ++ MT7981_PIN(4, "JTAG_JTDO"), ++ MT7981_PIN(5, "JTAG_JTDI"), ++ MT7981_PIN(6, "JTAG_JTMS"), ++ MT7981_PIN(7, "JTAG_JTCLK"), ++ MT7981_PIN(8, "JTAG_JTRST_N"), ++ MT7981_PIN(9, "WO_JTAG_JTDO"), ++ MT7981_PIN(10, "WO_JTAG_JTDI"), ++ MT7981_PIN(11, "WO_JTAG_JTMS"), ++ MT7981_PIN(12, "WO_JTAG_JTCLK"), ++ MT7981_PIN(13, "WO_JTAG_JTRST_N"), ++ MT7981_PIN(14, "USB_VBUS"), ++ MT7981_PIN(15, "PWM0"), ++ MT7981_PIN(16, "SPI0_CLK"), ++ MT7981_PIN(17, "SPI0_MOSI"), ++ MT7981_PIN(18, "SPI0_MISO"), ++ MT7981_PIN(19, "SPI0_CS"), ++ MT7981_PIN(20, "SPI0_HOLD"), ++ MT7981_PIN(21, "SPI0_WP"), ++ MT7981_PIN(22, "SPI1_CLK"), ++ MT7981_PIN(23, "SPI1_MOSI"), ++ MT7981_PIN(24, "SPI1_MISO"), ++ MT7981_PIN(25, "SPI1_CS"), ++ MT7981_PIN(26, "SPI2_CLK"), ++ MT7981_PIN(27, "SPI2_MOSI"), ++ MT7981_PIN(28, "SPI2_MISO"), ++ MT7981_PIN(29, "SPI2_CS"), ++ MT7981_PIN(30, "SPI2_HOLD"), ++ MT7981_PIN(31, "SPI2_WP"), ++ MT7981_PIN(32, "UART0_RXD"), ++ MT7981_PIN(33, "UART0_TXD"), ++ MT7981_PIN(34, "PCIE_CLK_REQ"), ++ MT7981_PIN(35, "PCIE_WAKE_N"), ++ MT7981_PIN(36, "SMI_MDC"), ++ MT7981_PIN(37, "SMI_MDIO"), ++ MT7981_PIN(38, "GBE_INT"), ++ MT7981_PIN(39, "GBE_RESET"), ++ MT7981_PIN(40, "WF_DIG_RESETB"), ++ MT7981_PIN(41, "WF_CBA_RESETB"), ++ MT7981_PIN(42, "WF_XO_REQ"), ++ MT7981_PIN(43, "WF_TOP_CLK"), ++ MT7981_PIN(44, "WF_TOP_DATA"), ++ MT7981_PIN(45, "WF_HB1"), ++ MT7981_PIN(46, "WF_HB2"), ++ MT7981_PIN(47, "WF_HB3"), ++ MT7981_PIN(48, "WF_HB4"), ++ MT7981_PIN(49, "WF_HB0"), ++ MT7981_PIN(50, "WF_HB0_B"), ++ MT7981_PIN(51, "WF_HB5"), ++ MT7981_PIN(52, "WF_HB6"), ++ MT7981_PIN(53, "WF_HB7"), ++ MT7981_PIN(54, "WF_HB8"), ++ MT7981_PIN(55, "WF_HB9"), ++ MT7981_PIN(56, "WF_HB10"), ++}; ++ ++/* List all groups consisting of these pins dedicated to the enablement of ++ * certain hardware block and the corresponding mode for all of the pins. ++ * The hardware probably has multiple combinations of these pinouts. ++ */ ++ ++/* WA_AICE */ ++static int mt7981_wa_aice1_pins[] = { 0, 1, }; ++static int mt7981_wa_aice1_funcs[] = { 2, 2, }; ++ ++static int mt7981_wa_aice2_pins[] = { 0, 1, }; ++static int mt7981_wa_aice2_funcs[] = { 3, 3, }; ++ ++static int mt7981_wa_aice3_pins[] = { 28, 29, }; ++static int mt7981_wa_aice3_funcs[] = { 3, 3, }; ++ ++static int mt7981_wm_aice1_pins[] = { 9, 10, }; ++static int mt7981_wm_aice1_funcs[] = { 2, 2, }; ++ ++static int mt7981_wm_aice2_pins[] = { 30, 31, }; ++static int mt7981_wm_aice2_funcs[] = { 5, 5, }; ++ ++/* WM_UART */ ++static int mt7981_wm_uart_0_pins[] = { 0, 1, }; ++static int mt7981_wm_uart_0_funcs[] = { 5, 5, }; ++ ++static int mt7981_wm_uart_1_pins[] = { 20, 21, }; ++static int mt7981_wm_uart_1_funcs[] = { 4, 4, }; ++ ++static int mt7981_wm_uart_2_pins[] = { 30, 31, }; ++static int mt7981_wm_uart_2_funcs[] = { 3, 3, }; ++ ++/* DFD */ ++static int mt7981_dfd_pins[] = { 0, 1, 4, 5, }; ++static int mt7981_dfd_funcs[] = { 5, 5, 6, 6, }; ++ ++/* SYS_WATCHDOG */ ++static int mt7981_watchdog_pins[] = { 2, }; ++static int mt7981_watchdog_funcs[] = { 1, }; ++ ++static int mt7981_watchdog1_pins[] = { 13, }; ++static int mt7981_watchdog1_funcs[] = { 5, }; ++ ++/* PCIE_PERESET_N */ ++static int mt7981_pcie_pereset_pins[] = { 3, }; ++static int mt7981_pcie_pereset_funcs[] = { 1, }; ++ ++/* JTAG */ ++static int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, }; ++static int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, }; ++ ++/* WM_JTAG */ ++static int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, }; ++static int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, }; ++ ++static int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, }; ++static int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; ++ ++/* WO0_JTAG */ ++static int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, }; ++static int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, }; ++ ++static int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, }; ++static int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; ++ ++/* UART2 */ ++static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, }; ++static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, }; ++ ++/* GBE_LED0 */ ++static int mt7981_gbe_led0_pins[] = { 8, }; ++static int mt7981_gbe_led0_funcs[] = { 3, }; ++ ++/* PTA_EXT */ ++static int mt7981_pta_ext_0_pins[] = { 4, 5, 6, }; ++static int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, }; ++ ++static int mt7981_pta_ext_1_pins[] = { 22, 23, 24, }; ++static int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, }; ++ ++/* PWM2 */ ++static int mt7981_pwm2_pins[] = { 7, }; ++static int mt7981_pwm2_funcs[] = { 4, }; ++ ++/* NET_WO0_UART_TXD */ ++static int mt7981_net_wo0_uart_txd_0_pins[] = { 8, }; ++static int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, }; ++ ++static int mt7981_net_wo0_uart_txd_1_pins[] = { 14, }; ++static int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, }; ++ ++static int mt7981_net_wo0_uart_txd_2_pins[] = { 15, }; ++static int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, }; ++ ++/* SPI1 */ ++static int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, }; ++static int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, }; ++ ++/* I2C */ ++static int mt7981_i2c0_0_pins[] = { 6, 7, }; ++static int mt7981_i2c0_0_funcs[] = { 6, 6, }; ++ ++static int mt7981_i2c0_1_pins[] = { 30, 31, }; ++static int mt7981_i2c0_1_funcs[] = { 4, 4, }; ++ ++static int mt7981_i2c0_2_pins[] = { 36, 37, }; ++static int mt7981_i2c0_2_funcs[] = { 2, 2, }; ++ ++static int mt7981_u2_phy_i2c_pins[] = { 30, 31, }; ++static int mt7981_u2_phy_i2c_funcs[] = { 6, 6, }; ++ ++static int mt7981_u3_phy_i2c_pins[] = { 32, 33, }; ++static int mt7981_u3_phy_i2c_funcs[] = { 3, 3, }; ++ ++static int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, }; ++static int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, }; ++ ++static int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, }; ++static int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, }; ++ ++/* DFD_NTRST */ ++static int mt7981_dfd_ntrst_pins[] = { 8, }; ++static int mt7981_dfd_ntrst_funcs[] = { 6, }; ++ ++/* PWM0 */ ++static int mt7981_pwm0_0_pins[] = { 13, }; ++static int mt7981_pwm0_0_funcs[] = { 2, }; ++ ++static int mt7981_pwm0_1_pins[] = { 15, }; ++static int mt7981_pwm0_1_funcs[] = { 1, }; ++ ++/* PWM1 */ ++static int mt7981_pwm1_0_pins[] = { 14, }; ++static int mt7981_pwm1_0_funcs[] = { 2, }; ++ ++static int mt7981_pwm1_1_pins[] = { 15, }; ++static int mt7981_pwm1_1_funcs[] = { 3, }; ++ ++/* GBE_LED1 */ ++static int mt7981_gbe_led1_pins[] = { 13, }; ++static int mt7981_gbe_led1_funcs[] = { 3, }; ++ ++/* PCM */ ++static int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 }; ++static int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, }; ++ ++/* UDI */ ++static int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, }; ++static int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, }; ++ ++/* DRV_VBUS */ ++static int mt7981_drv_vbus_pins[] = { 14, }; ++static int mt7981_drv_vbus_funcs[] = { 1, }; ++ ++/* EMMC */ ++static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, }; ++static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; ++ ++/* SNFI */ ++static int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, }; ++static int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, }; ++ ++/* SPI0 */ ++static int mt7981_spi0_pins[] = { 16, 17, 18, 19, }; ++static int mt7981_spi0_funcs[] = { 1, 1, 1, 1, }; ++ ++/* SPI0 */ ++static int mt7981_spi0_wp_hold_pins[] = { 20, 21, }; ++static int mt7981_spi0_wp_hold_funcs[] = { 1, 1, }; ++ ++/* SPI1 */ ++static int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, }; ++static int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, }; ++ ++/* SPI2 */ ++static int mt7981_spi2_pins[] = { 26, 27, 28, 29, }; ++static int mt7981_spi2_funcs[] = { 1, 1, 1, 1, }; ++ ++/* SPI2 */ ++static int mt7981_spi2_wp_hold_pins[] = { 30, 31, }; ++static int mt7981_spi2_wp_hold_funcs[] = { 1, 1, }; ++ ++/* UART1 */ ++static int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, }; ++static int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, }; ++ ++static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, }; ++static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, }; ++ ++/* UART2 */ ++static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, }; ++static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, }; ++ ++/* UART0 */ ++static int mt7981_uart0_pins[] = { 32, 33, }; ++static int mt7981_uart0_funcs[] = { 1, 1, }; ++ ++/* PCIE_CLK_REQ */ ++static int mt7981_pcie_clk_pins[] = { 34, }; ++static int mt7981_pcie_clk_funcs[] = { 2, }; ++ ++/* PCIE_WAKE_N */ ++static int mt7981_pcie_wake_pins[] = { 35, }; ++static int mt7981_pcie_wake_funcs[] = { 2, }; ++ ++/* MDC_MDIO */ ++static int mt7981_smi_mdc_mdio_pins[] = { 36, 37, }; ++static int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, }; ++ ++static int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, }; ++static int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, }; ++ ++/* WF0_MODE1 */ ++static int mt7981_wf0_mode1_pins[] = { 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56 }; ++static int mt7981_wf0_mode1_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; ++ ++/* WF0_MODE3 */ ++static int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 }; ++static int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 }; ++ ++/* WF2G_LED */ ++static int mt7981_wf2g_led0_pins[] = { 30, }; ++static int mt7981_wf2g_led0_funcs[] = { 2, }; ++ ++static int mt7981_wf2g_led1_pins[] = { 34, }; ++static int mt7981_wf2g_led1_funcs[] = { 1, }; ++ ++/* WF5G_LED */ ++static int mt7981_wf5g_led0_pins[] = { 31, }; ++static int mt7981_wf5g_led0_funcs[] = { 2, }; ++ ++static int mt7981_wf5g_led1_pins[] = { 35, }; ++static int mt7981_wf5g_led1_funcs[] = { 1, }; ++ ++/* MT7531_INT */ ++static int mt7981_mt7531_int_pins[] = { 38, }; ++static int mt7981_mt7531_int_funcs[] = { 1, }; ++ ++/* ANT_SEL */ ++static int mt7981_ant_sel_pins[] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 }; ++static int mt7981_ant_sel_funcs[] = { 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 }; ++ ++static const struct group_desc mt7981_groups[] = { ++ /* @GPIO(0,1): WA_AICE(2) */ ++ PINCTRL_PIN_GROUP("wa_aice1", mt7981_wa_aice1), ++ /* @GPIO(0,1): WA_AICE(3) */ ++ PINCTRL_PIN_GROUP("wa_aice2", mt7981_wa_aice2), ++ /* @GPIO(0,1): WM_UART(5) */ ++ PINCTRL_PIN_GROUP("wm_uart_0", mt7981_wm_uart_0), ++ /* @GPIO(0,1,4,5): DFD(6) */ ++ PINCTRL_PIN_GROUP("dfd", mt7981_dfd), ++ /* @GPIO(2): SYS_WATCHDOG(1) */ ++ PINCTRL_PIN_GROUP("watchdog", mt7981_watchdog), ++ /* @GPIO(3): PCIE_PERESET_N(1) */ ++ PINCTRL_PIN_GROUP("pcie_pereset", mt7981_pcie_pereset), ++ /* @GPIO(4,8) JTAG(1) */ ++ PINCTRL_PIN_GROUP("jtag", mt7981_jtag), ++ /* @GPIO(4,8) WM_JTAG(2) */ ++ PINCTRL_PIN_GROUP("wm_jtag_0", mt7981_wm_jtag_0), ++ /* @GPIO(9,13) WO0_JTAG(1) */ ++ PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0), ++ /* @GPIO(4,7) WM_JTAG(3) */ ++ PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0), ++ /* @GPIO(8) GBE_LED0(3) */ ++ PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0), ++ /* @GPIO(4,6) PTA_EXT(4) */ ++ PINCTRL_PIN_GROUP("pta_ext_0", mt7981_pta_ext_0), ++ /* @GPIO(7) PWM2(4) */ ++ PINCTRL_PIN_GROUP("pwm2", mt7981_pwm2), ++ /* @GPIO(8) NET_WO0_UART_TXD(4) */ ++ PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7981_net_wo0_uart_txd_0), ++ /* @GPIO(4,7) SPI1(5) */ ++ PINCTRL_PIN_GROUP("spi1_0", mt7981_spi1_0), ++ /* @GPIO(6,7) I2C(5) */ ++ PINCTRL_PIN_GROUP("i2c0_0", mt7981_i2c0_0), ++ /* @GPIO(0,1,4,5): DFD_NTRST(6) */ ++ PINCTRL_PIN_GROUP("dfd_ntrst", mt7981_dfd_ntrst), ++ /* @GPIO(9,10): WM_AICE(2) */ ++ PINCTRL_PIN_GROUP("wm_aice1", mt7981_wm_aice1), ++ /* @GPIO(13): PWM0(2) */ ++ PINCTRL_PIN_GROUP("pwm0_0", mt7981_pwm0_0), ++ /* @GPIO(15): PWM0(1) */ ++ PINCTRL_PIN_GROUP("pwm0_1", mt7981_pwm0_1), ++ /* @GPIO(14): PWM1(2) */ ++ PINCTRL_PIN_GROUP("pwm1_0", mt7981_pwm1_0), ++ /* @GPIO(15): PWM1(3) */ ++ PINCTRL_PIN_GROUP("pwm1_1", mt7981_pwm1_1), ++ /* @GPIO(14) NET_WO0_UART_TXD(3) */ ++ PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7981_net_wo0_uart_txd_1), ++ /* @GPIO(15) NET_WO0_UART_TXD(4) */ ++ PINCTRL_PIN_GROUP("net_wo0_uart_txd_2", mt7981_net_wo0_uart_txd_2), ++ /* @GPIO(13) GBE_LED0(3) */ ++ PINCTRL_PIN_GROUP("gbe_led1", mt7981_gbe_led1), ++ /* @GPIO(9,13) PCM(4) */ ++ PINCTRL_PIN_GROUP("pcm", mt7981_pcm), ++ /* @GPIO(13): SYS_WATCHDOG1(5) */ ++ PINCTRL_PIN_GROUP("watchdog1", mt7981_watchdog1), ++ /* @GPIO(9,13) UDI(4) */ ++ PINCTRL_PIN_GROUP("udi", mt7981_udi), ++ /* @GPIO(14) DRV_VBUS(1) */ ++ PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus), ++ /* @GPIO(15,25): EMMC(2) */ ++ PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45), ++ /* @GPIO(16,21): SNFI(3) */ ++ PINCTRL_PIN_GROUP("snfi", mt7981_snfi), ++ /* @GPIO(16,19): SPI0(1) */ ++ PINCTRL_PIN_GROUP("spi0", mt7981_spi0), ++ /* @GPIO(20,21): SPI0(1) */ ++ PINCTRL_PIN_GROUP("spi0_wp_hold", mt7981_spi0_wp_hold), ++ /* @GPIO(22,25) SPI1(1) */ ++ PINCTRL_PIN_GROUP("spi1_1", mt7981_spi1_1), ++ /* @GPIO(26,29): SPI2(1) */ ++ PINCTRL_PIN_GROUP("spi2", mt7981_spi2), ++ /* @GPIO(30,31): SPI0(1) */ ++ PINCTRL_PIN_GROUP("spi2_wp_hold", mt7981_spi2_wp_hold), ++ /* @GPIO(16,19): UART1(4) */ ++ PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0), ++ /* @GPIO(26,29): UART1(2) */ ++ PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1), ++ /* @GPIO(22,25): UART1(3) */ ++ PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1), ++ /* @GPIO(22,24) PTA_EXT(4) */ ++ PINCTRL_PIN_GROUP("pta_ext_1", mt7981_pta_ext_1), ++ /* @GPIO(20,21): WM_UART(4) */ ++ PINCTRL_PIN_GROUP("wm_aurt_1", mt7981_wm_uart_1), ++ /* @GPIO(30,31): WM_UART(3) */ ++ PINCTRL_PIN_GROUP("wm_aurt_2", mt7981_wm_uart_2), ++ /* @GPIO(20,24) WM_JTAG(5) */ ++ PINCTRL_PIN_GROUP("wm_jtag_1", mt7981_wm_jtag_1), ++ /* @GPIO(25,29) WO0_JTAG(5) */ ++ PINCTRL_PIN_GROUP("wo0_jtag_1", mt7981_wo0_jtag_1), ++ /* @GPIO(28,29): WA_AICE(3) */ ++ PINCTRL_PIN_GROUP("wa_aice3", mt7981_wa_aice3), ++ /* @GPIO(30,31): WM_AICE(5) */ ++ PINCTRL_PIN_GROUP("wm_aice2", mt7981_wm_aice2), ++ /* @GPIO(30,31): I2C(4) */ ++ PINCTRL_PIN_GROUP("i2c0_1", mt7981_i2c0_1), ++ /* @GPIO(30,31): I2C(6) */ ++ PINCTRL_PIN_GROUP("u2_phy_i2c", mt7981_u2_phy_i2c), ++ /* @GPIO(32,33): I2C(1) */ ++ PINCTRL_PIN_GROUP("uart0", mt7981_uart0), ++ /* @GPIO(32,33): I2C(2) */ ++ PINCTRL_PIN_GROUP("sgmii1_phy_i2c", mt7981_sgmii1_phy_i2c), ++ /* @GPIO(32,33): I2C(3) */ ++ PINCTRL_PIN_GROUP("u3_phy_i2c", mt7981_u3_phy_i2c), ++ /* @GPIO(32,33): I2C(5) */ ++ PINCTRL_PIN_GROUP("sgmii0_phy_i2c", mt7981_sgmii0_phy_i2c), ++ /* @GPIO(34): PCIE_CLK_REQ(2) */ ++ PINCTRL_PIN_GROUP("pcie_clk", mt7981_pcie_clk), ++ /* @GPIO(35): PCIE_WAKE_N(2) */ ++ PINCTRL_PIN_GROUP("pcie_wake", mt7981_pcie_wake), ++ /* @GPIO(36,37): I2C(2) */ ++ PINCTRL_PIN_GROUP("i2c0_2", mt7981_i2c0_2), ++ /* @GPIO(36,37): MDC_MDIO(1) */ ++ PINCTRL_PIN_GROUP("smi_mdc_mdio", mt7981_smi_mdc_mdio), ++ /* @GPIO(36,37): MDC_MDIO(3) */ ++ PINCTRL_PIN_GROUP("gbe_ext_mdc_mdio", mt7981_gbe_ext_mdc_mdio), ++ /* @GPIO(69,85): WF0_MODE1(1) */ ++ PINCTRL_PIN_GROUP("wf0_mode1", mt7981_wf0_mode1), ++ /* @GPIO(74,80): WF0_MODE3(3) */ ++ PINCTRL_PIN_GROUP("wf0_mode3", mt7981_wf0_mode3), ++ /* @GPIO(30): WF2G_LED(2) */ ++ PINCTRL_PIN_GROUP("wf2g_led0", mt7981_wf2g_led0), ++ /* @GPIO(34): WF2G_LED(1) */ ++ PINCTRL_PIN_GROUP("wf2g_led1", mt7981_wf2g_led1), ++ /* @GPIO(31): WF5G_LED(2) */ ++ PINCTRL_PIN_GROUP("wf5g_led0", mt7981_wf5g_led0), ++ /* @GPIO(35): WF5G_LED(1) */ ++ PINCTRL_PIN_GROUP("wf5g_led1", mt7981_wf5g_led1), ++ /* @GPIO(38): MT7531_INT(1) */ ++ PINCTRL_PIN_GROUP("mt7531_int", mt7981_mt7531_int), ++ /* @GPIO(14,15,26,17,18,19,20,21,22,23,24,25,34,35): ANT_SEL(1) */ ++ PINCTRL_PIN_GROUP("ant_sel", mt7981_ant_sel), ++}; ++ ++/* Joint those groups owning the same capability in user point of view which ++ * allows that people tend to use through the device tree. ++ */ ++static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1", ++ "wa_aice3", "wm_aice1_2", }; ++static const char *mt7981_uart_groups[] = { "wm_uart_0", "uart2_0", ++ "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2", ++ "uart1_0", "uart1_1", "uart2_1", "wm_aurt_1", "wm_aurt_2", "uart0", }; ++static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", }; ++static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", }; ++static const char *mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", "pcie_wake", }; ++static const char *mt7981_jtag_groups[] = { "jtag", "wm_jtag_0", "wo0_jtag_0", ++ "wo0_jtag_1", "wm_jtag_1", }; ++static const char *mt7981_led_groups[] = { "gbe_led0", "gbe_led1", "wf2g_led0", ++ "wf2g_led1", "wf5g_led0", "wf5g_led1", }; ++static const char *mt7981_pta_groups[] = { "pta_ext_0", "pta_ext_1", }; ++static const char *mt7981_pwm_groups[] = { "pwm2", "pwm0_0", "pwm0_1", ++ "pwm1_0", "pwm1_1", }; ++static const char *mt7981_spi_groups[] = { "spi1_0", "spi0", "spi0_wp_hold", "spi1_1", "spi2", ++ "spi2_wp_hold", }; ++static const char *mt7981_i2c_groups[] = { "i2c0_0", "i2c0_1", "u2_phy_i2c", ++ "sgmii1_phy_i2c", "u3_phy_i2c", "sgmii0_phy_i2c", "i2c0_2", }; ++static const char *mt7981_pcm_groups[] = { "pcm", }; ++static const char *mt7981_udi_groups[] = { "udi", }; ++static const char *mt7981_usb_groups[] = { "drv_vbus", }; ++static const char *mt7981_flash_groups[] = { "emmc_45", "snfi", }; ++static const char *mt7981_ethernet_groups[] = { "smi_mdc_mdio", "gbe_ext_mdc_mdio", ++ "wf0_mode1", "wf0_mode3", "mt7531_int", }; ++static const char *mt7981_ant_groups[] = { "ant_sel", }; ++ ++static const struct function_desc mt7981_functions[] = { ++ {"wa_aice", mt7981_wa_aice_groups, ARRAY_SIZE(mt7981_wa_aice_groups)}, ++ {"dfd", mt7981_dfd_groups, ARRAY_SIZE(mt7981_dfd_groups)}, ++ {"jtag", mt7981_jtag_groups, ARRAY_SIZE(mt7981_jtag_groups)}, ++ {"pta", mt7981_pta_groups, ARRAY_SIZE(mt7981_pta_groups)}, ++ {"pcm", mt7981_pcm_groups, ARRAY_SIZE(mt7981_pcm_groups)}, ++ {"udi", mt7981_udi_groups, ARRAY_SIZE(mt7981_udi_groups)}, ++ {"usb", mt7981_usb_groups, ARRAY_SIZE(mt7981_usb_groups)}, ++ {"ant", mt7981_ant_groups, ARRAY_SIZE(mt7981_ant_groups)}, ++ {"eth", mt7981_ethernet_groups, ARRAY_SIZE(mt7981_ethernet_groups)}, ++ {"i2c", mt7981_i2c_groups, ARRAY_SIZE(mt7981_i2c_groups)}, ++ {"led", mt7981_led_groups, ARRAY_SIZE(mt7981_led_groups)}, ++ {"pwm", mt7981_pwm_groups, ARRAY_SIZE(mt7981_pwm_groups)}, ++ {"spi", mt7981_spi_groups, ARRAY_SIZE(mt7981_spi_groups)}, ++ {"uart", mt7981_uart_groups, ARRAY_SIZE(mt7981_uart_groups)}, ++ {"watchdog", mt7981_wdt_groups, ARRAY_SIZE(mt7981_wdt_groups)}, ++ {"flash", mt7981_flash_groups, ARRAY_SIZE(mt7981_flash_groups)}, ++ {"pcie", mt7981_pcie_groups, ARRAY_SIZE(mt7981_pcie_groups)}, ++}; ++ ++static const struct mtk_eint_hw mt7981_eint_hw = { ++ .port_mask = 7, ++ .ports = 7, ++ .ap_num = ARRAY_SIZE(mt7981_pins), ++ .db_cnt = 16, ++}; ++ ++static const char * const mt7981_pinctrl_register_base_names[] = { ++ "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb", ++ "iocfg_lb", "iocfg_bl", "iocfg_tm", "iocfg_tl", ++}; ++ ++static struct mtk_pin_soc mt7981_data = { ++ .reg_cal = mt7981_reg_cals, ++ .pins = mt7981_pins, ++ .npins = ARRAY_SIZE(mt7981_pins), ++ .grps = mt7981_groups, ++ .ngrps = ARRAY_SIZE(mt7981_groups), ++ .funcs = mt7981_functions, ++ .nfuncs = ARRAY_SIZE(mt7981_functions), ++ .eint_hw = &mt7981_eint_hw, ++ .gpio_m = 0, ++ .ies_present = false, ++ .base_names = mt7981_pinctrl_register_base_names, ++ .nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names), ++ .pull_type = mt7981_pull_type, ++ .bias_set_combo = mtk_pinconf_bias_set_combo, ++ .bias_get_combo = mtk_pinconf_bias_get_combo, ++ .drive_set = mtk_pinconf_drive_set_rev1, ++ .drive_get = mtk_pinconf_drive_get_rev1, ++ .adv_pull_get = mtk_pinconf_adv_pull_get, ++ .adv_pull_set = mtk_pinconf_adv_pull_set, ++}; ++ ++static const struct of_device_id mt7981_pinctrl_of_match[] = { ++ { .compatible = "mediatek,mt7981-pinctrl", }, ++ {} ++}; ++ ++static int mt7981_pinctrl_probe(struct platform_device *pdev) ++{ ++ return mtk_moore_pinctrl_probe(pdev, &mt7981_data); ++} ++ ++static struct platform_driver mt7981_pinctrl_driver = { ++ .driver = { ++ .name = "mt7981-pinctrl", ++ .of_match_table = mt7981_pinctrl_of_match, ++ }, ++ .probe = mt7981_pinctrl_probe, ++}; ++ ++static int __init mt7981_pinctrl_init(void) ++{ ++ return platform_driver_register(&mt7981_pinctrl_driver); ++} ++arch_initcall(mt7981_pinctrl_init); diff --git a/target/linux/mediatek/patches-6.1/215-v6.3-pinctrl-mediatek-add-support-for-MT7981-SoC.patch b/target/linux/mediatek/patches-6.1/215-v6.3-pinctrl-mediatek-add-support-for-MT7981-SoC.patch deleted file mode 100644 index ae99685df4c..00000000000 --- a/target/linux/mediatek/patches-6.1/215-v6.3-pinctrl-mediatek-add-support-for-MT7981-SoC.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/drivers/pinctrl/mediatek/Kconfig -+++ b/drivers/pinctrl/mediatek/Kconfig -@@ -120,6 +120,13 @@ config PINCTRL_MT7622 - default ARM64 && ARCH_MEDIATEK - select PINCTRL_MTK_MOORE - -+config PINCTRL_MT7981 -+ bool "Mediatek MT7981 pin control" -+ depends on OF -+ depends on ARM64 || COMPILE_TEST -+ default ARM64 && ARCH_MEDIATEK -+ select PINCTRL_MTK_MOORE -+ - config PINCTRL_MT7986 - bool "Mediatek MT7986 pin control" - depends on OF ---- a/drivers/pinctrl/mediatek/Makefile -+++ b/drivers/pinctrl/mediatek/Makefile -@@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_MT6797) += pinctrl- - obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o - obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o - obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o -+obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7981.o - obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o - obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o - obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o diff --git a/target/linux/mediatek/patches-6.1/216-v6.3-pinctrl-mediatek-add-missing-options-to-PINCTRL_MT79.patch b/target/linux/mediatek/patches-6.1/216-v6.3-pinctrl-mediatek-add-missing-options-to-PINCTRL_MT79.patch new file mode 100644 index 00000000000..995e0dc7ed8 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/216-v6.3-pinctrl-mediatek-add-missing-options-to-PINCTRL_MT79.patch @@ -0,0 +1,30 @@ +From c0ad453e94e5c404efbcf668648d07eaa1a71ed7 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Sat, 18 Feb 2023 09:51:06 +0300 +Subject: [PATCH] pinctrl: mediatek: add missing options to PINCTRL_MT7981 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +There are options missing from PINCTRL_MT7981 whilst being on every other +pin controller. Add them. + +Signed-off-by: Arınç ÜNAL +Acked-by: Daniel Golle +Link: https://lore.kernel.org/r/20230218065108.8958-1-arinc.unal@arinc9.com +Signed-off-by: Linus Walleij +--- + drivers/pinctrl/mediatek/Kconfig | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/pinctrl/mediatek/Kconfig ++++ b/drivers/pinctrl/mediatek/Kconfig +@@ -130,6 +130,8 @@ config PINCTRL_MT7622 + config PINCTRL_MT7981 + bool "Mediatek MT7981 pin control" + depends on OF ++ depends on ARM64 || COMPILE_TEST ++ default ARM64 && ARCH_MEDIATEK + select PINCTRL_MTK_MOORE + + config PINCTRL_MT7986 diff --git a/target/linux/mediatek/patches-6.1/220-v6.3-clk-mediatek-clk-gate-Propagate-struct-device-with-m.patch b/target/linux/mediatek/patches-6.1/220-v6.3-clk-mediatek-clk-gate-Propagate-struct-device-with-m.patch new file mode 100644 index 00000000000..e3292a067ce --- /dev/null +++ b/target/linux/mediatek/patches-6.1/220-v6.3-clk-mediatek-clk-gate-Propagate-struct-device-with-m.patch @@ -0,0 +1,536 @@ +From fe5c8d03f3de89ae058e365b783f8c1314f47490 Mon Sep 17 00:00:00 2001 +From: AngeloGioacchino Del Regno +Date: Fri, 20 Jan 2023 10:20:33 +0100 +Subject: [PATCH 01/15] clk: mediatek: clk-gate: Propagate struct device with + mtk_clk_register_gates() + +Commit e4c23e19aa2a ("clk: mediatek: Register clock gate with device") +introduces a helper function for the sole purpose of propagating a +struct device pointer to the clk API when registering the mtk-gate +clocks to take advantage of Runtime PM when/where needed and where +a power domain is defined in devicetree. + +Function mtk_clk_register_gates() then becomes a wrapper around the +new mtk_clk_register_gates_with_dev() function that will simply pass +NULL as struct device: this is essential when registering drivers +with CLK_OF_DECLARE instead of as a platform device, as there will +be no struct device to pass... but we can as well simply have only +one function that always takes such pointer as a param and pass NULL +when unavoidable. + +This commit removes the mtk_clk_register_gates() wrapper and renames +mtk_clk_register_gates_with_dev() to the former and all of the calls +to either of the two functions were fixed in all drivers in order to +reflect this change; also, to improve consistency with other kernel +functions, the pointer to struct device was moved as the first param. + +Since a lot of MediaTek clock drivers are actually registering as a +platform device, but were still registering the mtk-gate clocks +without passing any struct device to the clock framework, they've +been changed to pass a valid one now, as to make all those platforms +able to use runtime power management where available. + +While at it, some much needed indentation changes were also done. + +Signed-off-by: AngeloGioacchino Del Regno +Reviewed-by: Chen-Yu Tsai +Reviewed-by: Markus Schneider-Pargmann +Tested-by: Miles Chen +Link: https://lore.kernel.org/r/20230120092053.182923-4-angelogioacchino.delregno@collabora.com +Tested-by: Mingming Su +Signed-off-by: Stephen Boyd + +[daniel@makrotopia.org: dropped parts not relevant for OpenWrt] +--- + drivers/clk/mediatek/clk-gate.c | 23 +++++++--------------- + drivers/clk/mediatek/clk-gate.h | 7 +------ + drivers/clk/mediatek/clk-mt2701-aud.c | 4 ++-- + drivers/clk/mediatek/clk-mt2701-eth.c | 4 ++-- + drivers/clk/mediatek/clk-mt2701-g3d.c | 2 +- + drivers/clk/mediatek/clk-mt2701-hif.c | 4 ++-- + drivers/clk/mediatek/clk-mt2701-mm.c | 4 ++-- + drivers/clk/mediatek/clk-mt2701.c | 12 +++++------ + drivers/clk/mediatek/clk-mt2712-mm.c | 4 ++-- + drivers/clk/mediatek/clk-mt2712.c | 12 +++++------ + drivers/clk/mediatek/clk-mt7622-aud.c | 4 ++-- + drivers/clk/mediatek/clk-mt7622-eth.c | 8 ++++---- + drivers/clk/mediatek/clk-mt7622-hif.c | 8 ++++---- + drivers/clk/mediatek/clk-mt7622.c | 14 ++++++------- + drivers/clk/mediatek/clk-mt7629-eth.c | 7 ++++--- + drivers/clk/mediatek/clk-mt7629-hif.c | 8 ++++---- + drivers/clk/mediatek/clk-mt7629.c | 10 +++++----- + drivers/clk/mediatek/clk-mt7986-eth.c | 10 +++++----- + drivers/clk/mediatek/clk-mt7986-infracfg.c | 4 ++-- + 19 files changed, 68 insertions(+), 81 deletions(-) + +--- a/drivers/clk/mediatek/clk-gate.c ++++ b/drivers/clk/mediatek/clk-gate.c +@@ -152,12 +152,12 @@ const struct clk_ops mtk_clk_gate_ops_no + }; + EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr_inv); + +-static struct clk_hw *mtk_clk_register_gate(const char *name, ++static struct clk_hw *mtk_clk_register_gate(struct device *dev, const char *name, + const char *parent_name, + struct regmap *regmap, int set_ofs, + int clr_ofs, int sta_ofs, u8 bit, + const struct clk_ops *ops, +- unsigned long flags, struct device *dev) ++ unsigned long flags) + { + struct mtk_clk_gate *cg; + int ret; +@@ -202,10 +202,9 @@ static void mtk_clk_unregister_gate(stru + kfree(cg); + } + +-int mtk_clk_register_gates_with_dev(struct device_node *node, +- const struct mtk_gate *clks, int num, +- struct clk_hw_onecell_data *clk_data, +- struct device *dev) ++int mtk_clk_register_gates(struct device *dev, struct device_node *node, ++ const struct mtk_gate *clks, int num, ++ struct clk_hw_onecell_data *clk_data) + { + int i; + struct clk_hw *hw; +@@ -229,13 +228,13 @@ int mtk_clk_register_gates_with_dev(stru + continue; + } + +- hw = mtk_clk_register_gate(gate->name, gate->parent_name, ++ hw = mtk_clk_register_gate(dev, gate->name, gate->parent_name, + regmap, + gate->regs->set_ofs, + gate->regs->clr_ofs, + gate->regs->sta_ofs, + gate->shift, gate->ops, +- gate->flags, dev); ++ gate->flags); + + if (IS_ERR(hw)) { + pr_err("Failed to register clk %s: %pe\n", gate->name, +@@ -261,14 +260,6 @@ err: + + return PTR_ERR(hw); + } +-EXPORT_SYMBOL_GPL(mtk_clk_register_gates_with_dev); +- +-int mtk_clk_register_gates(struct device_node *node, +- const struct mtk_gate *clks, int num, +- struct clk_hw_onecell_data *clk_data) +-{ +- return mtk_clk_register_gates_with_dev(node, clks, num, clk_data, NULL); +-} + EXPORT_SYMBOL_GPL(mtk_clk_register_gates); + + void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num, +--- a/drivers/clk/mediatek/clk-gate.h ++++ b/drivers/clk/mediatek/clk-gate.h +@@ -50,15 +50,10 @@ struct mtk_gate { + #define GATE_MTK(_id, _name, _parent, _regs, _shift, _ops) \ + GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, _ops, 0) + +-int mtk_clk_register_gates(struct device_node *node, ++int mtk_clk_register_gates(struct device *dev, struct device_node *node, + const struct mtk_gate *clks, int num, + struct clk_hw_onecell_data *clk_data); + +-int mtk_clk_register_gates_with_dev(struct device_node *node, +- const struct mtk_gate *clks, int num, +- struct clk_hw_onecell_data *clk_data, +- struct device *dev); +- + void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num, + struct clk_hw_onecell_data *clk_data); + +--- a/drivers/clk/mediatek/clk-mt2701-aud.c ++++ b/drivers/clk/mediatek/clk-mt2701-aud.c +@@ -127,8 +127,8 @@ static int clk_mt2701_aud_probe(struct p + + clk_data = mtk_alloc_clk_data(CLK_AUD_NR); + +- mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks), +- clk_data); ++ mtk_clk_register_gates(&pdev->dev, node, audio_clks, ++ ARRAY_SIZE(audio_clks), clk_data); + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) { +--- a/drivers/clk/mediatek/clk-mt2701-eth.c ++++ b/drivers/clk/mediatek/clk-mt2701-eth.c +@@ -51,8 +51,8 @@ static int clk_mt2701_eth_probe(struct p + + clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR); + +- mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), +- clk_data); ++ mtk_clk_register_gates(&pdev->dev, node, eth_clks, ++ ARRAY_SIZE(eth_clks), clk_data); + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) +--- a/drivers/clk/mediatek/clk-mt2701-g3d.c ++++ b/drivers/clk/mediatek/clk-mt2701-g3d.c +@@ -45,7 +45,7 @@ static int clk_mt2701_g3dsys_init(struct + + clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR); + +- mtk_clk_register_gates(node, g3d_clks, ARRAY_SIZE(g3d_clks), ++ mtk_clk_register_gates(&pdev->dev, node, g3d_clks, ARRAY_SIZE(g3d_clks), + clk_data); + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); +--- a/drivers/clk/mediatek/clk-mt2701-hif.c ++++ b/drivers/clk/mediatek/clk-mt2701-hif.c +@@ -48,8 +48,8 @@ static int clk_mt2701_hif_probe(struct p + + clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR); + +- mtk_clk_register_gates(node, hif_clks, ARRAY_SIZE(hif_clks), +- clk_data); ++ mtk_clk_register_gates(&pdev->dev, node, hif_clks, ++ ARRAY_SIZE(hif_clks), clk_data); + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) { +--- a/drivers/clk/mediatek/clk-mt2701-mm.c ++++ b/drivers/clk/mediatek/clk-mt2701-mm.c +@@ -76,8 +76,8 @@ static int clk_mt2701_mm_probe(struct pl + + clk_data = mtk_alloc_clk_data(CLK_MM_NR); + +- mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), +- clk_data); ++ mtk_clk_register_gates(&pdev->dev, node, mm_clks, ++ ARRAY_SIZE(mm_clks), clk_data); + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) +--- a/drivers/clk/mediatek/clk-mt2701.c ++++ b/drivers/clk/mediatek/clk-mt2701.c +@@ -683,8 +683,8 @@ static int mtk_topckgen_init(struct plat + mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), + base, &mt2701_clk_lock, clk_data); + +- mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), +- clk_data); ++ mtk_clk_register_gates(&pdev->dev, node, top_clks, ++ ARRAY_SIZE(top_clks), clk_data); + + return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + } +@@ -783,8 +783,8 @@ static int mtk_infrasys_init(struct plat + } + } + +- mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), +- infra_clk_data); ++ mtk_clk_register_gates(&pdev->dev, node, infra_clks, ++ ARRAY_SIZE(infra_clks), infra_clk_data); + mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs), + infra_clk_data); + +@@ -894,8 +894,8 @@ static int mtk_pericfg_init(struct platf + + clk_data = mtk_alloc_clk_data(CLK_PERI_NR); + +- mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), +- clk_data); ++ mtk_clk_register_gates(&pdev->dev, node, peri_clks, ++ ARRAY_SIZE(peri_clks), clk_data); + + mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base, + &mt2701_clk_lock, clk_data); +--- a/drivers/clk/mediatek/clk-mt2712-mm.c ++++ b/drivers/clk/mediatek/clk-mt2712-mm.c +@@ -117,8 +117,8 @@ static int clk_mt2712_mm_probe(struct pl + + clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK); + +- mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), +- clk_data); ++ mtk_clk_register_gates(&pdev->dev, node, mm_clks, ++ ARRAY_SIZE(mm_clks), clk_data); + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + +--- a/drivers/clk/mediatek/clk-mt2712.c ++++ b/drivers/clk/mediatek/clk-mt2712.c +@@ -1324,8 +1324,8 @@ static int clk_mt2712_top_probe(struct p + &mt2712_clk_lock, top_clk_data); + mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, + &mt2712_clk_lock, top_clk_data); +- mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), +- top_clk_data); ++ mtk_clk_register_gates(&pdev->dev, node, top_clks, ++ ARRAY_SIZE(top_clks), top_clk_data); + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data); + +@@ -1344,8 +1344,8 @@ static int clk_mt2712_infra_probe(struct + + clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); + +- mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), +- clk_data); ++ mtk_clk_register_gates(&pdev->dev, node, infra_clks, ++ ARRAY_SIZE(infra_clks), clk_data); + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + +@@ -1366,8 +1366,8 @@ static int clk_mt2712_peri_probe(struct + + clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); + +- mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), +- clk_data); ++ mtk_clk_register_gates(&pdev->dev, node, peri_clks, ++ ARRAY_SIZE(peri_clks), clk_data); + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + +--- a/drivers/clk/mediatek/clk-mt7622-aud.c ++++ b/drivers/clk/mediatek/clk-mt7622-aud.c +@@ -114,8 +114,8 @@ static int clk_mt7622_audiosys_init(stru + + clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK); + +- mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks), +- clk_data); ++ mtk_clk_register_gates(&pdev->dev, node, audio_clks, ++ ARRAY_SIZE(audio_clks), clk_data); + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) { +--- a/drivers/clk/mediatek/clk-mt7622-eth.c ++++ b/drivers/clk/mediatek/clk-mt7622-eth.c +@@ -69,8 +69,8 @@ static int clk_mt7622_ethsys_init(struct + + clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK); + +- mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), +- clk_data); ++ mtk_clk_register_gates(&pdev->dev, node, eth_clks, ++ ARRAY_SIZE(eth_clks), clk_data); + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) +@@ -91,8 +91,8 @@ static int clk_mt7622_sgmiisys_init(stru + + clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK); + +- mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks), +- clk_data); ++ mtk_clk_register_gates(&pdev->dev, node, sgmii_clks, ++ ARRAY_SIZE(sgmii_clks), clk_data); + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) +--- a/drivers/clk/mediatek/clk-mt7622-hif.c ++++ b/drivers/clk/mediatek/clk-mt7622-hif.c +@@ -80,8 +80,8 @@ static int clk_mt7622_ssusbsys_init(stru + + clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK); + +- mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks), +- clk_data); ++ mtk_clk_register_gates(&pdev->dev, node, ssusb_clks, ++ ARRAY_SIZE(ssusb_clks), clk_data); + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) +@@ -102,8 +102,8 @@ static int clk_mt7622_pciesys_init(struc + + clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK); + +- mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks), +- clk_data); ++ mtk_clk_register_gates(&pdev->dev, node, pcie_clks, ++ ARRAY_SIZE(pcie_clks), clk_data); + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) +--- a/drivers/clk/mediatek/clk-mt7622.c ++++ b/drivers/clk/mediatek/clk-mt7622.c +@@ -621,8 +621,8 @@ static int mtk_topckgen_init(struct plat + mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), + base, &mt7622_clk_lock, clk_data); + +- mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), +- clk_data); ++ mtk_clk_register_gates(&pdev->dev, node, top_clks, ++ ARRAY_SIZE(top_clks), clk_data); + + return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + } +@@ -635,8 +635,8 @@ static int mtk_infrasys_init(struct plat + + clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); + +- mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), +- clk_data); ++ mtk_clk_register_gates(&pdev->dev, node, infra_clks, ++ ARRAY_SIZE(infra_clks), clk_data); + + mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes), + clk_data); +@@ -663,7 +663,7 @@ static int mtk_apmixedsys_init(struct pl + mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), + clk_data); + +- mtk_clk_register_gates(node, apmixed_clks, ++ mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, + ARRAY_SIZE(apmixed_clks), clk_data); + + return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); +@@ -682,8 +682,8 @@ static int mtk_pericfg_init(struct platf + + clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); + +- mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), +- clk_data); ++ mtk_clk_register_gates(&pdev->dev, node, peri_clks, ++ ARRAY_SIZE(peri_clks), clk_data); + + mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base, + &mt7622_clk_lock, clk_data); +--- a/drivers/clk/mediatek/clk-mt7629-eth.c ++++ b/drivers/clk/mediatek/clk-mt7629-eth.c +@@ -80,7 +80,8 @@ static int clk_mt7629_ethsys_init(struct + + clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK); + +- mtk_clk_register_gates(node, eth_clks, CLK_ETH_NR_CLK, clk_data); ++ mtk_clk_register_gates(&pdev->dev, node, eth_clks, ++ CLK_ETH_NR_CLK, clk_data); + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) +@@ -102,8 +103,8 @@ static int clk_mt7629_sgmiisys_init(stru + + clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK); + +- mtk_clk_register_gates(node, sgmii_clks[id++], CLK_SGMII_NR_CLK, +- clk_data); ++ mtk_clk_register_gates(&pdev->dev, node, sgmii_clks[id++], ++ CLK_SGMII_NR_CLK, clk_data); + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) +--- a/drivers/clk/mediatek/clk-mt7629-hif.c ++++ b/drivers/clk/mediatek/clk-mt7629-hif.c +@@ -75,8 +75,8 @@ static int clk_mt7629_ssusbsys_init(stru + + clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK); + +- mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks), +- clk_data); ++ mtk_clk_register_gates(&pdev->dev, node, ssusb_clks, ++ ARRAY_SIZE(ssusb_clks), clk_data); + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) +@@ -97,8 +97,8 @@ static int clk_mt7629_pciesys_init(struc + + clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK); + +- mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks), +- clk_data); ++ mtk_clk_register_gates(&pdev->dev, node, pcie_clks, ++ ARRAY_SIZE(pcie_clks), clk_data); + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) +--- a/drivers/clk/mediatek/clk-mt7629.c ++++ b/drivers/clk/mediatek/clk-mt7629.c +@@ -581,8 +581,8 @@ static int mtk_infrasys_init(struct plat + + clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); + +- mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), +- clk_data); ++ mtk_clk_register_gates(&pdev->dev, node, infra_clks, ++ ARRAY_SIZE(infra_clks), clk_data); + + mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes), + clk_data); +@@ -604,8 +604,8 @@ static int mtk_pericfg_init(struct platf + + clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); + +- mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), +- clk_data); ++ mtk_clk_register_gates(&pdev->dev, node, peri_clks, ++ ARRAY_SIZE(peri_clks), clk_data); + + mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base, + &mt7629_clk_lock, clk_data); +@@ -631,7 +631,7 @@ static int mtk_apmixedsys_init(struct pl + mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), + clk_data); + +- mtk_clk_register_gates(node, apmixed_clks, ++ mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, + ARRAY_SIZE(apmixed_clks), clk_data); + + clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk); +--- a/drivers/clk/mediatek/clk-mt7986-eth.c ++++ b/drivers/clk/mediatek/clk-mt7986-eth.c +@@ -72,8 +72,8 @@ static void __init mtk_sgmiisys_0_init(s + + clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks)); + +- mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks), +- clk_data); ++ mtk_clk_register_gates(NULL, node, sgmii0_clks, ++ ARRAY_SIZE(sgmii0_clks), clk_data); + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) +@@ -90,8 +90,8 @@ static void __init mtk_sgmiisys_1_init(s + + clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks)); + +- mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks), +- clk_data); ++ mtk_clk_register_gates(NULL, node, sgmii1_clks, ++ ARRAY_SIZE(sgmii1_clks), clk_data); + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + +@@ -109,7 +109,7 @@ static void __init mtk_ethsys_init(struc + + clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks)); + +- mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data); ++ mtk_clk_register_gates(NULL, node, eth_clks, ARRAY_SIZE(eth_clks), clk_data); + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + +--- a/drivers/clk/mediatek/clk-mt7986-infracfg.c ++++ b/drivers/clk/mediatek/clk-mt7986-infracfg.c +@@ -180,8 +180,8 @@ static int clk_mt7986_infracfg_probe(str + mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data); + mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node, + &mt7986_clk_lock, clk_data); +- mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), +- clk_data); ++ mtk_clk_register_gates(&pdev->dev, node, infra_clks, ++ ARRAY_SIZE(infra_clks), clk_data); + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) { +--- a/drivers/clk/mediatek/clk-mtk.c ++++ b/drivers/clk/mediatek/clk-mtk.c +@@ -459,8 +459,8 @@ int mtk_clk_simple_probe(struct platform + if (!clk_data) + return -ENOMEM; + +- r = mtk_clk_register_gates_with_dev(node, mcd->clks, mcd->num_clks, +- clk_data, &pdev->dev); ++ r = mtk_clk_register_gates(&pdev->dev, node, mcd->clks, mcd->num_clks, ++ clk_data); + if (r) + goto free_data; + diff --git a/target/linux/mediatek/patches-6.1/221-v6.3-clk-mediatek-cpumux-Propagate-struct-device-where-po.patch b/target/linux/mediatek/patches-6.1/221-v6.3-clk-mediatek-cpumux-Propagate-struct-device-where-po.patch new file mode 100644 index 00000000000..2333e722e19 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/221-v6.3-clk-mediatek-cpumux-Propagate-struct-device-where-po.patch @@ -0,0 +1,140 @@ +From b888303c7d23d7bd0c8667cfc657669e5d153fea Mon Sep 17 00:00:00 2001 +From: AngeloGioacchino Del Regno +Date: Fri, 20 Jan 2023 10:20:34 +0100 +Subject: [PATCH 02/15] clk: mediatek: cpumux: Propagate struct device where + possible + +Take a pointer to a struct device in mtk_clk_register_cpumuxes() and +propagate the same to mtk_clk_register_cpumux() => clk_hw_register(). +Even though runtime pm is unlikely to be used with CPU muxes, this +helps with code consistency and possibly opens to commonization of +some mtk_clk_register_(x) functions. + +Signed-off-by: AngeloGioacchino Del Regno +Reviewed-by: Chen-Yu Tsai +Reviewed-by: Markus Schneider-Pargmann +Tested-by: Miles Chen +Link: https://lore.kernel.org/r/20230120092053.182923-5-angelogioacchino.delregno@collabora.com +Tested-by: Mingming Su +Signed-off-by: Stephen Boyd +--- + drivers/clk/mediatek/clk-cpumux.c | 8 ++++---- + drivers/clk/mediatek/clk-cpumux.h | 2 +- + drivers/clk/mediatek/clk-mt2701.c | 2 +- + drivers/clk/mediatek/clk-mt6795-infracfg.c | 3 ++- + drivers/clk/mediatek/clk-mt7622.c | 4 ++-- + drivers/clk/mediatek/clk-mt7629.c | 4 ++-- + drivers/clk/mediatek/clk-mt8173.c | 4 ++-- + 7 files changed, 14 insertions(+), 13 deletions(-) + +--- a/drivers/clk/mediatek/clk-cpumux.c ++++ b/drivers/clk/mediatek/clk-cpumux.c +@@ -58,7 +58,7 @@ static const struct clk_ops clk_cpumux_o + }; + + static struct clk_hw * +-mtk_clk_register_cpumux(const struct mtk_composite *mux, ++mtk_clk_register_cpumux(struct device *dev, const struct mtk_composite *mux, + struct regmap *regmap) + { + struct mtk_clk_cpumux *cpumux; +@@ -81,7 +81,7 @@ mtk_clk_register_cpumux(const struct mtk + cpumux->regmap = regmap; + cpumux->hw.init = &init; + +- ret = clk_hw_register(NULL, &cpumux->hw); ++ ret = clk_hw_register(dev, &cpumux->hw); + if (ret) { + kfree(cpumux); + return ERR_PTR(ret); +@@ -102,7 +102,7 @@ static void mtk_clk_unregister_cpumux(st + kfree(cpumux); + } + +-int mtk_clk_register_cpumuxes(struct device_node *node, ++int mtk_clk_register_cpumuxes(struct device *dev, struct device_node *node, + const struct mtk_composite *clks, int num, + struct clk_hw_onecell_data *clk_data) + { +@@ -125,7 +125,7 @@ int mtk_clk_register_cpumuxes(struct dev + continue; + } + +- hw = mtk_clk_register_cpumux(mux, regmap); ++ hw = mtk_clk_register_cpumux(dev, mux, regmap); + if (IS_ERR(hw)) { + pr_err("Failed to register clk %s: %pe\n", mux->name, + hw); +--- a/drivers/clk/mediatek/clk-cpumux.h ++++ b/drivers/clk/mediatek/clk-cpumux.h +@@ -11,7 +11,7 @@ struct clk_hw_onecell_data; + struct device_node; + struct mtk_composite; + +-int mtk_clk_register_cpumuxes(struct device_node *node, ++int mtk_clk_register_cpumuxes(struct device *dev, struct device_node *node, + const struct mtk_composite *clks, int num, + struct clk_hw_onecell_data *clk_data); + +--- a/drivers/clk/mediatek/clk-mt2701.c ++++ b/drivers/clk/mediatek/clk-mt2701.c +@@ -757,7 +757,7 @@ static void __init mtk_infrasys_init_ear + mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs), + infra_clk_data); + +- mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), ++ mtk_clk_register_cpumuxes(NULL, node, cpu_muxes, ARRAY_SIZE(cpu_muxes), + infra_clk_data); + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, +--- a/drivers/clk/mediatek/clk-mt6795-infracfg.c ++++ b/drivers/clk/mediatek/clk-mt6795-infracfg.c +@@ -105,7 +105,8 @@ static int clk_mt6795_infracfg_probe(str + if (ret) + goto free_clk_data; + +- ret = mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data); ++ ret = mtk_clk_register_cpumuxes(&pdev->dev, node, cpu_muxes, ++ ARRAY_SIZE(cpu_muxes), clk_data); + if (ret) + goto unregister_gates; + +--- a/drivers/clk/mediatek/clk-mt7622.c ++++ b/drivers/clk/mediatek/clk-mt7622.c +@@ -638,8 +638,8 @@ static int mtk_infrasys_init(struct plat + mtk_clk_register_gates(&pdev->dev, node, infra_clks, + ARRAY_SIZE(infra_clks), clk_data); + +- mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes), +- clk_data); ++ mtk_clk_register_cpumuxes(&pdev->dev, node, infra_muxes, ++ ARRAY_SIZE(infra_muxes), clk_data); + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, + clk_data); +--- a/drivers/clk/mediatek/clk-mt7629.c ++++ b/drivers/clk/mediatek/clk-mt7629.c +@@ -584,8 +584,8 @@ static int mtk_infrasys_init(struct plat + mtk_clk_register_gates(&pdev->dev, node, infra_clks, + ARRAY_SIZE(infra_clks), clk_data); + +- mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes), +- clk_data); ++ mtk_clk_register_cpumuxes(&pdev->dev, node, infra_muxes, ++ ARRAY_SIZE(infra_muxes), clk_data); + + return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, + clk_data); +--- a/drivers/clk/mediatek/clk-mt8173.c ++++ b/drivers/clk/mediatek/clk-mt8173.c +@@ -892,8 +892,8 @@ static void __init mtk_infrasys_init(str + clk_data); + mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data); + +- mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), +- clk_data); ++ mtk_clk_register_cpumuxes(NULL, node, cpu_muxes, ++ ARRAY_SIZE(cpu_muxes), clk_data); + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) diff --git a/target/linux/mediatek/patches-6.1/222-v6.3-clk-mediatek-clk-mtk-Propagate-struct-device-for-com.patch b/target/linux/mediatek/patches-6.1/222-v6.3-clk-mediatek-clk-mtk-Propagate-struct-device-for-com.patch new file mode 100644 index 00000000000..01eed6cc01b --- /dev/null +++ b/target/linux/mediatek/patches-6.1/222-v6.3-clk-mediatek-clk-mtk-Propagate-struct-device-for-com.patch @@ -0,0 +1,181 @@ +From f23375db001ec0fe9f565be75eff43adde15407e Mon Sep 17 00:00:00 2001 +From: AngeloGioacchino Del Regno +Date: Fri, 20 Jan 2023 10:20:35 +0100 +Subject: [PATCH 03/15] clk: mediatek: clk-mtk: Propagate struct device for + composites + +Like done for cpumux clocks, propagate struct device for composite +clocks registered through clk-mtk helpers to be able to get runtime +pm support for MTK clocks. + +Signed-off-by: AngeloGioacchino Del Regno +Tested-by: Miles Chen +Link: https://lore.kernel.org/r/20230120092053.182923-6-angelogioacchino.delregno@collabora.com +Tested-by: Mingming Su +Signed-off-by: Stephen Boyd + +[daniel@makrotopia.org: remove parts not relevant for OpenWrt] +--- + drivers/clk/mediatek/clk-mt2701.c | 10 ++++++---- + drivers/clk/mediatek/clk-mt2712.c | 12 ++++++++---- + drivers/clk/mediatek/clk-mt7622.c | 8 +++++--- + drivers/clk/mediatek/clk-mt7629.c | 8 +++++--- + drivers/clk/mediatek/clk-mtk.c | 11 ++++++----- + drivers/clk/mediatek/clk-mtk.h | 3 ++- + 6 files changed, 32 insertions(+), 20 deletions(-) + +--- a/drivers/clk/mediatek/clk-mt2701.c ++++ b/drivers/clk/mediatek/clk-mt2701.c +@@ -677,8 +677,9 @@ static int mtk_topckgen_init(struct plat + mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs), + clk_data); + +- mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), +- base, &mt2701_clk_lock, clk_data); ++ mtk_clk_register_composites(&pdev->dev, top_muxes, ++ ARRAY_SIZE(top_muxes), base, ++ &mt2701_clk_lock, clk_data); + + mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), + base, &mt2701_clk_lock, clk_data); +@@ -897,8 +898,9 @@ static int mtk_pericfg_init(struct platf + mtk_clk_register_gates(&pdev->dev, node, peri_clks, + ARRAY_SIZE(peri_clks), clk_data); + +- mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base, +- &mt2701_clk_lock, clk_data); ++ mtk_clk_register_composites(&pdev->dev, peri_muxs, ++ ARRAY_SIZE(peri_muxs), base, ++ &mt2701_clk_lock, clk_data); + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) +--- a/drivers/clk/mediatek/clk-mt2712.c ++++ b/drivers/clk/mediatek/clk-mt2712.c +@@ -1320,8 +1320,9 @@ static int clk_mt2712_top_probe(struct p + mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), + top_clk_data); + mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); +- mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, +- &mt2712_clk_lock, top_clk_data); ++ mtk_clk_register_composites(&pdev->dev, top_muxes, ++ ARRAY_SIZE(top_muxes), base, ++ &mt2712_clk_lock, top_clk_data); + mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, + &mt2712_clk_lock, top_clk_data); + mtk_clk_register_gates(&pdev->dev, node, top_clks, +@@ -1395,8 +1396,11 @@ static int clk_mt2712_mcu_probe(struct p + + clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK); + +- mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base, +- &mt2712_clk_lock, clk_data); ++ r = mtk_clk_register_composites(&pdev->dev, mcu_muxes, ++ ARRAY_SIZE(mcu_muxes), base, ++ &mt2712_clk_lock, clk_data); ++ if (r) ++ dev_err(&pdev->dev, "Could not register composites: %d\n", r); + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + +--- a/drivers/clk/mediatek/clk-mt7622.c ++++ b/drivers/clk/mediatek/clk-mt7622.c +@@ -615,8 +615,9 @@ static int mtk_topckgen_init(struct plat + mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), + clk_data); + +- mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), +- base, &mt7622_clk_lock, clk_data); ++ mtk_clk_register_composites(&pdev->dev, top_muxes, ++ ARRAY_SIZE(top_muxes), base, ++ &mt7622_clk_lock, clk_data); + + mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), + base, &mt7622_clk_lock, clk_data); +@@ -685,7 +686,8 @@ static int mtk_pericfg_init(struct platf + mtk_clk_register_gates(&pdev->dev, node, peri_clks, + ARRAY_SIZE(peri_clks), clk_data); + +- mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base, ++ mtk_clk_register_composites(&pdev->dev, peri_muxes, ++ ARRAY_SIZE(peri_muxes), base, + &mt7622_clk_lock, clk_data); + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); +--- a/drivers/clk/mediatek/clk-mt7629.c ++++ b/drivers/clk/mediatek/clk-mt7629.c +@@ -564,8 +564,9 @@ static int mtk_topckgen_init(struct plat + mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), + clk_data); + +- mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), +- base, &mt7629_clk_lock, clk_data); ++ mtk_clk_register_composites(&pdev->dev, top_muxes, ++ ARRAY_SIZE(top_muxes), base, ++ &mt7629_clk_lock, clk_data); + + clk_prepare_enable(clk_data->hws[CLK_TOP_AXI_SEL]->clk); + clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk); +@@ -607,7 +608,8 @@ static int mtk_pericfg_init(struct platf + mtk_clk_register_gates(&pdev->dev, node, peri_clks, + ARRAY_SIZE(peri_clks), clk_data); + +- mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base, ++ mtk_clk_register_composites(&pdev->dev, peri_muxes, ++ ARRAY_SIZE(peri_muxes), base, + &mt7629_clk_lock, clk_data); + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); +--- a/drivers/clk/mediatek/clk-mtk.c ++++ b/drivers/clk/mediatek/clk-mtk.c +@@ -197,8 +197,8 @@ void mtk_clk_unregister_factors(const st + } + EXPORT_SYMBOL_GPL(mtk_clk_unregister_factors); + +-static struct clk_hw *mtk_clk_register_composite(const struct mtk_composite *mc, +- void __iomem *base, spinlock_t *lock) ++static struct clk_hw *mtk_clk_register_composite(struct device *dev, ++ const struct mtk_composite *mc, void __iomem *base, spinlock_t *lock) + { + struct clk_hw *hw; + struct clk_mux *mux = NULL; +@@ -264,7 +264,7 @@ static struct clk_hw *mtk_clk_register_c + div_ops = &clk_divider_ops; + } + +- hw = clk_hw_register_composite(NULL, mc->name, parent_names, num_parents, ++ hw = clk_hw_register_composite(dev, mc->name, parent_names, num_parents, + mux_hw, mux_ops, + div_hw, div_ops, + gate_hw, gate_ops, +@@ -308,7 +308,8 @@ static void mtk_clk_unregister_composite + kfree(mux); + } + +-int mtk_clk_register_composites(const struct mtk_composite *mcs, int num, ++int mtk_clk_register_composites(struct device *dev, ++ const struct mtk_composite *mcs, int num, + void __iomem *base, spinlock_t *lock, + struct clk_hw_onecell_data *clk_data) + { +@@ -327,7 +328,7 @@ int mtk_clk_register_composites(const st + continue; + } + +- hw = mtk_clk_register_composite(mc, base, lock); ++ hw = mtk_clk_register_composite(dev, mc, base, lock); + + if (IS_ERR(hw)) { + pr_err("Failed to register clk %s: %pe\n", mc->name, +--- a/drivers/clk/mediatek/clk-mtk.h ++++ b/drivers/clk/mediatek/clk-mtk.h +@@ -149,7 +149,8 @@ struct mtk_composite { + .flags = 0, \ + } + +-int mtk_clk_register_composites(const struct mtk_composite *mcs, int num, ++int mtk_clk_register_composites(struct device *dev, ++ const struct mtk_composite *mcs, int num, + void __iomem *base, spinlock_t *lock, + struct clk_hw_onecell_data *clk_data); + void mtk_clk_unregister_composites(const struct mtk_composite *mcs, int num, diff --git a/target/linux/mediatek/patches-6.1/223-v6.3-clk-mediatek-clk-mux-Propagate-struct-device-for-mtk.patch b/target/linux/mediatek/patches-6.1/223-v6.3-clk-mediatek-clk-mux-Propagate-struct-device-for-mtk.patch new file mode 100644 index 00000000000..a50422da588 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/223-v6.3-clk-mediatek-clk-mux-Propagate-struct-device-for-mtk.patch @@ -0,0 +1,103 @@ +From 5d911479e4c732729bfa798e4a9e3e5aec3e30a7 Mon Sep 17 00:00:00 2001 +From: AngeloGioacchino Del Regno +Date: Fri, 20 Jan 2023 10:20:36 +0100 +Subject: [PATCH 04/15] clk: mediatek: clk-mux: Propagate struct device for + mtk-mux + +Like done for other clocks, propagate struct device for mtk mux clocks +registered through clk-mux helpers to enable runtime pm support. + +Signed-off-by: AngeloGioacchino Del Regno +Tested-by: Miles Chen +Link: https://lore.kernel.org/r/20230120092053.182923-7-angelogioacchino.delregno@collabora.com +Tested-by: Mingming Su +Signed-off-by: Stephen Boyd + +[daniel@makrotopia.org: removed parts not relevant for OpenWrt] +--- + drivers/clk/mediatek/clk-mt7986-infracfg.c | 3 ++- + drivers/clk/mediatek/clk-mt7986-topckgen.c | 3 ++- + drivers/clk/mediatek/clk-mux.c | 14 ++++++++------ + drivers/clk/mediatek/clk-mux.h | 3 ++- + 4 files changed, 14 insertions(+), 9 deletions(-) + +--- a/drivers/clk/mediatek/clk-mt7986-infracfg.c ++++ b/drivers/clk/mediatek/clk-mt7986-infracfg.c +@@ -178,7 +178,8 @@ static int clk_mt7986_infracfg_probe(str + return -ENOMEM; + + mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data); +- mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node, ++ mtk_clk_register_muxes(&pdev->dev, infra_muxes, ++ ARRAY_SIZE(infra_muxes), node, + &mt7986_clk_lock, clk_data); + mtk_clk_register_gates(&pdev->dev, node, infra_clks, + ARRAY_SIZE(infra_clks), clk_data); +--- a/drivers/clk/mediatek/clk-mt7986-topckgen.c ++++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c +@@ -303,7 +303,8 @@ static int clk_mt7986_topckgen_probe(str + mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), + clk_data); + mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); +- mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node, ++ mtk_clk_register_muxes(&pdev->dev, top_muxes, ++ ARRAY_SIZE(top_muxes), node, + &mt7986_clk_lock, clk_data); + + clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAXI_SEL]->clk); +--- a/drivers/clk/mediatek/clk-mux.c ++++ b/drivers/clk/mediatek/clk-mux.c +@@ -154,9 +154,10 @@ const struct clk_ops mtk_mux_gate_clr_se + }; + EXPORT_SYMBOL_GPL(mtk_mux_gate_clr_set_upd_ops); + +-static struct clk_hw *mtk_clk_register_mux(const struct mtk_mux *mux, +- struct regmap *regmap, +- spinlock_t *lock) ++static struct clk_hw *mtk_clk_register_mux(struct device *dev, ++ const struct mtk_mux *mux, ++ struct regmap *regmap, ++ spinlock_t *lock) + { + struct mtk_clk_mux *clk_mux; + struct clk_init_data init = {}; +@@ -177,7 +178,7 @@ static struct clk_hw *mtk_clk_register_m + clk_mux->lock = lock; + clk_mux->hw.init = &init; + +- ret = clk_hw_register(NULL, &clk_mux->hw); ++ ret = clk_hw_register(dev, &clk_mux->hw); + if (ret) { + kfree(clk_mux); + return ERR_PTR(ret); +@@ -198,7 +199,8 @@ static void mtk_clk_unregister_mux(struc + kfree(mux); + } + +-int mtk_clk_register_muxes(const struct mtk_mux *muxes, ++int mtk_clk_register_muxes(struct device *dev, ++ const struct mtk_mux *muxes, + int num, struct device_node *node, + spinlock_t *lock, + struct clk_hw_onecell_data *clk_data) +@@ -222,7 +224,7 @@ int mtk_clk_register_muxes(const struct + continue; + } + +- hw = mtk_clk_register_mux(mux, regmap, lock); ++ hw = mtk_clk_register_mux(dev, mux, regmap, lock); + + if (IS_ERR(hw)) { + pr_err("Failed to register clk %s: %pe\n", mux->name, +--- a/drivers/clk/mediatek/clk-mux.h ++++ b/drivers/clk/mediatek/clk-mux.h +@@ -83,7 +83,8 @@ extern const struct clk_ops mtk_mux_gate + 0, _upd_ofs, _upd, CLK_SET_RATE_PARENT, \ + mtk_mux_clr_set_upd_ops) + +-int mtk_clk_register_muxes(const struct mtk_mux *muxes, ++int mtk_clk_register_muxes(struct device *dev, ++ const struct mtk_mux *muxes, + int num, struct device_node *node, + spinlock_t *lock, + struct clk_hw_onecell_data *clk_data); diff --git a/target/linux/mediatek/patches-6.1/224-v6.3-clk-mediatek-clk-mtk-Add-dummy-clock-ops.patch b/target/linux/mediatek/patches-6.1/224-v6.3-clk-mediatek-clk-mtk-Add-dummy-clock-ops.patch new file mode 100644 index 00000000000..de2e6976c31 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/224-v6.3-clk-mediatek-clk-mtk-Add-dummy-clock-ops.patch @@ -0,0 +1,74 @@ +From b8eb1081d267708ba976525a1fe2162901b34f3a Mon Sep 17 00:00:00 2001 +From: AngeloGioacchino Del Regno +Date: Fri, 20 Jan 2023 10:20:37 +0100 +Subject: [PATCH] clk: mediatek: clk-mtk: Add dummy clock ops + +In order to migrate some (few) old clock drivers to the common +mtk_clk_simple_probe() function, add dummy clock ops to be able +to insert a dummy clock with ID 0 at the beginning of the list. + +Signed-off-by: AngeloGioacchino Del Regno +Reviewed-by: Miles Chen +Reviewed-by: Chen-Yu Tsai +Tested-by: Miles Chen +Link: https://lore.kernel.org/r/20230120092053.182923-8-angelogioacchino.delregno@collabora.com +Tested-by: Mingming Su +Signed-off-by: Stephen Boyd +--- + drivers/clk/mediatek/clk-mtk.c | 16 ++++++++++++++++ + drivers/clk/mediatek/clk-mtk.h | 19 +++++++++++++++++++ + 2 files changed, 35 insertions(+) + +--- a/drivers/clk/mediatek/clk-mtk.c ++++ b/drivers/clk/mediatek/clk-mtk.c +@@ -18,6 +18,22 @@ + #include "clk-mtk.h" + #include "clk-gate.h" + ++const struct mtk_gate_regs cg_regs_dummy = { 0, 0, 0 }; ++EXPORT_SYMBOL_GPL(cg_regs_dummy); ++ ++static int mtk_clk_dummy_enable(struct clk_hw *hw) ++{ ++ return 0; ++} ++ ++static void mtk_clk_dummy_disable(struct clk_hw *hw) { } ++ ++const struct clk_ops mtk_clk_dummy_ops = { ++ .enable = mtk_clk_dummy_enable, ++ .disable = mtk_clk_dummy_disable, ++}; ++EXPORT_SYMBOL_GPL(mtk_clk_dummy_ops); ++ + static void mtk_init_clk_data(struct clk_hw_onecell_data *clk_data, + unsigned int clk_num) + { +--- a/drivers/clk/mediatek/clk-mtk.h ++++ b/drivers/clk/mediatek/clk-mtk.h +@@ -22,6 +22,25 @@ + + struct platform_device; + ++/* ++ * We need the clock IDs to start from zero but to maintain devicetree ++ * backwards compatibility we can't change bindings to start from zero. ++ * Only a few platforms are affected, so we solve issues given by the ++ * commonized MTK clocks probe function(s) by adding a dummy clock at ++ * the beginning where needed. ++ */ ++#define CLK_DUMMY 0 ++ ++extern const struct clk_ops mtk_clk_dummy_ops; ++extern const struct mtk_gate_regs cg_regs_dummy; ++ ++#define GATE_DUMMY(_id, _name) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .regs = &cg_regs_dummy, \ ++ .ops = &mtk_clk_dummy_ops, \ ++ } ++ + struct mtk_fixed_clk { + int id; + const char *name; diff --git a/target/linux/mediatek/patches-6.1/225-v6.3-clk-mediatek-Switch-to-mtk_clk_simple_probe-where-po.patch b/target/linux/mediatek/patches-6.1/225-v6.3-clk-mediatek-Switch-to-mtk_clk_simple_probe-where-po.patch new file mode 100644 index 00000000000..becfcd0ed81 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/225-v6.3-clk-mediatek-Switch-to-mtk_clk_simple_probe-where-po.patch @@ -0,0 +1,790 @@ +From c26e28015b74af73e0b299f6ad3ff22931e600b4 Mon Sep 17 00:00:00 2001 +From: AngeloGioacchino Del Regno +Date: Fri, 20 Jan 2023 10:20:41 +0100 +Subject: [PATCH 05/15] clk: mediatek: Switch to mtk_clk_simple_probe() where + possible + +mtk_clk_simple_probe() is a function that registers mtk gate clocks +and, if reset data is present, a reset controller and across all of +the MTK clock drivers, such a function is duplicated many times: +switch to the common mtk_clk_simple_probe() function for all of the +clock drivers that are registering as platform drivers. + +Signed-off-by: AngeloGioacchino Del Regno +Reviewed-by: Miles Chen +Tested-by: Miles Chen +Link: https://lore.kernel.org/r/20230120092053.182923-12-angelogioacchino.delregno@collabora.com +Tested-by: Mingming Su +Signed-off-by: Stephen Boyd + +[daniel@makrotopia.org: removed parts not relevant for OpenWrt] +--- + drivers/clk/mediatek/clk-mt2701-aud.c | 31 ++++++---- + drivers/clk/mediatek/clk-mt2701-eth.c | 36 ++++-------- + drivers/clk/mediatek/clk-mt2701-g3d.c | 56 ++++-------------- + drivers/clk/mediatek/clk-mt2701-hif.c | 38 ++++-------- + drivers/clk/mediatek/clk-mt2712.c | 83 ++++++++++---------------- + drivers/clk/mediatek/clk-mt7622-aud.c | 54 ++++++----------- + drivers/clk/mediatek/clk-mt7622-eth.c | 82 +++++--------------------- + drivers/clk/mediatek/clk-mt7622-hif.c | 85 +++++---------------------- + drivers/clk/mediatek/clk-mt7629-hif.c | 85 +++++---------------------- + 9 files changed, 144 insertions(+), 406 deletions(-) + +--- a/drivers/clk/mediatek/clk-mt2701-aud.c ++++ b/drivers/clk/mediatek/clk-mt2701-aud.c +@@ -52,6 +52,7 @@ static const struct mtk_gate_regs audio3 + }; + + static const struct mtk_gate audio_clks[] = { ++ GATE_DUMMY(CLK_DUMMY, "aud_dummy"), + /* AUDIO0 */ + GATE_AUDIO0(CLK_AUD_AFE, "audio_afe", "aud_intbus_sel", 2), + GATE_AUDIO0(CLK_AUD_HDMI, "audio_hdmi", "audpll_sel", 20), +@@ -114,29 +115,27 @@ static const struct mtk_gate audio_clks[ + GATE_AUDIO3(CLK_AUD_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14), + }; + ++static const struct mtk_clk_desc audio_desc = { ++ .clks = audio_clks, ++ .num_clks = ARRAY_SIZE(audio_clks), ++}; ++ + static const struct of_device_id of_match_clk_mt2701_aud[] = { +- { .compatible = "mediatek,mt2701-audsys", }, +- {} ++ { .compatible = "mediatek,mt2701-audsys", .data = &audio_desc }, ++ { /* sentinel */ } + }; + + static int clk_mt2701_aud_probe(struct platform_device *pdev) + { +- struct clk_hw_onecell_data *clk_data; +- struct device_node *node = pdev->dev.of_node; + int r; + +- clk_data = mtk_alloc_clk_data(CLK_AUD_NR); +- +- mtk_clk_register_gates(&pdev->dev, node, audio_clks, +- ARRAY_SIZE(audio_clks), clk_data); +- +- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); ++ r = mtk_clk_simple_probe(pdev); + if (r) { + dev_err(&pdev->dev, + "could not register clock provider: %s: %d\n", + pdev->name, r); + +- goto err_clk_provider; ++ return r; + } + + r = devm_of_platform_populate(&pdev->dev); +@@ -146,13 +145,19 @@ static int clk_mt2701_aud_probe(struct p + return 0; + + err_plat_populate: +- of_clk_del_provider(node); +-err_clk_provider: ++ mtk_clk_simple_remove(pdev); + return r; + } + ++static int clk_mt2701_aud_remove(struct platform_device *pdev) ++{ ++ of_platform_depopulate(&pdev->dev); ++ return mtk_clk_simple_remove(pdev); ++} ++ + static struct platform_driver clk_mt2701_aud_drv = { + .probe = clk_mt2701_aud_probe, ++ .remove = clk_mt2701_aud_remove, + .driver = { + .name = "clk-mt2701-aud", + .of_match_table = of_match_clk_mt2701_aud, +--- a/drivers/clk/mediatek/clk-mt2701-eth.c ++++ b/drivers/clk/mediatek/clk-mt2701-eth.c +@@ -20,6 +20,7 @@ static const struct mtk_gate_regs eth_cg + GATE_MTK(_id, _name, _parent, ð_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) + + static const struct mtk_gate eth_clks[] = { ++ GATE_DUMMY(CLK_DUMMY, "eth_dummy"), + GATE_ETH(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5), + GATE_ETH(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6), + GATE_ETH(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7), +@@ -38,35 +39,20 @@ static const struct mtk_clk_rst_desc clk + .rst_bank_nr = ARRAY_SIZE(rst_ofs), + }; + +-static const struct of_device_id of_match_clk_mt2701_eth[] = { +- { .compatible = "mediatek,mt2701-ethsys", }, +- {} ++static const struct mtk_clk_desc eth_desc = { ++ .clks = eth_clks, ++ .num_clks = ARRAY_SIZE(eth_clks), ++ .rst_desc = &clk_rst_desc, + }; + +-static int clk_mt2701_eth_probe(struct platform_device *pdev) +-{ +- struct clk_hw_onecell_data *clk_data; +- int r; +- struct device_node *node = pdev->dev.of_node; +- +- clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR); +- +- mtk_clk_register_gates(&pdev->dev, node, eth_clks, +- ARRAY_SIZE(eth_clks), clk_data); +- +- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); +- if (r) +- dev_err(&pdev->dev, +- "could not register clock provider: %s: %d\n", +- pdev->name, r); +- +- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); +- +- return r; +-} ++static const struct of_device_id of_match_clk_mt2701_eth[] = { ++ { .compatible = "mediatek,mt2701-ethsys", .data = ð_desc }, ++ { /* sentinel */ } ++}; + + static struct platform_driver clk_mt2701_eth_drv = { +- .probe = clk_mt2701_eth_probe, ++ .probe = mtk_clk_simple_probe, ++ .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt2701-eth", + .of_match_table = of_match_clk_mt2701_eth, +--- a/drivers/clk/mediatek/clk-mt2701-g3d.c ++++ b/drivers/clk/mediatek/clk-mt2701-g3d.c +@@ -26,6 +26,7 @@ static const struct mtk_gate_regs g3d_cg + }; + + static const struct mtk_gate g3d_clks[] = { ++ GATE_DUMMY(CLK_DUMMY, "g3d_dummy"), + GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0), + }; + +@@ -37,57 +38,20 @@ static const struct mtk_clk_rst_desc clk + .rst_bank_nr = ARRAY_SIZE(rst_ofs), + }; + +-static int clk_mt2701_g3dsys_init(struct platform_device *pdev) +-{ +- struct clk_hw_onecell_data *clk_data; +- struct device_node *node = pdev->dev.of_node; +- int r; +- +- clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR); +- +- mtk_clk_register_gates(&pdev->dev, node, g3d_clks, ARRAY_SIZE(g3d_clks), +- clk_data); +- +- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); +- if (r) +- dev_err(&pdev->dev, +- "could not register clock provider: %s: %d\n", +- pdev->name, r); +- +- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); +- +- return r; +-} ++static const struct mtk_clk_desc g3d_desc = { ++ .clks = g3d_clks, ++ .num_clks = ARRAY_SIZE(g3d_clks), ++ .rst_desc = &clk_rst_desc, ++}; + + static const struct of_device_id of_match_clk_mt2701_g3d[] = { +- { +- .compatible = "mediatek,mt2701-g3dsys", +- .data = clk_mt2701_g3dsys_init, +- }, { +- /* sentinel */ +- } ++ { .compatible = "mediatek,mt2701-g3dsys", .data = &g3d_desc }, ++ { /* sentinel */ } + }; + +-static int clk_mt2701_g3d_probe(struct platform_device *pdev) +-{ +- int (*clk_init)(struct platform_device *); +- int r; +- +- clk_init = of_device_get_match_data(&pdev->dev); +- if (!clk_init) +- return -EINVAL; +- +- r = clk_init(pdev); +- if (r) +- dev_err(&pdev->dev, +- "could not register clock provider: %s: %d\n", +- pdev->name, r); +- +- return r; +-} +- + static struct platform_driver clk_mt2701_g3d_drv = { +- .probe = clk_mt2701_g3d_probe, ++ .probe = mtk_clk_simple_probe, ++ .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt2701-g3d", + .of_match_table = of_match_clk_mt2701_g3d, +--- a/drivers/clk/mediatek/clk-mt2701-hif.c ++++ b/drivers/clk/mediatek/clk-mt2701-hif.c +@@ -20,6 +20,7 @@ static const struct mtk_gate_regs hif_cg + GATE_MTK(_id, _name, _parent, &hif_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) + + static const struct mtk_gate hif_clks[] = { ++ GATE_DUMMY(CLK_DUMMY, "hif_dummy"), + GATE_HIF(CLK_HIFSYS_USB0PHY, "usb0_phy_clk", "ethpll_500m_ck", 21), + GATE_HIF(CLK_HIFSYS_USB1PHY, "usb1_phy_clk", "ethpll_500m_ck", 22), + GATE_HIF(CLK_HIFSYS_PCIE0, "pcie0_clk", "ethpll_500m_ck", 24), +@@ -35,37 +36,20 @@ static const struct mtk_clk_rst_desc clk + .rst_bank_nr = ARRAY_SIZE(rst_ofs), + }; + +-static const struct of_device_id of_match_clk_mt2701_hif[] = { +- { .compatible = "mediatek,mt2701-hifsys", }, +- {} ++static const struct mtk_clk_desc hif_desc = { ++ .clks = hif_clks, ++ .num_clks = ARRAY_SIZE(hif_clks), ++ .rst_desc = &clk_rst_desc, + }; + +-static int clk_mt2701_hif_probe(struct platform_device *pdev) +-{ +- struct clk_hw_onecell_data *clk_data; +- int r; +- struct device_node *node = pdev->dev.of_node; +- +- clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR); +- +- mtk_clk_register_gates(&pdev->dev, node, hif_clks, +- ARRAY_SIZE(hif_clks), clk_data); +- +- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); +- if (r) { +- dev_err(&pdev->dev, +- "could not register clock provider: %s: %d\n", +- pdev->name, r); +- return r; +- } +- +- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); +- +- return 0; +-} ++static const struct of_device_id of_match_clk_mt2701_hif[] = { ++ { .compatible = "mediatek,mt2701-hifsys", .data = &hif_desc }, ++ { /* sentinel */ } ++}; + + static struct platform_driver clk_mt2701_hif_drv = { +- .probe = clk_mt2701_hif_probe, ++ .probe = mtk_clk_simple_probe, ++ .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt2701-hif", + .of_match_table = of_match_clk_mt2701_hif, +--- a/drivers/clk/mediatek/clk-mt2712.c ++++ b/drivers/clk/mediatek/clk-mt2712.c +@@ -1337,50 +1337,6 @@ static int clk_mt2712_top_probe(struct p + return r; + } + +-static int clk_mt2712_infra_probe(struct platform_device *pdev) +-{ +- struct clk_hw_onecell_data *clk_data; +- int r; +- struct device_node *node = pdev->dev.of_node; +- +- clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); +- +- mtk_clk_register_gates(&pdev->dev, node, infra_clks, +- ARRAY_SIZE(infra_clks), clk_data); +- +- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); +- +- if (r != 0) +- pr_err("%s(): could not register clock provider: %d\n", +- __func__, r); +- +- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]); +- +- return r; +-} +- +-static int clk_mt2712_peri_probe(struct platform_device *pdev) +-{ +- struct clk_hw_onecell_data *clk_data; +- int r; +- struct device_node *node = pdev->dev.of_node; +- +- clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); +- +- mtk_clk_register_gates(&pdev->dev, node, peri_clks, +- ARRAY_SIZE(peri_clks), clk_data); +- +- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); +- +- if (r != 0) +- pr_err("%s(): could not register clock provider: %d\n", +- __func__, r); +- +- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]); +- +- return r; +-} +- + static int clk_mt2712_mcu_probe(struct platform_device *pdev) + { + struct clk_hw_onecell_data *clk_data; +@@ -1419,12 +1375,6 @@ static const struct of_device_id of_matc + .compatible = "mediatek,mt2712-topckgen", + .data = clk_mt2712_top_probe, + }, { +- .compatible = "mediatek,mt2712-infracfg", +- .data = clk_mt2712_infra_probe, +- }, { +- .compatible = "mediatek,mt2712-pericfg", +- .data = clk_mt2712_peri_probe, +- }, { + .compatible = "mediatek,mt2712-mcucfg", + .data = clk_mt2712_mcu_probe, + }, { +@@ -1450,6 +1400,33 @@ static int clk_mt2712_probe(struct platf + return r; + } + ++static const struct mtk_clk_desc infra_desc = { ++ .clks = infra_clks, ++ .num_clks = ARRAY_SIZE(infra_clks), ++ .rst_desc = &clk_rst_desc[0], ++}; ++ ++static const struct mtk_clk_desc peri_desc = { ++ .clks = peri_clks, ++ .num_clks = ARRAY_SIZE(peri_clks), ++ .rst_desc = &clk_rst_desc[1], ++}; ++ ++static const struct of_device_id of_match_clk_mt2712_simple[] = { ++ { .compatible = "mediatek,mt2712-infracfg", .data = &infra_desc }, ++ { .compatible = "mediatek,mt2712-pericfg", .data = &peri_desc, }, ++ { /* sentinel */ } ++}; ++ ++static struct platform_driver clk_mt2712_simple_drv = { ++ .probe = mtk_clk_simple_probe, ++ .remove = mtk_clk_simple_remove, ++ .driver = { ++ .name = "clk-mt2712-simple", ++ .of_match_table = of_match_clk_mt2712_simple, ++ }, ++}; ++ + static struct platform_driver clk_mt2712_drv = { + .probe = clk_mt2712_probe, + .driver = { +@@ -1460,7 +1437,11 @@ static struct platform_driver clk_mt2712 + + static int __init clk_mt2712_init(void) + { +- return platform_driver_register(&clk_mt2712_drv); ++ int ret = platform_driver_register(&clk_mt2712_drv); ++ ++ if (ret) ++ return ret; ++ return platform_driver_register(&clk_mt2712_simple_drv); + } + + arch_initcall(clk_mt2712_init); +--- a/drivers/clk/mediatek/clk-mt7622-aud.c ++++ b/drivers/clk/mediatek/clk-mt7622-aud.c +@@ -106,24 +106,22 @@ static const struct mtk_gate audio_clks[ + GATE_AUDIO3(CLK_AUDIO_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14), + }; + +-static int clk_mt7622_audiosys_init(struct platform_device *pdev) ++static const struct mtk_clk_desc audio_desc = { ++ .clks = audio_clks, ++ .num_clks = ARRAY_SIZE(audio_clks), ++}; ++ ++static int clk_mt7622_aud_probe(struct platform_device *pdev) + { +- struct clk_hw_onecell_data *clk_data; +- struct device_node *node = pdev->dev.of_node; + int r; + +- clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK); +- +- mtk_clk_register_gates(&pdev->dev, node, audio_clks, +- ARRAY_SIZE(audio_clks), clk_data); +- +- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); ++ r = mtk_clk_simple_probe(pdev); + if (r) { + dev_err(&pdev->dev, + "could not register clock provider: %s: %d\n", + pdev->name, r); + +- goto err_clk_provider; ++ return r; + } + + r = devm_of_platform_populate(&pdev->dev); +@@ -133,40 +131,24 @@ static int clk_mt7622_audiosys_init(stru + return 0; + + err_plat_populate: +- of_clk_del_provider(node); +-err_clk_provider: ++ mtk_clk_simple_remove(pdev); + return r; + } + +-static const struct of_device_id of_match_clk_mt7622_aud[] = { +- { +- .compatible = "mediatek,mt7622-audsys", +- .data = clk_mt7622_audiosys_init, +- }, { +- /* sentinel */ +- } +-}; +- +-static int clk_mt7622_aud_probe(struct platform_device *pdev) ++static int clk_mt7622_aud_remove(struct platform_device *pdev) + { +- int (*clk_init)(struct platform_device *); +- int r; +- +- clk_init = of_device_get_match_data(&pdev->dev); +- if (!clk_init) +- return -EINVAL; +- +- r = clk_init(pdev); +- if (r) +- dev_err(&pdev->dev, +- "could not register clock provider: %s: %d\n", +- pdev->name, r); +- +- return r; ++ of_platform_depopulate(&pdev->dev); ++ return mtk_clk_simple_remove(pdev); + } + ++static const struct of_device_id of_match_clk_mt7622_aud[] = { ++ { .compatible = "mediatek,mt7622-audsys", .data = &audio_desc }, ++ { /* sentinel */ } ++}; ++ + static struct platform_driver clk_mt7622_aud_drv = { + .probe = clk_mt7622_aud_probe, ++ .remove = clk_mt7622_aud_remove, + .driver = { + .name = "clk-mt7622-aud", + .of_match_table = of_match_clk_mt7622_aud, +--- a/drivers/clk/mediatek/clk-mt7622-eth.c ++++ b/drivers/clk/mediatek/clk-mt7622-eth.c +@@ -61,80 +61,26 @@ static const struct mtk_clk_rst_desc clk + .rst_bank_nr = ARRAY_SIZE(rst_ofs), + }; + +-static int clk_mt7622_ethsys_init(struct platform_device *pdev) +-{ +- struct clk_hw_onecell_data *clk_data; +- struct device_node *node = pdev->dev.of_node; +- int r; +- +- clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK); +- +- mtk_clk_register_gates(&pdev->dev, node, eth_clks, +- ARRAY_SIZE(eth_clks), clk_data); +- +- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); +- if (r) +- dev_err(&pdev->dev, +- "could not register clock provider: %s: %d\n", +- pdev->name, r); +- +- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); +- +- return r; +-} +- +-static int clk_mt7622_sgmiisys_init(struct platform_device *pdev) +-{ +- struct clk_hw_onecell_data *clk_data; +- struct device_node *node = pdev->dev.of_node; +- int r; +- +- clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK); +- +- mtk_clk_register_gates(&pdev->dev, node, sgmii_clks, +- ARRAY_SIZE(sgmii_clks), clk_data); +- +- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); +- if (r) +- dev_err(&pdev->dev, +- "could not register clock provider: %s: %d\n", +- pdev->name, r); ++static const struct mtk_clk_desc eth_desc = { ++ .clks = eth_clks, ++ .num_clks = ARRAY_SIZE(eth_clks), ++ .rst_desc = &clk_rst_desc, ++}; + +- return r; +-} ++static const struct mtk_clk_desc sgmii_desc = { ++ .clks = sgmii_clks, ++ .num_clks = ARRAY_SIZE(sgmii_clks), ++}; + + static const struct of_device_id of_match_clk_mt7622_eth[] = { +- { +- .compatible = "mediatek,mt7622-ethsys", +- .data = clk_mt7622_ethsys_init, +- }, { +- .compatible = "mediatek,mt7622-sgmiisys", +- .data = clk_mt7622_sgmiisys_init, +- }, { +- /* sentinel */ +- } ++ { .compatible = "mediatek,mt7622-ethsys", .data = ð_desc }, ++ { .compatible = "mediatek,mt7622-sgmiisys", .data = &sgmii_desc }, ++ { /* sentinel */ } + }; + +-static int clk_mt7622_eth_probe(struct platform_device *pdev) +-{ +- int (*clk_init)(struct platform_device *); +- int r; +- +- clk_init = of_device_get_match_data(&pdev->dev); +- if (!clk_init) +- return -EINVAL; +- +- r = clk_init(pdev); +- if (r) +- dev_err(&pdev->dev, +- "could not register clock provider: %s: %d\n", +- pdev->name, r); +- +- return r; +-} +- + static struct platform_driver clk_mt7622_eth_drv = { +- .probe = clk_mt7622_eth_probe, ++ .probe = mtk_clk_simple_probe, ++ .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt7622-eth", + .of_match_table = of_match_clk_mt7622_eth, +--- a/drivers/clk/mediatek/clk-mt7622-hif.c ++++ b/drivers/clk/mediatek/clk-mt7622-hif.c +@@ -72,82 +72,27 @@ static const struct mtk_clk_rst_desc clk + .rst_bank_nr = ARRAY_SIZE(rst_ofs), + }; + +-static int clk_mt7622_ssusbsys_init(struct platform_device *pdev) +-{ +- struct clk_hw_onecell_data *clk_data; +- struct device_node *node = pdev->dev.of_node; +- int r; +- +- clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK); +- +- mtk_clk_register_gates(&pdev->dev, node, ssusb_clks, +- ARRAY_SIZE(ssusb_clks), clk_data); +- +- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); +- if (r) +- dev_err(&pdev->dev, +- "could not register clock provider: %s: %d\n", +- pdev->name, r); +- +- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); +- +- return r; +-} +- +-static int clk_mt7622_pciesys_init(struct platform_device *pdev) +-{ +- struct clk_hw_onecell_data *clk_data; +- struct device_node *node = pdev->dev.of_node; +- int r; +- +- clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK); +- +- mtk_clk_register_gates(&pdev->dev, node, pcie_clks, +- ARRAY_SIZE(pcie_clks), clk_data); +- +- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); +- if (r) +- dev_err(&pdev->dev, +- "could not register clock provider: %s: %d\n", +- pdev->name, r); +- +- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); ++static const struct mtk_clk_desc ssusb_desc = { ++ .clks = ssusb_clks, ++ .num_clks = ARRAY_SIZE(ssusb_clks), ++ .rst_desc = &clk_rst_desc, ++}; + +- return r; +-} ++static const struct mtk_clk_desc pcie_desc = { ++ .clks = pcie_clks, ++ .num_clks = ARRAY_SIZE(pcie_clks), ++ .rst_desc = &clk_rst_desc, ++}; + + static const struct of_device_id of_match_clk_mt7622_hif[] = { +- { +- .compatible = "mediatek,mt7622-pciesys", +- .data = clk_mt7622_pciesys_init, +- }, { +- .compatible = "mediatek,mt7622-ssusbsys", +- .data = clk_mt7622_ssusbsys_init, +- }, { +- /* sentinel */ +- } ++ { .compatible = "mediatek,mt7622-pciesys", .data = &pcie_desc }, ++ { .compatible = "mediatek,mt7622-ssusbsys", .data = &ssusb_desc }, ++ { /* sentinel */ } + }; + +-static int clk_mt7622_hif_probe(struct platform_device *pdev) +-{ +- int (*clk_init)(struct platform_device *); +- int r; +- +- clk_init = of_device_get_match_data(&pdev->dev); +- if (!clk_init) +- return -EINVAL; +- +- r = clk_init(pdev); +- if (r) +- dev_err(&pdev->dev, +- "could not register clock provider: %s: %d\n", +- pdev->name, r); +- +- return r; +-} +- + static struct platform_driver clk_mt7622_hif_drv = { +- .probe = clk_mt7622_hif_probe, ++ .probe = mtk_clk_simple_probe, ++ .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt7622-hif", + .of_match_table = of_match_clk_mt7622_hif, +--- a/drivers/clk/mediatek/clk-mt7629-hif.c ++++ b/drivers/clk/mediatek/clk-mt7629-hif.c +@@ -67,82 +67,27 @@ static const struct mtk_clk_rst_desc clk + .rst_bank_nr = ARRAY_SIZE(rst_ofs), + }; + +-static int clk_mt7629_ssusbsys_init(struct platform_device *pdev) +-{ +- struct clk_hw_onecell_data *clk_data; +- struct device_node *node = pdev->dev.of_node; +- int r; +- +- clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK); +- +- mtk_clk_register_gates(&pdev->dev, node, ssusb_clks, +- ARRAY_SIZE(ssusb_clks), clk_data); +- +- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); +- if (r) +- dev_err(&pdev->dev, +- "could not register clock provider: %s: %d\n", +- pdev->name, r); +- +- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); +- +- return r; +-} +- +-static int clk_mt7629_pciesys_init(struct platform_device *pdev) +-{ +- struct clk_hw_onecell_data *clk_data; +- struct device_node *node = pdev->dev.of_node; +- int r; +- +- clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK); +- +- mtk_clk_register_gates(&pdev->dev, node, pcie_clks, +- ARRAY_SIZE(pcie_clks), clk_data); +- +- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); +- if (r) +- dev_err(&pdev->dev, +- "could not register clock provider: %s: %d\n", +- pdev->name, r); +- +- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); ++static const struct mtk_clk_desc ssusb_desc = { ++ .clks = ssusb_clks, ++ .num_clks = ARRAY_SIZE(ssusb_clks), ++ .rst_desc = &clk_rst_desc, ++}; + +- return r; +-} ++static const struct mtk_clk_desc pcie_desc = { ++ .clks = pcie_clks, ++ .num_clks = ARRAY_SIZE(pcie_clks), ++ .rst_desc = &clk_rst_desc, ++}; + + static const struct of_device_id of_match_clk_mt7629_hif[] = { +- { +- .compatible = "mediatek,mt7629-pciesys", +- .data = clk_mt7629_pciesys_init, +- }, { +- .compatible = "mediatek,mt7629-ssusbsys", +- .data = clk_mt7629_ssusbsys_init, +- }, { +- /* sentinel */ +- } ++ { .compatible = "mediatek,mt7629-pciesys", .data = &pcie_desc }, ++ { .compatible = "mediatek,mt7629-ssusbsys", .data = &ssusb_desc }, ++ { /* sentinel */ } + }; + +-static int clk_mt7629_hif_probe(struct platform_device *pdev) +-{ +- int (*clk_init)(struct platform_device *); +- int r; +- +- clk_init = of_device_get_match_data(&pdev->dev); +- if (!clk_init) +- return -EINVAL; +- +- r = clk_init(pdev); +- if (r) +- dev_err(&pdev->dev, +- "could not register clock provider: %s: %d\n", +- pdev->name, r); +- +- return r; +-} +- + static struct platform_driver clk_mt7629_hif_drv = { +- .probe = clk_mt7629_hif_probe, ++ .probe = mtk_clk_simple_probe, ++ .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt7629-hif", + .of_match_table = of_match_clk_mt7629_hif, diff --git a/target/linux/mediatek/patches-6.1/226-v6.3-clk-mediatek-clk-mtk-Extend-mtk_clk_simple_probe.patch b/target/linux/mediatek/patches-6.1/226-v6.3-clk-mediatek-clk-mtk-Extend-mtk_clk_simple_probe.patch new file mode 100644 index 00000000000..ad02df10b6f --- /dev/null +++ b/target/linux/mediatek/patches-6.1/226-v6.3-clk-mediatek-clk-mtk-Extend-mtk_clk_simple_probe.patch @@ -0,0 +1,189 @@ +From 7b6183108c8ccf0dc295f39cdf78bd8078455636 Mon Sep 17 00:00:00 2001 +From: AngeloGioacchino Del Regno +Date: Fri, 20 Jan 2023 10:20:42 +0100 +Subject: [PATCH] clk: mediatek: clk-mtk: Extend mtk_clk_simple_probe() + +As a preparation to increase probe functions commonization across +various MediaTek SoC clock controller drivers, extend function +mtk_clk_simple_probe() to be able to register not only gates, but +also fixed clocks, factors, muxes and composites. + +Signed-off-by: AngeloGioacchino Del Regno +Reviewed-by: Miles Chen +Reviewed-by: Chen-Yu Tsai +Tested-by: Miles Chen +Link: https://lore.kernel.org/r/20230120092053.182923-13-angelogioacchino.delregno@collabora.com +Tested-by: Mingming Su +Signed-off-by: Stephen Boyd +--- + drivers/clk/mediatek/clk-mtk.c | 101 ++++++++++++++++++++++++++++++--- + drivers/clk/mediatek/clk-mtk.h | 10 ++++ + 2 files changed, 103 insertions(+), 8 deletions(-) + +--- a/drivers/clk/mediatek/clk-mtk.c ++++ b/drivers/clk/mediatek/clk-mtk.c +@@ -11,12 +11,14 @@ + #include + #include + #include ++#include + #include + #include + #include + + #include "clk-mtk.h" + #include "clk-gate.h" ++#include "clk-mux.h" + + const struct mtk_gate_regs cg_regs_dummy = { 0, 0, 0 }; + EXPORT_SYMBOL_GPL(cg_regs_dummy); +@@ -466,20 +468,71 @@ int mtk_clk_simple_probe(struct platform + const struct mtk_clk_desc *mcd; + struct clk_hw_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; +- int r; ++ void __iomem *base; ++ int num_clks, r; + + mcd = of_device_get_match_data(&pdev->dev); + if (!mcd) + return -EINVAL; + +- clk_data = mtk_alloc_clk_data(mcd->num_clks); ++ /* Composite clocks needs us to pass iomem pointer */ ++ if (mcd->composite_clks) { ++ if (!mcd->shared_io) ++ base = devm_platform_ioremap_resource(pdev, 0); ++ else ++ base = of_iomap(node, 0); ++ ++ if (IS_ERR_OR_NULL(base)) ++ return IS_ERR(base) ? PTR_ERR(base) : -ENOMEM; ++ } ++ ++ /* Calculate how many clk_hw_onecell_data entries to allocate */ ++ num_clks = mcd->num_clks + mcd->num_composite_clks; ++ num_clks += mcd->num_fixed_clks + mcd->num_factor_clks; ++ num_clks += mcd->num_mux_clks; ++ ++ clk_data = mtk_alloc_clk_data(num_clks); + if (!clk_data) + return -ENOMEM; + +- r = mtk_clk_register_gates(&pdev->dev, node, mcd->clks, mcd->num_clks, +- clk_data); +- if (r) +- goto free_data; ++ if (mcd->fixed_clks) { ++ r = mtk_clk_register_fixed_clks(mcd->fixed_clks, ++ mcd->num_fixed_clks, clk_data); ++ if (r) ++ goto free_data; ++ } ++ ++ if (mcd->factor_clks) { ++ r = mtk_clk_register_factors(mcd->factor_clks, ++ mcd->num_factor_clks, clk_data); ++ if (r) ++ goto unregister_fixed_clks; ++ } ++ ++ if (mcd->mux_clks) { ++ r = mtk_clk_register_muxes(&pdev->dev, mcd->mux_clks, ++ mcd->num_mux_clks, node, ++ mcd->clk_lock, clk_data); ++ if (r) ++ goto unregister_factors; ++ }; ++ ++ if (mcd->composite_clks) { ++ /* We don't check composite_lock because it's optional */ ++ r = mtk_clk_register_composites(&pdev->dev, ++ mcd->composite_clks, ++ mcd->num_composite_clks, ++ base, mcd->clk_lock, clk_data); ++ if (r) ++ goto unregister_muxes; ++ } ++ ++ if (mcd->clks) { ++ r = mtk_clk_register_gates(&pdev->dev, node, mcd->clks, ++ mcd->num_clks, clk_data); ++ if (r) ++ goto unregister_composites; ++ } + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) +@@ -497,9 +550,28 @@ int mtk_clk_simple_probe(struct platform + return r; + + unregister_clks: +- mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data); ++ if (mcd->clks) ++ mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data); ++unregister_composites: ++ if (mcd->composite_clks) ++ mtk_clk_unregister_composites(mcd->composite_clks, ++ mcd->num_composite_clks, clk_data); ++unregister_muxes: ++ if (mcd->mux_clks) ++ mtk_clk_unregister_muxes(mcd->mux_clks, ++ mcd->num_mux_clks, clk_data); ++unregister_factors: ++ if (mcd->factor_clks) ++ mtk_clk_unregister_factors(mcd->factor_clks, ++ mcd->num_factor_clks, clk_data); ++unregister_fixed_clks: ++ if (mcd->fixed_clks) ++ mtk_clk_unregister_fixed_clks(mcd->fixed_clks, ++ mcd->num_fixed_clks, clk_data); + free_data: + mtk_free_clk_data(clk_data); ++ if (mcd->shared_io && base) ++ iounmap(base); + return r; + } + EXPORT_SYMBOL_GPL(mtk_clk_simple_probe); +@@ -511,7 +583,20 @@ int mtk_clk_simple_remove(struct platfor + struct device_node *node = pdev->dev.of_node; + + of_clk_del_provider(node); +- mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data); ++ if (mcd->clks) ++ mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data); ++ if (mcd->composite_clks) ++ mtk_clk_unregister_composites(mcd->composite_clks, ++ mcd->num_composite_clks, clk_data); ++ if (mcd->mux_clks) ++ mtk_clk_unregister_muxes(mcd->mux_clks, ++ mcd->num_mux_clks, clk_data); ++ if (mcd->factor_clks) ++ mtk_clk_unregister_factors(mcd->factor_clks, ++ mcd->num_factor_clks, clk_data); ++ if (mcd->fixed_clks) ++ mtk_clk_unregister_fixed_clks(mcd->fixed_clks, ++ mcd->num_fixed_clks, clk_data); + mtk_free_clk_data(clk_data); + + return 0; +--- a/drivers/clk/mediatek/clk-mtk.h ++++ b/drivers/clk/mediatek/clk-mtk.h +@@ -215,7 +215,17 @@ void mtk_clk_unregister_ref2usb_tx(struc + struct mtk_clk_desc { + const struct mtk_gate *clks; + size_t num_clks; ++ const struct mtk_composite *composite_clks; ++ size_t num_composite_clks; ++ const struct mtk_fixed_clk *fixed_clks; ++ size_t num_fixed_clks; ++ const struct mtk_fixed_factor *factor_clks; ++ size_t num_factor_clks; ++ const struct mtk_mux *mux_clks; ++ size_t num_mux_clks; + const struct mtk_clk_rst_desc *rst_desc; ++ spinlock_t *clk_lock; ++ bool shared_io; + }; + + int mtk_clk_simple_probe(struct platform_device *pdev); diff --git a/target/linux/mediatek/patches-6.1/227-v6.3-clk-mediatek-clk-mt7986-topckgen-Properly-keep-some-.patch b/target/linux/mediatek/patches-6.1/227-v6.3-clk-mediatek-clk-mt7986-topckgen-Properly-keep-some-.patch new file mode 100644 index 00000000000..bf9a172926e --- /dev/null +++ b/target/linux/mediatek/patches-6.1/227-v6.3-clk-mediatek-clk-mt7986-topckgen-Properly-keep-some-.patch @@ -0,0 +1,97 @@ +From 3511004225ce917a4aa6e6ac61481ac60f08f401 Mon Sep 17 00:00:00 2001 +From: AngeloGioacchino Del Regno +Date: Fri, 20 Jan 2023 10:20:52 +0100 +Subject: [PATCH 06/15] clk: mediatek: clk-mt7986-topckgen: Properly keep some + clocks enabled + +Instead of calling clk_prepare_enable() on a bunch of clocks at probe +time, set the CLK_IS_CRITICAL flag to the same as these are required +to be always on, and this is the right way of achieving that. + +Signed-off-by: AngeloGioacchino Del Regno +Reviewed-by: Chen-Yu Tsai +Reviewed-by: Miles Chen +Link: https://lore.kernel.org/r/20230120092053.182923-23-angelogioacchino.delregno@collabora.com +Tested-by: Mingming Su +Signed-off-by: Stephen Boyd +--- + drivers/clk/mediatek/clk-mt7986-topckgen.c | 46 +++++++++++----------- + 1 file changed, 24 insertions(+), 22 deletions(-) + +--- a/drivers/clk/mediatek/clk-mt7986-topckgen.c ++++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c +@@ -202,16 +202,23 @@ static const struct mtk_mux top_muxes[] + MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel", + f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23, + 0x1C0, 10), +- MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents, +- 0x020, 0x024, 0x028, 24, 1, 31, 0x1C0, 11), ++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", ++ f_26m_adc_parents, 0x020, 0x024, 0x028, ++ 24, 1, 31, 0x1C0, 11, ++ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), + /* CLK_CFG_3 */ +- MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", +- dramc_md32_parents, 0x030, 0x034, 0x038, 0, 1, 7, +- 0x1C0, 12), +- MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, +- 0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13), +- MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, +- 0x030, 0x034, 0x038, 16, 2, 23, 0x1C0, 14), ++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", ++ dramc_md32_parents, 0x030, 0x034, 0x038, ++ 0, 1, 7, 0x1C0, 12, ++ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), ++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", ++ sysaxi_parents, 0x030, 0x034, 0x038, ++ 8, 2, 15, 0x1C0, 13, ++ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), ++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", ++ sysapb_parents, 0x030, 0x034, 0x038, ++ 16, 2, 23, 0x1C0, 14, ++ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", + arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, + 31, 0x1C0, 15), +@@ -234,9 +241,10 @@ static const struct mtk_mux top_muxes[] + MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", + sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15, + 0x1C0, 21), +- MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", +- sgm_reg_parents, 0x050, 0x054, 0x058, 16, 1, 23, +- 0x1C0, 22), ++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", ++ sgm_reg_parents, 0x050, 0x054, 0x058, ++ 16, 1, 23, 0x1C0, 22, ++ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, + 0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23), + /* CLK_CFG_6 */ +@@ -252,9 +260,10 @@ static const struct mtk_mux top_muxes[] + f_26m_adc_parents, 0x060, 0x064, 0x068, 24, 1, 31, + 0x1C0, 27), + /* CLK_CFG_7 */ +- MUX_GATE_CLR_SET_UPD(CLK_TOP_F26M_SEL, "csw_f26m_sel", +- f_26m_adc_parents, 0x070, 0x074, 0x078, 0, 1, 7, +- 0x1C0, 28), ++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel", ++ f_26m_adc_parents, 0x070, 0x074, 0x078, ++ 0, 1, 7, 0x1C0, 28, ++ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, + 0x070, 0x074, 0x078, 8, 2, 15, 0x1C0, 29), + MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", +@@ -307,13 +316,6 @@ static int clk_mt7986_topckgen_probe(str + ARRAY_SIZE(top_muxes), node, + &mt7986_clk_lock, clk_data); + +- clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAXI_SEL]->clk); +- clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAPB_SEL]->clk); +- clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_SEL]->clk); +- clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_MD32_SEL]->clk); +- clk_prepare_enable(clk_data->hws[CLK_TOP_F26M_SEL]->clk); +- clk_prepare_enable(clk_data->hws[CLK_TOP_SGM_REG_SEL]->clk); +- + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + + if (r) { diff --git a/target/linux/mediatek/patches-6.1/228-v6.3-clk-mediatek-clk-mt7986-topckgen-Migrate-to-mtk_clk_.patch b/target/linux/mediatek/patches-6.1/228-v6.3-clk-mediatek-clk-mt7986-topckgen-Migrate-to-mtk_clk_.patch new file mode 100644 index 00000000000..d77b859f005 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/228-v6.3-clk-mediatek-clk-mt7986-topckgen-Migrate-to-mtk_clk_.patch @@ -0,0 +1,88 @@ +From 9ce3b4e4719d4eec38b2c8da939c073835573d1d Mon Sep 17 00:00:00 2001 +From: AngeloGioacchino Del Regno +Date: Fri, 20 Jan 2023 10:20:53 +0100 +Subject: [PATCH 07/15] clk: mediatek: clk-mt7986-topckgen: Migrate to + mtk_clk_simple_probe() + +There are no more non-common calls in clk_mt7986_topckgen_probe(): +migrate this driver to mtk_clk_simple_probe(). + +Signed-off-by: AngeloGioacchino Del Regno +Reviewed-by: Miles Chen +Reviewed-by: Chen-Yu Tsai +Link: https://lore.kernel.org/r/20230120092053.182923-24-angelogioacchino.delregno@collabora.com +Tested-by: Mingming Su +Signed-off-by: Stephen Boyd +--- + drivers/clk/mediatek/clk-mt7986-topckgen.c | 55 +++++----------------- + 1 file changed, 13 insertions(+), 42 deletions(-) + +--- a/drivers/clk/mediatek/clk-mt7986-topckgen.c ++++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c +@@ -290,53 +290,24 @@ static const struct mtk_mux top_muxes[] + 0x1C4, 5), + }; + +-static int clk_mt7986_topckgen_probe(struct platform_device *pdev) +-{ +- struct clk_hw_onecell_data *clk_data; +- struct device_node *node = pdev->dev.of_node; +- int r; +- void __iomem *base; +- int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) + +- ARRAY_SIZE(top_muxes); +- +- base = of_iomap(node, 0); +- if (!base) { +- pr_err("%s(): ioremap failed\n", __func__); +- return -ENOMEM; +- } +- +- clk_data = mtk_alloc_clk_data(nr); +- if (!clk_data) +- return -ENOMEM; +- +- mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), +- clk_data); +- mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); +- mtk_clk_register_muxes(&pdev->dev, top_muxes, +- ARRAY_SIZE(top_muxes), node, +- &mt7986_clk_lock, clk_data); +- +- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); +- +- if (r) { +- pr_err("%s(): could not register clock provider: %d\n", +- __func__, r); +- goto free_topckgen_data; +- } +- return r; +- +-free_topckgen_data: +- mtk_free_clk_data(clk_data); +- return r; +-} ++static const struct mtk_clk_desc topck_desc = { ++ .fixed_clks = top_fixed_clks, ++ .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), ++ .factor_clks = top_divs, ++ .num_factor_clks = ARRAY_SIZE(top_divs), ++ .mux_clks = top_muxes, ++ .num_mux_clks = ARRAY_SIZE(top_muxes), ++ .clk_lock = &mt7986_clk_lock, ++}; + + static const struct of_device_id of_match_clk_mt7986_topckgen[] = { +- { .compatible = "mediatek,mt7986-topckgen", }, +- {} ++ { .compatible = "mediatek,mt7986-topckgen", .data = &topck_desc }, ++ { /* sentinel */ } + }; + + static struct platform_driver clk_mt7986_topckgen_drv = { +- .probe = clk_mt7986_topckgen_probe, ++ .probe = mtk_clk_simple_probe, ++ .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt7986-topckgen", + .of_match_table = of_match_clk_mt7986_topckgen, diff --git a/target/linux/mediatek/patches-6.1/229-v6.4-clk-mediatek-mt7986-apmixed-Use-PLL_AO-flag-to-set-c.patch b/target/linux/mediatek/patches-6.1/229-v6.4-clk-mediatek-mt7986-apmixed-Use-PLL_AO-flag-to-set-c.patch new file mode 100644 index 00000000000..a47dd4b0539 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/229-v6.4-clk-mediatek-mt7986-apmixed-Use-PLL_AO-flag-to-set-c.patch @@ -0,0 +1,38 @@ +From 06abdc84080729dc2c54946e1712c5ee1589ca1c Mon Sep 17 00:00:00 2001 +From: AngeloGioacchino Del Regno +Date: Mon, 6 Mar 2023 15:05:21 +0100 +Subject: [PATCH 13/15] clk: mediatek: mt7986-apmixed: Use PLL_AO flag to set + critical clock + +Instead of calling clk_prepare_enable() at probe time, add the PLL_AO +flag to CLK_APMIXED_ARMPLL clock: this will set CLK_IS_CRITICAL. + +Signed-off-by: AngeloGioacchino Del Regno +Reviewed-by: Chen-Yu Tsai +Tested-by: Daniel Golle +Link: https://lore.kernel.org/r/20230306140543.1813621-33-angelogioacchino.delregno@collabora.com +Signed-off-by: Stephen Boyd +--- + drivers/clk/mediatek/clk-mt7986-apmixed.c | 4 +--- + 1 file changed, 1 insertion(+), 3 deletions(-) + +--- a/drivers/clk/mediatek/clk-mt7986-apmixed.c ++++ b/drivers/clk/mediatek/clk-mt7986-apmixed.c +@@ -42,7 +42,7 @@ + "clkxtal") + + static const struct mtk_pll_data plls[] = { +- PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, 0, 32, ++ PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, PLL_AO, 32, + 0x0200, 4, 0, 0x0204, 0), + PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x0, 0, 32, + 0x0210, 4, 0, 0x0214, 0), +@@ -77,8 +77,6 @@ static int clk_mt7986_apmixed_probe(stru + + mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + +- clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk); +- + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) { + pr_err("%s(): could not register clock provider: %d\n", diff --git a/target/linux/mediatek/patches-6.1/230-v6.4-dt-bindings-clock-mediatek-add-mt7981-clock-IDs.patch b/target/linux/mediatek/patches-6.1/230-v6.4-dt-bindings-clock-mediatek-add-mt7981-clock-IDs.patch new file mode 100644 index 00000000000..ae76940e1d8 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/230-v6.4-dt-bindings-clock-mediatek-add-mt7981-clock-IDs.patch @@ -0,0 +1,237 @@ +From a6473d0f9f07b1196f3a67099826f50a2a4e84e8 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Thu, 26 Jan 2023 03:34:05 +0000 +Subject: [PATCH] dt-bindings: clock: mediatek: add mt7981 clock IDs + +Add MT7981 clock dt-bindings, include topckgen, apmixedsys, +infracfg, and ethernet subsystem clocks. + +Acked-by: Krzysztof Kozlowski +Signed-off-by: Jianhui Zhao +Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/e353d32b5a4481766519a037afe1ed44e31ece1a.1674703830.git.daniel@makrotopia.org +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Stephen Boyd +--- + .../dt-bindings/clock/mediatek,mt7981-clk.h | 215 ++++++++++++++++++ + 1 file changed, 215 insertions(+) + create mode 100644 include/dt-bindings/clock/mediatek,mt7981-clk.h + +--- /dev/null ++++ b/include/dt-bindings/clock/mediatek,mt7981-clk.h +@@ -0,0 +1,215 @@ ++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ ++/* ++ * Copyright (c) 2021 MediaTek Inc. ++ * Author: Wenzhen.Yu ++ * Author: Jianhui Zhao ++ * Author: Daniel Golle ++ */ ++ ++#ifndef _DT_BINDINGS_CLK_MT7981_H ++#define _DT_BINDINGS_CLK_MT7981_H ++ ++/* TOPCKGEN */ ++#define CLK_TOP_CB_CKSQ_40M 0 ++#define CLK_TOP_CB_M_416M 1 ++#define CLK_TOP_CB_M_D2 2 ++#define CLK_TOP_CB_M_D3 3 ++#define CLK_TOP_M_D3_D2 4 ++#define CLK_TOP_CB_M_D4 5 ++#define CLK_TOP_CB_M_D8 6 ++#define CLK_TOP_M_D8_D2 7 ++#define CLK_TOP_CB_MM_720M 8 ++#define CLK_TOP_CB_MM_D2 9 ++#define CLK_TOP_CB_MM_D3 10 ++#define CLK_TOP_CB_MM_D3_D5 11 ++#define CLK_TOP_CB_MM_D4 12 ++#define CLK_TOP_CB_MM_D6 13 ++#define CLK_TOP_MM_D6_D2 14 ++#define CLK_TOP_CB_MM_D8 15 ++#define CLK_TOP_CB_APLL2_196M 16 ++#define CLK_TOP_APLL2_D2 17 ++#define CLK_TOP_APLL2_D4 18 ++#define CLK_TOP_NET1_2500M 19 ++#define CLK_TOP_CB_NET1_D4 20 ++#define CLK_TOP_CB_NET1_D5 21 ++#define CLK_TOP_NET1_D5_D2 22 ++#define CLK_TOP_NET1_D5_D4 23 ++#define CLK_TOP_CB_NET1_D8 24 ++#define CLK_TOP_NET1_D8_D2 25 ++#define CLK_TOP_NET1_D8_D4 26 ++#define CLK_TOP_CB_NET2_800M 27 ++#define CLK_TOP_CB_NET2_D2 28 ++#define CLK_TOP_CB_NET2_D4 29 ++#define CLK_TOP_NET2_D4_D2 30 ++#define CLK_TOP_NET2_D4_D4 31 ++#define CLK_TOP_CB_NET2_D6 32 ++#define CLK_TOP_CB_WEDMCU_208M 33 ++#define CLK_TOP_CB_SGM_325M 34 ++#define CLK_TOP_CKSQ_40M_D2 35 ++#define CLK_TOP_CB_RTC_32K 36 ++#define CLK_TOP_CB_RTC_32P7K 37 ++#define CLK_TOP_USB_TX250M 38 ++#define CLK_TOP_FAUD 39 ++#define CLK_TOP_NFI1X 40 ++#define CLK_TOP_USB_EQ_RX250M 41 ++#define CLK_TOP_USB_CDR_CK 42 ++#define CLK_TOP_USB_LN0_CK 43 ++#define CLK_TOP_SPINFI_BCK 44 ++#define CLK_TOP_SPI 45 ++#define CLK_TOP_SPIM_MST 46 ++#define CLK_TOP_UART_BCK 47 ++#define CLK_TOP_PWM_BCK 48 ++#define CLK_TOP_I2C_BCK 49 ++#define CLK_TOP_PEXTP_TL 50 ++#define CLK_TOP_EMMC_208M 51 ++#define CLK_TOP_EMMC_400M 52 ++#define CLK_TOP_DRAMC_REF 53 ++#define CLK_TOP_DRAMC_MD32 54 ++#define CLK_TOP_SYSAXI 55 ++#define CLK_TOP_SYSAPB 56 ++#define CLK_TOP_ARM_DB_MAIN 57 ++#define CLK_TOP_AP2CNN_HOST 58 ++#define CLK_TOP_NETSYS 59 ++#define CLK_TOP_NETSYS_500M 60 ++#define CLK_TOP_NETSYS_WED_MCU 61 ++#define CLK_TOP_NETSYS_2X 62 ++#define CLK_TOP_SGM_325M 63 ++#define CLK_TOP_SGM_REG 64 ++#define CLK_TOP_F26M 65 ++#define CLK_TOP_EIP97B 66 ++#define CLK_TOP_USB3_PHY 67 ++#define CLK_TOP_AUD 68 ++#define CLK_TOP_A1SYS 69 ++#define CLK_TOP_AUD_L 70 ++#define CLK_TOP_A_TUNER 71 ++#define CLK_TOP_U2U3_REF 72 ++#define CLK_TOP_U2U3_SYS 73 ++#define CLK_TOP_U2U3_XHCI 74 ++#define CLK_TOP_USB_FRMCNT 75 ++#define CLK_TOP_NFI1X_SEL 76 ++#define CLK_TOP_SPINFI_SEL 77 ++#define CLK_TOP_SPI_SEL 78 ++#define CLK_TOP_SPIM_MST_SEL 79 ++#define CLK_TOP_UART_SEL 80 ++#define CLK_TOP_PWM_SEL 81 ++#define CLK_TOP_I2C_SEL 82 ++#define CLK_TOP_PEXTP_TL_SEL 83 ++#define CLK_TOP_EMMC_208M_SEL 84 ++#define CLK_TOP_EMMC_400M_SEL 85 ++#define CLK_TOP_F26M_SEL 86 ++#define CLK_TOP_DRAMC_SEL 87 ++#define CLK_TOP_DRAMC_MD32_SEL 88 ++#define CLK_TOP_SYSAXI_SEL 89 ++#define CLK_TOP_SYSAPB_SEL 90 ++#define CLK_TOP_ARM_DB_MAIN_SEL 91 ++#define CLK_TOP_AP2CNN_HOST_SEL 92 ++#define CLK_TOP_NETSYS_SEL 93 ++#define CLK_TOP_NETSYS_500M_SEL 94 ++#define CLK_TOP_NETSYS_MCU_SEL 95 ++#define CLK_TOP_NETSYS_2X_SEL 96 ++#define CLK_TOP_SGM_325M_SEL 97 ++#define CLK_TOP_SGM_REG_SEL 98 ++#define CLK_TOP_EIP97B_SEL 99 ++#define CLK_TOP_USB3_PHY_SEL 100 ++#define CLK_TOP_AUD_SEL 101 ++#define CLK_TOP_A1SYS_SEL 102 ++#define CLK_TOP_AUD_L_SEL 103 ++#define CLK_TOP_A_TUNER_SEL 104 ++#define CLK_TOP_U2U3_SEL 105 ++#define CLK_TOP_U2U3_SYS_SEL 106 ++#define CLK_TOP_U2U3_XHCI_SEL 107 ++#define CLK_TOP_USB_FRMCNT_SEL 108 ++#define CLK_TOP_AUD_I2S_M 109 ++ ++/* INFRACFG */ ++#define CLK_INFRA_66M_MCK 0 ++#define CLK_INFRA_UART0_SEL 1 ++#define CLK_INFRA_UART1_SEL 2 ++#define CLK_INFRA_UART2_SEL 3 ++#define CLK_INFRA_SPI0_SEL 4 ++#define CLK_INFRA_SPI1_SEL 5 ++#define CLK_INFRA_SPI2_SEL 6 ++#define CLK_INFRA_PWM1_SEL 7 ++#define CLK_INFRA_PWM2_SEL 8 ++#define CLK_INFRA_PWM3_SEL 9 ++#define CLK_INFRA_PWM_BSEL 10 ++#define CLK_INFRA_PCIE_SEL 11 ++#define CLK_INFRA_GPT_STA 12 ++#define CLK_INFRA_PWM_HCK 13 ++#define CLK_INFRA_PWM_STA 14 ++#define CLK_INFRA_PWM1_CK 15 ++#define CLK_INFRA_PWM2_CK 16 ++#define CLK_INFRA_PWM3_CK 17 ++#define CLK_INFRA_CQ_DMA_CK 18 ++#define CLK_INFRA_AUD_BUS_CK 19 ++#define CLK_INFRA_AUD_26M_CK 20 ++#define CLK_INFRA_AUD_L_CK 21 ++#define CLK_INFRA_AUD_AUD_CK 22 ++#define CLK_INFRA_AUD_EG2_CK 23 ++#define CLK_INFRA_DRAMC_26M_CK 24 ++#define CLK_INFRA_DBG_CK 25 ++#define CLK_INFRA_AP_DMA_CK 26 ++#define CLK_INFRA_SEJ_CK 27 ++#define CLK_INFRA_SEJ_13M_CK 28 ++#define CLK_INFRA_THERM_CK 29 ++#define CLK_INFRA_I2C0_CK 30 ++#define CLK_INFRA_UART0_CK 31 ++#define CLK_INFRA_UART1_CK 32 ++#define CLK_INFRA_UART2_CK 33 ++#define CLK_INFRA_SPI2_CK 34 ++#define CLK_INFRA_SPI2_HCK_CK 35 ++#define CLK_INFRA_NFI1_CK 36 ++#define CLK_INFRA_SPINFI1_CK 37 ++#define CLK_INFRA_NFI_HCK_CK 38 ++#define CLK_INFRA_SPI0_CK 39 ++#define CLK_INFRA_SPI1_CK 40 ++#define CLK_INFRA_SPI0_HCK_CK 41 ++#define CLK_INFRA_SPI1_HCK_CK 42 ++#define CLK_INFRA_FRTC_CK 43 ++#define CLK_INFRA_MSDC_CK 44 ++#define CLK_INFRA_MSDC_HCK_CK 45 ++#define CLK_INFRA_MSDC_133M_CK 46 ++#define CLK_INFRA_MSDC_66M_CK 47 ++#define CLK_INFRA_ADC_26M_CK 48 ++#define CLK_INFRA_ADC_FRC_CK 49 ++#define CLK_INFRA_FBIST2FPC_CK 50 ++#define CLK_INFRA_I2C_MCK_CK 51 ++#define CLK_INFRA_I2C_PCK_CK 52 ++#define CLK_INFRA_IUSB_133_CK 53 ++#define CLK_INFRA_IUSB_66M_CK 54 ++#define CLK_INFRA_IUSB_SYS_CK 55 ++#define CLK_INFRA_IUSB_CK 56 ++#define CLK_INFRA_IPCIE_CK 57 ++#define CLK_INFRA_IPCIE_PIPE_CK 58 ++#define CLK_INFRA_IPCIER_CK 59 ++#define CLK_INFRA_IPCIEB_CK 60 ++ ++/* APMIXEDSYS */ ++#define CLK_APMIXED_ARMPLL 0 ++#define CLK_APMIXED_NET2PLL 1 ++#define CLK_APMIXED_MMPLL 2 ++#define CLK_APMIXED_SGMPLL 3 ++#define CLK_APMIXED_WEDMCUPLL 4 ++#define CLK_APMIXED_NET1PLL 5 ++#define CLK_APMIXED_MPLL 6 ++#define CLK_APMIXED_APLL2 7 ++ ++/* SGMIISYS_0 */ ++#define CLK_SGM0_TX_EN 0 ++#define CLK_SGM0_RX_EN 1 ++#define CLK_SGM0_CK0_EN 2 ++#define CLK_SGM0_CDR_CK0_EN 3 ++ ++/* SGMIISYS_1 */ ++#define CLK_SGM1_TX_EN 0 ++#define CLK_SGM1_RX_EN 1 ++#define CLK_SGM1_CK1_EN 2 ++#define CLK_SGM1_CDR_CK1_EN 3 ++ ++/* ETHSYS */ ++#define CLK_ETH_FE_EN 0 ++#define CLK_ETH_GP2_EN 1 ++#define CLK_ETH_GP1_EN 2 ++#define CLK_ETH_WOCPU0_EN 3 ++ ++#endif /* _DT_BINDINGS_CLK_MT7981_H */ diff --git a/target/linux/mediatek/patches-6.1/231-v6.4-clk-mediatek-add-MT7981-clock-support.patch b/target/linux/mediatek/patches-6.1/231-v6.4-clk-mediatek-add-MT7981-clock-support.patch new file mode 100644 index 00000000000..f9dd94a78a5 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/231-v6.4-clk-mediatek-add-MT7981-clock-support.patch @@ -0,0 +1,932 @@ +From 8efeeb9c8b4ecf4fb4a74be9403aba951403bbaa Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Thu, 26 Jan 2023 03:34:24 +0000 +Subject: [PATCH] clk: mediatek: add MT7981 clock support + +Add MT7981 clock support, include topckgen, apmixedsys, infracfg and +ethernet subsystem clocks. + +The drivers are based on clk-mt7981.c which can be found in MediaTek's +SDK sources. To be fit for upstream inclusion the driver has been split +into clock domains and the infracfg part has been significantly +de-bloated by removing all the 1:1 factors (aliases). + +Signed-off-by: Jianhui Zhao +Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/8136eb5b2049177bc2f6d3e0f2aefecc342d626f.1674703830.git.daniel@makrotopia.org +Reviewed-by: AngeloGioacchino Del Regno +[sboyd@kernel.org: Add module license] +Signed-off-by: Stephen Boyd +--- + drivers/clk/mediatek/Kconfig | 17 + + drivers/clk/mediatek/Makefile | 4 + + drivers/clk/mediatek/clk-mt7981-apmixed.c | 102 +++++ + drivers/clk/mediatek/clk-mt7981-eth.c | 118 ++++++ + drivers/clk/mediatek/clk-mt7981-infracfg.c | 207 ++++++++++ + drivers/clk/mediatek/clk-mt7981-topckgen.c | 422 +++++++++++++++++++++ + 6 files changed, 870 insertions(+) + create mode 100644 drivers/clk/mediatek/clk-mt7981-apmixed.c + create mode 100644 drivers/clk/mediatek/clk-mt7981-eth.c + create mode 100644 drivers/clk/mediatek/clk-mt7981-infracfg.c + create mode 100644 drivers/clk/mediatek/clk-mt7981-topckgen.c + +--- a/drivers/clk/mediatek/Kconfig ++++ b/drivers/clk/mediatek/Kconfig +@@ -381,6 +381,23 @@ config COMMON_CLK_MT7629_HIFSYS + This driver supports MediaTek MT7629 HIFSYS clocks providing + to PCI-E and USB. + ++config COMMON_CLK_MT7981 ++ bool "Clock driver for MediaTek MT7981" ++ depends on ARCH_MEDIATEK || COMPILE_TEST ++ select COMMON_CLK_MEDIATEK ++ default ARCH_MEDIATEK ++ help ++ This driver supports MediaTek MT7981 basic clocks and clocks ++ required for various peripherals found on this SoC. ++ ++config COMMON_CLK_MT7981_ETHSYS ++ tristate "Clock driver for MediaTek MT7981 ETHSYS" ++ depends on COMMON_CLK_MT7981 ++ default COMMON_CLK_MT7981 ++ help ++ This driver adds support for clocks for Ethernet and SGMII ++ required on MediaTek MT7981 SoC. ++ + config COMMON_CLK_MT7986 + bool "Clock driver for MediaTek MT7986" + depends on ARCH_MEDIATEK || COMPILE_TEST +--- a/drivers/clk/mediatek/Makefile ++++ b/drivers/clk/mediatek/Makefile +@@ -52,6 +52,10 @@ obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) + + obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o + obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o + obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o ++obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-apmixed.o ++obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-topckgen.o ++obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-infracfg.o ++obj-$(CONFIG_COMMON_CLK_MT7981_ETHSYS) += clk-mt7981-eth.o + obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-apmixed.o + obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o + obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o +--- /dev/null ++++ b/drivers/clk/mediatek/clk-mt7981-apmixed.c +@@ -0,0 +1,102 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2021 MediaTek Inc. ++ * Author: Sam Shih ++ * Author: Wenzhen Yu ++ * Author: Jianhui Zhao ++ * Author: Daniel Golle ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "clk-gate.h" ++#include "clk-mtk.h" ++#include "clk-mux.h" ++#include "clk-pll.h" ++ ++#include ++#include ++ ++#define MT7981_PLL_FMAX (2500UL * MHZ) ++#define CON0_MT7981_RST_BAR BIT(27) ++ ++#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ ++ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ ++ _div_table, _parent_name) \ ++ { \ ++ .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \ ++ .en_mask = _en_mask, .flags = _flags, \ ++ .rst_bar_mask = CON0_MT7981_RST_BAR, .fmax = MT7981_PLL_FMAX, \ ++ .pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \ ++ .tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg, \ ++ .pcw_shift = _pcw_shift, .div_table = _div_table, \ ++ .parent_name = _parent_name, \ ++ } ++ ++#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ ++ _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) \ ++ PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ ++ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL, \ ++ "clkxtal") ++ ++static const struct mtk_pll_data plls[] = { ++ PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, PLL_AO, ++ 32, 0x0200, 4, 0, 0x0204, 0), ++ PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32, ++ 0x0210, 4, 0, 0x0214, 0), ++ PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32, ++ 0x0220, 4, 0, 0x0224, 0), ++ PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023C, 0x00000001, 0, 32, ++ 0x0230, 4, 0, 0x0234, 0), ++ PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024C, 0x00000001, 0, 32, ++ 0x0240, 4, 0, 0x0244, 0), ++ PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025C, 0x00000001, 0, 32, ++ 0x0250, 4, 0, 0x0254, 0), ++ PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32, ++ 0x0260, 4, 0, 0x0264, 0), ++ PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32, ++ 0x0278, 4, 0, 0x027C, 0), ++}; ++ ++static const struct of_device_id of_match_clk_mt7981_apmixed[] = { ++ { .compatible = "mediatek,mt7981-apmixedsys", }, ++ { /* sentinel */ } ++}; ++ ++static int clk_mt7981_apmixed_probe(struct platform_device *pdev) ++{ ++ struct clk_hw_onecell_data *clk_data; ++ struct device_node *node = pdev->dev.of_node; ++ int r; ++ ++ clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls)); ++ if (!clk_data) ++ return -ENOMEM; ++ ++ mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); ++ ++ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); ++ if (r) { ++ pr_err("%s(): could not register clock provider: %d\n", ++ __func__, r); ++ goto free_apmixed_data; ++ } ++ return r; ++ ++free_apmixed_data: ++ mtk_free_clk_data(clk_data); ++ return r; ++} ++ ++static struct platform_driver clk_mt7981_apmixed_drv = { ++ .probe = clk_mt7981_apmixed_probe, ++ .driver = { ++ .name = "clk-mt7981-apmixed", ++ .of_match_table = of_match_clk_mt7981_apmixed, ++ }, ++}; ++builtin_platform_driver(clk_mt7981_apmixed_drv); +--- /dev/null ++++ b/drivers/clk/mediatek/clk-mt7981-eth.c +@@ -0,0 +1,118 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2021 MediaTek Inc. ++ * Author: Sam Shih ++ * Author: Wenzhen Yu ++ * Author: Jianhui Zhao ++ * Author: Daniel Golle ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "clk-mtk.h" ++#include "clk-gate.h" ++ ++#include ++ ++static const struct mtk_gate_regs sgmii0_cg_regs = { ++ .set_ofs = 0xE4, ++ .clr_ofs = 0xE4, ++ .sta_ofs = 0xE4, ++}; ++ ++#define GATE_SGMII0(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &sgmii0_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ ++ } ++ ++static const struct mtk_gate sgmii0_clks[] __initconst = { ++ GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "usb_tx250m", 2), ++ GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "usb_eq_rx250m", 3), ++ GATE_SGMII0(CLK_SGM0_CK0_EN, "sgm0_ck0_en", "usb_ln0", 4), ++ GATE_SGMII0(CLK_SGM0_CDR_CK0_EN, "sgm0_cdr_ck0_en", "usb_cdr", 5), ++}; ++ ++static const struct mtk_gate_regs sgmii1_cg_regs = { ++ .set_ofs = 0xE4, ++ .clr_ofs = 0xE4, ++ .sta_ofs = 0xE4, ++}; ++ ++#define GATE_SGMII1(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &sgmii1_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ ++ } ++ ++static const struct mtk_gate sgmii1_clks[] __initconst = { ++ GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "usb_tx250m", 2), ++ GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "usb_eq_rx250m", 3), ++ GATE_SGMII1(CLK_SGM1_CK1_EN, "sgm1_ck1_en", "usb_ln0", 4), ++ GATE_SGMII1(CLK_SGM1_CDR_CK1_EN, "sgm1_cdr_ck1_en", "usb_cdr", 5), ++}; ++ ++static const struct mtk_gate_regs eth_cg_regs = { ++ .set_ofs = 0x30, ++ .clr_ofs = 0x30, ++ .sta_ofs = 0x30, ++}; ++ ++#define GATE_ETH(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = ð_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ ++ } ++ ++static const struct mtk_gate eth_clks[] __initconst = { ++ GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x", 6), ++ GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m", 7), ++ GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m", 8), ++ GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_wed_mcu", 15), ++}; ++ ++static const struct mtk_clk_desc eth_desc = { ++ .clks = eth_clks, ++ .num_clks = ARRAY_SIZE(eth_clks), ++}; ++ ++static const struct mtk_clk_desc sgmii0_desc = { ++ .clks = sgmii0_clks, ++ .num_clks = ARRAY_SIZE(sgmii0_clks), ++}; ++ ++static const struct mtk_clk_desc sgmii1_desc = { ++ .clks = sgmii1_clks, ++ .num_clks = ARRAY_SIZE(sgmii1_clks), ++}; ++ ++static const struct of_device_id of_match_clk_mt7981_eth[] = { ++ { .compatible = "mediatek,mt7981-ethsys", .data = ð_desc }, ++ { .compatible = "mediatek,mt7981-sgmiisys_0", .data = &sgmii0_desc }, ++ { .compatible = "mediatek,mt7981-sgmiisys_1", .data = &sgmii1_desc }, ++ { /* sentinel */ } ++}; ++ ++static struct platform_driver clk_mt7981_eth_drv = { ++ .probe = mtk_clk_simple_probe, ++ .remove = mtk_clk_simple_remove, ++ .driver = { ++ .name = "clk-mt7981-eth", ++ .of_match_table = of_match_clk_mt7981_eth, ++ }, ++}; ++module_platform_driver(clk_mt7981_eth_drv); ++MODULE_LICENSE("GPL v2"); +--- /dev/null ++++ b/drivers/clk/mediatek/clk-mt7981-infracfg.c +@@ -0,0 +1,207 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2021 MediaTek Inc. ++ * Author: Sam Shih ++ * Author: Wenzhen Yu ++ * Author: Jianhui Zhao ++ * Author: Daniel Golle ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include "clk-mtk.h" ++#include "clk-gate.h" ++#include "clk-mux.h" ++ ++#include ++#include ++ ++static DEFINE_SPINLOCK(mt7981_clk_lock); ++ ++static const struct mtk_fixed_factor infra_divs[] = { ++ FACTOR(CLK_INFRA_66M_MCK, "infra_66m_mck", "sysaxi_sel", 1, 2), ++}; ++ ++static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel", ++ "uart_sel" }; ++ ++static const char *const infra_spi0_parents[] __initconst = { "i2c_sel", ++ "spi_sel" }; ++ ++static const char *const infra_spi1_parents[] __initconst = { "i2c_sel", ++ "spim_mst_sel" }; ++ ++static const char *const infra_pwm1_parents[] __initconst = { "pwm_sel" }; ++ ++static const char *const infra_pwm_bsel_parents[] __initconst = { ++ "cb_rtc_32p7k", "csw_f26m_sel", "infra_66m_mck", "pwm_sel" ++}; ++ ++static const char *const infra_pcie_parents[] __initconst = { ++ "cb_rtc_32p7k", "csw_f26m_sel", "cb_cksq_40m", "pextp_tl_ck_sel" ++}; ++ ++static const struct mtk_mux infra_muxes[] = { ++ /* MODULE_CLK_SEL_0 */ ++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel", ++ infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1, ++ -1, -1, -1), ++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel", ++ infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1, ++ -1, -1, -1), ++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel", ++ infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1, ++ -1, -1, -1), ++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel", ++ infra_spi0_parents, 0x0018, 0x0010, 0x0014, 4, 1, ++ -1, -1, -1), ++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel", ++ infra_spi1_parents, 0x0018, 0x0010, 0x0014, 5, 1, ++ -1, -1, -1), ++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI2_SEL, "infra_spi2_sel", ++ infra_spi0_parents, 0x0018, 0x0010, 0x0014, 6, 1, ++ -1, -1, -1), ++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel", ++ infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 9, 1, ++ -1, -1, -1), ++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel", ++ infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 11, 1, ++ -1, -1, -1), ++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM3_SEL, "infra_pwm3_sel", ++ infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 15, 1, ++ -1, -1, -1), ++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel", ++ infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13, ++ 2, -1, -1, -1), ++ /* MODULE_CLK_SEL_1 */ ++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel", ++ infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2, ++ -1, -1, -1), ++}; ++ ++static const struct mtk_gate_regs infra0_cg_regs = { ++ .set_ofs = 0x40, ++ .clr_ofs = 0x44, ++ .sta_ofs = 0x48, ++}; ++ ++static const struct mtk_gate_regs infra1_cg_regs = { ++ .set_ofs = 0x50, ++ .clr_ofs = 0x54, ++ .sta_ofs = 0x58, ++}; ++ ++static const struct mtk_gate_regs infra2_cg_regs = { ++ .set_ofs = 0x60, ++ .clr_ofs = 0x64, ++ .sta_ofs = 0x68, ++}; ++ ++#define GATE_INFRA0(_id, _name, _parent, _shift) \ ++ { \ ++ .id = _id, .name = _name, .parent_name = _parent, \ ++ .regs = &infra0_cg_regs, .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_setclr, \ ++ } ++ ++#define GATE_INFRA1(_id, _name, _parent, _shift) \ ++ { \ ++ .id = _id, .name = _name, .parent_name = _parent, \ ++ .regs = &infra1_cg_regs, .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_setclr, \ ++ } ++ ++#define GATE_INFRA2(_id, _name, _parent, _shift) \ ++ { \ ++ .id = _id, .name = _name, .parent_name = _parent, \ ++ .regs = &infra2_cg_regs, .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_setclr, \ ++ } ++ ++static const struct mtk_gate infra_clks[] = { ++ /* INFRA0 */ ++ GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_66m_mck", 0), ++ GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_66m_mck", 1), ++ GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2), ++ GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3), ++ GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4), ++ GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi", 6), ++ ++ GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi", 8), ++ GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9), ++ GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l", 10), ++ GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys", 11), ++ GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner", 13), ++ GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel", ++ 14), ++ GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_66m_mck", 15), ++ GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_66m_mck", 16), ++ GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_66m_mck", 24), ++ GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25), ++ GATE_INFRA0(CLK_INFRA_PWM3_CK, "infra_pwm3", "infra_pwm3_sel", 27), ++ /* INFRA1 */ ++ GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0), ++ GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_bck", 1), ++ GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2), ++ GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3), ++ GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4), ++ GATE_INFRA1(CLK_INFRA_SPI2_CK, "infra_spi2", "infra_spi2_sel", 6), ++ GATE_INFRA1(CLK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", "infra_66m_mck", 7), ++ GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x", 8), ++ GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_bck", 9), ++ GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_66m_mck", 10), ++ GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11), ++ GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12), ++ GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_66m_mck", ++ 13), ++ GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_66m_mck", ++ 14), ++ GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "cb_rtc_32k", 15), ++ GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_400m", 16), ++ GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_208m", 17), ++ GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi", 18), ++ GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "sysaxi", 19), ++ GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20), ++ GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m", 21), ++ GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x", 23), ++ GATE_INFRA1(CLK_INFRA_I2C_MCK_CK, "infra_i2c_mck", "sysaxi", 25), ++ GATE_INFRA1(CLK_INFRA_I2C_PCK_CK, "infra_i2c_pck", "infra_66m_mck", 26), ++ /* INFRA2 */ ++ GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi", 0), ++ GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "sysaxi", 1), ++ GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys", 2), ++ GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_ref", 3), ++ GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl", 12), ++ GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "cb_cksq_40m", ++ 13), ++ GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m", 14), ++ GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi", 15), ++}; ++ ++static const struct mtk_clk_desc infracfg_desc = { ++ .factor_clks = infra_divs, ++ .num_factor_clks = ARRAY_SIZE(infra_divs), ++ .mux_clks = infra_muxes, ++ .num_mux_clks = ARRAY_SIZE(infra_muxes), ++ .clks = infra_clks, ++ .num_clks = ARRAY_SIZE(infra_clks), ++ .clk_lock = &mt7981_clk_lock, ++}; ++ ++static const struct of_device_id of_match_clk_mt7981_infracfg[] = { ++ { .compatible = "mediatek,mt7981-infracfg", .data = &infracfg_desc }, ++ { /* sentinel */ } ++}; ++ ++static struct platform_driver clk_mt7981_infracfg_drv = { ++ .probe = mtk_clk_simple_probe, ++ .remove = mtk_clk_simple_remove, ++ .driver = { ++ .name = "clk-mt7981-infracfg", ++ .of_match_table = of_match_clk_mt7981_infracfg, ++ }, ++}; ++builtin_platform_driver(clk_mt7981_infracfg_drv); +--- /dev/null ++++ b/drivers/clk/mediatek/clk-mt7981-topckgen.c +@@ -0,0 +1,422 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2021 MediaTek Inc. ++ * Author: Sam Shih ++ * Author: Wenzhen Yu ++ * Author: Jianhui Zhao ++ */ ++ ++ ++#include ++#include ++#include ++#include ++#include ++#include "clk-mtk.h" ++#include "clk-gate.h" ++#include "clk-mux.h" ++ ++#include ++#include ++ ++static DEFINE_SPINLOCK(mt7981_clk_lock); ++ ++static const struct mtk_fixed_factor top_divs[] = { ++ FACTOR(CLK_TOP_CB_CKSQ_40M, "cb_cksq_40m", "clkxtal", 1, 1), ++ FACTOR(CLK_TOP_CB_M_416M, "cb_m_416m", "mpll", 1, 1), ++ FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", "mpll", 1, 2), ++ FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", "mpll", 1, 3), ++ FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", "mpll", 1, 2), ++ FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", "mpll", 1, 4), ++ FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", "mpll", 1, 8), ++ FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", "mpll", 1, 16), ++ FACTOR(CLK_TOP_CB_MM_720M, "cb_mm_720m", "mmpll", 1, 1), ++ FACTOR(CLK_TOP_CB_MM_D2, "cb_mm_d2", "mmpll", 1, 2), ++ FACTOR(CLK_TOP_CB_MM_D3, "cb_mm_d3", "mmpll", 1, 3), ++ FACTOR(CLK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", "mmpll", 1, 15), ++ FACTOR(CLK_TOP_CB_MM_D4, "cb_mm_d4", "mmpll", 1, 4), ++ FACTOR(CLK_TOP_CB_MM_D6, "cb_mm_d6", "mmpll", 1, 6), ++ FACTOR(CLK_TOP_MM_D6_D2, "mm_d6_d2", "mmpll", 1, 12), ++ FACTOR(CLK_TOP_CB_MM_D8, "cb_mm_d8", "mmpll", 1, 8), ++ FACTOR(CLK_TOP_CB_APLL2_196M, "cb_apll2_196m", "apll2", 1, 1), ++ FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2), ++ FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4), ++ FACTOR(CLK_TOP_NET1_2500M, "net1_2500m", "net1pll", 1, 1), ++ FACTOR(CLK_TOP_CB_NET1_D4, "cb_net1_d4", "net1pll", 1, 4), ++ FACTOR(CLK_TOP_CB_NET1_D5, "cb_net1_d5", "net1pll", 1, 5), ++ FACTOR(CLK_TOP_NET1_D5_D2, "net1_d5_d2", "net1pll", 1, 10), ++ FACTOR(CLK_TOP_NET1_D5_D4, "net1_d5_d4", "net1pll", 1, 20), ++ FACTOR(CLK_TOP_CB_NET1_D8, "cb_net1_d8", "net1pll", 1, 8), ++ FACTOR(CLK_TOP_NET1_D8_D2, "net1_d8_d2", "net1pll", 1, 16), ++ FACTOR(CLK_TOP_NET1_D8_D4, "net1_d8_d4", "net1pll", 1, 32), ++ FACTOR(CLK_TOP_CB_NET2_800M, "cb_net2_800m", "net2pll", 1, 1), ++ FACTOR(CLK_TOP_CB_NET2_D2, "cb_net2_d2", "net2pll", 1, 2), ++ FACTOR(CLK_TOP_CB_NET2_D4, "cb_net2_d4", "net2pll", 1, 4), ++ FACTOR(CLK_TOP_NET2_D4_D2, "net2_d4_d2", "net2pll", 1, 8), ++ FACTOR(CLK_TOP_NET2_D4_D4, "net2_d4_d4", "net2pll", 1, 16), ++ FACTOR(CLK_TOP_CB_NET2_D6, "cb_net2_d6", "net2pll", 1, 6), ++ FACTOR(CLK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", "wedmcupll", 1, 1), ++ FACTOR(CLK_TOP_CB_SGM_325M, "cb_sgm_325m", "sgmpll", 1, 1), ++ FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", "cb_cksq_40m", 1, 2), ++ FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", "cb_cksq_40m", 1, 1250), ++ FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", "cb_cksq_40m", 1, 1220), ++ FACTOR(CLK_TOP_USB_TX250M, "usb_tx250m", "cb_cksq_40m", 1, 1), ++ FACTOR(CLK_TOP_FAUD, "faud", "aud_sel", 1, 1), ++ FACTOR(CLK_TOP_NFI1X, "nfi1x", "nfi1x_sel", 1, 1), ++ FACTOR(CLK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", "cb_cksq_40m", 1, 1), ++ FACTOR(CLK_TOP_USB_CDR_CK, "usb_cdr", "cb_cksq_40m", 1, 1), ++ FACTOR(CLK_TOP_USB_LN0_CK, "usb_ln0", "cb_cksq_40m", 1, 1), ++ FACTOR(CLK_TOP_SPINFI_BCK, "spinfi_bck", "spinfi_sel", 1, 1), ++ FACTOR(CLK_TOP_SPI, "spi", "spi_sel", 1, 1), ++ FACTOR(CLK_TOP_SPIM_MST, "spim_mst", "spim_mst_sel", 1, 1), ++ FACTOR(CLK_TOP_UART_BCK, "uart_bck", "uart_sel", 1, 1), ++ FACTOR(CLK_TOP_PWM_BCK, "pwm_bck", "pwm_sel", 1, 1), ++ FACTOR(CLK_TOP_I2C_BCK, "i2c_bck", "i2c_sel", 1, 1), ++ FACTOR(CLK_TOP_PEXTP_TL, "pextp_tl", "pextp_tl_ck_sel", 1, 1), ++ FACTOR(CLK_TOP_EMMC_208M, "emmc_208m", "emmc_208m_sel", 1, 1), ++ FACTOR(CLK_TOP_EMMC_400M, "emmc_400m", "emmc_400m_sel", 1, 1), ++ FACTOR(CLK_TOP_DRAMC_REF, "dramc_ref", "dramc_sel", 1, 1), ++ FACTOR(CLK_TOP_DRAMC_MD32, "dramc_md32", "dramc_md32_sel", 1, 1), ++ FACTOR(CLK_TOP_SYSAXI, "sysaxi", "sysaxi_sel", 1, 1), ++ FACTOR(CLK_TOP_SYSAPB, "sysapb", "sysapb_sel", 1, 1), ++ FACTOR(CLK_TOP_ARM_DB_MAIN, "arm_db_main", "arm_db_main_sel", 1, 1), ++ FACTOR(CLK_TOP_AP2CNN_HOST, "ap2cnn_host", "ap2cnn_host_sel", 1, 1), ++ FACTOR(CLK_TOP_NETSYS, "netsys", "netsys_sel", 1, 1), ++ FACTOR(CLK_TOP_NETSYS_500M, "netsys_500m", "netsys_500m_sel", 1, 1), ++ FACTOR(CLK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", "netsys_mcu_sel", 1, 1), ++ FACTOR(CLK_TOP_NETSYS_2X, "netsys_2x", "netsys_2x_sel", 1, 1), ++ FACTOR(CLK_TOP_SGM_325M, "sgm_325m", "sgm_325m_sel", 1, 1), ++ FACTOR(CLK_TOP_SGM_REG, "sgm_reg", "sgm_reg_sel", 1, 1), ++ FACTOR(CLK_TOP_F26M, "csw_f26m", "csw_f26m_sel", 1, 1), ++ FACTOR(CLK_TOP_EIP97B, "eip97b", "eip97b_sel", 1, 1), ++ FACTOR(CLK_TOP_USB3_PHY, "usb3_phy", "usb3_phy_sel", 1, 1), ++ FACTOR(CLK_TOP_AUD, "aud", "faud", 1, 1), ++ FACTOR(CLK_TOP_A1SYS, "a1sys", "a1sys_sel", 1, 1), ++ FACTOR(CLK_TOP_AUD_L, "aud_l", "aud_l_sel", 1, 1), ++ FACTOR(CLK_TOP_A_TUNER, "a_tuner", "a_tuner_sel", 1, 1), ++ FACTOR(CLK_TOP_U2U3_REF, "u2u3_ref", "u2u3_sel", 1, 1), ++ FACTOR(CLK_TOP_U2U3_SYS, "u2u3_sys", "u2u3_sys_sel", 1, 1), ++ FACTOR(CLK_TOP_U2U3_XHCI, "u2u3_xhci", "u2u3_xhci_sel", 1, 1), ++ FACTOR(CLK_TOP_USB_FRMCNT, "usb_frmcnt", "usb_frmcnt_sel", 1, 1), ++}; ++ ++static const char * const nfi1x_parents[] __initconst = { ++ "cb_cksq_40m", ++ "cb_mm_d4", ++ "net1_d8_d2", ++ "cb_net2_d6", ++ "cb_m_d4", ++ "cb_mm_d8", ++ "net1_d8_d4", ++ "cb_m_d8" ++}; ++ ++static const char * const spinfi_parents[] __initconst = { ++ "cksq_40m_d2", ++ "cb_cksq_40m", ++ "net1_d5_d4", ++ "cb_m_d4", ++ "cb_mm_d8", ++ "net1_d8_d4", ++ "mm_d6_d2", ++ "cb_m_d8" ++}; ++ ++static const char * const spi_parents[] __initconst = { ++ "cb_cksq_40m", ++ "cb_m_d2", ++ "cb_mm_d4", ++ "net1_d8_d2", ++ "cb_net2_d6", ++ "net1_d5_d4", ++ "cb_m_d4", ++ "net1_d8_d4" ++}; ++ ++static const char * const uart_parents[] __initconst = { ++ "cb_cksq_40m", ++ "cb_m_d8", ++ "m_d8_d2" ++}; ++ ++static const char * const pwm_parents[] __initconst = { ++ "cb_cksq_40m", ++ "net1_d8_d2", ++ "net1_d5_d4", ++ "cb_m_d4", ++ "m_d8_d2", ++ "cb_rtc_32k" ++}; ++ ++static const char * const i2c_parents[] __initconst = { ++ "cb_cksq_40m", ++ "net1_d5_d4", ++ "cb_m_d4", ++ "net1_d8_d4" ++}; ++ ++static const char * const pextp_tl_ck_parents[] __initconst = { ++ "cb_cksq_40m", ++ "net1_d5_d4", ++ "cb_m_d4", ++ "cb_rtc_32k" ++}; ++ ++static const char * const emmc_208m_parents[] __initconst = { ++ "cb_cksq_40m", ++ "cb_m_d2", ++ "cb_net2_d4", ++ "cb_apll2_196m", ++ "cb_mm_d4", ++ "net1_d8_d2", ++ "cb_mm_d6" ++}; ++ ++static const char * const emmc_400m_parents[] __initconst = { ++ "cb_cksq_40m", ++ "cb_net2_d2", ++ "cb_mm_d2", ++ "cb_net2_d2" ++}; ++ ++static const char * const csw_f26m_parents[] __initconst = { ++ "cksq_40m_d2", ++ "m_d8_d2" ++}; ++ ++static const char * const dramc_md32_parents[] __initconst = { ++ "cb_cksq_40m", ++ "cb_m_d2", ++ "cb_wedmcu_208m" ++}; ++ ++static const char * const sysaxi_parents[] __initconst = { ++ "cb_cksq_40m", ++ "net1_d8_d2" ++}; ++ ++static const char * const sysapb_parents[] __initconst = { ++ "cb_cksq_40m", ++ "m_d3_d2" ++}; ++ ++static const char * const arm_db_main_parents[] __initconst = { ++ "cb_cksq_40m", ++ "cb_net2_d6" ++}; ++ ++static const char * const ap2cnn_host_parents[] __initconst = { ++ "cb_cksq_40m", ++ "net1_d8_d4" ++}; ++ ++static const char * const netsys_parents[] __initconst = { ++ "cb_cksq_40m", ++ "cb_mm_d2" ++}; ++ ++static const char * const netsys_500m_parents[] __initconst = { ++ "cb_cksq_40m", ++ "cb_net1_d5" ++}; ++ ++static const char * const netsys_mcu_parents[] __initconst = { ++ "cb_cksq_40m", ++ "cb_mm_720m", ++ "cb_net1_d4", ++ "cb_net1_d5", ++ "cb_m_416m" ++}; ++ ++static const char * const netsys_2x_parents[] __initconst = { ++ "cb_cksq_40m", ++ "cb_net2_800m", ++ "cb_mm_720m" ++}; ++ ++static const char * const sgm_325m_parents[] __initconst = { ++ "cb_cksq_40m", ++ "cb_sgm_325m" ++}; ++ ++static const char * const sgm_reg_parents[] __initconst = { ++ "cb_cksq_40m", ++ "cb_net2_d4" ++}; ++ ++static const char * const eip97b_parents[] __initconst = { ++ "cb_cksq_40m", ++ "cb_net1_d5", ++ "cb_m_416m", ++ "cb_mm_d2", ++ "net1_d5_d2" ++}; ++ ++static const char * const aud_parents[] __initconst = { ++ "cb_cksq_40m", ++ "cb_apll2_196m" ++}; ++ ++static const char * const a1sys_parents[] __initconst = { ++ "cb_cksq_40m", ++ "apll2_d4" ++}; ++ ++static const char * const aud_l_parents[] __initconst = { ++ "cb_cksq_40m", ++ "cb_apll2_196m", ++ "m_d8_d2" ++}; ++ ++static const char * const a_tuner_parents[] __initconst = { ++ "cb_cksq_40m", ++ "apll2_d4", ++ "m_d8_d2" ++}; ++ ++static const char * const u2u3_parents[] __initconst = { ++ "cb_cksq_40m", ++ "m_d8_d2" ++}; ++ ++static const char * const u2u3_sys_parents[] __initconst = { ++ "cb_cksq_40m", ++ "net1_d5_d4" ++}; ++ ++static const char * const usb_frmcnt_parents[] __initconst = { ++ "cb_cksq_40m", ++ "cb_mm_d3_d5" ++}; ++ ++static const struct mtk_mux top_muxes[] = { ++ /* CLK_CFG_0 */ ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, ++ 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, ++ 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, ++ 0x000, 0x004, 0x008, 16, 3, 23, 0x1C0, 2), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, ++ 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3), ++ /* CLK_CFG_1 */ ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, ++ 0x010, 0x014, 0x018, 0, 2, 7, 0x1C0, 4), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, ++ 0x010, 0x014, 0x018, 8, 3, 15, 0x1C0, 5), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, ++ 0x010, 0x014, 0x018, 16, 2, 23, 0x1C0, 6), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", ++ pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 31, ++ 0x1C0, 7), ++ /* CLK_CFG_2 */ ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel", ++ emmc_208m_parents, 0x020, 0x024, 0x028, 0, 3, 7, ++ 0x1C0, 8), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", ++ emmc_400m_parents, 0x020, 0x024, 0x028, 8, 2, 15, ++ 0x1C0, 9), ++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel", ++ csw_f26m_parents, 0x020, 0x024, 0x028, 16, 1, 23, ++ 0x1C0, 10, ++ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), ++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", ++ csw_f26m_parents, 0x020, 0x024, 0x028, 24, 1, ++ 31, 0x1C0, 11, ++ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), ++ /* CLK_CFG_3 */ ++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", ++ dramc_md32_parents, 0x030, 0x034, 0x038, 0, 2, ++ 7, 0x1C0, 12, ++ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), ++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", ++ sysaxi_parents, 0x030, 0x034, 0x038, 8, 1, 15, ++ 0x1C0, 13, ++ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), ++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", ++ sysapb_parents, 0x030, 0x034, 0x038, 16, 1, ++ 23, 0x1C0, 14, ++ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", ++ arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, 31, ++ 0x1C0, 15), ++ /* CLK_CFG_4 */ ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", ++ ap2cnn_host_parents, 0x040, 0x044, 0x048, 0, 1, 7, ++ 0x1C0, 16), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, ++ 0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", ++ netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1, 23, ++ 0x1C0, 18), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", ++ netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31, ++ 0x1C0, 19), ++ /* CLK_CFG_5 */ ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", ++ netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7, ++ 0x1C0, 20), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", ++ sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15, ++ 0x1C0, 21), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, ++ 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents, ++ 0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23), ++ /* CLK_CFG_6 */ ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel", ++ csw_f26m_parents, 0x060, 0x064, 0x068, 0, 1, ++ 7, 0x1C0, 24), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x060, ++ 0x064, 0x068, 8, 1, 15, 0x1C0, 25), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, ++ 0x060, 0x064, 0x068, 16, 1, 23, 0x1C0, 26), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, ++ 0x060, 0x064, 0x068, 24, 2, 31, 0x1C0, 27), ++ /* CLK_CFG_7 */ ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", ++ a_tuner_parents, 0x070, 0x074, 0x078, 0, 2, 7, ++ 0x1C0, 28), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x070, ++ 0x074, 0x078, 8, 1, 15, 0x1C0, 29), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", ++ u2u3_sys_parents, 0x070, 0x074, 0x078, 16, 1, 23, ++ 0x1C0, 30), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", ++ u2u3_sys_parents, 0x070, 0x074, 0x078, 24, 1, 31, ++ 0x1C4, 0), ++ /* CLK_CFG_8 */ ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", ++ usb_frmcnt_parents, 0x080, 0x084, 0x088, 0, 1, 7, ++ 0x1C4, 1), ++}; ++ ++static struct mtk_composite top_aud_divs[] = { ++ DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud", ++ 0x0420, 0, 0x0420, 8, 8), ++}; ++ ++static const struct mtk_clk_desc topck_desc = { ++ .factor_clks = top_divs, ++ .num_factor_clks = ARRAY_SIZE(top_divs), ++ .mux_clks = top_muxes, ++ .num_mux_clks = ARRAY_SIZE(top_muxes), ++ .composite_clks = top_aud_divs, ++ .num_composite_clks = ARRAY_SIZE(top_aud_divs), ++ .clk_lock = &mt7981_clk_lock, ++}; ++ ++static const struct of_device_id of_match_clk_mt7981_topckgen[] = { ++ { .compatible = "mediatek,mt7981-topckgen", .data = &topck_desc }, ++ { /* sentinel */ } ++}; ++ ++static struct platform_driver clk_mt7981_topckgen_drv = { ++ .probe = mtk_clk_simple_probe, ++ .remove = mtk_clk_simple_remove, ++ .driver = { ++ .name = "clk-mt7981-topckgen", ++ .of_match_table = of_match_clk_mt7981_topckgen, ++ }, ++}; ++builtin_platform_driver(clk_mt7981_topckgen_drv); diff --git a/target/linux/mediatek/patches-6.1/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch b/target/linux/mediatek/patches-6.1/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch index cbee45bc1f8..a365f0860bb 100644 --- a/target/linux/mediatek/patches-6.1/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch +++ b/target/linux/mediatek/patches-6.1/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch @@ -1,6 +1,6 @@ --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig -@@ -134,6 +134,13 @@ config PINCTRL_MT7986 +@@ -141,6 +141,13 @@ config PINCTRL_MT7986 default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_MOORE @@ -16,9 +16,9 @@ depends on OF --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile -@@ -19,6 +19,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl- +@@ -20,6 +20,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl- obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o - obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7981.o + obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o +obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o diff --git a/target/linux/mediatek/patches-6.1/241-clk-mediatek-Add-pcw-chg-shift-control.patch b/target/linux/mediatek/patches-6.1/241-clk-mediatek-Add-pcw-chg-shift-control.patch index 23a5b7c911a..75ca114a589 100644 --- a/target/linux/mediatek/patches-6.1/241-clk-mediatek-Add-pcw-chg-shift-control.patch +++ b/target/linux/mediatek/patches-6.1/241-clk-mediatek-Add-pcw-chg-shift-control.patch @@ -1,16 +1,6 @@ ---- a/drivers/clk/mediatek/clk-mtk.h -+++ b/drivers/clk/mediatek/clk-mtk.h -@@ -233,6 +233,7 @@ struct mtk_pll_data { - u32 pcw_reg; - int pcw_shift; - u32 pcw_chg_reg; -+ int pcw_chg_shift; - const struct mtk_pll_div_table *div_table; - const char *parent_name; - u32 en_reg; --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c -@@ -137,7 +137,10 @@ static void mtk_pll_set_rate_regs(struct +@@ -141,7 +141,10 @@ static void mtk_pll_set_rate_regs(struct pll->data->pcw_shift); val |= pcw << pll->data->pcw_shift; writel(val, pll->pcw_addr); @@ -22,3 +12,13 @@ writel(chg, pll->pcw_chg_addr); if (pll->tuner_addr) writel(val + 1, pll->tuner_addr); +--- a/drivers/clk/mediatek/clk-pll.h ++++ b/drivers/clk/mediatek/clk-pll.h +@@ -42,6 +42,7 @@ struct mtk_pll_data { + u32 pcw_reg; + int pcw_shift; + u32 pcw_chg_reg; ++ int pcw_chg_shift; + const struct mtk_pll_div_table *div_table; + const char *parent_name; + u32 en_reg; diff --git a/target/linux/mediatek/patches-6.1/242-clk-mediatek-add-mt7988-clock-support.patch b/target/linux/mediatek/patches-6.1/242-clk-mediatek-add-mt7988-clock-support.patch index bf9146352a6..3ced012495b 100644 --- a/target/linux/mediatek/patches-6.1/242-clk-mediatek-add-mt7988-clock-support.patch +++ b/target/linux/mediatek/patches-6.1/242-clk-mediatek-add-mt7988-clock-support.patch @@ -1,7 +1,7 @@ --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig -@@ -378,6 +378,15 @@ config COMMON_CLK_MT7986_ETHSYS - This driver add support for clocks for Ethernet and SGMII +@@ -415,6 +415,15 @@ config COMMON_CLK_MT7986_ETHSYS + This driver adds support for clocks for Ethernet and SGMII required on MediaTek MT7986 SoC. +config COMMON_CLK_MT7988 @@ -18,7 +18,7 @@ depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile -@@ -54,6 +54,10 @@ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-m +@@ -60,6 +60,10 @@ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-m obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o diff --git a/target/linux/mediatek/patches-6.1/320-mmc-mediatek-add-support-for-MT7986-SoC.patch b/target/linux/mediatek/patches-6.1/320-v6.2-mmc-mediatek-add-support-for-MT7986-SoC.patch similarity index 50% rename from target/linux/mediatek/patches-6.1/320-mmc-mediatek-add-support-for-MT7986-SoC.patch rename to target/linux/mediatek/patches-6.1/320-v6.2-mmc-mediatek-add-support-for-MT7986-SoC.patch index 56ffa73c00c..5e3afd856f7 100644 --- a/target/linux/mediatek/patches-6.1/320-mmc-mediatek-add-support-for-MT7986-SoC.patch +++ b/target/linux/mediatek/patches-6.1/320-v6.2-mmc-mediatek-add-support-for-MT7986-SoC.patch @@ -1,20 +1,23 @@ -From 1a7963e9843f6f1e4b02a30926d20b314c03e4df Mon Sep 17 00:00:00 2001 +From 24e961b93d292d0dd6380213d22a071a99ea787d Mon Sep 17 00:00:00 2001 From: Sam Shih -Date: Sat, 25 Jun 2022 02:10:13 +0800 -Subject: [PATCH] mmc: mediatek: add support for MT7986 SoC +Date: Tue, 25 Oct 2022 15:29:53 +0200 +Subject: [PATCH 1/6] mmc: mediatek: add support for MT7986 SoC Adding mt7986 own characteristics and of_device_id to have support of MT7986 SoC. Signed-off-by: Sam Shih -Change-Id: I07cf8406cbe8c1a7114b304f35fc3e689e512e5a +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20221025132953.81286-7-linux@fw-web.de +Signed-off-by: Ulf Hansson --- drivers/mmc/host/mtk-sd.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c -@@ -540,6 +540,19 @@ static const struct mtk_mmc_compatible m +@@ -552,6 +552,19 @@ static const struct mtk_mmc_compatible m .support_64g = false, }; @@ -31,14 +34,14 @@ Change-Id: I07cf8406cbe8c1a7114b304f35fc3e689e512e5a + .support_64g = true, +}; + - static const struct mtk_mmc_compatible mt8516_compat = { - .clk_div_bits = 12, + static const struct mtk_mmc_compatible mt8135_compat = { + .clk_div_bits = 8, .recheck_sdio_irq = true, -@@ -584,6 +597,7 @@ static const struct of_device_id msdc_of - { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, - { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, +@@ -609,6 +622,7 @@ static const struct of_device_id msdc_of + { .compatible = "mediatek,mt6795-mmc", .data = &mt6795_compat}, + { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, + { .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat}, - { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, - { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, - { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat}, + { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, + { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, + { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, diff --git a/target/linux/mediatek/patches-6.1/321-v6.2-mmc-mtk-sd-add-Inline-Crypto-Engine-clock-control.patch b/target/linux/mediatek/patches-6.1/321-v6.2-mmc-mtk-sd-add-Inline-Crypto-Engine-clock-control.patch new file mode 100644 index 00000000000..db2802bd0f4 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/321-v6.2-mmc-mtk-sd-add-Inline-Crypto-Engine-clock-control.patch @@ -0,0 +1,57 @@ +From 7b438d0377fbd520b475a68bdd9de1692393f22d Mon Sep 17 00:00:00 2001 +From: Mengqi Zhang +Date: Sun, 6 Nov 2022 11:39:24 +0800 +Subject: [PATCH 2/6] mmc: mtk-sd: add Inline Crypto Engine clock control + +Add crypto clock control and ungate it before CQHCI init. + +Signed-off-by: Mengqi Zhang +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20221106033924.9854-2-mengqi.zhang@mediatek.com +Signed-off-by: Ulf Hansson +--- + drivers/mmc/host/mtk-sd.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/drivers/mmc/host/mtk-sd.c ++++ b/drivers/mmc/host/mtk-sd.c +@@ -452,6 +452,7 @@ struct msdc_host { + struct clk *bus_clk; /* bus clock which used to access register */ + struct clk *src_clk_cg; /* msdc source clock control gate */ + struct clk *sys_clk_cg; /* msdc subsys clock control gate */ ++ struct clk *crypto_clk; /* msdc crypto clock control gate */ + struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS]; + u32 mclk; /* mmc subsystem clock frequency */ + u32 src_clk_freq; /* source clock frequency */ +@@ -840,6 +841,7 @@ static void msdc_set_busy_timeout(struct + static void msdc_gate_clock(struct msdc_host *host) + { + clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks); ++ clk_disable_unprepare(host->crypto_clk); + clk_disable_unprepare(host->src_clk_cg); + clk_disable_unprepare(host->src_clk); + clk_disable_unprepare(host->bus_clk); +@@ -855,6 +857,7 @@ static int msdc_ungate_clock(struct msdc + clk_prepare_enable(host->bus_clk); + clk_prepare_enable(host->src_clk); + clk_prepare_enable(host->src_clk_cg); ++ clk_prepare_enable(host->crypto_clk); + ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks); + if (ret) { + dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n"); +@@ -2670,6 +2673,15 @@ static int msdc_drv_probe(struct platfor + goto host_free; + } + ++ /* only eMMC has crypto property */ ++ if (!(mmc->caps2 & MMC_CAP2_NO_MMC)) { ++ host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto"); ++ if (IS_ERR(host->crypto_clk)) ++ host->crypto_clk = NULL; ++ else ++ mmc->caps2 |= MMC_CAP2_CRYPTO; ++ } ++ + host->irq = platform_get_irq(pdev, 0); + if (host->irq < 0) { + ret = host->irq; diff --git a/target/linux/mediatek/patches-6.1/322-v6.2-mmc-mtk-sd-fix-two-spelling-mistakes-in-comment.patch b/target/linux/mediatek/patches-6.1/322-v6.2-mmc-mtk-sd-fix-two-spelling-mistakes-in-comment.patch new file mode 100644 index 00000000000..921d249f8cc --- /dev/null +++ b/target/linux/mediatek/patches-6.1/322-v6.2-mmc-mtk-sd-fix-two-spelling-mistakes-in-comment.patch @@ -0,0 +1,36 @@ +From 4b323f02b6e8df1b04292635ef829e7f723bf50e Mon Sep 17 00:00:00 2001 +From: Yu Zhe +Date: Thu, 10 Nov 2022 15:28:19 +0800 +Subject: [PATCH 3/6] mmc: mtk-sd: fix two spelling mistakes in comment + +spelling mistake fix : "alreay" -> "already" + "checksume" -> "checksum" + +Signed-off-by: Yu Zhe +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20221110072819.11530-1-yuzhe@nfschina.com +Signed-off-by: Ulf Hansson +--- + drivers/mmc/host/mtk-sd.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/mmc/host/mtk-sd.c ++++ b/drivers/mmc/host/mtk-sd.c +@@ -750,7 +750,7 @@ static inline void msdc_dma_setup(struct + else + bd[j].bd_info &= ~BDMA_DESC_EOL; + +- /* checksume need to clear first */ ++ /* checksum need to clear first */ + bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; + bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; + } +@@ -1229,7 +1229,7 @@ static bool msdc_cmd_done(struct msdc_ho + !host->hs400_tuning)) + /* + * should not clear fifo/interrupt as the tune data +- * may have alreay come when cmd19/cmd21 gets response ++ * may have already come when cmd19/cmd21 gets response + * CRC error. + */ + msdc_reset_hw(host); diff --git a/target/linux/mediatek/patches-6.1/323-v6.2-mmc-Avoid-open-coding-by-using-mmc_op_tuning.patch b/target/linux/mediatek/patches-6.1/323-v6.2-mmc-Avoid-open-coding-by-using-mmc_op_tuning.patch new file mode 100644 index 00000000000..8e2151e16bd --- /dev/null +++ b/target/linux/mediatek/patches-6.1/323-v6.2-mmc-Avoid-open-coding-by-using-mmc_op_tuning.patch @@ -0,0 +1,39 @@ +From b98e7e8daf0ebab9dcc36812378a71e1be0b5089 Mon Sep 17 00:00:00 2001 +From: ChanWoo Lee +Date: Thu, 24 Nov 2022 17:00:31 +0900 +Subject: [PATCH 4/6] mmc: Avoid open coding by using mmc_op_tuning() + +Replace code with the already defined function. No functional changes. + +Signed-off-by: ChanWoo Lee +Reviewed-by: Adrian Hunter +Link: https://lore.kernel.org/r/20221124080031.14690-1-cw9316.lee@samsung.com +Signed-off-by: Ulf Hansson +--- + drivers/mmc/host/mtk-sd.c | 8 ++------ + 1 file changed, 2 insertions(+), 6 deletions(-) + +--- a/drivers/mmc/host/mtk-sd.c ++++ b/drivers/mmc/host/mtk-sd.c +@@ -1224,9 +1224,7 @@ static bool msdc_cmd_done(struct msdc_ho + + if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { + if (events & MSDC_INT_CMDTMO || +- (cmd->opcode != MMC_SEND_TUNING_BLOCK && +- cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200 && +- !host->hs400_tuning)) ++ (!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning)) + /* + * should not clear fifo/interrupt as the tune data + * may have already come when cmd19/cmd21 gets response +@@ -1320,9 +1318,7 @@ static void msdc_cmd_next(struct msdc_ho + { + if ((cmd->error && + !(cmd->error == -EILSEQ && +- (cmd->opcode == MMC_SEND_TUNING_BLOCK || +- cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200 || +- host->hs400_tuning))) || ++ (mmc_op_tuning(cmd->opcode) || host->hs400_tuning))) || + (mrq->sbc && mrq->sbc->error)) + msdc_request_done(host, mrq); + else if (cmd == mrq->sbc) diff --git a/target/linux/mediatek/patches-6.1/330-snand-mtk-bmt-support.patch b/target/linux/mediatek/patches-6.1/330-snand-mtk-bmt-support.patch index 6814e5f5e98..55a308e46cf 100644 --- a/target/linux/mediatek/patches-6.1/330-snand-mtk-bmt-support.patch +++ b/target/linux/mediatek/patches-6.1/330-snand-mtk-bmt-support.patch @@ -8,7 +8,7 @@ static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val) { -@@ -1343,6 +1344,7 @@ static int spinand_probe(struct spi_mem +@@ -1344,6 +1345,7 @@ static int spinand_probe(struct spi_mem if (ret) return ret; @@ -16,7 +16,7 @@ ret = mtd_device_register(mtd, NULL, 0); if (ret) goto err_spinand_cleanup; -@@ -1350,6 +1352,7 @@ static int spinand_probe(struct spi_mem +@@ -1351,6 +1353,7 @@ static int spinand_probe(struct spi_mem return 0; err_spinand_cleanup: @@ -24,7 +24,7 @@ spinand_cleanup(spinand); return ret; -@@ -1368,6 +1371,7 @@ static int spinand_remove(struct spi_mem +@@ -1369,6 +1372,7 @@ static int spinand_remove(struct spi_mem if (ret) return ret; diff --git a/target/linux/mediatek/patches-6.1/331-mt7622-rfb1-enable-bmt.patch b/target/linux/mediatek/patches-6.1/331-mt7622-rfb1-enable-bmt.patch index 9c1a8f284ab..662515f2c52 100644 --- a/target/linux/mediatek/patches-6.1/331-mt7622-rfb1-enable-bmt.patch +++ b/target/linux/mediatek/patches-6.1/331-mt7622-rfb1-enable-bmt.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -553,6 +553,7 @@ +@@ -552,6 +552,7 @@ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; nand-ecc-engine = <&snfi>; diff --git a/target/linux/mediatek/patches-6.1/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch b/target/linux/mediatek/patches-6.1/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch index 6baa32879bf..ec66363dc9d 100644 --- a/target/linux/mediatek/patches-6.1/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch +++ b/target/linux/mediatek/patches-6.1/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch @@ -18,18 +18,18 @@ Signed-off-by: Davide Fioravanti +++ b/drivers/mtd/nand/spi/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 --spinand-objs := core.o esmt.o etron.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o -+spinand-objs := core.o esmt.o etron.o fidelix.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o +-spinand-objs := core.o ato.o esmt.o etron.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o ++spinand-objs := core.o ato.o esmt.o etron.o fidelix.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o obj-$(CONFIG_MTD_SPI_NAND) += spinand.o --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c -@@ -939,6 +939,7 @@ static const struct nand_ops spinand_ops - +@@ -940,6 +940,7 @@ static const struct nand_ops spinand_ops static const struct spinand_manufacturer *spinand_manufacturers[] = { + &ato_spinand_manufacturer, &esmt_c8_spinand_manufacturer, + &fidelix_spinand_manufacturer, - &gigadevice_spinand_manufacturer, &etron_spinand_manufacturer, + &gigadevice_spinand_manufacturer, ¯onix_spinand_manufacturer, --- /dev/null +++ b/drivers/mtd/nand/spi/fidelix.c @@ -112,8 +112,8 @@ Signed-off-by: Davide Fioravanti +}; --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h -@@ -262,6 +262,7 @@ struct spinand_manufacturer { - /* SPI NAND manufacturers */ +@@ -263,6 +263,7 @@ struct spinand_manufacturer { + extern const struct spinand_manufacturer ato_spinand_manufacturer; extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer; extern const struct spinand_manufacturer etron_spinand_manufacturer; +extern const struct spinand_manufacturer fidelix_spinand_manufacturer; diff --git a/target/linux/mediatek/patches-6.1/350-01-cpufreq-mediatek-Cleanup-variables-and-error-handlin.patch b/target/linux/mediatek/patches-6.1/350-01-cpufreq-mediatek-Cleanup-variables-and-error-handlin.patch deleted file mode 100644 index 8fad64a5702..00000000000 --- a/target/linux/mediatek/patches-6.1/350-01-cpufreq-mediatek-Cleanup-variables-and-error-handlin.patch +++ /dev/null @@ -1,166 +0,0 @@ -From 7a768326fdba542144833b9198a6d0edab52fad2 Mon Sep 17 00:00:00 2001 -From: Jia-Wei Chang -Date: Fri, 8 Apr 2022 12:58:56 +0800 -Subject: [PATCH 01/21] cpufreq: mediatek: Cleanup variables and error handling - in mtk_cpu_dvfs_info_init() - -- Remove several unnecessary varaibles in mtk_cpu_dvfs_info_init(). -- Unify error message format and use dev_err_probe() if possible. - -Signed-off-by: Jia-Wei Chang -Signed-off-by: Rex-BC Chen -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 89 ++++++++++++------------------ - 1 file changed, 34 insertions(+), 55 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -302,96 +302,75 @@ static int mtk_cpufreq_set_target(struct - static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) - { - struct device *cpu_dev; -- struct regulator *proc_reg = ERR_PTR(-ENODEV); -- struct regulator *sram_reg = ERR_PTR(-ENODEV); -- struct clk *cpu_clk = ERR_PTR(-ENODEV); -- struct clk *inter_clk = ERR_PTR(-ENODEV); - struct dev_pm_opp *opp; - unsigned long rate; - int ret; - - cpu_dev = get_cpu_device(cpu); - if (!cpu_dev) { -- pr_err("failed to get cpu%d device\n", cpu); -+ dev_err(cpu_dev, "failed to get cpu%d device\n", cpu); - return -ENODEV; - } -+ info->cpu_dev = cpu_dev; - -- cpu_clk = clk_get(cpu_dev, "cpu"); -- if (IS_ERR(cpu_clk)) { -- if (PTR_ERR(cpu_clk) == -EPROBE_DEFER) -- pr_warn("cpu clk for cpu%d not ready, retry.\n", cpu); -- else -- pr_err("failed to get cpu clk for cpu%d\n", cpu); -- -- ret = PTR_ERR(cpu_clk); -- return ret; -- } -- -- inter_clk = clk_get(cpu_dev, "intermediate"); -- if (IS_ERR(inter_clk)) { -- if (PTR_ERR(inter_clk) == -EPROBE_DEFER) -- pr_warn("intermediate clk for cpu%d not ready, retry.\n", -- cpu); -- else -- pr_err("failed to get intermediate clk for cpu%d\n", -- cpu); -+ info->cpu_clk = clk_get(cpu_dev, "cpu"); -+ if (IS_ERR(info->cpu_clk)) { -+ ret = PTR_ERR(info->cpu_clk); -+ return dev_err_probe(cpu_dev, ret, -+ "cpu%d: failed to get cpu clk\n", cpu); -+ } - -- ret = PTR_ERR(inter_clk); -+ info->inter_clk = clk_get(cpu_dev, "intermediate"); -+ if (IS_ERR(info->inter_clk)) { -+ ret = PTR_ERR(info->inter_clk); -+ dev_err_probe(cpu_dev, ret, -+ "cpu%d: failed to get intermediate clk\n", cpu); - goto out_free_resources; - } - -- proc_reg = regulator_get_optional(cpu_dev, "proc"); -- if (IS_ERR(proc_reg)) { -- if (PTR_ERR(proc_reg) == -EPROBE_DEFER) -- pr_warn("proc regulator for cpu%d not ready, retry.\n", -- cpu); -- else -- pr_err("failed to get proc regulator for cpu%d\n", -- cpu); -- -- ret = PTR_ERR(proc_reg); -+ info->proc_reg = regulator_get_optional(cpu_dev, "proc"); -+ if (IS_ERR(info->proc_reg)) { -+ ret = PTR_ERR(info->proc_reg); -+ dev_err_probe(cpu_dev, ret, -+ "cpu%d: failed to get proc regulator\n", cpu); - goto out_free_resources; - } - - /* Both presence and absence of sram regulator are valid cases. */ -- sram_reg = regulator_get_exclusive(cpu_dev, "sram"); -+ info->sram_reg = regulator_get_exclusive(cpu_dev, "sram"); -+ if (IS_ERR(info->sram_reg)) -+ info->sram_reg = NULL; - - /* Get OPP-sharing information from "operating-points-v2" bindings */ - ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, &info->cpus); - if (ret) { -- pr_err("failed to get OPP-sharing information for cpu%d\n", -- cpu); -+ dev_err(cpu_dev, -+ "cpu%d: failed to get OPP-sharing information\n", cpu); - goto out_free_resources; - } - - ret = dev_pm_opp_of_cpumask_add_table(&info->cpus); - if (ret) { -- pr_warn("no OPP table for cpu%d\n", cpu); -+ dev_warn(cpu_dev, "cpu%d: no OPP table\n", cpu); - goto out_free_resources; - } - - /* Search a safe voltage for intermediate frequency. */ -- rate = clk_get_rate(inter_clk); -+ rate = clk_get_rate(info->inter_clk); - opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate); - if (IS_ERR(opp)) { -- pr_err("failed to get intermediate opp for cpu%d\n", cpu); -+ dev_err(cpu_dev, "cpu%d: failed to get intermediate opp\n", cpu); - ret = PTR_ERR(opp); - goto out_free_opp_table; - } - info->intermediate_voltage = dev_pm_opp_get_voltage(opp); - dev_pm_opp_put(opp); - -- info->cpu_dev = cpu_dev; -- info->proc_reg = proc_reg; -- info->sram_reg = IS_ERR(sram_reg) ? NULL : sram_reg; -- info->cpu_clk = cpu_clk; -- info->inter_clk = inter_clk; -- - /* - * If SRAM regulator is present, software "voltage tracking" is needed - * for this CPU power domain. - */ -- info->need_voltage_tracking = !IS_ERR(sram_reg); -+ info->need_voltage_tracking = (info->sram_reg != NULL); - - return 0; - -@@ -399,14 +378,14 @@ out_free_opp_table: - dev_pm_opp_of_cpumask_remove_table(&info->cpus); - - out_free_resources: -- if (!IS_ERR(proc_reg)) -- regulator_put(proc_reg); -- if (!IS_ERR(sram_reg)) -- regulator_put(sram_reg); -- if (!IS_ERR(cpu_clk)) -- clk_put(cpu_clk); -- if (!IS_ERR(inter_clk)) -- clk_put(inter_clk); -+ if (!IS_ERR(info->proc_reg)) -+ regulator_put(info->proc_reg); -+ if (!IS_ERR(info->sram_reg)) -+ regulator_put(info->sram_reg); -+ if (!IS_ERR(info->cpu_clk)) -+ clk_put(info->cpu_clk); -+ if (!IS_ERR(info->inter_clk)) -+ clk_put(info->inter_clk); - - return ret; - } diff --git a/target/linux/mediatek/patches-6.1/350-02-cpufreq-mediatek-Remove-unused-headers.patch b/target/linux/mediatek/patches-6.1/350-02-cpufreq-mediatek-Remove-unused-headers.patch deleted file mode 100644 index eebeeb09028..00000000000 --- a/target/linux/mediatek/patches-6.1/350-02-cpufreq-mediatek-Remove-unused-headers.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 756104b856d4bc3121420af3ced342f5fc2b2123 Mon Sep 17 00:00:00 2001 -From: Jia-Wei Chang -Date: Fri, 8 Apr 2022 12:58:57 +0800 -Subject: [PATCH 02/21] cpufreq: mediatek: Remove unused headers - -Remove unused headers. - -Signed-off-by: Jia-Wei Chang -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 2 -- - 1 file changed, 2 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -13,8 +13,6 @@ - #include - #include - #include --#include --#include - - #define MIN_VOLT_SHIFT (100000) - #define MAX_VOLT_SHIFT (200000) diff --git a/target/linux/mediatek/patches-6.1/350-03-cpufreq-mediatek-Enable-clocks-and-regulators.patch b/target/linux/mediatek/patches-6.1/350-03-cpufreq-mediatek-Enable-clocks-and-regulators.patch deleted file mode 100644 index c97d5fc3d91..00000000000 --- a/target/linux/mediatek/patches-6.1/350-03-cpufreq-mediatek-Enable-clocks-and-regulators.patch +++ /dev/null @@ -1,117 +0,0 @@ -From 342d5545e9f40496db9ae0d31c2427dd5f369a43 Mon Sep 17 00:00:00 2001 -From: Jia-Wei Chang -Date: Fri, 8 Apr 2022 12:58:58 +0800 -Subject: [PATCH 03/21] cpufreq: mediatek: Enable clocks and regulators - -We need to enable regulators so that the max and min requested values will -be recorded. -The intermediate clock is not always enabled by CCF in different projects, -so we should enable it in the cpufreq driver. - -Signed-off-by: Andrew-sh.Cheng -Signed-off-by: Jia-Wei Chang -Signed-off-by: Rex-BC Chen -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 50 +++++++++++++++++++++++++++--- - 1 file changed, 45 insertions(+), 5 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -334,10 +334,23 @@ static int mtk_cpu_dvfs_info_init(struct - goto out_free_resources; - } - -+ ret = regulator_enable(info->proc_reg); -+ if (ret) { -+ dev_warn(cpu_dev, "cpu%d: failed to enable vproc\n", cpu); -+ goto out_free_resources; -+ } -+ - /* Both presence and absence of sram regulator are valid cases. */ - info->sram_reg = regulator_get_exclusive(cpu_dev, "sram"); - if (IS_ERR(info->sram_reg)) - info->sram_reg = NULL; -+ else { -+ ret = regulator_enable(info->sram_reg); -+ if (ret) { -+ dev_warn(cpu_dev, "cpu%d: failed to enable vsram\n", cpu); -+ goto out_free_resources; -+ } -+ } - - /* Get OPP-sharing information from "operating-points-v2" bindings */ - ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, &info->cpus); -@@ -353,13 +366,21 @@ static int mtk_cpu_dvfs_info_init(struct - goto out_free_resources; - } - -+ ret = clk_prepare_enable(info->cpu_clk); -+ if (ret) -+ goto out_free_opp_table; -+ -+ ret = clk_prepare_enable(info->inter_clk); -+ if (ret) -+ goto out_disable_mux_clock; -+ - /* Search a safe voltage for intermediate frequency. */ - rate = clk_get_rate(info->inter_clk); - opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate); - if (IS_ERR(opp)) { - dev_err(cpu_dev, "cpu%d: failed to get intermediate opp\n", cpu); - ret = PTR_ERR(opp); -- goto out_free_opp_table; -+ goto out_disable_inter_clock; - } - info->intermediate_voltage = dev_pm_opp_get_voltage(opp); - dev_pm_opp_put(opp); -@@ -372,10 +393,21 @@ static int mtk_cpu_dvfs_info_init(struct - - return 0; - -+out_disable_inter_clock: -+ clk_disable_unprepare(info->inter_clk); -+ -+out_disable_mux_clock: -+ clk_disable_unprepare(info->cpu_clk); -+ - out_free_opp_table: - dev_pm_opp_of_cpumask_remove_table(&info->cpus); - - out_free_resources: -+ if (regulator_is_enabled(info->proc_reg)) -+ regulator_disable(info->proc_reg); -+ if (info->sram_reg && regulator_is_enabled(info->sram_reg)) -+ regulator_disable(info->sram_reg); -+ - if (!IS_ERR(info->proc_reg)) - regulator_put(info->proc_reg); - if (!IS_ERR(info->sram_reg)) -@@ -390,14 +422,22 @@ out_free_resources: - - static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info) - { -- if (!IS_ERR(info->proc_reg)) -+ if (!IS_ERR(info->proc_reg)) { -+ regulator_disable(info->proc_reg); - regulator_put(info->proc_reg); -- if (!IS_ERR(info->sram_reg)) -+ } -+ if (!IS_ERR(info->sram_reg)) { -+ regulator_disable(info->sram_reg); - regulator_put(info->sram_reg); -- if (!IS_ERR(info->cpu_clk)) -+ } -+ if (!IS_ERR(info->cpu_clk)) { -+ clk_disable_unprepare(info->cpu_clk); - clk_put(info->cpu_clk); -- if (!IS_ERR(info->inter_clk)) -+ } -+ if (!IS_ERR(info->inter_clk)) { -+ clk_disable_unprepare(info->inter_clk); - clk_put(info->inter_clk); -+ } - - dev_pm_opp_of_cpumask_remove_table(&info->cpus); - } diff --git a/target/linux/mediatek/patches-6.1/350-04-cpufreq-mediatek-Use-device-print-to-show-logs.patch b/target/linux/mediatek/patches-6.1/350-04-cpufreq-mediatek-Use-device-print-to-show-logs.patch deleted file mode 100644 index 18e1da728a8..00000000000 --- a/target/linux/mediatek/patches-6.1/350-04-cpufreq-mediatek-Use-device-print-to-show-logs.patch +++ /dev/null @@ -1,161 +0,0 @@ -From a02e2b359141035d2d6999940bc1b9f83ec88587 Mon Sep 17 00:00:00 2001 -From: Rex-BC Chen -Date: Fri, 22 Apr 2022 15:52:27 +0800 -Subject: [PATCH 04/21] cpufreq: mediatek: Use device print to show logs - -- Replace pr_* with dev_* to show logs. -- Remove usage of __func__. - -Signed-off-by: Rex-BC Chen -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 54 ++++++++++++++++-------------- - 1 file changed, 28 insertions(+), 26 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -67,7 +67,8 @@ static int mtk_cpufreq_voltage_tracking( - - old_vproc = regulator_get_voltage(proc_reg); - if (old_vproc < 0) { -- pr_err("%s: invalid Vproc value: %d\n", __func__, old_vproc); -+ dev_err(info->cpu_dev, -+ "invalid Vproc value: %d\n", old_vproc); - return old_vproc; - } - /* Vsram should not exceed the maximum allowed voltage of SoC. */ -@@ -83,14 +84,14 @@ static int mtk_cpufreq_voltage_tracking( - do { - old_vsram = regulator_get_voltage(sram_reg); - if (old_vsram < 0) { -- pr_err("%s: invalid Vsram value: %d\n", -- __func__, old_vsram); -+ dev_err(info->cpu_dev, -+ "invalid Vsram value: %d\n", old_vsram); - return old_vsram; - } - old_vproc = regulator_get_voltage(proc_reg); - if (old_vproc < 0) { -- pr_err("%s: invalid Vproc value: %d\n", -- __func__, old_vproc); -+ dev_err(info->cpu_dev, -+ "invalid Vproc value: %d\n", old_vproc); - return old_vproc; - } - -@@ -138,14 +139,14 @@ static int mtk_cpufreq_voltage_tracking( - do { - old_vproc = regulator_get_voltage(proc_reg); - if (old_vproc < 0) { -- pr_err("%s: invalid Vproc value: %d\n", -- __func__, old_vproc); -+ dev_err(info->cpu_dev, -+ "invalid Vproc value: %d\n", old_vproc); - return old_vproc; - } - old_vsram = regulator_get_voltage(sram_reg); - if (old_vsram < 0) { -- pr_err("%s: invalid Vsram value: %d\n", -- __func__, old_vsram); -+ dev_err(info->cpu_dev, -+ "invalid Vsram value: %d\n", old_vsram); - return old_vsram; - } - -@@ -216,7 +217,7 @@ static int mtk_cpufreq_set_target(struct - old_freq_hz = clk_get_rate(cpu_clk); - old_vproc = regulator_get_voltage(info->proc_reg); - if (old_vproc < 0) { -- pr_err("%s: invalid Vproc value: %d\n", __func__, old_vproc); -+ dev_err(cpu_dev, "invalid Vproc value: %d\n", old_vproc); - return old_vproc; - } - -@@ -224,8 +225,8 @@ static int mtk_cpufreq_set_target(struct - - opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz); - if (IS_ERR(opp)) { -- pr_err("cpu%d: failed to find OPP for %ld\n", -- policy->cpu, freq_hz); -+ dev_err(cpu_dev, "cpu%d: failed to find OPP for %ld\n", -+ policy->cpu, freq_hz); - return PTR_ERR(opp); - } - vproc = dev_pm_opp_get_voltage(opp); -@@ -239,8 +240,8 @@ static int mtk_cpufreq_set_target(struct - if (old_vproc < target_vproc) { - ret = mtk_cpufreq_set_voltage(info, target_vproc); - if (ret) { -- pr_err("cpu%d: failed to scale up voltage!\n", -- policy->cpu); -+ dev_err(cpu_dev, -+ "cpu%d: failed to scale up voltage!\n", policy->cpu); - mtk_cpufreq_set_voltage(info, old_vproc); - return ret; - } -@@ -249,8 +250,8 @@ static int mtk_cpufreq_set_target(struct - /* Reparent the CPU clock to intermediate clock. */ - ret = clk_set_parent(cpu_clk, info->inter_clk); - if (ret) { -- pr_err("cpu%d: failed to re-parent cpu clock!\n", -- policy->cpu); -+ dev_err(cpu_dev, -+ "cpu%d: failed to re-parent cpu clock!\n", policy->cpu); - mtk_cpufreq_set_voltage(info, old_vproc); - WARN_ON(1); - return ret; -@@ -259,8 +260,8 @@ static int mtk_cpufreq_set_target(struct - /* Set the original PLL to target rate. */ - ret = clk_set_rate(armpll, freq_hz); - if (ret) { -- pr_err("cpu%d: failed to scale cpu clock rate!\n", -- policy->cpu); -+ dev_err(cpu_dev, -+ "cpu%d: failed to scale cpu clock rate!\n", policy->cpu); - clk_set_parent(cpu_clk, armpll); - mtk_cpufreq_set_voltage(info, old_vproc); - return ret; -@@ -269,8 +270,8 @@ static int mtk_cpufreq_set_target(struct - /* Set parent of CPU clock back to the original PLL. */ - ret = clk_set_parent(cpu_clk, armpll); - if (ret) { -- pr_err("cpu%d: failed to re-parent cpu clock!\n", -- policy->cpu); -+ dev_err(cpu_dev, -+ "cpu%d: failed to re-parent cpu clock!\n", policy->cpu); - mtk_cpufreq_set_voltage(info, inter_vproc); - WARN_ON(1); - return ret; -@@ -283,8 +284,8 @@ static int mtk_cpufreq_set_target(struct - if (vproc < inter_vproc || vproc < old_vproc) { - ret = mtk_cpufreq_set_voltage(info, vproc); - if (ret) { -- pr_err("cpu%d: failed to scale down voltage!\n", -- policy->cpu); -+ dev_err(cpu_dev, -+ "cpu%d: failed to scale down voltage!\n", policy->cpu); - clk_set_parent(cpu_clk, info->inter_clk); - clk_set_rate(armpll, old_freq_hz); - clk_set_parent(cpu_clk, armpll); -@@ -450,15 +451,16 @@ static int mtk_cpufreq_init(struct cpufr - - info = mtk_cpu_dvfs_info_lookup(policy->cpu); - if (!info) { -- pr_err("dvfs info for cpu%d is not initialized.\n", -- policy->cpu); -+ dev_err(info->cpu_dev, -+ "dvfs info for cpu%d is not initialized.\n", policy->cpu); - return -EINVAL; - } - - ret = dev_pm_opp_init_cpufreq_table(info->cpu_dev, &freq_table); - if (ret) { -- pr_err("failed to init cpufreq table for cpu%d: %d\n", -- policy->cpu, ret); -+ dev_err(info->cpu_dev, -+ "failed to init cpufreq table for cpu%d: %d\n", -+ policy->cpu, ret); - return ret; - } - diff --git a/target/linux/mediatek/patches-6.1/350-05-cpufreq-mediatek-Replace-old_-with-pre_.patch b/target/linux/mediatek/patches-6.1/350-05-cpufreq-mediatek-Replace-old_-with-pre_.patch deleted file mode 100644 index 8506f4e4776..00000000000 --- a/target/linux/mediatek/patches-6.1/350-05-cpufreq-mediatek-Replace-old_-with-pre_.patch +++ /dev/null @@ -1,201 +0,0 @@ -From 35832d9f9c5c1da01420d962dc56e7e61d104829 Mon Sep 17 00:00:00 2001 -From: Rex-BC Chen -Date: Fri, 22 Apr 2022 15:52:28 +0800 -Subject: [PATCH 05/21] cpufreq: mediatek: Replace old_* with pre_* - -To make driver more readable, replace old_* with pre_*. - -Signed-off-by: Rex-BC Chen -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 84 +++++++++++++++--------------- - 1 file changed, 42 insertions(+), 42 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -63,18 +63,18 @@ static int mtk_cpufreq_voltage_tracking( - { - struct regulator *proc_reg = info->proc_reg; - struct regulator *sram_reg = info->sram_reg; -- int old_vproc, old_vsram, new_vsram, vsram, vproc, ret; -+ int pre_vproc, pre_vsram, new_vsram, vsram, vproc, ret; - -- old_vproc = regulator_get_voltage(proc_reg); -- if (old_vproc < 0) { -+ pre_vproc = regulator_get_voltage(proc_reg); -+ if (pre_vproc < 0) { - dev_err(info->cpu_dev, -- "invalid Vproc value: %d\n", old_vproc); -- return old_vproc; -+ "invalid Vproc value: %d\n", pre_vproc); -+ return pre_vproc; - } - /* Vsram should not exceed the maximum allowed voltage of SoC. */ - new_vsram = min(new_vproc + MIN_VOLT_SHIFT, MAX_VOLT_LIMIT); - -- if (old_vproc < new_vproc) { -+ if (pre_vproc < new_vproc) { - /* - * When scaling up voltages, Vsram and Vproc scale up step - * by step. At each step, set Vsram to (Vproc + 200mV) first, -@@ -82,20 +82,20 @@ static int mtk_cpufreq_voltage_tracking( - * Keep doing it until Vsram and Vproc hit target voltages. - */ - do { -- old_vsram = regulator_get_voltage(sram_reg); -- if (old_vsram < 0) { -+ pre_vsram = regulator_get_voltage(sram_reg); -+ if (pre_vsram < 0) { - dev_err(info->cpu_dev, -- "invalid Vsram value: %d\n", old_vsram); -- return old_vsram; -+ "invalid Vsram value: %d\n", pre_vsram); -+ return pre_vsram; - } -- old_vproc = regulator_get_voltage(proc_reg); -- if (old_vproc < 0) { -+ pre_vproc = regulator_get_voltage(proc_reg); -+ if (pre_vproc < 0) { - dev_err(info->cpu_dev, -- "invalid Vproc value: %d\n", old_vproc); -- return old_vproc; -+ "invalid Vproc value: %d\n", pre_vproc); -+ return pre_vproc; - } - -- vsram = min(new_vsram, old_vproc + MAX_VOLT_SHIFT); -+ vsram = min(new_vsram, pre_vproc + MAX_VOLT_SHIFT); - - if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) { - vsram = MAX_VOLT_LIMIT; -@@ -124,12 +124,12 @@ static int mtk_cpufreq_voltage_tracking( - ret = regulator_set_voltage(proc_reg, vproc, - vproc + VOLT_TOL); - if (ret) { -- regulator_set_voltage(sram_reg, old_vsram, -- old_vsram); -+ regulator_set_voltage(sram_reg, pre_vsram, -+ pre_vsram); - return ret; - } - } while (vproc < new_vproc || vsram < new_vsram); -- } else if (old_vproc > new_vproc) { -+ } else if (pre_vproc > new_vproc) { - /* - * When scaling down voltages, Vsram and Vproc scale down step - * by step. At each step, set Vproc to (Vsram - 200mV) first, -@@ -137,20 +137,20 @@ static int mtk_cpufreq_voltage_tracking( - * Keep doing it until Vsram and Vproc hit target voltages. - */ - do { -- old_vproc = regulator_get_voltage(proc_reg); -- if (old_vproc < 0) { -+ pre_vproc = regulator_get_voltage(proc_reg); -+ if (pre_vproc < 0) { - dev_err(info->cpu_dev, -- "invalid Vproc value: %d\n", old_vproc); -- return old_vproc; -+ "invalid Vproc value: %d\n", pre_vproc); -+ return pre_vproc; - } -- old_vsram = regulator_get_voltage(sram_reg); -- if (old_vsram < 0) { -+ pre_vsram = regulator_get_voltage(sram_reg); -+ if (pre_vsram < 0) { - dev_err(info->cpu_dev, -- "invalid Vsram value: %d\n", old_vsram); -- return old_vsram; -+ "invalid Vsram value: %d\n", pre_vsram); -+ return pre_vsram; - } - -- vproc = max(new_vproc, old_vsram - MAX_VOLT_SHIFT); -+ vproc = max(new_vproc, pre_vsram - MAX_VOLT_SHIFT); - ret = regulator_set_voltage(proc_reg, vproc, - vproc + VOLT_TOL); - if (ret) -@@ -180,8 +180,8 @@ static int mtk_cpufreq_voltage_tracking( - } - - if (ret) { -- regulator_set_voltage(proc_reg, old_vproc, -- old_vproc); -+ regulator_set_voltage(proc_reg, pre_vproc, -+ pre_vproc); - return ret; - } - } while (vproc > new_vproc + VOLT_TOL || -@@ -209,16 +209,16 @@ static int mtk_cpufreq_set_target(struct - struct mtk_cpu_dvfs_info *info = policy->driver_data; - struct device *cpu_dev = info->cpu_dev; - struct dev_pm_opp *opp; -- long freq_hz, old_freq_hz; -- int vproc, old_vproc, inter_vproc, target_vproc, ret; -+ long freq_hz, pre_freq_hz; -+ int vproc, pre_vproc, inter_vproc, target_vproc, ret; - - inter_vproc = info->intermediate_voltage; - -- old_freq_hz = clk_get_rate(cpu_clk); -- old_vproc = regulator_get_voltage(info->proc_reg); -- if (old_vproc < 0) { -- dev_err(cpu_dev, "invalid Vproc value: %d\n", old_vproc); -- return old_vproc; -+ pre_freq_hz = clk_get_rate(cpu_clk); -+ pre_vproc = regulator_get_voltage(info->proc_reg); -+ if (pre_vproc < 0) { -+ dev_err(cpu_dev, "invalid Vproc value: %d\n", pre_vproc); -+ return pre_vproc; - } - - freq_hz = freq_table[index].frequency * 1000; -@@ -237,12 +237,12 @@ static int mtk_cpufreq_set_target(struct - * current voltage, scale up voltage first. - */ - target_vproc = (inter_vproc > vproc) ? inter_vproc : vproc; -- if (old_vproc < target_vproc) { -+ if (pre_vproc < target_vproc) { - ret = mtk_cpufreq_set_voltage(info, target_vproc); - if (ret) { - dev_err(cpu_dev, - "cpu%d: failed to scale up voltage!\n", policy->cpu); -- mtk_cpufreq_set_voltage(info, old_vproc); -+ mtk_cpufreq_set_voltage(info, pre_vproc); - return ret; - } - } -@@ -252,7 +252,7 @@ static int mtk_cpufreq_set_target(struct - if (ret) { - dev_err(cpu_dev, - "cpu%d: failed to re-parent cpu clock!\n", policy->cpu); -- mtk_cpufreq_set_voltage(info, old_vproc); -+ mtk_cpufreq_set_voltage(info, pre_vproc); - WARN_ON(1); - return ret; - } -@@ -263,7 +263,7 @@ static int mtk_cpufreq_set_target(struct - dev_err(cpu_dev, - "cpu%d: failed to scale cpu clock rate!\n", policy->cpu); - clk_set_parent(cpu_clk, armpll); -- mtk_cpufreq_set_voltage(info, old_vproc); -+ mtk_cpufreq_set_voltage(info, pre_vproc); - return ret; - } - -@@ -281,13 +281,13 @@ static int mtk_cpufreq_set_target(struct - * If the new voltage is lower than the intermediate voltage or the - * original voltage, scale down to the new voltage. - */ -- if (vproc < inter_vproc || vproc < old_vproc) { -+ if (vproc < inter_vproc || vproc < pre_vproc) { - ret = mtk_cpufreq_set_voltage(info, vproc); - if (ret) { - dev_err(cpu_dev, - "cpu%d: failed to scale down voltage!\n", policy->cpu); - clk_set_parent(cpu_clk, info->inter_clk); -- clk_set_rate(armpll, old_freq_hz); -+ clk_set_rate(armpll, pre_freq_hz); - clk_set_parent(cpu_clk, armpll); - return ret; - } diff --git a/target/linux/mediatek/patches-6.1/350-06-cpufreq-mediatek-Record-previous-target-vproc-value.patch b/target/linux/mediatek/patches-6.1/350-06-cpufreq-mediatek-Record-previous-target-vproc-value.patch deleted file mode 100644 index 94e6617d267..00000000000 --- a/target/linux/mediatek/patches-6.1/350-06-cpufreq-mediatek-Record-previous-target-vproc-value.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 34737eb8d0daa0d4183f10286a2f55d8788066bc Mon Sep 17 00:00:00 2001 -From: Jia-Wei Chang -Date: Fri, 22 Apr 2022 15:52:29 +0800 -Subject: [PATCH 06/21] cpufreq: mediatek: Record previous target vproc value - -We found the buck voltage may not be exactly the same with what we set -because CPU may share the same buck with other module. -Therefore, we need to record the previous desired value instead of reading -it from regulators. - -Signed-off-by: Andrew-sh.Cheng -Signed-off-by: Jia-Wei Chang -Signed-off-by: Rex-BC Chen -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 20 ++++++++++++++++---- - 1 file changed, 16 insertions(+), 4 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -40,6 +40,7 @@ struct mtk_cpu_dvfs_info { - struct list_head list_head; - int intermediate_voltage; - bool need_voltage_tracking; -+ int pre_vproc; - }; - - static struct platform_device *cpufreq_pdev; -@@ -193,11 +194,17 @@ static int mtk_cpufreq_voltage_tracking( - - static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc) - { -+ int ret; -+ - if (info->need_voltage_tracking) -- return mtk_cpufreq_voltage_tracking(info, vproc); -+ ret = mtk_cpufreq_voltage_tracking(info, vproc); - else -- return regulator_set_voltage(info->proc_reg, vproc, -- vproc + VOLT_TOL); -+ ret = regulator_set_voltage(info->proc_reg, vproc, -+ MAX_VOLT_LIMIT); -+ if (!ret) -+ info->pre_vproc = vproc; -+ -+ return ret; - } - - static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, -@@ -215,7 +222,12 @@ static int mtk_cpufreq_set_target(struct - inter_vproc = info->intermediate_voltage; - - pre_freq_hz = clk_get_rate(cpu_clk); -- pre_vproc = regulator_get_voltage(info->proc_reg); -+ -+ if (unlikely(info->pre_vproc <= 0)) -+ pre_vproc = regulator_get_voltage(info->proc_reg); -+ else -+ pre_vproc = info->pre_vproc; -+ - if (pre_vproc < 0) { - dev_err(cpu_dev, "invalid Vproc value: %d\n", pre_vproc); - return pre_vproc; diff --git a/target/linux/mediatek/patches-6.1/350-07-cpufreq-mediatek-Make-sram-regulator-optional.patch b/target/linux/mediatek/patches-6.1/350-07-cpufreq-mediatek-Make-sram-regulator-optional.patch deleted file mode 100644 index 4b74873b158..00000000000 --- a/target/linux/mediatek/patches-6.1/350-07-cpufreq-mediatek-Make-sram-regulator-optional.patch +++ /dev/null @@ -1,30 +0,0 @@ -From f6114c2bc563a8050e9dc874ad87e1448865f031 Mon Sep 17 00:00:00 2001 -From: Jia-Wei Chang -Date: Fri, 22 Apr 2022 15:52:33 +0800 -Subject: [PATCH 07/21] cpufreq: mediatek: Make sram regulator optional - -For some MediaTek SoCs, like MT8186, it's possible that the sram regulator -is shared between CPU and CCI. -We hope regulator framework can return error for error handling rather -than a dummy handler from regulator_get api. -Therefore, we choose to use regulator_get_optional. - -Signed-off-by: Jia-Wei Chang -Signed-off-by: Rex-BC Chen -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -354,7 +354,7 @@ static int mtk_cpu_dvfs_info_init(struct - } - - /* Both presence and absence of sram regulator are valid cases. */ -- info->sram_reg = regulator_get_exclusive(cpu_dev, "sram"); -+ info->sram_reg = regulator_get_optional(cpu_dev, "sram"); - if (IS_ERR(info->sram_reg)) - info->sram_reg = NULL; - else { diff --git a/target/linux/mediatek/patches-6.1/350-08-cpufreq-mediatek-Fix-NULL-pointer-dereference-in-med.patch b/target/linux/mediatek/patches-6.1/350-08-cpufreq-mediatek-Fix-NULL-pointer-dereference-in-med.patch deleted file mode 100644 index f2f572a753f..00000000000 --- a/target/linux/mediatek/patches-6.1/350-08-cpufreq-mediatek-Fix-NULL-pointer-dereference-in-med.patch +++ /dev/null @@ -1,32 +0,0 @@ -From fa7030d8ad4638acfd9e0fac84a20716d031dc95 Mon Sep 17 00:00:00 2001 -From: Wan Jiabing -Date: Tue, 26 Apr 2022 19:17:14 +0800 -Subject: [PATCH 08/21] cpufreq: mediatek: Fix NULL pointer dereference in - mediatek-cpufreq - -Fix following coccicheck error: -drivers/cpufreq/mediatek-cpufreq.c:464:16-23: ERROR: info is NULL but dereferenced. - -Use pr_err instead of dev_err to avoid dereferring a NULL pointer. - -Fixes: f52b16ba9fe4 ("cpufreq: mediatek: Use device print to show logs") -Signed-off-by: Wan Jiabing -Reviewed-by: Matthias Brugger -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -463,8 +463,8 @@ static int mtk_cpufreq_init(struct cpufr - - info = mtk_cpu_dvfs_info_lookup(policy->cpu); - if (!info) { -- dev_err(info->cpu_dev, -- "dvfs info for cpu%d is not initialized.\n", policy->cpu); -+ pr_err("dvfs info for cpu%d is not initialized.\n", -+ policy->cpu); - return -EINVAL; - } - diff --git a/target/linux/mediatek/patches-6.1/350-09-cpufreq-mediatek-Move-voltage-limits-to-platform-dat.patch b/target/linux/mediatek/patches-6.1/350-09-cpufreq-mediatek-Move-voltage-limits-to-platform-dat.patch deleted file mode 100644 index 23b319648dc..00000000000 --- a/target/linux/mediatek/patches-6.1/350-09-cpufreq-mediatek-Move-voltage-limits-to-platform-dat.patch +++ /dev/null @@ -1,227 +0,0 @@ -From be2354b064e6bafbbad599ae2e10569ba4f7d5a6 Mon Sep 17 00:00:00 2001 -From: Rex-BC Chen -Date: Thu, 5 May 2022 19:52:19 +0800 -Subject: [PATCH 09/21] cpufreq: mediatek: Move voltage limits to platform data - -Voltages and shifts are defined as macros originally. -There are different requirements of these values for each MediaTek SoCs. -Therefore, we add the platform data and move these values into it. - -Signed-off-by: Jia-Wei Chang -Signed-off-by: Rex-BC Chen -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 84 +++++++++++++++++++++--------- - 1 file changed, 58 insertions(+), 26 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -10,15 +10,21 @@ - #include - #include - #include -+#include - #include - #include - #include - --#define MIN_VOLT_SHIFT (100000) --#define MAX_VOLT_SHIFT (200000) --#define MAX_VOLT_LIMIT (1150000) - #define VOLT_TOL (10000) - -+struct mtk_cpufreq_platform_data { -+ int min_volt_shift; -+ int max_volt_shift; -+ int proc_max_volt; -+ int sram_min_volt; -+ int sram_max_volt; -+}; -+ - /* - * The struct mtk_cpu_dvfs_info holds necessary information for doing CPU DVFS - * on each CPU power/clock domain of Mediatek SoCs. Each CPU cluster in -@@ -41,6 +47,7 @@ struct mtk_cpu_dvfs_info { - int intermediate_voltage; - bool need_voltage_tracking; - int pre_vproc; -+ const struct mtk_cpufreq_platform_data *soc_data; - }; - - static struct platform_device *cpufreq_pdev; -@@ -62,6 +69,7 @@ static struct mtk_cpu_dvfs_info *mtk_cpu - static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, - int new_vproc) - { -+ const struct mtk_cpufreq_platform_data *soc_data = info->soc_data; - struct regulator *proc_reg = info->proc_reg; - struct regulator *sram_reg = info->sram_reg; - int pre_vproc, pre_vsram, new_vsram, vsram, vproc, ret; -@@ -73,7 +81,8 @@ static int mtk_cpufreq_voltage_tracking( - return pre_vproc; - } - /* Vsram should not exceed the maximum allowed voltage of SoC. */ -- new_vsram = min(new_vproc + MIN_VOLT_SHIFT, MAX_VOLT_LIMIT); -+ new_vsram = min(new_vproc + soc_data->min_volt_shift, -+ soc_data->sram_max_volt); - - if (pre_vproc < new_vproc) { - /* -@@ -96,10 +105,11 @@ static int mtk_cpufreq_voltage_tracking( - return pre_vproc; - } - -- vsram = min(new_vsram, pre_vproc + MAX_VOLT_SHIFT); -+ vsram = min(new_vsram, -+ pre_vproc + soc_data->min_volt_shift); - -- if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) { -- vsram = MAX_VOLT_LIMIT; -+ if (vsram + VOLT_TOL >= soc_data->sram_max_volt) { -+ vsram = soc_data->sram_max_volt; - - /* - * If the target Vsram hits the maximum voltage, -@@ -117,7 +127,7 @@ static int mtk_cpufreq_voltage_tracking( - ret = regulator_set_voltage(sram_reg, vsram, - vsram + VOLT_TOL); - -- vproc = vsram - MIN_VOLT_SHIFT; -+ vproc = vsram - soc_data->min_volt_shift; - } - if (ret) - return ret; -@@ -151,7 +161,8 @@ static int mtk_cpufreq_voltage_tracking( - return pre_vsram; - } - -- vproc = max(new_vproc, pre_vsram - MAX_VOLT_SHIFT); -+ vproc = max(new_vproc, -+ pre_vsram - soc_data->max_volt_shift); - ret = regulator_set_voltage(proc_reg, vproc, - vproc + VOLT_TOL); - if (ret) -@@ -160,10 +171,11 @@ static int mtk_cpufreq_voltage_tracking( - if (vproc == new_vproc) - vsram = new_vsram; - else -- vsram = max(new_vsram, vproc + MIN_VOLT_SHIFT); -+ vsram = max(new_vsram, -+ vproc + soc_data->min_volt_shift); - -- if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) { -- vsram = MAX_VOLT_LIMIT; -+ if (vsram + VOLT_TOL >= soc_data->sram_max_volt) { -+ vsram = soc_data->sram_max_volt; - - /* - * If the target Vsram hits the maximum voltage, -@@ -194,13 +206,14 @@ static int mtk_cpufreq_voltage_tracking( - - static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc) - { -+ const struct mtk_cpufreq_platform_data *soc_data = info->soc_data; - int ret; - - if (info->need_voltage_tracking) - ret = mtk_cpufreq_voltage_tracking(info, vproc); - else - ret = regulator_set_voltage(info->proc_reg, vproc, -- MAX_VOLT_LIMIT); -+ soc_data->proc_max_volt); - if (!ret) - info->pre_vproc = vproc; - -@@ -509,9 +522,17 @@ static struct cpufreq_driver mtk_cpufreq - - static int mtk_cpufreq_probe(struct platform_device *pdev) - { -+ const struct mtk_cpufreq_platform_data *data; - struct mtk_cpu_dvfs_info *info, *tmp; - int cpu, ret; - -+ data = dev_get_platdata(&pdev->dev); -+ if (!data) { -+ dev_err(&pdev->dev, -+ "failed to get mtk cpufreq platform data\n"); -+ return -ENODEV; -+ } -+ - for_each_possible_cpu(cpu) { - info = mtk_cpu_dvfs_info_lookup(cpu); - if (info) -@@ -523,6 +544,7 @@ static int mtk_cpufreq_probe(struct plat - goto release_dvfs_info_list; - } - -+ info->soc_data = data; - ret = mtk_cpu_dvfs_info_init(info, cpu); - if (ret) { - dev_err(&pdev->dev, -@@ -558,20 +580,27 @@ static struct platform_driver mtk_cpufre - .probe = mtk_cpufreq_probe, - }; - -+static const struct mtk_cpufreq_platform_data mt2701_platform_data = { -+ .min_volt_shift = 100000, -+ .max_volt_shift = 200000, -+ .proc_max_volt = 1150000, -+ .sram_min_volt = 0, -+ .sram_max_volt = 1150000, -+}; -+ - /* List of machines supported by this driver */ - static const struct of_device_id mtk_cpufreq_machines[] __initconst = { -- { .compatible = "mediatek,mt2701", }, -- { .compatible = "mediatek,mt2712", }, -- { .compatible = "mediatek,mt7622", }, -- { .compatible = "mediatek,mt7623", }, -- { .compatible = "mediatek,mt8167", }, -- { .compatible = "mediatek,mt817x", }, -- { .compatible = "mediatek,mt8173", }, -- { .compatible = "mediatek,mt8176", }, -- { .compatible = "mediatek,mt8183", }, -- { .compatible = "mediatek,mt8365", }, -- { .compatible = "mediatek,mt8516", }, -- -+ { .compatible = "mediatek,mt2701", .data = &mt2701_platform_data }, -+ { .compatible = "mediatek,mt2712", .data = &mt2701_platform_data }, -+ { .compatible = "mediatek,mt7622", .data = &mt2701_platform_data }, -+ { .compatible = "mediatek,mt7623", .data = &mt2701_platform_data }, -+ { .compatible = "mediatek,mt8167", .data = &mt2701_platform_data }, -+ { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data }, -+ { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data }, -+ { .compatible = "mediatek,mt8176", .data = &mt2701_platform_data }, -+ { .compatible = "mediatek,mt8183", .data = &mt2701_platform_data }, -+ { .compatible = "mediatek,mt8365", .data = &mt2701_platform_data }, -+ { .compatible = "mediatek,mt8516", .data = &mt2701_platform_data }, - { } - }; - MODULE_DEVICE_TABLE(of, mtk_cpufreq_machines); -@@ -580,6 +609,7 @@ static int __init mtk_cpufreq_driver_ini - { - struct device_node *np; - const struct of_device_id *match; -+ const struct mtk_cpufreq_platform_data *data; - int err; - - np = of_find_node_by_path("/"); -@@ -592,6 +622,7 @@ static int __init mtk_cpufreq_driver_ini - pr_debug("Machine is not compatible with mtk-cpufreq\n"); - return -ENODEV; - } -+ data = match->data; - - err = platform_driver_register(&mtk_cpufreq_platdrv); - if (err) -@@ -603,7 +634,8 @@ static int __init mtk_cpufreq_driver_ini - * and the device registration codes are put here to handle defer - * probing. - */ -- cpufreq_pdev = platform_device_register_simple("mtk-cpufreq", -1, NULL, 0); -+ cpufreq_pdev = platform_device_register_data(NULL, "mtk-cpufreq", -1, -+ data, sizeof(*data)); - if (IS_ERR(cpufreq_pdev)) { - pr_err("failed to register mtk-cpufreq platform device\n"); - platform_driver_unregister(&mtk_cpufreq_platdrv); diff --git a/target/linux/mediatek/patches-6.1/350-10-cpufreq-mediatek-Refine-mtk_cpufreq_voltage_tracking.patch b/target/linux/mediatek/patches-6.1/350-10-cpufreq-mediatek-Refine-mtk_cpufreq_voltage_tracking.patch deleted file mode 100644 index 0ba9471ffa7..00000000000 --- a/target/linux/mediatek/patches-6.1/350-10-cpufreq-mediatek-Refine-mtk_cpufreq_voltage_tracking.patch +++ /dev/null @@ -1,255 +0,0 @@ -From 944b041c91f1e1cd762c39c1222f078550149486 Mon Sep 17 00:00:00 2001 -From: Jia-Wei Chang -Date: Thu, 5 May 2022 19:52:20 +0800 -Subject: [PATCH 10/21] cpufreq: mediatek: Refine - mtk_cpufreq_voltage_tracking() - -Because the difference of sram and proc should in a range of min_volt_shift -and max_volt_shift. We need to adjust the sram and proc step by step. - -We replace VOLT_TOL (voltage tolerance) with the platform data and update the -logic to determine the voltage boundary and invoking regulator_set_voltage. - -- Use 'sram_min_volt' and 'sram_max_volt' to determine the voltage boundary - of sram regulator. -- Use (sram_min_volt - min_volt_shift) and 'proc_max_volt' to determine the - voltage boundary of vproc regulator. - -Moreover, to prevent infinite loop when tracking voltage, we calculate the -maximum value for each platform data. -We assume min voltage is 0 and tracking target voltage using -min_volt_shift for each iteration. -The retry_max is 3 times of expeted iteration count. - -Signed-off-by: Jia-Wei Chang -Signed-off-by: Rex-BC Chen -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 147 ++++++++++------------------- - 1 file changed, 51 insertions(+), 96 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -8,6 +8,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -15,8 +16,6 @@ - #include - #include - --#define VOLT_TOL (10000) -- - struct mtk_cpufreq_platform_data { - int min_volt_shift; - int max_volt_shift; -@@ -48,6 +47,7 @@ struct mtk_cpu_dvfs_info { - bool need_voltage_tracking; - int pre_vproc; - const struct mtk_cpufreq_platform_data *soc_data; -+ int vtrack_max; - }; - - static struct platform_device *cpufreq_pdev; -@@ -73,6 +73,7 @@ static int mtk_cpufreq_voltage_tracking( - struct regulator *proc_reg = info->proc_reg; - struct regulator *sram_reg = info->sram_reg; - int pre_vproc, pre_vsram, new_vsram, vsram, vproc, ret; -+ int retry = info->vtrack_max; - - pre_vproc = regulator_get_voltage(proc_reg); - if (pre_vproc < 0) { -@@ -80,91 +81,44 @@ static int mtk_cpufreq_voltage_tracking( - "invalid Vproc value: %d\n", pre_vproc); - return pre_vproc; - } -- /* Vsram should not exceed the maximum allowed voltage of SoC. */ -- new_vsram = min(new_vproc + soc_data->min_volt_shift, -- soc_data->sram_max_volt); -- -- if (pre_vproc < new_vproc) { -- /* -- * When scaling up voltages, Vsram and Vproc scale up step -- * by step. At each step, set Vsram to (Vproc + 200mV) first, -- * then set Vproc to (Vsram - 100mV). -- * Keep doing it until Vsram and Vproc hit target voltages. -- */ -- do { -- pre_vsram = regulator_get_voltage(sram_reg); -- if (pre_vsram < 0) { -- dev_err(info->cpu_dev, -- "invalid Vsram value: %d\n", pre_vsram); -- return pre_vsram; -- } -- pre_vproc = regulator_get_voltage(proc_reg); -- if (pre_vproc < 0) { -- dev_err(info->cpu_dev, -- "invalid Vproc value: %d\n", pre_vproc); -- return pre_vproc; -- } - -- vsram = min(new_vsram, -- pre_vproc + soc_data->min_volt_shift); -+ pre_vsram = regulator_get_voltage(sram_reg); -+ if (pre_vsram < 0) { -+ dev_err(info->cpu_dev, "invalid Vsram value: %d\n", pre_vsram); -+ return pre_vsram; -+ } - -- if (vsram + VOLT_TOL >= soc_data->sram_max_volt) { -- vsram = soc_data->sram_max_volt; -+ new_vsram = clamp(new_vproc + soc_data->min_volt_shift, -+ soc_data->sram_min_volt, soc_data->sram_max_volt); -+ -+ do { -+ if (pre_vproc <= new_vproc) { -+ vsram = clamp(pre_vproc + soc_data->max_volt_shift, -+ soc_data->sram_min_volt, new_vsram); -+ ret = regulator_set_voltage(sram_reg, vsram, -+ soc_data->sram_max_volt); - -- /* -- * If the target Vsram hits the maximum voltage, -- * try to set the exact voltage value first. -- */ -- ret = regulator_set_voltage(sram_reg, vsram, -- vsram); -- if (ret) -- ret = regulator_set_voltage(sram_reg, -- vsram - VOLT_TOL, -- vsram); -+ if (ret) -+ return ret; - -+ if (vsram == soc_data->sram_max_volt || -+ new_vsram == soc_data->sram_min_volt) - vproc = new_vproc; -- } else { -- ret = regulator_set_voltage(sram_reg, vsram, -- vsram + VOLT_TOL); -- -+ else - vproc = vsram - soc_data->min_volt_shift; -- } -- if (ret) -- return ret; - - ret = regulator_set_voltage(proc_reg, vproc, -- vproc + VOLT_TOL); -+ soc_data->proc_max_volt); - if (ret) { - regulator_set_voltage(sram_reg, pre_vsram, -- pre_vsram); -+ soc_data->sram_max_volt); - return ret; - } -- } while (vproc < new_vproc || vsram < new_vsram); -- } else if (pre_vproc > new_vproc) { -- /* -- * When scaling down voltages, Vsram and Vproc scale down step -- * by step. At each step, set Vproc to (Vsram - 200mV) first, -- * then set Vproc to (Vproc + 100mV). -- * Keep doing it until Vsram and Vproc hit target voltages. -- */ -- do { -- pre_vproc = regulator_get_voltage(proc_reg); -- if (pre_vproc < 0) { -- dev_err(info->cpu_dev, -- "invalid Vproc value: %d\n", pre_vproc); -- return pre_vproc; -- } -- pre_vsram = regulator_get_voltage(sram_reg); -- if (pre_vsram < 0) { -- dev_err(info->cpu_dev, -- "invalid Vsram value: %d\n", pre_vsram); -- return pre_vsram; -- } -- -+ } else if (pre_vproc > new_vproc) { - vproc = max(new_vproc, - pre_vsram - soc_data->max_volt_shift); - ret = regulator_set_voltage(proc_reg, vproc, -- vproc + VOLT_TOL); -+ soc_data->proc_max_volt); - if (ret) - return ret; - -@@ -174,32 +128,24 @@ static int mtk_cpufreq_voltage_tracking( - vsram = max(new_vsram, - vproc + soc_data->min_volt_shift); - -- if (vsram + VOLT_TOL >= soc_data->sram_max_volt) { -- vsram = soc_data->sram_max_volt; -- -- /* -- * If the target Vsram hits the maximum voltage, -- * try to set the exact voltage value first. -- */ -- ret = regulator_set_voltage(sram_reg, vsram, -- vsram); -- if (ret) -- ret = regulator_set_voltage(sram_reg, -- vsram - VOLT_TOL, -- vsram); -- } else { -- ret = regulator_set_voltage(sram_reg, vsram, -- vsram + VOLT_TOL); -- } -- -+ ret = regulator_set_voltage(sram_reg, vsram, -+ soc_data->sram_max_volt); - if (ret) { - regulator_set_voltage(proc_reg, pre_vproc, -- pre_vproc); -+ soc_data->proc_max_volt); - return ret; - } -- } while (vproc > new_vproc + VOLT_TOL || -- vsram > new_vsram + VOLT_TOL); -- } -+ } -+ -+ pre_vproc = vproc; -+ pre_vsram = vsram; -+ -+ if (--retry < 0) { -+ dev_err(info->cpu_dev, -+ "over loop count, failed to set voltage\n"); -+ return -EINVAL; -+ } -+ } while (vproc != new_vproc || vsram != new_vsram); - - return 0; - } -@@ -261,8 +207,8 @@ static int mtk_cpufreq_set_target(struct - * If the new voltage or the intermediate voltage is higher than the - * current voltage, scale up voltage first. - */ -- target_vproc = (inter_vproc > vproc) ? inter_vproc : vproc; -- if (pre_vproc < target_vproc) { -+ target_vproc = max(inter_vproc, vproc); -+ if (pre_vproc <= target_vproc) { - ret = mtk_cpufreq_set_voltage(info, target_vproc); - if (ret) { - dev_err(cpu_dev, -@@ -417,6 +363,15 @@ static int mtk_cpu_dvfs_info_init(struct - */ - info->need_voltage_tracking = (info->sram_reg != NULL); - -+ /* -+ * We assume min voltage is 0 and tracking target voltage using -+ * min_volt_shift for each iteration. -+ * The vtrack_max is 3 times of expeted iteration count. -+ */ -+ info->vtrack_max = 3 * DIV_ROUND_UP(max(info->soc_data->sram_max_volt, -+ info->soc_data->proc_max_volt), -+ info->soc_data->min_volt_shift); -+ - return 0; - - out_disable_inter_clock: diff --git a/target/linux/mediatek/patches-6.1/350-11-cpufreq-mediatek-Add-opp-notification-support.patch b/target/linux/mediatek/patches-6.1/350-11-cpufreq-mediatek-Add-opp-notification-support.patch deleted file mode 100644 index 2cb99b907a6..00000000000 --- a/target/linux/mediatek/patches-6.1/350-11-cpufreq-mediatek-Add-opp-notification-support.patch +++ /dev/null @@ -1,184 +0,0 @@ -From 01be227eff7e5fc01f7c8de8f6daddd5fb17ddd1 Mon Sep 17 00:00:00 2001 -From: Rex-BC Chen -Date: Thu, 5 May 2022 19:52:21 +0800 -Subject: [PATCH 11/21] cpufreq: mediatek: Add opp notification support - -From this opp notifier, cpufreq should listen to opp notification and do -proper actions when receiving events of disable and voltage adjustment. - -One of the user for this opp notifier is MediaTek SVS. -The MediaTek Smart Voltage Scaling (SVS) is a hardware which calculates -suitable SVS bank voltages to OPP voltage table. - -Signed-off-by: Andrew-sh.Cheng -Signed-off-by: Jia-Wei Chang -Signed-off-by: Rex-BC Chen -Reviewed-by: AngeloGioacchino Del Regno -[ Viresh: Renamed opp_freq as current_freq and moved its initialization ] -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 90 +++++++++++++++++++++++++++--- - 1 file changed, 82 insertions(+), 8 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -46,6 +46,11 @@ struct mtk_cpu_dvfs_info { - int intermediate_voltage; - bool need_voltage_tracking; - int pre_vproc; -+ /* Avoid race condition for regulators between notify and policy */ -+ struct mutex reg_lock; -+ struct notifier_block opp_nb; -+ unsigned int opp_cpu; -+ unsigned long current_freq; - const struct mtk_cpufreq_platform_data *soc_data; - int vtrack_max; - }; -@@ -182,6 +187,8 @@ static int mtk_cpufreq_set_target(struct - - pre_freq_hz = clk_get_rate(cpu_clk); - -+ mutex_lock(&info->reg_lock); -+ - if (unlikely(info->pre_vproc <= 0)) - pre_vproc = regulator_get_voltage(info->proc_reg); - else -@@ -214,7 +221,7 @@ static int mtk_cpufreq_set_target(struct - dev_err(cpu_dev, - "cpu%d: failed to scale up voltage!\n", policy->cpu); - mtk_cpufreq_set_voltage(info, pre_vproc); -- return ret; -+ goto out; - } - } - -@@ -224,8 +231,7 @@ static int mtk_cpufreq_set_target(struct - dev_err(cpu_dev, - "cpu%d: failed to re-parent cpu clock!\n", policy->cpu); - mtk_cpufreq_set_voltage(info, pre_vproc); -- WARN_ON(1); -- return ret; -+ goto out; - } - - /* Set the original PLL to target rate. */ -@@ -235,7 +241,7 @@ static int mtk_cpufreq_set_target(struct - "cpu%d: failed to scale cpu clock rate!\n", policy->cpu); - clk_set_parent(cpu_clk, armpll); - mtk_cpufreq_set_voltage(info, pre_vproc); -- return ret; -+ goto out; - } - - /* Set parent of CPU clock back to the original PLL. */ -@@ -244,8 +250,7 @@ static int mtk_cpufreq_set_target(struct - dev_err(cpu_dev, - "cpu%d: failed to re-parent cpu clock!\n", policy->cpu); - mtk_cpufreq_set_voltage(info, inter_vproc); -- WARN_ON(1); -- return ret; -+ goto out; - } - - /* -@@ -260,15 +265,72 @@ static int mtk_cpufreq_set_target(struct - clk_set_parent(cpu_clk, info->inter_clk); - clk_set_rate(armpll, pre_freq_hz); - clk_set_parent(cpu_clk, armpll); -- return ret; -+ goto out; - } - } - -- return 0; -+ info->current_freq = freq_hz; -+ -+out: -+ mutex_unlock(&info->reg_lock); -+ -+ return ret; - } - - #define DYNAMIC_POWER "dynamic-power-coefficient" - -+static int mtk_cpufreq_opp_notifier(struct notifier_block *nb, -+ unsigned long event, void *data) -+{ -+ struct dev_pm_opp *opp = data; -+ struct dev_pm_opp *new_opp; -+ struct mtk_cpu_dvfs_info *info; -+ unsigned long freq, volt; -+ struct cpufreq_policy *policy; -+ int ret = 0; -+ -+ info = container_of(nb, struct mtk_cpu_dvfs_info, opp_nb); -+ -+ if (event == OPP_EVENT_ADJUST_VOLTAGE) { -+ freq = dev_pm_opp_get_freq(opp); -+ -+ mutex_lock(&info->reg_lock); -+ if (info->current_freq == freq) { -+ volt = dev_pm_opp_get_voltage(opp); -+ ret = mtk_cpufreq_set_voltage(info, volt); -+ if (ret) -+ dev_err(info->cpu_dev, -+ "failed to scale voltage: %d\n", ret); -+ } -+ mutex_unlock(&info->reg_lock); -+ } else if (event == OPP_EVENT_DISABLE) { -+ freq = dev_pm_opp_get_freq(opp); -+ -+ /* case of current opp item is disabled */ -+ if (info->current_freq == freq) { -+ freq = 1; -+ new_opp = dev_pm_opp_find_freq_ceil(info->cpu_dev, -+ &freq); -+ if (IS_ERR(new_opp)) { -+ dev_err(info->cpu_dev, -+ "all opp items are disabled\n"); -+ ret = PTR_ERR(new_opp); -+ return notifier_from_errno(ret); -+ } -+ -+ dev_pm_opp_put(new_opp); -+ policy = cpufreq_cpu_get(info->opp_cpu); -+ if (policy) { -+ cpufreq_driver_target(policy, freq / 1000, -+ CPUFREQ_RELATION_L); -+ cpufreq_cpu_put(policy); -+ } -+ } -+ } -+ -+ return notifier_from_errno(ret); -+} -+ - static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) - { - struct device *cpu_dev; -@@ -357,6 +419,17 @@ static int mtk_cpu_dvfs_info_init(struct - info->intermediate_voltage = dev_pm_opp_get_voltage(opp); - dev_pm_opp_put(opp); - -+ mutex_init(&info->reg_lock); -+ info->current_freq = clk_get_rate(info->cpu_clk); -+ -+ info->opp_cpu = cpu; -+ info->opp_nb.notifier_call = mtk_cpufreq_opp_notifier; -+ ret = dev_pm_opp_register_notifier(cpu_dev, &info->opp_nb); -+ if (ret) { -+ dev_err(cpu_dev, "cpu%d: failed to register opp notifier\n", cpu); -+ goto out_disable_inter_clock; -+ } -+ - /* - * If SRAM regulator is present, software "voltage tracking" is needed - * for this CPU power domain. -@@ -421,6 +494,7 @@ static void mtk_cpu_dvfs_info_release(st - } - - dev_pm_opp_of_cpumask_remove_table(&info->cpus); -+ dev_pm_opp_unregister_notifier(info->cpu_dev, &info->opp_nb); - } - - static int mtk_cpufreq_init(struct cpufreq_policy *policy) diff --git a/target/linux/mediatek/patches-6.1/350-12-cpufreq-mediatek-Fix-potential-deadlock-problem-in-m.patch b/target/linux/mediatek/patches-6.1/350-12-cpufreq-mediatek-Fix-potential-deadlock-problem-in-m.patch deleted file mode 100644 index 76bd795c004..00000000000 --- a/target/linux/mediatek/patches-6.1/350-12-cpufreq-mediatek-Fix-potential-deadlock-problem-in-m.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 6a1bd7cf4ed7a1948f564aaf16d34b7352c0029b Mon Sep 17 00:00:00 2001 -From: Wan Jiabing -Date: Tue, 10 May 2022 17:05:31 +0800 -Subject: [PATCH 12/21] cpufreq: mediatek: Fix potential deadlock problem in - mtk_cpufreq_set_target - -Fix following coccichek error: -./drivers/cpufreq/mediatek-cpufreq.c:199:2-8: preceding lock on line -./drivers/cpufreq/mediatek-cpufreq.c:208:2-8: preceding lock on line - -mutex_lock is acquired but not released before return. -Use 'goto out' to help releasing the mutex_lock. - -Fixes: c210063b40ac ("cpufreq: mediatek: Add opp notification support") -Signed-off-by: Wan Jiabing -Reviewed-by: Rex-BC Chen -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -196,7 +196,8 @@ static int mtk_cpufreq_set_target(struct - - if (pre_vproc < 0) { - dev_err(cpu_dev, "invalid Vproc value: %d\n", pre_vproc); -- return pre_vproc; -+ ret = pre_vproc; -+ goto out; - } - - freq_hz = freq_table[index].frequency * 1000; -@@ -205,7 +206,8 @@ static int mtk_cpufreq_set_target(struct - if (IS_ERR(opp)) { - dev_err(cpu_dev, "cpu%d: failed to find OPP for %ld\n", - policy->cpu, freq_hz); -- return PTR_ERR(opp); -+ ret = PTR_ERR(opp); -+ goto out; - } - vproc = dev_pm_opp_get_voltage(opp); - dev_pm_opp_put(opp); diff --git a/target/linux/mediatek/patches-6.1/350-13-cpufreq-mediatek-Link-CCI-device-to-CPU.patch b/target/linux/mediatek/patches-6.1/350-13-cpufreq-mediatek-Link-CCI-device-to-CPU.patch deleted file mode 100644 index eeaa466c326..00000000000 --- a/target/linux/mediatek/patches-6.1/350-13-cpufreq-mediatek-Link-CCI-device-to-CPU.patch +++ /dev/null @@ -1,188 +0,0 @@ -From 15aaf74fb734a3e69b10d00b97b322711b81e222 Mon Sep 17 00:00:00 2001 -From: Rex-BC Chen -Date: Thu, 5 May 2022 19:52:22 +0800 -Subject: [PATCH 13/21] cpufreq: mediatek: Link CCI device to CPU - -In some MediaTek SoCs, like MT8183, CPU and CCI share the same power -supplies. Cpufreq needs to check if CCI devfreq exists and wait until -CCI devfreq ready before scaling frequency. - -Before CCI devfreq is ready, we record the voltage when booting to -kernel and use the max(cpu target voltage, booting voltage) to -prevent cpufreq adjust to the lower voltage which will cause the CCI -crash because of high frequency and low voltage. - -- Add is_ccifreq_ready() to link CCI device to CPI, and CPU will start - DVFS when CCI is ready. -- Add platform data for MT8183. - -Signed-off-by: Jia-Wei Chang -Signed-off-by: Rex-BC Chen -Reviewed-by: AngeloGioacchino Del Regno -Reviewed-by: Kevin Hilman -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 82 +++++++++++++++++++++++++++++- - 1 file changed, 81 insertions(+), 1 deletion(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -22,6 +22,7 @@ struct mtk_cpufreq_platform_data { - int proc_max_volt; - int sram_min_volt; - int sram_max_volt; -+ bool ccifreq_supported; - }; - - /* -@@ -38,6 +39,7 @@ struct mtk_cpufreq_platform_data { - struct mtk_cpu_dvfs_info { - struct cpumask cpus; - struct device *cpu_dev; -+ struct device *cci_dev; - struct regulator *proc_reg; - struct regulator *sram_reg; - struct clk *cpu_clk; -@@ -45,6 +47,7 @@ struct mtk_cpu_dvfs_info { - struct list_head list_head; - int intermediate_voltage; - bool need_voltage_tracking; -+ int vproc_on_boot; - int pre_vproc; - /* Avoid race condition for regulators between notify and policy */ - struct mutex reg_lock; -@@ -53,6 +56,7 @@ struct mtk_cpu_dvfs_info { - unsigned long current_freq; - const struct mtk_cpufreq_platform_data *soc_data; - int vtrack_max; -+ bool ccifreq_bound; - }; - - static struct platform_device *cpufreq_pdev; -@@ -171,6 +175,28 @@ static int mtk_cpufreq_set_voltage(struc - return ret; - } - -+static bool is_ccifreq_ready(struct mtk_cpu_dvfs_info *info) -+{ -+ struct device_link *sup_link; -+ -+ if (info->ccifreq_bound) -+ return true; -+ -+ sup_link = device_link_add(info->cpu_dev, info->cci_dev, -+ DL_FLAG_AUTOREMOVE_CONSUMER); -+ if (!sup_link) { -+ dev_err(info->cpu_dev, "cpu%d: sup_link is NULL\n", info->opp_cpu); -+ return false; -+ } -+ -+ if (sup_link->supplier->links.status != DL_DEV_DRIVER_BOUND) -+ return false; -+ -+ info->ccifreq_bound = true; -+ -+ return true; -+} -+ - static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, - unsigned int index) - { -@@ -213,6 +239,14 @@ static int mtk_cpufreq_set_target(struct - dev_pm_opp_put(opp); - - /* -+ * If MediaTek cci is supported but is not ready, we will use the value -+ * of max(target cpu voltage, booting voltage) to prevent high freqeuncy -+ * low voltage crash. -+ */ -+ if (info->soc_data->ccifreq_supported && !is_ccifreq_ready(info)) -+ vproc = max(vproc, info->vproc_on_boot); -+ -+ /* - * If the new voltage or the intermediate voltage is higher than the - * current voltage, scale up voltage first. - */ -@@ -333,6 +367,23 @@ static int mtk_cpufreq_opp_notifier(stru - return notifier_from_errno(ret); - } - -+static struct device *of_get_cci(struct device *cpu_dev) -+{ -+ struct device_node *np; -+ struct platform_device *pdev; -+ -+ np = of_parse_phandle(cpu_dev->of_node, "mediatek,cci", 0); -+ if (IS_ERR_OR_NULL(np)) -+ return NULL; -+ -+ pdev = of_find_device_by_node(np); -+ of_node_put(np); -+ if (IS_ERR_OR_NULL(pdev)) -+ return NULL; -+ -+ return &pdev->dev; -+} -+ - static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) - { - struct device *cpu_dev; -@@ -347,6 +398,16 @@ static int mtk_cpu_dvfs_info_init(struct - } - info->cpu_dev = cpu_dev; - -+ info->ccifreq_bound = false; -+ if (info->soc_data->ccifreq_supported) { -+ info->cci_dev = of_get_cci(info->cpu_dev); -+ if (IS_ERR_OR_NULL(info->cci_dev)) { -+ ret = PTR_ERR(info->cci_dev); -+ dev_err(cpu_dev, "cpu%d: failed to get cci device\n", cpu); -+ return -ENODEV; -+ } -+ } -+ - info->cpu_clk = clk_get(cpu_dev, "cpu"); - if (IS_ERR(info->cpu_clk)) { - ret = PTR_ERR(info->cpu_clk); -@@ -410,6 +471,15 @@ static int mtk_cpu_dvfs_info_init(struct - if (ret) - goto out_disable_mux_clock; - -+ if (info->soc_data->ccifreq_supported) { -+ info->vproc_on_boot = regulator_get_voltage(info->proc_reg); -+ if (info->vproc_on_boot < 0) { -+ dev_err(info->cpu_dev, -+ "invalid Vproc value: %d\n", info->vproc_on_boot); -+ goto out_disable_inter_clock; -+ } -+ } -+ - /* Search a safe voltage for intermediate frequency. */ - rate = clk_get_rate(info->inter_clk); - opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate); -@@ -617,6 +687,16 @@ static const struct mtk_cpufreq_platform - .proc_max_volt = 1150000, - .sram_min_volt = 0, - .sram_max_volt = 1150000, -+ .ccifreq_supported = false, -+}; -+ -+static const struct mtk_cpufreq_platform_data mt8183_platform_data = { -+ .min_volt_shift = 100000, -+ .max_volt_shift = 200000, -+ .proc_max_volt = 1150000, -+ .sram_min_volt = 0, -+ .sram_max_volt = 1150000, -+ .ccifreq_supported = true, - }; - - /* List of machines supported by this driver */ -@@ -629,7 +709,7 @@ static const struct of_device_id mtk_cpu - { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt8176", .data = &mt2701_platform_data }, -- { .compatible = "mediatek,mt8183", .data = &mt2701_platform_data }, -+ { .compatible = "mediatek,mt8183", .data = &mt8183_platform_data }, - { .compatible = "mediatek,mt8365", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt8516", .data = &mt2701_platform_data }, - { } diff --git a/target/linux/mediatek/patches-6.1/350-14-cpufreq-mediatek-Add-support-for-MT8186.patch b/target/linux/mediatek/patches-6.1/350-14-cpufreq-mediatek-Add-support-for-MT8186.patch deleted file mode 100644 index 31000cfbe05..00000000000 --- a/target/linux/mediatek/patches-6.1/350-14-cpufreq-mediatek-Add-support-for-MT8186.patch +++ /dev/null @@ -1,42 +0,0 @@ -From b6be0baa6615afc65c3963adab674e36af1d4d5f Mon Sep 17 00:00:00 2001 -From: Jia-Wei Chang -Date: Thu, 5 May 2022 19:52:23 +0800 -Subject: [PATCH 14/21] cpufreq: mediatek: Add support for MT8186 - -The platform data of MT8186 is different from previous MediaTek SoCs, -so we add a new compatible and platform data for it. - -Signed-off-by: Jia-Wei Chang -Signed-off-by: Rex-BC Chen -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -699,6 +699,15 @@ static const struct mtk_cpufreq_platform - .ccifreq_supported = true, - }; - -+static const struct mtk_cpufreq_platform_data mt8186_platform_data = { -+ .min_volt_shift = 100000, -+ .max_volt_shift = 250000, -+ .proc_max_volt = 1118750, -+ .sram_min_volt = 850000, -+ .sram_max_volt = 1118750, -+ .ccifreq_supported = true, -+}; -+ - /* List of machines supported by this driver */ - static const struct of_device_id mtk_cpufreq_machines[] __initconst = { - { .compatible = "mediatek,mt2701", .data = &mt2701_platform_data }, -@@ -710,6 +719,7 @@ static const struct of_device_id mtk_cpu - { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt8176", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt8183", .data = &mt8183_platform_data }, -+ { .compatible = "mediatek,mt8186", .data = &mt8186_platform_data }, - { .compatible = "mediatek,mt8365", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt8516", .data = &mt2701_platform_data }, - { } diff --git a/target/linux/mediatek/patches-6.1/350-15-cpufreq-mediatek-Handle-sram-regulator-probe-deferra.patch b/target/linux/mediatek/patches-6.1/350-15-cpufreq-mediatek-Handle-sram-regulator-probe-deferra.patch deleted file mode 100644 index c0137894c93..00000000000 --- a/target/linux/mediatek/patches-6.1/350-15-cpufreq-mediatek-Handle-sram-regulator-probe-deferra.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 75d19b24aa3203d6c78e4c431c2cc07157ce12fe Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Wed, 13 Jul 2022 13:15:36 +0200 -Subject: [PATCH 15/21] cpufreq: mediatek: Handle sram regulator probe deferral - -If the regulator_get_optional() call for the SRAM regulator returns -a probe deferral, we must bail out and retry probing later: failing -to do this will produce unstabilities on platforms requiring the -handling for this regulator. - -Fixes: ffa7bdf7f344 ("cpufreq: mediatek: Make sram regulator optional") -Signed-off-by: AngeloGioacchino Del Regno -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 8 ++++++-- - 1 file changed, 6 insertions(+), 2 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -439,9 +439,13 @@ static int mtk_cpu_dvfs_info_init(struct - - /* Both presence and absence of sram regulator are valid cases. */ - info->sram_reg = regulator_get_optional(cpu_dev, "sram"); -- if (IS_ERR(info->sram_reg)) -+ if (IS_ERR(info->sram_reg)) { -+ ret = PTR_ERR(info->sram_reg); -+ if (ret == -EPROBE_DEFER) -+ goto out_free_resources; -+ - info->sram_reg = NULL; -- else { -+ } else { - ret = regulator_enable(info->sram_reg); - if (ret) { - dev_warn(cpu_dev, "cpu%d: failed to enable vsram\n", cpu); diff --git a/target/linux/mediatek/patches-6.1/350-16-cpufreq-mediatek-fix-error-return-code-in-mtk_cpu_dv.patch b/target/linux/mediatek/patches-6.1/350-16-cpufreq-mediatek-fix-error-return-code-in-mtk_cpu_dv.patch deleted file mode 100644 index 45c4477ff1a..00000000000 --- a/target/linux/mediatek/patches-6.1/350-16-cpufreq-mediatek-fix-error-return-code-in-mtk_cpu_dv.patch +++ /dev/null @@ -1,29 +0,0 @@ -From dd1174c21dacacd6c0129c1dabc5decad35c02c2 Mon Sep 17 00:00:00 2001 -From: Yang Yingliang -Date: Tue, 17 May 2022 21:34:50 +0800 -Subject: [PATCH 16/21] cpufreq: mediatek: fix error return code in - mtk_cpu_dvfs_info_init() - -If regulator_get_voltage() fails, it should return the error code in -mtk_cpu_dvfs_info_init(). - -Fixes: 0daa47325bae ("cpufreq: mediatek: Link CCI device to CPU") -Reported-by: Hulk Robot -Signed-off-by: Yang Yingliang -Reviewed-by: AngeloGioacchino Del Regno -Reviewed-by: Rex-BC Chen -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -478,6 +478,7 @@ static int mtk_cpu_dvfs_info_init(struct - if (info->soc_data->ccifreq_supported) { - info->vproc_on_boot = regulator_get_voltage(info->proc_reg); - if (info->vproc_on_boot < 0) { -+ ret = info->vproc_on_boot; - dev_err(info->cpu_dev, - "invalid Vproc value: %d\n", info->vproc_on_boot); - goto out_disable_inter_clock; diff --git a/target/linux/mediatek/patches-6.1/350-17-cpufreq-mediatek-fix-passing-zero-to-PTR_ERR.patch b/target/linux/mediatek/patches-6.1/350-17-cpufreq-mediatek-fix-passing-zero-to-PTR_ERR.patch deleted file mode 100644 index 557d02b822b..00000000000 --- a/target/linux/mediatek/patches-6.1/350-17-cpufreq-mediatek-fix-passing-zero-to-PTR_ERR.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 230a74d459244411db91bfd678f17fcf7aedfcd0 Mon Sep 17 00:00:00 2001 -From: Jia-Wei Chang -Date: Fri, 24 Mar 2023 18:11:27 +0800 -Subject: [PATCH 17/21] cpufreq: mediatek: fix passing zero to 'PTR_ERR' - -In order to prevent passing zero to 'PTR_ERR' in -mtk_cpu_dvfs_info_init(), we fix the return value of of_get_cci() using -error pointer by explicitly casting error number. - -Signed-off-by: Jia-Wei Chang -Fixes: 0daa47325bae ("cpufreq: mediatek: Link CCI device to CPU") -Reported-by: Dan Carpenter -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 10 +++++----- - 1 file changed, 5 insertions(+), 5 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -373,13 +373,13 @@ static struct device *of_get_cci(struct - struct platform_device *pdev; - - np = of_parse_phandle(cpu_dev->of_node, "mediatek,cci", 0); -- if (IS_ERR_OR_NULL(np)) -- return NULL; -+ if (!np) -+ return ERR_PTR(-ENODEV); - - pdev = of_find_device_by_node(np); - of_node_put(np); -- if (IS_ERR_OR_NULL(pdev)) -- return NULL; -+ if (!pdev) -+ return ERR_PTR(-ENODEV); - - return &pdev->dev; - } -@@ -401,7 +401,7 @@ static int mtk_cpu_dvfs_info_init(struct - info->ccifreq_bound = false; - if (info->soc_data->ccifreq_supported) { - info->cci_dev = of_get_cci(info->cpu_dev); -- if (IS_ERR_OR_NULL(info->cci_dev)) { -+ if (IS_ERR(info->cci_dev)) { - ret = PTR_ERR(info->cci_dev); - dev_err(cpu_dev, "cpu%d: failed to get cci device\n", cpu); - return -ENODEV; diff --git a/target/linux/mediatek/patches-6.1/350-18-cpufreq-mediatek-fix-KP-caused-by-handler-usage-afte.patch b/target/linux/mediatek/patches-6.1/350-18-cpufreq-mediatek-fix-KP-caused-by-handler-usage-afte.patch deleted file mode 100644 index 61531d38ad2..00000000000 --- a/target/linux/mediatek/patches-6.1/350-18-cpufreq-mediatek-fix-KP-caused-by-handler-usage-afte.patch +++ /dev/null @@ -1,149 +0,0 @@ -From fced531b7c7e18192e7982637c8e8f20c29aad64 Mon Sep 17 00:00:00 2001 -From: Jia-Wei Chang -Date: Fri, 24 Mar 2023 18:11:28 +0800 -Subject: [PATCH 18/21] cpufreq: mediatek: fix KP caused by handler usage after - regulator_put/clk_put - -Any kind of failure in mtk_cpu_dvfs_info_init() will lead to calling -regulator_put() or clk_put() and the KP will occur since the regulator/clk -handlers are used after released in mtk_cpu_dvfs_info_release(). - -To prevent the usage after regulator_put()/clk_put(), the regulator/clk -handlers are addressed in a way of "Free the Last Thing Style". - -Signed-off-by: Jia-Wei Chang -Fixes: 4b9ceb757bbb ("cpufreq: mediatek: Enable clocks and regulators") -Suggested-by: AngeloGioacchino Del Regno -Suggested-by: Dan Carpenter -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 62 +++++++++++++++--------------- - 1 file changed, 30 insertions(+), 32 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -420,7 +420,7 @@ static int mtk_cpu_dvfs_info_init(struct - ret = PTR_ERR(info->inter_clk); - dev_err_probe(cpu_dev, ret, - "cpu%d: failed to get intermediate clk\n", cpu); -- goto out_free_resources; -+ goto out_free_mux_clock; - } - - info->proc_reg = regulator_get_optional(cpu_dev, "proc"); -@@ -428,13 +428,13 @@ static int mtk_cpu_dvfs_info_init(struct - ret = PTR_ERR(info->proc_reg); - dev_err_probe(cpu_dev, ret, - "cpu%d: failed to get proc regulator\n", cpu); -- goto out_free_resources; -+ goto out_free_inter_clock; - } - - ret = regulator_enable(info->proc_reg); - if (ret) { - dev_warn(cpu_dev, "cpu%d: failed to enable vproc\n", cpu); -- goto out_free_resources; -+ goto out_free_proc_reg; - } - - /* Both presence and absence of sram regulator are valid cases. */ -@@ -442,14 +442,14 @@ static int mtk_cpu_dvfs_info_init(struct - if (IS_ERR(info->sram_reg)) { - ret = PTR_ERR(info->sram_reg); - if (ret == -EPROBE_DEFER) -- goto out_free_resources; -+ goto out_disable_proc_reg; - - info->sram_reg = NULL; - } else { - ret = regulator_enable(info->sram_reg); - if (ret) { - dev_warn(cpu_dev, "cpu%d: failed to enable vsram\n", cpu); -- goto out_free_resources; -+ goto out_free_sram_reg; - } - } - -@@ -458,13 +458,13 @@ static int mtk_cpu_dvfs_info_init(struct - if (ret) { - dev_err(cpu_dev, - "cpu%d: failed to get OPP-sharing information\n", cpu); -- goto out_free_resources; -+ goto out_disable_sram_reg; - } - - ret = dev_pm_opp_of_cpumask_add_table(&info->cpus); - if (ret) { - dev_warn(cpu_dev, "cpu%d: no OPP table\n", cpu); -- goto out_free_resources; -+ goto out_disable_sram_reg; - } - - ret = clk_prepare_enable(info->cpu_clk); -@@ -533,43 +533,41 @@ out_disable_mux_clock: - out_free_opp_table: - dev_pm_opp_of_cpumask_remove_table(&info->cpus); - --out_free_resources: -- if (regulator_is_enabled(info->proc_reg)) -- regulator_disable(info->proc_reg); -- if (info->sram_reg && regulator_is_enabled(info->sram_reg)) -+out_disable_sram_reg: -+ if (info->sram_reg) - regulator_disable(info->sram_reg); - -- if (!IS_ERR(info->proc_reg)) -- regulator_put(info->proc_reg); -- if (!IS_ERR(info->sram_reg)) -+out_free_sram_reg: -+ if (info->sram_reg) - regulator_put(info->sram_reg); -- if (!IS_ERR(info->cpu_clk)) -- clk_put(info->cpu_clk); -- if (!IS_ERR(info->inter_clk)) -- clk_put(info->inter_clk); -+ -+out_disable_proc_reg: -+ regulator_disable(info->proc_reg); -+ -+out_free_proc_reg: -+ regulator_put(info->proc_reg); -+ -+out_free_inter_clock: -+ clk_put(info->inter_clk); -+ -+out_free_mux_clock: -+ clk_put(info->cpu_clk); - - return ret; - } - - static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info) - { -- if (!IS_ERR(info->proc_reg)) { -- regulator_disable(info->proc_reg); -- regulator_put(info->proc_reg); -- } -- if (!IS_ERR(info->sram_reg)) { -+ regulator_disable(info->proc_reg); -+ regulator_put(info->proc_reg); -+ if (info->sram_reg) { - regulator_disable(info->sram_reg); - regulator_put(info->sram_reg); - } -- if (!IS_ERR(info->cpu_clk)) { -- clk_disable_unprepare(info->cpu_clk); -- clk_put(info->cpu_clk); -- } -- if (!IS_ERR(info->inter_clk)) { -- clk_disable_unprepare(info->inter_clk); -- clk_put(info->inter_clk); -- } -- -+ clk_disable_unprepare(info->cpu_clk); -+ clk_put(info->cpu_clk); -+ clk_disable_unprepare(info->inter_clk); -+ clk_put(info->inter_clk); - dev_pm_opp_of_cpumask_remove_table(&info->cpus); - dev_pm_opp_unregister_notifier(info->cpu_dev, &info->opp_nb); - } diff --git a/target/linux/mediatek/patches-6.1/350-19-cpufreq-mediatek-raise-proc-sram-max-voltage-for-MT8.patch b/target/linux/mediatek/patches-6.1/350-19-cpufreq-mediatek-raise-proc-sram-max-voltage-for-MT8.patch deleted file mode 100644 index 2b7d229f1c5..00000000000 --- a/target/linux/mediatek/patches-6.1/350-19-cpufreq-mediatek-raise-proc-sram-max-voltage-for-MT8.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 24bc42a2d44cb821818717a5c607270921ec5d20 Mon Sep 17 00:00:00 2001 -From: Jia-Wei Chang -Date: Fri, 24 Mar 2023 18:11:29 +0800 -Subject: [PATCH 19/21] cpufreq: mediatek: raise proc/sram max voltage for - MT8516 - -Since the upper boundary of proc/sram voltage of MT8516 is 1300 mV, -which is greater than the value of MT2701 1150 mV, we fix it by adding -the corresponding platform data and specify proc/sram_max_volt to -support MT8516. - -Signed-off-by: Jia-Wei Chang -Fixes: ead858bd128d ("cpufreq: mediatek: Move voltage limits to platform data") -Fixes: 6a17b3876bc8 ("cpufreq: mediatek: Refine mtk_cpufreq_voltage_tracking()") -Reported-by: Nick Hainke -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 13 +++++++++++-- - 1 file changed, 11 insertions(+), 2 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -711,20 +711,29 @@ static const struct mtk_cpufreq_platform - .ccifreq_supported = true, - }; - -+static const struct mtk_cpufreq_platform_data mt8516_platform_data = { -+ .min_volt_shift = 100000, -+ .max_volt_shift = 200000, -+ .proc_max_volt = 1310000, -+ .sram_min_volt = 0, -+ .sram_max_volt = 1310000, -+ .ccifreq_supported = false, -+}; -+ - /* List of machines supported by this driver */ - static const struct of_device_id mtk_cpufreq_machines[] __initconst = { - { .compatible = "mediatek,mt2701", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt2712", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt7622", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt7623", .data = &mt2701_platform_data }, -- { .compatible = "mediatek,mt8167", .data = &mt2701_platform_data }, -+ { .compatible = "mediatek,mt8167", .data = &mt8516_platform_data }, - { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt8176", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt8183", .data = &mt8183_platform_data }, - { .compatible = "mediatek,mt8186", .data = &mt8186_platform_data }, - { .compatible = "mediatek,mt8365", .data = &mt2701_platform_data }, -- { .compatible = "mediatek,mt8516", .data = &mt2701_platform_data }, -+ { .compatible = "mediatek,mt8516", .data = &mt8516_platform_data }, - { } - }; - MODULE_DEVICE_TABLE(of, mtk_cpufreq_machines); diff --git a/target/linux/mediatek/patches-6.1/350-20-cpufreq-mediatek-Raise-proc-and-sram-max-voltage-for.patch b/target/linux/mediatek/patches-6.1/350-20-cpufreq-mediatek-Raise-proc-and-sram-max-voltage-for.patch deleted file mode 100644 index 2de8eb6394c..00000000000 --- a/target/linux/mediatek/patches-6.1/350-20-cpufreq-mediatek-Raise-proc-and-sram-max-voltage-for.patch +++ /dev/null @@ -1,58 +0,0 @@ -From fe6ef09358dc0cfead9d383a8676fbe7a40fcef7 Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Fri, 24 Mar 2023 18:11:30 +0800 -Subject: [PATCH 20/21] cpufreq: mediatek: Raise proc and sram max voltage for - MT7622/7623 - -During the addition of SRAM voltage tracking for CCI scaling, this -driver got some voltage limits set for the vtrack algorithm: these -were moved to platform data first, then enforced in a later commit -6a17b3876bc8 ("cpufreq: mediatek: Refine mtk_cpufreq_voltage_tracking()") -using these as max values for the regulator_set_voltage() calls. - -In this case, the vsram/vproc constraints for MT7622 and MT7623 -were supposed to be the same as MT2701 (and a number of other SoCs), -but that turned out to be a mistake because the aforementioned two -SoCs' maximum voltage for both VPROC and VPROC_SRAM is 1.36V. - -Fix that by adding new platform data for MT7622/7623 declaring the -right {proc,sram}_max_volt parameter. - -Fixes: ead858bd128d ("cpufreq: mediatek: Move voltage limits to platform data") -Fixes: 6a17b3876bc8 ("cpufreq: mediatek: Refine mtk_cpufreq_voltage_tracking()") -Signed-off-by: AngeloGioacchino Del Regno -Signed-off-by: Jia-Wei Chang -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 13 +++++++++++-- - 1 file changed, 11 insertions(+), 2 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -693,6 +693,15 @@ static const struct mtk_cpufreq_platform - .ccifreq_supported = false, - }; - -+static const struct mtk_cpufreq_platform_data mt7622_platform_data = { -+ .min_volt_shift = 100000, -+ .max_volt_shift = 200000, -+ .proc_max_volt = 1360000, -+ .sram_min_volt = 0, -+ .sram_max_volt = 1360000, -+ .ccifreq_supported = false, -+}; -+ - static const struct mtk_cpufreq_platform_data mt8183_platform_data = { - .min_volt_shift = 100000, - .max_volt_shift = 200000, -@@ -724,8 +733,8 @@ static const struct mtk_cpufreq_platform - static const struct of_device_id mtk_cpufreq_machines[] __initconst = { - { .compatible = "mediatek,mt2701", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt2712", .data = &mt2701_platform_data }, -- { .compatible = "mediatek,mt7622", .data = &mt2701_platform_data }, -- { .compatible = "mediatek,mt7623", .data = &mt2701_platform_data }, -+ { .compatible = "mediatek,mt7622", .data = &mt7622_platform_data }, -+ { .compatible = "mediatek,mt7623", .data = &mt7622_platform_data }, - { .compatible = "mediatek,mt8167", .data = &mt8516_platform_data }, - { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data }, diff --git a/target/linux/mediatek/patches-6.1/405-mt7986-trng-add-rng-support.patch b/target/linux/mediatek/patches-6.1/405-v6.2-mt7986-trng-add-rng-support.patch similarity index 80% rename from target/linux/mediatek/patches-6.1/405-mt7986-trng-add-rng-support.patch rename to target/linux/mediatek/patches-6.1/405-v6.2-mt7986-trng-add-rng-support.patch index 332f17bae73..615a1a1d714 100644 --- a/target/linux/mediatek/patches-6.1/405-mt7986-trng-add-rng-support.patch +++ b/target/linux/mediatek/patches-6.1/405-v6.2-mt7986-trng-add-rng-support.patch @@ -1,12 +1,14 @@ -From f6ba5e17bee38f8ffe118c47fbfef3cf90eb87ff Mon Sep 17 00:00:00 2001 +From f1da27b7c4191f78ed81d3dabf64c769f896296c Mon Sep 17 00:00:00 2001 From: "Mingming.Su" -Date: Wed, 30 Jun 2021 16:59:32 +0800 -Subject: [PATCH] mt7986: trng: add rng support +Date: Sat, 8 Oct 2022 18:45:53 +0200 +Subject: [PATCH] hwrng: mtk - add mt7986 support 1. Add trng compatible name for MT7986 2. Fix mtk_rng_wait_ready() function Signed-off-by: Mingming.Su +Signed-off-by: Frank Wunderlich +Signed-off-by: Herbert Xu --- drivers/char/hw_random/mtk-rng.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/linux/mediatek/patches-6.1/410-bt-mtk-serial-fix.patch b/target/linux/mediatek/patches-6.1/410-bt-mtk-serial-fix.patch index 3f4597c65d6..5b94c9216d9 100644 --- a/target/linux/mediatek/patches-6.1/410-bt-mtk-serial-fix.patch +++ b/target/linux/mediatek/patches-6.1/410-bt-mtk-serial-fix.patch @@ -1,16 +1,16 @@ --- a/drivers/tty/serial/8250/8250.h +++ b/drivers/tty/serial/8250/8250.h -@@ -85,6 +85,7 @@ struct serial8250_config { - #define UART_CAP_MINI BIT(17) /* Mini UART on BCM283X family lacks: +@@ -86,6 +86,7 @@ struct serial8250_config { * STOP PARITY EPAR SPAR WLEN5 WLEN6 */ -+#define UART_CAP_NMOD (1 << 18) /* UART doesn't do termios */ + #define UART_CAP_NOTEMT BIT(18) /* UART without interrupt on TEMT available */ ++#define UART_CAP_NMOD BIT(19) /* UART doesn't do termios */ #define UART_BUG_QUOT BIT(0) /* UART has buggy quot LSB */ #define UART_BUG_TXEN BIT(1) /* UART has buggy TX IIR status */ --- a/drivers/tty/serial/8250/8250_port.c +++ b/drivers/tty/serial/8250/8250_port.c -@@ -289,7 +289,7 @@ static const struct serial8250_config ua +@@ -287,7 +287,7 @@ static const struct serial8250_config ua .tx_loadsz = 16, .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, @@ -19,7 +19,7 @@ }, [PORT_NPCM] = { .name = "Nuvoton 16550", -@@ -2766,6 +2766,11 @@ serial8250_do_set_termios(struct uart_po +@@ -2773,6 +2773,11 @@ serial8250_do_set_termios(struct uart_po unsigned long flags; unsigned int baud, quot, frac = 0; diff --git a/target/linux/mediatek/patches-6.1/420-mtd-spi-nor-add-support-for-Winbond-W25Q512JV.patch b/target/linux/mediatek/patches-6.1/420-mtd-spi-nor-add-support-for-Winbond-W25Q512JV.patch deleted file mode 100644 index cc9e9c55e36..00000000000 --- a/target/linux/mediatek/patches-6.1/420-mtd-spi-nor-add-support-for-Winbond-W25Q512JV.patch +++ /dev/null @@ -1,28 +0,0 @@ -From: David Bauer -To: linux-mtd@lists.infradead.org -Subject: [PATCH] mtd: spi-nor: add support for Winbond W25Q512JV -Date: Sat, 13 Feb 2021 16:10:47 +0100 - -The Winbond W25Q512JV is a 512mb SPI-NOR chip. It supports 4K -sectors as well as block protection and Dual-/Quad-read. - -Tested on: Ubiquiti UniFi 6 LR - -Signed-off-by: David Bauer ---- - drivers/mtd/spi-nor/winbond.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/drivers/mtd/spi-nor/winbond.c -+++ b/drivers/mtd/spi-nor/winbond.c -@@ -98,6 +98,10 @@ static const struct flash_info winbond_p - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "w25q256jw", INFO(0xef6019, 0, 64 * 1024, 512, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, -+ { "w25q512jv", INFO(0xef4020, 0, 64 * 1024, 1024, -+ SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ | -+ SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | -+ SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) }, - { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024, - SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) }, - { "w25q512jvq", INFO(0xef4020, 0, 64 * 1024, 1024, diff --git a/target/linux/mediatek/patches-6.1/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch b/target/linux/mediatek/patches-6.1/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch index a57ee253938..8c2c80d6bfd 100644 --- a/target/linux/mediatek/patches-6.1/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch +++ b/target/linux/mediatek/patches-6.1/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch @@ -21,7 +21,7 @@ Signed-off-by: SkyLake.Huang #include #include #include -@@ -142,6 +141,8 @@ struct mtk_spi { +@@ -171,6 +170,8 @@ struct mtk_spi { struct device *dev; dma_addr_t tx_dma; dma_addr_t rx_dma; @@ -30,7 +30,7 @@ Signed-off-by: SkyLake.Huang }; static const struct mtk_spi_compatible mtk_common_compat; -@@ -187,15 +188,6 @@ static const struct mtk_spi_compatible m +@@ -216,15 +217,6 @@ static const struct mtk_spi_compatible m .no_need_unprepare = true, }; @@ -46,7 +46,7 @@ Signed-off-by: SkyLake.Huang static const struct of_device_id mtk_spi_of_match[] = { { .compatible = "mediatek,spi-ipm", .data = (void *)&mtk_ipm_compat, -@@ -323,7 +315,6 @@ static int mtk_spi_hw_init(struct spi_ma +@@ -352,7 +344,6 @@ static int mtk_spi_hw_init(struct spi_ma { u16 cpha, cpol; u32 reg_val; @@ -54,7 +54,7 @@ Signed-off-by: SkyLake.Huang struct mtk_spi *mdata = spi_master_get_devdata(master); cpha = spi->mode & SPI_CPHA ? 1 : 0; -@@ -373,7 +364,7 @@ static int mtk_spi_hw_init(struct spi_ma +@@ -402,7 +393,7 @@ static int mtk_spi_hw_init(struct spi_ma else reg_val &= ~SPI_CMD_CS_POL; @@ -63,7 +63,7 @@ Signed-off-by: SkyLake.Huang reg_val |= SPI_CMD_SAMPLE_SEL; else reg_val &= ~SPI_CMD_SAMPLE_SEL; -@@ -400,20 +391,20 @@ static int mtk_spi_hw_init(struct spi_ma +@@ -429,20 +420,20 @@ static int mtk_spi_hw_init(struct spi_ma if (mdata->dev_comp->ipm_design) { reg_val = readl(mdata->base + SPI_CMD_REG); reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK; @@ -87,7 +87,7 @@ Signed-off-by: SkyLake.Huang << SPI_CFG1_GET_TICK_DLY_OFFSET_V1); writel(reg_val, mdata->base + SPI_CFG1_REG); } -@@ -700,9 +691,6 @@ static int mtk_spi_setup(struct spi_devi +@@ -732,9 +723,6 @@ static int mtk_spi_setup(struct spi_devi { struct mtk_spi *mdata = spi_master_get_devdata(spi->master); @@ -97,9 +97,9 @@ Signed-off-by: SkyLake.Huang if (mdata->dev_comp->need_pad_sel && spi->cs_gpiod) /* CS de-asserted, gpiolib will handle inversion */ gpiod_direction_output(spi->cs_gpiod, 0); -@@ -1115,6 +1103,10 @@ static int mtk_spi_probe(struct platform +@@ -1138,6 +1126,10 @@ static int mtk_spi_probe(struct platform mdata = spi_master_get_devdata(master); - mdata->dev_comp = of_id->data; + mdata->dev_comp = device_get_match_data(dev); + /* Set device configs to default first. Calibrate it later. */ + mdata->sample_sel = 0; diff --git a/target/linux/mediatek/patches-6.1/432-drivers-spi-Add-support-for-dynamic-calibration.patch b/target/linux/mediatek/patches-6.1/432-drivers-spi-Add-support-for-dynamic-calibration.patch index 4c980e9438d..280993e5db7 100644 --- a/target/linux/mediatek/patches-6.1/432-drivers-spi-Add-support-for-dynamic-calibration.patch +++ b/target/linux/mediatek/patches-6.1/432-drivers-spi-Add-support-for-dynamic-calibration.patch @@ -11,7 +11,7 @@ Signed-off-by: SkyLake.Huang --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c -@@ -1234,6 +1234,70 @@ static int spi_transfer_wait(struct spi_ +@@ -1374,6 +1374,70 @@ static int spi_transfer_wait(struct spi_ return 0; } @@ -82,7 +82,7 @@ Signed-off-by: SkyLake.Huang static void _spi_transfer_delay_ns(u32 ns) { if (!ns) -@@ -2021,6 +2085,75 @@ void spi_flush_queue(struct spi_controll +@@ -2208,6 +2272,75 @@ void spi_flush_queue(struct spi_controll /*-------------------------------------------------------------------------*/ #if defined(CONFIG_OF) @@ -158,7 +158,7 @@ Signed-off-by: SkyLake.Huang static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi, struct device_node *nc) { -@@ -2139,6 +2272,10 @@ of_register_spi_device(struct spi_contro +@@ -2326,6 +2459,10 @@ of_register_spi_device(struct spi_contro if (rc) goto err_out; @@ -171,7 +171,7 @@ Signed-off-by: SkyLake.Huang spi->dev.of_node = nc; --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h -@@ -290,6 +290,40 @@ struct spi_driver { +@@ -298,6 +298,40 @@ struct spi_driver { struct device_driver driver; }; @@ -212,7 +212,7 @@ Signed-off-by: SkyLake.Huang static inline struct spi_driver *to_spi_driver(struct device_driver *drv) { return drv ? container_of(drv, struct spi_driver, driver) : NULL; -@@ -665,6 +699,11 @@ struct spi_controller { +@@ -682,6 +716,11 @@ struct spi_controller { void *dummy_rx; void *dummy_tx; @@ -224,7 +224,7 @@ Signed-off-by: SkyLake.Huang int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs); /* -@@ -1477,6 +1516,9 @@ spi_register_board_info(struct spi_board +@@ -1489,6 +1528,9 @@ spi_register_board_info(struct spi_board { return 0; } #endif diff --git a/target/linux/mediatek/patches-6.1/433-drivers-spi-mem-Add-spi-calibration-hook.patch b/target/linux/mediatek/patches-6.1/433-drivers-spi-mem-Add-spi-calibration-hook.patch index aaacab01312..e87d63db698 100644 --- a/target/linux/mediatek/patches-6.1/433-drivers-spi-mem-Add-spi-calibration-hook.patch +++ b/target/linux/mediatek/patches-6.1/433-drivers-spi-mem-Add-spi-calibration-hook.patch @@ -11,7 +11,7 @@ Signed-off-by: SkyLake.Huang --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c -@@ -410,6 +410,14 @@ int spi_mem_exec_op(struct spi_mem *mem, +@@ -419,6 +419,14 @@ int spi_mem_exec_op(struct spi_mem *mem, } EXPORT_SYMBOL_GPL(spi_mem_exec_op); diff --git a/target/linux/mediatek/patches-6.1/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch b/target/linux/mediatek/patches-6.1/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch index a64d6229819..ee3dc278601 100644 --- a/target/linux/mediatek/patches-6.1/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch +++ b/target/linux/mediatek/patches-6.1/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch @@ -11,7 +11,7 @@ Signed-off-by: SkyLake.Huang --- a/drivers/spi/spi-mt65xx.c +++ b/drivers/spi/spi-mt65xx.c -@@ -800,6 +800,21 @@ static irqreturn_t mtk_spi_interrupt(int +@@ -832,6 +832,21 @@ static irqreturn_t mtk_spi_interrupt(int return IRQ_HANDLED; } @@ -33,11 +33,11 @@ Signed-off-by: SkyLake.Huang static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) { -@@ -1092,6 +1107,7 @@ static int mtk_spi_probe(struct platform +@@ -1122,6 +1137,7 @@ static int mtk_spi_probe(struct platform master->setup = mtk_spi_setup; master->set_cs_timing = mtk_spi_set_hw_cs_timing; master->use_gpio_descriptors = true; + master->append_caldata = mtk_spi_append_caldata; - of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node); - if (!of_id) { + mdata = spi_master_get_devdata(master); + mdata->dev_comp = device_get_match_data(dev); diff --git a/target/linux/mediatek/patches-6.1/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch b/target/linux/mediatek/patches-6.1/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch index e2684eebb74..3991d8925a4 100644 --- a/target/linux/mediatek/patches-6.1/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch +++ b/target/linux/mediatek/patches-6.1/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch @@ -11,7 +11,7 @@ Signed-off-by: SkyLake.Huang --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c -@@ -977,6 +977,56 @@ static int spinand_manufacturer_match(st +@@ -978,6 +978,56 @@ static int spinand_manufacturer_match(st return -ENOTSUPP; } @@ -68,7 +68,7 @@ Signed-off-by: SkyLake.Huang static int spinand_id_detect(struct spinand_device *spinand) { u8 *id = spinand->id.data; -@@ -1227,6 +1277,10 @@ static int spinand_init(struct spinand_d +@@ -1228,6 +1278,10 @@ static int spinand_init(struct spinand_d if (!spinand->scratchbuf) return -ENOMEM; diff --git a/target/linux/mediatek/patches-6.1/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch b/target/linux/mediatek/patches-6.1/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch index 25a7cd38614..704b81654af 100644 --- a/target/linux/mediatek/patches-6.1/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch +++ b/target/linux/mediatek/patches-6.1/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch @@ -12,7 +12,7 @@ Signed-off-by: SkyLake.Huang --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c -@@ -1018,7 +1018,10 @@ int spinand_cal_read(void *priv, u32 *ad +@@ -1019,7 +1019,10 @@ int spinand_cal_read(void *priv, u32 *ad if (ret) return ret; @@ -26,8 +26,8 @@ Signed-off-by: SkyLake.Huang --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c -@@ -3060,6 +3060,18 @@ static void spi_nor_debugfs_init(struct - info->id_len, info->id); +@@ -2899,6 +2899,18 @@ static const struct flash_info *spi_nor_ + return NULL; } +static int spi_nor_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen) @@ -45,7 +45,7 @@ Signed-off-by: SkyLake.Huang static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor, const char *name) { -@@ -3133,6 +3145,9 @@ int spi_nor_scan(struct spi_nor *nor, co +@@ -3002,6 +3014,9 @@ int spi_nor_scan(struct spi_nor *nor, co if (!nor->bouncebuf) return -ENOMEM; diff --git a/target/linux/mediatek/patches-6.1/500-gsw-rtl8367s-mt7622-support.patch b/target/linux/mediatek/patches-6.1/500-gsw-rtl8367s-mt7622-support.patch index b8964f4e765..cdfe79ebad7 100644 --- a/target/linux/mediatek/patches-6.1/500-gsw-rtl8367s-mt7622-support.patch +++ b/target/linux/mediatek/patches-6.1/500-gsw-rtl8367s-mt7622-support.patch @@ -1,6 +1,6 @@ --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig -@@ -367,6 +367,12 @@ config ROCKCHIP_PHY +@@ -382,6 +382,12 @@ config ROCKCHIP_PHY help Currently supports the integrated Ethernet PHY. @@ -15,7 +15,7 @@ help --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile -@@ -95,6 +95,7 @@ obj-$(CONFIG_QSEMI_PHY) += qsemi.o +@@ -98,6 +98,7 @@ obj-$(CONFIG_QSEMI_PHY) += qsemi.o obj-$(CONFIG_REALTEK_PHY) += realtek.o obj-$(CONFIG_RENESAS_PHY) += uPD60620.o obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o diff --git a/target/linux/mediatek/patches-6.1/600-v5.16-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-and-MT.patch b/target/linux/mediatek/patches-6.1/600-v5.16-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-and-MT.patch deleted file mode 100644 index 6a84ff47db1..00000000000 --- a/target/linux/mediatek/patches-6.1/600-v5.16-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-and-MT.patch +++ /dev/null @@ -1,332 +0,0 @@ -From: Chuanjia Liu -Date: Mon, 23 Aug 2021 11:27:59 +0800 -Subject: [PATCH] arm64: dts: mediatek: Split PCIe node for MT2712 and MT7622 - -There are two independent PCIe controllers in MT2712 and MT7622 -platform. Each of them should contain an independent MSI domain. - -In old dts architecture, MSI domain will be inherited from the root -bridge, and all of the devices will share the same MSI domain. -Hence that, the PCIe devices will not work properly if the irq number -which required is more than 32. - -Split the PCIe node for MT2712 and MT7622 platform to comply with -the hardware design and fix MSI issue. - -Signed-off-by: Chuanjia Liu -Acked-by: Ryder Lee -Link: https://lore.kernel.org/r/20210823032800.1660-6-chuanjia.liu@mediatek.com -Signed-off-by: Matthias Brugger ---- - ---- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi -@@ -915,64 +915,67 @@ - }; - }; - -- pcie: pcie@11700000 { -+ pcie1: pcie@112ff000 { - compatible = "mediatek,mt2712-pcie"; - device_type = "pci"; -- reg = <0 0x11700000 0 0x1000>, -- <0 0x112ff000 0 0x1000>; -- reg-names = "port0", "port1"; -+ reg = <0 0x112ff000 0 0x1000>; -+ reg-names = "port1"; -+ linux,pci-domain = <1>; - #address-cells = <3>; - #size-cells = <2>; -- interrupts = , -- ; -- clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, -- <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, -- <&pericfg CLK_PERI_PCIE0>, -+ interrupts = ; -+ interrupt-names = "pcie_irq"; -+ clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, - <&pericfg CLK_PERI_PCIE1>; -- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1"; -- phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>; -- phy-names = "pcie-phy0", "pcie-phy1"; -+ clock-names = "sys_ck1", "ahb_ck1"; -+ phys = <&u3port1 PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy1"; - bus-range = <0x00 0xff>; -- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; -+ ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>; -+ status = "disabled"; - -- pcie0: pcie@0,0 { -- device_type = "pci"; -- status = "disabled"; -- reg = <0x0000 0 0 0 0>; -- #address-cells = <3>; -- #size-cells = <2>; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &pcie_intc1 0>, -+ <0 0 0 2 &pcie_intc1 1>, -+ <0 0 0 3 &pcie_intc1 2>, -+ <0 0 0 4 &pcie_intc1 3>; -+ pcie_intc1: interrupt-controller { -+ interrupt-controller; -+ #address-cells = <0>; - #interrupt-cells = <1>; -- ranges; -- interrupt-map-mask = <0 0 0 7>; -- interrupt-map = <0 0 0 1 &pcie_intc0 0>, -- <0 0 0 2 &pcie_intc0 1>, -- <0 0 0 3 &pcie_intc0 2>, -- <0 0 0 4 &pcie_intc0 3>; -- pcie_intc0: interrupt-controller { -- interrupt-controller; -- #address-cells = <0>; -- #interrupt-cells = <1>; -- }; - }; -+ }; -+ -+ pcie0: pcie@11700000 { -+ compatible = "mediatek,mt2712-pcie"; -+ device_type = "pci"; -+ reg = <0 0x11700000 0 0x1000>; -+ reg-names = "port0"; -+ linux,pci-domain = <0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ interrupts = ; -+ interrupt-names = "pcie_irq"; -+ clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, -+ <&pericfg CLK_PERI_PCIE0>; -+ clock-names = "sys_ck0", "ahb_ck0"; -+ phys = <&u3port0 PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy0"; -+ bus-range = <0x00 0xff>; -+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; -+ status = "disabled"; - -- pcie1: pcie@1,0 { -- device_type = "pci"; -- status = "disabled"; -- reg = <0x0800 0 0 0 0>; -- #address-cells = <3>; -- #size-cells = <2>; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &pcie_intc0 0>, -+ <0 0 0 2 &pcie_intc0 1>, -+ <0 0 0 3 &pcie_intc0 2>, -+ <0 0 0 4 &pcie_intc0 3>; -+ pcie_intc0: interrupt-controller { -+ interrupt-controller; -+ #address-cells = <0>; - #interrupt-cells = <1>; -- ranges; -- interrupt-map-mask = <0 0 0 7>; -- interrupt-map = <0 0 0 1 &pcie_intc1 0>, -- <0 0 0 2 &pcie_intc1 1>, -- <0 0 0 3 &pcie_intc1 2>, -- <0 0 0 4 &pcie_intc1 3>; -- pcie_intc1: interrupt-controller { -- interrupt-controller; -- #address-cells = <0>; -- #interrupt-cells = <1>; -- }; - }; - }; - ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -302,18 +302,16 @@ - }; - }; - --&pcie { -+&pcie0 { - pinctrl-names = "default"; -- pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>; -+ pinctrl-0 = <&pcie0_pins>; - status = "okay"; -+}; - -- pcie@0,0 { -- status = "okay"; -- }; -- -- pcie@1,0 { -- status = "okay"; -- }; -+&pcie1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie1_pins>; -+ status = "okay"; - }; - - &pio { ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -232,18 +232,16 @@ - }; - }; - --&pcie { -+&pcie0 { - pinctrl-names = "default"; -- pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>; -+ pinctrl-0 = <&pcie0_pins>; - status = "okay"; -+}; - -- pcie@0,0 { -- status = "okay"; -- }; -- -- pcie@1,0 { -- status = "okay"; -- }; -+&pcie1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie1_pins>; -+ status = "okay"; - }; - - &pio { ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -809,75 +809,83 @@ - #reset-cells = <1>; - }; - -- pcie: pcie@1a140000 { -+ pciecfg: pciecfg@1a140000 { -+ compatible = "mediatek,generic-pciecfg", "syscon"; -+ reg = <0 0x1a140000 0 0x1000>; -+ }; -+ -+ pcie0: pcie@1a143000 { - compatible = "mediatek,mt7622-pcie"; - device_type = "pci"; -- reg = <0 0x1a140000 0 0x1000>, -- <0 0x1a143000 0 0x1000>, -- <0 0x1a145000 0 0x1000>; -- reg-names = "subsys", "port0", "port1"; -+ reg = <0 0x1a143000 0 0x1000>; -+ reg-names = "port0"; -+ linux,pci-domain = <0>; - #address-cells = <3>; - #size-cells = <2>; -- interrupts = , -- ; -+ interrupts = ; -+ interrupt-names = "pcie_irq"; - clocks = <&pciesys CLK_PCIE_P0_MAC_EN>, -- <&pciesys CLK_PCIE_P1_MAC_EN>, -- <&pciesys CLK_PCIE_P0_AHB_EN>, - <&pciesys CLK_PCIE_P0_AHB_EN>, - <&pciesys CLK_PCIE_P0_AUX_EN>, -- <&pciesys CLK_PCIE_P1_AUX_EN>, - <&pciesys CLK_PCIE_P0_AXI_EN>, -- <&pciesys CLK_PCIE_P1_AXI_EN>, - <&pciesys CLK_PCIE_P0_OBFF_EN>, -- <&pciesys CLK_PCIE_P1_OBFF_EN>, -- <&pciesys CLK_PCIE_P0_PIPE_EN>, -- <&pciesys CLK_PCIE_P1_PIPE_EN>; -- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1", -- "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1", -- "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1"; -+ <&pciesys CLK_PCIE_P0_PIPE_EN>; -+ clock-names = "sys_ck0", "ahb_ck0", "aux_ck0", -+ "axi_ck0", "obff_ck0", "pipe_ck0"; -+ - power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; - bus-range = <0x00 0xff>; -- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; -+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; - status = "disabled"; - -- pcie0: pcie@0,0 { -- reg = <0x0000 0 0 0 0>; -- #address-cells = <3>; -- #size-cells = <2>; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &pcie_intc0 0>, -+ <0 0 0 2 &pcie_intc0 1>, -+ <0 0 0 3 &pcie_intc0 2>, -+ <0 0 0 4 &pcie_intc0 3>; -+ pcie_intc0: interrupt-controller { -+ interrupt-controller; -+ #address-cells = <0>; - #interrupt-cells = <1>; -- ranges; -- status = "disabled"; -- -- interrupt-map-mask = <0 0 0 7>; -- interrupt-map = <0 0 0 1 &pcie_intc0 0>, -- <0 0 0 2 &pcie_intc0 1>, -- <0 0 0 3 &pcie_intc0 2>, -- <0 0 0 4 &pcie_intc0 3>; -- pcie_intc0: interrupt-controller { -- interrupt-controller; -- #address-cells = <0>; -- #interrupt-cells = <1>; -- }; - }; -+ }; - -- pcie1: pcie@1,0 { -- reg = <0x0800 0 0 0 0>; -- #address-cells = <3>; -- #size-cells = <2>; -- #interrupt-cells = <1>; -- ranges; -- status = "disabled"; -+ pcie1: pcie@1a145000 { -+ compatible = "mediatek,mt7622-pcie"; -+ device_type = "pci"; -+ reg = <0 0x1a145000 0 0x1000>; -+ reg-names = "port1"; -+ linux,pci-domain = <1>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ interrupts = ; -+ interrupt-names = "pcie_irq"; -+ clocks = <&pciesys CLK_PCIE_P1_MAC_EN>, -+ /* designer has connect RC1 with p0_ahb clock */ -+ <&pciesys CLK_PCIE_P0_AHB_EN>, -+ <&pciesys CLK_PCIE_P1_AUX_EN>, -+ <&pciesys CLK_PCIE_P1_AXI_EN>, -+ <&pciesys CLK_PCIE_P1_OBFF_EN>, -+ <&pciesys CLK_PCIE_P1_PIPE_EN>; -+ clock-names = "sys_ck1", "ahb_ck1", "aux_ck1", -+ "axi_ck1", "obff_ck1", "pipe_ck1"; -+ -+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; -+ bus-range = <0x00 0xff>; -+ ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; -+ status = "disabled"; - -- interrupt-map-mask = <0 0 0 7>; -- interrupt-map = <0 0 0 1 &pcie_intc1 0>, -- <0 0 0 2 &pcie_intc1 1>, -- <0 0 0 3 &pcie_intc1 2>, -- <0 0 0 4 &pcie_intc1 3>; -- pcie_intc1: interrupt-controller { -- interrupt-controller; -- #address-cells = <0>; -- #interrupt-cells = <1>; -- }; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &pcie_intc1 0>, -+ <0 0 0 2 &pcie_intc1 1>, -+ <0 0 0 3 &pcie_intc1 2>, -+ <0 0 0 4 &pcie_intc1 3>; -+ pcie_intc1: interrupt-controller { -+ interrupt-controller; -+ #address-cells = <0>; -+ #interrupt-cells = <1>; - }; - }; - diff --git a/target/linux/mediatek/patches-6.1/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch b/target/linux/mediatek/patches-6.1/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch index ff482272108..05a6ff0fdb0 100644 --- a/target/linux/mediatek/patches-6.1/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch +++ b/target/linux/mediatek/patches-6.1/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch @@ -20,7 +20,7 @@ Acked-by: Pali Rohár +++ b/drivers/pci/controller/pcie-mediatek.c @@ -702,6 +702,13 @@ static int mtk_pcie_startup_port_v2(stru */ - writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); + msleep(100); + /* + * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and diff --git a/target/linux/mediatek/patches-6.1/603-v5.16-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch b/target/linux/mediatek/patches-6.1/603-v5.16-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch deleted file mode 100644 index 252ef080f59..00000000000 --- a/target/linux/mediatek/patches-6.1/603-v5.16-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch +++ /dev/null @@ -1,203 +0,0 @@ -From patchwork Thu May 28 06:16:48 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Chuanjia Liu -X-Patchwork-Id: 11574797 -Return-Path: - -Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org - [172.30.200.123]) - by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 30A5E1392 - for ; - Thu, 28 May 2020 06:29:05 +0000 (UTC) -Received: from bombadil.infradead.org (bombadil.infradead.org - [198.137.202.133]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by mail.kernel.org (Postfix) with ESMTPS id 08B6320721 - for ; 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Thu, 28 May 2020 14:18:52 +0800 -From: -To: , , -Subject: [PATCH v2 4/4] ARM: dts: mediatek: Update mt7629 PCIe node -Date: Thu, 28 May 2020 14:16:48 +0800 -Message-ID: <20200528061648.32078-5-chuanjia.liu@mediatek.com> -X-Mailer: git-send-email 2.18.0 -In-Reply-To: <20200528061648.32078-1-chuanjia.liu@mediatek.com> -References: <20200528061648.32078-1-chuanjia.liu@mediatek.com> -MIME-Version: 1.0 -X-MTK: N -X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 -X-CRM114-CacheID: sfid-20200527_232901_719172_E5A99C62 -X-CRM114-Status: GOOD ( 11.61 ) -X-Spam-Score: -0.2 (/) -X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: - Content analysis details: (-0.2 points) - pts rule name description - ---- ---------------------- - -------------------------------------------------- - -0.0 SPF_PASS SPF: sender matches SPF record - 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record - 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 - encoding - -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from - author's domain - 0.1 DKIM_SIGNED Message has a DKIM or DK signature, - not necessarily - valid - -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature - -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from - envelope-from domain - 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay - lines -X-BeenThere: linux-mediatek@lists.infradead.org -X-Mailman-Version: 2.1.29 -Precedence: list -List-Id: -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Cc: devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com, - srv_heupstream@mediatek.com, "chuanjia.liu" , - linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, - jianjun.wang@mediatek.com, linux-mediatek@lists.infradead.org, - yong.wu@mediatek.com, bhelgaas@google.com, - linux-arm-kernel@lists.infradead.org, amurray@thegoodpenguin.co.uk -Sender: "Linux-mediatek" -Errors-To: - linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org - -From: "chuanjia.liu" - -Remove unused property and add pciecfg node. - -Signed-off-by: chuanjia.liu ---- - arch/arm/boot/dts/mt7629-rfb.dts | 3 ++- - arch/arm/boot/dts/mt7629.dtsi | 23 +++++++++++++---------- - 2 files changed, 15 insertions(+), 11 deletions(-) - ---- a/arch/arm/boot/dts/mt7629-rfb.dts -+++ b/arch/arm/boot/dts/mt7629-rfb.dts -@@ -149,9 +149,10 @@ - }; - }; - --&pcie { -+&pcie1 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pins>; -+ status = "okay"; - }; - - &pciephy1 { ---- a/arch/arm/boot/dts/mt7629.dtsi -+++ b/arch/arm/boot/dts/mt7629.dtsi -@@ -382,16 +382,21 @@ - #reset-cells = <1>; - }; - -- pcie: pcie@1a140000 { -+ pciecfg: pciecfg@1a140000 { -+ compatible = "mediatek,mt7629-pciecfg", "syscon"; -+ reg = <0x1a140000 0x1000>; -+ }; -+ -+ pcie1: pcie@1a145000 { - compatible = "mediatek,mt7629-pcie"; - device_type = "pci"; -- reg = <0x1a140000 0x1000>, -- <0x1a145000 0x1000>; -- reg-names = "subsys","port1"; -+ reg = <0x1a145000 0x1000>; -+ reg-names = "port1"; -+ mediatek,pcie-cfg = <&pciecfg>; - #address-cells = <3>; - #size-cells = <2>; -- interrupts = , -- ; -+ interrupts = ; -+ interrupt-names = "pcie_irq"; - clocks = <&pciesys CLK_PCIE_P1_MAC_EN>, - <&pciesys CLK_PCIE_P0_AHB_EN>, - <&pciesys CLK_PCIE_P1_AUX_EN>, -@@ -412,21 +417,19 @@ - power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>; -+ status = "disabled"; - -- pcie1: pcie@1,0 { -- device_type = "pci"; -+ slot1: pcie@1,0 { - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; -- num-lanes = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc1 0>, - <0 0 0 2 &pcie_intc1 1>, - <0 0 0 3 &pcie_intc1 2>, - <0 0 0 4 &pcie_intc1 3>; -- - pcie_intc1: interrupt-controller { - interrupt-controller; - #address-cells = <0>; diff --git a/target/linux/mediatek/patches-6.1/610-pcie-mediatek-fix-clearing-interrupt-status.patch b/target/linux/mediatek/patches-6.1/610-pcie-mediatek-fix-clearing-interrupt-status.patch index 2bebfddf5c6..2a49b2275c4 100644 --- a/target/linux/mediatek/patches-6.1/610-pcie-mediatek-fix-clearing-interrupt-status.patch +++ b/target/linux/mediatek/patches-6.1/610-pcie-mediatek-fix-clearing-interrupt-status.patch @@ -10,7 +10,7 @@ Signed-off-by: Felix Fietkau --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c -@@ -614,9 +614,9 @@ static void mtk_pcie_intr_handler(struct +@@ -607,9 +607,9 @@ static void mtk_pcie_intr_handler(struct if (status & INTX_MASK) { for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) { /* Clear the INTx */ diff --git a/target/linux/mediatek/patches-6.1/702-v5.17-net-mdio-add-helpers-to-extract-clause-45-regad-and-.patch b/target/linux/mediatek/patches-6.1/702-v5.17-net-mdio-add-helpers-to-extract-clause-45-regad-and-.patch deleted file mode 100644 index da33aaa72f3..00000000000 --- a/target/linux/mediatek/patches-6.1/702-v5.17-net-mdio-add-helpers-to-extract-clause-45-regad-and-.patch +++ /dev/null @@ -1,53 +0,0 @@ -From c6af53f038aa32cec12e8a305ba07c7ef168f1b0 Mon Sep 17 00:00:00 2001 -From: "Russell King (Oracle)" -Date: Tue, 4 Jan 2022 12:07:00 +0000 -Subject: [PATCH 2/3] net: mdio: add helpers to extract clause 45 regad and - devad fields - -Add a couple of helpers and definitions to extract the clause 45 regad -and devad fields from the regnum passed into MDIO drivers. - -Tested-by: Daniel Golle -Reviewed-by: Andrew Lunn -Signed-off-by: Russell King (Oracle) -Signed-off-by: Daniel Golle -Signed-off-by: David S. Miller ---- - include/linux/mdio.h | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - ---- a/include/linux/mdio.h -+++ b/include/linux/mdio.h -@@ -7,6 +7,7 @@ - #define __LINUX_MDIO_H__ - - #include -+#include - #include - - /* Or MII_ADDR_C45 into regnum for read/write on mii_bus to enable the 21 bit -@@ -14,6 +15,7 @@ - */ - #define MII_ADDR_C45 (1<<30) - #define MII_DEVADDR_C45_SHIFT 16 -+#define MII_DEVADDR_C45_MASK GENMASK(20, 16) - #define MII_REGADDR_C45_MASK GENMASK(15, 0) - - struct gpio_desc; -@@ -355,6 +357,16 @@ static inline u32 mdiobus_c45_addr(int d - return MII_ADDR_C45 | devad << MII_DEVADDR_C45_SHIFT | regnum; - } - -+static inline u16 mdiobus_c45_regad(u32 regnum) -+{ -+ return FIELD_GET(MII_REGADDR_C45_MASK, regnum); -+} -+ -+static inline u16 mdiobus_c45_devad(u32 regnum) -+{ -+ return FIELD_GET(MII_DEVADDR_C45_MASK, regnum); -+} -+ - static inline int __mdiobus_c45_read(struct mii_bus *bus, int prtad, int devad, - u16 regnum) - { diff --git a/target/linux/mediatek/patches-6.1/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch b/target/linux/mediatek/patches-6.1/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch deleted file mode 100644 index 84718d300b5..00000000000 --- a/target/linux/mediatek/patches-6.1/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch +++ /dev/null @@ -1,128 +0,0 @@ -From e2e7f6e29c99a1c6afc0e0aa4b9ea80302d28720 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Tue, 4 Jan 2022 12:07:46 +0000 -Subject: [PATCH 3/3] net: ethernet: mtk_eth_soc: implement Clause 45 MDIO - access - -Implement read and write access to IEEE 802.3 Clause 45 Ethernet -phy registers while making use of new mdiobus_c45_regad and -mdiobus_c45_devad helpers. - -Tested on the Ubiquiti UniFi 6 LR access point featuring -MediaTek MT7622BV WiSoC with Aquantia AQR112C. - -Signed-off-by: Daniel Golle -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 70 +++++++++++++++++---- - drivers/net/ethernet/mediatek/mtk_eth_soc.h | 3 + - 2 files changed, 60 insertions(+), 13 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -323,13 +323,35 @@ static int _mtk_mdio_write(struct mtk_et - if (ret < 0) - return ret; - -- mtk_w32(eth, PHY_IAC_ACCESS | -- PHY_IAC_START_C22 | -- PHY_IAC_CMD_WRITE | -- PHY_IAC_REG(phy_reg) | -- PHY_IAC_ADDR(phy_addr) | -- PHY_IAC_DATA(write_data), -- MTK_PHY_IAC); -+ if (phy_reg & MII_ADDR_C45) { -+ mtk_w32(eth, PHY_IAC_ACCESS | -+ PHY_IAC_START_C45 | -+ PHY_IAC_CMD_C45_ADDR | -+ PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | -+ PHY_IAC_ADDR(phy_addr) | -+ PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)), -+ MTK_PHY_IAC); -+ -+ ret = mtk_mdio_busy_wait(eth); -+ if (ret < 0) -+ return ret; -+ -+ mtk_w32(eth, PHY_IAC_ACCESS | -+ PHY_IAC_START_C45 | -+ PHY_IAC_CMD_WRITE | -+ PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | -+ PHY_IAC_ADDR(phy_addr) | -+ PHY_IAC_DATA(write_data), -+ MTK_PHY_IAC); -+ } else { -+ mtk_w32(eth, PHY_IAC_ACCESS | -+ PHY_IAC_START_C22 | -+ PHY_IAC_CMD_WRITE | -+ PHY_IAC_REG(phy_reg) | -+ PHY_IAC_ADDR(phy_addr) | -+ PHY_IAC_DATA(write_data), -+ MTK_PHY_IAC); -+ } - - ret = mtk_mdio_busy_wait(eth); - if (ret < 0) -@@ -346,12 +368,33 @@ static int _mtk_mdio_read(struct mtk_eth - if (ret < 0) - return ret; - -- mtk_w32(eth, PHY_IAC_ACCESS | -- PHY_IAC_START_C22 | -- PHY_IAC_CMD_C22_READ | -- PHY_IAC_REG(phy_reg) | -- PHY_IAC_ADDR(phy_addr), -- MTK_PHY_IAC); -+ if (phy_reg & MII_ADDR_C45) { -+ mtk_w32(eth, PHY_IAC_ACCESS | -+ PHY_IAC_START_C45 | -+ PHY_IAC_CMD_C45_ADDR | -+ PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | -+ PHY_IAC_ADDR(phy_addr) | -+ PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)), -+ MTK_PHY_IAC); -+ -+ ret = mtk_mdio_busy_wait(eth); -+ if (ret < 0) -+ return ret; -+ -+ mtk_w32(eth, PHY_IAC_ACCESS | -+ PHY_IAC_START_C45 | -+ PHY_IAC_CMD_C45_READ | -+ PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | -+ PHY_IAC_ADDR(phy_addr), -+ MTK_PHY_IAC); -+ } else { -+ mtk_w32(eth, PHY_IAC_ACCESS | -+ PHY_IAC_START_C22 | -+ PHY_IAC_CMD_C22_READ | -+ PHY_IAC_REG(phy_reg) | -+ PHY_IAC_ADDR(phy_addr), -+ MTK_PHY_IAC); -+ } - - ret = mtk_mdio_busy_wait(eth); - if (ret < 0) -@@ -1013,6 +1056,7 @@ static int mtk_mdio_init(struct mtk_eth - eth->mii_bus->name = "mdio"; - eth->mii_bus->read = mtk_mdio_read; - eth->mii_bus->write = mtk_mdio_write; -+ eth->mii_bus->probe_capabilities = MDIOBUS_C22_C45; - eth->mii_bus->priv = eth; - eth->mii_bus->parent = eth->dev; - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -382,9 +382,12 @@ - #define PHY_IAC_ADDR_MASK GENMASK(24, 20) - #define PHY_IAC_ADDR(x) FIELD_PREP(PHY_IAC_ADDR_MASK, (x)) - #define PHY_IAC_CMD_MASK GENMASK(19, 18) -+#define PHY_IAC_CMD_C45_ADDR FIELD_PREP(PHY_IAC_CMD_MASK, 0) - #define PHY_IAC_CMD_WRITE FIELD_PREP(PHY_IAC_CMD_MASK, 1) - #define PHY_IAC_CMD_C22_READ FIELD_PREP(PHY_IAC_CMD_MASK, 2) -+#define PHY_IAC_CMD_C45_READ FIELD_PREP(PHY_IAC_CMD_MASK, 3) - #define PHY_IAC_START_MASK GENMASK(17, 16) -+#define PHY_IAC_START_C45 FIELD_PREP(PHY_IAC_START_MASK, 0) - #define PHY_IAC_START_C22 FIELD_PREP(PHY_IAC_START_MASK, 1) - #define PHY_IAC_DATA_MASK GENMASK(15, 0) - #define PHY_IAC_DATA(x) FIELD_PREP(PHY_IAC_DATA_MASK, (x)) diff --git a/target/linux/mediatek/patches-6.1/730-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch b/target/linux/mediatek/patches-6.1/730-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch deleted file mode 100644 index 6af9e843357..00000000000 --- a/target/linux/mediatek/patches-6.1/730-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch +++ /dev/null @@ -1,82 +0,0 @@ -From 60ed9eb9605656c19ca402b7bd3f47552e901601 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Mon, 13 Feb 2023 02:33:14 +0000 -Subject: [PATCH] net: phy: add driver for MediaTek SoC built-in GE PHYs - -Some of MediaTek's Filogic SoCs come with built-in gigabit Ethernet -PHYs which require calibration data from the SoC's efuse. -Despite the similar design the driver doesn't share any code with the -existing mediatek-ge.c, so add support for these PHYs by introducing a -new driver for only MediaTek's ARM64 SoCs. - -Signed-off-by: Daniel Golle ---- - MAINTAINERS | 9 + - drivers/net/phy/Kconfig | 12 + - drivers/net/phy/Makefile | 1 + - drivers/net/phy/mediatek-ge-soc.c | 1263 +++++++++++++++++++++++++++++ - drivers/net/phy/mediatek-ge.c | 3 +- - 5 files changed, 1287 insertions(+), 1 deletion(-) - create mode 100644 drivers/net/phy/mediatek-ge-soc.c - ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -11797,6 +11797,15 @@ S: Maintained - F: drivers/net/pcs/pcs-mtk-lynxi.c - F: include/linux/pcs/pcs-mtk-lynxi.h - -+MEDIATEK ETHERNET PHY DRIVERS -+M: Daniel Golle -+M: Qingfang Deng -+M: SkyLake Huang -+L: netdev@vger.kernel.org -+S: Maintained -+F: drivers/net/phy/mediatek-ge-soc.c -+F: drivers/net/phy/mediatek-ge.c -+ - MEDIATEK I2C CONTROLLER DRIVER - M: Qii Wang - L: linux-i2c@vger.kernel.org ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -293,6 +293,18 @@ config MEDIATEK_GE_PHY - help - Supports the MediaTek Gigabit Ethernet PHYs. - -+config MEDIATEK_GE_SOC_PHY -+ tristate "MediaTek SoC Ethernet PHYs" -+ depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST -+ select NVMEM_MTK_EFUSE -+ help -+ Supports MediaTek SoC built-in Gigabit Ethernet PHYs. -+ -+ Include support for built-in Ethernet PHYs which are present in -+ the MT7981 and MT7988 SoCs. These PHYs need calibration data -+ present in the SoCs efuse and will dynamically calibrate VCM -+ (common-mode voltage) during startup. -+ - config MICREL_PHY - tristate "Micrel PHYs" - help ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -81,6 +81,7 @@ obj-$(CONFIG_MARVELL_PHY) += marvell.o - obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o - obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o - obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o -+obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mediatek-ge-soc.o - obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o - obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o - obj-$(CONFIG_MICREL_PHY) += micrel.o ---- a/drivers/net/phy/mediatek-ge.c -+++ b/drivers/net/phy/mediatek-ge.c -@@ -136,7 +136,8 @@ static struct phy_driver mtk_gephy_drive - module_phy_driver(mtk_gephy_driver); - - static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = { -- { PHY_ID_MATCH_VENDOR(0x03a29400) }, -+ { PHY_ID_MATCH_EXACT(0x03a29441) }, -+ { PHY_ID_MATCH_EXACT(0x03a29412) }, - { } - }; - diff --git a/target/linux/mediatek/patches-6.1/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch b/target/linux/mediatek/patches-6.1/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch new file mode 100644 index 00000000000..cba76ad77c3 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch @@ -0,0 +1,1204 @@ +From 98c485eaf509bc0e2a85f9b58d17cd501f274c4e Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Sun, 11 Jun 2023 00:48:10 +0100 +Subject: [PATCH] net: phy: add driver for MediaTek SoC built-in GE PHYs + +Some of MediaTek's Filogic SoCs come with built-in gigabit Ethernet +PHYs which require calibration data from the SoC's efuse. +Despite the similar design the driver doesn't share any code with the +existing mediatek-ge.c. +Add support for such PHYs by introducing a new driver with basic +support for MediaTek SoCs MT7981 and MT7988 built-in 1GE PHYs. + +Signed-off-by: Daniel Golle +Reviewed-by: Andrew Lunn +Signed-off-by: David S. Miller +--- + MAINTAINERS | 9 + + drivers/net/phy/Kconfig | 12 + + drivers/net/phy/Makefile | 1 + + drivers/net/phy/mediatek-ge-soc.c | 1116 +++++++++++++++++++++++++++++ + drivers/net/phy/mediatek-ge.c | 3 +- + 5 files changed, 1140 insertions(+), 1 deletion(-) + create mode 100644 drivers/net/phy/mediatek-ge-soc.c + +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -12934,6 +12934,15 @@ S: Maintained + F: drivers/net/pcs/pcs-mtk-lynxi.c + F: include/linux/pcs/pcs-mtk-lynxi.h + ++MEDIATEK ETHERNET PHY DRIVERS ++M: Daniel Golle ++M: Qingfang Deng ++M: SkyLake Huang ++L: netdev@vger.kernel.org ++S: Maintained ++F: drivers/net/phy/mediatek-ge-soc.c ++F: drivers/net/phy/mediatek-ge.c ++ + MEDIATEK I2C CONTROLLER DRIVER + M: Qii Wang + L: linux-i2c@vger.kernel.org +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -307,6 +307,18 @@ config MEDIATEK_GE_PHY + help + Supports the MediaTek Gigabit Ethernet PHYs. + ++config MEDIATEK_GE_SOC_PHY ++ tristate "MediaTek SoC Ethernet PHYs" ++ depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST ++ select NVMEM_MTK_EFUSE ++ help ++ Supports MediaTek SoC built-in Gigabit Ethernet PHYs. ++ ++ Include support for built-in Ethernet PHYs which are present in ++ the MT7981 and MT7988 SoCs. These PHYs need calibration data ++ present in the SoCs efuse and will dynamically calibrate VCM ++ (common-mode voltage) during startup. ++ + config MICREL_PHY + tristate "Micrel PHYs" + depends on PTP_1588_CLOCK_OPTIONAL +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -84,6 +84,7 @@ obj-$(CONFIG_MARVELL_PHY) += marvell.o + obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o + obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o + obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o ++obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mediatek-ge-soc.o + obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o + obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o + obj-$(CONFIG_MICREL_PHY) += micrel.o +--- /dev/null ++++ b/drivers/net/phy/mediatek-ge-soc.c +@@ -0,0 +1,1116 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define MTK_GPHY_ID_MT7981 0x03a29461 ++#define MTK_GPHY_ID_MT7988 0x03a29481 ++ ++#define MTK_EXT_PAGE_ACCESS 0x1f ++#define MTK_PHY_PAGE_STANDARD 0x0000 ++#define MTK_PHY_PAGE_EXTENDED_3 0x0003 ++ ++#define MTK_PHY_LPI_REG_14 0x14 ++#define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0) ++ ++#define MTK_PHY_LPI_REG_1c 0x1c ++#define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8) ++ ++#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 ++#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 ++ ++#define ANALOG_INTERNAL_OPERATION_MAX_US 20 ++#define TXRESERVE_MIN 0 ++#define TXRESERVE_MAX 7 ++ ++#define MTK_PHY_ANARG_RG 0x10 ++#define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8) ++ ++/* Registers on MDIO_MMD_VEND1 */ ++#define MTK_PHY_TXVLD_DA_RG 0x12 ++#define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10) ++#define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0) ++ ++#define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16 ++#define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10) ++#define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0) ++ ++#define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17 ++#define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8) ++#define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0) ++ ++#define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18 ++#define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8) ++#define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0) ++ ++#define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19 ++#define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8) ++#define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0) ++ ++#define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20 ++#define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8) ++#define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0) ++ ++#define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21 ++#define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8) ++#define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0) ++ ++#define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22 ++#define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8) ++#define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0) ++ ++#define MTK_PHY_RXADC_CTRL_RG7 0xc6 ++#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8) ++ ++#define MTK_PHY_RXADC_CTRL_RG9 0xc8 ++#define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12) ++#define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8) ++#define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4) ++#define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0) ++ ++#define MTK_PHY_LDO_OUTPUT_V 0xd7 ++ ++#define MTK_PHY_RG_ANA_CAL_RG0 0xdb ++#define MTK_PHY_RG_CAL_CKINV BIT(12) ++#define MTK_PHY_RG_ANA_CALEN BIT(8) ++#define MTK_PHY_RG_ZCALEN_A BIT(0) ++ ++#define MTK_PHY_RG_ANA_CAL_RG1 0xdc ++#define MTK_PHY_RG_ZCALEN_B BIT(12) ++#define MTK_PHY_RG_ZCALEN_C BIT(8) ++#define MTK_PHY_RG_ZCALEN_D BIT(4) ++#define MTK_PHY_RG_TXVOS_CALEN BIT(0) ++ ++#define MTK_PHY_RG_ANA_CAL_RG5 0xe0 ++#define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8) ++ ++#define MTK_PHY_RG_TX_FILTER 0xfe ++ ++#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120 ++#define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8) ++#define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0) ++ ++#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122 ++#define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0) ++ ++#define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144 ++#define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5) ++ ++#define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172 ++#define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8) ++#define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0) ++ ++#define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173 ++#define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8) ++#define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0) ++ ++#define MTK_PHY_RG_AD_CAL_COMP 0x17a ++#define MTK_PHY_AD_CAL_COMP_OUT_SHIFT (8) ++ ++#define MTK_PHY_RG_AD_CAL_CLK 0x17b ++#define MTK_PHY_DA_CAL_CLK BIT(0) ++ ++#define MTK_PHY_RG_AD_CALIN 0x17c ++#define MTK_PHY_DA_CALIN_FLAG BIT(0) ++ ++#define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d ++#define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0) ++ ++#define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e ++#define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0) ++ ++#define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f ++#define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0) ++ ++#define MTK_PHY_RG_DASN_DAC_IN0_D 0x180 ++#define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0) ++ ++#define MTK_PHY_RG_DASN_DAC_IN1_A 0x181 ++#define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0) ++ ++#define MTK_PHY_RG_DASN_DAC_IN1_B 0x182 ++#define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0) ++ ++#define MTK_PHY_RG_DASN_DAC_IN1_C 0x183 ++#define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0) ++ ++#define MTK_PHY_RG_DASN_DAC_IN1_D 0x184 ++#define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0) ++ ++#define MTK_PHY_RG_DEV1E_REG19b 0x19b ++#define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8) ++ ++#define MTK_PHY_RG_LP_IIR2_K1_L 0x22a ++#define MTK_PHY_RG_LP_IIR2_K1_U 0x22b ++#define MTK_PHY_RG_LP_IIR2_K2_L 0x22c ++#define MTK_PHY_RG_LP_IIR2_K2_U 0x22d ++#define MTK_PHY_RG_LP_IIR2_K3_L 0x22e ++#define MTK_PHY_RG_LP_IIR2_K3_U 0x22f ++#define MTK_PHY_RG_LP_IIR2_K4_L 0x230 ++#define MTK_PHY_RG_LP_IIR2_K4_U 0x231 ++#define MTK_PHY_RG_LP_IIR2_K5_L 0x232 ++#define MTK_PHY_RG_LP_IIR2_K5_U 0x233 ++ ++#define MTK_PHY_RG_DEV1E_REG234 0x234 ++#define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0) ++#define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4) ++#define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12) ++ ++#define MTK_PHY_RG_LPF_CNT_VAL 0x235 ++ ++#define MTK_PHY_RG_DEV1E_REG238 0x238 ++#define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0) ++#define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12) ++ ++#define MTK_PHY_RG_DEV1E_REG239 0x239 ++#define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0) ++#define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12) ++ ++#define MTK_PHY_RG_DEV1E_REG27C 0x27c ++#define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8) ++#define MTK_PHY_RG_DEV1E_REG27D 0x27d ++#define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0) ++ ++#define MTK_PHY_RG_DEV1E_REG2C7 0x2c7 ++#define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0) ++#define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8) ++ ++#define MTK_PHY_RG_DEV1E_REG2D1 0x2d1 ++#define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0) ++#define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8) ++#define MTK_PHY_LPI_TR_READY BIT(9) ++#define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10) ++ ++#define MTK_PHY_RG_DEV1E_REG323 0x323 ++#define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0) ++#define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4) ++ ++#define MTK_PHY_RG_DEV1E_REG324 0x324 ++#define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0) ++#define MTK_PHY_SMI_DET_MAX_EN BIT(8) ++ ++#define MTK_PHY_RG_DEV1E_REG326 0x326 ++#define MTK_PHY_LPI_MODE_SD_ON BIT(0) ++#define MTK_PHY_RESET_RANDUPD_CNT BIT(1) ++#define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2) ++#define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4) ++#define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5) ++ ++#define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502 ++#define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503 ++ ++#define MTK_PHY_DA_TX_R50_PAIR_A 0x53d ++#define MTK_PHY_DA_TX_R50_PAIR_B 0x53e ++#define MTK_PHY_DA_TX_R50_PAIR_C 0x53f ++#define MTK_PHY_DA_TX_R50_PAIR_D 0x540 ++ ++#define MTK_PHY_RG_BG_RASEL 0x115 ++#define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0) ++ ++/* These macro privides efuse parsing for internal phy. */ ++#define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0)) ++#define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0)) ++#define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0)) ++#define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0)) ++#define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0)) ++ ++#define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0)) ++#define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0)) ++#define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0)) ++#define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0)) ++#define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0)) ++ ++#define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0)) ++#define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0)) ++ ++#define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0)) ++#define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0)) ++ ++enum { ++ NO_PAIR, ++ PAIR_A, ++ PAIR_B, ++ PAIR_C, ++ PAIR_D, ++}; ++ ++enum { ++ GPHY_PORT0, ++ GPHY_PORT1, ++ GPHY_PORT2, ++ GPHY_PORT3, ++}; ++ ++enum calibration_mode { ++ EFUSE_K, ++ SW_K ++}; ++ ++enum CAL_ITEM { ++ REXT, ++ TX_OFFSET, ++ TX_AMP, ++ TX_R50, ++ TX_VCM ++}; ++ ++enum CAL_MODE { ++ EFUSE_M, ++ SW_M ++}; ++ ++static int mtk_socphy_read_page(struct phy_device *phydev) ++{ ++ return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); ++} ++ ++static int mtk_socphy_write_page(struct phy_device *phydev, int page) ++{ ++ return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); ++} ++ ++/* One calibration cycle consists of: ++ * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high ++ * until AD_CAL_COMP is ready to output calibration result. ++ * 2.Wait until DA_CAL_CLK is available. ++ * 3.Fetch AD_CAL_COMP_OUT. ++ */ ++static int cal_cycle(struct phy_device *phydev, int devad, ++ u32 regnum, u16 mask, u16 cal_val) ++{ ++ int reg_val; ++ int ret; ++ ++ phy_modify_mmd(phydev, devad, regnum, ++ mask, cal_val); ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, ++ MTK_PHY_DA_CALIN_FLAG); ++ ++ ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_AD_CAL_CLK, reg_val, ++ reg_val & MTK_PHY_DA_CAL_CLK, 500, ++ ANALOG_INTERNAL_OPERATION_MAX_US, false); ++ if (ret) { ++ phydev_err(phydev, "Calibration cycle timeout\n"); ++ return ret; ++ } ++ ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, ++ MTK_PHY_DA_CALIN_FLAG); ++ ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >> ++ MTK_PHY_AD_CAL_COMP_OUT_SHIFT; ++ phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); ++ ++ return ret; ++} ++ ++static int rext_fill_result(struct phy_device *phydev, u16 *buf) ++{ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, ++ MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL, ++ MTK_PHY_RG_BG_RASEL_MASK, buf[1]); ++ ++ return 0; ++} ++ ++static int rext_cal_efuse(struct phy_device *phydev, u32 *buf) ++{ ++ u16 rext_cal_val[2]; ++ ++ rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]); ++ rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]); ++ rext_fill_result(phydev, rext_cal_val); ++ ++ return 0; ++} ++ ++static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf) ++{ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, ++ MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, ++ MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, ++ MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, ++ MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]); ++ ++ return 0; ++} ++ ++static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf) ++{ ++ u16 tx_offset_cal_val[4]; ++ ++ tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]); ++ tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]); ++ tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]); ++ tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]); ++ ++ tx_offset_fill_result(phydev, tx_offset_cal_val); ++ ++ return 0; ++} ++ ++static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf) ++{ ++ int i; ++ int bias[16] = {}; ++ const int vals_9461[16] = { 7, 1, 4, 7, ++ 7, 1, 4, 7, ++ 7, 1, 4, 7, ++ 7, 1, 4, 7 }; ++ const int vals_9481[16] = { 10, 6, 6, 10, ++ 10, 6, 6, 10, ++ 10, 6, 6, 10, ++ 10, 6, 6, 10 }; ++ switch (phydev->drv->phy_id) { ++ case MTK_GPHY_ID_MT7981: ++ /* We add some calibration to efuse values ++ * due to board level influence. ++ * GBE: +7, TBT: +1, HBT: +4, TST: +7 ++ */ ++ memcpy(bias, (const void *)vals_9461, sizeof(bias)); ++ break; ++ case MTK_GPHY_ID_MT7988: ++ memcpy(bias, (const void *)vals_9481, sizeof(bias)); ++ break; ++ } ++ ++ /* Prevent overflow */ ++ for (i = 0; i < 12; i++) { ++ if (buf[i >> 2] + bias[i] > 63) { ++ buf[i >> 2] = 63; ++ bias[i] = 0; ++ } ++ } ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, ++ MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, ++ MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, ++ MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, ++ MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, ++ MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, (buf[1] + bias[4]) << 8); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, ++ MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, buf[1] + bias[5]); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, ++ MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, ++ MTK_PHY_DA_TX_I2MPB_B_TST_MASK, buf[1] + bias[7]); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, ++ MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, (buf[2] + bias[8]) << 8); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, ++ MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, buf[2] + bias[9]); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, ++ MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, (buf[2] + bias[10]) << 8); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, ++ MTK_PHY_DA_TX_I2MPB_C_TST_MASK, buf[2] + bias[11]); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, ++ MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, ++ MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, buf[3] + bias[13]); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, ++ MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, (buf[3] + bias[14]) << 8); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, ++ MTK_PHY_DA_TX_I2MPB_D_TST_MASK, buf[3] + bias[15]); ++ ++ return 0; ++} ++ ++static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf) ++{ ++ u16 tx_amp_cal_val[4]; ++ ++ tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]); ++ tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]); ++ tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]); ++ tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]); ++ tx_amp_fill_result(phydev, tx_amp_cal_val); ++ ++ return 0; ++} ++ ++static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val, ++ u8 txg_calen_x) ++{ ++ int bias = 0; ++ u16 reg, val; ++ ++ if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988) ++ bias = -2; ++ ++ val = clamp_val(bias + tx_r50_cal_val, 0, 63); ++ ++ switch (txg_calen_x) { ++ case PAIR_A: ++ reg = MTK_PHY_DA_TX_R50_PAIR_A; ++ break; ++ case PAIR_B: ++ reg = MTK_PHY_DA_TX_R50_PAIR_B; ++ break; ++ case PAIR_C: ++ reg = MTK_PHY_DA_TX_R50_PAIR_C; ++ break; ++ case PAIR_D: ++ reg = MTK_PHY_DA_TX_R50_PAIR_D; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8); ++ ++ return 0; ++} ++ ++static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf, ++ u8 txg_calen_x) ++{ ++ u16 tx_r50_cal_val; ++ ++ switch (txg_calen_x) { ++ case PAIR_A: ++ tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]); ++ break; ++ case PAIR_B: ++ tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]); ++ break; ++ case PAIR_C: ++ tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]); ++ break; ++ case PAIR_D: ++ tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]); ++ break; ++ default: ++ return -EINVAL; ++ } ++ tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x); ++ ++ return 0; ++} ++ ++static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x) ++{ ++ u8 lower_idx, upper_idx, txreserve_val; ++ u8 lower_ret, upper_ret; ++ int ret; ++ ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, ++ MTK_PHY_RG_ANA_CALEN); ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, ++ MTK_PHY_RG_CAL_CKINV); ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, ++ MTK_PHY_RG_TXVOS_CALEN); ++ ++ switch (rg_txreserve_x) { ++ case PAIR_A: ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DASN_DAC_IN0_A, ++ MTK_PHY_DASN_DAC_IN0_A_MASK); ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DASN_DAC_IN1_A, ++ MTK_PHY_DASN_DAC_IN1_A_MASK); ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_ANA_CAL_RG0, ++ MTK_PHY_RG_ZCALEN_A); ++ break; ++ case PAIR_B: ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DASN_DAC_IN0_B, ++ MTK_PHY_DASN_DAC_IN0_B_MASK); ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DASN_DAC_IN1_B, ++ MTK_PHY_DASN_DAC_IN1_B_MASK); ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_ANA_CAL_RG1, ++ MTK_PHY_RG_ZCALEN_B); ++ break; ++ case PAIR_C: ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DASN_DAC_IN0_C, ++ MTK_PHY_DASN_DAC_IN0_C_MASK); ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DASN_DAC_IN1_C, ++ MTK_PHY_DASN_DAC_IN1_C_MASK); ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_ANA_CAL_RG1, ++ MTK_PHY_RG_ZCALEN_C); ++ break; ++ case PAIR_D: ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DASN_DAC_IN0_D, ++ MTK_PHY_DASN_DAC_IN0_D_MASK); ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DASN_DAC_IN1_D, ++ MTK_PHY_DASN_DAC_IN1_D_MASK); ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_ANA_CAL_RG1, ++ MTK_PHY_RG_ZCALEN_D); ++ break; ++ default: ++ ret = -EINVAL; ++ goto restore; ++ } ++ ++ lower_idx = TXRESERVE_MIN; ++ upper_idx = TXRESERVE_MAX; ++ ++ phydev_dbg(phydev, "Start TX-VCM SW cal.\n"); ++ while ((upper_idx - lower_idx) > 1) { ++ txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2); ++ ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, ++ MTK_PHY_DA_RX_PSBN_TBT_MASK | ++ MTK_PHY_DA_RX_PSBN_HBT_MASK | ++ MTK_PHY_DA_RX_PSBN_GBE_MASK | ++ MTK_PHY_DA_RX_PSBN_LP_MASK, ++ txreserve_val << 12 | txreserve_val << 8 | ++ txreserve_val << 4 | txreserve_val); ++ if (ret == 1) { ++ upper_idx = txreserve_val; ++ upper_ret = ret; ++ } else if (ret == 0) { ++ lower_idx = txreserve_val; ++ lower_ret = ret; ++ } else { ++ goto restore; ++ } ++ } ++ ++ if (lower_idx == TXRESERVE_MIN) { ++ lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RXADC_CTRL_RG9, ++ MTK_PHY_DA_RX_PSBN_TBT_MASK | ++ MTK_PHY_DA_RX_PSBN_HBT_MASK | ++ MTK_PHY_DA_RX_PSBN_GBE_MASK | ++ MTK_PHY_DA_RX_PSBN_LP_MASK, ++ lower_idx << 12 | lower_idx << 8 | ++ lower_idx << 4 | lower_idx); ++ ret = lower_ret; ++ } else if (upper_idx == TXRESERVE_MAX) { ++ upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RXADC_CTRL_RG9, ++ MTK_PHY_DA_RX_PSBN_TBT_MASK | ++ MTK_PHY_DA_RX_PSBN_HBT_MASK | ++ MTK_PHY_DA_RX_PSBN_GBE_MASK | ++ MTK_PHY_DA_RX_PSBN_LP_MASK, ++ upper_idx << 12 | upper_idx << 8 | ++ upper_idx << 4 | upper_idx); ++ ret = upper_ret; ++ } ++ if (ret < 0) ++ goto restore; ++ ++ /* We calibrate TX-VCM in different logic. Check upper index and then ++ * lower index. If this calibration is valid, apply lower index's result. ++ */ ++ ret = upper_ret - lower_ret; ++ if (ret == 1) { ++ ret = 0; ++ /* Make sure we use upper_idx in our calibration system */ ++ cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, ++ MTK_PHY_DA_RX_PSBN_TBT_MASK | ++ MTK_PHY_DA_RX_PSBN_HBT_MASK | ++ MTK_PHY_DA_RX_PSBN_GBE_MASK | ++ MTK_PHY_DA_RX_PSBN_LP_MASK, ++ upper_idx << 12 | upper_idx << 8 | ++ upper_idx << 4 | upper_idx); ++ phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx); ++ } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 && ++ lower_ret == 1) { ++ ret = 0; ++ cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, ++ MTK_PHY_DA_RX_PSBN_TBT_MASK | ++ MTK_PHY_DA_RX_PSBN_HBT_MASK | ++ MTK_PHY_DA_RX_PSBN_GBE_MASK | ++ MTK_PHY_DA_RX_PSBN_LP_MASK, ++ lower_idx << 12 | lower_idx << 8 | ++ lower_idx << 4 | lower_idx); ++ phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n", ++ lower_idx); ++ } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 && ++ lower_ret == 0) { ++ ret = 0; ++ phydev_warn(phydev, "TX-VCM SW cal result at high margin 0x%x\n", ++ upper_idx); ++ } else { ++ ret = -EINVAL; ++ } ++ ++restore: ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, ++ MTK_PHY_RG_ANA_CALEN); ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, ++ MTK_PHY_RG_TXVOS_CALEN); ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, ++ MTK_PHY_RG_ZCALEN_A); ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, ++ MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C | ++ MTK_PHY_RG_ZCALEN_D); ++ ++ return ret; ++} ++ ++static void mt798x_phy_common_finetune(struct phy_device *phydev) ++{ ++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); ++ /* EnabRandUpdTrig = 1 */ ++ __phy_write(phydev, 0x11, 0x2f00); ++ __phy_write(phydev, 0x12, 0xe); ++ __phy_write(phydev, 0x10, 0x8fb0); ++ ++ /* NormMseLoThresh = 85 */ ++ __phy_write(phydev, 0x11, 0x55a0); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x83aa); ++ ++ /* TrFreeze = 0 */ ++ __phy_write(phydev, 0x11, 0x0); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x9686); ++ ++ /* SSTrKp1000Slv = 5 */ ++ __phy_write(phydev, 0x11, 0xbaef); ++ __phy_write(phydev, 0x12, 0x2e); ++ __phy_write(phydev, 0x10, 0x968c); ++ ++ /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2, ++ * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2 ++ */ ++ __phy_write(phydev, 0x11, 0xd10a); ++ __phy_write(phydev, 0x12, 0x34); ++ __phy_write(phydev, 0x10, 0x8f82); ++ ++ /* VcoSlicerThreshBitsHigh */ ++ __phy_write(phydev, 0x11, 0x5555); ++ __phy_write(phydev, 0x12, 0x55); ++ __phy_write(phydev, 0x10, 0x8ec0); ++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); ++ ++ /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, ++ MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK, ++ BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); ++ ++ /* rg_tr_lpf_cnt_val = 512 */ ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200); ++ ++ /* IIR2 related */ ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe); ++ ++ /* FFE peaking */ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C, ++ MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D, ++ MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e); ++ ++ /* Disable LDO pump */ ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0); ++ /* Adjust LDO output voltage */ ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222); ++} ++ ++static void mt7981_phy_finetune(struct phy_device *phydev) ++{ ++ u16 val[8] = { 0x01ce, 0x01c1, ++ 0x020f, 0x0202, ++ 0x03d0, 0x03c0, ++ 0x0013, 0x0005 }; ++ int i, k; ++ ++ /* 100M eye finetune: ++ * Keep middle level of TX MLT3 shapper as default. ++ * Only change TX MLT3 overshoot level here. ++ */ ++ for (k = 0, i = 1; i < 12; i++) { ++ if (i % 3 == 0) ++ continue; ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]); ++ } ++ ++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); ++ /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */ ++ __phy_write(phydev, 0x11, 0xc71); ++ __phy_write(phydev, 0x12, 0xc); ++ __phy_write(phydev, 0x10, 0x8fae); ++ ++ /* ResetSyncOffset = 6 */ ++ __phy_write(phydev, 0x11, 0x600); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x8fc0); ++ ++ /* VgaDecRate = 1 */ ++ __phy_write(phydev, 0x11, 0x4c2a); ++ __phy_write(phydev, 0x12, 0x3e); ++ __phy_write(phydev, 0x10, 0x8fa4); ++ ++ /* FfeUpdGainForce = 4 */ ++ __phy_write(phydev, 0x11, 0x240); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x9680); ++ ++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); ++} ++ ++static void mt7988_phy_finetune(struct phy_device *phydev) ++{ ++ u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182, ++ 0x020d, 0x0206, 0x0384, 0x03d0, ++ 0x03c6, 0x030a, 0x0011, 0x0005 }; ++ int i; ++ ++ /* Set default MLT3 shaper first */ ++ for (i = 0; i < 12; i++) ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]); ++ ++ /* TCT finetune */ ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5); ++ ++ /* Disable TX power saving */ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, ++ MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8); ++ ++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); ++ ++ /* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */ ++ __phy_write(phydev, 0x11, 0x671); ++ __phy_write(phydev, 0x12, 0xc); ++ __phy_write(phydev, 0x10, 0x8fae); ++ ++ /* ResetSyncOffset = 5 */ ++ __phy_write(phydev, 0x11, 0x500); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x8fc0); ++ ++ /* VgaDecRate is 1 at default on mt7988 */ ++ ++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); ++ ++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30); ++ /* TxClkOffset = 2 */ ++ __phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK, ++ FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2)); ++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); ++} ++ ++static void mt798x_phy_eee(struct phy_device *phydev) ++{ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120, ++ MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK | ++ MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, ++ FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) | ++ FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14)); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, ++ MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, ++ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, ++ 0xff)); ++ ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_TESTMUX_ADC_CTRL, ++ MTK_PHY_RG_TXEN_DIG_MASK); ++ ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY); ++ ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238, ++ MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK | ++ MTK_PHY_LPI_SLV_SEND_TX_EN, ++ FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120)); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239, ++ MTK_PHY_LPI_SEND_LOC_TIMER_MASK | ++ MTK_PHY_LPI_TXPCS_LOC_RCV, ++ FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117)); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7, ++ MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK, ++ FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) | ++ FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13)); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1, ++ MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, ++ FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, ++ 0x33) | ++ MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY | ++ MTK_PHY_LPI_VCO_EEE_STG0_EN); ++ ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323, ++ MTK_PHY_EEE_WAKE_MAS_INT_DC | ++ MTK_PHY_EEE_WAKE_SLV_INT_DC); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324, ++ MTK_PHY_SMI_DETCNT_MAX_MASK, ++ FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) | ++ MTK_PHY_SMI_DET_MAX_EN); ++ ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326, ++ MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT | ++ MTK_PHY_TREC_UPDATE_ENAB_CLR | ++ MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF | ++ MTK_PHY_TR_READY_SKIP_AFE_WAKEUP); ++ ++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); ++ /* Regsigdet_sel_1000 = 0 */ ++ __phy_write(phydev, 0x11, 0xb); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x9690); ++ ++ /* REG_EEE_st2TrKf1000 = 3 */ ++ __phy_write(phydev, 0x11, 0x114f); ++ __phy_write(phydev, 0x12, 0x2); ++ __phy_write(phydev, 0x10, 0x969a); ++ ++ /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */ ++ __phy_write(phydev, 0x11, 0x3028); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x969e); ++ ++ /* RegEEE_slv_wake_int_timer_tar = 8 */ ++ __phy_write(phydev, 0x11, 0x5010); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x96a0); ++ ++ /* RegEEE_trfreeze_timer2 = 586 */ ++ __phy_write(phydev, 0x11, 0x24a); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x96a8); ++ ++ /* RegEEE100Stg1_tar = 16 */ ++ __phy_write(phydev, 0x11, 0x3210); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x96b8); ++ ++ /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */ ++ __phy_write(phydev, 0x11, 0x1463); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x96ca); ++ ++ /* DfeTailEnableVgaThresh1000 = 27 */ ++ __phy_write(phydev, 0x11, 0x36); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x8f80); ++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); ++ ++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3); ++ __phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000_MASK, ++ FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c)); ++ ++ __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK, ++ FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc)); ++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, ++ MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, ++ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff)); ++} ++ ++static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item, ++ u8 start_pair, u8 end_pair) ++{ ++ u8 pair_n; ++ int ret; ++ ++ for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { ++ /* TX_OFFSET & TX_AMP have no SW calibration. */ ++ switch (cal_item) { ++ case TX_VCM: ++ ret = tx_vcm_cal_sw(phydev, pair_n); ++ break; ++ default: ++ return -EINVAL; ++ } ++ if (ret) ++ return ret; ++ } ++ return 0; ++} ++ ++static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item, ++ u8 start_pair, u8 end_pair, u32 *buf) ++{ ++ u8 pair_n; ++ int ret; ++ ++ for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { ++ /* TX_VCM has no efuse calibration. */ ++ switch (cal_item) { ++ case REXT: ++ ret = rext_cal_efuse(phydev, buf); ++ break; ++ case TX_OFFSET: ++ ret = tx_offset_cal_efuse(phydev, buf); ++ break; ++ case TX_AMP: ++ ret = tx_amp_cal_efuse(phydev, buf); ++ break; ++ case TX_R50: ++ ret = tx_r50_cal_efuse(phydev, buf, pair_n); ++ break; ++ default: ++ return -EINVAL; ++ } ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item, ++ enum CAL_MODE cal_mode, u8 start_pair, ++ u8 end_pair, u32 *buf) ++{ ++ int ret; ++ ++ switch (cal_mode) { ++ case EFUSE_M: ++ ret = cal_efuse(phydev, cal_item, start_pair, ++ end_pair, buf); ++ break; ++ case SW_M: ++ ret = cal_sw(phydev, cal_item, start_pair, end_pair); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ if (ret) { ++ phydev_err(phydev, "cal %d failed\n", cal_item); ++ return -EIO; ++ } ++ ++ return 0; ++} ++ ++static int mt798x_phy_calibration(struct phy_device *phydev) ++{ ++ int ret = 0; ++ u32 *buf; ++ size_t len; ++ struct nvmem_cell *cell; ++ ++ cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data"); ++ if (IS_ERR(cell)) { ++ if (PTR_ERR(cell) == -EPROBE_DEFER) ++ return PTR_ERR(cell); ++ return 0; ++ } ++ ++ buf = (u32 *)nvmem_cell_read(cell, &len); ++ if (IS_ERR(buf)) ++ return PTR_ERR(buf); ++ nvmem_cell_put(cell); ++ ++ if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) { ++ phydev_err(phydev, "invalid efuse data\n"); ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf); ++ if (ret) ++ goto out; ++ ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf); ++ if (ret) ++ goto out; ++ ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf); ++ if (ret) ++ goto out; ++ ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf); ++ if (ret) ++ goto out; ++ ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf); ++ if (ret) ++ goto out; ++ ++out: ++ kfree(buf); ++ return ret; ++} ++ ++static int mt798x_phy_config_init(struct phy_device *phydev) ++{ ++ switch (phydev->drv->phy_id) { ++ case MTK_GPHY_ID_MT7981: ++ mt7981_phy_finetune(phydev); ++ break; ++ case MTK_GPHY_ID_MT7988: ++ mt7988_phy_finetune(phydev); ++ break; ++ } ++ ++ mt798x_phy_common_finetune(phydev); ++ mt798x_phy_eee(phydev); ++ ++ return mt798x_phy_calibration(phydev); ++} ++ ++static struct phy_driver mtk_socphy_driver[] = { ++ { ++ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), ++ .name = "MediaTek MT7981 PHY", ++ .config_init = mt798x_phy_config_init, ++ .config_intr = genphy_no_config_intr, ++ .handle_interrupt = genphy_handle_interrupt_no_ack, ++ .probe = mt798x_phy_calibration, ++ .suspend = genphy_suspend, ++ .resume = genphy_resume, ++ .read_page = mtk_socphy_read_page, ++ .write_page = mtk_socphy_write_page, ++ }, ++ { ++ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988), ++ .name = "MediaTek MT7988 PHY", ++ .config_init = mt798x_phy_config_init, ++ .config_intr = genphy_no_config_intr, ++ .handle_interrupt = genphy_handle_interrupt_no_ack, ++ .probe = mt798x_phy_calibration, ++ .suspend = genphy_suspend, ++ .resume = genphy_resume, ++ .read_page = mtk_socphy_read_page, ++ .write_page = mtk_socphy_write_page, ++ }, ++}; ++ ++module_phy_driver(mtk_socphy_driver); ++ ++static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = { ++ { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) }, ++ { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) }, ++ { } ++}; ++ ++MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver"); ++MODULE_AUTHOR("Daniel Golle "); ++MODULE_AUTHOR("SkyLake Huang "); ++MODULE_LICENSE("GPL"); ++ ++MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl); +--- a/drivers/net/phy/mediatek-ge.c ++++ b/drivers/net/phy/mediatek-ge.c +@@ -136,7 +136,8 @@ static struct phy_driver mtk_gephy_drive + module_phy_driver(mtk_gephy_driver); + + static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = { +- { PHY_ID_MATCH_VENDOR(0x03a29400) }, ++ { PHY_ID_MATCH_EXACT(0x03a29441) }, ++ { PHY_ID_MATCH_EXACT(0x03a29412) }, + { } + }; + diff --git a/target/linux/mediatek/patches-6.1/731-net-phy-hack-mxl-gpy-disable-sgmii-an.patch b/target/linux/mediatek/patches-6.1/731-net-phy-hack-mxl-gpy-disable-sgmii-an.patch deleted file mode 100644 index 2e39ca3c26a..00000000000 --- a/target/linux/mediatek/patches-6.1/731-net-phy-hack-mxl-gpy-disable-sgmii-an.patch +++ /dev/null @@ -1,166 +0,0 @@ ---- a/drivers/net/phy/mxl-gpy.c -+++ b/drivers/net/phy/mxl-gpy.c -@@ -126,6 +126,12 @@ static int gpy_config_init(struct phy_de - if (ret < 0) - return ret; - -+ /* Disable SGMII auto-negotiation */ -+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, -+ VSPEC1_SGMII_CTRL_ANEN, 0); -+ if (ret < 0) -+ return ret; -+ - return gpy_led_write(phydev); - } - -@@ -151,65 +157,6 @@ static int gpy_probe(struct phy_device * - return 0; - } - --static bool gpy_sgmii_need_reaneg(struct phy_device *phydev) --{ -- int fw_ver, fw_type, fw_minor; -- size_t i; -- -- fw_ver = phy_read(phydev, PHY_FWV); -- if (fw_ver < 0) -- return true; -- -- fw_type = FIELD_GET(PHY_FWV_TYPE_MASK, fw_ver); -- fw_minor = FIELD_GET(PHY_FWV_MINOR_MASK, fw_ver); -- -- for (i = 0; i < ARRAY_SIZE(ver_need_sgmii_reaneg); i++) { -- if (fw_type != ver_need_sgmii_reaneg[i].type) -- continue; -- if (fw_minor < ver_need_sgmii_reaneg[i].minor) -- return true; -- break; -- } -- -- return false; --} -- --static bool gpy_2500basex_chk(struct phy_device *phydev) --{ -- int ret; -- -- ret = phy_read(phydev, PHY_MIISTAT); -- if (ret < 0) { -- phydev_err(phydev, "Error: MDIO register access failed: %d\n", -- ret); -- return false; -- } -- -- if (!(ret & PHY_MIISTAT_LS) || -- FIELD_GET(PHY_MIISTAT_SPD_MASK, ret) != PHY_MIISTAT_SPD_2500) -- return false; -- -- phydev->speed = SPEED_2500; -- phydev->interface = PHY_INTERFACE_MODE_2500BASEX; -- phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, -- VSPEC1_SGMII_CTRL_ANEN, 0); -- return true; --} -- --static bool gpy_sgmii_aneg_en(struct phy_device *phydev) --{ -- int ret; -- -- ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL); -- if (ret < 0) { -- phydev_err(phydev, "Error: MMD register access failed: %d\n", -- ret); -- return true; -- } -- -- return (ret & VSPEC1_SGMII_CTRL_ANEN) ? true : false; --} -- - static int gpy_config_aneg(struct phy_device *phydev) - { - bool changed = false; -@@ -248,53 +195,11 @@ static int gpy_config_aneg(struct phy_de - phydev->interface == PHY_INTERFACE_MODE_INTERNAL) - return 0; - -- /* No need to trigger re-ANEG if link speed is 2.5G or SGMII ANEG is -- * disabled. -- */ -- if (!gpy_sgmii_need_reaneg(phydev) || gpy_2500basex_chk(phydev) || -- !gpy_sgmii_aneg_en(phydev)) -- return 0; -- -- /* There is a design constraint in GPY2xx device where SGMII AN is -- * only triggered when there is change of speed. If, PHY link -- * partner`s speed is still same even after PHY TPI is down and up -- * again, SGMII AN is not triggered and hence no new in-band message -- * from GPY to MAC side SGMII. -- * This could cause an issue during power up, when PHY is up prior to -- * MAC. At this condition, once MAC side SGMII is up, MAC side SGMII -- * wouldn`t receive new in-band message from GPY with correct link -- * status, speed and duplex info. -- * -- * 1) If PHY is already up and TPI link status is still down (such as -- * hard reboot), TPI link status is polled for 4 seconds before -- * retriggerring SGMII AN. -- * 2) If PHY is already up and TPI link status is also up (such as soft -- * reboot), polling of TPI link status is not needed and SGMII AN is -- * immediately retriggered. -- * 3) Other conditions such as PHY is down, speed change etc, skip -- * retriggering SGMII AN. Note: in case of speed change, GPY FW will -- * initiate SGMII AN. -- */ -- -- if (phydev->state != PHY_UP) -- return 0; -- -- ret = phy_read_poll_timeout(phydev, MII_BMSR, ret, ret & BMSR_LSTATUS, -- 20000, 4000000, false); -- if (ret == -ETIMEDOUT) -- return 0; -- else if (ret < 0) -- return ret; -- -- /* Trigger SGMII AN. */ -- return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, -- VSPEC1_SGMII_CTRL_ANRS, VSPEC1_SGMII_CTRL_ANRS); -+ return 0; - } - - static void gpy_update_interface(struct phy_device *phydev) - { -- int ret; -- - /* Interface mode is fixed for USXGMII and integrated PHY */ - if (phydev->interface == PHY_INTERFACE_MODE_USXGMII || - phydev->interface == PHY_INTERFACE_MODE_INTERNAL) -@@ -306,29 +211,11 @@ static void gpy_update_interface(struct - switch (phydev->speed) { - case SPEED_2500: - phydev->interface = PHY_INTERFACE_MODE_2500BASEX; -- ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, -- VSPEC1_SGMII_CTRL_ANEN, 0); -- if (ret < 0) -- phydev_err(phydev, -- "Error: Disable of SGMII ANEG failed: %d\n", -- ret); - break; - case SPEED_1000: - case SPEED_100: - case SPEED_10: - phydev->interface = PHY_INTERFACE_MODE_SGMII; -- if (gpy_sgmii_aneg_en(phydev)) -- break; -- /* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed -- * if ANEG is disabled (in 2500-BaseX mode). -- */ -- ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, -- VSPEC1_SGMII_ANEN_ANRS, -- VSPEC1_SGMII_ANEN_ANRS); -- if (ret < 0) -- phydev_err(phydev, -- "Error: Enable of SGMII ANEG failed: %d\n", -- ret); - break; - } - } diff --git a/target/linux/mediatek/patches-6.1/731-net-phy-mediatek-ge-soc-initialize-MT7988-PHY-LEDs-d.patch b/target/linux/mediatek/patches-6.1/731-net-phy-mediatek-ge-soc-initialize-MT7988-PHY-LEDs-d.patch new file mode 100644 index 00000000000..83d0f26bf41 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/731-net-phy-mediatek-ge-soc-initialize-MT7988-PHY-LEDs-d.patch @@ -0,0 +1,213 @@ +From 5d2d78860f98eb5c03bc404eb024606878901ac8 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Tue, 13 Jun 2023 03:27:14 +0100 +Subject: [PATCH] net: phy: mediatek-ge-soc: initialize MT7988 PHY LEDs default + state + +Initialize LEDs and set sane default values. +Read boottrap register and apply LED polarities accordingly to get +uniform behavior from all LEDs on MT7988. +Requires syscon phandle 'mediatek,pio' present in parenting MDIO bus +which should point to the syscon holding the boottrap register. + +Signed-off-by: Daniel Golle +--- + drivers/net/phy/mediatek-ge-soc.c | 144 ++++++++++++++++++++++++++++-- + 1 file changed, 136 insertions(+), 8 deletions(-) + +--- a/drivers/net/phy/mediatek-ge-soc.c ++++ b/drivers/net/phy/mediatek-ge-soc.c +@@ -1,11 +1,13 @@ + // SPDX-License-Identifier: GPL-2.0+ + #include ++#include + #include + #include + #include + #include + #include + #include ++#include + + #define MTK_GPHY_ID_MT7981 0x03a29461 + #define MTK_GPHY_ID_MT7988 0x03a29481 +@@ -208,9 +210,40 @@ + #define MTK_PHY_DA_TX_R50_PAIR_C 0x53f + #define MTK_PHY_DA_TX_R50_PAIR_D 0x540 + ++/* Registers on MDIO_MMD_VEND2 */ ++#define MTK_PHY_LED0_ON_CTRL 0x24 ++#define MTK_PHY_LED1_ON_CTRL 0x26 ++#define MTK_PHY_LED_ON_MASK GENMASK(6, 0) ++#define MTK_PHY_LED_ON_LINK1000 BIT(0) ++#define MTK_PHY_LED_ON_LINK100 BIT(1) ++#define MTK_PHY_LED_ON_LINK10 BIT(2) ++#define MTK_PHY_LED_ON_LINKDOWN BIT(3) ++#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */ ++#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */ ++#define MTK_PHY_LED_FORCE_ON BIT(6) ++#define MTK_PHY_LED_POLARITY BIT(14) ++#define MTK_PHY_LED_ENABLE BIT(15) ++ ++#define MTK_PHY_LED0_BLINK_CTRL 0x25 ++#define MTK_PHY_LED1_BLINK_CTRL 0x27 ++#define MTK_PHY_LED_1000TX BIT(0) ++#define MTK_PHY_LED_1000RX BIT(1) ++#define MTK_PHY_LED_100TX BIT(2) ++#define MTK_PHY_LED_100RX BIT(3) ++#define MTK_PHY_LED_10TX BIT(4) ++#define MTK_PHY_LED_10RX BIT(5) ++#define MTK_PHY_LED_COLLISION BIT(6) ++#define MTK_PHY_LED_RX_CRC_ERR BIT(7) ++#define MTK_PHY_LED_RX_IDLE_ERR BIT(8) ++#define MTK_PHY_LED_FORCE_BLINK BIT(9) ++ + #define MTK_PHY_RG_BG_RASEL 0x115 + #define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0) + ++/* Register in boottrap syscon defining the initial state of the 4 PHY LEDs */ ++#define RG_GPIO_MISC_TPBANK0 0x6f0 ++#define RG_GPIO_MISC_TPBANK0_BOOTMODE GENMASK(11, 8) ++ + /* These macro privides efuse parsing for internal phy. */ + #define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0)) + #define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0)) +@@ -238,13 +271,6 @@ enum { + PAIR_D, + }; + +-enum { +- GPHY_PORT0, +- GPHY_PORT1, +- GPHY_PORT2, +- GPHY_PORT3, +-}; +- + enum calibration_mode { + EFUSE_K, + SW_K +@@ -263,6 +289,10 @@ enum CAL_MODE { + SW_M + }; + ++struct mtk_socphy_shared { ++ u32 boottrap; ++}; ++ + static int mtk_socphy_read_page(struct phy_device *phydev) + { + return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); +@@ -1073,6 +1103,104 @@ static int mt798x_phy_config_init(struct + return mt798x_phy_calibration(phydev); + } + ++static int mt798x_phy_setup_led(struct phy_device *phydev, bool inverted) ++{ ++ struct pinctrl *pinctrl; ++ const u16 led_on_ctrl_defaults = MTK_PHY_LED_ENABLE | ++ MTK_PHY_LED_ON_LINK1000 | ++ MTK_PHY_LED_ON_LINK100 | ++ MTK_PHY_LED_ON_LINK10; ++ const u16 led_blink_defaults = MTK_PHY_LED_1000TX | ++ MTK_PHY_LED_1000RX | ++ MTK_PHY_LED_100TX | ++ MTK_PHY_LED_100RX | ++ MTK_PHY_LED_10TX | ++ MTK_PHY_LED_10RX; ++ ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, ++ led_on_ctrl_defaults ^ ++ (inverted ? MTK_PHY_LED_POLARITY : 0)); ++ ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL, ++ led_on_ctrl_defaults); ++ ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_BLINK_CTRL, ++ led_blink_defaults); ++ ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_BLINK_CTRL, ++ led_blink_defaults); ++ ++ pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led"); ++ if (IS_ERR(pinctrl)) ++ dev_err(&phydev->mdio.bus->dev, "Failed to setup PHY LED\n"); ++ ++ return 0; ++} ++ ++static int mt7988_phy_probe_shared(struct phy_device *phydev) ++{ ++ struct device_node *np = dev_of_node(&phydev->mdio.bus->dev); ++ struct mtk_socphy_shared *priv = phydev->shared->priv; ++ struct regmap *regmap; ++ u32 reg; ++ int ret; ++ ++ /* The LED0 of the 4 PHYs in MT7988 are wired to SoC pins LED_A, LED_B, ++ * LED_C and LED_D respectively. At the same time those pins are used to ++ * bootstrap configuration of the reference clock source (LED_A), ++ * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D). ++ * In practise this is done using a LED and a resistor pulling the pin ++ * either to GND or to VIO. ++ * The detected value at boot time is accessible at run-time using the ++ * TPBANK0 register located in the gpio base of the pinctrl, in order ++ * to read it here it needs to be referenced by a phandle called ++ * 'mediatek,pio' in the MDIO bus hosting the PHY. ++ * The 4 bits in TPBANK0 are kept as package shared data and are used to ++ * set LED polarity for each of the LED0. ++ */ ++ regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,pio"); ++ if (IS_ERR(regmap)) ++ return PTR_ERR(regmap); ++ ++ ret = regmap_read(regmap, RG_GPIO_MISC_TPBANK0, ®); ++ if (ret) ++ return ret; ++ ++ priv->boottrap = FIELD_GET(RG_GPIO_MISC_TPBANK0_BOOTMODE, reg); ++ ++ return 0; ++} ++ ++static bool mt7988_phy_get_boottrap_polarity(struct phy_device *phydev) ++{ ++ struct mtk_socphy_shared *priv = phydev->shared->priv; ++ ++ if (priv->boottrap & BIT(phydev->mdio.addr)) ++ return false; ++ ++ return true; ++} ++ ++static int mt7988_phy_probe(struct phy_device *phydev) ++{ ++ int err; ++ ++ err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0, ++ sizeof(struct mtk_socphy_shared)); ++ if (err) ++ return err; ++ ++ if (phy_package_probe_once(phydev)) { ++ err = mt7988_phy_probe_shared(phydev); ++ if (err) ++ return err; ++ } ++ ++ mt798x_phy_setup_led(phydev, mt7988_phy_get_boottrap_polarity(phydev)); ++ ++ return mt798x_phy_calibration(phydev); ++} ++ + static struct phy_driver mtk_socphy_driver[] = { + { + PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), +@@ -1092,7 +1220,7 @@ static struct phy_driver mtk_socphy_driv + .config_init = mt798x_phy_config_init, + .config_intr = genphy_no_config_intr, + .handle_interrupt = genphy_handle_interrupt_no_ack, +- .probe = mt798x_phy_calibration, ++ .probe = mt7988_phy_probe, + .suspend = genphy_suspend, + .resume = genphy_resume, + .read_page = mtk_socphy_read_page, diff --git a/target/linux/mediatek/patches-6.1/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch b/target/linux/mediatek/patches-6.1/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch new file mode 100644 index 00000000000..d7457273712 --- /dev/null +++ b/target/linux/mediatek/patches-6.1/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch @@ -0,0 +1,63 @@ +From a969b663c866129ed9eb217785a6574fbe826f1d Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Thu, 6 Apr 2023 23:36:50 +0100 +Subject: [PATCH] net: phy: mxl-gpy: don't use SGMII AN if using phylink + +MAC drivers using phylink expect SGMII in-band-status to be switched off +when attached to a PHY. Make sure this is the case also for mxl-gpy which +keeps SGMII in-band-status in case of SGMII interface mode is used. + +Signed-off-by: Daniel Golle +--- + drivers/net/phy/mxl-gpy.c | 19 ++++++++++++++++--- + 1 file changed, 16 insertions(+), 3 deletions(-) + +--- a/drivers/net/phy/mxl-gpy.c ++++ b/drivers/net/phy/mxl-gpy.c +@@ -367,8 +367,11 @@ static bool gpy_2500basex_chk(struct phy + + phydev->speed = SPEED_2500; + phydev->interface = PHY_INTERFACE_MODE_2500BASEX; +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, +- VSPEC1_SGMII_CTRL_ANEN, 0); ++ ++ if (!phydev->phylink) ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, ++ VSPEC1_SGMII_CTRL_ANEN, 0); ++ + return true; + } + +@@ -392,6 +395,14 @@ static int gpy_config_aneg(struct phy_de + u32 adv; + int ret; + ++ /* Disable SGMII auto-negotiation if using phylink */ ++ if (phydev->phylink) { ++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, ++ VSPEC1_SGMII_CTRL_ANEN, 0); ++ if (ret < 0) ++ return ret; ++ } ++ + if (phydev->autoneg == AUTONEG_DISABLE) { + /* Configure half duplex with genphy_setup_forced, + * because genphy_c45_pma_setup_forced does not support. +@@ -482,6 +493,8 @@ static void gpy_update_interface(struct + switch (phydev->speed) { + case SPEED_2500: + phydev->interface = PHY_INTERFACE_MODE_2500BASEX; ++ if (phydev->phylink) ++ break; + ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, + VSPEC1_SGMII_CTRL_ANEN, 0); + if (ret < 0) +@@ -493,7 +506,7 @@ static void gpy_update_interface(struct + case SPEED_100: + case SPEED_10: + phydev->interface = PHY_INTERFACE_MODE_SGMII; +- if (gpy_sgmii_aneg_en(phydev)) ++ if (phydev->phylink || gpy_sgmii_aneg_en(phydev)) + break; + /* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed + * if ANEG is disabled (in 2500-BaseX mode). diff --git a/target/linux/mediatek/patches-6.1/732-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch b/target/linux/mediatek/patches-6.1/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch similarity index 90% rename from target/linux/mediatek/patches-6.1/732-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch rename to target/linux/mediatek/patches-6.1/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch index 7151eb35cc0..c3baafa2bbb 100644 --- a/target/linux/mediatek/patches-6.1/732-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch +++ b/target/linux/mediatek/patches-6.1/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch @@ -13,7 +13,7 @@ Signed-off-by: Daniel Golle --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig -@@ -305,6 +305,13 @@ config MEDIATEK_GE_SOC_PHY +@@ -319,6 +319,13 @@ config MEDIATEK_GE_SOC_PHY present in the SoCs efuse and will dynamically calibrate VCM (common-mode voltage) during startup. @@ -26,10 +26,10 @@ Signed-off-by: Daniel Golle + config MICREL_PHY tristate "Micrel PHYs" - help + depends on PTP_1588_CLOCK_OPTIONAL --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile -@@ -80,6 +80,7 @@ obj-$(CONFIG_MARVELL_10G_PHY) += marvell +@@ -83,6 +83,7 @@ obj-$(CONFIG_MARVELL_10G_PHY) += marvell obj-$(CONFIG_MARVELL_PHY) += marvell.o obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o diff --git a/target/linux/mediatek/patches-6.1/801-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch b/target/linux/mediatek/patches-6.1/801-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch deleted file mode 100644 index 691a7c0398e..00000000000 --- a/target/linux/mediatek/patches-6.1/801-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch +++ /dev/null @@ -1,225 +0,0 @@ -From 41ffe32e7ec23f592e21c508b5108899ad393059 Mon Sep 17 00:00:00 2001 -From: Zhanyong Wang -Date: Tue, 25 Jan 2022 16:50:47 +0800 -Subject: [PATCH 4/5] phy: phy-mtk-tphy: Add PCIe 2 lane efuse support - -Add PCIe 2 lane efuse support in tphy driver. - -Signed-off-by: Jie Yang -Signed-off-by: Zhanyong Wang ---- - drivers/phy/mediatek/phy-mtk-tphy.c | 140 ++++++++++++++++++++++++++++ - 1 file changed, 140 insertions(+) - ---- a/drivers/phy/mediatek/phy-mtk-tphy.c -+++ b/drivers/phy/mediatek/phy-mtk-tphy.c -@@ -44,6 +44,15 @@ - #define SSUSB_SIFSLV_V2_U3PHYD 0x200 - #define SSUSB_SIFSLV_V2_U3PHYA 0x400 - -+/* version V4 sub-banks offset base address */ -+/* pcie phy banks */ -+#define SSUSB_SIFSLV_V4_SPLLC 0x000 -+#define SSUSB_SIFSLV_V4_CHIP 0x100 -+#define SSUSB_SIFSLV_V4_U3PHYD 0x900 -+#define SSUSB_SIFSLV_V4_U3PHYA 0xb00 -+ -+#define SSUSB_LN1_OFFSET 0x10000 -+ - #define U3P_MISC_REG1 0x04 - #define MR1_EFUSE_AUTO_LOAD_DIS BIT(6) - -@@ -320,6 +329,7 @@ enum mtk_phy_version { - MTK_PHY_V1 = 1, - MTK_PHY_V2, - MTK_PHY_V3, -+ MTK_PHY_V4, - }; - - struct mtk_phy_pdata { -@@ -369,6 +379,9 @@ struct mtk_phy_instance { - u32 efuse_intr; - u32 efuse_tx_imp; - u32 efuse_rx_imp; -+ u32 efuse_intr_ln1; -+ u32 efuse_tx_imp_ln1; -+ u32 efuse_rx_imp_ln1; - int eye_src; - int eye_vrt; - int eye_term; -@@ -946,6 +959,36 @@ static void phy_v2_banks_init(struct mtk - } - } - -+static void phy_v4_banks_init(struct mtk_tphy *tphy, -+ struct mtk_phy_instance *instance) -+{ -+ struct u2phy_banks *u2_banks = &instance->u2_banks; -+ struct u3phy_banks *u3_banks = &instance->u3_banks; -+ -+ switch (instance->type) { -+ case PHY_TYPE_USB2: -+ u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC; -+ u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ; -+ u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM; -+ break; -+ case PHY_TYPE_USB3: -+ u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC; -+ u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP; -+ u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD; -+ u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA; -+ break; -+ case PHY_TYPE_PCIE: -+ u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V4_SPLLC; -+ u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V4_CHIP; -+ u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V4_U3PHYD; -+ u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V4_U3PHYA; -+ break; -+ default: -+ dev_err(tphy->dev, "incompatible PHY type\n"); -+ return; -+ } -+} -+ - static void phy_parse_property(struct mtk_tphy *tphy, - struct mtk_phy_instance *instance) - { -@@ -1144,6 +1187,40 @@ static int phy_efuse_get(struct mtk_tphy - - dev_dbg(dev, "u3 efuse - intr %x, rx_imp %x, tx_imp %x\n", - instance->efuse_intr, instance->efuse_rx_imp,instance->efuse_tx_imp); -+ -+ if (tphy->pdata->version != MTK_PHY_V4) -+ break; -+ -+ ret = nvmem_cell_read_variable_le_u32(dev, "intr_ln1", &instance->efuse_intr_ln1); -+ if (ret) { -+ dev_err(dev, "fail to get u3 lane1 intr efuse, %d\n", ret); -+ break; -+ } -+ -+ ret = nvmem_cell_read_variable_le_u32(dev, "rx_imp_ln1", &instance->efuse_rx_imp_ln1); -+ if (ret) { -+ dev_err(dev, "fail to get u3 lane1 rx_imp efuse, %d\n", ret); -+ break; -+ } -+ -+ ret = nvmem_cell_read_variable_le_u32(dev, "tx_imp_ln1", &instance->efuse_tx_imp_ln1); -+ if (ret) { -+ dev_err(dev, "fail to get u3 lane1 tx_imp efuse, %d\n", ret); -+ break; -+ } -+ -+ /* no efuse, ignore it */ -+ if (!instance->efuse_intr_ln1 && -+ !instance->efuse_rx_imp_ln1 && -+ !instance->efuse_tx_imp_ln1) { -+ dev_warn(dev, "no u3 lane1 efuse, but dts enable it\n"); -+ instance->efuse_sw_en = 0; -+ break; -+ } -+ -+ dev_info(dev, "u3 lane1 efuse - intr %x, rx_imp %x, tx_imp %x\n", -+ instance->efuse_intr_ln1, instance->efuse_rx_imp_ln1, -+ instance->efuse_tx_imp_ln1); - break; - default: - dev_err(dev, "no sw efuse for type %d\n", instance->type); -@@ -1175,6 +1252,31 @@ static void phy_efuse_set(struct mtk_phy - writel(tmp, u2_banks->com + U3P_USBPHYACR1); - break; - case PHY_TYPE_USB3: -+ tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV); -+ tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS; -+ writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV); -+ -+ tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0); -+ tmp &= ~P3D_RG_TX_IMPEL; -+ tmp |= P3D_RG_TX_IMPEL_VAL(instance->efuse_tx_imp); -+ tmp |= P3D_RG_FORCE_TX_IMPEL; -+ writel(tmp, u3_banks->phyd + U3P_U3_PHYD_IMPCAL0); -+ -+ tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1); -+ tmp &= ~P3D_RG_RX_IMPEL; -+ tmp |= P3D_RG_RX_IMPEL_VAL(instance->efuse_rx_imp); -+ tmp |= P3D_RG_FORCE_RX_IMPEL; -+ writel(tmp, u3_banks->phyd + U3P_U3_PHYD_IMPCAL1); -+ -+ tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0); -+ tmp &= ~P3A_RG_IEXT_INTR; -+ tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr); -+ writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0); -+ pr_err("%s set efuse, tx_imp %x, rx_imp %x intr %x\n", -+ __func__, instance->efuse_tx_imp, -+ instance->efuse_rx_imp, instance->efuse_intr); -+ -+ break; - case PHY_TYPE_PCIE: - tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV); - tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS; -@@ -1196,6 +1298,34 @@ static void phy_efuse_set(struct mtk_phy - tmp &= ~P3A_RG_IEXT_INTR; - tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr); - writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0); -+ if (!instance->efuse_intr_ln1 && -+ !instance->efuse_rx_imp_ln1 && -+ !instance->efuse_tx_imp_ln1) -+ break; -+ -+ tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV); -+ tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS; -+ writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV); -+ -+ tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL0); -+ tmp &= ~P3D_RG_TX_IMPEL; -+ tmp |= P3D_RG_TX_IMPEL_VAL(instance->efuse_tx_imp_ln1); -+ tmp |= P3D_RG_FORCE_TX_IMPEL; -+ writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL0); -+ -+ tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL1); -+ tmp &= ~P3D_RG_RX_IMPEL; -+ tmp |= P3D_RG_RX_IMPEL_VAL(instance->efuse_rx_imp_ln1); -+ tmp |= P3D_RG_FORCE_RX_IMPEL; -+ writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL1); -+ -+ tmp = readl(u3_banks->phya + SSUSB_LN1_OFFSET + U3P_U3_PHYA_REG0); -+ tmp &= ~P3A_RG_IEXT_INTR; -+ tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr_ln1); -+ writel(tmp, u3_banks->phya + SSUSB_LN1_OFFSET + U3P_U3_PHYA_REG0); -+ dev_info(dev, "%s set LN1 efuse, tx_imp %x, rx_imp %x intr %x\n", -+ __func__, instance->efuse_tx_imp_ln1, -+ instance->efuse_rx_imp_ln1, instance->efuse_intr_ln1); - break; - default: - dev_warn(dev, "no sw efuse for type %d\n", instance->type); -@@ -1335,6 +1465,9 @@ static struct phy *mtk_phy_xlate(struct - case MTK_PHY_V3: - phy_v2_banks_init(tphy, instance); - break; -+ case MTK_PHY_V4: -+ phy_v4_banks_init(tphy, instance); -+ break; - default: - dev_err(dev, "phy version is not supported\n"); - return ERR_PTR(-EINVAL); -@@ -1375,6 +1508,12 @@ static const struct mtk_phy_pdata tphy_v - .version = MTK_PHY_V3, - }; - -+static const struct mtk_phy_pdata tphy_v4_pdata = { -+ .avoid_rx_sen_degradation = false, -+ .sw_efuse_supported = true, -+ .version = MTK_PHY_V4, -+}; -+ - static const struct mtk_phy_pdata mt8173_pdata = { - .avoid_rx_sen_degradation = true, - .version = MTK_PHY_V1, -@@ -1394,6 +1533,7 @@ static const struct of_device_id mtk_tph - { .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata }, - { .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata }, - { .compatible = "mediatek,generic-tphy-v3", .data = &tphy_v3_pdata }, -+ { .compatible = "mediatek,generic-tphy-v4", .data = &tphy_v4_pdata }, - { }, - }; - MODULE_DEVICE_TABLE(of, mtk_tphy_id_table); diff --git a/target/linux/mediatek/patches-6.1/802-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch b/target/linux/mediatek/patches-6.1/802-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch deleted file mode 100644 index 3b8285bf479..00000000000 --- a/target/linux/mediatek/patches-6.1/802-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch +++ /dev/null @@ -1,149 +0,0 @@ -From 1d5819e90f2ef6dead11809744372a9863227a92 Mon Sep 17 00:00:00 2001 -From: Zhanyong Wang -Date: Tue, 25 Jan 2022 19:03:34 +0800 -Subject: [PATCH 5/5] phy: phy-mtk-tphy: add auto-load-valid check mechanism - support - -add auto-load-valid check mechanism support - -Signed-off-by: Zhanyong Wang ---- - drivers/phy/mediatek/phy-mtk-tphy.c | 67 +++++++++++++++++++++++++++-- - 1 file changed, 64 insertions(+), 3 deletions(-) - ---- a/drivers/phy/mediatek/phy-mtk-tphy.c -+++ b/drivers/phy/mediatek/phy-mtk-tphy.c -@@ -376,9 +376,13 @@ struct mtk_phy_instance { - u32 type_sw_reg; - u32 type_sw_index; - u32 efuse_sw_en; -+ bool efuse_alv_en; -+ u32 efuse_autoloadvalid; - u32 efuse_intr; - u32 efuse_tx_imp; - u32 efuse_rx_imp; -+ bool efuse_alv_ln1_en; -+ u32 efuse_ln1_autoloadvalid; - u32 efuse_intr_ln1; - u32 efuse_tx_imp_ln1; - u32 efuse_rx_imp_ln1; -@@ -1126,6 +1130,7 @@ static int phy_efuse_get(struct mtk_tphy - { - struct device *dev = &instance->phy->dev; - int ret = 0; -+ bool alv = false; - - /* tphy v1 doesn't support sw efuse, skip it */ - if (!tphy->pdata->sw_efuse_supported) { -@@ -1140,6 +1145,20 @@ static int phy_efuse_get(struct mtk_tphy - - switch (instance->type) { - case PHY_TYPE_USB2: -+ alv = of_property_read_bool(dev->of_node, "auto_load_valid"); -+ if (alv) { -+ instance->efuse_alv_en = alv; -+ ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid", -+ &instance->efuse_autoloadvalid); -+ if (ret) { -+ dev_err(dev, "fail to get u2 alv efuse, %d\n", ret); -+ break; -+ } -+ dev_info(dev, -+ "u2 auto load valid efuse: ENABLE with value: %u\n", -+ instance->efuse_autoloadvalid); -+ } -+ - ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr); - if (ret) { - dev_err(dev, "fail to get u2 intr efuse, %d\n", ret); -@@ -1158,6 +1177,20 @@ static int phy_efuse_get(struct mtk_tphy - - case PHY_TYPE_USB3: - case PHY_TYPE_PCIE: -+ alv = of_property_read_bool(dev->of_node, "auto_load_valid"); -+ if (alv) { -+ instance->efuse_alv_en = alv; -+ ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid", -+ &instance->efuse_autoloadvalid); -+ if (ret) { -+ dev_err(dev, "fail to get u3(pcei) alv efuse, %d\n", ret); -+ break; -+ } -+ dev_info(dev, -+ "u3 auto load valid efuse: ENABLE with value: %u\n", -+ instance->efuse_autoloadvalid); -+ } -+ - ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr); - if (ret) { - dev_err(dev, "fail to get u3 intr efuse, %d\n", ret); -@@ -1191,6 +1224,20 @@ static int phy_efuse_get(struct mtk_tphy - if (tphy->pdata->version != MTK_PHY_V4) - break; - -+ alv = of_property_read_bool(dev->of_node, "auto_load_valid_ln1"); -+ if (alv) { -+ instance->efuse_alv_ln1_en = alv; -+ ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid_ln1", -+ &instance->efuse_ln1_autoloadvalid); -+ if (ret) { -+ dev_err(dev, "fail to get pcie auto_load_valid efuse, %d\n", ret); -+ break; -+ } -+ dev_info(dev, -+ "pcie auto load valid efuse: ENABLE with value: %u\n", -+ instance->efuse_ln1_autoloadvalid); -+ } -+ - ret = nvmem_cell_read_variable_le_u32(dev, "intr_ln1", &instance->efuse_intr_ln1); - if (ret) { - dev_err(dev, "fail to get u3 lane1 intr efuse, %d\n", ret); -@@ -1242,6 +1289,10 @@ static void phy_efuse_set(struct mtk_phy - - switch (instance->type) { - case PHY_TYPE_USB2: -+ if (instance->efuse_alv_en && -+ instance->efuse_autoloadvalid == 1) -+ break; -+ - tmp = readl(u2_banks->misc + U3P_MISC_REG1); - tmp |= MR1_EFUSE_AUTO_LOAD_DIS; - writel(tmp, u2_banks->misc + U3P_MISC_REG1); -@@ -1252,6 +1303,10 @@ static void phy_efuse_set(struct mtk_phy - writel(tmp, u2_banks->com + U3P_USBPHYACR1); - break; - case PHY_TYPE_USB3: -+ if (instance->efuse_alv_en && -+ instance->efuse_autoloadvalid == 1) -+ break; -+ - tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV); - tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS; - writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV); -@@ -1278,6 +1333,10 @@ static void phy_efuse_set(struct mtk_phy - - break; - case PHY_TYPE_PCIE: -+ if (instance->efuse_alv_en && -+ instance->efuse_autoloadvalid == 1) -+ break; -+ - tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV); - tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS; - writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV); -@@ -1298,9 +1357,12 @@ static void phy_efuse_set(struct mtk_phy - tmp &= ~P3A_RG_IEXT_INTR; - tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr); - writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0); -- if (!instance->efuse_intr_ln1 && -- !instance->efuse_rx_imp_ln1 && -- !instance->efuse_tx_imp_ln1) -+ -+ if ((!instance->efuse_intr_ln1 && -+ !instance->efuse_rx_imp_ln1 && -+ !instance->efuse_tx_imp_ln1) || -+ (instance->efuse_alv_ln1_en && -+ instance->efuse_ln1_autoloadvalid == 1)) - break; - - tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV); diff --git a/target/linux/mediatek/patches-6.1/804-pwm-add-mt7986-support.patch b/target/linux/mediatek/patches-6.1/804-pwm-add-mt7986-support.patch index 7a10dac051c..0c73d520b46 100644 --- a/target/linux/mediatek/patches-6.1/804-pwm-add-mt7986-support.patch +++ b/target/linux/mediatek/patches-6.1/804-pwm-add-mt7986-support.patch @@ -1,6 +1,6 @@ --- a/drivers/pwm/pwm-mediatek.c +++ b/drivers/pwm/pwm-mediatek.c -@@ -302,6 +302,12 @@ static const struct pwm_mediatek_of_data +@@ -329,6 +329,12 @@ static const struct pwm_mediatek_of_data .has_ck_26m_sel = true, }; @@ -13,11 +13,11 @@ static const struct pwm_mediatek_of_data mt8516_pwm_data = { .num_pwms = 5, .pwm45_fixup = false, -@@ -314,6 +320,7 @@ static const struct of_device_id pwm_med +@@ -342,6 +348,7 @@ static const struct of_device_id pwm_med { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data }, { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data }, { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data }, + { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data }, { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data }, + { .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data }, { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data }, - { }, diff --git a/target/linux/mediatek/patches-6.1/805-v6.2-thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch b/target/linux/mediatek/patches-6.1/805-v6.2-thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch index b142b22eb8d..c58ae96403a 100644 --- a/target/linux/mediatek/patches-6.1/805-v6.2-thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch +++ b/target/linux/mediatek/patches-6.1/805-v6.2-thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch @@ -42,7 +42,7 @@ Signed-off-by: Daniel Golle /* * The first read of a sensor often contains very high bogus -@@ -1085,6 +1083,11 @@ static int mtk_thermal_probe(struct plat +@@ -1075,6 +1073,11 @@ static int mtk_thermal_probe(struct plat mtk_thermal_release_periodic_ts(mt, auxadc_base); } diff --git a/target/linux/mediatek/patches-6.1/806-v6.2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch b/target/linux/mediatek/patches-6.1/806-v6.2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch index 3ac2e7fc28c..65311d5718d 100644 --- a/target/linux/mediatek/patches-6.1/806-v6.2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch +++ b/target/linux/mediatek/patches-6.1/806-v6.2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch @@ -210,7 +210,7 @@ Signed-off-by: Daniel Golle .compatible = "mediatek,mt8183-thermal", .data = (void *)&mt8183_thermal_data, }, { -@@ -1078,15 +1196,24 @@ static int mtk_thermal_probe(struct plat +@@ -1068,15 +1186,24 @@ static int mtk_thermal_probe(struct plat goto err_disable_clk_auxadc; } diff --git a/target/linux/mediatek/patches-6.1/811-pwm-mediatek-Add-support-for-MT7981.patch b/target/linux/mediatek/patches-6.1/811-pwm-mediatek-Add-support-for-MT7981.patch deleted file mode 100644 index 8f27462cbdc..00000000000 --- a/target/linux/mediatek/patches-6.1/811-pwm-mediatek-Add-support-for-MT7981.patch +++ /dev/null @@ -1,122 +0,0 @@ -From 73d20ebc21c562fbe79d02fa0fa38e095e716fa9 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Wed, 19 Apr 2023 20:25:51 +0100 -Subject: [PATCH] pwm: mediatek: Add support for MT7981 - -The PWM unit on MT7981 uses different register offsets than previous -MediaTek PWM units. Add support for these new offsets and add support -for PWM on MT7981 which has 3 PWM channels, one of them is typically -used for a temperature controlled fan. - -Signed-off-by: Daniel Golle ---- - drivers/pwm/pwm-mediatek.c | 41 ++++++++++++++++++++++++++++++-------- - 1 file changed, 33 insertions(+), 8 deletions(-) - ---- a/drivers/pwm/pwm-mediatek.c -+++ b/drivers/pwm/pwm-mediatek.c -@@ -38,6 +38,7 @@ struct pwm_mediatek_of_data { - unsigned int num_pwms; - bool pwm45_fixup; - bool has_ck_26m_sel; -+ const unsigned int *reg_offset; - }; - - /** -@@ -59,10 +60,14 @@ struct pwm_mediatek_chip { - const struct pwm_mediatek_of_data *soc; - }; - --static const unsigned int pwm_mediatek_reg_offset[] = { -+static const unsigned int mtk_pwm_reg_offset_v1[] = { - 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220 - }; - -+static const unsigned int mtk_pwm_reg_offset_v2[] = { -+ 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240 -+}; -+ - static inline struct pwm_mediatek_chip * - to_pwm_mediatek_chip(struct pwm_chip *chip) - { -@@ -111,7 +116,7 @@ static inline void pwm_mediatek_writel(s - unsigned int num, unsigned int offset, - u32 value) - { -- writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset); -+ writel(value, chip->regs + chip->soc->reg_offset[num] + offset); - } - - static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm, -@@ -270,48 +275,63 @@ static const struct pwm_mediatek_of_data - .num_pwms = 8, - .pwm45_fixup = false, - .has_ck_26m_sel = false, -+ .reg_offset = mtk_pwm_reg_offset_v1, - }; - - static const struct pwm_mediatek_of_data mt7622_pwm_data = { - .num_pwms = 6, - .pwm45_fixup = false, - .has_ck_26m_sel = true, -+ .reg_offset = mtk_pwm_reg_offset_v1, - }; - - static const struct pwm_mediatek_of_data mt7623_pwm_data = { - .num_pwms = 5, - .pwm45_fixup = true, - .has_ck_26m_sel = false, -+ .reg_offset = mtk_pwm_reg_offset_v1, - }; - - static const struct pwm_mediatek_of_data mt7628_pwm_data = { - .num_pwms = 4, - .pwm45_fixup = true, - .has_ck_26m_sel = false, -+ .reg_offset = mtk_pwm_reg_offset_v1, - }; - - static const struct pwm_mediatek_of_data mt7629_pwm_data = { - .num_pwms = 1, - .pwm45_fixup = false, - .has_ck_26m_sel = false, -+ .reg_offset = mtk_pwm_reg_offset_v1, - }; - - static const struct pwm_mediatek_of_data mt8183_pwm_data = { - .num_pwms = 4, - .pwm45_fixup = false, - .has_ck_26m_sel = true, -+ .reg_offset = mtk_pwm_reg_offset_v1, -+}; -+ -+static const struct pwm_mediatek_of_data mt7981_pwm_data = { -+ .num_pwms = 3, -+ .pwm45_fixup = false, -+ .has_ck_26m_sel = true, -+ .reg_offset = mtk_pwm_reg_offset_v2, - }; - - static const struct pwm_mediatek_of_data mt7986_pwm_data = { - .num_pwms = 2, - .pwm45_fixup = false, - .has_ck_26m_sel = true, -+ .reg_offset = mtk_pwm_reg_offset_v1, - }; - - static const struct pwm_mediatek_of_data mt8516_pwm_data = { - .num_pwms = 5, - .pwm45_fixup = false, - .has_ck_26m_sel = true, -+ .reg_offset = mtk_pwm_reg_offset_v1, - }; - - static const struct of_device_id pwm_mediatek_of_match[] = { -@@ -320,6 +340,7 @@ static const struct of_device_id pwm_med - { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data }, - { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data }, - { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data }, -+ { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data }, - { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data }, - { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data }, - { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data }, diff --git a/target/linux/mediatek/patches-6.1/820-v5.16-dt-bindings-pinctrl-mt8195-add-rsel-define.patch b/target/linux/mediatek/patches-6.1/820-v5.16-dt-bindings-pinctrl-mt8195-add-rsel-define.patch deleted file mode 100644 index f2be737146e..00000000000 --- a/target/linux/mediatek/patches-6.1/820-v5.16-dt-bindings-pinctrl-mt8195-add-rsel-define.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 26564c44357e19d03c124550bbd0b5851e6638c2 Mon Sep 17 00:00:00 2001 -From: Zhiyong Tao -Date: Fri, 24 Sep 2021 16:06:28 +0800 -Subject: [PATCH] dt-bindings: pinctrl: mt8195: add rsel define - -This patch adds rsel define for mt8195. - -Signed-off-by: Zhiyong Tao -Acked-by: Rob Herring -Link: https://lore.kernel.org/r/20210924080632.28410-2-zhiyong.tao@mediatek.com -Signed-off-by: Linus Walleij ---- - include/dt-bindings/pinctrl/mt65xx.h | 9 +++++++++ - 1 file changed, 9 insertions(+) - ---- a/include/dt-bindings/pinctrl/mt65xx.h -+++ b/include/dt-bindings/pinctrl/mt65xx.h -@@ -16,6 +16,15 @@ - #define MTK_PUPD_SET_R1R0_10 102 - #define MTK_PUPD_SET_R1R0_11 103 - -+#define MTK_PULL_SET_RSEL_000 200 -+#define MTK_PULL_SET_RSEL_001 201 -+#define MTK_PULL_SET_RSEL_010 202 -+#define MTK_PULL_SET_RSEL_011 203 -+#define MTK_PULL_SET_RSEL_100 204 -+#define MTK_PULL_SET_RSEL_101 205 -+#define MTK_PULL_SET_RSEL_110 206 -+#define MTK_PULL_SET_RSEL_111 207 -+ - #define MTK_DRIVE_2mA 2 - #define MTK_DRIVE_4mA 4 - #define MTK_DRIVE_6mA 6 diff --git a/target/linux/mediatek/patches-6.1/821-v5.16-pinctrl-mediatek-moore-check-if-pin_desc-is-valid-be.patch b/target/linux/mediatek/patches-6.1/821-v5.16-pinctrl-mediatek-moore-check-if-pin_desc-is-valid-be.patch deleted file mode 100644 index aa9f879e3aa..00000000000 --- a/target/linux/mediatek/patches-6.1/821-v5.16-pinctrl-mediatek-moore-check-if-pin_desc-is-valid-be.patch +++ /dev/null @@ -1,93 +0,0 @@ -From d8b94c9ff96c2024a527086d850eb0b314337ff9 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Tue, 14 Sep 2021 16:51:32 +0800 -Subject: [PATCH] pinctrl: mediatek: moore: check if pin_desc is valid before - use - -Certain SoC are missing the middle part gpios in consecutive pins, -it's better to check if mtk_pin_desc is a valid pin for the extensibility - -Signed-off-by: Sam Shih -Acked-by: Sean Wang -Link: https://lore.kernel.org/r/20210914085137.31761-5-sam.shih@mediatek.com -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/mediatek/pinctrl-moore.c | 18 ++++++++++++++++++ - 1 file changed, 18 insertions(+) - ---- a/drivers/pinctrl/mediatek/pinctrl-moore.c -+++ b/drivers/pinctrl/mediatek/pinctrl-moore.c -@@ -60,6 +60,8 @@ static int mtk_pinmux_set_mux(struct pin - int pin = grp->pins[i]; - - desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; -+ if (!desc->name) -+ return -ENOTSUPP; - - mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, - pin_modes[i]); -@@ -76,6 +78,8 @@ static int mtk_pinmux_gpio_request_enabl - const struct mtk_pin_desc *desc; - - desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; -+ if (!desc->name) -+ return -ENOTSUPP; - - return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, - hw->soc->gpio_m); -@@ -89,6 +93,8 @@ static int mtk_pinmux_gpio_set_direction - const struct mtk_pin_desc *desc; - - desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; -+ if (!desc->name) -+ return -ENOTSUPP; - - /* hardware would take 0 as input direction */ - return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input); -@@ -103,6 +109,8 @@ static int mtk_pinconf_get(struct pinctr - const struct mtk_pin_desc *desc; - - desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; -+ if (!desc->name) -+ return -ENOTSUPP; - - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: -@@ -218,6 +226,8 @@ static int mtk_pinconf_set(struct pinctr - int cfg, err = 0; - - desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; -+ if (!desc->name) -+ return -ENOTSUPP; - - for (cfg = 0; cfg < num_configs; cfg++) { - param = pinconf_to_config_param(configs[cfg]); -@@ -435,6 +445,8 @@ static int mtk_gpio_get(struct gpio_chip - int value, err; - - desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; -+ if (!desc->name) -+ return -ENOTSUPP; - - err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value); - if (err) -@@ -449,6 +461,10 @@ static void mtk_gpio_set(struct gpio_chi - const struct mtk_pin_desc *desc; - - desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; -+ if (!desc->name) { -+ dev_err(hw->dev, "Failed to set gpio %d\n", gpio); -+ return; -+ } - - mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value); - } -@@ -490,6 +506,8 @@ static int mtk_gpio_set_config(struct gp - u32 debounce; - - desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset]; -+ if (!desc->name) -+ return -ENOTSUPP; - - if (!hw->eint || - pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE || diff --git a/target/linux/mediatek/patches-6.1/822-v5.16-pinctrl-mediatek-support-rsel-feature.patch b/target/linux/mediatek/patches-6.1/822-v5.16-pinctrl-mediatek-support-rsel-feature.patch deleted file mode 100644 index 0f5c0495fef..00000000000 --- a/target/linux/mediatek/patches-6.1/822-v5.16-pinctrl-mediatek-support-rsel-feature.patch +++ /dev/null @@ -1,457 +0,0 @@ -From fb34a9ae383ae26326d4889fd2513e49f1019b88 Mon Sep 17 00:00:00 2001 -From: Zhiyong Tao -Date: Fri, 24 Sep 2021 16:06:31 +0800 -Subject: [PATCH] pinctrl: mediatek: support rsel feature - -This patch supports rsel(resistance selection) feature for I2C pins. -It provides more resistance selection solution in different ICs. -It provides rsel define and si unit solution by identifying -"mediatek,rsel_resistance_in_si_unit" property in pio dtsi node. - -Signed-off-by: Zhiyong Tao -Reviewed-by: Chen-Yu Tsai -Link: https://lore.kernel.org/r/20210924080632.28410-5-zhiyong.tao@mediatek.com -Signed-off-by: Linus Walleij ---- - .../pinctrl/mediatek/pinctrl-mtk-common-v2.c | 231 +++++++++++++++--- - .../pinctrl/mediatek/pinctrl-mtk-common-v2.h | 46 ++++ - drivers/pinctrl/mediatek/pinctrl-paris.c | 60 +++-- - 3 files changed, 289 insertions(+), 48 deletions(-) - ---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c -@@ -665,6 +665,181 @@ out: - return err; - } - -+static int mtk_hw_pin_rsel_lookup(struct mtk_pinctrl *hw, -+ const struct mtk_pin_desc *desc, -+ u32 pullup, u32 arg, u32 *rsel_val) -+{ -+ const struct mtk_pin_rsel *rsel; -+ int check; -+ bool found = false; -+ -+ rsel = hw->soc->pin_rsel; -+ -+ for (check = 0; check <= hw->soc->npin_rsel - 1; check++) { -+ if (desc->number >= rsel[check].s_pin && -+ desc->number <= rsel[check].e_pin) { -+ if (pullup) { -+ if (rsel[check].up_rsel == arg) { -+ found = true; -+ *rsel_val = rsel[check].rsel_index; -+ break; -+ } -+ } else { -+ if (rsel[check].down_rsel == arg) { -+ found = true; -+ *rsel_val = rsel[check].rsel_index; -+ break; -+ } -+ } -+ } -+ } -+ -+ if (!found) { -+ dev_err(hw->dev, "Not support rsel value %d Ohm for pin = %d (%s)\n", -+ arg, desc->number, desc->name); -+ return -ENOTSUPP; -+ } -+ -+ return 0; -+} -+ -+static int mtk_pinconf_bias_set_rsel(struct mtk_pinctrl *hw, -+ const struct mtk_pin_desc *desc, -+ u32 pullup, u32 arg) -+{ -+ int err, rsel_val; -+ -+ if (hw->rsel_si_unit) { -+ /* find pin rsel_index from pin_rsel array*/ -+ err = mtk_hw_pin_rsel_lookup(hw, desc, pullup, arg, &rsel_val); -+ if (err) -+ goto out; -+ } else { -+ if (arg < MTK_PULL_SET_RSEL_000 || -+ arg > MTK_PULL_SET_RSEL_111) { -+ err = -EINVAL; -+ goto out; -+ } -+ -+ rsel_val = arg - MTK_PULL_SET_RSEL_000; -+ } -+ -+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_RSEL, rsel_val); -+ if (err) -+ goto out; -+ -+ err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, MTK_ENABLE); -+ -+out: -+ return err; -+} -+ -+int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw, -+ const struct mtk_pin_desc *desc, -+ u32 pullup, u32 arg) -+{ -+ int err = -ENOTSUPP; -+ u32 try_all_type; -+ -+ if (hw->soc->pull_type) -+ try_all_type = hw->soc->pull_type[desc->number]; -+ else -+ try_all_type = MTK_PULL_TYPE_MASK; -+ -+ if (try_all_type & MTK_PULL_RSEL_TYPE) { -+ err = mtk_pinconf_bias_set_rsel(hw, desc, pullup, arg); -+ if (!err) -+ return err; -+ } -+ -+ if (try_all_type & MTK_PULL_PU_PD_TYPE) { -+ err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg); -+ if (!err) -+ return err; -+ } -+ -+ if (try_all_type & MTK_PULL_PULLSEL_TYPE) { -+ err = mtk_pinconf_bias_set_pullsel_pullen(hw, desc, -+ pullup, arg); -+ if (!err) -+ return err; -+ } -+ -+ if (try_all_type & MTK_PULL_PUPD_R1R0_TYPE) -+ err = mtk_pinconf_bias_set_pupd_r1_r0(hw, desc, pullup, arg); -+ -+ if (err) -+ dev_err(hw->dev, "Invalid pull argument\n"); -+ -+ return err; -+} -+EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_combo); -+ -+static int mtk_rsel_get_si_unit(struct mtk_pinctrl *hw, -+ const struct mtk_pin_desc *desc, -+ u32 pullup, u32 rsel_val, u32 *si_unit) -+{ -+ const struct mtk_pin_rsel *rsel; -+ int check; -+ -+ rsel = hw->soc->pin_rsel; -+ -+ for (check = 0; check <= hw->soc->npin_rsel - 1; check++) { -+ if (desc->number >= rsel[check].s_pin && -+ desc->number <= rsel[check].e_pin) { -+ if (rsel_val == rsel[check].rsel_index) { -+ if (pullup) -+ *si_unit = rsel[check].up_rsel; -+ else -+ *si_unit = rsel[check].down_rsel; -+ break; -+ } -+ } -+ } -+ -+ return 0; -+} -+ -+static int mtk_pinconf_bias_get_rsel(struct mtk_pinctrl *hw, -+ const struct mtk_pin_desc *desc, -+ u32 *pullup, u32 *enable) -+{ -+ int pu, pd, rsel, err; -+ -+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_RSEL, &rsel); -+ if (err) -+ goto out; -+ -+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &pu); -+ if (err) -+ goto out; -+ -+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd); -+ -+ if (pu == 0 && pd == 0) { -+ *pullup = 0; -+ *enable = MTK_DISABLE; -+ } else if (pu == 1 && pd == 0) { -+ *pullup = 1; -+ if (hw->rsel_si_unit) -+ mtk_rsel_get_si_unit(hw, desc, *pullup, rsel, enable); -+ else -+ *enable = rsel + MTK_PULL_SET_RSEL_000; -+ } else if (pu == 0 && pd == 1) { -+ *pullup = 0; -+ if (hw->rsel_si_unit) -+ mtk_rsel_get_si_unit(hw, desc, *pullup, rsel, enable); -+ else -+ *enable = rsel + MTK_PULL_SET_RSEL_000; -+ } else { -+ err = -EINVAL; -+ goto out; -+ } -+ -+out: -+ return err; -+} -+ - static int mtk_pinconf_bias_get_pu_pd(struct mtk_pinctrl *hw, - const struct mtk_pin_desc *desc, - u32 *pullup, u32 *enable) -@@ -746,44 +921,40 @@ out: - return err; - } - --int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw, -- const struct mtk_pin_desc *desc, -- u32 pullup, u32 arg) --{ -- int err; -- -- err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg); -- if (!err) -- goto out; -- -- err = mtk_pinconf_bias_set_pullsel_pullen(hw, desc, pullup, arg); -- if (!err) -- goto out; -- -- err = mtk_pinconf_bias_set_pupd_r1_r0(hw, desc, pullup, arg); -- --out: -- return err; --} --EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_combo); -- - int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw, - const struct mtk_pin_desc *desc, - u32 *pullup, u32 *enable) - { -- int err; -+ int err = -ENOTSUPP; -+ u32 try_all_type; - -- err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable); -- if (!err) -- goto out; -+ if (hw->soc->pull_type) -+ try_all_type = hw->soc->pull_type[desc->number]; -+ else -+ try_all_type = MTK_PULL_TYPE_MASK; - -- err = mtk_pinconf_bias_get_pullsel_pullen(hw, desc, pullup, enable); -- if (!err) -- goto out; -+ if (try_all_type & MTK_PULL_RSEL_TYPE) { -+ err = mtk_pinconf_bias_get_rsel(hw, desc, pullup, enable); -+ if (!err) -+ return err; -+ } -+ -+ if (try_all_type & MTK_PULL_PU_PD_TYPE) { -+ err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable); -+ if (!err) -+ return err; -+ } -+ -+ if (try_all_type & MTK_PULL_PULLSEL_TYPE) { -+ err = mtk_pinconf_bias_get_pullsel_pullen(hw, desc, -+ pullup, enable); -+ if (!err) -+ return err; -+ } - -- err = mtk_pinconf_bias_get_pupd_r1_r0(hw, desc, pullup, enable); -+ if (try_all_type & MTK_PULL_PUPD_R1R0_TYPE) -+ err = mtk_pinconf_bias_get_pupd_r1_r0(hw, desc, pullup, enable); - --out: - return err; - } - EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_combo); ---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h -+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h -@@ -17,6 +17,22 @@ - #define MTK_ENABLE 1 - #define MTK_PULLDOWN 0 - #define MTK_PULLUP 1 -+#define MTK_PULL_PU_PD_TYPE BIT(0) -+#define MTK_PULL_PULLSEL_TYPE BIT(1) -+#define MTK_PULL_PUPD_R1R0_TYPE BIT(2) -+/* MTK_PULL_RSEL_TYPE can select resistance and can be -+ * turned on/off itself. But it can't be selected pull up/down -+ */ -+#define MTK_PULL_RSEL_TYPE BIT(3) -+/* MTK_PULL_PU_PD_RSEL_TYPE is a type which is controlled by -+ * MTK_PULL_PU_PD_TYPE and MTK_PULL_RSEL_TYPE. -+ */ -+#define MTK_PULL_PU_PD_RSEL_TYPE (MTK_PULL_PU_PD_TYPE \ -+ | MTK_PULL_RSEL_TYPE) -+#define MTK_PULL_TYPE_MASK (MTK_PULL_PU_PD_TYPE |\ -+ MTK_PULL_PULLSEL_TYPE |\ -+ MTK_PULL_PUPD_R1R0_TYPE |\ -+ MTK_PULL_RSEL_TYPE) - - #define EINT_NA U16_MAX - #define NO_EINT_SUPPORT EINT_NA -@@ -42,6 +58,14 @@ - PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \ - _x_bits, 32, 1) - -+#define PIN_RSEL(_s_pin, _e_pin, _rsel_index, _up_resl, _down_rsel) { \ -+ .s_pin = _s_pin, \ -+ .e_pin = _e_pin, \ -+ .rsel_index = _rsel_index, \ -+ .up_rsel = _up_resl, \ -+ .down_rsel = _down_rsel, \ -+ } -+ - /* List these attributes which could be modified for the pin */ - enum { - PINCTRL_PIN_REG_MODE, -@@ -67,6 +91,7 @@ enum { - PINCTRL_PIN_REG_DRV_E0, - PINCTRL_PIN_REG_DRV_E1, - PINCTRL_PIN_REG_DRV_ADV, -+ PINCTRL_PIN_REG_RSEL, - PINCTRL_PIN_REG_MAX, - }; - -@@ -129,6 +154,22 @@ struct mtk_pin_field_calc { - u8 fixed; - }; - -+/** -+ * struct mtk_pin_rsel - the structure that provides bias resistance selection. -+ * @s_pin: the start pin within the rsel range -+ * @e_pin: the end pin within the rsel range -+ * @rsel_index: the rsel bias resistance index -+ * @up_rsel: the pullup rsel bias resistance value -+ * @down_rsel: the pulldown rsel bias resistance value -+ */ -+struct mtk_pin_rsel { -+ u16 s_pin; -+ u16 e_pin; -+ u16 rsel_index; -+ u32 up_rsel; -+ u32 down_rsel; -+}; -+ - /* struct mtk_pin_reg_calc - the structure that holds all ranges used to - * determine which register the pin would make use of - * for certain pin attribute. -@@ -206,6 +247,9 @@ struct mtk_pin_soc { - bool ies_present; - const char * const *base_names; - unsigned int nbase_names; -+ const unsigned int *pull_type; -+ const struct mtk_pin_rsel *pin_rsel; -+ unsigned int npin_rsel; - - /* Specific pinconfig operations */ - int (*bias_disable_set)(struct mtk_pinctrl *hw, -@@ -254,6 +298,8 @@ struct mtk_pinctrl { - const char **grp_names; - /* lock pin's register resource to avoid multiple threads issue*/ - spinlock_t lock; -+ /* identify rsel setting by si unit or rsel define in dts node */ -+ bool rsel_si_unit; - }; - - void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set); ---- a/drivers/pinctrl/mediatek/pinctrl-paris.c -+++ b/drivers/pinctrl/mediatek/pinctrl-paris.c -@@ -574,8 +574,9 @@ static int mtk_hw_get_value_wrap(struct - ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw, - unsigned int gpio, char *buf, unsigned int buf_len) - { -- int pinmux, pullup = 0, pullen = 0, len = 0, r1 = -1, r0 = -1; -+ int pinmux, pullup = 0, pullen = 0, len = 0, r1 = -1, r0 = -1, rsel = -1; - const struct mtk_pin_desc *desc; -+ u32 try_all_type; - - if (gpio >= hw->soc->npins) - return -EINVAL; -@@ -589,24 +590,39 @@ ssize_t mtk_pctrl_show_one_pin(struct mt - pinmux -= hw->soc->nfuncs; - - mtk_pinconf_bias_get_combo(hw, desc, &pullup, &pullen); -- if (pullen == MTK_PUPD_SET_R1R0_00) { -- pullen = 0; -- r1 = 0; -- r0 = 0; -- } else if (pullen == MTK_PUPD_SET_R1R0_01) { -- pullen = 1; -- r1 = 0; -- r0 = 1; -- } else if (pullen == MTK_PUPD_SET_R1R0_10) { -- pullen = 1; -- r1 = 1; -- r0 = 0; -- } else if (pullen == MTK_PUPD_SET_R1R0_11) { -+ -+ if (hw->soc->pull_type) -+ try_all_type = hw->soc->pull_type[desc->number]; -+ -+ if (hw->rsel_si_unit && (try_all_type & MTK_PULL_RSEL_TYPE)) { -+ rsel = pullen; - pullen = 1; -- r1 = 1; -- r0 = 1; -- } else if (pullen != MTK_DISABLE && pullen != MTK_ENABLE) { -- pullen = 0; -+ } else { -+ /* Case for: R1R0 */ -+ if (pullen == MTK_PUPD_SET_R1R0_00) { -+ pullen = 0; -+ r1 = 0; -+ r0 = 0; -+ } else if (pullen == MTK_PUPD_SET_R1R0_01) { -+ pullen = 1; -+ r1 = 0; -+ r0 = 1; -+ } else if (pullen == MTK_PUPD_SET_R1R0_10) { -+ pullen = 1; -+ r1 = 1; -+ r0 = 0; -+ } else if (pullen == MTK_PUPD_SET_R1R0_11) { -+ pullen = 1; -+ r1 = 1; -+ r0 = 1; -+ } -+ -+ /* Case for: RSEL */ -+ if (pullen >= MTK_PULL_SET_RSEL_000 && -+ pullen <= MTK_PULL_SET_RSEL_111) { -+ rsel = pullen - MTK_PULL_SET_RSEL_000; -+ pullen = 1; -+ } - } - len += scnprintf(buf + len, buf_len - len, - "%03d: %1d%1d%1d%1d%02d%1d%1d%1d%1d", -@@ -624,6 +640,8 @@ ssize_t mtk_pctrl_show_one_pin(struct mt - if (r1 != -1) { - len += scnprintf(buf + len, buf_len - len, " (%1d %1d)\n", - r1, r0); -+ } else if (rsel != -1) { -+ len += scnprintf(buf + len, buf_len - len, " (%1d)\n", rsel); - } else { - len += scnprintf(buf + len, buf_len - len, "\n"); - } -@@ -966,6 +984,12 @@ int mtk_paris_pinctrl_probe(struct platf - - hw->nbase = hw->soc->nbase_names; - -+ if (of_find_property(hw->dev->of_node, -+ "mediatek,rsel_resistance_in_si_unit", NULL)) -+ hw->rsel_si_unit = true; -+ else -+ hw->rsel_si_unit = false; -+ - spin_lock_init(&hw->lock); - - err = mtk_pctrl_build_state(pdev); diff --git a/target/linux/mediatek/patches-6.1/823-v5.17-pinctrl-mediatek-add-a-check-for-error-in-mtk_pincon.patch b/target/linux/mediatek/patches-6.1/823-v5.17-pinctrl-mediatek-add-a-check-for-error-in-mtk_pincon.patch deleted file mode 100644 index 6752b4093b4..00000000000 --- a/target/linux/mediatek/patches-6.1/823-v5.17-pinctrl-mediatek-add-a-check-for-error-in-mtk_pincon.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 9f9d17c228c89e38ed612500126daf626270be9a Mon Sep 17 00:00:00 2001 -From: Dan Carpenter -Date: Sat, 27 Nov 2021 17:08:36 +0300 -Subject: [PATCH] pinctrl: mediatek: add a check for error in - mtk_pinconf_bias_get_rsel() - -All the other mtk_hw_get_value() calls have a check for "if (err)" so -we can add one here as well. This silences a Smatch warning: - - drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c:819 mtk_pinconf_bias_get_rsel() - error: uninitialized symbol 'pd'. - -Fixes: fb34a9ae383a ("pinctrl: mediatek: support rsel feature") -Signed-off-by: Dan Carpenter -Link: https://lore.kernel.org/r/20211127140836.GB24002@kili -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c -@@ -815,6 +815,8 @@ static int mtk_pinconf_bias_get_rsel(str - goto out; - - err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd); -+ if (err) -+ goto out; - - if (pu == 0 && pd == 0) { - *pullup = 0; diff --git a/target/linux/mediatek/patches-6.1/824-v6.1-pinctrl-mediatek-Fix-EINT-pins-input-debounce-time-c.patch b/target/linux/mediatek/patches-6.1/824-v6.1-pinctrl-mediatek-Fix-EINT-pins-input-debounce-time-c.patch deleted file mode 100644 index 47a29fbdba4..00000000000 --- a/target/linux/mediatek/patches-6.1/824-v6.1-pinctrl-mediatek-Fix-EINT-pins-input-debounce-time-c.patch +++ /dev/null @@ -1,297 +0,0 @@ -From e1ff91f9d2303cd4e706cc908bfca21cd17b9927 Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Fri, 11 Nov 2022 10:41:06 +0100 -Subject: [PATCH] pinctrl: mediatek: Fix EINT pins input debounce time - configuration - -The External Interrupt Controller (EINTC) on all of the supported -MediaTek SoCs does support input debouncing, but not all of them -index the debounce time values (DBNC_SETTING registers) the same way. - -Before this change, in some cases, as an example, requesting a debounce -time of 16 milliseconds would mistakenly set the relative DBNC_SETTING -register to 0x2, resulting in a way shorter debounce time of 500uS. - -To fix the aforementioned issue, define three different debounce_time -arrays, reflecting the correct register index for each value and for -each register index variant, and make sure that each SoC pinctrl -driver uses the right one. - -Signed-off-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20221111094106.18486-1-angelogioacchino.delregno@collabora.com -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/mediatek/mtk-eint.c | 31 +++++++++++++++++++---- - drivers/pinctrl/mediatek/mtk-eint.h | 6 +++++ - drivers/pinctrl/mediatek/pinctrl-mt2701.c | 1 + - drivers/pinctrl/mediatek/pinctrl-mt2712.c | 1 + - drivers/pinctrl/mediatek/pinctrl-mt6765.c | 1 + - drivers/pinctrl/mediatek/pinctrl-mt6779.c | 1 + - drivers/pinctrl/mediatek/pinctrl-mt7622.c | 1 + - drivers/pinctrl/mediatek/pinctrl-mt7623.c | 1 + - drivers/pinctrl/mediatek/pinctrl-mt7629.c | 1 + - drivers/pinctrl/mediatek/pinctrl-mt8127.c | 1 + - drivers/pinctrl/mediatek/pinctrl-mt8135.c | 1 + - drivers/pinctrl/mediatek/pinctrl-mt8167.c | 1 + - drivers/pinctrl/mediatek/pinctrl-mt8173.c | 1 + - drivers/pinctrl/mediatek/pinctrl-mt8183.c | 1 + - drivers/pinctrl/mediatek/pinctrl-mt8192.c | 1 + - drivers/pinctrl/mediatek/pinctrl-mt8195.c | 1 + - drivers/pinctrl/mediatek/pinctrl-mt8365.c | 1 + - drivers/pinctrl/mediatek/pinctrl-mt8516.c | 1 + - 22 files changed, 53 insertions(+), 5 deletions(-) - ---- a/drivers/pinctrl/mediatek/mtk-eint.c -+++ b/drivers/pinctrl/mediatek/mtk-eint.c -@@ -24,6 +24,7 @@ - #define MTK_EINT_EDGE_SENSITIVE 0 - #define MTK_EINT_LEVEL_SENSITIVE 1 - #define MTK_EINT_DBNC_SET_DBNC_BITS 4 -+#define MTK_EINT_DBNC_MAX 16 - #define MTK_EINT_DBNC_RST_BIT (0x1 << 1) - #define MTK_EINT_DBNC_SET_EN (0x1 << 0) - -@@ -48,6 +49,18 @@ static const struct mtk_eint_regs mtk_ge - .dbnc_clr = 0x700, - }; - -+const unsigned int debounce_time_mt2701[] = { -+ 500, 1000, 16000, 32000, 64000, 128000, 256000, 0 -+}; -+ -+const unsigned int debounce_time_mt6765[] = { -+ 125, 250, 500, 1000, 16000, 32000, 64000, 128000, 256000, 512000, 0 -+}; -+ -+const unsigned int debounce_time_mt6795[] = { -+ 500, 1000, 16000, 32000, 64000, 128000, 256000, 512000, 0 -+}; -+ - static void __iomem *mtk_eint_get_offset(struct mtk_eint *eint, - unsigned int eint_num, - unsigned int offset) -@@ -407,10 +420,11 @@ int mtk_eint_set_debounce(struct mtk_ein - int virq, eint_offset; - unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask, - dbnc; -- static const unsigned int debounce_time[] = {500, 1000, 16000, 32000, -- 64000, 128000, 256000}; - struct irq_data *d; - -+ if (!eint->hw->db_time) -+ return -EOPNOTSUPP; -+ - virq = irq_find_mapping(eint->domain, eint_num); - eint_offset = (eint_num % 4) * 8; - d = irq_get_irq_data(virq); -@@ -421,9 +435,9 @@ int mtk_eint_set_debounce(struct mtk_ein - if (!mtk_eint_can_en_debounce(eint, eint_num)) - return -EINVAL; - -- dbnc = ARRAY_SIZE(debounce_time); -- for (i = 0; i < ARRAY_SIZE(debounce_time); i++) { -- if (debounce <= debounce_time[i]) { -+ dbnc = eint->num_db_time; -+ for (i = 0; i < eint->num_db_time; i++) { -+ if (debounce <= eint->hw->db_time[i]) { - dbnc = i; - break; - } -@@ -497,6 +511,13 @@ int mtk_eint_do_init(struct mtk_eint *ei - if (!eint->domain) - return -ENOMEM; - -+ if (eint->hw->db_time) { -+ for (i = 0; i < MTK_EINT_DBNC_MAX; i++) -+ if (eint->hw->db_time[i] == 0) -+ break; -+ eint->num_db_time = i; -+ } -+ - mtk_eint_hw_init(eint); - for (i = 0; i < eint->hw->ap_num; i++) { - int virq = irq_create_mapping(eint->domain, i); ---- a/drivers/pinctrl/mediatek/mtk-eint.h -+++ b/drivers/pinctrl/mediatek/mtk-eint.h -@@ -37,8 +37,13 @@ struct mtk_eint_hw { - u8 ports; - unsigned int ap_num; - unsigned int db_cnt; -+ const unsigned int *db_time; - }; - -+extern const unsigned int debounce_time_mt2701[]; -+extern const unsigned int debounce_time_mt6765[]; -+extern const unsigned int debounce_time_mt6795[]; -+ - struct mtk_eint; - - struct mtk_eint_xt { -@@ -62,6 +67,7 @@ struct mtk_eint { - /* Used to fit into various EINT device */ - const struct mtk_eint_hw *hw; - const struct mtk_eint_regs *regs; -+ u16 num_db_time; - - /* Used to fit into various pinctrl device */ - void *pctl; ---- a/drivers/pinctrl/mediatek/pinctrl-mt2701.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c -@@ -531,6 +531,7 @@ static const struct mtk_pinctrl_devdata - .ports = 6, - .ap_num = 169, - .db_cnt = 16, -+ .db_time = debounce_time_mt2701, - }, - }; - ---- a/drivers/pinctrl/mediatek/pinctrl-mt2712.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt2712.c -@@ -584,6 +584,7 @@ static const struct mtk_pinctrl_devdata - .ports = 8, - .ap_num = 229, - .db_cnt = 40, -+ .db_time = debounce_time_mt2701, - }, - }; - ---- a/drivers/pinctrl/mediatek/pinctrl-mt6765.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt6765.c -@@ -1062,6 +1062,7 @@ static const struct mtk_eint_hw mt6765_e - .ports = 6, - .ap_num = 160, - .db_cnt = 13, -+ .db_time = debounce_time_mt6765, - }; - - static const struct mtk_pin_soc mt6765_data = { ---- a/drivers/pinctrl/mediatek/pinctrl-mt6779.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt6779.c -@@ -737,6 +737,7 @@ static const struct mtk_eint_hw mt6779_e - .ports = 6, - .ap_num = 195, - .db_cnt = 13, -+ .db_time = debounce_time_mt2701, - }; - - static const struct mtk_pin_soc mt6779_data = { ---- a/drivers/pinctrl/mediatek/pinctrl-mt7622.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c -@@ -846,6 +846,7 @@ static const struct mtk_eint_hw mt7622_e - .ports = 7, - .ap_num = ARRAY_SIZE(mt7622_pins), - .db_cnt = 20, -+ .db_time = debounce_time_mt6765, - }; - - static const struct mtk_pin_soc mt7622_data = { ---- a/drivers/pinctrl/mediatek/pinctrl-mt7623.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c -@@ -1369,6 +1369,7 @@ static const struct mtk_eint_hw mt7623_e - .ports = 6, - .ap_num = 169, - .db_cnt = 20, -+ .db_time = debounce_time_mt2701, - }; - - static struct mtk_pin_soc mt7623_data = { ---- a/drivers/pinctrl/mediatek/pinctrl-mt7629.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7629.c -@@ -402,6 +402,7 @@ static const struct mtk_eint_hw mt7629_e - .ports = 7, - .ap_num = ARRAY_SIZE(mt7629_pins), - .db_cnt = 16, -+ .db_time = debounce_time_mt2701, - }; - - static struct mtk_pin_soc mt7629_data = { ---- a/drivers/pinctrl/mediatek/pinctrl-mt8127.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt8127.c -@@ -300,6 +300,7 @@ static const struct mtk_pinctrl_devdata - .ports = 6, - .ap_num = 143, - .db_cnt = 16, -+ .db_time = debounce_time_mt2701, - }, - }; - ---- a/drivers/pinctrl/mediatek/pinctrl-mt8135.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c -@@ -313,6 +313,7 @@ static const struct mtk_pinctrl_devdata - .ports = 6, - .ap_num = 192, - .db_cnt = 16, -+ .db_time = debounce_time_mt2701, - }, - }; - ---- a/drivers/pinctrl/mediatek/pinctrl-mt8167.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt8167.c -@@ -332,6 +332,7 @@ static const struct mtk_pinctrl_devdata - .ports = 6, - .ap_num = 169, - .db_cnt = 64, -+ .db_time = debounce_time_mt6795, - }, - }; - ---- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c -@@ -340,6 +340,7 @@ static const struct mtk_pinctrl_devdata - .ports = 6, - .ap_num = 224, - .db_cnt = 16, -+ .db_time = debounce_time_mt2701, - }, - }; - ---- a/drivers/pinctrl/mediatek/pinctrl-mt8183.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt8183.c -@@ -545,6 +545,7 @@ static const struct mtk_eint_hw mt8183_e - .ports = 6, - .ap_num = 212, - .db_cnt = 13, -+ .db_time = debounce_time_mt6765, - }; - - static const struct mtk_pin_soc mt8183_data = { ---- a/drivers/pinctrl/mediatek/pinctrl-mt8192.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt8192.c -@@ -1339,6 +1339,7 @@ static const struct mtk_eint_hw mt8192_e - .ports = 7, - .ap_num = 224, - .db_cnt = 32, -+ .db_time = debounce_time_mt6765, - }; - - static const struct mtk_pin_reg_calc mt8192_reg_cals[PINCTRL_PIN_REG_MAX] = { ---- a/drivers/pinctrl/mediatek/pinctrl-mt8195.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt8195.c -@@ -805,6 +805,7 @@ static const struct mtk_eint_hw mt8195_e - .ports = 7, - .ap_num = 225, - .db_cnt = 32, -+ .db_time = debounce_time_mt6765, - }; - - static const struct mtk_pin_soc mt8195_data = { ---- a/drivers/pinctrl/mediatek/pinctrl-mt8365.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt8365.c -@@ -466,6 +466,7 @@ static const struct mtk_pinctrl_devdata - .ports = 5, - .ap_num = 160, - .db_cnt = 160, -+ .db_time = debounce_time_mt6765, - }, - }; - ---- a/drivers/pinctrl/mediatek/pinctrl-mt8516.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c -@@ -332,6 +332,7 @@ static const struct mtk_pinctrl_devdata - .ports = 6, - .ap_num = 169, - .db_cnt = 64, -+ .db_time = debounce_time_mt6795, - }, - }; - diff --git a/target/linux/mediatek/patches-6.1/825-v6.1-pinctrl-mediatek-Export-debounce-time-tables.patch b/target/linux/mediatek/patches-6.1/825-v6.1-pinctrl-mediatek-Export-debounce-time-tables.patch deleted file mode 100644 index 92f4e842e8a..00000000000 --- a/target/linux/mediatek/patches-6.1/825-v6.1-pinctrl-mediatek-Export-debounce-time-tables.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 2e35b25dd8e666b8619355fc3defb1b246a5dc02 Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Tue, 15 Nov 2022 09:11:07 +0100 -Subject: [PATCH] pinctrl: mediatek: Export debounce time tables - -The kernel test robot complains that in certain combinations -when building the Mediatek drivers as modules we lack some -debounce table symbols, so export them. - -Reported-by: kernel test robot -Fixes: e1ff91f9d230 ("pinctrl: mediatek: Fix EINT pins input debounce time configuration") -Cc: AngeloGioacchino Del Regno -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/mediatek/mtk-eint.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/pinctrl/mediatek/mtk-eint.c -+++ b/drivers/pinctrl/mediatek/mtk-eint.c -@@ -52,14 +52,17 @@ static const struct mtk_eint_regs mtk_ge - const unsigned int debounce_time_mt2701[] = { - 500, 1000, 16000, 32000, 64000, 128000, 256000, 0 - }; -+EXPORT_SYMBOL_GPL(debounce_time_mt2701); - - const unsigned int debounce_time_mt6765[] = { - 125, 250, 500, 1000, 16000, 32000, 64000, 128000, 256000, 512000, 0 - }; -+EXPORT_SYMBOL_GPL(debounce_time_mt6765); - - const unsigned int debounce_time_mt6795[] = { - 500, 1000, 16000, 32000, 64000, 128000, 256000, 512000, 0 - }; -+EXPORT_SYMBOL_GPL(debounce_time_mt6795); - - static void __iomem *mtk_eint_get_offset(struct mtk_eint *eint, - unsigned int eint_num, diff --git a/target/linux/mediatek/patches-6.1/830-v5.18-regulator-Add-bindings-for-Richtek-RT5190A-PMIC.patch b/target/linux/mediatek/patches-6.1/830-v5.18-regulator-Add-bindings-for-Richtek-RT5190A-PMIC.patch deleted file mode 100644 index 30891d34872..00000000000 --- a/target/linux/mediatek/patches-6.1/830-v5.18-regulator-Add-bindings-for-Richtek-RT5190A-PMIC.patch +++ /dev/null @@ -1,180 +0,0 @@ -From b77e70f6b8f2cc62fba847f3008a430a09ef275d Mon Sep 17 00:00:00 2001 -From: ChiYuan Huang -Date: Wed, 9 Mar 2022 16:01:42 +0800 -Subject: [PATCH 1/2] regulator: Add bindings for Richtek RT5190A PMIC - -Add bindings for Richtek RT5190A PMIC. - -Signed-off-by: ChiYuan Huang -Reviewed-by: Krzysztof Kozlowski -Link: https://lore.kernel.org/r/1646812903-32496-2-git-send-email-u0084500@gmail.com -Signed-off-by: Mark Brown ---- - .../regulator/richtek,rt5190a-regulator.yaml | 141 ++++++++++++++++++ - .../regulator/richtek,rt5190a-regulator.h | 15 ++ - 2 files changed, 156 insertions(+) - create mode 100644 Documentation/devicetree/bindings/regulator/richtek,rt5190a-regulator.yaml - create mode 100644 include/dt-bindings/regulator/richtek,rt5190a-regulator.h - ---- /dev/null -+++ b/Documentation/devicetree/bindings/regulator/richtek,rt5190a-regulator.yaml -@@ -0,0 +1,141 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/regulator/richtek,rt5190a-regulator.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Richtek RT5190A PMIC Regulator -+ -+maintainers: -+ - ChiYuan Huang -+ -+description: | -+ The RT5190A integrates 1 channel buck controller, 3 channels high efficiency -+ synchronous buck converters, 1 LDO, I2C control interface and peripherial -+ logical control. -+ -+ It also supports mute AC OFF depop sound and quick setting storage while -+ input power is removed. -+ -+properties: -+ compatible: -+ enum: -+ - richtek,rt5190a -+ -+ reg: -+ maxItems: 1 -+ -+ interrupts: -+ maxItems: 1 -+ -+ vin2-supply: -+ description: phandle to buck2 input voltage. -+ -+ vin3-supply: -+ description: phandle to buck3 input voltage. -+ -+ vin4-supply: -+ description: phandle to buck4 input voltage. -+ -+ vinldo-supply: -+ description: phandle to ldo input voltage -+ -+ richtek,mute-enable: -+ description: | -+ The mute function uses 'mutein', 'muteout', and 'vdet' pins as the control -+ signal. When enabled, The normal behavior is to bypass the 'mutein' signal -+ 'muteout'. But if the power source removal is detected from 'vdet', -+ whatever the 'mutein' signal is, it will pull down the 'muteout' to force -+ speakers mute. this function is commonly used to prevent the speaker pop -+ noise during AC power turned off in the modern TV system design. -+ type: boolean -+ -+ regulators: -+ type: object -+ -+ patternProperties: -+ "^buck[1-4]$|^ldo$": -+ type: object -+ $ref: regulator.yaml# -+ description: | -+ regulator description for buck1 and buck4. -+ -+ properties: -+ regulator-allowed-modes: -+ description: | -+ buck operating mode, only buck1/4 support mode operating. -+ 0: auto mode -+ 1: force pwm mode -+ items: -+ enum: [0, 1] -+ -+ richtek,latchup-enable: -+ type: boolean -+ description: | -+ If specified, undervolt protection mode changes from the default -+ hiccup to latchup. -+ -+ unevaluatedProperties: false -+ -+ additionalProperties: false -+ -+required: -+ - compatible -+ - reg -+ - regulators -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ #include -+ -+ i2c { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ pmic@64 { -+ compatible = "richtek,rt5190a"; -+ reg = <0x64>; -+ interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>; -+ vin2-supply = <&rt5190_buck1>; -+ vin3-supply = <&rt5190_buck1>; -+ vin4-supply = <&rt5190_buck1>; -+ -+ regulators { -+ rt5190_buck1: buck1 { -+ regulator-name = "rt5190a-buck1"; -+ regulator-min-microvolt = <5090000>; -+ regulator-max-microvolt = <5090000>; -+ regulator-allowed-modes = ; -+ regulator-boot-on; -+ }; -+ buck2 { -+ regulator-name = "rt5190a-buck2"; -+ regulator-min-microvolt = <600000>; -+ regulator-max-microvolt = <1400000>; -+ regulator-boot-on; -+ }; -+ buck3 { -+ regulator-name = "rt5190a-buck3"; -+ regulator-min-microvolt = <600000>; -+ regulator-max-microvolt = <1400000>; -+ regulator-boot-on; -+ }; -+ buck4 { -+ regulator-name = "rt5190a-buck4"; -+ regulator-min-microvolt = <850000>; -+ regulator-max-microvolt = <850000>; -+ regulator-allowed-modes = ; -+ regulator-boot-on; -+ }; -+ ldo { -+ regulator-name = "rt5190a-ldo"; -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <1200000>; -+ regulator-boot-on; -+ }; -+ }; -+ }; -+ }; ---- /dev/null -+++ b/include/dt-bindings/regulator/richtek,rt5190a-regulator.h -@@ -0,0 +1,15 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+ -+#ifndef __DT_BINDINGS_RICHTEK_RT5190A_REGULATOR_H__ -+#define __DT_BINDINGS_RICHTEK_RT5190A_REGULATOR_H__ -+ -+/* -+ * BUCK/LDO mode constants which may be used in devicetree properties -+ * (eg. regulator-allowed-modes). -+ * See the manufacturer's datasheet for more information on these modes. -+ */ -+ -+#define RT5190A_OPMODE_AUTO 0 -+#define RT5190A_OPMODE_FPWM 1 -+ -+#endif diff --git a/target/linux/mediatek/patches-6.1/831-v5.18-regulator-rt5190a-Add-support-for-Richtek-RT5190A-PM.patch b/target/linux/mediatek/patches-6.1/831-v5.18-regulator-rt5190a-Add-support-for-Richtek-RT5190A-PM.patch deleted file mode 100644 index 0e0f099e505..00000000000 --- a/target/linux/mediatek/patches-6.1/831-v5.18-regulator-rt5190a-Add-support-for-Richtek-RT5190A-PM.patch +++ /dev/null @@ -1,562 +0,0 @@ -From 760423dfad53877b468490758fe7ea968ded9402 Mon Sep 17 00:00:00 2001 -From: ChiYuan Huang -Date: Wed, 9 Mar 2022 16:01:43 +0800 -Subject: [PATCH 2/2] regulator: rt5190a: Add support for Richtek RT5190A PMIC - -Add support for Richtek RT5190A PMIC. - -Signed-off-by: ChiYuan Huang -Link: https://lore.kernel.org/r/1646812903-32496-3-git-send-email-u0084500@gmail.com -Signed-off-by: Mark Brown ---- - drivers/regulator/Kconfig | 10 + - drivers/regulator/Makefile | 1 + - drivers/regulator/rt5190a-regulator.c | 513 ++++++++++++++++++++++++++ - 3 files changed, 524 insertions(+) - create mode 100644 drivers/regulator/rt5190a-regulator.c - ---- a/drivers/regulator/Kconfig -+++ b/drivers/regulator/Kconfig -@@ -1037,6 +1037,16 @@ config REGULATOR_RT5033 - RT5033 PMIC. The device supports multiple regulators like - current source, LDO and Buck. - -+config REGULATOR_RT5190A -+ tristate "Richtek RT5190A PMIC" -+ depends on I2C -+ select REGMAP_I2C -+ help -+ This adds support for voltage regulator in Richtek RT5190A PMIC. -+ It integratas 1 channel buck controller, 3 channels high efficiency -+ buck converters, 1 LDO, mute AC OFF depop function, with the general -+ I2C control interface. -+ - config REGULATOR_RT6160 - tristate "Richtek RT6160 BuckBoost voltage regulator" - depends on I2C ---- a/drivers/regulator/Makefile -+++ b/drivers/regulator/Makefile -@@ -125,6 +125,7 @@ obj-$(CONFIG_REGULATOR_ROHM) += rohm-reg - obj-$(CONFIG_REGULATOR_RT4801) += rt4801-regulator.o - obj-$(CONFIG_REGULATOR_RT4831) += rt4831-regulator.o - obj-$(CONFIG_REGULATOR_RT5033) += rt5033-regulator.o -+obj-$(CONFIG_REGULATOR_RT5190A) += rt5190a-regulator.o - obj-$(CONFIG_REGULATOR_RT6160) += rt6160-regulator.o - obj-$(CONFIG_REGULATOR_RT6245) += rt6245-regulator.o - obj-$(CONFIG_REGULATOR_RTMV20) += rtmv20-regulator.o ---- /dev/null -+++ b/drivers/regulator/rt5190a-regulator.c -@@ -0,0 +1,513 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define RT5190A_REG_MANUFACTURE 0x00 -+#define RT5190A_REG_BUCK2VSEL 0x04 -+#define RT5190A_REG_BUCK3VSEL 0x05 -+#define RT5190A_REG_DCDCCNTL 0x06 -+#define RT5190A_REG_ENABLE 0x07 -+#define RT5190A_REG_DISCHARGE 0x09 -+#define RT5190A_REG_PROTMODE 0x0A -+#define RT5190A_REG_MUTECNTL 0x0B -+#define RT5190A_REG_PGSTAT 0x0F -+#define RT5190A_REG_OVINT 0x10 -+#define RT5190A_REG_HOTDIEMASK 0x17 -+ -+#define RT5190A_VSEL_MASK GENMASK(6, 0) -+#define RT5190A_RID_BITMASK(rid) BIT(rid + 1) -+#define RT5190A_BUCK1_DISCHG_MASK GENMASK(1, 0) -+#define RT5190A_BUCK1_DISCHG_ONVAL 0x01 -+#define RT5190A_OVERVOLT_MASK GENMASK(7, 0) -+#define RT5190A_UNDERVOLT_MASK GENMASK(15, 8) -+#define RT5190A_CH234OT_MASK BIT(29) -+#define RT5190A_CHIPOT_MASK BIT(28) -+ -+#define RT5190A_BUCK23_MINUV 600000 -+#define RT5190A_BUCK23_MAXUV 1400000 -+#define RT5190A_BUCK23_STEPUV 10000 -+#define RT5190A_BUCK23_STEPNUM ((1400000 - 600000) / 10000 + 1) -+ -+enum { -+ RT5190A_IDX_BUCK1 = 0, -+ RT5190A_IDX_BUCK2, -+ RT5190A_IDX_BUCK3, -+ RT5190A_IDX_BUCK4, -+ RT5190A_IDX_LDO, -+ RT5190A_MAX_IDX -+}; -+ -+struct rt5190a_priv { -+ struct device *dev; -+ struct regmap *regmap; -+ struct regulator_desc rdesc[RT5190A_MAX_IDX]; -+ struct regulator_dev *rdev[RT5190A_MAX_IDX]; -+}; -+ -+static int rt5190a_get_error_flags(struct regulator_dev *rdev, -+ unsigned int *flags) -+{ -+ struct regmap *regmap = rdev_get_regmap(rdev); -+ int rid = rdev_get_id(rdev); -+ unsigned int pgood_stat; -+ int ret; -+ -+ ret = regmap_read(regmap, RT5190A_REG_PGSTAT, &pgood_stat); -+ if (ret) -+ return ret; -+ -+ if (!(pgood_stat & RT5190A_RID_BITMASK(rid))) -+ *flags = REGULATOR_ERROR_FAIL; -+ else -+ *flags = 0; -+ -+ return 0; -+} -+ -+static int rt5190a_fixed_buck_set_mode(struct regulator_dev *rdev, -+ unsigned int mode) -+{ -+ struct regmap *regmap = rdev_get_regmap(rdev); -+ int rid = rdev_get_id(rdev); -+ unsigned int mask = RT5190A_RID_BITMASK(rid), val; -+ -+ switch (mode) { -+ case REGULATOR_MODE_FAST: -+ val = mask; -+ break; -+ case REGULATOR_MODE_NORMAL: -+ val = 0; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ return regmap_update_bits(regmap, RT5190A_REG_DCDCCNTL, mask, val); -+} -+ -+static unsigned int rt5190a_fixed_buck_get_mode(struct regulator_dev *rdev) -+{ -+ struct regmap *regmap = rdev_get_regmap(rdev); -+ int rid = rdev_get_id(rdev); -+ unsigned int val; -+ int ret; -+ -+ ret = regmap_read(regmap, RT5190A_REG_DCDCCNTL, &val); -+ if (ret) { -+ dev_err(&rdev->dev, "Failed to get mode [%d]\n", ret); -+ return ret; -+ } -+ -+ if (val & RT5190A_RID_BITMASK(rid)) -+ return REGULATOR_MODE_FAST; -+ -+ return REGULATOR_MODE_NORMAL; -+} -+ -+static const struct regulator_ops rt5190a_ranged_buck_ops = { -+ .enable = regulator_enable_regmap, -+ .disable = regulator_disable_regmap, -+ .is_enabled = regulator_is_enabled_regmap, -+ .set_voltage_sel = regulator_set_voltage_sel_regmap, -+ .get_voltage_sel = regulator_get_voltage_sel_regmap, -+ .list_voltage = regulator_list_voltage_linear, -+ .set_active_discharge = regulator_set_active_discharge_regmap, -+ .get_error_flags = rt5190a_get_error_flags, -+}; -+ -+static const struct regulator_ops rt5190a_fixed_buck_ops = { -+ .enable = regulator_enable_regmap, -+ .disable = regulator_disable_regmap, -+ .is_enabled = regulator_is_enabled_regmap, -+ .set_active_discharge = regulator_set_active_discharge_regmap, -+ .set_mode = rt5190a_fixed_buck_set_mode, -+ .get_mode = rt5190a_fixed_buck_get_mode, -+ .get_error_flags = rt5190a_get_error_flags, -+}; -+ -+static const struct regulator_ops rt5190a_fixed_ldo_ops = { -+ .enable = regulator_enable_regmap, -+ .disable = regulator_disable_regmap, -+ .is_enabled = regulator_is_enabled_regmap, -+ .set_active_discharge = regulator_set_active_discharge_regmap, -+ .get_error_flags = rt5190a_get_error_flags, -+}; -+ -+static irqreturn_t rt5190a_irq_handler(int irq, void *data) -+{ -+ struct rt5190a_priv *priv = data; -+ __le32 raws; -+ unsigned int events, fields; -+ static const struct { -+ unsigned int bitmask; -+ unsigned int report; -+ } event_tbl[] = { -+ { RT5190A_OVERVOLT_MASK, REGULATOR_ERROR_REGULATION_OUT }, -+ { RT5190A_UNDERVOLT_MASK, REGULATOR_ERROR_UNDER_VOLTAGE } -+ }; -+ int i, j, ret; -+ -+ ret = regmap_raw_read(priv->regmap, RT5190A_REG_OVINT, &raws, -+ sizeof(raws)); -+ if (ret) { -+ dev_err(priv->dev, "Failed to read events\n"); -+ return IRQ_NONE; -+ } -+ -+ events = le32_to_cpu(raws); -+ -+ ret = regmap_raw_write(priv->regmap, RT5190A_REG_OVINT, &raws, -+ sizeof(raws)); -+ if (ret) -+ dev_err(priv->dev, "Failed to write-clear events\n"); -+ -+ /* Handle OV,UV events */ -+ for (i = 0; i < ARRAY_SIZE(event_tbl); i++) { -+ fields = events & event_tbl[i].bitmask; -+ fields >>= ffs(event_tbl[i].bitmask) - 1; -+ -+ for (j = 0; j < RT5190A_MAX_IDX; j++) { -+ if (!(fields & RT5190A_RID_BITMASK(j))) -+ continue; -+ -+ regulator_notifier_call_chain(priv->rdev[j], -+ event_tbl[i].report, -+ NULL); -+ } -+ } -+ -+ /* Handle CH234 OT event */ -+ if (events & RT5190A_CH234OT_MASK) { -+ for (j = RT5190A_IDX_BUCK2; j < RT5190A_IDX_LDO; j++) { -+ regulator_notifier_call_chain(priv->rdev[j], -+ REGULATOR_ERROR_OVER_TEMP, -+ NULL); -+ } -+ } -+ -+ /* Warning if CHIP OT occur */ -+ if (events & RT5190A_CHIPOT_MASK) -+ dev_warn(priv->dev, "CHIP overheat\n"); -+ -+ return IRQ_HANDLED; -+} -+ -+static unsigned int rt5190a_of_map_mode(unsigned int mode) -+{ -+ switch (mode) { -+ case RT5190A_OPMODE_AUTO: -+ return REGULATOR_MODE_NORMAL; -+ case RT5190A_OPMODE_FPWM: -+ return REGULATOR_MODE_FAST; -+ default: -+ return REGULATOR_MODE_INVALID; -+ } -+} -+ -+static int rt5190a_of_parse_cb(struct rt5190a_priv *priv, int rid, -+ struct of_regulator_match *match) -+{ -+ struct regulator_desc *desc = priv->rdesc + rid; -+ struct regulator_init_data *init_data = match->init_data; -+ struct device_node *np = match->of_node; -+ bool latchup_enable; -+ unsigned int mask = RT5190A_RID_BITMASK(rid), val; -+ -+ switch (rid) { -+ case RT5190A_IDX_BUCK1: -+ case RT5190A_IDX_BUCK4: -+ case RT5190A_IDX_LDO: -+ init_data->constraints.apply_uV = 0; -+ -+ if (init_data->constraints.min_uV == -+ init_data->constraints.max_uV) -+ desc->fixed_uV = init_data->constraints.min_uV; -+ else { -+ dev_err(priv->dev, -+ "Variable voltage for fixed regulator\n"); -+ return -EINVAL; -+ } -+ break; -+ default: -+ break; -+ } -+ -+ latchup_enable = of_property_read_bool(np, "richtek,latchup-enable"); -+ -+ /* latchup: 0, default hiccup: 1 */ -+ val = !latchup_enable ? mask : 0; -+ -+ return regmap_update_bits(priv->regmap, RT5190A_REG_PROTMODE, mask, val); -+} -+ -+static void rt5190a_fillin_regulator_desc(struct regulator_desc *desc, int rid) -+{ -+ static const char * const regu_name[] = { "buck1", "buck2", -+ "buck3", "buck4", -+ "ldo" }; -+ static const char * const supply[] = { NULL, "vin2", "vin3", "vin4", -+ "vinldo" }; -+ -+ desc->name = regu_name[rid]; -+ desc->supply_name = supply[rid]; -+ desc->owner = THIS_MODULE; -+ desc->type = REGULATOR_VOLTAGE; -+ desc->id = rid; -+ desc->enable_reg = RT5190A_REG_ENABLE; -+ desc->enable_mask = RT5190A_RID_BITMASK(rid); -+ desc->active_discharge_reg = RT5190A_REG_DISCHARGE; -+ desc->active_discharge_mask = RT5190A_RID_BITMASK(rid); -+ desc->active_discharge_on = RT5190A_RID_BITMASK(rid); -+ -+ switch (rid) { -+ case RT5190A_IDX_BUCK1: -+ desc->active_discharge_mask = RT5190A_BUCK1_DISCHG_MASK; -+ desc->active_discharge_on = RT5190A_BUCK1_DISCHG_ONVAL; -+ desc->n_voltages = 1; -+ desc->ops = &rt5190a_fixed_buck_ops; -+ desc->of_map_mode = rt5190a_of_map_mode; -+ break; -+ case RT5190A_IDX_BUCK2: -+ desc->vsel_reg = RT5190A_REG_BUCK2VSEL; -+ desc->vsel_mask = RT5190A_VSEL_MASK; -+ desc->min_uV = RT5190A_BUCK23_MINUV; -+ desc->uV_step = RT5190A_BUCK23_STEPUV; -+ desc->n_voltages = RT5190A_BUCK23_STEPNUM; -+ desc->ops = &rt5190a_ranged_buck_ops; -+ break; -+ case RT5190A_IDX_BUCK3: -+ desc->vsel_reg = RT5190A_REG_BUCK3VSEL; -+ desc->vsel_mask = RT5190A_VSEL_MASK; -+ desc->min_uV = RT5190A_BUCK23_MINUV; -+ desc->uV_step = RT5190A_BUCK23_STEPUV; -+ desc->n_voltages = RT5190A_BUCK23_STEPNUM; -+ desc->ops = &rt5190a_ranged_buck_ops; -+ break; -+ case RT5190A_IDX_BUCK4: -+ desc->n_voltages = 1; -+ desc->ops = &rt5190a_fixed_buck_ops; -+ desc->of_map_mode = rt5190a_of_map_mode; -+ break; -+ case RT5190A_IDX_LDO: -+ desc->n_voltages = 1; -+ desc->ops = &rt5190a_fixed_ldo_ops; -+ break; -+ } -+} -+ -+static struct of_regulator_match rt5190a_regulator_match[] = { -+ { .name = "buck1", }, -+ { .name = "buck2", }, -+ { .name = "buck3", }, -+ { .name = "buck4", }, -+ { .name = "ldo", } -+}; -+ -+static int rt5190a_parse_regulator_dt_data(struct rt5190a_priv *priv) -+{ -+ struct device_node *regulator_np; -+ struct regulator_desc *reg_desc; -+ struct of_regulator_match *match; -+ int i, ret; -+ -+ for (i = 0; i < RT5190A_MAX_IDX; i++) { -+ reg_desc = priv->rdesc + i; -+ match = rt5190a_regulator_match + i; -+ -+ rt5190a_fillin_regulator_desc(reg_desc, i); -+ -+ match->desc = reg_desc; -+ } -+ -+ regulator_np = of_get_child_by_name(priv->dev->of_node, "regulators"); -+ if (!regulator_np) { -+ dev_err(priv->dev, "Could not find 'regulators' node\n"); -+ return -ENODEV; -+ } -+ -+ ret = of_regulator_match(priv->dev, regulator_np, -+ rt5190a_regulator_match, -+ ARRAY_SIZE(rt5190a_regulator_match)); -+ -+ of_node_put(regulator_np); -+ -+ if (ret < 0) { -+ dev_err(priv->dev, -+ "Error parsing regulator init data: %d\n", ret); -+ return ret; -+ } -+ -+ for (i = 0; i < RT5190A_MAX_IDX; i++) { -+ match = rt5190a_regulator_match + i; -+ -+ ret = rt5190a_of_parse_cb(priv, i, match); -+ if (ret) { -+ dev_err(priv->dev, "Failed in [%d] of_parse_cb\n", i); -+ return ret; -+ } -+ } -+ -+ return 0; -+} -+ -+static const struct reg_sequence rt5190a_init_patch[] = { -+ { 0x09, 0x3d, }, -+ { 0x0a, 0x3e, }, -+ { 0x0b, 0x01, }, -+ { 0x10, 0xff, }, -+ { 0x11, 0xff, }, -+ { 0x12, 0xff, }, -+ { 0x13, 0xff, }, -+ { 0x14, 0, }, -+ { 0x15, 0, }, -+ { 0x16, 0x3e, }, -+ { 0x17, 0, } -+}; -+ -+static int rt5190a_device_initialize(struct rt5190a_priv *priv) -+{ -+ bool mute_enable; -+ int ret; -+ -+ ret = regmap_register_patch(priv->regmap, rt5190a_init_patch, -+ ARRAY_SIZE(rt5190a_init_patch)); -+ if (ret) { -+ dev_err(priv->dev, "Failed to do register patch\n"); -+ return ret; -+ } -+ -+ mute_enable = device_property_read_bool(priv->dev, -+ "richtek,mute-enable"); -+ -+ if (mute_enable) { -+ ret = regmap_write(priv->regmap, RT5190A_REG_MUTECNTL, 0x00); -+ if (ret) { -+ dev_err(priv->dev, "Failed to enable mute function\n"); -+ return ret; -+ } -+ } -+ -+ return 0; -+} -+ -+static int rt5190a_device_check(struct rt5190a_priv *priv) -+{ -+ u16 devid; -+ int ret; -+ -+ ret = regmap_raw_read(priv->regmap, RT5190A_REG_MANUFACTURE, &devid, -+ sizeof(devid)); -+ if (ret) -+ return ret; -+ -+ if (devid) { -+ dev_err(priv->dev, "Incorrect device id 0x%04x\n", devid); -+ return -ENODEV; -+ } -+ -+ return 0; -+} -+ -+static const struct regmap_config rt5190a_regmap_config = { -+ .reg_bits = 8, -+ .val_bits = 8, -+ .max_register = RT5190A_REG_HOTDIEMASK, -+}; -+ -+static int rt5190a_probe(struct i2c_client *i2c) -+{ -+ struct rt5190a_priv *priv; -+ struct regulator_config cfg = {}; -+ int i, ret; -+ -+ priv = devm_kzalloc(&i2c->dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ priv->dev = &i2c->dev; -+ -+ priv->regmap = devm_regmap_init_i2c(i2c, &rt5190a_regmap_config); -+ if (IS_ERR(priv->regmap)) { -+ dev_err(&i2c->dev, "Failed to allocate regmap\n"); -+ return PTR_ERR(priv->regmap); -+ } -+ -+ ret = rt5190a_device_check(priv); -+ if (ret) { -+ dev_err(&i2c->dev, "Failed to check device %d\n", ret); -+ return ret; -+ } -+ -+ ret = rt5190a_device_initialize(priv); -+ if (ret) { -+ dev_err(&i2c->dev, "Failed to initialize the device\n"); -+ return ret; -+ } -+ -+ ret = rt5190a_parse_regulator_dt_data(priv); -+ if (ret) { -+ dev_err(&i2c->dev, "Failed to parse regulator dt\n"); -+ return ret; -+ } -+ -+ cfg.dev = &i2c->dev; -+ cfg.regmap = priv->regmap; -+ -+ for (i = 0; i < RT5190A_MAX_IDX; i++) { -+ struct regulator_desc *desc = priv->rdesc + i; -+ struct of_regulator_match *match = rt5190a_regulator_match + i; -+ -+ cfg.init_data = match->init_data; -+ cfg.of_node = match->of_node; -+ -+ priv->rdev[i] = devm_regulator_register(&i2c->dev, desc, &cfg); -+ if (IS_ERR(priv->rdev[i])) { -+ dev_err(&i2c->dev, "Failed to register regulator %s\n", -+ desc->name); -+ return PTR_ERR(priv->rdev[i]); -+ } -+ } -+ -+ if (i2c->irq) { -+ ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, -+ rt5190a_irq_handler, -+ IRQF_ONESHOT, -+ dev_name(&i2c->dev), priv); -+ if (ret) { -+ dev_err(&i2c->dev, "Failed to register interrupt\n"); -+ return ret; -+ } -+ } -+ -+ return 0; -+} -+ -+static const struct of_device_id __maybe_unused rt5190a_device_table[] = { -+ { .compatible = "richtek,rt5190a", }, -+ {} -+}; -+MODULE_DEVICE_TABLE(of, rt5190a_device_table); -+ -+static struct i2c_driver rt5190a_driver = { -+ .driver = { -+ .name = "rt5190a", -+ .of_match_table = rt5190a_device_table, -+ }, -+ .probe_new = rt5190a_probe, -+}; -+module_i2c_driver(rt5190a_driver); -+ -+MODULE_AUTHOR("ChiYuan Huang "); -+MODULE_DESCRIPTION("Richtek RT5190A Regulator Driver"); -+MODULE_LICENSE("GPL v2"); diff --git a/target/linux/mediatek/patches-6.1/840-v5.16-i2c-mediatek-Reset-the-handshake-signal-between-i2c-.patch b/target/linux/mediatek/patches-6.1/840-v5.16-i2c-mediatek-Reset-the-handshake-signal-between-i2c-.patch deleted file mode 100644 index 8b011964098..00000000000 --- a/target/linux/mediatek/patches-6.1/840-v5.16-i2c-mediatek-Reset-the-handshake-signal-between-i2c-.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 95e4dfbf33dc0a0843ba20db811f7ea271235e1e Mon Sep 17 00:00:00 2001 -From: Kewei Xu -Date: Sun, 10 Oct 2021 15:05:12 +0800 -Subject: [PATCH 01/16] i2c: mediatek: Reset the handshake signal between i2c - and dma - -Due to changes in the hardware design of the handshaking signal -between i2c and dma, it is necessary to reset the handshaking -signal before each transfer to ensure that the multi-msgs can -be transferred correctly. - -Signed-off-by: Kewei Xu -Reviewed-by: Qii Wang -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 26 ++++++++++++++++++++++++++ - 1 file changed, 26 insertions(+) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -15,6 +15,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -49,6 +50,8 @@ - #define I2C_RD_TRANAC_VALUE 0x0001 - #define I2C_SCL_MIS_COMP_VALUE 0x0000 - #define I2C_CHN_CLR_FLAG 0x0000 -+#define I2C_RELIABILITY 0x0010 -+#define I2C_DMAACK_ENABLE 0x0008 - - #define I2C_DMA_CON_TX 0x0000 - #define I2C_DMA_CON_RX 0x0001 -@@ -851,6 +854,7 @@ static int mtk_i2c_do_transfer(struct mt - u16 restart_flag = 0; - u16 dma_sync = 0; - u32 reg_4g_mode; -+ u32 reg_dma_reset; - u8 *dma_rd_buf = NULL; - u8 *dma_wr_buf = NULL; - dma_addr_t rpaddr = 0; -@@ -864,6 +868,28 @@ static int mtk_i2c_do_transfer(struct mt - - reinit_completion(&i2c->msg_complete); - -+ if (i2c->dev_comp->apdma_sync && -+ i2c->op != I2C_MASTER_WRRD && num > 1) { -+ mtk_i2c_writew(i2c, 0x00, OFFSET_DEBUGCTRL); -+ writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_WARM_RST, -+ i2c->pdmabase + OFFSET_RST); -+ -+ ret = readw_poll_timeout(i2c->pdmabase + OFFSET_RST, -+ reg_dma_reset, -+ !(reg_dma_reset & I2C_DMA_WARM_RST), -+ 0, 100); -+ if (ret) { -+ dev_err(i2c->dev, "DMA warm reset timeout\n"); -+ return -ETIMEDOUT; -+ } -+ -+ writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); -+ mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST, OFFSET_SOFTRESET); -+ mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET); -+ mtk_i2c_writew(i2c, I2C_RELIABILITY | I2C_DMAACK_ENABLE, -+ OFFSET_DEBUGCTRL); -+ } -+ - control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) & - ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS); - if ((i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) || (left_num >= 1)) diff --git a/target/linux/mediatek/patches-6.1/841-v5.16-i2c-mediatek-Dump-i2c-dma-register-when-a-timeout-oc.patch b/target/linux/mediatek/patches-6.1/841-v5.16-i2c-mediatek-Dump-i2c-dma-register-when-a-timeout-oc.patch deleted file mode 100644 index a2d2521c772..00000000000 --- a/target/linux/mediatek/patches-6.1/841-v5.16-i2c-mediatek-Dump-i2c-dma-register-when-a-timeout-oc.patch +++ /dev/null @@ -1,102 +0,0 @@ -From 5b8e29e566e086ef9b5b9ea0d054370a295e1d05 Mon Sep 17 00:00:00 2001 -From: Kewei Xu -Date: Sun, 10 Oct 2021 15:05:13 +0800 -Subject: [PATCH 02/16] i2c: mediatek: Dump i2c/dma register when a timeout - occurs - -When a timeout error occurs in i2c transter, it is usually related -to the i2c/dma IP hardware configuration. Therefore, the purpose of -this patch is to dump the key register values of i2c/dma when a -timeout occurs in i2c for debugging. - -Signed-off-by: Kewei Xu -Reviewed-by: Qii Wang -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 54 +++++++++++++++++++++++++++++++++ - 1 file changed, 54 insertions(+) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -130,6 +130,7 @@ enum I2C_REGS_OFFSET { - OFFSET_HS, - OFFSET_SOFTRESET, - OFFSET_DCM_EN, -+ OFFSET_MULTI_DMA, - OFFSET_PATH_DIR, - OFFSET_DEBUGSTAT, - OFFSET_DEBUGCTRL, -@@ -197,6 +198,7 @@ static const u16 mt_i2c_regs_v2[] = { - [OFFSET_TRANSFER_LEN_AUX] = 0x44, - [OFFSET_CLOCK_DIV] = 0x48, - [OFFSET_SOFTRESET] = 0x50, -+ [OFFSET_MULTI_DMA] = 0x8c, - [OFFSET_SCL_MIS_COMP_POINT] = 0x90, - [OFFSET_DEBUGSTAT] = 0xe4, - [OFFSET_DEBUGCTRL] = 0xe8, -@@ -845,6 +847,57 @@ static int mtk_i2c_set_speed(struct mtk_ - return 0; - } - -+static void i2c_dump_register(struct mtk_i2c *i2c) -+{ -+ dev_dbg(i2c->dev, "SLAVE_ADDR: 0x%x, INTR_MASK: 0x%x\n", -+ mtk_i2c_readw(i2c, OFFSET_SLAVE_ADDR), -+ mtk_i2c_readw(i2c, OFFSET_INTR_MASK)); -+ dev_dbg(i2c->dev, "INTR_STAT: 0x%x, CONTROL: 0x%x\n", -+ mtk_i2c_readw(i2c, OFFSET_INTR_STAT), -+ mtk_i2c_readw(i2c, OFFSET_CONTROL)); -+ dev_dbg(i2c->dev, "TRANSFER_LEN: 0x%x, TRANSAC_LEN: 0x%x\n", -+ mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN), -+ mtk_i2c_readw(i2c, OFFSET_TRANSAC_LEN)); -+ dev_dbg(i2c->dev, "DELAY_LEN: 0x%x, HTIMING: 0x%x\n", -+ mtk_i2c_readw(i2c, OFFSET_DELAY_LEN), -+ mtk_i2c_readw(i2c, OFFSET_TIMING)); -+ dev_dbg(i2c->dev, "START: 0x%x, EXT_CONF: 0x%x\n", -+ mtk_i2c_readw(i2c, OFFSET_START), -+ mtk_i2c_readw(i2c, OFFSET_EXT_CONF)); -+ dev_dbg(i2c->dev, "HS: 0x%x, IO_CONFIG: 0x%x\n", -+ mtk_i2c_readw(i2c, OFFSET_HS), -+ mtk_i2c_readw(i2c, OFFSET_IO_CONFIG)); -+ dev_dbg(i2c->dev, "DCM_EN: 0x%x, TRANSFER_LEN_AUX: 0x%x\n", -+ mtk_i2c_readw(i2c, OFFSET_DCM_EN), -+ mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN_AUX)); -+ dev_dbg(i2c->dev, "CLOCK_DIV: 0x%x, FIFO_STAT: 0x%x\n", -+ mtk_i2c_readw(i2c, OFFSET_CLOCK_DIV), -+ mtk_i2c_readw(i2c, OFFSET_FIFO_STAT)); -+ dev_dbg(i2c->dev, "DEBUGCTRL : 0x%x, DEBUGSTAT: 0x%x\n", -+ mtk_i2c_readw(i2c, OFFSET_DEBUGCTRL), -+ mtk_i2c_readw(i2c, OFFSET_DEBUGSTAT)); -+ if (i2c->dev_comp->regs == mt_i2c_regs_v2) { -+ dev_dbg(i2c->dev, "LTIMING: 0x%x, MULTI_DMA: 0x%x\n", -+ mtk_i2c_readw(i2c, OFFSET_LTIMING), -+ mtk_i2c_readw(i2c, OFFSET_MULTI_DMA)); -+ } -+ dev_dbg(i2c->dev, "\nDMA_INT_FLAG: 0x%x, DMA_INT_EN: 0x%x\n", -+ readl(i2c->pdmabase + OFFSET_INT_FLAG), -+ readl(i2c->pdmabase + OFFSET_INT_EN)); -+ dev_dbg(i2c->dev, "DMA_EN: 0x%x, DMA_CON: 0x%x\n", -+ readl(i2c->pdmabase + OFFSET_EN), -+ readl(i2c->pdmabase + OFFSET_CON)); -+ dev_dbg(i2c->dev, "DMA_TX_MEM_ADDR: 0x%x, DMA_RX_MEM_ADDR: 0x%x\n", -+ readl(i2c->pdmabase + OFFSET_TX_MEM_ADDR), -+ readl(i2c->pdmabase + OFFSET_RX_MEM_ADDR)); -+ dev_dbg(i2c->dev, "DMA_TX_LEN: 0x%x, DMA_RX_LEN: 0x%x\n", -+ readl(i2c->pdmabase + OFFSET_TX_LEN), -+ readl(i2c->pdmabase + OFFSET_RX_LEN)); -+ dev_dbg(i2c->dev, "DMA_TX_4G_MODE: 0x%x, DMA_RX_4G_MODE: 0x%x", -+ readl(i2c->pdmabase + OFFSET_TX_4G_MODE), -+ readl(i2c->pdmabase + OFFSET_RX_4G_MODE)); -+} -+ - static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, - int num, int left_num) - { -@@ -1075,6 +1128,7 @@ static int mtk_i2c_do_transfer(struct mt - - if (ret == 0) { - dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr); -+ i2c_dump_register(i2c); - mtk_i2c_init_hw(i2c); - return -ETIMEDOUT; - } diff --git a/target/linux/mediatek/patches-6.1/842-v5.18-i2c-mediatek-Add-i2c-compatible-for-Mediatek-MT8186.patch b/target/linux/mediatek/patches-6.1/842-v5.18-i2c-mediatek-Add-i2c-compatible-for-Mediatek-MT8186.patch deleted file mode 100644 index 184fe94ff80..00000000000 --- a/target/linux/mediatek/patches-6.1/842-v5.18-i2c-mediatek-Add-i2c-compatible-for-Mediatek-MT8186.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 83630e3c6147bf7bb18a18f3d5a99462464f450b Mon Sep 17 00:00:00 2001 -From: Kewei Xu -Date: Tue, 25 Jan 2022 19:04:13 +0800 -Subject: [PATCH 03/16] i2c: mediatek: Add i2c compatible for Mediatek MT8186 - -Add i2c compatible for MT8186. Compare to MT8192 i2c controller, -MT8186 doesn't need handshake signal witch apdma. - -Signed-off-by: Kewei Xu -Reviewed-by: Qii Wang -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -397,6 +397,19 @@ static const struct mtk_i2c_compatible m - .max_dma_support = 33, - }; - -+static const struct mtk_i2c_compatible mt8186_compat = { -+ .regs = mt_i2c_regs_v2, -+ .pmic_i2c = 0, -+ .dcm = 0, -+ .auto_restart = 1, -+ .aux_len_reg = 1, -+ .timing_adjust = 1, -+ .dma_sync = 0, -+ .ltiming_adjust = 1, -+ .apdma_sync = 0, -+ .max_dma_support = 36, -+}; -+ - static const struct mtk_i2c_compatible mt8192_compat = { - .quirks = &mt8183_i2c_quirks, - .regs = mt_i2c_regs_v2, -@@ -418,6 +431,7 @@ static const struct of_device_id mtk_i2c - { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat }, - { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, - { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat }, -+ { .compatible = "mediatek,mt8186-i2c", .data = &mt8186_compat }, - { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat }, - {} - }; diff --git a/target/linux/mediatek/patches-6.1/843-v5.18-i2c-mediatek-modify-bus-speed-calculation-formula.patch b/target/linux/mediatek/patches-6.1/843-v5.18-i2c-mediatek-modify-bus-speed-calculation-formula.patch deleted file mode 100644 index 0ace4a6701c..00000000000 --- a/target/linux/mediatek/patches-6.1/843-v5.18-i2c-mediatek-modify-bus-speed-calculation-formula.patch +++ /dev/null @@ -1,132 +0,0 @@ -From f606aab3f1a49d723d66e14e545f6ca45005bda6 Mon Sep 17 00:00:00 2001 -From: Kewei Xu -Date: Thu, 17 Feb 2022 20:22:43 +0800 -Subject: [PATCH 04/16] i2c: mediatek: modify bus speed calculation formula - -When clock-div is 0 or greater than 1, the bus speed -calculated by the old speed calculation formula will be -larger than the target speed. So we update the formula. - -Signed-off-by: Kewei Xu -Reviewed-by: AngeloGioacchino Del Regno -Reviewed-by: Qii Wang -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 51 ++++++++++++++++++++++++++------- - 1 file changed, 41 insertions(+), 10 deletions(-) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -67,11 +67,12 @@ - - #define MAX_SAMPLE_CNT_DIV 8 - #define MAX_STEP_CNT_DIV 64 --#define MAX_CLOCK_DIV 256 -+#define MAX_CLOCK_DIV_8BITS 256 -+#define MAX_CLOCK_DIV_5BITS 32 - #define MAX_HS_STEP_CNT_DIV 8 --#define I2C_STANDARD_MODE_BUFFER (1000 / 2) --#define I2C_FAST_MODE_BUFFER (300 / 2) --#define I2C_FAST_MODE_PLUS_BUFFER (20 / 2) -+#define I2C_STANDARD_MODE_BUFFER (1000 / 3) -+#define I2C_FAST_MODE_BUFFER (300 / 3) -+#define I2C_FAST_MODE_PLUS_BUFFER (20 / 3) - - #define I2C_CONTROL_RS (0x1 << 1) - #define I2C_CONTROL_DMA_EN (0x1 << 2) -@@ -604,6 +605,31 @@ static int mtk_i2c_max_step_cnt(unsigned - return MAX_STEP_CNT_DIV; - } - -+static int mtk_i2c_get_clk_div_restri(struct mtk_i2c *i2c, -+ unsigned int sample_cnt) -+{ -+ int clk_div_restri = 0; -+ -+ if (i2c->dev_comp->ltiming_adjust == 0) -+ return 0; -+ -+ if (sample_cnt == 1) { -+ if (i2c->ac_timing.inter_clk_div == 0) -+ clk_div_restri = 0; -+ else -+ clk_div_restri = 1; -+ } else { -+ if (i2c->ac_timing.inter_clk_div == 0) -+ clk_div_restri = -1; -+ else if (i2c->ac_timing.inter_clk_div == 1) -+ clk_div_restri = 0; -+ else -+ clk_div_restri = 1; -+ } -+ -+ return clk_div_restri; -+} -+ - /* - * Check and Calculate i2c ac-timing - * -@@ -732,6 +758,7 @@ static int mtk_i2c_calculate_speed(struc - unsigned int best_mul; - unsigned int cnt_mul; - int ret = -EINVAL; -+ int clk_div_restri = 0; - - if (target_speed > I2C_MAX_HIGH_SPEED_MODE_FREQ) - target_speed = I2C_MAX_HIGH_SPEED_MODE_FREQ; -@@ -749,7 +776,8 @@ static int mtk_i2c_calculate_speed(struc - * optimizing for sample_cnt * step_cnt being minimal - */ - for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) { -- step_cnt = DIV_ROUND_UP(opt_div, sample_cnt); -+ clk_div_restri = mtk_i2c_get_clk_div_restri(i2c, sample_cnt); -+ step_cnt = DIV_ROUND_UP(opt_div + clk_div_restri, sample_cnt); - cnt_mul = step_cnt * sample_cnt; - if (step_cnt > max_step_cnt) - continue; -@@ -763,7 +791,7 @@ static int mtk_i2c_calculate_speed(struc - best_mul = cnt_mul; - base_sample_cnt = sample_cnt; - base_step_cnt = step_cnt; -- if (best_mul == opt_div) -+ if (best_mul == (opt_div + clk_div_restri)) - break; - } - } -@@ -774,7 +802,8 @@ static int mtk_i2c_calculate_speed(struc - sample_cnt = base_sample_cnt; - step_cnt = base_step_cnt; - -- if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) { -+ if ((clk_src / (2 * (sample_cnt * step_cnt - clk_div_restri))) > -+ target_speed) { - /* In this case, hardware can't support such - * low i2c_bus_freq - */ -@@ -803,13 +832,16 @@ static int mtk_i2c_set_speed(struct mtk_ - target_speed = i2c->speed_hz; - parent_clk /= i2c->clk_src_div; - -- if (i2c->dev_comp->timing_adjust) -- max_clk_div = MAX_CLOCK_DIV; -+ if (i2c->dev_comp->timing_adjust && i2c->dev_comp->ltiming_adjust) -+ max_clk_div = MAX_CLOCK_DIV_5BITS; -+ else if (i2c->dev_comp->timing_adjust) -+ max_clk_div = MAX_CLOCK_DIV_8BITS; - else - max_clk_div = 1; - - for (clk_div = 1; clk_div <= max_clk_div; clk_div++) { - clk_src = parent_clk / clk_div; -+ i2c->ac_timing.inter_clk_div = clk_div - 1; - - if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) { - /* Set master code speed register */ -@@ -856,7 +888,6 @@ static int mtk_i2c_set_speed(struct mtk_ - break; - } - -- i2c->ac_timing.inter_clk_div = clk_div - 1; - - return 0; - } diff --git a/target/linux/mediatek/patches-6.1/844-v5.18-i2c-mediatek-remove-redundant-null-check.patch b/target/linux/mediatek/patches-6.1/844-v5.18-i2c-mediatek-remove-redundant-null-check.patch deleted file mode 100644 index 8f3c965a8d4..00000000000 --- a/target/linux/mediatek/patches-6.1/844-v5.18-i2c-mediatek-remove-redundant-null-check.patch +++ /dev/null @@ -1,41 +0,0 @@ -From eb4a2ae019815946f574cd9f8209e12bdcd8fd34 Mon Sep 17 00:00:00 2001 -From: Xu Wang -Date: Wed, 30 Sep 2020 08:42:33 +0000 -Subject: [PATCH 05/16] i2c: mediatek: remove redundant null check - -Because clk_disable_unprepare already checked NULL clock parameter, -so the additional checks are unnecessary, just remove it - -Signed-off-by: Xu Wang -Reviewed-by: Qii Wang -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 9 +++------ - 1 file changed, 3 insertions(+), 6 deletions(-) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -476,8 +476,7 @@ static int mtk_i2c_clock_enable(struct m - return 0; - - err_arb: -- if (i2c->have_pmic) -- clk_disable_unprepare(i2c->clk_pmic); -+ clk_disable_unprepare(i2c->clk_pmic); - err_pmic: - clk_disable_unprepare(i2c->clk_main); - err_main: -@@ -488,11 +487,9 @@ err_main: - - static void mtk_i2c_clock_disable(struct mtk_i2c *i2c) - { -- if (i2c->clk_arb) -- clk_disable_unprepare(i2c->clk_arb); -+ clk_disable_unprepare(i2c->clk_arb); - -- if (i2c->have_pmic) -- clk_disable_unprepare(i2c->clk_pmic); -+ clk_disable_unprepare(i2c->clk_pmic); - - clk_disable_unprepare(i2c->clk_main); - clk_disable_unprepare(i2c->clk_dma); diff --git a/target/linux/mediatek/patches-6.1/845-v5.18-i2c-mt65xx-Simplify-with-clk-bulk.patch b/target/linux/mediatek/patches-6.1/845-v5.18-i2c-mt65xx-Simplify-with-clk-bulk.patch deleted file mode 100644 index 71d083f31a9..00000000000 --- a/target/linux/mediatek/patches-6.1/845-v5.18-i2c-mt65xx-Simplify-with-clk-bulk.patch +++ /dev/null @@ -1,234 +0,0 @@ -From cc6faa5e0772296d815fd298c231277d47308a6a Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Thu, 3 Mar 2022 10:15:47 +0100 -Subject: [PATCH 06/16] i2c: mt65xx: Simplify with clk-bulk - -Since depending on the SoC or specific bus functionality some clocks -may be optional, we cannot get the benefit of using devm_clk_bulk_get() -but, by migrating to clk-bulk, we are able to remove the custom functions -mtk_i2c_clock_enable() and mtk_i2c_clock_disable(), increasing common -APIs usage, hence (lightly) decreasing kernel footprint. - -Signed-off-by: AngeloGioacchino Del Regno -Reviewed-by: Qii Wang -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 124 +++++++++++++------------------- - 1 file changed, 51 insertions(+), 73 deletions(-) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -86,6 +86,27 @@ - - #define I2C_DRV_NAME "i2c-mt65xx" - -+/** -+ * enum i2c_mt65xx_clks - Clocks enumeration for MT65XX I2C -+ * -+ * @I2C_MT65XX_CLK_MAIN: main clock for i2c bus -+ * @I2C_MT65XX_CLK_DMA: DMA clock for i2c via DMA -+ * @I2C_MT65XX_CLK_PMIC: PMIC clock for i2c from PMIC -+ * @I2C_MT65XX_CLK_ARB: Arbitrator clock for i2c -+ * @I2C_MT65XX_CLK_MAX: Number of supported clocks -+ */ -+enum i2c_mt65xx_clks { -+ I2C_MT65XX_CLK_MAIN = 0, -+ I2C_MT65XX_CLK_DMA, -+ I2C_MT65XX_CLK_PMIC, -+ I2C_MT65XX_CLK_ARB, -+ I2C_MT65XX_CLK_MAX -+}; -+ -+static const char * const i2c_mt65xx_clk_ids[I2C_MT65XX_CLK_MAX] = { -+ "main", "dma", "pmic", "arb" -+}; -+ - enum DMA_REGS_OFFSET { - OFFSET_INT_FLAG = 0x0, - OFFSET_INT_EN = 0x04, -@@ -244,10 +265,7 @@ struct mtk_i2c { - /* set in i2c probe */ - void __iomem *base; /* i2c base addr */ - void __iomem *pdmabase; /* dma base address*/ -- struct clk *clk_main; /* main clock for i2c bus */ -- struct clk *clk_dma; /* DMA clock for i2c via DMA */ -- struct clk *clk_pmic; /* PMIC clock for i2c from PMIC */ -- struct clk *clk_arb; /* Arbitrator clock for i2c */ -+ struct clk_bulk_data clocks[I2C_MT65XX_CLK_MAX]; /* clocks for i2c */ - bool have_pmic; /* can use i2c pins from PMIC */ - bool use_push_pull; /* IO config push-pull mode */ - -@@ -449,52 +467,6 @@ static void mtk_i2c_writew(struct mtk_i2 - writew(val, i2c->base + i2c->dev_comp->regs[reg]); - } - --static int mtk_i2c_clock_enable(struct mtk_i2c *i2c) --{ -- int ret; -- -- ret = clk_prepare_enable(i2c->clk_dma); -- if (ret) -- return ret; -- -- ret = clk_prepare_enable(i2c->clk_main); -- if (ret) -- goto err_main; -- -- if (i2c->have_pmic) { -- ret = clk_prepare_enable(i2c->clk_pmic); -- if (ret) -- goto err_pmic; -- } -- -- if (i2c->clk_arb) { -- ret = clk_prepare_enable(i2c->clk_arb); -- if (ret) -- goto err_arb; -- } -- -- return 0; -- --err_arb: -- clk_disable_unprepare(i2c->clk_pmic); --err_pmic: -- clk_disable_unprepare(i2c->clk_main); --err_main: -- clk_disable_unprepare(i2c->clk_dma); -- -- return ret; --} -- --static void mtk_i2c_clock_disable(struct mtk_i2c *i2c) --{ -- clk_disable_unprepare(i2c->clk_arb); -- -- clk_disable_unprepare(i2c->clk_pmic); -- -- clk_disable_unprepare(i2c->clk_main); -- clk_disable_unprepare(i2c->clk_dma); --} -- - static void mtk_i2c_init_hw(struct mtk_i2c *i2c) - { - u16 control_reg; -@@ -1191,7 +1163,7 @@ static int mtk_i2c_transfer(struct i2c_a - int left_num = num; - struct mtk_i2c *i2c = i2c_get_adapdata(adap); - -- ret = mtk_i2c_clock_enable(i2c); -+ ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks); - if (ret) - return ret; - -@@ -1245,7 +1217,7 @@ static int mtk_i2c_transfer(struct i2c_a - ret = num; - - err_exit: -- mtk_i2c_clock_disable(i2c); -+ clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); - return ret; - } - -@@ -1323,9 +1295,8 @@ static int mtk_i2c_probe(struct platform - { - int ret = 0; - struct mtk_i2c *i2c; -- struct clk *clk; - struct resource *res; -- int irq; -+ int i, irq, speed_clk; - - i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); - if (!i2c) -@@ -1371,35 +1342,42 @@ static int mtk_i2c_probe(struct platform - if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c) - return -EINVAL; - -- i2c->clk_main = devm_clk_get(&pdev->dev, "main"); -- if (IS_ERR(i2c->clk_main)) { -+ /* Fill in clk-bulk IDs */ -+ for (i = 0; i < I2C_MT65XX_CLK_MAX; i++) -+ i2c->clocks[i].id = i2c_mt65xx_clk_ids[i]; -+ -+ /* Get clocks one by one, some may be optional */ -+ i2c->clocks[I2C_MT65XX_CLK_MAIN].clk = devm_clk_get(&pdev->dev, "main"); -+ if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_MAIN].clk)) { - dev_err(&pdev->dev, "cannot get main clock\n"); -- return PTR_ERR(i2c->clk_main); -+ return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_MAIN].clk); - } - -- i2c->clk_dma = devm_clk_get(&pdev->dev, "dma"); -- if (IS_ERR(i2c->clk_dma)) { -+ i2c->clocks[I2C_MT65XX_CLK_DMA].clk = devm_clk_get(&pdev->dev, "dma"); -+ if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_DMA].clk)) { - dev_err(&pdev->dev, "cannot get dma clock\n"); -- return PTR_ERR(i2c->clk_dma); -+ return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_DMA].clk); - } - -- i2c->clk_arb = devm_clk_get(&pdev->dev, "arb"); -- if (IS_ERR(i2c->clk_arb)) -- i2c->clk_arb = NULL; -+ i2c->clocks[I2C_MT65XX_CLK_ARB].clk = devm_clk_get_optional(&pdev->dev, "arb"); -+ if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk)) -+ return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk); - -- clk = i2c->clk_main; - if (i2c->have_pmic) { -- i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic"); -- if (IS_ERR(i2c->clk_pmic)) { -+ i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get(&pdev->dev, "pmic"); -+ if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) { - dev_err(&pdev->dev, "cannot get pmic clock\n"); -- return PTR_ERR(i2c->clk_pmic); -+ return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk); - } -- clk = i2c->clk_pmic; -+ speed_clk = I2C_MT65XX_CLK_PMIC; -+ } else { -+ i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = NULL; -+ speed_clk = I2C_MT65XX_CLK_MAIN; - } - - strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name)); - -- ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk)); -+ ret = mtk_i2c_set_speed(i2c, clk_get_rate(i2c->clocks[speed_clk].clk)); - if (ret) { - dev_err(&pdev->dev, "Failed to set the speed.\n"); - return -EINVAL; -@@ -1414,13 +1392,13 @@ static int mtk_i2c_probe(struct platform - } - } - -- ret = mtk_i2c_clock_enable(i2c); -+ ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks); - if (ret) { - dev_err(&pdev->dev, "clock enable failed!\n"); - return ret; - } - mtk_i2c_init_hw(i2c); -- mtk_i2c_clock_disable(i2c); -+ clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); - - ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq, - IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE, -@@ -1465,7 +1443,7 @@ static int mtk_i2c_resume_noirq(struct d - int ret; - struct mtk_i2c *i2c = dev_get_drvdata(dev); - -- ret = mtk_i2c_clock_enable(i2c); -+ ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks); - if (ret) { - dev_err(dev, "clock enable failed!\n"); - return ret; -@@ -1473,7 +1451,7 @@ static int mtk_i2c_resume_noirq(struct d - - mtk_i2c_init_hw(i2c); - -- mtk_i2c_clock_disable(i2c); -+ clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); - - i2c_mark_adapter_resumed(&i2c->adap); - diff --git a/target/linux/mediatek/patches-6.1/846-v5.18-i2c-mediatek-Add-i2c-compatible-for-Mediatek-MT8168.patch b/target/linux/mediatek/patches-6.1/846-v5.18-i2c-mediatek-Add-i2c-compatible-for-Mediatek-MT8168.patch deleted file mode 100644 index fe5be94fca4..00000000000 --- a/target/linux/mediatek/patches-6.1/846-v5.18-i2c-mediatek-Add-i2c-compatible-for-Mediatek-MT8168.patch +++ /dev/null @@ -1,46 +0,0 @@ -From de054c03f90b3ea22bc346fbf78ac716df192b2d Mon Sep 17 00:00:00 2001 -From: Kewei Xu -Date: Mon, 7 Mar 2022 11:36:49 +0800 -Subject: [PATCH 07/16] i2c: mediatek: Add i2c compatible for Mediatek MT8168 - -Add i2c compatible for MT8168. Compare to MT2712 i2c controller, -MT8168 need to synchronize signal with dma. - -Signed-off-by: Kewei Xu -Reviewed-by: AngeloGioacchino Del Regno -Reviewed-by: Qii Wang -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -389,6 +389,19 @@ static const struct mtk_i2c_compatible m - .max_dma_support = 32, - }; - -+static const struct mtk_i2c_compatible mt8168_compat = { -+ .regs = mt_i2c_regs_v1, -+ .pmic_i2c = 0, -+ .dcm = 1, -+ .auto_restart = 1, -+ .aux_len_reg = 1, -+ .timing_adjust = 1, -+ .dma_sync = 1, -+ .ltiming_adjust = 0, -+ .apdma_sync = 0, -+ .max_dma_support = 33, -+}; -+ - static const struct mtk_i2c_compatible mt8173_compat = { - .regs = mt_i2c_regs_v1, - .pmic_i2c = 0, -@@ -448,6 +461,7 @@ static const struct of_device_id mtk_i2c - { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat }, - { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat }, - { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat }, -+ { .compatible = "mediatek,mt8168-i2c", .data = &mt8168_compat }, - { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, - { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat }, - { .compatible = "mediatek,mt8186-i2c", .data = &mt8186_compat }, diff --git a/target/linux/mediatek/patches-6.1/847-v5.19-i2c-mediatek-Optimize-master_xfer-and-avoid-circular.patch b/target/linux/mediatek/patches-6.1/847-v5.19-i2c-mediatek-Optimize-master_xfer-and-avoid-circular.patch deleted file mode 100644 index 5c4ce40765c..00000000000 --- a/target/linux/mediatek/patches-6.1/847-v5.19-i2c-mediatek-Optimize-master_xfer-and-avoid-circular.patch +++ /dev/null @@ -1,101 +0,0 @@ -From 2831f9a53ec3a16012d2d23590e3ebad6084b763 Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Mon, 11 Apr 2022 15:21:07 +0200 -Subject: [PATCH 08/16] i2c: mediatek: Optimize master_xfer() and avoid - circular locking -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Especially (but not only) during probe, it may happen that multiple -devices are communicating via i2c (or multiple i2c busses) and -sometimes while others are probing asynchronously. -For example, a Cr50 TPM may be filling entropy (or userspace may be -reading random data) while the rt5682 (i2c) codec driver reads/sets -some registers, like while getting/setting a clock's rate, which -happens both during probe and during system operation. - -In this driver, the mtk_i2c_transfer() function (which is the i2c -.master_xfer() callback) was granularly managing the clocks by -performing a clk_bulk_prepare_enable() to start them and its inverse. -This is not only creating possible circular locking dependencies in -the some cases (like former explanation), but it's also suboptimal, -as clk_core prepare/unprepare operations are using mutex locking, -which creates a bit of unwanted overhead (for example, i2c trackpads -will call master_xfer() every few milliseconds!). - -With this commit, we avoid both the circular locking and additional -overhead by changing how we handle the clocks in this driver: -- Prepare the clocks during probe (and PM resume) -- Enable/disable clocks in mtk_i2c_transfer() -- Unprepare the clocks only for driver removal (and PM suspend) - -For the sake of providing a full explanation: during probe, the -clocks are not only prepared but also enabled, as this is needed -for some hardware initialization but, after that, we are disabling -but not unpreparing them, leaving an expected state for the -aforementioned clock handling strategy. - -Signed-off-by: AngeloGioacchino Del Regno -Tested-by: Nícolas F. R. A. Prado -Reviewed-by: Qii Wang -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 11 +++++++---- - 1 file changed, 7 insertions(+), 4 deletions(-) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -1177,7 +1177,7 @@ static int mtk_i2c_transfer(struct i2c_a - int left_num = num; - struct mtk_i2c *i2c = i2c_get_adapdata(adap); - -- ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks); -+ ret = clk_bulk_enable(I2C_MT65XX_CLK_MAX, i2c->clocks); - if (ret) - return ret; - -@@ -1231,7 +1231,7 @@ static int mtk_i2c_transfer(struct i2c_a - ret = num; - - err_exit: -- clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); -+ clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks); - return ret; - } - -@@ -1412,7 +1412,7 @@ static int mtk_i2c_probe(struct platform - return ret; - } - mtk_i2c_init_hw(i2c); -- clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); -+ clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks); - - ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq, - IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE, -@@ -1439,6 +1439,8 @@ static int mtk_i2c_remove(struct platfor - - i2c_del_adapter(&i2c->adap); - -+ clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); -+ - return 0; - } - -@@ -1448,6 +1450,7 @@ static int mtk_i2c_suspend_noirq(struct - struct mtk_i2c *i2c = dev_get_drvdata(dev); - - i2c_mark_adapter_suspended(&i2c->adap); -+ clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); - - return 0; - } -@@ -1465,7 +1468,7 @@ static int mtk_i2c_resume_noirq(struct d - - mtk_i2c_init_hw(i2c); - -- clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); -+ clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks); - - i2c_mark_adapter_resumed(&i2c->adap); - diff --git a/target/linux/mediatek/patches-6.1/848-v5.19-i2c-mediatek-Fix-an-error-handling-path-in-mtk_i2c_p.patch b/target/linux/mediatek/patches-6.1/848-v5.19-i2c-mediatek-Fix-an-error-handling-path-in-mtk_i2c_p.patch deleted file mode 100644 index 354f12e2146..00000000000 --- a/target/linux/mediatek/patches-6.1/848-v5.19-i2c-mediatek-Fix-an-error-handling-path-in-mtk_i2c_p.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 6f3a5814c7aaea4176e0ac8b1ec6dc0a65aa2808 Mon Sep 17 00:00:00 2001 -From: Christophe JAILLET -Date: Sun, 22 May 2022 14:22:07 +0200 -Subject: [PATCH 09/16] i2c: mediatek: Fix an error handling path in - mtk_i2c_probe() - -The clsk are prepared, enabled, then disabled. So if an error occurs after -the disable step, they are still prepared. - -Add an error handling path to unprepare the clks in such a case, as already -done in the .remove function. - -Fixes: 8b4fc246c3ff ("i2c: mediatek: Optimize master_xfer() and avoid circular locking") -Signed-off-by: Christophe JAILLET -Reviewed-by: AngeloGioacchino Del Regno -Reviewed-by: Qii Wang -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 9 +++++++-- - 1 file changed, 7 insertions(+), 2 deletions(-) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -1420,17 +1420,22 @@ static int mtk_i2c_probe(struct platform - if (ret < 0) { - dev_err(&pdev->dev, - "Request I2C IRQ %d fail\n", irq); -- return ret; -+ goto err_bulk_unprepare; - } - - i2c_set_adapdata(&i2c->adap, i2c); - ret = i2c_add_adapter(&i2c->adap); - if (ret) -- return ret; -+ goto err_bulk_unprepare; - - platform_set_drvdata(pdev, i2c); - - return 0; -+ -+err_bulk_unprepare: -+ clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); -+ -+ return ret; - } - - static int mtk_i2c_remove(struct platform_device *pdev) diff --git a/target/linux/mediatek/patches-6.1/849-v6.0-i2c-mediatek-add-i2c-compatible-for-MT8188.patch b/target/linux/mediatek/patches-6.1/849-v6.0-i2c-mediatek-add-i2c-compatible-for-MT8188.patch deleted file mode 100644 index 744aa96ed0c..00000000000 --- a/target/linux/mediatek/patches-6.1/849-v6.0-i2c-mediatek-add-i2c-compatible-for-MT8188.patch +++ /dev/null @@ -1,82 +0,0 @@ -From 94c7f8af2c0a399c8aa66f2522b60c5784b5be6c Mon Sep 17 00:00:00 2001 -From: Kewei Xu -Date: Sat, 6 Aug 2022 18:02:49 +0800 -Subject: [PATCH 10/16] i2c: mediatek: add i2c compatible for MT8188 - -Add i2c compatible for MT8188 and added mt_i2c_regs_v3[], since -MT8188 i2c OFFSET_SLAVE_ADDR register changed from 0x04 to 0x94. - -Signed-off-by: Kewei Xu -Reviewed-by: AngeloGioacchino Del Regno -Reviewed-by: Qii Wang -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 43 +++++++++++++++++++++++++++++++++ - 1 file changed, 43 insertions(+) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -229,6 +229,35 @@ static const u16 mt_i2c_regs_v2[] = { - [OFFSET_DCM_EN] = 0xf88, - }; - -+static const u16 mt_i2c_regs_v3[] = { -+ [OFFSET_DATA_PORT] = 0x0, -+ [OFFSET_INTR_MASK] = 0x8, -+ [OFFSET_INTR_STAT] = 0xc, -+ [OFFSET_CONTROL] = 0x10, -+ [OFFSET_TRANSFER_LEN] = 0x14, -+ [OFFSET_TRANSAC_LEN] = 0x18, -+ [OFFSET_DELAY_LEN] = 0x1c, -+ [OFFSET_TIMING] = 0x20, -+ [OFFSET_START] = 0x24, -+ [OFFSET_EXT_CONF] = 0x28, -+ [OFFSET_LTIMING] = 0x2c, -+ [OFFSET_HS] = 0x30, -+ [OFFSET_IO_CONFIG] = 0x34, -+ [OFFSET_FIFO_ADDR_CLR] = 0x38, -+ [OFFSET_SDA_TIMING] = 0x3c, -+ [OFFSET_TRANSFER_LEN_AUX] = 0x44, -+ [OFFSET_CLOCK_DIV] = 0x48, -+ [OFFSET_SOFTRESET] = 0x50, -+ [OFFSET_MULTI_DMA] = 0x8c, -+ [OFFSET_SCL_MIS_COMP_POINT] = 0x90, -+ [OFFSET_SLAVE_ADDR] = 0x94, -+ [OFFSET_DEBUGSTAT] = 0xe4, -+ [OFFSET_DEBUGCTRL] = 0xe8, -+ [OFFSET_FIFO_STAT] = 0xf4, -+ [OFFSET_FIFO_THRESH] = 0xf8, -+ [OFFSET_DCM_EN] = 0xf88, -+}; -+ - struct mtk_i2c_compatible { - const struct i2c_adapter_quirks *quirks; - const u16 *regs; -@@ -442,6 +471,19 @@ static const struct mtk_i2c_compatible m - .max_dma_support = 36, - }; - -+static const struct mtk_i2c_compatible mt8188_compat = { -+ .regs = mt_i2c_regs_v3, -+ .pmic_i2c = 0, -+ .dcm = 0, -+ .auto_restart = 1, -+ .aux_len_reg = 1, -+ .timing_adjust = 1, -+ .dma_sync = 0, -+ .ltiming_adjust = 1, -+ .apdma_sync = 1, -+ .max_dma_support = 36, -+}; -+ - static const struct mtk_i2c_compatible mt8192_compat = { - .quirks = &mt8183_i2c_quirks, - .regs = mt_i2c_regs_v2, -@@ -465,6 +507,7 @@ static const struct of_device_id mtk_i2c - { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, - { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat }, - { .compatible = "mediatek,mt8186-i2c", .data = &mt8186_compat }, -+ { .compatible = "mediatek,mt8188-i2c", .data = &mt8188_compat }, - { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat }, - {} - }; diff --git a/target/linux/mediatek/patches-6.1/850-v6.0-i2c-move-drivers-from-strlcpy-to-strscpy.patch b/target/linux/mediatek/patches-6.1/850-v6.0-i2c-move-drivers-from-strlcpy-to-strscpy.patch deleted file mode 100644 index 1520a6cbe6d..00000000000 --- a/target/linux/mediatek/patches-6.1/850-v6.0-i2c-move-drivers-from-strlcpy-to-strscpy.patch +++ /dev/null @@ -1,579 +0,0 @@ -From 2f4ca256a98cc19787b7c861109dd1150a21b0bf Mon Sep 17 00:00:00 2001 -From: Wolfram Sang -Date: Thu, 11 Aug 2022 09:10:30 +0200 -Subject: [PATCH 11/16] i2c: move drivers from strlcpy to strscpy - -Follow the advice of the below link and prefer 'strscpy'. Conversion is -easy because no driver used the return value and has been done with a -simple sed invocation. - -Link: https://lore.kernel.org/r/CAHk-=wgfRnXz0W3D37d01q3JFkr_i_uTL=V6A6G1oUZcprmknw@mail.gmail.com/ -Signed-off-by: Wolfram Sang -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-altera.c | 2 +- - drivers/i2c/busses/i2c-aspeed.c | 2 +- - drivers/i2c/busses/i2c-au1550.c | 2 +- - drivers/i2c/busses/i2c-axxia.c | 2 +- - drivers/i2c/busses/i2c-bcm-kona.c | 2 +- - drivers/i2c/busses/i2c-cbus-gpio.c | 2 +- - drivers/i2c/busses/i2c-cht-wc.c | 2 +- - drivers/i2c/busses/i2c-cros-ec-tunnel.c | 2 +- - drivers/i2c/busses/i2c-davinci.c | 2 +- - drivers/i2c/busses/i2c-digicolor.c | 2 +- - drivers/i2c/busses/i2c-eg20t.c | 2 +- - drivers/i2c/busses/i2c-emev2.c | 2 +- - drivers/i2c/busses/i2c-exynos5.c | 2 +- - drivers/i2c/busses/i2c-gpio.c | 2 +- - drivers/i2c/busses/i2c-highlander.c | 2 +- - drivers/i2c/busses/i2c-hix5hd2.c | 2 +- - drivers/i2c/busses/i2c-i801.c | 4 ++-- - drivers/i2c/busses/i2c-ibm_iic.c | 2 +- - drivers/i2c/busses/i2c-icy.c | 2 +- - drivers/i2c/busses/i2c-imx-lpi2c.c | 2 +- - drivers/i2c/busses/i2c-lpc2k.c | 2 +- - drivers/i2c/busses/i2c-meson.c | 2 +- - drivers/i2c/busses/i2c-mt65xx.c | 2 +- - drivers/i2c/busses/i2c-mt7621.c | 2 +- - drivers/i2c/busses/i2c-mv64xxx.c | 2 +- - drivers/i2c/busses/i2c-mxs.c | 2 +- - drivers/i2c/busses/i2c-nvidia-gpu.c | 2 +- - drivers/i2c/busses/i2c-omap.c | 2 +- - drivers/i2c/busses/i2c-opal.c | 4 ++-- - drivers/i2c/busses/i2c-parport.c | 2 +- - drivers/i2c/busses/i2c-pxa.c | 2 +- - drivers/i2c/busses/i2c-qcom-geni.c | 2 +- - drivers/i2c/busses/i2c-qup.c | 2 +- - drivers/i2c/busses/i2c-rcar.c | 2 +- - drivers/i2c/busses/i2c-riic.c | 2 +- - drivers/i2c/busses/i2c-rk3x.c | 2 +- - drivers/i2c/busses/i2c-s3c2410.c | 2 +- - drivers/i2c/busses/i2c-sh_mobile.c | 2 +- - drivers/i2c/busses/i2c-simtec.c | 2 +- - drivers/i2c/busses/i2c-taos-evm.c | 2 +- - drivers/i2c/busses/i2c-tegra-bpmp.c | 2 +- - drivers/i2c/busses/i2c-tegra.c | 2 +- - drivers/i2c/busses/i2c-uniphier-f.c | 2 +- - drivers/i2c/busses/i2c-uniphier.c | 2 +- - drivers/i2c/busses/i2c-versatile.c | 2 +- - drivers/i2c/busses/i2c-wmt.c | 2 +- - 46 files changed, 48 insertions(+), 48 deletions(-) - ---- a/drivers/i2c/busses/i2c-altera.c -+++ b/drivers/i2c/busses/i2c-altera.c -@@ -447,7 +447,7 @@ static int altr_i2c_probe(struct platfor - mutex_unlock(&idev->isr_mutex); - - i2c_set_adapdata(&idev->adapter, idev); -- strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name)); -+ strscpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name)); - idev->adapter.owner = THIS_MODULE; - idev->adapter.algo = &altr_i2c_algo; - idev->adapter.dev.parent = &pdev->dev; ---- a/drivers/i2c/busses/i2c-aspeed.c -+++ b/drivers/i2c/busses/i2c-aspeed.c -@@ -1024,7 +1024,7 @@ static int aspeed_i2c_probe_bus(struct p - bus->adap.algo = &aspeed_i2c_algo; - bus->adap.dev.parent = &pdev->dev; - bus->adap.dev.of_node = pdev->dev.of_node; -- strlcpy(bus->adap.name, pdev->name, sizeof(bus->adap.name)); -+ strscpy(bus->adap.name, pdev->name, sizeof(bus->adap.name)); - i2c_set_adapdata(&bus->adap, bus); - - bus->dev = &pdev->dev; ---- a/drivers/i2c/busses/i2c-au1550.c -+++ b/drivers/i2c/busses/i2c-au1550.c -@@ -321,7 +321,7 @@ i2c_au1550_probe(struct platform_device - priv->adap.algo = &au1550_algo; - priv->adap.algo_data = priv; - priv->adap.dev.parent = &pdev->dev; -- strlcpy(priv->adap.name, "Au1xxx PSC I2C", sizeof(priv->adap.name)); -+ strscpy(priv->adap.name, "Au1xxx PSC I2C", sizeof(priv->adap.name)); - - /* Now, set up the PSC for SMBus PIO mode. */ - i2c_au1550_setup(priv); ---- a/drivers/i2c/busses/i2c-axxia.c -+++ b/drivers/i2c/busses/i2c-axxia.c -@@ -783,7 +783,7 @@ static int axxia_i2c_probe(struct platfo - } - - i2c_set_adapdata(&idev->adapter, idev); -- strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name)); -+ strscpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name)); - idev->adapter.owner = THIS_MODULE; - idev->adapter.algo = &axxia_i2c_algo; - idev->adapter.bus_recovery_info = &axxia_i2c_recovery_info; ---- a/drivers/i2c/busses/i2c-bcm-kona.c -+++ b/drivers/i2c/busses/i2c-bcm-kona.c -@@ -849,7 +849,7 @@ static int bcm_kona_i2c_probe(struct pla - adap = &dev->adapter; - i2c_set_adapdata(adap, dev); - adap->owner = THIS_MODULE; -- strlcpy(adap->name, "Broadcom I2C adapter", sizeof(adap->name)); -+ strscpy(adap->name, "Broadcom I2C adapter", sizeof(adap->name)); - adap->algo = &bcm_algo; - adap->dev.parent = &pdev->dev; - adap->dev.of_node = pdev->dev.of_node; ---- a/drivers/i2c/busses/i2c-cbus-gpio.c -+++ b/drivers/i2c/busses/i2c-cbus-gpio.c -@@ -245,7 +245,7 @@ static int cbus_i2c_probe(struct platfor - adapter->nr = pdev->id; - adapter->timeout = HZ; - adapter->algo = &cbus_i2c_algo; -- strlcpy(adapter->name, "CBUS I2C adapter", sizeof(adapter->name)); -+ strscpy(adapter->name, "CBUS I2C adapter", sizeof(adapter->name)); - - spin_lock_init(&chost->lock); - chost->dev = &pdev->dev; ---- a/drivers/i2c/busses/i2c-cht-wc.c -+++ b/drivers/i2c/busses/i2c-cht-wc.c -@@ -334,7 +334,7 @@ static int cht_wc_i2c_adap_i2c_probe(str - adap->adapter.class = I2C_CLASS_HWMON; - adap->adapter.algo = &cht_wc_i2c_adap_algo; - adap->adapter.lock_ops = &cht_wc_i2c_adap_lock_ops; -- strlcpy(adap->adapter.name, "PMIC I2C Adapter", -+ strscpy(adap->adapter.name, "PMIC I2C Adapter", - sizeof(adap->adapter.name)); - adap->adapter.dev.parent = &pdev->dev; - ---- a/drivers/i2c/busses/i2c-cros-ec-tunnel.c -+++ b/drivers/i2c/busses/i2c-cros-ec-tunnel.c -@@ -267,7 +267,7 @@ static int ec_i2c_probe(struct platform_ - bus->dev = dev; - - bus->adap.owner = THIS_MODULE; -- strlcpy(bus->adap.name, "cros-ec-i2c-tunnel", sizeof(bus->adap.name)); -+ strscpy(bus->adap.name, "cros-ec-i2c-tunnel", sizeof(bus->adap.name)); - bus->adap.algo = &ec_i2c_algorithm; - bus->adap.algo_data = bus; - bus->adap.dev.parent = &pdev->dev; ---- a/drivers/i2c/busses/i2c-davinci.c -+++ b/drivers/i2c/busses/i2c-davinci.c -@@ -847,7 +847,7 @@ static int davinci_i2c_probe(struct plat - i2c_set_adapdata(adap, dev); - adap->owner = THIS_MODULE; - adap->class = I2C_CLASS_DEPRECATED; -- strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name)); -+ strscpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name)); - adap->algo = &i2c_davinci_algo; - adap->dev.parent = &pdev->dev; - adap->timeout = DAVINCI_I2C_TIMEOUT; ---- a/drivers/i2c/busses/i2c-digicolor.c -+++ b/drivers/i2c/busses/i2c-digicolor.c -@@ -322,7 +322,7 @@ static int dc_i2c_probe(struct platform_ - if (ret < 0) - return ret; - -- strlcpy(i2c->adap.name, "Conexant Digicolor I2C adapter", -+ strscpy(i2c->adap.name, "Conexant Digicolor I2C adapter", - sizeof(i2c->adap.name)); - i2c->adap.owner = THIS_MODULE; - i2c->adap.algo = &dc_i2c_algorithm; ---- a/drivers/i2c/busses/i2c-eg20t.c -+++ b/drivers/i2c/busses/i2c-eg20t.c -@@ -773,7 +773,7 @@ static int pch_i2c_probe(struct pci_dev - - pch_adap->owner = THIS_MODULE; - pch_adap->class = I2C_CLASS_HWMON; -- strlcpy(pch_adap->name, KBUILD_MODNAME, sizeof(pch_adap->name)); -+ strscpy(pch_adap->name, KBUILD_MODNAME, sizeof(pch_adap->name)); - pch_adap->algo = &pch_algorithm; - pch_adap->algo_data = &adap_info->pch_data[i]; - ---- a/drivers/i2c/busses/i2c-emev2.c -+++ b/drivers/i2c/busses/i2c-emev2.c -@@ -371,7 +371,7 @@ static int em_i2c_probe(struct platform_ - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); - -- strlcpy(priv->adap.name, "EMEV2 I2C", sizeof(priv->adap.name)); -+ strscpy(priv->adap.name, "EMEV2 I2C", sizeof(priv->adap.name)); - - priv->sclk = devm_clk_get(&pdev->dev, "sclk"); - if (IS_ERR(priv->sclk)) ---- a/drivers/i2c/busses/i2c-exynos5.c -+++ b/drivers/i2c/busses/i2c-exynos5.c -@@ -751,7 +751,7 @@ static int exynos5_i2c_probe(struct plat - if (of_property_read_u32(np, "clock-frequency", &i2c->op_clock)) - i2c->op_clock = I2C_MAX_STANDARD_MODE_FREQ; - -- strlcpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name)); -+ strscpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name)); - i2c->adap.owner = THIS_MODULE; - i2c->adap.algo = &exynos5_i2c_algorithm; - i2c->adap.retries = 3; ---- a/drivers/i2c/busses/i2c-gpio.c -+++ b/drivers/i2c/busses/i2c-gpio.c -@@ -436,7 +436,7 @@ static int i2c_gpio_probe(struct platfor - - adap->owner = THIS_MODULE; - if (np) -- strlcpy(adap->name, dev_name(dev), sizeof(adap->name)); -+ strscpy(adap->name, dev_name(dev), sizeof(adap->name)); - else - snprintf(adap->name, sizeof(adap->name), "i2c-gpio%d", pdev->id); - ---- a/drivers/i2c/busses/i2c-highlander.c -+++ b/drivers/i2c/busses/i2c-highlander.c -@@ -402,7 +402,7 @@ static int highlander_i2c_probe(struct p - i2c_set_adapdata(adap, dev); - adap->owner = THIS_MODULE; - adap->class = I2C_CLASS_HWMON; -- strlcpy(adap->name, "HL FPGA I2C adapter", sizeof(adap->name)); -+ strscpy(adap->name, "HL FPGA I2C adapter", sizeof(adap->name)); - adap->algo = &highlander_i2c_algo; - adap->dev.parent = &pdev->dev; - adap->nr = pdev->id; ---- a/drivers/i2c/busses/i2c-hix5hd2.c -+++ b/drivers/i2c/busses/i2c-hix5hd2.c -@@ -423,7 +423,7 @@ static int hix5hd2_i2c_probe(struct plat - } - clk_prepare_enable(priv->clk); - -- strlcpy(priv->adap.name, "hix5hd2-i2c", sizeof(priv->adap.name)); -+ strscpy(priv->adap.name, "hix5hd2-i2c", sizeof(priv->adap.name)); - priv->dev = &pdev->dev; - priv->adap.owner = THIS_MODULE; - priv->adap.algo = &hix5hd2_i2c_algorithm; ---- a/drivers/i2c/busses/i2c-i801.c -+++ b/drivers/i2c/busses/i2c-i801.c -@@ -1111,7 +1111,7 @@ static void dmi_check_onboard_device(u8 - - memset(&info, 0, sizeof(struct i2c_board_info)); - info.addr = dmi_devices[i].i2c_addr; -- strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); -+ strscpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); - i2c_new_client_device(adap, &info); - break; - } -@@ -1267,7 +1267,7 @@ static void register_dell_lis3lv02d_i2c_ - - memset(&info, 0, sizeof(struct i2c_board_info)); - info.addr = dell_lis3lv02d_devices[i].i2c_addr; -- strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE); -+ strscpy(info.type, "lis3lv02d", I2C_NAME_SIZE); - i2c_new_client_device(&priv->adapter, &info); - } - ---- a/drivers/i2c/busses/i2c-ibm_iic.c -+++ b/drivers/i2c/busses/i2c-ibm_iic.c -@@ -738,7 +738,7 @@ static int iic_probe(struct platform_dev - adap = &dev->adap; - adap->dev.parent = &ofdev->dev; - adap->dev.of_node = of_node_get(np); -- strlcpy(adap->name, "IBM IIC", sizeof(adap->name)); -+ strscpy(adap->name, "IBM IIC", sizeof(adap->name)); - i2c_set_adapdata(adap, dev); - adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; - adap->algo = &iic_algo; ---- a/drivers/i2c/busses/i2c-icy.c -+++ b/drivers/i2c/busses/i2c-icy.c -@@ -141,7 +141,7 @@ static int icy_probe(struct zorro_dev *z - i2c->adapter.owner = THIS_MODULE; - /* i2c->adapter.algo assigned by i2c_pcf_add_bus() */ - i2c->adapter.algo_data = algo_data; -- strlcpy(i2c->adapter.name, "ICY I2C Zorro adapter", -+ strscpy(i2c->adapter.name, "ICY I2C Zorro adapter", - sizeof(i2c->adapter.name)); - - if (!devm_request_mem_region(&z->dev, ---- a/drivers/i2c/busses/i2c-imx-lpi2c.c -+++ b/drivers/i2c/busses/i2c-imx-lpi2c.c -@@ -564,7 +564,7 @@ static int lpi2c_imx_probe(struct platfo - lpi2c_imx->adapter.algo = &lpi2c_imx_algo; - lpi2c_imx->adapter.dev.parent = &pdev->dev; - lpi2c_imx->adapter.dev.of_node = pdev->dev.of_node; -- strlcpy(lpi2c_imx->adapter.name, pdev->name, -+ strscpy(lpi2c_imx->adapter.name, pdev->name, - sizeof(lpi2c_imx->adapter.name)); - - lpi2c_imx->clk = devm_clk_get(&pdev->dev, NULL); ---- a/drivers/i2c/busses/i2c-lpc2k.c -+++ b/drivers/i2c/busses/i2c-lpc2k.c -@@ -417,7 +417,7 @@ static int i2c_lpc2k_probe(struct platfo - - i2c_set_adapdata(&i2c->adap, i2c); - i2c->adap.owner = THIS_MODULE; -- strlcpy(i2c->adap.name, "LPC2K I2C adapter", sizeof(i2c->adap.name)); -+ strscpy(i2c->adap.name, "LPC2K I2C adapter", sizeof(i2c->adap.name)); - i2c->adap.algo = &i2c_lpc2k_algorithm; - i2c->adap.dev.parent = &pdev->dev; - i2c->adap.dev.of_node = pdev->dev.of_node; ---- a/drivers/i2c/busses/i2c-meson.c -+++ b/drivers/i2c/busses/i2c-meson.c -@@ -451,7 +451,7 @@ static int meson_i2c_probe(struct platfo - return ret; - } - -- strlcpy(i2c->adap.name, "Meson I2C adapter", -+ strscpy(i2c->adap.name, "Meson I2C adapter", - sizeof(i2c->adap.name)); - i2c->adap.owner = THIS_MODULE; - i2c->adap.algo = &meson_i2c_algorithm; ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -1432,7 +1432,7 @@ static int mtk_i2c_probe(struct platform - speed_clk = I2C_MT65XX_CLK_MAIN; - } - -- strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name)); -+ strscpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name)); - - ret = mtk_i2c_set_speed(i2c, clk_get_rate(i2c->clocks[speed_clk].clk)); - if (ret) { ---- a/drivers/i2c/busses/i2c-mt7621.c -+++ b/drivers/i2c/busses/i2c-mt7621.c -@@ -315,7 +315,7 @@ static int mtk_i2c_probe(struct platform - adap->dev.parent = &pdev->dev; - i2c_set_adapdata(adap, i2c); - adap->dev.of_node = pdev->dev.of_node; -- strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name)); -+ strscpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name)); - - platform_set_drvdata(pdev, i2c); - ---- a/drivers/i2c/busses/i2c-mv64xxx.c -+++ b/drivers/i2c/busses/i2c-mv64xxx.c -@@ -1000,7 +1000,7 @@ mv64xxx_i2c_probe(struct platform_device - if (IS_ERR(drv_data->reg_base)) - return PTR_ERR(drv_data->reg_base); - -- strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter", -+ strscpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter", - sizeof(drv_data->adapter.name)); - - init_waitqueue_head(&drv_data->waitq); ---- a/drivers/i2c/busses/i2c-mxs.c -+++ b/drivers/i2c/busses/i2c-mxs.c -@@ -838,7 +838,7 @@ static int mxs_i2c_probe(struct platform - return err; - - adap = &i2c->adapter; -- strlcpy(adap->name, "MXS I2C adapter", sizeof(adap->name)); -+ strscpy(adap->name, "MXS I2C adapter", sizeof(adap->name)); - adap->owner = THIS_MODULE; - adap->algo = &mxs_i2c_algo; - adap->quirks = &mxs_i2c_quirks; ---- a/drivers/i2c/busses/i2c-nvidia-gpu.c -+++ b/drivers/i2c/busses/i2c-nvidia-gpu.c -@@ -319,7 +319,7 @@ static int gpu_i2c_probe(struct pci_dev - - i2c_set_adapdata(&i2cd->adapter, i2cd); - i2cd->adapter.owner = THIS_MODULE; -- strlcpy(i2cd->adapter.name, "NVIDIA GPU I2C adapter", -+ strscpy(i2cd->adapter.name, "NVIDIA GPU I2C adapter", - sizeof(i2cd->adapter.name)); - i2cd->adapter.algo = &gpu_i2c_algorithm; - i2cd->adapter.quirks = &gpu_i2c_quirks; ---- a/drivers/i2c/busses/i2c-omap.c -+++ b/drivers/i2c/busses/i2c-omap.c -@@ -1488,7 +1488,7 @@ omap_i2c_probe(struct platform_device *p - i2c_set_adapdata(adap, omap); - adap->owner = THIS_MODULE; - adap->class = I2C_CLASS_DEPRECATED; -- strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name)); -+ strscpy(adap->name, "OMAP I2C adapter", sizeof(adap->name)); - adap->algo = &omap_i2c_algo; - adap->quirks = &omap_i2c_quirks; - adap->dev.parent = &pdev->dev; ---- a/drivers/i2c/busses/i2c-opal.c -+++ b/drivers/i2c/busses/i2c-opal.c -@@ -220,9 +220,9 @@ static int i2c_opal_probe(struct platfor - adapter->dev.of_node = of_node_get(pdev->dev.of_node); - pname = of_get_property(pdev->dev.of_node, "ibm,port-name", NULL); - if (pname) -- strlcpy(adapter->name, pname, sizeof(adapter->name)); -+ strscpy(adapter->name, pname, sizeof(adapter->name)); - else -- strlcpy(adapter->name, "opal", sizeof(adapter->name)); -+ strscpy(adapter->name, "opal", sizeof(adapter->name)); - - platform_set_drvdata(pdev, adapter); - rc = i2c_add_adapter(adapter); ---- a/drivers/i2c/busses/i2c-parport.c -+++ b/drivers/i2c/busses/i2c-parport.c -@@ -308,7 +308,7 @@ static void i2c_parport_attach(struct pa - /* Fill the rest of the structure */ - adapter->adapter.owner = THIS_MODULE; - adapter->adapter.class = I2C_CLASS_HWMON; -- strlcpy(adapter->adapter.name, "Parallel port adapter", -+ strscpy(adapter->adapter.name, "Parallel port adapter", - sizeof(adapter->adapter.name)); - adapter->algo_data = parport_algo_data; - /* Slow down if we can't sense SCL */ ---- a/drivers/i2c/busses/i2c-pxa.c -+++ b/drivers/i2c/busses/i2c-pxa.c -@@ -1403,7 +1403,7 @@ static int i2c_pxa_probe(struct platform - spin_lock_init(&i2c->lock); - init_waitqueue_head(&i2c->wait); - -- strlcpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name)); -+ strscpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name)); - - i2c->clk = devm_clk_get(&dev->dev, NULL); - if (IS_ERR(i2c->clk)) { ---- a/drivers/i2c/busses/i2c-qcom-geni.c -+++ b/drivers/i2c/busses/i2c-qcom-geni.c -@@ -577,7 +577,7 @@ static int geni_i2c_probe(struct platfor - i2c_set_adapdata(&gi2c->adap, gi2c); - gi2c->adap.dev.parent = dev; - gi2c->adap.dev.of_node = dev->of_node; -- strlcpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name)); -+ strscpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name)); - - ret = geni_icc_get(&gi2c->se, "qup-memory"); - if (ret) ---- a/drivers/i2c/busses/i2c-qup.c -+++ b/drivers/i2c/busses/i2c-qup.c -@@ -1878,7 +1878,7 @@ nodma: - qup->adap.dev.of_node = pdev->dev.of_node; - qup->is_last = true; - -- strlcpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name)); -+ strscpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name)); - - pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC); - pm_runtime_use_autosuspend(qup->dev); ---- a/drivers/i2c/busses/i2c-rcar.c -+++ b/drivers/i2c/busses/i2c-rcar.c -@@ -1059,7 +1059,7 @@ static int rcar_i2c_probe(struct platfor - adap->bus_recovery_info = &rcar_i2c_bri; - adap->quirks = &rcar_i2c_quirks; - i2c_set_adapdata(adap, priv); -- strlcpy(adap->name, pdev->name, sizeof(adap->name)); -+ strscpy(adap->name, pdev->name, sizeof(adap->name)); - - /* Init DMA */ - sg_init_table(&priv->sg, 1); ---- a/drivers/i2c/busses/i2c-riic.c -+++ b/drivers/i2c/busses/i2c-riic.c -@@ -447,7 +447,7 @@ static int riic_i2c_probe(struct platfor - - adap = &riic->adapter; - i2c_set_adapdata(adap, riic); -- strlcpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name)); -+ strscpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name)); - adap->owner = THIS_MODULE; - adap->algo = &riic_algo; - adap->dev.parent = &pdev->dev; ---- a/drivers/i2c/busses/i2c-rk3x.c -+++ b/drivers/i2c/busses/i2c-rk3x.c -@@ -1240,7 +1240,7 @@ static int rk3x_i2c_probe(struct platfor - /* use common interface to get I2C timing properties */ - i2c_parse_fw_timings(&pdev->dev, &i2c->t, true); - -- strlcpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name)); -+ strscpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name)); - i2c->adap.owner = THIS_MODULE; - i2c->adap.algo = &rk3x_i2c_algorithm; - i2c->adap.retries = 3; ---- a/drivers/i2c/busses/i2c-s3c2410.c -+++ b/drivers/i2c/busses/i2c-s3c2410.c -@@ -1076,7 +1076,7 @@ static int s3c24xx_i2c_probe(struct plat - else - s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c); - -- strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name)); -+ strscpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name)); - i2c->adap.owner = THIS_MODULE; - i2c->adap.algo = &s3c24xx_i2c_algorithm; - i2c->adap.retries = 2; ---- a/drivers/i2c/busses/i2c-sh_mobile.c -+++ b/drivers/i2c/busses/i2c-sh_mobile.c -@@ -930,7 +930,7 @@ static int sh_mobile_i2c_probe(struct pl - adap->nr = dev->id; - adap->dev.of_node = dev->dev.of_node; - -- strlcpy(adap->name, dev->name, sizeof(adap->name)); -+ strscpy(adap->name, dev->name, sizeof(adap->name)); - - spin_lock_init(&pd->lock); - init_waitqueue_head(&pd->wait); ---- a/drivers/i2c/busses/i2c-simtec.c -+++ b/drivers/i2c/busses/i2c-simtec.c -@@ -99,7 +99,7 @@ static int simtec_i2c_probe(struct platf - pd->adap.algo_data = &pd->bit; - pd->adap.dev.parent = &dev->dev; - -- strlcpy(pd->adap.name, "Simtec I2C", sizeof(pd->adap.name)); -+ strscpy(pd->adap.name, "Simtec I2C", sizeof(pd->adap.name)); - - pd->bit.data = pd; - pd->bit.setsda = simtec_i2c_setsda; ---- a/drivers/i2c/busses/i2c-taos-evm.c -+++ b/drivers/i2c/busses/i2c-taos-evm.c -@@ -239,7 +239,7 @@ static int taos_connect(struct serio *se - dev_err(&serio->dev, "TAOS EVM identification failed\n"); - goto exit_close; - } -- strlcpy(adapter->name, name, sizeof(adapter->name)); -+ strscpy(adapter->name, name, sizeof(adapter->name)); - - /* Turn echo off for better performance */ - taos->state = TAOS_STATE_EOFF; ---- a/drivers/i2c/busses/i2c-tegra-bpmp.c -+++ b/drivers/i2c/busses/i2c-tegra-bpmp.c -@@ -305,7 +305,7 @@ static int tegra_bpmp_i2c_probe(struct p - - i2c_set_adapdata(&i2c->adapter, i2c); - i2c->adapter.owner = THIS_MODULE; -- strlcpy(i2c->adapter.name, "Tegra BPMP I2C adapter", -+ strscpy(i2c->adapter.name, "Tegra BPMP I2C adapter", - sizeof(i2c->adapter.name)); - i2c->adapter.algo = &tegra_bpmp_i2c_algo; - i2c->adapter.dev.parent = &pdev->dev; ---- a/drivers/i2c/busses/i2c-tegra.c -+++ b/drivers/i2c/busses/i2c-tegra.c -@@ -1799,7 +1799,7 @@ static int tegra_i2c_probe(struct platfo - if (i2c_dev->hw->supports_bus_clear) - i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info; - -- strlcpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev), -+ strscpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev), - sizeof(i2c_dev->adapter.name)); - - err = i2c_add_numbered_adapter(&i2c_dev->adapter); ---- a/drivers/i2c/busses/i2c-uniphier-f.c -+++ b/drivers/i2c/busses/i2c-uniphier-f.c -@@ -564,7 +564,7 @@ static int uniphier_fi2c_probe(struct pl - priv->adap.algo = &uniphier_fi2c_algo; - priv->adap.dev.parent = dev; - priv->adap.dev.of_node = dev->of_node; -- strlcpy(priv->adap.name, "UniPhier FI2C", sizeof(priv->adap.name)); -+ strscpy(priv->adap.name, "UniPhier FI2C", sizeof(priv->adap.name)); - priv->adap.bus_recovery_info = &uniphier_fi2c_bus_recovery_info; - i2c_set_adapdata(&priv->adap, priv); - platform_set_drvdata(pdev, priv); ---- a/drivers/i2c/busses/i2c-uniphier.c -+++ b/drivers/i2c/busses/i2c-uniphier.c -@@ -358,7 +358,7 @@ static int uniphier_i2c_probe(struct pla - priv->adap.algo = &uniphier_i2c_algo; - priv->adap.dev.parent = dev; - priv->adap.dev.of_node = dev->of_node; -- strlcpy(priv->adap.name, "UniPhier I2C", sizeof(priv->adap.name)); -+ strscpy(priv->adap.name, "UniPhier I2C", sizeof(priv->adap.name)); - priv->adap.bus_recovery_info = &uniphier_i2c_bus_recovery_info; - i2c_set_adapdata(&priv->adap, priv); - platform_set_drvdata(pdev, priv); ---- a/drivers/i2c/busses/i2c-versatile.c -+++ b/drivers/i2c/busses/i2c-versatile.c -@@ -79,7 +79,7 @@ static int i2c_versatile_probe(struct pl - writel(SCL | SDA, i2c->base + I2C_CONTROLS); - - i2c->adap.owner = THIS_MODULE; -- strlcpy(i2c->adap.name, "Versatile I2C adapter", sizeof(i2c->adap.name)); -+ strscpy(i2c->adap.name, "Versatile I2C adapter", sizeof(i2c->adap.name)); - i2c->adap.algo_data = &i2c->algo; - i2c->adap.dev.parent = &dev->dev; - i2c->adap.dev.of_node = dev->dev.of_node; ---- a/drivers/i2c/busses/i2c-wmt.c -+++ b/drivers/i2c/busses/i2c-wmt.c -@@ -413,7 +413,7 @@ static int wmt_i2c_probe(struct platform - - adap = &i2c_dev->adapter; - i2c_set_adapdata(adap, i2c_dev); -- strlcpy(adap->name, "WMT I2C adapter", sizeof(adap->name)); -+ strscpy(adap->name, "WMT I2C adapter", sizeof(adap->name)); - adap->owner = THIS_MODULE; - adap->algo = &wmt_i2c_algo; - adap->dev.parent = &pdev->dev; diff --git a/target/linux/mediatek/patches-6.1/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch b/target/linux/mediatek/patches-6.1/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch index f779c1e0473..600b94d7bbe 100644 --- a/target/linux/mediatek/patches-6.1/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch +++ b/target/linux/mediatek/patches-6.1/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -318,7 +318,7 @@ +@@ -314,7 +314,7 @@ /* Attention: GPIO 90 is used to switch between PCIe@1,0 and * SATA functions. i.e. output-high: PCIe, output-low: SATA */ diff --git a/target/linux/mediatek/patches-6.1/901-arm-add-cmdline-override.patch b/target/linux/mediatek/patches-6.1/901-arm-add-cmdline-override.patch index 6016128bd4a..602bac5d3d4 100644 --- a/target/linux/mediatek/patches-6.1/901-arm-add-cmdline-override.patch +++ b/target/linux/mediatek/patches-6.1/901-arm-add-cmdline-override.patch @@ -1,6 +1,6 @@ --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig -@@ -1729,6 +1729,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN +@@ -1588,6 +1588,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN endchoice @@ -17,27 +17,27 @@ default "" --- a/drivers/of/fdt.c +++ b/drivers/of/fdt.c -@@ -1162,6 +1162,17 @@ int __init early_init_dt_scan_chosen(uns +@@ -1187,6 +1187,17 @@ int __init early_init_dt_scan_chosen(cha if (p != NULL && l > 0) - strlcat(data, p, min_t(int, strlen(data) + (int)l, COMMAND_LINE_SIZE)); + strlcat(cmdline, p, min_t(int, strlen(cmdline) + (int)l, COMMAND_LINE_SIZE)); -+ /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different -+ * device tree option of chosen/bootargs-override. This is -+ * helpful on boards where u-boot sets bootargs, and is unable -+ * to be modified. -+ */ ++ /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different ++ * device tree option of chosen/bootargs-override. This is ++ * helpful on boards where u-boot sets bootargs, and is unable ++ * to be modified. ++ */ +#ifdef CONFIG_CMDLINE_OVERRIDE + p = of_get_flat_dt_prop(node, "bootargs-override", &l); + if (p != NULL && l > 0) -+ strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE)); ++ strlcpy(cmdline, p, min((int)l, COMMAND_LINE_SIZE)); +#endif + + handle_cmdline: /* * CONFIG_CMDLINE is meant to be a default in case nothing else - * managed to set the command line, unless CONFIG_CMDLINE_FORCE --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig -@@ -1942,6 +1942,14 @@ config CMDLINE_FORCE +@@ -2202,6 +2202,14 @@ config CMDLINE_FORCE endchoice diff --git a/target/linux/mediatek/patches-6.1/910-dts-mt7622-bpi-r64-wifi-eeprom.patch b/target/linux/mediatek/patches-6.1/910-dts-mt7622-bpi-r64-wifi-eeprom.patch index 2a863aecf93..a45d51dd9f0 100644 --- a/target/linux/mediatek/patches-6.1/910-dts-mt7622-bpi-r64-wifi-eeprom.patch +++ b/target/linux/mediatek/patches-6.1/910-dts-mt7622-bpi-r64-wifi-eeprom.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -645,5 +645,28 @@ +@@ -641,5 +641,28 @@ }; &wmac { diff --git a/target/linux/mediatek/patches-6.1/920-v5.16-watchdog-mtk-add-disable_wdt_extrst-support.patch b/target/linux/mediatek/patches-6.1/920-v5.16-watchdog-mtk-add-disable_wdt_extrst-support.patch deleted file mode 100644 index d9379721fb8..00000000000 --- a/target/linux/mediatek/patches-6.1/920-v5.16-watchdog-mtk-add-disable_wdt_extrst-support.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 59b0f51335644ee603260faaa4298c0115fb7187 Mon Sep 17 00:00:00 2001 -From: Fengquan Chen -Date: Tue, 14 Sep 2021 20:34:54 +0800 -Subject: [PATCH] watchdog: mtk: add disable_wdt_extrst support - -In some cases, we may need watchdog just to trigger an -internal soc reset without sending any output signal. - -Provide a disable_wdt_extrst parameter for configuration. -We can disable or enable it just by configuring dts. - -Signed-off-by: Fengquan Chen -Reviewed-by: Guenter Roeck -Link: https://lore.kernel.org/r/20210914123454.32603-3-Fengquan.Chen@mediatek.com -Signed-off-by: Guenter Roeck -Signed-off-by: Wim Van Sebroeck ---- - drivers/watchdog/mtk_wdt.c | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/drivers/watchdog/mtk_wdt.c -+++ b/drivers/watchdog/mtk_wdt.c -@@ -65,6 +65,7 @@ struct mtk_wdt_dev { - void __iomem *wdt_base; - spinlock_t lock; /* protects WDT_SWSYSRST reg */ - struct reset_controller_dev rcdev; -+ bool disable_wdt_extrst; - }; - - struct mtk_wdt_data { -@@ -256,6 +257,8 @@ static int mtk_wdt_start(struct watchdog - reg |= (WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN); - else - reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN); -+ if (mtk_wdt->disable_wdt_extrst) -+ reg &= ~WDT_MODE_EXRST_EN; - reg |= (WDT_MODE_EN | WDT_MODE_KEY); - iowrite32(reg, wdt_base + WDT_MODE); - -@@ -381,6 +384,10 @@ static int mtk_wdt_probe(struct platform - if (err) - return err; - } -+ -+ mtk_wdt->disable_wdt_extrst = -+ of_property_read_bool(dev->of_node, "mediatek,disable-extrst"); -+ - return 0; - } - diff --git a/target/linux/mediatek/patches-6.1/921-v5.19-watchdog-mtk_wdt-mt7986-Add-toprgu-reset-controller.patch b/target/linux/mediatek/patches-6.1/921-v5.19-watchdog-mtk_wdt-mt7986-Add-toprgu-reset-controller.patch deleted file mode 100644 index 96fb215f76c..00000000000 --- a/target/linux/mediatek/patches-6.1/921-v5.19-watchdog-mtk_wdt-mt7986-Add-toprgu-reset-controller.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 711a5b25bac95dcd1111521ed71693330e74a926 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Wed, 5 Jan 2022 18:04:56 +0800 -Subject: [PATCH] watchdog: mtk_wdt: mt7986: Add toprgu reset controller - support - -Besides watchdog, the mt7986 toprgu module also provides software reset -functionality for various peripheral subsystems -(eg, ethernet, pcie, and connectivity) - -Signed-off-by: Sam Shih -Reviewed-by: Matthias Brugger -Reviewed-by: Guenter Roeck -Link: https://lore.kernel.org/r/20220105100456.7126-3-sam.shih@mediatek.com -Signed-off-by: Guenter Roeck -Signed-off-by: Wim Van Sebroeck ---- - drivers/watchdog/mtk_wdt.c | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/drivers/watchdog/mtk_wdt.c -+++ b/drivers/watchdog/mtk_wdt.c -@@ -10,6 +10,7 @@ - */ - - #include -+#include - #include - #include - #include -@@ -76,6 +77,10 @@ static const struct mtk_wdt_data mt2712_ - .toprgu_sw_rst_num = MT2712_TOPRGU_SW_RST_NUM, - }; - -+static const struct mtk_wdt_data mt7986_data = { -+ .toprgu_sw_rst_num = MT7986_TOPRGU_SW_RST_NUM, -+}; -+ - static const struct mtk_wdt_data mt8183_data = { - .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM, - }; -@@ -418,6 +423,7 @@ static int mtk_wdt_resume(struct device - static const struct of_device_id mtk_wdt_dt_ids[] = { - { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data }, - { .compatible = "mediatek,mt6589-wdt" }, -+ { .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data }, - { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data }, - { .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data }, - { .compatible = "mediatek,mt8195-wdt", .data = &mt8195_data }, diff --git a/target/linux/mediatek/patches-6.1/922-v6.1-PCI-mediatek-gen3-change-driver-name-to-mtk-pcie-gen.patch b/target/linux/mediatek/patches-6.1/922-v6.1-PCI-mediatek-gen3-change-driver-name-to-mtk-pcie-gen.patch deleted file mode 100644 index 44aed2207d5..00000000000 --- a/target/linux/mediatek/patches-6.1/922-v6.1-PCI-mediatek-gen3-change-driver-name-to-mtk-pcie-gen.patch +++ /dev/null @@ -1,20 +0,0 @@ -From: Felix Fietkau -Date: Wed, 4 May 2022 12:03:42 +0200 -Subject: [PATCH] PCI: mediatek-gen3: change driver name to mtk-pcie-gen3 - -This allows it to coexist with the other mtk pcie driver in the same kernel - -Signed-off-by: Felix Fietkau ---- - ---- a/drivers/pci/controller/pcie-mediatek-gen3.c -+++ b/drivers/pci/controller/pcie-mediatek-gen3.c -@@ -1025,7 +1025,7 @@ static struct platform_driver mtk_pcie_d - .probe = mtk_pcie_probe, - .remove = mtk_pcie_remove, - .driver = { -- .name = "mtk-pcie", -+ .name = "mtk-pcie-gen3", - .of_match_table = mtk_pcie_of_match, - .pm = &mtk_pcie_pm_ops, - }, diff --git a/target/linux/mediatek/patches-6.1/930-spi-mt65xx-enable-sel-clk.patch b/target/linux/mediatek/patches-6.1/930-spi-mt65xx-enable-sel-clk.patch index ebb6c060b54..6e6810b42af 100644 --- a/target/linux/mediatek/patches-6.1/930-spi-mt65xx-enable-sel-clk.patch +++ b/target/linux/mediatek/patches-6.1/930-spi-mt65xx-enable-sel-clk.patch @@ -1,29 +1,18 @@ --- a/drivers/spi/spi-mt65xx.c +++ b/drivers/spi/spi-mt65xx.c -@@ -1231,10 +1231,16 @@ static int mtk_spi_probe(struct platform - goto err_disable_spi_hclk; - } +@@ -1225,8 +1225,15 @@ static int mtk_spi_probe(struct platform + if (ret < 0) + return dev_err_probe(dev, ret, "failed to enable hclk\n"); + ret = clk_prepare_enable(mdata->sel_clk); + if (ret < 0) { -+ dev_err(&pdev->dev, "failed to enable sel_clk (%d)\n", ret); -+ goto err_disable_spi_clk; ++ clk_disable_unprepare(mdata->spi_hclk); ++ return dev_err_probe(dev, ret, "failed to enable sel_clk\n"); + } + - ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk); + ret = clk_prepare_enable(mdata->spi_clk); if (ret < 0) { - dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret); -- goto err_disable_spi_clk; -+ goto err_disable_spi_sel_clk; ++ clk_disable_unprepare(mdata->sel_clk); + clk_disable_unprepare(mdata->spi_hclk); + return dev_err_probe(dev, ret, "failed to enable spi_clk\n"); } - - mdata->spi_clk_hz = clk_get_rate(mdata->spi_clk); -@@ -1285,6 +1291,8 @@ static int mtk_spi_probe(struct platform - - err_disable_runtime_pm: - pm_runtime_disable(&pdev->dev); -+err_disable_spi_sel_clk: -+ clk_disable_unprepare(mdata->sel_clk); - err_disable_spi_clk: - clk_disable_unprepare(mdata->spi_clk); - err_disable_spi_hclk: diff --git a/target/linux/mediatek/patches-6.1/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch b/target/linux/mediatek/patches-6.1/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch index a455005504c..fb3940f5447 100644 --- a/target/linux/mediatek/patches-6.1/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch +++ b/target/linux/mediatek/patches-6.1/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch @@ -22,7 +22,7 @@ Signed-off-by: Lorenzo Bianconi --- a/drivers/net/ethernet/mediatek/mtk_wed.c +++ b/drivers/net/ethernet/mediatek/mtk_wed.c -@@ -813,6 +813,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device +@@ -806,6 +806,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device struct device_node *np; int index; @@ -47,7 +47,7 @@ Signed-off-by: Lorenzo Bianconi index = of_property_match_string(dev->hw->node, "memory-region-names", "wo-dlm"); if (index < 0) -@@ -829,6 +847,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device +@@ -822,6 +840,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device return -ENODEV; dev->rro.miod_phys = rmem->base; From 775fd1fc85f9c507638d65835f27a65eeaeb7a90 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Tue, 27 Jun 2023 02:22:57 +0200 Subject: [PATCH 30/53] mediatek: copy config-5.15 to config-6.1 for all subtargets To ease review, first copy all subtargets' kernel config-5.15 to the to-be-adapted config-6.1. Signed-off-by: Daniel Golle --- target/linux/mediatek/filogic/config-6.1 | 439 +++++++++++++++++ target/linux/mediatek/mt7622/config-6.1 | 458 ++++++++++++++++++ target/linux/mediatek/mt7623/config-6.1 | 576 +++++++++++++++++++++++ target/linux/mediatek/mt7629/config-6.1 | 325 +++++++++++++ 4 files changed, 1798 insertions(+) create mode 100644 target/linux/mediatek/filogic/config-6.1 create mode 100644 target/linux/mediatek/mt7622/config-6.1 create mode 100644 target/linux/mediatek/mt7623/config-6.1 create mode 100644 target/linux/mediatek/mt7629/config-6.1 diff --git a/target/linux/mediatek/filogic/config-6.1 b/target/linux/mediatek/filogic/config-6.1 new file mode 100644 index 00000000000..4cae8c50ac7 --- /dev/null +++ b/target/linux/mediatek/filogic/config-6.1 @@ -0,0 +1,439 @@ +CONFIG_64BIT=y +# CONFIG_AHCI_MTK is not set +CONFIG_AQUANTIA_PHY=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 +CONFIG_ARCH_PROC_KCORE_TEXT=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_WANTS_NO_INSTR=y +CONFIG_ARM64=y +CONFIG_ARM64_4K_PAGES=y +CONFIG_ARM64_CRYPTO=y +CONFIG_ARM64_ERRATUM_843419=y +CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y +CONFIG_ARM64_PAGE_SHIFT=12 +CONFIG_ARM64_PA_BITS=48 +CONFIG_ARM64_PA_BITS_48=y +CONFIG_ARM64_TAGGED_ADDR_ABI=y +CONFIG_ARM64_VA_BITS=39 +CONFIG_ARM64_VA_BITS_39=y +CONFIG_ARM_AMBA=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_V2M=y +CONFIG_ARM_GIC_V3=y +CONFIG_ARM_GIC_V3_ITS=y +CONFIG_ARM_GIC_V3_ITS_PCI=y +CONFIG_ARM_MEDIATEK_CPUFREQ=y +CONFIG_ARM_PMU=y +CONFIG_ARM_PSCI_FW=y +CONFIG_ATA=y +CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_PM=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_CC_HAVE_SHADOW_CALL_STACK=y +CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE_OVERRIDE=y +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_MEDIATEK=y +# CONFIG_COMMON_CLK_MT2712 is not set +# CONFIG_COMMON_CLK_MT6779 is not set +# CONFIG_COMMON_CLK_MT6797 is not set +# CONFIG_COMMON_CLK_MT7622 is not set +CONFIG_COMMON_CLK_MT7981=y +CONFIG_COMMON_CLK_MT7981_ETHSYS=y +CONFIG_COMMON_CLK_MT7986=y +CONFIG_COMMON_CLK_MT7986_ETHSYS=y +CONFIG_COMMON_CLK_MT7988=y +# CONFIG_COMMON_CLK_MT8173 is not set +# CONFIG_COMMON_CLK_MT8183 is not set +# CONFIG_COMMON_CLK_MT8516 is not set +# CONFIG_COMPAT_32BIT_TIME is not set +CONFIG_CONFIGFS_FS=y +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 +# CONFIG_CPUFREQ_DT is not set +CONFIG_CPU_FREQ=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_THERMAL=y +CONFIG_CRC16=y +CONFIG_CRYPTO_AES_ARM64=y +CONFIG_CRYPTO_AES_ARM64_CE=y +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRYPTD=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_ECC=y +CONFIG_CRYPTO_ECDH=y +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA256_ARM64=y +CONFIG_CRYPTO_SHA2_ARM64_CE=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_SIMD=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_MISC=y +CONFIG_DIMLIB=y +CONFIG_DMADEVICES=y +CONFIG_DMATEST=y +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_ENGINE_RAID=y +CONFIG_DMA_OF=y +CONFIG_DMA_REMAP=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DTC=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EINT_MTK=y +CONFIG_EXT4_FS=y +CONFIG_F2FS_FS=y +CONFIG_FIT_PARTITION=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FRAME_POINTER=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FWNODE_MDIO=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_FIND_FIRST_BIT=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GLOB=y +CONFIG_GPIO_CDEV=y +CONFIG_GRO_CELLS=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HWMON=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_MTK=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MT65XX=y +CONFIG_ICPLUS_PHY=y +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +CONFIG_JUMP_LABEL=y +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAXLINEAR_GPHY=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MEDIATEK_2P5G_PHY=y +CONFIG_MEDIATEK_GE_PHY=y +CONFIG_MEDIATEK_GE_SOC_PHY=y +CONFIG_MEDIATEK_WATCHDOG=y +CONFIG_MEMFD_CREATE=y +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 +CONFIG_MFD_SYSCON=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_CQHCI=y +CONFIG_MMC_MTK=y +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_MEDIATEK=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +CONFIG_MTD_NAND_MTK=y +CONFIG_MTD_NAND_MTK_BMT=y +CONFIG_MTD_PARSER_TRX=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_FIT_FW=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +# CONFIG_MTK_CMDQ is not set +# CONFIG_MTK_CQDMA is not set +CONFIG_MTK_HSDMA=y +CONFIG_MTK_INFRACFG=y +CONFIG_MTK_PMIC_WRAP=y +CONFIG_MTK_SCPSYS=y +CONFIG_MTK_SCPSYS_PM_DOMAINS=y +CONFIG_MTK_THERMAL=y +CONFIG_MTK_TIMER=y +# CONFIG_MTK_UART_APDMA is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_MT7530=y +CONFIG_NET_DSA_MT7530_MDIO=y +CONFIG_NET_DSA_MT7530_MMIO=y +CONFIG_NET_DSA_TAG_MTK=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_MEDIATEK_SOC=y +CONFIG_NET_MEDIATEK_SOC_USXGMII=y +CONFIG_NET_MEDIATEK_SOC_WED=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SWITCHDEV=y +CONFIG_NET_VENDOR_MEDIATEK=y +CONFIG_NLS=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=4 +CONFIG_NVMEM=y +CONFIG_NVMEM_MTK_EFUSE=y +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_OVERLAY=y +CONFIG_OF_RESOLVE=y +CONFIG_PADATA=y +CONFIG_PAGE_POOL=y +CONFIG_PAGE_POOL_STATS=y +CONFIG_PARTITION_PERCPU=y +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIEASPM=y +# CONFIG_PCIEASPM_DEFAULT is not set +CONFIG_PCIEASPM_PERFORMANCE=y +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +CONFIG_PCIEPORTBUS=y +# CONFIG_PCIE_MEDIATEK is not set +CONFIG_PCIE_MEDIATEK_GEN3=y +CONFIG_PCIE_PME=y +CONFIG_PCI_DEBUG=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PCS_MTK_LYNXI=y +CONFIG_PERF_EVENTS=y +CONFIG_PGTABLE_LEVELS=3 +CONFIG_PHYLIB=y +CONFIG_PHYLINK=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_PHY_MTK_TPHY=y +# CONFIG_PHY_MTK_UFS is not set +# CONFIG_PHY_MTK_XSPHY is not set +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_MT2712 is not set +# CONFIG_PINCTRL_MT6765 is not set +# CONFIG_PINCTRL_MT6797 is not set +# CONFIG_PINCTRL_MT7622 is not set +CONFIG_PINCTRL_MT7981=y +CONFIG_PINCTRL_MT7986=y +CONFIG_PINCTRL_MT7988=y +# CONFIG_PINCTRL_MT8173 is not set +# CONFIG_PINCTRL_MT8183 is not set +CONFIG_PINCTRL_MT8516=y +CONFIG_PINCTRL_MTK=y +CONFIG_PINCTRL_MTK_MOORE=y +CONFIG_PINCTRL_MTK_V2=y +CONFIG_PM=y +CONFIG_PM_CLK=y +CONFIG_PM_GENERIC_DOMAINS=y +CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_PM_OPP=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_SUPPLY=y +CONFIG_PRINTK_TIME=y +CONFIG_PSTORE=y +CONFIG_PSTORE_COMPRESS=y +CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_DEFLATE_COMPRESS=y +CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y +CONFIG_PSTORE_PMSG=y +CONFIG_PSTORE_RAM=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_PWM=y +CONFIG_PWM_MEDIATEK=y +# CONFIG_PWM_MTK_DISP is not set +CONFIG_PWM_SYSFS=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_RAS=y +CONFIG_RATIONAL=y +# CONFIG_RAVE_SP_CORE is not set +CONFIG_REALTEK_PHY=y +CONFIG_REED_SOLOMON=y +CONFIG_REED_SOLOMON_DEC8=y +CONFIG_REED_SOLOMON_ENC8=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_MT6380=y +CONFIG_REGULATOR_RT5190A=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_TI_SYSCON=y +CONFIG_RFS_ACCEL=y +CONFIG_RODATA_FULL_DEFAULT_ENABLED=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_MT7622=y +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RTL8367S_GSW=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_SCHED_MC=y +CONFIG_SCSI=y +CONFIG_SCSI_COMMON=y +# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_8250_MT6577=y +CONFIG_SERIAL_8250_NR_UARTS=3 +CONFIG_SERIAL_8250_RUNTIME_UARTS=3 +CONFIG_SERIAL_DEV_BUS=y +CONFIG_SERIAL_DEV_CTRL_TTYPORT=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SGL_ALLOC=y +CONFIG_SG_POOL=y +CONFIG_SMP=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_DYNAMIC=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SPI_MT65XX=y +CONFIG_SPI_MTK_NOR=y +CONFIG_SPI_MTK_SNFI=y +CONFIG_SRCU=y +CONFIG_SWIOTLB=y +CONFIG_SWPHY=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_THERMAL=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_GOV_BANG_BANG=y +CONFIG_THERMAL_GOV_FAIR_SHARE=y +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_GOV_USER_SPACE=y +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_UBIFS_FS=y +# CONFIG_UCLAMP_TASK is not set +# CONFIG_UNMAP_KERNEL_AT_EL0 is not set +CONFIG_USB_SUPPORT=y +CONFIG_VMAP_STACK=y +CONFIG_WATCHDOG_CORE=y +CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y +CONFIG_WATCHDOG_PRETIMEOUT_GOV=y +# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set +CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y +CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m +CONFIG_WATCHDOG_SYSFS=y +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA32=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/mediatek/mt7622/config-6.1 b/target/linux/mediatek/mt7622/config-6.1 new file mode 100644 index 00000000000..30a5ff948fa --- /dev/null +++ b/target/linux/mediatek/mt7622/config-6.1 @@ -0,0 +1,458 @@ +CONFIG_64BIT=y +# CONFIG_AHCI_MTK is not set +CONFIG_AQUANTIA_PHY=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 +CONFIG_ARCH_PROC_KCORE_TEXT=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_WANTS_NO_INSTR=y +CONFIG_ARM64=y +CONFIG_ARM64_4K_PAGES=y +# CONFIG_ARM64_CNP is not set +CONFIG_ARM64_CRYPTO=y +CONFIG_ARM64_ERRATUM_843419=y +CONFIG_ARM64_ERRATUM_845719=y +CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y +CONFIG_ARM64_PAGE_SHIFT=12 +CONFIG_ARM64_PA_BITS=48 +CONFIG_ARM64_PA_BITS_48=y +CONFIG_ARM64_TAGGED_ADDR_ABI=y +CONFIG_ARM64_VA_BITS=39 +CONFIG_ARM64_VA_BITS_39=y +# CONFIG_ARMV8_DEPRECATED is not set +CONFIG_ARM_AMBA=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_V2M=y +CONFIG_ARM_GIC_V3=y +CONFIG_ARM_GIC_V3_ITS=y +CONFIG_ARM_GIC_V3_ITS_PCI=y +CONFIG_ARM_MEDIATEK_CPUFREQ=y +CONFIG_ARM_PMU=y +CONFIG_ARM_PSCI_FW=y +CONFIG_ATA=y +CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_PM=y +CONFIG_BLOCK_COMPAT=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLONE_BACKWARDS=y +# CONFIG_CMDLINE_OVERRIDE is not set +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_MEDIATEK=y +CONFIG_COMMON_CLK_MT2712=y +# CONFIG_COMMON_CLK_MT2712_BDPSYS is not set +# CONFIG_COMMON_CLK_MT2712_IMGSYS is not set +# CONFIG_COMMON_CLK_MT2712_JPGDECSYS is not set +# CONFIG_COMMON_CLK_MT2712_MFGCFG is not set +# CONFIG_COMMON_CLK_MT2712_MMSYS is not set +# CONFIG_COMMON_CLK_MT2712_VDECSYS is not set +# CONFIG_COMMON_CLK_MT2712_VENCSYS is not set +# CONFIG_COMMON_CLK_MT6779 is not set +# CONFIG_COMMON_CLK_MT6797 is not set +CONFIG_COMMON_CLK_MT7622=y +CONFIG_COMMON_CLK_MT7622_AUDSYS=y +CONFIG_COMMON_CLK_MT7622_ETHSYS=y +CONFIG_COMMON_CLK_MT7622_HIFSYS=y +# CONFIG_COMMON_CLK_MT7981 is not set +# CONFIG_COMMON_CLK_MT7986 is not set +# CONFIG_COMMON_CLK_MT7988 is not set +# CONFIG_COMMON_CLK_MT8173 is not set +# CONFIG_COMMON_CLK_MT8183 is not set +# CONFIG_COMMON_CLK_MT8183_AUDIOSYS is not set +# CONFIG_COMMON_CLK_MT8183_CAMSYS is not set +# CONFIG_COMMON_CLK_MT8183_IMGSYS is not set +# CONFIG_COMMON_CLK_MT8183_IPU_ADL is not set +# CONFIG_COMMON_CLK_MT8183_IPU_CONN is not set +# CONFIG_COMMON_CLK_MT8183_IPU_CORE0 is not set +# CONFIG_COMMON_CLK_MT8183_IPU_CORE1 is not set +# CONFIG_COMMON_CLK_MT8183_MFGCFG is not set +# CONFIG_COMMON_CLK_MT8183_MMSYS is not set +# CONFIG_COMMON_CLK_MT8183_VDECSYS is not set +# CONFIG_COMMON_CLK_MT8183_VENCSYS is not set +# CONFIG_COMMON_CLK_MT8516 is not set +# CONFIG_COMMON_CLK_MT8516_AUDSYS is not set +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONFIGFS_FS=y +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 +# CONFIG_CPUFREQ_DT is not set +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_THERMAL=y +CONFIG_CRC16=y +CONFIG_CRYPTO_AES_ARM64=y +CONFIG_CRYPTO_AES_ARM64_CE=y +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_BLAKE2S=y +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRYPTD=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_ECC=y +CONFIG_CRYPTO_ECDH=y +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA256_ARM64=y +CONFIG_CRYPTO_SHA2_ARM64_CE=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_SIMD=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_MISC=y +CONFIG_DIMLIB=y +CONFIG_DMADEVICES=y +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_ENGINE_RAID=y +CONFIG_DMA_OF=y +CONFIG_DMA_REMAP=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DTC=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EINT_MTK=y +CONFIG_EXT4_FS=y +CONFIG_F2FS_FS=y +CONFIG_FIT_PARTITION=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FRAME_POINTER=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FWNODE_MDIO=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_FIND_FIRST_BIT=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GLOB=y +CONFIG_GPIO_CDEV=y +CONFIG_GRO_CELLS=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_MTK=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MT65XX=y +CONFIG_ICPLUS_PHY=y +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +CONFIG_JUMP_LABEL=y +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +# CONFIG_MEDIATEK_2P5G_PHY is not set +CONFIG_MEDIATEK_GE_PHY=y +# CONFIG_MEDIATEK_GE_SOC_PHY is not set +CONFIG_MEDIATEK_WATCHDOG=y +CONFIG_MEMFD_CREATE=y +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 +CONFIG_MFD_SYSCON=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_CQHCI=y +CONFIG_MMC_MTK=y +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_MEDIATEK=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +CONFIG_MTD_NAND_MTK=y +CONFIG_MTD_NAND_MTK_BMT=y +CONFIG_MTD_PARSER_TRX=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_FIT_FW=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +# CONFIG_MTK_CMDQ is not set +# CONFIG_MTK_CQDMA is not set +CONFIG_MTK_HSDMA=y +CONFIG_MTK_INFRACFG=y +CONFIG_MTK_PMIC_WRAP=y +CONFIG_MTK_SCPSYS=y +CONFIG_MTK_SCPSYS_PM_DOMAINS=y +CONFIG_MTK_THERMAL=y +CONFIG_MTK_TIMER=y +# CONFIG_MTK_UART_APDMA is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_MT7530=y +CONFIG_NET_DSA_MT7530_MDIO=y +# CONFIG_NET_DSA_MT7530_MMIO is not set +CONFIG_NET_DSA_TAG_MTK=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_MEDIATEK_SOC=y +# CONFIG_NET_MEDIATEK_SOC_USXGMII is not set +CONFIG_NET_MEDIATEK_SOC_WED=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SWITCHDEV=y +CONFIG_NET_VENDOR_MEDIATEK=y +CONFIG_NLS=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=2 +CONFIG_NVMEM=y +CONFIG_NVMEM_MTK_EFUSE=y +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_OVERLAY=y +CONFIG_OF_RESOLVE=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_PADATA=y +CONFIG_PARTITION_PERCPU=y +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIEASPM=y +# CONFIG_PCIEASPM_DEFAULT is not set +CONFIG_PCIEASPM_PERFORMANCE=y +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_MEDIATEK=y +CONFIG_PCIE_PME=y +CONFIG_PCI_DEBUG=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PERF_EVENTS=y +CONFIG_PGTABLE_LEVELS=3 +CONFIG_PHYLIB=y +CONFIG_PHYLINK=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_PHY_MTK_TPHY=y +# CONFIG_PHY_MTK_UFS is not set +# CONFIG_PHY_MTK_XSPHY is not set +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_MT2712 is not set +# CONFIG_PINCTRL_MT6765 is not set +# CONFIG_PINCTRL_MT6797 is not set +CONFIG_PINCTRL_MT7622=y +# CONFIG_PINCTRL_MT7981 is not set +# CONFIG_PINCTRL_MT7986 is not set +# CONFIG_PINCTRL_MT7988 is not set +# CONFIG_PINCTRL_MT8173 is not set +# CONFIG_PINCTRL_MT8183 is not set +CONFIG_PINCTRL_MT8516=y +CONFIG_PINCTRL_MTK=y +CONFIG_PINCTRL_MTK_MOORE=y +CONFIG_PINCTRL_MTK_V2=y +CONFIG_PM=y +CONFIG_PM_CLK=y +CONFIG_PM_GENERIC_DOMAINS=y +CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_PM_OPP=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_SUPPLY=y +CONFIG_PRINTK_TIME=y +CONFIG_PSTORE=y +CONFIG_PSTORE_COMPRESS=y +CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_DEFLATE_COMPRESS=y +CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y +CONFIG_PSTORE_PMSG=y +CONFIG_PSTORE_RAM=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_PWM=y +CONFIG_PWM_MEDIATEK=y +# CONFIG_PWM_MTK_DISP is not set +CONFIG_PWM_SYSFS=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_RAS=y +CONFIG_RATIONAL=y +# CONFIG_RAVE_SP_CORE is not set +CONFIG_REALTEK_PHY=y +CONFIG_REED_SOLOMON=y +CONFIG_REED_SOLOMON_DEC8=y +CONFIG_REED_SOLOMON_ENC8=y +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_MT6380=y +# CONFIG_REGULATOR_RT5190A is not set +CONFIG_RESET_CONTROLLER=y +CONFIG_RFS_ACCEL=y +CONFIG_RODATA_FULL_DEFAULT_ENABLED=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_MT7622=y +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RTL8367S_GSW=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_SCHED_MC=y +CONFIG_SCSI=y +CONFIG_SCSI_COMMON=y +# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_8250_MT6577=y +CONFIG_SERIAL_8250_NR_UARTS=3 +CONFIG_SERIAL_8250_RUNTIME_UARTS=3 +CONFIG_SERIAL_DEV_BUS=y +CONFIG_SERIAL_DEV_CTRL_TTYPORT=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SGL_ALLOC=y +CONFIG_SG_POOL=y +CONFIG_SMP=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_DYNAMIC=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SPI_MT65XX=y +CONFIG_SPI_MTK_NOR=y +CONFIG_SPI_MTK_SNFI=y +CONFIG_SRCU=y +CONFIG_SWCONFIG=y +CONFIG_SWIOTLB=y +CONFIG_SWPHY=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYSVIPC_COMPAT=y +CONFIG_THERMAL=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_EMULATION=y +CONFIG_THERMAL_GOV_BANG_BANG=y +CONFIG_THERMAL_GOV_FAIR_SHARE=y +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_GOV_USER_SPACE=y +CONFIG_THERMAL_OF=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_UBIFS_FS=y +# CONFIG_UCLAMP_TASK is not set +# CONFIG_UNMAP_KERNEL_AT_EL0 is not set +CONFIG_USB_SUPPORT=y +CONFIG_VMAP_STACK=y +CONFIG_WATCHDOG_CORE=y +CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y +CONFIG_WATCHDOG_PRETIMEOUT_GOV=y +# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set +CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y +CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m +CONFIG_WATCHDOG_SYSFS=y +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA32=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/mediatek/mt7623/config-6.1 b/target/linux/mediatek/mt7623/config-6.1 new file mode 100644 index 00000000000..039a904f197 --- /dev/null +++ b/target/linux/mediatek/mt7623/config-6.1 @@ -0,0 +1,576 @@ +# CONFIG_AIO is not set +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM=y +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +# CONFIG_ARM_ATAG_DTB_COMPAT is not set +CONFIG_ARM_CPU_SUSPEND=y +# CONFIG_ARM_CPU_TOPOLOGY is not set +CONFIG_ARM_CRYPTO=y +CONFIG_ARM_DMA_IOMMU_ALIGNMENT=8 +CONFIG_ARM_DMA_USE_IOMMU=y +CONFIG_ARM_GIC=y +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_MEDIATEK_CPUFREQ=y +CONFIG_ARM_PATCH_IDIV=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +# CONFIG_ARM_SMMU is not set +CONFIG_ARM_THUMB=y +CONFIG_ARM_THUMBEE=y +CONFIG_ARM_UNWIND=y +CONFIG_ARM_VIRT_EXT=y +CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y +CONFIG_ATAGS=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_BACKLIGHT_LED=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_PM=y +CONFIG_BOUNCE=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_CLEANCACHE=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE="earlyprintk console=ttyS0,115200 rootfstype=squashfs,jffs2" +CONFIG_CMDLINE_FROM_BOOTLOADER=y +# CONFIG_CMDLINE_OVERRIDE is not set +CONFIG_CMDLINE_PARTITION=y +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_MEDIATEK=y +CONFIG_COMMON_CLK_MT2701=y +CONFIG_COMMON_CLK_MT2701_AUDSYS=y +CONFIG_COMMON_CLK_MT2701_BDPSYS=y +CONFIG_COMMON_CLK_MT2701_ETHSYS=y +CONFIG_COMMON_CLK_MT2701_G3DSYS=y +CONFIG_COMMON_CLK_MT2701_HIFSYS=y +CONFIG_COMMON_CLK_MT2701_IMGSYS=y +CONFIG_COMMON_CLK_MT2701_MMSYS=y +CONFIG_COMMON_CLK_MT2701_VDECSYS=y +# CONFIG_COMMON_CLK_MT7622 is not set +# CONFIG_COMMON_CLK_MT7629 is not set +# CONFIG_COMMON_CLK_MT7981 is not set +# CONFIG_COMMON_CLK_MT7986 is not set +# CONFIG_COMMON_CLK_MT7988 is not set +# CONFIG_COMMON_CLK_MT8135 is not set +# CONFIG_COMMON_CLK_MT8173 is not set +CONFIG_COMMON_CLK_MT8516=y +# CONFIG_COMMON_CLK_MT8516_AUDSYS is not set +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONFIGFS_FS=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_COREDUMP=y +# CONFIG_CPUFREQ_DT is not set +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_SPECTRE=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRC16=y +# CONFIG_CRC32_SARWATE is not set +CONFIG_CRC32_SLICEBY8=y +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_ALIGN_RODATA=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_GPIO=y +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_LL_INCLUDE="debug/8250.S" +CONFIG_DEBUG_MISC=y +CONFIG_DEBUG_MT6589_UART0=y +# CONFIG_DEBUG_MT8127_UART0 is not set +# CONFIG_DEBUG_MT8135_UART3 is not set +CONFIG_DEBUG_PREEMPT=y +CONFIG_DEBUG_UART_8250=y +CONFIG_DEBUG_UART_8250_SHIFT=2 +CONFIG_DEBUG_UART_PHYS=0x11004000 +CONFIG_DEBUG_UART_VIRT=0xf1004000 +CONFIG_DEBUG_UNCOMPRESS=y +# CONFIG_DEVFREQ_GOV_PASSIVE is not set +# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set +# CONFIG_DEVFREQ_GOV_POWERSAVE is not set +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +# CONFIG_DEVFREQ_GOV_USERSPACE is not set +# CONFIG_DEVFREQ_THERMAL is not set +CONFIG_DIMLIB=y +CONFIG_DMADEVICES=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +CONFIG_DMA_OPS=y +CONFIG_DMA_REMAP=y +CONFIG_DMA_SHARED_BUFFER=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DRM=y +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_DISPLAY_CONNECTOR=y +CONFIG_DRM_FBDEV_EMULATION=y +CONFIG_DRM_FBDEV_OVERALLOC=100 +CONFIG_DRM_GEM_CMA_HELPER=y +CONFIG_DRM_GEM_SHMEM_HELPER=y +CONFIG_DRM_KMS_HELPER=y +CONFIG_DRM_LIMA=y +CONFIG_DRM_LVDS_CODEC=y +CONFIG_DRM_MEDIATEK=y +CONFIG_DRM_MEDIATEK_HDMI=y +CONFIG_DRM_MIPI_DSI=y +CONFIG_DRM_PANEL=y +CONFIG_DRM_PANEL_BRIDGE=y +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y +CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=y +CONFIG_DRM_SCHED=y +CONFIG_DRM_SIMPLE_BRIDGE=y +CONFIG_DTC=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_EARLY_PRINTK=y +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EINT_MTK=y +CONFIG_ELF_CORE=y +CONFIG_EXT4_FS=y +CONFIG_EXTCON=y +CONFIG_F2FS_FS=y +CONFIG_FB=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_CMDLINE=y +CONFIG_FB_DEFERRED_IO=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_FOPS=y +CONFIG_FB_SYS_IMAGEBLIT=y +CONFIG_FIT_PARTITION=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FONT_8x16=y +CONFIG_FONT_8x8=y +CONFIG_FONT_SUPPORT=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_FREEZER=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FWNODE_MDIO=y +CONFIG_FW_CACHE=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_VDSO_32=y +CONFIG_GPIO_CDEV=y +CONFIG_GRO_CELLS=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDEN_BRANCH_PREDICTOR=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAVE_SMP=y +CONFIG_HDMI=y +CONFIG_HID=y +CONFIG_HIGHMEM=y +CONFIG_HIGHPTE=y +CONFIG_HOTPLUG_CPU=y +CONFIG_HWMON=y +CONFIG_HW_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_MTK=y +CONFIG_HZ_FIXED=0 +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MT65XX=y +CONFIG_ICPLUS_PHY=y +CONFIG_IIO=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INPUT=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_KEYBOARD=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_IOMMU_API=y +# CONFIG_IOMMU_DEBUGFS is not set +CONFIG_IOMMU_DEFAULT_DMA_STRICT=y +CONFIG_IOMMU_IO_PGTABLE=y +CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y +# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set +# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set +CONFIG_IOMMU_SUPPORT=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +CONFIG_KALLSYMS=y +CONFIG_KCMP=y +CONFIG_KEYBOARD_MTK_PMIC=y +CONFIG_KMAP_LOCAL=y +CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_PLATFORM=y +CONFIG_LEDS_MT6323=y +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +# CONFIG_MACH_MT2701 is not set +# CONFIG_MACH_MT6589 is not set +# CONFIG_MACH_MT6592 is not set +CONFIG_MACH_MT7623=y +# CONFIG_MACH_MT7629 is not set +# CONFIG_MACH_MT8127 is not set +# CONFIG_MACH_MT8135 is not set +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAILBOX=y +# CONFIG_MAILBOX_TEST is not set +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MDIO_GPIO=y +CONFIG_MEDIATEK_GE_PHY=y +CONFIG_MEDIATEK_MT6577_AUXADC=y +CONFIG_MEDIATEK_WATCHDOG=y +CONFIG_MEMFD_CREATE=y +CONFIG_MEMORY=y +CONFIG_MFD_CORE=y +# CONFIG_MFD_HI6421_SPMI is not set +CONFIG_MFD_MT6397=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_CQHCI=y +CONFIG_MMC_MTK=y +CONFIG_MMC_SDHCI=y +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_NAND_ECC_MEDIATEK is not set +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_UIMAGE_FW=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTK_CMDQ=y +CONFIG_MTK_CMDQ_MBOX=y +CONFIG_MTK_CQDMA=y +# CONFIG_MTK_HSDMA is not set +CONFIG_MTK_INFRACFG=y +CONFIG_MTK_IOMMU=y +CONFIG_MTK_IOMMU_V1=y +CONFIG_MTK_MMSYS=y +CONFIG_MTK_PMIC_WRAP=y +CONFIG_MTK_SCPSYS=y +CONFIG_MTK_SCPSYS_PM_DOMAINS=y +CONFIG_MTK_SMI=y +CONFIG_MTK_THERMAL=y +CONFIG_MTK_TIMER=y +# CONFIG_MTK_UART_APDMA is not set +# CONFIG_MUSB_PIO_ONLY is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NEON=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_MT7530=y +CONFIG_NET_DSA_MT7530_MDIO=y +# CONFIG_NET_DSA_MT7530_MMIO is not set +CONFIG_NET_DSA_TAG_MTK=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_MEDIATEK_SOC=y +CONFIG_NET_MEDIATEK_SOC_WED=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SWITCHDEV=y +CONFIG_NET_VENDOR_MEDIATEK=y +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_NLS=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=4 +CONFIG_NVMEM=y +CONFIG_NVMEM_MTK_EFUSE=y +# CONFIG_NVMEM_SPMI_SDAM is not set +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IOMMU=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_OVERLAY=y +CONFIG_OF_RESOLVE=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_PADATA=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PAGE_POOL=y +CONFIG_PAGE_POOL_STATS=y +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_MEDIATEK=y +CONFIG_PCIE_PME=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PCS_MTK_LYNXI=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHYLINK=y +CONFIG_PHY_MTK_HDMI=y +CONFIG_PHY_MTK_MIPI_DSI=y +CONFIG_PHY_MTK_TPHY=y +# CONFIG_PHY_MTK_UFS is not set +# CONFIG_PHY_MTK_XSPHY is not set +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MT2701=y +CONFIG_PINCTRL_MT6397=y +CONFIG_PINCTRL_MT7623=y +CONFIG_PINCTRL_MTK=y +CONFIG_PINCTRL_MTK_MOORE=y +CONFIG_PINCTRL_MTK_V2=y +CONFIG_PM=y +CONFIG_PM_CLK=y +CONFIG_PM_DEVFREQ=y +# CONFIG_PM_DEVFREQ_EVENT is not set +CONFIG_PM_GENERIC_DOMAINS=y +CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_PM_GENERIC_DOMAINS_SLEEP=y +CONFIG_PM_OPP=y +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +CONFIG_POWER_RESET=y +# CONFIG_POWER_RESET_MT6323 is not set +CONFIG_POWER_SUPPLY=y +CONFIG_POWER_SUPPLY_HWMON=y +CONFIG_PREEMPT=y +CONFIG_PREEMPTION=y +CONFIG_PREEMPT_COUNT=y +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_RCU=y +CONFIG_PRINTK_TIME=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_PWM=y +CONFIG_PWM_MEDIATEK=y +# CONFIG_PWM_MTK_DISP is not set +CONFIG_PWM_SYSFS=y +CONFIG_RAS=y +CONFIG_RATIONAL=y +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_MT6323=y +# CONFIG_REGULATOR_MT6358 is not set +# CONFIG_REGULATOR_MT6380 is not set +# CONFIG_REGULATOR_MT6397 is not set +# CONFIG_REGULATOR_RT5190A is not set +# CONFIG_REGULATOR_QCOM_LABIBB is not set +# CONFIG_REGULATOR_QCOM_SPMI is not set +# CONFIG_REGULATOR_QCOM_USB_VBUS is not set +CONFIG_RESET_CONTROLLER=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_MT6397 is not set +# CONFIG_RTC_DRV_MT7622 is not set +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RTC_MC146818_LIB=y +# CONFIG_RTL8367S_GSW is not set +CONFIG_RWSEM_SPIN_ON_OWNER=y +# CONFIG_SERIAL_8250_DMA is not set +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_8250_MT6577=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SGL_ALLOC=y +CONFIG_SMP=y +# CONFIG_SMP_ON_UP is not set +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_DYNAMIC=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SPI_MT65XX=y +# CONFIG_SPI_MTK_NOR is not set +CONFIG_SPMI=y +# CONFIG_SPMI_HISI3670 is not set +CONFIG_SRCU=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_SWPHY=y +CONFIG_SWP_EMULATE=y +CONFIG_SYNC_FILE=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_THERMAL=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_OF=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TOUCHSCREEN_EDT_FT5X06=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +# CONFIG_UACCE is not set +CONFIG_UBIFS_FS=y +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_UNWINDER_ARM=y +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_F_ACM=y +CONFIG_USB_F_ECM=y +CONFIG_USB_F_MASS_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GPIO_VBUS=y +CONFIG_USB_G_MULTI=y +CONFIG_USB_G_MULTI_CDC=y +# CONFIG_USB_G_MULTI_RNDIS is not set +CONFIG_USB_HID=y +CONFIG_USB_HIDDEV=y +CONFIG_USB_INVENTRA_DMA=y +CONFIG_USB_LIBCOMPOSITE=y +CONFIG_USB_MUSB_DUAL_ROLE=y +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_MUSB_MEDIATEK=y +CONFIG_USB_OTG=y +CONFIG_USB_PHY=y +CONFIG_USB_ROLE_SWITCH=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_U_ETHER=y +CONFIG_USB_U_SERIAL=y +CONFIG_USE_OF=y +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_VIDEOMODE_HELPERS=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_WATCHDOG_CORE=y +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/mediatek/mt7629/config-6.1 b/target/linux/mediatek/mt7629/config-6.1 new file mode 100644 index 00000000000..08089dde2a3 --- /dev/null +++ b/target/linux/mediatek/mt7629/config-6.1 @@ -0,0 +1,325 @@ +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_CRYPTO=y +CONFIG_ARM_GIC=y +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_HEAVY_MB=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_PATCH_IDIV=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_THUMB=y +CONFIG_ARM_UNWIND=y +CONFIG_ARM_VIRT_EXT=y +CONFIG_ATAGS=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_PM=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_CACHE_L2X0=y +# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_CHR_DEV_SCH=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE="rootfstype=squashfs,jffs2" +CONFIG_CMDLINE_FROM_BOOTLOADER=y +CONFIG_CMDLINE_OVERRIDE=y +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_MEDIATEK=y +# CONFIG_COMMON_CLK_MT2701 is not set +# CONFIG_COMMON_CLK_MT7622 is not set +CONFIG_COMMON_CLK_MT7629=y +CONFIG_COMMON_CLK_MT7629_ETHSYS=y +CONFIG_COMMON_CLK_MT7629_HIFSYS=y +# CONFIG_COMMON_CLK_MT7981 is not set +# CONFIG_COMMON_CLK_MT7986 is not set +# CONFIG_COMMON_CLK_MT7988 is not set +# CONFIG_COMMON_CLK_MT8135 is not set +# CONFIG_COMMON_CLK_MT8173 is not set +CONFIG_COMMON_CLK_MT8516=y +# CONFIG_COMMON_CLK_MT8516_AUDSYS is not set +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_SPECTRE=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRC16=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +CONFIG_DEBUG_MISC=y +CONFIG_DEFAULT_HOSTNAME="(mt7629)" +CONFIG_DIMLIB=y +CONFIG_DMA_OPS=y +CONFIG_DMA_REMAP=y +CONFIG_DTC=y +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EINT_MTK=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FWNODE_MDIO=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_VDSO_32=y +CONFIG_GPIO_CDEV=y +CONFIG_GRO_CELLS=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDEN_BRANCH_PREDICTOR=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAVE_SMP=y +CONFIG_HOTPLUG_CPU=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_MTK=y +CONFIG_HZ_FIXED=0 +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_IRQ_WORK=y +# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +# CONFIG_MACH_MT2701 is not set +# CONFIG_MACH_MT6589 is not set +# CONFIG_MACH_MT6592 is not set +# CONFIG_MACH_MT7623 is not set +CONFIG_MACH_MT7629=y +# CONFIG_MACH_MT8127 is not set +# CONFIG_MACH_MT8135 is not set +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MEDIATEK_GE_PHY=y +CONFIG_MEDIATEK_WATCHDOG=y +CONFIG_MEMFD_CREATE=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGRATION=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_MEDIATEK=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +CONFIG_MTD_NAND_MTK_BMT=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_FIT_FW=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +# CONFIG_MTK_CMDQ is not set +CONFIG_MTK_INFRACFG=y +# CONFIG_MTK_PMIC_WRAP is not set +CONFIG_MTK_SCPSYS=y +CONFIG_MTK_SCPSYS_PM_DOMAINS=y +CONFIG_MTK_TIMER=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NETFILTER=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_MT7530=y +CONFIG_NET_DSA_MT7530_MDIO=y +# CONFIG_NET_DSA_MT7530_MMIO is not set +CONFIG_NET_DSA_TAG_MTK=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_MEDIATEK_SOC=y +CONFIG_NET_MEDIATEK_SOC_WED=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SWITCHDEV=y +CONFIG_NET_VENDOR_MEDIATEK=y +CONFIG_NLS=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=2 +CONFIG_NVMEM=y +# CONFIG_NVMEM_MTK_EFUSE is not set +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_PADATA=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PAGE_POOL=y +CONFIG_PAGE_POOL_STATS=y +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_MEDIATEK=y +CONFIG_PCIE_PME=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PCS_MTK_LYNXI=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHYLINK=y +CONFIG_PHY_MTK_TPHY=y +# CONFIG_PHY_MTK_UFS is not set +# CONFIG_PHY_MTK_XSPHY is not set +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MT7629=y +CONFIG_PINCTRL_MTK_MOORE=y +CONFIG_PINCTRL_MTK_V2=y +CONFIG_PM=y +CONFIG_PM_CLK=y +CONFIG_PM_GENERIC_DOMAINS=y +CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_PWM=y +CONFIG_PWM_MEDIATEK=y +# CONFIG_PWM_MTK_DISP is not set +CONFIG_PWM_SYSFS=y +CONFIG_RAS=y +CONFIG_RATIONAL=y +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +# CONFIG_RTL8367S_GSW is not set +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_SCSI=y +CONFIG_SCSI_COMMON=y +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_8250_MT6577=y +CONFIG_SERIAL_8250_NR_UARTS=3 +CONFIG_SERIAL_8250_RUNTIME_UARTS=3 +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SGL_ALLOC=y +CONFIG_SG_POOL=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SPI_MT65XX=y +CONFIG_SPI_MTK_NOR=y +CONFIG_SPI_MTK_SNFI=y +CONFIG_SRCU=y +CONFIG_STACKTRACE=y +# CONFIG_SWAP is not set +CONFIG_SWCONFIG=y +CONFIG_SWPHY=y +CONFIG_SWP_EMULATE=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_UBIFS_FS=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UNWINDER_ARM=y +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_MTK=y +# CONFIG_USB_XHCI_PLATFORM is not set +CONFIG_USE_OF=y +# CONFIG_VFP is not set +CONFIG_WATCHDOG_CORE=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y From 30d38d7541bcf8eba22f257080130387ac0382df Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Tue, 27 Jun 2023 02:25:08 +0200 Subject: [PATCH 31/53] mediatek: adapt kernel configuration for Linux 6.1 Update kernel configuration to build Linux 6.1 for all subtargets. Signed-off-by: Daniel Golle --- target/linux/mediatek/filogic/config-6.1 | 53 ++++++++++++++--- target/linux/mediatek/mt7622/config-6.1 | 74 ++++++++++++++---------- target/linux/mediatek/mt7623/config-6.1 | 55 ++++++++++++++---- target/linux/mediatek/mt7629/config-6.1 | 36 ++++++++++-- 4 files changed, 162 insertions(+), 56 deletions(-) diff --git a/target/linux/mediatek/filogic/config-6.1 b/target/linux/mediatek/filogic/config-6.1 index 4cae8c50ac7..96a75667354 100644 --- a/target/linux/mediatek/filogic/config-6.1 +++ b/target/linux/mediatek/filogic/config-6.1 @@ -1,7 +1,10 @@ CONFIG_64BIT=y # CONFIG_AHCI_MTK is not set CONFIG_AQUANTIA_PHY=y +CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y +CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_FORCE_MAX_ORDER=11 CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_ARCH_MEDIATEK=y CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y @@ -9,14 +12,15 @@ CONFIG_ARCH_MMAP_RND_BITS=18 CONFIG_ARCH_MMAP_RND_BITS_MAX=24 CONFIG_ARCH_MMAP_RND_BITS_MIN=18 CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 +CONFIG_ARCH_NR_GPIO=0 CONFIG_ARCH_PROC_KCORE_TEXT=y CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_ARCH_STACKWALK=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARCH_WANTS_NO_INSTR=y +CONFIG_ARCH_WANTS_THP_SWAP=y CONFIG_ARM64=y CONFIG_ARM64_4K_PAGES=y -CONFIG_ARM64_CRYPTO=y CONFIG_ARM64_ERRATUM_843419=y CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y CONFIG_ARM64_PAGE_SHIFT=12 @@ -46,6 +50,8 @@ CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_CC_HAVE_SHADOW_CALL_STACK=y CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +CONFIG_CC_NO_ARRAY_BOUNDS=y CONFIG_CLKSRC_MMIO=y CONFIG_CLONE_BACKWARDS=y CONFIG_CMDLINE_OVERRIDE=y @@ -53,6 +59,7 @@ CONFIG_COMMON_CLK=y CONFIG_COMMON_CLK_MEDIATEK=y # CONFIG_COMMON_CLK_MT2712 is not set # CONFIG_COMMON_CLK_MT6779 is not set +# CONFIG_COMMON_CLK_MT6795 is not set # CONFIG_COMMON_CLK_MT6797 is not set # CONFIG_COMMON_CLK_MT7622 is not set CONFIG_COMMON_CLK_MT7981=y @@ -62,10 +69,16 @@ CONFIG_COMMON_CLK_MT7986_ETHSYS=y CONFIG_COMMON_CLK_MT7988=y # CONFIG_COMMON_CLK_MT8173 is not set # CONFIG_COMMON_CLK_MT8183 is not set +# CONFIG_COMMON_CLK_MT8186 is not set +# CONFIG_COMMON_CLK_MT8195 is not set +# CONFIG_COMMON_CLK_MT8365 is not set # CONFIG_COMMON_CLK_MT8516 is not set +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 # CONFIG_COMPAT_32BIT_TIME is not set CONFIG_CONFIGFS_FS=y CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y # CONFIG_CPUFREQ_DT is not set CONFIG_CPU_FREQ=y # CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set @@ -103,7 +116,9 @@ CONFIG_CRYPTO_HASH_INFO=y CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_JITTERENTROPY=y CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_SHA1=y CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LIB_UTILS=y CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_RNG2=y @@ -111,10 +126,11 @@ CONFIG_CRYPTO_RNG_DEFAULT=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA256_ARM64=y CONFIG_CRYPTO_SHA2_ARM64_CE=y +CONFIG_CRYPTO_SHA3=y CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_SIMD=y CONFIG_CRYPTO_ZSTD=y CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_INFO=y CONFIG_DEBUG_MISC=y CONFIG_DIMLIB=y CONFIG_DMADEVICES=y @@ -123,21 +139,25 @@ CONFIG_DMA_DIRECT_REMAP=y CONFIG_DMA_ENGINE=y CONFIG_DMA_ENGINE_RAID=y CONFIG_DMA_OF=y -CONFIG_DMA_REMAP=y CONFIG_DMA_VIRTUAL_CHANNELS=y CONFIG_DTC=y CONFIG_EDAC_SUPPORT=y CONFIG_EINT_MTK=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y CONFIG_EXT4_FS=y CONFIG_F2FS_FS=y CONFIG_FIT_PARTITION=y CONFIG_FIXED_PHY=y CONFIG_FIX_EARLYCON_MEM=y CONFIG_FRAME_POINTER=y +CONFIG_FRAME_WARN=2048 CONFIG_FS_IOMAP=y CONFIG_FS_MBCACHE=y CONFIG_FWNODE_MDIO=y CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GCC11_NO_ARRAY_BOUNDS=y +CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_GENERIC_ARCH_TOPOLOGY=y CONFIG_GENERIC_BUG=y @@ -148,9 +168,9 @@ CONFIG_GENERIC_CPU_AUTOPROBE=y CONFIG_GENERIC_CPU_VULNERABILITIES=y CONFIG_GENERIC_CSUM=y CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_FIND_FIRST_BIT=y CONFIG_GENERIC_GETTIMEOFDAY=y CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IOREMAP=y CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_IRQ_SHOW_LEVEL=y @@ -170,7 +190,6 @@ CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GLOB=y CONFIG_GPIO_CDEV=y CONFIG_GRO_CELLS=y -CONFIG_HANDLE_DOMAIN_IRQ=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_HAS_DMA=y CONFIG_HAS_IOMEM=y @@ -241,6 +260,7 @@ CONFIG_MTK_INFRACFG=y CONFIG_MTK_PMIC_WRAP=y CONFIG_MTK_SCPSYS=y CONFIG_MTK_SCPSYS_PM_DOMAINS=y +# CONFIG_MTK_SVS is not set CONFIG_MTK_THERMAL=y CONFIG_MTK_TIMER=y # CONFIG_MTK_UART_APDMA is not set @@ -281,6 +301,8 @@ CONFIG_OF_RESOLVE=y CONFIG_PADATA=y CONFIG_PAGE_POOL=y CONFIG_PAGE_POOL_STATS=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y CONFIG_PARTITION_PERCPU=y CONFIG_PCI=y CONFIG_PCIEAER=y @@ -304,12 +326,15 @@ CONFIG_PGTABLE_LEVELS=3 CONFIG_PHYLIB=y CONFIG_PHYLINK=y CONFIG_PHYS_ADDR_T_64BIT=y +# CONFIG_PHY_MTK_DP is not set +# CONFIG_PHY_MTK_PCIE is not set CONFIG_PHY_MTK_TPHY=y # CONFIG_PHY_MTK_UFS is not set # CONFIG_PHY_MTK_XSPHY is not set CONFIG_PINCTRL=y # CONFIG_PINCTRL_MT2712 is not set # CONFIG_PINCTRL_MT6765 is not set +# CONFIG_PINCTRL_MT6795 is not set # CONFIG_PINCTRL_MT6797 is not set # CONFIG_PINCTRL_MT7622 is not set CONFIG_PINCTRL_MT7981=y @@ -317,18 +342,23 @@ CONFIG_PINCTRL_MT7986=y CONFIG_PINCTRL_MT7988=y # CONFIG_PINCTRL_MT8173 is not set # CONFIG_PINCTRL_MT8183 is not set -CONFIG_PINCTRL_MT8516=y -CONFIG_PINCTRL_MTK=y +# CONFIG_PINCTRL_MT8186 is not set +# CONFIG_PINCTRL_MT8188 is not set +# CONFIG_PINCTRL_MT8516 is not set CONFIG_PINCTRL_MTK_MOORE=y CONFIG_PINCTRL_MTK_V2=y +# CONFIG_PINCTRL_SINGLE is not set CONFIG_PM=y CONFIG_PM_CLK=y CONFIG_PM_GENERIC_DOMAINS=y CONFIG_PM_GENERIC_DOMAINS_OF=y CONFIG_PM_OPP=y +CONFIG_POLYNOMIAL=y +CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_SUPPLY=y +CONFIG_PREEMPT_NONE_BUILD=y CONFIG_PRINTK_TIME=y CONFIG_PSTORE=y CONFIG_PSTORE_COMPRESS=y @@ -345,6 +375,7 @@ CONFIG_PWM_MEDIATEK=y CONFIG_PWM_SYSFS=y CONFIG_QUEUED_RWLOCKS=y CONFIG_QUEUED_SPINLOCKS=y +CONFIG_RANDSTRUCT_NONE=y CONFIG_RAS=y CONFIG_RATIONAL=y # CONFIG_RAVE_SP_CORE is not set @@ -367,7 +398,7 @@ CONFIG_RPS=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_MT7622=y CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTL8367S_GSW=y +# CONFIG_RTL8367S_GSW is not set CONFIG_RWSEM_SPIN_ON_OWNER=y CONFIG_SCHED_MC=y CONFIG_SCSI=y @@ -385,6 +416,7 @@ CONFIG_SGL_ALLOC=y CONFIG_SG_POOL=y CONFIG_SMP=y CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y CONFIG_SPARSEMEM=y CONFIG_SPARSEMEM_EXTREME=y CONFIG_SPARSEMEM_VMEMMAP=y @@ -395,8 +427,10 @@ CONFIG_SPI_DYNAMIC=y CONFIG_SPI_MASTER=y CONFIG_SPI_MEM=y CONFIG_SPI_MT65XX=y -CONFIG_SPI_MTK_NOR=y +# CONFIG_SPI_MTK_NOR is not set CONFIG_SPI_MTK_SNFI=y +# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set +CONFIG_SQUASHFS_DECOMP_SINGLE=y CONFIG_SRCU=y CONFIG_SWIOTLB=y CONFIG_SWPHY=y @@ -435,5 +469,6 @@ CONFIG_XXHASH=y CONFIG_ZLIB_DEFLATE=y CONFIG_ZLIB_INFLATE=y CONFIG_ZONE_DMA32=y +CONFIG_ZSTD_COMMON=y CONFIG_ZSTD_COMPRESS=y CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/mediatek/mt7622/config-6.1 b/target/linux/mediatek/mt7622/config-6.1 index 30a5ff948fa..7055e4d7285 100644 --- a/target/linux/mediatek/mt7622/config-6.1 +++ b/target/linux/mediatek/mt7622/config-6.1 @@ -1,26 +1,27 @@ CONFIG_64BIT=y # CONFIG_AHCI_MTK is not set CONFIG_AQUANTIA_PHY=y +CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y +CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_FORCE_MAX_ORDER=11 CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_ARCH_MEDIATEK=y CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y CONFIG_ARCH_MMAP_RND_BITS=18 CONFIG_ARCH_MMAP_RND_BITS_MAX=24 CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 +CONFIG_ARCH_NR_GPIO=0 CONFIG_ARCH_PROC_KCORE_TEXT=y CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_ARCH_STACKWALK=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARCH_WANTS_NO_INSTR=y +CONFIG_ARCH_WANTS_THP_SWAP=y CONFIG_ARM64=y CONFIG_ARM64_4K_PAGES=y -# CONFIG_ARM64_CNP is not set -CONFIG_ARM64_CRYPTO=y CONFIG_ARM64_ERRATUM_843419=y -CONFIG_ARM64_ERRATUM_845719=y CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y CONFIG_ARM64_PAGE_SHIFT=12 CONFIG_ARM64_PA_BITS=48 @@ -28,7 +29,6 @@ CONFIG_ARM64_PA_BITS_48=y CONFIG_ARM64_TAGGED_ADDR_ABI=y CONFIG_ARM64_VA_BITS=39 CONFIG_ARM64_VA_BITS_39=y -# CONFIG_ARMV8_DEPRECATED is not set CONFIG_ARM_AMBA=y CONFIG_ARM_ARCH_TIMER=y CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y @@ -46,10 +46,12 @@ CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_SD=y CONFIG_BLK_MQ_PCI=y CONFIG_BLK_PM=y -CONFIG_BLOCK_COMPAT=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_CC_HAVE_SHADOW_CALL_STACK=y CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +CONFIG_CC_NO_ARRAY_BOUNDS=y CONFIG_CLKSRC_MMIO=y CONFIG_CLONE_BACKWARDS=y # CONFIG_CMDLINE_OVERRIDE is not set @@ -64,6 +66,7 @@ CONFIG_COMMON_CLK_MT2712=y # CONFIG_COMMON_CLK_MT2712_VDECSYS is not set # CONFIG_COMMON_CLK_MT2712_VENCSYS is not set # CONFIG_COMMON_CLK_MT6779 is not set +# CONFIG_COMMON_CLK_MT6795 is not set # CONFIG_COMMON_CLK_MT6797 is not set CONFIG_COMMON_CLK_MT7622=y CONFIG_COMMON_CLK_MT7622_AUDSYS=y @@ -74,22 +77,16 @@ CONFIG_COMMON_CLK_MT7622_HIFSYS=y # CONFIG_COMMON_CLK_MT7988 is not set # CONFIG_COMMON_CLK_MT8173 is not set # CONFIG_COMMON_CLK_MT8183 is not set -# CONFIG_COMMON_CLK_MT8183_AUDIOSYS is not set -# CONFIG_COMMON_CLK_MT8183_CAMSYS is not set -# CONFIG_COMMON_CLK_MT8183_IMGSYS is not set -# CONFIG_COMMON_CLK_MT8183_IPU_ADL is not set -# CONFIG_COMMON_CLK_MT8183_IPU_CONN is not set -# CONFIG_COMMON_CLK_MT8183_IPU_CORE0 is not set -# CONFIG_COMMON_CLK_MT8183_IPU_CORE1 is not set -# CONFIG_COMMON_CLK_MT8183_MFGCFG is not set -# CONFIG_COMMON_CLK_MT8183_MMSYS is not set -# CONFIG_COMMON_CLK_MT8183_VDECSYS is not set -# CONFIG_COMMON_CLK_MT8183_VENCSYS is not set +# CONFIG_COMMON_CLK_MT8186 is not set +# CONFIG_COMMON_CLK_MT8195 is not set +# CONFIG_COMMON_CLK_MT8365 is not set # CONFIG_COMMON_CLK_MT8516 is not set -# CONFIG_COMMON_CLK_MT8516_AUDSYS is not set +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 CONFIG_COMPAT_32BIT_TIME=y CONFIG_CONFIGFS_FS=y CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y # CONFIG_CPUFREQ_DT is not set CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y @@ -111,7 +108,6 @@ CONFIG_CRYPTO_AES_ARM64=y CONFIG_CRYPTO_AES_ARM64_CE=y CONFIG_CRYPTO_AES_ARM64_CE_BLK=y CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_BLAKE2S=y CONFIG_CRYPTO_CMAC=y CONFIG_CRYPTO_CRC32=y CONFIG_CRYPTO_CRC32C=y @@ -128,7 +124,9 @@ CONFIG_CRYPTO_HASH_INFO=y CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_JITTERENTROPY=y CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_SHA1=y CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LIB_UTILS=y CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_RNG2=y @@ -137,31 +135,34 @@ CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA256_ARM64=y CONFIG_CRYPTO_SHA2_ARM64_CE=y CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_SIMD=y CONFIG_CRYPTO_ZSTD=y CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_INFO=y CONFIG_DEBUG_MISC=y CONFIG_DIMLIB=y CONFIG_DMADEVICES=y CONFIG_DMA_DIRECT_REMAP=y CONFIG_DMA_ENGINE=y -CONFIG_DMA_ENGINE_RAID=y CONFIG_DMA_OF=y -CONFIG_DMA_REMAP=y CONFIG_DMA_VIRTUAL_CHANNELS=y CONFIG_DTC=y CONFIG_EDAC_SUPPORT=y CONFIG_EINT_MTK=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y CONFIG_EXT4_FS=y CONFIG_F2FS_FS=y CONFIG_FIT_PARTITION=y CONFIG_FIXED_PHY=y CONFIG_FIX_EARLYCON_MEM=y CONFIG_FRAME_POINTER=y +CONFIG_FRAME_WARN=2048 CONFIG_FS_IOMAP=y CONFIG_FS_MBCACHE=y CONFIG_FWNODE_MDIO=y CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GCC11_NO_ARRAY_BOUNDS=y +CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_GENERIC_ARCH_TOPOLOGY=y CONFIG_GENERIC_BUG=y @@ -172,9 +173,9 @@ CONFIG_GENERIC_CPU_AUTOPROBE=y CONFIG_GENERIC_CPU_VULNERABILITIES=y CONFIG_GENERIC_CSUM=y CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_FIND_FIRST_BIT=y CONFIG_GENERIC_GETTIMEOFDAY=y CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IOREMAP=y CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_IRQ_SHOW_LEVEL=y @@ -194,7 +195,6 @@ CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GLOB=y CONFIG_GPIO_CDEV=y CONFIG_GRO_CELLS=y -CONFIG_HANDLE_DOMAIN_IRQ=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_HAS_DMA=y CONFIG_HAS_IOMEM=y @@ -222,6 +222,7 @@ CONFIG_LOCK_SPIN_ON_OWNER=y CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y CONFIG_MAGIC_SYSRQ=y +CONFIG_MAXLINEAR_GPHY=y CONFIG_MDIO_BUS=y CONFIG_MDIO_DEVICE=y CONFIG_MDIO_DEVRES=y @@ -254,8 +255,8 @@ CONFIG_MTD_SPLIT_FIRMWARE=y CONFIG_MTD_SPLIT_FIT_FW=y CONFIG_MTD_UBI=y CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_WL_THRESHOLD=4096 # CONFIG_MTK_CMDQ is not set # CONFIG_MTK_CQDMA is not set @@ -264,6 +265,7 @@ CONFIG_MTK_INFRACFG=y CONFIG_MTK_PMIC_WRAP=y CONFIG_MTK_SCPSYS=y CONFIG_MTK_SCPSYS_PM_DOMAINS=y +# CONFIG_MTK_SVS is not set CONFIG_MTK_THERMAL=y CONFIG_MTK_TIMER=y # CONFIG_MTK_UART_APDMA is not set @@ -301,8 +303,11 @@ CONFIG_OF_KOBJ=y CONFIG_OF_MDIO=y CONFIG_OF_OVERLAY=y CONFIG_OF_RESOLVE=y -CONFIG_OLD_SIGSUSPEND3=y CONFIG_PADATA=y +CONFIG_PAGE_POOL=y +CONFIG_PAGE_POOL_STATS=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y CONFIG_PARTITION_PERCPU=y CONFIG_PCI=y CONFIG_PCIEAER=y @@ -319,17 +324,21 @@ CONFIG_PCI_DOMAINS=y CONFIG_PCI_DOMAINS_GENERIC=y CONFIG_PCI_MSI=y CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PCS_MTK_LYNXI=y CONFIG_PERF_EVENTS=y CONFIG_PGTABLE_LEVELS=3 CONFIG_PHYLIB=y CONFIG_PHYLINK=y CONFIG_PHYS_ADDR_T_64BIT=y +# CONFIG_PHY_MTK_DP is not set +# CONFIG_PHY_MTK_PCIE is not set CONFIG_PHY_MTK_TPHY=y # CONFIG_PHY_MTK_UFS is not set # CONFIG_PHY_MTK_XSPHY is not set CONFIG_PINCTRL=y # CONFIG_PINCTRL_MT2712 is not set # CONFIG_PINCTRL_MT6765 is not set +# CONFIG_PINCTRL_MT6795 is not set # CONFIG_PINCTRL_MT6797 is not set CONFIG_PINCTRL_MT7622=y # CONFIG_PINCTRL_MT7981 is not set @@ -337,8 +346,9 @@ CONFIG_PINCTRL_MT7622=y # CONFIG_PINCTRL_MT7988 is not set # CONFIG_PINCTRL_MT8173 is not set # CONFIG_PINCTRL_MT8183 is not set -CONFIG_PINCTRL_MT8516=y -CONFIG_PINCTRL_MTK=y +# CONFIG_PINCTRL_MT8186 is not set +# CONFIG_PINCTRL_MT8188 is not set +# CONFIG_PINCTRL_MT8516 is not set CONFIG_PINCTRL_MTK_MOORE=y CONFIG_PINCTRL_MTK_V2=y CONFIG_PM=y @@ -346,9 +356,11 @@ CONFIG_PM_CLK=y CONFIG_PM_GENERIC_DOMAINS=y CONFIG_PM_GENERIC_DOMAINS_OF=y CONFIG_PM_OPP=y +CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_SUPPLY=y +CONFIG_PREEMPT_NONE_BUILD=y CONFIG_PRINTK_TIME=y CONFIG_PSTORE=y CONFIG_PSTORE_COMPRESS=y @@ -365,6 +377,7 @@ CONFIG_PWM_MEDIATEK=y CONFIG_PWM_SYSFS=y CONFIG_QUEUED_RWLOCKS=y CONFIG_QUEUED_SPINLOCKS=y +CONFIG_RANDSTRUCT_NONE=y CONFIG_RAS=y CONFIG_RATIONAL=y # CONFIG_RAVE_SP_CORE is not set @@ -377,7 +390,6 @@ CONFIG_REGMAP_MMIO=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_MT6380=y -# CONFIG_REGULATOR_RT5190A is not set CONFIG_RESET_CONTROLLER=y CONFIG_RFS_ACCEL=y CONFIG_RODATA_FULL_DEFAULT_ENABLED=y @@ -403,6 +415,7 @@ CONFIG_SGL_ALLOC=y CONFIG_SG_POOL=y CONFIG_SMP=y CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y CONFIG_SPARSEMEM=y CONFIG_SPARSEMEM_EXTREME=y CONFIG_SPARSEMEM_VMEMMAP=y @@ -420,7 +433,6 @@ CONFIG_SWCONFIG=y CONFIG_SWIOTLB=y CONFIG_SWPHY=y CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYSVIPC_COMPAT=y CONFIG_THERMAL=y CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 @@ -435,6 +447,7 @@ CONFIG_THREAD_INFO_IN_TASK=y CONFIG_TICK_CPU_ACCOUNTING=y CONFIG_TIMER_OF=y CONFIG_TIMER_PROBE=y +CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y CONFIG_TREE_RCU=y CONFIG_TREE_SRCU=y CONFIG_UBIFS_FS=y @@ -454,5 +467,6 @@ CONFIG_XXHASH=y CONFIG_ZLIB_DEFLATE=y CONFIG_ZLIB_INFLATE=y CONFIG_ZONE_DMA32=y +CONFIG_ZSTD_COMMON=y CONFIG_ZSTD_COMPRESS=y CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/mediatek/mt7623/config-6.1 b/target/linux/mediatek/mt7623/config-6.1 index 039a904f197..b6a75ab80a6 100644 --- a/target/linux/mediatek/mt7623/config-6.1 +++ b/target/linux/mediatek/mt7623/config-6.1 @@ -1,6 +1,7 @@ # CONFIG_AIO is not set CONFIG_ALIGNMENT_TRAP=y CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_FORCE_MAX_ORDER=11 CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_ARCH_MEDIATEK=y @@ -21,13 +22,13 @@ CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y # CONFIG_ARM_ATAG_DTB_COMPAT is not set CONFIG_ARM_CPU_SUSPEND=y # CONFIG_ARM_CPU_TOPOLOGY is not set -CONFIG_ARM_CRYPTO=y CONFIG_ARM_DMA_IOMMU_ALIGNMENT=8 CONFIG_ARM_DMA_USE_IOMMU=y CONFIG_ARM_GIC=y -CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_HAS_GROUP_RELOCS=y CONFIG_ARM_L1_CACHE_SHIFT=6 CONFIG_ARM_L1_CACHE_SHIFT_6=y +# CONFIG_ARM_MEDIATEK_CCI_DEVFREQ is not set CONFIG_ARM_MEDIATEK_CPUFREQ=y CONFIG_ARM_PATCH_IDIV=y CONFIG_ARM_PATCH_PHYS_VIRT=y @@ -49,7 +50,9 @@ CONFIG_BLK_MQ_PCI=y CONFIG_BLK_PM=y CONFIG_BOUNCE=y # CONFIG_CACHE_L2X0 is not set -CONFIG_CLEANCACHE=y +CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y +CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +CONFIG_CC_NO_ARRAY_BOUNDS=y CONFIG_CLKSRC_MMIO=y CONFIG_CLONE_BACKWARDS=y CONFIG_CMDLINE="earlyprintk console=ttyS0,115200 rootfstype=squashfs,jffs2" @@ -67,6 +70,7 @@ CONFIG_COMMON_CLK_MT2701_HIFSYS=y CONFIG_COMMON_CLK_MT2701_IMGSYS=y CONFIG_COMMON_CLK_MT2701_MMSYS=y CONFIG_COMMON_CLK_MT2701_VDECSYS=y +# CONFIG_COMMON_CLK_MT6795 is not set # CONFIG_COMMON_CLK_MT7622 is not set # CONFIG_COMMON_CLK_MT7629 is not set # CONFIG_COMMON_CLK_MT7981 is not set @@ -74,11 +78,14 @@ CONFIG_COMMON_CLK_MT2701_VDECSYS=y # CONFIG_COMMON_CLK_MT7988 is not set # CONFIG_COMMON_CLK_MT8135 is not set # CONFIG_COMMON_CLK_MT8173 is not set -CONFIG_COMMON_CLK_MT8516=y -# CONFIG_COMMON_CLK_MT8516_AUDSYS is not set +# CONFIG_COMMON_CLK_MT8365 is not set +# CONFIG_COMMON_CLK_MT8516 is not set +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 CONFIG_COMPAT_32BIT_TIME=y CONFIG_CONFIGFS_FS=y CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y CONFIG_COREDUMP=y # CONFIG_CPUFREQ_DT is not set CONFIG_CPU_32v6K=y @@ -100,6 +107,7 @@ CONFIG_CPU_FREQ_GOV_POWERSAVE=y # CONFIG_CPU_FREQ_GOV_USERSPACE is not set CONFIG_CPU_FREQ_STAT=y CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_PABRT_V7=y CONFIG_CPU_PM=y CONFIG_CPU_RMAP=y @@ -122,7 +130,9 @@ CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_HW=y CONFIG_CRYPTO_JITTERENTROPY=y CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_SHA1=y CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LIB_UTILS=y CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_RNG2=y @@ -132,10 +142,12 @@ CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_ZSTD=y +CONFIG_CURRENT_POINTER_IN_TPIDRURO=y CONFIG_DCACHE_WORD_ACCESS=y CONFIG_DEBUG_ALIGN_RODATA=y CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_GPIO=y +CONFIG_DEBUG_INFO=y CONFIG_DEBUG_LL=y CONFIG_DEBUG_LL_INCLUDE="debug/8250.S" CONFIG_DEBUG_MISC=y @@ -147,7 +159,6 @@ CONFIG_DEBUG_UART_8250=y CONFIG_DEBUG_UART_8250_SHIFT=2 CONFIG_DEBUG_UART_PHYS=0x11004000 CONFIG_DEBUG_UART_VIRT=0xf1004000 -CONFIG_DEBUG_UNCOMPRESS=y # CONFIG_DEVFREQ_GOV_PASSIVE is not set # CONFIG_DEVFREQ_GOV_PERFORMANCE is not set # CONFIG_DEVFREQ_GOV_POWERSAVE is not set @@ -159,7 +170,6 @@ CONFIG_DMADEVICES=y CONFIG_DMA_ENGINE=y CONFIG_DMA_OF=y CONFIG_DMA_OPS=y -CONFIG_DMA_REMAP=y CONFIG_DMA_SHARED_BUFFER=y CONFIG_DMA_VIRTUAL_CHANNELS=y CONFIG_DRM=y @@ -167,14 +177,16 @@ CONFIG_DRM_BRIDGE=y CONFIG_DRM_DISPLAY_CONNECTOR=y CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 -CONFIG_DRM_GEM_CMA_HELPER=y +CONFIG_DRM_GEM_DMA_HELPER=y CONFIG_DRM_GEM_SHMEM_HELPER=y CONFIG_DRM_KMS_HELPER=y CONFIG_DRM_LIMA=y CONFIG_DRM_LVDS_CODEC=y CONFIG_DRM_MEDIATEK=y +# CONFIG_DRM_MEDIATEK_DP is not set CONFIG_DRM_MEDIATEK_HDMI=y CONFIG_DRM_MIPI_DSI=y +CONFIG_DRM_NOMODESET=y CONFIG_DRM_PANEL=y CONFIG_DRM_PANEL_BRIDGE=y CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y @@ -188,6 +200,7 @@ CONFIG_EDAC_ATOMIC_SCRUB=y CONFIG_EDAC_SUPPORT=y CONFIG_EINT_MTK=y CONFIG_ELF_CORE=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y CONFIG_EXT4_FS=y CONFIG_EXTCON=y CONFIG_F2FS_FS=y @@ -210,12 +223,15 @@ CONFIG_FONT_SUPPORT=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_FRAME_WARN=1024 CONFIG_FREEZER=y CONFIG_FS_IOMAP=y CONFIG_FS_MBCACHE=y CONFIG_FWNODE_MDIO=y CONFIG_FW_CACHE=y CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GCC11_NO_ARRAY_BOUNDS=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_GENERIC_BUG=y CONFIG_GENERIC_CLOCKEVENTS=y @@ -246,7 +262,6 @@ CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_VDSO_32=y CONFIG_GPIO_CDEV=y CONFIG_GRO_CELLS=y -CONFIG_HANDLE_DOMAIN_IRQ=y CONFIG_HARDEN_BRANCH_PREDICTOR=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_HAS_DMA=y @@ -277,13 +292,16 @@ CONFIG_INPUT_KEYBOARD=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_IOMMU_API=y # CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set CONFIG_IOMMU_DEFAULT_DMA_STRICT=y +# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set CONFIG_IOMMU_IO_PGTABLE=y CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y # CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set # CONFIG_IOMMU_IO_PGTABLE_LPAE is not set CONFIG_IOMMU_SUPPORT=y CONFIG_IRQCHIP=y +CONFIG_IRQSTACKS=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_IRQ_FORCED_THREADING=y @@ -291,12 +309,14 @@ CONFIG_IRQ_WORK=y CONFIG_JBD2=y CONFIG_KALLSYMS=y CONFIG_KCMP=y +# CONFIG_KEYBOARD_MT6779 is not set CONFIG_KEYBOARD_MTK_PMIC=y CONFIG_KMAP_LOCAL=y CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_PLATFORM=y CONFIG_LEDS_MT6323=y +# CONFIG_LEDS_QCOM_LPG is not set CONFIG_LIBFDT=y CONFIG_LOCK_DEBUGGING_SUPPORT=y CONFIG_LOCK_SPIN_ON_OWNER=y @@ -349,6 +369,7 @@ CONFIG_MTD_UBI=y CONFIG_MTD_UBI_BEB_LIMIT=20 CONFIG_MTD_UBI_BLOCK=y CONFIG_MTD_UBI_WL_THRESHOLD=4096 +# CONFIG_MTK_ADSP_MBOX is not set CONFIG_MTK_CMDQ=y CONFIG_MTK_CMDQ_MBOX=y CONFIG_MTK_CQDMA=y @@ -361,6 +382,7 @@ CONFIG_MTK_PMIC_WRAP=y CONFIG_MTK_SCPSYS=y CONFIG_MTK_SCPSYS_PM_DOMAINS=y CONFIG_MTK_SMI=y +# CONFIG_MTK_SVS is not set CONFIG_MTK_THERMAL=y CONFIG_MTK_TIMER=y # CONFIG_MTK_UART_APDMA is not set @@ -410,6 +432,8 @@ CONFIG_PADATA=y CONFIG_PAGE_OFFSET=0xC0000000 CONFIG_PAGE_POOL=y CONFIG_PAGE_POOL_STATS=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y CONFIG_PCI=y CONFIG_PCIEAER=y CONFIG_PCIEPORTBUS=y @@ -424,14 +448,16 @@ CONFIG_PERF_USE_VMALLOC=y CONFIG_PGTABLE_LEVELS=2 CONFIG_PHYLIB=y CONFIG_PHYLINK=y +# CONFIG_PHY_MTK_DP is not set CONFIG_PHY_MTK_HDMI=y CONFIG_PHY_MTK_MIPI_DSI=y +# CONFIG_PHY_MTK_PCIE is not set CONFIG_PHY_MTK_TPHY=y # CONFIG_PHY_MTK_UFS is not set # CONFIG_PHY_MTK_XSPHY is not set CONFIG_PINCTRL=y CONFIG_PINCTRL_MT2701=y -CONFIG_PINCTRL_MT6397=y +# CONFIG_PINCTRL_MT6397 is not set CONFIG_PINCTRL_MT7623=y CONFIG_PINCTRL_MTK=y CONFIG_PINCTRL_MTK_MOORE=y @@ -452,6 +478,7 @@ CONFIG_POWER_SUPPLY=y CONFIG_POWER_SUPPLY_HWMON=y CONFIG_PREEMPT=y CONFIG_PREEMPTION=y +CONFIG_PREEMPT_BUILD=y CONFIG_PREEMPT_COUNT=y # CONFIG_PREEMPT_NONE is not set CONFIG_PREEMPT_RCU=y @@ -461,6 +488,7 @@ CONFIG_PWM=y CONFIG_PWM_MEDIATEK=y # CONFIG_PWM_MTK_DISP is not set CONFIG_PWM_SYSFS=y +CONFIG_RANDSTRUCT_NONE=y CONFIG_RAS=y CONFIG_RATIONAL=y CONFIG_REGMAP=y @@ -469,10 +497,11 @@ CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_MT6323=y +# CONFIG_REGULATOR_MT6331 is not set +# CONFIG_REGULATOR_MT6332 is not set # CONFIG_REGULATOR_MT6358 is not set # CONFIG_REGULATOR_MT6380 is not set # CONFIG_REGULATOR_MT6397 is not set -# CONFIG_REGULATOR_RT5190A is not set # CONFIG_REGULATOR_QCOM_LABIBB is not set # CONFIG_REGULATOR_QCOM_SPMI is not set # CONFIG_REGULATOR_QCOM_USB_VBUS is not set @@ -496,6 +525,7 @@ CONFIG_SGL_ALLOC=y CONFIG_SMP=y # CONFIG_SMP_ON_UP is not set CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y CONFIG_SPARSE_IRQ=y CONFIG_SPI=y CONFIG_SPI_BITBANG=y @@ -506,6 +536,7 @@ CONFIG_SPI_MT65XX=y # CONFIG_SPI_MTK_NOR is not set CONFIG_SPMI=y # CONFIG_SPMI_HISI3670 is not set +# CONFIG_SPMI_MTK_PMIF is not set CONFIG_SRCU=y # CONFIG_STRIP_ASM_SYMS is not set CONFIG_SUSPEND=y @@ -519,6 +550,7 @@ CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 CONFIG_THERMAL_GOV_STEP_WISE=y CONFIG_THERMAL_OF=y +CONFIG_THREAD_INFO_IN_TASK=y CONFIG_TICK_CPU_ACCOUNTING=y CONFIG_TIMER_OF=y CONFIG_TIMER_PROBE=y @@ -572,5 +604,6 @@ CONFIG_ZBOOT_ROM_BSS=0 CONFIG_ZBOOT_ROM_TEXT=0 CONFIG_ZLIB_DEFLATE=y CONFIG_ZLIB_INFLATE=y +CONFIG_ZSTD_COMMON=y CONFIG_ZSTD_COMPRESS=y CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/mediatek/mt7629/config-6.1 b/target/linux/mediatek/mt7629/config-6.1 index 08089dde2a3..c0c501e59e1 100644 --- a/target/linux/mediatek/mt7629/config-6.1 +++ b/target/linux/mediatek/mt7629/config-6.1 @@ -1,5 +1,6 @@ CONFIG_ALIGNMENT_TRAP=y CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_FORCE_MAX_ORDER=11 CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_ARCH_MEDIATEK=y @@ -16,9 +17,8 @@ CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARM=y CONFIG_ARM_ARCH_TIMER=y CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_CRYPTO=y CONFIG_ARM_GIC=y -CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_HAS_GROUP_RELOCS=y CONFIG_ARM_HEAVY_MB=y CONFIG_ARM_L1_CACHE_SHIFT=6 CONFIG_ARM_L1_CACHE_SHIFT_6=y @@ -36,6 +36,9 @@ CONFIG_BLK_PM=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_CACHE_L2X0=y +CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y +CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +CONFIG_CC_NO_ARRAY_BOUNDS=y # CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_CHR_DEV_SCH=y @@ -47,6 +50,7 @@ CONFIG_CMDLINE_OVERRIDE=y CONFIG_COMMON_CLK=y CONFIG_COMMON_CLK_MEDIATEK=y # CONFIG_COMMON_CLK_MT2701 is not set +# CONFIG_COMMON_CLK_MT6795 is not set # CONFIG_COMMON_CLK_MT7622 is not set CONFIG_COMMON_CLK_MT7629=y CONFIG_COMMON_CLK_MT7629_ETHSYS=y @@ -56,9 +60,12 @@ CONFIG_COMMON_CLK_MT7629_HIFSYS=y # CONFIG_COMMON_CLK_MT7988 is not set # CONFIG_COMMON_CLK_MT8135 is not set # CONFIG_COMMON_CLK_MT8173 is not set -CONFIG_COMMON_CLK_MT8516=y -# CONFIG_COMMON_CLK_MT8516_AUDSYS is not set +# CONFIG_COMMON_CLK_MT8365 is not set +# CONFIG_COMMON_CLK_MT8516 is not set +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y CONFIG_CPU_32v6K=y CONFIG_CPU_32v7=y CONFIG_CPU_ABRT_EV7=y @@ -70,6 +77,7 @@ CONFIG_CPU_CP15_MMU=y CONFIG_CPU_HAS_ASID=y CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_PABRT_V7=y CONFIG_CPU_PM=y CONFIG_CPU_RMAP=y @@ -81,24 +89,31 @@ CONFIG_CRC16=y CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_HASH_INFO=y CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_UTILS=y CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_RNG2=y CONFIG_CRYPTO_ZSTD=y +CONFIG_CURRENT_POINTER_IN_TPIDRURO=y CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_INFO=y CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" CONFIG_DEBUG_MISC=y CONFIG_DEFAULT_HOSTNAME="(mt7629)" CONFIG_DIMLIB=y CONFIG_DMA_OPS=y -CONFIG_DMA_REMAP=y CONFIG_DTC=y CONFIG_EDAC_ATOMIC_SCRUB=y CONFIG_EDAC_SUPPORT=y CONFIG_EINT_MTK=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y CONFIG_FIXED_PHY=y CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FRAME_WARN=1024 CONFIG_FWNODE_MDIO=y CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GCC11_NO_ARRAY_BOUNDS=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_GENERIC_ARCH_TOPOLOGY=y CONFIG_GENERIC_BUG=y @@ -130,7 +145,6 @@ CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_VDSO_32=y CONFIG_GPIO_CDEV=y CONFIG_GRO_CELLS=y -CONFIG_HANDLE_DOMAIN_IRQ=y CONFIG_HARDEN_BRANCH_PREDICTOR=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_HAS_DMA=y @@ -143,6 +157,7 @@ CONFIG_HW_RANDOM_MTK=y CONFIG_HZ_FIXED=0 CONFIG_INITRAMFS_SOURCE="" CONFIG_IRQCHIP=y +CONFIG_IRQSTACKS=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_IRQ_FORCED_THREADING=y @@ -229,6 +244,8 @@ CONFIG_PADATA=y CONFIG_PAGE_OFFSET=0xC0000000 CONFIG_PAGE_POOL=y CONFIG_PAGE_POOL_STATS=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y CONFIG_PCI=y CONFIG_PCIEAER=y CONFIG_PCIEPORTBUS=y @@ -243,6 +260,8 @@ CONFIG_PERF_USE_VMALLOC=y CONFIG_PGTABLE_LEVELS=2 CONFIG_PHYLIB=y CONFIG_PHYLINK=y +# CONFIG_PHY_MTK_DP is not set +# CONFIG_PHY_MTK_PCIE is not set CONFIG_PHY_MTK_TPHY=y # CONFIG_PHY_MTK_UFS is not set # CONFIG_PHY_MTK_XSPHY is not set @@ -254,11 +273,13 @@ CONFIG_PM=y CONFIG_PM_CLK=y CONFIG_PM_GENERIC_DOMAINS=y CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_PREEMPT_NONE_BUILD=y CONFIG_PTP_1588_CLOCK_OPTIONAL=y CONFIG_PWM=y CONFIG_PWM_MEDIATEK=y # CONFIG_PWM_MTK_DISP is not set CONFIG_PWM_SYSFS=y +CONFIG_RANDSTRUCT_NONE=y CONFIG_RAS=y CONFIG_RATIONAL=y CONFIG_REGMAP=y @@ -281,6 +302,7 @@ CONFIG_SG_POOL=y CONFIG_SMP=y CONFIG_SMP_ON_UP=y CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y CONFIG_SPARSE_IRQ=y CONFIG_SPI=y CONFIG_SPI_MASTER=y @@ -295,6 +317,7 @@ CONFIG_SWCONFIG=y CONFIG_SWPHY=y CONFIG_SWP_EMULATE=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_THREAD_INFO_IN_TASK=y CONFIG_TICK_CPU_ACCOUNTING=y CONFIG_TIMER_OF=y CONFIG_TIMER_PROBE=y @@ -321,5 +344,6 @@ CONFIG_ZBOOT_ROM_BSS=0 CONFIG_ZBOOT_ROM_TEXT=0 CONFIG_ZLIB_DEFLATE=y CONFIG_ZLIB_INFLATE=y +CONFIG_ZSTD_COMMON=y CONFIG_ZSTD_COMPRESS=y CONFIG_ZSTD_DECOMPRESS=y From 1321007e1f68c07280b3ca5ba11941cbad7a5312 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sat, 17 Jun 2023 22:10:26 +0200 Subject: [PATCH 32/53] mediatek: expose testing Linux 6.1 testing kernel Set KERNEL_TESTING_PATCHVER:=6.1 to allow building all subtargets with Linux 6.1. Signed-off-by: Daniel Golle --- target/linux/mediatek/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/mediatek/Makefile b/target/linux/mediatek/Makefile index 73da79eaa08..f73f2daef61 100644 --- a/target/linux/mediatek/Makefile +++ b/target/linux/mediatek/Makefile @@ -9,6 +9,7 @@ SUBTARGETS:=mt7622 mt7623 mt7629 filogic FEATURES:=dt-overlay emmc fpu gpio nand pci pcie rootfs-part separate_ramdisk squashfs usb KERNEL_PATCHVER:=5.15 +KERNEL_TESTING_PATCHVER:=6.1 include $(INCLUDE_DIR)/target.mk DEFAULT_PACKAGES += \ From cd804c1ebb34c9740f8ad9fe393a81f3efb7b009 Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Thu, 6 Jul 2023 08:16:50 +0200 Subject: [PATCH 33/53] hostapd: update to 2023-06-22 Removed, merged upstream: - 170-wpa_supplicant-fix-compiling-without-IEEE8021X_EAPOL.patch Manually refreshed: - 040-mesh-allow-processing-authentication-frames-in-block.patch - 600-ubus_support.patch - 761-shared_das_port.patch Fixes: #12661 Fixes: 304423a4 ("hostapd: update to 2023-03-29") Signed-off-by: Andre Heider --- package/network/services/hostapd/Makefile | 6 +- ...hannels-to-be-selected-if-dfs-is-ena.patch | 22 +++--- ...erministic-channel-on-channel-switch.patch | 2 +- ...ix-sta-add-after-previous-connection.patch | 4 +- ...use-of-uninitialized-stack-variables.patch | 2 +- ...ewrite-neigh-code-to-not-depend-on-l.patch | 14 ++-- ...ssing-authentication-frames-in-block.patch | 4 +- ...ix-compiling-without-IEEE8021X_EAPOL.patch | 41 ---------- .../hostapd/patches/200-multicall.patch | 22 +++--- .../services/hostapd/patches/300-noscan.patch | 2 +- .../hostapd/patches/301-mesh-noscan.patch | 8 +- .../patches/310-rescan_immediately.patch | 2 +- .../patches/330-nl80211_fix_set_freq.patch | 2 +- .../patches/340-reload_freq_change.patch | 8 +- .../patches/350-nl80211_del_beacon_bss.patch | 6 +- .../patches/360-ctrl_iface_reload.patch | 4 +- .../hostapd/patches/370-ap_sta_support.patch | 26 +++---- .../patches/380-disable_ctrl_iface_mib.patch | 12 +-- .../patches/420-indicate-features.patch | 4 +- .../hostapd/patches/450-scan_wait.patch | 10 +-- ...dd-new-config-params-to-be-used-with.patch | 6 +- .../patches/463-add-mcast_rate-to-11s.patch | 6 +- .../patches/464-fix-mesh-obss-check.patch | 2 +- .../patches/590-rrm-wnm-statistics.patch | 6 +- .../hostapd/patches/600-ubus_support.patch | 77 ++++++++++--------- .../hostapd/patches/700-wifi-reload.patch | 26 +++---- .../patches/720-iface_max_num_sta.patch | 8 +- .../hostapd/patches/730-ft_iface.patch | 2 +- ...750-qos_map_set_without_interworking.patch | 10 +-- .../751-qos_map_ignore_when_unsupported.patch | 2 +- .../hostapd/patches/760-dynamic_own_ip.patch | 2 +- .../hostapd/patches/761-shared_das_port.patch | 16 ++-- 32 files changed, 162 insertions(+), 202 deletions(-) delete mode 100644 package/network/services/hostapd/patches/170-wpa_supplicant-fix-compiling-without-IEEE8021X_EAPOL.patch diff --git a/package/network/services/hostapd/Makefile b/package/network/services/hostapd/Makefile index dc296704898..0fe53dc8d4d 100644 --- a/package/network/services/hostapd/Makefile +++ b/package/network/services/hostapd/Makefile @@ -9,9 +9,9 @@ PKG_RELEASE:=1.2 PKG_SOURCE_URL:=http://w1.fi/hostap.git PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2023-03-29 -PKG_SOURCE_VERSION:=bb945b98fefc64887dffb40773a19d77585cee42 -PKG_MIRROR_HASH:=1da8a39c7c81ce257994874402a86d00080a6145b5eb5c5fc44b2fae1853fe8d +PKG_SOURCE_DATE:=2023-06-22 +PKG_SOURCE_VERSION:=599d00be9de2846c6ea18c1487d8329522ade22b +PKG_MIRROR_HASH:=828810c558ea181e45ed0c8b940f5c41e55775e2979a15aed8cf0ab17dd7723c PKG_MAINTAINER:=Felix Fietkau PKG_LICENSE:=BSD-3-Clause diff --git a/package/network/services/hostapd/patches/010-mesh-Allow-DFS-channels-to-be-selected-if-dfs-is-ena.patch b/package/network/services/hostapd/patches/010-mesh-Allow-DFS-channels-to-be-selected-if-dfs-is-ena.patch index 761fe368cd2..0a51c84d215 100644 --- a/package/network/services/hostapd/patches/010-mesh-Allow-DFS-channels-to-be-selected-if-dfs-is-ena.patch +++ b/package/network/services/hostapd/patches/010-mesh-Allow-DFS-channels-to-be-selected-if-dfs-is-ena.patch @@ -14,7 +14,7 @@ Signed-off-by: Peter Oh --- a/wpa_supplicant/wpa_supplicant.c +++ b/wpa_supplicant/wpa_supplicant.c -@@ -2621,7 +2621,7 @@ static int drv_supports_vht(struct wpa_s +@@ -2638,7 +2638,7 @@ static int drv_supports_vht(struct wpa_s } @@ -23,7 +23,7 @@ Signed-off-by: Peter Oh { int i; -@@ -2630,7 +2630,10 @@ static bool ibss_mesh_is_80mhz_avail(int +@@ -2647,7 +2647,10 @@ static bool ibss_mesh_is_80mhz_avail(int chan = hw_get_channel_chan(mode, i, NULL); if (!chan || @@ -35,7 +35,7 @@ Signed-off-by: Peter Oh return false; } -@@ -2757,7 +2760,7 @@ static void ibss_mesh_select_40mhz(struc +@@ -2774,7 +2777,7 @@ static void ibss_mesh_select_40mhz(struc const struct wpa_ssid *ssid, struct hostapd_hw_modes *mode, struct hostapd_freq_params *freq, @@ -44,7 +44,7 @@ Signed-off-by: Peter Oh int chan_idx; struct hostapd_channel_data *pri_chan = NULL, *sec_chan = NULL; int i, res; -@@ -2781,8 +2784,11 @@ static void ibss_mesh_select_40mhz(struc +@@ -2798,8 +2801,11 @@ static void ibss_mesh_select_40mhz(struc return; /* Check primary channel flags */ @@ -57,7 +57,7 @@ Signed-off-by: Peter Oh #ifdef CONFIG_HT_OVERRIDES if (ssid->disable_ht40) -@@ -2808,8 +2814,11 @@ static void ibss_mesh_select_40mhz(struc +@@ -2825,8 +2831,11 @@ static void ibss_mesh_select_40mhz(struc return; /* Check secondary channel flags */ @@ -70,7 +70,7 @@ Signed-off-by: Peter Oh if (ht40 == -1) { if (!(pri_chan->flag & HOSTAPD_CHAN_HT40MINUS)) -@@ -2863,7 +2872,7 @@ static bool ibss_mesh_select_80_160mhz(s +@@ -2880,7 +2889,7 @@ static bool ibss_mesh_select_80_160mhz(s const struct wpa_ssid *ssid, struct hostapd_hw_modes *mode, struct hostapd_freq_params *freq, @@ -79,7 +79,7 @@ Signed-off-by: Peter Oh static const int bw80[] = { 5180, 5260, 5500, 5580, 5660, 5745, 5825, 5955, 6035, 6115, 6195, 6275, 6355, 6435, -@@ -2908,7 +2917,7 @@ static bool ibss_mesh_select_80_160mhz(s +@@ -2925,7 +2934,7 @@ static bool ibss_mesh_select_80_160mhz(s goto skip_80mhz; /* Use 40 MHz if channel not usable */ @@ -88,7 +88,7 @@ Signed-off-by: Peter Oh goto skip_80mhz; chwidth = CONF_OPER_CHWIDTH_80MHZ; -@@ -2922,7 +2931,7 @@ static bool ibss_mesh_select_80_160mhz(s +@@ -2939,7 +2948,7 @@ static bool ibss_mesh_select_80_160mhz(s if ((mode->he_capab[ieee80211_mode].phy_cap[ HE_PHYCAP_CHANNEL_WIDTH_SET_IDX] & HE_PHYCAP_CHANNEL_WIDTH_SET_160MHZ_IN_5G) && is_6ghz && @@ -97,7 +97,7 @@ Signed-off-by: Peter Oh for (j = 0; j < ARRAY_SIZE(bw160); j++) { if (freq->freq == bw160[j]) { chwidth = CONF_OPER_CHWIDTH_160MHZ; -@@ -2950,10 +2959,12 @@ static bool ibss_mesh_select_80_160mhz(s +@@ -2967,10 +2976,12 @@ static bool ibss_mesh_select_80_160mhz(s if (!chan) continue; @@ -113,7 +113,7 @@ Signed-off-by: Peter Oh /* Found a suitable second segment for 80+80 */ chwidth = CONF_OPER_CHWIDTH_80P80MHZ; -@@ -3008,6 +3019,7 @@ void ibss_mesh_setup_freq(struct wpa_sup +@@ -3025,6 +3036,7 @@ void ibss_mesh_setup_freq(struct wpa_sup int i, obss_scan = 1; u8 channel; bool is_6ghz; @@ -121,7 +121,7 @@ Signed-off-by: Peter Oh freq->freq = ssid->frequency; -@@ -3053,9 +3065,9 @@ void ibss_mesh_setup_freq(struct wpa_sup +@@ -3070,9 +3082,9 @@ void ibss_mesh_setup_freq(struct wpa_sup freq->channel = channel; /* Setup higher BW only for 5 GHz */ if (mode->mode == HOSTAPD_MODE_IEEE80211A) { diff --git a/package/network/services/hostapd/patches/011-mesh-use-deterministic-channel-on-channel-switch.patch b/package/network/services/hostapd/patches/011-mesh-use-deterministic-channel-on-channel-switch.patch index 20a8bee0727..9b11f0e8031 100644 --- a/package/network/services/hostapd/patches/011-mesh-use-deterministic-channel-on-channel-switch.patch +++ b/package/network/services/hostapd/patches/011-mesh-use-deterministic-channel-on-channel-switch.patch @@ -68,7 +68,7 @@ Signed-off-by: Markus Theil if (!chan) { --- a/src/drivers/driver_nl80211.c +++ b/src/drivers/driver_nl80211.c -@@ -10739,6 +10739,10 @@ static int nl80211_switch_channel(void * +@@ -10977,6 +10977,10 @@ static int nl80211_switch_channel(void * if (ret) goto error; diff --git a/package/network/services/hostapd/patches/021-fix-sta-add-after-previous-connection.patch b/package/network/services/hostapd/patches/021-fix-sta-add-after-previous-connection.patch index 827e122baf4..4ee43b5186a 100644 --- a/package/network/services/hostapd/patches/021-fix-sta-add-after-previous-connection.patch +++ b/package/network/services/hostapd/patches/021-fix-sta-add-after-previous-connection.patch @@ -1,6 +1,6 @@ --- a/src/ap/ieee802_11.c +++ b/src/ap/ieee802_11.c -@@ -4168,6 +4168,13 @@ static int add_associated_sta(struct hos +@@ -4601,6 +4601,13 @@ static int add_associated_sta(struct hos * drivers to accept the STA parameter configuration. Since this is * after a new FT-over-DS exchange, a new TK has been derived, so key * reinstallation is not a concern for this case. @@ -14,7 +14,7 @@ */ wpa_printf(MSG_DEBUG, "Add associated STA " MACSTR " (added_unassoc=%d auth_alg=%u ft_over_ds=%u reassoc=%d authorized=%d ft_tk=%d fils_tk=%d)", -@@ -4181,7 +4188,8 @@ static int add_associated_sta(struct hos +@@ -4614,7 +4621,8 @@ static int add_associated_sta(struct hos (!(sta->flags & WLAN_STA_AUTHORIZED) || (reassoc && sta->ft_over_ds && sta->auth_alg == WLAN_AUTH_FT) || (!wpa_auth_sta_ft_tk_already_set(sta->wpa_sm) && diff --git a/package/network/services/hostapd/patches/022-hostapd-fix-use-of-uninitialized-stack-variables.patch b/package/network/services/hostapd/patches/022-hostapd-fix-use-of-uninitialized-stack-variables.patch index f4f56f5107c..8dec325c985 100644 --- a/package/network/services/hostapd/patches/022-hostapd-fix-use-of-uninitialized-stack-variables.patch +++ b/package/network/services/hostapd/patches/022-hostapd-fix-use-of-uninitialized-stack-variables.patch @@ -14,7 +14,7 @@ Signed-off-by: Felix Fietkau --- a/src/ap/hostapd.c +++ b/src/ap/hostapd.c -@@ -3562,7 +3562,7 @@ static int hostapd_change_config_freq(st +@@ -3764,7 +3764,7 @@ static int hostapd_change_config_freq(st struct hostapd_freq_params *old_params) { int channel; diff --git a/package/network/services/hostapd/patches/030-driver_nl80211-rewrite-neigh-code-to-not-depend-on-l.patch b/package/network/services/hostapd/patches/030-driver_nl80211-rewrite-neigh-code-to-not-depend-on-l.patch index c02d4b497e2..19248e80d8c 100644 --- a/package/network/services/hostapd/patches/030-driver_nl80211-rewrite-neigh-code-to-not-depend-on-l.patch +++ b/package/network/services/hostapd/patches/030-driver_nl80211-rewrite-neigh-code-to-not-depend-on-l.patch @@ -20,7 +20,7 @@ Signed-off-by: Felix Fietkau #include #include #include -@@ -5590,26 +5587,29 @@ fail: +@@ -5783,26 +5780,29 @@ fail: static void rtnl_neigh_delete_fdb_entry(struct i802_bss *bss, const u8 *addr) { @@ -64,7 +64,7 @@ Signed-off-by: Felix Fietkau if (err < 0) { wpa_printf(MSG_DEBUG, "nl80211: bridge FDB entry delete for " MACSTR " ifindex=%d failed: %s", MAC2STR(addr), -@@ -5619,9 +5619,8 @@ static void rtnl_neigh_delete_fdb_entry( +@@ -5812,9 +5812,8 @@ static void rtnl_neigh_delete_fdb_entry( MACSTR, MAC2STR(addr)); } @@ -76,7 +76,7 @@ Signed-off-by: Felix Fietkau } -@@ -8275,7 +8274,6 @@ static void *i802_init(struct hostapd_da +@@ -8492,7 +8491,6 @@ static void *i802_init(struct hostapd_da (params->num_bridge == 0 || !params->bridge[0])) add_ifidx(drv, br_ifindex, drv->ifindex); @@ -84,7 +84,7 @@ Signed-off-by: Felix Fietkau if (bss->added_if_into_bridge || bss->already_in_bridge) { int err; -@@ -8292,7 +8290,6 @@ static void *i802_init(struct hostapd_da +@@ -8509,7 +8507,6 @@ static void *i802_init(struct hostapd_da goto failed; } } @@ -92,7 +92,7 @@ Signed-off-by: Felix Fietkau if (drv->capa.flags2 & WPA_DRIVER_FLAGS2_CONTROL_PORT_RX) { wpa_printf(MSG_DEBUG, -@@ -11605,13 +11602,14 @@ static int wpa_driver_br_add_ip_neigh(vo +@@ -11843,13 +11840,14 @@ static int wpa_driver_br_add_ip_neigh(vo const u8 *ipaddr, int prefixlen, const u8 *addr) { @@ -112,7 +112,7 @@ Signed-off-by: Felix Fietkau int res; if (!ipaddr || prefixlen == 0 || !addr) -@@ -11630,85 +11628,66 @@ static int wpa_driver_br_add_ip_neigh(vo +@@ -11868,85 +11866,66 @@ static int wpa_driver_br_add_ip_neigh(vo } if (version == 4) { @@ -220,7 +220,7 @@ Signed-off-by: Felix Fietkau addrsize = 16; } else { return -EINVAL; -@@ -11726,41 +11705,30 @@ static int wpa_driver_br_delete_ip_neigh +@@ -11964,41 +11943,30 @@ static int wpa_driver_br_delete_ip_neigh return -1; } diff --git a/package/network/services/hostapd/patches/040-mesh-allow-processing-authentication-frames-in-block.patch b/package/network/services/hostapd/patches/040-mesh-allow-processing-authentication-frames-in-block.patch index 179d47ecc4e..f98d3806dc1 100644 --- a/package/network/services/hostapd/patches/040-mesh-allow-processing-authentication-frames-in-block.patch +++ b/package/network/services/hostapd/patches/040-mesh-allow-processing-authentication-frames-in-block.patch @@ -16,7 +16,7 @@ Signed-off-by: Felix Fietkau --- a/src/ap/ieee802_11.c +++ b/src/ap/ieee802_11.c -@@ -2948,15 +2948,6 @@ static void handle_auth(struct hostapd_d +@@ -3012,15 +3012,6 @@ static void handle_auth(struct hostapd_d seq_ctrl); return; } @@ -25,7 +25,7 @@ Signed-off-by: Felix Fietkau - sta->plink_state == PLINK_BLOCKED) { - wpa_printf(MSG_DEBUG, "Mesh peer " MACSTR - " is blocked - drop Authentication frame", -- MAC2STR(mgmt->sa)); +- MAC2STR(sa)); - return; - } -#endif /* CONFIG_MESH */ diff --git a/package/network/services/hostapd/patches/170-wpa_supplicant-fix-compiling-without-IEEE8021X_EAPOL.patch b/package/network/services/hostapd/patches/170-wpa_supplicant-fix-compiling-without-IEEE8021X_EAPOL.patch deleted file mode 100644 index 7724f1ae8d6..00000000000 --- a/package/network/services/hostapd/patches/170-wpa_supplicant-fix-compiling-without-IEEE8021X_EAPOL.patch +++ /dev/null @@ -1,41 +0,0 @@ -From c85ce84d942e1eabde33e120b18e5b1f1637b76e Mon Sep 17 00:00:00 2001 -From: Nick Hainke -Date: Tue, 14 Mar 2023 21:40:53 +0100 -Subject: [PATCH] wpa_supplicant: fix compiling without IEEE8021X_EAPOL - -If IEEE8021X_EAPOL is not defined wpa_supplicant will not compile with -following error: - - events.c: In function 'wpa_supplicant_connect': - events.c:1827:14: warning: implicit declaration of function 'eap_is_wps_pbc_enrollee' [-Wimplicit-function-declaration] - 1827 | if ((eap_is_wps_pbc_enrollee(&ssid->eap) && - | ^~~~~~~~~~~~~~~~~~~~~~~ - events.c:1827:43: error: 'struct wpa_ssid' has no member named 'eap' - 1827 | if ((eap_is_wps_pbc_enrollee(&ssid->eap) && - | ^~ - -Adding ifdef statements around the calling function fixes the issue. - -Signed-off-by: Nick Hainke ---- - wpa_supplicant/events.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/wpa_supplicant/events.c -+++ b/wpa_supplicant/events.c -@@ -1824,6 +1824,7 @@ int wpa_supplicant_connect(struct wpa_su - struct wpa_bss *selected, - struct wpa_ssid *ssid) - { -+#ifdef IEEE8021X_EAPOL - if ((eap_is_wps_pbc_enrollee(&ssid->eap) && - wpas_wps_partner_link_overlap_detect(wpa_s)) || - wpas_wps_scan_pbc_overlap(wpa_s, selected, ssid)) { -@@ -1846,6 +1847,7 @@ int wpa_supplicant_connect(struct wpa_su - #endif /* CONFIG_WPS */ - return -1; - } -+#endif /* IEEE8021X_EAPOL */ - - wpa_msg(wpa_s, MSG_DEBUG, - "Considering connect request: reassociate: %d selected: " diff --git a/package/network/services/hostapd/patches/200-multicall.patch b/package/network/services/hostapd/patches/200-multicall.patch index f12aeb0ca9e..f7e797a9c80 100644 --- a/package/network/services/hostapd/patches/200-multicall.patch +++ b/package/network/services/hostapd/patches/200-multicall.patch @@ -156,7 +156,7 @@ wpa_cli.exe: wpa_cli --- a/src/drivers/driver.h +++ b/src/drivers/driver.h -@@ -6544,8 +6544,8 @@ union wpa_event_data { +@@ -6651,8 +6651,8 @@ union wpa_event_data { * Driver wrapper code should call this function whenever an event is received * from the driver. */ @@ -167,7 +167,7 @@ /** * wpa_supplicant_event_global - Report a driver event for wpa_supplicant -@@ -6557,7 +6557,7 @@ void wpa_supplicant_event(void *ctx, enu +@@ -6664,7 +6664,7 @@ void wpa_supplicant_event(void *ctx, enu * Same as wpa_supplicant_event(), but we search for the interface in * wpa_global. */ @@ -178,7 +178,7 @@ /* --- a/src/ap/drv_callbacks.c +++ b/src/ap/drv_callbacks.c -@@ -1887,8 +1887,8 @@ err: +@@ -1994,8 +1994,8 @@ err: #endif /* CONFIG_OWE */ @@ -189,7 +189,7 @@ { struct hostapd_data *hapd = ctx; #ifndef CONFIG_NO_STDOUT_DEBUG -@@ -2161,7 +2161,7 @@ void wpa_supplicant_event(void *ctx, enu +@@ -2271,7 +2271,7 @@ void wpa_supplicant_event(void *ctx, enu } @@ -231,7 +231,7 @@ os_memset(&global, 0, sizeof(global)); --- a/wpa_supplicant/events.c +++ b/wpa_supplicant/events.c -@@ -5237,8 +5237,8 @@ static void wpas_event_unprot_beacon(str +@@ -5345,8 +5345,8 @@ static void wpas_link_reconfig(struct wp } @@ -242,7 +242,7 @@ { struct wpa_supplicant *wpa_s = ctx; int resched; -@@ -6149,7 +6149,7 @@ void wpa_supplicant_event(void *ctx, enu +@@ -6264,7 +6264,7 @@ void wpa_supplicant_event(void *ctx, enu } @@ -253,7 +253,7 @@ struct wpa_supplicant *wpa_s; --- a/wpa_supplicant/wpa_supplicant.c +++ b/wpa_supplicant/wpa_supplicant.c -@@ -7408,7 +7408,6 @@ struct wpa_interface * wpa_supplicant_ma +@@ -7435,7 +7435,6 @@ struct wpa_interface * wpa_supplicant_ma return NULL; } @@ -261,7 +261,7 @@ /** * wpa_supplicant_match_existing - Match existing interfaces * @global: Pointer to global data from wpa_supplicant_init() -@@ -7443,6 +7442,11 @@ static int wpa_supplicant_match_existing +@@ -7470,6 +7469,11 @@ static int wpa_supplicant_match_existing #endif /* CONFIG_MATCH_IFACE */ @@ -273,7 +273,7 @@ /** * wpa_supplicant_add_iface - Add a new network interface -@@ -7699,6 +7703,8 @@ struct wpa_global * wpa_supplicant_init( +@@ -7726,6 +7730,8 @@ struct wpa_global * wpa_supplicant_init( #ifndef CONFIG_NO_WPA_MSG wpa_msg_register_ifname_cb(wpa_supplicant_msg_ifname_cb); #endif /* CONFIG_NO_WPA_MSG */ @@ -284,7 +284,7 @@ wpa_debug_open_file(params->wpa_debug_file_path); --- a/hostapd/main.c +++ b/hostapd/main.c -@@ -595,6 +595,11 @@ fail: +@@ -685,6 +685,11 @@ fail: return -1; } @@ -296,7 +296,7 @@ #ifdef CONFIG_WPS static int gen_uuid(const char *txt_addr) -@@ -688,6 +693,8 @@ int main(int argc, char *argv[]) +@@ -778,6 +783,8 @@ int main(int argc, char *argv[]) return -1; #endif /* CONFIG_DPP */ diff --git a/package/network/services/hostapd/patches/300-noscan.patch b/package/network/services/hostapd/patches/300-noscan.patch index 91e1aaad833..c6f9eba9d53 100644 --- a/package/network/services/hostapd/patches/300-noscan.patch +++ b/package/network/services/hostapd/patches/300-noscan.patch @@ -13,7 +13,7 @@ } else if (os_strcmp(buf, "ht_capab") == 0) { --- a/src/ap/ap_config.h +++ b/src/ap/ap_config.h -@@ -1061,6 +1061,8 @@ struct hostapd_config { +@@ -1072,6 +1072,8 @@ struct hostapd_config { int ht_op_mode_fixed; u16 ht_capab; diff --git a/package/network/services/hostapd/patches/301-mesh-noscan.patch b/package/network/services/hostapd/patches/301-mesh-noscan.patch index 8a1bdaa1854..6b5416f0ea5 100644 --- a/package/network/services/hostapd/patches/301-mesh-noscan.patch +++ b/package/network/services/hostapd/patches/301-mesh-noscan.patch @@ -1,6 +1,6 @@ --- a/wpa_supplicant/config.c +++ b/wpa_supplicant/config.c -@@ -2599,6 +2599,7 @@ static const struct parse_data ssid_fiel +@@ -2600,6 +2600,7 @@ static const struct parse_data ssid_fiel #else /* CONFIG_MESH */ { INT_RANGE(mode, 0, 4) }, #endif /* CONFIG_MESH */ @@ -31,7 +31,7 @@ /* --- a/wpa_supplicant/wpa_supplicant.c +++ b/wpa_supplicant/wpa_supplicant.c -@@ -2693,7 +2693,7 @@ static bool ibss_mesh_can_use_vht(struct +@@ -2710,7 +2710,7 @@ static bool ibss_mesh_can_use_vht(struct const struct wpa_ssid *ssid, struct hostapd_hw_modes *mode) { @@ -40,7 +40,7 @@ return false; if (!drv_supports_vht(wpa_s, ssid)) -@@ -2766,7 +2766,7 @@ static void ibss_mesh_select_40mhz(struc +@@ -2783,7 +2783,7 @@ static void ibss_mesh_select_40mhz(struc int i, res; unsigned int j; static const int ht40plus[] = { @@ -49,7 +49,7 @@ 184, 192 }; int ht40 = -1; -@@ -3016,7 +3016,7 @@ void ibss_mesh_setup_freq(struct wpa_sup +@@ -3033,7 +3033,7 @@ void ibss_mesh_setup_freq(struct wpa_sup int ieee80211_mode = wpas_mode_to_ieee80211_mode(ssid->mode); enum hostapd_hw_mode hw_mode; struct hostapd_hw_modes *mode = NULL; diff --git a/package/network/services/hostapd/patches/310-rescan_immediately.patch b/package/network/services/hostapd/patches/310-rescan_immediately.patch index 033f763094d..a47546d38fc 100644 --- a/package/network/services/hostapd/patches/310-rescan_immediately.patch +++ b/package/network/services/hostapd/patches/310-rescan_immediately.patch @@ -1,6 +1,6 @@ --- a/wpa_supplicant/wpa_supplicant.c +++ b/wpa_supplicant/wpa_supplicant.c -@@ -5713,7 +5713,7 @@ wpa_supplicant_alloc(struct wpa_supplica +@@ -5740,7 +5740,7 @@ wpa_supplicant_alloc(struct wpa_supplica if (wpa_s == NULL) return NULL; wpa_s->scan_req = INITIAL_SCAN_REQ; diff --git a/package/network/services/hostapd/patches/330-nl80211_fix_set_freq.patch b/package/network/services/hostapd/patches/330-nl80211_fix_set_freq.patch index 93a03a6db67..c11c9572169 100644 --- a/package/network/services/hostapd/patches/330-nl80211_fix_set_freq.patch +++ b/package/network/services/hostapd/patches/330-nl80211_fix_set_freq.patch @@ -1,6 +1,6 @@ --- a/src/drivers/driver_nl80211.c +++ b/src/drivers/driver_nl80211.c -@@ -5224,7 +5224,7 @@ static int nl80211_set_channel(struct i8 +@@ -5407,7 +5407,7 @@ static int nl80211_set_channel(struct i8 freq->he_enabled, freq->eht_enabled, freq->bandwidth, freq->center_freq1, freq->center_freq2); diff --git a/package/network/services/hostapd/patches/340-reload_freq_change.patch b/package/network/services/hostapd/patches/340-reload_freq_change.patch index 9a468079d1a..ae6cd81ea4d 100644 --- a/package/network/services/hostapd/patches/340-reload_freq_change.patch +++ b/package/network/services/hostapd/patches/340-reload_freq_change.patch @@ -1,6 +1,6 @@ --- a/src/ap/hostapd.c +++ b/src/ap/hostapd.c -@@ -142,6 +142,29 @@ static void hostapd_reload_bss(struct ho +@@ -143,6 +143,29 @@ static void hostapd_reload_bss(struct ho #endif /* CONFIG_NO_RADIUS */ ssid = &hapd->conf->ssid; @@ -30,7 +30,7 @@ if (!ssid->wpa_psk_set && ssid->wpa_psk && !ssid->wpa_psk->next && ssid->wpa_passphrase_set && ssid->wpa_passphrase) { /* -@@ -250,6 +273,7 @@ int hostapd_reload_config(struct hostapd +@@ -251,6 +274,7 @@ int hostapd_reload_config(struct hostapd struct hostapd_data *hapd = iface->bss[0]; struct hostapd_config *newconf, *oldconf; size_t j; @@ -38,7 +38,7 @@ if (iface->config_fname == NULL) { /* Only in-memory config in use - assume it has been updated */ -@@ -300,6 +324,17 @@ int hostapd_reload_config(struct hostapd +@@ -301,6 +325,17 @@ int hostapd_reload_config(struct hostapd } iface->conf = newconf; @@ -56,7 +56,7 @@ for (j = 0; j < iface->num_bss; j++) { hapd = iface->bss[j]; if (!hapd->conf->config_id || !newconf->bss[j]->config_id || -@@ -307,21 +342,6 @@ int hostapd_reload_config(struct hostapd +@@ -308,21 +343,6 @@ int hostapd_reload_config(struct hostapd newconf->bss[j]->config_id) != 0) hostapd_clear_old_bss(hapd); hapd->iconf = newconf; diff --git a/package/network/services/hostapd/patches/350-nl80211_del_beacon_bss.patch b/package/network/services/hostapd/patches/350-nl80211_del_beacon_bss.patch index a943395b564..647ca2cbf97 100644 --- a/package/network/services/hostapd/patches/350-nl80211_del_beacon_bss.patch +++ b/package/network/services/hostapd/patches/350-nl80211_del_beacon_bss.patch @@ -1,6 +1,6 @@ --- a/src/drivers/driver_nl80211.c +++ b/src/drivers/driver_nl80211.c -@@ -3006,12 +3006,12 @@ static int wpa_driver_nl80211_del_beacon +@@ -3008,12 +3008,12 @@ static int wpa_driver_nl80211_del_beacon return 0; wpa_printf(MSG_DEBUG, "nl80211: Remove beacon (ifindex=%d)", @@ -15,7 +15,7 @@ if (!msg) return -ENOBUFS; -@@ -5907,7 +5907,7 @@ static void nl80211_teardown_ap(struct i +@@ -6100,7 +6100,7 @@ static void nl80211_teardown_ap(struct i nl80211_mgmt_unsubscribe(bss, "AP teardown"); nl80211_put_wiphy_data_ap(bss); @@ -24,7 +24,7 @@ } -@@ -8642,8 +8642,6 @@ static int wpa_driver_nl80211_if_remove( +@@ -8859,8 +8859,6 @@ static int wpa_driver_nl80211_if_remove( } else { wpa_printf(MSG_DEBUG, "nl80211: First BSS - reassign context"); nl80211_teardown_ap(bss); diff --git a/package/network/services/hostapd/patches/360-ctrl_iface_reload.patch b/package/network/services/hostapd/patches/360-ctrl_iface_reload.patch index e9f46ce9d36..4d85ea11f90 100644 --- a/package/network/services/hostapd/patches/360-ctrl_iface_reload.patch +++ b/package/network/services/hostapd/patches/360-ctrl_iface_reload.patch @@ -78,7 +78,7 @@ #ifdef NEED_AP_MLME static int hostapd_ctrl_iface_sa_query(struct hostapd_data *hapd, -@@ -3529,6 +3586,8 @@ static int hostapd_ctrl_iface_receive_pr +@@ -3564,6 +3621,8 @@ static int hostapd_ctrl_iface_receive_pr } else if (os_strncmp(buf, "VENDOR ", 7) == 0) { reply_len = hostapd_ctrl_iface_vendor(hapd, buf + 7, reply, reply_size); @@ -89,7 +89,7 @@ #ifdef RADIUS_SERVER --- a/src/ap/ctrl_iface_ap.c +++ b/src/ap/ctrl_iface_ap.c -@@ -1008,7 +1008,13 @@ int hostapd_parse_csa_settings(const cha +@@ -1023,7 +1023,13 @@ int hostapd_parse_csa_settings(const cha int hostapd_ctrl_iface_stop_ap(struct hostapd_data *hapd) { diff --git a/package/network/services/hostapd/patches/370-ap_sta_support.patch b/package/network/services/hostapd/patches/370-ap_sta_support.patch index 24064839f13..3baad2a52e5 100644 --- a/package/network/services/hostapd/patches/370-ap_sta_support.patch +++ b/package/network/services/hostapd/patches/370-ap_sta_support.patch @@ -172,7 +172,7 @@ wpa_s->new_connection = 1; wpa_drv_set_operstate(wpa_s, 0); #ifndef IEEE8021X_EAPOL -@@ -2520,6 +2572,8 @@ void wpa_supplicant_associate(struct wpa +@@ -2537,6 +2589,8 @@ void wpa_supplicant_associate(struct wpa return; } wpa_s->current_bss = bss; @@ -181,7 +181,7 @@ #else /* CONFIG_MESH */ wpa_msg(wpa_s, MSG_ERROR, "mesh mode support not included in the build"); -@@ -7010,6 +7064,16 @@ static int wpa_supplicant_init_iface(str +@@ -7037,6 +7091,16 @@ static int wpa_supplicant_init_iface(str sizeof(wpa_s->bridge_ifname)); } @@ -198,7 +198,7 @@ /* RSNA Supplicant Key Management - INITIALIZE */ eapol_sm_notify_portEnabled(wpa_s->eapol, false); eapol_sm_notify_portValid(wpa_s->eapol, false); -@@ -7352,6 +7416,11 @@ static void wpa_supplicant_deinit_iface( +@@ -7379,6 +7443,11 @@ static void wpa_supplicant_deinit_iface( if (terminate) wpa_msg(wpa_s, MSG_INFO, WPA_EVENT_TERMINATING); @@ -235,7 +235,7 @@ --- a/hostapd/ctrl_iface.c +++ b/hostapd/ctrl_iface.c -@@ -2716,6 +2716,12 @@ static int hostapd_ctrl_iface_chan_switc +@@ -2751,6 +2751,12 @@ static int hostapd_ctrl_iface_chan_switc return 0; } @@ -250,7 +250,7 @@ /* Save CHAN_SWITCH VHT, HE, and EHT config */ --- a/src/ap/beacon.c +++ b/src/ap/beacon.c -@@ -2052,11 +2052,6 @@ static int __ieee802_11_set_beacon(struc +@@ -2108,11 +2108,6 @@ static int __ieee802_11_set_beacon(struc return -1; } @@ -264,7 +264,7 @@ if (ieee802_11_build_ap_params(hapd, ¶ms) < 0) --- a/wpa_supplicant/events.c +++ b/wpa_supplicant/events.c -@@ -5237,6 +5237,60 @@ static void wpas_event_unprot_beacon(str +@@ -5345,6 +5345,60 @@ static void wpas_link_reconfig(struct wp } @@ -325,7 +325,7 @@ void supplicant_event(void *ctx, enum wpa_event_type event, union wpa_event_data *data) { -@@ -5586,8 +5640,10 @@ void supplicant_event(void *ctx, enum wp +@@ -5697,8 +5751,10 @@ void supplicant_event(void *ctx, enum wp channel_width_to_string(data->ch_switch.ch_width), data->ch_switch.cf1, data->ch_switch.cf2); @@ -339,7 +339,7 @@ wpa_s->current_ssid->frequency = data->ch_switch.freq; --- a/src/drivers/driver.h +++ b/src/drivers/driver.h -@@ -6324,6 +6324,7 @@ union wpa_event_data { +@@ -6421,6 +6421,7 @@ union wpa_event_data { /** * struct ch_switch @@ -347,7 +347,7 @@ * @freq: Frequency of new channel in MHz * @ht_enabled: Whether this is an HT channel * @ch_offset: Secondary channel offset -@@ -6334,6 +6335,7 @@ union wpa_event_data { +@@ -6431,6 +6432,7 @@ union wpa_event_data { * @punct_bitmap: Puncturing bitmap */ struct ch_switch { @@ -357,7 +357,7 @@ int ch_offset; --- a/src/drivers/driver_nl80211_event.c +++ b/src/drivers/driver_nl80211_event.c -@@ -997,6 +997,7 @@ static void mlme_event_ch_switch(struct +@@ -1202,6 +1202,7 @@ static void mlme_event_ch_switch(struct struct nlattr *bw, struct nlattr *cf1, struct nlattr *cf2, struct nlattr *punct_bitmap, @@ -365,7 +365,7 @@ int finished) { struct i802_bss *bss; -@@ -1060,6 +1061,8 @@ static void mlme_event_ch_switch(struct +@@ -1265,6 +1266,8 @@ static void mlme_event_ch_switch(struct data.ch_switch.cf1 = nla_get_u32(cf1); if (cf2) data.ch_switch.cf2 = nla_get_u32(cf2); @@ -374,7 +374,7 @@ if (finished) bss->flink->freq = data.ch_switch.freq; -@@ -3604,6 +3607,7 @@ static void do_process_drv_event(struct +@@ -3848,6 +3851,7 @@ static void do_process_drv_event(struct tb[NL80211_ATTR_CENTER_FREQ1], tb[NL80211_ATTR_CENTER_FREQ2], tb[NL80211_ATTR_PUNCT_BITMAP], @@ -382,7 +382,7 @@ 0); break; case NL80211_CMD_CH_SWITCH_NOTIFY: -@@ -3616,6 +3620,7 @@ static void do_process_drv_event(struct +@@ -3860,6 +3864,7 @@ static void do_process_drv_event(struct tb[NL80211_ATTR_CENTER_FREQ1], tb[NL80211_ATTR_CENTER_FREQ2], tb[NL80211_ATTR_PUNCT_BITMAP], diff --git a/package/network/services/hostapd/patches/380-disable_ctrl_iface_mib.patch b/package/network/services/hostapd/patches/380-disable_ctrl_iface_mib.patch index b886ab74927..456599db092 100644 --- a/package/network/services/hostapd/patches/380-disable_ctrl_iface_mib.patch +++ b/package/network/services/hostapd/patches/380-disable_ctrl_iface_mib.patch @@ -12,7 +12,7 @@ else --- a/hostapd/ctrl_iface.c +++ b/hostapd/ctrl_iface.c -@@ -3342,6 +3342,7 @@ static int hostapd_ctrl_iface_receive_pr +@@ -3377,6 +3377,7 @@ static int hostapd_ctrl_iface_receive_pr reply_size); } else if (os_strcmp(buf, "STATUS-DRIVER") == 0) { reply_len = hostapd_drv_status(hapd, reply, reply_size); @@ -20,7 +20,7 @@ } else if (os_strcmp(buf, "MIB") == 0) { reply_len = ieee802_11_get_mib(hapd, reply, reply_size); if (reply_len >= 0) { -@@ -3383,6 +3384,7 @@ static int hostapd_ctrl_iface_receive_pr +@@ -3418,6 +3419,7 @@ static int hostapd_ctrl_iface_receive_pr } else if (os_strncmp(buf, "STA-NEXT ", 9) == 0) { reply_len = hostapd_ctrl_iface_sta_next(hapd, buf + 9, reply, reply_size); @@ -172,7 +172,7 @@ if (os_snprintf_error(buflen - len, ret)) --- a/src/ap/ieee802_1x.c +++ b/src/ap/ieee802_1x.c -@@ -2753,6 +2753,7 @@ static const char * bool_txt(bool val) +@@ -2834,6 +2834,7 @@ static const char * bool_txt(bool val) return val ? "TRUE" : "FALSE"; } @@ -180,7 +180,7 @@ int ieee802_1x_get_mib(struct hostapd_data *hapd, char *buf, size_t buflen) { -@@ -2939,6 +2940,7 @@ int ieee802_1x_get_mib_sta(struct hostap +@@ -3020,6 +3021,7 @@ int ieee802_1x_get_mib_sta(struct hostap return len; } @@ -190,7 +190,7 @@ static void ieee802_1x_wnm_notif_send(void *eloop_ctx, void *timeout_ctx) --- a/src/ap/wpa_auth.c +++ b/src/ap/wpa_auth.c -@@ -4786,6 +4786,7 @@ static const char * wpa_bool_txt(int val +@@ -5328,6 +5328,7 @@ static const char * wpa_bool_txt(int val return val ? "TRUE" : "FALSE"; } @@ -198,7 +198,7 @@ #define RSN_SUITE "%02x-%02x-%02x-%d" #define RSN_SUITE_ARG(s) \ -@@ -4938,7 +4939,7 @@ int wpa_get_mib_sta(struct wpa_state_mac +@@ -5480,7 +5481,7 @@ int wpa_get_mib_sta(struct wpa_state_mac return len; } diff --git a/package/network/services/hostapd/patches/420-indicate-features.patch b/package/network/services/hostapd/patches/420-indicate-features.patch index 356d5f8c681..786b83d3151 100644 --- a/package/network/services/hostapd/patches/420-indicate-features.patch +++ b/package/network/services/hostapd/patches/420-indicate-features.patch @@ -9,7 +9,7 @@ struct hapd_global { void **drv_priv; -@@ -696,7 +696,7 @@ int main(int argc, char *argv[]) +@@ -786,7 +786,7 @@ int main(int argc, char *argv[]) wpa_supplicant_event = hostapd_wpa_event; wpa_supplicant_event_global = hostapd_wpa_event_global; for (;;) { @@ -18,7 +18,7 @@ if (c < 0) break; switch (c) { -@@ -733,6 +733,8 @@ int main(int argc, char *argv[]) +@@ -823,6 +823,8 @@ int main(int argc, char *argv[]) break; #endif /* CONFIG_DEBUG_LINUX_TRACING */ case 'v': diff --git a/package/network/services/hostapd/patches/450-scan_wait.patch b/package/network/services/hostapd/patches/450-scan_wait.patch index e265d1ac7ca..45886896ee9 100644 --- a/package/network/services/hostapd/patches/450-scan_wait.patch +++ b/package/network/services/hostapd/patches/450-scan_wait.patch @@ -24,16 +24,16 @@ /** * hostapd_driver_init - Preparate driver interface -@@ -164,6 +174,8 @@ static int hostapd_driver_init(struct ho - return -1; +@@ -217,6 +227,8 @@ static int hostapd_driver_init(struct ho } + #endif /* CONFIG_IEEE80211BE */ + hapd->setup_complete_cb = hostapd_setup_complete_cb; + /* Initialize the driver interface */ if (!(b[0] | b[1] | b[2] | b[3] | b[4] | b[5])) b = NULL; -@@ -407,8 +419,6 @@ static void hostapd_global_deinit(const +@@ -497,8 +509,6 @@ static void hostapd_global_deinit(const #endif /* CONFIG_NATIVE_WINDOWS */ eap_server_unregister_methods(); @@ -42,7 +42,7 @@ } -@@ -434,18 +444,6 @@ static int hostapd_global_run(struct hap +@@ -524,18 +534,6 @@ static int hostapd_global_run(struct hap } #endif /* EAP_SERVER_TNC */ @@ -61,7 +61,7 @@ eloop_run(); return 0; -@@ -649,8 +647,7 @@ int main(int argc, char *argv[]) +@@ -739,8 +737,7 @@ int main(int argc, char *argv[]) struct hapd_interfaces interfaces; int ret = 1; size_t i, j; diff --git a/package/network/services/hostapd/patches/460-wpa_supplicant-add-new-config-params-to-be-used-with.patch b/package/network/services/hostapd/patches/460-wpa_supplicant-add-new-config-params-to-be-used-with.patch index 80987774597..4c728681393 100644 --- a/package/network/services/hostapd/patches/460-wpa_supplicant-add-new-config-params-to-be-used-with.patch +++ b/package/network/services/hostapd/patches/460-wpa_supplicant-add-new-config-params-to-be-used-with.patch @@ -22,7 +22,7 @@ Signed-hostap: Antonio Quartulli #include "common/defs.h" #include "common/ieee802_11_defs.h" #include "common/wpa_common.h" -@@ -936,6 +937,9 @@ struct wpa_driver_associate_params { +@@ -953,6 +954,9 @@ struct wpa_driver_associate_params { * responsible for selecting with which BSS to associate. */ const u8 *bssid; @@ -140,7 +140,7 @@ Signed-hostap: Antonio Quartulli /* Helper macros for network block parser */ #ifdef OFFSET -@@ -2673,6 +2765,8 @@ static const struct parse_data ssid_fiel +@@ -2674,6 +2766,8 @@ static const struct parse_data ssid_fiel { INT(ap_max_inactivity) }, { INT(dtim_period) }, { INT(beacon_int) }, @@ -174,7 +174,7 @@ Signed-hostap: Antonio Quartulli * macsec_policy - Determines the policy for MACsec secure session --- a/wpa_supplicant/wpa_supplicant.c +++ b/wpa_supplicant/wpa_supplicant.c -@@ -4177,6 +4177,12 @@ static void wpas_start_assoc_cb(struct w +@@ -4203,6 +4203,12 @@ static void wpas_start_assoc_cb(struct w params.beacon_int = ssid->beacon_int; else params.beacon_int = wpa_s->conf->beacon_int; diff --git a/package/network/services/hostapd/patches/463-add-mcast_rate-to-11s.patch b/package/network/services/hostapd/patches/463-add-mcast_rate-to-11s.patch index e738ea13164..be9e0507d6d 100644 --- a/package/network/services/hostapd/patches/463-add-mcast_rate-to-11s.patch +++ b/package/network/services/hostapd/patches/463-add-mcast_rate-to-11s.patch @@ -19,7 +19,7 @@ Tested-by: Simon Wunderlich --- a/src/drivers/driver.h +++ b/src/drivers/driver.h -@@ -1768,6 +1768,7 @@ struct wpa_driver_mesh_join_params { +@@ -1827,6 +1827,7 @@ struct wpa_driver_mesh_join_params { #define WPA_DRIVER_MESH_FLAG_AMPE 0x00000008 unsigned int flags; bool handle_dfs; @@ -29,7 +29,7 @@ Tested-by: Simon Wunderlich struct wpa_driver_set_key_params { --- a/src/drivers/driver_nl80211.c +++ b/src/drivers/driver_nl80211.c -@@ -11388,6 +11388,18 @@ static int nl80211_put_mesh_id(struct nl +@@ -11626,6 +11626,18 @@ static int nl80211_put_mesh_id(struct nl } @@ -48,7 +48,7 @@ Tested-by: Simon Wunderlich static int nl80211_put_mesh_config(struct nl_msg *msg, struct wpa_driver_mesh_bss_params *params) { -@@ -11449,6 +11461,7 @@ static int nl80211_join_mesh(struct i802 +@@ -11687,6 +11699,7 @@ static int nl80211_join_mesh(struct i802 nl80211_put_basic_rates(msg, params->basic_rates) || nl80211_put_mesh_id(msg, params->meshid, params->meshid_len) || nl80211_put_beacon_int(msg, params->beacon_int) || diff --git a/package/network/services/hostapd/patches/464-fix-mesh-obss-check.patch b/package/network/services/hostapd/patches/464-fix-mesh-obss-check.patch index 73ccc65ad98..c7e8cf25ce8 100644 --- a/package/network/services/hostapd/patches/464-fix-mesh-obss-check.patch +++ b/package/network/services/hostapd/patches/464-fix-mesh-obss-check.patch @@ -1,6 +1,6 @@ --- a/wpa_supplicant/wpa_supplicant.c +++ b/wpa_supplicant/wpa_supplicant.c -@@ -3077,6 +3077,10 @@ void ibss_mesh_setup_freq(struct wpa_sup +@@ -3094,6 +3094,10 @@ void ibss_mesh_setup_freq(struct wpa_sup freq->freq = ssid->frequency; diff --git a/package/network/services/hostapd/patches/590-rrm-wnm-statistics.patch b/package/network/services/hostapd/patches/590-rrm-wnm-statistics.patch index a6f43171ccd..0efa6db9085 100644 --- a/package/network/services/hostapd/patches/590-rrm-wnm-statistics.patch +++ b/package/network/services/hostapd/patches/590-rrm-wnm-statistics.patch @@ -1,6 +1,6 @@ --- a/src/ap/hostapd.h +++ b/src/ap/hostapd.h -@@ -162,6 +162,21 @@ struct hostapd_sae_commit_queue { +@@ -163,6 +163,21 @@ struct hostapd_sae_commit_queue { }; /** @@ -22,9 +22,9 @@ * struct hostapd_data - hostapd per-BSS data structure */ struct hostapd_data { -@@ -175,6 +190,9 @@ struct hostapd_data { +@@ -182,6 +197,9 @@ struct hostapd_data { - u8 own_addr[ETH_ALEN]; + struct hostapd_data *mld_first_bss; + /* OpenWrt specific statistics */ + struct hostapd_openwrt_stats openwrt_stats; diff --git a/package/network/services/hostapd/patches/600-ubus_support.patch b/package/network/services/hostapd/patches/600-ubus_support.patch index aa68079fb26..f3936342a5f 100644 --- a/package/network/services/hostapd/patches/600-ubus_support.patch +++ b/package/network/services/hostapd/patches/600-ubus_support.patch @@ -31,7 +31,7 @@ }; enum hostapd_chan_status { -@@ -183,6 +184,7 @@ struct hostapd_data { +@@ -184,6 +185,7 @@ struct hostapd_data { struct hostapd_iface *iface; struct hostapd_config *iconf; struct hostapd_bss_config *conf; @@ -39,7 +39,7 @@ int interface_added; /* virtual interface added for this BSS */ unsigned int started:1; unsigned int disabled:1; -@@ -682,6 +684,7 @@ hostapd_alloc_bss_data(struct hostapd_if +@@ -695,6 +697,7 @@ hostapd_alloc_bss_data(struct hostapd_if struct hostapd_bss_config *bss); int hostapd_setup_interface(struct hostapd_iface *iface); int hostapd_setup_interface_complete(struct hostapd_iface *iface, int err); @@ -49,7 +49,7 @@ struct hostapd_iface * hostapd_alloc_iface(void); --- a/src/ap/hostapd.c +++ b/src/ap/hostapd.c -@@ -435,6 +435,7 @@ void hostapd_free_hapd_data(struct hosta +@@ -455,6 +455,7 @@ void hostapd_free_hapd_data(struct hosta hapd->beacon_set_done = 0; wpa_printf(MSG_DEBUG, "%s(%s)", __func__, hapd->conf->iface); @@ -57,7 +57,7 @@ accounting_deinit(hapd); hostapd_deinit_wpa(hapd); vlan_deinit(hapd); -@@ -1185,6 +1186,8 @@ static int hostapd_start_beacon(struct h +@@ -1207,6 +1208,8 @@ static int hostapd_start_beacon(struct h if (hapd->driver && hapd->driver->set_operstate) hapd->driver->set_operstate(hapd->drv_priv, 1); @@ -66,7 +66,7 @@ return 0; } -@@ -2126,6 +2129,7 @@ static int hostapd_setup_interface_compl +@@ -2295,6 +2298,7 @@ static int hostapd_setup_interface_compl if (err) goto fail; @@ -74,15 +74,15 @@ wpa_printf(MSG_DEBUG, "Completing interface initialization"); if (iface->freq) { #ifdef NEED_AP_MLME -@@ -2342,6 +2346,7 @@ dfs_offload: +@@ -2514,6 +2518,7 @@ dfs_offload: fail: wpa_printf(MSG_ERROR, "Interface initialization failed"); + hostapd_ubus_free_iface(iface); - hostapd_set_state(iface, HAPD_IFACE_DISABLED); - wpa_msg(hapd->msg_ctx, MSG_INFO, AP_EVENT_DISABLED); - #ifdef CONFIG_FST -@@ -2817,6 +2822,7 @@ void hostapd_interface_deinit_free(struc + + if (iface->is_no_ir) { + hostapd_set_state(iface, HAPD_IFACE_NO_IR); +@@ -3004,6 +3009,7 @@ void hostapd_interface_deinit_free(struc (unsigned int) iface->conf->num_bss); driver = iface->bss[0]->driver; drv_priv = iface->bss[0]->drv_priv; @@ -92,7 +92,7 @@ __func__, driver, drv_priv); --- a/src/ap/ieee802_11.c +++ b/src/ap/ieee802_11.c -@@ -2740,13 +2740,18 @@ static void handle_auth(struct hostapd_d +@@ -2778,7 +2778,7 @@ static void handle_auth(struct hostapd_d u16 auth_alg, auth_transaction, status_code; u16 resp = WLAN_STATUS_SUCCESS; struct sta_info *sta = NULL; @@ -101,9 +101,10 @@ u16 fc; const u8 *challenge = NULL; u8 resp_ies[2 + WLAN_AUTH_CHALLENGE_LEN]; - size_t resp_ies_len = 0; - u16 seq_ctrl; +@@ -2787,6 +2787,11 @@ static void handle_auth(struct hostapd_d struct radius_sta rad_info; + const u8 *dst, *sa, *bssid; + bool mld_sta = false; + struct hostapd_ubus_request req = { + .type = HOSTAPD_UBUS_AUTH_REQ, + .mgmt_frame = mgmt, @@ -112,7 +113,7 @@ if (len < IEEE80211_HDRLEN + sizeof(mgmt->u.auth)) { wpa_printf(MSG_INFO, "handle_auth - too short payload (len=%lu)", -@@ -2914,6 +2919,13 @@ static void handle_auth(struct hostapd_d +@@ -2978,6 +2983,13 @@ static void handle_auth(struct hostapd_d resp = WLAN_STATUS_UNSPECIFIED_FAILURE; goto fail; } @@ -126,7 +127,7 @@ if (res == HOSTAPD_ACL_PENDING) return; -@@ -4695,7 +4707,7 @@ static void handle_assoc(struct hostapd_ +@@ -5141,7 +5153,7 @@ static void handle_assoc(struct hostapd_ int resp = WLAN_STATUS_SUCCESS; u16 reply_res = WLAN_STATUS_UNSPECIFIED_FAILURE; const u8 *pos; @@ -135,7 +136,7 @@ struct sta_info *sta; u8 *tmp = NULL; #ifdef CONFIG_FILS -@@ -4908,6 +4920,11 @@ static void handle_assoc(struct hostapd_ +@@ -5354,6 +5366,11 @@ static void handle_assoc(struct hostapd_ left = res; } #endif /* CONFIG_FILS */ @@ -147,7 +148,7 @@ /* followed by SSID and Supported rates; and HT capabilities if 802.11n * is used */ -@@ -5006,6 +5023,13 @@ static void handle_assoc(struct hostapd_ +@@ -5452,6 +5469,13 @@ static void handle_assoc(struct hostapd_ } #endif /* CONFIG_FILS */ @@ -161,26 +162,26 @@ fail: /* -@@ -5099,6 +5123,7 @@ static void handle_disassoc(struct hosta - wpa_printf(MSG_DEBUG, "disassocation: STA=" MACSTR " reason_code=%d", - MAC2STR(mgmt->sa), - le_to_host16(mgmt->u.disassoc.reason_code)); +@@ -5733,6 +5757,7 @@ static void handle_disassoc(struct hosta + (unsigned long) len); + return; + } + hostapd_ubus_notify(hapd, "disassoc", mgmt->sa); sta = ap_get_sta(hapd, mgmt->sa); - if (sta == NULL) { -@@ -5168,6 +5193,8 @@ static void handle_deauth(struct hostapd + if (!sta) { +@@ -5764,6 +5789,8 @@ static void handle_deauth(struct hostapd /* Clear the PTKSA cache entries for PASN */ ptksa_cache_flush(hapd->ptksa, mgmt->sa, WPA_CIPHER_NONE); + hostapd_ubus_notify(hapd, "deauth", mgmt->sa); + sta = ap_get_sta(hapd, mgmt->sa); - if (sta == NULL) { - wpa_msg(hapd->msg_ctx, MSG_DEBUG, "Station " MACSTR " trying " + if (!sta) { + wpa_msg(hapd->msg_ctx, MSG_DEBUG, "Station " MACSTR --- a/src/ap/beacon.c +++ b/src/ap/beacon.c -@@ -1006,6 +1006,12 @@ void handle_probe_req(struct hostapd_dat +@@ -1036,6 +1036,12 @@ void handle_probe_req(struct hostapd_dat u16 csa_offs[2]; size_t csa_offs_len; struct radius_sta rad_info; @@ -193,7 +194,7 @@ if (hapd->iconf->rssi_ignore_probe_request && ssi_signal && ssi_signal < hapd->iconf->rssi_ignore_probe_request) -@@ -1192,6 +1198,12 @@ void handle_probe_req(struct hostapd_dat +@@ -1222,6 +1228,12 @@ void handle_probe_req(struct hostapd_dat } #endif /* CONFIG_P2P */ @@ -234,7 +235,7 @@ wpabuf_free(sta->p2p_ie); --- a/src/ap/sta_info.c +++ b/src/ap/sta_info.c -@@ -460,6 +460,7 @@ void ap_handle_timer(void *eloop_ctx, vo +@@ -471,6 +471,7 @@ void ap_handle_timer(void *eloop_ctx, vo hostapd_logger(hapd, sta->addr, HOSTAPD_MODULE_IEEE80211, HOSTAPD_LEVEL_INFO, "deauthenticated due to " "local deauth request"); @@ -242,7 +243,7 @@ ap_free_sta(hapd, sta); return; } -@@ -615,6 +616,7 @@ skip_poll: +@@ -626,6 +627,7 @@ skip_poll: mlme_deauthenticate_indication( hapd, sta, WLAN_REASON_PREV_AUTH_NOT_VALID); @@ -250,7 +251,7 @@ ap_free_sta(hapd, sta); break; } -@@ -1305,15 +1307,28 @@ void ap_sta_set_authorized(struct hostap +@@ -1344,15 +1346,28 @@ void ap_sta_set_authorized(struct hostap sta->addr, authorized, dev_addr); if (authorized) { @@ -279,7 +280,7 @@ #ifdef CONFIG_P2P if (wpa_auth_get_ip_addr(sta->wpa_sm, ip_addr_buf) == 0) { os_snprintf(ip_addr, sizeof(ip_addr), -@@ -1323,6 +1338,13 @@ void ap_sta_set_authorized(struct hostap +@@ -1362,6 +1377,13 @@ void ap_sta_set_authorized(struct hostap } #endif /* CONFIG_P2P */ @@ -293,7 +294,7 @@ keyid = ap_sta_wpa_get_keyid(hapd, sta); if (keyid) { os_snprintf(keyid_buf, sizeof(keyid_buf), -@@ -1341,17 +1363,19 @@ void ap_sta_set_authorized(struct hostap +@@ -1380,17 +1402,19 @@ void ap_sta_set_authorized(struct hostap dpp_pkhash, SHA256_MAC_LEN); } @@ -354,7 +355,7 @@ CFLAGS += -DEAP_SERVER -DEAP_SERVER_IDENTITY --- a/wpa_supplicant/wpa_supplicant.c +++ b/wpa_supplicant/wpa_supplicant.c -@@ -7608,6 +7608,8 @@ struct wpa_supplicant * wpa_supplicant_a +@@ -7635,6 +7635,8 @@ struct wpa_supplicant * wpa_supplicant_a } #endif /* CONFIG_P2P */ @@ -363,7 +364,7 @@ return wpa_s; } -@@ -7634,6 +7636,8 @@ int wpa_supplicant_remove_iface(struct w +@@ -7661,6 +7663,8 @@ int wpa_supplicant_remove_iface(struct w struct wpa_supplicant *parent = wpa_s->parent; #endif /* CONFIG_MESH */ @@ -372,7 +373,7 @@ /* Remove interface from the global list of interfaces */ prev = global->ifaces; if (prev == wpa_s) { -@@ -7980,8 +7984,12 @@ int wpa_supplicant_run(struct wpa_global +@@ -8007,8 +8011,12 @@ int wpa_supplicant_run(struct wpa_global eloop_register_signal_terminate(wpa_supplicant_terminate, global); eloop_register_signal_reconfig(wpa_supplicant_reconfig, global); @@ -433,7 +434,7 @@ --- a/hostapd/main.c +++ b/hostapd/main.c -@@ -901,6 +901,7 @@ int main(int argc, char *argv[]) +@@ -991,6 +991,7 @@ int main(int argc, char *argv[]) } hostapd_global_ctrl_iface_init(&interfaces); @@ -441,7 +442,7 @@ if (hostapd_global_run(&interfaces, daemonize, pid_file)) { wpa_printf(MSG_ERROR, "Failed to start eloop"); -@@ -910,6 +911,7 @@ int main(int argc, char *argv[]) +@@ -1000,6 +1001,7 @@ int main(int argc, char *argv[]) ret = 0; out: @@ -574,7 +575,7 @@ } --- a/src/ap/sta_info.h +++ b/src/ap/sta_info.h -@@ -293,6 +293,7 @@ struct sta_info { +@@ -322,6 +322,7 @@ struct sta_info { #endif /* CONFIG_TESTING_OPTIONS */ #ifdef CONFIG_AIRTIME_POLICY unsigned int airtime_weight; diff --git a/package/network/services/hostapd/patches/700-wifi-reload.patch b/package/network/services/hostapd/patches/700-wifi-reload.patch index 5ac7f711a5c..e0da149c443 100644 --- a/package/network/services/hostapd/patches/700-wifi-reload.patch +++ b/package/network/services/hostapd/patches/700-wifi-reload.patch @@ -20,7 +20,7 @@ } else if (os_strcmp(buf, "channel") == 0) { --- a/src/ap/ap_config.c +++ b/src/ap/ap_config.c -@@ -997,6 +997,7 @@ void hostapd_config_free(struct hostapd_ +@@ -998,6 +998,7 @@ void hostapd_config_free(struct hostapd_ for (i = 0; i < conf->num_bss; i++) hostapd_config_free_bss(conf->bss[i]); @@ -30,7 +30,7 @@ os_free(conf->basic_rates); --- a/src/ap/ap_config.h +++ b/src/ap/ap_config.h -@@ -987,6 +987,7 @@ struct eht_phy_capabilities_info { +@@ -998,6 +998,7 @@ struct eht_phy_capabilities_info { struct hostapd_config { struct hostapd_bss_config **bss, *last_bss; size_t num_bss; @@ -40,7 +40,7 @@ int rts_threshold; --- a/src/ap/hostapd.c +++ b/src/ap/hostapd.c -@@ -254,6 +254,10 @@ static int hostapd_iface_conf_changed(st +@@ -255,6 +255,10 @@ static int hostapd_iface_conf_changed(st { size_t i; @@ -51,7 +51,7 @@ if (newconf->num_bss != oldconf->num_bss) return 1; -@@ -267,7 +271,7 @@ static int hostapd_iface_conf_changed(st +@@ -268,7 +272,7 @@ static int hostapd_iface_conf_changed(st } @@ -60,7 +60,7 @@ { struct hapd_interfaces *interfaces = iface->interfaces; struct hostapd_data *hapd = iface->bss[0]; -@@ -295,6 +299,9 @@ int hostapd_reload_config(struct hostapd +@@ -296,6 +300,9 @@ int hostapd_reload_config(struct hostapd char *fname; int res; @@ -70,7 +70,7 @@ hostapd_clear_old(iface); wpa_printf(MSG_DEBUG, -@@ -321,6 +328,24 @@ int hostapd_reload_config(struct hostapd +@@ -322,6 +329,24 @@ int hostapd_reload_config(struct hostapd wpa_printf(MSG_ERROR, "Failed to enable interface on config reload"); return res; @@ -95,7 +95,7 @@ } iface->conf = newconf; -@@ -337,6 +362,12 @@ int hostapd_reload_config(struct hostapd +@@ -338,6 +363,12 @@ int hostapd_reload_config(struct hostapd for (j = 0; j < iface->num_bss; j++) { hapd = iface->bss[j]; @@ -108,7 +108,7 @@ if (!hapd->conf->config_id || !newconf->bss[j]->config_id || os_strcmp(hapd->conf->config_id, newconf->bss[j]->config_id) != 0) -@@ -2514,6 +2545,10 @@ hostapd_alloc_bss_data(struct hostapd_if +@@ -2700,6 +2731,10 @@ hostapd_alloc_bss_data(struct hostapd_if hapd->iconf = conf; hapd->conf = bss; hapd->iface = hapd_iface; @@ -130,7 +130,7 @@ struct hostapd_config * (*config_read_cb)(const char *config_fname); int (*ctrl_iface_init)(struct hostapd_data *hapd); void (*ctrl_iface_deinit)(struct hostapd_data *hapd); -@@ -185,6 +185,7 @@ struct hostapd_data { +@@ -186,6 +186,7 @@ struct hostapd_data { struct hostapd_config *iconf; struct hostapd_bss_config *conf; struct hostapd_ubus_bss ubus; @@ -138,7 +138,7 @@ int interface_added; /* virtual interface added for this BSS */ unsigned int started:1; unsigned int disabled:1; -@@ -676,7 +677,7 @@ struct hostapd_iface { +@@ -689,7 +690,7 @@ struct hostapd_iface { int hostapd_for_each_interface(struct hapd_interfaces *interfaces, int (*cb)(struct hostapd_iface *iface, void *ctx), void *ctx); @@ -149,7 +149,7 @@ hostapd_alloc_bss_data(struct hostapd_iface *hapd_iface, --- a/src/drivers/driver_nl80211.c +++ b/src/drivers/driver_nl80211.c -@@ -5054,6 +5054,9 @@ static int wpa_driver_nl80211_set_ap(voi +@@ -5322,6 +5322,9 @@ static int wpa_driver_nl80211_set_ap(voi if (ret) { wpa_printf(MSG_DEBUG, "nl80211: Beacon set failed: %d (%s)", ret, strerror(-ret)); @@ -157,7 +157,7 @@ + ret = 0; + bss->flink->beacon_set = 0; } else { - bss->flink->beacon_set = 1; + link->beacon_set = 1; nl80211_set_bss(bss, params->cts_protect, params->preamble, --- a/hostapd/ctrl_iface.c +++ b/hostapd/ctrl_iface.c @@ -172,7 +172,7 @@ } --- a/hostapd/main.c +++ b/hostapd/main.c -@@ -320,7 +320,7 @@ static void handle_term(int sig, void *s +@@ -410,7 +410,7 @@ static void handle_term(int sig, void *s static int handle_reload_iface(struct hostapd_iface *iface, void *ctx) { diff --git a/package/network/services/hostapd/patches/720-iface_max_num_sta.patch b/package/network/services/hostapd/patches/720-iface_max_num_sta.patch index a06f141c83f..bf7e8e76175 100644 --- a/package/network/services/hostapd/patches/720-iface_max_num_sta.patch +++ b/package/network/services/hostapd/patches/720-iface_max_num_sta.patch @@ -17,7 +17,7 @@ } else if (os_strcmp(buf, "extended_key_id") == 0) { --- a/src/ap/hostapd.h +++ b/src/ap/hostapd.h -@@ -721,6 +721,7 @@ void hostapd_cleanup_cs_params(struct ho +@@ -734,6 +734,7 @@ void hostapd_cleanup_cs_params(struct ho void hostapd_periodic_iface(struct hostapd_iface *iface); int hostapd_owe_trans_get_info(struct hostapd_data *hapd); void hostapd_ocv_check_csa_sa_query(void *eloop_ctx, void *timeout_ctx); @@ -27,7 +27,7 @@ void hostapd_cleanup_cca_params(struct hostapd_data *hapd); --- a/src/ap/hostapd.c +++ b/src/ap/hostapd.c -@@ -271,6 +271,30 @@ static int hostapd_iface_conf_changed(st +@@ -272,6 +272,30 @@ static int hostapd_iface_conf_changed(st } @@ -60,7 +60,7 @@ struct hapd_interfaces *interfaces = iface->interfaces; --- a/src/ap/beacon.c +++ b/src/ap/beacon.c -@@ -1222,7 +1222,7 @@ void handle_probe_req(struct hostapd_dat +@@ -1252,7 +1252,7 @@ void handle_probe_req(struct hostapd_dat if (hapd->conf->no_probe_resp_if_max_sta && is_multicast_ether_addr(mgmt->da) && is_multicast_ether_addr(mgmt->bssid) && @@ -71,7 +71,7 @@ " since no room for additional STA", --- a/src/ap/ap_config.h +++ b/src/ap/ap_config.h -@@ -1026,6 +1026,8 @@ struct hostapd_config { +@@ -1037,6 +1037,8 @@ struct hostapd_config { unsigned int track_sta_max_num; unsigned int track_sta_max_age; diff --git a/package/network/services/hostapd/patches/730-ft_iface.patch b/package/network/services/hostapd/patches/730-ft_iface.patch index 1826c976236..0795ed15a14 100644 --- a/package/network/services/hostapd/patches/730-ft_iface.patch +++ b/package/network/services/hostapd/patches/730-ft_iface.patch @@ -21,7 +21,7 @@ int bridge_hairpin; /* hairpin_mode on bridge members */ --- a/src/ap/wpa_auth_glue.c +++ b/src/ap/wpa_auth_glue.c -@@ -1616,8 +1616,12 @@ int hostapd_setup_wpa(struct hostapd_dat +@@ -1727,8 +1727,12 @@ int hostapd_setup_wpa(struct hostapd_dat wpa_key_mgmt_ft(hapd->conf->wpa_key_mgmt)) { const char *ft_iface; diff --git a/package/network/services/hostapd/patches/750-qos_map_set_without_interworking.patch b/package/network/services/hostapd/patches/750-qos_map_set_without_interworking.patch index c3a77bc6537..e06e36c37d1 100644 --- a/package/network/services/hostapd/patches/750-qos_map_set_without_interworking.patch +++ b/package/network/services/hostapd/patches/750-qos_map_set_without_interworking.patch @@ -32,7 +32,7 @@ os_free(bss->dump_msk_file); --- a/src/ap/hostapd.c +++ b/src/ap/hostapd.c -@@ -1499,6 +1499,7 @@ static int hostapd_setup_bss(struct host +@@ -1534,6 +1534,7 @@ static int hostapd_setup_bss(struct host wpa_printf(MSG_ERROR, "GAS server initialization failed"); return -1; } @@ -40,7 +40,7 @@ if (conf->qos_map_set_len && hostapd_drv_set_qos_map(hapd, conf->qos_map_set, -@@ -1506,7 +1507,6 @@ static int hostapd_setup_bss(struct host +@@ -1541,7 +1542,6 @@ static int hostapd_setup_bss(struct host wpa_printf(MSG_ERROR, "Failed to initialize QoS Map"); return -1; } @@ -50,7 +50,7 @@ wpa_printf(MSG_ERROR, "BSS Load initialization failed"); --- a/wpa_supplicant/events.c +++ b/wpa_supplicant/events.c -@@ -2672,8 +2672,6 @@ void wnm_bss_keep_alive_deinit(struct wp +@@ -2683,8 +2683,6 @@ void wnm_bss_keep_alive_deinit(struct wp } @@ -59,7 +59,7 @@ static int wpas_qos_map_set(struct wpa_supplicant *wpa_s, const u8 *qos_map, size_t len) { -@@ -2706,8 +2704,6 @@ static void interworking_process_assoc_r +@@ -2717,8 +2715,6 @@ static void interworking_process_assoc_r } } @@ -68,7 +68,7 @@ static void wpa_supplicant_set_4addr_mode(struct wpa_supplicant *wpa_s) { -@@ -3087,10 +3083,8 @@ static int wpa_supplicant_event_associnf +@@ -3098,10 +3094,8 @@ static int wpa_supplicant_event_associnf wnm_process_assoc_resp(wpa_s, data->assoc_info.resp_ies, data->assoc_info.resp_ies_len); #endif /* CONFIG_WNM */ diff --git a/package/network/services/hostapd/patches/751-qos_map_ignore_when_unsupported.patch b/package/network/services/hostapd/patches/751-qos_map_ignore_when_unsupported.patch index 1fc4e8a77cf..f5ebab70d1d 100644 --- a/package/network/services/hostapd/patches/751-qos_map_ignore_when_unsupported.patch +++ b/package/network/services/hostapd/patches/751-qos_map_ignore_when_unsupported.patch @@ -1,6 +1,6 @@ --- a/src/ap/ap_drv_ops.c +++ b/src/ap/ap_drv_ops.c -@@ -874,7 +874,8 @@ int hostapd_start_dfs_cac(struct hostapd +@@ -927,7 +927,8 @@ int hostapd_start_dfs_cac(struct hostapd int hostapd_drv_set_qos_map(struct hostapd_data *hapd, const u8 *qos_map_set, u8 qos_map_set_len) { diff --git a/package/network/services/hostapd/patches/760-dynamic_own_ip.patch b/package/network/services/hostapd/patches/760-dynamic_own_ip.patch index 2f5015892b7..2c705a68cf0 100644 --- a/package/network/services/hostapd/patches/760-dynamic_own_ip.patch +++ b/package/network/services/hostapd/patches/760-dynamic_own_ip.patch @@ -85,7 +85,7 @@ RadiusType msg_type, const u8 *addr); --- a/src/ap/ieee802_1x.c +++ b/src/ap/ieee802_1x.c -@@ -535,6 +535,10 @@ int add_common_radius_attr(struct hostap +@@ -598,6 +598,10 @@ int add_common_radius_attr(struct hostap struct hostapd_radius_attr *attr; int len; diff --git a/package/network/services/hostapd/patches/761-shared_das_port.patch b/package/network/services/hostapd/patches/761-shared_das_port.patch index 59c2a967953..dad7afddf13 100644 --- a/package/network/services/hostapd/patches/761-shared_das_port.patch +++ b/package/network/services/hostapd/patches/761-shared_das_port.patch @@ -10,14 +10,14 @@ unsigned int time_window; --- a/src/ap/hostapd.c +++ b/src/ap/hostapd.c -@@ -1442,6 +1442,7 @@ static int hostapd_setup_bss(struct host - struct radius_das_conf das_conf; - os_memset(&das_conf, 0, sizeof(das_conf)); - das_conf.port = conf->radius_das_port; -+ das_conf.nas_identifier = conf->nas_identifier; - das_conf.shared_secret = conf->radius_das_shared_secret; - das_conf.shared_secret_len = - conf->radius_das_shared_secret_len; +@@ -1471,6 +1471,7 @@ static int hostapd_setup_bss(struct host + + os_memset(&das_conf, 0, sizeof(das_conf)); + das_conf.port = conf->radius_das_port; ++ das_conf.nas_identifier = conf->nas_identifier; + das_conf.shared_secret = conf->radius_das_shared_secret; + das_conf.shared_secret_len = + conf->radius_das_shared_secret_len; --- a/src/radius/radius_das.c +++ b/src/radius/radius_das.c @@ -12,13 +12,26 @@ From 0dc0504fc8e5f0c3cafe6c1da7192f51a09c5bc3 Mon Sep 17 00:00:00 2001 From: John Audia Date: Wed, 5 Jul 2023 16:54:48 -0400 Subject: [PATCH 34/53] kernel: bump 5.15 to 5.15.120 All patches automatically rebased. Build system: x86_64 Build-tested: ramips/tplink_archer-a6-v3, filogic/xiaomi_redmi-router-ax6000-ubootmod Run-tested: ramips/tplink_archer-a6-v3, filogic/xiaomi_redmi-router-ax6000-ubootmod Signed-off-by: John Audia --- include/kernel-5.15 | 4 ++-- .../020-v6.1-01-mm-x86-arm64-add-arch_has_hw_pte_young.patch | 2 +- .../020-v6.1-05-mm-multi-gen-LRU-groundwork.patch | 4 ++-- .../backport-5.15/020-v6.3-19-mm-add-vma_has_recency.patch | 2 +- ...thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch | 2 +- ...2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch | 2 +- 6 files changed, 8 insertions(+), 8 deletions(-) diff --git a/include/kernel-5.15 b/include/kernel-5.15 index ac48a2e8b11..bf681e2edbe 100644 --- a/include/kernel-5.15 +++ b/include/kernel-5.15 @@ -1,2 +1,2 @@ -LINUX_VERSION-5.15 = .119 -LINUX_KERNEL_HASH-5.15.119 = 7aa5a0fd3520947e5599e811d28acdc30e36446c016c7dcee3793e6d1cbecfcf +LINUX_VERSION-5.15 = .120 +LINUX_KERNEL_HASH-5.15.120 = 6499089eae6b271063cb3e873ab7f4ba0543cfb21dcc9c54d9bcf5357db683f6 diff --git a/target/linux/generic/backport-5.15/020-v6.1-01-mm-x86-arm64-add-arch_has_hw_pte_young.patch b/target/linux/generic/backport-5.15/020-v6.1-01-mm-x86-arm64-add-arch_has_hw_pte_young.patch index df854ffd3d8..73acadd804c 100644 --- a/target/linux/generic/backport-5.15/020-v6.1-01-mm-x86-arm64-add-arch_has_hw_pte_young.patch +++ b/target/linux/generic/backport-5.15/020-v6.1-01-mm-x86-arm64-add-arch_has_hw_pte_young.patch @@ -414,7 +414,7 @@ Signed-off-by: Andrew Morton #ifndef arch_wants_old_prefaulted_pte static inline bool arch_wants_old_prefaulted_pte(void) { -@@ -2782,7 +2770,7 @@ static inline bool cow_user_page(struct +@@ -2791,7 +2779,7 @@ static inline int cow_user_page(struct p * On architectures with software "accessed" bits, we would * take a double page fault, so mark it accessed here. */ diff --git a/target/linux/generic/backport-5.15/020-v6.1-05-mm-multi-gen-LRU-groundwork.patch b/target/linux/generic/backport-5.15/020-v6.1-05-mm-multi-gen-LRU-groundwork.patch index 237bd84875d..25457926a48 100644 --- a/target/linux/generic/backport-5.15/020-v6.1-05-mm-multi-gen-LRU-groundwork.patch +++ b/target/linux/generic/backport-5.15/020-v6.1-05-mm-multi-gen-LRU-groundwork.patch @@ -612,7 +612,7 @@ Signed-off-by: Andrew Morton mem_cgroup_id_remove(memcg); --- a/mm/memory.c +++ b/mm/memory.c -@@ -4792,6 +4792,27 @@ static inline void mm_account_fault(stru +@@ -4805,6 +4805,27 @@ static inline void mm_account_fault(stru perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, regs, address); } @@ -640,7 +640,7 @@ Signed-off-by: Andrew Morton /* * By the time we get here, we already hold the mm semaphore * -@@ -4823,11 +4844,15 @@ vm_fault_t handle_mm_fault(struct vm_are +@@ -4836,11 +4857,15 @@ vm_fault_t handle_mm_fault(struct vm_are if (flags & FAULT_FLAG_USER) mem_cgroup_enter_user_fault(); diff --git a/target/linux/generic/backport-5.15/020-v6.3-19-mm-add-vma_has_recency.patch b/target/linux/generic/backport-5.15/020-v6.3-19-mm-add-vma_has_recency.patch index d740c5bd1d5..0e9ed9a7eb2 100644 --- a/target/linux/generic/backport-5.15/020-v6.3-19-mm-add-vma_has_recency.patch +++ b/target/linux/generic/backport-5.15/020-v6.3-19-mm-add-vma_has_recency.patch @@ -92,7 +92,7 @@ Signed-off-by: Andrew Morton mark_page_accessed(page); } rss[mm_counter(page)]--; -@@ -4795,8 +4795,8 @@ static inline void mm_account_fault(stru +@@ -4808,8 +4808,8 @@ static inline void mm_account_fault(stru #ifdef CONFIG_LRU_GEN static void lru_gen_enter_fault(struct vm_area_struct *vma) { diff --git a/target/linux/mediatek/patches-5.15/805-v6.2-thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch b/target/linux/mediatek/patches-5.15/805-v6.2-thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch index b142b22eb8d..c58ae96403a 100644 --- a/target/linux/mediatek/patches-5.15/805-v6.2-thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch +++ b/target/linux/mediatek/patches-5.15/805-v6.2-thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch @@ -42,7 +42,7 @@ Signed-off-by: Daniel Golle /* * The first read of a sensor often contains very high bogus -@@ -1085,6 +1083,11 @@ static int mtk_thermal_probe(struct plat +@@ -1075,6 +1073,11 @@ static int mtk_thermal_probe(struct plat mtk_thermal_release_periodic_ts(mt, auxadc_base); } diff --git a/target/linux/mediatek/patches-5.15/806-v6.2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch b/target/linux/mediatek/patches-5.15/806-v6.2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch index 3ac2e7fc28c..65311d5718d 100644 --- a/target/linux/mediatek/patches-5.15/806-v6.2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch +++ b/target/linux/mediatek/patches-5.15/806-v6.2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch @@ -210,7 +210,7 @@ Signed-off-by: Daniel Golle .compatible = "mediatek,mt8183-thermal", .data = (void *)&mt8183_thermal_data, }, { -@@ -1078,15 +1196,24 @@ static int mtk_thermal_probe(struct plat +@@ -1068,15 +1186,24 @@ static int mtk_thermal_probe(struct plat goto err_disable_clk_auxadc; } From 2024e84d640c397d119b2917ea98e036cd8fb606 Mon Sep 17 00:00:00 2001 From: John Audia Date: Wed, 5 Jul 2023 16:12:18 -0400 Subject: [PATCH 35/53] kernel: bump 6.1 to 6.1.38 Stable kernel git log: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/log/?h=v6.1.38 No patches needed to be rebased. Just updated checksum. Build system: x86_64 Build-tested: x86_64/AMD Ryzen 7 Run-tested: x86_64/AMD Ryzen 7 Signed-off-by: John Audia [add link to stable kernel git log] Signed-off-by: Nick Hainke --- include/kernel-6.1 | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/kernel-6.1 b/include/kernel-6.1 index 5a672efd323..f844ef1c295 100644 --- a/include/kernel-6.1 +++ b/include/kernel-6.1 @@ -1,2 +1,2 @@ -LINUX_VERSION-6.1 = .37 -LINUX_KERNEL_HASH-6.1.37 = 46cad712d261a23c8e483a3b79b6a84b9a5f731a8921c9127df35ae35cef1e80 \ No newline at end of file +LINUX_VERSION-6.1 = .38 +LINUX_KERNEL_HASH-6.1.38 = f9a4f91b609f7d332a5f2be01ab86336fa00149fae6bdc19f16fa19f78802d43 \ No newline at end of file From 0e83b5e6cc8e2970905a2b32c990fa7491ff733c Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Sun, 2 Apr 2023 23:32:11 +0200 Subject: [PATCH 36/53] wolfssl: update to 5.6.3 Release Notes: - https://github.com/wolfSSL/wolfssl/releases/tag/v5.6.0-stable - https://github.com/wolfSSL/wolfssl/releases/tag/v5.6.2-stable - https://github.com/wolfSSL/wolfssl/releases/tag/v5.6.3-stable Refresh patch: - 100-disable-hardening-check.patch Backport patch: - 001-fix-detection-of-cut-tool-in-configure.ac.patch Signed-off-by: Nick Hainke --- package/libs/wolfssl/Makefile | 6 ++--- ...etection-of-cut-tool-in-configure.ac.patch | 25 +++++++++++++++++++ .../patches/100-disable-hardening-check.patch | 6 ++--- 3 files changed, 31 insertions(+), 6 deletions(-) create mode 100644 package/libs/wolfssl/patches/001-fix-detection-of-cut-tool-in-configure.ac.patch diff --git a/package/libs/wolfssl/Makefile b/package/libs/wolfssl/Makefile index d9426d75fc3..ae802e210e7 100644 --- a/package/libs/wolfssl/Makefile +++ b/package/libs/wolfssl/Makefile @@ -8,12 +8,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=wolfssl -PKG_VERSION:=5.5.4-stable -PKG_RELEASE:=4 +PKG_VERSION:=5.6.3-stable +PKG_RELEASE:=1 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=https://github.com/wolfSSL/wolfssl/archive/v$(PKG_VERSION) -PKG_HASH:=b7ee150e49def77c765bc02aac92ddeb0bebefd4cb12aa263d8f95e405221fb8 +PKG_HASH:=2e74a397fa797c2902d7467d500de904907666afb4ff80f6464f6efd5afb114a PKG_FIXUP:=libtool libtool-abiver PKG_INSTALL:=1 diff --git a/package/libs/wolfssl/patches/001-fix-detection-of-cut-tool-in-configure.ac.patch b/package/libs/wolfssl/patches/001-fix-detection-of-cut-tool-in-configure.ac.patch new file mode 100644 index 00000000000..0d0c8b54236 --- /dev/null +++ b/package/libs/wolfssl/patches/001-fix-detection-of-cut-tool-in-configure.ac.patch @@ -0,0 +1,25 @@ +From 41d248461bd9ad44193a4806ecb5361513e8944e Mon Sep 17 00:00:00 2001 +From: jordan +Date: Tue, 27 Jun 2023 13:18:25 -0500 +Subject: [PATCH] fix detection of cut tool in configure.ac + +--- + configure.ac | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/configure.ac ++++ b/configure.ac +@@ -8723,10 +8723,11 @@ echo "extern \"C\" {" >> $OPTION_FILE + echo "#endif" >> $OPTION_FILE + echo "" >> $OPTION_FILE + +-# check for supported command to trim option with ++# Check for supported command to trim option with. ++# note: cut requires an argument to exit with success. + if colrm >/dev/null 2>&1 /dev/null 2>&1 /dev/null 2>&1 Date: Fri, 7 Jul 2023 18:26:32 +0300 Subject: [PATCH 37/53] apm821xx: fix autoloading of kmod-hw-crypto4xx Fixes: 55fbcad20a2d (apm821xx: make crypto4xx as a standalone module) Signed-off-by: Rani Hod --- target/linux/apm821xx/modules.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/apm821xx/modules.mk b/target/linux/apm821xx/modules.mk index f8880d67124..1abb12a483f 100644 --- a/target/linux/apm821xx/modules.mk +++ b/target/linux/apm821xx/modules.mk @@ -23,7 +23,7 @@ define KernelPackage/hw-crypto-4xx +kmod-crypto-ccm +kmod-crypto-gcm \ +kmod-crypto-sha1 +kmod-crypto-sha256 +kmod-crypto-sha512 FILES:=$(LINUX_DIR)/drivers/crypto/amcc/crypto4xx.ko - AUTOLOAD:=$(call AutoLoad,09,sata_dwc_460ex,1) + AUTOLOAD:=$(call AutoLoad,09,crypto4xx,1) $(call AddDepends/crypto) endef From 6b52a9b7520e6982c4876d792b10ad8771dc7f1b Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sat, 8 Jul 2023 12:33:17 +0100 Subject: [PATCH 38/53] kernel: add two missing symbols in 6.1 Two more new symbols were discovered when building mediatek targets with CONFIG_ALL_KMODS=y. Signed-off-by: Daniel Golle --- target/linux/generic/config-6.1 | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/linux/generic/config-6.1 b/target/linux/generic/config-6.1 index 4d7ef7b2bdd..6a3ed63f56a 100644 --- a/target/linux/generic/config-6.1 +++ b/target/linux/generic/config-6.1 @@ -3133,6 +3133,7 @@ CONFIG_KERNFS=y # CONFIG_KEYBOARD_MAX7359 is not set # CONFIG_KEYBOARD_MCS is not set # CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_MT6779 is not set # CONFIG_KEYBOARD_NEWTON is not set # CONFIG_KEYBOARD_OMAP4 is not set # CONFIG_KEYBOARD_OPENCORES is not set @@ -6297,6 +6298,7 @@ CONFIG_SND_SOC_INTEL_SST_TOPLEVEL=y # CONFIG_SND_SOC_MT6797 is not set # CONFIG_SND_SOC_MT8173 is not set # CONFIG_SND_SOC_MT8183 is not set +# CONFIG_SND_SOC_MT8186 is not set # CONFIG_SND_SOC_MT8192 is not set # CONFIG_SND_SOC_MT8195 is not set # CONFIG_SND_SOC_MTK_BTCVSD is not set From 0f9e8baa9ec38288c587893667ac4d103ccd7bfe Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sat, 8 Jul 2023 14:46:18 +0100 Subject: [PATCH 39/53] kernel: leds-ws2812b: fix build with Linux >= 5.18 The return value of the .remove function pointer has changed from int to void with Linux 5.18. Use a precompiler macro to allow building the leds-ws2812b module with both, Linux 5.15 and Linux 6.1. Signed-off-by: Daniel Golle --- package/kernel/leds-ws2812b/src/leds-ws2812b.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/package/kernel/leds-ws2812b/src/leds-ws2812b.c b/package/kernel/leds-ws2812b/src/leds-ws2812b.c index b0d13f52427..0dba128c1f0 100644 --- a/package/kernel/leds-ws2812b/src/leds-ws2812b.c +++ b/package/kernel/leds-ws2812b/src/leds-ws2812b.c @@ -17,6 +17,7 @@ #include #include #include +#include #define WS2812B_BYTES_PER_COLOR 3 #define WS2812B_NUM_COLORS 3 @@ -191,7 +192,11 @@ ERR_UNREG_LEDS: return ret; } +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,18,0) +static void ws2812b_remove(struct spi_device *spi) +#else static int ws2812b_remove(struct spi_device *spi) +#endif { struct ws2812b_priv *priv = spi_get_drvdata(spi); int cur_led; @@ -201,7 +206,9 @@ static int ws2812b_remove(struct spi_device *spi) kfree(priv->data_buf); mutex_destroy(&priv->mutex); +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,18,0) return 0; +#endif } static const struct spi_device_id ws2812b_spi_ids[] = { From 0b80c5725fd70bfd23701cd49fa9f252f6835506 Mon Sep 17 00:00:00 2001 From: Martin Schiller Date: Fri, 7 Jul 2023 13:29:45 +0200 Subject: [PATCH 40/53] e2fsprogs: do not symlink tune2fs to findfs commit c0611b45a998 ("e2fsprogs: symlink e2fsck to fsck.ext{2, 3, 4}, and tune2fs to findfs") introduced a symlink from tune2fs to findfs. This only works when the included private libblkid library is used, but commit 5b1660a5387b ("utils/e2fsprogs: Update to 1.43.6") disabled the usage of this private lib and enabled the shared lib support. Removing this symlink makes it possible to install tune2fs and findfs package. Signed-off-by: Martin Schiller --- package/utils/e2fsprogs/Makefile | 1 - 1 file changed, 1 deletion(-) diff --git a/package/utils/e2fsprogs/Makefile b/package/utils/e2fsprogs/Makefile index 42c29715294..2657077a16b 100644 --- a/package/utils/e2fsprogs/Makefile +++ b/package/utils/e2fsprogs/Makefile @@ -267,7 +267,6 @@ endef define Package/tune2fs/install $(INSTALL_DIR) $(1)/usr/sbin $(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/tune2fs $(1)/usr/sbin/ - $(LN) tune2fs $(1)/usr/sbin/findfs endef define Package/resize2fs/install From c170fc78ba6e4477cc06b2b77e11747da862dcf0 Mon Sep 17 00:00:00 2001 From: Christian Svensson Date: Sat, 8 Jul 2023 00:23:28 +0200 Subject: [PATCH 41/53] kernel: remove CRYPTO_BLAKE2S from all >=5.15 This option was removed from upstream kernel back in 2022. See commits: 2d16803c562ecc644803d42ba98a8e0aef9c014e (>=6.0) 3dd33a09f5dc12ccb0902923c4c784eb0f8c7554 (>=5.15.61 backport) Signed-off-by: Christian Svensson --- target/linux/armsr/armv8/config-6.1 | 1 - target/linux/ath79/config-5.15 | 1 - target/linux/bcm63xx/config-5.15 | 1 - target/linux/generic/config-5.15 | 1 - target/linux/generic/config-6.1 | 1 - target/linux/lantiq/config-5.15 | 1 - target/linux/malta/config-5.15 | 1 - target/linux/malta/config-6.1 | 1 - target/linux/mediatek/mt7622/config-5.15 | 1 - target/linux/octeon/config-5.15 | 1 - target/linux/sunxi/cortexa53/config-5.15 | 1 - target/linux/uml/config-5.15 | 1 - target/linux/x86/generic/config-5.15 | 1 - target/linux/x86/geode/config-5.15 | 1 - target/linux/x86/legacy/config-5.15 | 1 - 15 files changed, 15 deletions(-) diff --git a/target/linux/armsr/armv8/config-6.1 b/target/linux/armsr/armv8/config-6.1 index f6bcce191f1..5bdda2d5175 100644 --- a/target/linux/armsr/armv8/config-6.1 +++ b/target/linux/armsr/armv8/config-6.1 @@ -114,7 +114,6 @@ CONFIG_CRYPTO_AES_ARM64_CE_BLK=y CONFIG_CRYPTO_AES_ARM64_CE_CCM=y CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y -CONFIG_CRYPTO_BLAKE2S=y CONFIG_CRYPTO_CHACHA20=y CONFIG_CRYPTO_CHACHA20_NEON=y CONFIG_CRYPTO_CRYPTD=y diff --git a/target/linux/ath79/config-5.15 b/target/linux/ath79/config-5.15 index ce987c55390..21fd091a2e6 100644 --- a/target/linux/ath79/config-5.15 +++ b/target/linux/ath79/config-5.15 @@ -34,7 +34,6 @@ CONFIG_CPU_R4K_CACHE_TLB=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_HIGHMEM=y CONFIG_CPU_SUPPORTS_MSA=y -CONFIG_CRYPTO_BLAKE2S=y CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 CONFIG_CRYPTO_RNG2=y diff --git a/target/linux/bcm63xx/config-5.15 b/target/linux/bcm63xx/config-5.15 index c946302d31e..f19d45362ef 100644 --- a/target/linux/bcm63xx/config-5.15 +++ b/target/linux/bcm63xx/config-5.15 @@ -57,7 +57,6 @@ CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_CPUFREQ=y CONFIG_CPU_SUPPORTS_HIGHMEM=y CONFIG_CRASH_CORE=y -CONFIG_CRYPTO_BLAKE2S=y CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 CONFIG_CRYPTO_RNG2=y diff --git a/target/linux/generic/config-5.15 b/target/linux/generic/config-5.15 index a2770f2d5f6..d7e4742d633 100644 --- a/target/linux/generic/config-5.15 +++ b/target/linux/generic/config-5.15 @@ -1087,7 +1087,6 @@ CONFIG_CRYPTO_ALGAPI2=y # CONFIG_CRYPTO_AUTHENC is not set # CONFIG_CRYPTO_BLAKE2B is not set # CONFIG_CRYPTO_BLAKE2B_NEON is not set -# CONFIG_CRYPTO_BLAKE2S is not set # CONFIG_CRYPTO_BLAKE2S_ARM is not set # CONFIG_CRYPTO_BLAKE2S_X86 is not set # CONFIG_CRYPTO_BLOWFISH is not set diff --git a/target/linux/generic/config-6.1 b/target/linux/generic/config-6.1 index 6a3ed63f56a..8ba82f42227 100644 --- a/target/linux/generic/config-6.1 +++ b/target/linux/generic/config-6.1 @@ -1145,7 +1145,6 @@ CONFIG_CRYPTO_ALGAPI2=y # CONFIG_CRYPTO_AUTHENC is not set # CONFIG_CRYPTO_BLAKE2B is not set # CONFIG_CRYPTO_BLAKE2B_NEON is not set -# CONFIG_CRYPTO_BLAKE2S is not set # CONFIG_CRYPTO_BLAKE2S_ARM is not set # CONFIG_CRYPTO_BLAKE2S_X86 is not set # CONFIG_CRYPTO_BLOWFISH is not set diff --git a/target/linux/lantiq/config-5.15 b/target/linux/lantiq/config-5.15 index c37a543e1e7..90d48fff044 100644 --- a/target/linux/lantiq/config-5.15 +++ b/target/linux/lantiq/config-5.15 @@ -37,7 +37,6 @@ CONFIG_CPU_R4K_CACHE_TLB=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_HIGHMEM=y CONFIG_CPU_SUPPORTS_MSA=y -CONFIG_CRYPTO_BLAKE2S=y CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 CONFIG_CRYPTO_RNG2=y diff --git a/target/linux/malta/config-5.15 b/target/linux/malta/config-5.15 index f1ef5e8dfb0..bbedaf56336 100644 --- a/target/linux/malta/config-5.15 +++ b/target/linux/malta/config-5.15 @@ -57,7 +57,6 @@ CONFIG_CPU_RMAP=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_HIGHMEM=y CONFIG_CRC16=y -CONFIG_CRYPTO_BLAKE2S=y CONFIG_CRYPTO_CRC32=y CONFIG_CRYPTO_CRC32C=y CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y diff --git a/target/linux/malta/config-6.1 b/target/linux/malta/config-6.1 index 8ab648069d2..9ce439ee384 100644 --- a/target/linux/malta/config-6.1 +++ b/target/linux/malta/config-6.1 @@ -58,7 +58,6 @@ CONFIG_CPU_RMAP=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_HIGHMEM=y CONFIG_CRC16=y -CONFIG_CRYPTO_BLAKE2S=y CONFIG_CRYPTO_CRC32=y CONFIG_CRYPTO_CRC32C=y CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y diff --git a/target/linux/mediatek/mt7622/config-5.15 b/target/linux/mediatek/mt7622/config-5.15 index 30a5ff948fa..643eaa45b6d 100644 --- a/target/linux/mediatek/mt7622/config-5.15 +++ b/target/linux/mediatek/mt7622/config-5.15 @@ -111,7 +111,6 @@ CONFIG_CRYPTO_AES_ARM64=y CONFIG_CRYPTO_AES_ARM64_CE=y CONFIG_CRYPTO_AES_ARM64_CE_BLK=y CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_BLAKE2S=y CONFIG_CRYPTO_CMAC=y CONFIG_CRYPTO_CRC32=y CONFIG_CRYPTO_CRC32C=y diff --git a/target/linux/octeon/config-5.15 b/target/linux/octeon/config-5.15 index 5882c7dd757..cf64ae34f93 100644 --- a/target/linux/octeon/config-5.15 +++ b/target/linux/octeon/config-5.15 @@ -44,7 +44,6 @@ CONFIG_CPU_SUPPORTS_HIGHMEM=y CONFIG_CPU_SUPPORTS_HUGEPAGES=y CONFIG_CRAMFS=y CONFIG_CRC16=y -CONFIG_CRYPTO_BLAKE2S=y CONFIG_CRYPTO_CRC32=y CONFIG_CRYPTO_CRC32C=y CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y diff --git a/target/linux/sunxi/cortexa53/config-5.15 b/target/linux/sunxi/cortexa53/config-5.15 index 85ace5d9288..93d5b2b21c9 100644 --- a/target/linux/sunxi/cortexa53/config-5.15 +++ b/target/linux/sunxi/cortexa53/config-5.15 @@ -28,7 +28,6 @@ CONFIG_CRYPTO_AES_ARM64=y CONFIG_CRYPTO_AES_ARM64_CE=y CONFIG_CRYPTO_AES_ARM64_CE_BLK=y CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_BLAKE2S=y CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y CONFIG_CRYPTO_CRYPTD=y CONFIG_CRYPTO_GHASH_ARM64_CE=y diff --git a/target/linux/uml/config-5.15 b/target/linux/uml/config-5.15 index 549a31e1c62..ac13cda7038 100644 --- a/target/linux/uml/config-5.15 +++ b/target/linux/uml/config-5.15 @@ -20,7 +20,6 @@ CONFIG_CPU_SUP_HYGON=y CONFIG_CPU_SUP_INTEL=y CONFIG_CPU_SUP_ZHAOXIN=y CONFIG_CRC16=y -CONFIG_CRYPTO_BLAKE2S=y CONFIG_CRYPTO_CRC32=y CONFIG_CRYPTO_CRC32C=y CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y diff --git a/target/linux/x86/generic/config-5.15 b/target/linux/x86/generic/config-5.15 index 5fda82dd296..29c1e43b22f 100644 --- a/target/linux/x86/generic/config-5.15 +++ b/target/linux/x86/generic/config-5.15 @@ -61,7 +61,6 @@ CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y # CONFIG_CPU_IDLE_GOV_HALTPOLL is not set CONFIG_CPU_IDLE_GOV_MENU=y CONFIG_CPU_RMAP=y -CONFIG_CRYPTO_BLAKE2S=y CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y # CONFIG_CS89x0_ISA is not set # CONFIG_DEBUG_HOTPLUG_CPU0 is not set diff --git a/target/linux/x86/geode/config-5.15 b/target/linux/x86/geode/config-5.15 index 2ede23ea5ec..0104b1e7b37 100644 --- a/target/linux/x86/geode/config-5.15 +++ b/target/linux/x86/geode/config-5.15 @@ -37,7 +37,6 @@ CONFIG_ALIX=y # CONFIG_AMD_PMC is not set CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y # CONFIG_ATA_PIIX is not set -CONFIG_CRYPTO_BLAKE2S=y CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y CONFIG_CS5535_CLOCK_EVENT_SRC=y CONFIG_CS5535_MFGPT=y diff --git a/target/linux/x86/legacy/config-5.15 b/target/linux/x86/legacy/config-5.15 index a75ce40ab46..d6802d6c996 100644 --- a/target/linux/x86/legacy/config-5.15 +++ b/target/linux/x86/legacy/config-5.15 @@ -45,7 +45,6 @@ CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BLK_DEV_SR=y CONFIG_CDROM=y CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CRYPTO_BLAKE2S=y CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y # CONFIG_CS89x0_ISA is not set CONFIG_DMA_ACPI=y From 3a2e7c30d3e6a187ba1df740cdb24c8ad84dfe48 Mon Sep 17 00:00:00 2001 From: Adam Bailey Date: Mon, 3 Jul 2023 20:16:14 -0500 Subject: [PATCH 42/53] lua: fix integer overflow in LNUM patch Safely detect integer overflow in try_addint() and try_subint(). Old code relied on undefined behavior, and recent versions of GCC on x86 optimized away the if-statements. This caused integer overflow in Lua code instead of falling back to floating-point numbers. Signed-off-by: Adam Bailey --- .../010-lua-5.1.3-lnum-full-260308.patch | 16 ++++++++-------- .../patches/010-lua-5.1.3-lnum-full-260308.patch | 16 ++++++++-------- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/package/utils/lua/patches-host/010-lua-5.1.3-lnum-full-260308.patch b/package/utils/lua/patches-host/010-lua-5.1.3-lnum-full-260308.patch index 4530edd1812..fd398c28d11 100644 --- a/package/utils/lua/patches-host/010-lua-5.1.3-lnum-full-260308.patch +++ b/package/utils/lua/patches-host/010-lua-5.1.3-lnum-full-260308.patch @@ -1600,18 +1600,18 @@ + * (and doing them). + */ +int try_addint( lua_Integer *r, lua_Integer ib, lua_Integer ic ) { -+ lua_Integer v= ib+ic; /* may overflow */ -+ if (ib>0 && ic>0) { if (v < 0) return 0; /*overflow, use floats*/ } -+ else if (ib<0 && ic<0) { if (v >= 0) return 0; } -+ *r= v; ++ /* Signed int overflow is undefined behavior, so catch it without causing it. */ ++ if (ic>0) { if (ib > LUA_INTEGER_MAX - ic) return 0; /*overflow, use floats*/ } ++ else { if (ib < LUA_INTEGER_MIN - ic) return 0; } ++ *r = ib + ic; + return 1; +} + +int try_subint( lua_Integer *r, lua_Integer ib, lua_Integer ic ) { -+ lua_Integer v= ib-ic; /* may overflow */ -+ if (ib>=0 && ic<0) { if (v < 0) return 0; /*overflow, use floats*/ } -+ else if (ib<0 && ic>0) { if (v >= 0) return 0; } -+ *r= v; ++ /* Signed int overflow is undefined behavior, so catch it without causing it. */ ++ if (ic>0) { if (ib < LUA_INTEGER_MIN + ic) return 0; /*overflow, use floats*/ } ++ else { if (ib > LUA_INTEGER_MAX + ic) return 0; } ++ *r = ib - ic; + return 1; +} + diff --git a/package/utils/lua/patches/010-lua-5.1.3-lnum-full-260308.patch b/package/utils/lua/patches/010-lua-5.1.3-lnum-full-260308.patch index ac0722c7073..58cc894e1c8 100644 --- a/package/utils/lua/patches/010-lua-5.1.3-lnum-full-260308.patch +++ b/package/utils/lua/patches/010-lua-5.1.3-lnum-full-260308.patch @@ -1589,18 +1589,18 @@ + * (and doing them). + */ +int try_addint( lua_Integer *r, lua_Integer ib, lua_Integer ic ) { -+ lua_Integer v= ib+ic; /* may overflow */ -+ if (ib>0 && ic>0) { if (v < 0) return 0; /*overflow, use floats*/ } -+ else if (ib<0 && ic<0) { if (v >= 0) return 0; } -+ *r= v; ++ /* Signed int overflow is undefined behavior, so catch it without causing it. */ ++ if (ic>0) { if (ib > LUA_INTEGER_MAX - ic) return 0; /*overflow, use floats*/ } ++ else { if (ib < LUA_INTEGER_MIN - ic) return 0; } ++ *r = ib + ic; + return 1; +} + +int try_subint( lua_Integer *r, lua_Integer ib, lua_Integer ic ) { -+ lua_Integer v= ib-ic; /* may overflow */ -+ if (ib>=0 && ic<0) { if (v < 0) return 0; /*overflow, use floats*/ } -+ else if (ib<0 && ic>0) { if (v >= 0) return 0; } -+ *r= v; ++ /* Signed int overflow is undefined behavior, so catch it without causing it. */ ++ if (ic>0) { if (ib < LUA_INTEGER_MIN + ic) return 0; /*overflow, use floats*/ } ++ else { if (ib > LUA_INTEGER_MAX + ic) return 0; } ++ *r = ib - ic; + return 1; +} + From 1f1e0b1144ebaa4ba8b948a12d989a0a6fc9b76f Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sat, 8 Jul 2023 16:27:25 +0100 Subject: [PATCH 43/53] mediatek: dts: mt7988a: wire-up mediatek,pio for PHY LEDs The PHY driver needs to read a register containing the values of the bootstrap pins (which happen to be the PHY LEDs) to determine the LED polarities. Allow regmap access to first pinctrl bank by adding the 'syscon' compatible, and reference the pinctrl in the MDIO bus where the PHY driver will look for it. Signed-off-by: Daniel Golle --- .../arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts | 1 + .../files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 +- .../arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts | 1 + .../files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 +- 4 files changed, 4 insertions(+), 2 deletions(-) diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts index 98dbf8d6913..e204dc4f166 100644 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts @@ -156,6 +156,7 @@ mdio { #address-cells = <1>; #size-cells = <0>; + mediatek,pio = <&pio>; gsw_phy0: ethernet-phy@0 { compatible = "ethernet-phy-id03a2.9481"; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 13ad39500d1..17de885629e 100644 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -215,7 +215,7 @@ }; pio: pinctrl@1001f000 { - compatible = "mediatek,mt7988-pinctrl"; + compatible = "mediatek,mt7988-pinctrl", "syscon"; reg = <0 0x1001f000 0 0x1000>, <0 0x11c10000 0 0x1000>, <0 0x11d00000 0 0x1000>, diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts index 98dbf8d6913..e204dc4f166 100644 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts @@ -156,6 +156,7 @@ mdio { #address-cells = <1>; #size-cells = <0>; + mediatek,pio = <&pio>; gsw_phy0: ethernet-phy@0 { compatible = "ethernet-phy-id03a2.9481"; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 13ad39500d1..17de885629e 100644 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -215,7 +215,7 @@ }; pio: pinctrl@1001f000 { - compatible = "mediatek,mt7988-pinctrl"; + compatible = "mediatek,mt7988-pinctrl", "syscon"; reg = <0 0x1001f000 0 0x1000>, <0 0x11c10000 0 0x1000>, <0 0x11d00000 0 0x1000>, From 094c37708ace9040e294c5aa7be34bc9e7a8dcc1 Mon Sep 17 00:00:00 2001 From: Mathew McBride Date: Tue, 27 Jun 2023 06:37:28 +0000 Subject: [PATCH 44/53] layerscape: base-files: remove redundant RAMFS_COPY_* additions All the tools (e.g fw_setenv, ubiupdatevol) and config (fw_env.config) needed for sysupgrade are already included in /lib/upgrade/stage2 Signed-off-by: Mathew McBride --- target/linux/layerscape/base-files/lib/upgrade/platform.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/linux/layerscape/base-files/lib/upgrade/platform.sh b/target/linux/layerscape/base-files/lib/upgrade/platform.sh index 0b5d14b579c..8ad9df4a13d 100644 --- a/target/linux/layerscape/base-files/lib/upgrade/platform.sh +++ b/target/linux/layerscape/base-files/lib/upgrade/platform.sh @@ -3,8 +3,8 @@ # Copyright 2020 NXP # -RAMFS_COPY_BIN="/usr/sbin/fw_printenv /usr/sbin/fw_setenv /usr/sbin/ubinfo /bin/echo" -RAMFS_COPY_DATA="/etc/fw_env.config /var/lock/fw_printenv.lock" +RAMFS_COPY_BIN="" +RAMFS_COPY_DATA="" REQUIRE_IMAGE_METADATA=1 From 9fac59009657068d5a58b3d0255d4ca1507dd457 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sat, 8 Jul 2023 17:21:27 +0100 Subject: [PATCH 45/53] mediatek: use backported Ethernet PHY driver also for 5.15 Backport in-SoC Gigabit Ethernet PHY driver instead of carrying the driver in files-5.15. Signed-off-by: Daniel Golle --- .../drivers/net/phy/mediatek-ge-soc.c | 1263 ----------------- ...er-for-MediaTek-SoC-built-in-GE-PHYs.patch | 82 -- ...er-for-MediaTek-SoC-built-in-GE-PHYs.patch | 1204 ++++++++++++++++ ...-ge-soc-initialize-MT7988-PHY-LEDs-d.patch | 213 +++ 4 files changed, 1417 insertions(+), 1345 deletions(-) delete mode 100644 target/linux/mediatek/files-5.15/drivers/net/phy/mediatek-ge-soc.c delete mode 100644 target/linux/mediatek/patches-5.15/730-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch create mode 100644 target/linux/mediatek/patches-5.15/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch create mode 100644 target/linux/mediatek/patches-5.15/731-net-phy-mediatek-ge-soc-initialize-MT7988-PHY-LEDs-d.patch diff --git a/target/linux/mediatek/files-5.15/drivers/net/phy/mediatek-ge-soc.c b/target/linux/mediatek/files-5.15/drivers/net/phy/mediatek-ge-soc.c deleted file mode 100644 index e48502ac3fd..00000000000 --- a/target/linux/mediatek/files-5.15/drivers/net/phy/mediatek-ge-soc.c +++ /dev/null @@ -1,1263 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -#include -#include -#include -#include -#include -#include -#include - -#define MTK_GPHY_ID_MT7981 0x03a29461 -#define MTK_GPHY_ID_MT7988 0x03a29481 - -#define MTK_EXT_PAGE_ACCESS 0x1f -#define MTK_PHY_PAGE_STANDARD 0x0000 -#define MTK_PHY_PAGE_EXTENDED_3 0x0003 - -#define MTK_PHY_LPI_REG_14 0x14 -#define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0) - -#define MTK_PHY_LPI_REG_1c 0x1c -#define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8) - -#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 -#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 - -#define ANALOG_INTERNAL_OPERATION_MAX_US 20 -#define TXRESERVE_MIN 0 -#define TXRESERVE_MAX 7 - -#define MTK_PHY_ANARG_RG 0x10 -#define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8) - -/* Registers on MDIO_MMD_VEND1 */ -#define MTK_PHY_TXVLD_DA_RG 0x12 -#define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10) -#define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0) - -#define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16 -#define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10) -#define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0) - -#define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17 -#define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8) -#define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0) - -#define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18 -#define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8) -#define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0) - -#define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19 -#define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8) -#define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0) - -#define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20 -#define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8) -#define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0) - -#define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21 -#define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8) -#define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0) - -#define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22 -#define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8) -#define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0) - -#define MTK_PHY_RXADC_CTRL_RG7 0xc6 -#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8) - -#define MTK_PHY_RXADC_CTRL_RG9 0xc8 -#define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12) -#define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8) -#define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4) -#define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0) - -#define MTK_PHY_LDO_OUTPUT_V 0xd7 - -#define MTK_PHY_RG_ANA_CAL_RG0 0xdb -#define MTK_PHY_RG_CAL_CKINV BIT(12) -#define MTK_PHY_RG_ANA_CALEN BIT(8) -#define MTK_PHY_RG_ZCALEN_A BIT(0) - -#define MTK_PHY_RG_ANA_CAL_RG1 0xdc -#define MTK_PHY_RG_ZCALEN_B BIT(12) -#define MTK_PHY_RG_ZCALEN_C BIT(8) -#define MTK_PHY_RG_ZCALEN_D BIT(4) -#define MTK_PHY_RG_TXVOS_CALEN BIT(0) - -#define MTK_PHY_RG_ANA_CAL_RG5 0xe0 -#define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8) - -#define MTK_PHY_RG_TX_FILTER 0xfe - -#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120 -#define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8) -#define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0) - -#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122 -#define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0) - -#define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144 -#define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5) - -#define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172 -#define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8) -#define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0) - -#define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173 -#define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8) -#define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0) - -#define MTK_PHY_RG_AD_CAL_COMP 0x17a -#define MTK_PHY_AD_CAL_COMP_OUT_SHIFT (8) - -#define MTK_PHY_RG_AD_CAL_CLK 0x17b -#define MTK_PHY_DA_CAL_CLK BIT(0) - -#define MTK_PHY_RG_AD_CALIN 0x17c -#define MTK_PHY_DA_CALIN_FLAG BIT(0) - -#define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d -#define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0) - -#define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e -#define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0) - -#define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f -#define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0) - -#define MTK_PHY_RG_DASN_DAC_IN0_D 0x180 -#define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0) - -#define MTK_PHY_RG_DASN_DAC_IN1_A 0x181 -#define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0) - -#define MTK_PHY_RG_DASN_DAC_IN1_B 0x182 -#define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0) - -#define MTK_PHY_RG_DASN_DAC_IN1_C 0x183 -#define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0) - -#define MTK_PHY_RG_DASN_DAC_IN1_D 0x184 -#define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0) - -#define MTK_PHY_RG_DEV1E_REG19b 0x19b -#define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8) - -#define MTK_PHY_RG_LP_IIR2_K1_L 0x22a -#define MTK_PHY_RG_LP_IIR2_K1_U 0x22b -#define MTK_PHY_RG_LP_IIR2_K2_L 0x22c -#define MTK_PHY_RG_LP_IIR2_K2_U 0x22d -#define MTK_PHY_RG_LP_IIR2_K3_L 0x22e -#define MTK_PHY_RG_LP_IIR2_K3_U 0x22f -#define MTK_PHY_RG_LP_IIR2_K4_L 0x230 -#define MTK_PHY_RG_LP_IIR2_K4_U 0x231 -#define MTK_PHY_RG_LP_IIR2_K5_L 0x232 -#define MTK_PHY_RG_LP_IIR2_K5_U 0x233 - -#define MTK_PHY_RG_DEV1E_REG234 0x234 -#define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0) -#define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4) -#define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12) - -#define MTK_PHY_RG_LPF_CNT_VAL 0x235 - -#define MTK_PHY_RG_DEV1E_REG238 0x238 -#define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0) -#define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12) - -#define MTK_PHY_RG_DEV1E_REG239 0x239 -#define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0) -#define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12) - -#define MTK_PHY_RG_DEV1E_REG27C 0x27c -#define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8) -#define MTK_PHY_RG_DEV1E_REG27D 0x27d -#define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0) - -#define MTK_PHY_RG_DEV1E_REG2C7 0x2c7 -#define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0) -#define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8) - -#define MTK_PHY_RG_DEV1E_REG2D1 0x2d1 -#define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0) -#define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8) -#define MTK_PHY_LPI_TR_READY BIT(9) -#define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10) - -#define MTK_PHY_RG_DEV1E_REG323 0x323 -#define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0) -#define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4) - -#define MTK_PHY_RG_DEV1E_REG324 0x324 -#define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0) -#define MTK_PHY_SMI_DET_MAX_EN BIT(8) - -#define MTK_PHY_RG_DEV1E_REG326 0x326 -#define MTK_PHY_LPI_MODE_SD_ON BIT(0) -#define MTK_PHY_RESET_RANDUPD_CNT BIT(1) -#define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2) -#define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4) -#define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5) - -#define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502 -#define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503 - -#define MTK_PHY_DA_TX_R50_PAIR_A 0x53d -#define MTK_PHY_DA_TX_R50_PAIR_B 0x53e -#define MTK_PHY_DA_TX_R50_PAIR_C 0x53f -#define MTK_PHY_DA_TX_R50_PAIR_D 0x540 - -/* Registers on MDIO_MMD_VEND2 */ -#define MTK_PHY_LED0_ON_CTRL 0x24 -#define MTK_PHY_LED0_ON_MASK GENMASK(6, 0) -#define MTK_PHY_LED0_ON_LINK1000 BIT(0) -#define MTK_PHY_LED0_ON_LINK100 BIT(1) -#define MTK_PHY_LED0_ON_LINK10 BIT(2) -#define MTK_PHY_LED0_ON_LINKDOWN BIT(3) -#define MTK_PHY_LED0_ON_FDX BIT(4) /* Full duplex */ -#define MTK_PHY_LED0_ON_HDX BIT(5) /* Half duplex */ -#define MTK_PHY_LED0_FORCE_ON BIT(6) -#define MTK_PHY_LED0_POLARITY BIT(14) -#define MTK_PHY_LED0_ENABLE BIT(15) - -#define MTK_PHY_LED0_BLINK_CTRL 0x25 -#define MTK_PHY_LED0_1000TX BIT(0) -#define MTK_PHY_LED0_1000RX BIT(1) -#define MTK_PHY_LED0_100TX BIT(2) -#define MTK_PHY_LED0_100RX BIT(3) -#define MTK_PHY_LED0_10TX BIT(4) -#define MTK_PHY_LED0_10RX BIT(5) -#define MTK_PHY_LED0_COLLISION BIT(6) -#define MTK_PHY_LED0_RX_CRC_ERR BIT(7) -#define MTK_PHY_LED0_RX_IDLE_ERR BIT(8) -#define MTK_PHY_LED0_FORCE_BLINK BIT(9) - -#define MTK_PHY_LED1_ON_CTRL 0x26 -#define MTK_PHY_LED1_ON_MASK GENMASK(6, 0) -#define MTK_PHY_LED1_ON_LINK1000 BIT(0) -#define MTK_PHY_LED1_ON_LINK100 BIT(1) -#define MTK_PHY_LED1_ON_LINK10 BIT(2) -#define MTK_PHY_LED1_ON_LINKDOWN BIT(3) -#define MTK_PHY_LED1_ON_FDX BIT(4) /* Full duplex */ -#define MTK_PHY_LED1_ON_HDX BIT(5) /* Half duplex */ -#define MTK_PHY_LED1_FORCE_ON BIT(6) -#define MTK_PHY_LED1_POLARITY BIT(14) -#define MTK_PHY_LED1_ENABLE BIT(15) - -#define MTK_PHY_LED1_BLINK_CTRL 0x27 -#define MTK_PHY_LED1_1000TX BIT(0) -#define MTK_PHY_LED1_1000RX BIT(1) -#define MTK_PHY_LED1_100TX BIT(2) -#define MTK_PHY_LED1_100RX BIT(3) -#define MTK_PHY_LED1_10TX BIT(4) -#define MTK_PHY_LED1_10RX BIT(5) -#define MTK_PHY_LED1_COLLISION BIT(6) -#define MTK_PHY_LED1_RX_CRC_ERR BIT(7) -#define MTK_PHY_LED1_RX_IDLE_ERR BIT(8) -#define MTK_PHY_LED1_FORCE_BLINK BIT(9) - -#define MTK_PHY_RG_BG_RASEL 0x115 -#define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0) - -/* These macro privides efuse parsing for internal phy. */ -#define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0)) -#define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0)) -#define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0)) -#define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0)) -#define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0)) - -#define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0)) -#define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0)) -#define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0)) -#define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0)) -#define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0)) - -#define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0)) -#define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0)) - -#define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0)) -#define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0)) - -enum { - NO_PAIR, - PAIR_A, - PAIR_B, - PAIR_C, - PAIR_D, -}; - -enum { - GPHY_PORT0, - GPHY_PORT1, - GPHY_PORT2, - GPHY_PORT3, -}; - -enum calibration_mode { - EFUSE_K, - SW_K -}; - -enum CAL_ITEM { - REXT, - TX_OFFSET, - TX_AMP, - TX_R50, - TX_VCM -}; - -enum CAL_MODE { - EFUSE_M, - SW_M -}; - -struct mtk_socphy_shared_priv { - u32 boottrap; -}; - -static int mtk_socphy_read_page(struct phy_device *phydev) -{ - return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); -} - -static int mtk_socphy_write_page(struct phy_device *phydev, int page) -{ - return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); -} - -/* One calibration cycle consists of: - * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high - * until AD_CAL_COMP is ready to output calibration result. - * 2.Wait until DA_CAL_CLK is available. - * 3.Fetch AD_CAL_COMP_OUT. - */ -static int cal_cycle(struct phy_device *phydev, int devad, - u32 regnum, u16 mask, u16 cal_val) -{ - int reg_val; - int ret; - - phy_modify_mmd(phydev, devad, regnum, - mask, cal_val); - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, - MTK_PHY_DA_CALIN_FLAG); - - ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_AD_CAL_CLK, reg_val, - reg_val & MTK_PHY_DA_CAL_CLK, 500, - ANALOG_INTERNAL_OPERATION_MAX_US, false); - if (ret) { - phydev_err(phydev, "Calibration cycle timeout\n"); - return ret; - } - - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, - MTK_PHY_DA_CALIN_FLAG); - ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >> - MTK_PHY_AD_CAL_COMP_OUT_SHIFT; - phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); - - return ret; -} - -static int rext_fill_result(struct phy_device *phydev, u16 *buf) -{ - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, - MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8); - phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL, - MTK_PHY_RG_BG_RASEL_MASK, buf[1]); - - return 0; -} - -static int rext_cal_efuse(struct phy_device *phydev, u32 *buf) -{ - u16 rext_cal_val[2]; - - rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]); - rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]); - rext_fill_result(phydev, rext_cal_val); - - return 0; -} - -static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf) -{ - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, - MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, - MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, - MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, - MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]); - - return 0; -} - -static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf) -{ - u16 tx_offset_cal_val[4]; - - tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]); - tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]); - tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]); - tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]); - - tx_offset_fill_result(phydev, tx_offset_cal_val); - - return 0; -} - -static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf) -{ - int i; - int bias[16] = {}; - const int vals_9461[16] = { 7, 1, 4, 7, - 7, 1, 4, 7, - 7, 1, 4, 7, - 7, 1, 4, 7 }; - const int vals_9481[16] = { 10, 6, 6, 10, - 10, 6, 6, 10, - 10, 6, 6, 10, - 10, 6, 6, 10 }; - switch (phydev->drv->phy_id) { - case MTK_GPHY_ID_MT7981: - /* We add some calibration to efuse values - * due to board level influence. - * GBE: +7, TBT: +1, HBT: +4, TST: +7 - */ - memcpy(bias, (const void *)vals_9461, sizeof(bias)); - break; - case MTK_GPHY_ID_MT7988: - memcpy(bias, (const void *)vals_9481, sizeof(bias)); - break; - } - - /* Prevent overflow */ - for (i = 0; i < 12; i++) { - if (buf[i >> 2] + bias[i] > 63) { - buf[i >> 2] = 63; - bias[i] = 0; - } - } - - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, - MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, - MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, - MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, - MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]); - - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, - MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, (buf[1] + bias[4]) << 8); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, - MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, buf[1] + bias[5]); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, - MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, - MTK_PHY_DA_TX_I2MPB_B_TST_MASK, buf[1] + bias[7]); - - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, - MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, (buf[2] + bias[8]) << 8); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, - MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, buf[2] + bias[9]); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, - MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, (buf[2] + bias[10]) << 8); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, - MTK_PHY_DA_TX_I2MPB_C_TST_MASK, buf[2] + bias[11]); - - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, - MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, - MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, buf[3] + bias[13]); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, - MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, (buf[3] + bias[14]) << 8); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, - MTK_PHY_DA_TX_I2MPB_D_TST_MASK, buf[3] + bias[15]); - - return 0; -} - -static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf) -{ - u16 tx_amp_cal_val[4]; - - tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]); - tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]); - tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]); - tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]); - tx_amp_fill_result(phydev, tx_amp_cal_val); - - return 0; -} - -static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val, - u8 txg_calen_x) -{ - int bias = 0; - u16 reg, val; - - if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988) - bias = -2; - - val = clamp_val(bias + tx_r50_cal_val, 0, 63); - - switch (txg_calen_x) { - case PAIR_A: - reg = MTK_PHY_DA_TX_R50_PAIR_A; - break; - case PAIR_B: - reg = MTK_PHY_DA_TX_R50_PAIR_B; - break; - case PAIR_C: - reg = MTK_PHY_DA_TX_R50_PAIR_C; - break; - case PAIR_D: - reg = MTK_PHY_DA_TX_R50_PAIR_D; - break; - default: - return -EINVAL; - } - - phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8); - - return 0; -} - -static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf, - u8 txg_calen_x) -{ - u16 tx_r50_cal_val; - - switch (txg_calen_x) { - case PAIR_A: - tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]); - break; - case PAIR_B: - tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]); - break; - case PAIR_C: - tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]); - break; - case PAIR_D: - tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]); - break; - default: - return -EINVAL; - } - tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x); - - return 0; -} - -static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x) -{ - u8 lower_idx, upper_idx, txreserve_val; - u8 lower_ret, upper_ret; - int ret; - - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, - MTK_PHY_RG_ANA_CALEN); - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, - MTK_PHY_RG_CAL_CKINV); - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, - MTK_PHY_RG_TXVOS_CALEN); - - switch (rg_txreserve_x) { - case PAIR_A: - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_DASN_DAC_IN0_A, - MTK_PHY_DASN_DAC_IN0_A_MASK); - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_DASN_DAC_IN1_A, - MTK_PHY_DASN_DAC_IN1_A_MASK); - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_ANA_CAL_RG0, - MTK_PHY_RG_ZCALEN_A); - break; - case PAIR_B: - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_DASN_DAC_IN0_B, - MTK_PHY_DASN_DAC_IN0_B_MASK); - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_DASN_DAC_IN1_B, - MTK_PHY_DASN_DAC_IN1_B_MASK); - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_ANA_CAL_RG1, - MTK_PHY_RG_ZCALEN_B); - break; - case PAIR_C: - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_DASN_DAC_IN0_C, - MTK_PHY_DASN_DAC_IN0_C_MASK); - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_DASN_DAC_IN1_C, - MTK_PHY_DASN_DAC_IN1_C_MASK); - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_ANA_CAL_RG1, - MTK_PHY_RG_ZCALEN_C); - break; - case PAIR_D: - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_DASN_DAC_IN0_D, - MTK_PHY_DASN_DAC_IN0_D_MASK); - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_DASN_DAC_IN1_D, - MTK_PHY_DASN_DAC_IN1_D_MASK); - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_ANA_CAL_RG1, - MTK_PHY_RG_ZCALEN_D); - break; - default: - ret = -EINVAL; - goto restore; - } - - lower_idx = TXRESERVE_MIN; - upper_idx = TXRESERVE_MAX; - - phydev_dbg(phydev, "Start TX-VCM SW cal.\n"); - while ((upper_idx - lower_idx) > 1) { - txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2); - ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, - MTK_PHY_DA_RX_PSBN_TBT_MASK | - MTK_PHY_DA_RX_PSBN_HBT_MASK | - MTK_PHY_DA_RX_PSBN_GBE_MASK | - MTK_PHY_DA_RX_PSBN_LP_MASK, - txreserve_val << 12 | txreserve_val << 8 | - txreserve_val << 4 | txreserve_val); - if (ret == 1) { - upper_idx = txreserve_val; - upper_ret = ret; - } else if (ret == 0) { - lower_idx = txreserve_val; - lower_ret = ret; - } else { - goto restore; - } - } - - if (lower_idx == TXRESERVE_MIN) { - lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1, - MTK_PHY_RXADC_CTRL_RG9, - MTK_PHY_DA_RX_PSBN_TBT_MASK | - MTK_PHY_DA_RX_PSBN_HBT_MASK | - MTK_PHY_DA_RX_PSBN_GBE_MASK | - MTK_PHY_DA_RX_PSBN_LP_MASK, - lower_idx << 12 | lower_idx << 8 | - lower_idx << 4 | lower_idx); - ret = lower_ret; - } else if (upper_idx == TXRESERVE_MAX) { - upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1, - MTK_PHY_RXADC_CTRL_RG9, - MTK_PHY_DA_RX_PSBN_TBT_MASK | - MTK_PHY_DA_RX_PSBN_HBT_MASK | - MTK_PHY_DA_RX_PSBN_GBE_MASK | - MTK_PHY_DA_RX_PSBN_LP_MASK, - upper_idx << 12 | upper_idx << 8 | - upper_idx << 4 | upper_idx); - ret = upper_ret; - } - if (ret < 0) - goto restore; - - /* We calibrate TX-VCM in different logic. Check upper index and then - * lower index. If this calibration is valid, apply lower index's result. - */ - ret = upper_ret - lower_ret; - if (ret == 1) { - ret = 0; - /* Make sure we use upper_idx in our calibration system */ - cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, - MTK_PHY_DA_RX_PSBN_TBT_MASK | - MTK_PHY_DA_RX_PSBN_HBT_MASK | - MTK_PHY_DA_RX_PSBN_GBE_MASK | - MTK_PHY_DA_RX_PSBN_LP_MASK, - upper_idx << 12 | upper_idx << 8 | - upper_idx << 4 | upper_idx); - phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx); - } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 && - lower_ret == 1) { - ret = 0; - cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, - MTK_PHY_DA_RX_PSBN_TBT_MASK | - MTK_PHY_DA_RX_PSBN_HBT_MASK | - MTK_PHY_DA_RX_PSBN_GBE_MASK | - MTK_PHY_DA_RX_PSBN_LP_MASK, - lower_idx << 12 | lower_idx << 8 | - lower_idx << 4 | lower_idx); - phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n", - lower_idx); - } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 && - lower_ret == 0) { - ret = 0; - phydev_warn(phydev, "TX-VCM SW cal result at high margin 0x%x\n", - upper_idx); - } else { - ret = -EINVAL; - } - -restore: - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, - MTK_PHY_RG_ANA_CALEN); - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, - MTK_PHY_RG_TXVOS_CALEN); - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, - MTK_PHY_RG_ZCALEN_A); - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, - MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C | - MTK_PHY_RG_ZCALEN_D); - - return ret; -} - -static void mt798x_phy_common_finetune(struct phy_device *phydev) -{ - phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); - /* EnabRandUpdTrig = 1 */ - __phy_write(phydev, 0x11, 0x2f00); - __phy_write(phydev, 0x12, 0xe); - __phy_write(phydev, 0x10, 0x8fb0); - - /* NormMseLoThresh = 85 */ - __phy_write(phydev, 0x11, 0x55a0); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x83aa); - - /* TrFreeze = 0 */ - __phy_write(phydev, 0x11, 0x0); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x9686); - - /* SSTrKp1000Slv = 5 */ - __phy_write(phydev, 0x11, 0xbaef); - __phy_write(phydev, 0x12, 0x2e); - __phy_write(phydev, 0x10, 0x968c); - - /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2, - * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2 - */ - __phy_write(phydev, 0x11, 0xd10a); - __phy_write(phydev, 0x12, 0x34); - __phy_write(phydev, 0x10, 0x8f82); - - /* VcoSlicerThreshBitsHigh */ - __phy_write(phydev, 0x11, 0x5555); - __phy_write(phydev, 0x12, 0x55); - __phy_write(phydev, 0x10, 0x8ec0); - phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); - - /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/ - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, - MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK, - BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); - - /* rg_tr_lpf_cnt_val = 512 */ - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200); - - /* IIR2 related */ - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82); - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0); - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103); - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0); - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82); - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0); - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177); - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3); - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82); - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe); - - /* FFE peaking */ - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C, - MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8); - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D, - MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e); - - /* Disable LDO pump */ - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0); - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0); - /* Adjust LDO output voltage */ - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222); -} - -static void mt7981_phy_finetune(struct phy_device *phydev) -{ - u16 val[8] = { 0x01ce, 0x01c1, - 0x020f, 0x0202, - 0x03d0, 0x03c0, - 0x0013, 0x0005 }; - int i, k; - - /* 100M eye finetune: - * Keep middle level of TX MLT3 shapper as default. - * Only change TX MLT3 overshoot level here. - */ - for (k = 0, i = 1; i < 12; i++) { - if (i % 3 == 0) - continue; - phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]); - } - - phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); - /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */ - __phy_write(phydev, 0x11, 0xc71); - __phy_write(phydev, 0x12, 0xc); - __phy_write(phydev, 0x10, 0x8fae); - - /* ResetSyncOffset = 6 */ - __phy_write(phydev, 0x11, 0x600); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x8fc0); - - /* VgaDecRate = 1 */ - __phy_write(phydev, 0x11, 0x4c2a); - __phy_write(phydev, 0x12, 0x3e); - __phy_write(phydev, 0x10, 0x8fa4); - - /* FfeUpdGainForce = 4 */ - __phy_write(phydev, 0x11, 0x240); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x9680); - - phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); -} - -static void mt7988_phy_finetune(struct phy_device *phydev) -{ - u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182, - 0x020d, 0x0206, 0x0384, 0x03d0, - 0x03c6, 0x030a, 0x0011, 0x0005 }; - int i; - - /* Set default MLT3 shaper first */ - for (i = 0; i < 12; i++) - phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]); - - /* TCT finetune */ - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5); - - /* Disable TX power saving */ - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, - MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8); - - phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); - - /* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */ - __phy_write(phydev, 0x11, 0x671); - __phy_write(phydev, 0x12, 0xc); - __phy_write(phydev, 0x10, 0x8fae); - - /* ResetSyncOffset = 5 */ - __phy_write(phydev, 0x11, 0x500); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x8fc0); - - /* VgaDecRate is 1 at default on mt7988 */ - - phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); - - phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30); - /* TxClkOffset = 2 */ - __phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK, - FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2)); - phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); -} - -static void mt798x_phy_eee(struct phy_device *phydev) -{ - phy_modify_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120, - MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK | - MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, - FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) | - FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14)); - - phy_modify_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, - MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, - FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, - 0xff)); - - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_TESTMUX_ADC_CTRL, - MTK_PHY_RG_TXEN_DIG_MASK); - - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY); - - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN); - - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238, - MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK | - MTK_PHY_LPI_SLV_SEND_TX_EN, - FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120)); - - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239, - MTK_PHY_LPI_SEND_LOC_TIMER_MASK | - MTK_PHY_LPI_TXPCS_LOC_RCV, - FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117)); - - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7, - MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK, - FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) | - FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13)); - - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1, - MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, - FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, - 0x33) | - MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY | - MTK_PHY_LPI_VCO_EEE_STG0_EN); - - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323, - MTK_PHY_EEE_WAKE_MAS_INT_DC | - MTK_PHY_EEE_WAKE_SLV_INT_DC); - - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324, - MTK_PHY_SMI_DETCNT_MAX_MASK, - FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) | - MTK_PHY_SMI_DET_MAX_EN); - - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326, - MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT | - MTK_PHY_TREC_UPDATE_ENAB_CLR | - MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF | - MTK_PHY_TR_READY_SKIP_AFE_WAKEUP); - - phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); - /* Regsigdet_sel_1000 = 0 */ - __phy_write(phydev, 0x11, 0xb); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x9690); - - /* REG_EEE_st2TrKf1000 = 3 */ - __phy_write(phydev, 0x11, 0x114f); - __phy_write(phydev, 0x12, 0x2); - __phy_write(phydev, 0x10, 0x969a); - - /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */ - __phy_write(phydev, 0x11, 0x3028); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x969e); - - /* RegEEE_slv_wake_int_timer_tar = 8 */ - __phy_write(phydev, 0x11, 0x5010); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x96a0); - - /* RegEEE_trfreeze_timer2 = 586 */ - __phy_write(phydev, 0x11, 0x24a); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x96a8); - - /* RegEEE100Stg1_tar = 16 */ - __phy_write(phydev, 0x11, 0x3210); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x96b8); - - /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */ - __phy_write(phydev, 0x11, 0x1463); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x96ca); - - /* DfeTailEnableVgaThresh1000 = 27 */ - __phy_write(phydev, 0x11, 0x36); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x8f80); - phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); - - phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3); - __phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000_MASK, - FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c)); - - __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK, - FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc)); - phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); - - phy_modify_mmd(phydev, MDIO_MMD_VEND1, - MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, - MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, - FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff)); -} - -static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item, - u8 start_pair, u8 end_pair) -{ - u8 pair_n; - int ret; - - for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { - /* TX_OFFSET & TX_AMP have no SW calibration. */ - switch (cal_item) { - case TX_VCM: - ret = tx_vcm_cal_sw(phydev, pair_n); - break; - default: - return -EINVAL; - } - if (ret) - return ret; - } - return 0; -} - -static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item, - u8 start_pair, u8 end_pair, u32 *buf) -{ - u8 pair_n; - int ret; - - for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { - /* TX_VCM has no efuse calibration. */ - switch (cal_item) { - case REXT: - ret = rext_cal_efuse(phydev, buf); - break; - case TX_OFFSET: - ret = tx_offset_cal_efuse(phydev, buf); - break; - case TX_AMP: - ret = tx_amp_cal_efuse(phydev, buf); - break; - case TX_R50: - ret = tx_r50_cal_efuse(phydev, buf, pair_n); - break; - default: - return -EINVAL; - } - if (ret) - return ret; - } - - return 0; -} - -static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item, - enum CAL_MODE cal_mode, u8 start_pair, - u8 end_pair, u32 *buf) -{ - int ret; - - switch (cal_mode) { - case EFUSE_M: - ret = cal_efuse(phydev, cal_item, start_pair, - end_pair, buf); - break; - case SW_M: - ret = cal_sw(phydev, cal_item, start_pair, end_pair); - break; - default: - return -EINVAL; - } - - if (ret) { - phydev_err(phydev, "cal %d failed\n", cal_item); - return -EIO; - } - - return 0; -} - -static int mt798x_phy_calibration(struct phy_device *phydev) -{ - int ret = 0; - u32 *buf; - size_t len; - struct nvmem_cell *cell; - - cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data"); - if (IS_ERR(cell)) { - if (PTR_ERR(cell) == -EPROBE_DEFER) - return PTR_ERR(cell); - return 0; - } - - buf = (u32 *)nvmem_cell_read(cell, &len); - if (IS_ERR(buf)) - return PTR_ERR(buf); - nvmem_cell_put(cell); - - if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) { - phydev_err(phydev, "invalid efuse data\n"); - ret = -EINVAL; - goto out; - } - - ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf); - if (ret) - goto out; - ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf); - if (ret) - goto out; - ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf); - if (ret) - goto out; - ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf); - if (ret) - goto out; - ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf); - if (ret) - goto out; - -out: - kfree(buf); - return ret; -} - -static int mt798x_phy_config_init(struct phy_device *phydev) -{ - switch (phydev->drv->phy_id) { - case MTK_GPHY_ID_MT7981: - mt7981_phy_finetune(phydev); - break; - case MTK_GPHY_ID_MT7988: - mt7988_phy_finetune(phydev); - break; - } - - mt798x_phy_common_finetune(phydev); - mt798x_phy_eee(phydev); - - return mt798x_phy_calibration(phydev); -} - -static int mt7988_phy_setup_led(struct phy_device *phydev) -{ - struct mtk_socphy_shared_priv *priv = phydev->shared->priv; - int port = phydev->mdio.addr; - u32 reg = priv->boottrap; - struct pinctrl *pinctrl; - - phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, - MTK_PHY_LED0_ENABLE | MTK_PHY_LED0_POLARITY | - MTK_PHY_LED0_ON_LINK10 | - MTK_PHY_LED0_ON_LINK100 | - MTK_PHY_LED0_ON_LINK1000); - phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL, - MTK_PHY_LED1_ENABLE | MTK_PHY_LED1_POLARITY | - MTK_PHY_LED1_ON_LINK10 | - MTK_PHY_LED1_ON_LINK100 | - MTK_PHY_LED1_ON_LINK1000); - - if ((port == GPHY_PORT0 && reg & BIT(8)) || - (port == GPHY_PORT1 && reg & BIT(9)) || - (port == GPHY_PORT2 && reg & BIT(10)) || - (port == GPHY_PORT3 && reg & BIT(11))) { - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, - MTK_PHY_LED0_POLARITY); - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL, - MTK_PHY_LED1_POLARITY); - } - - phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_BLINK_CTRL, - MTK_PHY_LED0_1000TX | MTK_PHY_LED0_1000RX | - MTK_PHY_LED0_100TX | MTK_PHY_LED0_100RX | - MTK_PHY_LED0_10TX | MTK_PHY_LED0_10RX); - phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_BLINK_CTRL, - MTK_PHY_LED1_1000TX | MTK_PHY_LED1_1000RX | - MTK_PHY_LED1_100TX | MTK_PHY_LED1_100RX | - MTK_PHY_LED1_10TX | MTK_PHY_LED1_10RX); - - pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led"); - if (IS_ERR(pinctrl)) { - dev_err(&phydev->mdio.bus->dev, "Failed to setup LED pins\n"); - return PTR_ERR(pinctrl); - } - - return 0; -} - -static int mt7988_phy_probe_shared(struct phy_device *phydev) -{ - struct mtk_socphy_shared_priv *priv = phydev->shared->priv; - void __iomem *boottrap; - struct device_node *np; - u32 reg; - - np = of_find_compatible_node(NULL, NULL, "mediatek,boottrap"); - if (!np) - return -ENOENT; - - boottrap = of_iomap(np, 0); - if (!boottrap) - return -ENOMEM; - - reg = readl(boottrap); - iounmap(boottrap); - - priv->boottrap = reg; - - return 0; -} - -static int mt7981_phy_probe(struct phy_device *phydev) -{ - return mt798x_phy_calibration(phydev); -} - -static int mt7988_phy_probe(struct phy_device *phydev) -{ - int err; - - err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0, - sizeof(struct mtk_socphy_shared_priv)); - if (err) - return err; - - if (phy_package_probe_once(phydev)) { - err = mt7988_phy_probe_shared(phydev); - if (err) - return err; - } - - mt7988_phy_setup_led(phydev); - - return mt798x_phy_calibration(phydev); -} - -static struct phy_driver mtk_socphy_driver[] = { - { - PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), - .name = "MediaTek MT7981 PHY", - .config_init = mt798x_phy_config_init, - .config_intr = genphy_no_config_intr, - .handle_interrupt = genphy_handle_interrupt_no_ack, - .probe = mt7981_phy_probe, - .suspend = genphy_suspend, - .resume = genphy_resume, - .read_page = mtk_socphy_read_page, - .write_page = mtk_socphy_write_page, - }, - { - PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988), - .name = "MediaTek MT7988 PHY", - .config_init = mt798x_phy_config_init, - .config_intr = genphy_no_config_intr, - .handle_interrupt = genphy_handle_interrupt_no_ack, - .probe = mt7988_phy_probe, - .suspend = genphy_suspend, - .resume = genphy_resume, - .read_page = mtk_socphy_read_page, - .write_page = mtk_socphy_write_page, - }, -}; - -module_phy_driver(mtk_socphy_driver); - -static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = { - { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) }, - { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) }, - { } -}; - -MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver"); -MODULE_AUTHOR("Daniel Golle "); -MODULE_AUTHOR("SkyLake Huang "); -MODULE_LICENSE("GPL"); - -MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl); diff --git a/target/linux/mediatek/patches-5.15/730-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch b/target/linux/mediatek/patches-5.15/730-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch deleted file mode 100644 index 43876deb66c..00000000000 --- a/target/linux/mediatek/patches-5.15/730-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch +++ /dev/null @@ -1,82 +0,0 @@ -From 60ed9eb9605656c19ca402b7bd3f47552e901601 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Mon, 13 Feb 2023 02:33:14 +0000 -Subject: [PATCH] net: phy: add driver for MediaTek SoC built-in GE PHYs - -Some of MediaTek's Filogic SoCs come with built-in gigabit Ethernet -PHYs which require calibration data from the SoC's efuse. -Despite the similar design the driver doesn't share any code with the -existing mediatek-ge.c, so add support for these PHYs by introducing a -new driver for only MediaTek's ARM64 SoCs. - -Signed-off-by: Daniel Golle ---- - MAINTAINERS | 9 + - drivers/net/phy/Kconfig | 12 + - drivers/net/phy/Makefile | 1 + - drivers/net/phy/mediatek-ge-soc.c | 1263 +++++++++++++++++++++++++++++ - drivers/net/phy/mediatek-ge.c | 3 +- - 5 files changed, 1287 insertions(+), 1 deletion(-) - create mode 100644 drivers/net/phy/mediatek-ge-soc.c - ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -11790,6 +11790,15 @@ S: Maintained - F: drivers/net/pcs/pcs-mtk-lynxi.c - F: include/linux/pcs/pcs-mtk-lynxi.h - -+MEDIATEK ETHERNET PHY DRIVERS -+M: Daniel Golle -+M: Qingfang Deng -+M: SkyLake Huang -+L: netdev@vger.kernel.org -+S: Maintained -+F: drivers/net/phy/mediatek-ge-soc.c -+F: drivers/net/phy/mediatek-ge.c -+ - MEDIATEK I2C CONTROLLER DRIVER - M: Qii Wang - L: linux-i2c@vger.kernel.org ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -293,6 +293,18 @@ config MEDIATEK_GE_PHY - help - Supports the MediaTek Gigabit Ethernet PHYs. - -+config MEDIATEK_GE_SOC_PHY -+ tristate "MediaTek SoC Ethernet PHYs" -+ depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST -+ select NVMEM_MTK_EFUSE -+ help -+ Supports MediaTek SoC built-in Gigabit Ethernet PHYs. -+ -+ Include support for built-in Ethernet PHYs which are present in -+ the MT7981 and MT7988 SoCs. These PHYs need calibration data -+ present in the SoCs efuse and will dynamically calibrate VCM -+ (common-mode voltage) during startup. -+ - config MICREL_PHY - tristate "Micrel PHYs" - help ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -81,6 +81,7 @@ obj-$(CONFIG_MARVELL_PHY) += marvell.o - obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o - obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o - obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o -+obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mediatek-ge-soc.o - obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o - obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o - obj-$(CONFIG_MICREL_PHY) += micrel.o ---- a/drivers/net/phy/mediatek-ge.c -+++ b/drivers/net/phy/mediatek-ge.c -@@ -136,7 +136,8 @@ static struct phy_driver mtk_gephy_drive - module_phy_driver(mtk_gephy_driver); - - static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = { -- { PHY_ID_MATCH_VENDOR(0x03a29400) }, -+ { PHY_ID_MATCH_EXACT(0x03a29441) }, -+ { PHY_ID_MATCH_EXACT(0x03a29412) }, - { } - }; - diff --git a/target/linux/mediatek/patches-5.15/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch b/target/linux/mediatek/patches-5.15/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch new file mode 100644 index 00000000000..26ebcb6733b --- /dev/null +++ b/target/linux/mediatek/patches-5.15/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch @@ -0,0 +1,1204 @@ +From 98c485eaf509bc0e2a85f9b58d17cd501f274c4e Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Sun, 11 Jun 2023 00:48:10 +0100 +Subject: [PATCH] net: phy: add driver for MediaTek SoC built-in GE PHYs + +Some of MediaTek's Filogic SoCs come with built-in gigabit Ethernet +PHYs which require calibration data from the SoC's efuse. +Despite the similar design the driver doesn't share any code with the +existing mediatek-ge.c. +Add support for such PHYs by introducing a new driver with basic +support for MediaTek SoCs MT7981 and MT7988 built-in 1GE PHYs. + +Signed-off-by: Daniel Golle +Reviewed-by: Andrew Lunn +Signed-off-by: David S. Miller +--- + MAINTAINERS | 9 + + drivers/net/phy/Kconfig | 12 + + drivers/net/phy/Makefile | 1 + + drivers/net/phy/mediatek-ge-soc.c | 1116 +++++++++++++++++++++++++++++ + drivers/net/phy/mediatek-ge.c | 3 +- + 5 files changed, 1140 insertions(+), 1 deletion(-) + create mode 100644 drivers/net/phy/mediatek-ge-soc.c + +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -11790,6 +11790,15 @@ S: Maintained + F: drivers/net/pcs/pcs-mtk-lynxi.c + F: include/linux/pcs/pcs-mtk-lynxi.h + ++MEDIATEK ETHERNET PHY DRIVERS ++M: Daniel Golle ++M: Qingfang Deng ++M: SkyLake Huang ++L: netdev@vger.kernel.org ++S: Maintained ++F: drivers/net/phy/mediatek-ge-soc.c ++F: drivers/net/phy/mediatek-ge.c ++ + MEDIATEK I2C CONTROLLER DRIVER + M: Qii Wang + L: linux-i2c@vger.kernel.org +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -293,6 +293,18 @@ config MEDIATEK_GE_PHY + help + Supports the MediaTek Gigabit Ethernet PHYs. + ++config MEDIATEK_GE_SOC_PHY ++ tristate "MediaTek SoC Ethernet PHYs" ++ depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST ++ select NVMEM_MTK_EFUSE ++ help ++ Supports MediaTek SoC built-in Gigabit Ethernet PHYs. ++ ++ Include support for built-in Ethernet PHYs which are present in ++ the MT7981 and MT7988 SoCs. These PHYs need calibration data ++ present in the SoCs efuse and will dynamically calibrate VCM ++ (common-mode voltage) during startup. ++ + config MICREL_PHY + tristate "Micrel PHYs" + help +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -81,6 +81,7 @@ obj-$(CONFIG_MARVELL_PHY) += marvell.o + obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o + obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o + obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o ++obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mediatek-ge-soc.o + obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o + obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o + obj-$(CONFIG_MICREL_PHY) += micrel.o +--- /dev/null ++++ b/drivers/net/phy/mediatek-ge-soc.c +@@ -0,0 +1,1116 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define MTK_GPHY_ID_MT7981 0x03a29461 ++#define MTK_GPHY_ID_MT7988 0x03a29481 ++ ++#define MTK_EXT_PAGE_ACCESS 0x1f ++#define MTK_PHY_PAGE_STANDARD 0x0000 ++#define MTK_PHY_PAGE_EXTENDED_3 0x0003 ++ ++#define MTK_PHY_LPI_REG_14 0x14 ++#define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0) ++ ++#define MTK_PHY_LPI_REG_1c 0x1c ++#define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8) ++ ++#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 ++#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 ++ ++#define ANALOG_INTERNAL_OPERATION_MAX_US 20 ++#define TXRESERVE_MIN 0 ++#define TXRESERVE_MAX 7 ++ ++#define MTK_PHY_ANARG_RG 0x10 ++#define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8) ++ ++/* Registers on MDIO_MMD_VEND1 */ ++#define MTK_PHY_TXVLD_DA_RG 0x12 ++#define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10) ++#define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0) ++ ++#define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16 ++#define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10) ++#define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0) ++ ++#define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17 ++#define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8) ++#define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0) ++ ++#define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18 ++#define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8) ++#define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0) ++ ++#define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19 ++#define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8) ++#define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0) ++ ++#define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20 ++#define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8) ++#define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0) ++ ++#define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21 ++#define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8) ++#define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0) ++ ++#define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22 ++#define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8) ++#define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0) ++ ++#define MTK_PHY_RXADC_CTRL_RG7 0xc6 ++#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8) ++ ++#define MTK_PHY_RXADC_CTRL_RG9 0xc8 ++#define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12) ++#define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8) ++#define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4) ++#define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0) ++ ++#define MTK_PHY_LDO_OUTPUT_V 0xd7 ++ ++#define MTK_PHY_RG_ANA_CAL_RG0 0xdb ++#define MTK_PHY_RG_CAL_CKINV BIT(12) ++#define MTK_PHY_RG_ANA_CALEN BIT(8) ++#define MTK_PHY_RG_ZCALEN_A BIT(0) ++ ++#define MTK_PHY_RG_ANA_CAL_RG1 0xdc ++#define MTK_PHY_RG_ZCALEN_B BIT(12) ++#define MTK_PHY_RG_ZCALEN_C BIT(8) ++#define MTK_PHY_RG_ZCALEN_D BIT(4) ++#define MTK_PHY_RG_TXVOS_CALEN BIT(0) ++ ++#define MTK_PHY_RG_ANA_CAL_RG5 0xe0 ++#define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8) ++ ++#define MTK_PHY_RG_TX_FILTER 0xfe ++ ++#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120 ++#define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8) ++#define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0) ++ ++#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122 ++#define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0) ++ ++#define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144 ++#define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5) ++ ++#define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172 ++#define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8) ++#define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0) ++ ++#define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173 ++#define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8) ++#define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0) ++ ++#define MTK_PHY_RG_AD_CAL_COMP 0x17a ++#define MTK_PHY_AD_CAL_COMP_OUT_SHIFT (8) ++ ++#define MTK_PHY_RG_AD_CAL_CLK 0x17b ++#define MTK_PHY_DA_CAL_CLK BIT(0) ++ ++#define MTK_PHY_RG_AD_CALIN 0x17c ++#define MTK_PHY_DA_CALIN_FLAG BIT(0) ++ ++#define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d ++#define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0) ++ ++#define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e ++#define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0) ++ ++#define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f ++#define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0) ++ ++#define MTK_PHY_RG_DASN_DAC_IN0_D 0x180 ++#define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0) ++ ++#define MTK_PHY_RG_DASN_DAC_IN1_A 0x181 ++#define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0) ++ ++#define MTK_PHY_RG_DASN_DAC_IN1_B 0x182 ++#define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0) ++ ++#define MTK_PHY_RG_DASN_DAC_IN1_C 0x183 ++#define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0) ++ ++#define MTK_PHY_RG_DASN_DAC_IN1_D 0x184 ++#define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0) ++ ++#define MTK_PHY_RG_DEV1E_REG19b 0x19b ++#define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8) ++ ++#define MTK_PHY_RG_LP_IIR2_K1_L 0x22a ++#define MTK_PHY_RG_LP_IIR2_K1_U 0x22b ++#define MTK_PHY_RG_LP_IIR2_K2_L 0x22c ++#define MTK_PHY_RG_LP_IIR2_K2_U 0x22d ++#define MTK_PHY_RG_LP_IIR2_K3_L 0x22e ++#define MTK_PHY_RG_LP_IIR2_K3_U 0x22f ++#define MTK_PHY_RG_LP_IIR2_K4_L 0x230 ++#define MTK_PHY_RG_LP_IIR2_K4_U 0x231 ++#define MTK_PHY_RG_LP_IIR2_K5_L 0x232 ++#define MTK_PHY_RG_LP_IIR2_K5_U 0x233 ++ ++#define MTK_PHY_RG_DEV1E_REG234 0x234 ++#define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0) ++#define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4) ++#define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12) ++ ++#define MTK_PHY_RG_LPF_CNT_VAL 0x235 ++ ++#define MTK_PHY_RG_DEV1E_REG238 0x238 ++#define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0) ++#define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12) ++ ++#define MTK_PHY_RG_DEV1E_REG239 0x239 ++#define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0) ++#define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12) ++ ++#define MTK_PHY_RG_DEV1E_REG27C 0x27c ++#define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8) ++#define MTK_PHY_RG_DEV1E_REG27D 0x27d ++#define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0) ++ ++#define MTK_PHY_RG_DEV1E_REG2C7 0x2c7 ++#define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0) ++#define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8) ++ ++#define MTK_PHY_RG_DEV1E_REG2D1 0x2d1 ++#define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0) ++#define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8) ++#define MTK_PHY_LPI_TR_READY BIT(9) ++#define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10) ++ ++#define MTK_PHY_RG_DEV1E_REG323 0x323 ++#define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0) ++#define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4) ++ ++#define MTK_PHY_RG_DEV1E_REG324 0x324 ++#define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0) ++#define MTK_PHY_SMI_DET_MAX_EN BIT(8) ++ ++#define MTK_PHY_RG_DEV1E_REG326 0x326 ++#define MTK_PHY_LPI_MODE_SD_ON BIT(0) ++#define MTK_PHY_RESET_RANDUPD_CNT BIT(1) ++#define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2) ++#define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4) ++#define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5) ++ ++#define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502 ++#define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503 ++ ++#define MTK_PHY_DA_TX_R50_PAIR_A 0x53d ++#define MTK_PHY_DA_TX_R50_PAIR_B 0x53e ++#define MTK_PHY_DA_TX_R50_PAIR_C 0x53f ++#define MTK_PHY_DA_TX_R50_PAIR_D 0x540 ++ ++#define MTK_PHY_RG_BG_RASEL 0x115 ++#define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0) ++ ++/* These macro privides efuse parsing for internal phy. */ ++#define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0)) ++#define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0)) ++#define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0)) ++#define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0)) ++#define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0)) ++ ++#define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0)) ++#define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0)) ++#define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0)) ++#define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0)) ++#define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0)) ++ ++#define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0)) ++#define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0)) ++ ++#define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0)) ++#define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0)) ++ ++enum { ++ NO_PAIR, ++ PAIR_A, ++ PAIR_B, ++ PAIR_C, ++ PAIR_D, ++}; ++ ++enum { ++ GPHY_PORT0, ++ GPHY_PORT1, ++ GPHY_PORT2, ++ GPHY_PORT3, ++}; ++ ++enum calibration_mode { ++ EFUSE_K, ++ SW_K ++}; ++ ++enum CAL_ITEM { ++ REXT, ++ TX_OFFSET, ++ TX_AMP, ++ TX_R50, ++ TX_VCM ++}; ++ ++enum CAL_MODE { ++ EFUSE_M, ++ SW_M ++}; ++ ++static int mtk_socphy_read_page(struct phy_device *phydev) ++{ ++ return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); ++} ++ ++static int mtk_socphy_write_page(struct phy_device *phydev, int page) ++{ ++ return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); ++} ++ ++/* One calibration cycle consists of: ++ * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high ++ * until AD_CAL_COMP is ready to output calibration result. ++ * 2.Wait until DA_CAL_CLK is available. ++ * 3.Fetch AD_CAL_COMP_OUT. ++ */ ++static int cal_cycle(struct phy_device *phydev, int devad, ++ u32 regnum, u16 mask, u16 cal_val) ++{ ++ int reg_val; ++ int ret; ++ ++ phy_modify_mmd(phydev, devad, regnum, ++ mask, cal_val); ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, ++ MTK_PHY_DA_CALIN_FLAG); ++ ++ ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_AD_CAL_CLK, reg_val, ++ reg_val & MTK_PHY_DA_CAL_CLK, 500, ++ ANALOG_INTERNAL_OPERATION_MAX_US, false); ++ if (ret) { ++ phydev_err(phydev, "Calibration cycle timeout\n"); ++ return ret; ++ } ++ ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, ++ MTK_PHY_DA_CALIN_FLAG); ++ ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >> ++ MTK_PHY_AD_CAL_COMP_OUT_SHIFT; ++ phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); ++ ++ return ret; ++} ++ ++static int rext_fill_result(struct phy_device *phydev, u16 *buf) ++{ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, ++ MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL, ++ MTK_PHY_RG_BG_RASEL_MASK, buf[1]); ++ ++ return 0; ++} ++ ++static int rext_cal_efuse(struct phy_device *phydev, u32 *buf) ++{ ++ u16 rext_cal_val[2]; ++ ++ rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]); ++ rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]); ++ rext_fill_result(phydev, rext_cal_val); ++ ++ return 0; ++} ++ ++static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf) ++{ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, ++ MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, ++ MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, ++ MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, ++ MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]); ++ ++ return 0; ++} ++ ++static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf) ++{ ++ u16 tx_offset_cal_val[4]; ++ ++ tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]); ++ tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]); ++ tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]); ++ tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]); ++ ++ tx_offset_fill_result(phydev, tx_offset_cal_val); ++ ++ return 0; ++} ++ ++static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf) ++{ ++ int i; ++ int bias[16] = {}; ++ const int vals_9461[16] = { 7, 1, 4, 7, ++ 7, 1, 4, 7, ++ 7, 1, 4, 7, ++ 7, 1, 4, 7 }; ++ const int vals_9481[16] = { 10, 6, 6, 10, ++ 10, 6, 6, 10, ++ 10, 6, 6, 10, ++ 10, 6, 6, 10 }; ++ switch (phydev->drv->phy_id) { ++ case MTK_GPHY_ID_MT7981: ++ /* We add some calibration to efuse values ++ * due to board level influence. ++ * GBE: +7, TBT: +1, HBT: +4, TST: +7 ++ */ ++ memcpy(bias, (const void *)vals_9461, sizeof(bias)); ++ break; ++ case MTK_GPHY_ID_MT7988: ++ memcpy(bias, (const void *)vals_9481, sizeof(bias)); ++ break; ++ } ++ ++ /* Prevent overflow */ ++ for (i = 0; i < 12; i++) { ++ if (buf[i >> 2] + bias[i] > 63) { ++ buf[i >> 2] = 63; ++ bias[i] = 0; ++ } ++ } ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, ++ MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, ++ MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, ++ MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, ++ MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, ++ MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, (buf[1] + bias[4]) << 8); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, ++ MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, buf[1] + bias[5]); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, ++ MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, ++ MTK_PHY_DA_TX_I2MPB_B_TST_MASK, buf[1] + bias[7]); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, ++ MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, (buf[2] + bias[8]) << 8); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, ++ MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, buf[2] + bias[9]); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, ++ MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, (buf[2] + bias[10]) << 8); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, ++ MTK_PHY_DA_TX_I2MPB_C_TST_MASK, buf[2] + bias[11]); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, ++ MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, ++ MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, buf[3] + bias[13]); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, ++ MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, (buf[3] + bias[14]) << 8); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, ++ MTK_PHY_DA_TX_I2MPB_D_TST_MASK, buf[3] + bias[15]); ++ ++ return 0; ++} ++ ++static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf) ++{ ++ u16 tx_amp_cal_val[4]; ++ ++ tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]); ++ tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]); ++ tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]); ++ tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]); ++ tx_amp_fill_result(phydev, tx_amp_cal_val); ++ ++ return 0; ++} ++ ++static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val, ++ u8 txg_calen_x) ++{ ++ int bias = 0; ++ u16 reg, val; ++ ++ if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988) ++ bias = -2; ++ ++ val = clamp_val(bias + tx_r50_cal_val, 0, 63); ++ ++ switch (txg_calen_x) { ++ case PAIR_A: ++ reg = MTK_PHY_DA_TX_R50_PAIR_A; ++ break; ++ case PAIR_B: ++ reg = MTK_PHY_DA_TX_R50_PAIR_B; ++ break; ++ case PAIR_C: ++ reg = MTK_PHY_DA_TX_R50_PAIR_C; ++ break; ++ case PAIR_D: ++ reg = MTK_PHY_DA_TX_R50_PAIR_D; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8); ++ ++ return 0; ++} ++ ++static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf, ++ u8 txg_calen_x) ++{ ++ u16 tx_r50_cal_val; ++ ++ switch (txg_calen_x) { ++ case PAIR_A: ++ tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]); ++ break; ++ case PAIR_B: ++ tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]); ++ break; ++ case PAIR_C: ++ tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]); ++ break; ++ case PAIR_D: ++ tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]); ++ break; ++ default: ++ return -EINVAL; ++ } ++ tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x); ++ ++ return 0; ++} ++ ++static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x) ++{ ++ u8 lower_idx, upper_idx, txreserve_val; ++ u8 lower_ret, upper_ret; ++ int ret; ++ ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, ++ MTK_PHY_RG_ANA_CALEN); ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, ++ MTK_PHY_RG_CAL_CKINV); ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, ++ MTK_PHY_RG_TXVOS_CALEN); ++ ++ switch (rg_txreserve_x) { ++ case PAIR_A: ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DASN_DAC_IN0_A, ++ MTK_PHY_DASN_DAC_IN0_A_MASK); ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DASN_DAC_IN1_A, ++ MTK_PHY_DASN_DAC_IN1_A_MASK); ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_ANA_CAL_RG0, ++ MTK_PHY_RG_ZCALEN_A); ++ break; ++ case PAIR_B: ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DASN_DAC_IN0_B, ++ MTK_PHY_DASN_DAC_IN0_B_MASK); ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DASN_DAC_IN1_B, ++ MTK_PHY_DASN_DAC_IN1_B_MASK); ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_ANA_CAL_RG1, ++ MTK_PHY_RG_ZCALEN_B); ++ break; ++ case PAIR_C: ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DASN_DAC_IN0_C, ++ MTK_PHY_DASN_DAC_IN0_C_MASK); ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DASN_DAC_IN1_C, ++ MTK_PHY_DASN_DAC_IN1_C_MASK); ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_ANA_CAL_RG1, ++ MTK_PHY_RG_ZCALEN_C); ++ break; ++ case PAIR_D: ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DASN_DAC_IN0_D, ++ MTK_PHY_DASN_DAC_IN0_D_MASK); ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DASN_DAC_IN1_D, ++ MTK_PHY_DASN_DAC_IN1_D_MASK); ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_ANA_CAL_RG1, ++ MTK_PHY_RG_ZCALEN_D); ++ break; ++ default: ++ ret = -EINVAL; ++ goto restore; ++ } ++ ++ lower_idx = TXRESERVE_MIN; ++ upper_idx = TXRESERVE_MAX; ++ ++ phydev_dbg(phydev, "Start TX-VCM SW cal.\n"); ++ while ((upper_idx - lower_idx) > 1) { ++ txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2); ++ ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, ++ MTK_PHY_DA_RX_PSBN_TBT_MASK | ++ MTK_PHY_DA_RX_PSBN_HBT_MASK | ++ MTK_PHY_DA_RX_PSBN_GBE_MASK | ++ MTK_PHY_DA_RX_PSBN_LP_MASK, ++ txreserve_val << 12 | txreserve_val << 8 | ++ txreserve_val << 4 | txreserve_val); ++ if (ret == 1) { ++ upper_idx = txreserve_val; ++ upper_ret = ret; ++ } else if (ret == 0) { ++ lower_idx = txreserve_val; ++ lower_ret = ret; ++ } else { ++ goto restore; ++ } ++ } ++ ++ if (lower_idx == TXRESERVE_MIN) { ++ lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RXADC_CTRL_RG9, ++ MTK_PHY_DA_RX_PSBN_TBT_MASK | ++ MTK_PHY_DA_RX_PSBN_HBT_MASK | ++ MTK_PHY_DA_RX_PSBN_GBE_MASK | ++ MTK_PHY_DA_RX_PSBN_LP_MASK, ++ lower_idx << 12 | lower_idx << 8 | ++ lower_idx << 4 | lower_idx); ++ ret = lower_ret; ++ } else if (upper_idx == TXRESERVE_MAX) { ++ upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RXADC_CTRL_RG9, ++ MTK_PHY_DA_RX_PSBN_TBT_MASK | ++ MTK_PHY_DA_RX_PSBN_HBT_MASK | ++ MTK_PHY_DA_RX_PSBN_GBE_MASK | ++ MTK_PHY_DA_RX_PSBN_LP_MASK, ++ upper_idx << 12 | upper_idx << 8 | ++ upper_idx << 4 | upper_idx); ++ ret = upper_ret; ++ } ++ if (ret < 0) ++ goto restore; ++ ++ /* We calibrate TX-VCM in different logic. Check upper index and then ++ * lower index. If this calibration is valid, apply lower index's result. ++ */ ++ ret = upper_ret - lower_ret; ++ if (ret == 1) { ++ ret = 0; ++ /* Make sure we use upper_idx in our calibration system */ ++ cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, ++ MTK_PHY_DA_RX_PSBN_TBT_MASK | ++ MTK_PHY_DA_RX_PSBN_HBT_MASK | ++ MTK_PHY_DA_RX_PSBN_GBE_MASK | ++ MTK_PHY_DA_RX_PSBN_LP_MASK, ++ upper_idx << 12 | upper_idx << 8 | ++ upper_idx << 4 | upper_idx); ++ phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx); ++ } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 && ++ lower_ret == 1) { ++ ret = 0; ++ cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, ++ MTK_PHY_DA_RX_PSBN_TBT_MASK | ++ MTK_PHY_DA_RX_PSBN_HBT_MASK | ++ MTK_PHY_DA_RX_PSBN_GBE_MASK | ++ MTK_PHY_DA_RX_PSBN_LP_MASK, ++ lower_idx << 12 | lower_idx << 8 | ++ lower_idx << 4 | lower_idx); ++ phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n", ++ lower_idx); ++ } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 && ++ lower_ret == 0) { ++ ret = 0; ++ phydev_warn(phydev, "TX-VCM SW cal result at high margin 0x%x\n", ++ upper_idx); ++ } else { ++ ret = -EINVAL; ++ } ++ ++restore: ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, ++ MTK_PHY_RG_ANA_CALEN); ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, ++ MTK_PHY_RG_TXVOS_CALEN); ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, ++ MTK_PHY_RG_ZCALEN_A); ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, ++ MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C | ++ MTK_PHY_RG_ZCALEN_D); ++ ++ return ret; ++} ++ ++static void mt798x_phy_common_finetune(struct phy_device *phydev) ++{ ++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); ++ /* EnabRandUpdTrig = 1 */ ++ __phy_write(phydev, 0x11, 0x2f00); ++ __phy_write(phydev, 0x12, 0xe); ++ __phy_write(phydev, 0x10, 0x8fb0); ++ ++ /* NormMseLoThresh = 85 */ ++ __phy_write(phydev, 0x11, 0x55a0); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x83aa); ++ ++ /* TrFreeze = 0 */ ++ __phy_write(phydev, 0x11, 0x0); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x9686); ++ ++ /* SSTrKp1000Slv = 5 */ ++ __phy_write(phydev, 0x11, 0xbaef); ++ __phy_write(phydev, 0x12, 0x2e); ++ __phy_write(phydev, 0x10, 0x968c); ++ ++ /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2, ++ * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2 ++ */ ++ __phy_write(phydev, 0x11, 0xd10a); ++ __phy_write(phydev, 0x12, 0x34); ++ __phy_write(phydev, 0x10, 0x8f82); ++ ++ /* VcoSlicerThreshBitsHigh */ ++ __phy_write(phydev, 0x11, 0x5555); ++ __phy_write(phydev, 0x12, 0x55); ++ __phy_write(phydev, 0x10, 0x8ec0); ++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); ++ ++ /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, ++ MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK, ++ BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); ++ ++ /* rg_tr_lpf_cnt_val = 512 */ ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200); ++ ++ /* IIR2 related */ ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe); ++ ++ /* FFE peaking */ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C, ++ MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D, ++ MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e); ++ ++ /* Disable LDO pump */ ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0); ++ /* Adjust LDO output voltage */ ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222); ++} ++ ++static void mt7981_phy_finetune(struct phy_device *phydev) ++{ ++ u16 val[8] = { 0x01ce, 0x01c1, ++ 0x020f, 0x0202, ++ 0x03d0, 0x03c0, ++ 0x0013, 0x0005 }; ++ int i, k; ++ ++ /* 100M eye finetune: ++ * Keep middle level of TX MLT3 shapper as default. ++ * Only change TX MLT3 overshoot level here. ++ */ ++ for (k = 0, i = 1; i < 12; i++) { ++ if (i % 3 == 0) ++ continue; ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]); ++ } ++ ++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); ++ /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */ ++ __phy_write(phydev, 0x11, 0xc71); ++ __phy_write(phydev, 0x12, 0xc); ++ __phy_write(phydev, 0x10, 0x8fae); ++ ++ /* ResetSyncOffset = 6 */ ++ __phy_write(phydev, 0x11, 0x600); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x8fc0); ++ ++ /* VgaDecRate = 1 */ ++ __phy_write(phydev, 0x11, 0x4c2a); ++ __phy_write(phydev, 0x12, 0x3e); ++ __phy_write(phydev, 0x10, 0x8fa4); ++ ++ /* FfeUpdGainForce = 4 */ ++ __phy_write(phydev, 0x11, 0x240); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x9680); ++ ++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); ++} ++ ++static void mt7988_phy_finetune(struct phy_device *phydev) ++{ ++ u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182, ++ 0x020d, 0x0206, 0x0384, 0x03d0, ++ 0x03c6, 0x030a, 0x0011, 0x0005 }; ++ int i; ++ ++ /* Set default MLT3 shaper first */ ++ for (i = 0; i < 12; i++) ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]); ++ ++ /* TCT finetune */ ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5); ++ ++ /* Disable TX power saving */ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, ++ MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8); ++ ++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); ++ ++ /* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */ ++ __phy_write(phydev, 0x11, 0x671); ++ __phy_write(phydev, 0x12, 0xc); ++ __phy_write(phydev, 0x10, 0x8fae); ++ ++ /* ResetSyncOffset = 5 */ ++ __phy_write(phydev, 0x11, 0x500); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x8fc0); ++ ++ /* VgaDecRate is 1 at default on mt7988 */ ++ ++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); ++ ++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30); ++ /* TxClkOffset = 2 */ ++ __phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK, ++ FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2)); ++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); ++} ++ ++static void mt798x_phy_eee(struct phy_device *phydev) ++{ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120, ++ MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK | ++ MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, ++ FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) | ++ FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14)); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, ++ MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, ++ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, ++ 0xff)); ++ ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_TESTMUX_ADC_CTRL, ++ MTK_PHY_RG_TXEN_DIG_MASK); ++ ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY); ++ ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238, ++ MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK | ++ MTK_PHY_LPI_SLV_SEND_TX_EN, ++ FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120)); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239, ++ MTK_PHY_LPI_SEND_LOC_TIMER_MASK | ++ MTK_PHY_LPI_TXPCS_LOC_RCV, ++ FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117)); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7, ++ MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK, ++ FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) | ++ FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13)); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1, ++ MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, ++ FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, ++ 0x33) | ++ MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY | ++ MTK_PHY_LPI_VCO_EEE_STG0_EN); ++ ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323, ++ MTK_PHY_EEE_WAKE_MAS_INT_DC | ++ MTK_PHY_EEE_WAKE_SLV_INT_DC); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324, ++ MTK_PHY_SMI_DETCNT_MAX_MASK, ++ FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) | ++ MTK_PHY_SMI_DET_MAX_EN); ++ ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326, ++ MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT | ++ MTK_PHY_TREC_UPDATE_ENAB_CLR | ++ MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF | ++ MTK_PHY_TR_READY_SKIP_AFE_WAKEUP); ++ ++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); ++ /* Regsigdet_sel_1000 = 0 */ ++ __phy_write(phydev, 0x11, 0xb); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x9690); ++ ++ /* REG_EEE_st2TrKf1000 = 3 */ ++ __phy_write(phydev, 0x11, 0x114f); ++ __phy_write(phydev, 0x12, 0x2); ++ __phy_write(phydev, 0x10, 0x969a); ++ ++ /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */ ++ __phy_write(phydev, 0x11, 0x3028); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x969e); ++ ++ /* RegEEE_slv_wake_int_timer_tar = 8 */ ++ __phy_write(phydev, 0x11, 0x5010); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x96a0); ++ ++ /* RegEEE_trfreeze_timer2 = 586 */ ++ __phy_write(phydev, 0x11, 0x24a); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x96a8); ++ ++ /* RegEEE100Stg1_tar = 16 */ ++ __phy_write(phydev, 0x11, 0x3210); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x96b8); ++ ++ /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */ ++ __phy_write(phydev, 0x11, 0x1463); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x96ca); ++ ++ /* DfeTailEnableVgaThresh1000 = 27 */ ++ __phy_write(phydev, 0x11, 0x36); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x8f80); ++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); ++ ++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3); ++ __phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000_MASK, ++ FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c)); ++ ++ __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK, ++ FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc)); ++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, ++ MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, ++ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff)); ++} ++ ++static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item, ++ u8 start_pair, u8 end_pair) ++{ ++ u8 pair_n; ++ int ret; ++ ++ for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { ++ /* TX_OFFSET & TX_AMP have no SW calibration. */ ++ switch (cal_item) { ++ case TX_VCM: ++ ret = tx_vcm_cal_sw(phydev, pair_n); ++ break; ++ default: ++ return -EINVAL; ++ } ++ if (ret) ++ return ret; ++ } ++ return 0; ++} ++ ++static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item, ++ u8 start_pair, u8 end_pair, u32 *buf) ++{ ++ u8 pair_n; ++ int ret; ++ ++ for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { ++ /* TX_VCM has no efuse calibration. */ ++ switch (cal_item) { ++ case REXT: ++ ret = rext_cal_efuse(phydev, buf); ++ break; ++ case TX_OFFSET: ++ ret = tx_offset_cal_efuse(phydev, buf); ++ break; ++ case TX_AMP: ++ ret = tx_amp_cal_efuse(phydev, buf); ++ break; ++ case TX_R50: ++ ret = tx_r50_cal_efuse(phydev, buf, pair_n); ++ break; ++ default: ++ return -EINVAL; ++ } ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item, ++ enum CAL_MODE cal_mode, u8 start_pair, ++ u8 end_pair, u32 *buf) ++{ ++ int ret; ++ ++ switch (cal_mode) { ++ case EFUSE_M: ++ ret = cal_efuse(phydev, cal_item, start_pair, ++ end_pair, buf); ++ break; ++ case SW_M: ++ ret = cal_sw(phydev, cal_item, start_pair, end_pair); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ if (ret) { ++ phydev_err(phydev, "cal %d failed\n", cal_item); ++ return -EIO; ++ } ++ ++ return 0; ++} ++ ++static int mt798x_phy_calibration(struct phy_device *phydev) ++{ ++ int ret = 0; ++ u32 *buf; ++ size_t len; ++ struct nvmem_cell *cell; ++ ++ cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data"); ++ if (IS_ERR(cell)) { ++ if (PTR_ERR(cell) == -EPROBE_DEFER) ++ return PTR_ERR(cell); ++ return 0; ++ } ++ ++ buf = (u32 *)nvmem_cell_read(cell, &len); ++ if (IS_ERR(buf)) ++ return PTR_ERR(buf); ++ nvmem_cell_put(cell); ++ ++ if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) { ++ phydev_err(phydev, "invalid efuse data\n"); ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf); ++ if (ret) ++ goto out; ++ ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf); ++ if (ret) ++ goto out; ++ ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf); ++ if (ret) ++ goto out; ++ ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf); ++ if (ret) ++ goto out; ++ ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf); ++ if (ret) ++ goto out; ++ ++out: ++ kfree(buf); ++ return ret; ++} ++ ++static int mt798x_phy_config_init(struct phy_device *phydev) ++{ ++ switch (phydev->drv->phy_id) { ++ case MTK_GPHY_ID_MT7981: ++ mt7981_phy_finetune(phydev); ++ break; ++ case MTK_GPHY_ID_MT7988: ++ mt7988_phy_finetune(phydev); ++ break; ++ } ++ ++ mt798x_phy_common_finetune(phydev); ++ mt798x_phy_eee(phydev); ++ ++ return mt798x_phy_calibration(phydev); ++} ++ ++static struct phy_driver mtk_socphy_driver[] = { ++ { ++ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), ++ .name = "MediaTek MT7981 PHY", ++ .config_init = mt798x_phy_config_init, ++ .config_intr = genphy_no_config_intr, ++ .handle_interrupt = genphy_handle_interrupt_no_ack, ++ .probe = mt798x_phy_calibration, ++ .suspend = genphy_suspend, ++ .resume = genphy_resume, ++ .read_page = mtk_socphy_read_page, ++ .write_page = mtk_socphy_write_page, ++ }, ++ { ++ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988), ++ .name = "MediaTek MT7988 PHY", ++ .config_init = mt798x_phy_config_init, ++ .config_intr = genphy_no_config_intr, ++ .handle_interrupt = genphy_handle_interrupt_no_ack, ++ .probe = mt798x_phy_calibration, ++ .suspend = genphy_suspend, ++ .resume = genphy_resume, ++ .read_page = mtk_socphy_read_page, ++ .write_page = mtk_socphy_write_page, ++ }, ++}; ++ ++module_phy_driver(mtk_socphy_driver); ++ ++static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = { ++ { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) }, ++ { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) }, ++ { } ++}; ++ ++MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver"); ++MODULE_AUTHOR("Daniel Golle "); ++MODULE_AUTHOR("SkyLake Huang "); ++MODULE_LICENSE("GPL"); ++ ++MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl); +--- a/drivers/net/phy/mediatek-ge.c ++++ b/drivers/net/phy/mediatek-ge.c +@@ -136,7 +136,8 @@ static struct phy_driver mtk_gephy_drive + module_phy_driver(mtk_gephy_driver); + + static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = { +- { PHY_ID_MATCH_VENDOR(0x03a29400) }, ++ { PHY_ID_MATCH_EXACT(0x03a29441) }, ++ { PHY_ID_MATCH_EXACT(0x03a29412) }, + { } + }; + diff --git a/target/linux/mediatek/patches-5.15/731-net-phy-mediatek-ge-soc-initialize-MT7988-PHY-LEDs-d.patch b/target/linux/mediatek/patches-5.15/731-net-phy-mediatek-ge-soc-initialize-MT7988-PHY-LEDs-d.patch new file mode 100644 index 00000000000..83d0f26bf41 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/731-net-phy-mediatek-ge-soc-initialize-MT7988-PHY-LEDs-d.patch @@ -0,0 +1,213 @@ +From 5d2d78860f98eb5c03bc404eb024606878901ac8 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Tue, 13 Jun 2023 03:27:14 +0100 +Subject: [PATCH] net: phy: mediatek-ge-soc: initialize MT7988 PHY LEDs default + state + +Initialize LEDs and set sane default values. +Read boottrap register and apply LED polarities accordingly to get +uniform behavior from all LEDs on MT7988. +Requires syscon phandle 'mediatek,pio' present in parenting MDIO bus +which should point to the syscon holding the boottrap register. + +Signed-off-by: Daniel Golle +--- + drivers/net/phy/mediatek-ge-soc.c | 144 ++++++++++++++++++++++++++++-- + 1 file changed, 136 insertions(+), 8 deletions(-) + +--- a/drivers/net/phy/mediatek-ge-soc.c ++++ b/drivers/net/phy/mediatek-ge-soc.c +@@ -1,11 +1,13 @@ + // SPDX-License-Identifier: GPL-2.0+ + #include ++#include + #include + #include + #include + #include + #include + #include ++#include + + #define MTK_GPHY_ID_MT7981 0x03a29461 + #define MTK_GPHY_ID_MT7988 0x03a29481 +@@ -208,9 +210,40 @@ + #define MTK_PHY_DA_TX_R50_PAIR_C 0x53f + #define MTK_PHY_DA_TX_R50_PAIR_D 0x540 + ++/* Registers on MDIO_MMD_VEND2 */ ++#define MTK_PHY_LED0_ON_CTRL 0x24 ++#define MTK_PHY_LED1_ON_CTRL 0x26 ++#define MTK_PHY_LED_ON_MASK GENMASK(6, 0) ++#define MTK_PHY_LED_ON_LINK1000 BIT(0) ++#define MTK_PHY_LED_ON_LINK100 BIT(1) ++#define MTK_PHY_LED_ON_LINK10 BIT(2) ++#define MTK_PHY_LED_ON_LINKDOWN BIT(3) ++#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */ ++#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */ ++#define MTK_PHY_LED_FORCE_ON BIT(6) ++#define MTK_PHY_LED_POLARITY BIT(14) ++#define MTK_PHY_LED_ENABLE BIT(15) ++ ++#define MTK_PHY_LED0_BLINK_CTRL 0x25 ++#define MTK_PHY_LED1_BLINK_CTRL 0x27 ++#define MTK_PHY_LED_1000TX BIT(0) ++#define MTK_PHY_LED_1000RX BIT(1) ++#define MTK_PHY_LED_100TX BIT(2) ++#define MTK_PHY_LED_100RX BIT(3) ++#define MTK_PHY_LED_10TX BIT(4) ++#define MTK_PHY_LED_10RX BIT(5) ++#define MTK_PHY_LED_COLLISION BIT(6) ++#define MTK_PHY_LED_RX_CRC_ERR BIT(7) ++#define MTK_PHY_LED_RX_IDLE_ERR BIT(8) ++#define MTK_PHY_LED_FORCE_BLINK BIT(9) ++ + #define MTK_PHY_RG_BG_RASEL 0x115 + #define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0) + ++/* Register in boottrap syscon defining the initial state of the 4 PHY LEDs */ ++#define RG_GPIO_MISC_TPBANK0 0x6f0 ++#define RG_GPIO_MISC_TPBANK0_BOOTMODE GENMASK(11, 8) ++ + /* These macro privides efuse parsing for internal phy. */ + #define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0)) + #define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0)) +@@ -238,13 +271,6 @@ enum { + PAIR_D, + }; + +-enum { +- GPHY_PORT0, +- GPHY_PORT1, +- GPHY_PORT2, +- GPHY_PORT3, +-}; +- + enum calibration_mode { + EFUSE_K, + SW_K +@@ -263,6 +289,10 @@ enum CAL_MODE { + SW_M + }; + ++struct mtk_socphy_shared { ++ u32 boottrap; ++}; ++ + static int mtk_socphy_read_page(struct phy_device *phydev) + { + return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); +@@ -1073,6 +1103,104 @@ static int mt798x_phy_config_init(struct + return mt798x_phy_calibration(phydev); + } + ++static int mt798x_phy_setup_led(struct phy_device *phydev, bool inverted) ++{ ++ struct pinctrl *pinctrl; ++ const u16 led_on_ctrl_defaults = MTK_PHY_LED_ENABLE | ++ MTK_PHY_LED_ON_LINK1000 | ++ MTK_PHY_LED_ON_LINK100 | ++ MTK_PHY_LED_ON_LINK10; ++ const u16 led_blink_defaults = MTK_PHY_LED_1000TX | ++ MTK_PHY_LED_1000RX | ++ MTK_PHY_LED_100TX | ++ MTK_PHY_LED_100RX | ++ MTK_PHY_LED_10TX | ++ MTK_PHY_LED_10RX; ++ ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, ++ led_on_ctrl_defaults ^ ++ (inverted ? MTK_PHY_LED_POLARITY : 0)); ++ ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL, ++ led_on_ctrl_defaults); ++ ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_BLINK_CTRL, ++ led_blink_defaults); ++ ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_BLINK_CTRL, ++ led_blink_defaults); ++ ++ pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led"); ++ if (IS_ERR(pinctrl)) ++ dev_err(&phydev->mdio.bus->dev, "Failed to setup PHY LED\n"); ++ ++ return 0; ++} ++ ++static int mt7988_phy_probe_shared(struct phy_device *phydev) ++{ ++ struct device_node *np = dev_of_node(&phydev->mdio.bus->dev); ++ struct mtk_socphy_shared *priv = phydev->shared->priv; ++ struct regmap *regmap; ++ u32 reg; ++ int ret; ++ ++ /* The LED0 of the 4 PHYs in MT7988 are wired to SoC pins LED_A, LED_B, ++ * LED_C and LED_D respectively. At the same time those pins are used to ++ * bootstrap configuration of the reference clock source (LED_A), ++ * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D). ++ * In practise this is done using a LED and a resistor pulling the pin ++ * either to GND or to VIO. ++ * The detected value at boot time is accessible at run-time using the ++ * TPBANK0 register located in the gpio base of the pinctrl, in order ++ * to read it here it needs to be referenced by a phandle called ++ * 'mediatek,pio' in the MDIO bus hosting the PHY. ++ * The 4 bits in TPBANK0 are kept as package shared data and are used to ++ * set LED polarity for each of the LED0. ++ */ ++ regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,pio"); ++ if (IS_ERR(regmap)) ++ return PTR_ERR(regmap); ++ ++ ret = regmap_read(regmap, RG_GPIO_MISC_TPBANK0, ®); ++ if (ret) ++ return ret; ++ ++ priv->boottrap = FIELD_GET(RG_GPIO_MISC_TPBANK0_BOOTMODE, reg); ++ ++ return 0; ++} ++ ++static bool mt7988_phy_get_boottrap_polarity(struct phy_device *phydev) ++{ ++ struct mtk_socphy_shared *priv = phydev->shared->priv; ++ ++ if (priv->boottrap & BIT(phydev->mdio.addr)) ++ return false; ++ ++ return true; ++} ++ ++static int mt7988_phy_probe(struct phy_device *phydev) ++{ ++ int err; ++ ++ err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0, ++ sizeof(struct mtk_socphy_shared)); ++ if (err) ++ return err; ++ ++ if (phy_package_probe_once(phydev)) { ++ err = mt7988_phy_probe_shared(phydev); ++ if (err) ++ return err; ++ } ++ ++ mt798x_phy_setup_led(phydev, mt7988_phy_get_boottrap_polarity(phydev)); ++ ++ return mt798x_phy_calibration(phydev); ++} ++ + static struct phy_driver mtk_socphy_driver[] = { + { + PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), +@@ -1092,7 +1220,7 @@ static struct phy_driver mtk_socphy_driv + .config_init = mt798x_phy_config_init, + .config_intr = genphy_no_config_intr, + .handle_interrupt = genphy_handle_interrupt_no_ack, +- .probe = mt798x_phy_calibration, ++ .probe = mt7988_phy_probe, + .suspend = genphy_suspend, + .resume = genphy_resume, + .read_page = mtk_socphy_read_page, From f321a49fd523a8d393be8e3cd2de41d67855da91 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sat, 8 Jul 2023 16:48:39 +0100 Subject: [PATCH 46/53] mediatek: dts: mt7988a: remove boottrap hack The PHY driver now uses regmap created from pio syscon, we no longer need the boottrap device. Signed-off-by: Daniel Golle --- .../files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 5 ----- .../files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 5 ----- 2 files changed, 10 deletions(-) diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 17de885629e..94aa8251bd0 100644 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -303,11 +303,6 @@ }; }; - boottrap: boottrap@1001f6f0 { - compatible = "mediatek,boottrap"; - reg = <0 0x1001f6f0 0 0x4>; - }; - sgmiisys0: syscon@10060000 { compatible = "mediatek,mt7988-sgmiisys", "mediatek,mt7988-sgmiisys_0", diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 17de885629e..94aa8251bd0 100644 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -303,11 +303,6 @@ }; }; - boottrap: boottrap@1001f6f0 { - compatible = "mediatek,boottrap"; - reg = <0 0x1001f6f0 0 0x4>; - }; - sgmiisys0: syscon@10060000 { compatible = "mediatek,mt7988-sgmiisys", "mediatek,mt7988-sgmiisys_0", From 712fa3eff82086da8a13e7e5bc577df17892a581 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sat, 8 Jul 2023 17:31:24 +0100 Subject: [PATCH 47/53] mediatek: replace hack for MaxLinear 2.5G PHY Replace hack with proper patch also for Linux 5.15. Signed-off-by: Daniel Golle --- ...et-phy-hack-mxl-gpy-disable-sgmii-an.patch | 166 ------------------ ...-don-t-use-SGMII-AN-if-using-phylink.patch | 63 +++++++ ...hy-add-driver-for-MediaTek-2.5G-PHY.patch} | 0 3 files changed, 63 insertions(+), 166 deletions(-) delete mode 100644 target/linux/mediatek/patches-5.15/731-net-phy-hack-mxl-gpy-disable-sgmii-an.patch create mode 100644 target/linux/mediatek/patches-5.15/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch rename target/linux/mediatek/patches-5.15/{732-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch => 733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch} (100%) diff --git a/target/linux/mediatek/patches-5.15/731-net-phy-hack-mxl-gpy-disable-sgmii-an.patch b/target/linux/mediatek/patches-5.15/731-net-phy-hack-mxl-gpy-disable-sgmii-an.patch deleted file mode 100644 index 2e39ca3c26a..00000000000 --- a/target/linux/mediatek/patches-5.15/731-net-phy-hack-mxl-gpy-disable-sgmii-an.patch +++ /dev/null @@ -1,166 +0,0 @@ ---- a/drivers/net/phy/mxl-gpy.c -+++ b/drivers/net/phy/mxl-gpy.c -@@ -126,6 +126,12 @@ static int gpy_config_init(struct phy_de - if (ret < 0) - return ret; - -+ /* Disable SGMII auto-negotiation */ -+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, -+ VSPEC1_SGMII_CTRL_ANEN, 0); -+ if (ret < 0) -+ return ret; -+ - return gpy_led_write(phydev); - } - -@@ -151,65 +157,6 @@ static int gpy_probe(struct phy_device * - return 0; - } - --static bool gpy_sgmii_need_reaneg(struct phy_device *phydev) --{ -- int fw_ver, fw_type, fw_minor; -- size_t i; -- -- fw_ver = phy_read(phydev, PHY_FWV); -- if (fw_ver < 0) -- return true; -- -- fw_type = FIELD_GET(PHY_FWV_TYPE_MASK, fw_ver); -- fw_minor = FIELD_GET(PHY_FWV_MINOR_MASK, fw_ver); -- -- for (i = 0; i < ARRAY_SIZE(ver_need_sgmii_reaneg); i++) { -- if (fw_type != ver_need_sgmii_reaneg[i].type) -- continue; -- if (fw_minor < ver_need_sgmii_reaneg[i].minor) -- return true; -- break; -- } -- -- return false; --} -- --static bool gpy_2500basex_chk(struct phy_device *phydev) --{ -- int ret; -- -- ret = phy_read(phydev, PHY_MIISTAT); -- if (ret < 0) { -- phydev_err(phydev, "Error: MDIO register access failed: %d\n", -- ret); -- return false; -- } -- -- if (!(ret & PHY_MIISTAT_LS) || -- FIELD_GET(PHY_MIISTAT_SPD_MASK, ret) != PHY_MIISTAT_SPD_2500) -- return false; -- -- phydev->speed = SPEED_2500; -- phydev->interface = PHY_INTERFACE_MODE_2500BASEX; -- phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, -- VSPEC1_SGMII_CTRL_ANEN, 0); -- return true; --} -- --static bool gpy_sgmii_aneg_en(struct phy_device *phydev) --{ -- int ret; -- -- ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL); -- if (ret < 0) { -- phydev_err(phydev, "Error: MMD register access failed: %d\n", -- ret); -- return true; -- } -- -- return (ret & VSPEC1_SGMII_CTRL_ANEN) ? true : false; --} -- - static int gpy_config_aneg(struct phy_device *phydev) - { - bool changed = false; -@@ -248,53 +195,11 @@ static int gpy_config_aneg(struct phy_de - phydev->interface == PHY_INTERFACE_MODE_INTERNAL) - return 0; - -- /* No need to trigger re-ANEG if link speed is 2.5G or SGMII ANEG is -- * disabled. -- */ -- if (!gpy_sgmii_need_reaneg(phydev) || gpy_2500basex_chk(phydev) || -- !gpy_sgmii_aneg_en(phydev)) -- return 0; -- -- /* There is a design constraint in GPY2xx device where SGMII AN is -- * only triggered when there is change of speed. If, PHY link -- * partner`s speed is still same even after PHY TPI is down and up -- * again, SGMII AN is not triggered and hence no new in-band message -- * from GPY to MAC side SGMII. -- * This could cause an issue during power up, when PHY is up prior to -- * MAC. At this condition, once MAC side SGMII is up, MAC side SGMII -- * wouldn`t receive new in-band message from GPY with correct link -- * status, speed and duplex info. -- * -- * 1) If PHY is already up and TPI link status is still down (such as -- * hard reboot), TPI link status is polled for 4 seconds before -- * retriggerring SGMII AN. -- * 2) If PHY is already up and TPI link status is also up (such as soft -- * reboot), polling of TPI link status is not needed and SGMII AN is -- * immediately retriggered. -- * 3) Other conditions such as PHY is down, speed change etc, skip -- * retriggering SGMII AN. Note: in case of speed change, GPY FW will -- * initiate SGMII AN. -- */ -- -- if (phydev->state != PHY_UP) -- return 0; -- -- ret = phy_read_poll_timeout(phydev, MII_BMSR, ret, ret & BMSR_LSTATUS, -- 20000, 4000000, false); -- if (ret == -ETIMEDOUT) -- return 0; -- else if (ret < 0) -- return ret; -- -- /* Trigger SGMII AN. */ -- return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, -- VSPEC1_SGMII_CTRL_ANRS, VSPEC1_SGMII_CTRL_ANRS); -+ return 0; - } - - static void gpy_update_interface(struct phy_device *phydev) - { -- int ret; -- - /* Interface mode is fixed for USXGMII and integrated PHY */ - if (phydev->interface == PHY_INTERFACE_MODE_USXGMII || - phydev->interface == PHY_INTERFACE_MODE_INTERNAL) -@@ -306,29 +211,11 @@ static void gpy_update_interface(struct - switch (phydev->speed) { - case SPEED_2500: - phydev->interface = PHY_INTERFACE_MODE_2500BASEX; -- ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, -- VSPEC1_SGMII_CTRL_ANEN, 0); -- if (ret < 0) -- phydev_err(phydev, -- "Error: Disable of SGMII ANEG failed: %d\n", -- ret); - break; - case SPEED_1000: - case SPEED_100: - case SPEED_10: - phydev->interface = PHY_INTERFACE_MODE_SGMII; -- if (gpy_sgmii_aneg_en(phydev)) -- break; -- /* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed -- * if ANEG is disabled (in 2500-BaseX mode). -- */ -- ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, -- VSPEC1_SGMII_ANEN_ANRS, -- VSPEC1_SGMII_ANEN_ANRS); -- if (ret < 0) -- phydev_err(phydev, -- "Error: Enable of SGMII ANEG failed: %d\n", -- ret); - break; - } - } diff --git a/target/linux/mediatek/patches-5.15/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch b/target/linux/mediatek/patches-5.15/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch new file mode 100644 index 00000000000..598d9d0d218 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch @@ -0,0 +1,63 @@ +From a969b663c866129ed9eb217785a6574fbe826f1d Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Thu, 6 Apr 2023 23:36:50 +0100 +Subject: [PATCH] net: phy: mxl-gpy: don't use SGMII AN if using phylink + +MAC drivers using phylink expect SGMII in-band-status to be switched off +when attached to a PHY. Make sure this is the case also for mxl-gpy which +keeps SGMII in-band-status in case of SGMII interface mode is used. + +Signed-off-by: Daniel Golle +--- + drivers/net/phy/mxl-gpy.c | 19 ++++++++++++++++--- + 1 file changed, 16 insertions(+), 3 deletions(-) + +--- a/drivers/net/phy/mxl-gpy.c ++++ b/drivers/net/phy/mxl-gpy.c +@@ -191,8 +191,11 @@ static bool gpy_2500basex_chk(struct phy + + phydev->speed = SPEED_2500; + phydev->interface = PHY_INTERFACE_MODE_2500BASEX; +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, +- VSPEC1_SGMII_CTRL_ANEN, 0); ++ ++ if (!phydev->phylink) ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, ++ VSPEC1_SGMII_CTRL_ANEN, 0); ++ + return true; + } + +@@ -216,6 +219,14 @@ static int gpy_config_aneg(struct phy_de + u32 adv; + int ret; + ++ /* Disable SGMII auto-negotiation if using phylink */ ++ if (phydev->phylink) { ++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, ++ VSPEC1_SGMII_CTRL_ANEN, 0); ++ if (ret < 0) ++ return ret; ++ } ++ + if (phydev->autoneg == AUTONEG_DISABLE) { + /* Configure half duplex with genphy_setup_forced, + * because genphy_c45_pma_setup_forced does not support. +@@ -306,6 +317,8 @@ static void gpy_update_interface(struct + switch (phydev->speed) { + case SPEED_2500: + phydev->interface = PHY_INTERFACE_MODE_2500BASEX; ++ if (phydev->phylink) ++ break; + ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, + VSPEC1_SGMII_CTRL_ANEN, 0); + if (ret < 0) +@@ -317,7 +330,7 @@ static void gpy_update_interface(struct + case SPEED_100: + case SPEED_10: + phydev->interface = PHY_INTERFACE_MODE_SGMII; +- if (gpy_sgmii_aneg_en(phydev)) ++ if (phydev->phylink || gpy_sgmii_aneg_en(phydev)) + break; + /* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed + * if ANEG is disabled (in 2500-BaseX mode). diff --git a/target/linux/mediatek/patches-5.15/732-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch b/target/linux/mediatek/patches-5.15/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch similarity index 100% rename from target/linux/mediatek/patches-5.15/732-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch rename to target/linux/mediatek/patches-5.15/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch From 2b133ab19cd5d741f3191f917c607667943f5f58 Mon Sep 17 00:00:00 2001 From: David Bauer Date: Fri, 9 Jun 2023 14:12:47 +0200 Subject: [PATCH 48/53] scripts: use sep-char for hash nodes U-Boot with enabled secure-boot will not boot images with the @-character used for hash node-names. Use the existing separation character configurable for each device. Signed-off-by: David Bauer --- scripts/mkits.sh | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/scripts/mkits.sh b/scripts/mkits.sh index b1c6f988674..eeb01216f92 100755 --- a/scripts/mkits.sh +++ b/scripts/mkits.sh @@ -108,10 +108,10 @@ if [ -n "${DTB}" ]; then ${DTADDR:+load = <${DTADDR}>;} arch = \"${ARCH}\"; compression = \"none\"; - hash@1 { + hash${REFERENCE_CHAR}1 { algo = \"crc32\"; }; - hash@2 { + hash${REFERENCE_CHAR}2 { algo = \"${HASH}\"; }; }; @@ -128,10 +128,10 @@ if [ -n "${INITRD}" ]; then type = \"ramdisk\"; arch = \"${ARCH}\"; os = \"linux\"; - hash@1 { + hash${REFERENCE_CHAR}1 { algo = \"crc32\"; }; - hash@2 { + hash${REFERENCE_CHAR}2 { algo = \"${HASH}\"; }; }; @@ -150,10 +150,10 @@ if [ -n "${ROOTFS}" ]; then type = \"filesystem\"; arch = \"${ARCH}\"; compression = \"none\"; - hash@1 { + hash${REFERENCE_CHAR}1 { algo = \"crc32\"; }; - hash@2 { + hash${REFERENCE_CHAR}2 { algo = \"${HASH}\"; }; }; @@ -181,10 +181,10 @@ OVCONFIGS="" arch = \"${ARCH}\"; load = <${DTADDR}>; compression = \"none\"; - hash@1 { + hash${REFERENCE_CHAR}1 { algo = \"crc32\"; }; - hash@2 { + hash${REFERENCE_CHAR}2 { algo = \"${HASH}\"; }; }; @@ -216,10 +216,10 @@ DATA="/dts-v1/; compression = \"${COMPRESS}\"; load = <${LOAD_ADDR}>; entry = <${ENTRY_ADDR}>; - hash@1 { + hash${REFERENCE_CHAR}1 { algo = \"crc32\"; }; - hash@2 { + hash${REFERENCE_CHAR}2 { algo = \"$HASH\"; }; }; From 95330a5d605715179cc7e4047cbeaf66b097fc87 Mon Sep 17 00:00:00 2001 From: Wenli Looi Date: Sat, 1 Jul 2023 17:37:17 +0000 Subject: [PATCH 49/53] build: add ALT5 vendor/model/variant This allows adding another device variant. Signed-off-by: Wenli Looi --- include/image.mk | 21 ++++++++++++++++++++- scripts/json_add_image_info.py | 2 +- 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/include/image.mk b/include/image.mk index fae4d32a8bb..8f0cbead108 100644 --- a/include/image.mk +++ b/include/image.mk @@ -346,6 +346,7 @@ define Device/InitProfile DEVICE_ALT2_TITLE = $$(DEVICE_ALT2_VENDOR) $$(DEVICE_ALT2_MODEL)$$(if $$(DEVICE_ALT2_VARIANT), $$(DEVICE_ALT2_VARIANT)) DEVICE_ALT3_TITLE = $$(DEVICE_ALT3_VENDOR) $$(DEVICE_ALT3_MODEL)$$(if $$(DEVICE_ALT3_VARIANT), $$(DEVICE_ALT3_VARIANT)) DEVICE_ALT4_TITLE = $$(DEVICE_ALT4_VENDOR) $$(DEVICE_ALT4_MODEL)$$(if $$(DEVICE_ALT4_VARIANT), $$(DEVICE_ALT4_VARIANT)) + DEVICE_ALT5_TITLE = $$(DEVICE_ALT5_VENDOR) $$(DEVICE_ALT5_MODEL)$$(if $$(DEVICE_ALT5_VARIANT), $$(DEVICE_ALT5_VARIANT)) DEVICE_VENDOR := DEVICE_MODEL := DEVICE_VARIANT := @@ -364,6 +365,9 @@ define Device/InitProfile DEVICE_ALT4_VENDOR := DEVICE_ALT4_MODEL := DEVICE_ALT4_VARIANT := + DEVICE_ALT5_VENDOR := + DEVICE_ALT5_MODEL := + DEVICE_ALT5_VARIANT := DEVICE_PACKAGES := DEVICE_DESCRIPTION = Build firmware images for $$(DEVICE_TITLE) endef @@ -448,7 +452,8 @@ DEFAULT_DEVICE_VARS := \ DEVICE_ALT1_VENDOR DEVICE_ALT1_MODEL DEVICE_ALT1_VARIANT \ DEVICE_ALT2_VENDOR DEVICE_ALT2_MODEL DEVICE_ALT2_VARIANT \ DEVICE_ALT3_VENDOR DEVICE_ALT3_MODEL DEVICE_ALT3_VARIANT \ - DEVICE_ALT4_VENDOR DEVICE_ALT4_MODEL DEVICE_ALT4_VARIANT + DEVICE_ALT4_VENDOR DEVICE_ALT4_MODEL DEVICE_ALT4_VARIANT \ + DEVICE_ALT5_VENDOR DEVICE_ALT5_MODEL DEVICE_ALT5_VARIANT define Device/ExportVar $(1) : $(2):=$$($(2)) @@ -537,6 +542,9 @@ define Device/Build/initramfs DEVICE_ALT4_VENDOR="$$(DEVICE_ALT4_VENDOR)" \ DEVICE_ALT4_MODEL="$$(DEVICE_ALT4_MODEL)" \ DEVICE_ALT4_VARIANT="$$(DEVICE_ALT4_VARIANT)" \ + DEVICE_ALT5_VENDOR="$$(DEVICE_ALT5_VENDOR)" \ + DEVICE_ALT5_MODEL="$$(DEVICE_ALT5_MODEL)" \ + DEVICE_ALT5_VARIANT="$$(DEVICE_ALT5_VARIANT)" \ DEVICE_TITLE="$$(DEVICE_TITLE)" \ DEVICE_PACKAGES="$$(DEVICE_PACKAGES)" \ TARGET="$(BOARD)" \ @@ -668,6 +676,9 @@ define Device/Build/image DEVICE_ALT4_VENDOR="$(DEVICE_ALT4_VENDOR)" \ DEVICE_ALT4_MODEL="$(DEVICE_ALT4_MODEL)" \ DEVICE_ALT4_VARIANT="$(DEVICE_ALT4_VARIANT)" \ + DEVICE_ALT5_VENDOR="$(DEVICE_ALT5_VENDOR)" \ + DEVICE_ALT5_MODEL="$(DEVICE_ALT5_MODEL)" \ + DEVICE_ALT5_VARIANT="$(DEVICE_ALT5_VARIANT)" \ DEVICE_TITLE="$(DEVICE_TITLE)" \ DEVICE_PACKAGES="$(DEVICE_PACKAGES)" \ TARGET="$(BOARD)" \ @@ -719,6 +730,9 @@ define Device/Build/artifact DEVICE_ALT4_VENDOR="$(DEVICE_ALT4_VENDOR)" \ DEVICE_ALT4_MODEL="$(DEVICE_ALT4_MODEL)" \ DEVICE_ALT4_VARIANT="$(DEVICE_ALT4_VARIANT)" \ + DEVICE_ALT5_VENDOR="$(DEVICE_ALT5_VENDOR)" \ + DEVICE_ALT5_MODEL="$(DEVICE_ALT5_MODEL)" \ + DEVICE_ALT5_VARIANT="$(DEVICE_ALT5_VARIANT)" \ DEVICE_TITLE="$(DEVICE_TITLE)" \ DEVICE_PACKAGES="$(DEVICE_PACKAGES)" \ TARGET="$(BOARD)" \ @@ -762,6 +776,7 @@ $(if $(strip $(DEVICE_ALT1_TITLE)),- $(DEVICE_ALT1_TITLE)) $(if $(strip $(DEVICE_ALT2_TITLE)),- $(DEVICE_ALT2_TITLE)) $(if $(strip $(DEVICE_ALT3_TITLE)),- $(DEVICE_ALT3_TITLE)) $(if $(strip $(DEVICE_ALT4_TITLE)),- $(DEVICE_ALT4_TITLE)) +$(if $(strip $(DEVICE_ALT5_TITLE)),- $(DEVICE_ALT5_TITLE)) @@ endef @@ -787,6 +802,10 @@ ifneq ($$(strip $$(DEVICE_ALT4_TITLE)),) DEVICE_DISPLAY = $$(DEVICE_ALT4_TITLE) ($$(DEVICE_TITLE)) $$(info $$(call Device/DumpInfo,$(1))) endif +ifneq ($$(strip $$(DEVICE_ALT5_TITLE)),) +DEVICE_DISPLAY = $$(DEVICE_ALT5_TITLE) ($$(DEVICE_TITLE)) +$$(info $$(call Device/DumpInfo,$(1))) +endif DEVICE_DISPLAY = $$(DEVICE_TITLE) $$(eval $$(if $$(DEVICE_TITLE),$$(info $$(call Device/DumpInfo,$(1))))) endef diff --git a/scripts/json_add_image_info.py b/scripts/json_add_image_info.py index 0c441b93344..3aeb7ba5fc4 100755 --- a/scripts/json_add_image_info.py +++ b/scripts/json_add_image_info.py @@ -21,7 +21,7 @@ if not file_path.is_file(): def get_titles(): titles = [] - for prefix in ["", "ALT0_", "ALT1_", "ALT2_", "ALT3_", "ALT4_"]: + for prefix in ["", "ALT0_", "ALT1_", "ALT2_", "ALT3_", "ALT4_", "ALT5_"]: title = {} for var in ["vendor", "model", "variant"]: if getenv("DEVICE_{}{}".format(prefix, var.upper())): From 520c9917f8883766d47707cd560ffdaecc9b9dee Mon Sep 17 00:00:00 2001 From: Wenli Looi Date: Sat, 1 Jul 2023 17:46:15 +0000 Subject: [PATCH 50/53] ath79: add support for ASUS RT-AC59U / ZenWiFi CD6 ASUS RT-AC59U / RT-AC59U v2 are wi-fi routers with a large number of alternate names, including RT-AC1200GE, RT-AC1300G PLUS, RT-AC1500UHP, RT-AC57U v2/v3, RT-AC58U v2/v3, and RT-ACRH12. ASUS ZenWiFi AC Mini(CD6) is a mesh wifi system. The unit labeled CD6R is the router, and CD6N is the node. Hardware: - SoC: QCN5502 - RAM: 128 MiB - UART: 115200 baud (labeled on boards) - Wireless: - 2.4GHz: QCN5502 on-chip 4x4 802.11b/g/n currently unsupported due to missing support for QCN550x in ath9k - 5GHz: QCA9888 pcie 5GHz 2x2 802.11a/n/ac - Flash: SPI NOR - RT-AC59U / CD6N: 16 MiB - RT-AC59U v2 / CD6R: 32 MiB - Ethernet: gigabit - RT-AC59U / RT-AC59U v2: 4x LAN 1x WAN - CD6R: 3x LAN 1x WAN - CD6N: 2x LAN - USB: - RT-AC59U / RT-AC59U v2: 1 port USB 2.0 - CD6R / CD6N: none WiFi calibration data contains valid MAC addresses. The initramfs image is uncompressed because I was unable to boot a compressed initramfs from memory (gzip or lzma). Booting a compressed image from flash works fine. Installation: To install without opening the case: - Set your computer IP address to 192.168.1.10/24 - Power up with the Reset button pressed - Release the Reset button after about 5 seconds or until you see the power LED blinking slowly - Upload OpenWRT factory image via TFTP client to 192.168.1.1 Revert to stock firmware using the same TFTP method. Signed-off-by: Wenli Looi --- package/boot/uboot-envtools/files/ath79 | 4 + target/linux/ath79/dts/qcn5502_asus.dtsi | 114 ++++++++++++++++++ .../ath79/dts/qcn5502_asus_rt-ac59u-v2.dts | 19 +++ .../linux/ath79/dts/qcn5502_asus_rt-ac59u.dts | 19 +++ .../ath79/dts/qcn5502_asus_rt-ac59u.dtsi | 69 +++++++++++ .../ath79/dts/qcn5502_asus_zenwifi-cd6.dtsi | 57 +++++++++ .../ath79/dts/qcn5502_asus_zenwifi-cd6n.dts | 19 +++ .../ath79/dts/qcn5502_asus_zenwifi-cd6r.dts | 19 +++ .../generic/base-files/etc/board.d/02_network | 10 ++ target/linux/ath79/image/generic.mk | 64 ++++++++++ 10 files changed, 394 insertions(+) create mode 100644 target/linux/ath79/dts/qcn5502_asus.dtsi create mode 100644 target/linux/ath79/dts/qcn5502_asus_rt-ac59u-v2.dts create mode 100644 target/linux/ath79/dts/qcn5502_asus_rt-ac59u.dts create mode 100644 target/linux/ath79/dts/qcn5502_asus_rt-ac59u.dtsi create mode 100644 target/linux/ath79/dts/qcn5502_asus_zenwifi-cd6.dtsi create mode 100644 target/linux/ath79/dts/qcn5502_asus_zenwifi-cd6n.dts create mode 100644 target/linux/ath79/dts/qcn5502_asus_zenwifi-cd6r.dts diff --git a/package/boot/uboot-envtools/files/ath79 b/package/boot/uboot-envtools/files/ath79 index e83703b0355..aeeb9385d34 100644 --- a/package/boot/uboot-envtools/files/ath79 +++ b/package/boot/uboot-envtools/files/ath79 @@ -25,6 +25,10 @@ araknis,an-300-ap-i-n|\ araknis,an-500-ap-i-ac|\ araknis,an-700-ap-i-ac|\ arduino,yun|\ +asus,rt-ac59u|\ +asus,rt-ac59u-v2|\ +asus,zenwifi-cd6n|\ +asus,zenwifi-cd6r|\ buffalo,bhr-4grv2|\ devolo,magic-2-wifi|\ dlink,dir-859-a1|\ diff --git a/target/linux/ath79/dts/qcn5502_asus.dtsi b/target/linux/ath79/dts/qcn5502_asus.dtsi new file mode 100644 index 00000000000..a2b4a76e92e --- /dev/null +++ b/target/linux/ath79/dts/qcn5502_asus.dtsi @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qca956x.dtsi" + +#include +#include + +/ { + aliases { + label-mac-device = ð0; + }; +}; + +ð0 { + status = "okay"; + + pll-data = <0x03000101 0x00000101 0x00001919>; + + phy-mode = "sgmii"; + phy-handle = <&phy0>; + + nvmem-cells = <&macaddr_factory_1002>; + nvmem-cell-names = "mac-address"; +}; + +&mdio0 { + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + phy-mode = "sgmii"; + qca,mib-poll-interval = <500>; + + qca,ar8327-initvals = < + 0x04 0x80080080 /* PORT0 PAD MODE CTRL */ + 0x08 0x00000000 /* PORT5 PAD MODE CTRL */ + 0x0c 0x00000000 /* PORT6 PAD MODE CTRL */ + 0x10 0x00000080 /* POWER_ON_STRAP */ + 0x7c 0x0000007e /* PORT0_STATUS */ + 0x94 0x00000200 /* PORT6_STATUS */ + >; + }; +}; + +&pcie { + status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0 0 0 0 0>; + + nvmem-cells = <&precal_factory_5000>; + nvmem-cell-names = "pre-calibration"; + }; +}; + +&spi { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + m25p,fast-read; + + mtdparts: partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Bootloader"; + reg = <0x000000 0x040000>; + read-only; + }; + + partition@40000 { + label = "nvram"; + reg = <0x040000 0x010000>; + read-only; + }; + + partition@50000 { + label = "Factory"; + reg = <0x050000 0x010000>; + read-only; + + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + cal_factory_1000: cal@1000 { + reg = <0x1000 0x440>; + }; + + macaddr_factory_1002: macaddr@1002 { + reg = <0x1002 0x6>; + }; + + precal_factory_5000: precal@5000 { + reg = <0x5000 0x2f20>; + }; + }; + }; + }; +}; + +&wmac { + /* Does not work due to lack of QCN5502 support in ath9k. */ + status = "disabled"; + + nvmem-cells = <&cal_factory_1000>; + nvmem-cell-names = "calibration"; +}; diff --git a/target/linux/ath79/dts/qcn5502_asus_rt-ac59u-v2.dts b/target/linux/ath79/dts/qcn5502_asus_rt-ac59u-v2.dts new file mode 100644 index 00000000000..795bb299e9f --- /dev/null +++ b/target/linux/ath79/dts/qcn5502_asus_rt-ac59u-v2.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcn5502_asus_rt-ac59u.dtsi" + +#include +#include + +/ { + compatible = "asus,rt-ac59u-v2", "qca,qcn5500", "qca,qca9560"; + model = "ASUS RT-AC59U v2"; +}; + +&mtdparts { + partition@60000 { + label = "firmware"; + reg = <0x060000 0x1fa0000>; + compatible = "denx,uimage"; + }; +}; diff --git a/target/linux/ath79/dts/qcn5502_asus_rt-ac59u.dts b/target/linux/ath79/dts/qcn5502_asus_rt-ac59u.dts new file mode 100644 index 00000000000..a4ebeb39121 --- /dev/null +++ b/target/linux/ath79/dts/qcn5502_asus_rt-ac59u.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcn5502_asus_rt-ac59u.dtsi" + +#include +#include + +/ { + compatible = "asus,rt-ac59u", "qca,qcn5500", "qca,qca9560"; + model = "ASUS RT-AC59U"; +}; + +&mtdparts { + partition@60000 { + label = "firmware"; + reg = <0x060000 0xfa0000>; + compatible = "denx,uimage"; + }; +}; diff --git a/target/linux/ath79/dts/qcn5502_asus_rt-ac59u.dtsi b/target/linux/ath79/dts/qcn5502_asus_rt-ac59u.dtsi new file mode 100644 index 00000000000..ffc2b893451 --- /dev/null +++ b/target/linux/ath79/dts/qcn5502_asus_rt-ac59u.dtsi @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcn5502_asus.dtsi" + +#include +#include + +/ { + aliases { + led-boot = &led_power; + led-failsafe = &led_power; + led-running = &led_power; + led-upgrade = &led_power; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = ; + gpios = <&gpio 17 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + + wps { + label = "wps"; + linux,code = ; + gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_power: power { + label = "blue:power"; + gpios = <&gpio 16 GPIO_ACTIVE_LOW>; + }; + + usb { + label = "blue:usb"; + gpios = <&gpio 4 GPIO_ACTIVE_LOW>; + trigger-sources = <&hub_port0>; + linux,default-trigger = "usbport"; + }; + + wlan2g { + label = "blue:wlan2g"; + gpios = <&gpio 15 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy1tpt"; + }; + + wlan5g { + label = "blue:wlan5g"; + gpios = <&gpio 5 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0tpt"; + }; + }; +}; + +&usb_phy0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; diff --git a/target/linux/ath79/dts/qcn5502_asus_zenwifi-cd6.dtsi b/target/linux/ath79/dts/qcn5502_asus_zenwifi-cd6.dtsi new file mode 100644 index 00000000000..1d8fe7637a8 --- /dev/null +++ b/target/linux/ath79/dts/qcn5502_asus_zenwifi-cd6.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcn5502_asus.dtsi" + +#include +#include + +/ { + aliases { + led-boot = &led_blue; + led-failsafe = &led_red; + led-running = &led_blue; + led-upgrade = &led_red; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = ; + gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + + wps { + label = "wps"; + linux,code = ; + gpios = <&gpio 17 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_blue: blue { + label = "blue"; + gpios = <&gpio 5 GPIO_ACTIVE_LOW>; + }; + + green { + label = "green"; + gpios = <&gpio 15 GPIO_ACTIVE_LOW>; + }; + + led_red: red { + label = "red"; + gpios = <&gpio 4 GPIO_ACTIVE_LOW>; + }; + + white { + label = "white"; + gpios = <&gpio 16 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/target/linux/ath79/dts/qcn5502_asus_zenwifi-cd6n.dts b/target/linux/ath79/dts/qcn5502_asus_zenwifi-cd6n.dts new file mode 100644 index 00000000000..426f203357d --- /dev/null +++ b/target/linux/ath79/dts/qcn5502_asus_zenwifi-cd6n.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcn5502_asus_zenwifi-cd6.dtsi" + +#include +#include + +/ { + compatible = "asus,zenwifi-cd6n", "qca,qcn5500", "qca,qca9560"; + model = "ASUS ZenWiFi CD6N"; +}; + +&mtdparts { + partition@60000 { + label = "firmware"; + reg = <0x060000 0xfa0000>; + compatible = "denx,uimage"; + }; +}; diff --git a/target/linux/ath79/dts/qcn5502_asus_zenwifi-cd6r.dts b/target/linux/ath79/dts/qcn5502_asus_zenwifi-cd6r.dts new file mode 100644 index 00000000000..b9c2ba0288c --- /dev/null +++ b/target/linux/ath79/dts/qcn5502_asus_zenwifi-cd6r.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcn5502_asus_zenwifi-cd6.dtsi" + +#include +#include + +/ { + compatible = "asus,zenwifi-cd6r", "qca,qcn5500", "qca,qca9560"; + model = "ASUS ZenWiFi CD6R"; +}; + +&mtdparts { + partition@60000 { + label = "firmware"; + reg = <0x060000 0x1fa0000>; + compatible = "denx,uimage"; + }; +}; diff --git a/target/linux/ath79/generic/base-files/etc/board.d/02_network b/target/linux/ath79/generic/base-files/etc/board.d/02_network index 1b12a21d0d9..ddcb69f68c9 100644 --- a/target/linux/ath79/generic/base-files/etc/board.d/02_network +++ b/target/linux/ath79/generic/base-files/etc/board.d/02_network @@ -152,6 +152,14 @@ ath79_setup_interfaces() ucidef_add_switch "switch0" \ "0@eth0" "1:lan:1" "2:lan:2" "3:lan:3" "6:lan:4" ;; + asus,zenwifi-cd6n) + ucidef_add_switch "switch0" \ + "0@eth0" "1:lan:1" "4:lan:2" + ;; + asus,zenwifi-cd6r) + ucidef_add_switch "switch0" \ + "0@eth0" "1:lan:2" "3:lan:1" "4:lan:3" "2:wan" + ;; atheros,db120) ucidef_add_switch "switch0" \ "0@eth0" "2:lan" "3:lan" "4:lan" "5:lan" "1:wan" @@ -381,6 +389,8 @@ ath79_setup_interfaces() ucidef_add_switch "switch0" \ "0@eth1" "1:lan" ;; + asus,rt-ac59u|\ + asus,rt-ac59u-v2|\ mercury,mw4530r-v1|\ tplink,archer-a7-v5|\ tplink,archer-a9-v6|\ diff --git a/target/linux/ath79/image/generic.mk b/target/linux/ath79/image/generic.mk index b32a09f34b5..59cc3c5a2b3 100644 --- a/target/linux/ath79/image/generic.mk +++ b/target/linux/ath79/image/generic.mk @@ -483,6 +483,70 @@ define Device/asus_rp-ac66 endef TARGET_DEVICES += asus_rp-ac66 +define Device/asus_qcn5502 + SOC := qcn5502 + DEVICE_VENDOR := ASUS + DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca9888-ct + KERNEL_INITRAMFS := kernel-bin | append-dtb | uImage none + IMAGES += factory.bin + IMAGE/factory.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | \ + append-rootfs | pad-rootfs +endef + +define Device/asus_rt-ac59u + $(Device/asus_qcn5502) + DEVICE_MODEL := RT-AC59U + DEVICE_ALT0_VENDOR := ASUS + DEVICE_ALT0_MODEL := RT-AC1200GE + DEVICE_ALT1_VENDOR := ASUS + DEVICE_ALT1_MODEL := RT-AC1500G PLUS + DEVICE_ALT2_VENDOR := ASUS + DEVICE_ALT2_MODEL := RT-AC1500UHP + DEVICE_ALT3_VENDOR := ASUS + DEVICE_ALT3_MODEL := RT-AC57U + DEVICE_ALT3_VARIANT := v2 + DEVICE_ALT4_VENDOR := ASUS + DEVICE_ALT4_MODEL := RT-AC58U + DEVICE_ALT4_VARIANT := v2 + DEVICE_ALT5_VENDOR := ASUS + DEVICE_ALT5_MODEL := RT-ACRH12 + IMAGE_SIZE := 16000k + DEVICE_PACKAGES += kmod-usb2 kmod-usb-ledtrig-usbport +endef +TARGET_DEVICES += asus_rt-ac59u + +define Device/asus_rt-ac59u-v2 + $(Device/asus_qcn5502) + DEVICE_MODEL := RT-AC59U + DEVICE_VARIANT := v2 + DEVICE_ALT0_VENDOR := ASUS + DEVICE_ALT0_MODEL := RT-AC1300G PLUS + DEVICE_ALT0_VARIANT := v3 + DEVICE_ALT1_VENDOR := ASUS + DEVICE_ALT1_MODEL := RT-AC57U + DEVICE_ALT1_VARIANT := v3 + DEVICE_ALT2_VENDOR := ASUS + DEVICE_ALT2_MODEL := RT-AC58U + DEVICE_ALT2_VARIANT := v3 + IMAGE_SIZE := 32384k + DEVICE_PACKAGES += kmod-usb2 kmod-usb-ledtrig-usbport +endef +TARGET_DEVICES += asus_rt-ac59u-v2 + +define Device/asus_zenwifi-cd6n + $(Device/asus_qcn5502) + DEVICE_MODEL := ZenWiFi CD6N + IMAGE_SIZE := 16000k +endef +TARGET_DEVICES += asus_zenwifi-cd6n + +define Device/asus_zenwifi-cd6r + $(Device/asus_qcn5502) + DEVICE_MODEL := ZenWiFi CD6R + IMAGE_SIZE := 32384k +endef +TARGET_DEVICES += asus_zenwifi-cd6r + define Device/atheros_db120 $(Device/loader-okli-uimage) SOC := ar9344 From 98e3f82c3fb729c1d9de78fef215322528b50cb4 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Mon, 12 Jun 2023 04:06:40 +0100 Subject: [PATCH 51/53] uboot-mediatek: support classic uImage.FIT with internal images in imszb The side-effect and main motivation is to also drop the FIT structure size limit because with multiple device tree overlays it may easily grow beyond the previous 4kB limit in the future. Signed-off-by: Daniel Golle --- .../patches/200-cmd-add-imsz-and-imszb.patch | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch b/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch index 7cf0778e47d..fcbb6b28a06 100644 --- a/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch +++ b/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch @@ -70,7 +70,7 @@ { --- a/boot/image-fit.c +++ b/boot/image-fit.c -@@ -2051,6 +2051,50 @@ static const char *fit_get_image_type_pr +@@ -2051,6 +2051,49 @@ static const char *fit_get_image_type_pr return "unknown"; } @@ -89,9 +89,8 @@ + + hdrsize = fdt_totalsize(fit); + -+ /* simple FIT with internal images */ -+ if (hdrsize > 0x1000) -+ return hdrsize; ++ /* take care of simple FIT with internal images */ ++ max_size = hdrsize; + + images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH); + if (images_noffset < 0) { From 83aeb0bbd47638b42ee6cdda351d0c51e014d790 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Mon, 10 Jul 2023 11:38:01 +0200 Subject: [PATCH 52/53] bcm47xx: fix bgmac MTU patch filename MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes: 4970dd027bce ("bcm47xx: revert bgmac back to the old limited max frame size") Signed-off-by: Rafał Miłecki --- ...01-bgmac-reduce-max-frame-size-to-support-just-MTU-1500.patch} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename target/linux/bcm47xx/patches-5.15/{701-net-bgmac-connect-to-PHY-even-if-it-is-BGMAC_PHY_NOR.patch => 701-bgmac-reduce-max-frame-size-to-support-just-MTU-1500.patch} (100%) diff --git a/target/linux/bcm47xx/patches-5.15/701-net-bgmac-connect-to-PHY-even-if-it-is-BGMAC_PHY_NOR.patch b/target/linux/bcm47xx/patches-5.15/701-bgmac-reduce-max-frame-size-to-support-just-MTU-1500.patch similarity index 100% rename from target/linux/bcm47xx/patches-5.15/701-net-bgmac-connect-to-PHY-even-if-it-is-BGMAC_PHY_NOR.patch rename to target/linux/bcm47xx/patches-5.15/701-bgmac-reduce-max-frame-size-to-support-just-MTU-1500.patch From d54f3b2cfdbd34aa61ca67fd590eebfdf3db51cf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Mon, 10 Jul 2023 11:38:23 +0200 Subject: [PATCH 53/53] kernel: bgmac: fix regressed support for BCM53573 SoCs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Rafał Miłecki --- ...ne-turning-IRQs-off-to-avoid-SoC-han.patch | 45 +++++++++++++++++++ ...ne-turning-IRQs-off-to-avoid-SoC-han.patch | 45 +++++++++++++++++++ 2 files changed, 90 insertions(+) create mode 100644 target/linux/generic/backport-5.15/735-v6.5-net-bgmac-postpone-turning-IRQs-off-to-avoid-SoC-han.patch create mode 100644 target/linux/generic/backport-6.1/701-v6.5-net-bgmac-postpone-turning-IRQs-off-to-avoid-SoC-han.patch diff --git a/target/linux/generic/backport-5.15/735-v6.5-net-bgmac-postpone-turning-IRQs-off-to-avoid-SoC-han.patch b/target/linux/generic/backport-5.15/735-v6.5-net-bgmac-postpone-turning-IRQs-off-to-avoid-SoC-han.patch new file mode 100644 index 00000000000..26e9ae3bcd2 --- /dev/null +++ b/target/linux/generic/backport-5.15/735-v6.5-net-bgmac-postpone-turning-IRQs-off-to-avoid-SoC-han.patch @@ -0,0 +1,45 @@ +From e7731194fdf085f46d58b1adccfddbd0dfee4873 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Fri, 7 Jul 2023 08:53:25 +0200 +Subject: [PATCH] net: bgmac: postpone turning IRQs off to avoid SoC hangs +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Turning IRQs off is done by accessing Ethernet controller registers. +That can't be done until device's clock is enabled. It results in a SoC +hang otherwise. + +This bug remained unnoticed for years as most bootloaders keep all +Ethernet interfaces turned on. It seems to only affect a niche SoC +family BCM47189. It has two Ethernet controllers but CFE bootloader uses +only the first one. + +Fixes: 34322615cbaa ("net: bgmac: Mask interrupts during probe") +Signed-off-by: Rafał Miłecki +Reviewed-by: Michal Kubiak +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/broadcom/bgmac.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -1492,8 +1492,6 @@ int bgmac_enet_probe(struct bgmac *bgmac + + bgmac->in_init = true; + +- bgmac_chip_intrs_off(bgmac); +- + net_dev->irq = bgmac->irq; + SET_NETDEV_DEV(net_dev, bgmac->dev); + dev_set_drvdata(bgmac->dev, bgmac); +@@ -1511,6 +1509,8 @@ int bgmac_enet_probe(struct bgmac *bgmac + */ + bgmac_clk_enable(bgmac, 0); + ++ bgmac_chip_intrs_off(bgmac); ++ + /* This seems to be fixing IRQ by assigning OOB #6 to the core */ + if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK)) { + if (bgmac->feature_flags & BGMAC_FEAT_IRQ_ID_OOB_6) diff --git a/target/linux/generic/backport-6.1/701-v6.5-net-bgmac-postpone-turning-IRQs-off-to-avoid-SoC-han.patch b/target/linux/generic/backport-6.1/701-v6.5-net-bgmac-postpone-turning-IRQs-off-to-avoid-SoC-han.patch new file mode 100644 index 00000000000..26e9ae3bcd2 --- /dev/null +++ b/target/linux/generic/backport-6.1/701-v6.5-net-bgmac-postpone-turning-IRQs-off-to-avoid-SoC-han.patch @@ -0,0 +1,45 @@ +From e7731194fdf085f46d58b1adccfddbd0dfee4873 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Fri, 7 Jul 2023 08:53:25 +0200 +Subject: [PATCH] net: bgmac: postpone turning IRQs off to avoid SoC hangs +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Turning IRQs off is done by accessing Ethernet controller registers. +That can't be done until device's clock is enabled. It results in a SoC +hang otherwise. + +This bug remained unnoticed for years as most bootloaders keep all +Ethernet interfaces turned on. It seems to only affect a niche SoC +family BCM47189. It has two Ethernet controllers but CFE bootloader uses +only the first one. + +Fixes: 34322615cbaa ("net: bgmac: Mask interrupts during probe") +Signed-off-by: Rafał Miłecki +Reviewed-by: Michal Kubiak +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/broadcom/bgmac.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -1492,8 +1492,6 @@ int bgmac_enet_probe(struct bgmac *bgmac + + bgmac->in_init = true; + +- bgmac_chip_intrs_off(bgmac); +- + net_dev->irq = bgmac->irq; + SET_NETDEV_DEV(net_dev, bgmac->dev); + dev_set_drvdata(bgmac->dev, bgmac); +@@ -1511,6 +1509,8 @@ int bgmac_enet_probe(struct bgmac *bgmac + */ + bgmac_clk_enable(bgmac, 0); + ++ bgmac_chip_intrs_off(bgmac); ++ + /* This seems to be fixing IRQ by assigning OOB #6 to the core */ + if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK)) { + if (bgmac->feature_flags & BGMAC_FEAT_IRQ_ID_OOB_6)