Merge branch 'openwrt:master' into master

config/Config-kernel.in

@@ -1184,21 +1184,6 @@ config KERNEL_XDP_SOCKETS
 	  XDP sockets allows a channel between XDP programs and
 	  userspace applications.
 
-config KERNEL_WIRELESS_EXT
-	def_bool n
-
-config KERNEL_WEXT_CORE
-	def_bool KERNEL_WIRELESS_EXT
-
-config KERNEL_WEXT_PRIV
-	def_bool KERNEL_WIRELESS_EXT
-
-config KERNEL_WEXT_PROC
-	def_bool KERNEL_WIRELESS_EXT
-
-config KERNEL_WEXT_SPY
-	def_bool KERNEL_WIRELESS_EXT
-
 config KERNEL_PAGE_POOL
 	def_bool n
 

include/image-commands.mk

@@ -152,6 +152,20 @@ define Build/append-ubi
 		$(call Build/check-size,$(UBI_NAND_SIZE_LIMIT)))
 endef
 
+define Build/ubinize-image
+	sh $(TOPDIR)/scripts/ubinize-image.sh \
+		$(if $(UBOOTENV_IN_UBI),--uboot-env) \
+		$(foreach part,$(UBINIZE_PARTS),--part $(part)) \
+		--part $(word 1,$(1))="$(BIN_DIR)/$(DEVICE_IMG_PREFIX)-$(word 2,$(1))" \
+		$@.tmp \
+		-p $(BLOCKSIZE:%k=%KiB) -m $(PAGESIZE) \
+		$(if $(SUBPAGESIZE),-s $(SUBPAGESIZE)) \
+		$(if $(VID_HDR_OFFSET),-O $(VID_HDR_OFFSET)) \
+		$(UBINIZE_OPTS)
+	cat $@.tmp >> $@
+	rm $@.tmp
+endef
+
 define Build/ubinize-kernel
 	cp $@ $@.tmp
 	sh $(TOPDIR)/scripts/ubinize-image.sh \

include/image.mk

@@ -582,7 +582,7 @@ define Device/Build/dtb
   $(KDIR)/image-$(1).dtb: FORCE
 	$(call Image/BuildDTB,$(strip $(2))/$(strip $(3)).dts,$$@)
 
-  image_prepare: $(KDIR)/image-$(1).dtb
+  compile-dtb: $(KDIR)/image-$(1).dtb
   endif
 
 endef
@@ -593,7 +593,7 @@ define Device/Build/dtbo
   $(KDIR)/image-$(1).dtbo: FORCE
 	$(call Image/BuildDTBO,$(strip $(2))/$(strip $(3)).dtso,$$@)
 
-  image_prepare: $(KDIR)/image-$(1).dtbo
+  compile-dtb: $(KDIR)/image-$(1).dtbo
   endif
 
 endef
@@ -841,18 +841,20 @@ define BuildImage
   download:
   prepare:
   compile:
+  compile-dtb:
   clean:
   image_prepare:
 
   ifeq ($(IB),)
-    .PHONY: download prepare compile clean image_prepare kernel_prepare install install-images
+    .PHONY: download prepare compile compile-dtb clean image_prepare kernel_prepare install install-images
     compile:
 		$(call Build/Compile)
 
     clean:
 		$(call Build/Clean)
 
-    image_prepare: compile
+    compile-dtb:
+    image_prepare: compile compile-dtb
 		mkdir -p $(BIN_DIR) $(KDIR)/tmp
 		rm -rf $(BUILD_DIR)/json_info_files
 		$(call Image/Prepare)

include/kernel-5.15

@@ -1,2 +1,2 @@
-LINUX_VERSION-5.15 = .147
+LINUX_VERSION-5.15 = .148
-LINUX_KERNEL_HASH-5.15.147 = 56c1e65625d201db431efda7a3816e7b424071e7cb0245b2ba594d15b1fdfcd4
+LINUX_KERNEL_HASH-5.15.148 = c48575c97fd9f4767cbe50a13b1b2b40ee42830aba3182fabd35a03259a6e5d8

include/kernel-6.1

@@ -1,2 +1,2 @@
-LINUX_VERSION-6.1 = .74
+LINUX_VERSION-6.1 = .79
-LINUX_KERNEL_HASH-6.1.74 = b7fbd1d79faed2ce3570ef79dc1223e4e19c868b86326b14a435db56ebbb2022
+LINUX_KERNEL_HASH-6.1.79 = faa49ca22fb55ed4d5ca2a55e07dd10e4e171cfc3b92568a631453cd2068b39b

include/kernel-build.mk

@@ -156,6 +156,10 @@ define BuildKernel
   compile: $(LINUX_DIR)/.modules
 	$(MAKE) -C image compile TARGET_BUILD=
 
+  dtb: $(STAMP_CONFIGURED)
+	$(_SINGLE)$(KERNEL_MAKE) scripts_dtc
+	$(MAKE) -C image compile-dtb TARGET_BUILD=
+
   oldconfig menuconfig nconfig xconfig: $(STAMP_PREPARED) $(STAMP_CHECKED) FORCE
 	rm -f $(LINUX_DIR)/.config.prev
 	rm -f $(STAMP_CONFIGURED)

include/package-defaults.mk

@@ -20,7 +20,7 @@ define Package/Default
   PROVIDES:=
   EXTRA_DEPENDS:=
   MAINTAINER:=$(PKG_MAINTAINER)
-  SOURCE:=$(patsubst $(TOPDIR)/%,%,$(CURDIR))
+  SOURCE:=$(patsubst $(TOPDIR)/%,%,$(patsubst $(TOPDIR)/package/%,feeds/base/%,$(CURDIR)))
   ifneq ($(PKG_VERSION),)
     ifneq ($(PKG_RELEASE),)
       VERSION:=$(PKG_VERSION)-$(PKG_RELEASE)

include/rootfs.mk

@@ -87,6 +87,11 @@ define prepare_rootfs
 			fi; \
 		done || true \
 	)
+	awk -i inplace \
+		'/^Status:/ { \
+			if ($$3 == "user") { $$3 = "ok" } \
+			else { sub(/,\<user\>|\<user\>,/, "", $$3) } \
+		}1' $(1)/usr/lib/opkg/status
 	$(if $(SOURCE_DATE_EPOCH),sed -i "s/Installed-Time: .*/Installed-Time: $(SOURCE_DATE_EPOCH)/" $(1)/usr/lib/opkg/status)
 	@-find $(1) -name CVS -o -name .svn -o -name .git -o -name '.#*' | $(XARGS) rm -rf
 	rm -rf \

include/subdir.mk

@@ -5,6 +5,9 @@
 ifeq ($(MAKECMDGOALS),prereq)
   SUBTARGETS:=prereq
   PREREQ_ONLY:=1
+# For target/linux related target add dtb to selectively compile dtbs
+else ifneq ($(filter target/linux/%,$(MAKECMDGOALS)),)
+  SUBTARGETS:=$(DEFAULT_SUBDIR_TARGETS) dtb
 else
   SUBTARGETS:=$(DEFAULT_SUBDIR_TARGETS)
 endif

include/toplevel.mk

@@ -77,7 +77,8 @@ _ignore = $(foreach p,$(IGNORE_PACKAGES),--ignore $(p))
 
 prepare-tmpinfo: FORCE
 	@+$(MAKE) -r -s $(STAGING_DIR_HOST)/.prereq-build $(PREP_MK)
-	mkdir -p tmp/info
+	mkdir -p tmp/info feeds
+	[ -e $(TOPDIR)/feeds/base ] || ln -sf $(TOPDIR)/package $(TOPDIR)/feeds/base
 	$(_SINGLE)$(NO_TRACE_MAKE) -j1 -r -s -f include/scan.mk SCAN_TARGET="packageinfo" SCAN_DIR="package" SCAN_NAME="package" SCAN_DEPTH=5 SCAN_EXTRA=""
 	$(_SINGLE)$(NO_TRACE_MAKE) -j1 -r -s -f include/scan.mk SCAN_TARGET="targetinfo" SCAN_DIR="target/linux" SCAN_NAME="target" SCAN_DEPTH=3 SCAN_EXTRA="" SCAN_MAKEOPTS="TARGET_BUILD=1"
 	for type in package target; do \

package/base-files/files/etc/init.d/led

@@ -3,6 +3,39 @@
 
 START=96
 
+led_color_set() {
+	local cfg="$1"
+	local sysfs="$2"
+
+	local max_b
+	local colors
+	local color
+	local multi_intensity
+	local value
+	local write
+
+	[ -e /sys/class/leds/${sysfs}/multi_intensity ] || return
+	[ -e /sys/class/leds/${sysfs}/multi_index ] || return
+
+	max_b="$(cat /sys/class/leds/${sysfs}/max_brightness)"
+	colors="$(cat /sys/class/leds/${sysfs}/multi_index | tr " " "\n")"
+	multi_intensity=""
+	for color in $colors; do
+		config_get value $1 "color_${color}" "0"
+		[ "$value" -gt 0 ] && write=1
+		[ "$value" -gt "$max_b" ] && value="$max_b"
+		multi_intensity="${multi_intensity}${value} "
+	done
+
+	# Check if any color is configured
+	[ "$write" = 1 ] || return
+	# Remove last whitespace
+	multi_intensity="${multi_intensity:0:-1}"
+
+	echo "setting '${name}' led color to '${multi_intensity}'"
+	echo "${multi_intensity}" > /sys/class/leds/${sysfs}/multi_intensity
+}
+
 load_led() {
 	local name
 	local sysfs
@@ -49,21 +82,29 @@ load_led() {
 	[ -e /sys/class/leds/${sysfs}/brightness ] && {
 		echo "setting up led ${name}"
 
-		printf "%s %s %d\n" \
+		printf "%s %s %d" \
 			"$sysfs" \
 			"$(sed -ne 's/^.*\[\(.*\)\].*$/\1/p' /sys/class/leds/${sysfs}/trigger)" \
 			"$(cat /sys/class/leds/${sysfs}/brightness)" \
 				>> /var/run/led.state
+		# Save default color if supported
+		[ -e /sys/class/leds/${sysfs}/multi_intensity ] && {
+			printf " %s" \
+				"$(sed 's/\ /:/g' /sys/class/leds/${sysfs}/multi_intensity)" \
+				>> /var/run/led.state
+		}
+		printf "\n" >> /var/run/led.state
 
 		[ "$default" = 0 ] &&
 			echo 0 >/sys/class/leds/${sysfs}/brightness
 
-		echo $trigger > /sys/class/leds/${sysfs}/trigger 2> /dev/null
-		ret="$?"
-
 		[ $default = 1 ] &&
 			cat /sys/class/leds/${sysfs}/max_brightness > /sys/class/leds/${sysfs}/brightness
 
+		led_color_set "$1" "$sysfs"
+
+		echo $trigger > /sys/class/leds/${sysfs}/trigger 2> /dev/null
+		ret="$?"
 		[ $ret = 0 ] || {
 			echo >&2 "Skipping trigger '$trigger' for led '$name' due to missing kernel module"
 			return 1
@@ -128,13 +169,17 @@ load_led() {
 start() {
 	[ -e /sys/class/leds/ ] && {
 		[ -s /var/run/led.state ] && {
-			local led trigger brightness
+			local led trigger brightness color
-			while read led trigger brightness; do
+			while read led trigger brightness color; do
 				[ -e "/sys/class/leds/$led/trigger" ] && \
 					echo "$trigger" > "/sys/class/leds/$led/trigger"
 
 				[ -e "/sys/class/leds/$led/brightness" ] && \
 					echo "$brightness" > "/sys/class/leds/$led/brightness"
+
+				[ -e "/sys/class/leds/$led/multi_intensity" ] && \
+					echo "$color" | sed 's/:/\ /g' > \
+						"/sys/class/leds/$led/multi_intensity"
 			done < /var/run/led.state
 			rm /var/run/led.state
 		}

package/base-files/files/lib/functions/uci-defaults.sh

@@ -654,6 +654,17 @@ ucidef_set_ntpserver() {
 	json_select ..
 }
 
+ucidef_set_poe() {
+	json_select_object poe
+		json_add_string "budget" "$1"
+		json_select_array ports
+			for port in $2; do
+				json_add_string "" "$port"
+			done
+		json_select ..
+	json_select ..
+}
+
 ucidef_add_wlan() {
 	local path="$1"; shift
 

package/base-files/files/lib/upgrade/common.sh

@@ -165,6 +165,23 @@ part_magic_fat() {
 	[ "$magic" = "FAT" ] || [ "$magic_fat32" = "FAT32" ]
 }
 
+fitblk_get_bootdev() {
+	[ -e /sys/firmware/devicetree/base/chosen/rootdisk ] || return
+
+	local rootdisk="$(cat /sys/firmware/devicetree/base/chosen/rootdisk)"
+	local handle bootdev
+	for handle in /sys/class/block/*/of_node/phandle /sys/class/block/*/device/of_node/phandle; do
+		[ ! -e "$handle" ] && continue
+		if [ "$rootdisk" = "$(cat $handle)" ]; then
+			bootdev="${handle%/of_node/phandle}"
+			bootdev="${bootdev%/device}"
+			bootdev="${bootdev#/sys/class/block/}"
+			echo "$bootdev"
+			break
+		fi
+	done
+}
+
 export_bootdevice() {
 	local cmdline uuid blockdev uevent line class
 	local MAJOR MINOR DEVNAME DEVTYPE
@@ -196,6 +213,7 @@ export_bootdevice() {
 			done
 		;;
 		/dev/*)
+			[ "$rootpart" = "/dev/fit0" ] && rootpart="$(fitblk_get_bootdev)"
 			uevent="/sys/class/block/${rootpart##*/}/../uevent"
 		;;
 		0x[a-f0-9][a-f0-9][a-f0-9] | 0x[a-f0-9][a-f0-9][a-f0-9][a-f0-9] | \

package/base-files/files/lib/upgrade/nand.sh

@@ -111,7 +111,7 @@ nand_remove_ubiblock() {
 
 	local ubiblk="ubiblock${ubivol:3}"
 	if [ -e "/dev/$ubiblk" ]; then
-		umount "/dev/$ubiblk" && echo "unmounted /dev/$ubiblk" || :
+		umount "/dev/$ubiblk" 2>/dev/null && echo "unmounted /dev/$ubiblk" || :
 		if ! ubiblock -r "/dev/$ubivol"; then
 			echo "cannot remove $ubiblk"
 			return 1

package/base-files/files/sbin/sysupgrade

@@ -4,27 +4,35 @@
 . /lib/functions/system.sh
 . /usr/share/libubox/jshn.sh
 
-# initialize defaults
+# File-local constants
+CONF_TAR=/tmp/sysupgrade.tgz
+ETCBACKUP_DIR=/etc/backup
+INSTALLED_PACKAGES=${ETCBACKUP_DIR}/installed_packages.txt
+COMMAND=/lib/upgrade/do_stage2
+
+# File-local globals
+SAVE_OVERLAY=0
+SAVE_OVERLAY_PATH=
+SAVE_PARTITIONS=1
+SAVE_INSTALLED_PKGS=0
+SKIP_UNCHANGED=0
+CONF_IMAGE=
+CONF_BACKUP_LIST=0
+CONF_BACKUP=
+CONF_RESTORE=
+NEED_IMAGE=
+HELP=0
+TEST=0
+
+# Globals accessed in other files
 export MTD_ARGS=""
 export MTD_CONFIG_ARGS=""
 export INTERACTIVE=0
 export VERBOSE=1
 export SAVE_CONFIG=1
-export SAVE_OVERLAY=0
-export SAVE_OVERLAY_PATH=
-export SAVE_PARTITIONS=1
-export SAVE_INSTALLED_PKGS=0
-export SKIP_UNCHANGED=0
-export CONF_IMAGE=
-export CONF_BACKUP_LIST=0
-export CONF_BACKUP=
-export CONF_RESTORE=
 export IGNORE_MINOR_COMPAT=0
-export NEED_IMAGE=
-export HELP=0
 export FORCE=0
-export TEST=0
+export CONFFILES=/tmp/sysupgrade.conffiles
-export UMOUNT_ETCBACKUP_DIR=0
 
 # parse options
 while [ -n "$1" ]; do
@@ -33,18 +41,18 @@ while [ -n "$1" ]; do
 		-v) export VERBOSE="$(($VERBOSE + 1))";;
 		-q) export VERBOSE="$(($VERBOSE - 1))";;
 		-n) export SAVE_CONFIG=0;;
-		-c) export SAVE_OVERLAY=1 SAVE_OVERLAY_PATH=/etc;;
+		-c) SAVE_OVERLAY=1 SAVE_OVERLAY_PATH=/etc;;
-		-o) export SAVE_OVERLAY=1 SAVE_OVERLAY_PATH=/;;
+		-o) SAVE_OVERLAY=1 SAVE_OVERLAY_PATH=/;;
-		-p) export SAVE_PARTITIONS=0;;
+		-p) SAVE_PARTITIONS=0;;
-		-k) export SAVE_INSTALLED_PKGS=1;;
+		-k) SAVE_INSTALLED_PKGS=1;;
-		-u) export SKIP_UNCHANGED=1;;
+		-u) SKIP_UNCHANGED=1;;
-		-b|--create-backup) export CONF_BACKUP="$2" NEED_IMAGE=1; shift;;
+		-b|--create-backup) CONF_BACKUP="$2" NEED_IMAGE=1; shift;;
-		-r|--restore-backup) export CONF_RESTORE="$2" NEED_IMAGE=1; shift;;
+		-r|--restore-backup) CONF_RESTORE="$2" NEED_IMAGE=1; shift;;
-		-l|--list-backup) export CONF_BACKUP_LIST=1;;
+		-l|--list-backup) CONF_BACKUP_LIST=1;;
-		-f) export CONF_IMAGE="$2"; shift;;
+		-f) CONF_IMAGE="$2"; shift;;
 		-F|--force) export FORCE=1;;
-		-T|--test) export TEST=1;;
+		-T|--test) TEST=1;;
-		-h|--help) export HELP=1; break;;
+		-h|--help) HELP=1; break;;
 		--ignore-minor-compat-version) export IGNORE_MINOR_COMPAT=1;;
 		-*)
 			echo "Invalid option: $1" >&2
@@ -55,14 +63,7 @@ while [ -n "$1" ]; do
 	shift;
 done
 
-export CONFFILES=/tmp/sysupgrade.conffiles
+print_help() {
-export CONF_TAR=/tmp/sysupgrade.tgz
-export ETCBACKUP_DIR=/etc/backup
-export INSTALLED_PACKAGES=${ETCBACKUP_DIR}/installed_packages.txt
-
-IMAGE="$1"
-
-[ -z "$IMAGE" -a -z "$NEED_IMAGE" -a $CONF_BACKUP_LIST -eq 0 -o $HELP -gt 0 ] && {
 	cat <<EOF
 Usage: $0 [<upgrade-option>...] <image file or URL>
        $0 [-q] [-i] [-c] [-u] [-o] [-k] <backup-command> <file>
@@ -102,9 +103,20 @@ backup-command:
 	             sysupgrade -b. Does not create a backup file.
 
 EOF
-	exit 1
 }
 
+IMAGE="$1"
+
+if [ $HELP -gt 0 ]; then
+	print_help
+	exit 0
+fi
+
+if [ -z "$IMAGE" -a -z "$NEED_IMAGE" -a $CONF_BACKUP_LIST -eq 0 ]; then
+	print_help
+	exit 1
+fi
+
 [ -n "$IMAGE" -a -n "$NEED_IMAGE" ] && {
 	cat <<-EOF
 		-b|--create-backup and -r|--restore-backup do not perform a firmware upgrade.
@@ -143,7 +155,7 @@ list_static_conffiles() {
 		\( -type f -o -type l \) $filter 2>/dev/null
 }
 
-add_conffiles() {
+build_list_of_backup_config_files() {
 	local file="$1"
 
 	( list_static_conffiles "$find_filter"; list_changed_conffiles ) |
@@ -151,7 +163,7 @@ add_conffiles() {
 	return 0
 }
 
-add_overlayfiles() {
+build_list_of_backup_overlay_files() {
 	local file="$1"
 
 	local packagesfiles=$1.packagesfiles
@@ -203,12 +215,12 @@ add_overlayfiles() {
 
 if [ $SAVE_OVERLAY = 1 ]; then
 	[ ! -d /overlay/upper/etc ] && {
-		echo "Cannot find '/overlay/upper/etc', required for '-c'" >&2
+		echo "Cannot find '/overlay/upper/etc', required for '-c' or '-o'" >&2
 		exit 1
 	}
-	sysupgrade_init_conffiles="add_overlayfiles"
+	sysupgrade_init_conffiles="build_list_of_backup_overlay_files"
 else
-	sysupgrade_init_conffiles="add_conffiles"
+	sysupgrade_init_conffiles="build_list_of_backup_config_files"
 fi
 
 find_filter=""
@@ -222,9 +234,11 @@ fi
 
 include /lib/upgrade
 
-do_save_conffiles() {
+create_backup_archive() {
 	local conf_tar="$1"
 
+	local umount_etcbackup_dir=0
+
 	[ "$(rootfs_type)" = "tmpfs" ] && {
 		echo "Cannot save config while running from ramdisk." >&2
 		ask_bool 0 "Abort" && exit
@@ -241,12 +255,12 @@ do_save_conffiles() {
 		RAMFS="$(mktemp -d -t sysupgrade.XXXXXX)"
 		mkdir -p "$RAMFS/upper" "$RAMFS/work"
 		mount -t overlay overlay -o lowerdir=$ETCBACKUP_DIR,upperdir=$RAMFS/upper,workdir=$RAMFS/work $ETCBACKUP_DIR &&
-			UMOUNT_ETCBACKUP_DIR=1 || {
+			umount_etcbackup_dir=1 || {
 				echo "Cannot mount '$ETCBACKUP_DIR' as tmpfs to avoid touching disk while saving the list of installed packages." >&2
 				ask_bool 0 "Abort" && exit
 			}
 
-		# Format: pkg-name<TAB>{rom,overlay,unkown}
+		# Format: pkg-name<TAB>{rom,overlay,unknown}
 		# rom is used for pkgs in /rom, even if updated later
 		find /usr/lib/opkg/info -name "*.control" \( \
 			\( -exec test -f /rom/{} \; -exec echo {} rom \; \) -o \
@@ -257,18 +271,21 @@ do_save_conffiles() {
 
 	v "Saving config files..."
 	[ "$VERBOSE" -gt 1 ] && TAR_V="v" || TAR_V=""
-	tar c${TAR_V}zf "$conf_tar" -T "$CONFFILES" 2>/dev/null
+	sed -i -e 's,^/,,' "$CONFFILES"
-	if [ "$?" -ne 0 ]; then
+	tar c${TAR_V}zf "$conf_tar" -C / -T "$CONFFILES"
+	local err=$?
+	if [ "$err" -ne 0 ]; then
 		echo "Failed to create the configuration backup."
 		rm -f "$conf_tar"
-		exit 1
 	fi
 
-	[ "$UMOUNT_ETCBACKUP_DIR" -eq 1 ] && {
+	[ "$umount_etcbackup_dir" -eq 1 ] && {
 		umount "$ETCBACKUP_DIR"
 		rm -rf "$RAMFS"
 	}
 	rm -f "$CONFFILES"
+
+	return "$err"
 }
 
 if [ $CONF_BACKUP_LIST -eq 1 ]; then
@@ -280,8 +297,8 @@ if [ $CONF_BACKUP_LIST -eq 1 ]; then
 fi
 
 if [ -n "$CONF_BACKUP" ]; then
-	do_save_conffiles "$CONF_BACKUP"
+	create_backup_archive "$CONF_BACKUP"
-	exit $?
+	exit
 fi
 
 if [ -n "$CONF_RESTORE" ]; then
@@ -350,7 +367,7 @@ if [ -n "$CONF_IMAGE" ]; then
 	get_image "$CONF_IMAGE" "cat" > "$CONF_TAR"
 	export SAVE_CONFIG=1
 elif ask_bool $SAVE_CONFIG "Keep config files over reflash"; then
-	[ $TEST -eq 1 ] || do_save_conffiles "$CONF_TAR"
+	[ $TEST -eq 1 ] || create_backup_archive "$CONF_TAR" || exit
 	export SAVE_CONFIG=1
 else
 	[ $TEST -eq 1 ] || rm -f "$CONF_TAR"
@@ -364,8 +381,6 @@ fi
 install_bin /sbin/upgraded
 v "Commencing upgrade. Closing all shell sessions."
 
-COMMAND='/lib/upgrade/do_stage2'
-
 if [ -n "$FAILSAFE" ]; then
 	printf '%s\x00%s\x00%s' "$RAM_ROOT" "$IMAGE" "$COMMAND" >/tmp/sysupgrade
 	lock -u /tmp/.failsafe

package/boot/arm-trusted-firmware-mediatek/Makefile

@@ -26,12 +26,14 @@ include $(INCLUDE_DIR)/package.mk
 define Trusted-Firmware-A/Default
   BUILD_TARGET:=mediatek
   TFA_IMAGE:=bl2.img bl31.bin
+  HIDDEN:=y
   BOOT_DEVICE:=
   DDR3_FLYBY:=
   DDR_TYPE:=
   NAND_TYPE:=
   BOARD_QFN:=
   DRAM_USE_COMB:=
+  USE_UBI:=
 endef
 
 define Trusted-Firmware-A/mt7622-nor-1ddr
@@ -56,6 +58,14 @@ define Trusted-Firmware-A/mt7622-snand-1ddr
   BOOT_DEVICE:=snand
 endef
 
+define Trusted-Firmware-A/mt7622-snand-ubi-1ddr
+  NAME:=MediaTek MT7622 (SPI-NAND using UBI, 1x DDR3)
+  BUILD_SUBTARGET:=mt7622
+  PLAT:=mt7622
+  BOOT_DEVICE:=snand
+  USE_UBI:=1
+endef
+
 define Trusted-Firmware-A/mt7622-snand-2ddr
   NAME:=MediaTek MT7622 (SPI-NAND, 2x DDR3)
   BUILD_SUBTARGET:=mt7622
@@ -64,6 +74,15 @@ define Trusted-Firmware-A/mt7622-snand-2ddr
   DDR3_FLYBY:=1
 endef
 
+define Trusted-Firmware-A/mt7622-snand-ubi-2ddr
+  NAME:=MediaTek MT7622 (SPI-NAND using UBI, 2x DDR3)
+  BUILD_SUBTARGET:=mt7622
+  PLAT:=mt7622
+  BOOT_DEVICE:=snand
+  DDR3_FLYBY:=1
+  USE_UBI:=1
+endef
+
 define Trusted-Firmware-A/mt7622-emmc-1ddr
   NAME:=MediaTek MT7622 (eMMC, 1x DDR3)
   BUILD_SUBTARGET:=mt7622
@@ -191,6 +210,16 @@ define Trusted-Firmware-A/mt7986-spim-nand-ddr4
   NAND_TYPE:=spim:2k+64
 endef
 
+define Trusted-Firmware-A/mt7986-spim-nand-ubi-ddr4
+  NAME:=MediaTek MT7986 (SPI-NAND via SPIM using UBI, DDR4)
+  BOOT_DEVICE:=spim-nand
+  BUILD_SUBTARGET:=filogic
+  PLAT:=mt7986
+  DDR_TYPE:=ddr4
+  NAND_TYPE:=spim:2k+64
+  USE_UBI:=1
+endef
+
 define Trusted-Firmware-A/mt7986-spim-nand-4k-ddr4
   NAME:=MediaTek MT7986 (SPI-NAND via SPIM, DDR4)
   BOOT_DEVICE:=spim-nand
@@ -352,6 +381,15 @@ define Trusted-Firmware-A/mt7988-snand-comb
   DRAM_USE_COMB:=1
 endef
 
+define Trusted-Firmware-A/mt7988-snand-ubi-comb
+  NAME:=MediaTek MT7988 (SPI-NAND via SNFI, UBI)
+  BOOT_DEVICE:=snand
+  BUILD_SUBTARGET:=filogic
+  PLAT:=mt7988
+  DRAM_USE_COMB:=1
+  USE_UBI:=1
+endef
+
 define Trusted-Firmware-A/mt7988-spim-nand-comb
   NAME:=MediaTek MT7988 (SPI-NAND via SPIM)
   BOOT_DEVICE:=spim-nand
@@ -360,11 +398,22 @@ define Trusted-Firmware-A/mt7988-spim-nand-comb
   DRAM_USE_COMB:=1
 endef
 
+define Trusted-Firmware-A/mt7988-spim-nand-ubi-comb
+  NAME:=MediaTek MT7988 (SPI-NAND via SPIM, UBI)
+  BOOT_DEVICE:=spim-nand
+  BUILD_SUBTARGET:=filogic
+  PLAT:=mt7988
+  DRAM_USE_COMB:=1
+  USE_UBI:=1
+endef
+
 TFA_TARGETS:= \
 	mt7622-nor-1ddr \
 	mt7622-nor-2ddr \
 	mt7622-snand-1ddr \
+	mt7622-snand-ubi-1ddr \
 	mt7622-snand-2ddr \
+	mt7622-snand-ubi-2ddr \
 	mt7622-emmc-1ddr \
 	mt7622-emmc-2ddr \
 	mt7622-sdmmc-1ddr \
@@ -386,6 +435,7 @@ TFA_TARGETS:= \
 	mt7986-sdmmc-ddr4 \
 	mt7986-snand-ddr4 \
 	mt7986-spim-nand-ddr4 \
+	mt7986-spim-nand-ubi-ddr4 \
 	mt7986-spim-nand-4k-ddr4 \
 	mt7988-emmc-ddr3 \
 	mt7988-nor-ddr3 \
@@ -401,7 +451,9 @@ TFA_TARGETS:= \
 	mt7988-nor-comb \
 	mt7988-sdmmc-comb \
 	mt7988-snand-comb \
-	mt7988-spim-nand-comb
+	mt7988-snand-ubi-comb \
+	mt7988-spim-nand-comb \
+	mt7988-spim-nand-ubi-comb
 
 TFA_MAKE_FLAGS += \
 	BOOT_DEVICE=$(BOOT_DEVICE) \
@@ -412,6 +464,7 @@ TFA_MAKE_FLAGS += \
 	HAVE_DRAM_OBJ_FILE=yes \
 	$(if $(DDR3_FLYBY),DDR3_FLYBY=1) \
 	$(if $(DRAM_USE_COMB),DRAM_USE_COMB=1) \
+	$(if $(USE_UBI),UBI=1 $(if $(findstring mt7622,$(PLAT)),OVERRIDE_UBI_START_ADDR=0x80000)) \
 	all
 
 define Package/trusted-firmware-a/install

package/boot/kexec-tools/Makefile

@@ -8,12 +8,12 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=kexec-tools
-PKG_VERSION:=2.0.26
+PKG_VERSION:=2.0.28
 PKG_RELEASE:=1
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
 PKG_SOURCE_URL:=@KERNEL/linux/utils/kernel/kexec
-PKG_HASH:=7fe36a064101cd5c515e41b2be393dce3ca88adce59d6ee668e0af7c0c4570cd
+PKG_HASH:=d2f0ef872f39e2fe4b1b01feb62b0001383207239b9f8041f98a95564161d053
 
 PKG_CONFIG_DEPENDS := CONFIG_KEXEC_ZLIB CONFIG_KEXEC_LZMA
 

package/boot/rkbin/Makefile

@@ -25,6 +25,12 @@ define Trusted-Firmware-A/Default
   BUILD_TARGET:=rockchip
 endef
 
+define Trusted-Firmware-A/rk3566
+  BUILD_SUBTARGET:=armv8
+  ATF:=rk35/rk3568_bl31_v1.43.elf
+  TPL:=rk35/rk3566_ddr_1056MHz_v1.18.bin
+endef
+
 define Trusted-Firmware-A/rk3568
   BUILD_SUBTARGET:=armv8
   ATF:=rk35/rk3568_bl31_v1.43.elf
@@ -32,6 +38,7 @@ define Trusted-Firmware-A/rk3568
 endef
 
 TFA_TARGETS:= \
+	rk3566 \
 	rk3568
 
 define Build/Compile

package/boot/uboot-envtools/Makefile

@@ -9,15 +9,15 @@ include $(TOPDIR)/rules.mk
 
 PKG_NAME:=uboot-envtools
 PKG_DISTNAME:=u-boot
-PKG_VERSION:=2023.07.02
+PKG_VERSION:=2024.01
-PKG_RELEASE:=3
+PKG_RELEASE:=2
 
 PKG_SOURCE:=$(PKG_DISTNAME)-$(PKG_VERSION).tar.bz2
 PKG_SOURCE_URL:= \
     https://ftp.denx.de/pub/u-boot \
     https://mirror.cyberbits.eu/u-boot \
     ftp://ftp.denx.de/pub/u-boot
-PKG_HASH:=6b6a48581c14abb0f95bd87c1af4d740922406d7b801002a9f94727fdde021d5
+PKG_HASH:=b99611f1ed237bf3541bdc8434b68c96a6e05967061f992443cb30aabebef5b3
 PKG_SOURCE_SUBDIR:=$(PKG_DISTNAME)-$(PKG_VERSION)
 PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_DISTNAME)-$(PKG_VERSION)
 

package/boot/uboot-envtools/files/ipq40xx

@@ -53,7 +53,8 @@ aruba,ap-303)
 aruba,ap-365)
 	ubootenv_add_uci_config "/dev/mtd8" "0x0" "0x10000" "0x10000"
 	;;
-buffalo,wtr-m2133hp)
+buffalo,wtr-m2133hp|\
+netgear,lbr20)
 	ubootenv_add_uci_config "/dev/mtd8" "0x0" "0x40000" "0x20000"
 	;;
 linksys,ea6350v3)

package/boot/uboot-envtools/files/mediatek_filogic

@@ -11,52 +11,62 @@ touch /etc/config/ubootenv
 
 board=$(board_name)
 
+ubootenv_add_mmc_default() {
+	local envdev="$(find_mmc_part "ubootenv" "${1:-mmcblk0}")"
+	ubootenv_add_uci_config "$envdev" "0x0" "0x40000" "0x40000" "1"
+	ubootenv_add_uci_config "$envdev" "0x40000" "0x40000" "0x40000" "1"
+}
+
+ubootenv_add_nor_default() {
+	local envdev="/dev/mtd$(find_mtd_index "u-boot-env")"
+	ubootenv_add_uci_config "$envdev" "0x0" "0x20000" "0x20000" "1"
+	ubootenv_add_uci_config "$envdev" "0x20000" "0x20000" "0x20000" "1"
+}
+
+ubootenv_add_ubi_default() {
+	. /lib/upgrade/nand.sh
+	local envubi=$(nand_find_ubi ubi)
+	local envdev=/dev/$(nand_find_volume $envubi ubootenv)
+	local envdev2=/dev/$(nand_find_volume $envubi ubootenv2)
+	ubootenv_add_uci_config "$envdev" "0x0" "0x1f000" "0x1f000" "1"
+	ubootenv_add_uci_config "$envdev2" "0x0" "0x1f000" "0x1f000" "1"
+}
+
 case "$board" in
 asus,rt-ax59u)
 	ubootenv_add_uci_config "/dev/mtd0" "0x100000" "0x20000" "0x20000"
 	;;
-bananapi,bpi-r3)
+bananapi,bpi-r3|\
-	rootdev="$(cmdline_get_var root)"
+bananapi,bpi-r3-mini|\
-	rootdev="${rootdev##*/}"
+bananapi,bpi-r4)
-	rootdev="${rootdev%%p[0-9]*}"
+	. /lib/upgrade/common.sh
-	case "$rootdev" in
+
+	bootdev="$(fitblk_get_bootdev)"
+	case "$bootdev" in
+	ubi*)
+		ubootenv_add_ubi_default
+		;;
 	mmc*)
-		local envdev=$(find_mmc_part "ubootenv" $rootdev)
+		ubootenv_add_mmc_default "${bootdev%%p[0-9]*}"
-		ubootenv_add_uci_config "$envdev" "0x0" "0x40000" "0x40000" "1"
-		ubootenv_add_uci_config "$envdev" "0x40000" "0x40000" "0x40000" "1"
 		;;
 	mtd*)
-		local envdev=/dev/mtd$(find_mtd_index "u-boot-env")
+		ubootenv_add_nor_default
-		ubootenv_add_uci_config "$envdev" "0x0" "0x20000" "0x20000" "1"
-		ubootenv_add_uci_config "$envdev" "0x20000" "0x20000" "0x20000" "1"
-		;;
-	ubi*)
-		. /lib/upgrade/nand.sh
-		local envubi=$(nand_find_ubi ubi)
-		local envdev=/dev/$(nand_find_volume $envubi ubootenv)
-		local envdev2=/dev/$(nand_find_volume $envubi ubootenv2)
-		ubootenv_add_uci_config "$envdev" "0x0" "0x1f000" "0x1f000" "1"
-		ubootenv_add_uci_config "$envdev2" "0x0" "0x1f000" "0x1f000" "1"
 		;;
 	esac
 	;;
 cmcc,rax3000m)
 	case "$(cmdline_get_var root)" in
 	/dev/mmc*)
-		local envdev=$(find_mmc_part "ubootenv" "mmcblk0")
+		ubootenv_add_mmc_default
-		ubootenv_add_uci_config "$envdev" "0x0" "0x40000" "0x40000" "1"
-		ubootenv_add_uci_config "$envdev" "0x40000" "0x40000" "0x40000" "1"
 		;;
 	*)
-		. /lib/upgrade/nand.sh
+		ubootenv_add_ubi_default
-		local envubi=$(nand_find_ubi ubi)
-		local envdev=/dev/$(nand_find_volume $envubi ubootenv)
-		local envdev2=/dev/$(nand_find_volume $envubi ubootenv2)
-		ubootenv_add_uci_config "$envdev" "0x0" "0x1f000" "0x1f000" "1"
-		ubootenv_add_uci_config "$envdev2" "0x0" "0x1f000" "0x1f000" "1"
 		;;
 	esac
 	;;
+comfast,cf-e393ax)
+	ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x20000" "0x80000"
+	;;
 cetron,ct3003|\
 netgear,wax220|\
 zbtlink,zbt-z8102ax|\
@@ -71,13 +81,9 @@ tplink,tl-xdr6086|\
 tplink,tl-xdr6088|\
 xiaomi,mi-router-ax3000t-ubootmod|\
 xiaomi,mi-router-wr30u-ubootmod|\
-xiaomi,redmi-router-ax6000-ubootmod)
+xiaomi,redmi-router-ax6000-ubootmod|\
-	. /lib/upgrade/nand.sh
+zyxel,ex5601-t0-ubootmod)
-	local envubi=$(nand_find_ubi ubi)
+	ubootenv_add_ubi_default
-	local envdev=/dev/$(nand_find_volume $envubi ubootenv)
-	local envdev2=/dev/$(nand_find_volume $envubi ubootenv2)
-	ubootenv_add_uci_config "$envdev" "0x0" "0x1f000" "0x20000" "1"
-	ubootenv_add_uci_config "$envdev2" "0x0" "0x1f000" "0x20000" "1"
 	;;
 glinet,gl-mt2500|\
 glinet,gl-mt6000)
@@ -110,14 +116,6 @@ zyxel,ex5601-t0)
 	local envdev=/dev/mtd$(find_mtd_index "u-boot-env")
 	ubootenv_add_uci_config "$envdev" "0x0" "0x20000" "0x40000" "2"
 	;;
-zyxel,ex5601-t0-ubootmod)
-        . /lib/upgrade/nand.sh
-        local envubi=$(nand_find_ubi ubi)
-        local envdev=/dev/$(nand_find_volume $envubi ubootenv)
-        local envdev2=/dev/$(nand_find_volume $envubi ubootenv2)
-        ubootenv_add_uci_config "$envdev" "0x0" "0x1f000" "0x20000" "1"
-        ubootenv_add_uci_config "$envdev2" "0x0" "0x1f000" "0x20000" "1"
-        ;;
 zyxel,ex5700-telenor)
 	ubootenv_add_uci_config "/dev/ubootenv" "0x0" "0x4000" "0x4000" "1"
 	;;

package/boot/uboot-envtools/files/mediatek_mt7622

@@ -9,6 +9,21 @@ touch /etc/config/ubootenv
 . /lib/uboot-envtools.sh
 . /lib/functions.sh
 
+ubootenv_add_mmc_default() {
+	local envdev="$(find_mmc_part "ubootenv" "${1:-mmcblk0}")"
+	ubootenv_add_uci_config "$envdev" "0x0" "0x80000" "0x80000" "1"
+	ubootenv_add_uci_config "$envdev" "0x80000" "0x80000" "0x80000" "1"
+}
+
+ubootenv_add_ubi_default() {
+	. /lib/upgrade/nand.sh
+	local envubi=$(nand_find_ubi ubi)
+	local envdev=/dev/$(nand_find_volume $envubi ubootenv)
+	local envdev2=/dev/$(nand_find_volume $envubi ubootenv2)
+	ubootenv_add_uci_config "$envdev" "0x0" "0x1f000" "0x1f000" "1"
+	ubootenv_add_uci_config "$envdev2" "0x0" "0x1f000" "0x1f000" "1"
+}
+
 board=$(board_name)
 
 case "$board" in
@@ -17,22 +32,17 @@ dlink,eagle-pro-ai-r32-a1)
 	ubootenv_add_uci_config "/dev/mtd3" "0x0" "0x2000" "0x2000"
 	;;
 linksys,e8450-ubi)
-	ubootenv_add_uci_config "/dev/ubi0_0" "0x0" "0x1f000" "0x1f000" "1"
+	ubootenv_add_ubi_default
-	ubootenv_add_uci_config "/dev/ubi0_1" "0x0" "0x1f000" "0x1f000" "1"
 	;;
 bananapi,bpi-r64)
-	rootdev="$(cmdline_get_var root)"
+	. /lib/upgrade/common.sh
-	rootdev="${rootdev##*/}"
+	bootdev="$(fitblk_get_bootdev)"
-	rootdev="${rootdev%%p[0-9]*}"
+	case "$bootdev" in
-	case "$rootdev" in
 	mmc*)
-		local envdev=$(find_mmc_part "ubootenv" $rootdev)
+		ubootenv_add_mmc_default "${bootdev%p[0-9]*}"
-		ubootenv_add_uci_config "$envdev" "0x0" "0x80000" "0x80000" "1"
-		ubootenv_add_uci_config "$envdev" "0x80000" "0x80000" "0x80000" "1"
 		;;
 	ubi*)
-		ubootenv_add_uci_config "/dev/ubi0_0" "0x0" "0x1f000" "0x1f000" "1"
+		ubootenv_add_ubi_default
-		ubootenv_add_uci_config "/dev/ubi0_1" "0x0" "0x1f000" "0x1f000" "1"
 		;;
 	esac
 	;;
@@ -42,8 +52,10 @@ buffalo,wsr-2533dhp2)
 ruijie,rg-ew3200gx-pro)
 	ubootenv_add_uci_config "/dev/mtd3" "0x0" "0x20000" "0x20000"
 	;;
-ubnt,unifi-6-lr-ubootmod)
+ubnt,unifi-6-lr-v1-ubootmod|\
-	ubootenv_add_uci_config "/dev/mtd2" "0x0" "0x4000" "0x1000"
+ubnt,unifi-6-lr-v2-ubootmod|\
+ubnt,unifi-6-lr-v3-ubootmod)
+	ubootenv_add_uci_config "/dev/mtd$(find_mtd_index "u-boot-env")" "0x0" "0x4000" "0x1000"
 	;;
 xiaomi,redmi-router-ax6s)
 	ubootenv_add_uci_config "/dev/mtd3" "0x0" "0x10000" "0x40000"

package/boot/uboot-envtools/files/mediatek_mt7623

@@ -14,9 +14,8 @@ board=$(board_name)
 case "$board" in
 bananapi,bpi-r2)
 	. /lib/upgrade/common.sh
-	export_bootdevice
+	bootdev="$(fitblk_get_bootdev)"
-	export_partdevice ubootpart 1
+	ubootenv_add_uci_config "/dev/${bootdev%p[0-9]*}p1" "0xb0000" "0x10000" "0x10000" "1"
-	ubootenv_add_uci_config "/dev/$ubootpart" "0xb0000" "0x10000" "0x10000" "1"
 	;;
 unielec,u7623-02)
 	ubootenv_add_uci_config "/dev/mmcblk0p1" "0xc0000" "0x10000" "0x10000" "1"

package/boot/uboot-envtools/files/qualcommax_ipq60xx

@@ -0,0 +1,22 @@
+[ -e /etc/config/ubootenv ] && exit 0
+
+touch /etc/config/ubootenv
+
+. /lib/uboot-envtools.sh
+. /lib/functions.sh
+
+board=$(board_name)
+
+case "$board" in
+8devices,mango-dvk|\
+8devices,mango-dvk-sfp)
+	idx="$(find_mtd_index 0:APPSBLENV)"
+	[ -n "$idx" ] && \
+		ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x10000" "0x10000"
+	;;
+esac
+
+config_load ubootenv
+config_foreach ubootenv_add_app_config
+
+exit 0

package/boot/uboot-envtools/files/qualcommax_ipq807x

@@ -30,7 +30,8 @@ edimax,cax1800)
 		ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x10000" "0x20000"
 	;;
 linksys,mx4200v1|\
-linksys,mx4200v2)
+linksys,mx4200v2|\
+linksys,mx5300)
 	idx="$(find_mtd_index u_env)"
 	[ -n "$idx" ] && \
 		ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x40000" "0x20000" "2"

package/boot/uboot-envtools/patches/002-Revert-tools-env-use-run-to-store-lockfile.patch

@@ -10,8 +10,6 @@ This reverts upstream commit
  tools/env/fw_env_main.c | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)
 
-diff --git a/tools/env/fw_env_main.c b/tools/env/fw_env_main.c
-index 0b201b9e62..1d193bd437 100644
 --- a/tools/env/fw_env_main.c
 +++ b/tools/env/fw_env_main.c
 @@ -73,7 +73,7 @@ void usage_printenv(void)
@@ -32,7 +30,7 @@ index 0b201b9e62..1d193bd437 100644
  		" -s, --script         batch mode to minimize writes\n"
  		"\n"
  		"Examples:\n"
-@@ -206,7 +206,7 @@ int parse_setenv_args(int argc, char *argv[])
+@@ -206,7 +206,7 @@ int parse_setenv_args(int argc, char *ar
  
  int main(int argc, char *argv[])
  {
@@ -41,4 +39,3 @@ index 0b201b9e62..1d193bd437 100644
  	int lockfd = -1;
  	int retval = EXIT_SUCCESS;
  	char *_cmdname;
-

package/boot/uboot-envtools/patches/011-fw_env-keep-calling-read-until-whole-flash-block-is-.patch

@@ -0,0 +1,75 @@
+From 9e3003f79d168eac7ee65cd457e3904e2fb4eea8 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 13 Dec 2023 13:13:54 +0100
+Subject: [PATCH] fw_env: keep calling read() until whole flash block is read
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+It's totally valid for read() to provide less bytes than requested
+maximum. It may happen if there is no more data available yet or source
+pushes data in small chunks.
+
+This actually happens when trying to read env data from NVMEM device.
+Kernel may provide NVMEM content in page size parts (like 4096 B).
+
+This fixes warnings like:
+Warning on /sys/bus/nvmem/devices/u-boot-env0/nvmem: Attempted to read 16384 bytes but got 4096
+Warning on /sys/bus/nvmem/devices/u-boot-env0/nvmem: Attempted to read 12288 bytes but got 4096
+Warning on /sys/bus/nvmem/devices/u-boot-env0/nvmem: Attempted to read 8192 bytes but got 4096
+
+Since the main loop in flash_read_buf() is used to read blocks this
+patch adds a new nested one.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+---
+ tools/env/fw_env.c | 34 +++++++++++++++-------------------
+ 1 file changed, 15 insertions(+), 19 deletions(-)
+
+--- a/tools/env/fw_env.c
++++ b/tools/env/fw_env.c
+@@ -948,29 +948,25 @@ static int flash_read_buf(int dev, int f
+ 		 */
+ 		lseek(fd, blockstart + block_seek, SEEK_SET);
+ 
+-		rc = read(fd, buf + processed, readlen);
+-		if (rc == -1) {
+-			fprintf(stderr, "Read error on %s: %s\n",
+-				DEVNAME(dev), strerror(errno));
+-			return -1;
+-		}
++		while (readlen) {
++			rc = read(fd, buf + processed, readlen);
++			if (rc == -1) {
++				fprintf(stderr, "Read error on %s: %s\n",
++					DEVNAME(dev), strerror(errno));
++				return -1;
++			}
+ #ifdef DEBUG
+-		fprintf(stderr, "Read 0x%x bytes at 0x%llx on %s\n",
+-			rc, (unsigned long long)blockstart + block_seek,
+-			DEVNAME(dev));
++			fprintf(stderr, "Read 0x%x bytes at 0x%llx on %s\n",
++				rc, (unsigned long long)blockstart + block_seek,
++				DEVNAME(dev));
+ #endif
+-		processed += rc;
+-		if (rc != readlen) {
+-			fprintf(stderr,
+-				"Warning on %s: Attempted to read %zd bytes but got %d\n",
+-				DEVNAME(dev), readlen, rc);
++			processed += rc;
+ 			readlen -= rc;
+-			block_seek += rc;
+-		} else {
+-			blockstart += blocklen;
+-			readlen = min(blocklen, count - processed);
+-			block_seek = 0;
+ 		}
++
++		blockstart += blocklen;
++		readlen = min(blocklen, count - processed);
++		block_seek = 0;
+ 	}
+ 
+ 	return processed;

package/boot/uboot-envtools/patches/012-fw_env-autodetect-NAND-erase-size-and-env-sectors.patch

@@ -0,0 +1,49 @@
+From d73a6641868029b5cae53ed00c5766921c9d8b1f Mon Sep 17 00:00:00 2001
+From: Anthony Loiseau <anthony.loiseau@allcircuits.com>
+Date: Thu, 21 Dec 2023 23:44:38 +0100
+Subject: [PATCH] fw_env: autodetect NAND erase size and env sectors
+
+As already done for NOR chips, if device ESIZE and ENVSECTORS static
+configurations are both zero, then autodetect them at runtime.
+
+Cc: Joe Hershberger <joe.hershberger@ni.com>
+cc: Stefan Agner <stefan@agner.ch>
+cc: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
+Signed-off-by: Anthony Loiseau <anthony.loiseau@allcircuits.com>
+---
+ tools/env/README   |  3 +++
+ tools/env/fw_env.c | 11 +++++++++--
+ 2 files changed, 12 insertions(+), 2 deletions(-)
+
+--- a/tools/env/README
++++ b/tools/env/README
+@@ -58,6 +58,9 @@ DEVICEx_ENVSECTORS defines the number of
+ this environment instance. On NAND this is used to limit the range
+ within which bad blocks are skipped, on NOR it is not used.
+ 
++If DEVICEx_ESIZE and DEVICEx_ENVSECTORS are both zero, then a runtime
++detection is attempted for NOR and NAND mtd types.
++
+ To prevent losing changes to the environment and to prevent confusing the MTD
+ drivers, a lock file at /run/fw_printenv.lock is used to serialize access
+ to the environment.
+--- a/tools/env/fw_env.c
++++ b/tools/env/fw_env.c
+@@ -1655,8 +1655,15 @@ static int check_device_config(int dev)
+ 		}
+ 		DEVTYPE(dev) = mtdinfo.type;
+ 		if (DEVESIZE(dev) == 0 && ENVSECTORS(dev) == 0 &&
+-		    mtdinfo.type == MTD_NORFLASH)
+-			DEVESIZE(dev) = mtdinfo.erasesize;
++		    mtdinfo.erasesize > 0) {
++			if (mtdinfo.type == MTD_NORFLASH)
++				DEVESIZE(dev) = mtdinfo.erasesize;
++			else if (mtdinfo.type == MTD_NANDFLASH) {
++				DEVESIZE(dev) = mtdinfo.erasesize;
++				ENVSECTORS(dev) =
++				    mtdinfo.size / mtdinfo.erasesize;
++			}
++		}
+ 		if (DEVESIZE(dev) == 0)
+ 			/* Assume the erase size is the same as the env-size */
+ 			DEVESIZE(dev) = ENVSIZE(dev);

package/boot/uboot-mediatek/Makefile

@@ -1,8 +1,8 @@
 include $(TOPDIR)/rules.mk
 include $(INCLUDE_DIR)/kernel.mk
 
-PKG_VERSION:=2023.07.02
+PKG_VERSION:=2024.01
-PKG_HASH:=6b6a48581c14abb0f95bd87c1af4d740922406d7b801002a9f94727fdde021d5
+PKG_HASH:=b99611f1ed237bf3541bdc8434b68c96a6e05967061f992443cb30aabebef5b3
 PKG_BUILD_DEPENDS:=!(TARGET_ramips||TARGET_mediatek_mt7623):arm-trusted-firmware-tools/host
 
 UBOOT_USE_INTREE_DTC:=1
@@ -75,6 +75,15 @@ define U-Boot/mt7621_nand_rfb
   UBOOT_IMAGE:=u-boot-mt7621.bin
 endef
 
+define U-Boot/mt7621_zbtlink_zbt-wg3526-16m
+  NAME:=Zbtlink ZBT-WG3526-16m
+  UBOOT_CONFIG:=mt7621_zbtlink_zbt-wg3526-16m
+  BUILD_DEVICES:=zbtlink_zbt-wg3526-16m
+  BUILD_TARGET:=ramips
+  BUILD_SUBTARGET:=mt7621
+  UBOOT_IMAGE:=u-boot-mt7621.bin
+endef
+
 define U-Boot/mt7622_rfb1
   NAME:=MT7622 Reference Board 1
   UBOOT_CONFIG:=mt7622_rfb
@@ -88,9 +97,9 @@ define U-Boot/mt7622_linksys_e8450
   BUILD_DEVICES:=linksys_e8450-ubi
   BUILD_SUBTARGET:=mt7622
   UBOOT_IMAGE:=u-boot.fip
-  BL2_BOOTDEV:=snand
+  BL2_BOOTDEV:=snand-ubi
   BL2_DDRBLOB:=1
-  DEPENDS:=+trusted-firmware-a-mt7622-snand-1ddr
+  DEPENDS:=+trusted-firmware-a-mt7622-snand-ubi-1ddr
 endef
 
 define U-Boot/mt7622_bananapi_bpi-r64-emmc
@@ -121,9 +130,9 @@ define U-Boot/mt7622_bananapi_bpi-r64-snand
   BUILD_DEVICES:=bananapi_bpi-r64
   BUILD_SUBTARGET:=mt7622
   UBOOT_IMAGE:=u-boot.fip
-  BL2_BOOTDEV:=snand
+  BL2_BOOTDEV:=snand-ubi
   BL2_DDRBLOB:=2
-  DEPENDS:=+trusted-firmware-a-mt7622-snand-2ddr
+  DEPENDS:=+trusted-firmware-a-mt7622-snand-ubi-2ddr
 endef
 
 define U-Boot/mt7622_ubnt_unifi-6-lr-v1
@@ -186,7 +195,7 @@ define U-Boot/mt7628_rfb
   UBOOT_IMAGE:=u-boot-with-spl.bin
 endef
 
-define U-Boot/ravpower_rp-wd009
+define U-Boot/mt7628_ravpower_rp-wd009
   NAME:=RAVPower RP-WD009
   BUILD_TARGET:=ramips
   BUILD_DEVICES:=ravpower_rp-wd009
@@ -388,10 +397,10 @@ define U-Boot/mt7986_bananapi_bpi-r3-snand
   BUILD_DEVICES:=bananapi_bpi-r3
   UBOOT_CONFIG:=mt7986a_bpi-r3-snand
   UBOOT_IMAGE:=u-boot.fip
-  BL2_BOOTDEV:=spim-nand
+  BL2_BOOTDEV:=spim-nand-ubi
   BL2_SOC:=mt7986
   BL2_DDRTYPE:=ddr4
-  DEPENDS:=+trusted-firmware-a-mt7986-spim-nand-ddr4
+  DEPENDS:=+trusted-firmware-a-mt7986-spim-nand-ubi-ddr4
 endef
 
 define U-Boot/mt7986_bananapi_bpi-r3-nor
@@ -407,6 +416,30 @@ define U-Boot/mt7986_bananapi_bpi-r3-nor
   FIP_COMPRESS:=1
 endef
 
+define U-Boot/mt7986_bananapi_bpi-r3-mini-emmc
+  NAME:=BananaPi BPi-R3
+  BUILD_SUBTARGET:=filogic
+  BUILD_DEVICES:=bananapi_bpi-r3-mini
+  UBOOT_CONFIG:=mt7986a_bpi-r3-mini-emmc
+  UBOOT_IMAGE:=u-boot.fip
+  BL2_BOOTDEV:=emmc
+  BL2_SOC:=mt7986
+  BL2_DDRTYPE:=ddr4
+  DEPENDS:=+trusted-firmware-a-mt7986-emmc-ddr4
+endef
+
+define U-Boot/mt7986_bananapi_bpi-r3-mini-snand
+  NAME:=BananaPi BPi-R3
+  BUILD_SUBTARGET:=filogic
+  BUILD_DEVICES:=bananapi_bpi-r3-mini
+  UBOOT_CONFIG:=mt7986a_bpi-r3-mini-snand
+  UBOOT_IMAGE:=u-boot.fip
+  BL2_BOOTDEV:=spim-nand-ubi
+  BL2_SOC:=mt7986
+  BL2_DDRTYPE:=ddr4
+  DEPENDS:=+trusted-firmware-a-mt7986-spim-nand-ubi-ddr4
+endef
+
 define U-Boot/mt7986_glinet_gl-mt6000
   NAME:=GL.iNet GL-MT6000
   BUILD_SUBTARGET:=filogic
@@ -491,6 +524,42 @@ define U-Boot/mt7986_zyxel_ex5601-t0
   DEPENDS:=+trusted-firmware-a-mt7986-spim-nand-4k-ddr4
 endef
 
+define U-Boot/mt7988_bananapi_bpi-r4-emmc
+  NAME:=BananaPi BPi-R4
+  BUILD_SUBTARGET:=filogic
+  BUILD_DEVICES:=bananapi_bpi-r4
+  UBOOT_CONFIG:=mt7988a_bananapi_bpi-r4-emmc
+  UBOOT_IMAGE:=u-boot.fip
+  BL2_BOOTDEV:=emmc
+  BL2_SOC:=mt7988
+  BL2_DDRTYPE:=comb
+  DEPENDS:=+trusted-firmware-a-mt7988-emmc-comb
+endef
+
+define U-Boot/mt7988_bananapi_bpi-r4-sdmmc
+  NAME:=BananaPi BPi-R4
+  BUILD_SUBTARGET:=filogic
+  BUILD_DEVICES:=bananapi_bpi-r4
+  UBOOT_CONFIG:=mt7988a_bananapi_bpi-r4-sdmmc
+  UBOOT_IMAGE:=u-boot.fip
+  BL2_BOOTDEV:=sdmmc
+  BL2_SOC:=mt7988
+  BL2_DDRTYPE:=comb
+  DEPENDS:=+trusted-firmware-a-mt7988-sdmmc-comb
+endef
+
+define U-Boot/mt7988_bananapi_bpi-r4-snand
+  NAME:=BananaPi BPi-R4
+  BUILD_SUBTARGET:=filogic
+  BUILD_DEVICES:=bananapi_bpi-r4
+  UBOOT_CONFIG:=mt7988a_bananapi_bpi-r4-snand
+  UBOOT_IMAGE:=u-boot.fip
+  BL2_BOOTDEV:=spim-nand-ubi
+  BL2_SOC:=mt7988
+  BL2_DDRTYPE:=comb
+  DEPENDS:=+trusted-firmware-a-mt7988-spim-nand-ubi-comb
+endef
+
 define U-Boot/mt7988_rfb-spim-nand
   NAME:=MT7988 Reference Board
   BUILD_SUBTARGET:=filogic
@@ -557,6 +626,7 @@ UBOOT_TARGETS := \
 	mt7620_rfb \
 	mt7621_nand_rfb \
 	mt7621_rfb \
+	mt7621_zbtlink_zbt-wg3526-16m \
 	mt7622_bananapi_bpi-r64-emmc \
 	mt7622_bananapi_bpi-r64-sdmmc \
 	mt7622_bananapi_bpi-r64-snand \
@@ -568,7 +638,7 @@ UBOOT_TARGETS := \
 	mt7623n_bpir2 \
 	mt7623a_unielec_u7623 \
 	mt7628_rfb \
-	ravpower_rp-wd009 \
+	mt7628_ravpower_rp-wd009 \
 	mt7629_rfb \
 	mt7981_cmcc_rax3000m-emmc \
 	mt7981_cmcc_rax3000m-nand \
@@ -586,6 +656,8 @@ UBOOT_TARGETS := \
 	mt7986_bananapi_bpi-r3-sdmmc \
 	mt7986_bananapi_bpi-r3-snand \
 	mt7986_bananapi_bpi-r3-nor \
+	mt7986_bananapi_bpi-r3-mini-emmc \
+	mt7986_bananapi_bpi-r3-mini-snand \
 	mt7986_glinet_gl-mt6000 \
 	mt7986_jdcloud_re-cp-03 \
 	mt7986_tplink_tl-xdr4288 \
@@ -594,6 +666,9 @@ UBOOT_TARGETS := \
 	mt7986_xiaomi_redmi-router-ax6000 \
 	mt7986_zyxel_ex5601-t0 \
 	mt7986_rfb \
+	mt7988_bananapi_bpi-r4-emmc \
+	mt7988_bananapi_bpi-r4-sdmmc \
+	mt7988_bananapi_bpi-r4-snand \
 	mt7988_rfb-spim-nand \
 	mt7988_rfb-snand \
 	mt7988_rfb-nor \

package/boot/uboot-mediatek/patches/000-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch

@@ -18,9 +18,9 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  CONFIG_DEFAULT_DEVICE_TREE="mt7622-rfb"
 +CONFIG_ENV_SIZE=0x20000
 +CONFIG_ENV_OFFSET=0x280000
- CONFIG_SYS_PROMPT="MT7622> "
  CONFIG_DEBUG_UART_BASE=0x11002000
  CONFIG_DEBUG_UART_CLOCK=25000000
+ CONFIG_SYS_LOAD_ADDR=0x4007ff28
 @@ -25,6 +27,9 @@ CONFIG_CMD_SF_TEST=y
  CONFIG_CMD_PING=y
  CONFIG_CMD_SMC=y

package/boot/uboot-mediatek/patches/100-00-clk-remove-log_ret-from-clk_get_rate.patch

@@ -1,43 +0,0 @@
-From 19f2aa053d5531a9ca0ece04dca172a522d58b90 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Fri, 29 Jul 2022 11:32:28 +0800
-Subject: [PATCH 32/71] clk: remove log_ret from clk_get_rate
-
-The return value of clk_get_rate is ulong, an unsigned type. The size of
-ulong depends on the cpu architecture, i.e. 4 bytes on 32-bit CPUs and
-8 bytes on 64-bit CPUs.
-
-However log_ret only accepts and returns value in int type, a fixed 4-byte
-type. This may truncate the real clock value and cause unexpected error on
-64-bit platforms.
-
-This patch removes log_ret to solve this issue.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/clk/clk-uclass.c | 7 +------
- 1 file changed, 1 insertion(+), 6 deletions(-)
-
---- a/drivers/clk/clk-uclass.c
-+++ b/drivers/clk/clk-uclass.c
-@@ -471,7 +471,6 @@ void clk_free(struct clk *clk)
- ulong clk_get_rate(struct clk *clk)
- {
- 	const struct clk_ops *ops;
--	int ret;
- 
- 	debug("%s(clk=%p)\n", __func__, clk);
- 	if (!clk_valid(clk))
-@@ -481,11 +480,7 @@ ulong clk_get_rate(struct clk *clk)
- 	if (!ops->get_rate)
- 		return -ENOSYS;
- 
--	ret = ops->get_rate(clk);
--	if (ret)
--		return log_ret(ret);
--
--	return 0;
-+	return ops->get_rate(clk);
- }
- 
- struct clk *clk_get_parent(struct clk *clk)

package/boot/uboot-mediatek/patches/100-04-env-add-support-for-generic-MTD-device.patch

@@ -17,37 +17,18 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  7 files changed, 299 insertions(+), 3 deletions(-)
  create mode 100644 env/mtd.c
 
---- a/cmd/nvedit.c
-+++ b/cmd/nvedit.c
-@@ -48,6 +48,7 @@ DECLARE_GLOBAL_DATA_PTR;
- 	defined(CONFIG_ENV_IS_IN_MMC)		|| \
- 	defined(CONFIG_ENV_IS_IN_FAT)		|| \
- 	defined(CONFIG_ENV_IS_IN_EXT4)		|| \
-+	defined(CONFIG_ENV_IS_IN_MTD)		|| \
- 	defined(CONFIG_ENV_IS_IN_NAND)		|| \
- 	defined(CONFIG_ENV_IS_IN_NVRAM)		|| \
- 	defined(CONFIG_ENV_IS_IN_ONENAND)	|| \
-@@ -61,7 +62,7 @@ DECLARE_GLOBAL_DATA_PTR;
- 
- #if	!defined(ENV_IS_IN_DEVICE)		&& \
- 	!defined(CONFIG_ENV_IS_NOWHERE)
--# error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|MMC|FAT|EXT4|\
-+# error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|MMC|FAT|EXT4|MTD|\
- NAND|NVRAM|ONENAND|SATA|SPI_FLASH|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE
- #endif
- 
 --- a/env/Kconfig
 +++ b/env/Kconfig
-@@ -62,7 +62,7 @@ config ENV_IS_NOWHERE
+@@ -61,7 +61,7 @@ config ENV_IS_DEFAULT
  		     !ENV_IS_IN_MMC && !ENV_IS_IN_NAND && \
  		     !ENV_IS_IN_NVRAM && !ENV_IS_IN_ONENAND && \
  		     !ENV_IS_IN_REMOTE && !ENV_IS_IN_SPI_FLASH && \
 -		     !ENV_IS_IN_UBI
 +		     !ENV_IS_IN_UBI && !ENV_IS_IN_MTD
- 	help
+ 	select ENV_IS_NOWHERE
- 	  Define this if you don't want to or can't have an environment stored
+ 
- 	  on a storage medium. In this case the environment will still exist
+ config ENV_IS_NOWHERE
-@@ -251,6 +251,27 @@ config ENV_IS_IN_MMC
+@@ -254,6 +254,27 @@ config ENV_IS_IN_MMC
  	  offset: "u-boot,mmc-env-offset", "u-boot,mmc-env-offset-redundant".
  	  CONFIG_ENV_OFFSET and CONFIG_ENV_OFFSET_REDUND are not used.
  
@@ -75,7 +56,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  config ENV_IS_IN_NAND
  	bool "Environment in a NAND device"
  	depends on !CHAIN_OF_TRUST
-@@ -558,10 +579,16 @@ config ENV_ADDR_REDUND
+@@ -561,10 +582,16 @@ config ENV_ADDR_REDUND
  	  Offset from the start of the device (or partition) of the redundant
  	  environment location.
  
@@ -93,7 +74,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  	default 0x3f8000 if ARCH_ROCKCHIP && ENV_IS_IN_MMC
  	default 0x140000 if ARCH_ROCKCHIP && ENV_IS_IN_SPI_FLASH
  	default 0xF0000 if ARCH_SUNXI
-@@ -609,6 +636,12 @@ config ENV_SECT_SIZE
+@@ -622,6 +649,12 @@ config ENV_SECT_SIZE
  	help
  	  Size of the sector containing the environment.
  
@@ -118,7 +99,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_FLASH) += flash.o
 --- a/env/env.c
 +++ b/env/env.c
-@@ -69,6 +69,9 @@ static enum env_location env_locations[]
+@@ -46,6 +46,9 @@ static enum env_location env_locations[]
  #ifdef CONFIG_ENV_IS_IN_MMC
  	ENVL_MMC,
  #endif

package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch

@@ -13,7 +13,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 --- a/common/board_r.c
 +++ b/common/board_r.c
-@@ -388,6 +388,20 @@ static int initr_nand(void)
+@@ -373,6 +373,20 @@ static int initr_nand(void)
  }
  #endif
  
@@ -34,7 +34,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  #if defined(CONFIG_CMD_ONENAND)
  /* go init the NAND */
  static int initr_onenand(void)
-@@ -696,6 +710,9 @@ static init_fnc_t init_sequence_r[] = {
+@@ -675,6 +689,9 @@ static init_fnc_t init_sequence_r[] = {
  #ifdef CONFIG_CMD_ONENAND
  	initr_onenand,
  #endif

package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch

@@ -15,7 +15,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 --- a/cmd/Kconfig
 +++ b/cmd/Kconfig
-@@ -1353,6 +1353,12 @@ config CMD_NAND_TORTURE
+@@ -1392,6 +1392,12 @@ config CMD_NAND_TORTURE
  
  endif # CMD_NAND
  
@@ -30,7 +30,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  	depends on NVME
 --- a/cmd/Makefile
 +++ b/cmd/Makefile
-@@ -125,6 +125,7 @@ obj-y += legacy-mtd-utils.o
+@@ -127,6 +127,7 @@ obj-y += legacy-mtd-utils.o
  endif
  obj-$(CONFIG_CMD_MUX) += mux.o
  obj-$(CONFIG_CMD_NAND) += nand.o

package/boot/uboot-mediatek/patches/100-10-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch

@@ -63,7 +63,7 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
  #ifdef CONFIG_AUTO_COMPLETE
  static int mtd_name_complete(int argc, char *const argv[], char last_char,
  			     int maxv, char *cmdv[])
-@@ -552,6 +588,7 @@ static char mtd_help_text[] =
+@@ -551,6 +587,7 @@ U_BOOT_LONGHELP(mtd,
  	"\n"
  	"Specific functions:\n"
  	"mtd bad                               <name>\n"
@@ -71,7 +71,7 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
  	"\n"
  	"With:\n"
  	"\t<name>: NAND partition/chip name (or corresponding DM device name or OF path)\n"
-@@ -577,4 +614,6 @@ U_BOOT_CMD_WITH_SUBCMDS(mtd, "MTD utils"
+@@ -575,4 +612,6 @@ U_BOOT_CMD_WITH_SUBCMDS(mtd, "MTD utils"
  		U_BOOT_SUBCMD_MKENT_COMPLETE(erase, 4, 0, do_mtd_erase,
  					     mtd_name_complete),
  		U_BOOT_SUBCMD_MKENT_COMPLETE(bad, 2, 1, do_mtd_bad,

package/boot/uboot-mediatek/patches/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch

@@ -17,37 +17,17 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  7 files changed, 180 insertions(+), 3 deletions(-)
  create mode 100644 env/nmbm.c
 
---- a/cmd/nvedit.c
-+++ b/cmd/nvedit.c
-@@ -50,6 +50,7 @@ DECLARE_GLOBAL_DATA_PTR;
- 	defined(CONFIG_ENV_IS_IN_EXT4)		|| \
- 	defined(CONFIG_ENV_IS_IN_MTD)		|| \
- 	defined(CONFIG_ENV_IS_IN_NAND)		|| \
-+	defined(CONFIG_ENV_IS_IN_NMBM)		|| \
- 	defined(CONFIG_ENV_IS_IN_NVRAM)		|| \
- 	defined(CONFIG_ENV_IS_IN_ONENAND)	|| \
- 	defined(CONFIG_ENV_IS_IN_SPI_FLASH)	|| \
-@@ -63,7 +64,7 @@ DECLARE_GLOBAL_DATA_PTR;
- #if	!defined(ENV_IS_IN_DEVICE)		&& \
- 	!defined(CONFIG_ENV_IS_NOWHERE)
- # error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|MMC|FAT|EXT4|MTD|\
--NAND|NVRAM|ONENAND|SATA|SPI_FLASH|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE
-+NAND|NMBM|NVRAM|ONENAND|SATA|SPI_FLASH|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE
- #endif
- 
- /*
 --- a/env/Kconfig
 +++ b/env/Kconfig
-@@ -62,7 +62,7 @@ config ENV_IS_NOWHERE
+@@ -59,6 +59,7 @@ config ENV_IS_DEFAULT
+ 	def_bool y if !ENV_IS_IN_EEPROM && !ENV_IS_IN_EXT4 && \
+ 		     !ENV_IS_IN_FAT && !ENV_IS_IN_FLASH && \
  		     !ENV_IS_IN_MMC && !ENV_IS_IN_NAND && \
++		     !ENV_IS_IN_NMBM && \
  		     !ENV_IS_IN_NVRAM && !ENV_IS_IN_ONENAND && \
  		     !ENV_IS_IN_REMOTE && !ENV_IS_IN_SPI_FLASH && \
--		     !ENV_IS_IN_UBI && !ENV_IS_IN_MTD
+ 		     !ENV_IS_IN_UBI && !ENV_IS_IN_MTD
-+		     !ENV_IS_IN_UBI && !ENV_IS_IN_NMBM && !ENV_IS_IN_MTD
+@@ -315,6 +316,21 @@ config ENV_RANGE
- 	help
- 	  Define this if you don't want to or can't have an environment stored
- 	  on a storage medium. In this case the environment will still exist
-@@ -312,6 +312,21 @@ config ENV_RANGE
  	  Specifying a range with more erase blocks than are needed to hold
  	  CONFIG_ENV_SIZE allows bad blocks within the range to be avoided.
  
@@ -69,7 +49,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  config ENV_IS_IN_NVRAM
  	bool "Environment in a non-volatile RAM"
  	depends on !CHAIN_OF_TRUST
-@@ -588,7 +603,7 @@ config ENV_MTD_NAME
+@@ -591,7 +607,7 @@ config ENV_MTD_NAME
  config ENV_OFFSET
  	hex "Environment offset"
  	depends on ENV_IS_IN_EEPROM || ENV_IS_IN_MMC || ENV_IS_IN_NAND || \
@@ -90,7 +70,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  
 --- a/env/env.c
 +++ b/env/env.c
-@@ -75,6 +75,9 @@ static enum env_location env_locations[]
+@@ -52,6 +52,9 @@ static enum env_location env_locations[]
  #ifdef CONFIG_ENV_IS_IN_NAND
  	ENVL_NAND,
  #endif

package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch

@@ -26,7 +26,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 --- a/cmd/Kconfig
 +++ b/cmd/Kconfig
-@@ -1353,6 +1353,14 @@ config CMD_NAND_TORTURE
+@@ -1392,6 +1392,14 @@ config CMD_NAND_TORTURE
  
  endif # CMD_NAND
  
@@ -43,7 +43,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  	bool "nmbm"
 --- a/cmd/Makefile
 +++ b/cmd/Makefile
-@@ -125,6 +125,7 @@ obj-y += legacy-mtd-utils.o
+@@ -127,6 +127,7 @@ obj-y += legacy-mtd-utils.o
  endif
  obj-$(CONFIG_CMD_MUX) += mux.o
  obj-$(CONFIG_CMD_NAND) += nand.o

package/boot/uboot-mediatek/patches/100-14-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch

@@ -13,7 +13,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 --- a/drivers/mtd/spi/spi-nor-core.c
 +++ b/drivers/mtd/spi/spi-nor-core.c
-@@ -2848,6 +2848,100 @@ static int spi_nor_init_params(struct sp
+@@ -2854,6 +2854,100 @@ static int spi_nor_init_params(struct sp
  	return 0;
  }
  
@@ -114,7 +114,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
  {
  	size_t i;
-@@ -4045,6 +4139,7 @@ int spi_nor_scan(struct spi_nor *nor)
+@@ -4051,6 +4145,7 @@ int spi_nor_scan(struct spi_nor *nor)
  	nor->write = spi_nor_write_data;
  	nor->read_reg = spi_nor_read_reg;
  	nor->write_reg = spi_nor_write_reg;

package/boot/uboot-mediatek/patches/100-15-cmd-sf-add-support-to-read-flash-unique-ID.patch

@@ -12,7 +12,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 --- a/cmd/sf.c
 +++ b/cmd/sf.c
-@@ -407,6 +407,14 @@ static int do_spi_protect(int argc, char
+@@ -412,6 +412,14 @@ static int do_spi_protect(int argc, char
  	return ret == 0 ? 0 : 1;
  }
  
@@ -27,22 +27,20 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  enum {
  	STAGE_ERASE,
  	STAGE_CHECK,
-@@ -601,6 +609,8 @@ static int do_spi_flash(struct cmd_tbl *
+@@ -606,6 +614,8 @@ static int do_spi_flash(struct cmd_tbl *
  		ret = do_spi_flash_erase(argc, argv);
- 	else if (strcmp(cmd, "protect") == 0)
+ 	else if (IS_ENABLED(CONFIG_SPI_FLASH_LOCK) && strcmp(cmd, "protect") == 0)
  		ret = do_spi_protect(argc, argv);
 +	else if (strcmp(cmd, "uuid") == 0)
 +		ret = do_spi_flash_read_uuid();
  	else if (IS_ENABLED(CONFIG_CMD_SF_TEST) && !strcmp(cmd, "test"))
  		ret = do_spi_flash_test(argc, argv);
  	else
-@@ -626,7 +636,8 @@ static const char long_help[] =
+@@ -636,6 +646,7 @@ U_BOOT_LONGHELP(sf,
- 	"					  at `addr' to flash at `offset'\n"
- 	"					  or to start of mtd `partition'\n"
- 	"sf protect lock/unlock sector len	- protect/unprotect 'len' bytes starting\n"
--	"					  at address 'sector'"
-+	"					  at address 'sector'\n"
-+	"sf uuid					- read uuid from flash"
  #ifdef CONFIG_CMD_SF_TEST
  	"\nsf test offset len		- run a very basic destructive test"
  #endif
++	"sf uuid				- read uuid from flash"
+ 	);
+ 
+ U_BOOT_CMD(

package/boot/uboot-mediatek/patches/100-16-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch

@@ -255,15 +255,15 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  };
  
  /** enum bootmenu_key - keys that can be returned by the bootmenu */
-@@ -54,6 +59,7 @@ enum bootmenu_key {
+@@ -51,6 +56,7 @@ enum bootmenu_key {
- 	BKEY_MINUS,
+ 	BKEY_SELECT,
- 	BKEY_SPACE,
+ 	BKEY_QUIT,
  	BKEY_SAVE,
 +	BKEY_CHOICE,
  
- 	BKEY_COUNT,
+ 	/* 'extra' keys, which are used by menus but not cedit */
- };
+ 	BKEY_PLUS,
-@@ -76,7 +82,7 @@ enum bootmenu_key {
+@@ -81,7 +87,7 @@ enum bootmenu_key {
   *	anything else: KEY_NONE
   */
  enum bootmenu_key bootmenu_autoboot_loop(struct bootmenu_data *menu,
@@ -272,7 +272,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  
  /**
   * bootmenu_loop() - handle waiting for a keypress when autoboot is disabled
-@@ -102,7 +108,7 @@ enum bootmenu_key bootmenu_autoboot_loop
+@@ -107,7 +113,7 @@ enum bootmenu_key bootmenu_autoboot_loop
   *	Space: BKEY_SPACE
   */
  enum bootmenu_key bootmenu_loop(struct bootmenu_data *menu,
@@ -281,7 +281,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  
  /**
   * bootmenu_conv_key() - Convert a U-Boot keypress into a menu key
-@@ -110,6 +116,7 @@ enum bootmenu_key bootmenu_loop(struct b
+@@ -115,6 +121,7 @@ enum bootmenu_key bootmenu_loop(struct b
   * @ichar: Keypress to convert (ASCII, including control characters)
   * Returns: Menu key that corresponds to @ichar, or BKEY_NONE if none
   */
@@ -301,7 +301,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  
  		switch (key) {
  		case BKEY_UP:
-@@ -1937,7 +1937,7 @@ char *eficonfig_choice_change_boot_order
+@@ -1838,7 +1838,7 @@ char *eficonfig_choice_change_boot_order
  
  	cli_ch_init(cch);
  	while (1) {
@@ -312,7 +312,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  		case BKEY_PLUS:
 --- a/boot/bootflow_menu.c
 +++ b/boot/bootflow_menu.c
-@@ -231,7 +231,7 @@ int bootflow_menu_run(struct bootstd_pri
+@@ -235,7 +235,7 @@ int bootflow_menu_run(struct bootstd_pri
  
  		key = 0;
  		if (ichar) {

package/boot/uboot-mediatek/patches/100-17-common-spl-spl_nand-enable-CONFIG_SYS_NAND_U_BOOT_OF.patch

@@ -14,7 +14,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 --- a/common/spl/spl_nand.c
 +++ b/common/spl/spl_nand.c
-@@ -16,7 +16,11 @@
+@@ -17,7 +17,11 @@
  
  uint32_t __weak spl_nand_get_uboot_raw_page(void)
  {

package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch

@@ -89,14 +89,14 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  		reg = <0x11014000 0x1000>;
 --- a/arch/arm/mach-mediatek/Kconfig
 +++ b/arch/arm/mach-mediatek/Kconfig
-@@ -133,9 +133,11 @@ config SYS_CONFIG_NAME
+@@ -144,9 +144,11 @@ config SYS_CONFIG_NAME
  
  config MTK_BROM_HEADER_INFO
  	string
 -	default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622
 +	default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7622
  	default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183
- 	default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986
+ 	default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 || TARGET_MT7988
  	default "lk=1" if TARGET_MT7623
  
 +source "board/mediatek/mt7629/Kconfig"

package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch

@@ -18,7 +18,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 --- a/arch/arm/dts/Makefile
 +++ b/arch/arm/dts/Makefile
-@@ -1308,6 +1308,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
+@@ -1425,6 +1425,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
  	mt7623n-bananapi-bpi-r2.dtb \
  	mt7629-rfb.dtb \
  	mt7981-rfb.dtb \

package/boot/uboot-mediatek/patches/100-21-mtd-spi-nor-add-more-flash-ids.patch

@@ -13,7 +13,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 --- a/drivers/mtd/spi/spi-nor-core.c
 +++ b/drivers/mtd/spi/spi-nor-core.c
-@@ -673,6 +673,7 @@ static int set_4byte(struct spi_nor *nor
+@@ -674,6 +674,7 @@ static int set_4byte(struct spi_nor *nor
  	case SNOR_MFR_ISSI:
  	case SNOR_MFR_MACRONIX:
  	case SNOR_MFR_WINBOND:
@@ -45,7 +45,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  		INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256,
  			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
-@@ -468,6 +474,16 @@ const struct flash_info spi_nor_ids[] =
+@@ -474,6 +480,16 @@ const struct flash_info spi_nor_ids[] =
  			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  	},
  	{
@@ -62,7 +62,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  		INFO("w25q128jw", 0xef8018, 0, 64 * 1024, 256,
  			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
-@@ -517,6 +533,11 @@ const struct flash_info spi_nor_ids[] =
+@@ -523,6 +539,11 @@ const struct flash_info spi_nor_ids[] =
  			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  	},
  	{ INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch

@@ -15,7 +15,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 --- a/drivers/mmc/Kconfig
 +++ b/drivers/mmc/Kconfig
-@@ -820,6 +820,14 @@ config MMC_MTK
+@@ -815,6 +815,14 @@ config MMC_MTK
  	  This is needed if support for any SD/SDIO/MMC devices is required.
  	  If unsure, say N.
  
@@ -32,7 +32,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  config FSL_SDHC_V2_3
 --- a/drivers/mmc/Makefile
 +++ b/drivers/mmc/Makefile
-@@ -83,3 +83,7 @@ obj-$(CONFIG_RENESAS_SDHI)		+= tmio-comm
+@@ -82,3 +82,7 @@ obj-$(CONFIG_RENESAS_SDHI)		+= tmio-comm
  obj-$(CONFIG_MMC_BCM2835)		+= bcm2835_sdhost.o
  obj-$(CONFIG_MMC_MTK)			+= mtk-sd.o
  obj-$(CONFIG_MMC_SDHCI_F_SDH30)		+= f_sdh30.o
@@ -42,7 +42,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +endif
 --- a/drivers/mmc/mtk-sd.c
 +++ b/drivers/mmc/mtk-sd.c
-@@ -778,18 +778,24 @@ static int msdc_ops_send_cmd(struct udev
+@@ -779,18 +779,24 @@ static int msdc_ops_send_cmd(struct udev
  	if (cmd_ret &&
  	    !(cmd_ret == -EIO &&
  	    (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||

package/boot/uboot-mediatek/patches/100-26-env-ubi-add-support-to-create-environment-volume-if-.patch

@@ -14,7 +14,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 --- a/env/Kconfig
 +++ b/env/Kconfig
-@@ -675,6 +675,12 @@ config ENV_UBI_VOLUME_REDUND
+@@ -689,6 +689,12 @@ config ENV_UBI_VOLUME_REDUND
  	help
  	  Name of the redundant volume that you want to store the environment in.
  

package/boot/uboot-mediatek/patches/100-27-mtd-ubi-add-support-for-UBI-end-of-filesystem-marker.patch

@@ -15,7 +15,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 --- a/drivers/mtd/ubi/attach.c
 +++ b/drivers/mtd/ubi/attach.c
-@@ -802,6 +802,13 @@ out_unlock:
+@@ -803,6 +803,13 @@ out_unlock:
  	return err;
  }
  
@@ -29,7 +29,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  /**
   * scan_peb - scan and process UBI headers of a PEB.
   * @ubi: UBI device description object
-@@ -832,9 +839,21 @@ static int scan_peb(struct ubi_device *u
+@@ -833,9 +840,21 @@ static int scan_peb(struct ubi_device *u
  		return 0;
  	}
  
@@ -56,7 +56,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  		break;
 --- a/drivers/mtd/ubi/ubi.h
 +++ b/drivers/mtd/ubi/ubi.h
-@@ -745,6 +745,7 @@ struct ubi_attach_info {
+@@ -746,6 +746,7 @@ struct ubi_attach_info {
  	int mean_ec;
  	uint64_t ec_sum;
  	int ec_count;

package/boot/uboot-mediatek/patches/100-29-board-mediatek-wire-up-NMBM-support.patch

@@ -24,7 +24,7 @@ Subject: [PATCH] board: mediatek: wire-up NMBM support
  DECLARE_GLOBAL_DATA_PTR;
  
  int board_init(void)
-@@ -24,3 +29,36 @@ int board_late_init(void)
+@@ -23,3 +28,36 @@ int board_late_init(void)
  	env_relocate();
  	return 0;
  }

package/boot/uboot-mediatek/patches/101-01-arm-mediatek-retrieve-ram_base-from-dts-node-for-arm.patch

@@ -1,297 +0,0 @@
-From 63336ec7fd7d480ac58a91f3b20d08bf1b3a13ad Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:15:41 +0800
-Subject: [PATCH 01/29] arm: mediatek: retrieve ram_base from dts node for
- armv8 platform
-
-Now we use fdtdec_setup_mem_size_base() to get DRAM base from fdt ram node
-and update gd->ram_base. CFG_SYS_SDRAM_BASE is unused and will be removed.
-
-Also, since mt7622 always passes fdt to linux kernel, there's no need to
-assign value to gd->bd->bi_boot_params.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- arch/arm/dts/mt7981-emmc-rfb.dts     |  5 +++++
- arch/arm/dts/mt7981-rfb.dts          |  5 +++++
- arch/arm/dts/mt7981-sd-rfb.dts       |  5 +++++
- arch/arm/dts/mt7986a-bpi-r3-sd.dts   |  5 +++++
- arch/arm/dts/mt7986a-rfb.dts         |  5 +++++
- arch/arm/dts/mt7986a-sd-rfb.dts      |  5 +++++
- arch/arm/dts/mt7986b-rfb.dts         |  5 +++++
- arch/arm/dts/mt7986b-sd-rfb.dts      |  5 +++++
- arch/arm/mach-mediatek/mt7622/init.c | 13 +++++++++----
- arch/arm/mach-mediatek/mt7981/init.c | 11 +++++++++--
- arch/arm/mach-mediatek/mt7986/init.c | 11 +++++++++--
- board/mediatek/mt7622/mt7622_rfb.c   |  1 -
- include/configs/mt7622.h             | 10 ----------
- include/configs/mt7981.h             |  9 ---------
- include/configs/mt7986.h             |  9 ---------
- 15 files changed, 67 insertions(+), 37 deletions(-)
-
---- a/arch/arm/dts/mt7981-emmc-rfb.dts
-+++ b/arch/arm/dts/mt7981-emmc-rfb.dts
-@@ -18,6 +18,11 @@
- 		tick-timer = &timer0;
- 	};
- 
-+	memory@40000000 {
-+		device_type = "memory";
-+		reg = <0x40000000 0x10000000>;
-+	};
-+
- 	reg_3p3v: regulator-3p3v {
- 		  compatible = "regulator-fixed";
- 		  regulator-name = "fixed-3.3V";
---- a/arch/arm/dts/mt7981-rfb.dts
-+++ b/arch/arm/dts/mt7981-rfb.dts
-@@ -17,6 +17,11 @@
- 		stdout-path = &uart0;
- 		tick-timer = &timer0;
- 	};
-+
-+	memory@40000000 {
-+		device_type = "memory";
-+		reg = <0x40000000 0x10000000>;
-+	};
- };
- 
- &uart0 {
---- a/arch/arm/dts/mt7981-sd-rfb.dts
-+++ b/arch/arm/dts/mt7981-sd-rfb.dts
-@@ -18,6 +18,11 @@
- 		tick-timer = &timer0;
- 	};
- 
-+	memory@40000000 {
-+		device_type = "memory";
-+		reg = <0x40000000 0x10000000>;
-+	};
-+
- 	reg_3p3v: regulator-3p3v {
- 		  compatible = "regulator-fixed";
- 		  regulator-name = "fixed-3.3V";
---- a/arch/arm/dts/mt7986a-bpi-r3-sd.dts
-+++ b/arch/arm/dts/mt7986a-bpi-r3-sd.dts
-@@ -19,6 +19,11 @@
- 		tick-timer = &timer0;
- 	};
- 
-+	memory@40000000 {
-+		device_type = "memory";
-+		reg = <0x40000000 0x80000000>;
-+	};
-+
- 	reg_3p3v: regulator-3p3v {
- 		compatible = "regulator-fixed";
- 		regulator-name = "fixed-3.3V";
---- a/arch/arm/dts/mt7986a-rfb.dts
-+++ b/arch/arm/dts/mt7986a-rfb.dts
-@@ -18,6 +18,11 @@
- 		tick-timer = &timer0;
- 	};
- 
-+	memory@40000000 {
-+		device_type = "memory";
-+		reg = <0x40000000 0x10000000>;
-+	};
-+
- 	reg_1p8v: regulator-1p8v {
- 		compatible = "regulator-fixed";
- 		regulator-name = "fixed-1.8V";
---- a/arch/arm/dts/mt7986a-sd-rfb.dts
-+++ b/arch/arm/dts/mt7986a-sd-rfb.dts
-@@ -19,6 +19,11 @@
- 		tick-timer = &timer0;
- 	};
- 
-+	memory@40000000 {
-+		device_type = "memory";
-+		reg = <0x40000000 0x10000000>;
-+	};
-+
- 	reg_3p3v: regulator-3p3v {
- 		compatible = "regulator-fixed";
- 		regulator-name = "fixed-3.3V";
---- a/arch/arm/dts/mt7986b-rfb.dts
-+++ b/arch/arm/dts/mt7986b-rfb.dts
-@@ -18,6 +18,11 @@
- 		tick-timer = &timer0;
- 	};
- 
-+	memory@40000000 {
-+		device_type = "memory";
-+		reg = <0x40000000 0x10000000>;
-+	};
-+
- 	reg_3p3v: regulator-3p3v {
- 		compatible = "regulator-fixed";
- 		regulator-name = "fixed-3.3V";
---- a/arch/arm/dts/mt7986b-sd-rfb.dts
-+++ b/arch/arm/dts/mt7986b-sd-rfb.dts
-@@ -19,6 +19,11 @@
- 		tick-timer = &timer0;
- 	};
- 
-+	memory@40000000 {
-+		device_type = "memory";
-+		reg = <0x40000000 0x10000000>;
-+	};
-+
- 	reg_3p3v: regulator-3p3v {
- 		compatible = "regulator-fixed";
- 		regulator-name = "fixed-3.3V";
---- a/arch/arm/mach-mediatek/mt7622/init.c
-+++ b/arch/arm/mach-mediatek/mt7622/init.c
-@@ -4,11 +4,14 @@
-  * Author: Sam Shih <sam.shih@mediatek.com>
-  */
- 
--#include <common.h>
- #include <fdtdec.h>
- #include <init.h>
- #include <asm/armv8/mmu.h>
--#include <asm/cache.h>
-+#include <asm/global_data.h>
-+#include <asm/u-boot.h>
-+#include <linux/sizes.h>
-+
-+DECLARE_GLOBAL_DATA_PTR;
- 
- int print_cpuinfo(void)
- {
-@@ -20,11 +23,13 @@ int dram_init(void)
- {
- 	int ret;
- 
--	ret = fdtdec_setup_memory_banksize();
-+	ret = fdtdec_setup_mem_size_base();
- 	if (ret)
- 		return ret;
--	return fdtdec_setup_mem_size_base();
- 
-+	gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_2G);
-+
-+	return 0;
- }
- 
- void reset_cpu(void)
---- a/arch/arm/mach-mediatek/mt7981/init.c
-+++ b/arch/arm/mach-mediatek/mt7981/init.c
-@@ -4,18 +4,25 @@
-  * Author: Sam Shih <sam.shih@mediatek.com>
-  */
- 
--#include <cpu_func.h>
-+#include <fdtdec.h>
- #include <init.h>
- #include <asm/armv8/mmu.h>
- #include <asm/system.h>
- #include <asm/global_data.h>
-+#include <asm/u-boot.h>
- #include <linux/sizes.h>
- 
- DECLARE_GLOBAL_DATA_PTR;
- 
- int dram_init(void)
- {
--	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G);
-+	int ret;
-+
-+	ret = fdtdec_setup_mem_size_base();
-+	if (ret)
-+		return ret;
-+
-+	gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_1G);
- 
- 	return 0;
- }
---- a/arch/arm/mach-mediatek/mt7986/init.c
-+++ b/arch/arm/mach-mediatek/mt7986/init.c
-@@ -4,18 +4,25 @@
-  * Author: Sam Shih <sam.shih@mediatek.com>
-  */
- 
--#include <cpu_func.h>
-+#include <fdtdec.h>
- #include <init.h>
- #include <asm/armv8/mmu.h>
- #include <asm/system.h>
- #include <asm/global_data.h>
-+#include <asm/u-boot.h>
- #include <linux/sizes.h>
- 
- DECLARE_GLOBAL_DATA_PTR;
- 
- int dram_init(void)
- {
--	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G);
-+	int ret;
-+
-+	ret = fdtdec_setup_mem_size_base();
-+	if (ret)
-+		return ret;
-+
-+	gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_2G);
- 
- 	return 0;
- }
---- a/board/mediatek/mt7622/mt7622_rfb.c
-+++ b/board/mediatek/mt7622/mt7622_rfb.c
-@@ -19,7 +19,6 @@ DECLARE_GLOBAL_DATA_PTR;
- 
- int board_init(void)
- {
--	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
- 	return 0;
- }
- 
---- a/include/configs/mt7622.h
-+++ b/include/configs/mt7622.h
-@@ -9,14 +9,4 @@
- #ifndef __MT7622_H
- #define __MT7622_H
- 
--/* Uboot definition */
--#define CFG_SYS_UBOOT_BASE                   CONFIG_TEXT_BASE
--
--/* SPL -> Uboot */
--#define CFG_SYS_UBOOT_START		CONFIG_TEXT_BASE
--/* DRAM */
--#define CFG_SYS_SDRAM_BASE		0x40000000
--
--/* Ethernet */
--
- #endif
---- a/include/configs/mt7981.h
-+++ b/include/configs/mt7981.h
-@@ -9,13 +9,4 @@
- #ifndef __MT7981_H
- #define __MT7981_H
- 
--/* Uboot definition */
--#define CFG_SYS_UBOOT_BASE		CONFIG_TEXT_BASE
--
--/* SPL -> Uboot */
--#define CFG_SYS_UBOOT_START		CONFIG_TEXT_BASE
--
--/* DRAM */
--#define CFG_SYS_SDRAM_BASE		0x40000000
--
- #endif
---- a/include/configs/mt7986.h
-+++ b/include/configs/mt7986.h
-@@ -9,13 +9,4 @@
- #ifndef __MT7986_H
- #define __MT7986_H
- 
--/* Uboot definition */
--#define CFG_SYS_UBOOT_BASE		CONFIG_TEXT_BASE
--
--/* SPL -> Uboot */
--#define CFG_SYS_UBOOT_START		CONFIG_TEXT_BASE
--
--/* DRAM */
--#define CFG_SYS_SDRAM_BASE		0x40000000
--
- #endif

package/boot/uboot-mediatek/patches/101-02-board-mediatek-update-config-headers.patch

@@ -1,129 +0,0 @@
-From df3a0091b249ea82198ea019d145d05a7cf49c0d Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:15:47 +0800
-Subject: [PATCH 02/29] board: mediatek: update config headers
-
-Remove unused information from include/configs/mtxxxx.h
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- include/configs/mt7620.h |  3 +--
- include/configs/mt7621.h |  6 ++----
- include/configs/mt7623.h |  8 --------
- include/configs/mt7628.h |  5 ++---
- include/configs/mt7629.h | 13 +------------
- 5 files changed, 6 insertions(+), 29 deletions(-)
-
---- a/include/configs/mt7620.h
-+++ b/include/configs/mt7620.h
-@@ -10,10 +10,9 @@
- 
- #define CFG_SYS_SDRAM_BASE		0x80000000
- 
--#define CFG_SYS_INIT_SP_OFFSET	0x400000
-+#define CFG_SYS_INIT_SP_OFFSET		0x400000
- 
- /* SPL */
--
- #define CFG_SYS_UBOOT_START		CONFIG_TEXT_BASE
- 
- /* Dummy value */
---- a/include/configs/mt7621.h
-+++ b/include/configs/mt7621.h
-@@ -12,13 +12,11 @@
- 
- #define CFG_MAX_MEM_MAPPED		0x1c000000
- 
--#define CFG_SYS_INIT_SP_OFFSET	0x800000
-+#define CFG_SYS_INIT_SP_OFFSET		0x800000
- 
- /* MMC */
- #define MMC_SUPPORTS_TUNING
- 
--/* NAND */
--
- /* Serial SPL */
- #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
- #define CFG_SYS_NS16550_CLK		50000000
-@@ -26,7 +24,7 @@
- #endif
- 
- /* Serial common */
--#define CFG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
-+#define CFG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, 115200, \
- 					  230400, 460800, 921600 }
- 
- /* Dummy value */
---- a/include/configs/mt7623.h
-+++ b/include/configs/mt7623.h
-@@ -11,12 +11,6 @@
- 
- #include <linux/sizes.h>
- 
--/* Miscellaneous configurable options */
--
--/* Environment */
--
--/* Preloader -> Uboot */
--
- /* MMC */
- #define MMC_SUPPORTS_TUNING
- 
-@@ -32,8 +26,6 @@
- 	"fdt_addr_r=" FDT_HIGH "\0"			\
- 	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0"
- 
--/* Ethernet */
--
- #ifdef CONFIG_DISTRO_DEFAULTS
- 
- #define BOOT_TARGET_DEVICES(func)	\
---- a/include/configs/mt7628.h
-+++ b/include/configs/mt7628.h
-@@ -10,7 +10,7 @@
- 
- #define CFG_SYS_SDRAM_BASE		0x80000000
- 
--#define CFG_SYS_INIT_SP_OFFSET	0x80000
-+#define CFG_SYS_INIT_SP_OFFSET		0x80000
- 
- /* Serial SPL */
- #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
-@@ -19,11 +19,10 @@
- #endif
- 
- /* Serial common */
--#define CFG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
-+#define CFG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, 115200, \
- 					  230400, 460800, 921600 }
- 
- /* SPL */
--
- #define CFG_SYS_UBOOT_START		CONFIG_TEXT_BASE
- 
- /* Dummy value */
---- a/include/configs/mt7629.h
-+++ b/include/configs/mt7629.h
-@@ -9,21 +9,10 @@
- #ifndef __MT7629_H
- #define __MT7629_H
- 
--#include <linux/sizes.h>
--
--/* Miscellaneous configurable options */
--
--/* Environment */
--
-+/* SPL */
- #define CFG_SYS_UBOOT_BASE		(0x30000000 + CONFIG_SPL_PAD_TO)
- 
--/* SPL -> Uboot */
--
--/* UBoot -> Kernel */
--
- /* DRAM */
- #define CFG_SYS_SDRAM_BASE		0x40000000
- 
--/* Ethernet */
--
- #endif

package/boot/uboot-mediatek/patches/101-03-spi-mtk_spim-get-spi-clk-rate-only-once.patch

@@ -1,84 +0,0 @@
-From 0d6d8a408f80358dd47984320ea9c65e555ac4c9 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:15:54 +0800
-Subject: [PATCH 03/29] spi: mtk_spim: get spi clk rate only once
-
-We don't really need to switch clk rate during operating SPIM controller.
-Get clk rate only once at driver probing.
-
-Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
-Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
----
- drivers/spi/mtk_spim.c | 21 +++++++++++++--------
- 1 file changed, 13 insertions(+), 8 deletions(-)
-
---- a/drivers/spi/mtk_spim.c
-+++ b/drivers/spi/mtk_spim.c
-@@ -137,6 +137,8 @@ struct mtk_spim_capability {
-  * @state:		Controller state
-  * @sel_clk:		Pad clock
-  * @spi_clk:		Core clock
-+ * @pll_clk_rate:	Controller's PLL source clock rate, which is different
-+ *			from SPI bus clock rate
-  * @xfer_len:		Current length of data for transfer
-  * @hw_cap:		Controller capabilities
-  * @tick_dly:		Used to postpone SPI sampling time
-@@ -149,6 +151,7 @@ struct mtk_spim_priv {
- 	void __iomem *base;
- 	u32 state;
- 	struct clk sel_clk, spi_clk;
-+	u32 pll_clk_rate;
- 	u32 xfer_len;
- 	struct mtk_spim_capability hw_cap;
- 	u32 tick_dly;
-@@ -253,11 +256,10 @@ static int mtk_spim_hw_init(struct spi_s
- static void mtk_spim_prepare_transfer(struct mtk_spim_priv *priv,
- 				      u32 speed_hz)
- {
--	u32 spi_clk_hz, div, sck_time, cs_time, reg_val;
-+	u32 div, sck_time, cs_time, reg_val;
- 
--	spi_clk_hz = clk_get_rate(&priv->spi_clk);
--	if (speed_hz <= spi_clk_hz / 4)
--		div = DIV_ROUND_UP(spi_clk_hz, speed_hz);
-+	if (speed_hz <= priv->pll_clk_rate / 4)
-+		div = DIV_ROUND_UP(priv->pll_clk_rate, speed_hz);
- 	else
- 		div = 4;
- 
-@@ -404,7 +406,7 @@ static int mtk_spim_transfer_wait(struct
- {
- 	struct udevice *bus = dev_get_parent(slave->dev);
- 	struct mtk_spim_priv *priv = dev_get_priv(bus);
--	u32 sck_l, sck_h, spi_bus_clk, clk_count, reg;
-+	u32 sck_l, sck_h, clk_count, reg;
- 	ulong us = 1;
- 	int ret = 0;
- 
-@@ -413,12 +415,11 @@ static int mtk_spim_transfer_wait(struct
- 	else
- 		clk_count = op->data.nbytes;
- 
--	spi_bus_clk = clk_get_rate(&priv->spi_clk);
- 	sck_l = readl(priv->base + SPI_CFG2_REG) >> SPI_CFG2_SCK_LOW_OFFSET;
- 	sck_h = readl(priv->base + SPI_CFG2_REG) & SPI_CFG2_SCK_HIGH_MASK;
--	do_div(spi_bus_clk, sck_l + sck_h + 2);
-+	do_div(priv->pll_clk_rate, sck_l + sck_h + 2);
- 
--	us = CLK_TO_US(spi_bus_clk, clk_count * 8);
-+	us = CLK_TO_US(priv->pll_clk_rate, clk_count * 8);
- 	us += 1000 * 1000; /* 1s tolerance */
- 
- 	if (us > UINT_MAX)
-@@ -662,6 +663,10 @@ static int mtk_spim_probe(struct udevice
- 	clk_enable(&priv->sel_clk);
- 	clk_enable(&priv->spi_clk);
- 
-+	priv->pll_clk_rate = clk_get_rate(&priv->spi_clk);
-+	if (priv->pll_clk_rate == 0)
-+		return -EINVAL;
-+
- 	return 0;
- }
- 

package/boot/uboot-mediatek/patches/101-04-spi-mtk_spim-clear-IRQ-enable-bits.patch

@@ -1,35 +0,0 @@
-From a7b630f02bb12f71f23866aee6f9a1a07497d475 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:02 +0800
-Subject: [PATCH 04/29] spi: mtk_spim: clear IRQ enable bits
-
-In u-boot we don't use IRQ. Instead, we poll busy bit in SPI_STATUS.
-
-However these IRQ enable bits may be set in previous boot stage (BootROM).
-
-If we leave these bits not cleared, although u-boot has disabled IRQ and
-nothing will happen, the linux kernel may encounter panic during
-initializing the spim driver due to IRQ event happens before IRQ handler
-is properly setup.
-
-This patch clear IRQ bits to prevent this from happening.
-
-Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
-Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
----
- drivers/spi/mtk_spim.c | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/drivers/spi/mtk_spim.c
-+++ b/drivers/spi/mtk_spim.c
-@@ -242,6 +242,9 @@ static int mtk_spim_hw_init(struct spi_s
- 			reg_val &= ~SPI_CMD_SAMPLE_SEL;
- 	}
- 
-+	/* Disable interrupt enable for pause mode & normal mode */
-+	reg_val &= ~(SPI_CMD_PAUSE_IE | SPI_CMD_FINISH_IE);
-+
- 	/* disable dma mode */
- 	reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);
- 

package/boot/uboot-mediatek/patches/101-05-serial-mtk-initial-priv-data-before-using.patch

@@ -1,25 +0,0 @@
-From 73060da8b54e74c51ef6c1fd31c4fac6ad6b8d0e Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:07 +0800
-Subject: [PATCH 05/29] serial: mtk: initial priv data before using
-
-This patch ensures driver private data being fully initialized in
-_debug_uart_init which is not covered by .priv_auto ops.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
-Reviewed-by: Stefan Roese <sr@denx.de>
----
- drivers/serial/serial_mtk.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/serial/serial_mtk.c
-+++ b/drivers/serial/serial_mtk.c
-@@ -439,6 +439,7 @@ static inline void _debug_uart_init(void
- {
- 	struct mtk_serial_priv priv;
- 
-+	memset(&priv, 0, sizeof(struct mtk_serial_priv));
- 	priv.regs = (void *) CONFIG_VAL(DEBUG_UART_BASE);
- 	priv.fixed_clk_rate = CONFIG_DEBUG_UART_CLOCK;
- 

package/boot/uboot-mediatek/patches/101-06-reset-mediatek-check-malloc-return-valaue-before-use.patch

@@ -1,26 +0,0 @@
-From 06e6d224f7d564a34407eba21b51797da7f22628 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:11 +0800
-Subject: [PATCH 06/29] reset: mediatek: check malloc return valaue before use
-
-This patch add missing return value check for allocating the driver's
-private data. -ENOMEM will be returned if malloc() fails.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/reset/reset-mediatek.c | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/drivers/reset/reset-mediatek.c
-+++ b/drivers/reset/reset-mediatek.c
-@@ -79,6 +79,9 @@ int mediatek_reset_bind(struct udevice *
- 		return ret;
- 
- 	priv = malloc(sizeof(struct mediatek_reset_priv));
-+	if (!priv)
-+		return -ENOMEM;
-+
- 	priv->regofs = regofs;
- 	priv->nr_resets = num_regs * 32;
- 	dev_set_priv(rst_dev, priv);

package/boot/uboot-mediatek/patches/101-07-i2c-mediatek-fix-I2C-usability-for-MT7981.patch

@@ -1,125 +0,0 @@
-From 77898faf6ce56eb08109cdb853f074bad5acee55 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:15 +0800
-Subject: [PATCH 07/29] i2c: mediatek: fix I2C usability for MT7981
-
-MT7981 actually uses MediaTek I2C controller v3 instead of v1.
-This patch adds support for I2C controller v3 fix fixes the I2C usability
-for MT7981.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/i2c/mtk_i2c.c | 45 +++++++++++++++++++++++++++++++++++++++++--
- 1 file changed, 43 insertions(+), 2 deletions(-)
-
---- a/drivers/i2c/mtk_i2c.c
-+++ b/drivers/i2c/mtk_i2c.c
-@@ -183,9 +183,36 @@ static const uint mt_i2c_regs_v2[] = {
- 	[REG_DCM_EN] = 0xf88,
- };
- 
-+static const uint mt_i2c_regs_v3[] = {
-+	[REG_PORT] = 0x0,
-+	[REG_INTR_MASK] = 0x8,
-+	[REG_INTR_STAT] = 0xc,
-+	[REG_CONTROL] = 0x10,
-+	[REG_TRANSFER_LEN] = 0x14,
-+	[REG_TRANSAC_LEN] = 0x18,
-+	[REG_DELAY_LEN] = 0x1c,
-+	[REG_TIMING] = 0x20,
-+	[REG_START] = 0x24,
-+	[REG_EXT_CONF] = 0x28,
-+	[REG_LTIMING] = 0x2c,
-+	[REG_HS] = 0x30,
-+	[REG_IO_CONFIG] = 0x34,
-+	[REG_FIFO_ADDR_CLR] = 0x38,
-+	[REG_TRANSFER_LEN_AUX] = 0x44,
-+	[REG_CLOCK_DIV] = 0x48,
-+	[REG_SOFTRESET] = 0x50,
-+	[REG_SLAVE_ADDR] = 0x94,
-+	[REG_DEBUGSTAT] = 0xe4,
-+	[REG_DEBUGCTRL] = 0xe8,
-+	[REG_FIFO_STAT] = 0xf4,
-+	[REG_FIFO_THRESH] = 0xf8,
-+	[REG_DCM_EN] = 0xf88,
-+};
-+
- struct mtk_i2c_soc_data {
- 	const uint *regs;
- 	uint dma_sync: 1;
-+	uint ltiming_adjust: 1;
- };
- 
- struct mtk_i2c_priv {
-@@ -401,6 +428,10 @@ static int mtk_i2c_set_speed(struct udev
- 				(sample_cnt << HS_SAMPLE_OFFSET) |
- 				(step_cnt << HS_STEP_OFFSET);
- 		i2c_writel(priv, REG_HS, high_speed_reg);
-+		if (priv->soc_data->ltiming_adjust) {
-+			timing_reg = (sample_cnt << 12) | (step_cnt << 9);
-+			i2c_writel(priv, REG_LTIMING, timing_reg);
-+		}
- 	} else {
- 		ret = mtk_i2c_calculate_speed(clk_src, priv->speed,
- 					      &step_cnt, &sample_cnt);
-@@ -412,7 +443,12 @@ static int mtk_i2c_set_speed(struct udev
- 		high_speed_reg = I2C_TIME_CLR_VALUE;
- 		i2c_writel(priv, REG_TIMING, timing_reg);
- 		i2c_writel(priv, REG_HS, high_speed_reg);
-+		if (priv->soc_data->ltiming_adjust) {
-+			timing_reg = (sample_cnt << 6) | step_cnt;
-+			i2c_writel(priv, REG_LTIMING, timing_reg);
-+		}
- 	}
-+
- exit:
- 	if (mtk_i2c_clk_disable(priv))
- 		return log_msg_ret("set_speed disable clk", -1);
-@@ -725,7 +761,6 @@ static int mtk_i2c_probe(struct udevice
- 		return log_msg_ret("probe enable clk", -1);
- 
- 	mtk_i2c_init_hw(priv);
--
- 	if (mtk_i2c_clk_disable(priv))
- 		return log_msg_ret("probe disable clk", -1);
- 
-@@ -750,31 +785,37 @@ static int mtk_i2c_deblock(struct udevic
- static const struct mtk_i2c_soc_data mt76xx_soc_data = {
- 	.regs = mt_i2c_regs_v1,
- 	.dma_sync = 0,
-+	.ltiming_adjust = 0,
- };
- 
- static const struct mtk_i2c_soc_data mt7981_soc_data = {
--	.regs = mt_i2c_regs_v1,
-+	.regs = mt_i2c_regs_v3,
- 	.dma_sync = 1,
-+	.ltiming_adjust = 1,
- };
- 
- static const struct mtk_i2c_soc_data mt7986_soc_data = {
- 	.regs = mt_i2c_regs_v1,
- 	.dma_sync = 1,
-+	.ltiming_adjust = 0,
- };
- 
- static const struct mtk_i2c_soc_data mt8183_soc_data = {
- 	.regs = mt_i2c_regs_v2,
- 	.dma_sync = 1,
-+	.ltiming_adjust = 0,
- };
- 
- static const struct mtk_i2c_soc_data mt8518_soc_data = {
- 	.regs = mt_i2c_regs_v1,
- 	.dma_sync = 0,
-+	.ltiming_adjust = 0,
- };
- 
- static const struct mtk_i2c_soc_data mt8512_soc_data = {
- 	.regs = mt_i2c_regs_v1,
- 	.dma_sync = 1,
-+	.ltiming_adjust = 0,
- };
- 
- static const struct dm_i2c_ops mtk_i2c_ops = {

package/boot/uboot-mediatek/patches/101-08-arm-dts-enable-i2c-support-for-MediaTek-MT7981.patch

@@ -1,36 +0,0 @@
-From e9467f40d4327cfcb80944a0f12ae195b0d7cd40 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:19 +0800
-Subject: [PATCH 08/29] arm: dts: enable i2c support for MediaTek MT7981
-
-This patch enables i2c support for MediaTek MT7981
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- arch/arm/dts/mt7981.dtsi | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/arch/arm/dts/mt7981.dtsi
-+++ b/arch/arm/dts/mt7981.dtsi
-@@ -181,6 +181,20 @@
- 		status = "disabled";
- 	};
- 
-+	i2c0: i2c@11007000 {
-+		compatible = "mediatek,mt7981-i2c";
-+		reg = <0x11007000 0x1000>,
-+		      <0x10217080 0x80>;
-+		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
-+		clock-div = <1>;
-+		clocks = <&infracfg_ao CK_INFRA_I2CO_CK>,
-+			 <&infracfg_ao CK_INFRA_AP_DMA_CK>;
-+		clock-names = "main", "dma";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		status = "disabled";
-+	};
-+
- 	uart0: serial@11002000 {
- 		compatible = "mediatek,hsuart";
- 		reg = <0x11002000 0x400>;

package/boot/uboot-mediatek/patches/101-09-pwm-mtk-add-support-for-MediaTek-MT7988-SoC.patch

@@ -1,34 +0,0 @@
-From 646dab4a8e853b2d0789fa2ff64e7c48f5396cfa Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:24 +0800
-Subject: [PATCH 09/29] pwm: mtk: add support for MediaTek MT7988 SoC
-
-This patch adds PWM support for MediaTek MT7988 SoC.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/pwm/pwm-mtk.c | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/drivers/pwm/pwm-mtk.c
-+++ b/drivers/pwm/pwm-mtk.c
-@@ -205,12 +205,19 @@ static const struct mtk_pwm_soc mt7986_d
- 	.reg_ver = PWM_REG_V1,
- };
- 
-+static const struct mtk_pwm_soc mt7988_data = {
-+	.num_pwms = 8,
-+	.pwm45_fixup = false,
-+	.reg_ver = PWM_REG_V2,
-+};
-+
- static const struct udevice_id mtk_pwm_ids[] = {
- 	{ .compatible = "mediatek,mt7622-pwm", .data = (ulong)&mt7622_data },
- 	{ .compatible = "mediatek,mt7623-pwm", .data = (ulong)&mt7623_data },
- 	{ .compatible = "mediatek,mt7629-pwm", .data = (ulong)&mt7629_data },
- 	{ .compatible = "mediatek,mt7981-pwm", .data = (ulong)&mt7981_data },
- 	{ .compatible = "mediatek,mt7986-pwm", .data = (ulong)&mt7986_data },
-+	{ .compatible = "mediatek,mt7988-pwm", .data = (ulong)&mt7988_data },
- 	{ }
- };
- 

package/boot/uboot-mediatek/patches/101-11-reset-mediatek-add-reset-definition-for-MediaTek-MT7.patch

@@ -1,49 +0,0 @@
-From b4a308dd31a7c6754be230849a5e430052268b9c Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:33 +0800
-Subject: [PATCH 11/29] reset: mediatek: add reset definition for MediaTek
- MT7988 SoC
-
-This patch adds reset bits for MediaTek MT7988
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- include/dt-bindings/reset/mt7988-reset.h | 31 ++++++++++++++++++++++++
- 1 file changed, 31 insertions(+)
- create mode 100644 include/dt-bindings/reset/mt7988-reset.h
-
---- /dev/null
-+++ b/include/dt-bindings/reset/mt7988-reset.h
-@@ -0,0 +1,31 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * Copyright (C) 2023 MediaTek Inc.
-+ */
-+
-+#ifndef _DT_BINDINGS_MTK_RESET_H_
-+#define _DT_BINDINGS_MTK_RESET_H_
-+
-+/* ETHDMA Subsystem resets */
-+#define ETHDMA_FE_RST			6
-+#define ETHDMA_PMTR_RST			8
-+#define ETHDMA_GMAC_RST			23
-+#define ETHDMA_WDMA0_RST		24
-+#define ETHDMA_WDMA1_RST		25
-+#define ETHDMA_WDMA2_RST		26
-+#define ETHDMA_PPE0_RST			29
-+#define ETHDMA_PPE1_RST			30
-+#define ETHDMA_PPE2_RST			31
-+
-+/* ETHWARP Subsystem resets */
-+#define ETHWARP_GSW_RST			9
-+#define ETHWARP_EIP197_RST		10
-+#define ETHWARP_WOCPU0_RST		32
-+#define ETHWARP_WOCPU1_RST		33
-+#define ETHWARP_WOCPU2_RST		34
-+#define ETHWARP_WOX_NET_MUX_RST		35
-+#define ETHWARP_WED0_RST		36
-+#define ETHWARP_WED1_RST		37
-+#define ETHWARP_WED2_RST		38
-+
-+#endif /* _DT_BINDINGS_MTK_RESET_H_ */

package/boot/uboot-mediatek/patches/101-13-pinctrl-mediatek-fix-the-return-value-in-driving-con.patch

@@ -1,37 +0,0 @@
-From 783c46d29f8b186bd65f3e83f38ad883e8bcec69 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:42 +0800
-Subject: [PATCH 13/29] pinctrl: mediatek: fix the return value in driving
- configuration functions
-
-The original mediatek pinctrl functions for driving configuration
-'mtk_pinconf_drive_set_*' do not return -ENOSUPP even if input
-parameters are not supported.
-This patch fixes the return value in those functions.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
-@@ -513,7 +513,7 @@ int mtk_pinconf_drive_set_v0(struct udev
- 			return err;
- 	}
- 
--	return 0;
-+	return err;
- }
- 
- int mtk_pinconf_drive_set_v1(struct udevice *dev, u32 pin, u32 arg)
-@@ -531,7 +531,7 @@ int mtk_pinconf_drive_set_v1(struct udev
- 			return err;
- 	}
- 
--	return 0;
-+	return err;
- }
- 
- int mtk_pinconf_drive_set(struct udevice *dev, u32 pin, u32 arg)

package/boot/uboot-mediatek/patches/101-14-pinctrl-mediatek-add-pinmux_set-ops-support.patch

@@ -1,43 +0,0 @@
-From 090351b416e57e0f7b5d1a4c87d4ed9ab4f5c89b Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:46 +0800
-Subject: [PATCH 14/29] pinctrl: mediatek: add pinmux_set ops support
-
-This patch adds pinmux_set ops for mediatek pinctrl framework
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
-@@ -304,6 +304,19 @@ static const char *mtk_get_function_name
- 	return priv->soc->funcs[selector].name;
- }
- 
-+static int mtk_pinmux_set(struct udevice *dev, unsigned int pin_selector,
-+			  unsigned int func_selector)
-+{
-+	int err;
-+
-+	err = mtk_hw_set_value(dev, pin_selector, PINCTRL_PIN_REG_MODE,
-+			       func_selector);
-+	if (err)
-+		return err;
-+
-+	return 0;
-+}
-+
- static int mtk_pinmux_group_set(struct udevice *dev,
- 				unsigned int group_selector,
- 				unsigned int func_selector)
-@@ -647,6 +660,7 @@ const struct pinctrl_ops mtk_pinctrl_ops
- 	.get_group_name = mtk_get_group_name,
- 	.get_functions_count = mtk_get_functions_count,
- 	.get_function_name = mtk_get_function_name,
-+	.pinmux_set = mtk_pinmux_set,
- 	.pinmux_group_set = mtk_pinmux_group_set,
- #if CONFIG_IS_ENABLED(PINCONF)
- 	.pinconf_num_params = ARRAY_SIZE(mtk_conf_params),

package/boot/uboot-mediatek/patches/101-16-net-mediatek-connect-switch-to-PSE-only-when-startin.patch

@@ -1,138 +0,0 @@
-From a0405999ebecf21ed9f76f1dc9420682cd3feba0 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:54 +0800
-Subject: [PATCH 16/29] net: mediatek: connect switch to PSE only when starting
- eth is requested
-
-So far the switch is initialized in probe stage and is connected to PSE
-unconditionally. This will cause all packets being flooded to PSE and may
-cause PSE hang before entering linux.
-
-This patch changes the connection between switch and PSE:
-- Still initialize switch in probe stage, but disconnect it with PSE
-- Connect switch with PSE on eth start
-- Disconnect on eth stop
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/net/mtk_eth.c | 44 ++++++++++++++++++++++++++++++++++++++++---
- 1 file changed, 41 insertions(+), 3 deletions(-)
-
---- a/drivers/net/mtk_eth.c
-+++ b/drivers/net/mtk_eth.c
-@@ -123,8 +123,10 @@ struct mtk_eth_priv {
- 
- 	enum mtk_switch sw;
- 	int (*switch_init)(struct mtk_eth_priv *priv);
-+	void (*switch_mac_control)(struct mtk_eth_priv *priv, bool enable);
- 	u32 mt753x_smi_addr;
- 	u32 mt753x_phy_base;
-+	u32 mt753x_pmcr;
- 
- 	struct gpio_desc rst_gpio;
- 	int mcm;
-@@ -613,6 +615,16 @@ static int mt7530_pad_clk_setup(struct m
- 	return 0;
- }
- 
-+static void mt7530_mac_control(struct mtk_eth_priv *priv, bool enable)
-+{
-+	u32 pmcr = FORCE_MODE;
-+
-+	if (enable)
-+		pmcr = priv->mt753x_pmcr;
-+
-+	mt753x_reg_write(priv, PMCR_REG(6), pmcr);
-+}
-+
- static int mt7530_setup(struct mtk_eth_priv *priv)
- {
- 	u16 phy_addr, phy_val;
-@@ -663,11 +675,14 @@ static int mt7530_setup(struct mtk_eth_p
- 	      FORCE_DPX | FORCE_LINK;
- 
- 	/* MT7530 Port6: Forced 1000M/FD, FC disabled */
--	mt753x_reg_write(priv, PMCR_REG(6), val);
-+	priv->mt753x_pmcr = val;
- 
- 	/* MT7530 Port5: Forced link down */
- 	mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE);
- 
-+	/* Keep MAC link down before starting eth */
-+	mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE);
-+
- 	/* MT7530 Port6: Set to RGMII */
- 	mt753x_reg_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_M, P6_INTF_MODE_RGMII);
- 
-@@ -823,6 +838,17 @@ static void mt7531_phy_setting(struct mt
- 	}
- }
- 
-+static void mt7531_mac_control(struct mtk_eth_priv *priv, bool enable)
-+{
-+	u32 pmcr = FORCE_MODE_LNK;
-+
-+	if (enable)
-+		pmcr = priv->mt753x_pmcr;
-+
-+	mt753x_reg_write(priv, PMCR_REG(5), pmcr);
-+	mt753x_reg_write(priv, PMCR_REG(6), pmcr);
-+}
-+
- static int mt7531_setup(struct mtk_eth_priv *priv)
- {
- 	u16 phy_addr, phy_val;
-@@ -882,8 +908,11 @@ static int mt7531_setup(struct mtk_eth_p
- 	       (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX |
- 	       FORCE_LINK;
- 
--	mt753x_reg_write(priv, PMCR_REG(5), pmcr);
--	mt753x_reg_write(priv, PMCR_REG(6), pmcr);
-+	priv->mt753x_pmcr = pmcr;
-+
-+	/* Keep MAC link down before starting eth */
-+	mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE_LNK);
-+	mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK);
- 
- 	/* Turn on PHYs */
- 	for (i = 0; i < MT753X_NUM_PHYS; i++) {
-@@ -1227,6 +1256,9 @@ static int mtk_eth_start(struct udevice
- 
- 	mtk_eth_fifo_init(priv);
- 
-+	if (priv->switch_mac_control)
-+		priv->switch_mac_control(priv, true);
-+
- 	/* Start PHY */
- 	if (priv->sw == SW_NONE) {
- 		ret = mtk_phy_start(priv);
-@@ -1245,6 +1277,9 @@ static void mtk_eth_stop(struct udevice
- {
- 	struct mtk_eth_priv *priv = dev_get_priv(dev);
- 
-+	if (priv->switch_mac_control)
-+		priv->switch_mac_control(priv, false);
-+
- 	mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG,
- 		     TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN, 0);
- 	udelay(500);
-@@ -1484,16 +1519,19 @@ static int mtk_eth_of_to_plat(struct ude
- 	/* check for switch first, otherwise phy will be used */
- 	priv->sw = SW_NONE;
- 	priv->switch_init = NULL;
-+	priv->switch_mac_control = NULL;
- 	str = dev_read_string(dev, "mediatek,switch");
- 
- 	if (str) {
- 		if (!strcmp(str, "mt7530")) {
- 			priv->sw = SW_MT7530;
- 			priv->switch_init = mt7530_setup;
-+			priv->switch_mac_control = mt7530_mac_control;
- 			priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
- 		} else if (!strcmp(str, "mt7531")) {
- 			priv->sw = SW_MT7531;
- 			priv->switch_init = mt7531_setup;
-+			priv->switch_mac_control = mt7531_mac_control;
- 			priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
- 		} else {
- 			printf("error: unsupported switch\n");

package/boot/uboot-mediatek/patches/101-17-net-mediatek-optimize-the-switch-reset-delay-wait-ti.patch

@@ -1,56 +0,0 @@
-From d9a52701f6677889cc3332ab7a888f35cd69cc76 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:59 +0800
-Subject: [PATCH 17/29] net: mediatek: optimize the switch reset delay wait
- time
-
-Not all switches requires 1 second delay after deasserting reset.
-MT7531 requires only maximum 200ms.
-
-This patch defines dedicated reset wait time for each switch chip, and will
-significantly improve the boot time for boards using MT7531.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/net/mtk_eth.c | 7 +++++--
- 1 file changed, 5 insertions(+), 2 deletions(-)
-
---- a/drivers/net/mtk_eth.c
-+++ b/drivers/net/mtk_eth.c
-@@ -127,6 +127,7 @@ struct mtk_eth_priv {
- 	u32 mt753x_smi_addr;
- 	u32 mt753x_phy_base;
- 	u32 mt753x_pmcr;
-+	u32 mt753x_reset_wait_time;
- 
- 	struct gpio_desc rst_gpio;
- 	int mcm;
-@@ -943,12 +944,12 @@ int mt753x_switch_init(struct mtk_eth_pr
- 		reset_assert(&priv->rst_mcm);
- 		udelay(1000);
- 		reset_deassert(&priv->rst_mcm);
--		mdelay(1000);
-+		mdelay(priv->mt753x_reset_wait_time);
- 	} else if (dm_gpio_is_valid(&priv->rst_gpio)) {
- 		dm_gpio_set_value(&priv->rst_gpio, 0);
- 		udelay(1000);
- 		dm_gpio_set_value(&priv->rst_gpio, 1);
--		mdelay(1000);
-+		mdelay(priv->mt753x_reset_wait_time);
- 	}
- 
- 	ret = priv->switch_init(priv);
-@@ -1528,11 +1529,13 @@ static int mtk_eth_of_to_plat(struct ude
- 			priv->switch_init = mt7530_setup;
- 			priv->switch_mac_control = mt7530_mac_control;
- 			priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
-+			priv->mt753x_reset_wait_time = 1000;
- 		} else if (!strcmp(str, "mt7531")) {
- 			priv->sw = SW_MT7531;
- 			priv->switch_init = mt7531_setup;
- 			priv->switch_mac_control = mt7531_mac_control;
- 			priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
-+			priv->mt753x_reset_wait_time = 200;
- 		} else {
- 			printf("error: unsupported switch\n");
- 			return -EINVAL;

package/boot/uboot-mediatek/patches/101-18-net-mediatek-fix-direct-MDIO-clause-45-access-via-So.patch

@@ -1,34 +0,0 @@
-From c44f6ac1a31961b0d4faf982ee42167de5ac1672 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:03 +0800
-Subject: [PATCH 18/29] net: mediatek: fix direct MDIO clause 45 access via SoC
-
-The original direct MDIO clause 45 access via SoC is missing the
-data output. This patch adds it back to ensure MDIO clause 45 can
-work properly for external PHYs.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/net/mtk_eth.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/net/mtk_eth.c
-+++ b/drivers/net/mtk_eth.c
-@@ -198,7 +198,7 @@ static int mtk_mii_rw(struct mtk_eth_pri
- 	      (((u32)phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) |
- 	      (((u32)reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M);
- 
--	if (cmd == MDIO_CMD_WRITE)
-+	if (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR)
- 		val |= data & MDIO_RW_DATA_M;
- 
- 	mtk_gmac_write(priv, GMAC_PIAC_REG, val | PHY_ACS_ST);
-@@ -210,7 +210,7 @@ static int mtk_mii_rw(struct mtk_eth_pri
- 		return ret;
- 	}
- 
--	if (cmd == MDIO_CMD_READ) {
-+	if (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) {
- 		val = mtk_gmac_read(priv, GMAC_PIAC_REG);
- 		return val & MDIO_RW_DATA_M;
- 	}

package/boot/uboot-mediatek/patches/101-19-net-mediatek-add-missing-static-qualifier.patch

@@ -1,36 +0,0 @@
-From 9d35558bedfb82860c63cc11d3426afcbd82cb5c Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:07 +0800
-Subject: [PATCH 19/29] net: mediatek: add missing static qualifier
-
-mt7531_mmd_ind_read and mt753x_switch_init are defined without static.
-Since they're not used outside this file, we should add them back.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
-
-fixup to add static qualifier
----
- drivers/net/mtk_eth.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/drivers/net/mtk_eth.c
-+++ b/drivers/net/mtk_eth.c
-@@ -436,7 +436,8 @@ static int mt7531_mii_ind_write(struct m
- 			     MDIO_ST_C22);
- }
- 
--int mt7531_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg)
-+static int mt7531_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad,
-+			       u16 reg)
- {
- 	u8 phy_addr;
- 	int ret;
-@@ -934,7 +935,7 @@ static int mt7531_setup(struct mtk_eth_p
- 	return 0;
- }
- 
--int mt753x_switch_init(struct mtk_eth_priv *priv)
-+static int mt753x_switch_init(struct mtk_eth_priv *priv)
- {
- 	int ret;
- 	int i;

package/boot/uboot-mediatek/patches/101-20-net-mediatek-add-support-for-SGMII-1Gbps-auto-negoti.patch

@@ -1,149 +0,0 @@
-From 8e59c3cc700a6efb8db574f3c8e18b6181b4a07d Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:13 +0800
-Subject: [PATCH 20/29] net: mediatek: add support for SGMII 1Gbps
- auto-negotiation mode
-
-Existing SGMII support of mtk-eth is actually a MediaTek-specific
-2.5Gbps high-speed SGMII (HSGMII) which does not support
-auto-negotiation mode.
-
-This patch adds SGMII 1Gbps auto-negotiation mode and rename the
-existing HSGMII to 2500basex.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/net/mtk_eth.c | 46 +++++++++++++++++++++++++++++++++++++------
- drivers/net/mtk_eth.h |  2 ++
- 2 files changed, 42 insertions(+), 6 deletions(-)
-
---- a/drivers/net/mtk_eth.c
-+++ b/drivers/net/mtk_eth.c
-@@ -893,7 +893,7 @@ static int mt7531_setup(struct mtk_eth_p
- 		if (!port5_sgmii)
- 			mt7531_port_rgmii_init(priv, 5);
- 		break;
--	case PHY_INTERFACE_MODE_SGMII:
-+	case PHY_INTERFACE_MODE_2500BASEX:
- 		mt7531_port_sgmii_init(priv, 6);
- 		if (port5_sgmii)
- 			mt7531_port_sgmii_init(priv, 5);
-@@ -986,6 +986,7 @@ static void mtk_phy_link_adjust(struct m
- 	      (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) |
- 	      MAC_MODE | FORCE_MODE |
- 	      MAC_TX_EN | MAC_RX_EN |
-+	      DEL_RXFIFO_CLR |
- 	      BKOFF_EN | BACKPR_EN;
- 
- 	switch (priv->phydev->speed) {
-@@ -996,6 +997,7 @@ static void mtk_phy_link_adjust(struct m
- 		mcr |= (SPEED_100M << FORCE_SPD_S);
- 		break;
- 	case SPEED_1000:
-+	case SPEED_2500:
- 		mcr |= (SPEED_1000M << FORCE_SPD_S);
- 		break;
- 	};
-@@ -1048,7 +1050,8 @@ static int mtk_phy_start(struct mtk_eth_
- 		return 0;
- 	}
- 
--	mtk_phy_link_adjust(priv);
-+	if (!priv->force_mode)
-+		mtk_phy_link_adjust(priv);
- 
- 	debug("Speed: %d, %s duplex%s\n", phydev->speed,
- 	      (phydev->duplex) ? "full" : "half",
-@@ -1076,7 +1079,31 @@ static int mtk_phy_probe(struct udevice
- 	return 0;
- }
- 
--static void mtk_sgmii_init(struct mtk_eth_priv *priv)
-+static void mtk_sgmii_an_init(struct mtk_eth_priv *priv)
-+{
-+	/* Set SGMII GEN1 speed(1G) */
-+	clrsetbits_le32(priv->sgmii_base + priv->soc->ana_rgc3,
-+			SGMSYS_SPEED_2500, 0);
-+
-+	/* Enable SGMII AN */
-+	setbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1,
-+		     SGMII_AN_ENABLE);
-+
-+	/* SGMII AN mode setting */
-+	writel(SGMII_AN_MODE, priv->sgmii_base + SGMSYS_SGMII_MODE);
-+
-+	/* SGMII PN SWAP setting */
-+	if (priv->pn_swap) {
-+		setbits_le32(priv->sgmii_base + SGMSYS_QPHY_WRAP_CTRL,
-+			     SGMII_PN_SWAP_TX_RX);
-+	}
-+
-+	/* Release PHYA power down state */
-+	clrsetbits_le32(priv->sgmii_base + SGMSYS_QPHY_PWR_STATE_CTRL,
-+			SGMII_PHYA_PWD, 0);
-+}
-+
-+static void mtk_sgmii_force_init(struct mtk_eth_priv *priv)
- {
- 	/* Set SGMII GEN2 speed(2.5G) */
- 	setbits_le32(priv->sgmii_base + priv->soc->ana_rgc3,
-@@ -1111,10 +1138,14 @@ static void mtk_mac_init(struct mtk_eth_
- 		ge_mode = GE_MODE_RGMII;
- 		break;
- 	case PHY_INTERFACE_MODE_SGMII:
-+	case PHY_INTERFACE_MODE_2500BASEX:
- 		ge_mode = GE_MODE_RGMII;
- 		mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, SYSCFG0_SGMII_SEL_M,
- 			       SYSCFG0_SGMII_SEL(priv->gmac_id));
--		mtk_sgmii_init(priv);
-+		if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
-+			mtk_sgmii_an_init(priv);
-+		else
-+			mtk_sgmii_force_init(priv);
- 		break;
- 	case PHY_INTERFACE_MODE_MII:
- 	case PHY_INTERFACE_MODE_GMII:
-@@ -1148,6 +1179,7 @@ static void mtk_mac_init(struct mtk_eth_
- 			mcr |= SPEED_100M << FORCE_SPD_S;
- 			break;
- 		case SPEED_1000:
-+		case SPEED_2500:
- 			mcr |= SPEED_1000M << FORCE_SPD_S;
- 			break;
- 		}
-@@ -1490,13 +1522,15 @@ static int mtk_eth_of_to_plat(struct ude
- 		priv->duplex = ofnode_read_bool(subnode, "full-duplex");
- 
- 		if (priv->speed != SPEED_10 && priv->speed != SPEED_100 &&
--		    priv->speed != SPEED_1000) {
-+		    priv->speed != SPEED_1000 && priv->speed != SPEED_2500 &&
-+		    priv->speed != SPEED_10000) {
- 			printf("error: no valid speed set in fixed-link\n");
- 			return -EINVAL;
- 		}
- 	}
- 
--	if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) {
-+	if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII ||
-+	    priv->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
- 		/* get corresponding sgmii phandle */
- 		ret = dev_read_phandle_with_args(dev, "mediatek,sgmiisys",
- 						 NULL, 0, 0, &args);
---- a/drivers/net/mtk_eth.h
-+++ b/drivers/net/mtk_eth.h
-@@ -69,6 +69,7 @@ enum mkt_eth_capabilities {
- #define SGMII_AN_RESTART		BIT(9)
- 
- #define SGMSYS_SGMII_MODE		0x20
-+#define SGMII_AN_MODE			0x31120103
- #define SGMII_FORCE_MODE		0x31120019
- 
- #define SGMSYS_QPHY_PWR_STATE_CTRL	0xe8
-@@ -168,6 +169,7 @@ enum mkt_eth_capabilities {
- #define FORCE_MODE			BIT(15)
- #define MAC_TX_EN			BIT(14)
- #define MAC_RX_EN			BIT(13)
-+#define DEL_RXFIFO_CLR			BIT(12)
- #define BKOFF_EN			BIT(9)
- #define BACKPR_EN			BIT(8)
- #define FORCE_RX_FC			BIT(5)

package/boot/uboot-mediatek/patches/101-21-arm-dts-medaitek-convert-gmac-link-mode-to-2500base-.patch

@@ -1,214 +0,0 @@
-From 64ef7e977767e3b1305fb94a5169d8b7d3b19b6c Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:18 +0800
-Subject: [PATCH 21/29] arm: dts: mediatek: convert gmac link mode to
- 2500base-x
-
-Now that individual 2.5Gbps SGMII support has been added to
-mtk-eth, all boards that use 2.5Gbps link with mt7531 must be
-converted to use "2500base-x" instead of "sgmii".
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
-[also convert BPi-R3]
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- arch/arm/dts/mt7622-bananapi-bpi-r64.dts | 4 ++--
- arch/arm/dts/mt7622-rfb.dts              | 4 ++--
- arch/arm/dts/mt7629-rfb.dts              | 4 ++--
- arch/arm/dts/mt7981-emmc-rfb.dts         | 4 ++--
- arch/arm/dts/mt7981-rfb.dts              | 4 ++--
- arch/arm/dts/mt7981-sd-rfb.dts           | 4 ++--
- arch/arm/dts/mt7986a-bpi-r3-sd.dts       | 4 ++--
- arch/arm/dts/mt7986a-rfb.dts             | 4 ++--
- arch/arm/dts/mt7986a-sd-rfb.dts          | 4 ++--
- arch/arm/dts/mt7986b-rfb.dts             | 4 ++--
- arch/arm/dts/mt7986b-sd-rfb.dts          | 4 ++--
- 11 files changed, 22 insertions(+), 22 deletions(-)
-
---- a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
-@@ -224,12 +224,12 @@
- &eth {
- 	status = "okay";
- 	mediatek,gmac-id = <0>;
--	phy-mode = "sgmii";
-+	phy-mode = "2500base-x";
- 	mediatek,switch = "mt7531";
- 	reset-gpios = <&gpio 54 GPIO_ACTIVE_HIGH>;
- 
- 	fixed-link {
--		speed = <1000>;
-+		speed = <2500>;
- 		full-duplex;
- 	};
- };
---- a/arch/arm/dts/mt7622-rfb.dts
-+++ b/arch/arm/dts/mt7622-rfb.dts
-@@ -240,12 +240,12 @@
- &eth {
- 	status = "okay";
- 	mediatek,gmac-id = <0>;
--	phy-mode = "sgmii";
-+	phy-mode = "2500base-x";
- 	mediatek,switch = "mt7531";
- 	reset-gpios = <&gpio 54 GPIO_ACTIVE_HIGH>;
- 
- 	fixed-link {
--		speed = <1000>;
-+		speed = <2500>;
- 		full-duplex;
- 	};
- };
---- a/arch/arm/dts/mt7629-rfb.dts
-+++ b/arch/arm/dts/mt7629-rfb.dts
-@@ -25,12 +25,12 @@
- &eth {
- 	status = "okay";
- 	mediatek,gmac-id = <0>;
--	phy-mode = "sgmii";
-+	phy-mode = "2500base-x";
- 	mediatek,switch = "mt7531";
- 	reset-gpios = <&gpio 28 GPIO_ACTIVE_HIGH>;
- 
- 	fixed-link {
--		speed = <1000>;
-+		speed = <2500>;
- 		full-duplex;
- 	};
- };
---- a/arch/arm/dts/mt7981-emmc-rfb.dts
-+++ b/arch/arm/dts/mt7981-emmc-rfb.dts
-@@ -46,12 +46,12 @@
- &eth {
- 	status = "okay";
- 	mediatek,gmac-id = <0>;
--	phy-mode = "sgmii";
-+	phy-mode = "2500base-x";
- 	mediatek,switch = "mt7531";
- 	reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
- 
- 	fixed-link {
--		speed = <1000>;
-+		speed = <2500>;
- 		full-duplex;
- 	};
- };
---- a/arch/arm/dts/mt7981-rfb.dts
-+++ b/arch/arm/dts/mt7981-rfb.dts
-@@ -37,12 +37,12 @@
- &eth {
- 	status = "okay";
- 	mediatek,gmac-id = <0>;
--	phy-mode = "sgmii";
-+	phy-mode = "2500base-x";
- 	mediatek,switch = "mt7531";
- 	reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
- 
- 	fixed-link {
--		speed = <1000>;
-+		speed = <2500>;
- 		full-duplex;
- 	};
- };
---- a/arch/arm/dts/mt7981-sd-rfb.dts
-+++ b/arch/arm/dts/mt7981-sd-rfb.dts
-@@ -46,12 +46,12 @@
- &eth {
- 	status = "okay";
- 	mediatek,gmac-id = <0>;
--	phy-mode = "sgmii";
-+	phy-mode = "2500base-x";
- 	mediatek,switch = "mt7531";
- 	reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
- 
- 	fixed-link {
--		speed = <1000>;
-+		speed = <2500>;
- 		full-duplex;
- 	};
- };
---- a/arch/arm/dts/mt7986a-bpi-r3-sd.dts
-+++ b/arch/arm/dts/mt7986a-bpi-r3-sd.dts
-@@ -76,12 +76,12 @@
- &eth {
- 	status = "okay";
- 	mediatek,gmac-id = <0>;
--	phy-mode = "sgmii";
-+	phy-mode = "2500base-x";
- 	mediatek,switch = "mt7531";
- 	reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
- 
- 	fixed-link {
--		speed = <1000>;
-+		speed = <2500>;
- 		full-duplex;
- 	};
- };
---- a/arch/arm/dts/mt7986a-rfb.dts
-+++ b/arch/arm/dts/mt7986a-rfb.dts
-@@ -55,12 +55,12 @@
- &eth {
- 	status = "okay";
- 	mediatek,gmac-id = <0>;
--	phy-mode = "sgmii";
-+	phy-mode = "2500base-x";
- 	mediatek,switch = "mt7531";
- 	reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
- 
- 	fixed-link {
--		speed = <1000>;
-+		speed = <2500>;
- 		full-duplex;
- 	};
- };
---- a/arch/arm/dts/mt7986a-sd-rfb.dts
-+++ b/arch/arm/dts/mt7986a-sd-rfb.dts
-@@ -47,12 +47,12 @@
- &eth {
- 	status = "okay";
- 	mediatek,gmac-id = <0>;
--	phy-mode = "sgmii";
-+	phy-mode = "2500base-x";
- 	mediatek,switch = "mt7531";
- 	reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
- 
- 	fixed-link {
--		speed = <1000>;
-+		speed = <2500>;
- 		full-duplex;
- 	};
- };
---- a/arch/arm/dts/mt7986b-rfb.dts
-+++ b/arch/arm/dts/mt7986b-rfb.dts
-@@ -46,12 +46,12 @@
- &eth {
- 	status = "okay";
- 	mediatek,gmac-id = <0>;
--	phy-mode = "sgmii";
-+	phy-mode = "2500base-x";
- 	mediatek,switch = "mt7531";
- 	reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
- 
- 	fixed-link {
--		speed = <1000>;
-+		speed = <2500>;
- 		full-duplex;
- 	};
- };
---- a/arch/arm/dts/mt7986b-sd-rfb.dts
-+++ b/arch/arm/dts/mt7986b-sd-rfb.dts
-@@ -47,12 +47,12 @@
- &eth {
- 	status = "okay";
- 	mediatek,gmac-id = <0>;
--	phy-mode = "sgmii";
-+	phy-mode = "2500base-x";
- 	mediatek,switch = "mt7531";
- 	reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
- 
- 	fixed-link {
--		speed = <1000>;
-+		speed = <2500>;
- 		full-duplex;
- 	};
- };

package/boot/uboot-mediatek/patches/101-22-net-mediatek-add-support-for-GMAC-USB3-PHY-mux-mode-.patch

@@ -1,138 +0,0 @@
-From 542d455466bdf32e1bb70230ebcdefd8ed09643b Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:22 +0800
-Subject: [PATCH 22/29] net: mediatek: add support for GMAC/USB3 PHY mux mode
- for MT7981
-
-MT7981 has its GMAC2 PHY shared with USB3. To enable GMAC2, mux
-register must be set to connect the SGMII phy to GMAC2.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/net/mtk_eth.c | 33 ++++++++++++++++++++++++++++++++-
- drivers/net/mtk_eth.h | 16 ++++++++++++++++
- 2 files changed, 48 insertions(+), 1 deletion(-)
-
---- a/drivers/net/mtk_eth.c
-+++ b/drivers/net/mtk_eth.c
-@@ -103,6 +103,8 @@ struct mtk_eth_priv {
- 
- 	struct regmap *ethsys_regmap;
- 
-+	struct regmap *infra_regmap;
-+
- 	struct mii_dev *mdio_bus;
- 	int (*mii_read)(struct mtk_eth_priv *priv, u8 phy, u8 reg);
- 	int (*mii_write)(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 val);
-@@ -186,6 +188,17 @@ static void mtk_ethsys_rmw(struct mtk_et
- 	regmap_write(priv->ethsys_regmap, reg, val);
- }
- 
-+static void mtk_infra_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
-+			  u32 set)
-+{
-+	uint val;
-+
-+	regmap_read(priv->infra_regmap, reg, &val);
-+	val &= ~clr;
-+	val |= set;
-+	regmap_write(priv->infra_regmap, reg, val);
-+}
-+
- /* Direct MDIO clause 22/45 access via SoC */
- static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data,
- 		      u32 cmd, u32 st)
-@@ -1139,6 +1152,11 @@ static void mtk_mac_init(struct mtk_eth_
- 		break;
- 	case PHY_INTERFACE_MODE_SGMII:
- 	case PHY_INTERFACE_MODE_2500BASEX:
-+		if (MTK_HAS_CAPS(priv->soc->caps, MTK_GMAC2_U3_QPHY)) {
-+			mtk_infra_rmw(priv, USB_PHY_SWITCH_REG, QPHY_SEL_MASK,
-+				      SGMII_QPHY_SEL);
-+		}
-+
- 		ge_mode = GE_MODE_RGMII;
- 		mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, SYSCFG0_SGMII_SEL_M,
- 			       SYSCFG0_SGMII_SEL(priv->gmac_id));
-@@ -1497,6 +1515,19 @@ static int mtk_eth_of_to_plat(struct ude
- 	if (IS_ERR(priv->ethsys_regmap))
- 		return PTR_ERR(priv->ethsys_regmap);
- 
-+	if (MTK_HAS_CAPS(priv->soc->caps, MTK_INFRA)) {
-+		/* get corresponding infracfg phandle */
-+		ret = dev_read_phandle_with_args(dev, "mediatek,infracfg",
-+						 NULL, 0, 0, &args);
-+
-+		if (ret)
-+			return ret;
-+
-+		priv->infra_regmap = syscon_node_to_regmap(args.node);
-+		if (IS_ERR(priv->infra_regmap))
-+			return PTR_ERR(priv->infra_regmap);
-+	}
-+
- 	/* Reset controllers */
- 	ret = reset_get_by_name(dev, "fe", &priv->rst_fe);
- 	if (ret) {
-@@ -1614,7 +1645,7 @@ static const struct mtk_soc_data mt7986_
- };
- 
- static const struct mtk_soc_data mt7981_data = {
--	.caps = MT7986_CAPS,
-+	.caps = MT7981_CAPS,
- 	.ana_rgc3 = 0x128,
- 	.pdma_base = PDMA_V2_BASE,
- 	.txd_size = sizeof(struct mtk_tx_dma_v2),
---- a/drivers/net/mtk_eth.h
-+++ b/drivers/net/mtk_eth.h
-@@ -15,27 +15,38 @@
- enum mkt_eth_capabilities {
- 	MTK_TRGMII_BIT,
- 	MTK_TRGMII_MT7621_CLK_BIT,
-+	MTK_U3_COPHY_V2_BIT,
-+	MTK_INFRA_BIT,
- 	MTK_NETSYS_V2_BIT,
- 
- 	/* PATH BITS */
- 	MTK_ETH_PATH_GMAC1_TRGMII_BIT,
-+	MTK_ETH_PATH_GMAC2_SGMII_BIT,
- };
- 
- #define MTK_TRGMII			BIT(MTK_TRGMII_BIT)
- #define MTK_TRGMII_MT7621_CLK		BIT(MTK_TRGMII_MT7621_CLK_BIT)
-+#define MTK_U3_COPHY_V2			BIT(MTK_U3_COPHY_V2_BIT)
-+#define MTK_INFRA			BIT(MTK_INFRA_BIT)
- #define MTK_NETSYS_V2			BIT(MTK_NETSYS_V2_BIT)
- 
- /* Supported path present on SoCs */
- #define MTK_ETH_PATH_GMAC1_TRGMII	BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
- 
-+#define MTK_ETH_PATH_GMAC2_SGMII	BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT)
-+
- #define MTK_GMAC1_TRGMII	(MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
- 
-+#define MTK_GMAC2_U3_QPHY	(MTK_ETH_PATH_GMAC2_SGMII | MTK_U3_COPHY_V2 | MTK_INFRA)
-+
- #define MTK_HAS_CAPS(caps, _x)		(((caps) & (_x)) == (_x))
- 
- #define MT7621_CAPS  (MTK_GMAC1_TRGMII | MTK_TRGMII_MT7621_CLK)
- 
- #define MT7623_CAPS  (MTK_GMAC1_TRGMII)
- 
-+#define MT7981_CAPS  (MTK_GMAC2_U3_QPHY | MTK_NETSYS_V2)
-+
- #define MT7986_CAPS  (MTK_NETSYS_V2)
- 
- /* Frame Engine Register Bases */
-@@ -56,6 +67,11 @@ enum mkt_eth_capabilities {
- #define ETHSYS_CLKCFG0_REG		0x2c
- #define ETHSYS_TRGMII_CLK_SEL362_5	BIT(11)
- 
-+/* Top misc registers */
-+#define USB_PHY_SWITCH_REG		0x218
-+#define QPHY_SEL_MASK			0x3
-+#define SGMII_QPHY_SEL			0x2
-+
- /* SYSCFG0_GE_MODE: GE Modes */
- #define GE_MODE_RGMII			0
- #define GE_MODE_MII			1

package/boot/uboot-mediatek/patches/101-23-arm-dts-mediatek-add-infracfg-registers-to-support-G.patch

@@ -1,36 +0,0 @@
-From 64dab5fc8405005a78bdf1e0035d8b754cdf0c7e Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:27 +0800
-Subject: [PATCH 23/29] arm: dts: mediatek: add infracfg registers to support
- GMAC/USB3 Co-PHY
-
-This patch adds infracfg to eth node to support enabling GMAC2.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- arch/arm/dts/mt7981.dtsi | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/arch/arm/dts/mt7981.dtsi
-+++ b/arch/arm/dts/mt7981.dtsi
-@@ -266,6 +266,7 @@
- 		reset-names = "fe";
- 		mediatek,ethsys = <&ethsys>;
- 		mediatek,sgmiisys = <&sgmiisys0>;
-+		mediatek,infracfg = <&topmisc>;
- 		#address-cells = <1>;
- 		#size-cells = <0>;
- 		status = "disabled";
-@@ -284,6 +285,12 @@
- 		#clock-cells = <1>;
- 	};
- 
-+	topmisc: topmisc@11d10000 {
-+		compatible = "mediatek,mt7981-topmisc", "syscon";
-+		reg = <0x11d10000 0x10000>;
-+		#clock-cells = <1>;
-+	};
-+
- 	spi0: spi@1100a000 {
- 		compatible = "mediatek,ipm-spi";
- 		reg = <0x1100a000 0x100>;

package/boot/uboot-mediatek/patches/101-24-net-mediatek-add-USXGMII-support.patch

@@ -1,341 +0,0 @@
-From d62b483092035bc86d1db83ea4ac29bfa7bba77d Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:31 +0800
-Subject: [PATCH 24/29] net: mediatek: add USXGMII support
-
-This patch adds support for USXGMII of SoC.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/net/mtk_eth.c | 230 +++++++++++++++++++++++++++++++++++++++++-
- drivers/net/mtk_eth.h |  24 +++++
- 2 files changed, 251 insertions(+), 3 deletions(-)
-
---- a/drivers/net/mtk_eth.c
-+++ b/drivers/net/mtk_eth.c
-@@ -105,6 +105,11 @@ struct mtk_eth_priv {
- 
- 	struct regmap *infra_regmap;
- 
-+	struct regmap *usxgmii_regmap;
-+	struct regmap *xfi_pextp_regmap;
-+	struct regmap *xfi_pll_regmap;
-+	struct regmap *toprgu_regmap;
-+
- 	struct mii_dev *mdio_bus;
- 	int (*mii_read)(struct mtk_eth_priv *priv, u8 phy, u8 reg);
- 	int (*mii_write)(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 val);
-@@ -989,6 +994,42 @@ static int mt753x_switch_init(struct mtk
- 	return 0;
- }
- 
-+static void mtk_xphy_link_adjust(struct mtk_eth_priv *priv)
-+{
-+	u16 lcl_adv = 0, rmt_adv = 0;
-+	u8 flowctrl;
-+	u32 mcr;
-+
-+	mcr = mtk_gmac_read(priv, XGMAC_PORT_MCR(priv->gmac_id));
-+	mcr &= ~(XGMAC_FORCE_TX_FC | XGMAC_FORCE_RX_FC);
-+
-+	if (priv->phydev->duplex) {
-+		if (priv->phydev->pause)
-+			rmt_adv = LPA_PAUSE_CAP;
-+		if (priv->phydev->asym_pause)
-+			rmt_adv |= LPA_PAUSE_ASYM;
-+
-+		if (priv->phydev->advertising & ADVERTISED_Pause)
-+			lcl_adv |= ADVERTISE_PAUSE_CAP;
-+		if (priv->phydev->advertising & ADVERTISED_Asym_Pause)
-+			lcl_adv |= ADVERTISE_PAUSE_ASYM;
-+
-+		flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
-+
-+		if (flowctrl & FLOW_CTRL_TX)
-+			mcr |= XGMAC_FORCE_TX_FC;
-+		if (flowctrl & FLOW_CTRL_RX)
-+			mcr |= XGMAC_FORCE_RX_FC;
-+
-+		debug("rx pause %s, tx pause %s\n",
-+		      flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
-+		      flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
-+	}
-+
-+	mcr &= ~(XGMAC_TRX_DISABLE);
-+	mtk_gmac_write(priv, XGMAC_PORT_MCR(priv->gmac_id), mcr);
-+}
-+
- static void mtk_phy_link_adjust(struct mtk_eth_priv *priv)
- {
- 	u16 lcl_adv = 0, rmt_adv = 0;
-@@ -1063,8 +1104,12 @@ static int mtk_phy_start(struct mtk_eth_
- 		return 0;
- 	}
- 
--	if (!priv->force_mode)
--		mtk_phy_link_adjust(priv);
-+	if (!priv->force_mode) {
-+		if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII)
-+			mtk_xphy_link_adjust(priv);
-+		else
-+			mtk_phy_link_adjust(priv);
-+	}
- 
- 	debug("Speed: %d, %s duplex%s\n", phydev->speed,
- 	      (phydev->duplex) ? "full" : "half",
-@@ -1140,6 +1185,112 @@ static void mtk_sgmii_force_init(struct
- 			SGMII_PHYA_PWD, 0);
- }
- 
-+static void mtk_xfi_pll_enable(struct mtk_eth_priv *priv)
-+{
-+	u32 val = 0;
-+
-+	/* Add software workaround for USXGMII PLL TCL issue */
-+	regmap_write(priv->xfi_pll_regmap, XFI_PLL_ANA_GLB8,
-+		     RG_XFI_PLL_ANA_SWWA);
-+
-+	regmap_read(priv->xfi_pll_regmap, XFI_PLL_DIG_GLB8, &val);
-+	val |= RG_XFI_PLL_EN;
-+	regmap_write(priv->xfi_pll_regmap, XFI_PLL_DIG_GLB8, val);
-+}
-+
-+static void mtk_usxgmii_reset(struct mtk_eth_priv *priv)
-+{
-+	switch (priv->gmac_id) {
-+	case 1:
-+		regmap_write(priv->toprgu_regmap, 0xFC, 0x0000A004);
-+		regmap_write(priv->toprgu_regmap, 0x18, 0x88F0A004);
-+		regmap_write(priv->toprgu_regmap, 0xFC, 0x00000000);
-+		regmap_write(priv->toprgu_regmap, 0x18, 0x88F00000);
-+		regmap_write(priv->toprgu_regmap, 0x18, 0x00F00000);
-+		break;
-+	case 2:
-+		regmap_write(priv->toprgu_regmap, 0xFC, 0x00005002);
-+		regmap_write(priv->toprgu_regmap, 0x18, 0x88F05002);
-+		regmap_write(priv->toprgu_regmap, 0xFC, 0x00000000);
-+		regmap_write(priv->toprgu_regmap, 0x18, 0x88F00000);
-+		regmap_write(priv->toprgu_regmap, 0x18, 0x00F00000);
-+		break;
-+	}
-+
-+	mdelay(10);
-+}
-+
-+static void mtk_usxgmii_setup_phya_an_10000(struct mtk_eth_priv *priv)
-+{
-+	regmap_write(priv->usxgmii_regmap, 0x810, 0x000FFE6D);
-+	regmap_write(priv->usxgmii_regmap, 0x818, 0x07B1EC7B);
-+	regmap_write(priv->usxgmii_regmap, 0x80C, 0x30000000);
-+	ndelay(1020);
-+	regmap_write(priv->usxgmii_regmap, 0x80C, 0x10000000);
-+	ndelay(1020);
-+	regmap_write(priv->usxgmii_regmap, 0x80C, 0x00000000);
-+
-+	regmap_write(priv->xfi_pextp_regmap, 0x9024, 0x00C9071C);
-+	regmap_write(priv->xfi_pextp_regmap, 0x2020, 0xAA8585AA);
-+	regmap_write(priv->xfi_pextp_regmap, 0x2030, 0x0C020707);
-+	regmap_write(priv->xfi_pextp_regmap, 0x2034, 0x0E050F0F);
-+	regmap_write(priv->xfi_pextp_regmap, 0x2040, 0x00140032);
-+	regmap_write(priv->xfi_pextp_regmap, 0x50F0, 0x00C014AA);
-+	regmap_write(priv->xfi_pextp_regmap, 0x50E0, 0x3777C12B);
-+	regmap_write(priv->xfi_pextp_regmap, 0x506C, 0x005F9CFF);
-+	regmap_write(priv->xfi_pextp_regmap, 0x5070, 0x9D9DFAFA);
-+	regmap_write(priv->xfi_pextp_regmap, 0x5074, 0x27273F3F);
-+	regmap_write(priv->xfi_pextp_regmap, 0x5078, 0xA7883C68);
-+	regmap_write(priv->xfi_pextp_regmap, 0x507C, 0x11661166);
-+	regmap_write(priv->xfi_pextp_regmap, 0x5080, 0x0E000AAF);
-+	regmap_write(priv->xfi_pextp_regmap, 0x5084, 0x08080D0D);
-+	regmap_write(priv->xfi_pextp_regmap, 0x5088, 0x02030909);
-+	regmap_write(priv->xfi_pextp_regmap, 0x50E4, 0x0C0C0000);
-+	regmap_write(priv->xfi_pextp_regmap, 0x50E8, 0x04040000);
-+	regmap_write(priv->xfi_pextp_regmap, 0x50EC, 0x0F0F0C06);
-+	regmap_write(priv->xfi_pextp_regmap, 0x50A8, 0x506E8C8C);
-+	regmap_write(priv->xfi_pextp_regmap, 0x6004, 0x18190000);
-+	regmap_write(priv->xfi_pextp_regmap, 0x00F8, 0x01423342);
-+	regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F20);
-+	regmap_write(priv->xfi_pextp_regmap, 0x0030, 0x00050C00);
-+	regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x02002800);
-+	ndelay(1020);
-+	regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000020);
-+	regmap_write(priv->xfi_pextp_regmap, 0x3028, 0x00008A01);
-+	regmap_write(priv->xfi_pextp_regmap, 0x302C, 0x0000A884);
-+	regmap_write(priv->xfi_pextp_regmap, 0x3024, 0x00083002);
-+	regmap_write(priv->xfi_pextp_regmap, 0x3010, 0x00022220);
-+	regmap_write(priv->xfi_pextp_regmap, 0x5064, 0x0F020A01);
-+	regmap_write(priv->xfi_pextp_regmap, 0x50B4, 0x06100600);
-+	regmap_write(priv->xfi_pextp_regmap, 0x3048, 0x40704000);
-+	regmap_write(priv->xfi_pextp_regmap, 0x3050, 0xA8000000);
-+	regmap_write(priv->xfi_pextp_regmap, 0x3054, 0x000000AA);
-+	regmap_write(priv->xfi_pextp_regmap, 0x306C, 0x00000F00);
-+	regmap_write(priv->xfi_pextp_regmap, 0xA060, 0x00040000);
-+	regmap_write(priv->xfi_pextp_regmap, 0x90D0, 0x00000001);
-+	regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200E800);
-+	udelay(150);
-+	regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C111);
-+	ndelay(1020);
-+	regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C101);
-+	udelay(15);
-+	regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C111);
-+	ndelay(1020);
-+	regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C101);
-+	udelay(100);
-+	regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000030);
-+	regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F00);
-+	regmap_write(priv->xfi_pextp_regmap, 0x3040, 0x30000000);
-+	udelay(400);
-+}
-+
-+static void mtk_usxgmii_an_init(struct mtk_eth_priv *priv)
-+{
-+	mtk_xfi_pll_enable(priv);
-+	mtk_usxgmii_reset(priv);
-+	mtk_usxgmii_setup_phya_an_10000(priv);
-+}
-+
- static void mtk_mac_init(struct mtk_eth_priv *priv)
- {
- 	int i, ge_mode = 0;
-@@ -1222,6 +1373,36 @@ static void mtk_mac_init(struct mtk_eth_
- 	}
- }
- 
-+static void mtk_xmac_init(struct mtk_eth_priv *priv)
-+{
-+	u32 sts;
-+
-+	switch (priv->phy_interface) {
-+	case PHY_INTERFACE_MODE_USXGMII:
-+		mtk_usxgmii_an_init(priv);
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	/* Set GMAC to the correct mode */
-+	mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG,
-+		       SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id),
-+		       0);
-+
-+	if (priv->gmac_id == 1) {
-+		mtk_infra_rmw(priv, TOPMISC_NETSYS_PCS_MUX,
-+			      NETSYS_PCS_MUX_MASK, MUX_G2_USXGMII_SEL);
-+	} else if (priv->gmac_id == 2) {
-+		sts = mtk_gmac_read(priv, XGMAC_STS(priv->gmac_id));
-+		sts |= XGMAC_FORCE_LINK;
-+		mtk_gmac_write(priv, XGMAC_STS(priv->gmac_id), sts);
-+	}
-+
-+	/* Force GMAC link down */
-+	mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), FORCE_MODE);
-+}
-+
- static void mtk_eth_fifo_init(struct mtk_eth_priv *priv)
- {
- 	char *pkt_base = priv->pkt_pool;
-@@ -1463,7 +1644,10 @@ static int mtk_eth_probe(struct udevice
- 				ARCH_DMA_MINALIGN);
- 
- 	/* Set MAC mode */
--	mtk_mac_init(priv);
-+	if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII)
-+		mtk_xmac_init(priv);
-+	else
-+		mtk_mac_init(priv);
- 
- 	/* Probe phy if switch is not specified */
- 	if (priv->sw == SW_NONE)
-@@ -1581,6 +1765,46 @@ static int mtk_eth_of_to_plat(struct ude
- 		}
- 
- 		priv->pn_swap = ofnode_read_bool(args.node, "pn_swap");
-+	} else if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII) {
-+		/* get corresponding usxgmii phandle */
-+		ret = dev_read_phandle_with_args(dev, "mediatek,usxgmiisys",
-+						 NULL, 0, 0, &args);
-+		if (ret)
-+			return ret;
-+
-+		priv->usxgmii_regmap = syscon_node_to_regmap(args.node);
-+		if (IS_ERR(priv->usxgmii_regmap))
-+			return PTR_ERR(priv->usxgmii_regmap);
-+
-+		/* get corresponding xfi_pextp phandle */
-+		ret = dev_read_phandle_with_args(dev, "mediatek,xfi_pextp",
-+						 NULL, 0, 0, &args);
-+		if (ret)
-+			return ret;
-+
-+		priv->xfi_pextp_regmap = syscon_node_to_regmap(args.node);
-+		if (IS_ERR(priv->xfi_pextp_regmap))
-+			return PTR_ERR(priv->xfi_pextp_regmap);
-+
-+		/* get corresponding xfi_pll phandle */
-+		ret = dev_read_phandle_with_args(dev, "mediatek,xfi_pll",
-+						 NULL, 0, 0, &args);
-+		if (ret)
-+			return ret;
-+
-+		priv->xfi_pll_regmap = syscon_node_to_regmap(args.node);
-+		if (IS_ERR(priv->xfi_pll_regmap))
-+			return PTR_ERR(priv->xfi_pll_regmap);
-+
-+		/* get corresponding toprgu phandle */
-+		ret = dev_read_phandle_with_args(dev, "mediatek,toprgu",
-+						 NULL, 0, 0, &args);
-+		if (ret)
-+			return ret;
-+
-+		priv->toprgu_regmap = syscon_node_to_regmap(args.node);
-+		if (IS_ERR(priv->toprgu_regmap))
-+			return PTR_ERR(priv->toprgu_regmap);
- 	}
- 
- 	/* check for switch first, otherwise phy will be used */
---- a/drivers/net/mtk_eth.h
-+++ b/drivers/net/mtk_eth.h
-@@ -68,6 +68,11 @@ enum mkt_eth_capabilities {
- #define ETHSYS_TRGMII_CLK_SEL362_5	BIT(11)
- 
- /* Top misc registers */
-+#define TOPMISC_NETSYS_PCS_MUX		0x84
-+#define NETSYS_PCS_MUX_MASK		GENMASK(1, 0)
-+#define MUX_G2_USXGMII_SEL		BIT(1)
-+#define MUX_HSGMII1_G1_SEL		BIT(0)
-+
- #define USB_PHY_SWITCH_REG		0x218
- #define QPHY_SEL_MASK			0x3
- #define SGMII_QPHY_SEL			0x2
-@@ -98,6 +103,15 @@ enum mkt_eth_capabilities {
- #define SGMSYS_GEN2_SPEED_V2		0x128
- #define SGMSYS_SPEED_2500		BIT(2)
- 
-+/* USXGMII subsystem config registers */
-+/* Register to control USXGMII XFI PLL digital */
-+#define XFI_PLL_DIG_GLB8		0x08
-+#define RG_XFI_PLL_EN			BIT(31)
-+
-+/* Register to control USXGMII XFI PLL analog */
-+#define XFI_PLL_ANA_GLB8		0x108
-+#define RG_XFI_PLL_ANA_SWWA		0x02283248
-+
- /* Frame Engine Registers */
- #define FE_GLO_MISC_REG			0x124
- #define PDMA_VER_V2			BIT(4)
-@@ -221,6 +235,16 @@ enum mkt_eth_capabilities {
- #define TD_DM_DRVP_S			0
- #define TD_DM_DRVP_M			0x0f
- 
-+/* XGMAC Status Registers */
-+#define XGMAC_STS(x)			(((x) == 2) ? 0x001C : 0x000C)
-+#define XGMAC_FORCE_LINK		BIT(15)
-+
-+/* XGMAC Registers */
-+#define XGMAC_PORT_MCR(x)		(0x2000 + (((x) - 1) * 0x1000))
-+#define XGMAC_TRX_DISABLE		0xf
-+#define XGMAC_FORCE_TX_FC		BIT(5)
-+#define XGMAC_FORCE_RX_FC		BIT(4)
-+
- /* MT7530 Registers */
- 
- #define PCR_REG(p)			(0x2004 + (p) * 0x100)

package/boot/uboot-mediatek/patches/101-25-net-mediatek-add-support-for-NETSYS-v3.patch

@@ -1,221 +0,0 @@
-From 7d201749cc49a58fb5e791d1e099ec3e3489e16d Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:37 +0800
-Subject: [PATCH 25/29] net: mediatek: add support for NETSYS v3
-
-This patch adds support for NETSYS v3 hardware.
-Comparing to NETSYS v2, NETSYS v3 has three GMACs.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/net/mtk_eth.c | 49 ++++++++++++++++++++++++++++++++-----------
- drivers/net/mtk_eth.h |  7 +++++++
- 2 files changed, 44 insertions(+), 12 deletions(-)
-
---- a/drivers/net/mtk_eth.c
-+++ b/drivers/net/mtk_eth.c
-@@ -76,6 +76,7 @@ enum mtk_switch {
-  * @caps			Flags shown the extra capability for the SoC
-  * @ana_rgc3:			The offset for register ANA_RGC3 related to
-  *				sgmiisys syscon
-+ * @gdma_count:			Number of GDMAs
-  * @pdma_base:			Register base of PDMA block
-  * @txd_size:			Tx DMA descriptor size.
-  * @rxd_size:			Rx DMA descriptor size.
-@@ -83,6 +84,7 @@ enum mtk_switch {
- struct mtk_soc_data {
- 	u32 caps;
- 	u32 ana_rgc3;
-+	u32 gdma_count;
- 	u32 pdma_base;
- 	u32 txd_size;
- 	u32 rxd_size;
-@@ -159,7 +161,9 @@ static void mtk_gdma_write(struct mtk_et
- {
- 	u32 gdma_base;
- 
--	if (no == 1)
-+	if (no == 2)
-+		gdma_base = GDMA3_BASE;
-+	else if (no == 1)
- 		gdma_base = GDMA2_BASE;
- 	else
- 		gdma_base = GDMA1_BASE;
-@@ -1429,7 +1433,10 @@ static void mtk_eth_fifo_init(struct mtk
- 		txd->txd1 = virt_to_phys(pkt_base);
- 		txd->txd2 = PDMA_TXD2_DDONE | PDMA_TXD2_LS0;
- 
--		if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
-+		if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
-+			txd->txd5 = PDMA_V2_TXD5_FPORT_SET(priv->gmac_id == 2 ?
-+							   15 : priv->gmac_id + 1);
-+		else if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
- 			txd->txd5 = PDMA_V2_TXD5_FPORT_SET(priv->gmac_id + 1);
- 		else
- 			txd->txd4 = PDMA_V1_TXD4_FPORT_SET(priv->gmac_id + 1);
-@@ -1442,7 +1449,8 @@ static void mtk_eth_fifo_init(struct mtk
- 
- 		rxd->rxd1 = virt_to_phys(pkt_base);
- 
--		if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
-+		if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
-+		    MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
- 			rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
- 		else
- 			rxd->rxd2 = PDMA_V1_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
-@@ -1466,7 +1474,7 @@ static void mtk_eth_fifo_init(struct mtk
- static int mtk_eth_start(struct udevice *dev)
- {
- 	struct mtk_eth_priv *priv = dev_get_priv(dev);
--	int ret;
-+	int i, ret;
- 
- 	/* Reset FE */
- 	reset_assert(&priv->rst_fe);
-@@ -1474,16 +1482,24 @@ static int mtk_eth_start(struct udevice
- 	reset_deassert(&priv->rst_fe);
- 	mdelay(10);
- 
--	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
-+	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
-+	    MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
- 		setbits_le32(priv->fe_base + FE_GLO_MISC_REG, PDMA_VER_V2);
- 
- 	/* Packets forward to PDMA */
- 	mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, GDMA_FWD_TO_CPU);
- 
--	if (priv->gmac_id == 0)
--		mtk_gdma_write(priv, 1, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
--	else
--		mtk_gdma_write(priv, 0, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
-+	for (i = 0; i < priv->soc->gdma_count; i++) {
-+		if (i == priv->gmac_id)
-+			continue;
-+
-+		mtk_gdma_write(priv, i, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
-+	}
-+
-+	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) {
-+		mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG,
-+			       GDMA_CPU_BRIDGE_EN);
-+	}
- 
- 	udelay(500);
- 
-@@ -1557,7 +1573,8 @@ static int mtk_eth_send(struct udevice *
- 	flush_dcache_range((ulong)pkt_base, (ulong)pkt_base +
- 			   roundup(length, ARCH_DMA_MINALIGN));
- 
--	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
-+	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
-+	    MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
- 		txd->txd2 = PDMA_TXD2_LS0 | PDMA_V2_TXD2_SDL0_SET(length);
- 	else
- 		txd->txd2 = PDMA_TXD2_LS0 | PDMA_V1_TXD2_SDL0_SET(length);
-@@ -1583,7 +1600,8 @@ static int mtk_eth_recv(struct udevice *
- 		return -EAGAIN;
- 	}
- 
--	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
-+	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
-+	    MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
- 		length = PDMA_V2_RXD2_PLEN0_GET(rxd->rxd2);
- 	else
- 		length = PDMA_V1_RXD2_PLEN0_GET(rxd->rxd2);
-@@ -1606,7 +1624,8 @@ static int mtk_eth_free_pkt(struct udevi
- 
- 	rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size;
- 
--	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
-+	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
-+	    MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
- 		rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
- 	else
- 		rxd->rxd2 = PDMA_V1_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
-@@ -1863,6 +1882,7 @@ static int mtk_eth_of_to_plat(struct ude
- static const struct mtk_soc_data mt7986_data = {
- 	.caps = MT7986_CAPS,
- 	.ana_rgc3 = 0x128,
-+	.gdma_count = 2,
- 	.pdma_base = PDMA_V2_BASE,
- 	.txd_size = sizeof(struct mtk_tx_dma_v2),
- 	.rxd_size = sizeof(struct mtk_rx_dma_v2),
-@@ -1871,6 +1891,7 @@ static const struct mtk_soc_data mt7986_
- static const struct mtk_soc_data mt7981_data = {
- 	.caps = MT7981_CAPS,
- 	.ana_rgc3 = 0x128,
-+	.gdma_count = 2,
- 	.pdma_base = PDMA_V2_BASE,
- 	.txd_size = sizeof(struct mtk_tx_dma_v2),
- 	.rxd_size = sizeof(struct mtk_rx_dma_v2),
-@@ -1878,6 +1899,7 @@ static const struct mtk_soc_data mt7981_
- 
- static const struct mtk_soc_data mt7629_data = {
- 	.ana_rgc3 = 0x128,
-+	.gdma_count = 2,
- 	.pdma_base = PDMA_V1_BASE,
- 	.txd_size = sizeof(struct mtk_tx_dma),
- 	.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -1885,6 +1907,7 @@ static const struct mtk_soc_data mt7629_
- 
- static const struct mtk_soc_data mt7623_data = {
- 	.caps = MT7623_CAPS,
-+	.gdma_count = 2,
- 	.pdma_base = PDMA_V1_BASE,
- 	.txd_size = sizeof(struct mtk_tx_dma),
- 	.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -1892,6 +1915,7 @@ static const struct mtk_soc_data mt7623_
- 
- static const struct mtk_soc_data mt7622_data = {
- 	.ana_rgc3 = 0x2028,
-+	.gdma_count = 2,
- 	.pdma_base = PDMA_V1_BASE,
- 	.txd_size = sizeof(struct mtk_tx_dma),
- 	.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -1899,6 +1923,7 @@ static const struct mtk_soc_data mt7622_
- 
- static const struct mtk_soc_data mt7621_data = {
- 	.caps = MT7621_CAPS,
-+	.gdma_count = 2,
- 	.pdma_base = PDMA_V1_BASE,
- 	.txd_size = sizeof(struct mtk_tx_dma),
- 	.rxd_size = sizeof(struct mtk_rx_dma),
---- a/drivers/net/mtk_eth.h
-+++ b/drivers/net/mtk_eth.h
-@@ -18,6 +18,7 @@ enum mkt_eth_capabilities {
- 	MTK_U3_COPHY_V2_BIT,
- 	MTK_INFRA_BIT,
- 	MTK_NETSYS_V2_BIT,
-+	MTK_NETSYS_V3_BIT,
- 
- 	/* PATH BITS */
- 	MTK_ETH_PATH_GMAC1_TRGMII_BIT,
-@@ -29,6 +30,7 @@ enum mkt_eth_capabilities {
- #define MTK_U3_COPHY_V2			BIT(MTK_U3_COPHY_V2_BIT)
- #define MTK_INFRA			BIT(MTK_INFRA_BIT)
- #define MTK_NETSYS_V2			BIT(MTK_NETSYS_V2_BIT)
-+#define MTK_NETSYS_V3			BIT(MTK_NETSYS_V3_BIT)
- 
- /* Supported path present on SoCs */
- #define MTK_ETH_PATH_GMAC1_TRGMII	BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
-@@ -52,8 +54,10 @@ enum mkt_eth_capabilities {
- /* Frame Engine Register Bases */
- #define PDMA_V1_BASE			0x0800
- #define PDMA_V2_BASE			0x6000
-+#define PDMA_V3_BASE			0x6800
- #define GDMA1_BASE			0x0500
- #define GDMA2_BASE			0x1500
-+#define GDMA3_BASE			0x0540
- #define GMAC_BASE			0x10000
- 
- /* Ethernet subsystem registers */
-@@ -153,6 +157,9 @@ enum mkt_eth_capabilities {
- #define UN_DP_S				0
- #define UN_DP_M				0x0f
- 
-+#define GDMA_EG_CTRL_REG		0x004
-+#define GDMA_CPU_BRIDGE_EN		BIT(31)
-+
- #define GDMA_MAC_LSB_REG		0x008
- 
- #define GDMA_MAC_MSB_REG		0x00c

package/boot/uboot-mediatek/patches/101-26-net-mediatek-add-support-for-MediaTek-MT7988-SoC.patch

@@ -1,327 +0,0 @@
-From 59dba9d87c9caf04a5d797af46699055a53870f4 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:41 +0800
-Subject: [PATCH 26/29] net: mediatek: add support for MediaTek MT7988 SoC
-
-This patch adds support for MediaTek MT7988.
-
-MT7988 features MediaTek NETSYS v3, including three GMACs, and two
-of them supports 10Gbps USXGMII.
-
-MT7988 embeds a MT7531 switch (not MCM) which supports accessing
-internal registers through MMIO instead of MDIO.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/net/mtk_eth.c | 158 +++++++++++++++++++++++++++++++++++++++++-
- drivers/net/mtk_eth.h |  20 ++++++
- 2 files changed, 177 insertions(+), 1 deletion(-)
-
---- a/drivers/net/mtk_eth.c
-+++ b/drivers/net/mtk_eth.c
-@@ -54,6 +54,16 @@
- 	(DP_PDMA << MC_DP_S) | \
- 	(DP_PDMA << UN_DP_S))
- 
-+#define GDMA_BRIDGE_TO_CPU \
-+	(0xC0000000 | \
-+	GDM_ICS_EN | \
-+	GDM_TCS_EN | \
-+	GDM_UCS_EN | \
-+	(DP_PDMA << MYMAC_DP_S) | \
-+	(DP_PDMA << BC_DP_S) | \
-+	(DP_PDMA << MC_DP_S) | \
-+	(DP_PDMA << UN_DP_S))
-+
- #define GDMA_FWD_DISCARD \
- 	(0x20000000 | \
- 	GDM_ICS_EN | \
-@@ -68,7 +78,8 @@
- enum mtk_switch {
- 	SW_NONE,
- 	SW_MT7530,
--	SW_MT7531
-+	SW_MT7531,
-+	SW_MT7988,
- };
- 
- /* struct mtk_soc_data -	This is the structure holding all differences
-@@ -102,6 +113,7 @@ struct mtk_eth_priv {
- 	void __iomem *fe_base;
- 	void __iomem *gmac_base;
- 	void __iomem *sgmii_base;
-+	void __iomem *gsw_base;
- 
- 	struct regmap *ethsys_regmap;
- 
-@@ -171,6 +183,11 @@ static void mtk_gdma_write(struct mtk_et
- 	writel(val, priv->fe_base + gdma_base + reg);
- }
- 
-+static void mtk_fe_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set)
-+{
-+	clrsetbits_le32(priv->fe_base + reg, clr, set);
-+}
-+
- static u32 mtk_gmac_read(struct mtk_eth_priv *priv, u32 reg)
- {
- 	return readl(priv->gmac_base + reg);
-@@ -208,6 +225,16 @@ static void mtk_infra_rmw(struct mtk_eth
- 	regmap_write(priv->infra_regmap, reg, val);
- }
- 
-+static u32 mtk_gsw_read(struct mtk_eth_priv *priv, u32 reg)
-+{
-+	return readl(priv->gsw_base + reg);
-+}
-+
-+static void mtk_gsw_write(struct mtk_eth_priv *priv, u32 reg, u32 val)
-+{
-+	writel(val, priv->gsw_base + reg);
-+}
-+
- /* Direct MDIO clause 22/45 access via SoC */
- static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data,
- 		      u32 cmd, u32 st)
-@@ -342,6 +369,11 @@ static int mt753x_reg_read(struct mtk_et
- {
- 	int ret, low_word, high_word;
- 
-+	if (priv->sw == SW_MT7988) {
-+		*data = mtk_gsw_read(priv, reg);
-+		return 0;
-+	}
-+
- 	/* Write page address */
- 	ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6);
- 	if (ret)
-@@ -367,6 +399,11 @@ static int mt753x_reg_write(struct mtk_e
- {
- 	int ret;
- 
-+	if (priv->sw == SW_MT7988) {
-+		mtk_gsw_write(priv, reg, data);
-+		return 0;
-+	}
-+
- 	/* Write page address */
- 	ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6);
- 	if (ret)
-@@ -537,6 +574,7 @@ static int mtk_mdio_register(struct udev
- 		priv->mmd_write = mtk_mmd_ind_write;
- 		break;
- 	case SW_MT7531:
-+	case SW_MT7988:
- 		priv->mii_read = mt7531_mii_ind_read;
- 		priv->mii_write = mt7531_mii_ind_write;
- 		priv->mmd_read = mt7531_mmd_ind_read;
-@@ -957,6 +995,103 @@ static int mt7531_setup(struct mtk_eth_p
- 	return 0;
- }
- 
-+static void mt7988_phy_setting(struct mtk_eth_priv *priv)
-+{
-+	u16 val;
-+	u32 i;
-+
-+	for (i = 0; i < MT753X_NUM_PHYS; i++) {
-+		/* Enable HW auto downshift */
-+		priv->mii_write(priv, i, 0x1f, 0x1);
-+		val = priv->mii_read(priv, i, PHY_EXT_REG_14);
-+		val |= PHY_EN_DOWN_SHFIT;
-+		priv->mii_write(priv, i, PHY_EXT_REG_14, val);
-+
-+		/* PHY link down power saving enable */
-+		val = priv->mii_read(priv, i, PHY_EXT_REG_17);
-+		val |= PHY_LINKDOWN_POWER_SAVING_EN;
-+		priv->mii_write(priv, i, PHY_EXT_REG_17, val);
-+	}
-+}
-+
-+static void mt7988_mac_control(struct mtk_eth_priv *priv, bool enable)
-+{
-+	u32 pmcr = FORCE_MODE_LNK;
-+
-+	if (enable)
-+		pmcr = priv->mt753x_pmcr;
-+
-+	mt753x_reg_write(priv, PMCR_REG(6), pmcr);
-+}
-+
-+static int mt7988_setup(struct mtk_eth_priv *priv)
-+{
-+	u16 phy_addr, phy_val;
-+	u32 pmcr;
-+	int i;
-+
-+	priv->gsw_base = regmap_get_range(priv->ethsys_regmap, 0) + GSW_BASE;
-+
-+	priv->mt753x_phy_base = (priv->mt753x_smi_addr + 1) &
-+				MT753X_SMI_ADDR_MASK;
-+
-+	/* Turn off PHYs */
-+	for (i = 0; i < MT753X_NUM_PHYS; i++) {
-+		phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
-+		phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
-+		phy_val |= BMCR_PDOWN;
-+		priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
-+	}
-+
-+	switch (priv->phy_interface) {
-+	case PHY_INTERFACE_MODE_USXGMII:
-+		/* Use CPU bridge instead of actual USXGMII path */
-+
-+		/* Set GDM1 no drop */
-+		mtk_fe_rmw(priv, PSE_NO_DROP_CFG_REG, 0, PSE_NO_DROP_GDM1);
-+
-+		/* Enable GDM1 to GSW CPU bridge */
-+		mtk_gmac_rmw(priv, GMAC_MAC_MISC_REG, 0, BIT(0));
-+
-+		/* XGMAC force link up */
-+		mtk_gmac_rmw(priv, GMAC_XGMAC_STS_REG, 0, P1_XGMAC_FORCE_LINK);
-+
-+		/* Setup GSW CPU bridge IPG */
-+		mtk_gmac_rmw(priv, GMAC_GSW_CFG_REG, GSWTX_IPG_M | GSWRX_IPG_M,
-+			     (0xB << GSWTX_IPG_S) | (0xB << GSWRX_IPG_S));
-+		break;
-+	default:
-+		printf("Error: MT7988 GSW does not support %s interface\n",
-+		       phy_string_for_interface(priv->phy_interface));
-+		break;
-+	}
-+
-+	pmcr = MT7988_FORCE_MODE |
-+	       (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
-+	       MAC_MODE | MAC_TX_EN | MAC_RX_EN |
-+	       BKOFF_EN | BACKPR_EN |
-+	       FORCE_RX_FC | FORCE_TX_FC |
-+	       (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX |
-+	       FORCE_LINK;
-+
-+	priv->mt753x_pmcr = pmcr;
-+
-+	/* Keep MAC link down before starting eth */
-+	mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK);
-+
-+	/* Turn on PHYs */
-+	for (i = 0; i < MT753X_NUM_PHYS; i++) {
-+		phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
-+		phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
-+		phy_val &= ~BMCR_PDOWN;
-+		priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
-+	}
-+
-+	mt7988_phy_setting(priv);
-+
-+	return 0;
-+}
-+
- static int mt753x_switch_init(struct mtk_eth_priv *priv)
- {
- 	int ret;
-@@ -1497,6 +1632,11 @@ static int mtk_eth_start(struct udevice
- 	}
- 
- 	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) {
-+		if (priv->sw == SW_MT7988 && priv->gmac_id == 0) {
-+			mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG,
-+				       GDMA_BRIDGE_TO_CPU);
-+		}
-+
- 		mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG,
- 			       GDMA_CPU_BRIDGE_EN);
- 	}
-@@ -1845,6 +1985,12 @@ static int mtk_eth_of_to_plat(struct ude
- 			priv->switch_mac_control = mt7531_mac_control;
- 			priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
- 			priv->mt753x_reset_wait_time = 200;
-+		} else if (!strcmp(str, "mt7988")) {
-+			priv->sw = SW_MT7988;
-+			priv->switch_init = mt7988_setup;
-+			priv->switch_mac_control = mt7988_mac_control;
-+			priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
-+			priv->mt753x_reset_wait_time = 50;
- 		} else {
- 			printf("error: unsupported switch\n");
- 			return -EINVAL;
-@@ -1879,6 +2025,15 @@ static int mtk_eth_of_to_plat(struct ude
- 	return 0;
- }
- 
-+static const struct mtk_soc_data mt7988_data = {
-+	.caps = MT7988_CAPS,
-+	.ana_rgc3 = 0x128,
-+	.gdma_count = 3,
-+	.pdma_base = PDMA_V3_BASE,
-+	.txd_size = sizeof(struct mtk_tx_dma_v2),
-+	.rxd_size = sizeof(struct mtk_rx_dma_v2),
-+};
-+
- static const struct mtk_soc_data mt7986_data = {
- 	.caps = MT7986_CAPS,
- 	.ana_rgc3 = 0x128,
-@@ -1930,6 +2085,7 @@ static const struct mtk_soc_data mt7621_
- };
- 
- static const struct udevice_id mtk_eth_ids[] = {
-+	{ .compatible = "mediatek,mt7988-eth", .data = (ulong)&mt7988_data },
- 	{ .compatible = "mediatek,mt7986-eth", .data = (ulong)&mt7986_data },
- 	{ .compatible = "mediatek,mt7981-eth", .data = (ulong)&mt7981_data },
- 	{ .compatible = "mediatek,mt7629-eth", .data = (ulong)&mt7629_data },
---- a/drivers/net/mtk_eth.h
-+++ b/drivers/net/mtk_eth.h
-@@ -51,6 +51,8 @@ enum mkt_eth_capabilities {
- 
- #define MT7986_CAPS  (MTK_NETSYS_V2)
- 
-+#define MT7988_CAPS  (MTK_NETSYS_V3 | MTK_INFRA)
-+
- /* Frame Engine Register Bases */
- #define PDMA_V1_BASE			0x0800
- #define PDMA_V2_BASE			0x6000
-@@ -59,6 +61,7 @@ enum mkt_eth_capabilities {
- #define GDMA2_BASE			0x1500
- #define GDMA3_BASE			0x0540
- #define GMAC_BASE			0x10000
-+#define GSW_BASE			0x20000
- 
- /* Ethernet subsystem registers */
- 
-@@ -117,6 +120,9 @@ enum mkt_eth_capabilities {
- #define RG_XFI_PLL_ANA_SWWA		0x02283248
- 
- /* Frame Engine Registers */
-+#define PSE_NO_DROP_CFG_REG		0x108
-+#define PSE_NO_DROP_GDM1		BIT(1)
-+
- #define FE_GLO_MISC_REG			0x124
- #define PDMA_VER_V2			BIT(4)
- 
-@@ -187,6 +193,17 @@ enum mkt_eth_capabilities {
- #define MDIO_RW_DATA_S			0
- #define MDIO_RW_DATA_M			0xffff
- 
-+#define GMAC_XGMAC_STS_REG		0x000c
-+#define P1_XGMAC_FORCE_LINK		BIT(15)
-+
-+#define GMAC_MAC_MISC_REG		0x0010
-+
-+#define GMAC_GSW_CFG_REG		0x0080
-+#define GSWTX_IPG_M			0xF0000
-+#define GSWTX_IPG_S			16
-+#define GSWRX_IPG_M			0xF
-+#define GSWRX_IPG_S			0
-+
- /* MDIO_CMD: MDIO commands */
- #define MDIO_CMD_ADDR			0
- #define MDIO_CMD_WRITE			1
-@@ -285,6 +302,9 @@ enum mkt_eth_capabilities {
- 					FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \
- 					FORCE_MODE_DPX   | FORCE_MODE_SPD | \
- 					FORCE_MODE_LNK
-+#define MT7988_FORCE_MODE		FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \
-+					FORCE_MODE_DPX   | FORCE_MODE_SPD | \
-+					FORCE_MODE_LNK
- 
- /* MT7531 SGMII Registers */
- #define MT7531_SGMII_REG_BASE		0x5000

package/boot/uboot-mediatek/patches/101-27-tools-mtk_image-use-uint32_t-for-ghf-header-magic-an.patch

@@ -1,55 +0,0 @@
-From 757b997f1f5a958e6fec3d5aee1ff5cdf5766711 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:45 +0800
-Subject: [PATCH 27/29] tools: mtk_image: use uint32_t for ghf header magic and
- version
-
-This patch converts magic and version fields of ghf common header
-to one field with the type of uint32_t to make this header flexible
-for futher updates.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- tools/mtk_image.c | 10 ++++++----
- tools/mtk_image.h |  6 +++---
- 2 files changed, 9 insertions(+), 7 deletions(-)
-
---- a/tools/mtk_image.c
-+++ b/tools/mtk_image.c
-@@ -542,11 +542,13 @@ static void put_brom_layout_header(struc
- 	hdr->type = cpu_to_le32(type);
- }
- 
--static void put_ghf_common_header(struct gfh_common_header *gfh, int size,
--				  int type, int ver)
-+static void put_ghf_common_header(struct gfh_common_header *gfh, uint16_t size,
-+				  uint16_t type, uint8_t ver)
- {
--	memcpy(gfh->magic, GFH_HEADER_MAGIC, sizeof(gfh->magic));
--	gfh->version = ver;
-+	uint32_t magic_version = GFH_HEADER_MAGIC |
-+				 (uint32_t)ver << GFH_HEADER_VERSION_SHIFT;
-+
-+	gfh->magic_version = cpu_to_le32(magic_version);
- 	gfh->size = cpu_to_le16(size);
- 	gfh->type = cpu_to_le16(type);
- }
---- a/tools/mtk_image.h
-+++ b/tools/mtk_image.h
-@@ -63,13 +63,13 @@ struct gen_device_header {
- 
- /* BootROM header definitions */
- struct gfh_common_header {
--	uint8_t magic[3];
--	uint8_t version;
-+	uint32_t magic_version;
- 	uint16_t size;
- 	uint16_t type;
- };
- 
--#define GFH_HEADER_MAGIC	"MMM"
-+#define GFH_HEADER_MAGIC		0x4D4D4D
-+#define GFH_HEADER_VERSION_SHIFT	24
- 
- #define GFH_TYPE_FILE_INFO	0
- #define GFH_TYPE_BL_INFO	1

package/boot/uboot-mediatek/patches/101-28-arm-mediatek-add-support-for-MediaTek-MT7988-SoC.patch

@@ -1,606 +0,0 @@
-From 884430dadcc2c5d0a2b248795001955a9fa5a1a9 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:49 +0800
-Subject: [PATCH 28/29] arm: mediatek: add support for MediaTek MT7988 SoC
-
-This patch adds basic support for MediaTek MT7988 SoC.
-This includes files that will initialize the SoC after boot and
-its device tree.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- arch/arm/dts/mt7988-u-boot.dtsi               |  25 ++
- arch/arm/dts/mt7988.dtsi                      | 391 ++++++++++++++++++
- arch/arm/mach-mediatek/Kconfig                |  13 +-
- arch/arm/mach-mediatek/Makefile               |   1 +
- arch/arm/mach-mediatek/mt7988/Makefile        |   4 +
- arch/arm/mach-mediatek/mt7988/init.c          |  63 +++
- arch/arm/mach-mediatek/mt7988/lowlevel_init.S |  30 ++
- 7 files changed, 526 insertions(+), 1 deletion(-)
- create mode 100644 arch/arm/dts/mt7988-u-boot.dtsi
- create mode 100644 arch/arm/dts/mt7988.dtsi
- create mode 100644 arch/arm/mach-mediatek/mt7988/Makefile
- create mode 100644 arch/arm/mach-mediatek/mt7988/init.c
- create mode 100644 arch/arm/mach-mediatek/mt7988/lowlevel_init.S
-
---- /dev/null
-+++ b/arch/arm/dts/mt7988-u-boot.dtsi
-@@ -0,0 +1,25 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2022 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+&system_clk {
-+	bootph-all;
-+};
-+
-+&spi_clk {
-+	bootph-all;
-+};
-+
-+&uart0 {
-+	bootph-all;
-+};
-+
-+&uart1 {
-+	bootph-all;
-+};
-+
-+&uart2 {
-+	bootph-all;
-+};
---- /dev/null
-+++ b/arch/arm/dts/mt7988.dtsi
-@@ -0,0 +1,391 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2022 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+#include <dt-bindings/interrupt-controller/irq.h>
-+#include <dt-bindings/interrupt-controller/arm-gic.h>
-+#include <dt-bindings/clock/mt7988-clk.h>
-+#include <dt-bindings/reset/mt7988-reset.h>
-+#include <dt-bindings/gpio/gpio.h>
-+
-+/ {
-+	compatible = "mediatek,mt7988-rfb";
-+	interrupt-parent = <&gic>;
-+	#address-cells = <2>;
-+	#size-cells = <2>;
-+
-+	cpus {
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+
-+		cpu0: cpu@0 {
-+			device_type = "cpu";
-+			compatible = "arm,cortex-a73";
-+			reg = <0x0>;
-+			mediatek,hwver = <&hwver>;
-+		};
-+
-+		cpu1: cpu@1 {
-+			device_type = "cpu";
-+			compatible = "arm,cortex-a73";
-+			reg = <0x1>;
-+			mediatek,hwver = <&hwver>;
-+		};
-+
-+		cpu2: cpu@2 {
-+			device_type = "cpu";
-+			compatible = "arm,cortex-a73";
-+			reg = <0x2>;
-+			mediatek,hwver = <&hwver>;
-+		};
-+
-+		cpu3: cpu@3 {
-+			device_type = "cpu";
-+			compatible = "arm,cortex-a73";
-+			reg = <0x3>;
-+			mediatek,hwver = <&hwver>;
-+		};
-+	};
-+
-+	system_clk: dummy40m {
-+		compatible = "fixed-clock";
-+		clock-frequency = <40000000>;
-+		#clock-cells = <0>;
-+	};
-+
-+	spi_clk: dummy208m {
-+		compatible = "fixed-clock";
-+		clock-frequency = <208000000>;
-+		#clock-cells = <0>;
-+	};
-+
-+	hwver: hwver {
-+		compatible = "mediatek,hwver", "syscon";
-+		reg = <0 0x8000000 0 0x1000>;
-+	};
-+
-+	timer {
-+		compatible = "arm,armv8-timer";
-+		interrupt-parent = <&gic>;
-+		clock-frequency = <13000000>;
-+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
-+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
-+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
-+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
-+	};
-+
-+	watchdog: watchdog@1001c000 {
-+		compatible = "mediatek,mt7622-wdt",
-+			     "mediatek,mt6589-wdt",
-+			     "syscon";
-+		reg = <0 0x1001c000 0 0x1000>;
-+		interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-+		#reset-cells = <1>;
-+	};
-+
-+	gic: interrupt-controller@c000000 {
-+		compatible = "arm,gic-v3";
-+		#interrupt-cells = <3>;
-+		interrupt-parent = <&gic>;
-+		interrupt-controller;
-+		reg = <0 0x0c000000 0 0x40000>,  /* GICD */
-+		      <0 0x0c080000 0 0x200000>; /* GICR */
-+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-+	};
-+
-+	infracfg_ao_cgs: infracfg_ao_cgs@10001000 {
-+		compatible = "mediatek,mt7988-infracfg_ao_cgs", "syscon";
-+		reg = <0 0x10001000 0 0x1000>;
-+		clock-parent = <&infracfg_ao>;
-+		#clock-cells = <1>;
-+	};
-+
-+	apmixedsys: apmixedsys@1001e000 {
-+		compatible = "mediatek,mt7988-fixed-plls", "syscon";
-+		reg = <0 0x1001e000 0 0x1000>;
-+		#clock-cells = <1>;
-+	};
-+
-+	topckgen: topckgen@1001b000 {
-+		compatible = "mediatek,mt7988-topckgen", "syscon";
-+		reg = <0 0x1001b000 0 0x1000>;
-+		clock-parent = <&apmixedsys>;
-+		#clock-cells = <1>;
-+	};
-+
-+	pinctrl: pinctrl@1001f000 {
-+		compatible = "mediatek,mt7988-pinctrl";
-+		reg = <0 0x1001f000 0 0x1000>,
-+		      <0 0x11c10000 0 0x1000>,
-+		      <0 0x11d00000 0 0x1000>,
-+		      <0 0x11d20000 0 0x1000>,
-+		      <0 0x11e00000 0 0x1000>,
-+		      <0 0x11f00000 0 0x1000>,
-+		      <0 0x1000b000 0 0x1000>;
-+		reg-names = "gpio_base", "iocfg_tr_base", "iocfg_br_base",
-+			    "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base",
-+			    "eint";
-+		gpio: gpio-controller {
-+			gpio-controller;
-+			#gpio-cells = <2>;
-+		};
-+	};
-+
-+	sgmiisys0: syscon@10060000 {
-+		compatible = "mediatek,mt7988-sgmiisys_0", "syscon";
-+		reg = <0 0x10060000 0 0x1000>;
-+		clock-parent = <&topckgen>;
-+		#clock-cells = <1>;
-+	};
-+
-+	sgmiisys1: syscon@10070000 {
-+		compatible = "mediatek,mt7988-sgmiisys_1", "syscon";
-+		reg = <0 0x10070000 0 0x1000>;
-+		clock-parent = <&topckgen>;
-+		#clock-cells = <1>;
-+	};
-+
-+	usxgmiisys0: syscon@10080000 {
-+		compatible = "mediatek,mt7988-usxgmiisys_0", "syscon";
-+		reg = <0 0x10080000 0 0x1000>;
-+		clock-parent = <&topckgen>;
-+		#clock-cells = <1>;
-+	};
-+
-+	usxgmiisys1: syscon@10081000 {
-+		compatible = "mediatek,mt7988-usxgmiisys_1", "syscon";
-+		reg = <0 0x10081000 0 0x1000>;
-+		clock-parent = <&topckgen>;
-+		#clock-cells = <1>;
-+	};
-+
-+	xfi_pextp0: syscon@11f20000 {
-+		compatible = "mediatek,mt7988-xfi_pextp_0", "syscon";
-+		reg = <0 0x11f20000 0 0x10000>;
-+		clock-parent = <&topckgen>;
-+		#clock-cells = <1>;
-+	};
-+
-+	xfi_pextp1: syscon@11f30000 {
-+		compatible = "mediatek,mt7988-xfi_pextp_1", "syscon";
-+		reg = <0 0x11f30000 0 0x10000>;
-+		clock-parent = <&topckgen>;
-+		#clock-cells = <1>;
-+	};
-+
-+	xfi_pll: syscon@11f40000 {
-+		compatible = "mediatek,mt7988-xfi_pll", "syscon";
-+		reg = <0 0x11f40000 0 0x1000>;
-+		clock-parent = <&topckgen>;
-+		#clock-cells = <1>;
-+	};
-+
-+	topmisc: topmisc@11d10000 {
-+		compatible = "mediatek,mt7988-topmisc", "syscon",
-+			     "mediatek,mt7988-power-controller";
-+		reg = <0 0x11d10000 0 0x10000>;
-+		clock-parent = <&topckgen>;
-+		#clock-cells = <1>;
-+	};
-+
-+	infracfg_ao: infracfg@10001000 {
-+		compatible = "mediatek,mt7988-infracfg", "syscon";
-+		reg = <0 0x10001000 0 0x1000>;
-+		clock-parent = <&topckgen>;
-+		#clock-cells = <1>;
-+	};
-+
-+	uart0: serial@11000000 {
-+		compatible = "mediatek,hsuart";
-+		reg = <0 0x11000000 0 0x100>;
-+		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
-+		clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART0_CK>;
-+		assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
-+				  <&infracfg_ao CK_INFRA_MUX_UART0_SEL>;
-+		assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
-+					 <&infracfg_ao CK_INFRA_UART_O0>;
-+		status = "disabled";
-+	};
-+
-+	uart1: serial@11000100 {
-+		compatible = "mediatek,hsuart";
-+		reg = <0 0x11000100 0 0x100>;
-+		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
-+		clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART1_CK>;
-+		assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
-+				  <&infracfg_ao CK_INFRA_MUX_UART1_SEL>;
-+		assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
-+					 <&infracfg_ao CK_INFRA_UART_O1>;
-+		status = "disabled";
-+	};
-+
-+	uart2: serial@11000200 {
-+		compatible = "mediatek,hsuart";
-+		reg = <0 0x11000200 0 0x100>;
-+		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
-+		clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART2_CK>;
-+		assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
-+				  <&infracfg_ao CK_INFRA_MUX_UART2_SEL>;
-+		assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
-+					 <&infracfg_ao CK_INFRA_UART_O2>;
-+		status = "disabled";
-+	};
-+
-+	i2c0: i2c@11003000 {
-+		compatible = "mediatek,mt7988-i2c",
-+			     "mediatek,mt7981-i2c";
-+		reg = <0 0x11003000 0 0x1000>,
-+		      <0 0x10217080 0 0x80>;
-+		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
-+		clock-div = <1>;
-+		clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
-+			 <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
-+		clock-names = "main", "dma";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		status = "disabled";
-+	};
-+
-+	i2c1: i2c@11004000 {
-+		compatible = "mediatek,mt7988-i2c",
-+			     "mediatek,mt7981-i2c";
-+		reg = <0 0x11004000 0 0x1000>,
-+		      <0 0x10217100 0 0x80>;
-+		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
-+		clock-div = <1>;
-+		clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
-+			 <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
-+		clock-names = "main", "dma";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		status = "disabled";
-+	};
-+
-+	i2c2: i2c@11005000 {
-+		compatible = "mediatek,mt7988-i2c",
-+			     "mediatek,mt7981-i2c";
-+		reg = <0 0x11005000 0 0x1000>,
-+		      <0 0x10217180 0 0x80>;
-+		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
-+		clock-div = <1>;
-+		clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
-+			 <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
-+		clock-names = "main", "dma";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		status = "disabled";
-+	};
-+
-+	pwm: pwm@10048000 {
-+		compatible = "mediatek,mt7988-pwm";
-+		reg = <0 0x10048000 0 0x1000>;
-+		#pwm-cells = <2>;
-+		clocks = <&infracfg_ao CK_INFRA_66M_PWM_BCK>,
-+			 <&infracfg_ao CK_INFRA_66M_PWM_HCK>,
-+			 <&infracfg_ao CK_INFRA_66M_PWM_CK1>,
-+			 <&infracfg_ao CK_INFRA_66M_PWM_CK2>,
-+			 <&infracfg_ao CK_INFRA_66M_PWM_CK3>,
-+			 <&infracfg_ao CK_INFRA_66M_PWM_CK4>,
-+			 <&infracfg_ao CK_INFRA_66M_PWM_CK5>,
-+			 <&infracfg_ao CK_INFRA_66M_PWM_CK6>,
-+			 <&infracfg_ao CK_INFRA_66M_PWM_CK7>,
-+			 <&infracfg_ao CK_INFRA_66M_PWM_CK8>;
-+		clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
-+			      "pwm4","pwm5","pwm6","pwm7","pwm8";
-+		status = "disabled";
-+	};
-+
-+	snand: snand@11001000 {
-+		compatible = "mediatek,mt7988-snand",
-+			     "mediatek,mt7986-snand";
-+		reg = <0 0x11001000 0 0x1000>,
-+		      <0 0x11002000 0 0x1000>;
-+		reg-names = "nfi", "ecc";
-+		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
-+		clocks = <&infracfg_ao CK_INFRA_SPINFI>,
-+			 <&infracfg_ao CK_INFRA_NFI>,
-+			 <&infracfg_ao CK_INFRA_66M_NFI_HCK>;
-+		clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
-+		assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
-+				  <&topckgen CK_TOP_NFI1X_SEL>;
-+		assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>,
-+					 <&topckgen CK_TOP_CB_M_D8>;
-+		status = "disabled";
-+	};
-+
-+	spi0: spi@1100a000 {
-+		compatible = "mediatek,ipm-spi";
-+		reg = <0 0x11007000 0 0x100>;
-+		clocks = <&spi_clk>,
-+			 <&spi_clk>;
-+		clock-names = "sel-clk", "spi-clk";
-+		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-+		status = "disabled";
-+	};
-+
-+	spi1: spi@1100b000 {
-+		compatible = "mediatek,ipm-spi";
-+		reg = <0 0x11008000 0 0x100>;
-+		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
-+		status = "disabled";
-+	};
-+
-+	spi2: spi@11009000 {
-+		compatible = "mediatek,ipm-spi";
-+		reg = <0 0x11009000 0 0x100>;
-+		clocks = <&spi_clk>,
-+			 <&spi_clk>;
-+		clock-names = "sel-clk", "spi-clk";
-+		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
-+		status = "disabled";
-+	};
-+
-+	mmc0: mmc@11230000 {
-+		compatible = "mediatek,mt7988-mmc",
-+			     "mediatek,mt7986-mmc";
-+		reg = <0 0x11230000 0 0x1000>;
-+		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-+		clocks = <&infracfg_ao_cgs CK_INFRA_MSDC400>,
-+			 <&infracfg_ao_cgs CK_INFRA_MSDC2_HCK>,
-+			 <&infracfg_ao_cgs CK_INFRA_133M_MSDC_0_HCK>,
-+			 <&infracfg_ao_cgs CK_INFRA_66M_MSDC_0_HCK>;
-+		clock-names = "source", "hclk", "source_cg", "axi_cg";
-+		status = "disabled";
-+	};
-+
-+	ethdma: syscon@15000000 {
-+		compatible = "mediatek,mt7988-ethdma", "syscon";
-+		reg = <0 0x15000000 0 0x20000>;
-+		clock-parent = <&topckgen>;
-+		#clock-cells = <1>;
-+		#reset-cells = <1>;
-+	};
-+
-+	ethwarp: syscon@15031000 {
-+		compatible = "mediatek,mt7988-ethwarp", "syscon";
-+		reg = <0 0x15031000 0 0x1000>;
-+		clock-parent = <&topckgen>;
-+		#clock-cells = <1>;
-+		#reset-cells = <1>;
-+	};
-+
-+	eth: ethernet@15100000 {
-+		compatible = "mediatek,mt7988-eth", "syscon";
-+		reg = <0 0x15100000 0 0x20000>;
-+		mediatek,ethsys = <&ethdma>;
-+		mediatek,sgmiisys = <&sgmiisys0>;
-+		mediatek,usxgmiisys = <&usxgmiisys0>;
-+		mediatek,xfi_pextp = <&xfi_pextp0>;
-+		mediatek,xfi_pll = <&xfi_pll>;
-+		mediatek,infracfg = <&topmisc>;
-+		mediatek,toprgu = <&watchdog>;
-+		resets = <&ethdma ETHDMA_FE_RST>, <&ethwarp ETHWARP_GSW_RST>;
-+		reset-names = "fe", "mcm";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		mediatek,mcm;
-+		status = "disabled";
-+	};
-+};
---- a/arch/arm/mach-mediatek/Kconfig
-+++ b/arch/arm/mach-mediatek/Kconfig
-@@ -58,6 +58,15 @@ config TARGET_MT7986
- 	  including UART, SPI, SPI flash, USB3.0, MMC, NAND, SNFI, PWM, PCIe,
- 	  Gigabit Ethernet, I2C, built-in 4x4 Wi-Fi, and PCIe.
- 
-+config TARGET_MT7988
-+	bool "MediaTek MT7988 SoC"
-+	select ARM64
-+	select CPU
-+	help
-+	  The MediaTek MT7988 is a ARM64-based SoC with a quad-core Cortex-A73.
-+	  including UART, SPI, SPI flash, USB3.0, MMC, NAND, SNFI, PWM, PCIe,
-+	  10 Gigabit Ethernet , I2C, and PCIe.
-+
- config TARGET_MT8183
- 	bool "MediaTek MT8183 SoC"
- 	select ARM64
-@@ -104,6 +113,7 @@ config SYS_BOARD
- 	default "mt7629" if TARGET_MT7629
- 	default "mt7981" if TARGET_MT7981
- 	default "mt7986" if TARGET_MT7986
-+	default "mt7988" if TARGET_MT7988
- 	default "mt8183" if TARGET_MT8183
- 	default "mt8512" if TARGET_MT8512
- 	default "mt8516" if TARGET_MT8516
-@@ -121,6 +131,7 @@ config SYS_CONFIG_NAME
- 	default "mt7629" if TARGET_MT7629
- 	default "mt7981" if TARGET_MT7981
- 	default "mt7986" if TARGET_MT7986
-+	default "mt7988" if TARGET_MT7988
- 	default "mt8183" if TARGET_MT8183
- 	default "mt8512" if TARGET_MT8512
- 	default "mt8516" if TARGET_MT8516
-@@ -135,7 +146,7 @@ config MTK_BROM_HEADER_INFO
- 	string
- 	default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7622
- 	default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183
--	default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986
-+	default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 || TARGET_MT7988
- 	default "lk=1" if TARGET_MT7623
- 
- source "board/mediatek/mt7629/Kconfig"
---- a/arch/arm/mach-mediatek/Makefile
-+++ b/arch/arm/mach-mediatek/Makefile
-@@ -9,6 +9,7 @@ obj-$(CONFIG_TARGET_MT7623) += mt7623/
- obj-$(CONFIG_TARGET_MT7629) += mt7629/
- obj-$(CONFIG_TARGET_MT7981) += mt7981/
- obj-$(CONFIG_TARGET_MT7986) += mt7986/
-+obj-$(CONFIG_TARGET_MT7988) += mt7988/
- obj-$(CONFIG_TARGET_MT8183) += mt8183/
- obj-$(CONFIG_TARGET_MT8516) += mt8516/
- obj-$(CONFIG_TARGET_MT8518) += mt8518/
---- /dev/null
-+++ b/arch/arm/mach-mediatek/mt7988/Makefile
-@@ -0,0 +1,4 @@
-+# SPDX-License-Identifier:	GPL-2.0
-+
-+obj-y += init.o
-+obj-y += lowlevel_init.o
---- /dev/null
-+++ b/arch/arm/mach-mediatek/mt7988/init.c
-@@ -0,0 +1,63 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (C) 2022 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+#include <fdtdec.h>
-+#include <init.h>
-+#include <asm/armv8/mmu.h>
-+#include <asm/global_data.h>
-+#include <asm/u-boot.h>
-+#include <asm/system.h>
-+
-+DECLARE_GLOBAL_DATA_PTR;
-+
-+#define SZ_8G				_AC(0x200000000, ULL)
-+
-+int dram_init(void)
-+{
-+	int ret;
-+
-+	ret = fdtdec_setup_mem_size_base();
-+	if (ret)
-+		return ret;
-+
-+	gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_8G);
-+
-+	return 0;
-+}
-+
-+int dram_init_banksize(void)
-+{
-+	gd->bd->bi_dram[0].start = gd->ram_base;
-+	gd->bd->bi_dram[0].size = gd->ram_size;
-+
-+	return 0;
-+}
-+
-+void reset_cpu(ulong addr)
-+{
-+	psci_system_reset();
-+}
-+
-+static struct mm_region mt7988_mem_map[] = {
-+	{
-+		/* DDR */
-+		.virt = 0x40000000UL,
-+		.phys = 0x40000000UL,
-+		.size = 0x200000000ULL,
-+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
-+	}, {
-+		.virt = 0x00000000UL,
-+		.phys = 0x00000000UL,
-+		.size = 0x40000000UL,
-+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-+			 PTE_BLOCK_NON_SHARE |
-+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-+	}, {
-+		0,
-+	}
-+};
-+
-+struct mm_region *mem_map = mt7988_mem_map;
---- /dev/null
-+++ b/arch/arm/mach-mediatek/mt7988/lowlevel_init.S
-@@ -0,0 +1,30 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * Copyright (C) 2020 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+/*
-+ * Switch from AArch64 EL2 to AArch32 EL2
-+ * @param inputs:
-+ * x0: argument, zero
-+ * x1: machine nr
-+ * x2: fdt address
-+ * x3: input argument
-+ * x4: kernel entry point
-+ * @param outputs for secure firmware:
-+ * x0: function id
-+ * x1: kernel entry point
-+ * x2: machine nr
-+ * x3: fdt address
-+*/
-+
-+.global armv8_el2_to_aarch32
-+armv8_el2_to_aarch32:
-+	mov     x3, x2
-+	mov     x2, x1
-+	mov     x1, x4
-+	mov	x4, #0
-+	ldr x0, =0x82000200
-+	SMC #0
-+	ret

package/boot/uboot-mediatek/patches/101-29-board-mediatek-add-MT7988-reference-boards.patch

@@ -1,575 +0,0 @@
-From fd7d9124ffa6761f27747daeea599e0ab874c1fa Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:54 +0800
-Subject: [PATCH 29/29] board: mediatek: add MT7988 reference boards
-
-This patch adds general board files based on MT7988 SoCs.
-
-MT7988 uses one mmc controller for booting from both SD and eMMC,
-and the pins of mmc controller booting from SD are also shared with
-one of spi controllers.
-So two configs are need for these boot types:
-
-1. mt7988_rfb_defconfig - SPI-NOR, SPI-NAND and eMMC
-2. mt7988_sd_rfb_defconfig - SPI-NAND and SD
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- arch/arm/dts/Makefile              |   2 +
- arch/arm/dts/mt7988-rfb.dts        | 182 +++++++++++++++++++++++++++++
- arch/arm/dts/mt7988-sd-rfb.dts     | 134 +++++++++++++++++++++
- board/mediatek/mt7988/MAINTAINERS  |   7 ++
- board/mediatek/mt7988/Makefile     |   3 +
- board/mediatek/mt7988/mt7988_rfb.c |  10 ++
- configs/mt7988_rfb_defconfig       |  83 +++++++++++++
- configs/mt7988_sd_rfb_defconfig    |  71 +++++++++++
- include/configs/mt7988.h           |  14 +++
- 9 files changed, 506 insertions(+)
- create mode 100644 arch/arm/dts/mt7988-rfb.dts
- create mode 100644 arch/arm/dts/mt7988-sd-rfb.dts
- create mode 100644 board/mediatek/mt7988/MAINTAINERS
- create mode 100644 board/mediatek/mt7988/Makefile
- create mode 100644 board/mediatek/mt7988/mt7988_rfb.c
- create mode 100644 configs/mt7988_rfb_defconfig
- create mode 100644 configs/mt7988_sd_rfb_defconfig
- create mode 100644 include/configs/mt7988.h
-
---- a/arch/arm/dts/Makefile
-+++ b/arch/arm/dts/Makefile
-@@ -1319,6 +1319,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
- 	mt7986b-sd-rfb.dtb \
- 	mt7986a-emmc-rfb.dtb \
- 	mt7986b-emmc-rfb.dtb \
-+	mt7988-rfb.dtb \
-+	mt7988-sd-rfb.dtb \
- 	mt8183-pumpkin.dtb \
- 	mt8512-bm1-emmc.dtb \
- 	mt8516-pumpkin.dtb \
---- /dev/null
-+++ b/arch/arm/dts/mt7988-rfb.dts
-@@ -0,0 +1,182 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2022 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+/dts-v1/;
-+#include "mt7988.dtsi"
-+#include <dt-bindings/gpio/gpio.h>
-+
-+/ {
-+	model = "mt7988-rfb";
-+	compatible = "mediatek,mt7988-rfb";
-+
-+	chosen {
-+		stdout-path = &uart0;
-+	};
-+
-+	memory@40000000 {
-+		device_type = "memory";
-+		reg = <0 0x40000000 0 0x10000000>;
-+	};
-+
-+	reg_3p3v: regulator-3p3v {
-+		compatible = "regulator-fixed";
-+		regulator-name = "fixed-3.3V";
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		regulator-boot-on;
-+		regulator-always-on;
-+	};
-+
-+	reg_1p8v: regulator-1p8v {
-+		compatible = "regulator-fixed";
-+		regulator-name = "fixed-1.8V";
-+		regulator-min-microvolt = <1800000>;
-+		regulator-max-microvolt = <1800000>;
-+		regulator-boot-on;
-+		regulator-always-on;
-+	};
-+};
-+
-+&uart0 {
-+	status = "okay";
-+};
-+
-+&i2c1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2c1_pins>;
-+	status = "okay";
-+};
-+
-+&eth {
-+	status = "okay";
-+	mediatek,gmac-id = <0>;
-+	phy-mode = "usxgmii";
-+	mediatek,switch = "mt7988";
-+
-+	fixed-link {
-+		speed = <1000>;
-+		full-duplex;
-+		pause;
-+	};
-+};
-+
-+&pinctrl {
-+	i2c1_pins: i2c1-pins {
-+		mux {
-+			function = "i2c";
-+			groups = "i2c1_0";
-+		};
-+	};
-+
-+	pwm_pins: pwm-pins {
-+		mux {
-+			function = "pwm";
-+			groups = "pwm0", "pwm1", "pwm2", "pwm3", "pwm4",
-+				 "pwm5", "pwm6", "pwm7";
-+		};
-+	};
-+
-+	spi0_pins: spi0-pins {
-+		mux {
-+			function = "spi";
-+			groups = "spi0", "spi0_wp_hold";
-+		};
-+	};
-+
-+	spi2_pins: spi2-pins {
-+		mux {
-+			function = "spi";
-+			groups = "spi2", "spi2_wp_hold";
-+		};
-+	};
-+
-+	mmc0_pins_default: mmc0default {
-+		mux {
-+			function = "flash";
-+			groups =  "emmc_51";
-+		};
-+
-+		conf-cmd-dat {
-+			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
-+			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
-+			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
-+			input-enable;
-+		};
-+
-+		conf-clk {
-+			pins = "EMMC_CK";
-+		};
-+
-+		conf-dsl {
-+			pins = "EMMC_DSL";
-+		};
-+
-+		conf-rst {
-+			pins = "EMMC_RSTB";
-+		};
-+	};
-+};
-+
-+&pwm {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&pwm_pins>;
-+	status = "okay";
-+};
-+
-+&spi0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&spi0_pins>;
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+	status = "okay";
-+	must_tx;
-+	enhance_timing;
-+	dma_ext;
-+	ipm_design;
-+	support_quad;
-+	tick_dly = <2>;
-+	sample_sel = <0>;
-+
-+	spi_nand@0 {
-+		compatible = "spi-nand";
-+		reg = <0>;
-+		spi-max-frequency = <52000000>;
-+	};
-+};
-+
-+&spi2 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&spi2_pins>;
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+	status = "okay";
-+	must_tx;
-+	enhance_timing;
-+	dma_ext;
-+	ipm_design;
-+	support_quad;
-+	tick_dly = <2>;
-+	sample_sel = <0>;
-+
-+	spi_nor@0 {
-+		compatible = "jedec,spi-nor";
-+		reg = <0>;
-+		spi-max-frequency = <52000000>;
-+	};
-+};
-+
-+&mmc0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&mmc0_pins_default>;
-+	max-frequency = <52000000>;
-+	bus-width = <8>;
-+	cap-mmc-highspeed;
-+	cap-mmc-hw-reset;
-+	vmmc-supply = <&reg_3p3v>;
-+	vqmmc-supply = <&reg_1p8v>;
-+	non-removable;
-+	status = "okay";
-+};
---- /dev/null
-+++ b/arch/arm/dts/mt7988-sd-rfb.dts
-@@ -0,0 +1,134 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2022 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+/dts-v1/;
-+#include "mt7988.dtsi"
-+#include <dt-bindings/gpio/gpio.h>
-+
-+/ {
-+	model = "mt7988-rfb";
-+	compatible = "mediatek,mt7988-rfb", "mediatek,mt7988-sd-rfb";
-+
-+	chosen {
-+		stdout-path = &uart0;
-+	};
-+
-+	memory@40000000 {
-+		device_type = "memory";
-+		reg = <0 0x40000000 0 0x10000000>;
-+	};
-+
-+	reg_3p3v: regulator-3p3v {
-+		compatible = "regulator-fixed";
-+		regulator-name = "fixed-3.3V";
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		regulator-boot-on;
-+		regulator-always-on;
-+	};
-+};
-+
-+&uart0 {
-+	status = "okay";
-+};
-+
-+&i2c1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2c1_pins>;
-+	status = "okay";
-+};
-+
-+&eth {
-+	status = "okay";
-+	mediatek,gmac-id = <0>;
-+	phy-mode = "usxgmii";
-+	mediatek,switch = "mt7988";
-+
-+	fixed-link {
-+		speed = <1000>;
-+		full-duplex;
-+		pause;
-+	};
-+};
-+
-+&pinctrl {
-+	i2c1_pins: i2c1-pins {
-+		mux {
-+			function = "i2c";
-+			groups = "i2c1_0";
-+		};
-+	};
-+
-+	pwm_pins: pwm-pins {
-+		mux {
-+			function = "pwm";
-+			groups = "pwm0", "pwm1", "pwm2", "pwm3", "pwm4",
-+				 "pwm5", "pwm6", "pwm7";
-+		};
-+	};
-+
-+	spi0_pins: spi0-pins {
-+		mux {
-+			function = "spi";
-+			groups = "spi0", "spi0_wp_hold";
-+		};
-+	};
-+
-+	mmc1_pins_default: mmc1default {
-+		mux {
-+			function = "flash";
-+			groups =  "emmc_45";
-+		};
-+
-+		conf-cmd-dat {
-+			pins = "SPI2_CSB", "SPI2_MISO", "SPI2_MOSI",
-+			       "SPI2_CLK", "SPI2_HOLD";
-+			input-enable;
-+		};
-+
-+		conf-clk {
-+			pins = "SPI2_WP";
-+		};
-+	};
-+};
-+
-+&pwm {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&pwm_pins>;
-+	status = "okay";
-+};
-+
-+&spi0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&spi0_pins>;
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+	status = "okay";
-+	must_tx;
-+	enhance_timing;
-+	dma_ext;
-+	ipm_design;
-+	support_quad;
-+	tick_dly = <2>;
-+	sample_sel = <0>;
-+
-+	spi_nand@0 {
-+		compatible = "spi-nand";
-+		reg = <0>;
-+		spi-max-frequency = <52000000>;
-+	};
-+};
-+
-+&mmc0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&mmc1_pins_default>;
-+	max-frequency = <52000000>;
-+	bus-width = <4>;
-+	cap-sd-highspeed;
-+	vmmc-supply = <&reg_3p3v>;
-+	vqmmc-supply = <&reg_3p3v>;
-+	status = "okay";
-+};
---- /dev/null
-+++ b/board/mediatek/mt7988/MAINTAINERS
-@@ -0,0 +1,7 @@
-+MT7988
-+M:	Sam Shih <sam.shih@mediatek.com>
-+S:	Maintained
-+F:	board/mediatek/mt7988
-+F:	include/configs/mt7988.h
-+F:	configs/mt7988_rfb_defconfig
-+F:	configs/mt7988_sd_rfb_defconfig
---- /dev/null
-+++ b/board/mediatek/mt7988/Makefile
-@@ -0,0 +1,3 @@
-+# SPDX-License-Identifier:	GPL-2.0
-+
-+obj-y	+= mt7988_rfb.o
---- /dev/null
-+++ b/board/mediatek/mt7988/mt7988_rfb.c
-@@ -0,0 +1,10 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (C) 2022 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+int board_init(void)
-+{
-+	return 0;
-+}
---- /dev/null
-+++ b/configs/mt7988_rfb_defconfig
-@@ -0,0 +1,83 @@
-+CONFIG_ARM=y
-+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
-+CONFIG_POSITION_INDEPENDENT=y
-+CONFIG_ARCH_MEDIATEK=y
-+CONFIG_TEXT_BASE=0x41e00000
-+CONFIG_SYS_MALLOC_F_LEN=0x4000
-+CONFIG_NR_DRAM_BANKS=1
-+CONFIG_DEFAULT_DEVICE_TREE="mt7988-rfb"
-+CONFIG_SYS_PROMPT="MT7988> "
-+CONFIG_TARGET_MT7988=y
-+CONFIG_DEBUG_UART_BASE=0x11000000
-+CONFIG_DEBUG_UART_CLOCK=40000000
-+CONFIG_SYS_LOAD_ADDR=0x50000000
-+CONFIG_DEBUG_UART=y
-+# CONFIG_AUTOBOOT is not set
-+CONFIG_DEFAULT_FDT_FILE="mt7988-rfb"
-+CONFIG_LOGLEVEL=7
-+CONFIG_LOG=y
-+CONFIG_SYS_CBSIZE=512
-+CONFIG_SYS_PBSIZE=1049
-+# CONFIG_BOOTM_NETBSD is not set
-+# CONFIG_BOOTM_PLAN9 is not set
-+# CONFIG_BOOTM_RTEMS is not set
-+# CONFIG_BOOTM_VXWORKS is not set
-+# CONFIG_CMD_ELF is not set
-+CONFIG_CMD_CLK=y
-+CONFIG_CMD_DM=y
-+CONFIG_CMD_GPIO=y
-+CONFIG_CMD_PWM=y
-+CONFIG_CMD_MMC=y
-+CONFIG_CMD_MTD=y
-+CONFIG_CMD_PING=y
-+CONFIG_CMD_SMC=y
-+CONFIG_DOS_PARTITION=y
-+CONFIG_EFI_PARTITION=y
-+CONFIG_PARTITION_TYPE_GUID=y
-+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-+CONFIG_NET_RANDOM_ETHADDR=y
-+CONFIG_USE_IPADDR=y
-+CONFIG_IPADDR="192.168.1.1"
-+CONFIG_USE_NETMASK=y
-+CONFIG_NETMASK="255.255.255.0"
-+CONFIG_USE_SERVERIP=y
-+CONFIG_SERVERIP="192.168.1.2"
-+CONFIG_PROT_TCP=y
-+CONFIG_REGMAP=y
-+CONFIG_SYSCON=y
-+CONFIG_CLK=y
-+CONFIG_MMC_HS200_SUPPORT=y
-+CONFIG_MMC_MTK=y
-+CONFIG_MTD=y
-+CONFIG_DM_MTD=y
-+CONFIG_MTD_SPI_NAND=y
-+CONFIG_DM_SPI_FLASH=y
-+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
-+CONFIG_SPI_FLASH_EON=y
-+CONFIG_SPI_FLASH_GIGADEVICE=y
-+CONFIG_SPI_FLASH_ISSI=y
-+CONFIG_SPI_FLASH_MACRONIX=y
-+CONFIG_SPI_FLASH_SPANSION=y
-+CONFIG_SPI_FLASH_STMICRO=y
-+CONFIG_SPI_FLASH_WINBOND=y
-+CONFIG_SPI_FLASH_XMC=y
-+CONFIG_SPI_FLASH_XTX=y
-+CONFIG_SPI_FLASH_MTD=y
-+CONFIG_PHY_FIXED=y
-+CONFIG_MEDIATEK_ETH=y
-+CONFIG_PINCTRL=y
-+CONFIG_PINCONF=y
-+CONFIG_PINCTRL_MT7988=y
-+CONFIG_POWER_DOMAIN=y
-+CONFIG_MTK_POWER_DOMAIN=y
-+CONFIG_DM_PWM=y
-+CONFIG_PWM_MTK=y
-+CONFIG_RAM=y
-+CONFIG_DM_SERIAL=y
-+CONFIG_MTK_SERIAL=y
-+CONFIG_SPI=y
-+CONFIG_DM_SPI=y
-+CONFIG_MTK_SPIM=y
-+CONFIG_LZO=y
-+CONFIG_HEXDUMP=y
-+# CONFIG_EFI_LOADER is not set
---- /dev/null
-+++ b/configs/mt7988_sd_rfb_defconfig
-@@ -0,0 +1,71 @@
-+CONFIG_ARM=y
-+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
-+CONFIG_POSITION_INDEPENDENT=y
-+CONFIG_ARCH_MEDIATEK=y
-+CONFIG_TEXT_BASE=0x41e00000
-+CONFIG_SYS_MALLOC_F_LEN=0x4000
-+CONFIG_NR_DRAM_BANKS=1
-+CONFIG_DEFAULT_DEVICE_TREE="mt7988-sd-rfb"
-+CONFIG_SYS_PROMPT="MT7988> "
-+CONFIG_TARGET_MT7988=y
-+CONFIG_DEBUG_UART_BASE=0x11000000
-+CONFIG_DEBUG_UART_CLOCK=40000000
-+CONFIG_SYS_LOAD_ADDR=0x50000000
-+CONFIG_DEBUG_UART=y
-+# CONFIG_AUTOBOOT is not set
-+CONFIG_DEFAULT_FDT_FILE="mt7988-sd-rfb"
-+CONFIG_LOGLEVEL=7
-+CONFIG_LOG=y
-+CONFIG_SYS_CBSIZE=512
-+CONFIG_SYS_PBSIZE=1049
-+# CONFIG_BOOTM_NETBSD is not set
-+# CONFIG_BOOTM_PLAN9 is not set
-+# CONFIG_BOOTM_RTEMS is not set
-+# CONFIG_BOOTM_VXWORKS is not set
-+# CONFIG_CMD_ELF is not set
-+CONFIG_CMD_CLK=y
-+CONFIG_CMD_DM=y
-+CONFIG_CMD_GPIO=y
-+CONFIG_CMD_PWM=y
-+CONFIG_CMD_MMC=y
-+CONFIG_CMD_MTD=y
-+CONFIG_CMD_PING=y
-+CONFIG_CMD_SMC=y
-+CONFIG_DOS_PARTITION=y
-+CONFIG_EFI_PARTITION=y
-+CONFIG_PARTITION_TYPE_GUID=y
-+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-+CONFIG_NET_RANDOM_ETHADDR=y
-+CONFIG_USE_IPADDR=y
-+CONFIG_IPADDR="192.168.1.1"
-+CONFIG_USE_NETMASK=y
-+CONFIG_NETMASK="255.255.255.0"
-+CONFIG_USE_SERVERIP=y
-+CONFIG_SERVERIP="192.168.1.2"
-+CONFIG_PROT_TCP=y
-+CONFIG_REGMAP=y
-+CONFIG_SYSCON=y
-+CONFIG_CLK=y
-+CONFIG_MMC_HS200_SUPPORT=y
-+CONFIG_MMC_MTK=y
-+CONFIG_MTD=y
-+CONFIG_DM_MTD=y
-+CONFIG_MTD_SPI_NAND=y
-+CONFIG_PHY_FIXED=y
-+CONFIG_MEDIATEK_ETH=y
-+CONFIG_PINCTRL=y
-+CONFIG_PINCONF=y
-+CONFIG_PINCTRL_MT7988=y
-+CONFIG_POWER_DOMAIN=y
-+CONFIG_MTK_POWER_DOMAIN=y
-+CONFIG_DM_PWM=y
-+CONFIG_PWM_MTK=y
-+CONFIG_RAM=y
-+CONFIG_DM_SERIAL=y
-+CONFIG_MTK_SERIAL=y
-+CONFIG_SPI=y
-+CONFIG_DM_SPI=y
-+CONFIG_MTK_SPIM=y
-+CONFIG_LZO=y
-+CONFIG_HEXDUMP=y
-+# CONFIG_EFI_LOADER is not set
---- /dev/null
-+++ b/include/configs/mt7988.h
-@@ -0,0 +1,14 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * Configuration for MediaTek MT7988 SoC
-+ *
-+ * Copyright (C) 2022 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+#ifndef __MT7988_H
-+#define __MT7988_H
-+
-+#define CFG_MAX_MEM_MAPPED		0xC0000000
-+
-+#endif

package/boot/uboot-mediatek/patches/102-ram-mediatek-include-linux-sizes.h-for-SZ_-macros.patch

@@ -1,47 +0,0 @@
-From 4bd66fd5b69eda41b4320fd6f8db50a7b7fa7bf7 Mon Sep 17 00:00:00 2001
-Message-ID: <4bd66fd5b69eda41b4320fd6f8db50a7b7fa7bf7.1690828424.git.daniel@makrotopia.org>
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Mon, 31 Jul 2023 19:25:04 +0100
-Subject: [PATCH] ram: mediatek: include <linux/sizes.h> for SZ_* macros
-To: Ryder Lee <ryder.lee@mediatek.com>,
-    Weijie Gao <weijie.gao@mediatek.com>,
-    Chunfeng Yun <chunfeng.yun@mediatek.com>,
-    GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>,
-    u-boot@lists.denx.de
-
-Something between U-Boot 2023.04 and 2023.07.02 resulted in no longer
-implicitely including <linux/sizes.h> in the DDR3 RAM driver for the
-MT7929 SoC. The result is a build failure:
-drivers/ram/mediatek/ddr3-mt7629.c: In function 'mtk_ddr3_get_info':
-drivers/ram/mediatek/ddr3-mt7629.c:734:30: error: 'SZ_128M' undeclared (first use in this function)
-  734 |                 info->size = SZ_128M;
-      |                              ^~~~~~~
-drivers/ram/mediatek/ddr3-mt7629.c:734:30: note: each undeclared identifier is reported only once for each function it appears in
-drivers/ram/mediatek/ddr3-mt7629.c:737:30: error: 'SZ_256M' undeclared (first use in this function)
-  737 |                 info->size = SZ_256M;
-      |                              ^~~~~~~
-drivers/ram/mediatek/ddr3-mt7629.c:740:30: error: 'SZ_512M' undeclared (first use in this function)
-  740 |                 info->size = SZ_512M;
-      |                              ^~~~~~~
-drivers/ram/mediatek/ddr3-mt7629.c:743:30: error: 'SZ_1G' undeclared (first use in this function)
-  743 |                 info->size = SZ_1G;
-      |                              ^~~~~
-
-Include <linux/sizes.h> so SZ_* is defined.
-
-Reported-by: Tianling Shen <cnsztl@immortalwrt.org>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/ram/mediatek/ddr3-mt7629.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/ram/mediatek/ddr3-mt7629.c
-+++ b/drivers/ram/mediatek/ddr3-mt7629.c
-@@ -14,6 +14,7 @@
- #include <asm/io.h>
- #include <linux/bitops.h>
- #include <linux/delay.h>
-+#include <linux/sizes.h>
- 
- /* EMI */
- #define EMI_CONA			0x000

package/boot/uboot-mediatek/patches/103-mt7988-enable-pstore.patch

@@ -1,6 +1,6 @@
 --- a/arch/arm/dts/mt7988.dtsi
 +++ b/arch/arm/dts/mt7988.dtsi
-@@ -61,6 +61,30 @@
+@@ -62,6 +62,30 @@
  		#clock-cells = <0>;
  	};
  

package/boot/uboot-mediatek/patches/104-configs-set-CONFIG_LMB_MAX_REGIONS-64-for-MT7988-boards.patch

@@ -1,69 +0,0 @@
-From patchwork Mon Aug 21 19:38:23 2023
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
-X-Patchwork-Id: 1823742
-X-Patchwork-Delegate: trini@ti.com
-Return-Path: <u-boot-bounces@lists.denx.de>
-X-Original-To: incoming@patchwork.ozlabs.org
-Delivered-To: patchwork-incoming@legolas.ozlabs.org
-Date: Mon, 21 Aug 2023 20:38:23 +0100
-From: Daniel Golle <daniel@makrotopia.org>
-To: Sam Shih <sam.shih@mediatek.com>, Weijie Gao <weijie.gao@mediatek.com>,
- Lorenzo Bianconi <lorenzo@kernel.org>, u-boot@lists.denx.de
-Subject: [PATCH] configs: set CONFIG_LMB_MAX_REGIONS=64 for MT7988 boards
-Message-ID: 
- <568a8030acf9056266b5c96055cea54f810496c9.1692646620.git.daniel@makrotopia.org>
-MIME-Version: 1.0
-Content-Disposition: inline
-X-BeenThere: u-boot@lists.denx.de
-X-Mailman-Version: 2.1.39
-Precedence: list
-List-Id: U-Boot discussion <u-boot.lists.denx.de>
-List-Unsubscribe: <https://lists.denx.de/options/u-boot>,
- <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>
-List-Archive: <https://lists.denx.de/pipermail/u-boot/>
-List-Post: <mailto:u-boot@lists.denx.de>
-List-Help: <mailto:u-boot-request@lists.denx.de?subject=help>
-List-Subscribe: <https://lists.denx.de/listinfo/u-boot>,
- <mailto:u-boot-request@lists.denx.de?subject=subscribe>
-Errors-To: u-boot-bounces@lists.denx.de
-Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
-
-Similar to MT7981 and MT7986 also MT7988 can have a high number of
-reserved-memory regions used by the various hardware offloading
-subsystems.
-
-Raise CONFIG_LMB_MAX_REGIONS to 64 to avoid errors when trying to boot
-Linux with more then 6 reserved regions:
-
-ERROR: reserving fdt memory region failed (addr=4f700000 size=240000 flags=4)
-ERROR: reserving fdt memory region failed (addr=15194000 size=1000 flags=4)
-ERROR: reserving fdt memory region failed (addr=15294000 size=1000 flags=4)
-ERROR: reserving fdt memory region failed (addr=15394000 size=1000 flags=4)
-ERROR: Failed to allocate 0xb161 bytes below 0x80000000.
-device tree - allocation error
-
-Fixes: bc4adc97cfb ("board: mediatek: add MT7988 reference boards")
-Reported-by: Lorenzo Bianconi <lorenzo@kernel.org>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- configs/mt7988_rfb_defconfig    | 1 +
- configs/mt7988_sd_rfb_defconfig | 1 +
- 2 files changed, 2 insertions(+)
-
---- a/configs/mt7988_rfb_defconfig
-+++ b/configs/mt7988_rfb_defconfig
-@@ -81,3 +81,4 @@ CONFIG_MTK_SPIM=y
- CONFIG_LZO=y
- CONFIG_HEXDUMP=y
- # CONFIG_EFI_LOADER is not set
-+CONFIG_LMB_MAX_REGIONS=64
---- a/configs/mt7988_sd_rfb_defconfig
-+++ b/configs/mt7988_sd_rfb_defconfig
-@@ -69,3 +69,4 @@ CONFIG_MTK_SPIM=y
- CONFIG_LZO=y
- CONFIG_HEXDUMP=y
- # CONFIG_EFI_LOADER is not set
-+CONFIG_LMB_MAX_REGIONS=64

package/boot/uboot-mediatek/patches/105-configs-add-usefull-stuff-to-mt7988-rfb.patch

@@ -1,8 +1,8 @@
 --- a/configs/mt7988_sd_rfb_defconfig
 +++ b/configs/mt7988_sd_rfb_defconfig
-@@ -12,6 +12,24 @@ CONFIG_DEBUG_UART_BASE=0x11000000
+@@ -11,6 +11,24 @@ CONFIG_DEBUG_UART_BASE=0x11000000
  CONFIG_DEBUG_UART_CLOCK=40000000
- CONFIG_SYS_LOAD_ADDR=0x50000000
+ CONFIG_SYS_LOAD_ADDR=0x46000000
  CONFIG_DEBUG_UART=y
 +CONFIG_OF_LIBFDT_OVERLAY=y
 +CONFIG_SMBIOS_PRODUCT_NAME=""
@@ -157,9 +157,9 @@
  CONFIG_MTD=y
 --- a/configs/mt7988_rfb_defconfig
 +++ b/configs/mt7988_rfb_defconfig
-@@ -12,6 +12,24 @@ CONFIG_DEBUG_UART_BASE=0x11000000
+@@ -11,6 +11,24 @@ CONFIG_DEBUG_UART_BASE=0x11000000
  CONFIG_DEBUG_UART_CLOCK=40000000
- CONFIG_SYS_LOAD_ADDR=0x50000000
+ CONFIG_SYS_LOAD_ADDR=0x46000000
  CONFIG_DEBUG_UART=y
 +CONFIG_OF_LIBFDT_OVERLAY=y
 +CONFIG_SMBIOS_PRODUCT_NAME=""

package/boot/uboot-mediatek/patches/107-configs-add-useful-options-to-mt7981-rfb.patch

@@ -1,6 +1,6 @@
 --- a/configs/mt7981_emmc_rfb_defconfig
 +++ b/configs/mt7981_emmc_rfb_defconfig
-@@ -14,7 +14,22 @@ CONFIG_DEBUG_UART_BASE=0x11002000
+@@ -13,7 +13,22 @@ CONFIG_DEBUG_UART_BASE=0x11002000
  CONFIG_DEBUG_UART_CLOCK=40000000
  CONFIG_SYS_LOAD_ADDR=0x46000000
  CONFIG_DEBUG_UART=y
@@ -87,7 +87,7 @@
  CONFIG_CLK=y
 --- a/configs/mt7981_rfb_defconfig
 +++ b/configs/mt7981_rfb_defconfig
-@@ -12,7 +12,23 @@ CONFIG_DEBUG_UART_BASE=0x11002000
+@@ -11,7 +11,23 @@ CONFIG_DEBUG_UART_BASE=0x11002000
  CONFIG_DEBUG_UART_CLOCK=40000000
  CONFIG_SYS_LOAD_ADDR=0x46000000
  CONFIG_DEBUG_UART=y
@@ -191,7 +191,7 @@
  CONFIG_MTD_SPI_NAND=y
 --- a/configs/mt7981_sd_rfb_defconfig
 +++ b/configs/mt7981_sd_rfb_defconfig
-@@ -14,7 +14,22 @@ CONFIG_DEBUG_UART_BASE=0x11002000
+@@ -13,7 +13,22 @@ CONFIG_DEBUG_UART_BASE=0x11002000
  CONFIG_DEBUG_UART_CLOCK=40000000
  CONFIG_SYS_LOAD_ADDR=0x46000000
  CONFIG_DEBUG_UART=y

package/boot/uboot-mediatek/patches/110-no-kwbimage.patch

@@ -5,6 +5,6 @@
  			imx8image.o \
  			imx8mimage.o \
 -			kwbimage.o \
- 			lib/md5.o \
+ 			generated/lib/md5.o \
  			lpc32xximage.o \
  			mxsimage.o \

package/boot/uboot-mediatek/patches/120-use-xz-instead-of-lzma.patch

@@ -1,6 +1,6 @@
 --- a/Makefile
 +++ b/Makefile
-@@ -1070,7 +1070,7 @@ quiet_cmd_pad_cat = CAT     $@
+@@ -1083,7 +1083,7 @@ quiet_cmd_pad_cat = CAT     $@
  cmd_pad_cat = $(cmd_objcopy) && $(append) || { rm -f $@; false; }
  
  quiet_cmd_lzma = LZMA    $@

package/boot/uboot-mediatek/patches/130-fix-mkimage-host-build.patch

@@ -1,6 +1,6 @@
 --- a/tools/image-host.c
 +++ b/tools/image-host.c
-@@ -1125,6 +1125,7 @@ static int fit_config_add_verification_d
+@@ -1137,6 +1137,7 @@ static int fit_config_add_verification_d
   * 2) get public key (X509_get_pubkey)
   * 3) provide der format (d2i_RSAPublicKey)
   */
@@ -8,7 +8,7 @@
  static int read_pub_key(const char *keydir, const void *name,
  			unsigned char **pubkey, int *pubkey_len)
  {
-@@ -1178,6 +1179,13 @@ err_cert:
+@@ -1190,6 +1191,13 @@ err_cert:
  	fclose(f);
  	return ret;
  }

package/boot/uboot-mediatek/patches/131-spi-mtk_spim-prevent-global-pll-clock-override.patch

@@ -1,47 +0,0 @@
-From 41f225dae30ea6ddcff10f120a9e732f994d3a07 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Nicol=C3=B2=20Veronese?= <nicveronese@gmail.com>
-Date: Tue, 3 Oct 2023 23:46:52 +0200
-Subject: [PATCH] spi: mtk_spim: prevent global pll clock override
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-With commit 793e6230118032a099ec42a1ea67f434721edcc0
- a new system to calculate the SPI clocks has been added.
-
-Unfortunately, the do_div macro overrides the global
- priv->pll_clk_rate field. This will cause to have a reduced
- clock rate on each subsequent SPI call.
-
-Signed-off-by: Valerio 'ftp21' Mancini <ftp21@ftp21.eu>
-Signed-off-by: Nicolò Veronese <nicveronese@gmail.com>
----
- drivers/spi/mtk_spim.c | 7 ++++---
- 1 file changed, 4 insertions(+), 3 deletions(-)
-
---- a/drivers/spi/mtk_spim.c
-+++ b/drivers/spi/mtk_spim.c
-@@ -409,7 +409,7 @@ static int mtk_spim_transfer_wait(struct
- {
- 	struct udevice *bus = dev_get_parent(slave->dev);
- 	struct mtk_spim_priv *priv = dev_get_priv(bus);
--	u32 sck_l, sck_h, clk_count, reg;
-+	u32 pll_clk, sck_l, sck_h, clk_count, reg;
- 	ulong us = 1;
- 	int ret = 0;
- 
-@@ -418,11 +418,12 @@ static int mtk_spim_transfer_wait(struct
- 	else
- 		clk_count = op->data.nbytes;
- 
-+	pll_clk = priv->pll_clk_rate;
- 	sck_l = readl(priv->base + SPI_CFG2_REG) >> SPI_CFG2_SCK_LOW_OFFSET;
- 	sck_h = readl(priv->base + SPI_CFG2_REG) & SPI_CFG2_SCK_HIGH_MASK;
--	do_div(priv->pll_clk_rate, sck_l + sck_h + 2);
-+	do_div(pll_clk, sck_l + sck_h + 2);
- 
--	us = CLK_TO_US(priv->pll_clk_rate, clk_count * 8);
-+	us = CLK_TO_US(pll_clk, clk_count * 8);
- 	us += 1000 * 1000; /* 1s tolerance */
- 
- 	if (us > UINT_MAX)

package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch

@@ -1,6 +1,6 @@
 --- a/cmd/bootm.c
 +++ b/cmd/bootm.c
-@@ -259,6 +259,67 @@ U_BOOT_CMD(
+@@ -245,6 +245,67 @@ U_BOOT_CMD(
  /* iminfo - print header info for a requested image */
  /*******************************************************************/
  #if defined(CONFIG_CMD_IMI)
@@ -120,7 +120,7 @@
  		   int arch, int ph_type, int bootstage_id,
 --- a/include/image.h
 +++ b/include/image.h
-@@ -1047,6 +1047,7 @@ int fit_parse_subimage(const char *spec,
+@@ -1049,6 +1049,7 @@ int fit_parse_subimage(const char *spec,
  		ulong *addr, const char **image_name);
  
  int fit_get_subimage_count(const void *fit, int images_noffset);

package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch

@@ -1,6 +1,6 @@
 --- a/cmd/Kconfig
 +++ b/cmd/Kconfig
-@@ -602,6 +602,12 @@ config CMD_ENV_EXISTS
+@@ -622,6 +622,12 @@ config CMD_ENV_EXISTS
  	  Check if a variable is defined in the environment for use in
  	  shell scripting.
  
@@ -15,7 +15,7 @@
  	help
 --- a/cmd/nvedit.c
 +++ b/cmd/nvedit.c
-@@ -408,6 +408,60 @@ int do_env_ask(struct cmd_tbl *cmdtp, in
+@@ -385,6 +385,60 @@ int do_env_ask(struct cmd_tbl *cmdtp, in
  }
  #endif
  
@@ -76,7 +76,7 @@
  #if defined(CONFIG_CMD_ENV_CALLBACK)
  static int print_static_binding(const char *var_name, const char *callback_name,
  				void *priv)
-@@ -1228,6 +1282,9 @@ static struct cmd_tbl cmd_env_sub[] = {
+@@ -1201,6 +1255,9 @@ static struct cmd_tbl cmd_env_sub[] = {
  	U_BOOT_CMD_MKENT(load, 1, 0, do_env_load, "", ""),
  #endif
  	U_BOOT_CMD_MKENT(print, CONFIG_SYS_MAXARGS, 1, do_env_print, "", ""),
@@ -86,7 +86,7 @@
  #if defined(CONFIG_CMD_RUN)
  	U_BOOT_CMD_MKENT(run, CONFIG_SYS_MAXARGS, 1, do_run, "", ""),
  #endif
-@@ -1319,6 +1376,9 @@ static char env_help_text[] =
+@@ -1284,6 +1341,9 @@ U_BOOT_LONGHELP(env,
  #if defined(CONFIG_CMD_NVEDIT_EFI)
  	"env print -e [-guid guid] [-n] [name ...] - print UEFI environment\n"
  #endif
@@ -96,7 +96,7 @@
  #if defined(CONFIG_CMD_RUN)
  	"env run var [...] - run commands in an environment variable\n"
  #endif
-@@ -1428,6 +1488,17 @@ U_BOOT_CMD(
+@@ -1392,6 +1452,17 @@ U_BOOT_CMD(
  );
  #endif
  

package/boot/uboot-mediatek/patches/230-cmd-add-pstore-check.patch

@@ -67,7 +67,7 @@
  	U_BOOT_CMD_MKENT(display, 3, 0, pstore_display, "", ""),
  	U_BOOT_CMD_MKENT(save, 4, 0, pstore_save, "", ""),
  };
-@@ -560,6 +613,8 @@ U_BOOT_CMD(pstore, 10, 0, do_pstore,
+@@ -566,6 +619,8 @@ U_BOOT_CMD(pstore, 10, 0, do_pstore,
  	   "  'pmsg-size' is the size of the user space logs record.\n"
  	   "  'ecc-size' enables/disables ECC support and specifies ECC buffer size in\n"
  	   "  bytes (0 disables it, 1 is a special value, means 16 bytes ECC).\n"

package/boot/uboot-mediatek/patches/250-fix-mmc-erase-timeout.patch

@@ -0,0 +1,11 @@
+--- a/drivers/mmc/mmc_write.c
++++ b/drivers/mmc/mmc_write.c
+@@ -80,7 +80,7 @@ ulong mmc_berase(struct blk_desc *block_
+ 	u32 start_rem, blkcnt_rem, erase_args = 0;
+ 	struct mmc *mmc = find_mmc_device(dev_num);
+ 	lbaint_t blk = 0, blk_r = 0;
+-	int timeout_ms = 1000;
++	int timeout_ms = blkcnt;
+ 
+ 	if (!mmc)
+ 		return -1;

package/boot/uboot-mediatek/patches/300-mt7623-fix-mmc-get-env-dev.patch

@@ -0,0 +1,46 @@
+--- a/board/mediatek/mt7623/mt7623_rfb.c
++++ b/board/mediatek/mt7623/mt7623_rfb.c
+@@ -5,6 +5,7 @@
+ 
+ #include <common.h>
+ #include <mmc.h>
++#include <part.h>
+ #include <asm/global_data.h>
+ 
+ DECLARE_GLOBAL_DATA_PTR;
+@@ -22,8 +23,9 @@ int mmc_get_boot_dev(void)
+ {
+ 	int g_mmc_devid = -1;
+ 	char *uflag = (char *)0x81DFFFF0;
++	struct blk_desc *desc;
+ 
+-	if (!find_mmc_device(1))
++	if (blk_get_device_by_str("mmc", "1", &desc) < 0)
+ 		return 0;
+ 
+ 	if (strncmp(uflag,"eMMC",4)==0) {
+@@ -38,6 +40,23 @@ int mmc_get_boot_dev(void)
+ 
+ int mmc_get_env_dev(void)
+ {
+-	return mmc_get_boot_dev();
++	struct udevice *dev;
++	const char *mmcdev;
++
++	switch (mmc_get_boot_dev()) {
++	case 0:
++		mmcdev = "mmc@11230000";
++		break;
++	case 1:
++		mmcdev = "mmc@11240000";
++		break;
++	default:
++		return -1;
++	}
++
++	if (uclass_get_device_by_name(UCLASS_MMC, mmcdev, &dev))
++		return -1;
++
++	return dev_seq(dev);
+ }
+ #endif

package/boot/uboot-mediatek/patches/302-mt7623-generic-reset-button-ignore-env.patch

@@ -1,6 +1,6 @@
 --- a/board/mediatek/mt7623/mt7623_rfb.c
 +++ b/board/mediatek/mt7623/mt7623_rfb.c
-@@ -4,8 +4,17 @@
+@@ -4,9 +4,18 @@
   */
  
  #include <common.h>
@@ -9,6 +9,7 @@
 +#include <env.h>
 +#include <init.h>
  #include <mmc.h>
+ #include <part.h>
  #include <asm/global_data.h>
 +#include <linux/delay.h>
 +
@@ -18,8 +19,8 @@
  
  DECLARE_GLOBAL_DATA_PTR;
  
-@@ -41,3 +50,25 @@ int mmc_get_env_dev(void)
+@@ -60,3 +69,25 @@ int mmc_get_env_dev(void)
- 	return mmc_get_boot_dev();
+ 	return dev_seq(dev);
  }
  #endif
 +

package/boot/uboot-mediatek/patches/310-mt7988-select-rootdisk.patch

@@ -0,0 +1,67 @@
+--- a/board/mediatek/mt7988/mt7988_rfb.c
++++ b/board/mediatek/mt7988/mt7988_rfb.c
+@@ -11,7 +11,9 @@
+ #include <env.h>
+ #include <init.h>
+ #include <asm/global_data.h>
++#include <asm/io.h>
+ #include <linux/delay.h>
++#include <linux/libfdt.h>
+ 
+ #ifndef CONFIG_RESET_BUTTON_LABEL
+ #define CONFIG_RESET_BUTTON_LABEL "reset"
+@@ -44,3 +46,54 @@ int board_late_init(void)
+ 	env_relocate();
+ 	return 0;
+ }
++
++#define	MT7988_BOOT_NOR		0
++#define	MT7988_BOOT_SPIM_NAND	1
++#define	MT7988_BOOT_EMMC	2
++#define	MT7988_BOOT_SNFI_NAND	3
++
++int ft_system_setup(void *blob, struct bd_info *bd)
++{
++	const u32 *media_handle_p;
++	int chosen, len, ret;
++	const char *media;
++	u32 media_handle;
++
++	switch ((readl(0x1001f6f0) & 0xc00) >> 10) {
++	case MT7988_BOOT_NOR:
++		media = "rootdisk-nor";
++		break
++		;;
++	case MT7988_BOOT_SPIM_NAND:
++		media = "rootdisk-spim-nand";
++		break
++		;;
++	case MT7988_BOOT_EMMC:
++		media = "rootdisk-emmc";
++		break
++		;;
++	case MT7988_BOOT_SNFI_NAND:
++		media = "rootdisk-sd";
++		break
++		;;
++	}
++
++	chosen = fdt_path_offset(blob, "/chosen");
++	if (chosen <= 0)
++		return 0;
++
++	media_handle_p = fdt_getprop(blob, chosen, media, &len);
++	if (media_handle_p <= 0 || len != 4)
++		return 0;
++
++	media_handle = *media_handle_p;
++	ret = fdt_setprop(blob, chosen, "rootdisk", &media_handle, sizeof(media_handle));
++	if (ret) {
++		printf("cannot set media phandle %s as rootdisk /chosen node\n", media);
++		return ret;
++	}
++
++	printf("set /chosen/rootdisk to bootrom media: %s (phandle 0x%08x)\n", media, fdt32_to_cpu(media_handle));
++
++	return 0;
++}

package/boot/uboot-mediatek/patches/311-mt7986-select-roodisk.patch

@@ -0,0 +1,67 @@
+--- a/board/mediatek/mt7986/mt7986_rfb.c
++++ b/board/mediatek/mt7986/mt7986_rfb.c
+@@ -11,7 +11,9 @@
+ #include <env.h>
+ #include <init.h>
+ #include <asm/global_data.h>
++#include <asm/io.h>
+ #include <linux/delay.h>
++#include <linux/libfdt.h>
+ 
+ #ifndef CONFIG_RESET_BUTTON_LABEL
+ #define CONFIG_RESET_BUTTON_LABEL "reset"
+@@ -83,3 +85,54 @@ int board_nmbm_init(void)
+ 
+ 	return 0;
+ }
++
++#define	MT7986_BOOT_NOR		0
++#define	MT7986_BOOT_SPIM_NAND	1
++#define	MT7986_BOOT_EMMC	2
++#define	MT7986_BOOT_SNFI_NAND	3
++
++int ft_system_setup(void *blob, struct bd_info *bd)
++{
++	const u32 *media_handle_p;
++	int chosen, len, ret;
++	const char *media;
++	u32 media_handle;
++
++	switch ((readl(0x1001f6f0) & 0x300) >> 8) {
++	case MT7986_BOOT_NOR:
++		media = "rootdisk-nor";
++		break
++		;;
++	case MT7986_BOOT_SPIM_NAND:
++		media = "rootdisk-spim-nand";
++		break
++		;;
++	case MT7986_BOOT_EMMC:
++		media = "rootdisk-emmc";
++		break
++		;;
++	case MT7986_BOOT_SNFI_NAND:
++		media = "rootdisk-sd";
++		break
++		;;
++	}
++
++	chosen = fdt_path_offset(blob, "/chosen");
++	if (chosen <= 0)
++		return 0;
++
++	media_handle_p = fdt_getprop(blob, chosen, media, &len);
++	if (media_handle_p <= 0 || len != 4)
++		return 0;
++
++	media_handle = *media_handle_p;
++	ret = fdt_setprop(blob, chosen, "rootdisk", &media_handle, sizeof(media_handle));
++	if (ret) {
++		printf("cannot set media phandle %s as rootdisk /chosen node\n", media);
++		return ret;
++	}
++
++	printf("set /chosen/rootdisk to bootrom media: %s (phandle 0x%08x)\n", media, fdt32_to_cpu(media_handle));
++
++	return 0;
++}

package/boot/uboot-mediatek/patches/312-mt7622-select-rootdisk.patch

@@ -0,0 +1,141 @@
+--- a/board/mediatek/mt7622/mt7622_rfb.c
++++ b/board/mediatek/mt7622/mt7622_rfb.c
+@@ -11,7 +11,9 @@
+ #include <env.h>
+ #include <init.h>
+ #include <asm/global_data.h>
++#include <asm/io.h>
+ #include <linux/delay.h>
++#include <linux/libfdt.h>
+ 
+ #ifndef CONFIG_RESET_BUTTON_LABEL
+ #define CONFIG_RESET_BUTTON_LABEL "reset"
+@@ -22,10 +24,43 @@
+ #include <nmbm/nmbm.h>
+ #include <nmbm/nmbm-mtd.h>
+ 
++#define MT7622_TOPRGUSTRAP_PAR			0x10212060
++#define MT7622_BOOT_SEQ_MASK			0x18
++#define MT7622_BOOT_SEQ_SHIFT			3
++#define MT7622_BOOT_SEQ_NOR_EMMC_SDXC		0x0
++#define MT7622_BOOT_SEQ_SPI_NAND_EMMC_SDXC	0x1
++#define MT7622_BOOT_SEQ_NAND_EMMC_SDXC		0x2
++#define MT7622_BOOT_SEQ_SDXC_EMMC_NAND		0x3
++
++#define MT7622_GPIO_MODE0			0x10211300
++#define MT7622_GPIO_NAND_MODE_MASK		0x00f00000
++#define MT7622_GPIO_NAND_MODE_SHIFT		20
++#define MT7622_GPIO_NAND_MODE_EMMC		0x2
++#define MT7622_GPIO_RGMII_MODE_MASK		0x0000f000
++#define MT7622_GPIO_RGMII_MODE_SHIFT		12
++#define MT7622_GPIO_RGMII_MODE_SDCX		0x2
++#define MT7622_GPIO_SPI_MODE_MASK		0x00000f00
++#define MT7622_GPIO_SPI_MODE_SHIFT		8
++#define MT7622_GPIO_SPI_MODE_NAND		0x2
++
++#define MT7622_MSDC_INT				0x1124000C
++#define MT7622_MSDC_INT_BD_CS_ERR		0x200
++
+ DECLARE_GLOBAL_DATA_PTR;
+ 
++static int	gpio_mode0;
++static int	msdc_int;
++
+ int board_init(void)
+ {
++	/*
++	 * Save content of GPIO_MODE0 as left behind by the BootROM.
++	 * Also grab MSDC1 INT status to see if BootROM has been reading
++	 * from SD card.
++	 * Together this will allow to infer the device used for booting.
++	 */
++	gpio_mode0 = readl(MT7622_GPIO_MODE0);
++	msdc_int = readl(MT7622_MSDC_INT);
+ 	return 0;
+ }
+ 
+@@ -83,3 +118,84 @@ int board_nmbm_init(void)
+ 
+ 	return 0;
+ }
++
++int ft_system_setup(void *blob, struct bd_info *bd)
++{
++	bool pinctrl_set_mmc = false;
++	bool pinctrl_set_snfi = false;
++	bool pinctrl_set_emmc = false;
++	bool msdc_bd_cs_err = false;
++
++	const u32 *media_handle_p;
++	int chosen, len, ret;
++	const char *media;
++	u32 media_handle, strap;
++
++	if ((gpio_mode0 & MT7622_GPIO_RGMII_MODE_MASK) >>
++	    MT7622_GPIO_RGMII_MODE_SHIFT == MT7622_GPIO_RGMII_MODE_SDCX)
++		pinctrl_set_mmc = true;
++
++	if ((gpio_mode0 & MT7622_GPIO_SPI_MODE_MASK) >>
++	    MT7622_GPIO_SPI_MODE_SHIFT == MT7622_GPIO_SPI_MODE_NAND)
++		pinctrl_set_snfi = true;
++
++	if ((gpio_mode0 & MT7622_GPIO_NAND_MODE_MASK) >>
++	    MT7622_GPIO_NAND_MODE_SHIFT == MT7622_GPIO_NAND_MODE_EMMC)
++		pinctrl_set_emmc = true;
++
++	if (msdc_int & MT7622_MSDC_INT_BD_CS_ERR)
++		msdc_bd_cs_err = true;
++
++	strap = readl(MT7622_TOPRGUSTRAP_PAR);
++	strap &= MT7622_BOOT_SEQ_MASK;
++	strap >>= MT7622_BOOT_SEQ_SHIFT;
++	switch (strap) {
++	case MT7622_BOOT_SEQ_NOR_EMMC_SDXC:
++		if (!pinctrl_set_emmc)
++			media = "rootdisk-nor";
++		else if (pinctrl_set_mmc)
++			media = "rootdisk-emmc";
++		else
++			media = "rootdisk-sd";
++		break
++		;;
++	case MT7622_BOOT_SEQ_SPI_NAND_EMMC_SDXC:
++		if (pinctrl_set_snfi)
++			media = "rootdisk-snfi";
++		else if (pinctrl_set_emmc)
++			media = "rootdisk-emmc";
++		else
++			media = "rootdisk-sd";
++		break
++		;;
++	case MT7622_BOOT_SEQ_NAND_EMMC_SDXC:
++	case MT7622_BOOT_SEQ_SDXC_EMMC_NAND:
++		if (!pinctrl_set_emmc && pinctrl_set_mmc)
++			media = "rootdisk-nand";
++		else if (pinctrl_set_emmc)
++			media = "rootdisk-emmc";
++		else
++			media = "rootdisk-sd";
++		break
++		;;
++	}
++
++	chosen = fdt_path_offset(blob, "/chosen");
++	if (chosen <= 0)
++		return 0;
++
++	media_handle_p = fdt_getprop(blob, chosen, media, &len);
++	if (media_handle_p <= 0 || len != 4)
++		return 0;
++
++	media_handle = *media_handle_p;
++	ret = fdt_setprop(blob, chosen, "rootdisk", &media_handle, sizeof(media_handle));
++	if (ret) {
++		printf("cannot set media phandle %s as rootdisk /chosen node\n", media);
++		return ret;
++	}
++
++	printf("set /chosen/rootdisk to bootrom media: %s (phandle 0x%08x)\n", media, fdt32_to_cpu(media_handle));
++
++	return 0;
++}

package/boot/uboot-mediatek/patches/313-mt7623-select-rootdisk.patch

@@ -0,0 +1,46 @@
+--- a/board/mediatek/mt7623/mt7623_rfb.c
++++ b/board/mediatek/mt7623/mt7623_rfb.c
+@@ -91,3 +91,43 @@ int board_late_init(void)
+ 	env_relocate();
+ 	return 0;
+ }
++
++int ft_system_setup(void *blob, struct bd_info *bd)
++{
++	const u32 *media_handle_p;
++	int chosen, len, ret;
++	const char *media;
++	u32 media_handle;
++
++#ifdef CONFIG_MMC
++	switch (mmc_get_boot_dev()) {
++	case 0:
++		media = "rootdisk-emmc";
++		break
++		;;
++	case 1:
++		media = "rootdisk-sd";
++		break
++		;;
++	}
++
++	chosen = fdt_path_offset(blob, "/chosen");
++	if (chosen <= 0)
++		return 0;
++
++	media_handle_p = fdt_getprop(blob, chosen, media, &len);
++	if (media_handle_p <= 0 || len != 4)
++		return 0;
++
++	media_handle = *media_handle_p;
++	ret = fdt_setprop(blob, chosen, "rootdisk", &media_handle, sizeof(media_handle));
++	if (ret) {
++		printf("cannot set media phandle %s as rootdisk /chosen node\n", media);
++		return ret;
++	}
++
++	printf("set /chosen/rootdisk to bootrom media: %s (phandle 0x%08x)\n", media, fdt32_to_cpu(media_handle));
++#endif
++
++	return 0;
++}

package/boot/uboot-mediatek/patches/400-update-bpir2-defconfig.patch

@@ -1,6 +1,6 @@
 --- a/configs/mt7623n_bpir2_defconfig
 +++ b/configs/mt7623n_bpir2_defconfig
-@@ -7,35 +7,105 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000
+@@ -7,34 +7,106 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000
  CONFIG_NR_DRAM_BANKS=1
  CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
  CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81ffff10
@@ -8,19 +8,17 @@
 +CONFIG_ENV_SIZE=0x10000
  CONFIG_ENV_OFFSET=0x100000
  CONFIG_DEFAULT_DEVICE_TREE="mt7623n-bananapi-bpi-r2"
--CONFIG_SYS_PROMPT="U-Boot> "
-+CONFIG_USE_DEFAULT_ENV_FILE=y
-+CONFIG_SYS_PROMPT="MT7623> "
  CONFIG_TARGET_MT7623=y
  CONFIG_SYS_LOAD_ADDR=0x84000000
  CONFIG_FIT=y
--CONFIG_FIT_VERBOSE=y
+ CONFIG_FIT_VERBOSE=y
 +CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
 +CONFIG_LED=y
 +CONFIG_LED_BLINK=y
 +CONFIG_LED_GPIO=y
 +CONFIG_LOGLEVEL=7
 +CONFIG_LOG=y
++CONFIG_OF_SYSTEM_SETUP=y
 +CONFIG_AUTOBOOT_KEYED=y
 +CONFIG_AUTOBOOT_MENU_SHOW=y
 +CONFIG_BOARD_LATE_INIT=y
@@ -38,6 +36,9 @@
 +CONFIG_CFB_CONSOLE_ANSI=y
 +CONFIG_CMD_ENV_FLAGS=y
  # CONFIG_DISPLAY_BOARDINFO is not set
+-CONFIG_SYS_PROMPT="U-Boot> "
++CONFIG_USE_DEFAULT_ENV_FILE=y
++CONFIG_SYS_PROMPT="MT7623> "
  CONFIG_SYS_MAXARGS=8
  CONFIG_SYS_PBSIZE=1049
  CONFIG_SYS_BOOTM_LEN=0x4000000
@@ -70,7 +71,6 @@
  CONFIG_CMD_MMC=y
  CONFIG_CMD_READ=y
 -# CONFIG_CMD_SETEXPR is not set
- # CONFIG_CMD_NFS is not set
 +CONFIG_CMD_SF_TEST=y
 +CONFIG_CMD_PING=y
 +CONFIG_CMD_PXE=y
@@ -111,7 +111,7 @@
  CONFIG_USE_IPADDR=y
  CONFIG_IPADDR="192.168.1.1"
  CONFIG_USE_SERVERIP=y
-@@ -47,6 +117,12 @@ CONFIG_CLK=y
+@@ -46,6 +118,12 @@ CONFIG_CLK=y
  CONFIG_SUPPORT_EMMC_BOOT=y
  CONFIG_MMC_HS400_SUPPORT=y
  CONFIG_MMC_MTK=y
@@ -124,7 +124,7 @@
  CONFIG_PHY_FIXED=y
  CONFIG_MEDIATEK_ETH=y
  CONFIG_PINCTRL=y
-@@ -56,10 +132,13 @@ CONFIG_POWER_DOMAIN=y
+@@ -55,10 +133,13 @@ CONFIG_POWER_DOMAIN=y
  CONFIG_MTK_POWER_DOMAIN=y
  CONFIG_DM_SERIAL=y
  CONFIG_MTK_SERIAL=y
@@ -140,7 +140,7 @@
  # CONFIG_EFI_GRUB_ARM32_WORKAROUND is not set
 --- /dev/null
 +++ b/bananapi_bpi-r2_env
-@@ -0,0 +1,70 @@
+@@ -0,0 +1,69 @@
 +ipaddr=192.168.1.1
 +serverip=192.168.1.254
 +loadaddr=0x88000000
@@ -193,14 +193,13 @@
 +sdmmc_write_recovery=iminfo $fileaddr && mmc dev 1 && part start mmc 1 $part_recovery part_addr && part size mmc 1 $part_recovery part_size && run mmc_write_vol
 +_checkbootedfrom=setenv _checkbootedfrom ; if itest.l *81dffff0 == 434d4d65 ; then setenv bootedfrom eMMC ; else setenv bootedfrom SD ; fi
 +_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv
-+_firstboot=setenv _firstboot ; led $bootled_pwr off ;led $bootled_rec on ; run _checkbootedfrom _switch_to_menu _update_bootdev _update_bootcmd _update_bootcmd2 _init_env boot_first
++_firstboot=setenv _firstboot ; led $bootled_pwr off ;led $bootled_rec on ; run _checkbootedfrom _switch_to_menu _update_bootcmd _update_bootcmd2 _init_env boot_first
 +_set_bootcmd_sdmmc=setenv boot_production "led $bootled_rec off ; led $bootled_pwr on ; run sdmmc_read_production && bootm $loadaddr ; led $bootled_pwr off"
 +_set_bootcmd_emmc=setenv boot_production "led $bootled_rec off ; led $bootled_pwr on ; run emmc_read_production && bootm $loadaddr ; led $bootled_pwr off"
 +_update_bootcmd=setenv _update_bootcmd ; if test "$bootedfrom" = "SD" ; then run _set_bootcmd_sdmmc ; else run _set_bootcmd_emmc ; fi ; setenv _set_bootcmd_sdmmc ; setenv _set_bootcmd_emmc
 +_set_bootcmd2_sdmmc=setenv boot_recovery "led $bootled_pwr off ; led $bootled_rec on ; run sdmmc_read_recovery && bootm $loadaddr ; led $bootled_rec off"
 +_set_bootcmd2_emmc=setenv boot_recovery "led $bootled_pwr off ; led $bootled_rec on ; run emmc_read_recovery && bootm $loadaddr ; led $bootled_rec off"
 +_update_bootcmd2=setenv _update_bootcmd2 ; if test "$bootedfrom" = "SD" ; then run _set_bootcmd2_sdmmc ; else run _set_bootcmd2_emmc ; fi ; setenv _set_bootcmd2_sdmmc ; setenv _set_bootcmd2_emmc
-+_update_bootdev=setenv _update_bootdev ; if test "$bootedfrom" = "SD" ; then setenv bootargs "$console root=/dev/mmcblk1p65" ; else setenv bootargs "$console root=/dev/mmcblk0p65" ; fi
 +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
 +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title  [$bootedfrom]    $ver" ; run _set_bm2
 +_set_bm2=setenv _set_bm2 ; setenv bootmenu_2 "Boot production system from $bootedfrom.=run boot_production ; run bootmenu_confirm_return" ; run _set_bm3

package/boot/uboot-mediatek/patches/401-update-u7623-defconfig.patch

@@ -1,6 +1,6 @@
 --- a/configs/mt7623a_unielec_u7623_02_defconfig
 +++ b/configs/mt7623a_unielec_u7623_02_defconfig
-@@ -7,34 +7,110 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000
+@@ -7,33 +7,109 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000
  CONFIG_NR_DRAM_BANKS=1
  CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
  CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81ffff10
@@ -8,13 +8,10 @@
 +CONFIG_ENV_SIZE=0x10000
  CONFIG_ENV_OFFSET=0x100000
  CONFIG_DEFAULT_DEVICE_TREE="mt7623a-unielec-u7623-02-emmc"
--CONFIG_SYS_PROMPT="U-Boot> "
-+CONFIG_USE_DEFAULT_ENV_FILE=y
-+CONFIG_SYS_PROMPT="MT7623> "
  CONFIG_TARGET_MT7623=y
  CONFIG_SYS_LOAD_ADDR=0x84000000
  CONFIG_FIT=y
--CONFIG_FIT_VERBOSE=y
+ CONFIG_FIT_VERBOSE=y
 +CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
 +CONFIG_LED=y
 +CONFIG_LED_BLINK=y
@@ -38,6 +35,9 @@
 +CONFIG_CFB_CONSOLE_ANSI=y
 +CONFIG_CMD_ENV_FLAGS=y
  # CONFIG_DISPLAY_BOARDINFO is not set
+-CONFIG_SYS_PROMPT="U-Boot> "
++CONFIG_USE_DEFAULT_ENV_FILE=y
++CONFIG_SYS_PROMPT="MT7623> "
  CONFIG_SYS_MAXARGS=8
  CONFIG_SYS_PBSIZE=1049
  CONFIG_SYS_BOOTM_LEN=0x4000000
@@ -71,7 +71,6 @@
  CONFIG_CMD_MMC=y
  CONFIG_CMD_READ=y
 -# CONFIG_CMD_SETEXPR is not set
- # CONFIG_CMD_NFS is not set
 +CONFIG_CMD_SF_TEST=y
 +CONFIG_CMD_PING=y
 +CONFIG_CMD_PXE=y
@@ -110,13 +109,12 @@
  CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 +CONFIG_SYS_MMC_ENV_DEV=0
 +CONFIG_ENV_OVERWRITE=y
-+CONFIG_ENV_IS_IN_MMC=y
  CONFIG_NET_RANDOM_ETHADDR=y
 +CONFIG_NETCONSOLE=y
  CONFIG_USE_IPADDR=y
  CONFIG_IPADDR="192.168.1.1"
  CONFIG_USE_SERVERIP=y
-@@ -46,6 +122,11 @@ CONFIG_CLK=y
+@@ -45,6 +121,11 @@ CONFIG_CLK=y
  CONFIG_SUPPORT_EMMC_BOOT=y
  CONFIG_MMC_HS400_SUPPORT=y
  CONFIG_MMC_MTK=y
@@ -128,7 +126,7 @@
  CONFIG_PHY_FIXED=y
  CONFIG_MEDIATEK_ETH=y
  CONFIG_PINCTRL=y
-@@ -55,9 +136,12 @@ CONFIG_POWER_DOMAIN=y
+@@ -54,9 +135,12 @@ CONFIG_POWER_DOMAIN=y
  CONFIG_MTK_POWER_DOMAIN=y
  CONFIG_DM_SERIAL=y
  CONFIG_MTK_SERIAL=y