mediatek: filogic: set correct PWM clock and clean thermal zone

* set correct clocks for PWM to work.
 * MT7986 PWM does have the 26MHz-clock-select, set that in patch
 * drop useless 'passive' trip point in thermal zone
 * extend pwm-fan to have 3 active operating points
 * set reasonable trip points in thermal zone
 * invert pwm-fan operating points and set shorter period to allow
   less noisy operation of the PWM fan of the BPi-R3.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
This commit is contained in:
Daniel Golle 2022-10-09 16:34:35 +01:00
parent 629f2de1a7
commit 88eae0f036
No known key found for this signature in database
GPG key ID: 5A8F39C31C3217CA
3 changed files with 19 additions and 19 deletions

View file

@ -447,7 +447,8 @@
}; };
&fan { &fan {
pwms = <&pwm 0 500000 0>; pwms = <&pwm 0 10000 0>;
cooling-levels = <255 96 52 0>;
status = "okay"; status = "okay";
}; };

View file

@ -206,8 +206,8 @@
#clock-cells = <1>; #clock-cells = <1>;
#pwm-cells = <2>; #pwm-cells = <2>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CLK_TOP_PWM_SEL>, clocks = <&infracfg CLK_INFRA_PWM_HCK>,
<&infracfg CLK_INFRA_PWM_BSEL>, <&infracfg CLK_INFRA_PWM_STA>,
<&infracfg CLK_INFRA_PWM1_CK>, <&infracfg CLK_INFRA_PWM1_CK>,
<&infracfg CLK_INFRA_PWM2_CK>; <&infracfg CLK_INFRA_PWM2_CK>;
clock-names = "top", "main", "pwm1", "pwm2"; clock-names = "top", "main", "pwm1", "pwm2";
@ -664,8 +664,8 @@
fan: pwm-fan { fan: pwm-fan {
compatible = "pwm-fan"; compatible = "pwm-fan";
/* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */ /* cooling level (0, 1, 2, 3) : (0% duty, 33% duty, 66% duty, 100% duty) */
cooling-levels = <0 128 255>; cooling-levels = <0 86 172 255>;
#cooling-cells = <2>; #cooling-cells = <2>;
status = "disabled"; status = "disabled";
}; };
@ -694,14 +694,14 @@
type = "active"; type = "active";
}; };
cpu_trip_active_low: active-low { cpu_trip_active_med: active-med {
temperature = <85000>; temperature = <85000>;
hysteresis = <2000>; hysteresis = <2000>;
type = "active"; type = "active";
}; };
cpu_trip_passive: passive { cpu_trip_active_low: active-low {
temperature = <40000>; temperature = <60000>;
hysteresis = <2000>; hysteresis = <2000>;
type = "passive"; type = "passive";
}; };
@ -709,24 +709,23 @@
cooling-maps { cooling-maps {
cpu-active-high { cpu-active-high {
/* active: set fan to cooling level 2 */ /* active: set fan to cooling level 3 */
cooling-device = <&fan 2 2>; cooling-device = <&fan 3 3>;
trip = <&cpu_trip_active_high>; trip = <&cpu_trip_active_high>;
}; };
cpu-active-med {
/* active: set fan to cooling level 2 */
cooling-device = <&fan 2 2>;
trip = <&cpu_trip_active_med>;
};
cpu-active-low { cpu-active-low {
/* active: set fan to cooling level 1 */ /* passive: set fan to cooling level 1 */
cooling-device = <&fan 1 1>; cooling-device = <&fan 1 1>;
trip = <&cpu_trip_active_low>; trip = <&cpu_trip_active_low>;
}; };
};
cpu-passive {
/* passive: set fan to cooling level 0 */
cooling-device = <&fan 0 0>;
trip = <&cpu_trip_passive>;
};
};
}; };
}; };
}; };

View file

@ -7,7 +7,7 @@
+static const struct pwm_mediatek_of_data mt7986_pwm_data = { +static const struct pwm_mediatek_of_data mt7986_pwm_data = {
+ .num_pwms = 2, + .num_pwms = 2,
+ .pwm45_fixup = false, + .pwm45_fixup = false,
+ .has_ck_26m_sel = false, + .has_ck_26m_sel = true,
+}; +};
+ +
static const struct pwm_mediatek_of_data mt8516_pwm_data = { static const struct pwm_mediatek_of_data mt8516_pwm_data = {