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Revert "ramips: pci: sync with staging driver"

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This reverts commit e07baec9fa.

Signed-off-by: John Crispin <john@phrozen.org>
This commit is contained in:
John Crispin 2018-06-01 11:41:08 +02:00
parent 8a570921b5
commit 784943e3f2
1 changed files with 157 additions and 139 deletions
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50
target/linux/ramips/files-4.14/arch/mips/pci/pci-mt7621.c
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@ -52,10 +52,14 @@
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/of.h> #include <linux/of.h>
#include <linux/of_pci.h> #include <linux/of_pci.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <ralink_regs.h> #include <ralink_regs.h>
extern void pcie_phy_init(void);
extern void chk_phy_pll(void);
/* /*
* These functions and structures provide the BIOS scan and mapping of the PCI * These functions and structures provide the BIOS scan and mapping of the PCI
* devices. * devices.
@ -113,6 +117,7 @@
#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000) #define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
#define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000) #define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000)
#define MV_WRITE(ofs, data) \ #define MV_WRITE(ofs, data) \
*(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data) *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
#define MV_READ(ofs, data) \ #define MV_READ(ofs, data) \
@ -130,20 +135,20 @@
#define MV_READ_8(ofs, data) \ #define MV_READ_8(ofs, data) \
*(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
#define RALINK_PCI_MM_MAP_BASE 0x60000000 #define RALINK_PCI_MM_MAP_BASE 0x60000000
#define RALINK_PCI_IO_MAP_BASE 0x1e160000 #define RALINK_PCI_IO_MAP_BASE 0x1e160000
#define RALINK_SYSTEM_CONTROL_BASE 0xbe000000 #define RALINK_SYSTEM_CONTROL_BASE 0xbe000000
#define ASSERT_SYSRST_PCIE(val) \ #define ASSERT_SYSRST_PCIE(val) do { \
do { \
if (*(unsigned int *)(0xbe00000c) == 0x00030101) \ if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
RALINK_RSTCTRL |= val; \ RALINK_RSTCTRL |= val; \
else \ else \
RALINK_RSTCTRL &= ~val; \ RALINK_RSTCTRL &= ~val; \
} while(0) } while(0)
#define DEASSERT_SYSRST_PCIE(val) \ #define DEASSERT_SYSRST_PCIE(val) do { \
do { \
if (*(unsigned int *)(0xbe00000c) == 0x00030101) \ if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
RALINK_RSTCTRL &= ~val; \ RALINK_RSTCTRL &= ~val; \
else \ else \
@ -183,6 +188,8 @@ static int pcie_link_status = 0;
#define PCI_ACCESS_WRITE_2 4 #define PCI_ACCESS_WRITE_2 4
#define PCI_ACCESS_WRITE_4 5 #define PCI_ACCESS_WRITE_4 5
static int pcie_irq[3];
static int config_access(unsigned char access_type, struct pci_bus *bus, static int config_access(unsigned char access_type, struct pci_bus *bus,
unsigned int devfn, unsigned int where, u32 * data) unsigned int devfn, unsigned int where, u32 * data)
{ {
@ -268,6 +275,7 @@ write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
return PCIBIOS_SUCCESSFUL; return PCIBIOS_SUCCESSFUL;
} }
static int static int
pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val) pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
{ {
@ -301,6 +309,7 @@ struct pci_ops mt7621_pci_ops= {
static struct resource mt7621_res_pci_mem1; static struct resource mt7621_res_pci_mem1;
static struct resource mt7621_res_pci_io1; static struct resource mt7621_res_pci_io1;
static struct pci_controller mt7621_controller = { static struct pci_controller mt7621_controller = {
.pci_ops = &mt7621_pci_ops, .pci_ops = &mt7621_pci_ops,
.mem_resource = &mt7621_res_pci_mem1, .mem_resource = &mt7621_res_pci_mem1,
@ -333,6 +342,7 @@ write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned
return; return;
} }
int int
pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{ {
@ -361,8 +371,11 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
void void
set_pcie_phy(u32 *addr, int start_b, int bits, int val) set_pcie_phy(u32 *addr, int start_b, int bits, int val)
{ {
// printk("0x%p:", addr);
// printk(" %x", *addr);
*(unsigned int *)(addr) &= ~(((1<<bits) - 1)<<start_b); *(unsigned int *)(addr) &= ~(((1<<bits) - 1)<<start_b);
*(unsigned int *)(addr) |= val << start_b; *(unsigned int *)(addr) |= val << start_b;
// printk(" -> %x\n", *addr);
} }
void void
@ -465,21 +478,25 @@ void setup_cm_memory_region(struct resource *mem_resource)
resource_size_t mask; resource_size_t mask;
if (mips_cps_numiocu(0)) { if (mips_cps_numiocu(0)) {
/* FIXME: hardware doesn't accept mask values with 1s after /* FIXME: hardware doesn't accept mask values with 1s after
* 0s (e.g. 0xffef), so it would be great to warn if that's 0s (e.g. 0xffef), so it would be great to warn if that's
* about to happen */ about to happen */
mask = ~(mem_resource->end - mem_resource->start); mask = ~(mem_resource->end - mem_resource->start);
write_gcr_reg1_base(mem_resource->start); write_gcr_reg1_base(mem_resource->start);
write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0); write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
printk("PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n", printk("PCI coherence region base: 0x%08lx, mask/settings: 0x%08lx\n",
(unsigned long long)read_gcr_reg1_base(), read_gcr_reg1_base(),
(unsigned long long)read_gcr_reg1_mask()); read_gcr_reg1_mask());
} }
} }
static int mt7621_pci_probe(struct platform_device *pdev) static int mt7621_pci_probe(struct platform_device *pdev)
{ {
unsigned long val = 0; unsigned long val = 0;
int i;
for (i = 0; i < 3; i++)
pcie_irq[i] = irq_of_parse_and_map(pdev->dev.of_node, i);
iomem_resource.start = 0; iomem_resource.start = 0;
iomem_resource.end= ~0; iomem_resource.end= ~0;
@ -491,6 +508,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
val |= RALINK_PCIE2_RST; val |= RALINK_PCIE2_RST;
ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST); ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
printk("pull PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
*(unsigned int *)(0xbe000060) &= ~(0x3<<10 | 0x3<<3); *(unsigned int *)(0xbe000060) &= ~(0x3<<10 | 0x3<<3);
*(unsigned int *)(0xbe000060) |= 0x1<<10 | 0x1<<3; *(unsigned int *)(0xbe000060) |= 0x1<<10 | 0x1<<3;
@ -506,17 +524,17 @@ static int mt7621_pci_probe(struct platform_device *pdev)
val |= RALINK_PCIE2_RST; val |= RALINK_PCIE2_RST;
DEASSERT_SYSRST_PCIE(val); DEASSERT_SYSRST_PCIE(val);
printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
if ((*(unsigned int *)(0xbe00000c)&0xFFFF) == 0x0101) // MT7621 E2 if ((*(unsigned int *)(0xbe00000c)&0xFFFF) == 0x0101) // MT7621 E2
bypass_pipe_rst(); bypass_pipe_rst();
set_phy_for_ssc(); set_phy_for_ssc();
printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
read_config(0, 0, 0, 0x70c, &val); read_config(0, 0, 0, 0x70c, &val);
printk("Port 0 N_FTS = %x\n", (unsigned int)val); printk("Port 0 N_FTS = %x\n", (unsigned int)val);
read_config(0, 1, 0, 0x70c, &val); read_config(0, 1, 0, 0x70c, &val);
printk("Port 1 N_FTS = %x\n", (unsigned int)val); printk("Port 1 N_FTS = %x\n", (unsigned int)val);
read_config(0, 2, 0, 0x70c, &val); read_config(0, 2, 0, 0x70c, &val);
printk("Port 2 N_FTS = %x\n", (unsigned int)val); printk("Port 2 N_FTS = %x\n", (unsigned int)val);
@ -544,7 +562,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
pcie_link_status |= 1<<0; pcie_link_status |= 1<<0;
RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
} }
if(( RALINK_PCI1_STATUS & 0x1) == 0) if(( RALINK_PCI1_STATUS & 0x1) == 0)
{ {
printk("PCIE1 no card, disable it(RST&CLK)\n"); printk("PCIE1 no card, disable it(RST&CLK)\n");
@ -555,7 +572,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
pcie_link_status |= 1<<1; pcie_link_status |= 1<<1;
RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
} }
if (( RALINK_PCI2_STATUS & 0x1) == 0) { if (( RALINK_PCI2_STATUS & 0x1) == 0) {
printk("PCIE2 no card, disable it(RST&CLK)\n"); printk("PCIE2 no card, disable it(RST&CLK)\n");
ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST); ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
@ -565,7 +581,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
pcie_link_status |= 1<<2; pcie_link_status |= 1<<2;
RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt
} }
if (pcie_link_status == 0) if (pcie_link_status == 0)
return 0; return 0;
@ -605,6 +620,8 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
RALINK_PCI_PCICFG_ADDR |= 0x1 << 24; //port2 RALINK_PCI_PCICFG_ADDR |= 0x1 << 24; //port2
break; break;
} }
printk(" -> %x\n", RALINK_PCI_PCICFG_ADDR);
//printk(" RALINK_PCI_ARBCTL = %x\n", RALINK_PCI_ARBCTL);
/* /*
ioport_resource.start = mt7621_res_pci_io1.start; ioport_resource.start = mt7621_res_pci_io1.start;
@ -621,7 +638,6 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
RALINK_PCI0_CLASS = 0x06040001; RALINK_PCI0_CLASS = 0x06040001;
printk("PCIE0 enabled\n"); printk("PCIE0 enabled\n");
} }
//PCIe1 //PCIe1
if ((pcie_link_status & 0x2) != 0) { if ((pcie_link_status & 0x2) != 0) {
RALINK_PCI1_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE RALINK_PCI1_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
@ -629,7 +645,6 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
RALINK_PCI1_CLASS = 0x06040001; RALINK_PCI1_CLASS = 0x06040001;
printk("PCIE1 enabled\n"); printk("PCIE1 enabled\n");
} }
//PCIe2 //PCIe2
if ((pcie_link_status & 0x4) != 0) { if ((pcie_link_status & 0x4) != 0) {
RALINK_PCI2_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE RALINK_PCI2_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
@ -642,6 +657,7 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
case 7: case 7:
read_config(0, 2, 0, 0x4, &val); read_config(0, 2, 0, 0x4, &val);
write_config(0, 2, 0, 0x4, val|0x4); write_config(0, 2, 0, 0x4, val|0x4);
// write_config(0, 1, 0, 0x4, val|0x7);
read_config(0, 2, 0, 0x70c, &val); read_config(0, 2, 0, 0x70c, &val);
val &= ~(0xff)<<8; val &= ~(0xff)<<8;
val |= 0x50<<8; val |= 0x50<<8;
@ -651,6 +667,7 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
case 6: case 6:
read_config(0, 1, 0, 0x4, &val); read_config(0, 1, 0, 0x4, &val);
write_config(0, 1, 0, 0x4, val|0x4); write_config(0, 1, 0, 0x4, val|0x4);
// write_config(0, 1, 0, 0x4, val|0x7);
read_config(0, 1, 0, 0x70c, &val); read_config(0, 1, 0, 0x70c, &val);
val &= ~(0xff)<<8; val &= ~(0xff)<<8;
val |= 0x50<<8; val |= 0x50<<8;
@ -658,6 +675,7 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
default: default:
read_config(0, 0, 0, 0x4, &val); read_config(0, 0, 0, 0x4, &val);
write_config(0, 0, 0, 0x4, val|0x4); //bus master enable write_config(0, 0, 0, 0x4, val|0x4); //bus master enable
// write_config(0, 0, 0, 0x4, val|0x7); //bus master enable
read_config(0, 0, 0, 0x70c, &val); read_config(0, 0, 0, 0x70c, &val);
val &= ~(0xff)<<8; val &= ~(0xff)<<8;
val |= 0x50<<8; val |= 0x50<<8;