From fc33c41c21362b7186aa051a2140623943fa3143 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Wed, 19 Oct 2022 14:43:00 +0300 Subject: [PATCH 01/51] ramips: do not use GPIO function on switch pins on certain devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The pins of the MT7530 switch that translate to GPIO 0, 3, 6, 9 and 12 has got a function, by default, which does the same thing as the netdev trigger. Because of bridge offloading on DSA, the netdev trigger won't see the frames between the switch ports whilst the default function will. Do not use the GPIO function on switch pins on devices that fall under this category. Keep it for: mt7621_belkin_rt1800.dts: There's only one LED which is for the wan interface and there's no bridge offloading between the "wan" interface and other interfaces. mt7621_yuncore_ax820.dts: There's no bridge offloading between the "wan" and "lan" interfaces. Signed-off-by: Arınç ÜNAL --- .../linux/ramips/dts/mt7621_linksys_e7350.dts | 37 ------------------- .../ramips/dts/mt7621_netgear_wax202.dts | 18 --------- .../ramips/dts/mt7621_zbtlink_zbt-wg1608.dtsi | 37 ------------------- .../mt7621/base-files/etc/board.d/01_leds | 17 --------- 4 files changed, 109 deletions(-) diff --git a/target/linux/ramips/dts/mt7621_linksys_e7350.dts b/target/linux/ramips/dts/mt7621_linksys_e7350.dts index d7b8c214b9b..ea8a6841488 100644 --- a/target/linux/ramips/dts/mt7621_linksys_e7350.dts +++ b/target/linux/ramips/dts/mt7621_linksys_e7350.dts @@ -57,40 +57,6 @@ function = LED_FUNCTION_WAN; gpios = <&gpio 15 GPIO_ACTIVE_LOW>; }; - - led-wan2 { - color = ; - function = LED_FUNCTION_WAN; - gpios = <&switch0 0 GPIO_ACTIVE_LOW>; - }; - - led-lan4 { - color = ; - function = LED_FUNCTION_LAN; - function-enumerator = <4>; - gpios = <&switch0 3 GPIO_ACTIVE_LOW>; - }; - - led-lan3 { - color = ; - function = LED_FUNCTION_LAN; - function-enumerator = <3>; - gpios = <&switch0 6 GPIO_ACTIVE_LOW>; - }; - - led-lan2 { - color = ; - function = LED_FUNCTION_LAN; - function-enumerator = <2>; - gpios = <&switch0 9 GPIO_ACTIVE_HIGH>; - }; - - led-lan1 { - color = ; - function = LED_FUNCTION_LAN; - function-enumerator = <1>; - gpios = <&switch0 12 GPIO_ACTIVE_LOW>; - }; }; }; @@ -185,9 +151,6 @@ }; &switch0 { - gpio-controller; - #gpio-cells = <2>; - ports { port@1 { status = "okay"; diff --git a/target/linux/ramips/dts/mt7621_netgear_wax202.dts b/target/linux/ramips/dts/mt7621_netgear_wax202.dts index f17a8053630..02f540d7431 100644 --- a/target/linux/ramips/dts/mt7621_netgear_wax202.dts +++ b/target/linux/ramips/dts/mt7621_netgear_wax202.dts @@ -53,31 +53,16 @@ gpios = <&gpio 16 GPIO_ACTIVE_LOW>; }; - led_lan1_green: lan1_green { - label = "green:lan1"; - gpios = <&switch0 3 GPIO_ACTIVE_LOW>; - }; - led_lan1_orange: lan1_orange { label = "orange:lan1"; gpios = <&gpio 15 GPIO_ACTIVE_LOW>; }; - led_lan2_green: lan2_green { - label = "green:lan2"; - gpios = <&switch0 6 GPIO_ACTIVE_LOW>; - }; - led_lan2_orange: lan2_orange { label = "orange:lan2"; gpios = <&gpio 13 GPIO_ACTIVE_LOW>; }; - led_lan3_green: lan3_green { - label = "green:lan3"; - gpios = <&switch0 12 GPIO_ACTIVE_LOW>; - }; - led_lan3_orange: lan3_orange { label = "orange:lan3"; gpios = <&gpio 14 GPIO_ACTIVE_LOW>; @@ -256,9 +241,6 @@ }; &switch0 { - gpio-controller; - #gpio-cells = <2>; - ports { port@1 { status = "okay"; diff --git a/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1608.dtsi b/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1608.dtsi index f19cb4db171..59fab90ed1d 100644 --- a/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1608.dtsi +++ b/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1608.dtsi @@ -51,40 +51,6 @@ gpios = <&gpio 14 GPIO_ACTIVE_LOW>; linux,default-trigger = "phy1tpt"; }; - - lan1 { - color = ; - function = LED_FUNCTION_LAN; - function-enumerator = <1>; - gpios = <&switch0 0 GPIO_ACTIVE_LOW>; - }; - - lan2 { - color = ; - function = LED_FUNCTION_LAN; - function-enumerator = <2>; - gpios = <&switch0 3 GPIO_ACTIVE_LOW>; - }; - - lan3 { - color = ; - function = LED_FUNCTION_LAN; - function-enumerator = <3>; - gpios = <&switch0 6 GPIO_ACTIVE_LOW>; - }; - - lan4 { - color = ; - function = LED_FUNCTION_LAN; - function-enumerator = <4>; - gpios = <&switch0 9 GPIO_ACTIVE_HIGH>; - }; - - wan { - color = ; - function = LED_FUNCTION_WAN; - gpios = <&switch0 12 GPIO_ACTIVE_LOW>; - }; }; }; @@ -186,9 +152,6 @@ }; &switch0 { - gpio-controller; - #gpio-cells = <2>; - ports { port@0 { status = "okay"; diff --git a/target/linux/ramips/mt7621/base-files/etc/board.d/01_leds b/target/linux/ramips/mt7621/base-files/etc/board.d/01_leds index 5fafb9b50a9..985eefb8604 100644 --- a/target/linux/ramips/mt7621/base-files/etc/board.d/01_leds +++ b/target/linux/ramips/mt7621/base-files/etc/board.d/01_leds @@ -94,13 +94,6 @@ keenetic,kn-3010) linksys,e5600) ucidef_set_led_netdev "wan" "wan link" "blue:wan" "wan" "link" ;; -linksys,e7350) - ucidef_set_led_netdev "lan1" "lan1" "blue:lan-1" "lan1" - ucidef_set_led_netdev "lan2" "lan2" "blue:lan-2" "lan2" - ucidef_set_led_netdev "lan3" "lan4" "blue:lan-3" "lan3" - ucidef_set_led_netdev "lan4" "lan4" "blue:lan-4" "lan4" - ucidef_set_led_netdev "wan" "wan" "blue:wan" "wan" - ;; linksys,ea6350-v4|\ linksys,ea7300-v1|\ linksys,ea7300-v2|\ @@ -149,9 +142,6 @@ netgear,r7450) ;; netgear,wax202) ucidef_set_led_netdev "internet" "Internet" "green:net" "wan" - ucidef_set_led_netdev "lan1" "LAN1" "green:lan1" "lan1" - ucidef_set_led_netdev "lan2" "LAN2" "green:lan2" "lan2" - ucidef_set_led_netdev "lan3" "LAN3" "green:lan3" "lan3" ;; oraybox,x3a) ucidef_set_led_netdev "wan" "wan link" "red:status" "wan" @@ -204,13 +194,6 @@ yuncore,ax820) ucidef_set_led_netdev "lan" "LAN" "green:lan" "lan" ucidef_set_led_netdev "wan" "WAN" "green:wan" "wan" ;; -zbtlink,zbt-wg1608-16m) - ucidef_set_led_netdev "lan1" "LAN1" "green:lan-1" "lan1" - ucidef_set_led_netdev "lan2" "LAN2" "green:lan-2" "lan2" - ucidef_set_led_netdev "lan3" "LAN3" "green:lan-3" "lan3" - ucidef_set_led_netdev "lan4" "LAN4" "green:lan-4" "lan4" - ucidef_set_led_netdev "wan" "WAN" "green:wan" "wan" - ;; zyxel,lte3301-plus) ucidef_set_led_netdev "internet" "internet" "white:internet" "wwan0" ;; From 89eb8b50d18d29dc0360d94b2daaf2bd4f0faa02 Mon Sep 17 00:00:00 2001 From: Daniel Groth Date: Fri, 14 Oct 2022 16:23:33 +0200 Subject: [PATCH 02/51] realtek: dgs-1210-10mp: add full sfp description Added the full SFP description for both SFP ports (lan9, 10) on D-Link DGS-1210-10MP, which enables hot-plug detection of SFP modules. Added the patch to both kernel 5.10 and 5.15 dts files. Signed-off-by: Daniel Groth --- .../rtl8380_d-link_dgs-1210-10mp-f.dts | 56 ++++++++++++++++++- .../rtl8380_d-link_dgs-1210-10mp-f.dts | 56 ++++++++++++++++++- 2 files changed, 108 insertions(+), 4 deletions(-) diff --git a/target/linux/realtek/dts-5.10/rtl8380_d-link_dgs-1210-10mp-f.dts b/target/linux/realtek/dts-5.10/rtl8380_d-link_dgs-1210-10mp-f.dts index e7db688ad52..39e37ee5959 100644 --- a/target/linux/realtek/dts-5.10/rtl8380_d-link_dgs-1210-10mp-f.dts +++ b/target/linux/realtek/dts-5.10/rtl8380_d-link_dgs-1210-10mp-f.dts @@ -8,6 +8,42 @@ compatible = "d-link,dgs-1210-10mp-f", "realtek,rtl8382-soc", "realtek,rtl838x-soc"; model = "D-Link DGS-1210-10MP F"; + + /* i2c for sfp port9 */ + i2c0: i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + sfp0: sfp-p9 { + compatible = "sff,sfp"; + i2c-bus = <&i2c0>; + los-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + tx-disable-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>; + }; + + /* i2c for sfp port10 */ + i2c1: i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + sfp1: sfp-p10 { + compatible = "sff,sfp"; + i2c-bus = <&i2c1>; + los-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + tx-disable-gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; }; &leds { @@ -72,8 +108,24 @@ SWITCH_PORT(13, 6, internal) SWITCH_PORT(14, 7, internal) SWITCH_PORT(15, 8, internal) - SWITCH_SFP_PORT(24, 9, rgmii-id) - SWITCH_SFP_PORT(26, 10, rgmii-id) + + port@24 { + reg = <24>; + label = "lan9"; + phy-handle = <14>; + phy-mode = "1000base-x"; + managed = "in-band-status"; + sfp = <&sfp0>; + }; + + port@26 { + reg = <26>; + label = "lan10"; + phy-handle = <15>; + phy-mode = "1000base-x"; + managed = "in-band-status"; + sfp = <&sfp1>; + }; port@28 { ethernet = <ðernet0>; diff --git a/target/linux/realtek/dts-5.15/rtl8380_d-link_dgs-1210-10mp-f.dts b/target/linux/realtek/dts-5.15/rtl8380_d-link_dgs-1210-10mp-f.dts index e7db688ad52..39e37ee5959 100644 --- a/target/linux/realtek/dts-5.15/rtl8380_d-link_dgs-1210-10mp-f.dts +++ b/target/linux/realtek/dts-5.15/rtl8380_d-link_dgs-1210-10mp-f.dts @@ -8,6 +8,42 @@ compatible = "d-link,dgs-1210-10mp-f", "realtek,rtl8382-soc", "realtek,rtl838x-soc"; model = "D-Link DGS-1210-10MP F"; + + /* i2c for sfp port9 */ + i2c0: i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + sfp0: sfp-p9 { + compatible = "sff,sfp"; + i2c-bus = <&i2c0>; + los-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + tx-disable-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>; + }; + + /* i2c for sfp port10 */ + i2c1: i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + sfp1: sfp-p10 { + compatible = "sff,sfp"; + i2c-bus = <&i2c1>; + los-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + tx-disable-gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; }; &leds { @@ -72,8 +108,24 @@ SWITCH_PORT(13, 6, internal) SWITCH_PORT(14, 7, internal) SWITCH_PORT(15, 8, internal) - SWITCH_SFP_PORT(24, 9, rgmii-id) - SWITCH_SFP_PORT(26, 10, rgmii-id) + + port@24 { + reg = <24>; + label = "lan9"; + phy-handle = <14>; + phy-mode = "1000base-x"; + managed = "in-band-status"; + sfp = <&sfp0>; + }; + + port@26 { + reg = <26>; + label = "lan10"; + phy-handle = <15>; + phy-mode = "1000base-x"; + managed = "in-band-status"; + sfp = <&sfp1>; + }; port@28 { ethernet = <ðernet0>; From 0627874594074737f6bd5d8effc5090e6d7fd1e6 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sun, 8 Jan 2023 14:55:44 +0100 Subject: [PATCH 03/51] kernel: Refresh kernel patches Make the patches apply cleanly again. Fixes: 8dfe69cdfc5c ("kernel: update nvmem subsystem to the latest upstream") Signed-off-by: Hauke Mehrtens --- .../008-5.17-watchdog-add-realtek-otto-watchdog-timer.patch | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/realtek/patches-5.15/008-5.17-watchdog-add-realtek-otto-watchdog-timer.patch b/target/linux/realtek/patches-5.15/008-5.17-watchdog-add-realtek-otto-watchdog-timer.patch index 78b050df185..794cdfa37a1 100644 --- a/target/linux/realtek/patches-5.15/008-5.17-watchdog-add-realtek-otto-watchdog-timer.patch +++ b/target/linux/realtek/patches-5.15/008-5.17-watchdog-add-realtek-otto-watchdog-timer.patch @@ -32,7 +32,7 @@ Signed-off-by: Guenter Roeck --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -15882,6 +15882,13 @@ S: Maintained +@@ -15890,6 +15890,13 @@ S: Maintained F: include/sound/rt*.h F: sound/soc/codecs/rt* From 111b183ca9eb6fb73d5ebf0d56ffbb12449a7b81 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sun, 8 Jan 2023 16:09:04 +0100 Subject: [PATCH 04/51] at91: Add CONFIG_NVMEM_MICROCHIP_OTPC kernel configuration option The kernel configuration option is now available on kernel 5.10 and 5.15, add it to the config for 5.15 too. Fixes: 8dfe69cdfc5c ("kernel: update nvmem subsystem to the latest upstream") Signed-off-by: Hauke Mehrtens --- target/linux/at91/sam9x/config-5.15 | 1 + target/linux/at91/sama5/config-5.15 | 1 + target/linux/at91/sama7/config-5.15 | 1 + 3 files changed, 3 insertions(+) diff --git a/target/linux/at91/sam9x/config-5.15 b/target/linux/at91/sam9x/config-5.15 index 3aa652c1888..ce7deb17a7c 100644 --- a/target/linux/at91/sam9x/config-5.15 +++ b/target/linux/at91/sam9x/config-5.15 @@ -200,6 +200,7 @@ CONFIG_NET_PTP_CLASSIFY=y CONFIG_NET_SELFTESTS=y CONFIG_NLS=y CONFIG_NVMEM=y +# CONFIG_NVMEM_MICROCHIP_OTPC is not set CONFIG_NVMEM_SYSFS=y CONFIG_OF=y CONFIG_OF_ADDRESS=y diff --git a/target/linux/at91/sama5/config-5.15 b/target/linux/at91/sama5/config-5.15 index e2fbc5ba7d7..4790e26dff5 100644 --- a/target/linux/at91/sama5/config-5.15 +++ b/target/linux/at91/sama5/config-5.15 @@ -305,6 +305,7 @@ CONFIG_NLS_UTF8=y CONFIG_NO_HZ_COMMON=y CONFIG_NO_HZ_IDLE=y CONFIG_NVMEM=y +# CONFIG_NVMEM_MICROCHIP_OTPC is not set CONFIG_NVMEM_SYSFS=y CONFIG_OF=y CONFIG_OF_ADDRESS=y diff --git a/target/linux/at91/sama7/config-5.15 b/target/linux/at91/sama7/config-5.15 index 4ff0d3df236..2cdf4cb4347 100644 --- a/target/linux/at91/sama7/config-5.15 +++ b/target/linux/at91/sama7/config-5.15 @@ -269,6 +269,7 @@ CONFIG_NLS_UTF8=y CONFIG_NO_HZ_COMMON=y CONFIG_NO_HZ_IDLE=y CONFIG_NVMEM=y +# CONFIG_NVMEM_MICROCHIP_OTPC is not set CONFIG_NVMEM_SYSFS=y CONFIG_OF=y CONFIG_OF_ADDRESS=y From ef3919bea962ad48f8d0634dd0d3a3ad6fb79238 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sun, 8 Jan 2023 18:51:27 +0100 Subject: [PATCH 05/51] layerscape: Add CONFIG_NVMEM_LAYERSCAPE_SFP kernel configuration option The kernel configuration option is now available on kernel 5.10 and 5.15, add it to the config for 5.15 too. Fixes: 8dfe69cdfc5c ("kernel: update nvmem subsystem to the latest upstream") Signed-off-by: Hauke Mehrtens --- target/linux/layerscape/armv8_64b/config-5.15 | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/layerscape/armv8_64b/config-5.15 b/target/linux/layerscape/armv8_64b/config-5.15 index e959d4393bc..73815b174de 100644 --- a/target/linux/layerscape/armv8_64b/config-5.15 +++ b/target/linux/layerscape/armv8_64b/config-5.15 @@ -544,6 +544,7 @@ CONFIG_NUMA=y CONFIG_NUMA_BALANCING=y CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y CONFIG_NVMEM=y +# CONFIG_NVMEM_LAYERSCAPE_SFP is not set # CONFIG_NVMEM_SPMI_SDAM is not set CONFIG_NVMEM_SYSFS=y CONFIG_OF=y From 2748c45d468b6208f70972adc7ae2e532b2c3015 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Mon, 19 Dec 2022 01:07:38 +0100 Subject: [PATCH 06/51] elfutils: Ignore wrong use-after-free error GCC 12.2.0 shows this false positive error message: ```` In function 'bigger_buffer', inlined from '__libdw_gunzip' at gzip.c:374:12: gzip.c:96:9: error: pointer may be used after 'realloc' [-Werror=use-after-free] 96 | b = realloc (state->buffer, more -= 1024); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ gzip.c:94:13: note: call to 'realloc' here 94 | char *b = realloc (state->buffer, more); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ cc1: all warnings being treated as errors ```` GCC bug report: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104069 Signed-off-by: Hauke Mehrtens --- package/libs/elfutils/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/package/libs/elfutils/Makefile b/package/libs/elfutils/Makefile index d4e5d994e8c..1e41e296b3a 100644 --- a/package/libs/elfutils/Makefile +++ b/package/libs/elfutils/Makefile @@ -81,7 +81,7 @@ HOST_CONFIGURE_VARS += \ CONFIGURE_VARS += \ ac_cv_search__obstack_free=yes -TARGET_CFLAGS += -D_GNU_SOURCE -Wno-unused-result -Wno-format-nonliteral +TARGET_CFLAGS += -D_GNU_SOURCE -Wno-unused-result -Wno-format-nonliteral -Wno-error=use-after-free define Build/InstallDev $(INSTALL_DIR) $(1)/usr/include From dc12c76dc52028b24cddba6a32141f9dbff64d0f Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Mon, 19 Dec 2022 01:19:32 +0100 Subject: [PATCH 07/51] uqmi: Ignore wrong maybe-uninitialized and dangling-pointer error GCC 12.2.0 shows this false positive error message: ```` uqmi-2022-05-04-56cb2d40/dev.c: In function 'qmi_request_wait': uqmi-2022-05-04-56cb2d40/dev.c:217:23: error: storing the address of local variable 'complete' in '*req.complete' [-Werror=dangling-pointer=] 217 | req->complete = &complete; | ~~~~~~~~~~~~~~^~~~~~~~~~~ uqmi-2022-05-04-56cb2d40/dev.c:208:14: note: 'complete' declared here 208 | bool complete = false; | ^~~~~~~~ uqmi-2022-05-04-56cb2d40/dev.c:208:14: note: 'req' declared here cc1: all warnings being treated as errors ```` and this one: ```` In file included from uqmi-2022-05-04-56cb2d40/commands.c:28: In function 'blobmsg_close_table', inlined from 'cmd_nas_get_cell_location_info_cb' at /home/haukeuqmi-2022-05-04-56cb2d40/commands-nas.c:897:4: /usr/include/libubox/blobmsg.h:256:9: error: 'c' may be used uninitialized [-Werror=maybe-uninitialized] 256 | blob_nest_end(buf, cookie); | ^~~~~~~~~~~~~~~~~~~~~~~~~~ In file included from uqmi-2022-05-04-56cb2d40/commands.c:169: uqmi-2022-05-04-56cb2d40/commands-nas.c: In function 'cmd_nas_get_cell_location_info_cb': uqmi-2022-05-04-56cb2d40/commands-nas.c:713:15: note: 'c' was declared here 713 | void *c, *t, *cell, *freq; | ^ cc1: all warnings being treated as errors ```` Signed-off-by: Hauke Mehrtens --- package/network/utils/uqmi/Makefile | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/package/network/utils/uqmi/Makefile b/package/network/utils/uqmi/Makefile index c4ca98012a0..02265d400c1 100644 --- a/package/network/utils/uqmi/Makefile +++ b/package/network/utils/uqmi/Makefile @@ -32,7 +32,11 @@ define Package/uqmi/description endef TARGET_CFLAGS += \ - -I$(STAGING_DIR)/usr/include -ffunction-sections -fdata-sections + -I$(STAGING_DIR)/usr/include \ + -ffunction-sections \ + -fdata-sections \ + -Wno-error=dangling-pointer \ + -Wno-error=maybe-uninitialized TARGET_LDFLAGS += -Wl,--gc-sections From 25223b22c86ab07aa174e0285784f591f145a825 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Mon, 19 Dec 2022 01:40:04 +0100 Subject: [PATCH 08/51] rtl8812au-ct: Ignore address errors GCC 12.2.0 shows these error messages: ```` rtl8812au-ct-2021-11-07-39df5596/core/rtw_sta_mgt.c: In function 'rtw_mfree_stainfo': rtl8812au-ct-2021-11-07-39df5596/core/rtw_sta_mgt.c:210:24: error: the comparison will always evaluate as 'true' for the address of 'lock' will never be NULL [-Werror=address] 210 | if(&psta->lock != NULL) | ^~ In file included from rtl8812au-ct-2021-11-07-39df5596/include/drv_types.h:109, from rtl8812au-ct-2021-11-07-39df5596/core/rtw_sta_mgt.c:22: rtl8812au-ct-2021-11-07-39df5596/include/sta_info.h:95:17: note: 'lock' declared here 95 | _lock lock; | ^~~~ ```` ```` CC [M] rtl8812au-ct-2021-11-07-39df5596/os_dep/linux/ioctl_cfg80211.o rtl8812au-ct-2021-11-07-39df5596/os_dep/linux/ioctl_cfg80211.c: In function 'cfg80211_rtw_scan': rtl8812au-ct-2021-11-07-39df5596/os_dep/linux/ioctl_cfg80211.c:2176:32: warning: the comparison will always evaluate as 'true' for the address of 'ssid' will never be NULL [-Waddress] 2176 | if(ssids->ssid != NULL | ^~ In file included from rtl8812au-ct-2021-11-07-39df5596/include/osdep_service_linux.h:88, from rtl8812au-ct-2021-11-07-39df5596/include/osdep_service.h:41, from rtl8812au-ct-2021-11-07-39df5596/include/drv_types.h:32, from rtl8812au-ct-2021-11-07-39df5596/os_dep/linux/ioctl_cfg80211.c:22: /home/hauke/openwrt/openwrt/staging_dir/target-mips_24kc_musl/usr/include/mac80211/net/cfg80211.h:2364:12: note: 'ssid' declared here 2364 | u8 ssid[IEEE80211_MAX_SSID_LEN]; | ^~~~ ```` ```` CC [M] rtl8812au-ct-2021-11-07-39df5596/hal/OUTSRC/phydm_debug.o rtl8812au-ct-2021-11-07-39df5596/hal/OUTSRC/phydm_debug.c: In function 'phydm_cmd_parser': rtl8812au-ct-2021-11-07-39df5596/hal/OUTSRC/phydm_debug.c:873:28: warning: the comparison will always evaluate as 'true' for the pointer operand in 'input + ((sizetype)i + 1) * 16' must not be NULL [-Waddress] 873 | if(input[i+1]) { | ^~~~~ rtl8812au-ct-2021-11-07-39df5596/hal/OUTSRC/phydm_debug.c:894:28: warning: the comparison will always evaluate as 'true' for the pointer operand in 'input + ((sizetype)i + 1) * 16' must not be NULL [-Waddress] 894 | if(input[i+1]) { | ^~~~~ ```` This one was only seen on the rockchip/armv8 target: ```` CC [M] rtl8812au-ct-2021-11-07-39df5596/core/rtw_br_ext.o In function '__nat25_add_pppoe_tag', inlined from 'nat25_db_handle' at rtl8812au-ct-2021-11-07-39df5596/core/rtw_br_ext.c:909:10: rtl8812au-ct-2021-11-07-39df5596/core/rtw_br_ext.c:118:9: error: 'memcpy' reading between 2052 and 9220 bytes from a region of size 40 [-Werror=stringop-overread] 118 | memcpy((unsigned char *)ph->tag, tag, data_len); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ rtl8812au-ct-2021-11-07-39df5596/core/rtw_br_ext.c: In function 'nat25_db_handle': rtl8812au-ct-2021-11-07-39df5596/core/rtw_br_ext.c:878:63: note: source object 'tag_buf' of size 40 878 | unsigned char tag_buf[40]; | ^~~~~~~ ```` Most of them are looking like real errors to me, but some fixes need a deeper understanding of the driver and probably bigger changes to the driver. Ignore these error messages for now. It would be nice if someone would fix them. Signed-off-by: Hauke Mehrtens --- package/kernel/rtl8812au-ct/Makefile | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/package/kernel/rtl8812au-ct/Makefile b/package/kernel/rtl8812au-ct/Makefile index c8dd4170673..be1acabf287 100644 --- a/package/kernel/rtl8812au-ct/Makefile +++ b/package/kernel/rtl8812au-ct/Makefile @@ -39,7 +39,9 @@ NOSTDINC_FLAGS := \ -I$(STAGING_DIR)/usr/include/mac80211-backport/uapi \ -I$(STAGING_DIR)/usr/include/mac80211 \ -I$(STAGING_DIR)/usr/include/mac80211/uapi \ - -include backport/backport.h + -include backport/backport.h \ + -Wno-error=address \ + -Wno-error=stringop-overread NOSTDINC_FLAGS+=-DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT -DBUILD_OPENWRT From a58b29ded7a6d3209aad1d2ff30b5a38d692a45f Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Tue, 20 Dec 2022 00:58:19 +0100 Subject: [PATCH 09/51] toolchain/gcc: Fix GCC version check The version check which sets GCC_VERSION_FILE to the correct value only worked when the advanced options menu was active and not when it was not active. Thank you Tony Butler for the fix. Signed-off-by: Hauke Mehrtens --- toolchain/gcc/common.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/toolchain/gcc/common.mk b/toolchain/gcc/common.mk index 6661b0aa38d..ea2e2634b69 100644 --- a/toolchain/gcc/common.mk +++ b/toolchain/gcc/common.mk @@ -178,7 +178,7 @@ define Host/SetToolchainInfo endef -ifdef CONFIG_GCC_USE_VERSION_12 +ifeq ($(GCC_MAJOR_VERSION),12) GCC_VERSION_FILE:=gcc/genversion.cc else GCC_VERSION_FILE:=gcc/version.c From d9de5252a44e208cecaa1e2edad3d1615b84302c Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Mon, 19 Dec 2022 01:47:48 +0100 Subject: [PATCH 10/51] toolchain/gcc: switch to version 12 by default This was build tested with all core packages on all targets successfully. Most packages from the feed are also building fine. This was run tested on the following systems: * lantiq/xrx200 musl * pistachio/generic musl * sunxi/cortexa53 musl * x86/64 musl * x86/64 glibc * armvirt/64 musl The size of the images stays more or less the same for MIPS BE and aarch64. I haven't tested other architectures. With GCC 11 I got these sizes for lantiq/xrx200: 7,219,848 openwrt-lantiq-xrx200-tplink_tdw8970-initramfs-kernel.bin 7,472,208 openwrt-lantiq-xrx200-tplink_tdw8970-squashfs-sysupgrade.bin With GCC 12 I got these sizes for lantiq/xrx200: 7,217,355 openwrt-lantiq-xrx200-tplink_tdw8970-initramfs-kernel.bin 7,406,674 openwrt-lantiq-xrx200-tplink_tdw8970-squashfs-sysupgrade.bin The sysupgrade image is probably padded. The initramfs image is 0.03% smaller. With GCC 11 I got these sizes for armvirt/64: 4,143,943 openwrt-armvirt-64-default-rootfs.tar.gz 10,887,176 openwrt-armvirt-64-Image 24,911,880 openwrt-armvirt-64-Image-initramfs 4,141,572 openwrt-armvirt-64-rootfs.cpio.gz 4,255,854 openwrt-armvirt-64-rootfs-ext4.img.gz 3,391,178 openwrt-armvirt-64-rootfs-squashfs.img.gz With GCC 12 I got these sizes for armvirt/64: 4,142,778 openwrt-armvirt-64-default-rootfs.tar.gz 10,887,176 openwrt-armvirt-64-Image 24,911,880 openwrt-armvirt-64-Image-initramfs 4,138,105 openwrt-armvirt-64-rootfs.cpio.gz 4,255,463 openwrt-armvirt-64-rootfs-ext4.img.gz 3,390,390 openwrt-armvirt-64-rootfs-squashfs.img.gz Signed-off-by: Hauke Mehrtens --- toolchain/gcc/Config.in | 2 +- toolchain/gcc/Config.version | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/toolchain/gcc/Config.in b/toolchain/gcc/Config.in index 3c074c99b2f..af4d54c73e5 100644 --- a/toolchain/gcc/Config.in +++ b/toolchain/gcc/Config.in @@ -2,7 +2,7 @@ choice prompt "GCC compiler Version" if TOOLCHAINOPTS - default GCC_USE_VERSION_11 + default GCC_USE_VERSION_12 help Select the version of gcc you wish to use. diff --git a/toolchain/gcc/Config.version b/toolchain/gcc/Config.version index 65f272746b0..6202ca732f1 100644 --- a/toolchain/gcc/Config.version +++ b/toolchain/gcc/Config.version @@ -1,8 +1,8 @@ -config GCC_VERSION_12 - default y if GCC_USE_VERSION_12 +config GCC_VERSION_11 + default y if GCC_USE_VERSION_11 bool config GCC_VERSION string - default "12.2.0" if GCC_VERSION_12 - default "11.3.0" + default "12.2.0" + default "11.3.0" if GCC_VERSION_11 From f9653cbaac1bcb7fd15c83858f117c419ed59847 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Petr=20=C5=A0tetiar?= Date: Mon, 9 Jan 2023 10:49:35 +0100 Subject: [PATCH 11/51] ci: show_build_failures: fix missing output for configure failures MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We're currently missing log output in cases where `configure` fails which returns 77 as its error code: make[3]: *** [Makefile:118: elfutils-0.188/.configured_889556d2f423f99e091beece9c8d870a] Error 77 So lets adjust the regexps so they can handle multiple digits. Signed-off-by: Petr Štetiar --- .github/workflows/scripts/show_build_failures.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/scripts/show_build_failures.sh b/.github/workflows/scripts/show_build_failures.sh index 14f699c93d8..7b1a021155b 100755 --- a/.github/workflows/scripts/show_build_failures.sh +++ b/.github/workflows/scripts/show_build_failures.sh @@ -5,9 +5,9 @@ log_dir_path="${1:-logs}" context="${2:-10}" show_make_build_errors() { - grep -slr 'make\[[[:digit:]]\].*Error [[:digit:]]$' "$log_dir_path" | while IFS= read -r log_file; do + grep -slr 'make\[[[:digit:]]\+\].*Error [[:digit:]]\+$' "$log_dir_path" | while IFS= read -r log_file; do printf "====== Make errors from %s ======\n" "$log_file"; - grep -r -C"$context" 'make\[[[:digit:]]\].*Error [[:digit:]]$' "$log_file" ; + grep -r -C"$context" 'make\[[[:digit:]]\+\].*Error [[:digit:]]\+$' "$log_file" ; done } From d6a284e4cea46129a18542c6f23309b7bf1af174 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Sun, 8 Jan 2023 20:38:40 +0100 Subject: [PATCH 12/51] ucode: update to the latest version 34cfbb922c96 README.md: various spelling and documentation fixes ff32355ea645 build: make rtnl/nl80211 depend on linux instead of !APPLE c0e413c21f7b include: add uc_fn_thisval() 1e4d20932646 Merge pull request #134 from nbd168/thisval Signed-off-by: Felix Fietkau --- package/utils/ucode/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/utils/ucode/Makefile b/package/utils/ucode/Makefile index fafc449090b..228403e0415 100644 --- a/package/utils/ucode/Makefile +++ b/package/utils/ucode/Makefile @@ -12,9 +12,9 @@ PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=https://github.com/jow-/ucode.git -PKG_SOURCE_DATE:=2022-12-02 -PKG_SOURCE_VERSION:=46d93c9cc5da6fce581df86159bd0fc4357de41c -PKG_MIRROR_HASH:=970a47f1bef719f056d40d17398db492bd4de92b98ef9aba4582cb18b4c9b270 +PKG_SOURCE_DATE:=2023-01-07 +PKG_SOURCE_VERSION:=1e4d20932646f90523d21ea358c72901e3ee689e +PKG_MIRROR_HASH:=8c43b9a0a80c3de92961caad65c934bd3989e6f7f9389f676d91e2e926c9e4a6 PKG_MAINTAINER:=Jo-Philipp Wich PKG_LICENSE:=ISC From 0cc1c302b188f905ccf081d8f3984cee27bd7524 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Sun, 8 Jan 2023 20:40:40 +0100 Subject: [PATCH 13/51] ucode-mod-bpf: add new package for a ucode libbpf binding The bpf plugin provides functionality for loading and interacting with eBPF modules. It allows loading full modules and pinned maps/programs and supports interacting with maps and attaching programs as tc classifiers. Signed-off-by: Felix Fietkau --- package/utils/ucode-mod-bpf/Makefile | 40 ++ package/utils/ucode-mod-bpf/src/bpf.c | 814 ++++++++++++++++++++++++++ 2 files changed, 854 insertions(+) create mode 100644 package/utils/ucode-mod-bpf/Makefile create mode 100644 package/utils/ucode-mod-bpf/src/bpf.c diff --git a/package/utils/ucode-mod-bpf/Makefile b/package/utils/ucode-mod-bpf/Makefile new file mode 100644 index 00000000000..a748b9dbbd0 --- /dev/null +++ b/package/utils/ucode-mod-bpf/Makefile @@ -0,0 +1,40 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=ucode-mod-bpf +PKG_RELEASE:=1 +PKG_LICENSE:=ISC +PKG_MAINTAINER:=Felix Fietkau + +include $(INCLUDE_DIR)/package.mk +include $(INCLUDE_DIR)/nls.mk + +define Package/ucode-mod-bpf + SECTION:=utils + CATEGORY:=Utilities + TITLE:=ucode eBPF module + DEPENDS:=+libucode +libbpf +endef + +define Package/ucode-mod-bpf/description +The bpf plugin provides functionality for loading and interacting with +eBPF modules. + +It allows loading full modules and pinned maps/programs and supports +interacting with maps and attaching programs as tc classifiers. +endef + +define Package/ucode-mod-bpf/install + $(INSTALL_DIR) $(1)/usr/lib/ucode + $(CP) $(PKG_BUILD_DIR)/bpf.so $(1)/usr/lib/ucode/ +endef + +define Build/Configure +endef + +define Build/Compile + $(TARGET_CC) $(TARGET_CFLAGS) $(TARGET_LDFLAGS) $(FPIC) \ + -Wall -ffunction-sections -Wl,--gc-sections -shared -Wl,--no-as-needed -lbpf \ + -o $(PKG_BUILD_DIR)/bpf.so $(PKG_BUILD_DIR)/bpf.c +endef + +$(eval $(call BuildPackage,ucode-mod-bpf)) diff --git a/package/utils/ucode-mod-bpf/src/bpf.c b/package/utils/ucode-mod-bpf/src/bpf.c new file mode 100644 index 00000000000..415215e54e1 --- /dev/null +++ b/package/utils/ucode-mod-bpf/src/bpf.c @@ -0,0 +1,814 @@ +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include "ucode/module.h" + +#define err_return_int(err, ...) do { set_error(err, __VA_ARGS__); return -1; } while(0) +#define err_return(err, ...) do { set_error(err, __VA_ARGS__); return NULL; } while(0) +#define TRUE ucv_boolean_new(true) + +static uc_resource_type_t *module_type, *map_type, *map_iter_type, *program_type; +static uc_value_t *registry; +static uc_vm_t *debug_vm; + +static struct { + int code; + char *msg; +} last_error; + +struct uc_bpf_fd { + int fd; + bool close; +}; + +struct uc_bpf_map { + struct uc_bpf_fd fd; /* must be first */ + unsigned int key_size, val_size; +}; + +struct uc_bpf_map_iter { + int fd; + unsigned int key_size; + bool has_next; + uint8_t key[]; +}; + +__attribute__((format(printf, 2, 3))) static void +set_error(int errcode, const char *fmt, ...) +{ + va_list ap; + + free(last_error.msg); + + last_error.code = errcode; + last_error.msg = NULL; + + if (fmt) { + va_start(ap, fmt); + xvasprintf(&last_error.msg, fmt, ap); + va_end(ap); + } +} + +static void init_env(void) +{ + static bool init_done = false; + struct rlimit limit = { + .rlim_cur = RLIM_INFINITY, + .rlim_max = RLIM_INFINITY, + }; + + if (init_done) + return; + + setrlimit(RLIMIT_MEMLOCK, &limit); + init_done = true; +} + +static uc_value_t * +uc_bpf_error(uc_vm_t *vm, size_t nargs) +{ + uc_value_t *numeric = uc_fn_arg(0); + const char *msg = last_error.msg; + int code = last_error.code; + uc_stringbuf_t *buf; + const char *s; + + if (last_error.code == 0) + return NULL; + + set_error(0, NULL); + + if (ucv_is_truish(numeric)) + return ucv_int64_new(code); + + buf = ucv_stringbuf_new(); + if (code < 0 && msg) { + ucv_stringbuf_addstr(buf, msg, strlen(msg)); + } else { + s = strerror(code); + ucv_stringbuf_addstr(buf, s, strlen(s)); + if (msg) + ucv_stringbuf_printf(buf, ": %s", msg); + } + + return ucv_stringbuf_finish(buf); +} + +static int +uc_bpf_module_set_opts(struct bpf_object *obj, uc_value_t *opts) +{ + uc_value_t *val; + + if (!opts) + return 0; + + if (ucv_type(opts) != UC_OBJECT) + err_return_int(EINVAL, "options argument"); + + if ((val = ucv_object_get(opts, "rodata", NULL)) != NULL) { + struct bpf_map *map = NULL; + + if (ucv_type(val) != UC_STRING) + err_return_int(EINVAL, "rodata type"); + + while ((map = bpf_object__next_map(obj, map)) != NULL) { + if (!strstr(bpf_map__name(map), ".rodata")) + continue; + + break; + } + + if (!map) + err_return_int(errno, "rodata map"); + + if (bpf_map__set_initial_value(map, ucv_string_get(val), + ucv_string_length(val))) + err_return_int(errno, "rodata"); + } + + if ((val = ucv_object_get(opts, "program-type", NULL)) != NULL) { + if (ucv_type(val) != UC_OBJECT) + err_return_int(EINVAL, "prog_types argument"); + + ucv_object_foreach(val, name, type) { + struct bpf_program *prog; + + if (ucv_type(type) != UC_INTEGER) + err_return_int(EINVAL, "program %s type", name); + + prog = bpf_object__find_program_by_name(obj, name); + if (!prog) + err_return_int(-1, "program %s not found", name); + + bpf_program__set_type(prog, ucv_int64_get(type)); + } + } + + return 0; +} + +static uc_value_t * +uc_bpf_open_module(uc_vm_t *vm, size_t nargs) +{ + DECLARE_LIBBPF_OPTS(bpf_object_open_opts, bpf_opts); + uc_value_t *path = uc_fn_arg(0); + uc_value_t *opts = uc_fn_arg(1); + struct bpf_object *obj; + + if (ucv_type(path) != UC_STRING) + err_return(EINVAL, "module path"); + + init_env(); + obj = bpf_object__open_file(ucv_string_get(path), &bpf_opts); + if (libbpf_get_error(obj)) + err_return(errno, NULL); + + if (uc_bpf_module_set_opts(obj, opts)) { + bpf_object__close(obj); + return NULL; + } + + if (bpf_object__load(obj)) { + bpf_object__close(obj); + err_return(errno, NULL); + } + + return uc_resource_new(module_type, obj); +} + +static uc_value_t * +uc_bpf_map_create(int fd, unsigned int key_size, unsigned int val_size, bool close) +{ + struct uc_bpf_map *uc_map; + + uc_map = xalloc(sizeof(*uc_map)); + uc_map->fd.fd = fd; + uc_map->key_size = key_size; + uc_map->val_size = val_size; + uc_map->fd.close = close; + + return uc_resource_new(map_type, uc_map); +} + +static uc_value_t * +uc_bpf_open_map(uc_vm_t *vm, size_t nargs) +{ + struct bpf_map_info info; + uc_value_t *path = uc_fn_arg(0); + __u32 len = sizeof(info); + int err; + int fd; + + if (ucv_type(path) != UC_STRING) + err_return(EINVAL, "module path"); + + fd = bpf_obj_get(ucv_string_get(path)); + if (fd < 0) + err_return(errno, NULL); + + err = bpf_obj_get_info_by_fd(fd, &info, &len); + if (err) { + close(fd); + err_return(errno, NULL); + } + + return uc_bpf_map_create(fd, info.key_size, info.value_size, true); +} + +static uc_value_t * +uc_bpf_open_program(uc_vm_t *vm, size_t nargs) +{ + uc_value_t *path = uc_fn_arg(0); + struct uc_bpf_fd *f; + int fd; + + if (ucv_type(path) != UC_STRING) + err_return(EINVAL, "module path"); + + fd = bpf_obj_get(ucv_string_get(path)); + if (fd < 0) + err_return(errno, NULL); + + f = xalloc(sizeof(*f)); + f->fd = fd; + f->close = true; + + return uc_resource_new(program_type, f); +} + +static uc_value_t * +uc_bpf_module_get_maps(uc_vm_t *vm, size_t nargs) +{ + struct bpf_object *obj = uc_fn_thisval("bpf.module"); + struct bpf_map *map = NULL; + uc_value_t *rv; + int i = 0; + + if (!obj) + err_return(EINVAL, NULL); + + rv = ucv_array_new(vm); + bpf_object__for_each_map(map, obj) + ucv_array_set(rv, i++, ucv_string_new(bpf_map__name(map))); + + return rv; +} + +static uc_value_t * +uc_bpf_module_get_map(uc_vm_t *vm, size_t nargs) +{ + struct bpf_object *obj = uc_fn_thisval("bpf.module"); + struct bpf_map *map; + uc_value_t *name = uc_fn_arg(0); + int fd; + + if (!obj || ucv_type(name) != UC_STRING) + err_return(EINVAL, NULL); + + map = bpf_object__find_map_by_name(obj, ucv_string_get(name)); + if (!map) + err_return(errno, NULL); + + fd = bpf_map__fd(map); + if (fd < 0) + err_return(EINVAL, NULL); + + return uc_bpf_map_create(fd, bpf_map__key_size(map), bpf_map__value_size(map), false); +} + +static uc_value_t * +uc_bpf_module_get_programs(uc_vm_t *vm, size_t nargs) +{ + struct bpf_object *obj = uc_fn_thisval("bpf.module"); + struct bpf_program *prog = NULL; + uc_value_t *rv; + int i = 0; + + if (!obj) + err_return(EINVAL, NULL); + + rv = ucv_array_new(vm); + bpf_object__for_each_program(prog, obj) + ucv_array_set(rv, i++, ucv_string_new(bpf_program__name(prog))); + + return rv; +} + +static uc_value_t * +uc_bpf_module_get_program(uc_vm_t *vm, size_t nargs) +{ + struct bpf_object *obj = uc_fn_thisval("bpf.module"); + struct bpf_program *prog; + uc_value_t *name = uc_fn_arg(0); + struct uc_bpf_fd *f; + int fd; + + if (!obj || !name || ucv_type(name) != UC_STRING) + err_return(EINVAL, NULL); + + prog = bpf_object__find_program_by_name(obj, ucv_string_get(name)); + if (!prog) + err_return(errno, NULL); + + fd = bpf_program__fd(prog); + if (fd < 0) + err_return(EINVAL, NULL); + + f = xalloc(sizeof(*f)); + f->fd = fd; + + return uc_resource_new(program_type, f); +} + +static void * +uc_bpf_map_arg(uc_value_t *val, const char *kind, unsigned int size) +{ + static union { + uint32_t u32; + uint64_t u64; + } val_int; + + switch (ucv_type(val)) { + case UC_INTEGER: + if (size == 4) + val_int.u32 = ucv_int64_get(val); + else if (size == 8) + val_int.u64 = ucv_int64_get(val); + else + break; + + return &val_int; + case UC_STRING: + if (size != ucv_string_length(val)) + break; + + return ucv_string_get(val); + default: + err_return(EINVAL, "%s type", kind); + } + + err_return(EINVAL, "%s size mismatch (expected: %d)", kind, size); +} + +static uc_value_t * +uc_bpf_map_get(uc_vm_t *vm, size_t nargs) +{ + struct uc_bpf_map *map = uc_fn_thisval("bpf.map"); + uc_value_t *a_key = uc_fn_arg(0); + void *key, *val; + + if (!map) + err_return(EINVAL, NULL); + + key = uc_bpf_map_arg(a_key, "key", map->key_size); + if (!key) + return NULL; + + val = alloca(map->val_size); + if (bpf_map_lookup_elem(map->fd.fd, key, val)) + return NULL; + + return ucv_string_new_length(val, map->val_size); +} + +static uc_value_t * +uc_bpf_map_set(uc_vm_t *vm, size_t nargs) +{ + struct uc_bpf_map *map = uc_fn_thisval("bpf.map"); + uc_value_t *a_key = uc_fn_arg(0); + uc_value_t *a_val = uc_fn_arg(1); + uc_value_t *a_flags = uc_fn_arg(2); + uint64_t flags; + void *key, *val; + + if (!map) + err_return(EINVAL, NULL); + + key = uc_bpf_map_arg(a_key, "key", map->key_size); + if (!key) + return NULL; + + val = uc_bpf_map_arg(a_val, "value", map->val_size); + if (!val) + return NULL; + + if (!a_flags) + flags = BPF_ANY; + else if (ucv_type(a_flags) != UC_INTEGER) + err_return(EINVAL, "flags"); + else + flags = ucv_int64_get(a_flags); + + if (bpf_map_update_elem(map->fd.fd, key, val, flags)) + return NULL; + + return ucv_string_new_length(val, map->val_size); +} + +static uc_value_t * +uc_bpf_map_delete(uc_vm_t *vm, size_t nargs) +{ + struct uc_bpf_map *map = uc_fn_thisval("bpf.map"); + uc_value_t *a_key = uc_fn_arg(0); + uc_value_t *a_return = uc_fn_arg(1); + void *key, *val = NULL; + int ret; + + if (!map) + err_return(EINVAL, NULL); + + key = uc_bpf_map_arg(a_key, "key", map->key_size); + if (!key) + return NULL; + + if (!ucv_is_truish(a_return)) { + ret = bpf_map_delete_elem(map->fd.fd, key); + + return ucv_boolean_new(ret == 0); + } + + val = alloca(map->val_size); + if (bpf_map_lookup_and_delete_elem(map->fd.fd, key, val)) + return NULL; + + return ucv_string_new_length(val, map->val_size); +} + +static uc_value_t * +uc_bpf_map_delete_all(uc_vm_t *vm, size_t nargs) +{ + struct uc_bpf_map *map = uc_fn_thisval("bpf.map"); + uc_value_t *filter = uc_fn_arg(0); + bool has_next; + void *key, *next; + + if (!map) + err_return(EINVAL, NULL); + + key = alloca(map->key_size); + next = alloca(map->key_size); + has_next = !bpf_map_get_next_key(map->fd.fd, NULL, next); + while (has_next) { + bool skip = false; + + memcpy(key, next, map->key_size); + has_next = !bpf_map_get_next_key(map->fd.fd, next, next); + + if (ucv_is_callable(filter)) { + uc_value_t *rv; + + uc_value_push(ucv_get(filter)); + uc_value_push(ucv_string_new_length((const char *)key, map->key_size)); + if (uc_call(1) != EXCEPTION_NONE) + break; + + rv = uc_vm_stack_pop(vm); + if (!rv) + break; + + skip = !ucv_is_truish(rv); + ucv_put(rv); + } + + if (!skip) + bpf_map_delete_elem(map->fd.fd, key); + } + + return TRUE; +} + +static uc_value_t * +uc_bpf_map_iterator(uc_vm_t *vm, size_t nargs) +{ + struct uc_bpf_map *map = uc_fn_thisval("bpf.map"); + struct uc_bpf_map_iter *iter; + + if (!map) + err_return(EINVAL, NULL); + + iter = xalloc(sizeof(*iter) + map->key_size); + iter->fd = map->fd.fd; + iter->key_size = map->key_size; + iter->has_next = !bpf_map_get_next_key(iter->fd, NULL, &iter->key); + + return uc_resource_new(map_iter_type, iter); +} + +static uc_value_t * +uc_bpf_map_iter_next(uc_vm_t *vm, size_t nargs) +{ + struct uc_bpf_map_iter *iter = uc_fn_thisval("bpf.map_iter"); + uc_value_t *rv; + + if (!iter->has_next) + return NULL; + + rv = ucv_string_new_length((const char *)iter->key, iter->key_size); + iter->has_next = !bpf_map_get_next_key(iter->fd, &iter->key, &iter->key); + + return rv; +} + +static uc_value_t * +uc_bpf_map_iter_next_int(uc_vm_t *vm, size_t nargs) +{ + struct uc_bpf_map_iter *iter = uc_fn_thisval("bpf.map_iter"); + uint64_t intval; + uc_value_t *rv; + + if (!iter->has_next) + return NULL; + + if (iter->key_size == 4) + intval = *(uint32_t *)iter->key; + else if (iter->key_size == 8) + intval = *(uint64_t *)iter->key; + else + return NULL; + + rv = ucv_int64_new(intval); + iter->has_next = !bpf_map_get_next_key(iter->fd, &iter->key, &iter->key); + + return rv; +} + +static uc_value_t * +uc_bpf_map_foreach(uc_vm_t *vm, size_t nargs) +{ + struct uc_bpf_map *map = uc_fn_thisval("bpf.map"); + uc_value_t *func = uc_fn_arg(0); + bool has_next; + void *key, *next; + bool ret = false; + + key = alloca(map->key_size); + next = alloca(map->key_size); + has_next = !bpf_map_get_next_key(map->fd.fd, NULL, next); + + while (has_next) { + uc_value_t *rv; + bool stop; + + memcpy(key, next, map->key_size); + has_next = !bpf_map_get_next_key(map->fd.fd, next, next); + + uc_value_push(ucv_get(func)); + uc_value_push(ucv_string_new_length((const char *)key, map->key_size)); + + if (uc_call(1) != EXCEPTION_NONE) + break; + + rv = uc_vm_stack_pop(vm); + stop = (ucv_type(rv) == UC_BOOLEAN && !ucv_boolean_get(rv)); + ucv_put(rv); + + if (stop) + break; + + ret = true; + } + + return ucv_boolean_new(ret); +} + +static uc_value_t * +uc_bpf_obj_pin(uc_vm_t *vm, size_t nargs, const char *type) +{ + struct uc_bpf_fd *f = uc_fn_thisval(type); + uc_value_t *path = uc_fn_arg(0); + + if (ucv_type(path) != UC_STRING) + err_return(EINVAL, NULL); + + if (bpf_obj_pin(f->fd, ucv_string_get(path))) + err_return(errno, NULL); + + return TRUE; +} + +static uc_value_t * +uc_bpf_program_pin(uc_vm_t *vm, size_t nargs) +{ + return uc_bpf_obj_pin(vm, nargs, "bpf.program"); +} + +static uc_value_t * +uc_bpf_map_pin(uc_vm_t *vm, size_t nargs) +{ + return uc_bpf_obj_pin(vm, nargs, "bpf.map"); +} + +static uc_value_t * +uc_bpf_set_tc_hook(uc_value_t *ifname, uc_value_t *type, uc_value_t *prio, + int fd) +{ + DECLARE_LIBBPF_OPTS(bpf_tc_hook, hook); + DECLARE_LIBBPF_OPTS(bpf_tc_opts, attach_tc, + .handle = 1); + const char *type_str; + uint64_t prio_val; + + if (ucv_type(ifname) != UC_STRING || ucv_type(type) != UC_STRING || + ucv_type(prio) != UC_INTEGER) + err_return(EINVAL, NULL); + + prio_val = ucv_int64_get(prio); + if (prio_val > 0xffff) + err_return(EINVAL, NULL); + + type_str = ucv_string_get(type); + if (!strcmp(type_str, "ingress")) + hook.attach_point = BPF_TC_INGRESS; + else if (!strcmp(type_str, "egress")) + hook.attach_point = BPF_TC_EGRESS; + else + err_return(EINVAL, NULL); + + hook.ifindex = if_nametoindex(ucv_string_get(ifname)); + if (!hook.ifindex) + goto error; + + bpf_tc_hook_create(&hook); + attach_tc.priority = prio_val; + if (bpf_tc_detach(&hook, &attach_tc) < 0 && fd < 0) + goto error; + + if (fd < 0) + goto out; + + attach_tc.prog_fd = fd; + if (bpf_tc_attach(&hook, &attach_tc) < 0) + goto error; + +out: + return TRUE; + +error: + if (fd >= 0) + err_return(ENOENT, NULL); + return NULL; +} + +static uc_value_t * +uc_bpf_program_tc_attach(uc_vm_t *vm, size_t nargs) +{ + struct uc_bpf_fd *f = uc_fn_thisval("bpf.program"); + uc_value_t *ifname = uc_fn_arg(0); + uc_value_t *type = uc_fn_arg(1); + uc_value_t *prio = uc_fn_arg(2); + + if (!f) + err_return(EINVAL, NULL); + + return uc_bpf_set_tc_hook(ifname, type, prio, f->fd); +} + +static uc_value_t * +uc_bpf_tc_detach(uc_vm_t *vm, size_t nargs) +{ + uc_value_t *ifname = uc_fn_arg(0); + uc_value_t *type = uc_fn_arg(1); + uc_value_t *prio = uc_fn_arg(2); + + return uc_bpf_set_tc_hook(ifname, type, prio, -1); +} + +static int +uc_bpf_debug_print(enum libbpf_print_level level, const char *format, + va_list args) +{ + char buf[256], *str = NULL; + uc_value_t *val; + va_list ap; + int size; + + va_copy(ap, args); + size = vsnprintf(buf, sizeof(buf), format, ap); + va_end(ap); + + if (size > 0 && (unsigned long)size < ARRAY_SIZE(buf) - 1) { + val = ucv_string_new(buf); + goto out; + } + + if (vasprintf(&str, format, args) < 0) + return 0; + + val = ucv_string_new(str); + free(str); + +out: + uc_vm_stack_push(debug_vm, ucv_get(ucv_array_get(registry, 0))); + uc_vm_stack_push(debug_vm, ucv_int64_new(level)); + uc_vm_stack_push(debug_vm, val); + if (uc_vm_call(debug_vm, false, 2) == EXCEPTION_NONE) + ucv_put(uc_vm_stack_pop(debug_vm)); + + return 0; +} + +static uc_value_t * +uc_bpf_set_debug_handler(uc_vm_t *vm, size_t nargs) +{ + uc_value_t *handler = uc_fn_arg(0); + + if (handler && !ucv_is_callable(handler)) + err_return(EINVAL, NULL); + + debug_vm = vm; + libbpf_set_print(handler ? uc_bpf_debug_print : NULL); + + ucv_array_set(registry, 0, ucv_get(handler)); + + return NULL; +} + +static void +register_constants(uc_vm_t *vm, uc_value_t *scope) +{ +#define ADD_CONST(x) ucv_object_add(scope, #x, ucv_int64_new(x)) + ADD_CONST(BPF_PROG_TYPE_SCHED_CLS); + ADD_CONST(BPF_PROG_TYPE_SCHED_ACT); + + ADD_CONST(BPF_ANY); + ADD_CONST(BPF_NOEXIST); + ADD_CONST(BPF_EXIST); + ADD_CONST(BPF_F_LOCK); +} + +static const uc_function_list_t module_fns[] = { + { "get_map", uc_bpf_module_get_map }, + { "get_maps", uc_bpf_module_get_maps }, + { "get_programs", uc_bpf_module_get_programs }, + { "get_program", uc_bpf_module_get_program }, +}; + +static void module_free(void *ptr) +{ + struct bpf_object *obj = ptr; + + bpf_object__close(obj); +} + +static const uc_function_list_t map_fns[] = { + { "pin", uc_bpf_map_pin }, + { "get", uc_bpf_map_get }, + { "set", uc_bpf_map_set }, + { "delete", uc_bpf_map_delete }, + { "delete_all", uc_bpf_map_delete_all }, + { "foreach", uc_bpf_map_foreach }, + { "iterator", uc_bpf_map_iterator }, +}; + +static void uc_bpf_fd_free(void *ptr) +{ + struct uc_bpf_fd *f = ptr; + + if (f->close) + close(f->fd); + free(f); +} + +static const uc_function_list_t map_iter_fns[] = { + { "next", uc_bpf_map_iter_next }, + { "next_int", uc_bpf_map_iter_next_int }, +}; + +static const uc_function_list_t prog_fns[] = { + { "pin", uc_bpf_program_pin }, + { "tc_attach", uc_bpf_program_tc_attach }, +}; + +static const uc_function_list_t global_fns[] = { + { "error", uc_bpf_error }, + { "set_debug_handler", uc_bpf_set_debug_handler }, + { "open_module", uc_bpf_open_module }, + { "open_map", uc_bpf_open_map }, + { "open_program", uc_bpf_open_program }, + { "tc_detach", uc_bpf_tc_detach }, +}; + +void uc_module_init(uc_vm_t *vm, uc_value_t *scope) +{ + uc_function_list_register(scope, global_fns); + register_constants(vm, scope); + + registry = ucv_array_new(vm); + uc_vm_registry_set(vm, "bpf.registry", registry); + + module_type = uc_type_declare(vm, "bpf.module", module_fns, module_free); + map_type = uc_type_declare(vm, "bpf.map", map_fns, uc_bpf_fd_free); + map_iter_type = uc_type_declare(vm, "bpf.map_iter", map_iter_fns, free); + program_type = uc_type_declare(vm, "bpf.program", prog_fns, uc_bpf_fd_free); +} From 55f93085bbac1d22a786f9aa39d200e61892cb06 Mon Sep 17 00:00:00 2001 From: Stijn Tintel Date: Mon, 9 Jan 2023 17:30:42 +0200 Subject: [PATCH 14/51] qoriq: drop unused kernel config While switching qoriq to kernel 5.15, the config for kernel 5.10 was left behind. Drop it. Fixes: 230f2fccd14e ("qoriq: switch to kernel 5.15") Signed-off-by: Stijn Tintel --- target/linux/qoriq/config-5.10 | 384 --------------------------------- 1 file changed, 384 deletions(-) delete mode 100644 target/linux/qoriq/config-5.10 diff --git a/target/linux/qoriq/config-5.10 b/target/linux/qoriq/config-5.10 deleted file mode 100644 index c40f2b3084b..00000000000 --- a/target/linux/qoriq/config-5.10 +++ /dev/null @@ -1,384 +0,0 @@ -CONFIG_64BIT=y -CONFIG_ALTIVEC=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MAY_HAVE_PC_FDC=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=32 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_WEAK_RELEASE_ACQUIRE=y -CONFIG_ASN1=y -CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y -CONFIG_AUDIT_ARCH=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BOOKE=y -CONFIG_BOOKE_WDT=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLK_QORIQ=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CLZ_TAB=y -CONFIG_COMMON_CLK=y -# CONFIG_COMPAT_32BIT_TIME is not set -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_CORENET_GENERIC=y -# CONFIG_CPUFREQ_DT is not set -CONFIG_CPU_BIG_ENDIAN=y -CONFIG_CPU_FREQ=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -# CONFIG_CPU_FREQ_STAT is not set -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_TEO=y -CONFIG_CPU_ISOLATION=y -CONFIG_CPU_RMAP=y -CONFIG_CRC16=y -CONFIG_CRYPTO_AUTHENC=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -# CONFIG_CRYPTO_CRC32C_VPMSUM is not set -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_DEV_FSL_CAAM=y -CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y -CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC=y -CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON=y -CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y -CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC=y -CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI=y -# CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG is not set -# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set -CONFIG_CRYPTO_DEV_FSL_CAAM_JR=y -CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API=y -CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9 -CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y -# CONFIG_CRYPTO_DEV_NX is not set -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_ENGINE=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_DES=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1 -# CONFIG_CRYPTO_MD5_PPC is not set -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RSA=y -# CONFIG_CRYPTO_SHA1_PPC is not set -CONFIG_CRYPTO_XTS=y -CONFIG_DATA_SHIFT=12 -CONFIG_DEFAULT_UIMAGE=y -CONFIG_DMADEVICES=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_OPS=y -CONFIG_DMA_OPS_BYPASS=y -CONFIG_DTC=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_DYNAMIC_DEBUG=y -CONFIG_E500=y -# CONFIG_E5500_CPU is not set -CONFIG_E6500_CPU=y -CONFIG_EARLY_PRINTK=y -CONFIG_EDAC=y -CONFIG_EDAC_ATOMIC_SCRUB=y -# CONFIG_EDAC_CPC925 is not set -# CONFIG_EDAC_DEBUG is not set -CONFIG_EDAC_LEGACY_SYSFS=y -CONFIG_EDAC_MPC85XX=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EPAPR_PARAVIRT=y -CONFIG_EXT4_FS=y -CONFIG_EXT4_FS_POSIX_ACL=y -CONFIG_F2FS_FS=y -CONFIG_FIXED_PHY=y -CONFIG_FORCE_MAX_ZONEORDER=13 -# CONFIG_FSL_BMAN_TEST is not set -CONFIG_FSL_CORENET_CF=y -CONFIG_FSL_CORENET_RCPM=y -CONFIG_FSL_DMA=y -CONFIG_FSL_DPAA=y -# CONFIG_FSL_DPAA_CHECKING is not set -CONFIG_FSL_DPAA_ETH=y -CONFIG_FSL_EMB_PERFMON=y -CONFIG_FSL_FMAN=y -CONFIG_FSL_GUTS=y -CONFIG_FSL_IFC=y -CONFIG_FSL_LBC=y -CONFIG_FSL_MPIC_TIMER_WAKEUP=y -CONFIG_FSL_PAMU=y -CONFIG_FSL_PCI=y -# CONFIG_FSL_QMAN_TEST is not set -CONFIG_FSL_SOC=y -CONFIG_FSL_SOC_BOOKE=y -CONFIG_FSL_XGMAC_MDIO=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FS_POSIX_ACL=y -CONFIG_FTL=y -CONFIG_FUNCTION_ERROR_INJECTION=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CMOS_UPDATE=y -# CONFIG_GENERIC_CPU is not set -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_ISA_DMA=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -# CONFIG_GEN_RTC is not set -# CONFIG_GIANFAR is not set -CONFIG_GLOB=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_MPC8XXX=y -CONFIG_GRO_CELLS=y -# CONFIG_HANGCHECK_TIMER is not set -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HWMON=y -CONFIG_HW_CONSOLE=y -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_MPC=y -CONFIG_ILLEGAL_POINTER_VALUE=0x5deadbeef0000000 -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INPUT=y -CONFIG_IOMMU_API=y -# CONFIG_IOMMU_DEBUGFS is not set -CONFIG_IOMMU_HELPER=y -CONFIG_IOMMU_SUPPORT=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_ISA_DMA_API=y -CONFIG_JBD2=y -CONFIG_JUMP_LABEL=y -CONFIG_JUMP_LABEL_FEATURE_CHECKS=y -# CONFIG_JUMP_LABEL_FEATURE_CHECK_DEBUG is not set -CONFIG_KALLSYMS=y -CONFIG_KERNEL_GZIP=y -CONFIG_KERNEL_START=0xc000000000000000 -CONFIG_KPROBES=y -CONFIG_KRETPROBES=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_MARVELL_PHY=y -CONFIG_MATH_EMULATION=y -# CONFIG_MATH_EMULATION_FULL is not set -CONFIG_MATH_EMULATION_HW_UNIMPLEMENTED=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEMFD_CREATE=y -CONFIG_MEMORY=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_DEBUG=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_IO_ACCESSORS=y -CONFIG_MMC_SDHCI_OF_ESDHC=y -# CONFIG_MMC_SDHCI_PCI is not set -CONFIG_MMC_SDHCI_PLTFM=y -# CONFIG_MMC_WBSD is not set -CONFIG_MMIOWB=y -CONFIG_MMU_GATHER_PAGE_SIZE=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MPIC=y -CONFIG_MPIC_MSGR=y -CONFIG_MPIC_TIMER=y -CONFIG_MPILIB=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_FSL_IFC=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y -CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MV88E6XXX=y -CONFIG_NET_DSA_MV88E6XXX_GLOBAL2=y -CONFIG_NET_DSA_TAG_DSA=y -CONFIG_NET_DSA_TAG_EDSA=y -CONFIG_NET_DSA_TAG_OCELOT=y -CONFIG_NET_DSA_TAG_TRAILER=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NLS=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=24 -CONFIG_NR_IRQS=512 -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_DMA_DEFAULT_COHERENT=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IOMMU=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_OLD_SIGSUSPEND=y -CONFIG_OPTPROBES=y -CONFIG_PACKING=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xc000000000000000 -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_ARCH_FALLBACKS=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PGTABLE_LEVELS=4 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PHYSICAL_START=0x00000000 -CONFIG_PHYS_64BIT=y -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_PM=y -# CONFIG_PMU_SYSFS is not set -CONFIG_PM_CLK=y -CONFIG_PPC=y -CONFIG_PPC64=y -CONFIG_PPC_ADV_DEBUG_DACS=2 -CONFIG_PPC_ADV_DEBUG_DVCS=0 -CONFIG_PPC_ADV_DEBUG_IACS=2 -CONFIG_PPC_ADV_DEBUG_REGS=y -CONFIG_PPC_BARRIER_NOSPEC=y -CONFIG_PPC_BOOK3E=y -CONFIG_PPC_BOOK3E_64=y -CONFIG_PPC_BOOK3E_MMU=y -# CONFIG_PPC_BOOK3S_64 is not set -CONFIG_PPC_DAWR=y -CONFIG_PPC_DOORBELL=y -CONFIG_PPC_E500MC=y -# CONFIG_PPC_EARLY_DEBUG is not set -CONFIG_PPC_EPAPR_HV_PIC=y -CONFIG_PPC_FPU=y -CONFIG_PPC_FSL_BOOK3E=y -CONFIG_PPC_INDIRECT_PCI=y -# CONFIG_PPC_IRQ_SOFT_MASK_DEBUG is not set -CONFIG_PPC_MMU_NOHASH=y -CONFIG_PPC_MSI_BITMAP=y -CONFIG_PPC_OF_BOOT_TRAMPOLINE=y -CONFIG_PPC_PAGE_SHIFT=12 -# CONFIG_PPC_PTDUMP is not set -# CONFIG_PPC_QEMU_E500 is not set -CONFIG_PPC_QUEUED_SPINLOCKS=y -CONFIG_PPC_SMP_MUXED_IPI=y -CONFIG_PPC_UDBG_16550=y -CONFIG_PPC_WERROR=y -CONFIG_PPS=y -CONFIG_PTE_64BIT=y -CONFIG_QORIQ_CPUFREQ=y -CONFIG_QORIQ_THERMAL=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -# CONFIG_RAVE_SP_CORE is not set -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -# CONFIG_SCOM_DEBUGFS is not set -CONFIG_SCSI=y -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_DEV_BUS=y -CONFIG_SERIAL_DEV_CTRL_TTYPORT=y -CONFIG_SERIAL_FSL_LINFLEXUART=y -CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y -CONFIG_SERIAL_FSL_LPUART=y -CONFIG_SERIAL_FSL_LPUART_CONSOLE=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SG_POOL=y -CONFIG_SLUB_DEBUG=y -CONFIG_SMP=y -CONFIG_SOC_BUS=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_FSL_ESPI=y -CONFIG_SPI_MASTER=y -CONFIG_SRCU=y -CONFIG_SWIOTLB=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_SUPPORTS_HUGETLBFS=y -CONFIG_TARGET_CPU_BOOL=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_OF=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_THREAD_SHIFT=14 -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -# CONFIG_UACCE is not set -# CONFIG_UCLAMP_TASK is not set -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_EHCI_FSL=y -CONFIG_USB_EHCI_HCD=y -# CONFIG_USB_EHCI_HCD_PLATFORM is not set -CONFIG_USB_STORAGE=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_UAS=y -CONFIG_VGA_CONSOLE=y -CONFIG_VIRT_CPU_ACCOUNTING=y -CONFIG_VIRT_CPU_ACCOUNTING_NATIVE=y -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -CONFIG_WATCHDOG_CORE=y -# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set -CONFIG_XPS=y -CONFIG_ZLIB_DEFLATE=y From f1aa8f34ffe3af1bd922ca8e92f8726dd883b7f9 Mon Sep 17 00:00:00 2001 From: Stijn Tintel Date: Mon, 9 Jan 2023 17:24:21 +0200 Subject: [PATCH 15/51] sunxi: switch to kernel 5.15 The testing kernel has been available since early 2022, and is running fine for several people. Let's switch to it by default. Signed-off-by: Stijn Tintel Tested-by: Karl Palsson Tested-by: Jan-Niklas Burfeind --- target/linux/sunxi/Makefile | 3 +- target/linux/sunxi/config-5.10 | 511 ------------------ .../062-add-sun8i-h3-zeropi-support.patch | 79 --- ...0-sunxi-h3-add-support-for-nanopi-r1.patch | 186 ------- ...nxi-h5-add-support-for-nanopi-r1s-h5.patch | 230 -------- ...OF-node-for-USB-eth-on-NanoPi-R1S-H5.patch | 30 - ...angepi_pc2_usb_otg_to_host_key_power.patch | 20 - ...a64-sopine-Add-Sopine-flash-partitio.patch | 46 -- ...ner-a64-olinuxino-add-status-LED-ali.patch | 32 -- ...lwinner-nanopi-r1s-h5-add-status-LED.patch | 35 -- ...m64-dts-orangepi-one-plus-enable-PWM.patch | 10 - ...m64-dts-enable-wifi-on-pine64-boards.patch | 72 --- 12 files changed, 1 insertion(+), 1253 deletions(-) delete mode 100644 target/linux/sunxi/config-5.10 delete mode 100644 target/linux/sunxi/patches-5.10/062-add-sun8i-h3-zeropi-support.patch delete mode 100644 target/linux/sunxi/patches-5.10/100-sunxi-h3-add-support-for-nanopi-r1.patch delete mode 100644 target/linux/sunxi/patches-5.10/101-sunxi-h5-add-support-for-nanopi-r1s-h5.patch delete mode 100644 target/linux/sunxi/patches-5.10/102-sunxi-add-OF-node-for-USB-eth-on-NanoPi-R1S-H5.patch delete mode 100644 target/linux/sunxi/patches-5.10/301-orangepi_pc2_usb_otg_to_host_key_power.patch delete mode 100644 target/linux/sunxi/patches-5.10/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch delete mode 100644 target/linux/sunxi/patches-5.10/430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch delete mode 100644 target/linux/sunxi/patches-5.10/431-arm64-dts-allwinner-nanopi-r1s-h5-add-status-LED.patch delete mode 100644 target/linux/sunxi/patches-5.10/442-arm64-dts-orangepi-one-plus-enable-PWM.patch delete mode 100644 target/linux/sunxi/patches-5.10/450-arm64-dts-enable-wifi-on-pine64-boards.patch diff --git a/target/linux/sunxi/Makefile b/target/linux/sunxi/Makefile index 2a031c2df1c..7a2b8af05a9 100644 --- a/target/linux/sunxi/Makefile +++ b/target/linux/sunxi/Makefile @@ -10,8 +10,7 @@ BOARDNAME:=Allwinner A1x/A20/A3x/H3/H5/R40 FEATURES:=fpu usb ext4 display rootfs-part rtc squashfs SUBTARGETS:=cortexa8 cortexa7 cortexa53 -KERNEL_PATCHVER:=5.10 -KERNEL_TESTING_PATCHVER:=5.15 +KERNEL_PATCHVER:=5.15 KERNELNAME:=zImage dtbs diff --git a/target/linux/sunxi/config-5.10 b/target/linux/sunxi/config-5.10 deleted file mode 100644 index caac9e14361..00000000000 --- a/target/linux/sunxi/config-5.10 +++ /dev/null @@ -1,511 +0,0 @@ -# CONFIG_AHCI_SUNXI is not set -CONFIG_ALIGNMENT_TRAP=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_NR_GPIO=416 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUNXI=y -CONFIG_ARCH_SUNXI_MC_SMP=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM=y -# CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM is not set -CONFIG_ARM_APPENDED_DTB=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_ATAG_DTB_COMPAT=y -CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y -CONFIG_ARM_CCI=y -CONFIG_ARM_CCI400_COMMON=y -CONFIG_ARM_CCI400_PORT_CTRL=y -CONFIG_ARM_CPU_SUSPEND=y -CONFIG_ARM_CRYPTO=y -CONFIG_ARM_ERRATA_643719=y -CONFIG_ARM_GIC=y -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_HEAVY_MB=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -CONFIG_ARM_LPAE=y -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -CONFIG_ARM_PSCI=y -CONFIG_ARM_PSCI_FW=y -CONFIG_ARM_THUMB=y -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_ATA=y -CONFIG_ATAGS=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_AXP20X_POWER=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_PWM=y -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_PM=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BOUNCE=y -CONFIG_CACHE_L2X0=y -CONFIG_CAN=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLK_SUNXI=y -CONFIG_CLK_SUNXI_CLOCKS=y -CONFIG_CLK_SUNXI_PRCM_SUN6I=y -CONFIG_CLK_SUNXI_PRCM_SUN8I=y -CONFIG_CLK_SUNXI_PRCM_SUN9I=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_COMMON_CLK=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONFIGFS_FS=y -CONFIG_CONNECTOR=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_COREDUMP=y -CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y -CONFIG_CPUFREQ_DT=y -CONFIG_CPUFREQ_DT_PLATDEV=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THERMAL=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRC16=y -CONFIG_CRC_T10DIF=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRCT10DIF=y -CONFIG_CRYPTO_CRCT10DIF_ARM_CE=y -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_DEV_ALLWINNER=y -CONFIG_CRYPTO_DEV_SUN4I_SS=y -CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y -# CONFIG_CRYPTO_DEV_SUN8I_CE is not set -# CONFIG_CRYPTO_DEV_SUN8I_SS is not set -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_LIB_DES=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_SHA1=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -CONFIG_DEBUG_MEMORY_INIT=y -CONFIG_DMADEVICES=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_OPS=y -CONFIG_DMA_REMAP=y -CONFIG_DMA_SUN4I=y -CONFIG_DMA_SUN6I=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DNOTIFY=y -CONFIG_DTC=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_DVB_CORE=y -CONFIG_DWMAC_GENERIC=y -# CONFIG_DWMAC_SUN8I is not set -CONFIG_DWMAC_SUNXI=y -CONFIG_DYNAMIC_DEBUG=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_ELF_CORE=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_EXT4_FS=y -CONFIG_EXTCON=y -CONFIG_F2FS_FS=y -CONFIG_FAT_FS=y -CONFIG_FB=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_CMDLINE=y -CONFIG_FB_FOREIGN_ENDIAN=y -CONFIG_FB_LITTLE_ENDIAN=y -CONFIG_FB_MODE_HELPERS=y -CONFIG_FB_SIMPLE=y -CONFIG_FB_TILEBLITTING=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FONT_8x16=y -CONFIG_FONT_8x8=y -CONFIG_FONT_SUPPORT=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -CONFIG_FRAME_WARN=2048 -CONFIG_FREEZER=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FS_POSIX_ACL=y -CONFIG_FW_CACHE=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_VDSO_32=y -CONFIG_GLOB=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_SMP=y -CONFIG_HIGHMEM=y -CONFIG_HIGHPTE=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HWMON=y -CONFIG_HW_CONSOLE=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_TIMERIOMEM=y -CONFIG_HZ_FIXED=0 -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_COMPAT=y -CONFIG_I2C_HELPER_AUTO=y -CONFIG_I2C_MV64XXX=y -CONFIG_I2C_SUN6I_P2WI=y -CONFIG_IIO=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INPUT=y -CONFIG_INPUT_AXP20X_PEK=y -CONFIG_INPUT_KEYBOARD=y -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_KALLSYMS=y -CONFIG_KEYBOARD_SUN4I_LRADC=y -CONFIG_KSM=y -CONFIG_LCD_CLASS_DEVICE=y -CONFIG_LCD_PLATFORM=y -CONFIG_LEDS_GPIO=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LOGO=y -CONFIG_LOGO_LINUX_CLUT224=y -CONFIG_LOGO_LINUX_MONO=y -CONFIG_LOGO_LINUX_VGA16=y -CONFIG_MACH_SUN4I=y -CONFIG_MACH_SUN5I=y -CONFIG_MACH_SUN6I=y -CONFIG_MACH_SUN7I=y -CONFIG_MACH_SUN8I=y -CONFIG_MACH_SUN9I=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MDIO_SUN4I=y -CONFIG_MEDIA_ANALOG_TV_SUPPORT=y -CONFIG_MEDIA_ATTACH=y -CONFIG_MEDIA_CAMERA_SUPPORT=y -CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y -CONFIG_MEDIA_PLATFORM_SUPPORT=y -CONFIG_MEDIA_RADIO_SUPPORT=y -CONFIG_MEDIA_SDR_SUPPORT=y -CONFIG_MEDIA_SUPPORT=y -CONFIG_MEDIA_TEST_SUPPORT=y -CONFIG_MEDIA_TUNER=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_AXP20X=y -CONFIG_MFD_AXP20X_I2C=y -CONFIG_MFD_AXP20X_RSB=y -CONFIG_MFD_CORE=y -CONFIG_MFD_SUN6I_PRCM=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_SUNXI=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIT_FW=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEON=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_PTP_CLASSIFY=y -CONFIG_NET_VENDOR_ALLWINNER=y -CONFIG_NLS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NO_HZ=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=8 -CONFIG_NVMEM=y -CONFIG_NVMEM_SUNXI_SID=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_OUTER_CACHE=y -CONFIG_OUTER_CACHE_SYNC=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PAGE_POOL=y -CONFIG_PCS_XPCS=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=3 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_PHY_SUN4I_USB=y -# CONFIG_PHY_SUN50I_USB3 is not set -# CONFIG_PHY_SUN6I_MIPI_DPHY is not set -CONFIG_PHY_SUN9I_USB=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_AXP209=y -CONFIG_PINCTRL_SUN4I_A10=y -# CONFIG_PINCTRL_SUN50I_A100 is not set -# CONFIG_PINCTRL_SUN50I_A100_R is not set -# CONFIG_PINCTRL_SUN50I_A64 is not set -# CONFIG_PINCTRL_SUN50I_A64_R is not set -# CONFIG_PINCTRL_SUN50I_H5 is not set -# CONFIG_PINCTRL_SUN50I_H6 is not set -# CONFIG_PINCTRL_SUN50I_H6_R is not set -CONFIG_PINCTRL_SUN5I=y -CONFIG_PINCTRL_SUN6I_A31=y -CONFIG_PINCTRL_SUN6I_A31_R=y -CONFIG_PINCTRL_SUN8I_A23=y -CONFIG_PINCTRL_SUN8I_A23_R=y -CONFIG_PINCTRL_SUN8I_A33=y -CONFIG_PINCTRL_SUN8I_A83T=y -CONFIG_PINCTRL_SUN8I_A83T_R=y -CONFIG_PINCTRL_SUN8I_H3=y -CONFIG_PINCTRL_SUN8I_H3_R=y -CONFIG_PINCTRL_SUN8I_V3S=y -CONFIG_PINCTRL_SUN9I_A80=y -CONFIG_PINCTRL_SUN9I_A80_R=y -CONFIG_PINCTRL_SUNXI=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_OPP=y -CONFIG_PM_SLEEP=y -CONFIG_PM_SLEEP_SMP=y -CONFIG_POWER_RESET=y -CONFIG_POWER_SUPPLY=y -CONFIG_PPS=y -CONFIG_PRINTK_TIME=y -CONFIG_PROC_EVENTS=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_PTP_1588_CLOCK=y -CONFIG_PWM=y -CONFIG_PWM_SUN4I=y -CONFIG_PWM_SYSFS=y -CONFIG_RATIONAL=y -CONFIG_REALTEK_PHY=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_IRQ=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGMAP_SPI=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_AXP20X=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_GPIO=y -CONFIG_REGULATOR_SY8106A=y -CONFIG_RELAY=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RESET_SIMPLE=y -CONFIG_RESET_SUNXI=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SATA_HOST=y -CONFIG_SATA_PMP=y -CONFIG_SCSI=y -CONFIG_SDIO_UART=y -CONFIG_SECURITYFS=y -CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y -CONFIG_SERIAL_8250_DW=y -CONFIG_SERIAL_8250_DWLIB=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_NR_UARTS=8 -CONFIG_SERIAL_8250_RUNTIME_UARTS=8 -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SERIO=y -CONFIG_SERIO_SERPORT=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SMP_ON_UP=y -CONFIG_SND=y -CONFIG_SND_COMPRESS_OFFLOAD=y -CONFIG_SND_JACK=y -CONFIG_SND_JACK_INPUT_DEV=y -CONFIG_SND_PCM=y -CONFIG_SND_SIMPLE_CARD=y -CONFIG_SND_SIMPLE_CARD_UTILS=y -CONFIG_SND_SOC=y -CONFIG_SND_SOC_I2C_AND_SPI=y -# CONFIG_SND_SUN4I_I2S is not set -# CONFIG_SND_SUN4I_SPDIF is not set -# CONFIG_SND_SUN8I_CODEC is not set -# CONFIG_SND_SUN8I_CODEC_ANALOG is not set -CONFIG_SOUND=y -CONFIG_SOUND_OSS_CORE=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_SUN4I=y -CONFIG_SPI_SUN6I=y -CONFIG_SRCU=y -CONFIG_STMMAC_ETH=y -CONFIG_STMMAC_PLATFORM=y -# CONFIG_STMMAC_SELFTESTS is not set -CONFIG_SUN4I_A10_CCU=y -# CONFIG_SUN4I_EMAC is not set -CONFIG_SUN4I_TIMER=y -CONFIG_SUN5I_CCU=y -CONFIG_SUN5I_HSTIMER=y -CONFIG_SUN6I_A31_CCU=y -CONFIG_SUN8I_A23_CCU=y -CONFIG_SUN8I_A33_CCU=y -CONFIG_SUN8I_A83T_CCU=y -CONFIG_SUN8I_DE2_CCU=y -CONFIG_SUN8I_H3_CCU=y -CONFIG_SUN8I_R40_CCU=y -CONFIG_SUN8I_R_CCU=y -CONFIG_SUN8I_THERMAL=y -CONFIG_SUN8I_V3S_CCU=y -CONFIG_SUN9I_A80_CCU=y -CONFIG_SUNXI_CCU=y -CONFIG_SUNXI_RSB=y -CONFIG_SUNXI_SRAM=y -CONFIG_SUNXI_WATCHDOG=y -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -CONFIG_SWIOTLB=y -CONFIG_SWPHY=y -CONFIG_SWP_EMULATE=y -CONFIG_SYSFS_SYSCALL=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_SYS_SUPPORTS_HUGETLBFS=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_OF=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_TOUCHSCREEN_PROPERTIES=y -CONFIG_TOUCHSCREEN_SUN4I=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNWINDER_ARM=y -CONFIG_USB=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -# CONFIG_USB_AUDIO is not set -CONFIG_USB_COMMON=y -CONFIG_USB_DWC2=y -CONFIG_USB_DWC2_HOST=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_HCD_PLATFORM=y -CONFIG_USB_GADGET=y -CONFIG_USB_NET_DRIVERS=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PLATFORM=y -CONFIG_USB_ROLE_SWITCH=y -CONFIG_USB_STORAGE=y -CONFIG_USB_SUPPORT=y -CONFIG_USERIO=y -CONFIG_USE_OF=y -CONFIG_VFAT_FS=y -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_VHOST=y -CONFIG_VHOST_IOTLB=y -CONFIG_VHOST_NET=y -# CONFIG_VIDEO_SUN4I_CSI is not set -# CONFIG_VIDEO_SUN6I_CSI is not set -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_VT_CONSOLE_SLEEP=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_WATCHDOG_CORE=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 diff --git a/target/linux/sunxi/patches-5.10/062-add-sun8i-h3-zeropi-support.patch b/target/linux/sunxi/patches-5.10/062-add-sun8i-h3-zeropi-support.patch deleted file mode 100644 index 3dd37fedbaf..00000000000 --- a/target/linux/sunxi/patches-5.10/062-add-sun8i-h3-zeropi-support.patch +++ /dev/null @@ -1,79 +0,0 @@ ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -1204,6 +1204,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ - sun8i-h3-orangepi-zero-plus2.dtb \ - sun8i-h3-rervision-dvk.dtb \ - sun8i-h3-emlid-neutis-n5h3-devboard.dtb \ -+ sun8i-h3-zeropi.dtb \ - sun8i-r16-bananapi-m2m.dtb \ - sun8i-r16-nintendo-nes-classic.dtb \ - sun8i-r16-nintendo-super-nes-classic.dtb \ ---- /dev/null -+++ b/arch/arm/boot/dts/sun8i-h3-zeropi.dts -@@ -0,0 +1,66 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+#include "sun8i-h3-nanopi.dtsi" -+ -+/ { -+ model = "FriendlyElec ZeroPi"; -+ compatible = "friendlyarm,zeropi", "allwinner,sun8i-h3"; -+ -+ aliases { -+ ethernet0 = &emac; -+ }; -+ -+ reg_gmac_3v3: gmac-3v3 { -+ compatible = "regulator-fixed"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gmac_power_pin_nanopi>; -+ regulator-name = "gmac-3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <100000>; -+ enable-active-high; -+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; -+ }; -+}; -+ -+&ehci0 { -+ status = "okay"; -+}; -+ -+&ohci0 { -+ status = "okay"; -+}; -+ -+&pio { -+ gmac_power_pin_nanopi: gmac_power_pin@0 { -+ pins = "PD6"; -+ function = "gpio_out"; -+ }; -+}; -+ -+&external_mdio { -+ ext_rgmii_phy: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <7>; -+ }; -+}; -+ -+&emac { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emac_rgmii_pins>; -+ phy-supply = <®_gmac_3v3>; -+ phy-handle = <&ext_rgmii_phy>; -+ phy-mode = "rgmii"; -+ -+ allwinner,leds-active-low; -+ status = "okay"; -+}; -+ -+&usb_otg { -+ status = "okay"; -+ dr_mode = "peripheral"; -+}; -+ -+&usbphy { -+ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ -+}; diff --git a/target/linux/sunxi/patches-5.10/100-sunxi-h3-add-support-for-nanopi-r1.patch b/target/linux/sunxi/patches-5.10/100-sunxi-h3-add-support-for-nanopi-r1.patch deleted file mode 100644 index cbdf5ed3d4d..00000000000 --- a/target/linux/sunxi/patches-5.10/100-sunxi-h3-add-support-for-nanopi-r1.patch +++ /dev/null @@ -1,186 +0,0 @@ -From 5aee0b1272cd5b42933ef629d66b677669e2e8d2 Mon Sep 17 00:00:00 2001 -From: Jayantajit Gogoi -Date: Mon, 12 Oct 2020 05:24:51 +0000 -Subject: [PATCH] sunxi: add support for friendlyarm nanopi r1 - -Signed-off-by: Jayantajit Gogoi ---- - .../devicetree/bindings/arm/sunxi.yaml | 5 + - arch/arm/boot/dts/Makefile | 1 + - arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts | 146 ++++++++++++++++++ - 3 files changed, 152 insertions(+) - create mode 100644 arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts - ---- a/Documentation/devicetree/bindings/arm/sunxi.yaml -+++ b/Documentation/devicetree/bindings/arm/sunxi.yaml -@@ -251,6 +251,11 @@ properties: - - const: friendlyarm,nanopi-neo-plus2 - - const: allwinner,sun50i-h5 - -+ - description: FriendlyARM NanoPi R1 -+ items: -+ - const: friendlyarm,nanopi-r1 -+ - const: allwinner,sun8i-h3 -+ - - description: Gemei G9 Tablet - items: - - const: gemei,g9 ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -1194,6 +1194,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ - sun8i-h3-nanopi-m1-plus.dtb \ - sun8i-h3-nanopi-neo.dtb \ - sun8i-h3-nanopi-neo-air.dtb \ -+ sun8i-h3-nanopi-r1.dtb \ - sun8i-h3-orangepi-2.dtb \ - sun8i-h3-orangepi-lite.dtb \ - sun8i-h3-orangepi-one.dtb \ ---- /dev/null -+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts -@@ -0,0 +1,146 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (C) 2019 Igor Pecovnik -+ * Copyright (C) 2020 Jayantajit Gogoi -+ */ -+ -+/* NanoPi R1 is based on the NanoPi-H3 design from FriendlyARM */ -+#include "sun8i-h3-nanopi.dtsi" -+ -+/ { -+ model = "FriendlyARM NanoPi R1"; -+ compatible = "friendlyarm,nanopi-r1", "allwinner,sun8i-h3"; -+ -+ reg_gmac_3v3: gmac-3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "gmac-3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <100000>; -+ enable-active-high; -+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ vdd_cpux: gpio-regulator { -+ compatible = "regulator-gpio"; -+ pinctrl-names = "default"; -+ regulator-name = "vdd-cpux"; -+ regulator-type = "voltage"; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-min-microvolt = <1100000>; -+ regulator-max-microvolt = <1300000>; -+ regulator-ramp-delay = <50>; -+ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; -+ gpios-states = <0x1>; -+ states = <1100000 0x0 -+ 1300000 0x1>; -+ }; -+ -+ wifi_pwrseq: wifi_pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ pinctrl-names = "default"; -+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; -+ }; -+ -+ leds { -+ /delete-node/ pwr; -+ status { -+ label = "nanopi:red:status"; -+ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "heartbeat"; -+ }; -+ -+ wan { -+ label = "nanopi:green:wan"; -+ gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ lan { -+ label = "nanopi:green:lan"; -+ gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+ -+ r_gpio_keys { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sw_r_npi>; -+ -+ /delete-node/ k1; -+ reset { -+ label = "reset"; -+ linux,code = ; -+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vdd_cpux>; -+}; -+ -+&ehci1 { -+ status = "okay"; -+}; -+ -+&ehci2 { -+ status = "okay"; -+}; -+ -+&emac { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emac_rgmii_pins>; -+ phy-supply = <®_gmac_3v3>; -+ phy-handle = <&ext_rgmii_phy>; -+ phy-mode = "rgmii"; -+ status = "okay"; -+}; -+ -+&external_mdio { -+ ext_rgmii_phy: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <7>; -+ }; -+}; -+ -+&mmc1 { -+ vmmc-supply = <®_vcc3v3>; -+ vqmmc-supply = <®_vcc3v3>; -+ mmc-pwrseq = <&wifi_pwrseq>; -+ bus-width = <4>; -+ non-removable; -+ status = "okay"; -+ -+ sdio_wifi: sdio_wifi@1 { -+ reg = <1>; -+ compatible = "brcm,bcm4329-fmac"; -+ interrupt-parent = <&pio>; -+ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-names = "host-wake"; -+ }; -+}; -+ -+&mmc2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc2_8bit_pins>; -+ vmmc-supply = <®_vcc3v3>; -+ vqmmc-supply = <®_vcc3v3>; -+ bus-width = <8>; -+ non-removable; -+ status = "okay"; -+}; -+ -+&ohci1 { -+ status = "okay"; -+}; -+ -+&ohci2 { -+ status = "okay"; -+}; -+ -+&r_pio { -+ sw_r_npi: key_pins { -+ pins = "PL3"; -+ function = "gpio_in"; -+ }; -+}; diff --git a/target/linux/sunxi/patches-5.10/101-sunxi-h5-add-support-for-nanopi-r1s-h5.patch b/target/linux/sunxi/patches-5.10/101-sunxi-h5-add-support-for-nanopi-r1s-h5.patch deleted file mode 100644 index e0c25bcb532..00000000000 --- a/target/linux/sunxi/patches-5.10/101-sunxi-h5-add-support-for-nanopi-r1s-h5.patch +++ /dev/null @@ -1,230 +0,0 @@ -From 9962cb9be2db877c232aaf00db40125c0d7bf4bc Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Mon, 17 May 2021 00:35:22 +0800 -Subject: [PATCH] arm64: dts: allwinner: h5: Add NanoPi R1S H5 support - -The NanoPi R1S H5 is a open source board made by FriendlyElec. -It has the following features: - -- Allwinner H5, Quad-core Cortex-A53 -- 512MB DDR3 RAM -- 10/100/1000M Ethernet x 2 -- RTL8189ETV WiFi 802.11b/g/n -- USB 2.0 host port (A) -- MicroSD Slot -- Serial Debug Port -- 5V 2A DC power-supply - -Signed-off-by: Chukun Pan -Signed-off-by: Maxime Ripard -Link: https://lore.kernel.org/r/20210516163523.9484-2-amadeus@jmu.edu.cn ---- - arch/arm64/boot/dts/allwinner/Makefile | 1 + - .../dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts | 195 ++++++++++++++++++ - 2 files changed, 196 insertions(+) - create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts - ---- a/arch/arm64/boot/dts/allwinner/Makefile -+++ b/arch/arm64/boot/dts/allwinner/Makefile -@@ -24,6 +24,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-li - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h5-cc.dtb - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb -+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-r1s-h5.dtb - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts -@@ -0,0 +1,191 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (C) 2021 Chukun Pan -+ * -+ * Based on sun50i-h5-nanopi-neo-plus2.dts, which is: -+ * Copyright (C) 2017 Antony Antony -+ * Copyright (C) 2016 ARM Ltd. -+ */ -+ -+/dts-v1/; -+#include "sun50i-h5.dtsi" -+#include "sun50i-h5-cpu-opp.dtsi" -+ -+#include -+#include -+ -+/ { -+ model = "FriendlyARM NanoPi R1S H5"; -+ compatible = "friendlyarm,nanopi-r1s-h5", "allwinner,sun50i-h5"; -+ -+ aliases { -+ ethernet0 = &emac; -+ ethernet1 = &rtl8189etv; -+ serial0 = &uart0; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ sys { -+ label = "nanopi:red:sys"; -+ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "heartbeat"; -+ }; -+ -+ lan { -+ label = "nanopi:green:lan"; -+ gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ wan { -+ label = "nanopi:green:wan"; -+ gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+ -+ r-gpio-keys { -+ compatible = "gpio-keys"; -+ -+ reset { -+ label = "reset"; -+ linux,code = ; -+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ reg_gmac_3v3: gmac-3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "gmac-3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <100000>; -+ enable-active-high; -+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ reg_vcc3v3: vcc3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ -+ reg_usb0_vbus: usb0-vbus { -+ compatible = "regulator-fixed"; -+ regulator-name = "usb0-vbus"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ enable-active-high; -+ gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ -+ status = "okay"; -+ }; -+ -+ vdd_cpux: gpio-regulator { -+ compatible = "regulator-gpio"; -+ regulator-name = "vdd-cpux"; -+ regulator-type = "voltage"; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-min-microvolt = <1100000>; -+ regulator-max-microvolt = <1300000>; -+ regulator-ramp-delay = <50>; /* 4ms */ -+ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; -+ gpios-states = <0x1>; -+ states = <1100000 0x0>, <1300000 0x1>; -+ }; -+ -+ wifi_pwrseq: wifi_pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ -+ post-power-on-delay-ms = <200>; -+ }; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vdd_cpux>; -+}; -+ -+&ehci1 { -+ status = "okay"; -+}; -+ -+&ehci2 { -+ status = "okay"; -+}; -+ -+&emac { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emac_rgmii_pins>; -+ phy-supply = <®_gmac_3v3>; -+ phy-handle = <&ext_rgmii_phy>; -+ phy-mode = "rgmii-id"; -+ status = "okay"; -+}; -+ -+&external_mdio { -+ ext_rgmii_phy: ethernet-phy@7 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <7>; -+ }; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ eeprom@51 { -+ compatible = "microchip,24c02"; -+ reg = <0x51>; -+ pagesize = <16>; -+ }; -+}; -+ -+&mmc0 { -+ vmmc-supply = <®_vcc3v3>; -+ bus-width = <4>; -+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ -+ status = "okay"; -+}; -+ -+&mmc1 { -+ vmmc-supply = <®_vcc3v3>; -+ vqmmc-supply = <®_vcc3v3>; -+ mmc-pwrseq = <&wifi_pwrseq>; -+ bus-width = <4>; -+ non-removable; -+ status = "okay"; -+ -+ rtl8189etv: sdio_wifi@1 { -+ reg = <1>; -+ }; -+}; -+ -+&ohci1 { -+ status = "okay"; -+}; -+ -+&ohci2 { -+ status = "okay"; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pa_pins>; -+ status = "okay"; -+}; -+ -+&usb_otg { -+ dr_mode = "peripheral"; -+ status = "okay"; -+}; -+ -+&usbphy { -+ /* USB Type-A port's VBUS is always on */ -+ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ -+ usb0_vbus-supply = <®_usb0_vbus>; -+ status = "okay"; -+}; diff --git a/target/linux/sunxi/patches-5.10/102-sunxi-add-OF-node-for-USB-eth-on-NanoPi-R1S-H5.patch b/target/linux/sunxi/patches-5.10/102-sunxi-add-OF-node-for-USB-eth-on-NanoPi-R1S-H5.patch deleted file mode 100644 index e14311aa641..00000000000 --- a/target/linux/sunxi/patches-5.10/102-sunxi-add-OF-node-for-USB-eth-on-NanoPi-R1S-H5.patch +++ /dev/null @@ -1,30 +0,0 @@ -From a896bc1d79e3c00f0aacfe225499d811775616f3 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Sun, 10 Oct 2021 21:50:17 +0800 -Subject: [PATCH] arm64: allwinner: add OF node for USB eth on NanoPi R1S H5 - -This adds the OF node for the USB3 ethernet adapter on the FriendlyARM -NanoPi R1S H5. Add the correct value for the RTL8153 LED configuration -register to match the blink behavior of the other port on the device. - -Signed-off-by: Chukun Pan ---- - arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts -@@ -112,6 +112,13 @@ - - &ehci1 { - status = "okay"; -+ -+ usb-eth@1 { -+ compatible = "realtek,rtl8153"; -+ reg = <1>; -+ -+ realtek,led-data = <0x78>; -+ }; - }; - - &ehci2 { diff --git a/target/linux/sunxi/patches-5.10/301-orangepi_pc2_usb_otg_to_host_key_power.patch b/target/linux/sunxi/patches-5.10/301-orangepi_pc2_usb_otg_to_host_key_power.patch deleted file mode 100644 index 427911c94e6..00000000000 --- a/target/linux/sunxi/patches-5.10/301-orangepi_pc2_usb_otg_to_host_key_power.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts -@@ -59,7 +59,7 @@ - - sw4 { - label = "sw4"; -- linux,code = ; -+ linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - wakeup-source; - }; -@@ -220,7 +220,7 @@ - }; - - &usb_otg { -- dr_mode = "otg"; -+ dr_mode = "host"; - status = "okay"; - }; - diff --git a/target/linux/sunxi/patches-5.10/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch b/target/linux/sunxi/patches-5.10/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch deleted file mode 100644 index a8dfcd9dbce..00000000000 --- a/target/linux/sunxi/patches-5.10/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 7d87d3dafc4b1ea5659eb71ee6c5fd5308490d1f Mon Sep 17 00:00:00 2001 -From: Oskari Lemmela -Date: Mon, 31 Dec 2018 07:44:49 +0200 -Subject: [PATCH] arm64: allwinner: a64-sopine: Add Sopine flash partitions. - -First 896kB to u-boot. Enough space for SPL, u-boot and ATF. -Next 128kB to u-boot environment and rest to firmware. - -Firmware partition is compatible FIT image dynamic splitting. - -Signed-off-by: Oskari Lemmela ---- - .../boot/dts/allwinner/sun50i-a64-sopine.dtsi | 22 +++++++++++++++++++ - 1 file changed, 22 insertions(+) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi -@@ -58,6 +58,28 @@ - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "u-boot"; -+ reg = <0x000000 0x0E0000>; -+ }; -+ -+ partition@e0000 { -+ label = "u-boot-env"; -+ reg = <0x0E0000 0x020000>; -+ }; -+ -+ partition@100000 { -+ compatible = "denx,fit"; -+ label = "firmware"; -+ reg = <0x100000 0xF00000>; -+ }; -+ }; - }; - }; - diff --git a/target/linux/sunxi/patches-5.10/430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch b/target/linux/sunxi/patches-5.10/430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch deleted file mode 100644 index 68ec333e374..00000000000 --- a/target/linux/sunxi/patches-5.10/430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Petr=20=C5=A0tetiar?= -Date: Thu, 26 Mar 2020 10:09:19 +0100 -Subject: [PATCH] arm64: dts: allwinner: a64: olinuxino: add status LED aliases -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Petr Štetiar - ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts -@@ -15,6 +15,10 @@ - aliases { - ethernet0 = &emac; - serial0 = &uart0; -+ led-boot = &led_user; -+ led-failsafe = &led_user; -+ led-running = &led_user; -+ led-upgrade = &led_user; - }; - - chosen { -@@ -35,7 +39,7 @@ - leds { - compatible = "gpio-leds"; - -- led-0 { -+ led_user: led-0 { - label = "a64-olinuxino:red:user"; - gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */ - }; diff --git a/target/linux/sunxi/patches-5.10/431-arm64-dts-allwinner-nanopi-r1s-h5-add-status-LED.patch b/target/linux/sunxi/patches-5.10/431-arm64-dts-allwinner-nanopi-r1s-h5-add-status-LED.patch deleted file mode 100644 index 4a429c746e6..00000000000 --- a/target/linux/sunxi/patches-5.10/431-arm64-dts-allwinner-nanopi-r1s-h5-add-status-LED.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 1845163a052efac124f00656eb72f38947630a42 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Sun, 10 Oct 2021 21:50:18 +0800 -Subject: [PATCH] arm64: dts: allwinner: NanoPi R1S H5: add status LED aliases - -Use the SYS LED on the casing for showing system status. - -Signed-off-by: Chukun Pan ---- - arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts | 7 ++++++- - 1 file changed, 6 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts -@@ -22,6 +22,11 @@ - ethernet0 = &emac; - ethernet1 = &rtl8189etv; - serial0 = &uart0; -+ -+ led-boot = &led_sys; -+ led-failsafe = &led_sys; -+ led-running = &led_sys; -+ led-upgrade = &led_sys; - }; - - chosen { -@@ -31,7 +36,7 @@ - leds { - compatible = "gpio-leds"; - -- sys { -+ led_sys: sys { - label = "nanopi:red:sys"; - gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; diff --git a/target/linux/sunxi/patches-5.10/442-arm64-dts-orangepi-one-plus-enable-PWM.patch b/target/linux/sunxi/patches-5.10/442-arm64-dts-orangepi-one-plus-enable-PWM.patch deleted file mode 100644 index 76a73ee1f0d..00000000000 --- a/target/linux/sunxi/patches-5.10/442-arm64-dts-orangepi-one-plus-enable-PWM.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts -@@ -41,3 +41,7 @@ - reg = <1>; - }; - }; -+ -+&pwm { -+ status = "okay"; -+}; diff --git a/target/linux/sunxi/patches-5.10/450-arm64-dts-enable-wifi-on-pine64-boards.patch b/target/linux/sunxi/patches-5.10/450-arm64-dts-enable-wifi-on-pine64-boards.patch deleted file mode 100644 index 3876852c2bc..00000000000 --- a/target/linux/sunxi/patches-5.10/450-arm64-dts-enable-wifi-on-pine64-boards.patch +++ /dev/null @@ -1,72 +0,0 @@ ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts -@@ -42,6 +42,11 @@ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; -+ -+ wifi_pwrseq: wifi_pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ -+ }; - }; - - &ac_power_supply { -@@ -102,6 +107,21 @@ - reg = <1>; - }; - }; -+ -+&mmc1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc1_pins>; -+ vmmc-supply = <®_dldo4>; -+ vqmmc-supply = <®_eldo1>; -+ mmc-pwrseq = <&wifi_pwrseq>; -+ bus-width = <4>; -+ non-removable; -+ status = "okay"; -+ -+ rtl8723cs: wifi@1 { -+ reg = <1>; -+ }; -+}; - - &mmc2 { - pinctrl-names = "default"; ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts -@@ -35,6 +35,11 @@ - }; - }; - }; -+ -+ wifi_pwrseq: wifi_pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ -+ }; - }; - - &codec { -@@ -124,6 +129,21 @@ - status = "okay"; - }; - -+&mmc1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc1_pins>; -+ vmmc-supply = <®_dldo4>; -+ vqmmc-supply = <®_eldo1>; -+ mmc-pwrseq = <&wifi_pwrseq>; -+ bus-width = <4>; -+ non-removable; -+ status = "okay"; -+ -+ rtl8723cs: wifi@1 { -+ reg = <1>; -+ }; -+}; -+ - &ohci0 { - status = "okay"; - }; From 35135842ca8b633c0f8ee32b70eee92d918345d6 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Mon, 9 Jan 2023 14:23:23 +0100 Subject: [PATCH 16/51] include/prereq.mk: add RequireCHeader helper Add RequireCHeader helper that will try to compile a fake c program with the requested header included. This is useful to check if a specific header is present in the system without checking for the specific path. This is a generilized version of the current ncurses test. Signed-off-by: Christian Marangi --- include/prereq.mk | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/prereq.mk b/include/prereq.mk index 0033535e782..d34539ec304 100644 --- a/include/prereq.mk +++ b/include/prereq.mk @@ -63,6 +63,18 @@ define RequireHeader $$(eval $$(call Require,$(1),$(2))) endef +# 1: header to test +# 2: failure message +# 3: optional compile time test +# 4: optional link library test (example -lncurses) +define RequireCHeader + define Require/$(1) + echo 'int main(int argc, char **argv) { $(3); return 0; }' | gcc -include $(1) -x c -o $(TMP_DIR)/a.out - $(4) + endef + + $$(eval $$(call Require,$(1),$(2))) +endef + define CleanupPython2 define Require/python2-cleanup if [ -f "$(STAGING_DIR_HOST)/bin/python" ] && \ From 848b3445fba43b8ae2e1a299418551d8bc8cd400 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Mon, 9 Jan 2023 18:40:00 +0100 Subject: [PATCH 17/51] prereq-build: use RequireCHeader test for ncurses prereq RequireCHeader is a generilized version of the ncurses prereq test. Use that indetad. Signed-off-by: Christian Marangi --- include/prereq-build.mk | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/include/prereq-build.mk b/include/prereq-build.mk index 9c4ef547ad0..7959890eb52 100644 --- a/include/prereq-build.mk +++ b/include/prereq-build.mk @@ -49,10 +49,9 @@ $(eval $(call TestHostCommand,working-g++, \ g++ -x c++ -o $(TMP_DIR)/a.out - -lstdc++ && \ $(TMP_DIR)/a.out)) -$(eval $(call TestHostCommand,ncurses, \ +$(eval $(call RequireCHeader,ncurses.h, \ Please install ncurses. (Missing libncurses.so or ncurses.h), \ - echo 'int main(int argc, char **argv) { initscr(); return 0; }' | \ - gcc -include ncurses.h -x c -o $(TMP_DIR)/a.out - -lncurses)) + initscr(), -lncurses)) $(eval $(call SetupHostCommand,git,Please install Git (git-core) >= 1.7.12.2, \ git --exec-path | xargs -I % -- grep -q -- --recursive %/git-submodule, \ From 36bc306ae61133a4e7907f0648b8cf8ad8587619 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Mon, 9 Jan 2023 14:24:49 +0100 Subject: [PATCH 18/51] prereq-build: add extra check for elfutils required header While testing tools build on an alpine image it was found that with musl libc some header are missing for elfutils tool. Add extra prereq-build check to make sure these header are present in the system to correctly compile host tools. Signed-off-by: Christian Marangi --- include/prereq-build.mk | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/prereq-build.mk b/include/prereq-build.mk index 7959890eb52..7b345ebbaa4 100644 --- a/include/prereq-build.mk +++ b/include/prereq-build.mk @@ -204,6 +204,18 @@ $(eval $(call SetupHostCommand,which,Please install 'which', \ /bin/which which, \ which which)) +$(eval $(call RequireCHeader,argp.h, \ + Missing argp.h Please install the argp-standalone package if musl libc)) + +$(eval $(call RequireCHeader,fts.h, \ + Missing fts.h Please install the musl-fts-dev package if musl libc)) + +$(eval $(call RequireCHeader,obstack.h, \ + Missing obstack.h Please install the musl-obstack-dev package if musl libc)) + +$(eval $(call RequireCHeader,libintl.h, \ + Missing libintl.h Please install the musl-libintl package if musl libc)) + $(STAGING_DIR_HOST)/bin/mkhash: $(SCRIPT_DIR)/mkhash.c mkdir -p $(dir $@) $(CC) -O2 -I$(TOPDIR)/tools/include -o $@ $< From 9988832c464054847c22188e65b22cf0f86f25e6 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Mon, 9 Jan 2023 21:19:02 +0100 Subject: [PATCH 19/51] toolchain/gcc: fix broken gcc version selection Config evaluation require default with if to be put before the generic default config with no condition. Putting the default config before any conditional default results in always selecting the non conditional one. This results in the version be hardcoded to gcc 12 even if gcc 11 is selected in the Advanced build options. Fix this by putting the gcc 12 default option as last after ANY conditional default config. Fixes: d9de5252a44e ("toolchain/gcc: switch to version 12 by default") Signed-off-by: Christian Marangi --- toolchain/gcc/Config.version | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/toolchain/gcc/Config.version b/toolchain/gcc/Config.version index 6202ca732f1..7d4bedfbe99 100644 --- a/toolchain/gcc/Config.version +++ b/toolchain/gcc/Config.version @@ -4,5 +4,5 @@ config GCC_VERSION_11 config GCC_VERSION string - default "12.2.0" default "11.3.0" if GCC_VERSION_11 + default "12.2.0" From 3606fcce0ba2ede47c3fe47b0b62033df2d231dd Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Thu, 10 Nov 2022 17:44:13 +0100 Subject: [PATCH 20/51] automake: use STAGING_DIR_HOST in relocatable patch Instead of using STAGING_DIR and then go up one dir with '../' use directly STAGING_DIR_HOST env variable. This should produce cleaner symbolic links. Signed-off-by: Christian Marangi --- tools/automake/Makefile | 2 +- tools/automake/patches/000-relocatable.patch | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/tools/automake/Makefile b/tools/automake/Makefile index a1121f1378c..85ccc0ded4d 100644 --- a/tools/automake/Makefile +++ b/tools/automake/Makefile @@ -25,7 +25,7 @@ HOST_CONFIGURE_VARS += \ am_cv_prog_PERL_ithreads=no define Host/Configure - (cd $(HOST_BUILD_DIR); $(AM_TOOL_PATHS) STAGING_DIR="" ./bootstrap) + (cd $(HOST_BUILD_DIR); $(AM_TOOL_PATHS) STAGING_DIR_HOST="" ./bootstrap) $(call Host/Configure/Default) endef diff --git a/tools/automake/patches/000-relocatable.patch b/tools/automake/patches/000-relocatable.patch index d05b25e61c2..02382ba8c86 100644 --- a/tools/automake/patches/000-relocatable.patch +++ b/tools/automake/patches/000-relocatable.patch @@ -5,7 +5,7 @@ our $VERSION = '@VERSION@'; our $RELEASE_YEAR = '@RELEASE_YEAR@'; -our $libdir = '@datadir@/@PACKAGE@-@APIVERSION@'; -+our $libdir = $ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/share/@PACKAGE@-@APIVERSION@' : '@datadir@/@PACKAGE@-@APIVERSION@'; ++our $libdir = $ENV{'STAGING_DIR_HOST'} ? $ENV{'STAGING_DIR_HOST'} . '/share/@PACKAGE@-@APIVERSION@' : '@datadir@/@PACKAGE@-@APIVERSION@'; our $perl_threads = 0; # We need at least this version for CLONE support. @@ -30,7 +30,7 @@ BEGIN { - @Aclocal::perl_libdirs = ('@datadir@/@PACKAGE@-@APIVERSION@') -+ @Aclocal::perl_libdirs = ($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/share/@PACKAGE@-@APIVERSION@' : '@datadir@/@PACKAGE@-@APIVERSION@') ++ @Aclocal::perl_libdirs = ($ENV{'STAGING_DIR_HOST'} ? $ENV{'STAGING_DIR_HOST'} . '/share/@PACKAGE@-@APIVERSION@' : '@datadir@/@PACKAGE@-@APIVERSION@') unless @Aclocal::perl_libdirs; unshift @INC, @Aclocal::perl_libdirs; } @@ -40,8 +40,8 @@ my @user_includes = (); -my @automake_includes = ("@datadir@/aclocal-$APIVERSION"); -my @system_includes = ('@datadir@/aclocal'); -+my @automake_includes = ($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . "/../host/share/aclocal-$APIVERSION" : "@datadir@/aclocal-$APIVERSION"); -+my @system_includes = ($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/share/aclocal' : '@datadir@/aclocal'); ++my @automake_includes = ($ENV{'STAGING_DIR_HOST'} ? $ENV{'STAGING_DIR_HOST'} . "/share/aclocal-$APIVERSION" : "@datadir@/aclocal-$APIVERSION"); ++my @system_includes = ($ENV{'STAGING_DIR_HOST'} ? $ENV{'STAGING_DIR_HOST'} . '/share/aclocal' : '@datadir@/aclocal'); # Whether we should copy M4 file in $user_includes[0]. my $install = 0; @@ -66,7 +66,7 @@ BEGIN { - @Automake::perl_libdirs = ('@datadir@/@PACKAGE@-@APIVERSION@') -+ @Automake::perl_libdirs = ($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/share/@PACKAGE@-@APIVERSION@' : '@datadir@/@PACKAGE@-@APIVERSION@') ++ @Automake::perl_libdirs = ($ENV{'STAGING_DIR_HOST'} ? $ENV{'STAGING_DIR_HOST'} . '/share/@PACKAGE@-@APIVERSION@' : '@datadir@/@PACKAGE@-@APIVERSION@') unless @Automake::perl_libdirs; unshift @INC, @Automake::perl_libdirs; From b344da76403a0bc01fd310bc2726842a89add146 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Thu, 10 Nov 2022 17:47:06 +0100 Subject: [PATCH 21/51] autoconf: use STAGING_DIR_HOST in relocatable patch Instead of using STAGING_DIR and then go up one dir with '../' use directly STAGING_DIR_HOST env variable. This should produce cleaner symbolic links. Signed-off-by: Christian Marangi --- tools/autoconf/patches/000-relocatable.patch | 40 ++++++++++---------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/tools/autoconf/patches/000-relocatable.patch b/tools/autoconf/patches/000-relocatable.patch index 12e94ae9a15..a935671ce8a 100644 --- a/tools/autoconf/patches/000-relocatable.patch +++ b/tools/autoconf/patches/000-relocatable.patch @@ -6,7 +6,7 @@ { - my $pkgdatadir = $ENV{'autom4te_perllibdir'} || '@pkgdatadir@'; + my $pkgdatadir = $ENV{'autom4te_perllibdir'} || -+ ($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/share/autoconf' : '@pkgdatadir@'); ++ ($ENV{'STAGING_DIR_HOST'} ? $ENV{'STAGING_DIR_HOST'} . '/share/autoconf' : '@pkgdatadir@'); unshift @INC, "$pkgdatadir"; # Override SHELL. On DJGPP SHELL may not be set to a shell @@ -15,7 +15,7 @@ # Lib files. -my $autom4te = $ENV{'AUTOM4TE'} || '@bindir@/@autom4te-name@'; -+my $autom4te = $ENV{'AUTOM4TE'} || ($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/bin/@autom4te-name@' : '@bindir@/@autom4te-name@'); ++my $autom4te = $ENV{'AUTOM4TE'} || ($ENV{'STAGING_DIR_HOST'} ? $ENV{'STAGING_DIR_HOST'} . '/bin/@autom4te-name@' : '@bindir@/@autom4te-name@'); local $config_h; my $config_h_in; my @prepend_include; @@ -41,7 +41,7 @@ { - my $pkgdatadir = $ENV{'autom4te_perllibdir'} || '@pkgdatadir@'; + my $pkgdatadir = $ENV{'autom4te_perllibdir'} || -+ ($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/share/autoconf' : '@pkgdatadir@'); ++ ($ENV{'STAGING_DIR_HOST'} ? $ENV{'STAGING_DIR_HOST'} . '/share/autoconf' : '@pkgdatadir@'); unshift @INC, $pkgdatadir; # Override SHELL. On DJGPP SHELL may not be set to a shell @@ -51,7 +51,7 @@ # Data directory. -my $pkgdatadir = $ENV{'AC_MACRODIR'} || '@pkgdatadir@'; +my $pkgdatadir = $ENV{'AC_MACRODIR'} || -+ ($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/share/autoconf' : '@pkgdatadir@'); ++ ($ENV{'STAGING_DIR_HOST'} ? $ENV{'STAGING_DIR_HOST'} . '/share/autoconf' : '@pkgdatadir@'); # $LANGUAGE{LANGUAGE} -- Automatic options for LANGUAGE. my %language; @@ -60,7 +60,7 @@ # $M4. -my $m4 = $ENV{"M4"} || '@M4@'; -+my $m4 = $ENV{"M4"} || ($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/bin/m4' : '@M4@'); ++my $m4 = $ENV{"M4"} || ($ENV{'STAGING_DIR_HOST'} ? $ENV{'STAGING_DIR_HOST'} . '/bin/m4' : '@M4@'); # Some non-GNU m4's don't reject the --help option, so give them /dev/null. fatal "need GNU m4 1.4 or later: $m4" if system "$m4 --help &1 | grep reload-state >/dev/null"; @@ -69,9 +69,9 @@ my @words = shellwords ($_); my $type = shift @words; + -+ if ($ENV{'STAGING_DIR'}) ++ if ($ENV{'STAGING_DIR_HOST'}) + { -+ @words = map { s!^@pkgdatadir@!$ENV{'STAGING_DIR'}/../host/share/autoconf!; $_ } @words; ++ @words = map { s!^@pkgdatadir@!$ENV{'STAGING_DIR_HOST'}/share/autoconf!; $_ } @words; + } + if ($type eq 'begin-language:') @@ -99,7 +99,7 @@ { - my $pkgdatadir = $ENV{'autom4te_perllibdir'} || '@pkgdatadir@'; + my $pkgdatadir = $ENV{'autom4te_perllibdir'} || -+ ($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/share/autoconf' : '@pkgdatadir@'); ++ ($ENV{'STAGING_DIR_HOST'} ? $ENV{'STAGING_DIR_HOST'} . '/share/autoconf' : '@pkgdatadir@'); unshift @INC, $pkgdatadir; # Override SHELL. On DJGPP SHELL may not be set to a shell @@ -110,9 +110,9 @@ -my $autoconf = $ENV{'AUTOCONF'} || '@bindir@/@autoconf-name@'; -my $autoheader = $ENV{'AUTOHEADER'} || '@bindir@/@autoheader-name@'; -my $autom4te = $ENV{'AUTOM4TE'} || '@bindir@/@autom4te-name@'; -+my $autoconf = $ENV{'AUTOCONF'} || ($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/bin/@autoconf-name@' : '@bindir@/@autoconf-name@'); -+my $autoheader = $ENV{'AUTOHEADER'} || ($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/bin/@autoheader-name@' : '@bindir@/@autoheader-name@'); -+my $autom4te = $ENV{'AUTOM4TE'} || ($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/bin/@autom4te-name@' : '@bindir@/@autom4te-name@'); ++my $autoconf = $ENV{'AUTOCONF'} || ($ENV{'STAGING_DIR_HOST'} ? $ENV{'STAGING_DIR_HOST'} . '/bin/@autoconf-name@' : '@bindir@/@autoconf-name@'); ++my $autoheader = $ENV{'AUTOHEADER'} || ($ENV{'STAGING_DIR_HOST'} ? $ENV{'STAGING_DIR_HOST'} . '/bin/@autoheader-name@' : '@bindir@/@autoheader-name@'); ++my $autom4te = $ENV{'AUTOM4TE'} || ($ENV{'STAGING_DIR_HOST'} ? $ENV{'STAGING_DIR_HOST'} . '/bin/@autom4te-name@' : '@bindir@/@autom4te-name@'); my $automake = $ENV{'AUTOMAKE'} || 'automake'; my $aclocal = $ENV{'ACLOCAL'} || 'aclocal'; my $libtoolize = $ENV{'LIBTOOLIZE'} || 'libtoolize'; @@ -134,7 +134,7 @@ { - my $pkgdatadir = $ENV{'autom4te_perllibdir'} || '@pkgdatadir@'; + my $pkgdatadir = $ENV{'autom4te_perllibdir'} || -+ ($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/share/autoconf' : '@pkgdatadir@'); ++ ($ENV{'STAGING_DIR_HOST'} ? $ENV{'STAGING_DIR_HOST'} . '/share/autoconf' : '@pkgdatadir@'); unshift @INC, $pkgdatadir; # Override SHELL. On DJGPP SHELL may not be set to a shell @@ -143,11 +143,11 @@ # Autoconf and lib files. -my $autom4te = $ENV{'AUTOM4TE'} || '@bindir@/@autom4te-name@'; -+my $autom4te = $ENV{'AUTOM4TE'} || ($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/bin/@autom4te-name@' : '@bindir@/@autom4te-name@'); ++my $autom4te = $ENV{'AUTOM4TE'} || ($ENV{'STAGING_DIR_HOST'} ? $ENV{'STAGING_DIR_HOST'} . '/bin/@autom4te-name@' : '@bindir@/@autom4te-name@'); my $autoconf = "$autom4te --language=autoconf"; my @prepend_include; -my @include = ('@pkgdatadir@'); -+my @include = ($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/share/autoconf' : '@pkgdatadir@'); ++my @include = ($ENV{'STAGING_DIR_HOST'} ? $ENV{'STAGING_DIR_HOST'} . '/share/autoconf' : '@pkgdatadir@'); # $help # ----- @@ -169,7 +169,7 @@ { - my $pkgdatadir = $ENV{'autom4te_perllibdir'} || '@pkgdatadir@'; + my $pkgdatadir = $ENV{'autom4te_perllibdir'} || -+ ($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/share/autoconf' : '@pkgdatadir@'); ++ ($ENV{'STAGING_DIR_HOST'} ? $ENV{'STAGING_DIR_HOST'} . '/share/autoconf' : '@pkgdatadir@'); unshift @INC, $pkgdatadir; # Override SHELL. On DJGPP SHELL may not be set to a shell @@ -178,11 +178,11 @@ # We need to find m4sugar. my @prepend_include; -my @include = ('@pkgdatadir@'); -+my @include = ($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/share/autoconf' : '@pkgdatadir@'); ++my @include = ($ENV{'STAGING_DIR_HOST'} ? $ENV{'STAGING_DIR_HOST'} . '/share/autoconf' : '@pkgdatadir@'); my $force = 0; # m4. -my $m4 = $ENV{"M4"} || '@M4@'; -+my $m4 = $ENV{"M4"} || ($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/bin/m4' : '@M4@'); ++my $m4 = $ENV{"M4"} || ($ENV{'STAGING_DIR_HOST'} ? $ENV{'STAGING_DIR_HOST'} . '/bin/m4' : '@M4@'); # $HELP @@ -208,7 +208,7 @@ { - my $pkgdatadir = $ENV{'autom4te_perllibdir'} || '@pkgdatadir@'; + my $pkgdatadir = $ENV{'autom4te_perllibdir'} || -+ ($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/share/autoconf' : '@pkgdatadir@'); ++ ($ENV{'STAGING_DIR_HOST'} ? $ENV{'STAGING_DIR_HOST'} . '/share/autoconf' : '@pkgdatadir@'); unshift @INC, $pkgdatadir; # Override SHELL. On DJGPP SHELL may not be set to a shell @@ -219,8 +219,8 @@ # Variables. -: ${AUTOM4TE='@bindir@/@autom4te-name@'} -+if test -n "$STAGING_DIR"; then -+ : ${AUTOM4TE="$STAGING_DIR/../host/bin/@autom4te-name@"} ++if test -n "$STAGING_DIR_HOST"; then ++ : ${AUTOM4TE="$STAGING_DIR_HOST/bin/@autom4te-name@"} +else + : ${AUTOM4TE='@bindir@/@autom4te-name@'} +fi From 7b56ca399a539600090f1710f9225f706dd5b2eb Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Thu, 10 Nov 2022 17:48:54 +0100 Subject: [PATCH 22/51] libtool: use STAGING_DIR_HOST in relocatable patch Instead of using STAGING_DIR and then go up one dir with '../' use directly STAGING_DIR_HOST env variable. This should produce cleaner symbolic links. Signed-off-by: Christian Marangi --- tools/libtool/patches/000-relocatable.patch | 50 ++++++++++----------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/tools/libtool/patches/000-relocatable.patch b/tools/libtool/patches/000-relocatable.patch index 6d1651be317..996e6445be9 100644 --- a/tools/libtool/patches/000-relocatable.patch +++ b/tools/libtool/patches/000-relocatable.patch @@ -13,11 +13,11 @@ : ${MV="mv -f"} : ${RM="rm -f"} -: ${SED="@SED@"} -+if test -n "$STAGING_DIR"; then -+ : ${EGREP="$STAGING_DIR/../host/bin/grep -E"} -+ : ${FGREP="$STAGING_DIR/../host/bin/grep -F"} -+ : ${GREP="$STAGING_DIR/../host/bin/grep"} -+ : ${SED="$STAGING_DIR/../host/bin/sed"} ++if test -n "$STAGING_DIR_HOST"; then ++ : ${EGREP="$STAGING_DIR_HOST/bin/grep -E"} ++ : ${FGREP="$STAGING_DIR_HOST/bin/grep -F"} ++ : ${GREP="$STAGING_DIR_HOST/bin/grep"} ++ : ${SED="$STAGING_DIR_HOST/bin/sed"} +else + : ${EGREP="@EGREP@"} + : ${FGREP="@FGREP@"} @@ -42,11 +42,11 @@ : ${MV="mv -f"} : ${RM="rm -f"} -: ${SED="@SED@"} -+if test -n "$STAGING_DIR"; then -+ : ${EGREP="$STAGING_DIR/../host/bin/grep -E"} -+ : ${FGREP="$STAGING_DIR/../host/bin/grep -F"} -+ : ${GREP="$STAGING_DIR/../host/bin/grep"} -+ : ${SED="$STAGING_DIR/../host/bin/sed"} ++if test -n "$STAGING_DIR_HOST"; then ++ : ${EGREP="$STAGING_DIR_HOST/bin/grep -E"} ++ : ${FGREP="$STAGING_DIR_HOST/bin/grep -F"} ++ : ${GREP="$STAGING_DIR_HOST/bin/grep"} ++ : ${SED="$STAGING_DIR_HOST/bin/sed"} +else + : ${EGREP="@EGREP@"} + : ${FGREP="@FGREP@"} @@ -64,11 +64,11 @@ - pkgdatadir=@pkgdatadir@ - pkgltdldir=@pkgdatadir@ - aclocaldir=@aclocaldir@ -+ if test -n "$STAGING_DIR"; then -+ datadir="$STAGING_DIR/../host/share" -+ pkgdatadir="$STAGING_DIR/../host/share/libtool" -+ pkgltdldir="$STAGING_DIR/../host/share/libtool" -+ aclocaldir="$STAGING_DIR/../host/share/aclocal" ++ if test -n "$STAGING_DIR_HOST"; then ++ datadir="$STAGING_DIR_HOST/share" ++ pkgdatadir="$STAGING_DIR_HOST/share/libtool" ++ pkgltdldir="$STAGING_DIR_HOST/share/libtool" ++ aclocaldir="$STAGING_DIR_HOST/share/aclocal" + else + datadir=@datadir@ + pkgdatadir=@pkgdatadir@ @@ -88,11 +88,11 @@ - pkgdatadir=@pkgdatadir@ - pkgltdldir=@pkgdatadir@ - aclocaldir=@aclocaldir@ -+ if test -n "$STAGING_DIR"; then -+ datadir="$STAGING_DIR/../host/share" -+ pkgdatadir="$STAGING_DIR/../host/share/libtool" -+ pkgltdldir="$STAGING_DIR/../host/share/libtool" -+ aclocaldir="$STAGING_DIR/../host/share/aclocal" ++ if test -n "$STAGING_DIR_HOST"; then ++ datadir="$STAGING_DIR_HOST/share" ++ pkgdatadir="$STAGING_DIR_HOST/share/libtool" ++ pkgltdldir="$STAGING_DIR_HOST/share/libtool" ++ aclocaldir="$STAGING_DIR_HOST/share/aclocal" + else + datadir=@datadir@ + pkgdatadir=@pkgdatadir@ @@ -111,7 +111,7 @@ - _LT_DECL([LTCC], [CC], [1], [A C compiler])dnl -_LT_DECL([LTCFLAGS], [CFLAGS], [1], [LTCC compiler flags])dnl -+_LT_DECL([LTCFLAGS], [CFLAGS], ["-O2 -I\${STAGING_DIR:-$STAGING_DIR}/../host/include"], [LTCC compiler flags])dnl ++_LT_DECL([LTCFLAGS], [CFLAGS], ["-O2 -I\${STAGING_DIR_HOST:-$STAGING_DIR_HOST}/include"], [LTCC compiler flags])dnl _LT_TAGDECL([CC], [compiler], [1], [A language specific compiler])dnl _LT_TAGDECL([with_gcc], [GCC], [0], [Is the compiler the GNU compiler?])dnl @@ -122,9 +122,9 @@ -_LT_DECL([], [GREP], [1], [A grep program that handles long lines]) -_LT_DECL([], [EGREP], [1], [An ERE matcher]) -_LT_DECL([], [FGREP], [1], [A literal string matcher]) -+_LT_DECL([], [GREP], ["\${STAGING_DIR:-$STAGING_DIR}/../host/bin/grep"], [A grep program that handles long lines]) -+_LT_DECL([], [EGREP], ["\${STAGING_DIR:-$STAGING_DIR}/../host/bin/grep -E"], [An ERE matcher]) -+_LT_DECL([], [FGREP], ["\${STAGING_DIR:-$STAGING_DIR}/../host/bin/grep -F"], [A literal string matcher]) ++_LT_DECL([], [GREP], ["\${STAGING_DIR_HOST:-$STAGING_DIR_HOST}/bin/grep"], [A grep program that handles long lines]) ++_LT_DECL([], [EGREP], ["\${STAGING_DIR_HOST:-$STAGING_DIR_HOST}/bin/grep -E"], [An ERE matcher]) ++_LT_DECL([], [FGREP], ["\${STAGING_DIR_HOST:-$STAGING_DIR_HOST}/bin/grep -F"], [A literal string matcher]) dnl Non-bleeding-edge autoconf doesn't subst GREP, so do it here too AC_SUBST([GREP]) ]) @@ -135,7 +135,7 @@ -test -z "$SED" && SED=sed Xsed="$SED -e 1s/^X//" -_LT_DECL([], [SED], [1], [A sed program that does not truncate output]) -+_LT_DECL([], [SED], ["\${STAGING_DIR:-$STAGING_DIR}/../host/bin/sed"], [A sed program that does not truncate output]) ++_LT_DECL([], [SED], ["\${STAGING_DIR_HOST:-$STAGING_DIR_HOST}/bin/sed"], [A sed program that does not truncate output]) _LT_DECL([], [Xsed], ["\$SED -e 1s/^X//"], [Sed that helps us avoid accidentally triggering echo(1) options like -n]) ])# _LT_DECL_SED From e854dcaef37cdb59109448889e9da9358591748a Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Fri, 2 Dec 2022 20:13:06 +0100 Subject: [PATCH 23/51] tools/mpc: use STAGING_DIR_HOST instead of hardcoding default Use STAGING_DIR_HOST to reference the staging dir for host tools instead of hardcoding it to the default location. Signed-off-by: Christian Marangi --- tools/mpc/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/mpc/Makefile b/tools/mpc/Makefile index 5c196a27ef7..97e94291cb7 100644 --- a/tools/mpc/Makefile +++ b/tools/mpc/Makefile @@ -22,8 +22,8 @@ unexport CFLAGS HOST_CONFIGURE_ARGS += \ --enable-static \ --disable-shared \ - --with-mpfr=$(TOPDIR)/staging_dir/host \ - --with-gmp=$(TOPDIR)/staging_dir/host + --with-mpfr=$(STAGING_DIR_HOST) \ + --with-gmp=$(STAGING_DIR_HOST) define Host/Uninstall -$(call Host/Compile/Default,uninstall) From 9590e1155d7a9dcfc30ba0a95ccea43698bab8cf Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Fri, 2 Dec 2022 20:31:38 +0100 Subject: [PATCH 24/51] toolchain/gcc: use STAGING_DIR_HOST instead of hardcoding default Use STAGING_DIR_HOST to reference staging host directory instead of hardcoding it to default path. Signed-off-by: Christian Marangi --- toolchain/gcc/common.mk | 8 ++++---- toolchain/gcc/final/Makefile | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/toolchain/gcc/common.mk b/toolchain/gcc/common.mk index ea2e2634b69..7eae855eea4 100644 --- a/toolchain/gcc/common.mk +++ b/toolchain/gcc/common.mk @@ -72,7 +72,7 @@ ifdef CONFIG_INSTALL_GCCGO endif ifdef CONFIG_GCC_USE_GRAPHITE - GRAPHITE_CONFIGURE:= --with-isl=$(TOPDIR)/staging_dir/host + GRAPHITE_CONFIGURE:= --with-isl=$(STAGING_DIR_HOST) else GRAPHITE_CONFIGURE:= --without-isl --without-cloog endif @@ -106,9 +106,9 @@ GCC_CONFIGURE:= \ --with-abi=$(call qstrip,$(CONFIG_MIPS64_ABI))) \ $(if $(CONFIG_arc),--with-cpu=$(CONFIG_CPU_TYPE)) \ $(if $(CONFIG_powerpc64), $(if $(CONFIG_USE_MUSL),--with-abi=elfv2)) \ - --with-gmp=$(TOPDIR)/staging_dir/host \ - --with-mpfr=$(TOPDIR)/staging_dir/host \ - --with-mpc=$(TOPDIR)/staging_dir/host \ + --with-gmp=$(STAGING_DIR_HOST) \ + --with-mpfr=$(STAGING_DIR_HOST) \ + --with-mpc=$(STAGING_DIR_HOST) \ --disable-decimal-float \ --with-diagnostics-color=auto-if-env \ --enable-__cxa_atexit \ diff --git a/toolchain/gcc/final/Makefile b/toolchain/gcc/final/Makefile index 0315b9d1f16..049ddf61f03 100644 --- a/toolchain/gcc/final/Makefile +++ b/toolchain/gcc/final/Makefile @@ -9,7 +9,7 @@ GCC_CONFIGURE += \ --enable-threads \ --with-slibdir=$(TOOLCHAIN_DIR)/lib \ --enable-lto \ - --with-libelf=$(TOPDIR)/staging_dir/host + --with-libelf=$(STAGING_DIR_HOST) ifndef CONFIG_USE_GLIBC GCC_CONFIGURE += --disable-libsanitizer From d10e6591d1523738852dd0ab625df1f9ea7fc63c Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Fri, 2 Dec 2022 20:33:14 +0100 Subject: [PATCH 25/51] toolchain/gdb: use STAGING_DIR_HOST instead of hardcoding default Use STAGING_DIR_HOST to reference staging host directory instead of hardcoding it to default path. Signed-off-by: Christian Marangi --- toolchain/gdb/Makefile | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/toolchain/gdb/Makefile b/toolchain/gdb/Makefile index 4587c591f4e..70a4fa59026 100644 --- a/toolchain/gdb/Makefile +++ b/toolchain/gdb/Makefile @@ -30,10 +30,10 @@ HOST_CONFIGURE_ARGS = \ --build=$(GNU_HOST_NAME) \ --host=$(GNU_HOST_NAME) \ --target=$(REAL_GNU_TARGET_NAME) \ - --with-gmp=$(TOPDIR)/staging_dir/host \ - --with-mpfr=$(TOPDIR)/staging_dir/host \ - --with-mpc=$(TOPDIR)/staging_dir/host \ - --with-expat=$(TOPDIR)/staging_dir/host \ + --with-gmp=$(STAGING_DIR_HOST) \ + --with-mpfr=$(STAGING_DIR_HOST) \ + --with-mpc=$(STAGING_DIR_HOST) \ + --with-expat=$(STAGING_DIR_HOST) \ --disable-werror \ --without-uiout \ --enable-tui --disable-gdbtk --without-x \ From 2a3283643ccf77b55d67c7a3f96d40576227499c Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Fri, 2 Dec 2022 20:56:12 +0100 Subject: [PATCH 26/51] treewide: derive host and hostpkg path from STAGING_DIR STAGING_DIR may be provided from command line. We currently hardcoded STAGING_DIR_HOST and STAGING_DIR_HOSTPKG to the default location but we currently have some relocatable patch that derive the path from STAGING_DIR. Fix this and correctly derive STAGING_DIR_HOST and STAGING_DIR_HOSTPKG from STAGING_DIR. The intention is to fix inconsistency from the relocatable patch and the use of STAGING_DIR_HOST that is always hardcoded. This with a wrong configuration may end up in broken state with some host tools expecing a PATH from STAGING_DIR and others using library from the default staging_dir/host path. To save downstream project the original implementation is saved while fixing the inconsistency between patch and .mk. Signed-off-by: Christian Marangi --- Makefile | 2 +- include/scan.mk | 2 +- include/toplevel.mk | 16 ++++++++-------- rules.mk | 4 ++-- 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/Makefile b/Makefile index cbf9fa2cd13..cff0e1d8d48 100644 --- a/Makefile +++ b/Makefile @@ -15,7 +15,7 @@ $(if $(findstring $(space),$(TOPDIR)),$(error ERROR: The path to the OpenWrt dir world: DISTRO_PKG_CONFIG:=$(shell $(TOPDIR)/scripts/command_all.sh pkg-config | grep '/usr' -m 1) -export PATH:=$(TOPDIR)/staging_dir/host/bin:$(PATH) +export PATH:=$(if $(STAGING_DIR),$(abspath $(STAGING_DIR)/../host/bin),$(TOPDIR)/staging_dir/host/bin):$(PATH) ifneq ($(OPENWRT_BUILD),1) _SINGLE=export MAKEFLAGS=$(space); diff --git a/include/scan.mk b/include/scan.mk index 5032afa8186..12ef5d1dc77 100644 --- a/include/scan.mk +++ b/include/scan.mk @@ -11,7 +11,7 @@ TARGET_STAMP:=$(TMP_DIR)/info/.files-$(SCAN_TARGET).stamp FILELIST:=$(TMP_DIR)/info/.files-$(SCAN_TARGET)-$(SCAN_COOKIE) OVERRIDELIST:=$(TMP_DIR)/info/.overrides-$(SCAN_TARGET)-$(SCAN_COOKIE) -export PATH:=$(TOPDIR)/staging_dir/host/bin:$(PATH) +export PATH:=$(STAGING_DIR_HOST)/bin:$(PATH) define feedname $(if $(patsubst feeds/%,,$(1)),,$(word 2,$(subst /, ,$(1)))) diff --git a/include/toplevel.mk b/include/toplevel.mk index 455fc9c4da0..2fda7ed2239 100644 --- a/include/toplevel.mk +++ b/include/toplevel.mk @@ -51,22 +51,22 @@ path:=$(subst :,$(space),$(PATH)) path:=$(filter-out .%,$(path)) path:=$(subst $(space),:,$(path)) export PATH:=$(path) +export STAGING_DIR_HOST:=$(if $(STAGING_DIR),$(abspath $(STAGING_DIR)/../host),$(TOPDIR)/staging_dir/host) unexport TAR_OPTIONS ifeq ($(FORCE),) - .config scripts/config/conf scripts/config/mconf: staging_dir/host/.prereq-build + .config scripts/config/conf scripts/config/mconf: $(STAGING_DIR_HOST)/.prereq-build endif SCAN_COOKIE?=$(shell echo $$$$) export SCAN_COOKIE -export STAGING_DIR_HOST=$(TOPDIR)/staging_dir/host SUBMAKE:=umask 022; $(SUBMAKE) ULIMIT_FIX=_limit=`ulimit -n`; [ "$$_limit" = "unlimited" -o "$$_limit" -ge 1024 ] || ulimit -n 1024; -prepare-mk: staging_dir/host/.prereq-build FORCE ; +prepare-mk: $(STAGING_DIR_HOST)/.prereq-build FORCE ; ifdef SDK IGNORE_PACKAGES = linux @@ -75,7 +75,7 @@ endif _ignore = $(foreach p,$(IGNORE_PACKAGES),--ignore $(p)) prepare-tmpinfo: FORCE - @+$(MAKE) -r -s staging_dir/host/.prereq-build $(PREP_MK) + @+$(MAKE) -r -s $(STAGING_DIR_HOST)/.prereq-build $(PREP_MK) mkdir -p tmp/info $(_SINGLE)$(NO_TRACE_MAKE) -j1 -r -s -f include/scan.mk SCAN_TARGET="packageinfo" SCAN_DIR="package" SCAN_NAME="package" SCAN_DEPTH=5 SCAN_EXTRA="" $(_SINGLE)$(NO_TRACE_MAKE) -j1 -r -s -f include/scan.mk SCAN_TARGET="targetinfo" SCAN_DIR="target/linux" SCAN_NAME="target" SCAN_DEPTH=3 SCAN_EXTRA="" SCAN_MAKEOPTS="TARGET_BUILD=1" @@ -152,7 +152,7 @@ xconfig: scripts/config/qconf prepare-tmpinfo FORCE prepare_kernel_conf: .config toolchain/install FORCE -ifeq ($(wildcard staging_dir/host/bin/quilt),) +ifeq ($(wildcard $(STAGING_DIR_HOST)/bin/quilt),) prepare_kernel_conf: @+$(SUBMAKE) -r tools/quilt/compile else @@ -176,7 +176,7 @@ kernel_nconfig: prepare_kernel_conf kernel_xconfig: prepare_kernel_conf $(_SINGLE)$(NO_TRACE_MAKE) -C target/linux xconfig -staging_dir/host/.prereq-build: include/prereq-build.mk +$(STAGING_DIR_HOST)/.prereq-build: include/prereq-build.mk mkdir -p tmp @$(_SINGLE)$(NO_TRACE_MAKE) -j1 -r -s -f $(TOPDIR)/include/prereq-build.mk prereq 2>/dev/null || { \ echo "Prerequisite check failed. Use FORCE=1 to override."; \ @@ -199,7 +199,7 @@ else DOWNLOAD_DIRS = package/download endif -download: .config FORCE $(if $(wildcard $(TOPDIR)/staging_dir/host/bin/flock),,tools/flock/compile) +download: .config FORCE $(if $(wildcard $(STAGING_DIR_HOST)/bin/flock),,tools/flock/compile) @+$(foreach dir,$(DOWNLOAD_DIRS),$(SUBMAKE) $(dir);) clean dirclean: .config @@ -263,7 +263,7 @@ distclean: @$(_SINGLE)$(SUBMAKE) -C scripts/config clean ifeq ($(findstring v,$(DEBUG)),) - .SILENT: symlinkclean clean dirclean distclean config-clean download help tmpinfo-clean .config scripts/config/mconf scripts/config/conf menuconfig staging_dir/host/.prereq-build tmp/.prereq-package prepare-tmpinfo + .SILENT: symlinkclean clean dirclean distclean config-clean download help tmpinfo-clean .config scripts/config/mconf scripts/config/conf menuconfig $(STAGING_DIR_HOST)/.prereq-build tmp/.prereq-package prepare-tmpinfo endif .PHONY: help FORCE .NOTPARALLEL: diff --git a/rules.mk b/rules.mk index d53f673d425..3d151338af1 100644 --- a/rules.mk +++ b/rules.mk @@ -156,8 +156,8 @@ BUILD_LOG_DIR:=$(if $(call qstrip,$(CONFIG_BUILD_LOG_DIR)),$(call qstrip,$(CONFI PKG_INFO_DIR := $(STAGING_DIR)/pkginfo BUILD_DIR_HOST:=$(if $(IS_PACKAGE_BUILD),$(BUILD_DIR_BASE)/hostpkg,$(BUILD_DIR_BASE)/host) -STAGING_DIR_HOST:=$(TOPDIR)/staging_dir/host -STAGING_DIR_HOSTPKG:=$(TOPDIR)/staging_dir/hostpkg +STAGING_DIR_HOST:=$(abspath $(STAGING_DIR)/../host) +STAGING_DIR_HOSTPKG:=$(abspath $(STAGING_DIR)/../hostpkg) TARGET_PATH:=$(subst $(space),:,$(filter-out .,$(filter-out ./,$(subst :,$(space),$(PATH))))) TARGET_INIT_PATH:=$(call qstrip,$(CONFIG_TARGET_INIT_PATH)) From ee397759b65a1e2ab9a58be37c22c9b3bdfd7a7e Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Fri, 6 Jan 2023 15:23:28 +0100 Subject: [PATCH 27/51] iwinfo: update to latest Git HEAD c7b420a devices: add Qualcomm Atheros QCN6024/9024/9074 cards 5914d71 iwinfo: devices: add Qualcomm Atheros IPQ8074 WiSoC Signed-off-by: Christian Marangi --- package/network/utils/iwinfo/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/network/utils/iwinfo/Makefile b/package/network/utils/iwinfo/Makefile index 6263e47fc9e..9d562fbaf97 100644 --- a/package/network/utils/iwinfo/Makefile +++ b/package/network/utils/iwinfo/Makefile @@ -11,9 +11,9 @@ PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/iwinfo.git -PKG_SOURCE_DATE:=2022-12-15 -PKG_SOURCE_VERSION:=8d158096a9882d3090c7e180a296ca7b035b4865 -PKG_MIRROR_HASH:=c376d3f2794fcef2956c038a16b4a1a4d30082ca4f2d2b955bd191d06e78f6ec +PKG_SOURCE_DATE:=2023-01-06 +PKG_SOURCE_VERSION:=c7b420a2f33c6f1034c3e2191eba0cb0374af7b6 +PKG_MIRROR_HASH:=c5d188b2c7aa0fe987ffba8330c956670047ebf5be9a217ef647549c65002cd6 PKG_MAINTAINER:=Jo-Philipp Wich PKG_LICENSE:=GPL-2.0 From 7af1713a29441c47330f9dd1b1f1c9772af5e033 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Mon, 9 Jan 2023 22:16:26 +0100 Subject: [PATCH 28/51] prereq-build: limit argp/fts/obstack/libintl.h to Linux OS BSD based OS have different fixup and doesn't require these header. Limit these Header to Linux based OS. Fixes: 36bc306ae611 ("prereq-build: add extra check for elfutils required header") Signed-off-by: Christian Marangi --- include/prereq-build.mk | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/include/prereq-build.mk b/include/prereq-build.mk index 7b345ebbaa4..8fae92ab977 100644 --- a/include/prereq-build.mk +++ b/include/prereq-build.mk @@ -204,17 +204,19 @@ $(eval $(call SetupHostCommand,which,Please install 'which', \ /bin/which which, \ which which)) -$(eval $(call RequireCHeader,argp.h, \ +ifeq ($(HOST_OS),Linux) + $(eval $(call RequireCHeader,argp.h, \ Missing argp.h Please install the argp-standalone package if musl libc)) -$(eval $(call RequireCHeader,fts.h, \ + $(eval $(call RequireCHeader,fts.h, \ Missing fts.h Please install the musl-fts-dev package if musl libc)) -$(eval $(call RequireCHeader,obstack.h, \ + $(eval $(call RequireCHeader,obstack.h, \ Missing obstack.h Please install the musl-obstack-dev package if musl libc)) -$(eval $(call RequireCHeader,libintl.h, \ + $(eval $(call RequireCHeader,libintl.h, \ Missing libintl.h Please install the musl-libintl package if musl libc)) +endif $(STAGING_DIR_HOST)/bin/mkhash: $(SCRIPT_DIR)/mkhash.c mkdir -p $(dir $@) From 55c32a6ce385576875fa0dc2c0866196eef451e3 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Tue, 10 Jan 2023 20:10:28 +0100 Subject: [PATCH 29/51] ipq806x: refresh upstreamed patch with kernel version tag Refresh upstreamed patch with kernel version tag and replace them with the upstream version. For krait-cc patch rework them with the upstream changes. Signed-off-by: Christian Marangi --- ...syscon-and-cxo-pxo-clock-to-gcc-nod.patch} | 23 +- ...ace-gcc-PXO-with-pxo_board-fixed-cl.patch} | 25 +- ...rpmcc-missing-clocks-for-apq-ipq806.patch} | 10 +- ...-clk-rpm-convert-to-parent_data-API.patch} | 8 +- ...pss-xcc-register-it-as-clk-provider.patch} | 8 +- ...-krait-cc-convert-to-parent_data-API.patch | 264 ----------- ...t-cc-fix-never-enabled-secondary-mux.patch | 47 -- ...c-handle-secondary-mux-sourcing-out-.patch | 70 --- ...-use-devm-variant-for-clk-notifier-.patch} | 10 +- ...c-fix-wrong-parent-order-for-seconda.patch | 46 ++ ...c-also-enable-secondary-mux-and-div-.patch | 68 +++ ...c-handle-secondary-mux-sourcing-out-.patch | 48 ++ ...t-cc-convert-to-devm_clk_hw_register.patch | 104 +++++ ...-krait-cc-convert-to-parent_data-API.patch | 414 ++++++++++++++++++ ...-cc-handle-qsb-clock-defined-in-DTS.patch} | 8 +- ...it-cc-register-REAL-qsb-fixed-clock.patch} | 26 +- ...it-cc-drop-pr_info-and-use-dev_info.patch} | 26 +- ...-rework-mux-reset-logic-and-reset-h.patch} | 51 +-- ...-clk-krait-generilize-div-functions.patch} | 8 +- ...pq806x-remove-cc_register_board-for.patch} | 0 ...handle-ret-from-parse-with-codeword.patch} | 9 +- ...8064-disable-mmc-ddr-1_8v-for-sdcc1.patch} | 6 +- 22 files changed, 782 insertions(+), 497 deletions(-) rename target/linux/ipq806x/patches-5.15/{103-v5.19-02-ARM-dts-qcom-add-syscon-and-cxo-pxo-clock-to-gcc-.patch => 103-v5.19-ARM-dts-qcom-add-syscon-and-cxo-pxo-clock-to-gcc-nod.patch} (62%) rename target/linux/ipq806x/patches-5.15/{103-01-ARM-dts-qcom-replace-gcc-PXO-with-pxo_board-fixed.patch => 103-v6.0-01-ARM-dts-qcom-replace-gcc-PXO-with-pxo_board-fixed-cl.patch} (59%) rename target/linux/ipq806x/patches-5.15/{119-02-ARM-DTS-qcom-add-rpmcc-missing-clocks-for-apq-ipq.patch => 119-v6.0-02-ARM-dts-qcom-add-rpmcc-missing-clocks-for-apq-ipq806.patch} (82%) rename target/linux/ipq806x/patches-5.15/{119-03-clk-qcom-clk-rpm-convert-to-parent_data-API.patch => 119-v6.0-03-clk-qcom-clk-rpm-convert-to-parent_data-API.patch} (88%) rename target/linux/ipq806x/patches-5.15/{121-01-clk-qcom-kpss-xcc-register-it-as-clk-provider.patch => 120-v6.2-clk-qcom-kpss-xcc-register-it-as-clk-provider.patch} (84%) delete mode 100644 target/linux/ipq806x/patches-5.15/121-02-clk-qcom-krait-cc-convert-to-parent_data-API.patch delete mode 100644 target/linux/ipq806x/patches-5.15/121-06-clk-qcom-krait-cc-fix-never-enabled-secondary-mux.patch delete mode 100644 target/linux/ipq806x/patches-5.15/121-08-clk-qcom-krait-cc-handle-secondary-mux-sourcing-out-.patch rename target/linux/ipq806x/patches-5.15/{121-05-clk-qcom-krait-cc-use-devm-variant-for-clk-notifier-.patch => 121-v6.2-01-clk-qcom-krait-cc-use-devm-variant-for-clk-notifier-.patch} (64%) create mode 100644 target/linux/ipq806x/patches-5.15/121-v6.2-02-clk-qcom-krait-cc-fix-wrong-parent-order-for-seconda.patch create mode 100644 target/linux/ipq806x/patches-5.15/121-v6.2-03-clk-qcom-krait-cc-also-enable-secondary-mux-and-div-.patch create mode 100644 target/linux/ipq806x/patches-5.15/121-v6.2-04-clk-qcom-krait-cc-handle-secondary-mux-sourcing-out-.patch create mode 100644 target/linux/ipq806x/patches-5.15/121-v6.2-05-clk-qcom-krait-cc-convert-to-devm_clk_hw_register.patch create mode 100644 target/linux/ipq806x/patches-5.15/121-v6.2-06-clk-qcom-krait-cc-convert-to-parent_data-API.patch rename target/linux/ipq806x/patches-5.15/{121-03-clk-qcom-krait-cc-handle-qsb-clock-defined-in-DTS.patch => 122-01-clk-qcom-krait-cc-handle-qsb-clock-defined-in-DTS.patch} (88%) rename target/linux/ipq806x/patches-5.15/{121-04-clk-qcom-krait-cc-register-REAL-qsb-fixed-clock.patch => 122-02-clk-qcom-krait-cc-register-REAL-qsb-fixed-clock.patch} (60%) rename target/linux/ipq806x/patches-5.15/{121-07-clk-qcom-krait-cc-drop-pr_info-and-use-dev_info.patch => 122-03-clk-qcom-krait-cc-drop-pr_info-and-use-dev_info.patch} (59%) rename target/linux/ipq806x/patches-5.15/{121-09-clk-qcom-krait-cc-rework-mux-reset-logic-and-reset-h.patch => 122-04-clk-qcom-krait-cc-rework-mux-reset-logic-and-reset-h.patch} (62%) rename target/linux/ipq806x/patches-5.15/{122-02-clk-qcom-clk-krait-generilize-div-functions.patch => 122-05-clk-qcom-clk-krait-generilize-div-functions.patch} (96%) rename target/linux/ipq806x/patches-5.15/{119-04-clk-qcom-gcc-ipq806x-remove-cc_register_board-for.patch => 123-clk-qcom-gcc-ipq806x-remove-cc_register_board-for.patch} (100%) rename target/linux/ipq806x/patches-5.15/{130-mtd-nand-raw-qcom_nandc-handle-ret-from-parse-with-c.patch => 130-6.1-mtd-rawnand-qcom-handle-ret-from-parse-with-codeword.patch} (82%) rename target/linux/ipq806x/patches-5.15/{131-ARM-dts-qcom-ipq8064-disable-mmc-ddr-1_8v-for-sdcc1.patch => 131-6.2-ARM-dts-qcom-ipq8064-disable-mmc-ddr-1_8v-for-sdcc1.patch} (77%) diff --git a/target/linux/ipq806x/patches-5.15/103-v5.19-02-ARM-dts-qcom-add-syscon-and-cxo-pxo-clock-to-gcc-.patch b/target/linux/ipq806x/patches-5.15/103-v5.19-ARM-dts-qcom-add-syscon-and-cxo-pxo-clock-to-gcc-nod.patch similarity index 62% rename from target/linux/ipq806x/patches-5.15/103-v5.19-02-ARM-dts-qcom-add-syscon-and-cxo-pxo-clock-to-gcc-.patch rename to target/linux/ipq806x/patches-5.15/103-v5.19-ARM-dts-qcom-add-syscon-and-cxo-pxo-clock-to-gcc-nod.patch index db23af128f5..2ce526b6ca7 100644 --- a/target/linux/ipq806x/patches-5.15/103-v5.19-02-ARM-dts-qcom-add-syscon-and-cxo-pxo-clock-to-gcc-.patch +++ b/target/linux/ipq806x/patches-5.15/103-v5.19-ARM-dts-qcom-add-syscon-and-cxo-pxo-clock-to-gcc-nod.patch @@ -1,8 +1,8 @@ -From 9fa82f98cb85e5432060f469253adcf14fa38082 Mon Sep 17 00:00:00 2001 +From a5ba119455c77a07e05f2fe0af446c8bf43d1a00 Mon Sep 17 00:00:00 2001 From: Ansuel Smith -Date: Mon, 17 Jan 2022 21:59:39 +0100 -Subject: [PATCH v2 2/2] ARM: dts: qcom: add syscon and cxo/pxo clock to gcc - node for ipq8064 +Date: Sat, 26 Feb 2022 14:52:35 +0100 +Subject: [PATCH] ARM: dts: qcom: add syscon and cxo/pxo clock to gcc node for + ipq8064 Add syscon compatible required for tsens driver to correctly probe driver and access the reg. Also add cxo and pxo tag and declare them as gcc clock @@ -11,13 +11,15 @@ now requires them for the ipq8064 gcc driver that has now been modernized. Signed-off-by: Ansuel Smith Reviewed-by: Bjorn Andersson Reviewed-by: Stephen Boyd +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220226135235.10051-16-ansuelsmth@gmail.com --- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) + arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -298,7 +298,7 @@ +@@ -298,13 +298,13 @@ }; clocks { @@ -26,6 +28,13 @@ Reviewed-by: Stephen Boyd compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; + }; + +- pxo_board { ++ pxo_board: pxo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; @@ -736,7 +736,9 @@ }; diff --git a/target/linux/ipq806x/patches-5.15/103-01-ARM-dts-qcom-replace-gcc-PXO-with-pxo_board-fixed.patch b/target/linux/ipq806x/patches-5.15/103-v6.0-01-ARM-dts-qcom-replace-gcc-PXO-with-pxo_board-fixed-cl.patch similarity index 59% rename from target/linux/ipq806x/patches-5.15/103-01-ARM-dts-qcom-replace-gcc-PXO-with-pxo_board-fixed.patch rename to target/linux/ipq806x/patches-5.15/103-v6.0-01-ARM-dts-qcom-replace-gcc-PXO-with-pxo_board-fixed-cl.patch index 0c25062214d..d0bc34c07fa 100644 --- a/target/linux/ipq806x/patches-5.15/103-01-ARM-dts-qcom-replace-gcc-PXO-with-pxo_board-fixed.patch +++ b/target/linux/ipq806x/patches-5.15/103-v6.0-01-ARM-dts-qcom-replace-gcc-PXO-with-pxo_board-fixed-cl.patch @@ -1,8 +1,7 @@ -From 5a8aa766cedac0ceaa4beabc30e9fa62dd9f1ac1 Mon Sep 17 00:00:00 2001 +From eb9e93937756a05787977875830c0dc482cb57e0 Mon Sep 17 00:00:00 2001 From: Ansuel Smith -Date: Fri, 29 Apr 2022 14:23:16 +0200 -Subject: [PATCH v2 1/2] ARM: dts: qcom: replace gcc PXO with pxo_board fixed - clock +Date: Sat, 30 Apr 2022 07:51:17 +0200 +Subject: [PATCH] ARM: dts: qcom: replace gcc PXO with pxo_board fixed clock Replace gcc PXO phandle to pxo_board fixed clock declared in the dts. gcc driver doesn't provide PXO_SRC as it's a fixed-clock. This cause a @@ -10,22 +9,16 @@ kernel panic if any driver actually try to use it. Fixes: 40cf5c884a96 ("ARM: dts: qcom: add L2CC and RPM for IPQ8064") Signed-off-by: Ansuel Smith +Reviewed-by: Dmitry Baryshkov +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220430055118.1947-2-ansuelsmth@gmail.com --- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) + arch/arm/boot/dts/qcom-ipq8064.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -304,7 +304,7 @@ - clock-frequency = <25000000>; - }; - -- pxo_board { -+ pxo_board: pxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; -@@ -782,7 +782,7 @@ +@@ -784,7 +784,7 @@ l2cc: clock-controller@2011000 { compatible = "qcom,kpss-gcc", "syscon"; reg = <0x2011000 0x1000>; diff --git a/target/linux/ipq806x/patches-5.15/119-02-ARM-DTS-qcom-add-rpmcc-missing-clocks-for-apq-ipq.patch b/target/linux/ipq806x/patches-5.15/119-v6.0-02-ARM-dts-qcom-add-rpmcc-missing-clocks-for-apq-ipq806.patch similarity index 82% rename from target/linux/ipq806x/patches-5.15/119-02-ARM-DTS-qcom-add-rpmcc-missing-clocks-for-apq-ipq.patch rename to target/linux/ipq806x/patches-5.15/119-v6.0-02-ARM-dts-qcom-add-rpmcc-missing-clocks-for-apq-ipq806.patch index b82239f1355..f853b5d2f24 100644 --- a/target/linux/ipq806x/patches-5.15/119-02-ARM-DTS-qcom-add-rpmcc-missing-clocks-for-apq-ipq.patch +++ b/target/linux/ipq806x/patches-5.15/119-v6.0-02-ARM-dts-qcom-add-rpmcc-missing-clocks-for-apq-ipq806.patch @@ -1,14 +1,16 @@ -From 3a0cf0a2b99fb3d193d72e3804292697d73d3aab Mon Sep 17 00:00:00 2001 +From aa7fd3bb6017b343585e97a909f9b7d2fe174018 Mon Sep 17 00:00:00 2001 From: Christian Marangi -Date: Tue, 5 Jul 2022 21:29:01 +0200 -Subject: [PATCH v2 2/4] ARM: DTS: qcom: add rpmcc missing clocks for - apq/ipq8064 and msm8660 +Date: Thu, 7 Jul 2022 00:53:19 +0200 +Subject: [PATCH] ARM: dts: qcom: add rpmcc missing clocks for apq/ipq8064 and + msm8660 Add missing rpmcc pxo and cxo clock for apq8064, ipq8064 and msm8660 dtsi. Signed-off-by: Christian Marangi Reviewed-by: Dmitry Baryshkov +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220706225321.26215-3-ansuelsmth@gmail.com --- arch/arm/boot/dts/qcom-apq8064.dtsi | 2 ++ arch/arm/boot/dts/qcom-ipq8064.dtsi | 2 ++ diff --git a/target/linux/ipq806x/patches-5.15/119-03-clk-qcom-clk-rpm-convert-to-parent_data-API.patch b/target/linux/ipq806x/patches-5.15/119-v6.0-03-clk-qcom-clk-rpm-convert-to-parent_data-API.patch similarity index 88% rename from target/linux/ipq806x/patches-5.15/119-03-clk-qcom-clk-rpm-convert-to-parent_data-API.patch rename to target/linux/ipq806x/patches-5.15/119-v6.0-03-clk-qcom-clk-rpm-convert-to-parent_data-API.patch index 8398fb4ae3b..8481b636708 100644 --- a/target/linux/ipq806x/patches-5.15/119-03-clk-qcom-clk-rpm-convert-to-parent_data-API.patch +++ b/target/linux/ipq806x/patches-5.15/119-v6.0-03-clk-qcom-clk-rpm-convert-to-parent_data-API.patch @@ -1,7 +1,7 @@ -From 3d8c0e94a792ae62fa0495ac940c9850a059afc2 Mon Sep 17 00:00:00 2001 +From 129d9cd9c25041f8b8681fd6e8584fa47c385f3b Mon Sep 17 00:00:00 2001 From: Christian Marangi -Date: Tue, 5 Jul 2022 21:39:18 +0200 -Subject: [PATCH v2 3/4] clk: qcom: clk-rpm: convert to parent_data API +Date: Thu, 7 Jul 2022 00:53:20 +0200 +Subject: [PATCH] clk: qcom: clk-rpm: convert to parent_data API Convert clk-rpm driver to parent_data API. We keep the old pxo/cxo_board parent naming to keep compatibility with @@ -9,6 +9,8 @@ old DT and we use the new pxo/cxo for new implementation where these clock are defined in DTS. Signed-off-by: Christian Marangi +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220706225321.26215-4-ansuelsmth@gmail.com --- drivers/clk/qcom/clk-rpm.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/target/linux/ipq806x/patches-5.15/121-01-clk-qcom-kpss-xcc-register-it-as-clk-provider.patch b/target/linux/ipq806x/patches-5.15/120-v6.2-clk-qcom-kpss-xcc-register-it-as-clk-provider.patch similarity index 84% rename from target/linux/ipq806x/patches-5.15/121-01-clk-qcom-kpss-xcc-register-it-as-clk-provider.patch rename to target/linux/ipq806x/patches-5.15/120-v6.2-clk-qcom-kpss-xcc-register-it-as-clk-provider.patch index 5423c342423..ace313663d5 100644 --- a/target/linux/ipq806x/patches-5.15/121-01-clk-qcom-kpss-xcc-register-it-as-clk-provider.patch +++ b/target/linux/ipq806x/patches-5.15/120-v6.2-clk-qcom-kpss-xcc-register-it-as-clk-provider.patch @@ -1,12 +1,14 @@ -From 09930efb4f4fb81019ca33bf64827ce258eca66f Mon Sep 17 00:00:00 2001 +From 09be1a39e685d8c5edd471fd1cac9a8f8280d2de Mon Sep 17 00:00:00 2001 From: Christian Marangi -Date: Thu, 15 Sep 2022 01:58:12 +0200 -Subject: [PATCH 1/9] clk: qcom: kpss-xcc: register it as clk provider +Date: Tue, 8 Nov 2022 22:17:34 +0100 +Subject: [PATCH] clk: qcom: kpss-xcc: register it as clk provider krait-cc use this driver for the secondary mux. Register it as a clk provider to correctly use this clk in other drivers. Signed-off-by: Christian Marangi +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20221108211734.3707-1-ansuelsmth@gmail.com --- drivers/clk/qcom/kpss-xcc.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/target/linux/ipq806x/patches-5.15/121-02-clk-qcom-krait-cc-convert-to-parent_data-API.patch b/target/linux/ipq806x/patches-5.15/121-02-clk-qcom-krait-cc-convert-to-parent_data-API.patch deleted file mode 100644 index f257cf38216..00000000000 --- a/target/linux/ipq806x/patches-5.15/121-02-clk-qcom-krait-cc-convert-to-parent_data-API.patch +++ /dev/null @@ -1,264 +0,0 @@ -From 334c1540d5753a3c83a4cb84d935d606cb47a03b Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 17 Feb 2022 23:02:59 +0100 -Subject: [PATCH 2/9] clk: qcom: krait-cc: convert to parent_data API - -Modernize the krait-cc driver to parent-data API and refactor to drop -any use of clk_names. From Documentation all the required clocks should -be declared in DTS so fw_name can be correctly used to get the parents -for all the muxes. .name is also declared to save compatibility with old -implementation. - -Signed-off-by: Christian Marangi ---- - drivers/clk/qcom/krait-cc.c | 126 +++++++++++++++++++----------------- - 1 file changed, 66 insertions(+), 60 deletions(-) - ---- a/drivers/clk/qcom/krait-cc.c -+++ b/drivers/clk/qcom/krait-cc.c -@@ -69,21 +69,22 @@ static int krait_notifier_register(struc - return ret; - } - --static int -+static struct clk * - krait_add_div(struct device *dev, int id, const char *s, unsigned int offset) - { - struct krait_div2_clk *div; -+ static struct clk_parent_data p_data[1]; - struct clk_init_data init = { -- .num_parents = 1, -+ .num_parents = ARRAY_SIZE(p_data), - .ops = &krait_div2_clk_ops, - .flags = CLK_SET_RATE_PARENT, - }; -- const char *p_names[1]; - struct clk *clk; -+ char *parent_name; - - div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); - if (!div) -- return -ENOMEM; -+ return ERR_PTR(-ENOMEM); - - div->width = 2; - div->shift = 6; -@@ -93,43 +94,49 @@ krait_add_div(struct device *dev, int id - - init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s); - if (!init.name) -- return -ENOMEM; -+ return ERR_PTR(-ENOMEM); - -- init.parent_names = p_names; -- p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s); -- if (!p_names[0]) { -- kfree(init.name); -- return -ENOMEM; -+ init.parent_data = p_data; -+ parent_name = kasprintf(GFP_KERNEL, "hfpll%s", s); -+ if (!parent_name) { -+ clk = ERR_PTR(-ENOMEM); -+ goto err_parent_name; - } - -+ p_data[0].fw_name = parent_name; -+ p_data[0].name = parent_name; -+ - clk = devm_clk_register(dev, &div->hw); -- kfree(p_names[0]); -+ -+ kfree(parent_name); -+err_parent_name: - kfree(init.name); - -- return PTR_ERR_OR_ZERO(clk); -+ return clk; - } - --static int -+static struct clk * - krait_add_sec_mux(struct device *dev, int id, const char *s, - unsigned int offset, bool unique_aux) - { - int ret; - struct krait_mux_clk *mux; -- static const char *sec_mux_list[] = { -- "acpu_aux", -- "qsb", -+ static struct clk_parent_data sec_mux_list[2] = { -+ { .name = "qsb", .fw_name = "qsb" }, -+ {}, - }; - struct clk_init_data init = { -- .parent_names = sec_mux_list, -+ .parent_data = sec_mux_list, - .num_parents = ARRAY_SIZE(sec_mux_list), - .ops = &krait_mux_clk_ops, - .flags = CLK_SET_RATE_PARENT, - }; - struct clk *clk; -+ char *parent_name; - - mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); - if (!mux) -- return -ENOMEM; -+ return ERR_PTR(-ENOMEM); - - mux->offset = offset; - mux->lpl = id >= 0; -@@ -149,44 +156,51 @@ krait_add_sec_mux(struct device *dev, in - - init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); - if (!init.name) -- return -ENOMEM; -+ return ERR_PTR(-ENOMEM); - - if (unique_aux) { -- sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s); -- if (!sec_mux_list[0]) { -+ parent_name = kasprintf(GFP_KERNEL, "acpu%s_aux", s); -+ if (!parent_name) { - clk = ERR_PTR(-ENOMEM); - goto err_aux; - } -+ sec_mux_list[1].fw_name = parent_name; -+ sec_mux_list[1].name = parent_name; -+ } else { -+ sec_mux_list[1].name = "apu_aux"; - } - - clk = devm_clk_register(dev, &mux->hw); -+ if (IS_ERR(clk)) -+ goto err_clk; - - ret = krait_notifier_register(dev, clk, mux); - if (ret) -- goto unique_aux; -+ clk = ERR_PTR(ret); - --unique_aux: -+err_clk: - if (unique_aux) -- kfree(sec_mux_list[0]); -+ kfree(parent_name); - err_aux: - kfree(init.name); -- return PTR_ERR_OR_ZERO(clk); -+ return clk; - } - - static struct clk * --krait_add_pri_mux(struct device *dev, int id, const char *s, -- unsigned int offset) -+krait_add_pri_mux(struct device *dev, struct clk *hfpll_div, struct clk *sec_mux, -+ int id, const char *s, unsigned int offset) - { - int ret; - struct krait_mux_clk *mux; -- const char *p_names[3]; -+ static struct clk_parent_data p_data[3]; - struct clk_init_data init = { -- .parent_names = p_names, -- .num_parents = ARRAY_SIZE(p_names), -+ .parent_data = p_data, -+ .num_parents = ARRAY_SIZE(p_data), - .ops = &krait_mux_clk_ops, - .flags = CLK_SET_RATE_PARENT, - }; - struct clk *clk; -+ char *hfpll_name; - - mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); - if (!mux) -@@ -204,36 +218,29 @@ krait_add_pri_mux(struct device *dev, in - if (!init.name) - return ERR_PTR(-ENOMEM); - -- p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s); -- if (!p_names[0]) { -+ hfpll_name = kasprintf(GFP_KERNEL, "hfpll%s", s); -+ if (!hfpll_name) { - clk = ERR_PTR(-ENOMEM); -- goto err_p0; -+ goto err_hfpll; - } - -- p_names[1] = kasprintf(GFP_KERNEL, "hfpll%s_div", s); -- if (!p_names[1]) { -- clk = ERR_PTR(-ENOMEM); -- goto err_p1; -- } -+ p_data[0].fw_name = hfpll_name; -+ p_data[0].name = hfpll_name; - -- p_names[2] = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); -- if (!p_names[2]) { -- clk = ERR_PTR(-ENOMEM); -- goto err_p2; -- } -+ p_data[1].hw = __clk_get_hw(hfpll_div); -+ p_data[2].hw = __clk_get_hw(sec_mux); - - clk = devm_clk_register(dev, &mux->hw); -+ if (IS_ERR(clk)) -+ goto err_clk; - - ret = krait_notifier_register(dev, clk, mux); - if (ret) -- goto err_p3; --err_p3: -- kfree(p_names[2]); --err_p2: -- kfree(p_names[1]); --err_p1: -- kfree(p_names[0]); --err_p0: -+ clk = ERR_PTR(ret); -+ -+err_clk: -+ kfree(hfpll_name); -+err_hfpll: - kfree(init.name); - return clk; - } -@@ -241,11 +248,10 @@ err_p0: - /* id < 0 for L2, otherwise id == physical CPU number */ - static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux) - { -- int ret; - unsigned int offset; - void *p = NULL; - const char *s; -- struct clk *clk; -+ struct clk *hfpll_div, *sec_mux, *clk; - - if (id >= 0) { - offset = 0x4501 + (0x1000 * id); -@@ -257,19 +263,19 @@ static struct clk *krait_add_clks(struct - s = "_l2"; - } - -- ret = krait_add_div(dev, id, s, offset); -- if (ret) { -- clk = ERR_PTR(ret); -+ hfpll_div = krait_add_div(dev, id, s, offset); -+ if (IS_ERR(hfpll_div)) { -+ clk = hfpll_div; - goto err; - } - -- ret = krait_add_sec_mux(dev, id, s, offset, unique_aux); -- if (ret) { -- clk = ERR_PTR(ret); -+ sec_mux = krait_add_sec_mux(dev, id, s, offset, unique_aux); -+ if (IS_ERR(sec_mux)) { -+ clk = sec_mux; - goto err; - } - -- clk = krait_add_pri_mux(dev, id, s, offset); -+ clk = krait_add_pri_mux(dev, hfpll_div, sec_mux, id, s, offset); - err: - kfree(p); - return clk; diff --git a/target/linux/ipq806x/patches-5.15/121-06-clk-qcom-krait-cc-fix-never-enabled-secondary-mux.patch b/target/linux/ipq806x/patches-5.15/121-06-clk-qcom-krait-cc-fix-never-enabled-secondary-mux.patch deleted file mode 100644 index 647b4e8db1f..00000000000 --- a/target/linux/ipq806x/patches-5.15/121-06-clk-qcom-krait-cc-fix-never-enabled-secondary-mux.patch +++ /dev/null @@ -1,47 +0,0 @@ -From a0f6d7abe7f5da1a9b435eed89acace7cde4add6 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 15 Sep 2022 02:39:11 +0200 -Subject: [PATCH 6/9] clk: qcom: krait-cc: fix never enabled secondary mux - -While never actually used as a pure mux, the secondary mux is used as a -safe selection for the primary mux to switch while the hfpll are -reprogrammed. -The secondary muxes were never enabled and this cause the krait-clk -drivers to silently ignore any set parent request without any error. -Enable the secondary mux to actually apply the parent and apply the -requested frequency. - -Fixes: bb5c4a85051e ("clk: qcom: Add Krait clock controller driver") -Signed-off-by: Christian Marangi ---- - drivers/clk/qcom/krait-cc.c | 12 +++++++++++- - 1 file changed, 11 insertions(+), 1 deletion(-) - ---- a/drivers/clk/qcom/krait-cc.c -+++ b/drivers/clk/qcom/krait-cc.c -@@ -121,7 +121,7 @@ static struct clk * - krait_add_sec_mux(struct device *dev, int id, const char *s, - unsigned int offset, bool unique_aux) - { -- int ret; -+ int ret, cpu; - struct krait_mux_clk *mux; - static struct clk_parent_data sec_mux_list[2] = { - { .name = "qsb", .fw_name = "qsb" }, -@@ -180,6 +180,16 @@ krait_add_sec_mux(struct device *dev, in - if (ret) - clk = ERR_PTR(ret); - -+ /* The secondary mux MUST be enabled or clk-krait silently -+ * ignore any request. -+ * Increase refcount for every CPU if it's the L2 secondary mux. -+ */ -+ if (id < 0) -+ for_each_possible_cpu(cpu) -+ clk_prepare_enable(clk); -+ else -+ clk_prepare_enable(clk); -+ - err_clk: - if (unique_aux) - kfree(parent_name); diff --git a/target/linux/ipq806x/patches-5.15/121-08-clk-qcom-krait-cc-handle-secondary-mux-sourcing-out-.patch b/target/linux/ipq806x/patches-5.15/121-08-clk-qcom-krait-cc-handle-secondary-mux-sourcing-out-.patch deleted file mode 100644 index 82c088f1a0f..00000000000 --- a/target/linux/ipq806x/patches-5.15/121-08-clk-qcom-krait-cc-handle-secondary-mux-sourcing-out-.patch +++ /dev/null @@ -1,70 +0,0 @@ -From b6655ca513b3f1b40417287ab7f706409455fe48 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 15 Sep 2022 02:56:47 +0200 -Subject: [PATCH 8/9] clk: qcom: krait-cc: handle secondary mux sourcing out of - PXO - -The secondary mux can sourc out of PXO as the secondary MUX is attached -to QSB and to another mux that can source out of PXO or PLL8_VOTE. - -Many device may run with uncorrect configuration with the mux sourcing -out of PXO instead of PLL8_VOTE. - -To handle this case we add also PXO as required clocks and we check if -the frequency is currently set to PXO and force a correct rate if it's -the case. - -Signed-off-by: Christian Marangi ---- - drivers/clk/qcom/krait-cc.c | 19 ++++++++++++++++++- - 1 file changed, 18 insertions(+), 1 deletion(-) - ---- a/drivers/clk/qcom/krait-cc.c -+++ b/drivers/clk/qcom/krait-cc.c -@@ -317,7 +317,7 @@ static int krait_cc_probe(struct platfor - { - struct device *dev = &pdev->dev; - const struct of_device_id *id; -- unsigned long cur_rate, aux_rate, qsb_rate; -+ unsigned long cur_rate, aux_rate, qsb_rate, pxo_rate; - int cpu; - struct clk *clk; - struct clk **clks; -@@ -327,6 +327,15 @@ static int krait_cc_probe(struct platfor - if (!id) - return -ENODEV; - -+ clk = clk_get(dev, "pxo"); -+ if (IS_ERR(clk)) -+ clk = __clk_lookup("pxo_board"); -+ -+ if (IS_ERR_OR_NULL(clk)) -+ return clk == NULL ? -ENODEV : PTR_ERR(clk); -+ -+ pxo_rate = clk_get_rate(clk); -+ - /* - * Per Documentation qsb should be provided from DTS. - * To address old implementation, register the fixed clock anyway. -@@ -394,6 +403,10 @@ static int krait_cc_probe(struct platfor - dev_info(dev, "L2 @ QSB rate. Forcing new rate.\n"); - cur_rate = aux_rate; - } -+ if (cur_rate == pxo_rate) { -+ dev_info(dev, "L2 @ PXO rate. Forcing new rate.\n"); -+ cur_rate = aux_rate; -+ } - clk_set_rate(l2_pri_mux_clk, aux_rate); - clk_set_rate(l2_pri_mux_clk, 2); - clk_set_rate(l2_pri_mux_clk, cur_rate); -@@ -405,6 +418,10 @@ static int krait_cc_probe(struct platfor - dev_info(dev, "CPU%d @ QSB rate. Forcing new rate.\n", cpu); - cur_rate = aux_rate; - } -+ if (cur_rate ==pxo_rate) { -+ dev_info(dev, "CPU%d @ PXO rate. Forcing new rate.\n", cpu); -+ cur_rate = aux_rate; -+ } - - clk_set_rate(clk, aux_rate); - clk_set_rate(clk, 2); diff --git a/target/linux/ipq806x/patches-5.15/121-05-clk-qcom-krait-cc-use-devm-variant-for-clk-notifier-.patch b/target/linux/ipq806x/patches-5.15/121-v6.2-01-clk-qcom-krait-cc-use-devm-variant-for-clk-notifier-.patch similarity index 64% rename from target/linux/ipq806x/patches-5.15/121-05-clk-qcom-krait-cc-use-devm-variant-for-clk-notifier-.patch rename to target/linux/ipq806x/patches-5.15/121-v6.2-01-clk-qcom-krait-cc-use-devm-variant-for-clk-notifier-.patch index a417daf3f28..65c1fc17f21 100644 --- a/target/linux/ipq806x/patches-5.15/121-05-clk-qcom-krait-cc-use-devm-variant-for-clk-notifier-.patch +++ b/target/linux/ipq806x/patches-5.15/121-v6.2-01-clk-qcom-krait-cc-use-devm-variant-for-clk-notifier-.patch @@ -1,20 +1,22 @@ -From ff65b60fa89be06ba68e3e22702dd71700afb6a5 Mon Sep 17 00:00:00 2001 +From 3198106a99e73dbc4c02bd5128cec0997c73af82 Mon Sep 17 00:00:00 2001 From: Christian Marangi -Date: Thu, 15 Sep 2022 02:34:58 +0200 -Subject: [PATCH 5/9] clk: qcom: krait-cc: use devm variant for clk notifier +Date: Tue, 8 Nov 2022 22:58:27 +0100 +Subject: [PATCH 1/6] clk: qcom: krait-cc: use devm variant for clk notifier register Use devm variant for clk notifier register and correctly handle free resource on driver remove. Signed-off-by: Christian Marangi +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20221108215827.30475-1-ansuelsmth@gmail.com --- drivers/clk/qcom/krait-cc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c -@@ -64,7 +64,7 @@ static int krait_notifier_register(struc +@@ -62,7 +62,7 @@ static int krait_notifier_register(struc int ret = 0; mux->clk_nb.notifier_call = krait_notifier_cb; diff --git a/target/linux/ipq806x/patches-5.15/121-v6.2-02-clk-qcom-krait-cc-fix-wrong-parent-order-for-seconda.patch b/target/linux/ipq806x/patches-5.15/121-v6.2-02-clk-qcom-krait-cc-fix-wrong-parent-order-for-seconda.patch new file mode 100644 index 00000000000..2dcb69399cf --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/121-v6.2-02-clk-qcom-krait-cc-fix-wrong-parent-order-for-seconda.patch @@ -0,0 +1,46 @@ +From 8e456411abcbf899c04740b9dbb3dcefcd61c946 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Wed, 9 Nov 2022 01:56:27 +0100 +Subject: [PATCH 2/6] clk: qcom: krait-cc: fix wrong parent order for secondary + mux + +The secondary mux parent order is swapped. +This currently doesn't cause problems as the secondary mux is used for idle +clk and as a safe clk source while reprogramming the hfpll. + +Each mux have 2 or more output but he always have a safe source to +switch while reprogramming the connected pll. We use a clk notifier to +switch to the correct parent before clk core can apply the correct rate. +The parent to switch is hardcoded in the mux struct. + +For the secondary mux the safe source to use is the qsb parent as it's +the only fixed clk as the acpus_aux is a pll that can source from pxo or +from pll8. + +The hardcoded safe parent for the secondary mux is set to index 0 that +in the secondary mux map is set to 2. + +But the index 0 is actually acpu_aux in the parent list. + +Fix the swapped parents to correctly handle idle frequency and output a +sane clk_summary report. + +Signed-off-by: Christian Marangi +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20221109005631.3189-1-ansuelsmth@gmail.com +--- + drivers/clk/qcom/krait-cc.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/clk/qcom/krait-cc.c ++++ b/drivers/clk/qcom/krait-cc.c +@@ -116,8 +116,8 @@ krait_add_sec_mux(struct device *dev, in + int ret; + struct krait_mux_clk *mux; + static const char *sec_mux_list[] = { +- "acpu_aux", + "qsb", ++ "acpu_aux", + }; + struct clk_init_data init = { + .parent_names = sec_mux_list, diff --git a/target/linux/ipq806x/patches-5.15/121-v6.2-03-clk-qcom-krait-cc-also-enable-secondary-mux-and-div-.patch b/target/linux/ipq806x/patches-5.15/121-v6.2-03-clk-qcom-krait-cc-also-enable-secondary-mux-and-div-.patch new file mode 100644 index 00000000000..6261a940d71 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/121-v6.2-03-clk-qcom-krait-cc-also-enable-secondary-mux-and-div-.patch @@ -0,0 +1,68 @@ +From 18ae57b1e8abee6c453381470f6e18991d2901a8 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Wed, 9 Nov 2022 01:56:28 +0100 +Subject: [PATCH 3/6] clk: qcom: krait-cc: also enable secondary mux and div + clk + +clk-krait ignore any rate change if clk is not flagged as enabled. +Correctly enable the secondary mux and div clk to correctly change rate +instead of silently ignoring the request. + +Signed-off-by: Christian Marangi +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20221109005631.3189-2-ansuelsmth@gmail.com +--- + drivers/clk/qcom/krait-cc.c | 21 ++++++++++++++++++++- + 1 file changed, 20 insertions(+), 1 deletion(-) + +--- a/drivers/clk/qcom/krait-cc.c ++++ b/drivers/clk/qcom/krait-cc.c +@@ -80,6 +80,7 @@ krait_add_div(struct device *dev, int id + }; + const char *p_names[1]; + struct clk *clk; ++ int cpu; + + div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); + if (!div) +@@ -103,6 +104,17 @@ krait_add_div(struct device *dev, int id + } + + clk = devm_clk_register(dev, &div->hw); ++ if (IS_ERR(clk)) ++ goto err; ++ ++ /* clk-krait ignore any rate change if mux is not flagged as enabled */ ++ if (id < 0) ++ for_each_online_cpu(cpu) ++ clk_prepare_enable(div->hw.clk); ++ else ++ clk_prepare_enable(div->hw.clk); ++ ++err: + kfree(p_names[0]); + kfree(init.name); + +@@ -113,7 +125,7 @@ static int + krait_add_sec_mux(struct device *dev, int id, const char *s, + unsigned int offset, bool unique_aux) + { +- int ret; ++ int cpu, ret; + struct krait_mux_clk *mux; + static const char *sec_mux_list[] = { + "qsb", +@@ -165,6 +177,13 @@ krait_add_sec_mux(struct device *dev, in + if (ret) + goto unique_aux; + ++ /* clk-krait ignore any rate change if mux is not flagged as enabled */ ++ if (id < 0) ++ for_each_online_cpu(cpu) ++ clk_prepare_enable(mux->hw.clk); ++ else ++ clk_prepare_enable(mux->hw.clk); ++ + unique_aux: + if (unique_aux) + kfree(sec_mux_list[0]); diff --git a/target/linux/ipq806x/patches-5.15/121-v6.2-04-clk-qcom-krait-cc-handle-secondary-mux-sourcing-out-.patch b/target/linux/ipq806x/patches-5.15/121-v6.2-04-clk-qcom-krait-cc-handle-secondary-mux-sourcing-out-.patch new file mode 100644 index 00000000000..fabb299f427 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/121-v6.2-04-clk-qcom-krait-cc-handle-secondary-mux-sourcing-out-.patch @@ -0,0 +1,48 @@ +From e5dc1a4c01510da8438dddfdf4200b79d73990dc Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Wed, 9 Nov 2022 01:56:29 +0100 +Subject: [PATCH 4/6] clk: qcom: krait-cc: handle secondary mux sourcing out of + acpu_aux + +Some bootloader may leave the system in an even more undefined state +with the secondary mux of L2 or other cores sourcing out of the acpu_aux +parent. This results in the clk set to the PXO rate or a PLL8 rate. + +The current logic to reset the mux and set them to a defined state only +handle if the mux are configured to source out of QSB. Change this and +force a new and defined state if the current clk is lower than the aux +rate. This way we can handle any wrong configuration where the mux is +sourcing out of QSB (rate 225MHz, currently set to a virtual rate of 1), +PXO rate (rate 25MHz) or PLL8 (needs to be configured to run at 384Mhz). + +Signed-off-by: Christian Marangi +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20221109005631.3189-3-ansuelsmth@gmail.com +--- + drivers/clk/qcom/krait-cc.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/clk/qcom/krait-cc.c ++++ b/drivers/clk/qcom/krait-cc.c +@@ -383,8 +383,8 @@ static int krait_cc_probe(struct platfor + */ + cur_rate = clk_get_rate(l2_pri_mux_clk); + aux_rate = 384000000; +- if (cur_rate == 1) { +- pr_info("L2 @ QSB rate. Forcing new rate.\n"); ++ if (cur_rate < aux_rate) { ++ pr_info("L2 @ Undefined rate. Forcing new rate.\n"); + cur_rate = aux_rate; + } + clk_set_rate(l2_pri_mux_clk, aux_rate); +@@ -394,8 +394,8 @@ static int krait_cc_probe(struct platfor + for_each_possible_cpu(cpu) { + clk = clks[cpu]; + cur_rate = clk_get_rate(clk); +- if (cur_rate == 1) { +- pr_info("CPU%d @ QSB rate. Forcing new rate.\n", cpu); ++ if (cur_rate < aux_rate) { ++ pr_info("CPU%d @ Undefined rate. Forcing new rate.\n", cpu); + cur_rate = aux_rate; + } + diff --git a/target/linux/ipq806x/patches-5.15/121-v6.2-05-clk-qcom-krait-cc-convert-to-devm_clk_hw_register.patch b/target/linux/ipq806x/patches-5.15/121-v6.2-05-clk-qcom-krait-cc-convert-to-devm_clk_hw_register.patch new file mode 100644 index 00000000000..049b1fa49f1 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/121-v6.2-05-clk-qcom-krait-cc-convert-to-devm_clk_hw_register.patch @@ -0,0 +1,104 @@ +From 8ea9fb841a7e528bc8ae79d726ce951dcf7b46e2 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Wed, 9 Nov 2022 01:56:30 +0100 +Subject: [PATCH 5/6] clk: qcom: krait-cc: convert to devm_clk_hw_register + +clk_register is now deprecated. Convert the driver to devm_clk_hw_register. + +Signed-off-by: Christian Marangi +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20221109005631.3189-4-ansuelsmth@gmail.com +--- + drivers/clk/qcom/krait-cc.c | 31 +++++++++++++++++++------------ + 1 file changed, 19 insertions(+), 12 deletions(-) + +--- a/drivers/clk/qcom/krait-cc.c ++++ b/drivers/clk/qcom/krait-cc.c +@@ -79,8 +79,7 @@ krait_add_div(struct device *dev, int id + .flags = CLK_SET_RATE_PARENT, + }; + const char *p_names[1]; +- struct clk *clk; +- int cpu; ++ int cpu, ret; + + div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); + if (!div) +@@ -103,8 +102,8 @@ krait_add_div(struct device *dev, int id + return -ENOMEM; + } + +- clk = devm_clk_register(dev, &div->hw); +- if (IS_ERR(clk)) ++ ret = devm_clk_hw_register(dev, &div->hw); ++ if (ret) + goto err; + + /* clk-krait ignore any rate change if mux is not flagged as enabled */ +@@ -118,7 +117,7 @@ err: + kfree(p_names[0]); + kfree(init.name); + +- return PTR_ERR_OR_ZERO(clk); ++ return ret; + } + + static int +@@ -137,7 +136,6 @@ krait_add_sec_mux(struct device *dev, in + .ops = &krait_mux_clk_ops, + .flags = CLK_SET_RATE_PARENT, + }; +- struct clk *clk; + + mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); + if (!mux) +@@ -166,14 +164,16 @@ krait_add_sec_mux(struct device *dev, in + if (unique_aux) { + sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s); + if (!sec_mux_list[0]) { +- clk = ERR_PTR(-ENOMEM); ++ ret = -ENOMEM; + goto err_aux; + } + } + +- clk = devm_clk_register(dev, &mux->hw); ++ ret = devm_clk_hw_register(dev, &mux->hw); ++ if (ret) ++ goto unique_aux; + +- ret = krait_notifier_register(dev, clk, mux); ++ ret = krait_notifier_register(dev, mux->hw.clk, mux); + if (ret) + goto unique_aux; + +@@ -189,7 +189,7 @@ unique_aux: + kfree(sec_mux_list[0]); + err_aux: + kfree(init.name); +- return PTR_ERR_OR_ZERO(clk); ++ return ret; + } + + static struct clk * +@@ -241,11 +241,18 @@ krait_add_pri_mux(struct device *dev, in + goto err_p2; + } + +- clk = devm_clk_register(dev, &mux->hw); ++ ret = devm_clk_hw_register(dev, &mux->hw); ++ if (ret) { ++ clk = ERR_PTR(ret); ++ goto err_p3; ++ } ++ ++ clk = mux->hw.clk; + + ret = krait_notifier_register(dev, clk, mux); + if (ret) +- goto err_p3; ++ clk = ERR_PTR(ret); ++ + err_p3: + kfree(p_names[2]); + err_p2: diff --git a/target/linux/ipq806x/patches-5.15/121-v6.2-06-clk-qcom-krait-cc-convert-to-parent_data-API.patch b/target/linux/ipq806x/patches-5.15/121-v6.2-06-clk-qcom-krait-cc-convert-to-parent_data-API.patch new file mode 100644 index 00000000000..453a37dfc08 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/121-v6.2-06-clk-qcom-krait-cc-convert-to-parent_data-API.patch @@ -0,0 +1,414 @@ +From 56a655e1c41a86445cf2de656649ad93424b2a63 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Wed, 9 Nov 2022 01:56:31 +0100 +Subject: [PATCH 6/6] clk: qcom: krait-cc: convert to parent_data API + +Modernize the krait-cc driver to parent-data API and refactor to drop +any use of parent_names. From Documentation all the required clocks should +be declared in DTS so fw_name can be correctly used to get the parents +for all the muxes. .name is also declared to save compatibility with old +DT. + +While at it also drop some hardcoded index and introduce an enum to make +index values more clear. + +Signed-off-by: Christian Marangi +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20221109005631.3189-5-ansuelsmth@gmail.com +--- + drivers/clk/qcom/krait-cc.c | 202 ++++++++++++++++++++---------------- + 1 file changed, 112 insertions(+), 90 deletions(-) + +--- a/drivers/clk/qcom/krait-cc.c ++++ b/drivers/clk/qcom/krait-cc.c +@@ -15,6 +15,16 @@ + + #include "clk-krait.h" + ++enum { ++ cpu0_mux = 0, ++ cpu1_mux, ++ cpu2_mux, ++ cpu3_mux, ++ l2_mux, ++ ++ clks_max, ++}; ++ + static unsigned int sec_mux_map[] = { + 2, + 0, +@@ -69,21 +79,23 @@ static int krait_notifier_register(struc + return ret; + } + +-static int ++static struct clk_hw * + krait_add_div(struct device *dev, int id, const char *s, unsigned int offset) + { + struct krait_div2_clk *div; ++ static struct clk_parent_data p_data[1]; + struct clk_init_data init = { +- .num_parents = 1, ++ .num_parents = ARRAY_SIZE(p_data), + .ops = &krait_div2_clk_ops, + .flags = CLK_SET_RATE_PARENT, + }; +- const char *p_names[1]; ++ struct clk_hw *clk; ++ char *parent_name; + int cpu, ret; + + div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); + if (!div) +- return -ENOMEM; ++ return ERR_PTR(-ENOMEM); + + div->width = 2; + div->shift = 6; +@@ -93,18 +105,25 @@ krait_add_div(struct device *dev, int id + + init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s); + if (!init.name) +- return -ENOMEM; ++ return ERR_PTR(-ENOMEM); + +- init.parent_names = p_names; +- p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s); +- if (!p_names[0]) { +- kfree(init.name); +- return -ENOMEM; ++ init.parent_data = p_data; ++ parent_name = kasprintf(GFP_KERNEL, "hfpll%s", s); ++ if (!parent_name) { ++ clk = ERR_PTR(-ENOMEM); ++ goto err_parent_name; + } + ++ p_data[0].fw_name = parent_name; ++ p_data[0].name = parent_name; ++ + ret = devm_clk_hw_register(dev, &div->hw); +- if (ret) +- goto err; ++ if (ret) { ++ clk = ERR_PTR(ret); ++ goto err_clk; ++ } ++ ++ clk = &div->hw; + + /* clk-krait ignore any rate change if mux is not flagged as enabled */ + if (id < 0) +@@ -113,33 +132,36 @@ krait_add_div(struct device *dev, int id + else + clk_prepare_enable(div->hw.clk); + +-err: +- kfree(p_names[0]); ++err_clk: ++ kfree(parent_name); ++err_parent_name: + kfree(init.name); + +- return ret; ++ return clk; + } + +-static int ++static struct clk_hw * + krait_add_sec_mux(struct device *dev, int id, const char *s, + unsigned int offset, bool unique_aux) + { + int cpu, ret; + struct krait_mux_clk *mux; +- static const char *sec_mux_list[] = { +- "qsb", +- "acpu_aux", ++ static struct clk_parent_data sec_mux_list[2] = { ++ { .name = "qsb", .fw_name = "qsb" }, ++ {}, + }; + struct clk_init_data init = { +- .parent_names = sec_mux_list, ++ .parent_data = sec_mux_list, + .num_parents = ARRAY_SIZE(sec_mux_list), + .ops = &krait_mux_clk_ops, + .flags = CLK_SET_RATE_PARENT, + }; ++ struct clk_hw *clk; ++ char *parent_name; + + mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); + if (!mux) +- return -ENOMEM; ++ return ERR_PTR(-ENOMEM); + + mux->offset = offset; + mux->lpl = id >= 0; +@@ -159,23 +181,33 @@ krait_add_sec_mux(struct device *dev, in + + init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); + if (!init.name) +- return -ENOMEM; ++ return ERR_PTR(-ENOMEM); + + if (unique_aux) { +- sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s); +- if (!sec_mux_list[0]) { +- ret = -ENOMEM; ++ parent_name = kasprintf(GFP_KERNEL, "acpu%s_aux", s); ++ if (!parent_name) { ++ clk = ERR_PTR(-ENOMEM); + goto err_aux; + } ++ sec_mux_list[1].fw_name = parent_name; ++ sec_mux_list[1].name = parent_name; ++ } else { ++ sec_mux_list[1].name = "apu_aux"; + } + + ret = devm_clk_hw_register(dev, &mux->hw); +- if (ret) +- goto unique_aux; ++ if (ret) { ++ clk = ERR_PTR(ret); ++ goto err_clk; ++ } ++ ++ clk = &mux->hw; + + ret = krait_notifier_register(dev, mux->hw.clk, mux); +- if (ret) +- goto unique_aux; ++ if (ret) { ++ clk = ERR_PTR(ret); ++ goto err_clk; ++ } + + /* clk-krait ignore any rate change if mux is not flagged as enabled */ + if (id < 0) +@@ -184,28 +216,29 @@ krait_add_sec_mux(struct device *dev, in + else + clk_prepare_enable(mux->hw.clk); + +-unique_aux: ++err_clk: + if (unique_aux) +- kfree(sec_mux_list[0]); ++ kfree(parent_name); + err_aux: + kfree(init.name); +- return ret; ++ return clk; + } + +-static struct clk * +-krait_add_pri_mux(struct device *dev, int id, const char *s, +- unsigned int offset) ++static struct clk_hw * ++krait_add_pri_mux(struct device *dev, struct clk_hw *hfpll_div, struct clk_hw *sec_mux, ++ int id, const char *s, unsigned int offset) + { + int ret; + struct krait_mux_clk *mux; +- const char *p_names[3]; ++ static struct clk_parent_data p_data[3]; + struct clk_init_data init = { +- .parent_names = p_names, +- .num_parents = ARRAY_SIZE(p_names), ++ .parent_data = p_data, ++ .num_parents = ARRAY_SIZE(p_data), + .ops = &krait_mux_clk_ops, + .flags = CLK_SET_RATE_PARENT, + }; +- struct clk *clk; ++ struct clk_hw *clk; ++ char *hfpll_name; + + mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); + if (!mux) +@@ -223,55 +256,44 @@ krait_add_pri_mux(struct device *dev, in + if (!init.name) + return ERR_PTR(-ENOMEM); + +- p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s); +- if (!p_names[0]) { ++ hfpll_name = kasprintf(GFP_KERNEL, "hfpll%s", s); ++ if (!hfpll_name) { + clk = ERR_PTR(-ENOMEM); +- goto err_p0; ++ goto err_hfpll; + } + +- p_names[1] = kasprintf(GFP_KERNEL, "hfpll%s_div", s); +- if (!p_names[1]) { +- clk = ERR_PTR(-ENOMEM); +- goto err_p1; +- } ++ p_data[0].fw_name = hfpll_name; ++ p_data[0].name = hfpll_name; + +- p_names[2] = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); +- if (!p_names[2]) { +- clk = ERR_PTR(-ENOMEM); +- goto err_p2; +- } ++ p_data[1].hw = hfpll_div; ++ p_data[2].hw = sec_mux; + + ret = devm_clk_hw_register(dev, &mux->hw); + if (ret) { + clk = ERR_PTR(ret); +- goto err_p3; ++ goto err_clk; + } + +- clk = mux->hw.clk; ++ clk = &mux->hw; + +- ret = krait_notifier_register(dev, clk, mux); ++ ret = krait_notifier_register(dev, mux->hw.clk, mux); + if (ret) + clk = ERR_PTR(ret); + +-err_p3: +- kfree(p_names[2]); +-err_p2: +- kfree(p_names[1]); +-err_p1: +- kfree(p_names[0]); +-err_p0: ++err_clk: ++ kfree(hfpll_name); ++err_hfpll: + kfree(init.name); + return clk; + } + + /* id < 0 for L2, otherwise id == physical CPU number */ +-static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux) ++static struct clk_hw *krait_add_clks(struct device *dev, int id, bool unique_aux) + { +- int ret; ++ struct clk_hw *hfpll_div, *sec_mux, *pri_mux; + unsigned int offset; + void *p = NULL; + const char *s; +- struct clk *clk; + + if (id >= 0) { + offset = 0x4501 + (0x1000 * id); +@@ -283,22 +305,23 @@ static struct clk *krait_add_clks(struct + s = "_l2"; + } + +- ret = krait_add_div(dev, id, s, offset); +- if (ret) { +- clk = ERR_PTR(ret); ++ hfpll_div = krait_add_div(dev, id, s, offset); ++ if (IS_ERR(hfpll_div)) { ++ pri_mux = hfpll_div; + goto err; + } + +- ret = krait_add_sec_mux(dev, id, s, offset, unique_aux); +- if (ret) { +- clk = ERR_PTR(ret); ++ sec_mux = krait_add_sec_mux(dev, id, s, offset, unique_aux); ++ if (IS_ERR(sec_mux)) { ++ pri_mux = sec_mux; + goto err; + } + +- clk = krait_add_pri_mux(dev, id, s, offset); ++ pri_mux = krait_add_pri_mux(dev, hfpll_div, sec_mux, id, s, offset); ++ + err: + kfree(p); +- return clk; ++ return pri_mux; + } + + static struct clk *krait_of_get(struct of_phandle_args *clkspec, void *data) +@@ -306,7 +329,7 @@ static struct clk *krait_of_get(struct o + unsigned int idx = clkspec->args[0]; + struct clk **clks = data; + +- if (idx >= 5) { ++ if (idx >= clks_max) { + pr_err("%s: invalid clock index %d\n", __func__, idx); + return ERR_PTR(-EINVAL); + } +@@ -327,9 +350,8 @@ static int krait_cc_probe(struct platfor + const struct of_device_id *id; + unsigned long cur_rate, aux_rate; + int cpu; +- struct clk *clk; +- struct clk **clks; +- struct clk *l2_pri_mux_clk; ++ struct clk_hw *mux, *l2_pri_mux; ++ struct clk *clk, **clks; + + id = of_match_device(krait_cc_match_table, dev); + if (!id) +@@ -348,21 +370,21 @@ static int krait_cc_probe(struct platfor + } + + /* Krait configurations have at most 4 CPUs and one L2 */ +- clks = devm_kcalloc(dev, 5, sizeof(*clks), GFP_KERNEL); ++ clks = devm_kcalloc(dev, clks_max, sizeof(*clks), GFP_KERNEL); + if (!clks) + return -ENOMEM; + + for_each_possible_cpu(cpu) { +- clk = krait_add_clks(dev, cpu, id->data); ++ mux = krait_add_clks(dev, cpu, id->data); + if (IS_ERR(clk)) + return PTR_ERR(clk); +- clks[cpu] = clk; ++ clks[cpu] = mux->clk; + } + +- l2_pri_mux_clk = krait_add_clks(dev, -1, id->data); +- if (IS_ERR(l2_pri_mux_clk)) +- return PTR_ERR(l2_pri_mux_clk); +- clks[4] = l2_pri_mux_clk; ++ l2_pri_mux = krait_add_clks(dev, -1, id->data); ++ if (IS_ERR(l2_pri_mux)) ++ return PTR_ERR(l2_pri_mux); ++ clks[l2_mux] = l2_pri_mux->clk; + + /* + * We don't want the CPU or L2 clocks to be turned off at late init +@@ -372,7 +394,7 @@ static int krait_cc_probe(struct platfor + * they take over. + */ + for_each_online_cpu(cpu) { +- clk_prepare_enable(l2_pri_mux_clk); ++ clk_prepare_enable(clks[l2_mux]); + WARN(clk_prepare_enable(clks[cpu]), + "Unable to turn on CPU%d clock", cpu); + } +@@ -388,16 +410,16 @@ static int krait_cc_probe(struct platfor + * two different rates to force a HFPLL reinit under all + * circumstances. + */ +- cur_rate = clk_get_rate(l2_pri_mux_clk); ++ cur_rate = clk_get_rate(clks[l2_mux]); + aux_rate = 384000000; + if (cur_rate < aux_rate) { + pr_info("L2 @ Undefined rate. Forcing new rate.\n"); + cur_rate = aux_rate; + } +- clk_set_rate(l2_pri_mux_clk, aux_rate); +- clk_set_rate(l2_pri_mux_clk, 2); +- clk_set_rate(l2_pri_mux_clk, cur_rate); +- pr_info("L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000); ++ clk_set_rate(clks[l2_mux], aux_rate); ++ clk_set_rate(clks[l2_mux], 2); ++ clk_set_rate(clks[l2_mux], cur_rate); ++ pr_info("L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000); + for_each_possible_cpu(cpu) { + clk = clks[cpu]; + cur_rate = clk_get_rate(clk); diff --git a/target/linux/ipq806x/patches-5.15/121-03-clk-qcom-krait-cc-handle-qsb-clock-defined-in-DTS.patch b/target/linux/ipq806x/patches-5.15/122-01-clk-qcom-krait-cc-handle-qsb-clock-defined-in-DTS.patch similarity index 88% rename from target/linux/ipq806x/patches-5.15/121-03-clk-qcom-krait-cc-handle-qsb-clock-defined-in-DTS.patch rename to target/linux/ipq806x/patches-5.15/122-01-clk-qcom-krait-cc-handle-qsb-clock-defined-in-DTS.patch index 8a5e054dfc9..c30c245d0a5 100644 --- a/target/linux/ipq806x/patches-5.15/121-03-clk-qcom-krait-cc-handle-qsb-clock-defined-in-DTS.patch +++ b/target/linux/ipq806x/patches-5.15/122-01-clk-qcom-krait-cc-handle-qsb-clock-defined-in-DTS.patch @@ -14,16 +14,16 @@ Signed-off-by: Christian Marangi --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c -@@ -305,7 +305,7 @@ static int krait_cc_probe(struct platfor +@@ -348,7 +348,7 @@ static int krait_cc_probe(struct platfor { struct device *dev = &pdev->dev; const struct of_device_id *id; - unsigned long cur_rate, aux_rate; + unsigned long cur_rate, aux_rate, qsb_rate; int cpu; - struct clk *clk; - struct clk **clks; -@@ -315,11 +315,19 @@ static int krait_cc_probe(struct platfor + struct clk_hw *mux, *l2_pri_mux; + struct clk *clk, **clks; +@@ -357,11 +357,19 @@ static int krait_cc_probe(struct platfor if (!id) return -ENODEV; diff --git a/target/linux/ipq806x/patches-5.15/121-04-clk-qcom-krait-cc-register-REAL-qsb-fixed-clock.patch b/target/linux/ipq806x/patches-5.15/122-02-clk-qcom-krait-cc-register-REAL-qsb-fixed-clock.patch similarity index 60% rename from target/linux/ipq806x/patches-5.15/121-04-clk-qcom-krait-cc-register-REAL-qsb-fixed-clock.patch rename to target/linux/ipq806x/patches-5.15/122-02-clk-qcom-krait-cc-register-REAL-qsb-fixed-clock.patch index 12abfcb47a1..e2f78f79fb1 100644 --- a/target/linux/ipq806x/patches-5.15/121-04-clk-qcom-krait-cc-register-REAL-qsb-fixed-clock.patch +++ b/target/linux/ipq806x/patches-5.15/122-02-clk-qcom-krait-cc-register-REAL-qsb-fixed-clock.patch @@ -16,16 +16,16 @@ Signed-off-by: Christian Marangi --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c -@@ -15,6 +15,8 @@ - - #include "clk-krait.h" +@@ -25,6 +25,8 @@ enum { + clks_max, + }; +#define QSB_RATE 2250000000 + static unsigned int sec_mux_map[] = { 2, 0, -@@ -322,7 +324,7 @@ static int krait_cc_probe(struct platfor +@@ -364,7 +366,7 @@ static int krait_cc_probe(struct platfor */ clk = clk_get(dev, "qsb"); if (IS_ERR(clk)) @@ -34,21 +34,3 @@ Signed-off-by: Christian Marangi if (IS_ERR(clk)) return PTR_ERR(clk); -@@ -378,7 +380,7 @@ static int krait_cc_probe(struct platfor - */ - cur_rate = clk_get_rate(l2_pri_mux_clk); - aux_rate = 384000000; -- if (cur_rate == 1) { -+ if (cur_rate == qsb_rate) { - pr_info("L2 @ QSB rate. Forcing new rate.\n"); - cur_rate = aux_rate; - } -@@ -389,7 +391,7 @@ static int krait_cc_probe(struct platfor - for_each_possible_cpu(cpu) { - clk = clks[cpu]; - cur_rate = clk_get_rate(clk); -- if (cur_rate == 1) { -+ if (cur_rate == qsb_rate) { - pr_info("CPU%d @ QSB rate. Forcing new rate.\n", cpu); - cur_rate = aux_rate; - } diff --git a/target/linux/ipq806x/patches-5.15/121-07-clk-qcom-krait-cc-drop-pr_info-and-use-dev_info.patch b/target/linux/ipq806x/patches-5.15/122-03-clk-qcom-krait-cc-drop-pr_info-and-use-dev_info.patch similarity index 59% rename from target/linux/ipq806x/patches-5.15/121-07-clk-qcom-krait-cc-drop-pr_info-and-use-dev_info.patch rename to target/linux/ipq806x/patches-5.15/122-03-clk-qcom-krait-cc-drop-pr_info-and-use-dev_info.patch index fb4ec29701c..d95a63fc44f 100644 --- a/target/linux/ipq806x/patches-5.15/121-07-clk-qcom-krait-cc-drop-pr_info-and-use-dev_info.patch +++ b/target/linux/ipq806x/patches-5.15/122-03-clk-qcom-krait-cc-drop-pr_info-and-use-dev_info.patch @@ -12,25 +12,25 @@ Signed-off-by: Christian Marangi --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c -@@ -391,25 +391,25 @@ static int krait_cc_probe(struct platfor - cur_rate = clk_get_rate(l2_pri_mux_clk); +@@ -423,25 +423,25 @@ static int krait_cc_probe(struct platfor + cur_rate = clk_get_rate(clks[l2_mux]); aux_rate = 384000000; - if (cur_rate == qsb_rate) { -- pr_info("L2 @ QSB rate. Forcing new rate.\n"); -+ dev_info(dev, "L2 @ QSB rate. Forcing new rate.\n"); + if (cur_rate < aux_rate) { +- pr_info("L2 @ Undefined rate. Forcing new rate.\n"); ++ dev_info(dev, "L2 @ Undefined rate. Forcing new rate.\n"); cur_rate = aux_rate; } - clk_set_rate(l2_pri_mux_clk, aux_rate); - clk_set_rate(l2_pri_mux_clk, 2); - clk_set_rate(l2_pri_mux_clk, cur_rate); -- pr_info("L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000); -+ dev_info(dev, "L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000); + clk_set_rate(clks[l2_mux], aux_rate); + clk_set_rate(clks[l2_mux], 2); + clk_set_rate(clks[l2_mux], cur_rate); +- pr_info("L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000); ++ dev_info(dev, "L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000); for_each_possible_cpu(cpu) { clk = clks[cpu]; cur_rate = clk_get_rate(clk); - if (cur_rate == qsb_rate) { -- pr_info("CPU%d @ QSB rate. Forcing new rate.\n", cpu); -+ dev_info(dev, "CPU%d @ QSB rate. Forcing new rate.\n", cpu); + if (cur_rate < aux_rate) { +- pr_info("CPU%d @ Undefined rate. Forcing new rate.\n", cpu); ++ dev_info(dev, "CPU%d @ Undefined rate. Forcing new rate.\n", cpu); cur_rate = aux_rate; } diff --git a/target/linux/ipq806x/patches-5.15/121-09-clk-qcom-krait-cc-rework-mux-reset-logic-and-reset-h.patch b/target/linux/ipq806x/patches-5.15/122-04-clk-qcom-krait-cc-rework-mux-reset-logic-and-reset-h.patch similarity index 62% rename from target/linux/ipq806x/patches-5.15/121-09-clk-qcom-krait-cc-rework-mux-reset-logic-and-reset-h.patch rename to target/linux/ipq806x/patches-5.15/122-04-clk-qcom-krait-cc-rework-mux-reset-logic-and-reset-h.patch index 23596f711ec..8f88e069912 100644 --- a/target/linux/ipq806x/patches-5.15/121-09-clk-qcom-krait-cc-rework-mux-reset-logic-and-reset-h.patch +++ b/target/linux/ipq806x/patches-5.15/122-04-clk-qcom-krait-cc-rework-mux-reset-logic-and-reset-h.patch @@ -19,9 +19,9 @@ Signed-off-by: Christian Marangi --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c -@@ -15,7 +15,9 @@ - - #include "clk-krait.h" +@@ -25,7 +25,9 @@ enum { + clks_max, + }; -#define QSB_RATE 2250000000 +#define QSB_RATE 225000000 @@ -30,33 +30,29 @@ Signed-off-by: Christian Marangi static unsigned int sec_mux_map[] = { 2, -@@ -317,7 +319,7 @@ static int krait_cc_probe(struct platfor +@@ -350,7 +352,7 @@ static int krait_cc_probe(struct platfor { struct device *dev = &pdev->dev; const struct of_device_id *id; -- unsigned long cur_rate, aux_rate, qsb_rate, pxo_rate; -+ unsigned long cur_rate, qsb_rate, pxo_rate; +- unsigned long cur_rate, aux_rate, qsb_rate; ++ unsigned long cur_rate, qsb_rate; int cpu; - struct clk *clk; - struct clk **clks; -@@ -397,36 +399,30 @@ static int krait_cc_probe(struct platfor + struct clk_hw *mux, *l2_pri_mux; + struct clk *clk, **clks; +@@ -420,28 +422,29 @@ static int krait_cc_probe(struct platfor * two different rates to force a HFPLL reinit under all * circumstances. */ -- cur_rate = clk_get_rate(l2_pri_mux_clk); +- cur_rate = clk_get_rate(clks[l2_mux]); - aux_rate = 384000000; -- if (cur_rate == qsb_rate) { -- dev_info(dev, "L2 @ QSB rate. Forcing new rate.\n"); +- if (cur_rate < aux_rate) { +- dev_info(dev, "L2 @ Undefined rate. Forcing new rate.\n"); - cur_rate = aux_rate; - } -- if (cur_rate == pxo_rate) { -- dev_info(dev, "L2 @ PXO rate. Forcing new rate.\n"); -- cur_rate = aux_rate; -- } -- clk_set_rate(l2_pri_mux_clk, aux_rate); -- clk_set_rate(l2_pri_mux_clk, 2); -- clk_set_rate(l2_pri_mux_clk, cur_rate); -- dev_info(dev, "L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000); +- clk_set_rate(clks[l2_mux], aux_rate); +- clk_set_rate(clks[l2_mux], 2); +- clk_set_rate(clks[l2_mux], cur_rate); +- dev_info(dev, "L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000); - for_each_possible_cpu(cpu) { + for (cpu = 0; cpu < 5; cpu++) { + const char *l2_s = "L2"; @@ -70,17 +66,12 @@ Signed-off-by: Christian Marangi + snprintf(cpu_s, 5, "CPU%d", cpu); + cur_rate = clk_get_rate(clk); -- if (cur_rate == qsb_rate) { -- dev_info(dev, "CPU%d @ QSB rate. Forcing new rate.\n", cpu); +- if (cur_rate < aux_rate) { +- dev_info(dev, "CPU%d @ Undefined rate. Forcing new rate.\n", cpu); - cur_rate = aux_rate; -- } -- if (cur_rate ==pxo_rate) { -- dev_info(dev, "CPU%d @ PXO rate. Forcing new rate.\n", cpu); -- cur_rate = aux_rate; -+ if (cur_rate == qsb_rate || cur_rate == pxo_rate) { -+ dev_info(dev, "%s @ %s rate. Forcing new rate.\n", -+ cpu < 4 ? cpu_s : l2_s, -+ cur_rate == qsb_rate ? "QSB" : "PXO"); ++ if (cur_rate < AUX_RATE) { ++ dev_info(dev, "%s @ Undefined rate. Forcing new rate.\n", ++ cpu < 4 ? cpu_s : l2_s); + cur_rate = AUX_RATE; } diff --git a/target/linux/ipq806x/patches-5.15/122-02-clk-qcom-clk-krait-generilize-div-functions.patch b/target/linux/ipq806x/patches-5.15/122-05-clk-qcom-clk-krait-generilize-div-functions.patch similarity index 96% rename from target/linux/ipq806x/patches-5.15/122-02-clk-qcom-clk-krait-generilize-div-functions.patch rename to target/linux/ipq806x/patches-5.15/122-05-clk-qcom-clk-krait-generilize-div-functions.patch index 8f9c2bd7e41..a7c0f046c84 100644 --- a/target/linux/ipq806x/patches-5.15/122-02-clk-qcom-clk-krait-generilize-div-functions.patch +++ b/target/linux/ipq806x/patches-5.15/122-05-clk-qcom-clk-krait-generilize-div-functions.patch @@ -130,8 +130,8 @@ Signed-off-by: Christian Marangi #endif --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c -@@ -76,11 +76,11 @@ static int krait_notifier_register(struc - static struct clk * +@@ -86,11 +86,11 @@ static int krait_notifier_register(struc + static struct clk_hw * krait_add_div(struct device *dev, int id, const char *s, unsigned int offset) { - struct krait_div2_clk *div; @@ -143,8 +143,8 @@ Signed-off-by: Christian Marangi + .ops = &krait_div_clk_ops, .flags = CLK_SET_RATE_PARENT, }; - struct clk *clk; -@@ -90,7 +90,8 @@ krait_add_div(struct device *dev, int id + struct clk_hw *clk; +@@ -101,7 +101,8 @@ krait_add_div(struct device *dev, int id if (!div) return ERR_PTR(-ENOMEM); diff --git a/target/linux/ipq806x/patches-5.15/119-04-clk-qcom-gcc-ipq806x-remove-cc_register_board-for.patch b/target/linux/ipq806x/patches-5.15/123-clk-qcom-gcc-ipq806x-remove-cc_register_board-for.patch similarity index 100% rename from target/linux/ipq806x/patches-5.15/119-04-clk-qcom-gcc-ipq806x-remove-cc_register_board-for.patch rename to target/linux/ipq806x/patches-5.15/123-clk-qcom-gcc-ipq806x-remove-cc_register_board-for.patch diff --git a/target/linux/ipq806x/patches-5.15/130-mtd-nand-raw-qcom_nandc-handle-ret-from-parse-with-c.patch b/target/linux/ipq806x/patches-5.15/130-6.1-mtd-rawnand-qcom-handle-ret-from-parse-with-codeword.patch similarity index 82% rename from target/linux/ipq806x/patches-5.15/130-mtd-nand-raw-qcom_nandc-handle-ret-from-parse-with-c.patch rename to target/linux/ipq806x/patches-5.15/130-6.1-mtd-rawnand-qcom-handle-ret-from-parse-with-codeword.patch index b6ed7554ce4..2e7e6833bb8 100644 --- a/target/linux/ipq806x/patches-5.15/130-mtd-nand-raw-qcom_nandc-handle-ret-from-parse-with-c.patch +++ b/target/linux/ipq806x/patches-5.15/130-6.1-mtd-rawnand-qcom-handle-ret-from-parse-with-codeword.patch @@ -1,8 +1,7 @@ -From 99d897e04c0856188e371e60b00e13106cd44a24 Mon Sep 17 00:00:00 2001 +From 7df140e84a75c89962feef659d686303d3ce75e5 Mon Sep 17 00:00:00 2001 From: Christian Marangi -Date: Fri, 21 Oct 2022 18:38:21 +0200 -Subject: [PATCH] mtd: nand: raw: qcom_nandc: handle ret from parse with - codeword_fixup +Date: Fri, 21 Oct 2022 18:53:04 +0200 +Subject: [PATCH] mtd: rawnand: qcom: handle ret from parse with codeword_fixup With use_codeword_fixup enabled, any return from mtd_device_parse_register gets overwritten. Aside from the clear bug, this @@ -22,6 +21,8 @@ any error from this function is not ignored. Fixes: 862bdedd7f4b ("mtd: nand: raw: qcom_nandc: add support for unprotected spare data pages") Cc: stable@vger.kernel.org # v6.0+ Signed-off-by: Christian Marangi +Signed-off-by: Miquel Raynal +Link: https://lore.kernel.org/linux-mtd/20221021165304.19991-1-ansuelsmth@gmail.com --- drivers/mtd/nand/raw/qcom_nandc.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/target/linux/ipq806x/patches-5.15/131-ARM-dts-qcom-ipq8064-disable-mmc-ddr-1_8v-for-sdcc1.patch b/target/linux/ipq806x/patches-5.15/131-6.2-ARM-dts-qcom-ipq8064-disable-mmc-ddr-1_8v-for-sdcc1.patch similarity index 77% rename from target/linux/ipq806x/patches-5.15/131-ARM-dts-qcom-ipq8064-disable-mmc-ddr-1_8v-for-sdcc1.patch rename to target/linux/ipq806x/patches-5.15/131-6.2-ARM-dts-qcom-ipq8064-disable-mmc-ddr-1_8v-for-sdcc1.patch index a5a8dd10088..8493f380fe0 100644 --- a/target/linux/ipq806x/patches-5.15/131-ARM-dts-qcom-ipq8064-disable-mmc-ddr-1_8v-for-sdcc1.patch +++ b/target/linux/ipq806x/patches-5.15/131-6.2-ARM-dts-qcom-ipq8064-disable-mmc-ddr-1_8v-for-sdcc1.patch @@ -1,6 +1,6 @@ -From f7b300f770683cd063f922e43fa4ad818761c1fb Mon Sep 17 00:00:00 2001 +From c9713e4ede1e5d044b64fe4d3cbb84223625637f Mon Sep 17 00:00:00 2001 From: Christian Marangi -Date: Sat, 22 Oct 2022 16:55:21 +0200 +Date: Tue, 25 Oct 2022 01:38:17 +0200 Subject: [PATCH] ARM: dts: qcom: ipq8064: disable mmc-ddr-1_8v for sdcc1 It was reported non working mmc with this option enabled. @@ -10,6 +10,8 @@ Disable it to restore correct functionality of this SoC feature. Tested-by: Hendrik Koerner Signed-off-by: Christian Marangi +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20221024233817.27410-1-ansuelsmth@gmail.com --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 1 - 1 file changed, 1 deletion(-) From 895f38ca1efeb46f0cd3029c732e6156d4589eb0 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Tue, 10 Jan 2023 23:51:32 +0100 Subject: [PATCH 30/51] CI: build: fallback to compile toolchain if external toolchain fail If for whatever reason external toolchain can't be found or downloaded, fallback to internal toolchain build. This can be useful when new target are introduced and external toolchain are not present in openwrt fileserver. Signed-off-by: Christian Marangi --- .github/workflows/build.yml | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index c892857999c..de168c0cb90 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -189,6 +189,8 @@ jobs: TOOLCHAIN_SHA256=$(echo "$TOOLCHAIN_STRING" | cut -d ' ' -f 1) echo "toolchain-type=external_sdk" >> $GITHUB_OUTPUT + else + echo "toolchain-type=internal" >> $GITHUB_OUTPUT fi echo "TOOLCHAIN_FILE=$TOOLCHAIN_FILE" >> "$GITHUB_ENV" @@ -196,7 +198,7 @@ jobs: echo "TOOLCHAIN_PATH=$TOOLCHAIN_PATH" >> "$GITHUB_ENV" - name: Cache external toolchain/sdk - if: inputs.build_toolchain == false + if: inputs.build_toolchain == false && steps.parse-toolchain.outputs.toolchain-type != 'internal' id: cache-external-toolchain uses: actions/cache@v3 with: @@ -212,7 +214,7 @@ jobs: ccache-kernel-${{ env.TARGET }}/${{ env.SUBTARGET }}- - name: Download external toolchain/sdk - if: inputs.build_toolchain == false && steps.cache-external-toolchain.outputs.cache-hit != 'true' + if: inputs.build_toolchain == false && steps.cache-external-toolchain.outputs.cache-hit != 'true' && steps.parse-toolchain.outputs.toolchain-type != 'internal' shell: su buildbot -c "sh -e {0}" working-directory: openwrt run: | @@ -311,7 +313,7 @@ jobs: --config ${{ env.TARGET }}/${{ env.SUBTARGET }} - name: Configure internal toolchain - if: inputs.build_toolchain == true + if: inputs.build_toolchain == true || steps.parse-toolchain.outputs.toolchain-type == 'internal' shell: su buildbot -c "sh -e {0}" working-directory: openwrt run: | From 04ada8bc4118b390cceca9dc67e7a593f7dc77b0 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Tue, 10 Jan 2023 23:20:07 +0100 Subject: [PATCH 31/51] CI: kernel: build only changed targets Detect changes in commit and build only changed targets. If a change is related to the generic target, build test each target. The matrix json is split. For target check patch only the first subtarget is selected, for build test each target subtarget is built. Signed-off-by: Christian Marangi --- .github/workflows/kernel.yml | 59 ++++++++++++++++++++++++++++-------- 1 file changed, 46 insertions(+), 13 deletions(-) diff --git a/.github/workflows/kernel.yml b/.github/workflows/kernel.yml index d886002ed16..6cff102091e 100644 --- a/.github/workflows/kernel.yml +++ b/.github/workflows/kernel.yml @@ -16,7 +16,7 @@ on: - '.github/workflows/kernel.yml' - 'include/kernel*' - 'package/kernel/**' - - 'target/linux/generic/**' + - 'target/linux/**' permissions: contents: read @@ -26,33 +26,66 @@ jobs: name: Set targets runs-on: ubuntu-latest outputs: - target: ${{ steps.find_targets.outputs.target }} + targets_subtargets: ${{ steps.find_targets.outputs.targets_subtargets }} + targets: ${{ steps.find_targets.outputs.targets }} steps: - name: Checkout uses: actions/checkout@v3 + with: + fetch-depth: 2 + + - name: Get changed files + id: changed-files + uses: tj-actions/changed-files@v35 + with: + since_last_remote_commit: true - name: Set targets id: find_targets run: | + export TARGETS_SUBTARGETS="$(perl ./scripts/dump-target-info.pl targets 2>/dev/null \ + | sort -u -t '/' -k1 \ + | awk '{ print $1 }')" + export TARGETS="$(perl ./scripts/dump-target-info.pl targets 2>/dev/null \ | sort -u -t '/' -k1,1 \ | awk '{ print $1 }')" - JSON='[' + JSON_TARGETS_SUBTARGETS='[' + FIRST=1 + for TARGET in $TARGETS_SUBTARGETS; do + if echo ${{ steps.changed-files.outputs.all_changed_files }} | grep -q target/linux/generic || + echo ${{ steps.changed-files.outputs.all_changed_files }} | grep -q $(echo $TARGET | cut -d "/" -f 1); then + [[ $FIRST -ne 1 ]] && JSON_TARGETS_SUBTARGETS="$JSON_TARGETS_SUBTARGETS"',' + JSON_TARGETS_SUBTARGETS="$JSON_TARGETS_SUBTARGETS"'"'"${TARGET}"'"' + FIRST=0 + fi + done + JSON_TARGETS_SUBTARGETS="$JSON_TARGETS_SUBTARGETS"']' + + JSON_TARGETS='[' FIRST=1 for TARGET in $TARGETS; do - [[ $FIRST -ne 1 ]] && JSON="$JSON"',' - JSON="$JSON"'"'"${TARGET}"'"' - FIRST=0 + if echo ${{ steps.changed-files.outputs.all_changed_files }} | grep -q target/linux/generic || + echo ${{ steps.changed-files.outputs.all_changed_files }} | grep -q $(echo $TARGET | cut -d "/" -f 1); then + [[ $FIRST -ne 1 ]] && JSON_TARGETS="$JSON_TARGETS"',' + JSON_TARGETS="$JSON_TARGETS"'"'"${TARGET}"'"' + FIRST=0 + fi done - JSON="$JSON"']' + JSON_TARGETS="$JSON_TARGETS"']' - echo -e "\n---- targets ----\n" - echo "$JSON" - echo -e "\n---- targets ----\n" + echo -e "\n---- targets to build ----\n" + echo "$JSON_TARGETS_SUBTARGETS" + echo -e "\n---- targets to build ----\n" - echo "target=$JSON" >> $GITHUB_OUTPUT + echo -e "\n---- targets to check patch ----\n" + echo "$JSON_TARGETS" + echo -e "\n---- targets to check patch ----\n" + + echo "targets_subtargets=$JSON_TARGETS_SUBTARGETS" >> $GITHUB_OUTPUT + echo "targets=$JSON_TARGETS" >> $GITHUB_OUTPUT build: name: Build Kernel with external toolchain @@ -63,7 +96,7 @@ jobs: strategy: fail-fast: False matrix: - target: ${{fromJson(needs.determine_targets.outputs.target)}} + target: ${{fromJson(needs.determine_targets.outputs.targets_subtargets)}} uses: ./.github/workflows/build.yml with: target: ${{ matrix.target }} @@ -79,7 +112,7 @@ jobs: strategy: fail-fast: False matrix: - target: ${{fromJson(needs.determine_targets.outputs.target)}} + target: ${{fromJson(needs.determine_targets.outputs.targets)}} uses: ./.github/workflows/check-kernel-patches.yml with: target: ${{ matrix.target }} From 4eb587f7e0a49b9c404857b18571f45981b3a7fc Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Wed, 11 Jan 2023 00:07:57 +0100 Subject: [PATCH 32/51] TODROP: test for ipq4019 target COMMIT TO DROP Signed-off-by: Christian Marangi --- target/linux/ipq40xx/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/ipq40xx/Makefile b/target/linux/ipq40xx/Makefile index 1da72664adb..85fb2a37bd4 100644 --- a/target/linux/ipq40xx/Makefile +++ b/target/linux/ipq40xx/Makefile @@ -6,7 +6,7 @@ BOARDNAME:=Qualcomm Atheros IPQ40XX FEATURES:=squashfs fpu ramdisk nand CPU_TYPE:=cortex-a7 CPU_SUBTYPE:=neon-vfpv4 -SUBTARGETS:=generic chromium mikrotik +SUBTARGETS:=generic chromium mikrotik KERNEL_PATCHVER:=5.15 From dca1b92ecddb19ff5cb6309921cd1fd5573817a0 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Wed, 11 Jan 2023 14:29:44 +0100 Subject: [PATCH 33/51] Revert "TODROP: test for ipq4019 target" This reverts commit 4eb587f7e0a49b9c404857b18571f45981b3a7fc. Pushed by mistake while merging a pr using script. Signed-off-by: Christian Marangi --- target/linux/ipq40xx/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/ipq40xx/Makefile b/target/linux/ipq40xx/Makefile index 85fb2a37bd4..1da72664adb 100644 --- a/target/linux/ipq40xx/Makefile +++ b/target/linux/ipq40xx/Makefile @@ -6,7 +6,7 @@ BOARDNAME:=Qualcomm Atheros IPQ40XX FEATURES:=squashfs fpu ramdisk nand CPU_TYPE:=cortex-a7 CPU_SUBTYPE:=neon-vfpv4 -SUBTARGETS:=generic chromium mikrotik +SUBTARGETS:=generic chromium mikrotik KERNEL_PATCHVER:=5.15 From cb679adf184d30261368707cd2b4f6cc7cf2a686 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Wed, 11 Jan 2023 13:52:38 +0100 Subject: [PATCH 34/51] CI: add concurrency limits for pr test Add concurrency limits for pull request test so that on pull request refresh old jobs are cancelled. The group is created based on the github ref + workflow name and the workflow is cancelled only it it comes from a pull_request event. Push events are not affected by this limit. Signed-off-by: Christian Marangi --- .github/workflows/kernel.yml | 4 ++++ .github/workflows/packages.yml | 4 ++++ .github/workflows/toolchain.yml | 4 ++++ .github/workflows/tools.yml | 4 ++++ 4 files changed, 16 insertions(+) diff --git a/.github/workflows/kernel.yml b/.github/workflows/kernel.yml index 6cff102091e..bc39eb359c5 100644 --- a/.github/workflows/kernel.yml +++ b/.github/workflows/kernel.yml @@ -21,6 +21,10 @@ on: permissions: contents: read +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: ${{ github.event_name == 'pull_request' }} + jobs: determine_targets: name: Set targets diff --git a/.github/workflows/packages.yml b/.github/workflows/packages.yml index 7bcaa2b3d33..340ee0c2044 100644 --- a/.github/workflows/packages.yml +++ b/.github/workflows/packages.yml @@ -23,6 +23,10 @@ on: permissions: contents: read +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: ${{ github.event_name == 'pull_request' }} + jobs: build: name: Build Packages with external toolchain diff --git a/.github/workflows/toolchain.yml b/.github/workflows/toolchain.yml index d6abab4dec4..2a24d82e30f 100644 --- a/.github/workflows/toolchain.yml +++ b/.github/workflows/toolchain.yml @@ -15,6 +15,10 @@ on: permissions: contents: read +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: ${{ github.event_name == 'pull_request' }} + jobs: determine_targets: name: Set targets diff --git a/.github/workflows/tools.yml b/.github/workflows/tools.yml index 69ee456bce9..19c11f03a62 100644 --- a/.github/workflows/tools.yml +++ b/.github/workflows/tools.yml @@ -15,6 +15,10 @@ on: permissions: contents: read +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: ${{ github.event_name == 'pull_request' }} + jobs: build-macos-latest: name: Build tools with macos latest From 5c3679e39b615ff29c9315f810e8e15775cc2d01 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Petr=20=C5=A0tetiar?= Date: Tue, 3 Jan 2023 12:44:51 +0100 Subject: [PATCH 35/51] at91: sama7: fix racy SD card image generation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We've few low spec (make -j3) build workers attached to the 22.03 buildbot instance which from time to time exhibit following build failure during image generation: + dd bs=512 if=root.ext4 of=openwrt-22.03-snapshot-r20028-43d71ad93e-at91-sama7-microchip_sama7g5-ek-ext4-sdcard.img.gz.img seek=135168 conv=notrunc dd: failed to open 'root.ext4': No such file or directory Thats likely due to the fact, that on buildbots we've `TARGET_PER_DEVICE_ROOTFS=y` which produces differently named filesystem image in the SD card image target dependency chain: make_ext4fs -L rootfs ... root.ext4+pkg=68b329da and that hardcoded root.ext4 becomes available from other target in the later stages. So lets fix this issue by using IMAGE_ROOTFS Make variable which should contain proper path to the root filesystem image. Signed-off-by: Petr Štetiar --- target/linux/at91/image/sama7.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/at91/image/sama7.mk b/target/linux/at91/image/sama7.mk index bf1704dfb33..8d6f67d80e6 100644 --- a/target/linux/at91/image/sama7.mk +++ b/target/linux/at91/image/sama7.mk @@ -35,7 +35,7 @@ define Build/at91-sdcard ./gen_at91_sdcard_img.sh \ $@.img \ $@.boot \ - $(KDIR)/root.ext4 \ + $(IMAGE_ROOTFS) \ $(AT91_SD_BOOT_PARTSIZE) \ $(CONFIG_TARGET_ROOTFS_PARTSIZE) From 5ffa8d06c87fea2ce2159d2933c178b2ffe8399a Mon Sep 17 00:00:00 2001 From: Philip Prindeville Date: Fri, 30 Dec 2022 11:03:47 -0700 Subject: [PATCH 36/51] x86: Add definitions for APU6 platform MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The board is similar to an APU4 except it has an SFP cage for eth0. Signed-off-by: Philip Prindeville Signed-off-by: Petr Štetiar [patch refresh] --- .../103-pcengines_apu6_platform.patch | 280 ++++++++++++++++++ 1 file changed, 280 insertions(+) create mode 100644 target/linux/x86/patches-5.15/103-pcengines_apu6_platform.patch diff --git a/target/linux/x86/patches-5.15/103-pcengines_apu6_platform.patch b/target/linux/x86/patches-5.15/103-pcengines_apu6_platform.patch new file mode 100644 index 00000000000..0ef3c0c087c --- /dev/null +++ b/target/linux/x86/patches-5.15/103-pcengines_apu6_platform.patch @@ -0,0 +1,280 @@ +From 970d9af9015a387bb81841faf05dcc1a171eb97a Mon Sep 17 00:00:00 2001 +From: Philip Prindeville +Date: Sun, 1 Jan 2023 15:25:04 -0700 +Subject: [PATCH v3 1/1] x86: Support APU5 in PCEngines platform driver +To: platform-driver-x86@vger.kernel.org, linux-x86_64@vger.kernel.org +Cc: Ed Wildgoose , Andres Salomon , Andreas Eberlein , Paul Spooren + +PCEngines make a number of SBC. APU5 has 5 mpcie slots + MSATA. +It also has support for 3x LTE modems with 6x SIM slots (pairs with a +SIM switch device). Each mpcie slot for modems has a reset GPIO + +To ensure that the naming is sane between APU2-6 the GPIOS are +renamed to be modem1-reset, modem2-reset, etc. This is significant +because the slots that can be reset change between APU2 and APU3/4 + +GPIO for simswap is moved to the end of the list as it could be dropped +for APU2 boards (but causes no harm to leave it in, hardware could be +added to a future rev of the board). + +Structure of the GPIOs for APU5 is extremely similar to APU2-4, but +many lines are moved around and there are simply more +modems/resets/sim-swap lines to breakout. + +Also added APU6, which is essentially APU4 with a different ethernet +interface and SFP cage on eth0. + +Revision history: + +v1: originally titled, "apu6: add apu6 variation to apu2 driver family" +this dealt only with detecting the APUv6, which is otherwise identical +to the v4 excepting the SFP cage on eth0. + +v2: at Ed's request, merged with his previous pull-request titled +"x86: Support APU5 in PCEngines platform driver", and some cleanup +to that changeset (including dropping the table "apu5_driver_data" +which did not have a defined type "struct apu_driver_data"), but got +mistitled when the Subject of that commit got accidentally dropped. + +v3: retitled to match Ed's previous pull-request. + +Cc: platform-driver-x86@vger.kernel.org +Cc: linux-x86_64@vger.kernel.org +Reviewed-by: Andreas Eberlein +Reviewed-by: Paul Spooren +Signed-off-by: Ed Wildgoose +Sighed-off-by: Philip Prindeville +--- + drivers/leds/leds-apu.c | 2 +- + drivers/platform/x86/Kconfig | 4 +- + drivers/platform/x86/pcengines-apuv2.c | 118 ++++++++++++++++++++++--- + 3 files changed, 107 insertions(+), 17 deletions(-) + +--- a/drivers/leds/leds-apu.c ++++ b/drivers/leds/leds-apu.c +@@ -183,7 +183,7 @@ static int __init apu_led_init(void) + + if (!(dmi_match(DMI_SYS_VENDOR, "PC Engines") && + (dmi_match(DMI_PRODUCT_NAME, "APU") || dmi_match(DMI_PRODUCT_NAME, "apu1")))) { +- pr_err("No PC Engines APUv1 board detected. For APUv2,3 support, enable CONFIG_PCENGINES_APU2\n"); ++ pr_err("No PC Engines APUv1 board detected. For APUv2,3,4,5,6 support, enable CONFIG_PCENGINES_APU2\n"); + return -ENODEV; + } + +--- a/drivers/platform/x86/Kconfig ++++ b/drivers/platform/x86/Kconfig +@@ -700,7 +700,7 @@ config XO1_RFKILL + laptop. + + config PCENGINES_APU2 +- tristate "PC Engines APUv2/3 front button and LEDs driver" ++ tristate "PC Engines APUv2/3/4/5/6 front button and LEDs driver" + depends on INPUT && INPUT_KEYBOARD && GPIOLIB + depends on LEDS_CLASS + select GPIO_AMD_FCH +@@ -708,7 +708,7 @@ config PCENGINES_APU2 + select LEDS_GPIO + help + This driver provides support for the front button and LEDs on +- PC Engines APUv2/APUv3 board. ++ PC Engines APUv2/APUv3/APUv4/APUv5/APUv6 board. + + To compile this driver as a module, choose M here: the module + will be called pcengines-apuv2. +--- a/drivers/platform/x86/pcengines-apuv2.c ++++ b/drivers/platform/x86/pcengines-apuv2.c +@@ -1,10 +1,12 @@ + // SPDX-License-Identifier: GPL-2.0+ + + /* +- * PC-Engines APUv2/APUv3 board platform driver ++ * PC-Engines APUv2-6 board platform driver + * for GPIO buttons and LEDs + * + * Copyright (C) 2018 metux IT consult ++ * Copyright (C) 2022 Ed Wildgoose ++ * Copyright (C) 2022 Philip Prindeville + * Author: Enrico Weigelt + */ + +@@ -22,38 +24,70 @@ + #include + + /* +- * NOTE: this driver only supports APUv2/3 - not APUv1, as this one ++ * NOTE: this driver only supports APUv2-6 - not APUv1, as this one + * has completely different register layouts. + */ + ++/* ++ * There are a number of APU variants, with differing features ++ * APU2 has SIM slots 1/2 mapping to mPCIe sockets 1/2 ++ * APU3/4 moved SIM slot 1 to mPCIe socket 3, ie logically reversed ++ * However, most APU3/4 have a SIM switch which we default on to reverse ++ * the order and keep physical SIM order matching physical modem order ++ * APU6 is approximately the same as APU4 with different ethernet layout ++ * ++ * APU5 has 3x SIM sockets, all with a SIM switch ++ * several GPIOs are shuffled (see schematic), including MODESW ++ */ ++ + /* Register mappings */ + #define APU2_GPIO_REG_LED1 AMD_FCH_GPIO_REG_GPIO57 + #define APU2_GPIO_REG_LED2 AMD_FCH_GPIO_REG_GPIO58 + #define APU2_GPIO_REG_LED3 AMD_FCH_GPIO_REG_GPIO59_DEVSLP1 + #define APU2_GPIO_REG_MODESW AMD_FCH_GPIO_REG_GPIO32_GE1 + #define APU2_GPIO_REG_SIMSWAP AMD_FCH_GPIO_REG_GPIO33_GE2 +-#define APU2_GPIO_REG_MPCIE2 AMD_FCH_GPIO_REG_GPIO55_DEVSLP0 +-#define APU2_GPIO_REG_MPCIE3 AMD_FCH_GPIO_REG_GPIO51 ++#define APU2_GPIO_REG_RESETM1 AMD_FCH_GPIO_REG_GPIO51 ++#define APU2_GPIO_REG_RESETM2 AMD_FCH_GPIO_REG_GPIO55_DEVSLP0 ++ ++#define APU5_GPIO_REG_MODESW AMT_FCH_GPIO_REG_GEVT22 ++#define APU5_GPIO_REG_SIMSWAP1 AMD_FCH_GPIO_REG_GPIO68 ++#define APU5_GPIO_REG_SIMSWAP2 AMD_FCH_GPIO_REG_GPIO32_GE1 ++#define APU5_GPIO_REG_SIMSWAP3 AMD_FCH_GPIO_REG_GPIO33_GE2 ++#define APU5_GPIO_REG_RESETM1 AMD_FCH_GPIO_REG_GPIO51 ++#define APU5_GPIO_REG_RESETM2 AMD_FCH_GPIO_REG_GPIO55_DEVSLP0 ++#define APU5_GPIO_REG_RESETM3 AMD_FCH_GPIO_REG_GPIO64 + + /* Order in which the GPIO lines are defined in the register list */ + #define APU2_GPIO_LINE_LED1 0 + #define APU2_GPIO_LINE_LED2 1 + #define APU2_GPIO_LINE_LED3 2 + #define APU2_GPIO_LINE_MODESW 3 +-#define APU2_GPIO_LINE_SIMSWAP 4 +-#define APU2_GPIO_LINE_MPCIE2 5 +-#define APU2_GPIO_LINE_MPCIE3 6 ++#define APU2_GPIO_LINE_RESETM1 4 ++#define APU2_GPIO_LINE_RESETM2 5 ++#define APU2_GPIO_LINE_SIMSWAP 6 ++ ++#define APU5_GPIO_LINE_LED1 0 ++#define APU5_GPIO_LINE_LED2 1 ++#define APU5_GPIO_LINE_LED3 2 ++#define APU5_GPIO_LINE_MODESW 3 ++#define APU5_GPIO_LINE_RESETM1 4 ++#define APU5_GPIO_LINE_RESETM2 5 ++#define APU5_GPIO_LINE_RESETM3 6 ++#define APU5_GPIO_LINE_SIMSWAP1 7 ++#define APU5_GPIO_LINE_SIMSWAP2 8 ++#define APU5_GPIO_LINE_SIMSWAP3 9 ++ + +-/* GPIO device */ ++/* GPIO device - APU2/3/4/6 */ + + static int apu2_gpio_regs[] = { + [APU2_GPIO_LINE_LED1] = APU2_GPIO_REG_LED1, + [APU2_GPIO_LINE_LED2] = APU2_GPIO_REG_LED2, + [APU2_GPIO_LINE_LED3] = APU2_GPIO_REG_LED3, + [APU2_GPIO_LINE_MODESW] = APU2_GPIO_REG_MODESW, ++ [APU2_GPIO_LINE_RESETM1] = APU2_GPIO_REG_RESETM1, ++ [APU2_GPIO_LINE_RESETM2] = APU2_GPIO_REG_RESETM2, + [APU2_GPIO_LINE_SIMSWAP] = APU2_GPIO_REG_SIMSWAP, +- [APU2_GPIO_LINE_MPCIE2] = APU2_GPIO_REG_MPCIE2, +- [APU2_GPIO_LINE_MPCIE3] = APU2_GPIO_REG_MPCIE3, + }; + + static const char * const apu2_gpio_names[] = { +@@ -61,9 +95,9 @@ static const char * const apu2_gpio_name + [APU2_GPIO_LINE_LED2] = "front-led2", + [APU2_GPIO_LINE_LED3] = "front-led3", + [APU2_GPIO_LINE_MODESW] = "front-button", ++ [APU2_GPIO_LINE_RESETM1] = "modem1-reset", ++ [APU2_GPIO_LINE_RESETM2] = "modem2-reset", + [APU2_GPIO_LINE_SIMSWAP] = "simswap", +- [APU2_GPIO_LINE_MPCIE2] = "mpcie2_reset", +- [APU2_GPIO_LINE_MPCIE3] = "mpcie3_reset", + }; + + static const struct amd_fch_gpio_pdata board_apu2 = { +@@ -72,6 +106,40 @@ static const struct amd_fch_gpio_pdata b + .gpio_names = apu2_gpio_names, + }; + ++/* GPIO device - APU5 */ ++ ++static int apu5_gpio_regs[] = { ++ [APU5_GPIO_LINE_LED1] = APU2_GPIO_REG_LED1, ++ [APU5_GPIO_LINE_LED2] = APU2_GPIO_REG_LED2, ++ [APU5_GPIO_LINE_LED3] = APU2_GPIO_REG_LED3, ++ [APU5_GPIO_LINE_MODESW] = APU5_GPIO_REG_MODESW, ++ [APU5_GPIO_LINE_RESETM1] = APU5_GPIO_REG_RESETM1, ++ [APU5_GPIO_LINE_RESETM2] = APU5_GPIO_REG_RESETM2, ++ [APU5_GPIO_LINE_RESETM3] = APU5_GPIO_REG_RESETM3, ++ [APU5_GPIO_LINE_SIMSWAP1] = APU5_GPIO_REG_SIMSWAP1, ++ [APU5_GPIO_LINE_SIMSWAP2] = APU5_GPIO_REG_SIMSWAP2, ++ [APU5_GPIO_LINE_SIMSWAP3] = APU5_GPIO_REG_SIMSWAP3, ++}; ++ ++static const char * const apu5_gpio_names[] = { ++ [APU5_GPIO_LINE_LED1] = "front-led1", ++ [APU5_GPIO_LINE_LED2] = "front-led2", ++ [APU5_GPIO_LINE_LED3] = "front-led3", ++ [APU5_GPIO_LINE_MODESW] = "front-button", ++ [APU5_GPIO_LINE_RESETM1] = "modem1-reset", ++ [APU5_GPIO_LINE_RESETM2] = "modem2-reset", ++ [APU5_GPIO_LINE_RESETM3] = "modem3-reset", ++ [APU5_GPIO_LINE_SIMSWAP1] = "simswap1", ++ [APU5_GPIO_LINE_SIMSWAP2] = "simswap2", ++ [APU5_GPIO_LINE_SIMSWAP3] = "simswap3", ++}; ++ ++static const struct amd_fch_gpio_pdata board_apu5 = { ++ .gpio_num = ARRAY_SIZE(apu5_gpio_regs), ++ .gpio_reg = apu5_gpio_regs, ++ .gpio_names = apu5_gpio_names, ++}; ++ + /* GPIO LEDs device */ + + static const struct gpio_led apu2_leds[] = { +@@ -215,6 +283,24 @@ static const struct dmi_system_id apu_gp + }, + .driver_data = (void *)&board_apu2, + }, ++ /* APU5 w/ mainline BIOS */ ++ { ++ .ident = "apu5", ++ .matches = { ++ DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"), ++ DMI_MATCH(DMI_BOARD_NAME, "apu5") ++ }, ++ .driver_data = (void *)&board_apu5, ++ }, ++ /* APU6 w/ mainline BIOS */ ++ { ++ .ident = "apu6", ++ .matches = { ++ DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"), ++ DMI_MATCH(DMI_BOARD_NAME, "apu6") ++ }, ++ .driver_data = (void *)&board_apu2, ++ }, + {} + }; + +@@ -249,7 +335,7 @@ static int __init apu_board_init(void) + + id = dmi_first_match(apu_gpio_dmi_table); + if (!id) { +- pr_err("failed to detect APU board via DMI\n"); ++ pr_err("No APU board detected via DMI\n"); + return -ENODEV; + } + +@@ -288,8 +374,12 @@ module_init(apu_board_init); + module_exit(apu_board_exit); + + MODULE_AUTHOR("Enrico Weigelt, metux IT consult "); +-MODULE_DESCRIPTION("PC Engines APUv2/APUv3 board GPIO/LEDs/keys driver"); ++MODULE_DESCRIPTION("PC Engines APUv2-6 board GPIO/LEDs/keys driver"); + MODULE_LICENSE("GPL"); + MODULE_DEVICE_TABLE(dmi, apu_gpio_dmi_table); + MODULE_ALIAS("platform:pcengines-apuv2"); ++MODULE_ALIAS("platform:pcengines-apuv3"); ++MODULE_ALIAS("platform:pcengines-apuv4"); ++MODULE_ALIAS("platform:pcengines-apuv5"); ++MODULE_ALIAS("platform:pcengines-apuv6"); + MODULE_SOFTDEP("pre: platform:" AMD_FCH_GPIO_DRIVER_NAME " platform:leds-gpio platform:gpio_keys_polled"); From 26595eac0580053e5910b04db0458074c6f3b8ee Mon Sep 17 00:00:00 2001 From: Philip Prindeville Date: Fri, 30 Dec 2022 11:17:10 -0700 Subject: [PATCH 37/51] x86: Add APU6 board support for startup detection The APU6 is similar to the APU4 except for eth0 having an SFP cage instead of RJ45. Signed-off-by: Philip Prindeville --- target/linux/x86/base-files/etc/board.d/01_leds | 2 +- target/linux/x86/base-files/etc/board.d/02_network | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/target/linux/x86/base-files/etc/board.d/01_leds b/target/linux/x86/base-files/etc/board.d/01_leds index 74ad2d59fe1..e639d108081 100644 --- a/target/linux/x86/base-files/etc/board.d/01_leds +++ b/target/linux/x86/base-files/etc/board.d/01_leds @@ -11,7 +11,7 @@ cisco-mx100-hw) ucidef_set_led_usbport "usb" "USB" "mx100:green:usb" "1-1-port2" ucidef_set_led_default "diag" "DIAG" "mx100:green:tricolor" "1" ;; -pc-engines-apu1|pc-engines-apu2|pc-engines-apu3) +pc-engines-apu1|pc-engines-apu2|pc-engines-apu3|pc-engines-apu4|pc-engines-apu5|pc-engines-apu6) ucidef_set_led_netdev "wan" "WAN" "apu:green:3" "eth0" ucidef_set_led_netdev "lan" "LAN" "apu:green:2" "br-lan" ucidef_set_led_default "diag" "DIAG" "apu:green:1" "1" diff --git a/target/linux/x86/base-files/etc/board.d/02_network b/target/linux/x86/base-files/etc/board.d/02_network index 9335e297ba2..5befba0a62d 100644 --- a/target/linux/x86/base-files/etc/board.d/02_network +++ b/target/linux/x86/base-files/etc/board.d/02_network @@ -26,6 +26,12 @@ cisco-mx100-hw) pc-engines-apu1|pc-engines-apu2|pc-engines-apu3) ucidef_set_interfaces_lan_wan "eth1 eth2" "eth0" ;; +pc-engines-apu5) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ;; +pc-engines-apu4|pc-engines-apu6) + ucidef_set_interfaces_lan_wan "eth1 eth2 eth3" "eth0" + ;; roqos-roqos-core-rc10) ucidef_set_interfaces_lan_wan "eth1" "eth0" ;; From 3b669bc3f32f7594f38187a284a65ca2c35a0121 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Petr=20=C5=A0tetiar?= Date: Tue, 3 Jan 2023 12:44:51 +0100 Subject: [PATCH 38/51] at91: sam9x,sama5: fix racy SD card image generation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We've few low spec (make -j3) build workers attached to the 22.03 buildbot instance which from time to time exhibit following build failure during image generation (shortened for brewity): + dd bs=512 if=root.ext4 of=openwrt-22.03...sdcard.img.gz.img dd: failed to open 'root.ext4': No such file or directory Thats happening likely due to the fact, that on buildbots we've `TARGET_PER_DEVICE_ROOTFS=y` which produces differently named filesystem image in the SD card image target dependency chain: make_ext4fs -L rootfs ... root.ext4+pkg=68b329da and that hardcoded `root.ext4` image filename becomes available from other Make targets in the later stages. So lets fix this issue by using IMAGE_ROOTFS Make variable which should contain proper path to the root filesystem image. Fixing remaining subtargets ommited in commit 5c3679e39b61 ("at91: sama7: fix racy SD card image generation"). Fixes: 5c3679e39b61 ("at91: sama7: fix racy SD card image generation") Signed-off-by: Petr Štetiar --- target/linux/at91/image/sam9x.mk | 2 +- target/linux/at91/image/sama5.mk | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/linux/at91/image/sam9x.mk b/target/linux/at91/image/sam9x.mk index 4de96097758..409e43ca6e9 100644 --- a/target/linux/at91/image/sam9x.mk +++ b/target/linux/at91/image/sam9x.mk @@ -35,7 +35,7 @@ define Build/at91-sdcard ./gen_at91_sdcard_img.sh \ $@.img \ $@.boot \ - $(KDIR)/root.ext4 \ + $(IMAGE_ROOTFS) \ $(AT91_SD_BOOT_PARTSIZE) \ $(CONFIG_TARGET_ROOTFS_PARTSIZE) diff --git a/target/linux/at91/image/sama5.mk b/target/linux/at91/image/sama5.mk index 39db3e1cd02..7f4dd3316a8 100644 --- a/target/linux/at91/image/sama5.mk +++ b/target/linux/at91/image/sama5.mk @@ -39,7 +39,7 @@ define Build/at91-sdcard ./gen_at91_sdcard_img.sh \ $@.img \ $@.boot \ - $(KDIR)/root.ext4 \ + $(IMAGE_ROOTFS) \ $(AT91_SD_BOOT_PARTSIZE) \ $(CONFIG_TARGET_ROOTFS_PARTSIZE) From 57a02cbbff5bc1b9610437c4cedb2072f9647f00 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Wed, 11 Jan 2023 16:24:37 +0100 Subject: [PATCH 39/51] CI: kernel: test each target with additional changes than target/linux Test each target if there are additional changes than target/linux. This is needed to do wide test with changes to kmods, include/kernel and changes to the workflow files. While at it also cleanup and rework the code to drop duplication. Also drop since_last_remote_commit to better track changes. Fixes: 04ada8bc4118 ("CI: kernel: build only changed targets") Signed-off-by: Christian Marangi --- .github/workflows/kernel.yml | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/.github/workflows/kernel.yml b/.github/workflows/kernel.yml index bc39eb359c5..2582a594ba4 100644 --- a/.github/workflows/kernel.yml +++ b/.github/workflows/kernel.yml @@ -42,25 +42,22 @@ jobs: - name: Get changed files id: changed-files uses: tj-actions/changed-files@v35 - with: - since_last_remote_commit: true - name: Set targets id: find_targets run: | - export TARGETS_SUBTARGETS="$(perl ./scripts/dump-target-info.pl targets 2>/dev/null \ - | sort -u -t '/' -k1 \ - | awk '{ print $1 }')" + ALL_TARGETS="$(perl ./scripts/dump-target-info.pl targets 2>/dev/null)" + CHANGED_FILES="$(echo ${{ steps.changed-files.outputs.all_changed_files }} | tr ' ' '\n')" - export TARGETS="$(perl ./scripts/dump-target-info.pl targets 2>/dev/null \ - | sort -u -t '/' -k1,1 \ - | awk '{ print $1 }')" + TARGETS_SUBTARGETS="$(echo "$ALL_TARGETS" | sort -u -t '/' -k1 | awk '{ print $1 }')" + TARGETS="$(echo "$ALL_TARGETS" | sort -u -t '/' -k1,1 | awk '{ print $1 }')" JSON_TARGETS_SUBTARGETS='[' FIRST=1 for TARGET in $TARGETS_SUBTARGETS; do - if echo ${{ steps.changed-files.outputs.all_changed_files }} | grep -q target/linux/generic || - echo ${{ steps.changed-files.outputs.all_changed_files }} | grep -q $(echo $TARGET | cut -d "/" -f 1); then + if echo "$CHANGED_FILES" | grep -v -q target/linux || + echo "$CHANGED_FILES" | grep -q target/linux/generic || + echo "$CHANGED_FILES" | grep -q $(echo $TARGET | cut -d "/" -f 1); then [[ $FIRST -ne 1 ]] && JSON_TARGETS_SUBTARGETS="$JSON_TARGETS_SUBTARGETS"',' JSON_TARGETS_SUBTARGETS="$JSON_TARGETS_SUBTARGETS"'"'"${TARGET}"'"' FIRST=0 @@ -71,8 +68,9 @@ jobs: JSON_TARGETS='[' FIRST=1 for TARGET in $TARGETS; do - if echo ${{ steps.changed-files.outputs.all_changed_files }} | grep -q target/linux/generic || - echo ${{ steps.changed-files.outputs.all_changed_files }} | grep -q $(echo $TARGET | cut -d "/" -f 1); then + if echo "$CHANGED_FILES" | grep -v -q target/linux || + echo "$CHANGED_FILES" | grep -q target/linux/generic || + echo "$CHANGED_FILES" | grep -q $(echo $TARGET | cut -d "/" -f 1); then [[ $FIRST -ne 1 ]] && JSON_TARGETS="$JSON_TARGETS"',' JSON_TARGETS="$JSON_TARGETS"'"'"${TARGET}"'"' FIRST=0 From f6b46c9269a2e83e88b0a353a87812cd4837f97e Mon Sep 17 00:00:00 2001 From: Michal Hrusecky Date: Mon, 9 Jan 2023 15:59:02 +0100 Subject: [PATCH 40/51] mvebu: backport upstream patch to fix COMPHY reset Upstream commit [1] included in the Linux kernel version 6.2 was backported to Linux kernels 6.1.4, 6.0.18. It should be possible that it is going to be backported even to the 5.15 series, but before it happens, let's include it here. It was discovered that on SOC Marvell Armada 3720, which is using e.g. Turris MOX, and if you are also using it with older ARM Trusted Firmware v1.5, it is not possible to detect connected USB 3.0 devices, but they are working just fine when connected with USB 2.0 cable. This patch fixes it. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/phy/marvell/phy-mvebu-a3700-comphy.c?id=b01d622d76134e9401970ffd3fbbb9a7051f976a Reviewed-by: Robert Marko Signed-off-by: Michal Hrusecky Signed-off-by: Josef Schlehofer [improve commit description, added tag to the patch] --- ...mvebu-a3700-comphy-Reset-COMPHY-regi.patch | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 target/linux/mvebu/patches-5.15/710-v6.2-phy-marvell-phy-mvebu-a3700-comphy-Reset-COMPHY-regi.patch diff --git a/target/linux/mvebu/patches-5.15/710-v6.2-phy-marvell-phy-mvebu-a3700-comphy-Reset-COMPHY-regi.patch b/target/linux/mvebu/patches-5.15/710-v6.2-phy-marvell-phy-mvebu-a3700-comphy-Reset-COMPHY-regi.patch new file mode 100644 index 00000000000..a852dc1fc11 --- /dev/null +++ b/target/linux/mvebu/patches-5.15/710-v6.2-phy-marvell-phy-mvebu-a3700-comphy-Reset-COMPHY-regi.patch @@ -0,0 +1,50 @@ +From b01d622d76134e9401970ffd3fbbb9a7051f976a Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= +Date: Tue, 20 Sep 2022 14:11:54 +0200 +Subject: [PATCH] phy: marvell: phy-mvebu-a3700-comphy: Reset COMPHY registers + before USB 3.0 power on +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Turris MOX board with older ARM Trusted Firmware version v1.5 is not able +to detect any USB 3.0 device connected to USB-A port on Mox-A module after +commit 0a6fc70d76bd ("phy: marvell: phy-mvebu-a3700-comphy: Remove broken +reset support"). On the other hand USB 2.0 devices connected to the same +USB-A port are working fine. + +It looks as if the older firmware configures COMPHY registers for USB 3.0 +somehow incompatibly for kernel driver. Experiments show that resetting +COMPHY registers via setting SFT_RST auto-clearing bit in COMPHY_SFT_RESET +register fixes this issue. + +Reset the COMPHY in mvebu_a3700_comphy_usb3_power_on() function as a first +step after selecting COMPHY lane and USB 3.0 function. With this change +Turris MOX board can successfully detect USB 3.0 devices again. + +Before the above mentioned commit this reset was implemented in PHY reset +method, so this is the reason why there was no issue with older firmware +version then. + +Fixes: 0a6fc70d76bd ("phy: marvell: phy-mvebu-a3700-comphy: Remove broken reset support") +Reported-by: Marek Behún +Signed-off-by: Pali Rohár +Tested-by: Shin'ichiro Kawasaki +Link: https://lore.kernel.org/r/20220920121154.30115-1-pali@kernel.org +Signed-off-by: Vinod Koul +--- + drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c ++++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c +@@ -826,6 +826,9 @@ mvebu_a3700_comphy_usb3_power_on(struct + if (ret) + return ret; + ++ /* COMPHY register reset (cleared automatically) */ ++ comphy_lane_reg_set(lane, COMPHY_SFT_RESET, SFT_RST, SFT_RST); ++ + /* + * 0. Set PHY OTG Control(0x5d034), bit 4, Power up OTG module The + * register belong to UTMI module, so it is set in UTMI phy driver. From 2e3d1edf59109d6329a00d90b1e953261d602af5 Mon Sep 17 00:00:00 2001 From: Florian Maurer Date: Tue, 10 Jan 2023 13:39:50 +0100 Subject: [PATCH 41/51] lantiq: xrx200: Fix wifi LED on o2 box 6431 Wifi LED did not work using phy0radio, which somehow slipped through in the previous testing Signed-off-by: Florian Maurer --- .../arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22.dtsi | 1 + target/linux/lantiq/xrx200/base-files/etc/board.d/01_leds | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22.dtsi index 1158aa371ec..1a7a11db420 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22.dtsi +++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22.dtsi @@ -80,6 +80,7 @@ wifi: wifi { label = "green:wlan"; gpios = <&gpio 20 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0tpt"; }; power_red: power2 { diff --git a/target/linux/lantiq/xrx200/base-files/etc/board.d/01_leds b/target/linux/lantiq/xrx200/base-files/etc/board.d/01_leds index 8f59538b831..0c80aaa3b84 100644 --- a/target/linux/lantiq/xrx200/base-files/etc/board.d/01_leds +++ b/target/linux/lantiq/xrx200/base-files/etc/board.d/01_leds @@ -30,7 +30,6 @@ arcadyan,arv7519rw22) arcadyan,vgv7510kw22-nor|\ arcadyan,vgv7510kw22-brn) ucidef_set_led_netdev "internet" "internet" "$led_internet" "wan" - ucidef_set_led_wlan "wifi" "wifi" "green:wlan" "phy0radio" ;; zyxel,p-2812hnu-f1|\ zyxel,p-2812hnu-f3) From 76c67fcc66116381c69439f20159b636573080ba Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sat, 7 Jan 2023 14:41:04 +0100 Subject: [PATCH 42/51] ksmbd: Fix ZDI-CAN-18259 This fixes a security problem in ksmbd. It currently has the ZDI-CAN-18259 ID assigned, but no CVE yet. Backported from: https://github.com/cifsd-team/ksmbd/commit/8824b7af409f51f1316e92e9887c2fd48c0b26d6 https://github.com/cifsd-team/ksmbd/commit/cc4f3b5a6ab4693aba94a45cc073188df4d67175 Signed-off-by: Hauke Mehrtens --- package/kernel/ksmbd/Makefile | 2 +- ...en-to-be-at-least-CIFS_ENCPWD_SIZE-i.patch | 36 +++++++++++ ...nite-loop-in-ksmbd_conn_handler_loop.patch | 63 +++++++++++++++++++ 3 files changed, 100 insertions(+), 1 deletion(-) create mode 100644 package/kernel/ksmbd/patches/10-ksmbd-check-nt_len-to-be-at-least-CIFS_ENCPWD_SIZE-i.patch create mode 100644 package/kernel/ksmbd/patches/11-ksmbd-fix-infinite-loop-in-ksmbd_conn_handler_loop.patch diff --git a/package/kernel/ksmbd/Makefile b/package/kernel/ksmbd/Makefile index 86207508e54..8a0ebc54f89 100644 --- a/package/kernel/ksmbd/Makefile +++ b/package/kernel/ksmbd/Makefile @@ -2,7 +2,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=ksmbd PKG_VERSION:=3.4.6 -PKG_RELEASE:=$(AUTORELEASE) +PKG_RELEASE:=2 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=https://codeload.github.com/cifsd-team/cifsd/tar.gz/$(PKG_VERSION)? diff --git a/package/kernel/ksmbd/patches/10-ksmbd-check-nt_len-to-be-at-least-CIFS_ENCPWD_SIZE-i.patch b/package/kernel/ksmbd/patches/10-ksmbd-check-nt_len-to-be-at-least-CIFS_ENCPWD_SIZE-i.patch new file mode 100644 index 00000000000..198e7521061 --- /dev/null +++ b/package/kernel/ksmbd/patches/10-ksmbd-check-nt_len-to-be-at-least-CIFS_ENCPWD_SIZE-i.patch @@ -0,0 +1,36 @@ +From 8824b7af409f51f1316e92e9887c2fd48c0b26d6 Mon Sep 17 00:00:00 2001 +From: William Liu +Date: Fri, 30 Dec 2022 09:13:35 +0900 +Subject: ksmbd: check nt_len to be at least CIFS_ENCPWD_SIZE in + ksmbd_decode_ntlmssp_auth_blob +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +"nt_len - CIFS_ENCPWD_SIZE" is passed directly from +ksmbd_decode_ntlmssp_auth_blob to ksmbd_auth_ntlmv2. Malicious requests +can set nt_len to less than CIFS_ENCPWD_SIZE, which results in a negative +number (or large unsigned value) used for a subsequent memcpy in +ksmbd_auth_ntlvm2 and can cause a panic. + +Fixes: e2f3448 ("cifsd: add server-side procedures for SMB3") +Cc: stable@vger.kernel.org +Signed-off-by: William Liu +Signed-off-by: Hrvoje Mišetić +Signed-off-by: Namjae Jeon +--- + auth.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/auth.c ++++ b/auth.c +@@ -583,7 +583,8 @@ int ksmbd_decode_ntlmssp_auth_blob(struc + dn_off = le32_to_cpu(authblob->DomainName.BufferOffset); + dn_len = le16_to_cpu(authblob->DomainName.Length); + +- if (blob_len < (u64)dn_off + dn_len || blob_len < (u64)nt_off + nt_len) ++ if (blob_len < (u64)dn_off + dn_len || blob_len < (u64)nt_off + nt_len || ++ nt_len < CIFS_ENCPWD_SIZE) + return -EINVAL; + + #ifdef CONFIG_SMB_INSECURE_SERVER diff --git a/package/kernel/ksmbd/patches/11-ksmbd-fix-infinite-loop-in-ksmbd_conn_handler_loop.patch b/package/kernel/ksmbd/patches/11-ksmbd-fix-infinite-loop-in-ksmbd_conn_handler_loop.patch new file mode 100644 index 00000000000..1b3c5c1aaba --- /dev/null +++ b/package/kernel/ksmbd/patches/11-ksmbd-fix-infinite-loop-in-ksmbd_conn_handler_loop.patch @@ -0,0 +1,63 @@ +From cc4f3b5a6ab4693aba94a45cc073188df4d67175 Mon Sep 17 00:00:00 2001 +From: Namjae Jeon +Date: Mon, 26 Dec 2022 01:28:52 +0900 +Subject: ksmbd: fix infinite loop in ksmbd_conn_handler_loop() + +If kernel_recvmsg() return -EAGAIN in ksmbd_tcp_readv() and go round +again, It will cause infinite loop issue. And all threads from next +connections would be doing that. This patch add max retry count(2) to +avoid it. kernel_recvmsg() will wait during 7sec timeout and try to +retry two time if -EAGAIN is returned. And add flags of kvmalloc to +__GFP_NOWARN and __GFP_NORETRY to disconnect immediately without +retrying on memory alloation failure. + +Fixes: 0626e66 ("cifsd: add server handler for central processing and tranport layers") +Cc: stable@vger.kernel.org +Reported-by: zdi-disclosures@trendmicro.com # ZDI-CAN-18259 +Reviewed-by: Sergey Senozhatsky +Signed-off-by: Namjae Jeon +--- + connection.c | 7 +++++-- + transport_tcp.c | 5 ++++- + 2 files changed, 9 insertions(+), 3 deletions(-) + +--- a/connection.c ++++ b/connection.c +@@ -337,9 +337,12 @@ int ksmbd_conn_handler_loop(void *p) + + /* 4 for rfc1002 length field */ + size = pdu_size + 4; +- conn->request_buf = kvmalloc(size, GFP_KERNEL); ++ conn->request_buf = kvmalloc(size, ++ GFP_KERNEL | ++ __GFP_NOWARN | ++ __GFP_NORETRY); + if (!conn->request_buf) +- continue; ++ break; + + memcpy(conn->request_buf, hdr_buf, sizeof(hdr_buf)); + if (!ksmbd_smb_request(conn)) +--- a/transport_tcp.c ++++ b/transport_tcp.c +@@ -323,6 +323,7 @@ static int ksmbd_tcp_readv(struct tcp_tr + struct msghdr ksmbd_msg; + struct kvec *iov; + struct ksmbd_conn *conn = KSMBD_TRANS(t)->conn; ++ int max_retry = 2; + + iov = get_conn_iovec(t, nr_segs); + if (!iov) +@@ -349,9 +350,11 @@ static int ksmbd_tcp_readv(struct tcp_tr + } else if (conn->status == KSMBD_SESS_NEED_RECONNECT) { + total_read = -EAGAIN; + break; +- } else if (length == -ERESTARTSYS || length == -EAGAIN) { ++ } else if ((length == -ERESTARTSYS || length == -EAGAIN) && ++ max_retry) { + usleep_range(1000, 2000); + length = 0; ++ max_retry--; + continue; + } else if (length <= 0) { + total_read = -EAGAIN; From 11627f3ac19b022468e163836d88c76eb0d22a88 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Fri, 30 Dec 2022 18:58:19 -0800 Subject: [PATCH 43/51] CI: remove various tools from macOS zstd, openssl, and quilt are already built in tools/. No need to install them. The rest are unused. Signed-off-by: Rosen Penev --- .github/workflows/tools.yml | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/.github/workflows/tools.yml b/.github/workflows/tools.yml index 19c11f03a62..61308603eed 100644 --- a/.github/workflows/tools.yml +++ b/.github/workflows/tools.yml @@ -54,19 +54,13 @@ jobs: gnu-sed \ gnu-tar \ grep \ - libidn2 \ - libunistring \ m4 \ make \ mpfr \ ncurses \ - openssl@1.1 \ pcre \ pkg-config \ - quilt \ - readline \ - wget \ - zstd + wget echo "/bin" >> "$GITHUB_PATH" echo "/sbin/Library/Apple/usr/bin" >> "$GITHUB_PATH" From dd357409f68522469042ca85c740e34aaab253db Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Sun, 8 Jan 2023 12:04:41 -0800 Subject: [PATCH 44/51] CI: remove already installed packages The GitHub image already includes these. Signed-off-by: Rosen Penev --- .github/workflows/tools.yml | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/.github/workflows/tools.yml b/.github/workflows/tools.yml index 61308603eed..f95dbf77128 100644 --- a/.github/workflows/tools.yml +++ b/.github/workflows/tools.yml @@ -41,26 +41,16 @@ jobs: working-directory: ${{ env.WORKPATH }}/openwrt run: | brew install \ - autoconf \ automake \ coreutils \ diffutils \ findutils \ gawk \ - gettext \ git-extras \ - gmp \ - gnu-getopt \ gnu-sed \ - gnu-tar \ grep \ - m4 \ make \ - mpfr \ - ncurses \ - pcre \ - pkg-config \ - wget + pcre echo "/bin" >> "$GITHUB_PATH" echo "/sbin/Library/Apple/usr/bin" >> "$GITHUB_PATH" From 0a35d3f9923703fc229abc16e2e7459a9f68b1d9 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Sun, 8 Jan 2023 12:05:29 -0800 Subject: [PATCH 45/51] CI: remove pcre from macOS ff02e1561f2073b39814f2d73205a5209471b115 added a host version of pcre for packages that need it. Signed-off-by: Rosen Penev --- .github/workflows/tools.yml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/.github/workflows/tools.yml b/.github/workflows/tools.yml index f95dbf77128..b315346ed6f 100644 --- a/.github/workflows/tools.yml +++ b/.github/workflows/tools.yml @@ -49,8 +49,7 @@ jobs: git-extras \ gnu-sed \ grep \ - make \ - pcre + make echo "/bin" >> "$GITHUB_PATH" echo "/sbin/Library/Apple/usr/bin" >> "$GITHUB_PATH" From d9aa41dcdaeb38d48e0e74c61fd3fa6a41ac7f87 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Thu, 12 Jan 2023 01:05:44 +0100 Subject: [PATCH 46/51] lldpd: use release tar instead of codeload There is currently a problem with making reproducible version of lldpd. The tool version is generated based on 3 source: 1. .dist-version file in release tar 2. git hash with presence of .git directory 3. current date Using the codeload tar from github results in getting the repo without the .git directory and since they are not release tar, we don't have .dist-version. This results in having lldpd bin with a version set to the current build time. Switch to release tar so that we correctly have a .dist-version file and the version is not based on the build time. Signed-off-by: Christian Marangi Reviewed-by: Robert Marko --- package/network/services/lldpd/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/package/network/services/lldpd/Makefile b/package/network/services/lldpd/Makefile index b9770909a9f..a08626366f9 100644 --- a/package/network/services/lldpd/Makefile +++ b/package/network/services/lldpd/Makefile @@ -12,8 +12,8 @@ PKG_VERSION:=1.0.16 PKG_RELEASE:=1 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz -PKG_SOURCE_URL:=https://codeload.github.com/lldpd/lldpd/tar.gz/$(PKG_VERSION)? -PKG_HASH:=9bc6154377b97187d96d5e22aa5c4946c6cbc85f1416149853cc0940639a77e5 +PKG_SOURCE_URL:=https://github.com/lldpd/lldpd/releases/download/$(PKG_VERSION)/ +PKG_HASH:=7753c6e31e938923185f4e10c4ab328929729e22ee4a9687d08881fb82c092ee PKG_MAINTAINER:=Stijn Tintel PKG_LICENSE:=ISC From 5f1758ef14575df4e86896526b1c2035c231899e Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Thu, 12 Jan 2023 14:46:58 +0100 Subject: [PATCH 47/51] scripts/dl_github_archieve.py: fix generating unreproducible tar Allign dl_github_archieve.py to 8252511dc0b5a71e9e64b96f233a27ad73e28b7f change. On supported system the sigid bit is applied to files and tar archieve that on tar creation. This cause unreproducible tar for these system and these bit should be dropped to produce reproducible tar. Add the missing option following the command options used in other scripts. Fixes: 75ab064d2b38 ("build: download code from github using archive API") Suggested-by: Eneas U de Queiroz Tested-by: Robert Marko Signed-off-by: Christian Marangi --- scripts/dl_github_archive.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/dl_github_archive.py b/scripts/dl_github_archive.py index b992227dc98..328d588e781 100755 --- a/scripts/dl_github_archive.py +++ b/scripts/dl_github_archive.py @@ -133,7 +133,7 @@ class Path(object): def tar(path, subdir, into=None, ts=None): """Pack ``path`` into tarball ``into``.""" # --sort=name requires a recent build of GNU tar - args = ['tar', '--numeric-owner', '--owner=0', '--group=0', '--sort=name'] + args = ['tar', '--numeric-owner', '--owner=0', '--group=0', '--sort=name', '--mode=a-s'] args += ['-C', path, '-cf', into, subdir] envs = os.environ.copy() if ts is not None: From c83dbcdf8f1a045437e91fe7c022c990ea9b83ff Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Wed, 11 Jan 2023 22:42:34 +0100 Subject: [PATCH 48/51] mac80211: ath11k: fix monitor bringup Currently, ath11k will crash the crash if we try to bringup the monitor mode interface. Luckily, it has already been fixed upstream, so backport the patches fixing it. Fixes: 93ae4353cdf6 ("mac80211: add ath11k PCI support") Signed-off-by: Robert Marko --- ...scan-request-param-frame-size-warnin.patch | 161 ++++++++++++++++++ ...th11k-fix-monitor-mode-bringup-crash.patch | 79 +++++++++ 2 files changed, 240 insertions(+) create mode 100644 package/kernel/mac80211/patches/ath11k/0019-wifi-ath11k-Fix-scan-request-param-frame-size-warnin.patch create mode 100644 package/kernel/mac80211/patches/ath11k/0020-wifi-ath11k-fix-monitor-mode-bringup-crash.patch diff --git a/package/kernel/mac80211/patches/ath11k/0019-wifi-ath11k-Fix-scan-request-param-frame-size-warnin.patch b/package/kernel/mac80211/patches/ath11k/0019-wifi-ath11k-Fix-scan-request-param-frame-size-warnin.patch new file mode 100644 index 00000000000..50c14e7b98f --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0019-wifi-ath11k-Fix-scan-request-param-frame-size-warnin.patch @@ -0,0 +1,161 @@ +From d45daa6d1a8da080f1b516c570a8428a7b9225e4 Mon Sep 17 00:00:00 2001 +From: Karthikeyan Kathirvel +Date: Tue, 6 Dec 2022 00:51:25 +0530 +Subject: [PATCH] wifi: ath11k: Fix scan request param frame size warning + +Following warning was observed + +drivers/net/wireless/ath/ath11k/mac.c:2351:1: warning: the frame +size of 1184 bytes is larger than 1024 bytes [-Wframe-larger-than=] + +A local variable is declared with a size larger than 1024 bytes +this causing a compilation warning. Change the local variable to +heap memory to fix the warning. + +Tested-on: IPQ8074 AHB WLAN.HK.2.7.0.1-01701-QCAHKSWPL_SILICONZ-1 v2 + +Signed-off-by: Karthikeyan Kathirvel +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20221205192125.13533-1-quic_kathirve@quicinc.com +--- + drivers/net/wireless/ath/ath11k/mac.c | 83 +++++++++++++++------------ + 1 file changed, 45 insertions(+), 38 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/mac.c ++++ b/drivers/net/wireless/ath/ath11k/mac.c +@@ -3612,7 +3612,7 @@ static int ath11k_mac_op_hw_scan(struct + struct ath11k *ar = hw->priv; + struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif); + struct cfg80211_scan_request *req = &hw_req->req; +- struct scan_req_params arg; ++ struct scan_req_params *arg = NULL; + int ret = 0; + int i; + u32 scan_timeout; +@@ -3640,72 +3640,78 @@ static int ath11k_mac_op_hw_scan(struct + if (ret) + goto exit; + +- memset(&arg, 0, sizeof(arg)); +- ath11k_wmi_start_scan_init(ar, &arg); +- arg.vdev_id = arvif->vdev_id; +- arg.scan_id = ATH11K_SCAN_ID; ++ arg = kzalloc(sizeof(*arg), GFP_KERNEL); ++ ++ if (!arg) { ++ ret = -ENOMEM; ++ goto exit; ++ } ++ ++ ath11k_wmi_start_scan_init(ar, arg); ++ arg->vdev_id = arvif->vdev_id; ++ arg->scan_id = ATH11K_SCAN_ID; + + if (req->ie_len) { +- arg.extraie.ptr = kmemdup(req->ie, req->ie_len, GFP_KERNEL); +- if (!arg.extraie.ptr) { ++ arg->extraie.ptr = kmemdup(req->ie, req->ie_len, GFP_KERNEL); ++ if (!arg->extraie.ptr) { + ret = -ENOMEM; + goto exit; + } +- arg.extraie.len = req->ie_len; ++ arg->extraie.len = req->ie_len; + } + + if (req->n_ssids) { +- arg.num_ssids = req->n_ssids; +- for (i = 0; i < arg.num_ssids; i++) { +- arg.ssid[i].length = req->ssids[i].ssid_len; +- memcpy(&arg.ssid[i].ssid, req->ssids[i].ssid, ++ arg->num_ssids = req->n_ssids; ++ for (i = 0; i < arg->num_ssids; i++) { ++ arg->ssid[i].length = req->ssids[i].ssid_len; ++ memcpy(&arg->ssid[i].ssid, req->ssids[i].ssid, + req->ssids[i].ssid_len); + } + } else { +- arg.scan_flags |= WMI_SCAN_FLAG_PASSIVE; ++ arg->scan_flags |= WMI_SCAN_FLAG_PASSIVE; + } + + if (req->n_channels) { +- arg.num_chan = req->n_channels; +- arg.chan_list = kcalloc(arg.num_chan, sizeof(*arg.chan_list), +- GFP_KERNEL); ++ arg->num_chan = req->n_channels; ++ arg->chan_list = kcalloc(arg->num_chan, sizeof(*arg->chan_list), ++ GFP_KERNEL); + +- if (!arg.chan_list) { ++ if (!arg->chan_list) { + ret = -ENOMEM; + goto exit; + } + +- for (i = 0; i < arg.num_chan; i++) +- arg.chan_list[i] = req->channels[i]->center_freq; ++ for (i = 0; i < arg->num_chan; i++) ++ arg->chan_list[i] = req->channels[i]->center_freq; + } + + if (req->flags & NL80211_SCAN_FLAG_RANDOM_ADDR) { +- arg.scan_f_add_spoofed_mac_in_probe = 1; +- ether_addr_copy(arg.mac_addr.addr, req->mac_addr); +- ether_addr_copy(arg.mac_mask.addr, req->mac_addr_mask); ++ arg->scan_f_add_spoofed_mac_in_probe = 1; ++ ether_addr_copy(arg->mac_addr.addr, req->mac_addr); ++ ether_addr_copy(arg->mac_mask.addr, req->mac_addr_mask); + } + + /* if duration is set, default dwell times will be overwritten */ + if (req->duration) { +- arg.dwell_time_active = req->duration; +- arg.dwell_time_active_2g = req->duration; +- arg.dwell_time_active_6g = req->duration; +- arg.dwell_time_passive = req->duration; +- arg.dwell_time_passive_6g = req->duration; +- arg.burst_duration = req->duration; ++ arg->dwell_time_active = req->duration; ++ arg->dwell_time_active_2g = req->duration; ++ arg->dwell_time_active_6g = req->duration; ++ arg->dwell_time_passive = req->duration; ++ arg->dwell_time_passive_6g = req->duration; ++ arg->burst_duration = req->duration; + +- scan_timeout = min_t(u32, arg.max_rest_time * +- (arg.num_chan - 1) + (req->duration + ++ scan_timeout = min_t(u32, arg->max_rest_time * ++ (arg->num_chan - 1) + (req->duration + + ATH11K_SCAN_CHANNEL_SWITCH_WMI_EVT_OVERHEAD) * +- arg.num_chan, arg.max_scan_time); ++ arg->num_chan, arg->max_scan_time); + } else { +- scan_timeout = arg.max_scan_time; ++ scan_timeout = arg->max_scan_time; + } + + /* Add a margin to account for event/command processing */ + scan_timeout += ATH11K_MAC_SCAN_CMD_EVT_OVERHEAD; + +- ret = ath11k_start_scan(ar, &arg); ++ ret = ath11k_start_scan(ar, arg); + if (ret) { + ath11k_warn(ar->ab, "failed to start hw scan: %d\n", ret); + spin_lock_bh(&ar->data_lock); +@@ -3717,10 +3723,11 @@ static int ath11k_mac_op_hw_scan(struct + msecs_to_jiffies(scan_timeout)); + + exit: +- kfree(arg.chan_list); +- +- if (req->ie_len) +- kfree(arg.extraie.ptr); ++ if (arg) { ++ kfree(arg->chan_list); ++ kfree(arg->extraie.ptr); ++ kfree(arg); ++ } + + mutex_unlock(&ar->conf_mutex); + diff --git a/package/kernel/mac80211/patches/ath11k/0020-wifi-ath11k-fix-monitor-mode-bringup-crash.patch b/package/kernel/mac80211/patches/ath11k/0020-wifi-ath11k-fix-monitor-mode-bringup-crash.patch new file mode 100644 index 00000000000..62397de7264 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0020-wifi-ath11k-fix-monitor-mode-bringup-crash.patch @@ -0,0 +1,79 @@ +From 950b43f8bd8a4d476d2da6d2a083a89bcd3c90d7 Mon Sep 17 00:00:00 2001 +From: Nagarajan Maran +Date: Tue, 29 Nov 2022 19:55:32 +0530 +Subject: [PATCH] wifi: ath11k: fix monitor mode bringup crash + +When the interface is brought up in monitor mode, it leads +to NULL pointer dereference crash. This crash happens when +the packet type is extracted for a SKB. This extraction +which is present in the received msdu delivery path,is +not needed for the monitor ring packets since they are +all RAW packets. Hence appending the flags with +"RX_FLAG_ONLY_MONITOR" to skip that extraction. + +Observed calltrace: + +Unable to handle kernel NULL pointer dereference at virtual address +0000000000000064 +Mem abort info: + ESR = 0x0000000096000004 + EC = 0x25: DABT (current EL), IL = 32 bits + SET = 0, FnV = 0 + EA = 0, S1PTW = 0 + FSC = 0x04: level 0 translation fault +Data abort info: + ISV = 0, ISS = 0x00000004 + CM = 0, WnR = 0 +user pgtable: 4k pages, 48-bit VAs, pgdp=0000000048517000 +[0000000000000064] pgd=0000000000000000, p4d=0000000000000000 +Internal error: Oops: 0000000096000004 [#1] PREEMPT SMP +Modules linked in: ath11k_pci ath11k qmi_helpers +CPU: 2 PID: 1781 Comm: napi/-271 Not tainted +6.1.0-rc5-wt-ath-656295-gef907406320c-dirty #6 +Hardware name: Qualcomm Technologies, Inc. IPQ8074/AP-HK10-C2 (DT) +pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) +pc : ath11k_hw_qcn9074_rx_desc_get_decap_type+0x34/0x60 [ath11k] +lr : ath11k_hw_qcn9074_rx_desc_get_decap_type+0x5c/0x60 [ath11k] +sp : ffff80000ef5bb10 +x29: ffff80000ef5bb10 x28: 0000000000000000 x27: ffff000007baafa0 +x26: ffff000014a91ed0 x25: 0000000000000000 x24: 0000000000000000 +x23: ffff800002b77378 x22: ffff000014a91ec0 x21: ffff000006c8d600 +x20: 0000000000000000 x19: ffff800002b77740 x18: 0000000000000006 +x17: 736564203634343a x16: 656e694c20657079 x15: 0000000000000143 +x14: 00000000ffffffea x13: ffff80000ef5b8b8 x12: ffff80000ef5b8c8 +x11: ffff80000a591d30 x10: ffff80000a579d40 x9 : c0000000ffffefff +x8 : 0000000000000003 x7 : 0000000000017fe8 x6 : ffff80000a579ce8 +x5 : 0000000000000000 x4 : 0000000000000000 x3 : 0000000000000000 +x2 : 3a35ec12ed7f8900 x1 : 0000000000000000 x0 : 0000000000000052 +Call trace: + ath11k_hw_qcn9074_rx_desc_get_decap_type+0x34/0x60 [ath11k] + ath11k_dp_rx_deliver_msdu.isra.42+0xa4/0x3d0 [ath11k] + ath11k_dp_rx_mon_deliver.isra.43+0x2f8/0x458 [ath11k] + ath11k_dp_rx_process_mon_rings+0x310/0x4c0 [ath11k] + ath11k_dp_service_srng+0x234/0x338 [ath11k] + ath11k_pcic_ext_grp_napi_poll+0x30/0xb8 [ath11k] + __napi_poll+0x5c/0x190 + napi_threaded_poll+0xf0/0x118 + kthread+0xf4/0x110 + ret_from_fork+0x10/0x20 + +Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 +Reported-by: Florian Schmidt +Link: https://bugzilla.kernel.org/show_bug.cgi?id=216573 +Signed-off-by: Nagarajan Maran +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20221129142532.23421-1-quic_nmaran@quicinc.com +--- + drivers/net/wireless/ath/ath11k/dp_rx.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/net/wireless/ath/ath11k/dp_rx.c ++++ b/drivers/net/wireless/ath/ath11k/dp_rx.c +@@ -5022,6 +5022,7 @@ static int ath11k_dp_rx_mon_deliver(stru + } else { + rxs->flag |= RX_FLAG_ALLOW_SAME_PN; + } ++ rxs->flag |= RX_FLAG_ONLY_MONITOR; + ath11k_update_radiotap(ar, ppduinfo, mon_skb, rxs); + + ath11k_dp_rx_deliver_msdu(ar, napi, mon_skb, rxs); From 1909a3d69be15b34430f8c30b9ec7c8ef07c9650 Mon Sep 17 00:00:00 2001 From: Linhui Liu Date: Thu, 12 Jan 2023 18:10:02 +0800 Subject: [PATCH 49/51] tools/mkimage: update to 2023.01 Remove upstreamed patches: - 020-tools-mtk_image-split-gfh-header-verification-into-a.patch - 021-tools-mtk_image-split-the-code-of-generating-NAND-he.patch - 022-tools-mtk_image-add-support-for-nand-headers-used-by.patch Signed-off-by: Linhui Liu --- tools/mkimage/Makefile | 4 +- ...split-gfh-header-verification-into-a.patch | 89 -- ...split-the-code-of-generating-NAND-he.patch | 821 ------------------ ...add-support-for-nand-headers-used-by.patch | 702 --------------- .../030-allow-to-use-different-magic.patch | 4 +- 5 files changed, 4 insertions(+), 1616 deletions(-) delete mode 100644 tools/mkimage/patches/020-tools-mtk_image-split-gfh-header-verification-into-a.patch delete mode 100644 tools/mkimage/patches/021-tools-mtk_image-split-the-code-of-generating-NAND-he.patch delete mode 100644 tools/mkimage/patches/022-tools-mtk_image-add-support-for-nand-headers-used-by.patch diff --git a/tools/mkimage/Makefile b/tools/mkimage/Makefile index 10fe6eea431..022ac219749 100644 --- a/tools/mkimage/Makefile +++ b/tools/mkimage/Makefile @@ -7,14 +7,14 @@ include $(TOPDIR)/rules.mk PKG_NAME:=mkimage -PKG_VERSION:=2022.10 +PKG_VERSION:=2023.01 PKG_SOURCE:=u-boot-$(PKG_VERSION).tar.bz2 PKG_SOURCE_URL:= \ https://mirror.cyberbits.eu/u-boot \ https://ftp.denx.de/pub/u-boot \ ftp://ftp.denx.de/pub/u-boot -PKG_HASH:=50b4482a505bc281ba8470c399a3c26e145e29b23500bc35c50debd7fa46bdf8 +PKG_HASH:=69423bad380f89a0916636e89e6dcbd2e4512d584308d922d1039d1e4331950f HOST_BUILD_DIR:=$(BUILD_DIR_HOST)/u-boot-$(PKG_VERSION) diff --git a/tools/mkimage/patches/020-tools-mtk_image-split-gfh-header-verification-into-a.patch b/tools/mkimage/patches/020-tools-mtk_image-split-gfh-header-verification-into-a.patch deleted file mode 100644 index c8747ae1547..00000000000 --- a/tools/mkimage/patches/020-tools-mtk_image-split-gfh-header-verification-into-a.patch +++ /dev/null @@ -1,89 +0,0 @@ -From b6bb61fd3818f4a3025fedbe4d15dbeeaef6ee82 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Tue, 2 Aug 2022 17:21:34 +0800 -Subject: [PATCH 28/31] tools: mtk_image: split gfh header verification into a - new function - -The verification code of gfh header for NAND and non-NAND are identical. -It's better to define a individual function to reduce redundancy. - -Reviewed-by: Simon Glass -Signed-off-by: Weijie Gao ---- - tools/mtk_image.c | 51 +++++++++++++++++++---------------------------- - 1 file changed, 21 insertions(+), 30 deletions(-) - ---- a/tools/mtk_image.c -+++ b/tools/mtk_image.c -@@ -480,6 +480,25 @@ static int mtk_image_vrec_header(struct - return SHA256_SUM_LEN; - } - -+static int mtk_image_verify_gfh(struct gfh_header *gfh, uint32_t type, int print) -+{ -+ if (strcmp(gfh->file_info.name, GFH_FILE_INFO_NAME)) -+ return -1; -+ -+ if (le32_to_cpu(gfh->file_info.flash_type) != type) -+ return -1; -+ -+ if (print) -+ printf("Load Address: %08x\n", -+ le32_to_cpu(gfh->file_info.load_addr) + -+ le32_to_cpu(gfh->file_info.jump_offset)); -+ -+ if (print) -+ printf("Architecture: %s\n", is_arm64_image ? "ARM64" : "ARM"); -+ -+ return 0; -+} -+ - static int mtk_image_verify_gen_header(const uint8_t *ptr, int print) - { - union gen_boot_header *gbh = (union gen_boot_header *)ptr; -@@ -542,21 +561,7 @@ static int mtk_image_verify_gen_header(c - - gfh = (struct gfh_header *)(ptr + gfh_offset); - -- if (strcmp(gfh->file_info.name, GFH_FILE_INFO_NAME)) -- return -1; -- -- if (le32_to_cpu(gfh->file_info.flash_type) != GFH_FLASH_TYPE_GEN) -- return -1; -- -- if (print) -- printf("Load Address: %08x\n", -- le32_to_cpu(gfh->file_info.load_addr) + -- le32_to_cpu(gfh->file_info.jump_offset)); -- -- if (print) -- printf("Architecture: %s\n", is_arm64_image ? "ARM64" : "ARM"); -- -- return 0; -+ return mtk_image_verify_gfh(gfh, GFH_FLASH_TYPE_GEN, print); - } - - static int mtk_image_verify_nand_header(const uint8_t *ptr, int print) -@@ -610,21 +615,7 @@ static int mtk_image_verify_nand_header( - - gfh = (struct gfh_header *)(ptr + 2 * le16_to_cpu(nh->pagesize)); - -- if (strcmp(gfh->file_info.name, GFH_FILE_INFO_NAME)) -- return -1; -- -- if (le32_to_cpu(gfh->file_info.flash_type) != GFH_FLASH_TYPE_NAND) -- return -1; -- -- if (print) -- printf("Load Address: %08x\n", -- le32_to_cpu(gfh->file_info.load_addr) + -- le32_to_cpu(gfh->file_info.jump_offset)); -- -- if (print) -- printf("Architecture: %s\n", is_arm64_image ? "ARM64" : "ARM"); -- -- return 0; -+ return mtk_image_verify_gfh(gfh, GFH_FLASH_TYPE_NAND, print); - } - - static uint32_t crc32be_cal(const void *data, size_t length) diff --git a/tools/mkimage/patches/021-tools-mtk_image-split-the-code-of-generating-NAND-he.patch b/tools/mkimage/patches/021-tools-mtk_image-split-the-code-of-generating-NAND-he.patch deleted file mode 100644 index 9a5332f6950..00000000000 --- a/tools/mkimage/patches/021-tools-mtk_image-split-the-code-of-generating-NAND-he.patch +++ /dev/null @@ -1,821 +0,0 @@ -From 20ebf03eab571b25e9f62b2764ab84932111dcd6 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Tue, 2 Aug 2022 17:23:57 +0800 -Subject: [PATCH 29/31] tools: mtk_image: split the code of generating NAND - header into a new file - -The predefined NAND headers take too much spaces in the mtk_image.c. -Moving them into a new file can significantly improve the readability of -both mtk_image.c and the new mtk_nand_headers.c. - -This is a preparation for adding more NAND headers. - -Reviewed-by: Simon Glass -Signed-off-by: Weijie Gao ---- - tools/Makefile | 1 + - tools/mtk_image.c | 305 ++++++--------------------------------- - tools/mtk_image.h | 25 ---- - tools/mtk_nand_headers.c | 286 ++++++++++++++++++++++++++++++++++++ - tools/mtk_nand_headers.h | 61 ++++++++ - 5 files changed, 389 insertions(+), 289 deletions(-) - create mode 100644 tools/mtk_nand_headers.c - create mode 100644 tools/mtk_nand_headers.h - ---- a/tools/Makefile -+++ b/tools/Makefile -@@ -147,6 +147,7 @@ dumpimage-mkimage-objs := aisimage.o \ - gpimage.o \ - gpimage-common.o \ - mtk_image.o \ -+ mtk_nand_headers.o \ - $(ECDSA_OBJS-y) \ - $(RSA_OBJS-y) \ - $(AES_OBJS-y) ---- a/tools/mtk_image.c -+++ b/tools/mtk_image.c -@@ -12,216 +12,7 @@ - #include - #include "imagetool.h" - #include "mtk_image.h" -- --/* NAND header for SPI-NAND with 2KB page + 64B spare */ --static const union nand_boot_header snand_hdr_2k_64_data = { -- .data = { -- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -- 0x00, 0x00, 0x00, 0x08, 0x03, 0x00, 0x40, 0x00, -- 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x7B, 0xC4, 0x17, 0x9D, -- 0xCA, 0x42, 0x90, 0xD0, 0x98, 0xD0, 0xE0, 0xF7, -- 0xDB, 0xCD, 0x16, 0xF6, 0x03, 0x73, 0xD2, 0xB8, -- 0x93, 0xB2, 0x56, 0x5A, 0x84, 0x6E, 0x00, 0x00 -- } --}; -- --/* NAND header for SPI-NAND with 2KB page + 120B/128B spare */ --static const union nand_boot_header snand_hdr_2k_128_data = { -- .data = { -- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, -- 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x90, 0x28, 0xED, 0x13, -- 0x7F, 0x12, 0x22, 0xCD, 0x3D, 0x06, 0xF1, 0xB3, -- 0x6F, 0x2E, 0xD9, 0xA0, 0x9D, 0x7A, 0xBD, 0xD7, -- 0xB3, 0x28, 0x3C, 0x13, 0xDB, 0x4E, 0x00, 0x00 -- } --}; -- --/* NAND header for SPI-NAND with 4KB page + 256B spare */ --static const union nand_boot_header snand_hdr_4k_256_data = { -- .data = { -- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -- 0x00, 0x00, 0x00, 0x10, 0x05, 0x00, 0xE0, 0x00, -- 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x47, 0xED, 0x0E, 0xC3, -- 0x83, 0xBF, 0x41, 0xD2, 0x85, 0x21, 0x97, 0x57, -- 0xC4, 0x2E, 0x6B, 0x7A, 0x40, 0xE0, 0xCF, 0x8F, -- 0x37, 0xBD, 0x17, 0xB6, 0xC7, 0xFE, 0x00, 0x00 -- } --}; -- --/* NAND header for Parallel NAND 1Gb with 2KB page + 64B spare */ --static const union nand_boot_header nand_hdr_1gb_2k_64_data = { -- .data = { -- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, -- 0x40, 0x00, 0x00, 0x04, 0x0B, 0x00, 0x11, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x12, 0x28, 0x1C, 0x12, -- 0x8F, 0xFD, 0xF8, 0x32, 0x6F, 0x6D, 0xCF, 0x6C, -- 0xDA, 0x21, 0x70, 0x8C, 0xDA, 0x0A, 0x22, 0x82, -- 0xAA, 0x59, 0xFA, 0x7C, 0x42, 0x2D, 0x00, 0x00 -- } --}; -- --/* NAND header for Parallel NAND 2Gb with 2KB page + 64B spare */ --static const union nand_boot_header nand_hdr_2gb_2k_64_data = { -- .data = { -- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, -- 0x40, 0x00, 0x00, 0x08, 0x0B, 0x00, 0x11, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x20, 0x9C, 0x3D, 0x2D, -- 0x7B, 0x68, 0x63, 0x52, 0x2E, 0x04, 0x63, 0xF1, -- 0x35, 0x4E, 0x44, 0x3E, 0xF8, 0xAC, 0x9B, 0x95, -- 0xAB, 0xFE, 0xE4, 0xE1, 0xD5, 0xF9, 0x00, 0x00 -- } --}; -- --/* NAND header for Parallel NAND 4Gb with 2KB page + 64B spare */ --static const union nand_boot_header nand_hdr_4gb_2k_64_data = { -- .data = { -- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, -- 0x40, 0x00, 0x00, 0x10, 0x0B, 0x00, 0x11, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0xE3, 0x0F, 0x86, 0x32, -- 0x68, 0x05, 0xD9, 0xC8, 0x13, 0xDF, 0xC5, 0x0B, -- 0x35, 0x3A, 0x68, 0xA5, 0x3C, 0x0C, 0x73, 0x87, -- 0x63, 0xB0, 0xBE, 0xCC, 0x84, 0x47, 0x00, 0x00 -- } --}; -- --/* NAND header for Parallel NAND 2Gb with 2KB page + 128B spare */ --static const union nand_boot_header nand_hdr_2gb_2k_128_data = { -- .data = { -- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, -- 0x40, 0x00, 0x00, 0x08, 0x0B, 0x00, 0x11, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x01, 0xA5, 0xE9, 0x5A, -- 0xDF, 0x58, 0x62, 0x41, 0xD6, 0x26, 0x77, 0xBC, -- 0x76, 0x1F, 0x27, 0x4E, 0x4F, 0x6C, 0xC3, 0xF0, -- 0x36, 0xDE, 0xD9, 0xB3, 0xFF, 0x93, 0x00, 0x00 -- } --}; -- --/* NAND header for Parallel NAND 4Gb with 2KB page + 128B spare */ --static const union nand_boot_header nand_hdr_4gb_2k_128_data = { -- .data = { -- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, -- 0x40, 0x00, 0x00, 0x10, 0x0B, 0x00, 0x11, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0xC2, 0x36, 0x52, 0x45, -- 0xCC, 0x35, 0xD8, 0xDB, 0xEB, 0xFD, 0xD1, 0x46, -- 0x76, 0x6B, 0x0B, 0xD5, 0x8B, 0xCC, 0x2B, 0xE2, -- 0xFE, 0x90, 0x83, 0x9E, 0xAE, 0x2D, 0x00, 0x00 -- } --}; -- --static const struct nand_header_type { -- const char *name; -- const union nand_boot_header *data; --} nand_headers[] = { -- { -- .name = "2k+64", -- .data = &snand_hdr_2k_64_data -- }, { -- .name = "2k+120", -- .data = &snand_hdr_2k_128_data -- }, { -- .name = "2k+128", -- .data = &snand_hdr_2k_128_data -- }, { -- .name = "4k+256", -- .data = &snand_hdr_4k_256_data -- }, { -- .name = "1g:2k+64", -- .data = &nand_hdr_1gb_2k_64_data -- }, { -- .name = "2g:2k+64", -- .data = &nand_hdr_2gb_2k_64_data -- }, { -- .name = "4g:2k+64", -- .data = &nand_hdr_4gb_2k_64_data -- }, { -- .name = "2g:2k+128", -- .data = &nand_hdr_2gb_2k_128_data -- }, { -- .name = "4g:2k+128", -- .data = &nand_hdr_4gb_2k_128_data -- } --}; -+#include "mtk_nand_headers.h" - - static const struct brom_img_type { - const char *name; -@@ -264,6 +55,7 @@ static uint32_t crc32tbl[256]; - - /* NAND header selected by user */ - static const union nand_boot_header *hdr_nand; -+static uint32_t hdr_nand_size; - - /* GFH header + 2 * 4KB pages of NAND */ - static char hdr_tmp[sizeof(struct gfh_header) + 0x2000]; -@@ -402,12 +194,7 @@ static int mtk_brom_parse_imagename(cons - } - - /* parse nand header type */ -- for (i = 0; i < ARRAY_SIZE(nand_headers); i++) { -- if (!strcmp(nand_headers[i].name, nandinfo)) { -- hdr_nand = nand_headers[i].data; -- break; -- } -- } -+ hdr_nand = mtk_nand_header_find(nandinfo); - - /* parse device header offset */ - if (hdr_offs && hdr_offs[0]) -@@ -432,6 +219,9 @@ static int mtk_brom_parse_imagename(cons - return -EINVAL; - } - -+ if (hdr_media == BRLYT_TYPE_NAND || hdr_media == BRLYT_TYPE_SNAND) -+ hdr_nand_size = mtk_nand_header_size(hdr_nand); -+ - return 0; - } - -@@ -468,7 +258,7 @@ static int mtk_image_vrec_header(struct - } - - if (hdr_media == BRLYT_TYPE_NAND || hdr_media == BRLYT_TYPE_SNAND) -- tparams->header_size = 2 * le16_to_cpu(hdr_nand->pagesize); -+ tparams->header_size = hdr_nand_size; - else - tparams->header_size = sizeof(struct gen_device_header); - -@@ -566,16 +356,17 @@ static int mtk_image_verify_gen_header(c - - static int mtk_image_verify_nand_header(const uint8_t *ptr, int print) - { -- union nand_boot_header *nh = (union nand_boot_header *)ptr; - struct brom_layout_header *bh; -+ struct nand_header_info info; - struct gfh_header *gfh; - const char *bootmedia; -+ int ret; - -- if (strncmp(nh->version, NAND_BOOT_VERSION, sizeof(nh->version)) || -- strcmp(nh->id, NAND_BOOT_ID)) -- return -1; -+ ret = mtk_nand_header_info(ptr, &info); -+ if (ret < 0) -+ return ret; - -- bh = (struct brom_layout_header *)(ptr + le16_to_cpu(nh->pagesize)); -+ bh = (struct brom_layout_header *)(ptr + info.page_size); - - if (strcmp(bh->name, BRLYT_NAME)) - return -1; -@@ -586,34 +377,23 @@ static int mtk_image_verify_nand_header( - if (le32_to_cpu(bh->type) == BRLYT_TYPE_NAND) - bootmedia = "Parallel NAND"; - else if (le32_to_cpu(bh->type) == BRLYT_TYPE_SNAND) -- bootmedia = "Serial NAND"; -+ bootmedia = "Serial NAND (SNFI/AP)"; - else - return -1; - } - - if (print) { -- printf("Boot Media: %s\n", bootmedia); -- -- if (le32_to_cpu(bh->type) == BRLYT_TYPE_NAND) { -- uint64_t capacity = -- (uint64_t)le16_to_cpu(nh->numblocks) * -- (uint64_t)le16_to_cpu(nh->pages_of_block) * -- (uint64_t)le16_to_cpu(nh->pagesize) * 8; -- printf("Capacity: %dGb\n", -- (uint32_t)(capacity >> 30)); -- } -+ printf("Boot Media: %s\n", bootmedia); - -- if (le16_to_cpu(nh->pagesize) >= 1024) -- printf("Page Size: %dKB\n", -- le16_to_cpu(nh->pagesize) >> 10); -+ if (info.page_size >= 1024) -+ printf("Page Size: %dKB\n", info.page_size >> 10); - else -- printf("Page Size: %dB\n", -- le16_to_cpu(nh->pagesize)); -+ printf("Page Size: %dB\n", info.page_size); - -- printf("Spare Size: %dB\n", le16_to_cpu(nh->oobsize)); -+ printf("Spare Size: %dB\n", info.spare_size); - } - -- gfh = (struct gfh_header *)(ptr + 2 * le16_to_cpu(nh->pagesize)); -+ gfh = (struct gfh_header *)(ptr + info.gfh_offset); - - return mtk_image_verify_gfh(gfh, GFH_FLASH_TYPE_NAND, print); - } -@@ -713,7 +493,7 @@ static int mtk_image_verify_header(unsig - if (image_get_magic(hdr) == IH_MAGIC) - return mtk_image_verify_mt7621_header(ptr, 0); - -- if (!strcmp((char *)ptr, NAND_BOOT_NAME)) -+ if (is_mtk_nand_header(ptr)) - return mtk_image_verify_nand_header(ptr, 0); - else - return mtk_image_verify_gen_header(ptr, 0); -@@ -739,7 +519,7 @@ static void mtk_image_print_header(const - return; - } - -- if (!strcmp((char *)ptr, NAND_BOOT_NAME)) -+ if (is_mtk_nand_header(ptr)) - mtk_image_verify_nand_header(ptr, 1); - else - mtk_image_verify_gen_header(ptr, 1); -@@ -870,36 +650,33 @@ static void mtk_image_set_gen_header(voi - static void mtk_image_set_nand_header(void *ptr, off_t filesize, - uint32_t loadaddr) - { -- union nand_boot_header *nh = (union nand_boot_header *)ptr; - struct brom_layout_header *brlyt; - struct gfh_header *gfh; -- uint32_t payload_pages; -- int i; -+ uint32_t payload_pages, nand_page_size; - -- /* NAND device header, repeat 4 times */ -- for (i = 0; i < 4; i++) -- memcpy(nh + i, hdr_nand, sizeof(union nand_boot_header)); -+ /* NAND header */ -+ nand_page_size = mtk_nand_header_put(hdr_nand, ptr); - -- /* BRLYT header */ -- payload_pages = (filesize + le16_to_cpu(hdr_nand->pagesize) - 1) / -- le16_to_cpu(hdr_nand->pagesize); -- brlyt = (struct brom_layout_header *) -- (ptr + le16_to_cpu(hdr_nand->pagesize)); -- put_brom_layout_header(brlyt, hdr_media); -- brlyt->header_size = cpu_to_le32(2); -- brlyt->total_size = cpu_to_le32(payload_pages); -- brlyt->header_size_2 = brlyt->header_size; -- brlyt->total_size_2 = brlyt->total_size; -- brlyt->unused = cpu_to_le32(1); -+ if (nand_page_size) { -+ /* BRLYT header */ -+ payload_pages = (filesize + nand_page_size - 1) / -+ nand_page_size; -+ brlyt = (struct brom_layout_header *)(ptr + nand_page_size); -+ put_brom_layout_header(brlyt, hdr_media); -+ brlyt->header_size = cpu_to_le32(2); -+ brlyt->total_size = cpu_to_le32(payload_pages); -+ brlyt->header_size_2 = brlyt->header_size; -+ brlyt->total_size_2 = brlyt->total_size; -+ brlyt->unused = cpu_to_le32(1); -+ } - - /* GFH header */ -- gfh = (struct gfh_header *)(ptr + 2 * le16_to_cpu(hdr_nand->pagesize)); -- put_ghf_header(gfh, filesize, 2 * le16_to_cpu(hdr_nand->pagesize), -- loadaddr, GFH_FLASH_TYPE_NAND); -+ gfh = (struct gfh_header *)(ptr + hdr_nand_size); -+ put_ghf_header(gfh, filesize, hdr_nand_size, loadaddr, -+ GFH_FLASH_TYPE_NAND); - - /* Generate SHA256 hash */ -- put_hash((uint8_t *)gfh, -- filesize - 2 * le16_to_cpu(hdr_nand->pagesize) - SHA256_SUM_LEN); -+ put_hash((uint8_t *)gfh, filesize - hdr_nand_size - SHA256_SUM_LEN); - } - - static void mtk_image_set_mt7621_header(void *ptr, off_t filesize, ---- a/tools/mtk_image.h -+++ b/tools/mtk_image.h -@@ -26,31 +26,6 @@ union gen_boot_header { - #define SF_BOOT_NAME "SF_BOOT" - #define SDMMC_BOOT_NAME "SDMMC_BOOT" - --/* Header for NAND */ --union nand_boot_header { -- struct { -- char name[12]; -- char version[4]; -- char id[8]; -- uint16_t ioif; -- uint16_t pagesize; -- uint16_t addrcycles; -- uint16_t oobsize; -- uint16_t pages_of_block; -- uint16_t numblocks; -- uint16_t writesize_shift; -- uint16_t erasesize_shift; -- uint8_t dummy[60]; -- uint8_t ecc_parity[28]; -- }; -- -- uint8_t data[0x80]; --}; -- --#define NAND_BOOT_NAME "BOOTLOADER!" --#define NAND_BOOT_VERSION "V006" --#define NAND_BOOT_ID "NFIINFO" -- - /* BootROM layout header */ - struct brom_layout_header { - char name[8]; ---- /dev/null -+++ b/tools/mtk_nand_headers.c -@@ -0,0 +1,286 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * MediaTek BootROM NAND header definitions -+ * -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Weijie Gao -+ */ -+ -+#include -+#include -+#include "imagetool.h" -+#include "mtk_image.h" -+#include "mtk_nand_headers.h" -+ -+/* NAND header for SPI-NAND with 2KB page + 64B spare */ -+static const union nand_boot_header snand_hdr_2k_64_data = { -+ .data = { -+ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -+ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -+ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -+ 0x00, 0x00, 0x00, 0x08, 0x03, 0x00, 0x40, 0x00, -+ 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x7B, 0xC4, 0x17, 0x9D, -+ 0xCA, 0x42, 0x90, 0xD0, 0x98, 0xD0, 0xE0, 0xF7, -+ 0xDB, 0xCD, 0x16, 0xF6, 0x03, 0x73, 0xD2, 0xB8, -+ 0x93, 0xB2, 0x56, 0x5A, 0x84, 0x6E, 0x00, 0x00 -+ } -+}; -+ -+/* NAND header for SPI-NAND with 2KB page + 120B/128B spare */ -+static const union nand_boot_header snand_hdr_2k_128_data = { -+ .data = { -+ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -+ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -+ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -+ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, -+ 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x90, 0x28, 0xED, 0x13, -+ 0x7F, 0x12, 0x22, 0xCD, 0x3D, 0x06, 0xF1, 0xB3, -+ 0x6F, 0x2E, 0xD9, 0xA0, 0x9D, 0x7A, 0xBD, 0xD7, -+ 0xB3, 0x28, 0x3C, 0x13, 0xDB, 0x4E, 0x00, 0x00 -+ } -+}; -+ -+/* NAND header for SPI-NAND with 4KB page + 256B spare */ -+static const union nand_boot_header snand_hdr_4k_256_data = { -+ .data = { -+ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -+ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -+ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -+ 0x00, 0x00, 0x00, 0x10, 0x05, 0x00, 0xE0, 0x00, -+ 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x47, 0xED, 0x0E, 0xC3, -+ 0x83, 0xBF, 0x41, 0xD2, 0x85, 0x21, 0x97, 0x57, -+ 0xC4, 0x2E, 0x6B, 0x7A, 0x40, 0xE0, 0xCF, 0x8F, -+ 0x37, 0xBD, 0x17, 0xB6, 0xC7, 0xFE, 0x00, 0x00 -+ } -+}; -+ -+/* NAND header for Parallel NAND 1Gb with 2KB page + 64B spare */ -+static const union nand_boot_header nand_hdr_1gb_2k_64_data = { -+ .data = { -+ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -+ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -+ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -+ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, -+ 0x40, 0x00, 0x00, 0x04, 0x0B, 0x00, 0x11, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x12, 0x28, 0x1C, 0x12, -+ 0x8F, 0xFD, 0xF8, 0x32, 0x6F, 0x6D, 0xCF, 0x6C, -+ 0xDA, 0x21, 0x70, 0x8C, 0xDA, 0x0A, 0x22, 0x82, -+ 0xAA, 0x59, 0xFA, 0x7C, 0x42, 0x2D, 0x00, 0x00 -+ } -+}; -+ -+/* NAND header for Parallel NAND 2Gb with 2KB page + 64B spare */ -+static const union nand_boot_header nand_hdr_2gb_2k_64_data = { -+ .data = { -+ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -+ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -+ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -+ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, -+ 0x40, 0x00, 0x00, 0x08, 0x0B, 0x00, 0x11, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x20, 0x9C, 0x3D, 0x2D, -+ 0x7B, 0x68, 0x63, 0x52, 0x2E, 0x04, 0x63, 0xF1, -+ 0x35, 0x4E, 0x44, 0x3E, 0xF8, 0xAC, 0x9B, 0x95, -+ 0xAB, 0xFE, 0xE4, 0xE1, 0xD5, 0xF9, 0x00, 0x00 -+ } -+}; -+ -+/* NAND header for Parallel NAND 4Gb with 2KB page + 64B spare */ -+static const union nand_boot_header nand_hdr_4gb_2k_64_data = { -+ .data = { -+ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -+ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -+ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -+ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, -+ 0x40, 0x00, 0x00, 0x10, 0x0B, 0x00, 0x11, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xE3, 0x0F, 0x86, 0x32, -+ 0x68, 0x05, 0xD9, 0xC8, 0x13, 0xDF, 0xC5, 0x0B, -+ 0x35, 0x3A, 0x68, 0xA5, 0x3C, 0x0C, 0x73, 0x87, -+ 0x63, 0xB0, 0xBE, 0xCC, 0x84, 0x47, 0x00, 0x00 -+ } -+}; -+ -+/* NAND header for Parallel NAND 2Gb with 2KB page + 128B spare */ -+static const union nand_boot_header nand_hdr_2gb_2k_128_data = { -+ .data = { -+ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -+ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -+ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -+ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, -+ 0x40, 0x00, 0x00, 0x08, 0x0B, 0x00, 0x11, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x01, 0xA5, 0xE9, 0x5A, -+ 0xDF, 0x58, 0x62, 0x41, 0xD6, 0x26, 0x77, 0xBC, -+ 0x76, 0x1F, 0x27, 0x4E, 0x4F, 0x6C, 0xC3, 0xF0, -+ 0x36, 0xDE, 0xD9, 0xB3, 0xFF, 0x93, 0x00, 0x00 -+ } -+}; -+ -+/* NAND header for Parallel NAND 4Gb with 2KB page + 128B spare */ -+static const union nand_boot_header nand_hdr_4gb_2k_128_data = { -+ .data = { -+ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -+ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -+ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -+ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, -+ 0x40, 0x00, 0x00, 0x10, 0x0B, 0x00, 0x11, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xC2, 0x36, 0x52, 0x45, -+ 0xCC, 0x35, 0xD8, 0xDB, 0xEB, 0xFD, 0xD1, 0x46, -+ 0x76, 0x6B, 0x0B, 0xD5, 0x8B, 0xCC, 0x2B, 0xE2, -+ 0xFE, 0x90, 0x83, 0x9E, 0xAE, 0x2D, 0x00, 0x00 -+ } -+}; -+ -+static const struct nand_header_type { -+ const char *name; -+ const union nand_boot_header *data; -+} nand_headers[] = { -+ { -+ .name = "2k+64", -+ .data = &snand_hdr_2k_64_data -+ }, { -+ .name = "2k+120", -+ .data = &snand_hdr_2k_128_data -+ }, { -+ .name = "2k+128", -+ .data = &snand_hdr_2k_128_data -+ }, { -+ .name = "4k+256", -+ .data = &snand_hdr_4k_256_data -+ }, { -+ .name = "1g:2k+64", -+ .data = &nand_hdr_1gb_2k_64_data -+ }, { -+ .name = "2g:2k+64", -+ .data = &nand_hdr_2gb_2k_64_data -+ }, { -+ .name = "4g:2k+64", -+ .data = &nand_hdr_4gb_2k_64_data -+ }, { -+ .name = "2g:2k+128", -+ .data = &nand_hdr_2gb_2k_128_data -+ }, { -+ .name = "4g:2k+128", -+ .data = &nand_hdr_4gb_2k_128_data -+ } -+}; -+ -+const union nand_boot_header *mtk_nand_header_find(const char *name) -+{ -+ uint32_t i; -+ -+ for (i = 0; i < ARRAY_SIZE(nand_headers); i++) { -+ if (!strcmp(nand_headers[i].name, name)) -+ return nand_headers[i].data; -+ } -+ -+ return NULL; -+} -+ -+uint32_t mtk_nand_header_size(const union nand_boot_header *hdr_nand) -+{ -+ return 2 * le16_to_cpu(hdr_nand->pagesize); -+} -+ -+static int mtk_nand_header_ap_info(const void *ptr, -+ struct nand_header_info *info) -+{ -+ union nand_boot_header *nh = (union nand_boot_header *)ptr; -+ -+ if (strncmp(nh->version, NAND_BOOT_VERSION, sizeof(nh->version)) || -+ strcmp(nh->id, NAND_BOOT_ID)) -+ return -1; -+ -+ info->page_size = le16_to_cpu(nh->pagesize); -+ info->spare_size = le16_to_cpu(nh->oobsize); -+ info->gfh_offset = 2 * info->page_size; -+ -+ return 0; -+} -+ -+int mtk_nand_header_info(const void *ptr, struct nand_header_info *info) -+{ -+ if (!strcmp((char *)ptr, NAND_BOOT_NAME)) -+ return mtk_nand_header_ap_info(ptr, info); -+ -+ return -1; -+} -+ -+bool is_mtk_nand_header(const void *ptr) -+{ -+ struct nand_header_info info; -+ -+ if (mtk_nand_header_info(ptr, &info) >= 0) -+ return true; -+ -+ return false; -+} -+ -+uint32_t mtk_nand_header_put(const union nand_boot_header *hdr_nand, void *ptr) -+{ -+ union nand_boot_header *nh = (union nand_boot_header *)ptr; -+ int i; -+ -+ /* NAND device header, repeat 4 times */ -+ for (i = 0; i < 4; i++) -+ memcpy(nh + i, hdr_nand, sizeof(union nand_boot_header)); -+ -+ return le16_to_cpu(hdr_nand->pagesize); -+} ---- /dev/null -+++ b/tools/mtk_nand_headers.h -@@ -0,0 +1,61 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * MediaTek BootROM NAND header definitions -+ * -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Weijie Gao -+ */ -+ -+#ifndef _MTK_NAND_HEADERS_H -+#define _MTK_NAND_HEADERS_H -+ -+#include -+#include -+ -+struct nand_header_info { -+ uint32_t page_size; -+ uint32_t spare_size; -+ uint32_t gfh_offset; -+}; -+ -+/* AP BROM Header for NAND */ -+union nand_boot_header { -+ struct { -+ char name[12]; -+ char version[4]; -+ char id[8]; -+ uint16_t ioif; /* I/O interface */ -+ uint16_t pagesize; /* NAND page size */ -+ uint16_t addrcycles; /* Address cycles */ -+ uint16_t oobsize; /* NAND page spare size */ -+ uint16_t pages_of_block; /* Pages of one block */ -+ uint16_t numblocks; /* Total blocks of NAND chip */ -+ uint16_t writesize_shift; -+ uint16_t erasesize_shift; -+ uint8_t dummy[60]; -+ uint8_t ecc_parity[28]; /* ECC parity of this header */ -+ }; -+ -+ uint8_t data[0x80]; -+}; -+ -+#define NAND_BOOT_NAME "BOOTLOADER!" -+#define NAND_BOOT_VERSION "V006" -+#define NAND_BOOT_ID "NFIINFO" -+ -+/* Find nand header data by name */ -+const union nand_boot_header *mtk_nand_header_find(const char *name); -+ -+/* Device header size using this nand header */ -+uint32_t mtk_nand_header_size(const union nand_boot_header *hdr_nand); -+ -+/* Get nand info from nand header (page size, spare size, ...) */ -+int mtk_nand_header_info(const void *ptr, struct nand_header_info *info); -+ -+/* Whether given header data is valid */ -+bool is_mtk_nand_header(const void *ptr); -+ -+/* Generate Device header using give nand header */ -+uint32_t mtk_nand_header_put(const union nand_boot_header *hdr_nand, void *ptr); -+ -+#endif /* _MTK_NAND_HEADERS_H */ diff --git a/tools/mkimage/patches/022-tools-mtk_image-add-support-for-nand-headers-used-by.patch b/tools/mkimage/patches/022-tools-mtk_image-add-support-for-nand-headers-used-by.patch deleted file mode 100644 index 0ce095998f4..00000000000 --- a/tools/mkimage/patches/022-tools-mtk_image-add-support-for-nand-headers-used-by.patch +++ /dev/null @@ -1,702 +0,0 @@ -From fbf296f9ed5daab70020686e9ba072efe663bbab Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 3 Aug 2022 11:14:36 +0800 -Subject: [PATCH 30/31] tools: mtk_image: add support for nand headers used by - newer chips - -This patch adds more nand headers in two new types: -1. HSM header, used for spi-nand thru SNFI interface -2. SPIM header, used for spi-nand thru spi-mem interface - -The original nand header is renamed to AP header. - -Signed-off-by: Weijie Gao ---- - tools/mtk_image.c | 23 ++- - tools/mtk_nand_headers.c | 422 +++++++++++++++++++++++++++++++++++++-- - tools/mtk_nand_headers.h | 110 +++++++++- - 3 files changed, 525 insertions(+), 30 deletions(-) - ---- a/tools/mtk_image.c -+++ b/tools/mtk_image.c -@@ -33,6 +33,9 @@ static const struct brom_img_type { - }, { - .name = "snand", - .type = BRLYT_TYPE_SNAND -+ }, { -+ .name = "spim-nand", -+ .type = BRLYT_TYPE_SNAND - } - }; - -@@ -54,7 +57,7 @@ static char lk_name[32] = "U-Boot"; - static uint32_t crc32tbl[256]; - - /* NAND header selected by user */ --static const union nand_boot_header *hdr_nand; -+static const struct nand_header_type *hdr_nand; - static uint32_t hdr_nand_size; - - /* GFH header + 2 * 4KB pages of NAND */ -@@ -366,20 +369,26 @@ static int mtk_image_verify_nand_header( - if (ret < 0) - return ret; - -- bh = (struct brom_layout_header *)(ptr + info.page_size); -+ if (!ret) { -+ bh = (struct brom_layout_header *)(ptr + info.page_size); - -- if (strcmp(bh->name, BRLYT_NAME)) -- return -1; -+ if (strcmp(bh->name, BRLYT_NAME)) -+ return -1; -+ -+ if (le32_to_cpu(bh->magic) != BRLYT_MAGIC) -+ return -1; - -- if (le32_to_cpu(bh->magic) != BRLYT_MAGIC) { -- return -1; -- } else { - if (le32_to_cpu(bh->type) == BRLYT_TYPE_NAND) - bootmedia = "Parallel NAND"; - else if (le32_to_cpu(bh->type) == BRLYT_TYPE_SNAND) - bootmedia = "Serial NAND (SNFI/AP)"; - else - return -1; -+ } else { -+ if (info.snfi) -+ bootmedia = "Serial NAND (SNFI/HSM)"; -+ else -+ bootmedia = "Serial NAND (SPIM)"; - } - - if (print) { ---- a/tools/mtk_nand_headers.c -+++ b/tools/mtk_nand_headers.c -@@ -188,55 +188,346 @@ static const union nand_boot_header nand - } - }; - --static const struct nand_header_type { -+/* HSM BROM NAND header for SPI NAND with 2KB page + 64B spare */ -+static const union hsm_nand_boot_header hsm_nand_hdr_2k_64_data = { -+ .data = { -+ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x08, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, -+ 0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, -+ 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, -+ 0xFF, 0x00, 0x00, 0x00, 0x21, 0xD2, 0xEE, 0xF6, -+ 0xAE, 0xDD, 0x5E, 0xC2, 0x82, 0x8E, 0x9A, 0x62, -+ 0x09, 0x8E, 0x80, 0xE2, 0x37, 0x0D, 0xC9, 0xFA, -+ 0xA9, 0xDD, 0xFC, 0x92, 0x34, 0x2A, 0xED, 0x51, -+ 0xA4, 0x1B, 0xF7, 0x63, 0xCC, 0x5A, 0xC7, 0xFB, -+ 0xED, 0x21, 0x02, 0x23, 0x51, 0x31 -+ } -+}; -+ -+/* HSM BROM NAND header for SPI NAND with 2KB page + 128B spare */ -+static const union hsm_nand_boot_header hsm_nand_hdr_2k_128_data = { -+ .data = { -+ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x08, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, -+ 0x40, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, -+ 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, -+ 0xFF, 0x00, 0x00, 0x00, 0x71, 0x7f, 0x71, 0xAC, -+ 0x42, 0xD0, 0x5B, 0xD2, 0x12, 0x81, 0x15, 0x0A, -+ 0x0C, 0xD4, 0xF6, 0x32, 0x1E, 0x63, 0xE7, 0x81, -+ 0x8A, 0x7F, 0xDE, 0xF9, 0x4B, 0x91, 0xEC, 0xC2, -+ 0x70, 0x00, 0x7F, 0x57, 0xAF, 0xDC, 0xE4, 0x24, -+ 0x57, 0x09, 0xBC, 0xC5, 0x35, 0xDC -+ } -+}; -+ -+/* HSM BROM NAND header for SPI NAND with 4KB page + 256B spare */ -+static const union hsm_nand_boot_header hsm_nand_hdr_4k_256_data = { -+ .data = { -+ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, -+ 0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, -+ 0x0C, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, -+ 0xFF, 0x00, 0x00, 0x00, 0x62, 0x04, 0xD6, 0x1F, -+ 0x2B, 0x57, 0x7A, 0x2D, 0xFE, 0xBB, 0x4A, 0x50, -+ 0xEC, 0xF8, 0x70, 0x1A, 0x44, 0x15, 0xF6, 0xA2, -+ 0x8E, 0xB0, 0xFD, 0xFA, 0xDC, 0xAA, 0x5A, 0x4E, -+ 0xCB, 0x8E, 0xC9, 0x72, 0x08, 0xDC, 0x20, 0xB9, -+ 0x98, 0xC8, 0x82, 0xD8, 0xBE, 0x44 -+ } -+}; -+ -+/* HSM2.0 BROM NAND header for SPI NAND with 2KB page + 64B spare */ -+static const union hsm20_nand_boot_header hsm20_nand_hdr_2k_64_data = { -+ .data = { -+ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, -+ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x08, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, -+ 0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, -+ 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0x01, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x5F, 0x4B, 0xB2, 0x5B, 0x8B, 0x1C, 0x35, 0xDA, -+ 0x83, 0xE6, 0x6C, 0xC3, 0xFB, 0x8C, 0x78, 0x23, -+ 0xD0, 0x89, 0x24, 0xD9, 0x6C, 0x35, 0x2C, 0x5D, -+ 0x8F, 0xBB, 0xFC, 0x10, 0xD0, 0xE2, 0x22, 0x7D, -+ 0xC8, 0x97, 0x9A, 0xEF, 0xC6, 0xB5, 0xA7, 0x4E, -+ 0x4E, 0x0E -+ } -+}; -+ -+/* HSM2.0 BROM NAND header for SPI NAND with 2KB page + 128B spare */ -+static const union hsm20_nand_boot_header hsm20_nand_hdr_2k_128_data = { -+ .data = { -+ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, -+ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x08, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, -+ 0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, -+ 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0x01, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0xF8, 0x7E, 0xC1, 0x5D, 0x61, 0x54, 0xEA, 0x9F, -+ 0x5E, 0x66, 0x39, 0x66, 0x21, 0xFF, 0x8C, 0x3B, -+ 0xBE, 0xA7, 0x5A, 0x9E, 0xD7, 0xBD, 0x9E, 0x89, -+ 0xEE, 0x7E, 0x10, 0x31, 0x9A, 0x1D, 0x82, 0x49, -+ 0xA3, 0x4E, 0xD8, 0x47, 0xD7, 0x19, 0xF4, 0x2D, -+ 0x8E, 0x53 -+ } -+}; -+ -+/* HSM2.0 BROM NAND header for SPI NAND with 4KB page + 256B spare */ -+static const union hsm20_nand_boot_header hsm20_nand_hdr_4k_256_data = { -+ .data = { -+ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, -+ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, -+ 0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, -+ 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0x01, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x79, 0x01, 0x1F, 0x86, 0x62, 0x6A, 0x43, 0xAE, -+ 0xE6, 0xF8, 0xDD, 0x5B, 0x29, 0xB7, 0xA2, 0x7F, -+ 0x29, 0x72, 0x54, 0x37, 0xBE, 0x50, 0xD4, 0x24, -+ 0xAB, 0x60, 0xF4, 0x44, 0x97, 0x3B, 0x65, 0x21, -+ 0x73, 0x24, 0x1F, 0x93, 0x0E, 0x9E, 0x96, 0x88, -+ 0x78, 0x6C -+ } -+}; -+ -+/* SPIM-NAND header for SPI NAND with 2KB page + 64B spare */ -+static const union spim_nand_boot_header spim_nand_hdr_2k_64_data = { -+ .data = { -+ 0x53, 0x50, 0x49, 0x4e, 0x41, 0x4e, 0x44, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, -+ 0x00, 0x08, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, -+ 0x40, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x20, 0x30, -+ 0x01, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -+ } -+}; -+ -+/* SPIM-NAND header for SPI NAND with 2KB page + 128B spare */ -+static const union spim_nand_boot_header spim_nand_hdr_2k_128_data = { -+ .data = { -+ 0x53, 0x50, 0x49, 0x4e, 0x41, 0x4e, 0x44, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, -+ 0x00, 0x08, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, -+ 0x40, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x20, 0x30, -+ 0x01, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -+ } -+}; -+ -+/* SPIM-NAND header for SPI NAND with 4KB page + 256B spare */ -+static const union spim_nand_boot_header spim_nand_hdr_4k_256_data = { -+ .data = { -+ 0x53, 0x50, 0x49, 0x4e, 0x41, 0x4e, 0x44, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, -+ 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, -+ 0x40, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x20, 0x30, -+ 0x01, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -+ } -+}; -+ -+struct nand_header_type { - const char *name; -- const union nand_boot_header *data; -+ enum nand_boot_header_type type; -+ union { -+ const union nand_boot_header *ap; -+ const union hsm_nand_boot_header *hsm; -+ const union hsm20_nand_boot_header *hsm20; -+ const union spim_nand_boot_header *spim; -+ }; - } nand_headers[] = { - { - .name = "2k+64", -- .data = &snand_hdr_2k_64_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &snand_hdr_2k_64_data, - }, { - .name = "2k+120", -- .data = &snand_hdr_2k_128_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &snand_hdr_2k_128_data, - }, { - .name = "2k+128", -- .data = &snand_hdr_2k_128_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &snand_hdr_2k_128_data, - }, { - .name = "4k+256", -- .data = &snand_hdr_4k_256_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &snand_hdr_4k_256_data, - }, { - .name = "1g:2k+64", -- .data = &nand_hdr_1gb_2k_64_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &nand_hdr_1gb_2k_64_data, - }, { - .name = "2g:2k+64", -- .data = &nand_hdr_2gb_2k_64_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &nand_hdr_2gb_2k_64_data, - }, { - .name = "4g:2k+64", -- .data = &nand_hdr_4gb_2k_64_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &nand_hdr_4gb_2k_64_data, - }, { - .name = "2g:2k+128", -- .data = &nand_hdr_2gb_2k_128_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &nand_hdr_2gb_2k_128_data, - }, { - .name = "4g:2k+128", -- .data = &nand_hdr_4gb_2k_128_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &nand_hdr_4gb_2k_128_data, -+ }, { -+ .name = "hsm:2k+64", -+ .type = NAND_BOOT_HSM_HEADER, -+ .hsm = &hsm_nand_hdr_2k_64_data, -+ }, { -+ .name = "hsm:2k+128", -+ .type = NAND_BOOT_HSM_HEADER, -+ .hsm = &hsm_nand_hdr_2k_128_data, -+ }, { -+ .name = "hsm:4k+256", -+ .type = NAND_BOOT_HSM_HEADER, -+ .hsm = &hsm_nand_hdr_4k_256_data, -+ }, { -+ .name = "hsm20:2k+64", -+ .type = NAND_BOOT_HSM20_HEADER, -+ .hsm20 = &hsm20_nand_hdr_2k_64_data, -+ }, { -+ .name = "hsm20:2k+128", -+ .type = NAND_BOOT_HSM20_HEADER, -+ .hsm20 = &hsm20_nand_hdr_2k_128_data, -+ }, { -+ .name = "hsm20:4k+256", -+ .type = NAND_BOOT_HSM20_HEADER, -+ .hsm20 = &hsm20_nand_hdr_4k_256_data, -+ }, { -+ .name = "spim:2k+64", -+ .type = NAND_BOOT_SPIM_HEADER, -+ .spim = &spim_nand_hdr_2k_64_data, -+ }, { -+ .name = "spim:2k+128", -+ .type = NAND_BOOT_SPIM_HEADER, -+ .spim = &spim_nand_hdr_2k_128_data, -+ }, { -+ .name = "spim:4k+256", -+ .type = NAND_BOOT_SPIM_HEADER, -+ .spim = &spim_nand_hdr_4k_256_data, - } - }; - --const union nand_boot_header *mtk_nand_header_find(const char *name) -+const struct nand_header_type *mtk_nand_header_find(const char *name) - { - uint32_t i; - - for (i = 0; i < ARRAY_SIZE(nand_headers); i++) { - if (!strcmp(nand_headers[i].name, name)) -- return nand_headers[i].data; -+ return &nand_headers[i]; - } - - return NULL; - } - --uint32_t mtk_nand_header_size(const union nand_boot_header *hdr_nand) -+uint32_t mtk_nand_header_size(const struct nand_header_type *hdr_nand) - { -- return 2 * le16_to_cpu(hdr_nand->pagesize); -+ switch (hdr_nand->type) { -+ case NAND_BOOT_HSM_HEADER: -+ return le32_to_cpu(hdr_nand->hsm->page_size); -+ -+ case NAND_BOOT_HSM20_HEADER: -+ return le32_to_cpu(hdr_nand->hsm20->page_size); -+ -+ case NAND_BOOT_SPIM_HEADER: -+ return le32_to_cpu(hdr_nand->spim->page_size); -+ -+ default: -+ return 2 * le16_to_cpu(hdr_nand->ap->pagesize); -+ } - } - - static int mtk_nand_header_ap_info(const void *ptr, -@@ -251,14 +542,45 @@ static int mtk_nand_header_ap_info(const - info->page_size = le16_to_cpu(nh->pagesize); - info->spare_size = le16_to_cpu(nh->oobsize); - info->gfh_offset = 2 * info->page_size; -+ info->snfi = true; - - return 0; - } - -+static int mtk_nand_header_hsm_info(const void *ptr, -+ struct nand_header_info *info) -+{ -+ union hsm_nand_boot_header *nh = (union hsm_nand_boot_header *)ptr; -+ -+ info->page_size = le16_to_cpu(nh->page_size); -+ info->spare_size = le16_to_cpu(nh->spare_size); -+ info->gfh_offset = info->page_size; -+ info->snfi = true; -+ -+ return 1; -+} -+ -+static int mtk_nand_header_spim_info(const void *ptr, -+ struct nand_header_info *info) -+{ -+ union spim_nand_boot_header *nh = (union spim_nand_boot_header *)ptr; -+ -+ info->page_size = le16_to_cpu(nh->page_size); -+ info->spare_size = le16_to_cpu(nh->spare_size); -+ info->gfh_offset = info->page_size; -+ info->snfi = false; -+ -+ return 1; -+} -+ - int mtk_nand_header_info(const void *ptr, struct nand_header_info *info) - { - if (!strcmp((char *)ptr, NAND_BOOT_NAME)) - return mtk_nand_header_ap_info(ptr, info); -+ else if (!strncmp((char *)ptr, HSM_NAND_BOOT_NAME, 8)) -+ return mtk_nand_header_hsm_info(ptr, info); -+ else if (!strncmp((char *)ptr, SPIM_NAND_BOOT_NAME, 8)) -+ return mtk_nand_header_spim_info(ptr, info); - - return -1; - } -@@ -273,14 +595,74 @@ bool is_mtk_nand_header(const void *ptr) - return false; - } - --uint32_t mtk_nand_header_put(const union nand_boot_header *hdr_nand, void *ptr) -+static uint16_t crc16(const uint8_t *p, uint32_t len) -+{ -+ uint16_t crc = 0x4f4e; -+ uint32_t i; -+ -+ while (len--) { -+ crc ^= *p++ << 8; -+ for (i = 0; i < 8; i++) -+ crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0); -+ } -+ -+ return crc; -+} -+ -+static uint32_t mtk_nand_header_put_ap(const struct nand_header_type *hdr_nand, -+ void *ptr) - { -- union nand_boot_header *nh = (union nand_boot_header *)ptr; - int i; - - /* NAND device header, repeat 4 times */ -- for (i = 0; i < 4; i++) -- memcpy(nh + i, hdr_nand, sizeof(union nand_boot_header)); -+ for (i = 0; i < 4; i++) { -+ memcpy(ptr, hdr_nand->ap, sizeof(*hdr_nand->ap)); -+ ptr += sizeof(*hdr_nand->ap); -+ } -+ -+ return le16_to_cpu(hdr_nand->ap->pagesize); -+} - -- return le16_to_cpu(hdr_nand->pagesize); -+static uint32_t mtk_nand_header_put_hsm(const struct nand_header_type *hdr_nand, -+ void *ptr) -+{ -+ memcpy(ptr, hdr_nand->hsm, sizeof(*hdr_nand->hsm)); -+ return 0; -+} -+ -+static uint32_t mtk_nand_header_put_hsm20(const struct nand_header_type *hdr_nand, -+ void *ptr) -+{ -+ memcpy(ptr, hdr_nand->hsm20, sizeof(*hdr_nand->hsm20)); -+ return 0; -+} -+ -+static uint32_t mtk_nand_header_put_spim(const struct nand_header_type *hdr_nand, -+ void *ptr) -+{ -+ uint16_t crc; -+ -+ memcpy(ptr, hdr_nand->spim, sizeof(*hdr_nand->spim)); -+ -+ crc = crc16(ptr, 0x4e); -+ memcpy(ptr + 0x4e, &crc, sizeof(uint16_t)); -+ -+ return 0; -+} -+ -+uint32_t mtk_nand_header_put(const struct nand_header_type *hdr_nand, void *ptr) -+{ -+ switch (hdr_nand->type) { -+ case NAND_BOOT_HSM_HEADER: -+ return mtk_nand_header_put_hsm(hdr_nand, ptr); -+ -+ case NAND_BOOT_HSM20_HEADER: -+ return mtk_nand_header_put_hsm20(hdr_nand, ptr); -+ -+ case NAND_BOOT_SPIM_HEADER: -+ return mtk_nand_header_put_spim(hdr_nand, ptr); -+ -+ default: -+ return mtk_nand_header_put_ap(hdr_nand, ptr); -+ } - } ---- a/tools/mtk_nand_headers.h -+++ b/tools/mtk_nand_headers.h -@@ -16,6 +16,7 @@ struct nand_header_info { - uint32_t page_size; - uint32_t spare_size; - uint32_t gfh_offset; -+ bool snfi; - }; - - /* AP BROM Header for NAND */ -@@ -39,15 +40,117 @@ union nand_boot_header { - uint8_t data[0x80]; - }; - -+/* HSM BROM Header for NAND */ -+union hsm_nand_boot_header { -+ struct { -+ char id[8]; -+ uint32_t version; /* Header version */ -+ uint32_t config; /* Header config */ -+ uint32_t sector_size; /* ECC step size */ -+ uint32_t fdm_size; /* User OOB size of a step */ -+ uint32_t fdm_ecc_size; /* ECC parity size of a step */ -+ uint32_t lbs; -+ uint32_t page_size; /* NAND page size */ -+ uint32_t spare_size; /* NAND page spare size */ -+ uint32_t page_per_block; /* Pages of one block */ -+ uint32_t blocks; /* Total blocks of NAND chip */ -+ uint32_t plane_sel_position; /* Plane bit position */ -+ uint32_t pll; /* Value of pll reg */ -+ uint32_t acccon; /* Value of access timing reg */ -+ uint32_t strobe_sel; /* Value of DQS selection reg*/ -+ uint32_t acccon1; /* Value of access timing reg */ -+ uint32_t dqs_mux; /* Value of DQS mux reg */ -+ uint32_t dqs_ctrl; /* Value of DQS control reg */ -+ uint32_t delay_ctrl; /* Value of delay ctrl reg */ -+ uint32_t latch_lat; /* Value of latch latency reg */ -+ uint32_t sample_delay; /* Value of sample delay reg */ -+ uint32_t driving; /* Value of driving reg */ -+ uint32_t bl_start; /* Bootloader start addr */ -+ uint32_t bl_end; /* Bootloader end addr */ -+ uint8_t ecc_parity[42]; /* ECC parity of this header */ -+ }; -+ -+ uint8_t data[0x8E]; -+}; -+ -+/* HSM2.0 BROM Header for NAND */ -+union hsm20_nand_boot_header { -+ struct { -+ char id[8]; -+ uint32_t version; /* Header version */ -+ uint32_t config; /* Header config */ -+ uint32_t sector_size; /* ECC step size */ -+ uint32_t fdm_size; /* User OOB size of a step */ -+ uint32_t fdm_ecc_size; /* ECC parity size of a step */ -+ uint32_t lbs; -+ uint32_t page_size; /* NAND page size */ -+ uint32_t spare_size; /* NAND page spare size */ -+ uint32_t page_per_block; /* Pages of one block */ -+ uint32_t blocks; /* Total blocks of NAND chip */ -+ uint32_t plane_sel_position; /* Plane bit position */ -+ uint32_t pll; /* Value of pll reg */ -+ uint32_t acccon; /* Value of access timing reg */ -+ uint32_t strobe_sel; /* Value of DQS selection reg*/ -+ uint32_t acccon1; /* Value of access timing reg */ -+ uint32_t dqs_mux; /* Value of DQS mux reg */ -+ uint32_t dqs_ctrl; /* Value of DQS control reg */ -+ uint32_t delay_ctrl; /* Value of delay ctrl reg */ -+ uint32_t latch_lat; /* Value of latch latency reg */ -+ uint32_t sample_delay; /* Value of sample delay reg */ -+ uint32_t driving; /* Value of driving reg */ -+ uint32_t reserved; -+ uint32_t bl0_start; /* Bootloader start addr */ -+ uint32_t bl0_end; /* Bootloader end addr */ -+ uint32_t bl0_type; /* Bootloader type */ -+ uint8_t bl_reserve[84]; -+ uint8_t ecc_parity[42]; /* ECC parity of this header */ -+ }; -+ -+ uint8_t data[0xEA]; -+}; -+ -+/* SPIM BROM Header for SPI-NAND */ -+union spim_nand_boot_header { -+ struct { -+ char id[8]; -+ uint32_t version; /* Header version */ -+ uint32_t config; /* Header config */ -+ uint32_t page_size; /* NAND page size */ -+ uint32_t spare_size; /* NAND page spare size */ -+ uint16_t page_per_block; /* Pages of one block */ -+ uint16_t plane_sel_position; /* Plane bit position */ -+ uint16_t reserve_reg; -+ uint16_t reserve_val; -+ uint16_t ecc_error; /* ECC error reg addr */ -+ uint16_t ecc_mask; /* ECC error bit mask */ -+ uint32_t bl_start; /* Bootloader start addr */ -+ uint32_t bl_end; /* Bootloader end addr */ -+ uint8_t ecc_parity[32]; /* ECC parity of this header */ -+ uint32_t integrity_crc; /* CRC of this header */ -+ }; -+ -+ uint8_t data[0x50]; -+}; -+ -+enum nand_boot_header_type { -+ NAND_BOOT_AP_HEADER, -+ NAND_BOOT_HSM_HEADER, -+ NAND_BOOT_HSM20_HEADER, -+ NAND_BOOT_SPIM_HEADER -+}; -+ - #define NAND_BOOT_NAME "BOOTLOADER!" - #define NAND_BOOT_VERSION "V006" - #define NAND_BOOT_ID "NFIINFO" - -+#define HSM_NAND_BOOT_NAME "NANDCFG!" -+#define SPIM_NAND_BOOT_NAME "SPINAND!" -+ - /* Find nand header data by name */ --const union nand_boot_header *mtk_nand_header_find(const char *name); -+const struct nand_header_type *mtk_nand_header_find(const char *name); - - /* Device header size using this nand header */ --uint32_t mtk_nand_header_size(const union nand_boot_header *hdr_nand); -+uint32_t mtk_nand_header_size(const struct nand_header_type *hdr_nand); - - /* Get nand info from nand header (page size, spare size, ...) */ - int mtk_nand_header_info(const void *ptr, struct nand_header_info *info); -@@ -56,6 +159,7 @@ int mtk_nand_header_info(const void *ptr - bool is_mtk_nand_header(const void *ptr); - - /* Generate Device header using give nand header */ --uint32_t mtk_nand_header_put(const union nand_boot_header *hdr_nand, void *ptr); -+uint32_t mtk_nand_header_put(const struct nand_header_type *hdr_nand, -+ void *ptr); - - #endif /* _MTK_NAND_HEADERS_H */ diff --git a/tools/mkimage/patches/030-allow-to-use-different-magic.patch b/tools/mkimage/patches/030-allow-to-use-different-magic.patch index 591edf24eaf..d88f1cf9496 100644 --- a/tools/mkimage/patches/030-allow-to-use-different-magic.patch +++ b/tools/mkimage/patches/030-allow-to-use-different-magic.patch @@ -52,14 +52,14 @@ This patch makes it possible to set a custom image magic. +++ b/tools/default_image.c @@ -56,7 +56,7 @@ static int image_verify_header(unsigned */ - memcpy(hdr, ptr, sizeof(image_header_t)); + memcpy(hdr, ptr, sizeof(struct legacy_img_hdr)); - if (be32_to_cpu(hdr->ih_magic) != IH_MAGIC) { + if (be32_to_cpu(hdr->ih_magic) != params->magic) { debug("%s: Bad Magic Number: \"%s\" is no valid image\n", params->cmdname, params->imagefile); return -FDT_ERR_BADMAGIC; -@@ -120,7 +120,7 @@ static void image_set_header(void *ptr, +@@ -119,7 +119,7 @@ static void image_set_header(void *ptr, } /* Build new header */ From 5b605f4b51b9049a1a610a10abb6c5726b469338 Mon Sep 17 00:00:00 2001 From: Linhui Liu Date: Thu, 12 Jan 2023 23:03:58 +0800 Subject: [PATCH 50/51] uboot-envtools: update to 2023.01 Update to latest version. Signed-off-by: Linhui Liu --- package/boot/uboot-envtools/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/boot/uboot-envtools/Makefile b/package/boot/uboot-envtools/Makefile index 5c4d5850214..9ed39cbf551 100644 --- a/package/boot/uboot-envtools/Makefile +++ b/package/boot/uboot-envtools/Makefile @@ -9,15 +9,15 @@ include $(TOPDIR)/rules.mk PKG_NAME:=uboot-envtools PKG_DISTNAME:=u-boot -PKG_VERSION:=2022.10 -PKG_RELEASE:=$(AUTORELEASE) +PKG_VERSION:=2023.01 +PKG_RELEASE:=1 PKG_SOURCE:=$(PKG_DISTNAME)-$(PKG_VERSION).tar.bz2 PKG_SOURCE_URL:= \ https://ftp.denx.de/pub/u-boot \ https://mirror.cyberbits.eu/u-boot \ ftp://ftp.denx.de/pub/u-boot -PKG_HASH:=50b4482a505bc281ba8470c399a3c26e145e29b23500bc35c50debd7fa46bdf8 +PKG_HASH:=69423bad380f89a0916636e89e6dcbd2e4512d584308d922d1039d1e4331950f PKG_SOURCE_SUBDIR:=$(PKG_DISTNAME)-$(PKG_VERSION) PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_DISTNAME)-$(PKG_VERSION) From 3d5c5427e17a870041e0c94b6fbbfb9301cd2c70 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Fri, 13 Jan 2023 03:13:24 +0000 Subject: [PATCH 51/51] uboot-mediatek: update to U-Boot 2023.01 Support for MT7981 and MT7986 has been merged, remove patches. Tested on a couple of MT7986, MT7622 and MT7623 boards. MIPS builds are untested. Signed-off-by: Daniel Golle --- package/boot/uboot-mediatek/Makefile | 6 +- ...22-enable-environment-for-mt7622_rfb.patch | 4 +- ...-add-support-for-MediaTek-MT7986-SoC.patch | 552 -------- ...-add-support-for-MediaTek-MT7981-SoC.patch | 462 ------- ...mediatek-add-MT7986-reference-boards.patch | 1148 ----------------- ...mediatek-add-MT7981-reference-boards.patch | 779 ----------- ...-support-for-MediaTek-MT7891-MT7986-.patch | 132 -- ...-a-struct-to-cover-variations-of-all.patch | 163 --- ...p-using-bitfileds-for-DMA-descriptor.patch | 317 ----- ...net-mediatek-add-support-for-PDMA-v2.patch | 298 ----- ...d-support-for-MediaTek-MT7981-MT7986.patch | 100 -- ...upport-for-using-dynamic-baud-clock-.patch | 202 --- ...t7622-force-high-speed-mode-for-uart.patch | 26 - ...-add-support-for-MediaTek-MT7986-SoC.patch | 32 - ...-add-support-for-MediaTek-MT7981-SoC.patch | 99 -- ...pport-for-MediaTek-MT7981-MT7986-SoC.patch | 119 -- ...k-add-support-for-MediaTek-MT7986-So.patch | 23 - ...port-for-MediaTek-spi-mem-controller.patch | 748 ----------- ...d-support-for-MediaTek-I2C-interface.patch | 870 ------------- ...-0018-arm-dts-mt7622-add-i2c-support.patch | 76 -- ...trl-mediatek-add-a-header-for-common.patch | 60 - ...ek-add-pinctrl-driver-for-MT7981-SoC.patch | 1091 ---------------- ...ek-add-pinctrl-driver-for-MT7986-SoC.patch | 817 ------------ ...-CLK_BYPASS_XTAL-flag-to-allow-bypas.patch | 63 - ...-support-to-configure-clock-driver-p.patch | 198 --- ...iatek-add-infrasys-clock-mux-support.patch | 135 -- ...dd-CLK_XTAL-support-for-clock-driver.patch | 46 - ...-clock-driver-support-for-MediaTek-M.patch | 956 -------------- ...-clock-driver-support-for-MediaTek-M.patch | 985 -------------- ...ic-cpu-driver-for-MediaTek-ARM-chips.patch | 133 -- ...split-gfh-header-verification-into-a.patch | 89 -- ...split-the-code-of-generating-NAND-he.patch | 821 ------------ ...add-support-for-nand-headers-used-by.patch | 702 ---------- ...te-maintainer-for-MediaTek-ARM-platf.patch | 43 - .../patches/051-mt7986-enable-pstore.patch | 2 +- ...atek-add-more-network-configurations.patch | 10 +- ...support-for-MediaTek-SPI-NAND-flash-.patch | 6 +- ...03-mtd-mtk-snand-add-support-for-SPL.patch | 2 +- ...v-add-support-for-generic-MTD-device.patch | 4 +- ...6-mtd-add-core-facility-code-of-NMBM.patch | 34 +- .../100-07-mtd-nmbm-add-support-for-mtd.patch | 4 +- ...dd-support-to-initialize-NMBM-after-.patch | 4 +- .../patches/100-09-cmd-add-nmbm-command.patch | 4 +- ...-markbad-subcommand-for-NMBM-testing.patch | 6 +- ...add-support-for-NMBM-upper-MTD-layer.patch | 2 +- ...new-command-for-NAND-flash-debugging.patch | 4 +- ...-add-support-to-read-flash-unique-ID.patch | 8 +- ...-add-support-to-read-flash-unique-ID.patch | 6 +- ...d-ability-to-select-item-by-shortkey.patch | 22 +- ...board-mt7622-use-new-spi-nand-driver.patch | 4 +- ...-reference-board-using-new-spi-nand-.patch | 2 +- ...00-21-mtd-spi-nor-add-more-flash-ids.patch | 6 +- ...support-to-display-verbose-error-log.patch | 2 +- ...olume-find-create-remove-APIs-public.patch | 6 +- ...creating-volume-with-all-free-spaces.patch | 2 +- ...ort-to-create-environment-volume-if-.patch | 2 +- .../patches/120-use-xz-instead-of-lzma.patch | 2 +- .../patches/130-fix-mkimage-host-build.patch | 4 +- .../patches/200-cmd-add-imsz-and-imszb.patch | 11 +- .../211-cmd-bootmenu-custom-title.patch | 6 +- .../patches/220-cmd-env-readmem.patch | 2 +- ...-of-FIT-configuration-in-chosen-node.patch | 2 +- .../patches/300-force-pylibfdt-build.patch | 2 +- .../patches/400-update-bpir2-defconfig.patch | 4 +- .../patches/401-update-u7623-defconfig.patch | 4 +- .../404-add-bananapi_bpi-r64_defconfigs.patch | 9 +- .../patches/410-add-linksys-e8450.patch | 5 +- .../patches/412-add-ubnt-unifi-6-lr.patch | 11 +- .../patches/430-add-bpi-r3.patch | 14 +- .../patches/431-add-xiaomi_redmi-ax6000.patch | 3 +- 70 files changed, 118 insertions(+), 12398 deletions(-) delete mode 100644 package/boot/uboot-mediatek/patches/002-0001-arm-mediatek-add-support-for-MediaTek-MT7986-SoC.patch delete mode 100644 package/boot/uboot-mediatek/patches/002-0002-arm-mediatek-add-support-for-MediaTek-MT7981-SoC.patch delete mode 100644 package/boot/uboot-mediatek/patches/002-0003-board-mediatek-add-MT7986-reference-boards.patch delete mode 100644 package/boot/uboot-mediatek/patches/002-0004-board-mediatek-add-MT7981-reference-boards.patch delete mode 100644 package/boot/uboot-mediatek/patches/002-0005-mmc-mediatek-add-support-for-MediaTek-MT7891-MT7986-.patch delete mode 100644 package/boot/uboot-mediatek/patches/002-0006-net-mediatek-use-a-struct-to-cover-variations-of-all.patch delete mode 100644 package/boot/uboot-mediatek/patches/002-0007-net-mediatek-stop-using-bitfileds-for-DMA-descriptor.patch delete mode 100644 package/boot/uboot-mediatek/patches/002-0008-net-mediatek-add-support-for-PDMA-v2.patch delete mode 100644 package/boot/uboot-mediatek/patches/002-0009-net-mediatek-add-support-for-MediaTek-MT7981-MT7986.patch delete mode 100644 package/boot/uboot-mediatek/patches/002-0010-serial-mtk-add-support-for-using-dynamic-baud-clock-.patch delete mode 100644 package/boot/uboot-mediatek/patches/002-0011-arm-dts-mt7622-force-high-speed-mode-for-uart.patch delete mode 100644 package/boot/uboot-mediatek/patches/002-0012-pwm-mtk-add-support-for-MediaTek-MT7986-SoC.patch delete mode 100644 package/boot/uboot-mediatek/patches/002-0013-pwm-mtk-add-support-for-MediaTek-MT7981-SoC.patch delete mode 100644 package/boot/uboot-mediatek/patches/002-0014-timer-mtk-add-support-for-MediaTek-MT7981-MT7986-SoC.patch delete mode 100644 package/boot/uboot-mediatek/patches/002-0015-watchdog-mediatek-add-support-for-MediaTek-MT7986-So.patch delete mode 100644 package/boot/uboot-mediatek/patches/002-0016-spi-add-support-for-MediaTek-spi-mem-controller.patch delete mode 100644 package/boot/uboot-mediatek/patches/002-0017-i2c-add-support-for-MediaTek-I2C-interface.patch delete mode 100644 package/boot/uboot-mediatek/patches/002-0018-arm-dts-mt7622-add-i2c-support.patch delete mode 100644 package/boot/uboot-mediatek/patches/002-0019-dt-bindings-pinctrl-mediatek-add-a-header-for-common.patch delete mode 100644 package/boot/uboot-mediatek/patches/002-0020-pinctrl-mediatek-add-pinctrl-driver-for-MT7981-SoC.patch delete mode 100644 package/boot/uboot-mediatek/patches/002-0021-pinctrl-mediatek-add-pinctrl-driver-for-MT7986-SoC.patch delete mode 100644 package/boot/uboot-mediatek/patches/002-0022-clk-mediatek-add-CLK_BYPASS_XTAL-flag-to-allow-bypas.patch delete mode 100644 package/boot/uboot-mediatek/patches/002-0023-clk-mediatek-add-support-to-configure-clock-driver-p.patch delete mode 100644 package/boot/uboot-mediatek/patches/002-0024-clk-mediatek-add-infrasys-clock-mux-support.patch delete mode 100644 package/boot/uboot-mediatek/patches/002-0025-clk-mediatek-add-CLK_XTAL-support-for-clock-driver.patch delete mode 100644 package/boot/uboot-mediatek/patches/002-0026-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch delete mode 100644 package/boot/uboot-mediatek/patches/002-0027-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch delete mode 100644 package/boot/uboot-mediatek/patches/002-0028-cpu-add-basic-cpu-driver-for-MediaTek-ARM-chips.patch delete mode 100644 package/boot/uboot-mediatek/patches/002-0029-tools-mtk_image-split-gfh-header-verification-into-a.patch delete mode 100644 package/boot/uboot-mediatek/patches/002-0030-tools-mtk_image-split-the-code-of-generating-NAND-he.patch delete mode 100644 package/boot/uboot-mediatek/patches/002-0031-tools-mtk_image-add-support-for-nand-headers-used-by.patch delete mode 100644 package/boot/uboot-mediatek/patches/002-0032-MAINTAINERS-update-maintainer-for-MediaTek-ARM-platf.patch diff --git a/package/boot/uboot-mediatek/Makefile b/package/boot/uboot-mediatek/Makefile index 866f6fa51a6..7fbca24d0a5 100644 --- a/package/boot/uboot-mediatek/Makefile +++ b/package/boot/uboot-mediatek/Makefile @@ -1,9 +1,9 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk -PKG_VERSION:=2022.10 -PKG_HASH:=50b4482a505bc281ba8470c399a3c26e145e29b23500bc35c50debd7fa46bdf8 -PKG_BUILD_DEPENDS:=arm-trusted-firmware-tools/host +PKG_VERSION:=2023.01 +PKG_HASH:=69423bad380f89a0916636e89e6dcbd2e4512d584308d922d1039d1e4331950f +PKG_BUILD_DEPENDS:=!(TARGET_ramips||TARGET_mediatek_mt7623):arm-trusted-firmware-tools/host include $(INCLUDE_DIR)/u-boot.mk include $(INCLUDE_DIR)/package.mk diff --git a/package/boot/uboot-mediatek/patches/000-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch b/package/boot/uboot-mediatek/patches/000-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch index 077cac81b42..4e019ed6a97 100644 --- a/package/boot/uboot-mediatek/patches/000-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch +++ b/package/boot/uboot-mediatek/patches/000-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch @@ -12,7 +12,7 @@ Signed-off-by: Weijie Gao --- a/configs/mt7622_rfb_defconfig +++ b/configs/mt7622_rfb_defconfig -@@ -5,6 +5,8 @@ CONFIG_SYS_TEXT_BASE=0x41e00000 +@@ -6,6 +6,8 @@ CONFIG_TEXT_BASE=0x41e00000 CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=1 CONFIG_DEFAULT_DEVICE_TREE="mt7622-rfb" @@ -21,7 +21,7 @@ Signed-off-by: Weijie Gao CONFIG_SYS_PROMPT="MT7622> " CONFIG_DEBUG_UART_BASE=0x11002000 CONFIG_DEBUG_UART_CLOCK=25000000 -@@ -23,6 +25,9 @@ CONFIG_CMD_SF_TEST=y +@@ -24,6 +26,9 @@ CONFIG_CMD_SF_TEST=y CONFIG_CMD_PING=y CONFIG_CMD_SMC=y CONFIG_ENV_OVERWRITE=y diff --git a/package/boot/uboot-mediatek/patches/002-0001-arm-mediatek-add-support-for-MediaTek-MT7986-SoC.patch b/package/boot/uboot-mediatek/patches/002-0001-arm-mediatek-add-support-for-MediaTek-MT7986-SoC.patch deleted file mode 100644 index 07d7e4a6ae8..00000000000 --- a/package/boot/uboot-mediatek/patches/002-0001-arm-mediatek-add-support-for-MediaTek-MT7986-SoC.patch +++ /dev/null @@ -1,552 +0,0 @@ -From 13d81db4723241e33316d7d134e4d279116e3158 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 31 Aug 2022 19:00:17 +0800 -Subject: [PATCH 01/32] arm: mediatek: add support for MediaTek MT7986 SoC - -This patch adds basic support for MediaTek MT7986 SoC. -This include the file that will initialize the SoC after boot and its -device tree. - -Signed-off-by: Weijie Gao ---- - arch/arm/dts/mt7986-u-boot.dtsi | 33 ++ - arch/arm/dts/mt7986.dtsi | 346 ++++++++++++++++++ - arch/arm/mach-mediatek/Kconfig | 12 + - arch/arm/mach-mediatek/Makefile | 1 + - arch/arm/mach-mediatek/mt7986/Makefile | 4 + - arch/arm/mach-mediatek/mt7986/init.c | 45 +++ - arch/arm/mach-mediatek/mt7986/lowlevel_init.S | 32 ++ - 7 files changed, 473 insertions(+) - create mode 100644 arch/arm/dts/mt7986-u-boot.dtsi - create mode 100644 arch/arm/dts/mt7986.dtsi - create mode 100644 arch/arm/mach-mediatek/mt7986/Makefile - create mode 100644 arch/arm/mach-mediatek/mt7986/init.c - create mode 100644 arch/arm/mach-mediatek/mt7986/lowlevel_init.S - ---- /dev/null -+++ b/arch/arm/dts/mt7986-u-boot.dtsi -@@ -0,0 +1,33 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2022 MediaTek Inc. -+ * Author: Sam Shih -+ */ -+ -+&topckgen { -+ u-boot,dm-pre-reloc; -+}; -+ -+&pericfg { -+ u-boot,dm-pre-reloc; -+}; -+ -+&apmixedsys { -+ u-boot,dm-pre-reloc; -+}; -+ -+&timer0 { -+ u-boot,dm-pre-reloc; -+}; -+ -+&uart0 { -+ u-boot,dm-pre-reloc; -+}; -+ -+&snand { -+ u-boot,dm-pre-reloc; -+}; -+ -+&pinctrl { -+ u-boot,dm-pre-reloc; -+}; ---- /dev/null -+++ b/arch/arm/dts/mt7986.dtsi -@@ -0,0 +1,346 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2022 MediaTek Inc. -+ * Author: Sam Shih -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/ { -+ compatible = "mediatek,mt7986"; -+ interrupt-parent = <&gic>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ config { -+ u-boot,mmc-env-partition = "u-boot-env"; -+ }; -+ -+ cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ cpu0: cpu@0 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x0>; -+ }; -+ cpu1: cpu@1 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x1>; -+ }; -+ cpu2: cpu@2 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x1>; -+ }; -+ cpu3: cpu@3 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x1>; -+ }; -+ }; -+ -+ dummy_clk: dummy12m { -+ compatible = "fixed-clock"; -+ clock-frequency = <12000000>; -+ #clock-cells = <0>; -+ /* must need this line, or uart uanable to get dummy_clk */ -+ u-boot,dm-pre-reloc; -+ }; -+ -+ hwver: hwver { -+ compatible = "mediatek,hwver"; -+ reg = <0x8000000 0x1000>; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupt-parent = <&gic>; -+ clock-frequency = <13000000>; -+ interrupts = , -+ , -+ , -+ ; -+ arm,cpu-registers-not-fw-configured; -+ }; -+ -+ timer0: timer@10008000 { -+ compatible = "mediatek,mt7986-timer"; -+ reg = <0x10008000 0x1000>; -+ interrupts = ; -+ clocks = <&infracfg CK_INFRA_CK_F26M>; -+ clock-names = "gpt-clk"; -+ u-boot,dm-pre-reloc; -+ }; -+ -+ watchdog: watchdog@1001c000 { -+ compatible = "mediatek,mt7986-wdt"; -+ reg = <0x1001c000 0x1000>; -+ interrupts = ; -+ #reset-cells = <1>; -+ status = "disabled"; -+ }; -+ -+ gic: interrupt-controller@c000000 { -+ compatible = "arm,gic-v3"; -+ #interrupt-cells = <3>; -+ interrupt-parent = <&gic>; -+ interrupt-controller; -+ reg = <0x0c000000 0x40000>, /* GICD */ -+ <0x0c080000 0x200000>; /* GICR */ -+ -+ interrupts = ; -+ }; -+ -+ fixed_plls: apmixedsys@1001E000 { -+ compatible = "mediatek,mt7986-fixed-plls"; -+ reg = <0x1001E000 0x1000>; -+ #clock-cells = <1>; -+ }; -+ -+ topckgen: topckgen@1001B000 { -+ compatible = "mediatek,mt7986-topckgen"; -+ reg = <0x1001B000 0x1000>; -+ clock-parent = <&fixed_plls>; -+ #clock-cells = <1>; -+ }; -+ -+ infracfg_ao: infracfg_ao@10001000 { -+ compatible = "mediatek,mt7986-infracfg_ao"; -+ reg = <0x10001000 0x68>; -+ clock-parent = <&infracfg>; -+ #clock-cells = <1>; -+ }; -+ -+ infracfg: infracfg@10001040 { -+ compatible = "mediatek,mt7986-infracfg"; -+ reg = <0x10001000 0x1000>; -+ clock-parent = <&topckgen>; -+ #clock-cells = <1>; -+ }; -+ -+ pinctrl: pinctrl@1001f000 { -+ compatible = "mediatek,mt7986-pinctrl"; -+ reg = <0x1001f000 0x1000>, -+ <0x11c30000 0x1000>, -+ <0x11c40000 0x1000>, -+ <0x11e20000 0x1000>, -+ <0x11e30000 0x1000>, -+ <0x11f00000 0x1000>, -+ <0x11f10000 0x1000>, -+ <0x1000b000 0x1000>; -+ reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rb_base", -+ "iocfg_lt_base", "iocfg_lb_base", "iocfg_tr_base", -+ "iocfg_tl_base", "eint"; -+ gpio: gpio-controller { -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ }; -+ -+ pwm: pwm@10048000 { -+ compatible = "mediatek,mt7986-pwm"; -+ reg = <0x10048000 0x1000>; -+ #clock-cells = <1>; -+ #pwm-cells = <2>; -+ interrupts = ; -+ clocks = <&infracfg CK_INFRA_PWM>, -+ <&infracfg_ao CK_INFRA_PWM_BSEL>, -+ <&infracfg_ao CK_INFRA_PWM1_CK>, -+ <&infracfg_ao CK_INFRA_PWM2_CK>; -+ assigned-clocks = <&topckgen CK_TOP_PWM_SEL>, -+ <&infracfg CK_INFRA_PWM_BSEL>, -+ <&infracfg CK_INFRA_PWM1_SEL>, -+ <&infracfg CK_INFRA_PWM2_SEL>; -+ assigned-clock-parents = <&topckgen CK_TOP_CB_M_D4>, -+ <&infracfg CK_INFRA_PWM>, -+ <&infracfg CK_INFRA_PWM>, -+ <&infracfg CK_INFRA_PWM>; -+ clock-names = "top", "main", "pwm1", "pwm2"; -+ status = "disabled"; -+ u-boot,dm-pre-reloc; -+ }; -+ -+ uart0: serial@11002000 { -+ compatible = "mediatek,hsuart"; -+ reg = <0x11002000 0x400>; -+ interrupts = ; -+ clocks = <&infracfg_ao CK_INFRA_UART0_CK>; -+ assigned-clocks = <&topckgen CK_TOP_UART_SEL>, -+ <&infracfg_ao CK_INFRA_UART0_SEL>; -+ assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, -+ <&infracfg CK_INFRA_UART>; -+ mediatek,force-highspeed; -+ status = "disabled"; -+ u-boot,dm-pre-reloc; -+ }; -+ -+ uart1: serial@11003000 { -+ compatible = "mediatek,hsuart"; -+ reg = <0x11003000 0x400>; -+ interrupts = ; -+ clocks = <&infracfg_ao CK_INFRA_UART1_CK>; -+ assigned-clocks = <&infracfg CK_INFRA_UART1_SEL>; -+ assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>; -+ mediatek,force-highspeed; -+ status = "disabled"; -+ }; -+ -+ uart2: serial@11004000 { -+ compatible = "mediatek,hsuart"; -+ reg = <0x11004000 0x400>; -+ interrupts = ; -+ clocks = <&infracfg_ao CK_INFRA_UART2_CK>; -+ assigned-clocks = <&infracfg CK_INFRA_UART2_SEL>; -+ assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>; -+ mediatek,force-highspeed; -+ status = "disabled"; -+ }; -+ -+ snand: snand@11005000 { -+ compatible = "mediatek,mt7986-snand"; -+ reg = <0x11005000 0x1000>, -+ <0x11006000 0x1000>; -+ reg-names = "nfi", "ecc"; -+ clocks = <&infracfg_ao CK_INFRA_SPINFI1_CK>, -+ <&infracfg_ao CK_INFRA_NFI1_CK>, -+ <&infracfg_ao CK_INFRA_NFI_HCK_CK>; -+ clock-names = "pad_clk", "nfi_clk", "nfi_hclk"; -+ assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>, -+ <&topckgen CK_TOP_NFI1X_SEL>; -+ assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>, -+ <&topckgen CK_TOP_CB_M_D8>; -+ status = "disabled"; -+ }; -+ -+ ethsys: syscon@15000000 { -+ compatible = "mediatek,mt7986-ethsys", "syscon"; -+ reg = <0x15000000 0x1000>; -+ clock-parent = <&topckgen>; -+ #clock-cells = <1>; -+ #reset-cells = <1>; -+ }; -+ -+ eth: ethernet@15100000 { -+ compatible = "mediatek,mt7986-eth", "syscon"; -+ reg = <0x15100000 0x20000>; -+ resets = <ðsys ETHSYS_FE_RST>; -+ reset-names = "fe"; -+ mediatek,ethsys = <ðsys>; -+ mediatek,sgmiisys = <&sgmiisys0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ sgmiisys0: syscon@10060000 { -+ compatible = "mediatek,mt7986-sgmiisys", "syscon"; -+ reg = <0x10060000 0x1000>; -+ #clock-cells = <1>; -+ }; -+ -+ sgmiisys1: syscon@10070000 { -+ compatible = "mediatek,mt7986-sgmiisys", "syscon"; -+ reg = <0x10070000 0x1000>; -+ #clock-cells = <1>; -+ }; -+ -+ spi0: spi@1100a000 { -+ compatible = "mediatek,ipm-spi"; -+ reg = <0x1100a000 0x100>; -+ clocks = <&infracfg_ao CK_INFRA_SPI0_CK>, -+ <&topckgen CK_TOP_SPI_SEL>; -+ assigned-clocks = <&topckgen CK_TOP_SPI_SEL>, -+ <&infracfg CK_INFRA_SPI0_SEL>; -+ assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>, -+ <&topckgen CK_INFRA_ISPI0>; -+ clock-names = "sel-clk", "spi-clk"; -+ interrupts = ; -+ status = "disabled"; -+ }; -+ -+ spi1: spi@1100b000 { -+ compatible = "mediatek,ipm-spi"; -+ reg = <0x1100b000 0x100>; -+ interrupts = ; -+ status = "disabled"; -+ }; -+ -+ mmc0: mmc@11230000 { -+ compatible = "mediatek,mt7986-mmc"; -+ reg = <0x11230000 0x1000>, -+ <0x11C20000 0x1000>; -+ interrupts = ; -+ clocks = <&topckgen CK_TOP_EMMC_416M>, -+ <&topckgen CK_TOP_EMMC_250M>, -+ <&infracfg_ao CK_INFRA_MSDC_CK>; -+ assigned-clocks = <&topckgen CK_TOP_EMMC_416M_SEL>, -+ <&topckgen CK_TOP_EMMC_250M_SEL>; -+ assigned-clock-parents = <&topckgen CK_TOP_CB_M_416M>, -+ <&topckgen CK_TOP_NET1_D5_D2>; -+ clock-names = "source", "hclk", "source_cg"; -+ status = "disabled"; -+ }; -+ -+ xhci: xhci@11200000 { -+ compatible = "mediatek,mt7986-xhci", -+ "mediatek,mtk-xhci"; -+ reg = <0x11200000 0x2e00>, -+ <0x11203e00 0x0100>; -+ reg-names = "mac", "ippc"; -+ interrupts = ; -+ phys = <&u2port0 PHY_TYPE_USB2>, -+ <&u3port0 PHY_TYPE_USB3>, -+ <&u2port1 PHY_TYPE_USB2>; -+ clocks = <&dummy_clk>, -+ <&dummy_clk>, -+ <&dummy_clk>, -+ <&dummy_clk>, -+ <&dummy_clk>; -+ clock-names = "sys_ck", -+ "xhci_ck", -+ "ref_ck", -+ "mcu_ck", -+ "dma_ck"; -+ tpl-support; -+ status = "okay"; -+ }; -+ -+ usbtphy: usb-phy@11e10000 { -+ compatible = "mediatek,mt7986", -+ "mediatek,generic-tphy-v2"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ status = "okay"; -+ -+ u2port0: usb-phy@11e10000 { -+ reg = <0x11e10000 0x700>; -+ clocks = <&dummy_clk>; -+ clock-names = "ref"; -+ #phy-cells = <1>; -+ status = "okay"; -+ }; -+ -+ u3port0: usb-phy@11e10700 { -+ reg = <0x11e10700 0x900>; -+ clocks = <&dummy_clk>; -+ clock-names = "ref"; -+ #phy-cells = <1>; -+ status = "okay"; -+ }; -+ -+ u2port1: usb-phy@11e11000 { -+ reg = <0x11e11000 0x700>; -+ clocks = <&dummy_clk>; -+ clock-names = "ref"; -+ #phy-cells = <1>; -+ status = "okay"; -+ }; -+ }; -+}; ---- a/arch/arm/mach-mediatek/Kconfig -+++ b/arch/arm/mach-mediatek/Kconfig -@@ -40,6 +40,15 @@ config TARGET_MT7629 - including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet, - switch, USB3.0, PCIe, UART, SPI, I2C and PWM. - -+config TARGET_MT7986 -+ bool "MediaTek MT7986 SoC" -+ select ARM64 -+ select CPU -+ help -+ The MediaTek MT7986 is a ARM64-based SoC with a quad-core Cortex-A53. -+ including UART, SPI, SPI flash, USB3.0, MMC, NAND, SNFI, PWM, PCIe, -+ Gigabit Ethernet, I2C, built-in 4x4 Wi-Fi, and PCIe. -+ - config TARGET_MT8183 - bool "MediaTek MT8183 SoC" - select ARM64 -@@ -84,6 +93,7 @@ config SYS_BOARD - default "mt7622" if TARGET_MT7622 - default "mt7623" if TARGET_MT7623 - default "mt7629" if TARGET_MT7629 -+ default "mt7986" if TARGET_MT7986 - default "mt8183" if TARGET_MT8183 - default "mt8512" if TARGET_MT8512 - default "mt8516" if TARGET_MT8516 -@@ -99,6 +109,7 @@ config SYS_CONFIG_NAME - default "mt7622" if TARGET_MT7622 - default "mt7623" if TARGET_MT7623 - default "mt7629" if TARGET_MT7629 -+ default "mt7986" if TARGET_MT7986 - default "mt8183" if TARGET_MT8183 - default "mt8512" if TARGET_MT8512 - default "mt8516" if TARGET_MT8516 -@@ -113,6 +124,7 @@ config MTK_BROM_HEADER_INFO - string - default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622 - default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 -+ default "media=snand;nandinfo=2k+64" if TARGET_MT7986 - default "lk=1" if TARGET_MT7623 - - endif ---- a/arch/arm/mach-mediatek/Makefile -+++ b/arch/arm/mach-mediatek/Makefile -@@ -7,6 +7,7 @@ obj-$(CONFIG_MT8512) += mt8512/ - obj-$(CONFIG_TARGET_MT7622) += mt7622/ - obj-$(CONFIG_TARGET_MT7623) += mt7623/ - obj-$(CONFIG_TARGET_MT7629) += mt7629/ -+obj-$(CONFIG_TARGET_MT7986) += mt7986/ - obj-$(CONFIG_TARGET_MT8183) += mt8183/ - obj-$(CONFIG_TARGET_MT8516) += mt8516/ - obj-$(CONFIG_TARGET_MT8518) += mt8518/ ---- /dev/null -+++ b/arch/arm/mach-mediatek/mt7986/Makefile -@@ -0,0 +1,4 @@ -+# SPDX-License-Identifier: GPL-2.0 -+ -+obj-y += init.o -+obj-y += lowlevel_init.o ---- /dev/null -+++ b/arch/arm/mach-mediatek/mt7986/init.c -@@ -0,0 +1,45 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Sam Shih -+ */ -+ -+#include -+#include -+#include -+#include -+ -+DECLARE_GLOBAL_DATA_PTR; -+ -+int dram_init(void) -+{ -+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G); -+ -+ return 0; -+} -+ -+void reset_cpu(ulong addr) -+{ -+ psci_system_reset(); -+} -+ -+static struct mm_region mt7986_mem_map[] = { -+ { -+ /* DDR */ -+ .virt = 0x40000000UL, -+ .phys = 0x40000000UL, -+ .size = 0x80000000UL, -+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, -+ }, { -+ .virt = 0x00000000UL, -+ .phys = 0x00000000UL, -+ .size = 0x40000000UL, -+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | -+ PTE_BLOCK_NON_SHARE | -+ PTE_BLOCK_PXN | PTE_BLOCK_UXN -+ }, { -+ 0, -+ } -+}; -+ -+struct mm_region *mem_map = mt7986_mem_map; ---- /dev/null -+++ b/arch/arm/mach-mediatek/mt7986/lowlevel_init.S -@@ -0,0 +1,32 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Sam Shih -+ */ -+ -+/* -+ * Switch from AArch64 EL2 to AArch32 EL2 -+ * @param inputs: -+ * x0: argument, zero -+ * x1: machine nr -+ * x2: fdt address -+ * x3: input argument -+ * x4: kernel entry point -+ * @param outputs for secure firmware: -+ * x0: function id -+ * x1: kernel entry point -+ * x2: machine nr -+ * x3: fdt address -+ * -+ * [1] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/mediatek/common/mtk_sip_svc.c -+*/ -+ -+.global armv8_el2_to_aarch32 -+armv8_el2_to_aarch32: -+ mov x3, x2 -+ mov x2, x1 -+ mov x1, x4 -+ mov x4, #0 -+ ldr x0, =0x82000200 /* MTK_SIP_KERNEL_BOOT_AARCH32 */ -+ SMC #0 -+ ret diff --git a/package/boot/uboot-mediatek/patches/002-0002-arm-mediatek-add-support-for-MediaTek-MT7981-SoC.patch b/package/boot/uboot-mediatek/patches/002-0002-arm-mediatek-add-support-for-MediaTek-MT7981-SoC.patch deleted file mode 100644 index 425f0de1b49..00000000000 --- a/package/boot/uboot-mediatek/patches/002-0002-arm-mediatek-add-support-for-MediaTek-MT7981-SoC.patch +++ /dev/null @@ -1,462 +0,0 @@ -From 5512a2e8257b0a733cf90ec247f34094ff31f750 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 31 Aug 2022 19:00:20 +0800 -Subject: [PATCH 02/32] arm: mediatek: add support for MediaTek MT7981 SoC - -This patch adds basic support for MediaTek MT7981 SoC. -This include the file that will initialize the SoC after boot and its -device tree. - -Signed-off-by: Weijie Gao ---- - arch/arm/dts/mt7981.dtsi | 293 ++++++++++++++++++ - arch/arm/mach-mediatek/Kconfig | 13 +- - arch/arm/mach-mediatek/Makefile | 1 + - arch/arm/mach-mediatek/mt7981/Makefile | 4 + - arch/arm/mach-mediatek/mt7981/init.c | 45 +++ - arch/arm/mach-mediatek/mt7981/lowlevel_init.S | 32 ++ - 6 files changed, 387 insertions(+), 1 deletion(-) - create mode 100644 arch/arm/dts/mt7981.dtsi - create mode 100644 arch/arm/mach-mediatek/mt7981/Makefile - create mode 100644 arch/arm/mach-mediatek/mt7981/init.c - create mode 100644 arch/arm/mach-mediatek/mt7981/lowlevel_init.S - ---- /dev/null -+++ b/arch/arm/dts/mt7981.dtsi -@@ -0,0 +1,293 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2022 MediaTek Inc. -+ * Author: Sam Shih -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+/ { -+ compatible = "mediatek,mt7981"; -+ interrupt-parent = <&gic>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ cpu0: cpu@0 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x0>; -+ }; -+ cpu1: cpu@1 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x1>; -+ }; -+ }; -+ -+ gpt_clk: gpt_dummy20m { -+ compatible = "fixed-clock"; -+ clock-frequency = <13000000>; -+ #clock-cells = <0>; -+ u-boot,dm-pre-reloc; -+ }; -+ -+ hwver: hwver { -+ compatible = "mediatek,hwver"; -+ reg = <0x8000000 0x1000>; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupt-parent = <&gic>; -+ clock-frequency = <13000000>; -+ interrupts = , -+ , -+ , -+ ; -+ arm,cpu-registers-not-fw-configured; -+ }; -+ -+ timer0: timer@10008000 { -+ compatible = "mediatek,mt7986-timer"; -+ reg = <0x10008000 0x1000>; -+ interrupts = ; -+ clocks = <&gpt_clk>; -+ clock-names = "gpt-clk"; -+ u-boot,dm-pre-reloc; -+ }; -+ -+ watchdog: watchdog@1001c000 { -+ compatible = "mediatek,mt7986-wdt"; -+ reg = <0x1001c000 0x1000>; -+ interrupts = ; -+ #reset-cells = <1>; -+ status = "disabled"; -+ }; -+ -+ gic: interrupt-controller@c000000 { -+ compatible = "arm,gic-v3"; -+ #interrupt-cells = <3>; -+ interrupt-parent = <&gic>; -+ interrupt-controller; -+ reg = <0x0c000000 0x40000>, /* GICD */ -+ <0x0c080000 0x200000>; /* GICR */ -+ -+ interrupts = ; -+ }; -+ -+ fixed_plls: apmixedsys@1001e000 { -+ compatible = "mediatek,mt7981-fixed-plls"; -+ reg = <0x1001e000 0x1000>; -+ #clock-cells = <1>; -+ u-boot,dm-pre-reloc; -+ }; -+ -+ topckgen: topckgen@1001b000 { -+ compatible = "mediatek,mt7981-topckgen"; -+ reg = <0x1001b000 0x1000>; -+ clock-parent = <&fixed_plls>; -+ #clock-cells = <1>; -+ u-boot,dm-pre-reloc; -+ }; -+ -+ infracfg_ao: infracfg_ao@10001000 { -+ compatible = "mediatek,mt7981-infracfg_ao"; -+ reg = <0x10001000 0x80>; -+ clock-parent = <&infracfg>; -+ #clock-cells = <1>; -+ u-boot,dm-pre-reloc; -+ }; -+ -+ infracfg: infracfg@10001000 { -+ compatible = "mediatek,mt7981-infracfg"; -+ reg = <0x10001000 0x30>; -+ clock-parent = <&topckgen>; -+ #clock-cells = <1>; -+ u-boot,dm-pre-reloc; -+ }; -+ -+ pinctrl: pinctrl@11d00000 { -+ compatible = "mediatek,mt7981-pinctrl"; -+ reg = <0x11d00000 0x1000>, -+ <0x11c00000 0x1000>, -+ <0x11c10000 0x1000>, -+ <0x11d20000 0x1000>, -+ <0x11e00000 0x1000>, -+ <0x11e20000 0x1000>, -+ <0x11f00000 0x1000>, -+ <0x11f10000 0x1000>, -+ <0x1000b000 0x1000>; -+ reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rm_base", -+ "iocfg_rb_base", "iocfg_lb_base", "iocfg_bl_base", -+ "iocfg_tm_base", "iocfg_tl_base", "eint"; -+ gpio: gpio-controller { -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ }; -+ -+ pwm: pwm@10048000 { -+ compatible = "mediatek,mt7981-pwm"; -+ reg = <0x10048000 0x1000>; -+ #clock-cells = <1>; -+ #pwm-cells = <2>; -+ interrupts = ; -+ clocks = <&infracfg CK_INFRA_PWM>, -+ <&infracfg_ao CK_INFRA_PWM_BSEL>, -+ <&infracfg_ao CK_INFRA_PWM1_CK>, -+ <&infracfg_ao CK_INFRA_PWM2_CK>, -+ /* FIXME */ -+ <&infracfg_ao CK_INFRA_PWM2_CK>; -+ assigned-clocks = <&topckgen CK_TOP_PWM_SEL>; -+ assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>; -+ clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; -+ status = "disabled"; -+ }; -+ -+ uart0: serial@11002000 { -+ compatible = "mediatek,hsuart"; -+ reg = <0x11002000 0x400>; -+ interrupts = ; -+ clocks = <&infracfg_ao CK_INFRA_UART0_CK>; -+ assigned-clocks = <&topckgen CK_TOP_UART_SEL>, -+ <&infracfg_ao CK_INFRA_UART0_SEL>; -+ assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, -+ <&infracfg CK_INFRA_UART>; -+ mediatek,force-highspeed; -+ status = "disabled"; -+ u-boot,dm-pre-reloc; -+ }; -+ -+ uart1: serial@11003000 { -+ compatible = "mediatek,hsuart"; -+ reg = <0x11003000 0x400>; -+ interrupts = ; -+ clocks = <&infracfg_ao CK_INFRA_UART1_CK>; -+ assigned-clocks = <&topckgen CK_TOP_UART_SEL>, -+ <&infracfg_ao CK_INFRA_UART1_SEL>; -+ assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, -+ <&infracfg CK_INFRA_UART>; -+ mediatek,force-highspeed; -+ status = "disabled"; -+ }; -+ -+ uart2: serial@11004000 { -+ compatible = "mediatek,hsuart"; -+ reg = <0x11004000 0x400>; -+ interrupts = ; -+ clocks = <&infracfg_ao CK_INFRA_UART2_CK>; -+ assigned-clocks = <&topckgen CK_TOP_UART_SEL>, -+ <&infracfg_ao CK_INFRA_UART2_SEL>; -+ assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, -+ <&infracfg CK_INFRA_UART>; -+ mediatek,force-highspeed; -+ status = "disabled"; -+ }; -+ -+ snand: snand@11005000 { -+ compatible = "mediatek,mt7986-snand"; -+ reg = <0x11005000 0x1000>, -+ <0x11006000 0x1000>; -+ reg-names = "nfi", "ecc"; -+ clocks = <&infracfg_ao CK_INFRA_SPINFI1_CK>, -+ <&infracfg_ao CK_INFRA_NFI1_CK>, -+ <&infracfg_ao CK_INFRA_NFI_HCK_CK>; -+ clock-names = "pad_clk", "nfi_clk", "nfi_hclk"; -+ assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>, -+ <&topckgen CK_TOP_NFI1X_SEL>; -+ assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>, -+ <&topckgen CK_TOP_CB_M_D8>; -+ status = "disabled"; -+ }; -+ -+ ethsys: syscon@15000000 { -+ compatible = "mediatek,mt7981-ethsys", "syscon"; -+ reg = <0x15000000 0x1000>; -+ clock-parent = <&topckgen>; -+ #clock-cells = <1>; -+ #reset-cells = <1>; -+ }; -+ -+ eth: ethernet@15100000 { -+ compatible = "mediatek,mt7981-eth", "syscon"; -+ reg = <0x15100000 0x20000>; -+ resets = <ðsys ETHSYS_FE_RST>; -+ reset-names = "fe"; -+ mediatek,ethsys = <ðsys>; -+ mediatek,sgmiisys = <&sgmiisys0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ sgmiisys0: syscon@10060000 { -+ compatible = "mediatek,mt7986-sgmiisys", "syscon"; -+ reg = <0x10060000 0x1000>; -+ pn_swap; -+ #clock-cells = <1>; -+ }; -+ -+ sgmiisys1: syscon@10070000 { -+ compatible = "mediatek,mt7986-sgmiisys", "syscon"; -+ reg = <0x10070000 0x1000>; -+ #clock-cells = <1>; -+ }; -+ -+ spi0: spi@1100a000 { -+ compatible = "mediatek,ipm-spi"; -+ reg = <0x1100a000 0x100>; -+ clocks = <&infracfg_ao CK_INFRA_SPI0_CK>, -+ <&topckgen CK_TOP_SPI_SEL>; -+ assigned-clocks = <&topckgen CK_TOP_SPI_SEL>, -+ <&infracfg CK_INFRA_SPI0_SEL>; -+ assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>, -+ <&topckgen CK_INFRA_ISPI0>; -+ clock-names = "sel-clk", "spi-clk"; -+ interrupts = ; -+ status = "disabled"; -+ }; -+ -+ spi1: spi@1100b000 { -+ compatible = "mediatek,ipm-spi"; -+ reg = <0x1100b000 0x100>; -+ interrupts = ; -+ status = "disabled"; -+ }; -+ -+ spi2: spi@11009000 { -+ compatible = "mediatek,ipm-spi"; -+ reg = <0x11009000 0x100>; -+ clocks = <&infracfg_ao CK_INFRA_SPI0_CK>, -+ <&topckgen CK_TOP_SPI_SEL>; -+ assigned-clocks = <&topckgen CK_TOP_SPI_SEL>, -+ <&infracfg CK_INFRA_SPI0_SEL>; -+ assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>, -+ <&topckgen CK_INFRA_ISPI0>; -+ clock-names = "sel-clk", "spi-clk"; -+ interrupts = ; -+ status = "disabled"; -+ }; -+ -+ mmc0: mmc@11230000 { -+ compatible = "mediatek,mt7981-mmc"; -+ reg = <0x11230000 0x1000>, -+ <0x11C20000 0x1000>; -+ interrupts = ; -+ clocks = <&topckgen CK_TOP_EMMC_400M>, -+ <&topckgen CK_TOP_EMMC_208M>, -+ <&infracfg_ao CK_INFRA_MSDC_CK>; -+ assigned-clocks = <&topckgen CK_TOP_EMMC_400M_SEL>, -+ <&topckgen CK_TOP_EMMC_208M_SEL>; -+ assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_D2>, -+ <&topckgen CK_TOP_CB_M_D2>; -+ clock-names = "source", "hclk", "source_cg"; -+ status = "disabled"; -+ }; -+ -+}; ---- a/arch/arm/mach-mediatek/Kconfig -+++ b/arch/arm/mach-mediatek/Kconfig -@@ -40,6 +40,15 @@ config TARGET_MT7629 - including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet, - switch, USB3.0, PCIe, UART, SPI, I2C and PWM. - -+config TARGET_MT7981 -+ bool "MediaTek MT7981 SoC" -+ select ARM64 -+ select CPU -+ help -+ The MediaTek MT7981 is a ARM64-based SoC with a dual-core Cortex-A53. -+ including UART, SPI, USB, NAND, SNFI, PWM, Gigabit Ethernet, I2C, -+ built-in Wi-Fi, and PCIe. -+ - config TARGET_MT7986 - bool "MediaTek MT7986 SoC" - select ARM64 -@@ -93,6 +102,7 @@ config SYS_BOARD - default "mt7622" if TARGET_MT7622 - default "mt7623" if TARGET_MT7623 - default "mt7629" if TARGET_MT7629 -+ default "mt7981" if TARGET_MT7981 - default "mt7986" if TARGET_MT7986 - default "mt8183" if TARGET_MT8183 - default "mt8512" if TARGET_MT8512 -@@ -109,6 +119,7 @@ config SYS_CONFIG_NAME - default "mt7622" if TARGET_MT7622 - default "mt7623" if TARGET_MT7623 - default "mt7629" if TARGET_MT7629 -+ default "mt7981" if TARGET_MT7981 - default "mt7986" if TARGET_MT7986 - default "mt8183" if TARGET_MT8183 - default "mt8512" if TARGET_MT8512 -@@ -124,7 +135,7 @@ config MTK_BROM_HEADER_INFO - string - default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622 - default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 -- default "media=snand;nandinfo=2k+64" if TARGET_MT7986 -+ default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 - default "lk=1" if TARGET_MT7623 - - endif ---- a/arch/arm/mach-mediatek/Makefile -+++ b/arch/arm/mach-mediatek/Makefile -@@ -7,6 +7,7 @@ obj-$(CONFIG_MT8512) += mt8512/ - obj-$(CONFIG_TARGET_MT7622) += mt7622/ - obj-$(CONFIG_TARGET_MT7623) += mt7623/ - obj-$(CONFIG_TARGET_MT7629) += mt7629/ -+obj-$(CONFIG_TARGET_MT7981) += mt7981/ - obj-$(CONFIG_TARGET_MT7986) += mt7986/ - obj-$(CONFIG_TARGET_MT8183) += mt8183/ - obj-$(CONFIG_TARGET_MT8516) += mt8516/ ---- /dev/null -+++ b/arch/arm/mach-mediatek/mt7981/Makefile -@@ -0,0 +1,4 @@ -+# SPDX-License-Identifier: GPL-2.0 -+ -+obj-y += init.o -+obj-y += lowlevel_init.o ---- /dev/null -+++ b/arch/arm/mach-mediatek/mt7981/init.c -@@ -0,0 +1,45 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Sam Shih -+ */ -+ -+#include -+#include -+#include -+#include -+ -+DECLARE_GLOBAL_DATA_PTR; -+ -+int dram_init(void) -+{ -+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G); -+ -+ return 0; -+} -+ -+void reset_cpu(ulong addr) -+{ -+ psci_system_reset(); -+} -+ -+static struct mm_region mt7981_mem_map[] = { -+ { -+ /* DDR */ -+ .virt = 0x40000000UL, -+ .phys = 0x40000000UL, -+ .size = 0x80000000UL, -+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, -+ }, { -+ .virt = 0x00000000UL, -+ .phys = 0x00000000UL, -+ .size = 0x40000000UL, -+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | -+ PTE_BLOCK_NON_SHARE | -+ PTE_BLOCK_PXN | PTE_BLOCK_UXN -+ }, { -+ 0, -+ } -+}; -+ -+struct mm_region *mem_map = mt7981_mem_map; ---- /dev/null -+++ b/arch/arm/mach-mediatek/mt7981/lowlevel_init.S -@@ -0,0 +1,32 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Sam Shih -+ */ -+ -+/* -+ * Switch from AArch64 EL2 to AArch32 EL2 -+ * @param inputs: -+ * x0: argument, zero -+ * x1: machine nr -+ * x2: fdt address -+ * x3: input argument -+ * x4: kernel entry point -+ * @param outputs for secure firmware: -+ * x0: function id -+ * x1: kernel entry point -+ * x2: machine nr -+ * x3: fdt address -+ * -+ * [1] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/mediatek/common/mtk_sip_svc.c -+*/ -+ -+.global armv8_el2_to_aarch32 -+armv8_el2_to_aarch32: -+ mov x3, x2 -+ mov x2, x1 -+ mov x1, x4 -+ mov x4, #0 -+ ldr x0, =0x82000200 /* MTK_SIP_KERNEL_BOOT_AARCH32 */ -+ SMC #0 -+ ret diff --git a/package/boot/uboot-mediatek/patches/002-0003-board-mediatek-add-MT7986-reference-boards.patch b/package/boot/uboot-mediatek/patches/002-0003-board-mediatek-add-MT7986-reference-boards.patch deleted file mode 100644 index 10edb0a3e68..00000000000 --- a/package/boot/uboot-mediatek/patches/002-0003-board-mediatek-add-MT7986-reference-boards.patch +++ /dev/null @@ -1,1148 +0,0 @@ -From bad27c737d27f8afc4d597b6de1bdbc26a152ad9 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 31 Aug 2022 19:00:22 +0800 -Subject: [PATCH 03/32] board: mediatek: add MT7986 reference boards - -Add general board files based on MT7986 SoCs. - -MT7986 uses one mmc controller for booting from both SD and eMMC. -Both MT7986A and MT7986B use the same pins for spi controller. - -Configs for various boot types: -1. mt7986_rfb_defconfig - SPI-NOR and SPI-NAND for MT7986A/B -2. mt7986a_bpir3_emmc_defconfig - eMMC for MT7986A only -3. mt7986a_bpir3_sd_defconfig - SD for MT7986A only - -Reviewed-by: Simon Glass -Signed-off-by: Weijie Gao ---- - arch/arm/dts/Makefile | 6 + - arch/arm/dts/mt7986a-emmc-rfb.dts | 16 ++ - arch/arm/dts/mt7986a-rfb.dts | 218 +++++++++++++++++++++++++++ - arch/arm/dts/mt7986a-sd-rfb.dts | 177 ++++++++++++++++++++++ - arch/arm/dts/mt7986b-emmc-rfb.dts | 16 ++ - arch/arm/dts/mt7986b-rfb.dts | 204 +++++++++++++++++++++++++ - arch/arm/dts/mt7986b-sd-rfb.dts | 173 +++++++++++++++++++++ - board/mediatek/mt7986/MAINTAINERS | 10 ++ - board/mediatek/mt7986/Makefile | 3 + - board/mediatek/mt7986/mt7986_rfb.c | 10 ++ - configs/mt7986_rfb_defconfig | 66 ++++++++ - configs/mt7986a_bpir3_emmc_defconfig | 64 ++++++++ - configs/mt7986a_bpir3_sd_defconfig | 64 ++++++++ - include/configs/mt7986.h | 26 ++++ - 14 files changed, 1053 insertions(+) - create mode 100644 arch/arm/dts/mt7986a-emmc-rfb.dts - create mode 100644 arch/arm/dts/mt7986a-rfb.dts - create mode 100644 arch/arm/dts/mt7986a-sd-rfb.dts - create mode 100644 arch/arm/dts/mt7986b-emmc-rfb.dts - create mode 100644 arch/arm/dts/mt7986b-rfb.dts - create mode 100644 arch/arm/dts/mt7986b-sd-rfb.dts - create mode 100644 board/mediatek/mt7986/MAINTAINERS - create mode 100644 board/mediatek/mt7986/Makefile - create mode 100644 board/mediatek/mt7986/mt7986_rfb.c - create mode 100644 configs/mt7986_rfb_defconfig - create mode 100644 configs/mt7986a_bpir3_emmc_defconfig - create mode 100644 configs/mt7986a_bpir3_sd_defconfig - create mode 100644 include/configs/mt7986.h - ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -1233,6 +1233,12 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ - mt7622-bananapi-bpi-r64.dtb \ - mt7623n-bananapi-bpi-r2.dtb \ - mt7629-rfb.dtb \ -+ mt7986a-rfb.dtb \ -+ mt7986b-rfb.dtb \ -+ mt7986a-sd-rfb.dtb \ -+ mt7986b-sd-rfb.dtb \ -+ mt7986a-emmc-rfb.dtb \ -+ mt7986b-emmc-rfb.dtb \ - mt8183-pumpkin.dtb \ - mt8512-bm1-emmc.dtb \ - mt8516-pumpkin.dtb \ ---- /dev/null -+++ b/arch/arm/dts/mt7986a-emmc-rfb.dts -@@ -0,0 +1,16 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2022 MediaTek Inc. -+ * Author: Sam Shih -+ */ -+ -+/dts-v1/; -+#include "mt7986a-rfb.dts" -+ -+/ { -+ compatible = "mediatek,mt7986", "mediatek,mt7986-rfb", -+ "mediatek,mt7986-emmc-rfb"; -+ bl2_verify { -+ bl2_compatible = "emmc"; -+ }; -+}; ---- /dev/null -+++ b/arch/arm/dts/mt7986a-rfb.dts -@@ -0,0 +1,218 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2022 MediaTek Inc. -+ * Author: Sam Shih -+ */ -+ -+/dts-v1/; -+#include "mt7986.dtsi" -+#include -+ -+/ { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ model = "mt7986-rfb"; -+ compatible = "mediatek,mt7986", "mediatek,mt7986-rfb"; -+ chosen { -+ stdout-path = &uart0; -+ tick-timer = &timer0; -+ }; -+ -+ reg_1p8v: regulator-1p8v { -+ compatible = "regulator-fixed"; -+ regulator-name = "fixed-1.8V"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ reg_3p3v: regulator-3p3v { -+ compatible = "regulator-fixed"; -+ regulator-name = "fixed-3.3V"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>; -+ status = "disabled"; -+}; -+ -+ð { -+ status = "okay"; -+ mediatek,gmac-id = <0>; -+ phy-mode = "sgmii"; -+ mediatek,switch = "mt7531"; -+ reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; -+ -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+}; -+ -+&pinctrl { -+ spi_flash_pins: spi0-pins-func-1 { -+ mux { -+ function = "flash"; -+ groups = "spi0", "spi0_wp_hold"; -+ }; -+ -+ conf-pu { -+ pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; -+ drive-strength = ; -+ bias-pull-up = ; -+ }; -+ -+ conf-pd { -+ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; -+ drive-strength = ; -+ bias-pull-down = ; -+ }; -+ }; -+ -+ snfi_pins: snfi-pins-func-1 { -+ mux { -+ function = "flash"; -+ groups = "snfi"; -+ }; -+ -+ clk { -+ pins = "SPI0_CLK"; -+ drive-strength = ; -+ bias-pull-down = ; -+ }; -+ -+ conf-pu { -+ pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; -+ drive-strength = ; -+ bias-pull-up = ; -+ }; -+ -+ conf-pd { -+ pins = "SPI0_MOSI", "SPI0_MISO"; -+ drive-strength = ; -+ bias-pull-down = ; -+ }; -+ }; -+ -+ spic_pins: spi1-pins-func-1 { -+ mux { -+ function = "spi"; -+ groups = "spi1_2"; -+ }; -+ }; -+ -+ uart1_pins: spi1-pins-func-3 { -+ mux { -+ function = "uart"; -+ groups = "uart1_2"; -+ }; -+ }; -+ -+ pwm_pins: pwm0-pins-func-1 { -+ mux { -+ function = "pwm"; -+ groups = "pwm0"; -+ }; -+ }; -+ -+ mmc0_pins_default: mmc0default { -+ mux { -+ function = "flash"; -+ groups = "emmc_51"; -+ }; -+ -+ conf-cmd-dat { -+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", -+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", -+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; -+ input-enable; -+ drive-strength = ; -+ bias-pull-up = ; -+ }; -+ -+ conf-clk { -+ pins = "EMMC_CK"; -+ drive-strength = ; -+ bias-pull-down = ; -+ }; -+ -+ conf-dsl { -+ pins = "EMMC_DSL"; -+ bias-pull-down = ; -+ }; -+ -+ conf-rst { -+ pins = "EMMC_RSTB"; -+ drive-strength = ; -+ bias-pull-up = ; -+ }; -+ }; -+}; -+ -+&snand { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&snfi_pins>; -+ status = "okay"; -+ quad-spi; -+}; -+ -+&spi0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi_flash_pins>; -+ status = "okay"; -+ must_tx; -+ enhance_timing; -+ dma_ext; -+ ipm_design; -+ support_quad; -+ tick_dly = <2>; -+ sample_sel = <0>; -+ -+ spi_nor@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <52000000>; -+ }; -+ -+ spi_nand@1 { -+ compatible = "spi-nand"; -+ reg = <1>; -+ spi-max-frequency = <52000000>; -+ }; -+}; -+ -+&pwm { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pwm_pins>; -+ status = "okay"; -+}; -+ -+&watchdog { -+ status = "disabled"; -+}; -+ -+&mmc0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc0_pins_default>; -+ bus-width = <8>; -+ max-frequency = <52000000>; -+ cap-mmc-highspeed; -+ cap-mmc-hw-reset; -+ vmmc-supply = <®_3p3v>; -+ vqmmc-supply = <®_1p8v>; -+ non-removable; -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/dts/mt7986a-sd-rfb.dts -@@ -0,0 +1,177 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2022 MediaTek Inc. -+ * Author: Sam Shih -+ */ -+ -+/dts-v1/; -+#include "mt7986.dtsi" -+#include -+ -+/ { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ model = "mt7986-rfb"; -+ compatible = "mediatek,mt7986", "mediatek,mt7986-rfb", -+ "mediatek,mt7986-sd-rfb"; -+ chosen { -+ stdout-path = &uart0; -+ tick-timer = &timer0; -+ }; -+ -+ reg_3p3v: regulator-3p3v { -+ compatible = "regulator-fixed"; -+ regulator-name = "fixed-3.3V"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>; -+ status = "disabled"; -+}; -+ -+ð { -+ status = "okay"; -+ mediatek,gmac-id = <0>; -+ phy-mode = "sgmii"; -+ mediatek,switch = "mt7531"; -+ reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; -+ -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+}; -+ -+&pinctrl { -+ spi_flash_pins: spi0-pins-func-1 { -+ mux { -+ function = "flash"; -+ groups = "spi0", "spi0_wp_hold"; -+ }; -+ -+ conf-pu { -+ pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; -+ drive-strength = ; -+ bias-pull-up = ; -+ }; -+ -+ conf-pd { -+ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; -+ drive-strength = ; -+ bias-pull-down = ; -+ }; -+ }; -+ -+ spic_pins: spi1-pins-func-1 { -+ mux { -+ function = "spi"; -+ groups = "spi1_2"; -+ }; -+ }; -+ -+ uart1_pins: spi1-pins-func-3 { -+ mux { -+ function = "uart"; -+ groups = "uart1_2"; -+ }; -+ }; -+ -+ pwm_pins: pwm0-pins-func-1 { -+ mux { -+ function = "pwm"; -+ groups = "pwm0"; -+ }; -+ }; -+ -+ mmc0_pins_default: mmc0default { -+ mux { -+ function = "flash"; -+ groups = "emmc_51"; -+ }; -+ -+ conf-cmd-dat { -+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", -+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", -+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; -+ input-enable; -+ drive-strength = ; -+ bias-pull-up = ; -+ }; -+ -+ conf-clk { -+ pins = "EMMC_CK"; -+ drive-strength = ; -+ bias-pull-down = ; -+ }; -+ -+ conf-dsl { -+ pins = "EMMC_DSL"; -+ bias-pull-down = ; -+ }; -+ -+ conf-rst { -+ pins = "EMMC_RSTB"; -+ drive-strength = ; -+ bias-pull-up = ; -+ }; -+ }; -+}; -+ -+&spi0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi_flash_pins>; -+ status = "okay"; -+ must_tx; -+ enhance_timing; -+ dma_ext; -+ ipm_design; -+ support_quad; -+ tick_dly = <2>; -+ sample_sel = <0>; -+ -+ spi_nor@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <52000000>; -+ }; -+ -+ spi_nand@1 { -+ compatible = "spi-nand"; -+ reg = <1>; -+ spi-max-frequency = <52000000>; -+ }; -+}; -+ -+&pwm { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pwm_pins>; -+ status = "okay"; -+}; -+ -+&watchdog { -+ status = "disabled"; -+}; -+ -+&mmc0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc0_pins_default>; -+ bus-width = <4>; -+ max-frequency = <52000000>; -+ cap-sd-highspeed; -+ r_smpl = <1>; -+ vmmc-supply = <®_3p3v>; -+ vqmmc-supply = <®_3p3v>; -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/dts/mt7986b-emmc-rfb.dts -@@ -0,0 +1,16 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2022 MediaTek Inc. -+ * Author: Sam Shih -+ */ -+ -+/dts-v1/; -+#include "mt7986a-rfb.dts" -+ -+/ { -+ compatible = "mediatek,mt7986", "mediatek,mt7986-rfb", -+ "mediatek,mt7986-emmc-rfb"; -+ bl2_verify { -+ bl2_compatible = "emmc"; -+ }; -+}; ---- /dev/null -+++ b/arch/arm/dts/mt7986b-rfb.dts -@@ -0,0 +1,204 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2022 MediaTek Inc. -+ * Author: Sam Shih -+ */ -+ -+/dts-v1/; -+#include "mt7986.dtsi" -+#include -+ -+/ { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ model = "mt7986-rfb"; -+ compatible = "mediatek,mt7986", "mediatek,mt7986-rfb"; -+ chosen { -+ stdout-path = &uart0; -+ tick-timer = &timer0; -+ }; -+ -+ reg_3p3v: regulator-3p3v { -+ compatible = "regulator-fixed"; -+ regulator-name = "fixed-3.3V"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>; -+ status = "disabled"; -+}; -+ -+ð { -+ status = "okay"; -+ mediatek,gmac-id = <0>; -+ phy-mode = "sgmii"; -+ mediatek,switch = "mt7531"; -+ reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; -+ -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+}; -+ -+&pinctrl { -+ spi_flash_pins: spi0-pins-func-1 { -+ mux { -+ function = "flash"; -+ groups = "spi0", "spi0_wp_hold"; -+ }; -+ -+ conf-pu { -+ pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; -+ drive-strength = ; -+ bias-pull-up = ; -+ }; -+ -+ conf-pd { -+ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; -+ drive-strength = ; -+ bias-pull-down = ; -+ }; -+ }; -+ -+ snfi_pins: snfi-pins-func-1 { -+ mux { -+ function = "flash"; -+ groups = "snfi"; -+ }; -+ -+ clk { -+ pins = "SPI0_CLK"; -+ drive-strength = ; -+ bias-pull-down = ; -+ }; -+ -+ conf-pu { -+ pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; -+ drive-strength = ; -+ bias-pull-up = ; -+ }; -+ -+ conf-pd { -+ pins = "SPI0_MOSI", "SPI0_MISO"; -+ drive-strength = ; -+ bias-pull-down = ; -+ }; -+ }; -+ -+ spic_pins: spi1-pins-func-1 { -+ mux { -+ function = "spi"; -+ groups = "spi1_2"; -+ }; -+ }; -+ -+ uart1_pins: spi1-pins-func-3 { -+ mux { -+ function = "uart"; -+ groups = "uart1_2"; -+ }; -+ }; -+ -+ pwm_pins: pwm0-pins-func-1 { -+ mux { -+ function = "pwm"; -+ groups = "pwm0"; -+ }; -+ }; -+ -+ mmc0_pins_default: mmc0default { -+ mux { -+ function = "flash"; -+ groups = "emmc_45"; -+ input-schmitt-enable; -+ }; -+ -+ conf-cmd-dat { -+ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", -+ "SPI0_CS", "SPI0_HOLD", "SPI0_WP", -+ "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO"; -+ input-enable; -+ drive-strength = ; -+ bias-pull-up = ; -+ }; -+ -+ conf-clk { -+ pins = "SPI1_CS"; -+ drive-strength = ; -+ bias-pull-down = ; -+ }; -+ -+ conf-rst { -+ pins = "PWM1"; -+ drive-strength = ; -+ bias-pull-up = ; -+ }; -+ }; -+}; -+ -+&snand { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&snfi_pins>; -+ status = "okay"; -+ quad-spi; -+}; -+ -+&spi0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi_flash_pins>; -+ status = "okay"; -+ must_tx; -+ enhance_timing; -+ dma_ext; -+ ipm_design; -+ support_quad; -+ tick_dly = <2>; -+ sample_sel = <0>; -+ -+ spi_nor@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <52000000>; -+ }; -+ -+ spi_nand@1 { -+ compatible = "spi-nand"; -+ reg = <1>; -+ spi-max-frequency = <52000000>; -+ }; -+}; -+ -+&pwm { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pwm_pins>; -+ status = "okay"; -+}; -+ -+&watchdog { -+ status = "disabled"; -+}; -+ -+&mmc0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc0_pins_default>; -+ bus-width = <8>; -+ max-frequency = <52000000>; -+ cap-mmc-highspeed; -+ cap-mmc-hw-reset; -+ vmmc-supply = <®_3p3v>; -+ non-removable; -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/dts/mt7986b-sd-rfb.dts -@@ -0,0 +1,173 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2022 MediaTek Inc. -+ * Author: Sam Shih -+ */ -+ -+/dts-v1/; -+#include "mt7986.dtsi" -+#include -+ -+/ { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ model = "mt7986-rfb"; -+ compatible = "mediatek,mt7986", "mediatek,mt7986-rfb", -+ "mediatek,mt7986-sd-rfb"; -+ chosen { -+ stdout-path = &uart0; -+ tick-timer = &timer0; -+ }; -+ -+ reg_3p3v: regulator-3p3v { -+ compatible = "regulator-fixed"; -+ regulator-name = "fixed-3.3V"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>; -+ status = "disabled"; -+}; -+ -+ð { -+ status = "okay"; -+ mediatek,gmac-id = <0>; -+ phy-mode = "sgmii"; -+ mediatek,switch = "mt7531"; -+ reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; -+ -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+}; -+ -+&pinctrl { -+ spi_flash_pins: spi0-pins-func-1 { -+ mux { -+ function = "flash"; -+ groups = "spi0", "spi0_wp_hold"; -+ }; -+ -+ conf-pu { -+ pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; -+ drive-strength = ; -+ bias-pull-up = ; -+ }; -+ -+ conf-pd { -+ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; -+ drive-strength = ; -+ bias-pull-down = ; -+ }; -+ }; -+ -+ spic_pins: spi1-pins-func-1 { -+ mux { -+ function = "spi"; -+ groups = "spi1_2"; -+ }; -+ }; -+ -+ uart1_pins: spi1-pins-func-3 { -+ mux { -+ function = "uart"; -+ groups = "uart1_2"; -+ }; -+ }; -+ -+ pwm_pins: pwm0-pins-func-1 { -+ mux { -+ function = "pwm"; -+ groups = "pwm0"; -+ }; -+ }; -+ -+ mmc0_pins_default: mmc0default { -+ mux { -+ function = "flash"; -+ groups = "emmc_45"; -+ input-schmitt-enable; -+ }; -+ -+ conf-cmd-dat { -+ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", -+ "SPI0_CS", "SPI0_HOLD", "SPI0_WP", -+ "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO"; -+ input-enable; -+ drive-strength = ; -+ bias-pull-up = ; -+ }; -+ -+ conf-clk { -+ pins = "SPI1_CS"; -+ drive-strength = ; -+ bias-pull-down = ; -+ }; -+ -+ conf-rst { -+ pins = "PWM1"; -+ drive-strength = ; -+ bias-pull-up = ; -+ }; -+ }; -+}; -+ -+&spi0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi_flash_pins>; -+ status = "okay"; -+ must_tx; -+ enhance_timing; -+ dma_ext; -+ ipm_design; -+ support_quad; -+ tick_dly = <2>; -+ sample_sel = <0>; -+ -+ spi_nor@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <52000000>; -+ }; -+ -+ spi_nand@1 { -+ compatible = "spi-nand"; -+ reg = <1>; -+ spi-max-frequency = <52000000>; -+ }; -+}; -+ -+&pwm { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pwm_pins>; -+ status = "okay"; -+}; -+ -+&watchdog { -+ status = "disabled"; -+}; -+ -+&mmc0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc0_pins_default>; -+ bus-width = <4>; -+ max-frequency = <52000000>; -+ cap-sd-highspeed; -+ r_smpl = <1>; -+ vmmc-supply = <®_3p3v>; -+ vqmmc-supply = <®_3p3v>; -+ status = "okay"; -+}; ---- /dev/null -+++ b/board/mediatek/mt7986/MAINTAINERS -@@ -0,0 +1,10 @@ -+MT7986 -+M: Sam Shih -+S: Maintained -+F: board/mediatek/mt7986 -+F: include/configs/mt7986.h -+F: configs/mt7986_rfb_defconfig -+F: configs/mt7986a_emmc_rfb_defconfig -+F: configs/mt7986a_sd_rfb_defconfig -+F: configs/mt7986b_emmc_rfb_defconfig -+F: configs/mt7986b_sd_rfb_defconfig ---- /dev/null -+++ b/board/mediatek/mt7986/Makefile -@@ -0,0 +1,3 @@ -+# SPDX-License-Identifier: GPL-2.0 -+ -+obj-y += mt7986_rfb.o ---- /dev/null -+++ b/board/mediatek/mt7986/mt7986_rfb.c -@@ -0,0 +1,10 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Sam Shih -+ */ -+ -+int board_init(void) -+{ -+ return 0; -+} ---- /dev/null -+++ b/configs/mt7986_rfb_defconfig -@@ -0,0 +1,66 @@ -+CONFIG_ARM=y -+CONFIG_POSITION_INDEPENDENT=y -+CONFIG_ARCH_MEDIATEK=y -+CONFIG_SYS_TEXT_BASE=0x41e00000 -+CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_DEFAULT_DEVICE_TREE="mt7986a-rfb" -+CONFIG_TARGET_MT7986=y -+CONFIG_DEBUG_UART_BASE=0x11002000 -+CONFIG_DEBUG_UART_CLOCK=40000000 -+CONFIG_SYS_LOAD_ADDR=0x46000000 -+CONFIG_DEBUG_UART=y -+# CONFIG_AUTOBOOT is not set -+CONFIG_DEFAULT_FDT_FILE="mt7986a-rfb" -+CONFIG_LOGLEVEL=7 -+CONFIG_LOG=y -+CONFIG_SYS_PROMPT="MT7986> " -+CONFIG_SYS_CBSIZE=512 -+CONFIG_SYS_PBSIZE=1049 -+# CONFIG_BOOTM_NETBSD is not set -+# CONFIG_BOOTM_PLAN9 is not set -+# CONFIG_BOOTM_RTEMS is not set -+# CONFIG_BOOTM_VXWORKS is not set -+# CONFIG_CMD_ELF is not set -+# CONFIG_CMD_UNLZ4 is not set -+# CONFIG_CMD_UNZIP is not set -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_MTD=y -+CONFIG_CMD_SF_TEST=y -+CONFIG_CMD_PING=y -+CONFIG_CMD_SMC=y -+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+# CONFIG_MMC is not set -+CONFIG_MTD=y -+CONFIG_DM_MTD=y -+CONFIG_MTD_SPI_NAND=y -+CONFIG_DM_SPI_FLASH=y -+CONFIG_SPI_FLASH_SFDP_SUPPORT=y -+CONFIG_SPI_FLASH_EON=y -+CONFIG_SPI_FLASH_GIGADEVICE=y -+CONFIG_SPI_FLASH_ISSI=y -+CONFIG_SPI_FLASH_MACRONIX=y -+CONFIG_SPI_FLASH_SPANSION=y -+CONFIG_SPI_FLASH_STMICRO=y -+CONFIG_SPI_FLASH_WINBOND=y -+CONFIG_SPI_FLASH_XMC=y -+CONFIG_SPI_FLASH_XTX=y -+CONFIG_SPI_FLASH_MTD=y -+CONFIG_PHY_FIXED=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PINCTRL=y -+CONFIG_PINCONF=y -+CONFIG_PINCTRL_MT7986=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_MTK_POWER_DOMAIN=y -+CONFIG_DM_SERIAL=y -+CONFIG_MTK_SERIAL=y -+CONFIG_SPI=y -+CONFIG_DM_SPI=y -+CONFIG_MTK_SPIM=y -+CONFIG_HEXDUMP=y ---- /dev/null -+++ b/configs/mt7986a_bpir3_emmc_defconfig -@@ -0,0 +1,64 @@ -+CONFIG_ARM=y -+CONFIG_POSITION_INDEPENDENT=y -+CONFIG_ARCH_MEDIATEK=y -+CONFIG_SYS_TEXT_BASE=0x41e00000 -+CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_ENV_SIZE=0x80000 -+CONFIG_ENV_OFFSET=0x300000 -+CONFIG_DEFAULT_DEVICE_TREE="mt7986a-emmc-rfb" -+CONFIG_TARGET_MT7986=y -+CONFIG_DEBUG_UART_BASE=0x11002000 -+CONFIG_DEBUG_UART_CLOCK=40000000 -+CONFIG_SYS_LOAD_ADDR=0x46000000 -+CONFIG_DEBUG_UART=y -+# CONFIG_AUTOBOOT is not set -+CONFIG_DEFAULT_FDT_FILE="mt7986a-emmc-rfb" -+CONFIG_LOGLEVEL=7 -+CONFIG_LOG=y -+CONFIG_SYS_PROMPT="MT7986> " -+CONFIG_SYS_CBSIZE=512 -+CONFIG_SYS_PBSIZE=1049 -+# CONFIG_BOOTM_NETBSD is not set -+# CONFIG_BOOTM_PLAN9 is not set -+# CONFIG_BOOTM_RTEMS is not set -+# CONFIG_BOOTM_VXWORKS is not set -+# CONFIG_CMD_ELF is not set -+# CONFIG_CMD_UNLZ4 is not set -+# CONFIG_CMD_UNZIP is not set -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_GPT_RENAME=y -+CONFIG_CMD_LSBLK=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_PART=y -+CONFIG_CMD_READ=y -+CONFIG_CMD_PING=y -+CONFIG_CMD_SMC=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_PARTITION_TYPE_GUID=y -+CONFIG_ENV_OVERWRITE=y -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_MMC_HS200_SUPPORT=y -+CONFIG_MMC_MTK=y -+CONFIG_PHY_FIXED=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PINCTRL=y -+CONFIG_PINCONF=y -+CONFIG_PINCTRL_MT7986=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_MTK_POWER_DOMAIN=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_SERIAL=y -+CONFIG_MTK_SERIAL=y -+CONFIG_FAT_WRITE=y -+CONFIG_HEXDUMP=y -+# CONFIG_EFI_LOADER is not set ---- /dev/null -+++ b/configs/mt7986a_bpir3_sd_defconfig -@@ -0,0 +1,64 @@ -+CONFIG_ARM=y -+CONFIG_POSITION_INDEPENDENT=y -+CONFIG_ARCH_MEDIATEK=y -+CONFIG_SYS_TEXT_BASE=0x41e00000 -+CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_ENV_SIZE=0x80000 -+CONFIG_ENV_OFFSET=0x300000 -+CONFIG_DEFAULT_DEVICE_TREE="mt7986a-sd-rfb" -+CONFIG_TARGET_MT7986=y -+CONFIG_DEBUG_UART_BASE=0x11002000 -+CONFIG_DEBUG_UART_CLOCK=40000000 -+CONFIG_SYS_LOAD_ADDR=0x46000000 -+CONFIG_DEBUG_UART=y -+# CONFIG_AUTOBOOT is not set -+CONFIG_DEFAULT_FDT_FILE="mt7986a-sd-rfb" -+CONFIG_LOGLEVEL=7 -+CONFIG_LOG=y -+CONFIG_SYS_PROMPT="MT7986> " -+CONFIG_SYS_CBSIZE=512 -+CONFIG_SYS_PBSIZE=1049 -+# CONFIG_BOOTM_NETBSD is not set -+# CONFIG_BOOTM_PLAN9 is not set -+# CONFIG_BOOTM_RTEMS is not set -+# CONFIG_BOOTM_VXWORKS is not set -+# CONFIG_CMD_ELF is not set -+# CONFIG_CMD_UNLZ4 is not set -+# CONFIG_CMD_UNZIP is not set -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_GPT_RENAME=y -+CONFIG_CMD_LSBLK=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_PART=y -+CONFIG_CMD_READ=y -+CONFIG_CMD_PING=y -+CONFIG_CMD_SMC=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_PARTITION_TYPE_GUID=y -+CONFIG_ENV_OVERWRITE=y -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_MMC_HS200_SUPPORT=y -+CONFIG_MMC_MTK=y -+CONFIG_PHY_FIXED=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PINCTRL=y -+CONFIG_PINCONF=y -+CONFIG_PINCTRL_MT7986=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_MTK_POWER_DOMAIN=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_SERIAL=y -+CONFIG_MTK_SERIAL=y -+CONFIG_FAT_WRITE=y -+CONFIG_HEXDUMP=y -+# CONFIG_EFI_LOADER is not set ---- /dev/null -+++ b/include/configs/mt7986.h -@@ -0,0 +1,26 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Configuration for MediaTek MT7986 SoC -+ * -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Sam Shih -+ */ -+ -+#ifndef __MT7986_H -+#define __MT7986_H -+ -+#include -+ -+#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M -+#define CONFIG_SYS_MMC_ENV_DEV 0 -+ -+/* Uboot definition */ -+#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE -+ -+/* SPL -> Uboot */ -+#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE -+ -+/* DRAM */ -+#define CONFIG_SYS_SDRAM_BASE 0x40000000 -+ -+#endif diff --git a/package/boot/uboot-mediatek/patches/002-0004-board-mediatek-add-MT7981-reference-boards.patch b/package/boot/uboot-mediatek/patches/002-0004-board-mediatek-add-MT7981-reference-boards.patch deleted file mode 100644 index 4f07e4d4ce5..00000000000 --- a/package/boot/uboot-mediatek/patches/002-0004-board-mediatek-add-MT7981-reference-boards.patch +++ /dev/null @@ -1,779 +0,0 @@ -From 37bcf4d1acb5f7ce93fa0bd59dc313a79004ae34 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 31 Aug 2022 19:00:25 +0800 -Subject: [PATCH 04/32] board: mediatek: add MT7981 reference boards - -This patch adds general board files based on MT7981 SoCs. - -MT7981 uses one mmc controller for booting from both SD and eMMC, and the -pins of mmc controller are also shared with spi controller. -So three configs are need for these boot types: - -1. mt7981_rfb_defconfig - SPI-NOR and SPI-NAND -2. mt7981_emmc_rfb_defconfig - eMMC only -3. mt7981_sd_rfb_defconfig - SD only - -Signed-off-by: Weijie Gao ---- - arch/arm/dts/Makefile | 3 + - arch/arm/dts/mt7981-emmc-rfb.dts | 139 +++++++++++++++++++++++ - arch/arm/dts/mt7981-rfb.dts | 173 +++++++++++++++++++++++++++++ - arch/arm/dts/mt7981-sd-rfb.dts | 139 +++++++++++++++++++++++ - board/mediatek/mt7981/MAINTAINERS | 10 ++ - board/mediatek/mt7981/Makefile | 3 + - board/mediatek/mt7981/mt7981_rfb.c | 10 ++ - configs/mt7981_emmc_rfb_defconfig | 64 +++++++++++ - configs/mt7981_rfb_defconfig | 69 ++++++++++++ - configs/mt7981_sd_rfb_defconfig | 64 +++++++++++ - include/configs/mt7981.h | 26 +++++ - 11 files changed, 700 insertions(+) - create mode 100644 arch/arm/dts/mt7981-emmc-rfb.dts - create mode 100644 arch/arm/dts/mt7981-rfb.dts - create mode 100644 arch/arm/dts/mt7981-sd-rfb.dts - create mode 100644 board/mediatek/mt7981/MAINTAINERS - create mode 100644 board/mediatek/mt7981/Makefile - create mode 100644 board/mediatek/mt7981/mt7981_rfb.c - create mode 100644 configs/mt7981_emmc_rfb_defconfig - create mode 100644 configs/mt7981_rfb_defconfig - create mode 100644 configs/mt7981_sd_rfb_defconfig - create mode 100644 include/configs/mt7981.h - ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -1233,6 +1233,9 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ - mt7622-bananapi-bpi-r64.dtb \ - mt7623n-bananapi-bpi-r2.dtb \ - mt7629-rfb.dtb \ -+ mt7981-rfb.dtb \ -+ mt7981-emmc-rfb.dtb \ -+ mt7981-sd-rfb.dtb \ - mt7986a-rfb.dtb \ - mt7986b-rfb.dtb \ - mt7986a-sd-rfb.dtb \ ---- /dev/null -+++ b/arch/arm/dts/mt7981-emmc-rfb.dts -@@ -0,0 +1,139 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2022 MediaTek Inc. -+ * Author: Sam Shih -+ */ -+ -+/dts-v1/; -+#include "mt7981.dtsi" -+#include -+ -+/ { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ model = "mt7981-rfb"; -+ compatible = "mediatek,mt7981", "mediatek,mt7981-rfb"; -+ chosen { -+ stdout-path = &uart0; -+ tick-timer = &timer0; -+ }; -+ -+ reg_3p3v: regulator-3p3v { -+ compatible = "regulator-fixed"; -+ regulator-name = "fixed-3.3V"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>; -+ status = "disabled"; -+}; -+ -+ð { -+ status = "okay"; -+ mediatek,gmac-id = <0>; -+ phy-mode = "sgmii"; -+ mediatek,switch = "mt7531"; -+ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; -+ -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+}; -+ -+&pinctrl { -+ spic_pins: spi1-pins-func-1 { -+ mux { -+ function = "spi"; -+ groups = "spi1_1"; -+ }; -+ }; -+ -+ uart1_pins: spi1-pins-func-3 { -+ mux { -+ function = "uart"; -+ groups = "uart1_2"; -+ }; -+ }; -+ -+ /* pin15 as pwm0 */ -+ one_pwm_pins: one-pwm-pins { -+ mux { -+ function = "pwm"; -+ groups = "pwm0_1"; -+ }; -+ }; -+ -+ /* pin15 as pwm0 and pin14 as pwm1 */ -+ two_pwm_pins: two-pwm-pins { -+ mux { -+ function = "pwm"; -+ groups = "pwm0_1", "pwm1_0"; -+ }; -+ }; -+ -+ /* pin15 as pwm0, pin14 as pwm1, pin7 as pwm2 */ -+ three_pwm_pins: three-pwm-pins { -+ mux { -+ function = "pwm"; -+ groups = "pwm0_1", "pwm1_0", "pwm2"; -+ }; -+ }; -+ -+ mmc0_pins_default: mmc0default { -+ mux { -+ function = "flash"; -+ groups = "emmc_45"; -+ }; -+ conf-cmd-dat { -+ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", -+ "SPI0_CS", "SPI0_HOLD", "SPI0_WP", -+ "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO"; -+ input-enable; -+ drive-strength = ; -+ bias-pull-up = ; -+ }; -+ conf-clk { -+ pins = "SPI1_CS"; -+ drive-strength = ; -+ bias-pull-down = ; -+ }; -+ conf-rst { -+ pins = "PWM0"; -+ drive-strength = ; -+ bias-pull-up = ; -+ }; -+ }; -+}; -+ -+&pwm { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&two_pwm_pins>; -+ status = "okay"; -+}; -+ -+&watchdog { -+ status = "disabled"; -+}; -+ -+&mmc0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc0_pins_default>; -+ bus-width = <8>; -+ max-frequency = <52000000>; -+ cap-mmc-highspeed; -+ cap-mmc-hw-reset; -+ vmmc-supply = <®_3p3v>; -+ non-removable; -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/dts/mt7981-rfb.dts -@@ -0,0 +1,173 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2022 MediaTek Inc. -+ * Author: Sam Shih -+ */ -+ -+/dts-v1/; -+#include "mt7981.dtsi" -+#include -+ -+/ { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ model = "mt7981-rfb"; -+ compatible = "mediatek,mt7981", "mediatek,mt7981-rfb"; -+ chosen { -+ stdout-path = &uart0; -+ tick-timer = &timer0; -+ }; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>; -+ status = "disabled"; -+}; -+ -+ð { -+ status = "okay"; -+ mediatek,gmac-id = <0>; -+ phy-mode = "sgmii"; -+ mediatek,switch = "mt7531"; -+ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; -+ -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+}; -+ -+&pinctrl { -+ spi_flash_pins: spi0-pins-func-1 { -+ mux { -+ function = "flash"; -+ groups = "spi0", "spi0_wp_hold"; -+ }; -+ -+ conf-pu { -+ pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; -+ drive-strength = ; -+ bias-pull-up = ; -+ }; -+ -+ conf-pd { -+ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; -+ drive-strength = ; -+ bias-pull-down = ; -+ }; -+ }; -+ -+ spi2_flash_pins: spi2-spi2-pins { -+ mux { -+ function = "spi"; -+ groups = "spi2", "spi2_wp_hold"; -+ }; -+ -+ conf-pu { -+ pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; -+ drive-strength = ; -+ bias-pull-down = ; -+ }; -+ -+ conf-pd { -+ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; -+ drive-strength = ; -+ bias-pull-down = ; -+ }; -+ }; -+ -+ spic_pins: spi1-pins-func-1 { -+ mux { -+ function = "spi"; -+ groups = "spi1_1"; -+ }; -+ }; -+ -+ uart1_pins: spi1-pins-func-3 { -+ mux { -+ function = "uart"; -+ groups = "uart1_2"; -+ }; -+ }; -+ -+ /* pin15 as pwm0 */ -+ one_pwm_pins: one-pwm-pins { -+ mux { -+ function = "pwm"; -+ groups = "pwm0_1"; -+ }; -+ }; -+ -+ /* pin15 as pwm0 and pin14 as pwm1 */ -+ two_pwm_pins: two-pwm-pins { -+ mux { -+ function = "pwm"; -+ groups = "pwm0_1", "pwm1_0"; -+ }; -+ }; -+ -+ /* pin15 as pwm0, pin14 as pwm1, pin7 as pwm2 */ -+ three_pwm_pins: three-pwm-pins { -+ mux { -+ function = "pwm"; -+ groups = "pwm0_1", "pwm1_0", "pwm2"; -+ }; -+ }; -+}; -+ -+&spi0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi_flash_pins>; -+ status = "okay"; -+ must_tx; -+ enhance_timing; -+ dma_ext; -+ ipm_design; -+ support_quad; -+ tick_dly = <2>; -+ sample_sel = <0>; -+ -+ spi_nand@0 { -+ compatible = "spi-nand"; -+ reg = <0>; -+ spi-max-frequency = <52000000>; -+ }; -+}; -+ -+&spi2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi2_flash_pins>; -+ status = "okay"; -+ must_tx; -+ enhance_timing; -+ dma_ext; -+ ipm_design; -+ support_quad; -+ tick_dly = <2>; -+ sample_sel = <0>; -+ -+ spi_nor@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <52000000>; -+ }; -+}; -+ -+&pwm { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&two_pwm_pins>; -+ status = "okay"; -+}; -+ -+&watchdog { -+ status = "disabled"; -+}; ---- /dev/null -+++ b/arch/arm/dts/mt7981-sd-rfb.dts -@@ -0,0 +1,139 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2022 MediaTek Inc. -+ * Author: Sam Shih -+ */ -+ -+/dts-v1/; -+#include "mt7981.dtsi" -+#include -+ -+/ { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ model = "mt7981-rfb"; -+ compatible = "mediatek,mt7981", "mediatek,mt7981-sd-rfb"; -+ chosen { -+ stdout-path = &uart0; -+ tick-timer = &timer0; -+ }; -+ -+ reg_3p3v: regulator-3p3v { -+ compatible = "regulator-fixed"; -+ regulator-name = "fixed-3.3V"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>; -+ status = "disabled"; -+}; -+ -+ð { -+ status = "okay"; -+ mediatek,gmac-id = <0>; -+ phy-mode = "sgmii"; -+ mediatek,switch = "mt7531"; -+ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; -+ -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+}; -+ -+&pinctrl { -+ spic_pins: spi1-pins-func-1 { -+ mux { -+ function = "spi"; -+ groups = "spi1_1"; -+ }; -+ }; -+ -+ uart1_pins: spi1-pins-func-3 { -+ mux { -+ function = "uart"; -+ groups = "uart1_2"; -+ }; -+ }; -+ -+ /* pin15 as pwm0 */ -+ one_pwm_pins: one-pwm-pins { -+ mux { -+ function = "pwm"; -+ groups = "pwm0_1"; -+ }; -+ }; -+ -+ /* pin15 as pwm0 and pin14 as pwm1 */ -+ two_pwm_pins: two-pwm-pins { -+ mux { -+ function = "pwm"; -+ groups = "pwm0_1", "pwm1_0"; -+ }; -+ }; -+ -+ /* pin15 as pwm0, pin14 as pwm1, pin7 as pwm2 */ -+ three_pwm_pins: three-pwm-pins { -+ mux { -+ function = "pwm"; -+ groups = "pwm0_1", "pwm1_0", "pwm2"; -+ }; -+ }; -+ -+ mmc0_pins_default: mmc0default { -+ mux { -+ function = "flash"; -+ groups = "emmc_45"; -+ }; -+ conf-cmd-dat { -+ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", -+ "SPI0_CS", "SPI0_HOLD", "SPI0_WP", -+ "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO"; -+ input-enable; -+ drive-strength = ; -+ bias-pull-up = ; -+ }; -+ conf-clk { -+ pins = "SPI1_CS"; -+ drive-strength = ; -+ bias-pull-down = ; -+ }; -+ conf-rst { -+ pins = "PWM0"; -+ drive-strength = ; -+ bias-pull-up = ; -+ }; -+ }; -+}; -+ -+&pwm { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&two_pwm_pins>; -+ status = "okay"; -+}; -+ -+&watchdog { -+ status = "disabled"; -+}; -+ -+&mmc0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc0_pins_default>; -+ bus-width = <4>; -+ max-frequency = <52000000>; -+ cap-sd-highspeed; -+ r_smpl = <0>; -+ vmmc-supply = <®_3p3v>; -+ vqmmc-supply = <®_3p3v>; -+ status = "okay"; -+}; ---- /dev/null -+++ b/board/mediatek/mt7981/MAINTAINERS -@@ -0,0 +1,10 @@ -+MT7981 -+M: Sam Shih -+S: Maintained -+F: board/mediatek/mt7981 -+F: include/configs/mt7981.h -+F: configs/mt7981_emmc_rfb_defconfig -+F: configs/mt7981_rfb_defconfig -+F: configs/mt7981_sd_rfb_defconfig -+F: configs/mt7981_spim_nand_rfb_defconfig -+F: configs/mt7981_spim_nor_rfb_defconfig ---- /dev/null -+++ b/board/mediatek/mt7981/Makefile -@@ -0,0 +1,3 @@ -+# SPDX-License-Identifier: GPL-2.0 -+ -+obj-y += mt7981_rfb.o ---- /dev/null -+++ b/board/mediatek/mt7981/mt7981_rfb.c -@@ -0,0 +1,10 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Sam Shih -+ */ -+ -+int board_init(void) -+{ -+ return 0; -+} ---- /dev/null -+++ b/configs/mt7981_emmc_rfb_defconfig -@@ -0,0 +1,64 @@ -+CONFIG_ARM=y -+CONFIG_POSITION_INDEPENDENT=y -+CONFIG_ARCH_MEDIATEK=y -+CONFIG_SYS_TEXT_BASE=0x41e00000 -+CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_ENV_SIZE=0x80000 -+CONFIG_ENV_OFFSET=0x300000 -+CONFIG_DEFAULT_DEVICE_TREE="mt7981-emmc-rfb" -+CONFIG_TARGET_MT7981=y -+CONFIG_DEBUG_UART_BASE=0x11002000 -+CONFIG_DEBUG_UART_CLOCK=40000000 -+CONFIG_SYS_LOAD_ADDR=0x46000000 -+CONFIG_DEBUG_UART=y -+# CONFIG_AUTOBOOT is not set -+CONFIG_DEFAULT_FDT_FILE="mt7981-emmc-rfb" -+CONFIG_LOGLEVEL=7 -+CONFIG_LOG=y -+CONFIG_SYS_PROMPT="MT7981> " -+CONFIG_SYS_CBSIZE=512 -+CONFIG_SYS_PBSIZE=1049 -+# CONFIG_BOOTM_NETBSD is not set -+# CONFIG_BOOTM_PLAN9 is not set -+# CONFIG_BOOTM_RTEMS is not set -+# CONFIG_BOOTM_VXWORKS is not set -+# CONFIG_CMD_ELF is not set -+# CONFIG_CMD_UNLZ4 is not set -+# CONFIG_CMD_UNZIP is not set -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_GPT_RENAME=y -+CONFIG_CMD_LSBLK=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_PART=y -+CONFIG_CMD_READ=y -+CONFIG_CMD_PING=y -+CONFIG_CMD_SMC=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_PARTITION_TYPE_GUID=y -+CONFIG_ENV_OVERWRITE=y -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_MMC_HS200_SUPPORT=y -+CONFIG_MMC_MTK=y -+CONFIG_PHY_FIXED=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PINCTRL=y -+CONFIG_PINCONF=y -+CONFIG_PINCTRL_MT7981=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_MTK_POWER_DOMAIN=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_SERIAL=y -+CONFIG_MTK_SERIAL=y -+CONFIG_FAT_WRITE=y -+CONFIG_HEXDUMP=y -+# CONFIG_EFI_LOADER is not set ---- /dev/null -+++ b/configs/mt7981_rfb_defconfig -@@ -0,0 +1,69 @@ -+CONFIG_ARM=y -+CONFIG_POSITION_INDEPENDENT=y -+CONFIG_ARCH_MEDIATEK=y -+CONFIG_SYS_TEXT_BASE=0x41e00000 -+CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_DEFAULT_DEVICE_TREE="mt7981-rfb" -+CONFIG_TARGET_MT7981=y -+CONFIG_DEBUG_UART_BASE=0x11002000 -+CONFIG_DEBUG_UART_CLOCK=40000000 -+CONFIG_SYS_LOAD_ADDR=0x46000000 -+CONFIG_DEBUG_UART=y -+# CONFIG_AUTOBOOT is not set -+CONFIG_DEFAULT_FDT_FILE="mt7981-rfb" -+CONFIG_LOGLEVEL=7 -+CONFIG_LOG=y -+CONFIG_SYS_PROMPT="MT7981> " -+CONFIG_SYS_CBSIZE=512 -+CONFIG_SYS_PBSIZE=1049 -+# CONFIG_BOOTM_NETBSD is not set -+# CONFIG_BOOTM_PLAN9 is not set -+# CONFIG_BOOTM_RTEMS is not set -+# CONFIG_BOOTM_VXWORKS is not set -+# CONFIG_CMD_ELF is not set -+# CONFIG_CMD_UNLZ4 is not set -+# CONFIG_CMD_UNZIP is not set -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_MTD=y -+CONFIG_CMD_SF_TEST=y -+CONFIG_CMD_PING=y -+CONFIG_CMD_SMC=y -+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_BLK=y -+CONFIG_HAVE_BLOCK_DEVICE=y -+CONFIG_CLK=y -+# CONFIG_MMC is not set -+CONFIG_MTD=y -+CONFIG_DM_MTD=y -+CONFIG_MTD_SPI_NAND=y -+CONFIG_DM_SPI_FLASH=y -+CONFIG_SPI_FLASH_SFDP_SUPPORT=y -+CONFIG_SPI_FLASH_EON=y -+CONFIG_SPI_FLASH_GIGADEVICE=y -+CONFIG_SPI_FLASH_ISSI=y -+CONFIG_SPI_FLASH_MACRONIX=y -+CONFIG_SPI_FLASH_SPANSION=y -+CONFIG_SPI_FLASH_STMICRO=y -+CONFIG_SPI_FLASH_WINBOND=y -+CONFIG_SPI_FLASH_XMC=y -+CONFIG_SPI_FLASH_XTX=y -+CONFIG_SPI_FLASH_MTD=y -+CONFIG_PHY_FIXED=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PINCTRL=y -+CONFIG_PINCONF=y -+CONFIG_PINCTRL_MT7981=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_MTK_POWER_DOMAIN=y -+CONFIG_DM_SERIAL=y -+CONFIG_MTK_SERIAL=y -+CONFIG_SPI=y -+CONFIG_DM_SPI=y -+CONFIG_MTK_SPIM=y -+CONFIG_HEXDUMP=y -+# CONFIG_EFI_LOADER is not set ---- /dev/null -+++ b/configs/mt7981_sd_rfb_defconfig -@@ -0,0 +1,64 @@ -+CONFIG_ARM=y -+CONFIG_POSITION_INDEPENDENT=y -+CONFIG_ARCH_MEDIATEK=y -+CONFIG_SYS_TEXT_BASE=0x41e00000 -+CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_ENV_SIZE=0x80000 -+CONFIG_ENV_OFFSET=0x300000 -+CONFIG_DEFAULT_DEVICE_TREE="mt7981-sd-rfb" -+CONFIG_TARGET_MT7981=y -+CONFIG_DEBUG_UART_BASE=0x11002000 -+CONFIG_DEBUG_UART_CLOCK=40000000 -+CONFIG_SYS_LOAD_ADDR=0x46000000 -+CONFIG_DEBUG_UART=y -+# CONFIG_AUTOBOOT is not set -+CONFIG_DEFAULT_FDT_FILE="mt7981-sd-rfb" -+CONFIG_LOGLEVEL=7 -+CONFIG_LOG=y -+CONFIG_SYS_PROMPT="MT7981> " -+CONFIG_SYS_CBSIZE=512 -+CONFIG_SYS_PBSIZE=1049 -+# CONFIG_BOOTM_NETBSD is not set -+# CONFIG_BOOTM_PLAN9 is not set -+# CONFIG_BOOTM_RTEMS is not set -+# CONFIG_BOOTM_VXWORKS is not set -+# CONFIG_CMD_ELF is not set -+# CONFIG_CMD_UNLZ4 is not set -+# CONFIG_CMD_UNZIP is not set -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_GPT_RENAME=y -+CONFIG_CMD_LSBLK=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_PART=y -+CONFIG_CMD_READ=y -+CONFIG_CMD_PING=y -+CONFIG_CMD_SMC=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_PARTITION_TYPE_GUID=y -+CONFIG_ENV_OVERWRITE=y -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_MMC_HS200_SUPPORT=y -+CONFIG_MMC_MTK=y -+CONFIG_PHY_FIXED=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PINCTRL=y -+CONFIG_PINCONF=y -+CONFIG_PINCTRL_MT7981=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_MTK_POWER_DOMAIN=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_SERIAL=y -+CONFIG_MTK_SERIAL=y -+CONFIG_FAT_WRITE=y -+CONFIG_HEXDUMP=y -+# CONFIG_EFI_LOADER is not set ---- /dev/null -+++ b/include/configs/mt7981.h -@@ -0,0 +1,26 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Configuration for MediaTek MT7981 SoC -+ * -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Sam Shih -+ */ -+ -+#ifndef __MT7981_H -+#define __MT7981_H -+ -+#include -+ -+#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M -+#define CONFIG_SYS_MMC_ENV_DEV 0 -+ -+/* Uboot definition */ -+#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE -+ -+/* SPL -> Uboot */ -+#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE -+ -+/* DRAM */ -+#define CONFIG_SYS_SDRAM_BASE 0x40000000 -+ -+#endif diff --git a/package/boot/uboot-mediatek/patches/002-0005-mmc-mediatek-add-support-for-MediaTek-MT7891-MT7986-.patch b/package/boot/uboot-mediatek/patches/002-0005-mmc-mediatek-add-support-for-MediaTek-MT7891-MT7986-.patch deleted file mode 100644 index aa9adf40ffe..00000000000 --- a/package/boot/uboot-mediatek/patches/002-0005-mmc-mediatek-add-support-for-MediaTek-MT7891-MT7986-.patch +++ /dev/null @@ -1,132 +0,0 @@ -From 9a10182f21cc4007f46284d5c64c49dc892336be Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 31 Aug 2022 19:04:12 +0800 -Subject: [PATCH 05/32] mmc: mediatek: add support for MediaTek MT7891/MT7986 - SoCs - -Add eMMC and SDXC support for MediaTek MT7981/MT7986 SoCs -Both chips support SDXC and eMMC 4.5. MT7986A supports eMMC 5.1. - -Reviewed-by: Jaehoon Chung -Reviewed-by: Simon Glass -Signed-off-by: Weijie Gao ---- - drivers/mmc/mtk-sd.c | 68 ++++++++++++++++++++++++++++++++++---------- - 1 file changed, 53 insertions(+), 15 deletions(-) - ---- a/drivers/mmc/mtk-sd.c -+++ b/drivers/mmc/mtk-sd.c -@@ -1496,7 +1496,12 @@ static void msdc_init_hw(struct msdc_hos - /* Enable data & cmd interrupts */ - writel(DATA_INTS_MASK | CMD_INTS_MASK, &host->base->msdc_inten); - -- writel(0, tune_reg); -+ if (host->top_base) { -+ writel(0, &host->top_base->emmc_top_control); -+ writel(0, &host->top_base->emmc_top_cmd); -+ } else { -+ writel(0, tune_reg); -+ } - writel(0, &host->base->msdc_iocon); - - if (host->r_smpl) -@@ -1507,9 +1512,14 @@ static void msdc_init_hw(struct msdc_hos - writel(0x403c0046, &host->base->patch_bit0); - writel(0xffff4089, &host->base->patch_bit1); - -- if (host->dev_comp->stop_clk_fix) -+ if (host->dev_comp->stop_clk_fix) { - clrsetbits_le32(&host->base->patch_bit1, MSDC_PB1_STOP_DLY_M, - 3 << MSDC_PB1_STOP_DLY_S); -+ clrbits_le32(&host->base->sdc_fifo_cfg, -+ SDC_FIFO_CFG_WRVALIDSEL); -+ clrbits_le32(&host->base->sdc_fifo_cfg, -+ SDC_FIFO_CFG_RDVALIDSEL); -+ } - - if (host->dev_comp->busy_check) - clrbits_le32(&host->base->patch_bit1, (1 << 7)); -@@ -1544,15 +1554,28 @@ static void msdc_init_hw(struct msdc_hos - } - - if (host->dev_comp->data_tune) { -- setbits_le32(tune_reg, -- MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL); -- clrsetbits_le32(&host->base->patch_bit0, -- MSDC_INT_DAT_LATCH_CK_SEL_M, -- host->latch_ck << -- MSDC_INT_DAT_LATCH_CK_SEL_S); -+ if (host->top_base) { -+ setbits_le32(&host->top_base->emmc_top_control, -+ PAD_DAT_RD_RXDLY_SEL); -+ clrbits_le32(&host->top_base->emmc_top_control, -+ DATA_K_VALUE_SEL); -+ setbits_le32(&host->top_base->emmc_top_cmd, -+ PAD_CMD_RD_RXDLY_SEL); -+ } else { -+ setbits_le32(tune_reg, -+ MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL); -+ clrsetbits_le32(&host->base->patch_bit0, -+ MSDC_INT_DAT_LATCH_CK_SEL_M, -+ host->latch_ck << -+ MSDC_INT_DAT_LATCH_CK_SEL_S); -+ } - } else { - /* choose clock tune */ -- setbits_le32(tune_reg, MSDC_PAD_TUNE_RXDLYSEL); -+ if (host->top_base) -+ setbits_le32(&host->top_base->emmc_top_control, -+ PAD_RXDLY_SEL); -+ else -+ setbits_le32(tune_reg, MSDC_PAD_TUNE_RXDLYSEL); - } - - if (host->dev_comp->builtin_pad_ctrl) { -@@ -1604,12 +1627,6 @@ static void msdc_init_hw(struct msdc_hos - clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M, - 3 << SDC_CFG_DTOC_S); - -- if (host->dev_comp->stop_clk_fix) { -- clrbits_le32(&host->base->sdc_fifo_cfg, -- SDC_FIFO_CFG_WRVALIDSEL); -- clrbits_le32(&host->base->sdc_fifo_cfg, -- SDC_FIFO_CFG_RDVALIDSEL); -- } - - host->def_tune_para.iocon = readl(&host->base->msdc_iocon); - host->def_tune_para.pad_tune = readl(&host->base->pad_tune); -@@ -1792,6 +1809,25 @@ static const struct msdc_compatible mt76 - .enhance_rx = false - }; - -+static const struct msdc_compatible mt7986_compat = { -+ .clk_div_bits = 12, -+ .pad_tune0 = true, -+ .async_fifo = true, -+ .data_tune = true, -+ .busy_check = true, -+ .stop_clk_fix = true, -+ .enhance_rx = true, -+}; -+ -+static const struct msdc_compatible mt7981_compat = { -+ .clk_div_bits = 12, -+ .pad_tune0 = true, -+ .async_fifo = true, -+ .data_tune = true, -+ .busy_check = true, -+ .stop_clk_fix = true, -+}; -+ - static const struct msdc_compatible mt8512_compat = { - .clk_div_bits = 12, - .pad_tune0 = true, -@@ -1824,6 +1860,8 @@ static const struct udevice_id msdc_ids[ - { .compatible = "mediatek,mt7621-mmc", .data = (ulong)&mt7621_compat }, - { .compatible = "mediatek,mt7622-mmc", .data = (ulong)&mt7622_compat }, - { .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat }, -+ { .compatible = "mediatek,mt7986-mmc", .data = (ulong)&mt7986_compat }, -+ { .compatible = "mediatek,mt7981-mmc", .data = (ulong)&mt7981_compat }, - { .compatible = "mediatek,mt8512-mmc", .data = (ulong)&mt8512_compat }, - { .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat }, - { .compatible = "mediatek,mt8183-mmc", .data = (ulong)&mt8183_compat }, diff --git a/package/boot/uboot-mediatek/patches/002-0006-net-mediatek-use-a-struct-to-cover-variations-of-all.patch b/package/boot/uboot-mediatek/patches/002-0006-net-mediatek-use-a-struct-to-cover-variations-of-all.patch deleted file mode 100644 index 08cad1bb530..00000000000 --- a/package/boot/uboot-mediatek/patches/002-0006-net-mediatek-use-a-struct-to-cover-variations-of-all.patch +++ /dev/null @@ -1,163 +0,0 @@ -From ba6af13fd58c0ec418720d959152e0db47e91b02 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 31 Aug 2022 19:04:19 +0800 -Subject: [PATCH 06/32] net: mediatek: use a struct to cover variations of all - SoCs - -Using a single soc id to control different initialization and TX/RX flow -for all SoCs is not extensible if more hardware variations are added in -the future. - -This patch introduces a struct to replace the original mtk_soc to allow -the driver be able handle newer hardwares. - -Reviewed-by: Simon Glass -Signed-off-by: Weijie Gao ---- - drivers/net/mtk_eth.c | 56 ++++++++++++++++++++++++++++++------------- - drivers/net/mtk_eth.h | 25 ++++++++++++++++++- - 2 files changed, 64 insertions(+), 17 deletions(-) - ---- a/drivers/net/mtk_eth.c -+++ b/drivers/net/mtk_eth.c -@@ -142,11 +142,15 @@ enum mtk_switch { - SW_MT7531 - }; - --enum mtk_soc { -- SOC_MT7623, -- SOC_MT7629, -- SOC_MT7622, -- SOC_MT7621 -+/* struct mtk_soc_data - This is the structure holding all differences -+ * among various plaforms -+ * @caps Flags shown the extra capability for the SoC -+ * @ana_rgc3: The offset for register ANA_RGC3 related to -+ * sgmiisys syscon -+ */ -+struct mtk_soc_data { -+ u32 caps; -+ u32 ana_rgc3; - }; - - struct mtk_eth_priv { -@@ -171,7 +175,7 @@ struct mtk_eth_priv { - int (*mmd_write)(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg, - u16 val); - -- enum mtk_soc soc; -+ const struct mtk_soc_data *soc; - int gmac_id; - int force_mode; - int speed; -@@ -679,7 +683,7 @@ static int mt7530_setup(struct mtk_eth_p - u32 val, txdrv; - int i; - -- if (priv->soc != SOC_MT7621) { -+ if (!MTK_HAS_CAPS(priv->soc->caps, MTK_TRGMII_MT7621_CLK)) { - /* Select 250MHz clk for RGMII mode */ - mtk_ethsys_rmw(priv, ETHSYS_CLKCFG0_REG, - ETHSYS_TRGMII_CLK_SEL362_5, 0); -@@ -1108,9 +1112,8 @@ static int mtk_phy_probe(struct udevice - static void mtk_sgmii_init(struct mtk_eth_priv *priv) - { - /* Set SGMII GEN2 speed(2.5G) */ -- clrsetbits_le32(priv->sgmii_base + ((priv->soc == SOC_MT7622) ? -- SGMSYS_GEN2_SPEED : SGMSYS_GEN2_SPEED_V2), -- SGMSYS_SPEED_2500, SGMSYS_SPEED_2500); -+ setbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, -+ SGMSYS_SPEED_2500); - - /* Disable SGMII AN */ - clrsetbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1, -@@ -1182,7 +1185,8 @@ static void mtk_mac_init(struct mtk_eth_ - mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), mcr); - } - -- if (priv->soc == SOC_MT7623) { -+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_GMAC1_TRGMII) && -+ !MTK_HAS_CAPS(priv->soc->caps, MTK_TRGMII_MT7621_CLK)) { - /* Lower Tx Driving for TRGMII path */ - for (i = 0 ; i < NUM_TRGMII_CTRL; i++) - mtk_gmac_write(priv, GMAC_TRGMII_TD_ODT(i), -@@ -1431,7 +1435,11 @@ static int mtk_eth_of_to_plat(struct ude - ofnode subnode; - int ret; - -- priv->soc = dev_get_driver_data(dev); -+ priv->soc = (const struct mtk_soc_data *)dev_get_driver_data(dev); -+ if (!priv->soc) { -+ dev_err(dev, "missing soc compatible data\n"); -+ return -EINVAL; -+ } - - pdata->iobase = (phys_addr_t)dev_remap_addr(dev); - -@@ -1544,11 +1552,27 @@ static int mtk_eth_of_to_plat(struct ude - return 0; - } - -+static const struct mtk_soc_data mt7629_data = { -+ .ana_rgc3 = 0x128, -+}; -+ -+static const struct mtk_soc_data mt7623_data = { -+ .caps = MT7623_CAPS, -+}; -+ -+static const struct mtk_soc_data mt7622_data = { -+ .ana_rgc3 = 0x2028, -+}; -+ -+static const struct mtk_soc_data mt7621_data = { -+ .caps = MT7621_CAPS, -+}; -+ - static const struct udevice_id mtk_eth_ids[] = { -- { .compatible = "mediatek,mt7629-eth", .data = SOC_MT7629 }, -- { .compatible = "mediatek,mt7623-eth", .data = SOC_MT7623 }, -- { .compatible = "mediatek,mt7622-eth", .data = SOC_MT7622 }, -- { .compatible = "mediatek,mt7621-eth", .data = SOC_MT7621 }, -+ { .compatible = "mediatek,mt7629-eth", .data = (ulong)&mt7629_data }, -+ { .compatible = "mediatek,mt7623-eth", .data = (ulong)&mt7623_data }, -+ { .compatible = "mediatek,mt7622-eth", .data = (ulong)&mt7622_data }, -+ { .compatible = "mediatek,mt7621-eth", .data = (ulong)&mt7621_data }, - {} - }; - ---- a/drivers/net/mtk_eth.h -+++ b/drivers/net/mtk_eth.h -@@ -9,8 +9,31 @@ - #ifndef _MTK_ETH_H_ - #define _MTK_ETH_H_ - --/* Frame Engine Register Bases */ - #include -+ -+enum mkt_eth_capabilities { -+ MTK_TRGMII_BIT, -+ MTK_TRGMII_MT7621_CLK_BIT, -+ -+ /* PATH BITS */ -+ MTK_ETH_PATH_GMAC1_TRGMII_BIT, -+}; -+ -+#define MTK_TRGMII BIT(MTK_TRGMII_BIT) -+#define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) -+ -+/* Supported path present on SoCs */ -+#define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) -+ -+#define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) -+ -+#define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) -+ -+#define MT7621_CAPS (MTK_GMAC1_TRGMII | MTK_TRGMII_MT7621_CLK) -+ -+#define MT7623_CAPS (MTK_GMAC1_TRGMII) -+ -+/* Frame Engine Register Bases */ - #define PDMA_BASE 0x0800 - #define GDMA1_BASE 0x0500 - #define GDMA2_BASE 0x1500 diff --git a/package/boot/uboot-mediatek/patches/002-0007-net-mediatek-stop-using-bitfileds-for-DMA-descriptor.patch b/package/boot/uboot-mediatek/patches/002-0007-net-mediatek-stop-using-bitfileds-for-DMA-descriptor.patch deleted file mode 100644 index 41f5ce63354..00000000000 --- a/package/boot/uboot-mediatek/patches/002-0007-net-mediatek-stop-using-bitfileds-for-DMA-descriptor.patch +++ /dev/null @@ -1,317 +0,0 @@ -From 5f6f3600a334398e27802de33a6a8726aacbe88c Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 31 Aug 2022 19:04:23 +0800 -Subject: [PATCH 07/32] net: mediatek: stop using bitfileds for DMA descriptors - -This patch is a preparation for adding a new version of PDMA of which the -DMA descriptor fields has changed. Using bitfields will result in a complex -modification. Convert bitfields to u32 units can solve this problem easily. - -Reviewed-by: Simon Glass -Signed-off-by: Weijie Gao ---- - drivers/net/mtk_eth.c | 144 ++++++++++++++---------------------------- - drivers/net/mtk_eth.h | 32 ++++++++++ - 2 files changed, 80 insertions(+), 96 deletions(-) - ---- a/drivers/net/mtk_eth.c -+++ b/drivers/net/mtk_eth.c -@@ -65,77 +65,6 @@ - (DP_DISCARD << MC_DP_S) | \ - (DP_DISCARD << UN_DP_S)) - --struct pdma_rxd_info1 { -- u32 PDP0; --}; -- --struct pdma_rxd_info2 { -- u32 PLEN1 : 14; -- u32 LS1 : 1; -- u32 UN_USED : 1; -- u32 PLEN0 : 14; -- u32 LS0 : 1; -- u32 DDONE : 1; --}; -- --struct pdma_rxd_info3 { -- u32 PDP1; --}; -- --struct pdma_rxd_info4 { -- u32 FOE_ENTRY : 14; -- u32 CRSN : 5; -- u32 SP : 3; -- u32 L4F : 1; -- u32 L4VLD : 1; -- u32 TACK : 1; -- u32 IP4F : 1; -- u32 IP4 : 1; -- u32 IP6 : 1; -- u32 UN_USED : 4; --}; -- --struct pdma_rxdesc { -- struct pdma_rxd_info1 rxd_info1; -- struct pdma_rxd_info2 rxd_info2; -- struct pdma_rxd_info3 rxd_info3; -- struct pdma_rxd_info4 rxd_info4; --}; -- --struct pdma_txd_info1 { -- u32 SDP0; --}; -- --struct pdma_txd_info2 { -- u32 SDL1 : 14; -- u32 LS1 : 1; -- u32 BURST : 1; -- u32 SDL0 : 14; -- u32 LS0 : 1; -- u32 DDONE : 1; --}; -- --struct pdma_txd_info3 { -- u32 SDP1; --}; -- --struct pdma_txd_info4 { -- u32 VLAN_TAG : 16; -- u32 INS : 1; -- u32 RESV : 2; -- u32 UDF : 6; -- u32 FPORT : 3; -- u32 TSO : 1; -- u32 TUI_CO : 3; --}; -- --struct pdma_txdesc { -- struct pdma_txd_info1 txd_info1; -- struct pdma_txd_info2 txd_info2; -- struct pdma_txd_info3 txd_info3; -- struct pdma_txd_info4 txd_info4; --}; -- - enum mtk_switch { - SW_NONE, - SW_MT7530, -@@ -151,13 +80,15 @@ enum mtk_switch { - struct mtk_soc_data { - u32 caps; - u32 ana_rgc3; -+ u32 txd_size; -+ u32 rxd_size; - }; - - struct mtk_eth_priv { - char pkt_pool[TOTAL_PKT_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN); - -- struct pdma_txdesc *tx_ring_noc; -- struct pdma_rxdesc *rx_ring_noc; -+ void *tx_ring_noc; -+ void *rx_ring_noc; - - int rx_dma_owner_idx0; - int tx_cpu_owner_idx0; -@@ -1202,14 +1133,16 @@ static void mtk_mac_init(struct mtk_eth_ - static void mtk_eth_fifo_init(struct mtk_eth_priv *priv) - { - char *pkt_base = priv->pkt_pool; -+ struct mtk_tx_dma *txd; -+ struct mtk_rx_dma *rxd; - int i; - - mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, 0xffff0000, 0); - udelay(500); - -- memset(priv->tx_ring_noc, 0, NUM_TX_DESC * sizeof(struct pdma_txdesc)); -- memset(priv->rx_ring_noc, 0, NUM_RX_DESC * sizeof(struct pdma_rxdesc)); -- memset(priv->pkt_pool, 0, TOTAL_PKT_BUF_SIZE); -+ memset(priv->tx_ring_noc, 0, NUM_TX_DESC * priv->soc->txd_size); -+ memset(priv->rx_ring_noc, 0, NUM_RX_DESC * priv->soc->rxd_size); -+ memset(priv->pkt_pool, 0xff, TOTAL_PKT_BUF_SIZE); - - flush_dcache_range((ulong)pkt_base, - (ulong)(pkt_base + TOTAL_PKT_BUF_SIZE)); -@@ -1218,17 +1151,21 @@ static void mtk_eth_fifo_init(struct mtk - priv->tx_cpu_owner_idx0 = 0; - - for (i = 0; i < NUM_TX_DESC; i++) { -- priv->tx_ring_noc[i].txd_info2.LS0 = 1; -- priv->tx_ring_noc[i].txd_info2.DDONE = 1; -- priv->tx_ring_noc[i].txd_info4.FPORT = priv->gmac_id + 1; -+ txd = priv->tx_ring_noc + i * priv->soc->txd_size; -+ -+ txd->txd1 = virt_to_phys(pkt_base); -+ txd->txd2 = PDMA_TXD2_DDONE | PDMA_TXD2_LS0; -+ txd->txd4 = PDMA_TXD4_FPORT_SET(priv->gmac_id + 1); - -- priv->tx_ring_noc[i].txd_info1.SDP0 = virt_to_phys(pkt_base); - pkt_base += PKTSIZE_ALIGN; - } - - for (i = 0; i < NUM_RX_DESC; i++) { -- priv->rx_ring_noc[i].rxd_info2.PLEN0 = PKTSIZE_ALIGN; -- priv->rx_ring_noc[i].rxd_info1.PDP0 = virt_to_phys(pkt_base); -+ rxd = priv->rx_ring_noc + i * priv->soc->rxd_size; -+ -+ rxd->rxd1 = virt_to_phys(pkt_base); -+ rxd->rxd2 = PDMA_RXD2_PLEN0_SET(PKTSIZE_ALIGN); -+ - pkt_base += PKTSIZE_ALIGN; - } - -@@ -1315,20 +1252,22 @@ static int mtk_eth_send(struct udevice * - { - struct mtk_eth_priv *priv = dev_get_priv(dev); - u32 idx = priv->tx_cpu_owner_idx0; -+ struct mtk_tx_dma *txd; - void *pkt_base; - -- if (!priv->tx_ring_noc[idx].txd_info2.DDONE) { -+ txd = priv->tx_ring_noc + idx * priv->soc->txd_size; -+ -+ if (!(txd->txd2 & PDMA_TXD2_DDONE)) { - debug("mtk-eth: TX DMA descriptor ring is full\n"); - return -EPERM; - } - -- pkt_base = (void *)phys_to_virt(priv->tx_ring_noc[idx].txd_info1.SDP0); -+ pkt_base = (void *)phys_to_virt(txd->txd1); - memcpy(pkt_base, packet, length); - flush_dcache_range((ulong)pkt_base, (ulong)pkt_base + - roundup(length, ARCH_DMA_MINALIGN)); - -- priv->tx_ring_noc[idx].txd_info2.SDL0 = length; -- priv->tx_ring_noc[idx].txd_info2.DDONE = 0; -+ txd->txd2 = PDMA_TXD2_LS0 | PDMA_TXD2_SDL0_SET(length); - - priv->tx_cpu_owner_idx0 = (priv->tx_cpu_owner_idx0 + 1) % NUM_TX_DESC; - mtk_pdma_write(priv, TX_CTX_IDX_REG(0), priv->tx_cpu_owner_idx0); -@@ -1340,16 +1279,20 @@ static int mtk_eth_recv(struct udevice * - { - struct mtk_eth_priv *priv = dev_get_priv(dev); - u32 idx = priv->rx_dma_owner_idx0; -+ struct mtk_rx_dma *rxd; - uchar *pkt_base; - u32 length; - -- if (!priv->rx_ring_noc[idx].rxd_info2.DDONE) { -+ rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size; -+ -+ if (!(rxd->rxd2 & PDMA_RXD2_DDONE)) { - debug("mtk-eth: RX DMA descriptor ring is empty\n"); - return -EAGAIN; - } - -- length = priv->rx_ring_noc[idx].rxd_info2.PLEN0; -- pkt_base = (void *)phys_to_virt(priv->rx_ring_noc[idx].rxd_info1.PDP0); -+ length = PDMA_RXD2_PLEN0_GET(rxd->rxd2); -+ -+ pkt_base = (void *)phys_to_virt(rxd->rxd1); - invalidate_dcache_range((ulong)pkt_base, (ulong)pkt_base + - roundup(length, ARCH_DMA_MINALIGN)); - -@@ -1363,10 +1306,11 @@ static int mtk_eth_free_pkt(struct udevi - { - struct mtk_eth_priv *priv = dev_get_priv(dev); - u32 idx = priv->rx_dma_owner_idx0; -+ struct mtk_rx_dma *rxd; -+ -+ rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size; - -- priv->rx_ring_noc[idx].rxd_info2.DDONE = 0; -- priv->rx_ring_noc[idx].rxd_info2.LS0 = 0; -- priv->rx_ring_noc[idx].rxd_info2.PLEN0 = PKTSIZE_ALIGN; -+ rxd->rxd2 = PDMA_RXD2_PLEN0_SET(PKTSIZE_ALIGN); - - mtk_pdma_write(priv, RX_CRX_IDX_REG(0), idx); - priv->rx_dma_owner_idx0 = (priv->rx_dma_owner_idx0 + 1) % NUM_RX_DESC; -@@ -1393,11 +1337,11 @@ static int mtk_eth_probe(struct udevice - return ret; - - /* Prepare for tx/rx rings */ -- priv->tx_ring_noc = (struct pdma_txdesc *) -- noncached_alloc(sizeof(struct pdma_txdesc) * NUM_TX_DESC, -+ priv->tx_ring_noc = (void *) -+ noncached_alloc(priv->soc->txd_size * NUM_TX_DESC, - ARCH_DMA_MINALIGN); -- priv->rx_ring_noc = (struct pdma_rxdesc *) -- noncached_alloc(sizeof(struct pdma_rxdesc) * NUM_RX_DESC, -+ priv->rx_ring_noc = (void *) -+ noncached_alloc(priv->soc->rxd_size * NUM_RX_DESC, - ARCH_DMA_MINALIGN); - - /* Set MAC mode */ -@@ -1554,18 +1498,26 @@ static int mtk_eth_of_to_plat(struct ude - - static const struct mtk_soc_data mt7629_data = { - .ana_rgc3 = 0x128, -+ .txd_size = sizeof(struct mtk_tx_dma), -+ .rxd_size = sizeof(struct mtk_rx_dma), - }; - - static const struct mtk_soc_data mt7623_data = { - .caps = MT7623_CAPS, -+ .txd_size = sizeof(struct mtk_tx_dma), -+ .rxd_size = sizeof(struct mtk_rx_dma), - }; - - static const struct mtk_soc_data mt7622_data = { - .ana_rgc3 = 0x2028, -+ .txd_size = sizeof(struct mtk_tx_dma), -+ .rxd_size = sizeof(struct mtk_rx_dma), - }; - - static const struct mtk_soc_data mt7621_data = { - .caps = MT7621_CAPS, -+ .txd_size = sizeof(struct mtk_tx_dma), -+ .rxd_size = sizeof(struct mtk_rx_dma), - }; - - static const struct udevice_id mtk_eth_ids[] = { ---- a/drivers/net/mtk_eth.h -+++ b/drivers/net/mtk_eth.h -@@ -10,6 +10,7 @@ - #define _MTK_ETH_H_ - - #include -+#include - - enum mkt_eth_capabilities { - MTK_TRGMII_BIT, -@@ -435,4 +436,35 @@ enum mkt_eth_capabilities { - #define PHY_POWER_SAVING_M 0x300 - #define PHY_POWER_SAVING_TX 0x0 - -+/* PDMA descriptors */ -+struct mtk_rx_dma { -+ unsigned int rxd1; -+ unsigned int rxd2; -+ unsigned int rxd3; -+ unsigned int rxd4; -+} __packed __aligned(4); -+ -+struct mtk_tx_dma { -+ unsigned int txd1; -+ unsigned int txd2; -+ unsigned int txd3; -+ unsigned int txd4; -+} __packed __aligned(4); -+ -+/* PDMA TXD fields */ -+#define PDMA_TXD2_DDONE BIT(31) -+#define PDMA_TXD2_LS0 BIT(30) -+#define PDMA_TXD2_SDL0_M GENMASK(29, 16) -+#define PDMA_TXD2_SDL0_SET(_v) FIELD_PREP(PDMA_TXD2_SDL0_M, (_v)) -+ -+#define PDMA_TXD4_FPORT_M GENMASK(27, 25) -+#define PDMA_TXD4_FPORT_SET(_v) FIELD_PREP(PDMA_TXD4_FPORT_M, (_v)) -+ -+/* PDMA RXD fields */ -+#define PDMA_RXD2_DDONE BIT(31) -+#define PDMA_RXD2_LS0 BIT(30) -+#define PDMA_RXD2_PLEN0_M GENMASK(29, 16) -+#define PDMA_RXD2_PLEN0_GET(_v) FIELD_GET(PDMA_RXD2_PLEN0_M, (_v)) -+#define PDMA_RXD2_PLEN0_SET(_v) FIELD_PREP(PDMA_RXD2_PLEN0_M, (_v)) -+ - #endif /* _MTK_ETH_H_ */ diff --git a/package/boot/uboot-mediatek/patches/002-0008-net-mediatek-add-support-for-PDMA-v2.patch b/package/boot/uboot-mediatek/patches/002-0008-net-mediatek-add-support-for-PDMA-v2.patch deleted file mode 100644 index 043e9a91d48..00000000000 --- a/package/boot/uboot-mediatek/patches/002-0008-net-mediatek-add-support-for-PDMA-v2.patch +++ /dev/null @@ -1,298 +0,0 @@ -From 72241607b955639a51b79297776991de7dd59915 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 31 Aug 2022 19:04:27 +0800 -Subject: [PATCH 08/32] net: mediatek: add support for PDMA v2 - -This patch adds support for PDMA v2 hardware. The PDMA v2 has extended the -DMA descriptor to 8-words, and some of its fields have changed comparing -to the v1 hardware. - -Reviewed-by: Ramon Fried -Reviewed-by: Simon Glass -Signed-off-by: Weijie Gao ---- - drivers/net/mtk_eth.c | 54 ++++++++++++++++++++++++++++++++----------- - drivers/net/mtk_eth.h | 53 +++++++++++++++++++++++++++++++++++------- - 2 files changed, 86 insertions(+), 21 deletions(-) - ---- a/drivers/net/mtk_eth.c -+++ b/drivers/net/mtk_eth.c -@@ -76,10 +76,14 @@ enum mtk_switch { - * @caps Flags shown the extra capability for the SoC - * @ana_rgc3: The offset for register ANA_RGC3 related to - * sgmiisys syscon -+ * @pdma_base: Register base of PDMA block -+ * @txd_size: Tx DMA descriptor size. -+ * @rxd_size: Rx DMA descriptor size. - */ - struct mtk_soc_data { - u32 caps; - u32 ana_rgc3; -+ u32 pdma_base; - u32 txd_size; - u32 rxd_size; - }; -@@ -130,13 +134,13 @@ struct mtk_eth_priv { - - static void mtk_pdma_write(struct mtk_eth_priv *priv, u32 reg, u32 val) - { -- writel(val, priv->fe_base + PDMA_BASE + reg); -+ writel(val, priv->fe_base + priv->soc->pdma_base + reg); - } - - static void mtk_pdma_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, - u32 set) - { -- clrsetbits_le32(priv->fe_base + PDMA_BASE + reg, clr, set); -+ clrsetbits_le32(priv->fe_base + priv->soc->pdma_base + reg, clr, set); - } - - static void mtk_gdma_write(struct mtk_eth_priv *priv, int no, u32 reg, -@@ -1133,8 +1137,8 @@ static void mtk_mac_init(struct mtk_eth_ - static void mtk_eth_fifo_init(struct mtk_eth_priv *priv) - { - char *pkt_base = priv->pkt_pool; -- struct mtk_tx_dma *txd; -- struct mtk_rx_dma *rxd; -+ struct mtk_tx_dma_v2 *txd; -+ struct mtk_rx_dma_v2 *rxd; - int i; - - mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, 0xffff0000, 0); -@@ -1155,7 +1159,11 @@ static void mtk_eth_fifo_init(struct mtk - - txd->txd1 = virt_to_phys(pkt_base); - txd->txd2 = PDMA_TXD2_DDONE | PDMA_TXD2_LS0; -- txd->txd4 = PDMA_TXD4_FPORT_SET(priv->gmac_id + 1); -+ -+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2)) -+ txd->txd5 = PDMA_V2_TXD5_FPORT_SET(priv->gmac_id + 1); -+ else -+ txd->txd4 = PDMA_V1_TXD4_FPORT_SET(priv->gmac_id + 1); - - pkt_base += PKTSIZE_ALIGN; - } -@@ -1164,7 +1172,11 @@ static void mtk_eth_fifo_init(struct mtk - rxd = priv->rx_ring_noc + i * priv->soc->rxd_size; - - rxd->rxd1 = virt_to_phys(pkt_base); -- rxd->rxd2 = PDMA_RXD2_PLEN0_SET(PKTSIZE_ALIGN); -+ -+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2)) -+ rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN); -+ else -+ rxd->rxd2 = PDMA_V1_RXD2_PLEN0_SET(PKTSIZE_ALIGN); - - pkt_base += PKTSIZE_ALIGN; - } -@@ -1193,6 +1205,9 @@ static int mtk_eth_start(struct udevice - reset_deassert(&priv->rst_fe); - mdelay(10); - -+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2)) -+ setbits_le32(priv->fe_base + FE_GLO_MISC_REG, PDMA_VER_V2); -+ - /* Packets forward to PDMA */ - mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, GDMA_FWD_TO_CPU); - -@@ -1227,7 +1242,7 @@ static void mtk_eth_stop(struct udevice - TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN, 0); - udelay(500); - -- wait_for_bit_le32(priv->fe_base + PDMA_BASE + PDMA_GLO_CFG_REG, -+ wait_for_bit_le32(priv->fe_base + priv->soc->pdma_base + PDMA_GLO_CFG_REG, - RX_DMA_BUSY | TX_DMA_BUSY, 0, 5000, 0); - } - -@@ -1252,7 +1267,7 @@ static int mtk_eth_send(struct udevice * - { - struct mtk_eth_priv *priv = dev_get_priv(dev); - u32 idx = priv->tx_cpu_owner_idx0; -- struct mtk_tx_dma *txd; -+ struct mtk_tx_dma_v2 *txd; - void *pkt_base; - - txd = priv->tx_ring_noc + idx * priv->soc->txd_size; -@@ -1267,7 +1282,10 @@ static int mtk_eth_send(struct udevice * - flush_dcache_range((ulong)pkt_base, (ulong)pkt_base + - roundup(length, ARCH_DMA_MINALIGN)); - -- txd->txd2 = PDMA_TXD2_LS0 | PDMA_TXD2_SDL0_SET(length); -+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2)) -+ txd->txd2 = PDMA_TXD2_LS0 | PDMA_V2_TXD2_SDL0_SET(length); -+ else -+ txd->txd2 = PDMA_TXD2_LS0 | PDMA_V1_TXD2_SDL0_SET(length); - - priv->tx_cpu_owner_idx0 = (priv->tx_cpu_owner_idx0 + 1) % NUM_TX_DESC; - mtk_pdma_write(priv, TX_CTX_IDX_REG(0), priv->tx_cpu_owner_idx0); -@@ -1279,7 +1297,7 @@ static int mtk_eth_recv(struct udevice * - { - struct mtk_eth_priv *priv = dev_get_priv(dev); - u32 idx = priv->rx_dma_owner_idx0; -- struct mtk_rx_dma *rxd; -+ struct mtk_rx_dma_v2 *rxd; - uchar *pkt_base; - u32 length; - -@@ -1290,7 +1308,10 @@ static int mtk_eth_recv(struct udevice * - return -EAGAIN; - } - -- length = PDMA_RXD2_PLEN0_GET(rxd->rxd2); -+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2)) -+ length = PDMA_V2_RXD2_PLEN0_GET(rxd->rxd2); -+ else -+ length = PDMA_V1_RXD2_PLEN0_GET(rxd->rxd2); - - pkt_base = (void *)phys_to_virt(rxd->rxd1); - invalidate_dcache_range((ulong)pkt_base, (ulong)pkt_base + -@@ -1306,11 +1327,14 @@ static int mtk_eth_free_pkt(struct udevi - { - struct mtk_eth_priv *priv = dev_get_priv(dev); - u32 idx = priv->rx_dma_owner_idx0; -- struct mtk_rx_dma *rxd; -+ struct mtk_rx_dma_v2 *rxd; - - rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size; - -- rxd->rxd2 = PDMA_RXD2_PLEN0_SET(PKTSIZE_ALIGN); -+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2)) -+ rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN); -+ else -+ rxd->rxd2 = PDMA_V1_RXD2_PLEN0_SET(PKTSIZE_ALIGN); - - mtk_pdma_write(priv, RX_CRX_IDX_REG(0), idx); - priv->rx_dma_owner_idx0 = (priv->rx_dma_owner_idx0 + 1) % NUM_RX_DESC; -@@ -1498,24 +1522,28 @@ static int mtk_eth_of_to_plat(struct ude - - static const struct mtk_soc_data mt7629_data = { - .ana_rgc3 = 0x128, -+ .pdma_base = PDMA_V1_BASE, - .txd_size = sizeof(struct mtk_tx_dma), - .rxd_size = sizeof(struct mtk_rx_dma), - }; - - static const struct mtk_soc_data mt7623_data = { - .caps = MT7623_CAPS, -+ .pdma_base = PDMA_V1_BASE, - .txd_size = sizeof(struct mtk_tx_dma), - .rxd_size = sizeof(struct mtk_rx_dma), - }; - - static const struct mtk_soc_data mt7622_data = { - .ana_rgc3 = 0x2028, -+ .pdma_base = PDMA_V1_BASE, - .txd_size = sizeof(struct mtk_tx_dma), - .rxd_size = sizeof(struct mtk_rx_dma), - }; - - static const struct mtk_soc_data mt7621_data = { - .caps = MT7621_CAPS, -+ .pdma_base = PDMA_V1_BASE, - .txd_size = sizeof(struct mtk_tx_dma), - .rxd_size = sizeof(struct mtk_rx_dma), - }; ---- a/drivers/net/mtk_eth.h -+++ b/drivers/net/mtk_eth.h -@@ -15,6 +15,7 @@ - enum mkt_eth_capabilities { - MTK_TRGMII_BIT, - MTK_TRGMII_MT7621_CLK_BIT, -+ MTK_NETSYS_V2_BIT, - - /* PATH BITS */ - MTK_ETH_PATH_GMAC1_TRGMII_BIT, -@@ -22,6 +23,7 @@ enum mkt_eth_capabilities { - - #define MTK_TRGMII BIT(MTK_TRGMII_BIT) - #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) -+#define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) - - /* Supported path present on SoCs */ - #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) -@@ -35,7 +37,8 @@ enum mkt_eth_capabilities { - #define MT7623_CAPS (MTK_GMAC1_TRGMII) - - /* Frame Engine Register Bases */ --#define PDMA_BASE 0x0800 -+#define PDMA_V1_BASE 0x0800 -+#define PDMA_V2_BASE 0x6000 - #define GDMA1_BASE 0x0500 - #define GDMA2_BASE 0x1500 - #define GMAC_BASE 0x10000 -@@ -74,6 +77,8 @@ enum mkt_eth_capabilities { - #define SGMSYS_SPEED_2500 BIT(2) - - /* Frame Engine Registers */ -+#define FE_GLO_MISC_REG 0x124 -+#define PDMA_VER_V2 BIT(4) - - /* PDMA */ - #define TX_BASE_PTR_REG(n) (0x000 + (n) * 0x10) -@@ -444,6 +449,17 @@ struct mtk_rx_dma { - unsigned int rxd4; - } __packed __aligned(4); - -+struct mtk_rx_dma_v2 { -+ unsigned int rxd1; -+ unsigned int rxd2; -+ unsigned int rxd3; -+ unsigned int rxd4; -+ unsigned int rxd5; -+ unsigned int rxd6; -+ unsigned int rxd7; -+ unsigned int rxd8; -+} __packed __aligned(4); -+ - struct mtk_tx_dma { - unsigned int txd1; - unsigned int txd2; -@@ -451,20 +467,41 @@ struct mtk_tx_dma { - unsigned int txd4; - } __packed __aligned(4); - -+struct mtk_tx_dma_v2 { -+ unsigned int txd1; -+ unsigned int txd2; -+ unsigned int txd3; -+ unsigned int txd4; -+ unsigned int txd5; -+ unsigned int txd6; -+ unsigned int txd7; -+ unsigned int txd8; -+} __packed __aligned(4); -+ - /* PDMA TXD fields */ - #define PDMA_TXD2_DDONE BIT(31) - #define PDMA_TXD2_LS0 BIT(30) --#define PDMA_TXD2_SDL0_M GENMASK(29, 16) --#define PDMA_TXD2_SDL0_SET(_v) FIELD_PREP(PDMA_TXD2_SDL0_M, (_v)) -+#define PDMA_V1_TXD2_SDL0_M GENMASK(29, 16) -+#define PDMA_V1_TXD2_SDL0_SET(_v) FIELD_PREP(PDMA_V1_TXD2_SDL0_M, (_v)) -+#define PDMA_V2_TXD2_SDL0_M GENMASK(23, 8) -+#define PDMA_V2_TXD2_SDL0_SET(_v) FIELD_PREP(PDMA_V2_TXD2_SDL0_M, (_v)) -+ -+#define PDMA_V1_TXD4_FPORT_M GENMASK(27, 25) -+#define PDMA_V1_TXD4_FPORT_SET(_v) FIELD_PREP(PDMA_V1_TXD4_FPORT_M, (_v)) -+#define PDMA_V2_TXD4_FPORT_M GENMASK(27, 24) -+#define PDMA_V2_TXD4_FPORT_SET(_v) FIELD_PREP(PDMA_V2_TXD4_FPORT_M, (_v)) - --#define PDMA_TXD4_FPORT_M GENMASK(27, 25) --#define PDMA_TXD4_FPORT_SET(_v) FIELD_PREP(PDMA_TXD4_FPORT_M, (_v)) -+#define PDMA_V2_TXD5_FPORT_M GENMASK(19, 16) -+#define PDMA_V2_TXD5_FPORT_SET(_v) FIELD_PREP(PDMA_V2_TXD5_FPORT_M, (_v)) - - /* PDMA RXD fields */ - #define PDMA_RXD2_DDONE BIT(31) - #define PDMA_RXD2_LS0 BIT(30) --#define PDMA_RXD2_PLEN0_M GENMASK(29, 16) --#define PDMA_RXD2_PLEN0_GET(_v) FIELD_GET(PDMA_RXD2_PLEN0_M, (_v)) --#define PDMA_RXD2_PLEN0_SET(_v) FIELD_PREP(PDMA_RXD2_PLEN0_M, (_v)) -+#define PDMA_V1_RXD2_PLEN0_M GENMASK(29, 16) -+#define PDMA_V1_RXD2_PLEN0_GET(_v) FIELD_GET(PDMA_V1_RXD2_PLEN0_M, (_v)) -+#define PDMA_V1_RXD2_PLEN0_SET(_v) FIELD_PREP(PDMA_V1_RXD2_PLEN0_M, (_v)) -+#define PDMA_V2_RXD2_PLEN0_M GENMASK(23, 8) -+#define PDMA_V2_RXD2_PLEN0_GET(_v) FIELD_GET(PDMA_V2_RXD2_PLEN0_M, (_v)) -+#define PDMA_V2_RXD2_PLEN0_SET(_v) FIELD_PREP(PDMA_V2_RXD2_PLEN0_M, (_v)) - - #endif /* _MTK_ETH_H_ */ diff --git a/package/boot/uboot-mediatek/patches/002-0009-net-mediatek-add-support-for-MediaTek-MT7981-MT7986.patch b/package/boot/uboot-mediatek/patches/002-0009-net-mediatek-add-support-for-MediaTek-MT7981-MT7986.patch deleted file mode 100644 index e2a16e2d6d5..00000000000 --- a/package/boot/uboot-mediatek/patches/002-0009-net-mediatek-add-support-for-MediaTek-MT7981-MT7986.patch +++ /dev/null @@ -1,100 +0,0 @@ -From 4bbe44513bf9dc7041b2ce4aac6e841a0e10d2e6 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 31 Aug 2022 19:04:29 +0800 -Subject: [PATCH 09/32] net: mediatek: add support for MediaTek MT7981/MT7986 - -This patch adds support for MediaTek MT7981 and MT7986. Both chips uses -PDMA v2. - -Reviewed-by: Ramon Fried -Signed-off-by: Weijie Gao ---- - drivers/net/mtk_eth.c | 27 +++++++++++++++++++++++++++ - drivers/net/mtk_eth.h | 5 +++++ - 2 files changed, 32 insertions(+) - ---- a/drivers/net/mtk_eth.c -+++ b/drivers/net/mtk_eth.c -@@ -115,6 +115,7 @@ struct mtk_eth_priv { - int force_mode; - int speed; - int duplex; -+ bool pn_swap; - - struct phy_device *phydev; - int phy_interface; -@@ -1057,6 +1058,12 @@ static void mtk_sgmii_init(struct mtk_et - /* SGMII force mode setting */ - writel(SGMII_FORCE_MODE, priv->sgmii_base + SGMSYS_SGMII_MODE); - -+ /* SGMII PN SWAP setting */ -+ if (priv->pn_swap) { -+ setbits_le32(priv->sgmii_base + SGMSYS_QPHY_WRAP_CTRL, -+ SGMII_PN_SWAP_TX_RX); -+ } -+ - /* Release PHYA power down state */ - clrsetbits_le32(priv->sgmii_base + SGMSYS_QPHY_PWR_STATE_CTRL, - SGMII_PHYA_PWD, 0); -@@ -1470,6 +1477,8 @@ static int mtk_eth_of_to_plat(struct ude - dev_err(dev, "Unable to find sgmii\n"); - return -ENODEV; - } -+ -+ priv->pn_swap = ofnode_read_bool(args.node, "pn_swap"); - } - - /* check for switch first, otherwise phy will be used */ -@@ -1520,6 +1529,22 @@ static int mtk_eth_of_to_plat(struct ude - return 0; - } - -+static const struct mtk_soc_data mt7986_data = { -+ .caps = MT7986_CAPS, -+ .ana_rgc3 = 0x128, -+ .pdma_base = PDMA_V2_BASE, -+ .txd_size = sizeof(struct mtk_tx_dma_v2), -+ .rxd_size = sizeof(struct mtk_rx_dma_v2), -+}; -+ -+static const struct mtk_soc_data mt7981_data = { -+ .caps = MT7986_CAPS, -+ .ana_rgc3 = 0x128, -+ .pdma_base = PDMA_V2_BASE, -+ .txd_size = sizeof(struct mtk_tx_dma_v2), -+ .rxd_size = sizeof(struct mtk_rx_dma_v2), -+}; -+ - static const struct mtk_soc_data mt7629_data = { - .ana_rgc3 = 0x128, - .pdma_base = PDMA_V1_BASE, -@@ -1549,6 +1574,8 @@ static const struct mtk_soc_data mt7621_ - }; - - static const struct udevice_id mtk_eth_ids[] = { -+ { .compatible = "mediatek,mt7986-eth", .data = (ulong)&mt7986_data }, -+ { .compatible = "mediatek,mt7981-eth", .data = (ulong)&mt7981_data }, - { .compatible = "mediatek,mt7629-eth", .data = (ulong)&mt7629_data }, - { .compatible = "mediatek,mt7623-eth", .data = (ulong)&mt7623_data }, - { .compatible = "mediatek,mt7622-eth", .data = (ulong)&mt7622_data }, ---- a/drivers/net/mtk_eth.h -+++ b/drivers/net/mtk_eth.h -@@ -36,6 +36,8 @@ enum mkt_eth_capabilities { - - #define MT7623_CAPS (MTK_GMAC1_TRGMII) - -+#define MT7986_CAPS (MTK_NETSYS_V2) -+ - /* Frame Engine Register Bases */ - #define PDMA_V1_BASE 0x0800 - #define PDMA_V2_BASE 0x6000 -@@ -72,6 +74,9 @@ enum mkt_eth_capabilities { - #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 - #define SGMII_PHYA_PWD BIT(4) - -+#define SGMSYS_QPHY_WRAP_CTRL 0xec -+#define SGMII_PN_SWAP_TX_RX 0x03 -+ - #define SGMSYS_GEN2_SPEED 0x2028 - #define SGMSYS_GEN2_SPEED_V2 0x128 - #define SGMSYS_SPEED_2500 BIT(2) diff --git a/package/boot/uboot-mediatek/patches/002-0010-serial-mtk-add-support-for-using-dynamic-baud-clock-.patch b/package/boot/uboot-mediatek/patches/002-0010-serial-mtk-add-support-for-using-dynamic-baud-clock-.patch deleted file mode 100644 index d2f28f2bc9f..00000000000 --- a/package/boot/uboot-mediatek/patches/002-0010-serial-mtk-add-support-for-using-dynamic-baud-clock-.patch +++ /dev/null @@ -1,202 +0,0 @@ -From d19ad7515a7ef4ee58b5c6606ee9f74c94f28932 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 31 Aug 2022 19:04:32 +0800 -Subject: [PATCH 10/32] serial: mtk: add support for using dynamic baud clock - souce - -The baud clock on some platform may change due to assigned-clock-parent -set in DT. In current flow the baud clock is only retrieved during probe -stage. If the parent of the source clock changes after probe stage, the -setbrg will set wrong baudrate. - -To get the right clock rate, this patch records the baud clk struct to the -driver's priv, and changes the driver's flow to get the clock rate before -calling _mtk_serial_setbrg(). - -Reviewed-by: Simon Glass -Signed-off-by: Weijie Gao ---- - drivers/serial/serial_mtk.c | 80 ++++++++++++++++++++++--------------- - 1 file changed, 47 insertions(+), 33 deletions(-) - ---- a/drivers/serial/serial_mtk.c -+++ b/drivers/serial/serial_mtk.c -@@ -10,6 +10,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -70,27 +71,37 @@ struct mtk_serial_regs { - #define BAUD_ALLOW_MAX(baud) ((baud) + (baud) * 3 / 100) - #define BAUD_ALLOW_MIX(baud) ((baud) - (baud) * 3 / 100) - -+/* struct mtk_serial_priv - Structure holding all information used by the -+ * driver -+ * @regs: Register base of the serial port -+ * @clk: The baud clock device -+ * @fixed_clk_rate: Fallback fixed baud clock rate if baud clock -+ * device is not specified -+ * @force_highspeed: Force using high-speed mode -+ */ - struct mtk_serial_priv { - struct mtk_serial_regs __iomem *regs; -- u32 clock; -+ struct clk clk; -+ u32 fixed_clk_rate; - bool force_highspeed; - }; - --static void _mtk_serial_setbrg(struct mtk_serial_priv *priv, int baud) -+static void _mtk_serial_setbrg(struct mtk_serial_priv *priv, int baud, -+ uint clk_rate) - { - u32 quot, realbaud, samplecount = 1; - - /* Special case for low baud clock */ -- if (baud <= 115200 && priv->clock <= 12000000) { -+ if (baud <= 115200 && clk_rate == 12000000) { - writel(3, &priv->regs->highspeed); - -- quot = DIV_ROUND_CLOSEST(priv->clock, 256 * baud); -+ quot = DIV_ROUND_CLOSEST(clk_rate, 256 * baud); - if (quot == 0) - quot = 1; - -- samplecount = DIV_ROUND_CLOSEST(priv->clock, quot * baud); -+ samplecount = DIV_ROUND_CLOSEST(clk_rate, quot * baud); - -- realbaud = priv->clock / samplecount / quot; -+ realbaud = clk_rate / samplecount / quot; - if (realbaud > BAUD_ALLOW_MAX(baud) || - realbaud < BAUD_ALLOW_MIX(baud)) { - pr_info("baud %d can't be handled\n", baud); -@@ -104,7 +115,7 @@ static void _mtk_serial_setbrg(struct mt - - if (baud <= 115200) { - writel(0, &priv->regs->highspeed); -- quot = DIV_ROUND_CLOSEST(priv->clock, 16 * baud); -+ quot = DIV_ROUND_CLOSEST(clk_rate, 16 * baud); - } else if (baud <= 576000) { - writel(2, &priv->regs->highspeed); - -@@ -112,13 +123,13 @@ static void _mtk_serial_setbrg(struct mt - if ((baud == 500000) || (baud == 576000)) - baud = 460800; - -- quot = DIV_ROUND_UP(priv->clock, 4 * baud); -+ quot = DIV_ROUND_UP(clk_rate, 4 * baud); - } else { - use_hs3: - writel(3, &priv->regs->highspeed); - -- quot = DIV_ROUND_UP(priv->clock, 256 * baud); -- samplecount = DIV_ROUND_CLOSEST(priv->clock, quot * baud); -+ quot = DIV_ROUND_UP(clk_rate, 256 * baud); -+ samplecount = DIV_ROUND_CLOSEST(clk_rate, quot * baud); - } - - set_baud: -@@ -167,8 +178,13 @@ static int _mtk_serial_pending(struct mt - static int mtk_serial_setbrg(struct udevice *dev, int baudrate) - { - struct mtk_serial_priv *priv = dev_get_priv(dev); -+ u32 clk_rate; -+ -+ clk_rate = clk_get_rate(&priv->clk); -+ if (IS_ERR_VALUE(clk_rate) || clk_rate == 0) -+ clk_rate = priv->fixed_clk_rate; - -- _mtk_serial_setbrg(priv, baudrate); -+ _mtk_serial_setbrg(priv, baudrate, clk_rate); - - return 0; - } -@@ -211,7 +227,6 @@ static int mtk_serial_of_to_plat(struct - { - struct mtk_serial_priv *priv = dev_get_priv(dev); - fdt_addr_t addr; -- struct clk clk; - int err; - - addr = dev_read_addr(dev); -@@ -220,22 +235,19 @@ static int mtk_serial_of_to_plat(struct - - priv->regs = map_physmem(addr, 0, MAP_NOCACHE); - -- err = clk_get_by_index(dev, 0, &clk); -- if (!err) { -- err = clk_get_rate(&clk); -- if (!IS_ERR_VALUE(err)) -- priv->clock = err; -- } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) { -- debug("mtk_serial: failed to get clock\n"); -- return err; -- } -- -- if (!priv->clock) -- priv->clock = dev_read_u32_default(dev, "clock-frequency", 0); -- -- if (!priv->clock) { -- debug("mtk_serial: clock not defined\n"); -- return -EINVAL; -+ err = clk_get_by_index(dev, 0, &priv->clk); -+ if (err) { -+ err = dev_read_u32(dev, "clock-frequency", &priv->fixed_clk_rate); -+ if (err) { -+ dev_err(dev, "baud clock not defined\n"); -+ return -EINVAL; -+ } -+ } else { -+ err = clk_get_rate(&priv->clk); -+ if (IS_ERR_VALUE(err)) { -+ dev_err(dev, "invalid baud clock\n"); -+ return -EINVAL; -+ } - } - - priv->force_highspeed = dev_read_bool(dev, "mediatek,force-highspeed"); -@@ -273,7 +285,7 @@ DECLARE_GLOBAL_DATA_PTR; - #define DECLARE_HSUART_PRIV(port) \ - static struct mtk_serial_priv mtk_hsuart##port = { \ - .regs = (struct mtk_serial_regs *)CONFIG_SYS_NS16550_COM##port, \ -- .clock = CONFIG_SYS_NS16550_CLK \ -+ .fixed_clk_rate = CONFIG_SYS_NS16550_CLK \ - }; - - #define DECLARE_HSUART_FUNCTIONS(port) \ -@@ -282,12 +294,14 @@ DECLARE_GLOBAL_DATA_PTR; - writel(0, &mtk_hsuart##port.regs->ier); \ - writel(UART_MCRVAL, &mtk_hsuart##port.regs->mcr); \ - writel(UART_FCRVAL, &mtk_hsuart##port.regs->fcr); \ -- _mtk_serial_setbrg(&mtk_hsuart##port, gd->baudrate); \ -+ _mtk_serial_setbrg(&mtk_hsuart##port, gd->baudrate, \ -+ mtk_hsuart##port.fixed_clk_rate); \ - return 0 ; \ - } \ - static void mtk_serial##port##_setbrg(void) \ - { \ -- _mtk_serial_setbrg(&mtk_hsuart##port, gd->baudrate); \ -+ _mtk_serial_setbrg(&mtk_hsuart##port, gd->baudrate, \ -+ mtk_hsuart##port.fixed_clk_rate); \ - } \ - static int mtk_serial##port##_getc(void) \ - { \ -@@ -427,13 +441,13 @@ static inline void _debug_uart_init(void - struct mtk_serial_priv priv; - - priv.regs = (void *) CONFIG_VAL(DEBUG_UART_BASE); -- priv.clock = CONFIG_DEBUG_UART_CLOCK; -+ priv.fixed_clk_rate = CONFIG_DEBUG_UART_CLOCK; - - writel(0, &priv.regs->ier); - writel(UART_MCRVAL, &priv.regs->mcr); - writel(UART_FCRVAL, &priv.regs->fcr); - -- _mtk_serial_setbrg(&priv, CONFIG_BAUDRATE); -+ _mtk_serial_setbrg(&priv, CONFIG_BAUDRATE, priv.fixed_clk_rate); - } - - static inline void _debug_uart_putc(int ch) diff --git a/package/boot/uboot-mediatek/patches/002-0011-arm-dts-mt7622-force-high-speed-mode-for-uart.patch b/package/boot/uboot-mediatek/patches/002-0011-arm-dts-mt7622-force-high-speed-mode-for-uart.patch deleted file mode 100644 index 0777848f01b..00000000000 --- a/package/boot/uboot-mediatek/patches/002-0011-arm-dts-mt7622-force-high-speed-mode-for-uart.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 79786aa175010dde78f95970939e8efadd7a3295 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 31 Aug 2022 19:04:34 +0800 -Subject: [PATCH 11/32] arm: dts: mt7622: force high-speed mode for uart - -The input clock for uart is too slow (25MHz) which introduces frequent data -error on both receiving and transmitting even if the baudrate is 115200. - -Using high-speed can significantly solve this issue. - -Reviewed-by: Simon Glass -Signed-off-by: Weijie Gao ---- - arch/arm/dts/mt7622.dtsi | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm/dts/mt7622.dtsi -+++ b/arch/arm/dts/mt7622.dtsi -@@ -175,6 +175,7 @@ - status = "disabled"; - assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>; -+ mediatek,force-highspeed; - }; - - mmc0: mmc@11230000 { diff --git a/package/boot/uboot-mediatek/patches/002-0012-pwm-mtk-add-support-for-MediaTek-MT7986-SoC.patch b/package/boot/uboot-mediatek/patches/002-0012-pwm-mtk-add-support-for-MediaTek-MT7986-SoC.patch deleted file mode 100644 index da5f53f49c2..00000000000 --- a/package/boot/uboot-mediatek/patches/002-0012-pwm-mtk-add-support-for-MediaTek-MT7986-SoC.patch +++ /dev/null @@ -1,32 +0,0 @@ -From d7dae84aad997f4f9b5d039f7ab180bd1f54fa37 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 31 Aug 2022 19:04:35 +0800 -Subject: [PATCH 12/32] pwm: mtk: add support for MediaTek MT7986 SoC - -This patch adds PWM support for MediaTek MT7986 SoC. - -Reviewed-by: Simon Glass -Signed-off-by: Weijie Gao ---- - drivers/pwm/pwm-mtk.c | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/drivers/pwm/pwm-mtk.c -+++ b/drivers/pwm/pwm-mtk.c -@@ -171,10 +171,16 @@ static const struct mtk_pwm_soc mt7629_d - .pwm45_fixup = false, - }; - -+static const struct mtk_pwm_soc mt7986_data = { -+ .num_pwms = 2, -+ .pwm45_fixup = false, -+}; -+ - static const struct udevice_id mtk_pwm_ids[] = { - { .compatible = "mediatek,mt7622-pwm", .data = (ulong)&mt7622_data }, - { .compatible = "mediatek,mt7623-pwm", .data = (ulong)&mt7623_data }, - { .compatible = "mediatek,mt7629-pwm", .data = (ulong)&mt7629_data }, -+ { .compatible = "mediatek,mt7986-pwm", .data = (ulong)&mt7986_data }, - { } - }; - diff --git a/package/boot/uboot-mediatek/patches/002-0013-pwm-mtk-add-support-for-MediaTek-MT7981-SoC.patch b/package/boot/uboot-mediatek/patches/002-0013-pwm-mtk-add-support-for-MediaTek-MT7981-SoC.patch deleted file mode 100644 index cd8ecd59179..00000000000 --- a/package/boot/uboot-mediatek/patches/002-0013-pwm-mtk-add-support-for-MediaTek-MT7981-SoC.patch +++ /dev/null @@ -1,99 +0,0 @@ -From 230003c14f7beedf4042bf2258b04e2cd5aac270 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 31 Aug 2022 19:04:38 +0800 -Subject: [PATCH 13/32] pwm: mtk: add support for MediaTek MT7981 SoC - -This patch adds PWM support for MediaTek MT7981 SoC. -MT7981 uses a different register offset so we have to add a version field -to indicate the IP core version. - -Reviewed-by: Simon Glass -Signed-off-by: Weijie Gao ---- - drivers/pwm/pwm-mtk.c | 34 ++++++++++++++++++++++++++++++++-- - 1 file changed, 32 insertions(+), 2 deletions(-) - ---- a/drivers/pwm/pwm-mtk.c -+++ b/drivers/pwm/pwm-mtk.c -@@ -29,13 +29,23 @@ - - #define NSEC_PER_SEC 1000000000L - --static const unsigned int mtk_pwm_reg_offset[] = { -+enum mtk_pwm_reg_ver { -+ PWM_REG_V1, -+ PWM_REG_V2, -+}; -+ -+static const unsigned int mtk_pwm_reg_offset_v1[] = { - 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220 - }; - -+static const unsigned int mtk_pwm_reg_offset_v2[] = { -+ 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240 -+}; -+ - struct mtk_pwm_soc { - unsigned int num_pwms; - bool pwm45_fixup; -+ enum mtk_pwm_reg_ver reg_ver; - }; - - struct mtk_pwm_priv { -@@ -49,7 +59,16 @@ struct mtk_pwm_priv { - static void mtk_pwm_w32(struct udevice *dev, uint channel, uint reg, uint val) - { - struct mtk_pwm_priv *priv = dev_get_priv(dev); -- u32 offset = mtk_pwm_reg_offset[channel]; -+ u32 offset; -+ -+ switch (priv->soc->reg_ver) { -+ case PWM_REG_V2: -+ offset = mtk_pwm_reg_offset_v2[channel]; -+ break; -+ -+ default: -+ offset = mtk_pwm_reg_offset_v1[channel]; -+ } - - writel(val, priv->base + offset + reg); - } -@@ -159,27 +178,38 @@ static const struct pwm_ops mtk_pwm_ops - static const struct mtk_pwm_soc mt7622_data = { - .num_pwms = 6, - .pwm45_fixup = false, -+ .reg_ver = PWM_REG_V1, - }; - - static const struct mtk_pwm_soc mt7623_data = { - .num_pwms = 5, - .pwm45_fixup = true, -+ .reg_ver = PWM_REG_V1, - }; - - static const struct mtk_pwm_soc mt7629_data = { - .num_pwms = 1, - .pwm45_fixup = false, -+ .reg_ver = PWM_REG_V1, -+}; -+ -+static const struct mtk_pwm_soc mt7981_data = { -+ .num_pwms = 2, -+ .pwm45_fixup = false, -+ .reg_ver = PWM_REG_V2, - }; - - static const struct mtk_pwm_soc mt7986_data = { - .num_pwms = 2, - .pwm45_fixup = false, -+ .reg_ver = PWM_REG_V1, - }; - - static const struct udevice_id mtk_pwm_ids[] = { - { .compatible = "mediatek,mt7622-pwm", .data = (ulong)&mt7622_data }, - { .compatible = "mediatek,mt7623-pwm", .data = (ulong)&mt7623_data }, - { .compatible = "mediatek,mt7629-pwm", .data = (ulong)&mt7629_data }, -+ { .compatible = "mediatek,mt7981-pwm", .data = (ulong)&mt7981_data }, - { .compatible = "mediatek,mt7986-pwm", .data = (ulong)&mt7986_data }, - { } - }; diff --git a/package/boot/uboot-mediatek/patches/002-0014-timer-mtk-add-support-for-MediaTek-MT7981-MT7986-SoC.patch b/package/boot/uboot-mediatek/patches/002-0014-timer-mtk-add-support-for-MediaTek-MT7981-MT7986-SoC.patch deleted file mode 100644 index d02841951da..00000000000 --- a/package/boot/uboot-mediatek/patches/002-0014-timer-mtk-add-support-for-MediaTek-MT7981-MT7986-SoC.patch +++ /dev/null @@ -1,119 +0,0 @@ -From a77b8f6d9aa90f80090e505d823a6dcf6b877136 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 31 Aug 2022 19:04:40 +0800 -Subject: [PATCH 14/32] timer: mtk: add support for MediaTek MT7981/MT7986 SoCs - -This patch add general-purpose timer support for MediaTek MT7981/MT7986. -These two SoCs uses a newer version of timer with its register definition -slightly changed. - -Reviewed-by: Simon Glass -Signed-off-by: Weijie Gao ---- - drivers/timer/mtk_timer.c | 59 ++++++++++++++++++++++++--------------- - 1 file changed, 37 insertions(+), 22 deletions(-) - ---- a/drivers/timer/mtk_timer.c -+++ b/drivers/timer/mtk_timer.c -@@ -13,24 +13,32 @@ - #include - #include - --#define MTK_GPT4_CTRL 0x40 --#define MTK_GPT4_CLK 0x44 --#define MTK_GPT4_CNT 0x48 -- --#define GPT4_ENABLE BIT(0) --#define GPT4_CLEAR BIT(1) --#define GPT4_FREERUN GENMASK(5, 4) --#define GPT4_CLK_SYS 0x0 --#define GPT4_CLK_DIV1 0x0 -+#define MTK_GPT4_OFFSET_V1 0x40 -+#define MTK_GPT4_OFFSET_V2 0x80 -+ -+#define MTK_GPT_CON 0x0 -+#define MTK_GPT_V1_CLK 0x4 -+#define MTK_GPT_CNT 0x8 -+ -+#define GPT_ENABLE BIT(0) -+#define GPT_CLEAR BIT(1) -+#define GPT_V1_FREERUN GENMASK(5, 4) -+#define GPT_V2_FREERUN GENMASK(6, 5) -+ -+enum mtk_gpt_ver { -+ MTK_GPT_V1, -+ MTK_GPT_V2 -+}; - - struct mtk_timer_priv { - void __iomem *base; -+ unsigned int gpt4_offset; - }; - - static u64 mtk_timer_get_count(struct udevice *dev) - { - struct mtk_timer_priv *priv = dev_get_priv(dev); -- u32 val = readl(priv->base + MTK_GPT4_CNT); -+ u32 val = readl(priv->base + priv->gpt4_offset + MTK_GPT_CNT); - - return timer_conv_64(val); - } -@@ -40,12 +48,27 @@ static int mtk_timer_probe(struct udevic - struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); - struct mtk_timer_priv *priv = dev_get_priv(dev); - struct clk clk, parent; -- int ret; -+ int ret, gpt_ver; - - priv->base = dev_read_addr_ptr(dev); -+ gpt_ver = dev_get_driver_data(dev); -+ - if (!priv->base) - return -ENOENT; - -+ if (gpt_ver == MTK_GPT_V2) { -+ priv->gpt4_offset = MTK_GPT4_OFFSET_V2; -+ -+ writel(GPT_V2_FREERUN | GPT_CLEAR | GPT_ENABLE, -+ priv->base + priv->gpt4_offset + MTK_GPT_CON); -+ } else { -+ priv->gpt4_offset = MTK_GPT4_OFFSET_V1; -+ -+ writel(GPT_V1_FREERUN | GPT_CLEAR | GPT_ENABLE, -+ priv->base + priv->gpt4_offset + MTK_GPT_CON); -+ writel(0, priv->base + priv->gpt4_offset + MTK_GPT_V1_CLK); -+ } -+ - ret = clk_get_by_index(dev, 0, &clk); - if (ret) - return ret; -@@ -61,16 +84,6 @@ static int mtk_timer_probe(struct udevic - if (!uc_priv->clock_rate) - return -EINVAL; - -- /* -- * Initialize the timer: -- * 1. set clock source to system clock with clock divider setting to 1 -- * 2. set timer mode to free running -- * 3. reset timer counter to 0 then enable the timer -- */ -- writel(GPT4_CLK_SYS | GPT4_CLK_DIV1, priv->base + MTK_GPT4_CLK); -- writel(GPT4_FREERUN | GPT4_CLEAR | GPT4_ENABLE, -- priv->base + MTK_GPT4_CTRL); -- - return 0; - } - -@@ -79,8 +92,10 @@ static const struct timer_ops mtk_timer_ - }; - - static const struct udevice_id mtk_timer_ids[] = { -- { .compatible = "mediatek,timer" }, -- { .compatible = "mediatek,mt6577-timer" }, -+ { .compatible = "mediatek,timer", .data = MTK_GPT_V1 }, -+ { .compatible = "mediatek,mt6577-timer", .data = MTK_GPT_V1 }, -+ { .compatible = "mediatek,mt7981-timer", .data = MTK_GPT_V2 }, -+ { .compatible = "mediatek,mt7986-timer", .data = MTK_GPT_V2 }, - { } - }; - diff --git a/package/boot/uboot-mediatek/patches/002-0015-watchdog-mediatek-add-support-for-MediaTek-MT7986-So.patch b/package/boot/uboot-mediatek/patches/002-0015-watchdog-mediatek-add-support-for-MediaTek-MT7986-So.patch deleted file mode 100644 index 3215d17050c..00000000000 --- a/package/boot/uboot-mediatek/patches/002-0015-watchdog-mediatek-add-support-for-MediaTek-MT7986-So.patch +++ /dev/null @@ -1,23 +0,0 @@ -From 18f761770d7aa53abf187fa64bbd92f0682d154c Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 31 Aug 2022 19:04:42 +0800 -Subject: [PATCH 15/32] watchdog: mediatek: add support for MediaTek MT7986 SoC - -Add watchdog support for MediaTek MT7986 SoC - -Reviewed-by: Simon Glass -Signed-off-by: Weijie Gao ---- - drivers/watchdog/mtk_wdt.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/watchdog/mtk_wdt.c -+++ b/drivers/watchdog/mtk_wdt.c -@@ -145,6 +145,7 @@ static const struct wdt_ops mtk_wdt_ops - static const struct udevice_id mtk_wdt_ids[] = { - { .compatible = "mediatek,wdt"}, - { .compatible = "mediatek,mt6589-wdt"}, -+ { .compatible = "mediatek,mt7986-wdt" }, - {} - }; - diff --git a/package/boot/uboot-mediatek/patches/002-0016-spi-add-support-for-MediaTek-spi-mem-controller.patch b/package/boot/uboot-mediatek/patches/002-0016-spi-add-support-for-MediaTek-spi-mem-controller.patch deleted file mode 100644 index a1d009d3aec..00000000000 --- a/package/boot/uboot-mediatek/patches/002-0016-spi-add-support-for-MediaTek-spi-mem-controller.patch +++ /dev/null @@ -1,748 +0,0 @@ -From e6b225ff8990635dc2d6d8dbd72e78dec1f36c62 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 31 Aug 2022 19:04:45 +0800 -Subject: [PATCH 16/32] spi: add support for MediaTek spi-mem controller - -This patch adds support for spi-mem controller found on newer MediaTek SoCs -This controller supports Single/Dual/Quad SPI mode. - -Reviewed-by: Simon Glass -Signed-off-by: SkyLake.Huang ---- - drivers/spi/Kconfig | 8 + - drivers/spi/Makefile | 1 + - drivers/spi/mtk_spim.c | 701 +++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 710 insertions(+) - create mode 100644 drivers/spi/mtk_spim.c - ---- a/drivers/spi/Kconfig -+++ b/drivers/spi/Kconfig -@@ -276,6 +276,14 @@ config MTK_SNFI_SPI - used to access SPI memory devices like SPI-NOR or SPI-NAND on - platforms embedding this IP core, like MT7622/M7629. - -+config MTK_SPIM -+ bool "Mediatek SPI-MEM master controller driver" -+ depends on SPI_MEM -+ help -+ Enable MediaTek SPI-MEM master controller driver. This driver mainly -+ supports SPI flashes. You can use single, dual or quad mode -+ transmission on this controller. -+ - config MVEBU_A3700_SPI - bool "Marvell Armada 3700 SPI driver" - select CLK_ARMADA_3720 ---- a/drivers/spi/Makefile -+++ b/drivers/spi/Makefile -@@ -43,6 +43,7 @@ obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o - obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o - obj-$(CONFIG_MTK_SNFI_SPI) += mtk_snfi_spi.o - obj-$(CONFIG_MTK_SNOR) += mtk_snor.o -+obj-$(CONFIG_MTK_SPIM) += mtk_spim.o - obj-$(CONFIG_MT7620_SPI) += mt7620_spi.o - obj-$(CONFIG_MT7621_SPI) += mt7621_spi.o - obj-$(CONFIG_MSCC_BB_SPI) += mscc_bb_spi.o ---- /dev/null -+++ b/drivers/spi/mtk_spim.c -@@ -0,0 +1,701 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (C) 2022 MediaTek Inc. All Rights Reserved. -+ * -+ * Author: SkyLake.Huang -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define SPI_CFG0_REG 0x0000 -+#define SPI_CFG1_REG 0x0004 -+#define SPI_TX_SRC_REG 0x0008 -+#define SPI_RX_DST_REG 0x000c -+#define SPI_TX_DATA_REG 0x0010 -+#define SPI_RX_DATA_REG 0x0014 -+#define SPI_CMD_REG 0x0018 -+#define SPI_IRQ_REG 0x001c -+#define SPI_STATUS_REG 0x0020 -+#define SPI_PAD_SEL_REG 0x0024 -+#define SPI_CFG2_REG 0x0028 -+#define SPI_TX_SRC_REG_64 0x002c -+#define SPI_RX_DST_REG_64 0x0030 -+#define SPI_CFG3_IPM_REG 0x0040 -+ -+#define SPI_CFG0_SCK_HIGH_OFFSET 0 -+#define SPI_CFG0_SCK_LOW_OFFSET 8 -+#define SPI_CFG0_CS_HOLD_OFFSET 16 -+#define SPI_CFG0_CS_SETUP_OFFSET 24 -+#define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0 -+#define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16 -+ -+#define SPI_CFG1_CS_IDLE_OFFSET 0 -+#define SPI_CFG1_PACKET_LOOP_OFFSET 8 -+#define SPI_CFG1_PACKET_LENGTH_OFFSET 16 -+#define SPI_CFG1_GET_TICKDLY_OFFSET 29 -+ -+#define SPI_CFG1_GET_TICKDLY_MASK GENMASK(31, 29) -+#define SPI_CFG1_CS_IDLE_MASK 0xff -+#define SPI_CFG1_PACKET_LOOP_MASK 0xff00 -+#define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000 -+#define SPI_CFG1_IPM_PACKET_LENGTH_MASK GENMASK(31, 16) -+#define SPI_CFG2_SCK_HIGH_OFFSET 0 -+#define SPI_CFG2_SCK_LOW_OFFSET 16 -+#define SPI_CFG2_SCK_HIGH_MASK GENMASK(15, 0) -+#define SPI_CFG2_SCK_LOW_MASK GENMASK(31, 16) -+ -+#define SPI_CMD_ACT BIT(0) -+#define SPI_CMD_RESUME BIT(1) -+#define SPI_CMD_RST BIT(2) -+#define SPI_CMD_PAUSE_EN BIT(4) -+#define SPI_CMD_DEASSERT BIT(5) -+#define SPI_CMD_SAMPLE_SEL BIT(6) -+#define SPI_CMD_CS_POL BIT(7) -+#define SPI_CMD_CPHA BIT(8) -+#define SPI_CMD_CPOL BIT(9) -+#define SPI_CMD_RX_DMA BIT(10) -+#define SPI_CMD_TX_DMA BIT(11) -+#define SPI_CMD_TXMSBF BIT(12) -+#define SPI_CMD_RXMSBF BIT(13) -+#define SPI_CMD_RX_ENDIAN BIT(14) -+#define SPI_CMD_TX_ENDIAN BIT(15) -+#define SPI_CMD_FINISH_IE BIT(16) -+#define SPI_CMD_PAUSE_IE BIT(17) -+#define SPI_CMD_IPM_NONIDLE_MODE BIT(19) -+#define SPI_CMD_IPM_SPIM_LOOP BIT(21) -+#define SPI_CMD_IPM_GET_TICKDLY_OFFSET 22 -+ -+#define SPI_CMD_IPM_GET_TICKDLY_MASK GENMASK(24, 22) -+ -+#define PIN_MODE_CFG(x) ((x) / 2) -+ -+#define SPI_CFG3_IPM_PIN_MODE_OFFSET 0 -+#define SPI_CFG3_IPM_HALF_DUPLEX_DIR BIT(2) -+#define SPI_CFG3_IPM_HALF_DUPLEX_EN BIT(3) -+#define SPI_CFG3_IPM_XMODE_EN BIT(4) -+#define SPI_CFG3_IPM_NODATA_FLAG BIT(5) -+#define SPI_CFG3_IPM_CMD_BYTELEN_OFFSET 8 -+#define SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET 12 -+#define SPI_CFG3_IPM_DUMMY_BYTELEN_OFFSET 16 -+ -+#define SPI_CFG3_IPM_CMD_PIN_MODE_MASK GENMASK(1, 0) -+#define SPI_CFG3_IPM_CMD_BYTELEN_MASK GENMASK(11, 8) -+#define SPI_CFG3_IPM_ADDR_BYTELEN_MASK GENMASK(15, 12) -+#define SPI_CFG3_IPM_DUMMY_BYTELEN_MASK GENMASK(19, 16) -+ -+#define MT8173_SPI_MAX_PAD_SEL 3 -+ -+#define MTK_SPI_PAUSE_INT_STATUS 0x2 -+ -+#define MTK_SPI_IDLE 0 -+#define MTK_SPI_PAUSED 1 -+ -+#define MTK_SPI_MAX_FIFO_SIZE 32U -+#define MTK_SPI_PACKET_SIZE 1024 -+#define MTK_SPI_IPM_PACKET_SIZE SZ_64K -+#define MTK_SPI_IPM_PACKET_LOOP SZ_256 -+ -+#define MTK_SPI_32BITS_MASK 0xffffffff -+ -+#define DMA_ADDR_EXT_BITS 36 -+#define DMA_ADDR_DEF_BITS 32 -+ -+#define CLK_TO_US(freq, clkcnt) DIV_ROUND_UP((clkcnt), (freq) / 1000000) -+ -+/* struct mtk_spim_capability -+ * @enhance_timing: Some IC design adjust cfg register to enhance time accuracy -+ * @dma_ext: Some IC support DMA addr extension -+ * @ipm_design: The IPM IP design improves some features, and supports dual/quad mode -+ * @support_quad: Whether quad mode is supported -+ */ -+struct mtk_spim_capability { -+ bool enhance_timing; -+ bool dma_ext; -+ bool ipm_design; -+ bool support_quad; -+}; -+ -+/* struct mtk_spim_priv -+ * @base: Base address of the spi controller -+ * @state: Controller state -+ * @sel_clk: Pad clock -+ * @spi_clk: Core clock -+ * @xfer_len: Current length of data for transfer -+ * @hw_cap: Controller capabilities -+ * @tick_dly: Used to postpone SPI sampling time -+ * @sample_sel: Sample edge of MISO -+ * @dev: udevice of this spi controller -+ * @tx_dma: Tx DMA address -+ * @rx_dma: Rx DMA address -+ */ -+struct mtk_spim_priv { -+ void __iomem *base; -+ u32 state; -+ struct clk sel_clk, spi_clk; -+ u32 xfer_len; -+ struct mtk_spim_capability hw_cap; -+ u32 tick_dly; -+ u32 sample_sel; -+ -+ struct device *dev; -+ dma_addr_t tx_dma; -+ dma_addr_t rx_dma; -+}; -+ -+static void mtk_spim_reset(struct mtk_spim_priv *priv) -+{ -+ /* set the software reset bit in SPI_CMD_REG. */ -+ setbits_le32(priv->base + SPI_CMD_REG, SPI_CMD_RST); -+ clrbits_le32(priv->base + SPI_CMD_REG, SPI_CMD_RST); -+} -+ -+static int mtk_spim_hw_init(struct spi_slave *slave) -+{ -+ struct udevice *bus = dev_get_parent(slave->dev); -+ struct mtk_spim_priv *priv = dev_get_priv(bus); -+ u16 cpha, cpol; -+ u32 reg_val; -+ -+ cpha = slave->mode & SPI_CPHA ? 1 : 0; -+ cpol = slave->mode & SPI_CPOL ? 1 : 0; -+ -+ if (priv->hw_cap.enhance_timing) { -+ if (priv->hw_cap.ipm_design) { -+ /* CFG3 reg only used for spi-mem, -+ * here write to default value -+ */ -+ writel(0x0, priv->base + SPI_CFG3_IPM_REG); -+ clrsetbits_le32(priv->base + SPI_CMD_REG, -+ SPI_CMD_IPM_GET_TICKDLY_MASK, -+ priv->tick_dly << -+ SPI_CMD_IPM_GET_TICKDLY_OFFSET); -+ } else { -+ clrsetbits_le32(priv->base + SPI_CFG1_REG, -+ SPI_CFG1_GET_TICKDLY_MASK, -+ priv->tick_dly << -+ SPI_CFG1_GET_TICKDLY_OFFSET); -+ } -+ } -+ -+ reg_val = readl(priv->base + SPI_CMD_REG); -+ if (priv->hw_cap.ipm_design) { -+ /* SPI transfer without idle time until packet length done */ -+ reg_val |= SPI_CMD_IPM_NONIDLE_MODE; -+ if (slave->mode & SPI_LOOP) -+ reg_val |= SPI_CMD_IPM_SPIM_LOOP; -+ else -+ reg_val &= ~SPI_CMD_IPM_SPIM_LOOP; -+ } -+ -+ if (cpha) -+ reg_val |= SPI_CMD_CPHA; -+ else -+ reg_val &= ~SPI_CMD_CPHA; -+ if (cpol) -+ reg_val |= SPI_CMD_CPOL; -+ else -+ reg_val &= ~SPI_CMD_CPOL; -+ -+ /* set the mlsbx and mlsbtx */ -+ if (slave->mode & SPI_LSB_FIRST) { -+ reg_val &= ~SPI_CMD_TXMSBF; -+ reg_val &= ~SPI_CMD_RXMSBF; -+ } else { -+ reg_val |= SPI_CMD_TXMSBF; -+ reg_val |= SPI_CMD_RXMSBF; -+ } -+ -+ /* do not reverse tx/rx endian */ -+ reg_val &= ~SPI_CMD_TX_ENDIAN; -+ reg_val &= ~SPI_CMD_RX_ENDIAN; -+ -+ if (priv->hw_cap.enhance_timing) { -+ /* set CS polarity */ -+ if (slave->mode & SPI_CS_HIGH) -+ reg_val |= SPI_CMD_CS_POL; -+ else -+ reg_val &= ~SPI_CMD_CS_POL; -+ -+ if (priv->sample_sel) -+ reg_val |= SPI_CMD_SAMPLE_SEL; -+ else -+ reg_val &= ~SPI_CMD_SAMPLE_SEL; -+ } -+ -+ /* disable dma mode */ -+ reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA); -+ -+ /* disable deassert mode */ -+ reg_val &= ~SPI_CMD_DEASSERT; -+ -+ writel(reg_val, priv->base + SPI_CMD_REG); -+ -+ return 0; -+} -+ -+static void mtk_spim_prepare_transfer(struct mtk_spim_priv *priv, -+ u32 speed_hz) -+{ -+ u32 spi_clk_hz, div, sck_time, cs_time, reg_val; -+ -+ spi_clk_hz = clk_get_rate(&priv->spi_clk); -+ if (speed_hz <= spi_clk_hz / 4) -+ div = DIV_ROUND_UP(spi_clk_hz, speed_hz); -+ else -+ div = 4; -+ -+ sck_time = (div + 1) / 2; -+ cs_time = sck_time * 2; -+ -+ if (priv->hw_cap.enhance_timing) { -+ reg_val = ((sck_time - 1) & 0xffff) -+ << SPI_CFG2_SCK_HIGH_OFFSET; -+ reg_val |= ((sck_time - 1) & 0xffff) -+ << SPI_CFG2_SCK_LOW_OFFSET; -+ writel(reg_val, priv->base + SPI_CFG2_REG); -+ -+ reg_val = ((cs_time - 1) & 0xffff) -+ << SPI_ADJUST_CFG0_CS_HOLD_OFFSET; -+ reg_val |= ((cs_time - 1) & 0xffff) -+ << SPI_ADJUST_CFG0_CS_SETUP_OFFSET; -+ writel(reg_val, priv->base + SPI_CFG0_REG); -+ } else { -+ reg_val = ((sck_time - 1) & 0xff) -+ << SPI_CFG0_SCK_HIGH_OFFSET; -+ reg_val |= ((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET; -+ reg_val |= ((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET; -+ reg_val |= ((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET; -+ writel(reg_val, priv->base + SPI_CFG0_REG); -+ } -+ -+ reg_val = readl(priv->base + SPI_CFG1_REG); -+ reg_val &= ~SPI_CFG1_CS_IDLE_MASK; -+ reg_val |= ((cs_time - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET; -+ writel(reg_val, priv->base + SPI_CFG1_REG); -+} -+ -+/** -+ * mtk_spim_setup_packet() - setup packet format. -+ * @priv: controller priv -+ * -+ * This controller sents/receives data in packets. The packet size is -+ * configurable. -+ * -+ * This function calculates the maximum packet size available for current -+ * data, and calculates the number of packets required to sent/receive data -+ * as much as possible. -+ */ -+static void mtk_spim_setup_packet(struct mtk_spim_priv *priv) -+{ -+ u32 packet_size, packet_loop, reg_val; -+ -+ /* Calculate maximum packet size */ -+ if (priv->hw_cap.ipm_design) -+ packet_size = min_t(u32, -+ priv->xfer_len, -+ MTK_SPI_IPM_PACKET_SIZE); -+ else -+ packet_size = min_t(u32, -+ priv->xfer_len, -+ MTK_SPI_PACKET_SIZE); -+ -+ /* Calculates number of packets to sent/receive */ -+ packet_loop = priv->xfer_len / packet_size; -+ -+ reg_val = readl(priv->base + SPI_CFG1_REG); -+ if (priv->hw_cap.ipm_design) -+ reg_val &= ~SPI_CFG1_IPM_PACKET_LENGTH_MASK; -+ else -+ reg_val &= ~SPI_CFG1_PACKET_LENGTH_MASK; -+ -+ reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET; -+ -+ reg_val &= ~SPI_CFG1_PACKET_LOOP_MASK; -+ -+ reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET; -+ -+ writel(reg_val, priv->base + SPI_CFG1_REG); -+} -+ -+static void mtk_spim_enable_transfer(struct mtk_spim_priv *priv) -+{ -+ u32 cmd; -+ -+ cmd = readl(priv->base + SPI_CMD_REG); -+ if (priv->state == MTK_SPI_IDLE) -+ cmd |= SPI_CMD_ACT; -+ else -+ cmd |= SPI_CMD_RESUME; -+ writel(cmd, priv->base + SPI_CMD_REG); -+} -+ -+static bool mtk_spim_supports_op(struct spi_slave *slave, -+ const struct spi_mem_op *op) -+{ -+ struct udevice *bus = dev_get_parent(slave->dev); -+ struct mtk_spim_priv *priv = dev_get_priv(bus); -+ -+ if (op->cmd.buswidth == 0 || op->cmd.buswidth > 4 || -+ op->addr.buswidth > 4 || op->dummy.buswidth > 4 || -+ op->data.buswidth > 4) -+ return false; -+ -+ if (!priv->hw_cap.support_quad && (op->cmd.buswidth > 2 || -+ op->addr.buswidth > 2 || op->dummy.buswidth > 2 || -+ op->data.buswidth > 2)) -+ return false; -+ -+ if (op->addr.nbytes && op->dummy.nbytes && -+ op->addr.buswidth != op->dummy.buswidth) -+ return false; -+ -+ if (op->addr.nbytes + op->dummy.nbytes > 16) -+ return false; -+ -+ if (op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) { -+ if (op->data.nbytes / MTK_SPI_IPM_PACKET_SIZE > -+ MTK_SPI_IPM_PACKET_LOOP || -+ op->data.nbytes % MTK_SPI_IPM_PACKET_SIZE != 0) -+ return false; -+ } -+ -+ return true; -+} -+ -+static void mtk_spim_setup_dma_xfer(struct mtk_spim_priv *priv, -+ const struct spi_mem_op *op) -+{ -+ writel((u32)(priv->tx_dma & MTK_SPI_32BITS_MASK), -+ priv->base + SPI_TX_SRC_REG); -+ -+ if (priv->hw_cap.dma_ext) -+ writel((u32)(priv->tx_dma >> 32), -+ priv->base + SPI_TX_SRC_REG_64); -+ -+ if (op->data.dir == SPI_MEM_DATA_IN) { -+ writel((u32)(priv->rx_dma & MTK_SPI_32BITS_MASK), -+ priv->base + SPI_RX_DST_REG); -+ -+ if (priv->hw_cap.dma_ext) -+ writel((u32)(priv->rx_dma >> 32), -+ priv->base + SPI_RX_DST_REG_64); -+ } -+} -+ -+static int mtk_spim_transfer_wait(struct spi_slave *slave, -+ const struct spi_mem_op *op) -+{ -+ struct udevice *bus = dev_get_parent(slave->dev); -+ struct mtk_spim_priv *priv = dev_get_priv(bus); -+ u32 sck_l, sck_h, spi_bus_clk, clk_count, reg; -+ ulong us = 1; -+ int ret = 0; -+ -+ if (op->data.dir == SPI_MEM_NO_DATA) -+ clk_count = 32; -+ else -+ clk_count = op->data.nbytes; -+ -+ spi_bus_clk = clk_get_rate(&priv->spi_clk); -+ sck_l = readl(priv->base + SPI_CFG2_REG) >> SPI_CFG2_SCK_LOW_OFFSET; -+ sck_h = readl(priv->base + SPI_CFG2_REG) & SPI_CFG2_SCK_HIGH_MASK; -+ do_div(spi_bus_clk, sck_l + sck_h + 2); -+ -+ us = CLK_TO_US(spi_bus_clk, clk_count * 8); -+ us += 1000 * 1000; /* 1s tolerance */ -+ -+ if (us > UINT_MAX) -+ us = UINT_MAX; -+ -+ ret = readl_poll_timeout(priv->base + SPI_STATUS_REG, reg, -+ reg & 0x1, us); -+ if (ret < 0) { -+ dev_err(priv->dev, "transfer timeout, val: 0x%lx\n", us); -+ return -ETIMEDOUT; -+ } -+ -+ return 0; -+} -+ -+static int mtk_spim_exec_op(struct spi_slave *slave, -+ const struct spi_mem_op *op) -+{ -+ struct udevice *bus = dev_get_parent(slave->dev); -+ struct mtk_spim_priv *priv = dev_get_priv(bus); -+ u32 reg_val, nio = 1, tx_size; -+ char *tx_tmp_buf; -+ char *rx_tmp_buf; -+ int i, ret = 0; -+ -+ mtk_spim_reset(priv); -+ mtk_spim_hw_init(slave); -+ mtk_spim_prepare_transfer(priv, slave->max_hz); -+ -+ reg_val = readl(priv->base + SPI_CFG3_IPM_REG); -+ /* opcode byte len */ -+ reg_val &= ~SPI_CFG3_IPM_CMD_BYTELEN_MASK; -+ reg_val |= 1 << SPI_CFG3_IPM_CMD_BYTELEN_OFFSET; -+ -+ /* addr & dummy byte len */ -+ if (op->addr.nbytes || op->dummy.nbytes) -+ reg_val |= (op->addr.nbytes + op->dummy.nbytes) << -+ SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET; -+ -+ /* data byte len */ -+ if (!op->data.nbytes) { -+ reg_val |= SPI_CFG3_IPM_NODATA_FLAG; -+ writel(0, priv->base + SPI_CFG1_REG); -+ } else { -+ reg_val &= ~SPI_CFG3_IPM_NODATA_FLAG; -+ priv->xfer_len = op->data.nbytes; -+ mtk_spim_setup_packet(priv); -+ } -+ -+ if (op->addr.nbytes || op->dummy.nbytes) { -+ if (op->addr.buswidth == 1 || op->dummy.buswidth == 1) -+ reg_val |= SPI_CFG3_IPM_XMODE_EN; -+ else -+ reg_val &= ~SPI_CFG3_IPM_XMODE_EN; -+ } -+ -+ if (op->addr.buswidth == 2 || -+ op->dummy.buswidth == 2 || -+ op->data.buswidth == 2) -+ nio = 2; -+ else if (op->addr.buswidth == 4 || -+ op->dummy.buswidth == 4 || -+ op->data.buswidth == 4) -+ nio = 4; -+ -+ reg_val &= ~SPI_CFG3_IPM_CMD_PIN_MODE_MASK; -+ reg_val |= PIN_MODE_CFG(nio) << SPI_CFG3_IPM_PIN_MODE_OFFSET; -+ -+ reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN; -+ if (op->data.dir == SPI_MEM_DATA_IN) -+ reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR; -+ else -+ reg_val &= ~SPI_CFG3_IPM_HALF_DUPLEX_DIR; -+ writel(reg_val, priv->base + SPI_CFG3_IPM_REG); -+ -+ tx_size = 1 + op->addr.nbytes + op->dummy.nbytes; -+ if (op->data.dir == SPI_MEM_DATA_OUT) -+ tx_size += op->data.nbytes; -+ -+ tx_size = max(tx_size, (u32)32); -+ -+ /* Fill up tx data */ -+ tx_tmp_buf = kzalloc(tx_size, GFP_KERNEL); -+ if (!tx_tmp_buf) { -+ ret = -ENOMEM; -+ goto exit; -+ } -+ -+ tx_tmp_buf[0] = op->cmd.opcode; -+ -+ if (op->addr.nbytes) { -+ for (i = 0; i < op->addr.nbytes; i++) -+ tx_tmp_buf[i + 1] = op->addr.val >> -+ (8 * (op->addr.nbytes - i - 1)); -+ } -+ -+ if (op->dummy.nbytes) -+ memset(tx_tmp_buf + op->addr.nbytes + 1, 0xff, -+ op->dummy.nbytes); -+ -+ if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) -+ memcpy(tx_tmp_buf + op->dummy.nbytes + op->addr.nbytes + 1, -+ op->data.buf.out, op->data.nbytes); -+ /* Finish filling up tx data */ -+ -+ priv->tx_dma = dma_map_single(tx_tmp_buf, tx_size, DMA_TO_DEVICE); -+ if (dma_mapping_error(priv->dev, priv->tx_dma)) { -+ ret = -ENOMEM; -+ goto tx_free; -+ } -+ -+ if (op->data.dir == SPI_MEM_DATA_IN) { -+ if (!IS_ALIGNED((size_t)op->data.buf.in, 4)) { -+ rx_tmp_buf = kzalloc(op->data.nbytes, GFP_KERNEL); -+ if (!rx_tmp_buf) { -+ ret = -ENOMEM; -+ goto tx_unmap; -+ } -+ } else { -+ rx_tmp_buf = op->data.buf.in; -+ } -+ -+ priv->rx_dma = dma_map_single(rx_tmp_buf, op->data.nbytes, -+ DMA_FROM_DEVICE); -+ if (dma_mapping_error(priv->dev, priv->rx_dma)) { -+ ret = -ENOMEM; -+ goto rx_free; -+ } -+ } -+ -+ reg_val = readl(priv->base + SPI_CMD_REG); -+ reg_val |= SPI_CMD_TX_DMA; -+ if (op->data.dir == SPI_MEM_DATA_IN) -+ reg_val |= SPI_CMD_RX_DMA; -+ -+ writel(reg_val, priv->base + SPI_CMD_REG); -+ -+ mtk_spim_setup_dma_xfer(priv, op); -+ -+ mtk_spim_enable_transfer(priv); -+ -+ /* Wait for the interrupt. */ -+ ret = mtk_spim_transfer_wait(slave, op); -+ if (ret) -+ goto rx_unmap; -+ -+ if (op->data.dir == SPI_MEM_DATA_IN && -+ !IS_ALIGNED((size_t)op->data.buf.in, 4)) -+ memcpy(op->data.buf.in, rx_tmp_buf, op->data.nbytes); -+ -+rx_unmap: -+ /* spi disable dma */ -+ reg_val = readl(priv->base + SPI_CMD_REG); -+ reg_val &= ~SPI_CMD_TX_DMA; -+ if (op->data.dir == SPI_MEM_DATA_IN) -+ reg_val &= ~SPI_CMD_RX_DMA; -+ writel(reg_val, priv->base + SPI_CMD_REG); -+ -+ writel(0, priv->base + SPI_TX_SRC_REG); -+ writel(0, priv->base + SPI_RX_DST_REG); -+ -+ if (op->data.dir == SPI_MEM_DATA_IN) -+ dma_unmap_single(priv->rx_dma, -+ op->data.nbytes, DMA_FROM_DEVICE); -+rx_free: -+ if (op->data.dir == SPI_MEM_DATA_IN && -+ !IS_ALIGNED((size_t)op->data.buf.in, 4)) -+ kfree(rx_tmp_buf); -+tx_unmap: -+ dma_unmap_single(priv->tx_dma, -+ tx_size, DMA_TO_DEVICE); -+tx_free: -+ kfree(tx_tmp_buf); -+exit: -+ return ret; -+} -+ -+static int mtk_spim_adjust_op_size(struct spi_slave *slave, -+ struct spi_mem_op *op) -+{ -+ int opcode_len; -+ -+ if (!op->data.nbytes) -+ return 0; -+ -+ if (op->data.dir != SPI_MEM_NO_DATA) { -+ opcode_len = 1 + op->addr.nbytes + op->dummy.nbytes; -+ if (opcode_len + op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) { -+ op->data.nbytes = MTK_SPI_IPM_PACKET_SIZE - opcode_len; -+ /* force data buffer dma-aligned. */ -+ op->data.nbytes -= op->data.nbytes % 4; -+ } -+ } -+ -+ return 0; -+} -+ -+static int mtk_spim_get_attr(struct mtk_spim_priv *priv, struct udevice *dev) -+{ -+ int ret; -+ -+ priv->hw_cap.enhance_timing = dev_read_bool(dev, "enhance_timing"); -+ priv->hw_cap.dma_ext = dev_read_bool(dev, "dma_ext"); -+ priv->hw_cap.ipm_design = dev_read_bool(dev, "ipm_design"); -+ priv->hw_cap.support_quad = dev_read_bool(dev, "support_quad"); -+ -+ ret = dev_read_u32(dev, "tick_dly", &priv->tick_dly); -+ if (ret < 0) -+ dev_err(priv->dev, "tick dly not set.\n"); -+ -+ ret = dev_read_u32(dev, "sample_sel", &priv->sample_sel); -+ if (ret < 0) -+ dev_err(priv->dev, "sample sel not set.\n"); -+ -+ return ret; -+} -+ -+static int mtk_spim_probe(struct udevice *dev) -+{ -+ struct mtk_spim_priv *priv = dev_get_priv(dev); -+ int ret; -+ -+ priv->base = (void __iomem *)devfdt_get_addr(dev); -+ if (!priv->base) -+ return -EINVAL; -+ -+ mtk_spim_get_attr(priv, dev); -+ -+ ret = clk_get_by_name(dev, "sel-clk", &priv->sel_clk); -+ if (ret < 0) { -+ dev_err(dev, "failed to get sel-clk\n"); -+ return ret; -+ } -+ -+ ret = clk_get_by_name(dev, "spi-clk", &priv->spi_clk); -+ if (ret < 0) { -+ dev_err(dev, "failed to get spi-clk\n"); -+ return ret; -+ } -+ -+ clk_enable(&priv->sel_clk); -+ clk_enable(&priv->spi_clk); -+ -+ return 0; -+} -+ -+static int mtk_spim_set_speed(struct udevice *dev, uint speed) -+{ -+ return 0; -+} -+ -+static int mtk_spim_set_mode(struct udevice *dev, uint mode) -+{ -+ return 0; -+} -+ -+static const struct spi_controller_mem_ops mtk_spim_mem_ops = { -+ .adjust_op_size = mtk_spim_adjust_op_size, -+ .supports_op = mtk_spim_supports_op, -+ .exec_op = mtk_spim_exec_op -+}; -+ -+static const struct dm_spi_ops mtk_spim_ops = { -+ .mem_ops = &mtk_spim_mem_ops, -+ .set_speed = mtk_spim_set_speed, -+ .set_mode = mtk_spim_set_mode, -+}; -+ -+static const struct udevice_id mtk_spim_ids[] = { -+ { .compatible = "mediatek,ipm-spi" }, -+ {} -+}; -+ -+U_BOOT_DRIVER(mtk_spim) = { -+ .name = "mtk_spim", -+ .id = UCLASS_SPI, -+ .of_match = mtk_spim_ids, -+ .ops = &mtk_spim_ops, -+ .priv_auto = sizeof(struct mtk_spim_priv), -+ .probe = mtk_spim_probe, -+}; diff --git a/package/boot/uboot-mediatek/patches/002-0017-i2c-add-support-for-MediaTek-I2C-interface.patch b/package/boot/uboot-mediatek/patches/002-0017-i2c-add-support-for-MediaTek-I2C-interface.patch deleted file mode 100644 index 7146e3fac34..00000000000 --- a/package/boot/uboot-mediatek/patches/002-0017-i2c-add-support-for-MediaTek-I2C-interface.patch +++ /dev/null @@ -1,870 +0,0 @@ -From 987dc8d079cd399e753e10fce12d526b42f90ed0 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 31 Aug 2022 19:04:47 +0800 -Subject: [PATCH 17/32] i2c: add support for MediaTek I2C interface - -This patch adds support for MediaTek I2C interface - -Reviewed-by: Heiko Schocher -Reviewed-by: Simon Glass -Signed-off-by: Weijie Gao ---- - drivers/i2c/Kconfig | 9 + - drivers/i2c/Makefile | 1 + - drivers/i2c/mtk_i2c.c | 822 ++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 832 insertions(+) - create mode 100644 drivers/i2c/mtk_i2c.c - ---- a/drivers/i2c/Kconfig -+++ b/drivers/i2c/Kconfig -@@ -261,6 +261,15 @@ config SYS_I2C_MESON - internal buffer holding up to 8 bytes for transfers and supports - both 7-bit and 10-bit addresses. - -+config SYS_I2C_MTK -+ bool "MediaTek I2C driver" -+ help -+ This selects the MediaTek Integrated Inter Circuit bus driver. -+ The I2C bus adapter is the base for some other I2C client, -+ eg: touch, sensors. -+ If you want to use MediaTek I2C interface, say Y here. -+ If unsure, say N. -+ - config SYS_I2C_MICROCHIP - bool "Microchip I2C driver" - help ---- a/drivers/i2c/Makefile -+++ b/drivers/i2c/Makefile -@@ -32,6 +32,7 @@ obj-$(CONFIG_SYS_I2C_MICROCHIP) += i2c-m - obj-$(CONFIG_SYS_I2C_MV) += mv_i2c.o - obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o - obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o -+obj-$(CONFIG_SYS_I2C_MTK) += mtk_i2c.o - obj-$(CONFIG_SYS_I2C_NEXELL) += nx_i2c.o - obj-$(CONFIG_SYS_I2C_NPCM) += npcm_i2c.o - obj-$(CONFIG_SYS_I2C_OCORES) += ocores_i2c.o ---- /dev/null -+++ b/drivers/i2c/mtk_i2c.c -@@ -0,0 +1,822 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (C) 2022 MediaTek Inc. All Rights Reserved. -+ * -+ * Author: Mingming Lee -+ * -+ * MediaTek I2C Interface driver -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define I2C_RS_TRANSFER BIT(4) -+#define I2C_HS_NACKERR BIT(2) -+#define I2C_ACKERR BIT(1) -+#define I2C_TRANSAC_COMP BIT(0) -+#define I2C_TRANSAC_START BIT(0) -+#define I2C_RS_MUL_CNFG BIT(15) -+#define I2C_RS_MUL_TRIG BIT(14) -+#define I2C_DCM_DISABLE 0x0000 -+#define I2C_IO_CONFIG_OPEN_DRAIN 0x0003 -+#define I2C_IO_CONFIG_PUSH_PULL 0x0000 -+#define I2C_SOFT_RST 0x0001 -+#define I2C_FIFO_ADDR_CLR 0x0001 -+#define I2C_DELAY_LEN 0x0002 -+#define I2C_ST_START_CON 0x8001 -+#define I2C_FS_START_CON 0x1800 -+#define I2C_TIME_CLR_VALUE 0x0000 -+#define I2C_TIME_DEFAULT_VALUE 0x0003 -+#define I2C_WRRD_TRANAC_VALUE 0x0002 -+#define I2C_RD_TRANAC_VALUE 0x0001 -+ -+#define I2C_DMA_CON_TX 0x0000 -+#define I2C_DMA_CON_RX 0x0001 -+#define I2C_DMA_START_EN 0x0001 -+#define I2C_DMA_INT_FLAG_NONE 0x0000 -+#define I2C_DMA_CLR_FLAG 0x0000 -+#define I2C_DMA_TX_RX 0x0000 -+#define I2C_DMA_HARD_RST 0x0002 -+ -+#define MAX_ST_MODE_SPEED 100000 -+#define MAX_FS_MODE_SPEED 400000 -+#define MAX_HS_MODE_SPEED 3400000 -+#define MAX_SAMPLE_CNT_DIV 8 -+#define MAX_STEP_CNT_DIV 64 -+#define MAX_HS_STEP_CNT_DIV 8 -+#define I2C_DEFAULT_CLK_DIV 4 -+ -+#define MAX_I2C_ADDR 0x7f -+#define MAX_I2C_LEN 0xff -+#define TRANS_ADDR_ONLY BIT(8) -+#define TRANSFER_TIMEOUT 50000 /* us */ -+#define I2C_FIFO_STAT1_MASK 0x001f -+#define TIMING_SAMPLE_OFFSET 8 -+#define HS_SAMPLE_OFFSET 12 -+#define HS_STEP_OFFSET 8 -+ -+#define I2C_CONTROL_WRAPPER BIT(0) -+#define I2C_CONTROL_RS BIT(1) -+#define I2C_CONTROL_DMA_EN BIT(2) -+#define I2C_CONTROL_CLK_EXT_EN BIT(3) -+#define I2C_CONTROL_DIR_CHANGE BIT(4) -+#define I2C_CONTROL_ACKERR_DET_EN BIT(5) -+#define I2C_CONTROL_TRANSFER_LEN_CHANGE BIT(6) -+#define I2C_CONTROL_DMAACK BIT(8) -+#define I2C_CONTROL_ASYNC BIT(9) -+ -+#define I2C_MASTER_WR BIT(0) -+#define I2C_MASTER_RD BIT(1) -+#define I2C_MASTER_WRRD (I2C_MASTER_WR | I2C_MASTER_RD) -+ -+enum I2C_REGS_OFFSET { -+ REG_PORT, -+ REG_SLAVE_ADDR, -+ REG_INTR_MASK, -+ REG_INTR_STAT, -+ REG_CONTROL, -+ REG_TRANSFER_LEN, -+ REG_TRANSAC_LEN, -+ REG_DELAY_LEN, -+ REG_TIMING, -+ REG_START, -+ REG_EXT_CONF, -+ REG_FIFO_STAT1, -+ REG_LTIMING, -+ REG_FIFO_STAT, -+ REG_FIFO_THRESH, -+ REG_FIFO_ADDR_CLR, -+ REG_IO_CONFIG, -+ REG_RSV_DEBUG, -+ REG_HS, -+ REG_SOFTRESET, -+ REG_DCM_EN, -+ REG_PATH_DIR, -+ REG_DEBUGSTAT, -+ REG_DEBUGCTRL, -+ REG_TRANSFER_LEN_AUX, -+ REG_CLOCK_DIV, -+ REG_SCL_HL_RATIO, -+ REG_SCL_HS_HL_RATIO, -+ REG_SCL_MIS_COMP_POINT, -+ REG_STA_STOP_AC_TIME, -+ REG_HS_STA_STOP_AC_TIME, -+ REG_DATA_TIME, -+}; -+ -+enum DMA_REGS_OFFSET { -+ REG_INT_FLAG = 0x0, -+ REG_INT_EN = 0x04, -+ REG_EN = 0x08, -+ REG_RST = 0x0c, -+ REG_CON = 0x18, -+ REG_TX_MEM_ADDR = 0x1c, -+ REG_RX_MEM_ADDR = 0x20, -+ REG_TX_LEN = 0x24, -+ REG_RX_LEN = 0x28, -+}; -+ -+static const uint mt_i2c_regs_v1[] = { -+ [REG_PORT] = 0x0, -+ [REG_SLAVE_ADDR] = 0x4, -+ [REG_INTR_MASK] = 0x8, -+ [REG_INTR_STAT] = 0xc, -+ [REG_CONTROL] = 0x10, -+ [REG_TRANSFER_LEN] = 0x14, -+ [REG_TRANSAC_LEN] = 0x18, -+ [REG_DELAY_LEN] = 0x1c, -+ [REG_TIMING] = 0x20, -+ [REG_START] = 0x24, -+ [REG_EXT_CONF] = 0x28, -+ [REG_FIFO_STAT1] = 0x2c, -+ [REG_FIFO_STAT] = 0x30, -+ [REG_FIFO_THRESH] = 0x34, -+ [REG_FIFO_ADDR_CLR] = 0x38, -+ [REG_IO_CONFIG] = 0x40, -+ [REG_RSV_DEBUG] = 0x44, -+ [REG_HS] = 0x48, -+ [REG_SOFTRESET] = 0x50, -+ [REG_SOFTRESET] = 0x50, -+ [REG_DCM_EN] = 0x54, -+ [REG_DEBUGSTAT] = 0x64, -+ [REG_DEBUGCTRL] = 0x68, -+ [REG_TRANSFER_LEN_AUX] = 0x6c, -+ [REG_CLOCK_DIV] = 0x70, -+ [REG_SCL_HL_RATIO] = 0x74, -+ [REG_SCL_HS_HL_RATIO] = 0x78, -+ [REG_SCL_MIS_COMP_POINT] = 0x7c, -+ [REG_STA_STOP_AC_TIME] = 0x80, -+ [REG_HS_STA_STOP_AC_TIME] = 0x84, -+ [REG_DATA_TIME] = 0x88, -+}; -+ -+static const uint mt_i2c_regs_v2[] = { -+ [REG_PORT] = 0x0, -+ [REG_SLAVE_ADDR] = 0x4, -+ [REG_INTR_MASK] = 0x8, -+ [REG_INTR_STAT] = 0xc, -+ [REG_CONTROL] = 0x10, -+ [REG_TRANSFER_LEN] = 0x14, -+ [REG_TRANSAC_LEN] = 0x18, -+ [REG_DELAY_LEN] = 0x1c, -+ [REG_TIMING] = 0x20, -+ [REG_START] = 0x24, -+ [REG_EXT_CONF] = 0x28, -+ [REG_LTIMING] = 0x2c, -+ [REG_HS] = 0x30, -+ [REG_IO_CONFIG] = 0x34, -+ [REG_FIFO_ADDR_CLR] = 0x38, -+ [REG_TRANSFER_LEN_AUX] = 0x44, -+ [REG_CLOCK_DIV] = 0x48, -+ [REG_SOFTRESET] = 0x50, -+ [REG_DEBUGSTAT] = 0xe0, -+ [REG_DEBUGCTRL] = 0xe8, -+ [REG_FIFO_STAT] = 0xf4, -+ [REG_FIFO_THRESH] = 0xf8, -+ [REG_DCM_EN] = 0xf88, -+}; -+ -+struct mtk_i2c_soc_data { -+ const uint *regs; -+ uint dma_sync: 1; -+}; -+ -+struct mtk_i2c_priv { -+ /* set in i2c probe */ -+ void __iomem *base; /* i2c base addr */ -+ void __iomem *pdmabase; /* dma base address*/ -+ struct clk clk_main; /* main clock for i2c bus */ -+ struct clk clk_dma; /* DMA clock for i2c via DMA */ -+ const struct mtk_i2c_soc_data *soc_data; /* Compatible data for different IC */ -+ int op; /* operation mode */ -+ bool zero_len; /* Only transfer slave address, no data */ -+ bool pushpull; /* push pull mode or open drain mode */ -+ bool filter_msg; /* filter msg error log */ -+ bool auto_restart; /* restart mode */ -+ bool ignore_restart_irq; /* ignore restart IRQ */ -+ uint speed; /* i2c speed, unit: hz */ -+}; -+ -+static inline void i2c_writel(struct mtk_i2c_priv *priv, uint reg, uint value) -+{ -+ u32 offset = priv->soc_data->regs[reg]; -+ -+ writel(value, priv->base + offset); -+} -+ -+static inline uint i2c_readl(struct mtk_i2c_priv *priv, uint offset) -+{ -+ return readl(priv->base + priv->soc_data->regs[offset]); -+} -+ -+static int mtk_i2c_clk_enable(struct mtk_i2c_priv *priv) -+{ -+ int ret; -+ -+ ret = clk_enable(&priv->clk_main); -+ if (ret) -+ return log_msg_ret("enable clk_main", ret); -+ -+ ret = clk_enable(&priv->clk_dma); -+ if (ret) -+ return log_msg_ret("enable clk_dma", ret); -+ -+ return 0; -+} -+ -+static int mtk_i2c_clk_disable(struct mtk_i2c_priv *priv) -+{ -+ int ret; -+ -+ ret = clk_disable(&priv->clk_dma); -+ if (ret) -+ return log_msg_ret("disable clk_dma", ret); -+ -+ ret = clk_disable(&priv->clk_main); -+ if (ret) -+ return log_msg_ret("disable clk_main", ret); -+ -+ return 0; -+} -+ -+static void mtk_i2c_init_hw(struct mtk_i2c_priv *priv) -+{ -+ uint control_reg; -+ -+ writel(I2C_DMA_HARD_RST, priv->pdmabase + REG_RST); -+ writel(I2C_DMA_CLR_FLAG, priv->pdmabase + REG_RST); -+ i2c_writel(priv, REG_SOFTRESET, I2C_SOFT_RST); -+ /* set ioconfig */ -+ if (priv->pushpull) -+ i2c_writel(priv, REG_IO_CONFIG, I2C_IO_CONFIG_PUSH_PULL); -+ else -+ i2c_writel(priv, REG_IO_CONFIG, I2C_IO_CONFIG_OPEN_DRAIN); -+ -+ i2c_writel(priv, REG_DCM_EN, I2C_DCM_DISABLE); -+ control_reg = I2C_CONTROL_ACKERR_DET_EN | I2C_CONTROL_CLK_EXT_EN; -+ if (priv->soc_data->dma_sync) -+ control_reg |= I2C_CONTROL_DMAACK | I2C_CONTROL_ASYNC; -+ i2c_writel(priv, REG_CONTROL, control_reg); -+ i2c_writel(priv, REG_DELAY_LEN, I2C_DELAY_LEN); -+} -+ -+/* -+ * Calculate i2c port speed -+ * -+ * Hardware design: -+ * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt) -+ * clock_div: fixed in hardware, but may be various in different SoCs -+ * -+ * The calculation want to pick the highest bus frequency that is still -+ * less than or equal to target_speed. The calculation try to get -+ * sample_cnt and step_cn -+ * @param[in] -+ * clk_src: i2c clock source -+ * @param[out] -+ * timing_step_cnt: step cnt calculate result -+ * @param[out] -+ * timing_sample_cnt: sample cnt calculate result -+ * @return -+ * 0, set speed successfully. -+ * -EINVAL, Unsupported speed. -+ */ -+static int mtk_i2c_calculate_speed(uint clk_src, -+ uint target_speed, -+ uint *timing_step_cnt, -+ uint *timing_sample_cnt) -+{ -+ uint base_sample_cnt = MAX_SAMPLE_CNT_DIV; -+ uint base_step_cnt; -+ uint max_step_cnt; -+ uint sample_cnt; -+ uint step_cnt; -+ uint opt_div; -+ uint best_mul; -+ uint cnt_mul; -+ -+ if (target_speed > MAX_HS_MODE_SPEED) -+ target_speed = MAX_HS_MODE_SPEED; -+ -+ if (target_speed > MAX_FS_MODE_SPEED) -+ max_step_cnt = MAX_HS_STEP_CNT_DIV; -+ else -+ max_step_cnt = MAX_STEP_CNT_DIV; -+ -+ base_step_cnt = max_step_cnt; -+ /* Find the best combination */ -+ opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed); -+ best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt; -+ -+ /* -+ * Search for the best pair (sample_cnt, step_cnt) with -+ * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV -+ * 0 < step_cnt < max_step_cnt -+ * sample_cnt * step_cnt >= opt_div -+ * optimizing for sample_cnt * step_cnt being minimal -+ */ -+ for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) { -+ step_cnt = DIV_ROUND_UP(opt_div, sample_cnt); -+ cnt_mul = step_cnt * sample_cnt; -+ if (step_cnt > max_step_cnt) -+ continue; -+ -+ if (cnt_mul < best_mul) { -+ best_mul = cnt_mul; -+ base_sample_cnt = sample_cnt; -+ base_step_cnt = step_cnt; -+ if (best_mul == opt_div) -+ break; -+ } -+ } -+ -+ sample_cnt = base_sample_cnt; -+ step_cnt = base_step_cnt; -+ -+ if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) { -+ /* -+ * In this case, hardware can't support such -+ * low i2c_bus_freq -+ */ -+ debug("Unsupported speed(%uhz)\n", target_speed); -+ return log_msg_ret("calculate speed", -EINVAL); -+ } -+ -+ *timing_step_cnt = step_cnt - 1; -+ *timing_sample_cnt = sample_cnt - 1; -+ -+ return 0; -+} -+ -+/* -+ * mtk_i2c_set_speed -+ * -+ * @par Description -+ * Calculate i2c speed and write sample_cnt, step_cnt to TIMING register. -+ * @param[in] -+ * dev: udevice pointer, struct udevice contains i2c source clock, -+ * clock divide and speed. -+ * @return -+ * 0, set speed successfully.\n -+ * error code from mtk_i2c_calculate_speed(). -+ */ -+static int mtk_i2c_set_speed(struct udevice *dev, uint speed) -+{ -+ struct mtk_i2c_priv *priv = dev_get_priv(dev); -+ uint high_speed_reg; -+ uint sample_cnt; -+ uint timing_reg; -+ uint step_cnt; -+ uint clk_src; -+ int ret = 0; -+ -+ priv->speed = speed; -+ if (mtk_i2c_clk_enable(priv)) -+ return log_msg_ret("set_speed enable clk", -1); -+ -+ clk_src = clk_get_rate(&priv->clk_main) / I2C_DEFAULT_CLK_DIV; -+ i2c_writel(priv, REG_CLOCK_DIV, (I2C_DEFAULT_CLK_DIV - 1)); -+ if (priv->speed > MAX_FS_MODE_SPEED) { -+ /* Set master code speed register */ -+ ret = mtk_i2c_calculate_speed(clk_src, MAX_FS_MODE_SPEED, -+ &step_cnt, &sample_cnt); -+ if (ret < 0) -+ goto exit; -+ -+ timing_reg = (sample_cnt << TIMING_SAMPLE_OFFSET) | step_cnt; -+ i2c_writel(priv, REG_TIMING, timing_reg); -+ /* Set the high speed mode register */ -+ ret = mtk_i2c_calculate_speed(clk_src, priv->speed, -+ &step_cnt, &sample_cnt); -+ if (ret < 0) -+ goto exit; -+ -+ high_speed_reg = I2C_TIME_DEFAULT_VALUE | -+ (sample_cnt << HS_SAMPLE_OFFSET) | -+ (step_cnt << HS_STEP_OFFSET); -+ i2c_writel(priv, REG_HS, high_speed_reg); -+ } else { -+ ret = mtk_i2c_calculate_speed(clk_src, priv->speed, -+ &step_cnt, &sample_cnt); -+ if (ret < 0) -+ goto exit; -+ -+ timing_reg = (sample_cnt << TIMING_SAMPLE_OFFSET) | step_cnt; -+ /* Disable the high speed transaction */ -+ high_speed_reg = I2C_TIME_CLR_VALUE; -+ i2c_writel(priv, REG_TIMING, timing_reg); -+ i2c_writel(priv, REG_HS, high_speed_reg); -+ } -+exit: -+ if (mtk_i2c_clk_disable(priv)) -+ return log_msg_ret("set_speed disable clk", -1); -+ -+ return ret; -+} -+ -+/* -+ * mtk_i2c_do_transfer -+ * -+ * @par Description -+ * Configure i2c register and trigger transfer. -+ * @param[in] -+ * priv: mtk_i2cmtk_i2c_priv pointer, struct mtk_i2c_priv contains register base\n -+ * address, operation mode, interrupt status and i2c driver data. -+ * @param[in] -+ * msgs: i2c_msg pointer, struct i2c_msg contains slave\n -+ * address, operation mode, msg length and data buffer. -+ * @param[in] -+ * num: i2c_msg number. -+ * @param[in] -+ * left_num: left i2c_msg number. -+ * @return -+ * 0, i2c transfer successfully.\n -+ * -ETIMEDOUT, i2c transfer timeout.\n -+ * -EREMOTEIO, i2c transfer ack error. -+ */ -+static int mtk_i2c_do_transfer(struct mtk_i2c_priv *priv, -+ struct i2c_msg *msgs, -+ int num, int left_num) -+{ -+ struct i2c_msg *msg_rx = NULL; -+ uint restart_flag = 0; -+ uint trans_error = 0; -+ uint irq_stat = 0; -+ uint tmo_poll = 0; -+ uint control_reg; -+ bool tmo = false; -+ uint start_reg; -+ uint addr_reg; -+ int ret = 0; -+ -+ if (priv->auto_restart) -+ restart_flag = I2C_RS_TRANSFER; -+ -+ control_reg = i2c_readl(priv, REG_CONTROL) & -+ ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS); -+ -+ if (priv->speed > MAX_FS_MODE_SPEED || num > 1) -+ control_reg |= I2C_CONTROL_RS; -+ -+ if (priv->op == I2C_MASTER_WRRD) -+ control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS; -+ -+ control_reg |= I2C_CONTROL_DMA_EN; -+ i2c_writel(priv, REG_CONTROL, control_reg); -+ -+ /* set start condition */ -+ if (priv->speed <= MAX_ST_MODE_SPEED) -+ i2c_writel(priv, REG_EXT_CONF, I2C_ST_START_CON); -+ else -+ i2c_writel(priv, REG_EXT_CONF, I2C_FS_START_CON); -+ -+ addr_reg = msgs->addr << 1; -+ if (priv->op == I2C_MASTER_RD) -+ addr_reg |= I2C_M_RD; -+ if (priv->zero_len) -+ i2c_writel(priv, REG_SLAVE_ADDR, addr_reg | TRANS_ADDR_ONLY); -+ else -+ i2c_writel(priv, REG_SLAVE_ADDR, addr_reg); -+ -+ /* clear interrupt status */ -+ i2c_writel(priv, REG_INTR_STAT, restart_flag | I2C_HS_NACKERR | -+ I2C_ACKERR | I2C_TRANSAC_COMP); -+ i2c_writel(priv, REG_FIFO_ADDR_CLR, I2C_FIFO_ADDR_CLR); -+ -+ /* enable interrupt */ -+ i2c_writel(priv, REG_INTR_MASK, restart_flag | I2C_HS_NACKERR | -+ I2C_ACKERR | I2C_TRANSAC_COMP); -+ -+ /* set transfer and transaction len */ -+ if (priv->op == I2C_MASTER_WRRD) { -+ i2c_writel(priv, REG_TRANSFER_LEN, msgs->len); -+ i2c_writel(priv, REG_TRANSFER_LEN_AUX, (msgs + 1)->len); -+ i2c_writel(priv, REG_TRANSAC_LEN, I2C_WRRD_TRANAC_VALUE); -+ } else { -+ i2c_writel(priv, REG_TRANSFER_LEN, msgs->len); -+ i2c_writel(priv, REG_TRANSAC_LEN, num); -+ } -+ -+ /* Clear DMA interrupt flag */ -+ writel(I2C_DMA_INT_FLAG_NONE, priv->pdmabase + REG_INT_FLAG); -+ -+ /* Flush cache for first msg */ -+ flush_cache((ulong)msgs->buf, msgs->len); -+ -+ /* -+ * prepare buffer data to start transfer -+ * three cases here: read, write, write then read -+ */ -+ if (priv->op & I2C_MASTER_WR) { -+ /* Set DMA direction TX (w/ or w/o RX) */ -+ writel(I2C_DMA_CON_TX, priv->pdmabase + REG_CON); -+ -+ /* Write the tx buffer address to dma register */ -+ writel((ulong)msgs->buf, priv->pdmabase + REG_TX_MEM_ADDR); -+ /* Write the tx length to dma register */ -+ writel(msgs->len, priv->pdmabase + REG_TX_LEN); -+ -+ if (priv->op & I2C_MASTER_RD) { -+ /* write then read */ -+ msg_rx = msgs + 1; -+ -+ /* Flush cache for second msg */ -+ flush_cache((ulong)msg_rx->buf, msg_rx->len); -+ } -+ } -+ -+ if (priv->op & I2C_MASTER_RD) { -+ if (!msg_rx) { -+ /* Set DMA direction RX */ -+ writel(I2C_DMA_CON_RX, priv->pdmabase + REG_CON); -+ -+ msg_rx = msgs; -+ } -+ -+ /* Write the rx buffer address to dma register */ -+ writel((ulong)msg_rx->buf, priv->pdmabase + REG_RX_MEM_ADDR); -+ /* Write the rx length to dma register */ -+ writel(msg_rx->len, priv->pdmabase + REG_RX_LEN); -+ } -+ -+ writel(I2C_DMA_START_EN, priv->pdmabase + REG_EN); -+ -+ if (!priv->auto_restart) { -+ start_reg = I2C_TRANSAC_START; -+ } else { -+ start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG; -+ if (left_num >= 1) -+ start_reg |= I2C_RS_MUL_CNFG; -+ } -+ i2c_writel(priv, REG_START, start_reg); -+ -+ for (;;) { -+ irq_stat = i2c_readl(priv, REG_INTR_STAT); -+ -+ /* ignore the first restart irq after the master code */ -+ if (priv->ignore_restart_irq && (irq_stat & restart_flag)) { -+ priv->ignore_restart_irq = false; -+ irq_stat = 0; -+ i2c_writel(priv, REG_START, I2C_RS_MUL_CNFG | -+ I2C_RS_MUL_TRIG | I2C_TRANSAC_START); -+ } -+ -+ if (irq_stat & (I2C_TRANSAC_COMP | restart_flag)) { -+ tmo = false; -+ if (irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) -+ trans_error = 1; -+ -+ break; -+ } -+ udelay(1); -+ if (tmo_poll++ >= TRANSFER_TIMEOUT) { -+ tmo = true; -+ break; -+ } -+ } -+ -+ /* clear interrupt mask */ -+ i2c_writel(priv, REG_INTR_MASK, ~(restart_flag | I2C_HS_NACKERR | -+ I2C_ACKERR | I2C_TRANSAC_COMP)); -+ -+ if (!tmo && trans_error != 0) { -+ if (tmo) { -+ ret = -ETIMEDOUT; -+ if (!priv->filter_msg) -+ debug("I2C timeout! addr: 0x%x,\n", msgs->addr); -+ } else { -+ ret = -EREMOTEIO; -+ if (!priv->filter_msg) -+ debug("I2C ACKERR! addr: 0x%x,IRQ:0x%x\n", -+ msgs->addr, irq_stat); -+ } -+ mtk_i2c_init_hw(priv); -+ } -+ -+ return ret; -+} -+ -+/* -+ * mtk_i2c_transfer -+ * -+ * @par Description -+ * Common i2c transfer API. Set i2c transfer mode according to i2c_msg\n -+ * information, then call mtk_i2c_do_transfer() to configure i2c register\n -+ * and trigger transfer. -+ * @param[in] -+ * dev: udevice pointer, struct udevice contains struct mtk_i2c_priv, \n -+ * struct mtk_i2c_priv contains register base\n -+ * address, operation mode, interrupt status and i2c driver data. -+ * @param[in] -+ * msgs: i2c_msg pointer, struct i2c_msg contains slave\n -+ * address, operation mode, msg length and data buffer. -+ * @param[in] -+ * num: i2c_msg number. -+ * @return -+ * i2c_msg number, i2c transfer successfully.\n -+ * -EINVAL, msg length is more than 16\n -+ * use DMA MODE or slave address more than 0x7f.\n -+ * error code from mtk_i2c_init_base().\n -+ * error code from mtk_i2c_set_speed().\n -+ * error code from mtk_i2c_do_transfer(). -+ */ -+static int mtk_i2c_transfer(struct udevice *dev, struct i2c_msg *msg, -+ int nmsgs) -+{ -+ struct mtk_i2c_priv *priv = dev_get_priv(dev); -+ int left_num; -+ uint num_cnt; -+ int ret; -+ -+ priv->auto_restart = true; -+ left_num = nmsgs; -+ if (mtk_i2c_clk_enable(priv)) -+ return log_msg_ret("transfer enable clk", -1); -+ -+ for (num_cnt = 0; num_cnt < nmsgs; num_cnt++) { -+ if (((msg + num_cnt)->addr) > MAX_I2C_ADDR) { -+ ret = -EINVAL; -+ goto err_exit; -+ } -+ if ((msg + num_cnt)->len > MAX_I2C_LEN) { -+ ret = -EINVAL; -+ goto err_exit; -+ } -+ } -+ -+ /* check if we can skip restart and optimize using WRRD mode */ -+ if (priv->auto_restart && nmsgs == 2) { -+ if (!(msg[0].flags & I2C_M_RD) && (msg[1].flags & I2C_M_RD) && -+ msg[0].addr == msg[1].addr) { -+ priv->auto_restart = false; -+ } -+ } -+ -+ if (priv->auto_restart && nmsgs >= 2 && priv->speed > MAX_FS_MODE_SPEED) -+ /* ignore the first restart irq after the master code, -+ * otherwise the first transfer will be discarded. -+ */ -+ priv->ignore_restart_irq = true; -+ else -+ priv->ignore_restart_irq = false; -+ -+ while (left_num--) { -+ /* transfer slave address only to support devices detect */ -+ if (!msg->buf) -+ priv->zero_len = true; -+ else -+ priv->zero_len = false; -+ -+ if (msg->flags & I2C_M_RD) -+ priv->op = I2C_MASTER_RD; -+ else -+ priv->op = I2C_MASTER_WR; -+ -+ if (!priv->auto_restart) { -+ if (nmsgs > 1) { -+ /* combined two messages into one transaction */ -+ priv->op = I2C_MASTER_WRRD; -+ left_num--; -+ } -+ } -+ ret = mtk_i2c_do_transfer(priv, msg, nmsgs, left_num); -+ if (ret < 0) -+ goto err_exit; -+ msg++; -+ } -+ ret = 0; -+ -+err_exit: -+ if (mtk_i2c_clk_disable(priv)) -+ return log_msg_ret("transfer disable clk", -1); -+ -+ return ret; -+} -+ -+static int mtk_i2c_of_to_plat(struct udevice *dev) -+{ -+ struct mtk_i2c_priv *priv = dev_get_priv(dev); -+ int ret; -+ -+ priv->base = dev_remap_addr_index(dev, 0); -+ priv->pdmabase = dev_remap_addr_index(dev, 1); -+ ret = clk_get_by_index(dev, 0, &priv->clk_main); -+ if (ret) -+ return log_msg_ret("clk_get_by_index 0", ret); -+ -+ ret = clk_get_by_index(dev, 1, &priv->clk_dma); -+ -+ return ret; -+} -+ -+static int mtk_i2c_probe(struct udevice *dev) -+{ -+ struct mtk_i2c_priv *priv = dev_get_priv(dev); -+ -+ priv->soc_data = (struct mtk_i2c_soc_data *)dev_get_driver_data(dev); -+ -+ if (mtk_i2c_clk_enable(priv)) -+ return log_msg_ret("probe enable clk", -1); -+ -+ mtk_i2c_init_hw(priv); -+ -+ if (mtk_i2c_clk_disable(priv)) -+ return log_msg_ret("probe disable clk", -1); -+ -+ return 0; -+} -+ -+static int mtk_i2c_deblock(struct udevice *dev) -+{ -+ struct mtk_i2c_priv *priv = dev_get_priv(dev); -+ -+ if (mtk_i2c_clk_enable(priv)) -+ return log_msg_ret("deblock enable clk", -1); -+ -+ mtk_i2c_init_hw(priv); -+ -+ if (mtk_i2c_clk_disable(priv)) -+ return log_msg_ret("deblock disable clk", -1); -+ -+ return 0; -+} -+ -+static const struct mtk_i2c_soc_data mt76xx_soc_data = { -+ .regs = mt_i2c_regs_v1, -+ .dma_sync = 0, -+}; -+ -+static const struct mtk_i2c_soc_data mt7981_soc_data = { -+ .regs = mt_i2c_regs_v1, -+ .dma_sync = 1, -+}; -+ -+static const struct mtk_i2c_soc_data mt7986_soc_data = { -+ .regs = mt_i2c_regs_v1, -+ .dma_sync = 1, -+}; -+ -+static const struct mtk_i2c_soc_data mt8183_soc_data = { -+ .regs = mt_i2c_regs_v2, -+ .dma_sync = 1, -+}; -+ -+static const struct mtk_i2c_soc_data mt8518_soc_data = { -+ .regs = mt_i2c_regs_v1, -+ .dma_sync = 0, -+}; -+ -+static const struct mtk_i2c_soc_data mt8512_soc_data = { -+ .regs = mt_i2c_regs_v1, -+ .dma_sync = 1, -+}; -+ -+static const struct dm_i2c_ops mtk_i2c_ops = { -+ .xfer = mtk_i2c_transfer, -+ .set_bus_speed = mtk_i2c_set_speed, -+ .deblock = mtk_i2c_deblock, -+}; -+ -+static const struct udevice_id mtk_i2c_ids[] = { -+ { -+ .compatible = "mediatek,mt7622-i2c", -+ .data = (ulong)&mt76xx_soc_data, -+ }, { -+ .compatible = "mediatek,mt7623-i2c", -+ .data = (ulong)&mt76xx_soc_data, -+ }, { -+ .compatible = "mediatek,mt7629-i2c", -+ .data = (ulong)&mt76xx_soc_data, -+ }, { -+ .compatible = "mediatek,mt7981-i2c", -+ .data = (ulong)&mt7981_soc_data, -+ }, { -+ .compatible = "mediatek,mt7986-i2c", -+ .data = (ulong)&mt7986_soc_data, -+ }, { -+ .compatible = "mediatek,mt8183-i2c", -+ .data = (ulong)&mt8183_soc_data, -+ }, { -+ .compatible = "mediatek,mt8512-i2c", -+ .data = (ulong)&mt8512_soc_data, -+ }, { -+ .compatible = "mediatek,mt8518-i2c", -+ .data = (ulong)&mt8518_soc_data, -+ } -+}; -+ -+U_BOOT_DRIVER(mtk_i2c) = { -+ .name = "mtk_i2c", -+ .id = UCLASS_I2C, -+ .of_match = mtk_i2c_ids, -+ .of_to_plat = mtk_i2c_of_to_plat, -+ .probe = mtk_i2c_probe, -+ .priv_auto = sizeof(struct mtk_i2c_priv), -+ .ops = &mtk_i2c_ops, -+}; diff --git a/package/boot/uboot-mediatek/patches/002-0018-arm-dts-mt7622-add-i2c-support.patch b/package/boot/uboot-mediatek/patches/002-0018-arm-dts-mt7622-add-i2c-support.patch deleted file mode 100644 index c87f17f6ef1..00000000000 --- a/package/boot/uboot-mediatek/patches/002-0018-arm-dts-mt7622-add-i2c-support.patch +++ /dev/null @@ -1,76 +0,0 @@ -From ceb4b900586299b12e2c8edffecef1d09b57eb30 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 31 Aug 2022 19:04:49 +0800 -Subject: [PATCH 18/32] arm: dts: mt7622: add i2c support - -Add both hardware and software i2c support for mt7622. - -Reviewed-by: Simon Glass -Signed-off-by: Weijie Gao ---- - arch/arm/dts/mt7622-rfb.dts | 18 ++++++++++++++++++ - arch/arm/dts/mt7622.dtsi | 24 ++++++++++++++++++++++++ - 2 files changed, 42 insertions(+) - ---- a/arch/arm/dts/mt7622-rfb.dts -+++ b/arch/arm/dts/mt7622-rfb.dts -@@ -159,6 +159,14 @@ - }; - - }; -+ -+ i2c1_pins_default: i2c1-default { -+ mux { -+ function = "i2c"; -+ groups = "i2c1_0"; -+ }; -+ }; -+ - }; - - &snfi { -@@ -242,3 +250,13 @@ - &u3phy { - status = "okay"; - }; -+ -+&soft_i2c { -+ status = "disabled"; -+}; -+ -+&i2c1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c1_pins_default>; -+ status = "okay"; -+}; ---- a/arch/arm/dts/mt7622.dtsi -+++ b/arch/arm/dts/mt7622.dtsi -@@ -424,4 +424,28 @@ - status = "disabled"; - }; - -+ soft_i2c: soft_i2c@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "i2c-gpio"; -+ gpios = <&gpio 56 GPIO_ACTIVE_HIGH>, /* SDA */ -+ <&gpio 55 GPIO_ACTIVE_HIGH>; /* CLK */ -+ i2c-gpio,delay-us = <5>; -+ status = "disabled"; -+ }; -+ -+ i2c1: i2c@11008000 { -+ compatible = "mediatek,mt7622-i2c"; -+ reg = <0x11008000 0x90>, -+ <0x11000180 0x80>; -+ interrupts = ; -+ clock-div = <16>; -+ clocks = <&pericfg CLK_PERI_I2C1_PD>, -+ <&pericfg CLK_PERI_AP_DMA_PD>; -+ clock-names = "main", "dma"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ - }; diff --git a/package/boot/uboot-mediatek/patches/002-0019-dt-bindings-pinctrl-mediatek-add-a-header-for-common.patch b/package/boot/uboot-mediatek/patches/002-0019-dt-bindings-pinctrl-mediatek-add-a-header-for-common.patch deleted file mode 100644 index b4b38f26a4c..00000000000 --- a/package/boot/uboot-mediatek/patches/002-0019-dt-bindings-pinctrl-mediatek-add-a-header-for-common.patch +++ /dev/null @@ -1,60 +0,0 @@ -From e1c55c0ad21daafcb3551b4f5286c1e11c51acc3 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 31 Aug 2022 19:04:51 +0800 -Subject: [PATCH 19/32] dt-bindings: pinctrl: mediatek: add a header for common - pinconf parameters - -This patch adds a pinctrl header for common pinconf parameters such as -pull-up/pull-down resistors and drive strengths. - -Reviewed-by: Simon Glass -Signed-off-by: Weijie Gao ---- - include/dt-bindings/pinctrl/mt65xx.h | 41 ++++++++++++++++++++++++++++ - 1 file changed, 41 insertions(+) - create mode 100644 include/dt-bindings/pinctrl/mt65xx.h - ---- /dev/null -+++ b/include/dt-bindings/pinctrl/mt65xx.h -@@ -0,0 +1,41 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * Copyright (c) 2022 MediaTek Inc. -+ * Author: Hongzhou.Yang -+ */ -+ -+#ifndef _DT_BINDINGS_PINCTRL_MT65XX_H -+#define _DT_BINDINGS_PINCTRL_MT65XX_H -+ -+#define MTK_PIN_NO(x) ((x) << 8) -+#define MTK_GET_PIN_NO(x) ((x) >> 8) -+#define MTK_GET_PIN_FUNC(x) ((x) & 0xf) -+ -+#define MTK_PUPD_SET_R1R0_00 100 -+#define MTK_PUPD_SET_R1R0_01 101 -+#define MTK_PUPD_SET_R1R0_10 102 -+#define MTK_PUPD_SET_R1R0_11 103 -+ -+#define MTK_PULL_SET_RSEL_000 200 -+#define MTK_PULL_SET_RSEL_001 201 -+#define MTK_PULL_SET_RSEL_010 202 -+#define MTK_PULL_SET_RSEL_011 203 -+#define MTK_PULL_SET_RSEL_100 204 -+#define MTK_PULL_SET_RSEL_101 205 -+#define MTK_PULL_SET_RSEL_110 206 -+#define MTK_PULL_SET_RSEL_111 207 -+ -+#define MTK_DRIVE_2mA 2 -+#define MTK_DRIVE_4mA 4 -+#define MTK_DRIVE_6mA 6 -+#define MTK_DRIVE_8mA 8 -+#define MTK_DRIVE_10mA 10 -+#define MTK_DRIVE_12mA 12 -+#define MTK_DRIVE_14mA 14 -+#define MTK_DRIVE_16mA 16 -+#define MTK_DRIVE_20mA 20 -+#define MTK_DRIVE_24mA 24 -+#define MTK_DRIVE_28mA 28 -+#define MTK_DRIVE_32mA 32 -+ -+#endif /* _DT_BINDINGS_PINCTRL_MT65XX_H */ diff --git a/package/boot/uboot-mediatek/patches/002-0020-pinctrl-mediatek-add-pinctrl-driver-for-MT7981-SoC.patch b/package/boot/uboot-mediatek/patches/002-0020-pinctrl-mediatek-add-pinctrl-driver-for-MT7981-SoC.patch deleted file mode 100644 index f4bc27f93df..00000000000 --- a/package/boot/uboot-mediatek/patches/002-0020-pinctrl-mediatek-add-pinctrl-driver-for-MT7981-SoC.patch +++ /dev/null @@ -1,1091 +0,0 @@ -From 95df7f4bfacf810be4f94112ab2a4215f6de288d Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 31 Aug 2022 19:04:55 +0800 -Subject: [PATCH 20/32] pinctrl: mediatek: add pinctrl driver for MT7981 SoC - -This patch adds pinctrl and gpio support for MT7981 SoC - -Reviewed-by: Simon Glass -Signed-off-by: Weijie Gao ---- - drivers/pinctrl/mediatek/Kconfig | 4 + - drivers/pinctrl/mediatek/Makefile | 1 + - drivers/pinctrl/mediatek/pinctrl-mt7981.c | 1049 +++++++++++++++++++++ - 3 files changed, 1054 insertions(+) - create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7981.c - ---- a/drivers/pinctrl/mediatek/Kconfig -+++ b/drivers/pinctrl/mediatek/Kconfig -@@ -16,6 +16,10 @@ config PINCTRL_MT7629 - bool "MT7629 SoC pinctrl driver" - select PINCTRL_MTK - -+config PINCTRL_MT7981 -+ bool "MT7981 SoC pinctrl driver" -+ select PINCTRL_MTK -+ - config PINCTRL_MT8512 - bool "MT8512 SoC pinctrl driver" - select PINCTRL_MTK ---- a/drivers/pinctrl/mediatek/Makefile -+++ b/drivers/pinctrl/mediatek/Makefile -@@ -6,6 +6,7 @@ obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk - obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o - obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o - obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o -+obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o - obj-$(CONFIG_PINCTRL_MT8512) += pinctrl-mt8512.o - obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o - obj-$(CONFIG_PINCTRL_MT8518) += pinctrl-mt8518.o ---- /dev/null -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c -@@ -0,0 +1,1049 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * The MT7981 driver based on Linux generic pinctrl binding. -+ * -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Sam Shih -+ */ -+ -+#include -+#include "pinctrl-mtk-common.h" -+ -+#define MT7981_TYPE0_PIN(_number, _name) \ -+ MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP0) -+ -+#define MT7981_TYPE1_PIN(_number, _name) \ -+ MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP1) -+ -+#define PIN_FIELD_GPIO(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ -+ PIN_FIELD_BASE_CALC(_s_pin, _e_pin, GPIO_BASE, _s_addr, _x_addrs, \ -+ _s_bit, _x_bits, 32, 0) -+ -+#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ -+ _x_bits) \ -+ PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ -+ _x_bits, 32, 0) -+ -+/** -+ * enum - Locking variants of the iocfg bases -+ * -+ * MT7981 have multiple bases to program pin configuration listed as the below: -+ * iocfg_rt:0x11c00000, iocfg_rm:0x11c10000, iocfg_rb:0x11d20000, -+ * iocfg_lb:0x11e00000, iocfg_bl:0x11e20000, iocfg_tm:0x11f00000, -+ * iocfg_tl:0x11f10000, -+ * _i_based could be used to indicate what base the pin should be mapped into. -+ * -+ * Each iocfg register base control different group of pads on the SoC -+ * -+ * -+ * chip carrier -+ * -+ * A B C D E F G H -+ * +------------------------+ -+ * 8 | o o o o o o o o | -+ * 7 | o o o o o o o o | -+ * 6 | o o o o o o o o | -+ * 5 | o o o o o o o o | -+ * 4 | o o o o o o o o | -+ * 3 | o o o o o o o o | -+ * 2 | o o o o o o o o | -+ * 1 | o o o o o o o o | -+ * +------------------------+ -+ * -+ * inside Chip carrier -+ * -+ * A B C D E F G H -+ * +------------------------+ -+ * 8 | | -+ * 7 | TL TM | -+ * 6 | +---------+ | -+ * 5 | | | RT | -+ * 4 | | | RM | -+ * 3 | LB | | RB | -+ * 2 | +---------+ | -+ * 1 | BL | -+ * +------------------------+ -+ * -+ */ -+ -+enum { -+ GPIO_BASE, -+ IOCFG_RT_BASE, -+ IOCFG_RM_BASE, -+ IOCFG_RB_BASE, -+ IOCFG_LB_BASE, -+ IOCFG_BL_BASE, -+ IOCFG_TM_BASE, -+ IOCFG_TL_BASE, -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_mode_range[] = { -+ PIN_FIELD_GPIO(0, 56, 0x300, 0x10, 0, 4), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_dir_range[] = { -+ PIN_FIELD_GPIO(0, 56, 0x0, 0x10, 0, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_di_range[] = { -+ PIN_FIELD_GPIO(0, 56, 0x200, 0x10, 0, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_do_range[] = { -+ PIN_FIELD_GPIO(0, 56, 0x100, 0x10, 0, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_ies_range[] = { -+ PIN_FIELD_BASE(0, 0, 1, 0x10, 0x10, 1, 1), -+ PIN_FIELD_BASE(1, 1, 1, 0x10, 0x10, 0, 1), -+ PIN_FIELD_BASE(2, 2, 5, 0x20, 0x10, 6, 1), -+ PIN_FIELD_BASE(3, 3, 4, 0x20, 0x10, 6, 1), -+ PIN_FIELD_BASE(4, 4, 4, 0x20, 0x10, 2, 1), -+ PIN_FIELD_BASE(5, 5, 4, 0x20, 0x10, 1, 1), -+ PIN_FIELD_BASE(6, 6, 4, 0x20, 0x10, 3, 1), -+ PIN_FIELD_BASE(7, 7, 4, 0x20, 0x10, 0, 1), -+ PIN_FIELD_BASE(8, 8, 4, 0x20, 0x10, 4, 1), -+ PIN_FIELD_BASE(9, 9, 4, 0x20, 0x10, 9, 1), -+ -+ PIN_FIELD_BASE(10, 10, 5, 0x20, 0x10, 8, 1), -+ PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1), -+ PIN_FIELD_BASE(12, 12, 5, 0x20, 0x10, 7, 1), -+ PIN_FIELD_BASE(13, 13, 5, 0x20, 0x10, 11, 1), -+ -+ PIN_FIELD_BASE(14, 14, 4, 0x20, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(15, 15, 2, 0x20, 0x10, 0, 1), -+ PIN_FIELD_BASE(16, 16, 2, 0x20, 0x10, 1, 1), -+ PIN_FIELD_BASE(17, 17, 2, 0x20, 0x10, 5, 1), -+ PIN_FIELD_BASE(18, 18, 2, 0x20, 0x10, 4, 1), -+ PIN_FIELD_BASE(19, 19, 2, 0x20, 0x10, 2, 1), -+ PIN_FIELD_BASE(20, 20, 2, 0x20, 0x10, 3, 1), -+ PIN_FIELD_BASE(21, 21, 2, 0x20, 0x10, 6, 1), -+ PIN_FIELD_BASE(22, 22, 2, 0x20, 0x10, 7, 1), -+ PIN_FIELD_BASE(23, 23, 2, 0x20, 0x10, 10, 1), -+ PIN_FIELD_BASE(24, 24, 2, 0x20, 0x10, 9, 1), -+ PIN_FIELD_BASE(25, 25, 2, 0x20, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(26, 26, 5, 0x20, 0x10, 0, 1), -+ PIN_FIELD_BASE(27, 27, 5, 0x20, 0x10, 4, 1), -+ PIN_FIELD_BASE(28, 28, 5, 0x20, 0x10, 3, 1), -+ PIN_FIELD_BASE(29, 29, 5, 0x20, 0x10, 1, 1), -+ PIN_FIELD_BASE(30, 30, 5, 0x20, 0x10, 2, 1), -+ PIN_FIELD_BASE(31, 31, 5, 0x20, 0x10, 5, 1), -+ -+ PIN_FIELD_BASE(32, 32, 1, 0x10, 0x10, 2, 1), -+ PIN_FIELD_BASE(33, 33, 1, 0x10, 0x10, 3, 1), -+ -+ PIN_FIELD_BASE(34, 34, 4, 0x20, 0x10, 5, 1), -+ PIN_FIELD_BASE(35, 35, 4, 0x20, 0x10, 7, 1), -+ -+ PIN_FIELD_BASE(36, 36, 3, 0x10, 0x10, 2, 1), -+ PIN_FIELD_BASE(37, 37, 3, 0x10, 0x10, 3, 1), -+ PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 0, 1), -+ PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 1, 1), -+ -+ PIN_FIELD_BASE(40, 40, 7, 0x30, 0x10, 1, 1), -+ PIN_FIELD_BASE(41, 41, 7, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(42, 42, 7, 0x30, 0x10, 9, 1), -+ PIN_FIELD_BASE(43, 43, 7, 0x30, 0x10, 7, 1), -+ PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1), -+ PIN_FIELD_BASE(45, 45, 7, 0x30, 0x10, 3, 1), -+ PIN_FIELD_BASE(46, 46, 7, 0x30, 0x10, 4, 1), -+ PIN_FIELD_BASE(47, 47, 7, 0x30, 0x10, 5, 1), -+ PIN_FIELD_BASE(48, 48, 7, 0x30, 0x10, 6, 1), -+ PIN_FIELD_BASE(49, 49, 7, 0x30, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(50, 50, 6, 0x10, 0x10, 0, 1), -+ PIN_FIELD_BASE(51, 51, 6, 0x10, 0x10, 2, 1), -+ PIN_FIELD_BASE(52, 52, 6, 0x10, 0x10, 3, 1), -+ PIN_FIELD_BASE(53, 53, 6, 0x10, 0x10, 4, 1), -+ PIN_FIELD_BASE(54, 54, 6, 0x10, 0x10, 5, 1), -+ PIN_FIELD_BASE(55, 55, 6, 0x10, 0x10, 6, 1), -+ PIN_FIELD_BASE(56, 56, 6, 0x10, 0x10, 1, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_smt_range[] = { -+ PIN_FIELD_BASE(0, 0, 1, 0x60, 0x10, 1, 1), -+ PIN_FIELD_BASE(1, 1, 1, 0x60, 0x10, 0, 1), -+ PIN_FIELD_BASE(2, 2, 5, 0x90, 0x10, 6, 1), -+ PIN_FIELD_BASE(3, 3, 4, 0x80, 0x10, 6, 1), -+ PIN_FIELD_BASE(4, 4, 4, 0x80, 0x10, 2, 1), -+ PIN_FIELD_BASE(5, 5, 4, 0x80, 0x10, 1, 1), -+ PIN_FIELD_BASE(6, 6, 4, 0x80, 0x10, 3, 1), -+ PIN_FIELD_BASE(7, 7, 4, 0x80, 0x10, 0, 1), -+ PIN_FIELD_BASE(8, 8, 4, 0x80, 0x10, 4, 1), -+ PIN_FIELD_BASE(9, 9, 4, 0x80, 0x10, 9, 1), -+ -+ PIN_FIELD_BASE(10, 10, 5, 0x90, 0x10, 8, 1), -+ PIN_FIELD_BASE(11, 11, 5, 0x90, 0x10, 10, 1), -+ PIN_FIELD_BASE(12, 12, 5, 0x90, 0x10, 7, 1), -+ PIN_FIELD_BASE(13, 13, 5, 0x90, 0x10, 11, 1), -+ -+ PIN_FIELD_BASE(14, 14, 4, 0x80, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(15, 15, 2, 0x90, 0x10, 0, 1), -+ PIN_FIELD_BASE(16, 16, 2, 0x90, 0x10, 1, 1), -+ PIN_FIELD_BASE(17, 17, 2, 0x90, 0x10, 5, 1), -+ PIN_FIELD_BASE(18, 18, 2, 0x90, 0x10, 4, 1), -+ PIN_FIELD_BASE(19, 19, 2, 0x90, 0x10, 2, 1), -+ PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1), -+ PIN_FIELD_BASE(21, 21, 2, 0x90, 0x10, 6, 1), -+ PIN_FIELD_BASE(22, 22, 2, 0x90, 0x10, 7, 1), -+ PIN_FIELD_BASE(23, 23, 2, 0x90, 0x10, 10, 1), -+ PIN_FIELD_BASE(24, 24, 2, 0x90, 0x10, 9, 1), -+ PIN_FIELD_BASE(25, 25, 2, 0x90, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(26, 26, 5, 0x90, 0x10, 0, 1), -+ PIN_FIELD_BASE(27, 27, 5, 0x90, 0x10, 4, 1), -+ PIN_FIELD_BASE(28, 28, 5, 0x90, 0x10, 3, 1), -+ PIN_FIELD_BASE(29, 29, 5, 0x90, 0x10, 1, 1), -+ PIN_FIELD_BASE(30, 30, 5, 0x90, 0x10, 2, 1), -+ PIN_FIELD_BASE(31, 31, 5, 0x90, 0x10, 5, 1), -+ -+ PIN_FIELD_BASE(32, 32, 1, 0x60, 0x10, 2, 1), -+ PIN_FIELD_BASE(33, 33, 1, 0x60, 0x10, 3, 1), -+ -+ PIN_FIELD_BASE(34, 34, 4, 0x80, 0x10, 5, 1), -+ PIN_FIELD_BASE(35, 35, 4, 0x80, 0x10, 7, 1), -+ -+ PIN_FIELD_BASE(36, 36, 3, 0x60, 0x10, 2, 1), -+ PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 3, 1), -+ PIN_FIELD_BASE(38, 38, 3, 0x60, 0x10, 0, 1), -+ PIN_FIELD_BASE(39, 39, 3, 0x60, 0x10, 1, 1), -+ -+ PIN_FIELD_BASE(40, 40, 7, 0x70, 0x10, 1, 1), -+ PIN_FIELD_BASE(41, 41, 7, 0x70, 0x10, 0, 1), -+ PIN_FIELD_BASE(42, 42, 7, 0x70, 0x10, 9, 1), -+ PIN_FIELD_BASE(43, 43, 7, 0x70, 0x10, 7, 1), -+ PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1), -+ PIN_FIELD_BASE(45, 45, 7, 0x70, 0x10, 3, 1), -+ PIN_FIELD_BASE(46, 46, 7, 0x70, 0x10, 4, 1), -+ PIN_FIELD_BASE(47, 47, 7, 0x70, 0x10, 5, 1), -+ PIN_FIELD_BASE(48, 48, 7, 0x70, 0x10, 6, 1), -+ PIN_FIELD_BASE(49, 49, 7, 0x70, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(50, 50, 6, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(51, 51, 6, 0x50, 0x10, 2, 1), -+ PIN_FIELD_BASE(52, 52, 6, 0x50, 0x10, 3, 1), -+ PIN_FIELD_BASE(53, 53, 6, 0x50, 0x10, 4, 1), -+ PIN_FIELD_BASE(54, 54, 6, 0x50, 0x10, 5, 1), -+ PIN_FIELD_BASE(55, 55, 6, 0x50, 0x10, 6, 1), -+ PIN_FIELD_BASE(56, 56, 6, 0x50, 0x10, 1, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_pu_range[] = { -+ PIN_FIELD_BASE(40, 40, 7, 0x50, 0x10, 1, 1), -+ PIN_FIELD_BASE(41, 41, 7, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(42, 42, 7, 0x50, 0x10, 9, 1), -+ PIN_FIELD_BASE(43, 43, 7, 0x50, 0x10, 7, 1), -+ PIN_FIELD_BASE(44, 44, 7, 0x50, 0x10, 8, 1), -+ PIN_FIELD_BASE(45, 45, 7, 0x50, 0x10, 3, 1), -+ PIN_FIELD_BASE(46, 46, 7, 0x50, 0x10, 4, 1), -+ PIN_FIELD_BASE(47, 47, 7, 0x50, 0x10, 5, 1), -+ PIN_FIELD_BASE(48, 48, 7, 0x50, 0x10, 6, 1), -+ PIN_FIELD_BASE(49, 49, 7, 0x50, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(50, 50, 6, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(51, 51, 6, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(52, 52, 6, 0x30, 0x10, 3, 1), -+ PIN_FIELD_BASE(53, 53, 6, 0x30, 0x10, 4, 1), -+ PIN_FIELD_BASE(54, 54, 6, 0x30, 0x10, 5, 1), -+ PIN_FIELD_BASE(55, 55, 6, 0x30, 0x10, 6, 1), -+ PIN_FIELD_BASE(56, 56, 6, 0x30, 0x10, 1, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_pd_range[] = { -+ PIN_FIELD_BASE(40, 40, 7, 0x40, 0x10, 1, 1), -+ PIN_FIELD_BASE(41, 41, 7, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(42, 42, 7, 0x40, 0x10, 9, 1), -+ PIN_FIELD_BASE(43, 43, 7, 0x40, 0x10, 7, 1), -+ PIN_FIELD_BASE(44, 44, 7, 0x40, 0x10, 8, 1), -+ PIN_FIELD_BASE(45, 45, 7, 0x40, 0x10, 3, 1), -+ PIN_FIELD_BASE(46, 46, 7, 0x40, 0x10, 4, 1), -+ PIN_FIELD_BASE(47, 47, 7, 0x40, 0x10, 5, 1), -+ PIN_FIELD_BASE(48, 48, 7, 0x40, 0x10, 6, 1), -+ PIN_FIELD_BASE(49, 49, 7, 0x40, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(50, 50, 6, 0x20, 0x10, 0, 1), -+ PIN_FIELD_BASE(51, 51, 6, 0x20, 0x10, 2, 1), -+ PIN_FIELD_BASE(52, 52, 6, 0x20, 0x10, 3, 1), -+ PIN_FIELD_BASE(53, 53, 6, 0x20, 0x10, 4, 1), -+ PIN_FIELD_BASE(54, 54, 6, 0x20, 0x10, 5, 1), -+ PIN_FIELD_BASE(55, 55, 6, 0x20, 0x10, 6, 1), -+ PIN_FIELD_BASE(56, 56, 6, 0x20, 0x10, 1, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_drv_range[] = { -+ PIN_FIELD_BASE(0, 0, 1, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(1, 1, 1, 0x00, 0x10, 0, 3), -+ -+ PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 18, 3), -+ -+ PIN_FIELD_BASE(3, 3, 4, 0x00, 0x10, 18, 1), -+ PIN_FIELD_BASE(4, 4, 4, 0x00, 0x10, 6, 1), -+ PIN_FIELD_BASE(5, 5, 4, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(6, 6, 4, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 12, 3), -+ PIN_FIELD_BASE(9, 9, 4, 0x00, 0x10, 27, 3), -+ -+ PIN_FIELD_BASE(10, 10, 5, 0x00, 0x10, 24, 3), -+ PIN_FIELD_BASE(11, 11, 5, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(12, 12, 5, 0x00, 0x10, 21, 3), -+ PIN_FIELD_BASE(13, 13, 5, 0x00, 0x10, 3, 3), -+ -+ PIN_FIELD_BASE(14, 14, 4, 0x00, 0x10, 27, 3), -+ -+ PIN_FIELD_BASE(15, 15, 2, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(16, 16, 2, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(17, 17, 2, 0x00, 0x10, 15, 3), -+ PIN_FIELD_BASE(18, 18, 2, 0x00, 0x10, 12, 3), -+ PIN_FIELD_BASE(19, 19, 2, 0x00, 0x10, 6, 3), -+ PIN_FIELD_BASE(20, 20, 2, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(21, 21, 2, 0x00, 0x10, 18, 3), -+ PIN_FIELD_BASE(22, 22, 2, 0x00, 0x10, 21, 3), -+ PIN_FIELD_BASE(23, 23, 2, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(24, 24, 2, 0x00, 0x10, 27, 3), -+ PIN_FIELD_BASE(25, 25, 2, 0x00, 0x10, 24, 3), -+ -+ PIN_FIELD_BASE(26, 26, 5, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(27, 27, 5, 0x00, 0x10, 12, 3), -+ PIN_FIELD_BASE(28, 28, 5, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(29, 29, 5, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(30, 30, 5, 0x00, 0x10, 6, 3), -+ PIN_FIELD_BASE(31, 31, 5, 0x00, 0x10, 15, 3), -+ -+ PIN_FIELD_BASE(32, 32, 1, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(33, 33, 1, 0x00, 0x10, 12, 3), -+ -+ PIN_FIELD_BASE(34, 34, 4, 0x00, 0x10, 15, 3), -+ PIN_FIELD_BASE(35, 35, 4, 0x00, 0x10, 21, 3), -+ -+ PIN_FIELD_BASE(36, 36, 3, 0x00, 0x10, 6, 3), -+ PIN_FIELD_BASE(37, 37, 3, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(38, 38, 3, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(39, 39, 3, 0x00, 0x10, 3, 3), -+ -+ PIN_FIELD_BASE(40, 40, 7, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(41, 41, 7, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(42, 42, 7, 0x00, 0x10, 27, 3), -+ PIN_FIELD_BASE(43, 43, 7, 0x00, 0x10, 21, 3), -+ PIN_FIELD_BASE(44, 44, 7, 0x00, 0x10, 24, 3), -+ PIN_FIELD_BASE(45, 45, 7, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(46, 46, 7, 0x00, 0x10, 12, 3), -+ PIN_FIELD_BASE(47, 47, 7, 0x00, 0x10, 15, 3), -+ PIN_FIELD_BASE(48, 48, 7, 0x00, 0x10, 18, 3), -+ PIN_FIELD_BASE(49, 49, 7, 0x00, 0x10, 6, 3), -+ -+ PIN_FIELD_BASE(50, 50, 6, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(51, 51, 6, 0x00, 0x10, 6, 3), -+ PIN_FIELD_BASE(52, 52, 6, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(53, 53, 6, 0x00, 0x10, 12, 3), -+ PIN_FIELD_BASE(54, 54, 6, 0x00, 0x10, 15, 3), -+ PIN_FIELD_BASE(55, 55, 6, 0x00, 0x10, 18, 3), -+ PIN_FIELD_BASE(56, 56, 6, 0x00, 0x10, 3, 3), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_pupd_range[] = { -+ PIN_FIELD_BASE(0, 0, 1, 0x20, 0x10, 1, 1), -+ PIN_FIELD_BASE(1, 1, 1, 0x20, 0x10, 0, 1), -+ PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 6, 1), -+ PIN_FIELD_BASE(3, 3, 4, 0x30, 0x10, 6, 1), -+ PIN_FIELD_BASE(4, 4, 4, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(5, 5, 4, 0x30, 0x10, 1, 1), -+ PIN_FIELD_BASE(6, 6, 4, 0x30, 0x10, 3, 1), -+ PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 4, 1), -+ PIN_FIELD_BASE(9, 9, 4, 0x30, 0x10, 9, 1), -+ -+ PIN_FIELD_BASE(10, 10, 5, 0x30, 0x10, 8, 1), -+ PIN_FIELD_BASE(11, 11, 5, 0x30, 0x10, 10, 1), -+ PIN_FIELD_BASE(12, 12, 5, 0x30, 0x10, 7, 1), -+ PIN_FIELD_BASE(13, 13, 5, 0x30, 0x10, 11, 1), -+ -+ PIN_FIELD_BASE(14, 14, 4, 0x30, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(15, 15, 2, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(16, 16, 2, 0x30, 0x10, 1, 1), -+ PIN_FIELD_BASE(17, 17, 2, 0x30, 0x10, 5, 1), -+ PIN_FIELD_BASE(18, 18, 2, 0x30, 0x10, 4, 1), -+ PIN_FIELD_BASE(19, 19, 2, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1), -+ PIN_FIELD_BASE(21, 21, 2, 0x30, 0x10, 6, 1), -+ PIN_FIELD_BASE(22, 22, 2, 0x30, 0x10, 7, 1), -+ PIN_FIELD_BASE(23, 23, 2, 0x30, 0x10, 10, 1), -+ PIN_FIELD_BASE(24, 24, 2, 0x30, 0x10, 9, 1), -+ PIN_FIELD_BASE(25, 25, 2, 0x30, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(26, 26, 5, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(27, 27, 5, 0x30, 0x10, 4, 1), -+ PIN_FIELD_BASE(28, 28, 5, 0x30, 0x10, 3, 1), -+ PIN_FIELD_BASE(29, 29, 5, 0x30, 0x10, 1, 1), -+ PIN_FIELD_BASE(30, 30, 5, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(31, 31, 5, 0x30, 0x10, 5, 1), -+ -+ PIN_FIELD_BASE(32, 32, 1, 0x20, 0x10, 2, 1), -+ PIN_FIELD_BASE(33, 33, 1, 0x20, 0x10, 3, 1), -+ -+ PIN_FIELD_BASE(34, 34, 4, 0x30, 0x10, 5, 1), -+ PIN_FIELD_BASE(35, 35, 4, 0x30, 0x10, 7, 1), -+ -+ PIN_FIELD_BASE(36, 36, 3, 0x20, 0x10, 2, 1), -+ PIN_FIELD_BASE(37, 37, 3, 0x20, 0x10, 3, 1), -+ PIN_FIELD_BASE(38, 38, 3, 0x20, 0x10, 0, 1), -+ PIN_FIELD_BASE(39, 39, 3, 0x20, 0x10, 1, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_r0_range[] = { -+ PIN_FIELD_BASE(0, 0, 1, 0x30, 0x10, 1, 1), -+ PIN_FIELD_BASE(1, 1, 1, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(2, 2, 5, 0x40, 0x10, 6, 1), -+ PIN_FIELD_BASE(3, 3, 4, 0x40, 0x10, 6, 1), -+ PIN_FIELD_BASE(4, 4, 4, 0x40, 0x10, 2, 1), -+ PIN_FIELD_BASE(5, 5, 4, 0x40, 0x10, 1, 1), -+ PIN_FIELD_BASE(6, 6, 4, 0x40, 0x10, 3, 1), -+ PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1), -+ PIN_FIELD_BASE(9, 9, 4, 0x40, 0x10, 9, 1), -+ -+ PIN_FIELD_BASE(10, 10, 5, 0x40, 0x10, 8, 1), -+ PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1), -+ PIN_FIELD_BASE(12, 12, 5, 0x40, 0x10, 7, 1), -+ PIN_FIELD_BASE(13, 13, 5, 0x40, 0x10, 11, 1), -+ -+ PIN_FIELD_BASE(14, 14, 4, 0x40, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(15, 15, 2, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(16, 16, 2, 0x40, 0x10, 1, 1), -+ PIN_FIELD_BASE(17, 17, 2, 0x40, 0x10, 5, 1), -+ PIN_FIELD_BASE(18, 18, 2, 0x40, 0x10, 4, 1), -+ PIN_FIELD_BASE(19, 19, 2, 0x40, 0x10, 2, 1), -+ PIN_FIELD_BASE(20, 20, 2, 0x40, 0x10, 3, 1), -+ PIN_FIELD_BASE(21, 21, 2, 0x40, 0x10, 6, 1), -+ PIN_FIELD_BASE(22, 22, 2, 0x40, 0x10, 7, 1), -+ PIN_FIELD_BASE(23, 23, 2, 0x40, 0x10, 10, 1), -+ PIN_FIELD_BASE(24, 24, 2, 0x40, 0x10, 9, 1), -+ PIN_FIELD_BASE(25, 25, 2, 0x40, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(26, 26, 5, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(27, 27, 5, 0x40, 0x10, 4, 1), -+ PIN_FIELD_BASE(28, 28, 5, 0x40, 0x10, 3, 1), -+ PIN_FIELD_BASE(29, 29, 5, 0x40, 0x10, 1, 1), -+ PIN_FIELD_BASE(30, 30, 5, 0x40, 0x10, 2, 1), -+ PIN_FIELD_BASE(31, 31, 5, 0x40, 0x10, 5, 1), -+ -+ PIN_FIELD_BASE(32, 32, 1, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(33, 33, 1, 0x30, 0x10, 3, 1), -+ -+ PIN_FIELD_BASE(34, 34, 4, 0x40, 0x10, 5, 1), -+ PIN_FIELD_BASE(35, 35, 4, 0x40, 0x10, 7, 1), -+ -+ PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 3, 1), -+ PIN_FIELD_BASE(38, 38, 3, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(39, 39, 3, 0x30, 0x10, 1, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_r1_range[] = { -+ PIN_FIELD_BASE(0, 0, 1, 0x40, 0x10, 1, 1), -+ PIN_FIELD_BASE(1, 1, 1, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 6, 1), -+ PIN_FIELD_BASE(3, 3, 4, 0x50, 0x10, 6, 1), -+ PIN_FIELD_BASE(4, 4, 4, 0x50, 0x10, 2, 1), -+ PIN_FIELD_BASE(5, 5, 4, 0x50, 0x10, 1, 1), -+ PIN_FIELD_BASE(6, 6, 4, 0x50, 0x10, 3, 1), -+ PIN_FIELD_BASE(7, 7, 4, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(8, 8, 4, 0x50, 0x10, 4, 1), -+ PIN_FIELD_BASE(9, 9, 4, 0x50, 0x10, 9, 1), -+ -+ PIN_FIELD_BASE(10, 10, 5, 0x50, 0x10, 8, 1), -+ PIN_FIELD_BASE(11, 11, 5, 0x50, 0x10, 10, 1), -+ PIN_FIELD_BASE(12, 12, 5, 0x50, 0x10, 7, 1), -+ PIN_FIELD_BASE(13, 13, 5, 0x50, 0x10, 11, 1), -+ -+ PIN_FIELD_BASE(14, 14, 4, 0x50, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(15, 15, 2, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(16, 16, 2, 0x50, 0x10, 1, 1), -+ PIN_FIELD_BASE(17, 17, 2, 0x50, 0x10, 5, 1), -+ PIN_FIELD_BASE(18, 18, 2, 0x50, 0x10, 4, 1), -+ PIN_FIELD_BASE(19, 19, 2, 0x50, 0x10, 2, 1), -+ PIN_FIELD_BASE(20, 20, 2, 0x50, 0x10, 3, 1), -+ PIN_FIELD_BASE(21, 21, 2, 0x50, 0x10, 6, 1), -+ PIN_FIELD_BASE(22, 22, 2, 0x50, 0x10, 7, 1), -+ PIN_FIELD_BASE(23, 23, 2, 0x50, 0x10, 10, 1), -+ PIN_FIELD_BASE(24, 24, 2, 0x50, 0x10, 9, 1), -+ PIN_FIELD_BASE(25, 25, 2, 0x50, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(26, 26, 5, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(27, 27, 5, 0x50, 0x10, 4, 1), -+ PIN_FIELD_BASE(28, 28, 5, 0x50, 0x10, 3, 1), -+ PIN_FIELD_BASE(29, 29, 5, 0x50, 0x10, 1, 1), -+ PIN_FIELD_BASE(30, 30, 5, 0x50, 0x10, 2, 1), -+ PIN_FIELD_BASE(31, 31, 5, 0x50, 0x10, 5, 1), -+ -+ PIN_FIELD_BASE(32, 32, 1, 0x40, 0x10, 2, 1), -+ PIN_FIELD_BASE(33, 33, 1, 0x40, 0x10, 3, 1), -+ -+ PIN_FIELD_BASE(34, 34, 4, 0x50, 0x10, 5, 1), -+ PIN_FIELD_BASE(35, 35, 4, 0x50, 0x10, 7, 1), -+ -+ PIN_FIELD_BASE(36, 36, 3, 0x40, 0x10, 2, 1), -+ PIN_FIELD_BASE(37, 37, 3, 0x40, 0x10, 3, 1), -+ PIN_FIELD_BASE(38, 38, 3, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(39, 39, 3, 0x40, 0x10, 1, 1), -+}; -+ -+static const struct mtk_pin_reg_calc mt7981_reg_cals[] = { -+ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7981_pin_mode_range), -+ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7981_pin_dir_range), -+ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7981_pin_di_range), -+ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7981_pin_do_range), -+ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7981_pin_smt_range), -+ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7981_pin_ies_range), -+ [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7981_pin_pu_range), -+ [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7981_pin_pd_range), -+ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7981_pin_drv_range), -+ [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7981_pin_pupd_range), -+ [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7981_pin_r0_range), -+ [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7981_pin_r1_range), -+}; -+ -+static const struct mtk_pin_desc mt7981_pins[] = { -+ MT7981_TYPE0_PIN(0, "GPIO_WPS"), -+ MT7981_TYPE0_PIN(1, "GPIO_RESET"), -+ MT7981_TYPE0_PIN(2, "SYS_WATCHDOG"), -+ MT7981_TYPE0_PIN(3, "PCIE_PERESET_N"), -+ MT7981_TYPE0_PIN(4, "JTAG_JTDO"), -+ MT7981_TYPE0_PIN(5, "JTAG_JTDI"), -+ MT7981_TYPE0_PIN(6, "JTAG_JTMS"), -+ MT7981_TYPE0_PIN(7, "JTAG_JTCLK"), -+ MT7981_TYPE0_PIN(8, "JTAG_JTRST_N"), -+ MT7981_TYPE0_PIN(9, "WO_JTAG_JTDO"), -+ MT7981_TYPE0_PIN(10, "WO_JTAG_JTDI"), -+ MT7981_TYPE0_PIN(11, "WO_JTAG_JTMS"), -+ MT7981_TYPE0_PIN(12, "WO_JTAG_JTCLK"), -+ MT7981_TYPE0_PIN(13, "WO_JTAG_JTRST_N"), -+ MT7981_TYPE0_PIN(14, "USB_VBUS"), -+ MT7981_TYPE0_PIN(15, "PWM0"), -+ MT7981_TYPE0_PIN(16, "SPI0_CLK"), -+ MT7981_TYPE0_PIN(17, "SPI0_MOSI"), -+ MT7981_TYPE0_PIN(18, "SPI0_MISO"), -+ MT7981_TYPE0_PIN(19, "SPI0_CS"), -+ MT7981_TYPE0_PIN(20, "SPI0_HOLD"), -+ MT7981_TYPE0_PIN(21, "SPI0_WP"), -+ MT7981_TYPE0_PIN(22, "SPI1_CLK"), -+ MT7981_TYPE0_PIN(23, "SPI1_MOSI"), -+ MT7981_TYPE0_PIN(24, "SPI1_MISO"), -+ MT7981_TYPE0_PIN(25, "SPI1_CS"), -+ MT7981_TYPE0_PIN(26, "SPI2_CLK"), -+ MT7981_TYPE0_PIN(27, "SPI2_MOSI"), -+ MT7981_TYPE0_PIN(28, "SPI2_MISO"), -+ MT7981_TYPE0_PIN(29, "SPI2_CS"), -+ MT7981_TYPE0_PIN(30, "SPI2_HOLD"), -+ MT7981_TYPE0_PIN(31, "SPI2_WP"), -+ MT7981_TYPE0_PIN(32, "UART0_RXD"), -+ MT7981_TYPE0_PIN(33, "UART0_TXD"), -+ MT7981_TYPE0_PIN(34, "PCIE_CLK_REQ"), -+ MT7981_TYPE0_PIN(35, "PCIE_WAKE_N"), -+ MT7981_TYPE0_PIN(36, "SMI_MDC"), -+ MT7981_TYPE0_PIN(37, "SMI_MDIO"), -+ MT7981_TYPE0_PIN(38, "GBE_INT"), -+ MT7981_TYPE0_PIN(39, "GBE_RESET"), -+ MT7981_TYPE1_PIN(40, "WF_DIG_RESETB"), -+ MT7981_TYPE1_PIN(41, "WF_CBA_RESETB"), -+ MT7981_TYPE1_PIN(42, "WF_XO_REQ"), -+ MT7981_TYPE1_PIN(43, "WF_TOP_CLK"), -+ MT7981_TYPE1_PIN(44, "WF_TOP_DATA"), -+ MT7981_TYPE1_PIN(45, "WF_HB1"), -+ MT7981_TYPE1_PIN(46, "WF_HB2"), -+ MT7981_TYPE1_PIN(47, "WF_HB3"), -+ MT7981_TYPE1_PIN(48, "WF_HB4"), -+ MT7981_TYPE1_PIN(49, "WF_HB0"), -+ MT7981_TYPE1_PIN(50, "WF_HB0_B"), -+ MT7981_TYPE1_PIN(51, "WF_HB5"), -+ MT7981_TYPE1_PIN(52, "WF_HB6"), -+ MT7981_TYPE1_PIN(53, "WF_HB7"), -+ MT7981_TYPE1_PIN(54, "WF_HB8"), -+ MT7981_TYPE1_PIN(55, "WF_HB9"), -+ MT7981_TYPE1_PIN(56, "WF_HB10"), -+}; -+ -+/* WA_AICE */ -+static int mt7981_wa_aice1_pins[] = { 0, 1, }; -+static int mt7981_wa_aice1_funcs[] = { 2, 2, }; -+ -+static int mt7981_wa_aice2_pins[] = { 0, 1, }; -+static int mt7981_wa_aice2_funcs[] = { 3, 3, }; -+ -+static int mt7981_wa_aice3_pins[] = { 28, 29, }; -+static int mt7981_wa_aice3_funcs[] = { 3, 3, }; -+ -+static int mt7981_wm_aice1_pins[] = { 9, 10, }; -+static int mt7981_wm_aice1_funcs[] = { 2, 2, }; -+ -+static int mt7981_wm_aice2_pins[] = { 30, 31, }; -+static int mt7981_wm_aice2_funcs[] = { 5, 5, }; -+ -+/* WM_UART */ -+static int mt7981_wm_uart_0_pins[] = { 0, 1, }; -+static int mt7981_wm_uart_0_funcs[] = { 5, 5, }; -+ -+static int mt7981_wm_uart_1_pins[] = { 20, 21, }; -+static int mt7981_wm_uart_1_funcs[] = { 4, 4, }; -+ -+static int mt7981_wm_uart_2_pins[] = { 30, 31, }; -+static int mt7981_wm_uart_2_funcs[] = { 3, 3, }; -+ -+/* DFD */ -+static int mt7981_dfd_pins[] = { 0, 1, 4, 5, }; -+static int mt7981_dfd_funcs[] = { 5, 5, 6, 6, }; -+ -+/* SYS_WATCHDOG */ -+static int mt7981_watchdog_pins[] = { 2, }; -+static int mt7981_watchdog_funcs[] = { 1, }; -+ -+static int mt7981_watchdog1_pins[] = { 13, }; -+static int mt7981_watchdog1_funcs[] = { 5, }; -+ -+/* PCIE_PERESET_N */ -+static int mt7981_pcie_pereset_pins[] = { 3, }; -+static int mt7981_pcie_pereset_funcs[] = { 1, }; -+ -+/* JTAG */ -+static int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, }; -+static int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, }; -+ -+/* WM_JTAG */ -+static int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, }; -+static int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, }; -+ -+static int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, }; -+static int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; -+ -+/* WO0_JTAG */ -+static int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, }; -+static int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, }; -+ -+static int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, }; -+static int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; -+ -+/* UART2 */ -+static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, }; -+static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, }; -+ -+/* GBE_LED0 */ -+static int mt7981_gbe_led0_pins[] = { 8, }; -+static int mt7981_gbe_led0_funcs[] = { 3, }; -+ -+/* PTA_EXT */ -+static int mt7981_pta_ext_0_pins[] = { 4, 5, 6, }; -+static int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, }; -+ -+static int mt7981_pta_ext_1_pins[] = { 22, 23, 24, }; -+static int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, }; -+ -+/* PWM2 */ -+static int mt7981_pwm2_pins[] = { 7, }; -+static int mt7981_pwm2_funcs[] = { 4, }; -+ -+/* NET_WO0_UART_TXD */ -+static int mt7981_net_wo0_uart_txd_0_pins[] = { 8, }; -+static int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, }; -+ -+static int mt7981_net_wo0_uart_txd_1_pins[] = { 14, }; -+static int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, }; -+ -+static int mt7981_net_wo0_uart_txd_2_pins[] = { 15, }; -+static int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, }; -+ -+/* SPI1 */ -+static int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, }; -+static int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, }; -+ -+/* I2C */ -+static int mt7981_i2c0_0_pins[] = { 6, 7, }; -+static int mt7981_i2c0_0_funcs[] = { 6, 6, }; -+ -+static int mt7981_i2c0_1_pins[] = { 30, 31, }; -+static int mt7981_i2c0_1_funcs[] = { 4, 4, }; -+ -+static int mt7981_i2c0_2_pins[] = { 36, 37, }; -+static int mt7981_i2c0_2_funcs[] = { 2, 2, }; -+ -+static int mt7981_u2_phy_i2c_pins[] = { 30, 31, }; -+static int mt7981_u2_phy_i2c_funcs[] = { 6, 6, }; -+ -+static int mt7981_u3_phy_i2c_pins[] = { 32, 33, }; -+static int mt7981_u3_phy_i2c_funcs[] = { 3, 3, }; -+ -+static int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, }; -+static int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, }; -+ -+static int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, }; -+static int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, }; -+ -+/* DFD_NTRST */ -+static int mt7981_dfd_ntrst_pins[] = { 8, }; -+static int mt7981_dfd_ntrst_funcs[] = { 6, }; -+ -+/* PWM0 */ -+static int mt7981_pwm0_0_pins[] = { 13, }; -+static int mt7981_pwm0_0_funcs[] = { 2, }; -+ -+static int mt7981_pwm0_1_pins[] = { 15, }; -+static int mt7981_pwm0_1_funcs[] = { 1, }; -+ -+/* PWM1 */ -+static int mt7981_pwm1_0_pins[] = { 14, }; -+static int mt7981_pwm1_0_funcs[] = { 2, }; -+ -+static int mt7981_pwm1_1_pins[] = { 15, }; -+static int mt7981_pwm1_1_funcs[] = { 3, }; -+ -+/* GBE_LED1 */ -+static int mt7981_gbe_led1_pins[] = { 13, }; -+static int mt7981_gbe_led1_funcs[] = { 3, }; -+ -+/* PCM */ -+static int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 }; -+static int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, }; -+ -+/* UDI */ -+static int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, }; -+static int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, }; -+ -+/* DRV_VBUS */ -+static int mt7981_drv_vbus_pins[] = { 14, }; -+static int mt7981_drv_vbus_funcs[] = { 1, }; -+ -+/* EMMC */ -+static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, }; -+static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; -+ -+/* SNFI */ -+static int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, }; -+static int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, }; -+ -+/* SPI0 */ -+static int mt7981_spi0_pins[] = { 16, 17, 18, 19, }; -+static int mt7981_spi0_funcs[] = { 1, 1, 1, 1, }; -+ -+/* SPI0 */ -+static int mt7981_spi0_wp_hold_pins[] = { 20, 21, }; -+static int mt7981_spi0_wp_hold_funcs[] = { 1, 1, }; -+ -+/* SPI1 */ -+static int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, }; -+static int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, }; -+ -+/* SPI2 */ -+static int mt7981_spi2_pins[] = { 26, 27, 28, 29, }; -+static int mt7981_spi2_funcs[] = { 1, 1, 1, 1, }; -+ -+/* SPI2 */ -+static int mt7981_spi2_wp_hold_pins[] = { 30, 31, }; -+static int mt7981_spi2_wp_hold_funcs[] = { 1, 1, }; -+ -+/* UART1 */ -+static int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, }; -+static int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, }; -+ -+static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, }; -+static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, }; -+ -+/* UART2 */ -+static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, }; -+static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, }; -+ -+/* UART0 */ -+static int mt7981_uart0_pins[] = { 32, 33, }; -+static int mt7981_uart0_funcs[] = { 1, 1, }; -+ -+/* PCIE_CLK_REQ */ -+static int mt7981_pcie_clk_pins[] = { 34, }; -+static int mt7981_pcie_clk_funcs[] = { 2, }; -+ -+/* PCIE_WAKE_N */ -+static int mt7981_pcie_wake_pins[] = { 35, }; -+static int mt7981_pcie_wake_funcs[] = { 2, }; -+ -+/* MDC_MDIO */ -+static int mt7981_smi_mdc_mdio_pins[] = { 36, 37, }; -+static int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, }; -+ -+static int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, }; -+static int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, }; -+ -+/* WF0_MODE1 */ -+static int mt7981_wf0_mode1_pins[] = { 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, -+ 50, 51, 52, 53, 54, 55, 56 }; -+static int mt7981_wf0_mode1_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, -+ 1, 1, 1, 1 }; -+ -+/* WF0_MODE3 */ -+static int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 }; -+static int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 }; -+ -+/* WF2G_LED */ -+static int mt7981_wf2g_led0_pins[] = { 30, }; -+static int mt7981_wf2g_led0_funcs[] = { 2, }; -+ -+static int mt7981_wf2g_led1_pins[] = { 34, }; -+static int mt7981_wf2g_led1_funcs[] = { 1, }; -+ -+/* WF5G_LED */ -+static int mt7981_wf5g_led0_pins[] = { 31, }; -+static int mt7981_wf5g_led0_funcs[] = { 2, }; -+ -+static int mt7981_wf5g_led1_pins[] = { 35, }; -+static int mt7981_wf5g_led1_funcs[] = { 1, }; -+ -+/* MT7531_INT */ -+static int mt7981_mt7531_int_pins[] = { 38, }; -+static int mt7981_mt7531_int_funcs[] = { 1, }; -+ -+/* ANT_SEL */ -+static int mt7981_ant_sel_pins[] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 }; -+static int mt7981_ant_sel_funcs[] = { 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 }; -+ -+static const struct mtk_group_desc mt7981_groups[] = { -+ /* @GPIO(0,1): WA_AICE(2) */ -+ PINCTRL_PIN_GROUP("wa_aice1", mt7981_wa_aice1), -+ /* @GPIO(0,1): WA_AICE(3) */ -+ PINCTRL_PIN_GROUP("wa_aice2", mt7981_wa_aice2), -+ /* @GPIO(0,1): WM_UART(5) */ -+ PINCTRL_PIN_GROUP("wm_uart_0", mt7981_wm_uart_0), -+ /* @GPIO(0,1,4,5): DFD(6) */ -+ PINCTRL_PIN_GROUP("dfd", mt7981_dfd), -+ /* @GPIO(2): SYS_WATCHDOG(1) */ -+ PINCTRL_PIN_GROUP("watchdog", mt7981_watchdog), -+ /* @GPIO(3): PCIE_PERESET_N(1) */ -+ PINCTRL_PIN_GROUP("pcie_pereset", mt7981_pcie_pereset), -+ /* @GPIO(4,8) JTAG(1) */ -+ PINCTRL_PIN_GROUP("jtag", mt7981_jtag), -+ /* @GPIO(4,8) WM_JTAG(2) */ -+ PINCTRL_PIN_GROUP("wm_jtag_0", mt7981_wm_jtag_0), -+ /* @GPIO(9,13) WO0_JTAG(1) */ -+ PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0), -+ /* @GPIO(4,7) WM_JTAG(3) */ -+ PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0), -+ /* @GPIO(8) GBE_LED0(3) */ -+ PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0), -+ /* @GPIO(4,6) PTA_EXT(4) */ -+ PINCTRL_PIN_GROUP("pta_ext_0", mt7981_pta_ext_0), -+ /* @GPIO(7) PWM2(4) */ -+ PINCTRL_PIN_GROUP("pwm2", mt7981_pwm2), -+ /* @GPIO(8) NET_WO0_UART_TXD(4) */ -+ PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7981_net_wo0_uart_txd_0), -+ /* @GPIO(4,7) SPI1(5) */ -+ PINCTRL_PIN_GROUP("spi1_0", mt7981_spi1_0), -+ /* @GPIO(6,7) I2C(5) */ -+ PINCTRL_PIN_GROUP("i2c0_0", mt7981_i2c0_0), -+ /* @GPIO(8): DFD_NTRST(6) */ -+ PINCTRL_PIN_GROUP("dfd_ntrst", mt7981_dfd_ntrst), -+ /* @GPIO(9,10): WM_AICE(2) */ -+ PINCTRL_PIN_GROUP("wm_aice1", mt7981_wm_aice1), -+ /* @GPIO(13): PWM0(2) */ -+ PINCTRL_PIN_GROUP("pwm0_0", mt7981_pwm0_0), -+ /* @GPIO(15): PWM0(1) */ -+ PINCTRL_PIN_GROUP("pwm0_1", mt7981_pwm0_1), -+ /* @GPIO(14): PWM1(2) */ -+ PINCTRL_PIN_GROUP("pwm1_0", mt7981_pwm1_0), -+ /* @GPIO(15): PWM1(3) */ -+ PINCTRL_PIN_GROUP("pwm1_1", mt7981_pwm1_1), -+ /* @GPIO(14) NET_WO0_UART_TXD(3) */ -+ PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7981_net_wo0_uart_txd_1), -+ /* @GPIO(15) NET_WO0_UART_TXD(4) */ -+ PINCTRL_PIN_GROUP("net_wo0_uart_txd_2", mt7981_net_wo0_uart_txd_2), -+ /* @GPIO(13) GBE_LED0(3) */ -+ PINCTRL_PIN_GROUP("gbe_led1", mt7981_gbe_led1), -+ /* @GPIO(9,13) PCM(4) */ -+ PINCTRL_PIN_GROUP("pcm", mt7981_pcm), -+ /* @GPIO(13): SYS_WATCHDOG1(5) */ -+ PINCTRL_PIN_GROUP("watchdog1", mt7981_watchdog1), -+ /* @GPIO(9,13) UDI(4) */ -+ PINCTRL_PIN_GROUP("udi", mt7981_udi), -+ /* @GPIO(14) DRV_VBUS(1) */ -+ PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus), -+ /* @GPIO(15,25): EMMC(2) */ -+ PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45), -+ /* @GPIO(16,21): SNFI(3) */ -+ PINCTRL_PIN_GROUP("snfi", mt7981_snfi), -+ /* @GPIO(16,19): SPI0(1) */ -+ PINCTRL_PIN_GROUP("spi0", mt7981_spi0), -+ /* @GPIO(20,21): SPI0(1) */ -+ PINCTRL_PIN_GROUP("spi0_wp_hold", mt7981_spi0_wp_hold), -+ /* @GPIO(22,25) SPI1(1) */ -+ PINCTRL_PIN_GROUP("spi1_1", mt7981_spi1_1), -+ /* @GPIO(26,29): SPI2(1) */ -+ PINCTRL_PIN_GROUP("spi2", mt7981_spi2), -+ /* @GPIO(30,31): SPI2(1) */ -+ PINCTRL_PIN_GROUP("spi2_wp_hold", mt7981_spi2_wp_hold), -+ /* @GPIO(16,19): UART1(4) */ -+ PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0), -+ /* @GPIO(26,29): UART1(2) */ -+ PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1), -+ /* @GPIO(22,25): UART2(3) */ -+ PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_1), -+ /* @GPIO(22,24) PTA_EXT(4) */ -+ PINCTRL_PIN_GROUP("pta_ext_1", mt7981_pta_ext_1), -+ /* @GPIO(20,21): WM_UART(4) */ -+ PINCTRL_PIN_GROUP("wm_aurt_1", mt7981_wm_uart_1), -+ /* @GPIO(30,31): WM_UART(3) */ -+ PINCTRL_PIN_GROUP("wm_aurt_2", mt7981_wm_uart_2), -+ /* @GPIO(20,24) WM_JTAG(5) */ -+ PINCTRL_PIN_GROUP("wm_jtag_1", mt7981_wm_jtag_1), -+ /* @GPIO(25,29) WO0_JTAG(5) */ -+ PINCTRL_PIN_GROUP("wo0_jtag_1", mt7981_wo0_jtag_1), -+ /* @GPIO(28,29): WA_AICE(3) */ -+ PINCTRL_PIN_GROUP("wa_aice3", mt7981_wa_aice3), -+ /* @GPIO(30,31): WM_AICE(5) */ -+ PINCTRL_PIN_GROUP("wm_aice2", mt7981_wm_aice2), -+ /* @GPIO(30,31): I2C(4) */ -+ PINCTRL_PIN_GROUP("i2c0_1", mt7981_i2c0_1), -+ /* @GPIO(30,31): I2C(6) */ -+ PINCTRL_PIN_GROUP("u2_phy_i2c", mt7981_u2_phy_i2c), -+ /* @GPIO(32,33): I2C(1) */ -+ PINCTRL_PIN_GROUP("uart0", mt7981_uart0), -+ /* @GPIO(32,33): I2C(2) */ -+ PINCTRL_PIN_GROUP("sgmii1_phy_i2c", mt7981_sgmii1_phy_i2c), -+ /* @GPIO(32,33): I2C(3) */ -+ PINCTRL_PIN_GROUP("u3_phy_i2c", mt7981_u3_phy_i2c), -+ /* @GPIO(32,33): I2C(5) */ -+ PINCTRL_PIN_GROUP("sgmii0_phy_i2c", mt7981_sgmii0_phy_i2c), -+ /* @GPIO(34): PCIE_CLK_REQ(2) */ -+ PINCTRL_PIN_GROUP("pcie_clk", mt7981_pcie_clk), -+ /* @GPIO(35): PCIE_WAKE_N(2) */ -+ PINCTRL_PIN_GROUP("pcie_wake", mt7981_pcie_wake), -+ /* @GPIO(36,37): I2C(2) */ -+ PINCTRL_PIN_GROUP("i2c0_2", mt7981_i2c0_2), -+ /* @GPIO(36,37): MDC_MDIO(1) */ -+ PINCTRL_PIN_GROUP("smi_mdc_mdio", mt7981_smi_mdc_mdio), -+ /* @GPIO(36,37): MDC_MDIO(3) */ -+ PINCTRL_PIN_GROUP("gbe_ext_mdc_mdio", mt7981_gbe_ext_mdc_mdio), -+ /* @GPIO(40,56): WF0_MODE1(1) */ -+ PINCTRL_PIN_GROUP("wf0_mode1", mt7981_wf0_mode1), -+ /* @GPIO(45,46,47,48,49,51): WF0_MODE3(3) */ -+ PINCTRL_PIN_GROUP("wf0_mode3", mt7981_wf0_mode3), -+ /* @GPIO(30): WF2G_LED(2) */ -+ PINCTRL_PIN_GROUP("wf2g_led0", mt7981_wf2g_led0), -+ /* @GPIO(34): WF2G_LED(1) */ -+ PINCTRL_PIN_GROUP("wf2g_led1", mt7981_wf2g_led1), -+ /* @GPIO(31): WF5G_LED(2) */ -+ PINCTRL_PIN_GROUP("wf5g_led0", mt7981_wf5g_led0), -+ /* @GPIO(35): WF5G_LED(1) */ -+ PINCTRL_PIN_GROUP("wf5g_led1", mt7981_wf5g_led1), -+ /* @GPIO(38): MT7531_INT(1) */ -+ PINCTRL_PIN_GROUP("mt7531_int", mt7981_mt7531_int), -+ /* @GPIO(14,15,26,17,18,19,20,21,22,23,24,25,34,35): ANT_SEL(1) */ -+ PINCTRL_PIN_GROUP("ant_sel", mt7981_ant_sel), -+}; -+ -+static const struct mtk_io_type_desc mt7981_io_type_desc[] = { -+ [IO_TYPE_GRP0] = { -+ .name = "18OD33", -+ .bias_set = mtk_pinconf_bias_set_pupd_r1_r0, -+ .drive_set = mtk_pinconf_drive_set_v1, -+ .input_enable = mtk_pinconf_input_enable_v1, -+ }, -+ [IO_TYPE_GRP1] = { -+ .name = "18A01", -+ .bias_set = mtk_pinconf_bias_set_pu_pd, -+ .drive_set = mtk_pinconf_drive_set_v1, -+ .input_enable = mtk_pinconf_input_enable_v1, -+ }, -+}; -+ -+/* Joint those groups owning the same capability in user point of view which -+ * allows that people tend to use through the device tree. -+ */ -+static const char *const mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", -+ "wm_aice1_1", "wa_aice3", "wm_aice1_2", }; -+static const char *const mt7981_uart_groups[] = { "wm_uart_0", "uart2_0", -+ "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2", -+ "uart1_0", "uart1_1", "uart2_0", "wm_aurt_1", "wm_aurt_2", "uart0", }; -+static const char *const mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", }; -+static const char *const mt7981_wdt_groups[] = { "watchdog", "watchdog1", }; -+static const char *const mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", -+ "pcie_wake", }; -+static const char *const mt7981_jtag_groups[] = { "jtag", "wm_jtag_0", -+ "wo0_jtag_0", "wo0_jtag_1", "wm_jtag_1", }; -+static const char *const mt7981_led_groups[] = { "gbe_led0", "gbe_led1", -+ "wf2g_led0", "wf2g_led1", "wf5g_led0", "wf5g_led1", }; -+static const char *const mt7981_pta_groups[] = { "pta_ext_0", "pta_ext_1", }; -+static const char *const mt7981_pwm_groups[] = { "pwm2", "pwm0_0", "pwm0_1", -+ "pwm1_0", "pwm1_1", }; -+static const char *const mt7981_spi_groups[] = { "spi1_0", "spi0", -+ "spi0_wp_hold", "spi1_1", "spi2", "spi2_wp_hold", }; -+static const char *const mt7981_i2c_groups[] = { "i2c0_0", "i2c0_1", -+ "u2_phy_i2c", "sgmii1_phy_i2c", "u3_phy_i2c", "sgmii0_phy_i2c", -+ "i2c0_2", }; -+static const char *const mt7981_pcm_groups[] = { "pcm", }; -+static const char *const mt7981_udi_groups[] = { "udi", }; -+static const char *const mt7981_usb_groups[] = { "drv_vbus", }; -+static const char *const mt7981_flash_groups[] = { "emmc_45", "snfi", }; -+static const char *const mt7981_ethernet_groups[] = { "smi_mdc_mdio", -+ "gbe_ext_mdc_mdio", "wf0_mode1", "wf0_mode3", "mt7531_int", }; -+static const char *const mt7981_ant_groups[] = { "ant_sel", }; -+ -+static const struct mtk_function_desc mt7981_functions[] = { -+ {"wa_aice", mt7981_wa_aice_groups, ARRAY_SIZE(mt7981_wa_aice_groups)}, -+ {"dfd", mt7981_dfd_groups, ARRAY_SIZE(mt7981_dfd_groups)}, -+ {"jtag", mt7981_jtag_groups, ARRAY_SIZE(mt7981_jtag_groups)}, -+ {"pta", mt7981_pta_groups, ARRAY_SIZE(mt7981_pta_groups)}, -+ {"pcm", mt7981_pcm_groups, ARRAY_SIZE(mt7981_pcm_groups)}, -+ {"udi", mt7981_udi_groups, ARRAY_SIZE(mt7981_udi_groups)}, -+ {"usb", mt7981_usb_groups, ARRAY_SIZE(mt7981_usb_groups)}, -+ {"ant", mt7981_ant_groups, ARRAY_SIZE(mt7981_ant_groups)}, -+ {"eth", mt7981_ethernet_groups, ARRAY_SIZE(mt7981_ethernet_groups)}, -+ {"i2c", mt7981_i2c_groups, ARRAY_SIZE(mt7981_i2c_groups)}, -+ {"led", mt7981_led_groups, ARRAY_SIZE(mt7981_led_groups)}, -+ {"pwm", mt7981_pwm_groups, ARRAY_SIZE(mt7981_pwm_groups)}, -+ {"spi", mt7981_spi_groups, ARRAY_SIZE(mt7981_spi_groups)}, -+ {"uart", mt7981_uart_groups, ARRAY_SIZE(mt7981_uart_groups)}, -+ {"watchdog", mt7981_wdt_groups, ARRAY_SIZE(mt7981_wdt_groups)}, -+ {"flash", mt7981_flash_groups, ARRAY_SIZE(mt7981_flash_groups)}, -+ {"pcie", mt7981_pcie_groups, ARRAY_SIZE(mt7981_pcie_groups)}, -+}; -+ -+static const char *const mt7981_pinctrl_register_base_names[] = { -+ "gpio_base", "iocfg_rt_base", "iocfg_rm_base", "iocfg_rb_base", -+ "iocfg_lb_base", "iocfg_bl_base", "iocfg_tm_base", "iocfg_tl_base", -+}; -+ -+static struct mtk_pinctrl_soc mt7981_data = { -+ .name = "mt7981_pinctrl", -+ .reg_cal = mt7981_reg_cals, -+ .pins = mt7981_pins, -+ .npins = ARRAY_SIZE(mt7981_pins), -+ .grps = mt7981_groups, -+ .ngrps = ARRAY_SIZE(mt7981_groups), -+ .funcs = mt7981_functions, -+ .nfuncs = ARRAY_SIZE(mt7981_functions), -+ .io_type = mt7981_io_type_desc, -+ .ntype = ARRAY_SIZE(mt7981_io_type_desc), -+ .gpio_mode = 0, -+ .base_names = mt7981_pinctrl_register_base_names, -+ .nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names), -+ .base_calc = 1, -+}; -+ -+static int mtk_pinctrl_mt7981_probe(struct udevice *dev) -+{ -+ return mtk_pinctrl_common_probe(dev, &mt7981_data); -+} -+ -+static const struct udevice_id mt7981_pctrl_match[] = { -+ {.compatible = "mediatek,mt7981-pinctrl"}, -+ { /* sentinel */ } -+}; -+ -+U_BOOT_DRIVER(mt7981_pinctrl) = { -+ .name = "mt7981_pinctrl", -+ .id = UCLASS_PINCTRL, -+ .of_match = mt7981_pctrl_match, -+ .ops = &mtk_pinctrl_ops, -+ .probe = mtk_pinctrl_mt7981_probe, -+ .priv_auto = sizeof(struct mtk_pinctrl_priv), -+}; diff --git a/package/boot/uboot-mediatek/patches/002-0021-pinctrl-mediatek-add-pinctrl-driver-for-MT7986-SoC.patch b/package/boot/uboot-mediatek/patches/002-0021-pinctrl-mediatek-add-pinctrl-driver-for-MT7986-SoC.patch deleted file mode 100644 index 56bb68c8b6b..00000000000 --- a/package/boot/uboot-mediatek/patches/002-0021-pinctrl-mediatek-add-pinctrl-driver-for-MT7986-SoC.patch +++ /dev/null @@ -1,817 +0,0 @@ -From 201880cacf1498dd4c6749780163157148d0445d Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 31 Aug 2022 19:04:57 +0800 -Subject: [PATCH 21/32] pinctrl: mediatek: add pinctrl driver for MT7986 SoC - -This patch adds pinctrl and gpio support for MT7986 SoC - -Reviewed-by: Simon Glass -Signed-off-by: Weijie Gao ---- - drivers/pinctrl/mediatek/Kconfig | 4 + - drivers/pinctrl/mediatek/Makefile | 1 + - drivers/pinctrl/mediatek/pinctrl-mt7986.c | 775 ++++++++++++++++++++++ - 3 files changed, 780 insertions(+) - create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7986.c - ---- a/drivers/pinctrl/mediatek/Kconfig -+++ b/drivers/pinctrl/mediatek/Kconfig -@@ -20,6 +20,10 @@ config PINCTRL_MT7981 - bool "MT7981 SoC pinctrl driver" - select PINCTRL_MTK - -+config PINCTRL_MT7986 -+ bool "MT7986 SoC pinctrl driver" -+ select PINCTRL_MTK -+ - config PINCTRL_MT8512 - bool "MT8512 SoC pinctrl driver" - select PINCTRL_MTK ---- a/drivers/pinctrl/mediatek/Makefile -+++ b/drivers/pinctrl/mediatek/Makefile -@@ -7,6 +7,7 @@ obj-$(CONFIG_PINCTRL_MT7622) += pinctrl- - obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o - obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o - obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o -+obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o - obj-$(CONFIG_PINCTRL_MT8512) += pinctrl-mt8512.o - obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o - obj-$(CONFIG_PINCTRL_MT8518) += pinctrl-mt8518.o ---- /dev/null -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c -@@ -0,0 +1,775 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * The MT7986 driver based on Linux generic pinctrl binding. -+ * -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Sam Shih -+ */ -+ -+#include -+#include "pinctrl-mtk-common.h" -+ -+#define MT7986_TYPE0_PIN(_number, _name) \ -+ MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP0) -+ -+#define MT7986_TYPE1_PIN(_number, _name) \ -+ MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP1) -+ -+#define PIN_FIELD_GPIO(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ -+ PIN_FIELD_BASE_CALC(_s_pin, _e_pin, GPIO_BASE, _s_addr, _x_addrs, \ -+ _s_bit, _x_bits, 32, 0) -+ -+#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ -+ _x_bits) \ -+ PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ -+ _x_bits, 32, 0) -+ -+/** -+ * enum - Locking variants of the iocfg bases -+ * -+ * MT7986 have multiple bases to program pin configuration listed as the below: -+ * iocfg_rt:0x11c30000, iocfg_rb:0x11c40000, iocfg_lt:0x11e20000, -+ * iocfg_lb:0x11e30000, iocfg_tr:0x11f00000, iocfg_tl:0x11f10000, -+ * _i_based could be used to indicate what base the pin should be mapped into. -+ * -+ * Each iocfg register base control different group of pads on the SoC -+ * -+ * -+ * chip carrier -+ * -+ * A B C D E F G H -+ * +------------------------+ -+ * 8 | o o o o o o o o | -+ * 7 | o o o o o o o o | -+ * 6 | o o o o o o o o | -+ * 5 | o o o o o o o o | -+ * 4 | o o o o o o o o | -+ * 3 | o o o o o o o o | -+ * 2 | o o o o o o o o | -+ * 1 | o o o o o o o o | -+ * +------------------------+ -+ * -+ * inside Chip carrier -+ * -+ * A B C D E F G H -+ * +------------------------+ -+ * 8 | | -+ * 7 | TL TR | -+ * 6 | +---------+ | -+ * 5 | LT | | RT | -+ * 4 | | | | -+ * 3 | LB | | RB | -+ * 2 | +---------+ | -+ * 1 | | -+ * +------------------------+ -+ * -+ */ -+ -+enum { -+ GPIO_BASE, -+ IOCFG_RT_BASE, -+ IOCFG_RB_BASE, -+ IOCFG_LT_BASE, -+ IOCFG_LB_BASE, -+ IOCFG_TR_BASE, -+ IOCFG_TL_BASE, -+}; -+ -+static const char *const mt7986_pinctrl_register_base_names[] = { -+ "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt", "iocfg_lb", "iocfg_tr", -+ "iocfg_tl", -+}; -+ -+static const struct mtk_pin_field_calc mt7986_pin_mode_range[] = { -+ PIN_FIELD_GPIO(0, 100, 0x300, 0x10, 0, 4), -+}; -+ -+static const struct mtk_pin_field_calc mt7986_pin_dir_range[] = { -+ PIN_FIELD_GPIO(0, 100, 0x0, 0x10, 0, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7986_pin_di_range[] = { -+ PIN_FIELD_GPIO(0, 100, 0x200, 0x10, 0, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7986_pin_do_range[] = { -+ PIN_FIELD_GPIO(0, 100, 0x100, 0x10, 0, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7986_pin_ies_range[] = { -+ PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x40, 0x10, 17, 1), -+ PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x20, 0x10, 10, 1), -+ PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x20, 0x10, 0, 1), -+ PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x20, 0x10, 0, 1), -+ PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x40, 0x10, 8, 1), -+ PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x40, 0x10, 2, 1), -+ PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x30, 0x10, 12, 1), -+ PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x30, 0x10, 18, 1), -+ PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x30, 0x10, 17, 1), -+ PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x30, 0x10, 15, 1), -+ PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x30, 0x10, 19, 1), -+ PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x30, 0x10, 23, 1), -+ PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x30, 0x10, 22, 1), -+ PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x30, 0x10, 21, 1), -+ PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x20, 0x10, 4, 1), -+ PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x20, 0x10, 8, 1), -+ PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x20, 0x10, 7, 1), -+ PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x20, 0x10, 5, 1), -+ PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x20, 0x10, 9, 1), -+ PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x40, 0x10, 18, 1), -+ PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x40, 0x10, 12, 1), -+ PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x40, 0x10, 22, 1), -+ PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x40, 0x10, 20, 1), -+ PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x40, 0x10, 26, 1), -+ PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x40, 0x10, 24, 1), -+ PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x30, 0x10, 1, 1), -+ PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x30, 0x10, 10, 1), -+ PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x40, 0x10, 15, 1), -+ PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x40, 0x10, 14, 1), -+ PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x40, 0x10, 13, 1), -+ PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x40, 0x10, 16, 1), -+ PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x20, 0x10, 2, 1), -+ PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x30, 0x10, 1, 1), -+ PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x30, 0x10, 16, 1), -+ PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x30, 0x10, 14, 1), -+ PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x30, 0x10, 4, 1), -+ PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x30, 0x10, 6, 1), -+ PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x30, 0x10, 9, 1), -+ PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x30, 0x10, 5, 1), -+ PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x30, 0x10, 1, 1), -+ PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x30, 0x10, 14, 1), -+ PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x30, 0x10, 12, 1), -+ PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x30, 0x10, 4, 1), -+ PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x30, 0x10, 8, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7986_pin_smt_range[] = { -+ PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0xf0, 0x10, 17, 1), -+ PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x90, 0x10, 10, 1), -+ PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x90, 0x10, 0, 1), -+ PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0xf0, 0x10, 0, 1), -+ PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x90, 0x10, 0, 1), -+ PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0xf0, 0x10, 8, 1), -+ PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0xf0, 0x10, 2, 1), -+ PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0xc0, 0x10, 12, 1), -+ PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0xc0, 0x10, 18, 1), -+ PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0xc0, 0x10, 17, 1), -+ PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0xc0, 0x10, 15, 1), -+ PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0xc0, 0x10, 19, 1), -+ PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0xc0, 0x10, 23, 1), -+ PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0xc0, 0x10, 22, 1), -+ PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0xc0, 0x10, 21, 1), -+ PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x90, 0x10, 4, 1), -+ PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x90, 0x10, 8, 1), -+ PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x90, 0x10, 7, 1), -+ PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x90, 0x10, 5, 1), -+ PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x90, 0x10, 9, 1), -+ PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0xf0, 0x10, 18, 1), -+ PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0xf0, 0x10, 12, 1), -+ PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0xf0, 0x10, 22, 1), -+ PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0xf0, 0x10, 20, 1), -+ PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0xf0, 0x10, 26, 1), -+ PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0xf0, 0x10, 24, 1), -+ PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0xc0, 0x10, 2, 1), -+ PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0xc0, 0x10, 1, 1), -+ PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0xc0, 0x10, 0, 1), -+ PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0xc0, 0x10, 10, 1), -+ PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0xf0, 0x10, 15, 1), -+ PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0xf0, 0x10, 14, 1), -+ PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0xf0, 0x10, 13, 1), -+ PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0xf0, 0x10, 16, 1), -+ PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x90, 0x10, 2, 1), -+ PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x80, 0x10, 1, 1), -+ PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x80, 0x10, 0, 1), -+ PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x80, 0x10, 16, 1), -+ PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x80, 0x10, 14, 1), -+ PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x80, 0x10, 4, 1), -+ PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x80, 0x10, 6, 1), -+ PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x80, 0x10, 2, 1), -+ PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x80, 0x10, 9, 1), -+ PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x80, 0x10, 5, 1), -+ PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x70, 0x10, 1, 1), -+ PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x70, 0x10, 0, 1), -+ PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x70, 0x10, 14, 1), -+ PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x70, 0x10, 12, 1), -+ PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x70, 0x10, 4, 1), -+ PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x70, 0x10, 2, 1), -+ PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x70, 0x10, 8, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7986_pin_pu_range[] = { -+ PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x50, 0x10, 1, 1), -+ PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x50, 0x10, 16, 1), -+ PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x50, 0x10, 14, 1), -+ PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x50, 0x10, 4, 1), -+ PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x50, 0x10, 6, 1), -+ PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x50, 0x10, 2, 1), -+ PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x50, 0x10, 9, 1), -+ PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x50, 0x10, 5, 1), -+ PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x50, 0x10, 1, 1), -+ PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x50, 0x10, 14, 1), -+ PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x50, 0x10, 12, 1), -+ PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x50, 0x10, 4, 1), -+ PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x50, 0x10, 2, 1), -+ PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x50, 0x10, 8, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7986_pin_pd_range[] = { -+ PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x40, 0x10, 1, 1), -+ PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x40, 0x10, 16, 1), -+ PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x40, 0x10, 14, 1), -+ PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x40, 0x10, 4, 1), -+ PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x40, 0x10, 6, 1), -+ PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x40, 0x10, 2, 1), -+ PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x40, 0x10, 9, 1), -+ PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x40, 0x10, 5, 1), -+ PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x40, 0x10, 1, 1), -+ PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x40, 0x10, 14, 1), -+ PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x40, 0x10, 12, 1), -+ PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x40, 0x10, 4, 1), -+ PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x40, 0x10, 2, 1), -+ PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x40, 0x10, 8, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7986_pin_drv_range[] = { -+ PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x10, 0x10, 21, 3), -+ PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x10, 0x10, 0, 3), -+ PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x00, 0x10, 0, 1), -+ PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0x00, 0x10, 21, 3), -+ PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(11, 12, IOCFG_RB_BASE, 0x00, 0x10, 24, 3), -+ PIN_FIELD_BASE(13, 14, IOCFG_RB_BASE, 0x10, 0x10, 0, 3), -+ PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x10, 0x10, 6, 3), -+ PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x10, 0x10, 24, 3), -+ PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x10, 0x10, 21, 3), -+ PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x10, 0x10, 15, 3), -+ PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0x10, 0x10, 27, 3), -+ PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0x20, 0x10, 0, 3), -+ PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x20, 0x10, 9, 3), -+ PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x20, 0x10, 6, 3), -+ PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x20, 0x10, 3, 3), -+ PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x00, 0x10, 12, 3), -+ PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x00, 0x10, 24, 3), -+ PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x00, 0x10, 21, 3), -+ PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x00, 0x10, 15, 3), -+ PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x00, 0x10, 27, 3), -+ PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x10, 0x10, 27, 3), -+ PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x20, 0x10, 0, 3), -+ PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x10, 0x10, 6, 3), -+ PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x20, 0x10, 9, 3), -+ PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x20, 0x10, 3, 3), -+ PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x20, 0x10, 21, 3), -+ PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x20, 0x10, 15, 3), -+ PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x00, 0x10, 6, 3), -+ PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x10, 0x10, 0, 3), -+ PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x10, 0x10, 15, 3), -+ PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x10, 0x10, 12, 3), -+ PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x10, 0x10, 9, 3), -+ PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x10, 0x10, 18, 3), -+ PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x00, 0x10, 2, 3), -+ PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x10, 0x10, 18, 3), -+ PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x10, 0x10, 12, 3), -+ PIN_FIELD_BASE(74, 77, IOCFG_TR_BASE, 0x00, 0x10, 15, 3), -+ PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x00, 0x10, 6, 3), -+ PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x00, 0x10, 27, 3), -+ PIN_FIELD_BASE(81, 84, IOCFG_TR_BASE, 0x10, 0x10, 0, 3), -+ PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x00, 0x10, 12, 3), -+ PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x10, 0x10, 12, 3), -+ PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x10, 0x10, 6, 3), -+ PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x00, 0x10, 12, 3), -+ PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x00, 0x10, 6, 3), -+ PIN_FIELD_BASE(97, 98, IOCFG_TL_BASE, 0x00, 0x10, 24, 3), -+ PIN_FIELD_BASE(99, 100, IOCFG_TL_BASE, 0x10, 0x10, 2, 3), -+}; -+ -+static const struct mtk_pin_field_calc mt7986_pin_pupd_range[] = { -+ PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x60, 0x10, 17, 1), -+ PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x30, 0x10, 10, 1), -+ PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x60, 0x10, 0, 1), -+ PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x60, 0x10, 8, 1), -+ PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x60, 0x10, 2, 1), -+ PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x40, 0x10, 12, 1), -+ PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x40, 0x10, 18, 1), -+ PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x40, 0x10, 17, 1), -+ PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x40, 0x10, 15, 1), -+ PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x40, 0x10, 19, 1), -+ PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x40, 0x10, 23, 1), -+ PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x40, 0x10, 22, 1), -+ PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x40, 0x10, 21, 1), -+ PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x30, 0x10, 4, 1), -+ PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x30, 0x10, 8, 1), -+ PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x30, 0x10, 7, 1), -+ PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x30, 0x10, 5, 1), -+ PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x30, 0x10, 9, 1), -+ PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x60, 0x10, 18, 1), -+ PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x60, 0x10, 12, 1), -+ PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x60, 0x10, 23, 1), -+ PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x60, 0x10, 21, 1), -+ PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x60, 0x10, 27, 1), -+ PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x60, 0x10, 25, 1), -+ PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x40, 0x10, 2, 1), -+ PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x40, 0x10, 1, 1), -+ PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x40, 0x10, 10, 1), -+ PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x60, 0x10, 15, 1), -+ PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x60, 0x10, 14, 1), -+ PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x60, 0x10, 13, 1), -+ PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x60, 0x10, 16, 1), -+ PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x40, 0x10, 2, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7986_pin_r0_range[] = { -+ PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x70, 0x10, 17, 1), -+ PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x40, 0x10, 10, 1), -+ PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x70, 0x10, 0, 1), -+ PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x70, 0x10, 8, 1), -+ PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x70, 0x10, 2, 1), -+ PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x50, 0x10, 12, 1), -+ PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x50, 0x10, 18, 1), -+ PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x50, 0x10, 17, 1), -+ PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x50, 0x10, 15, 1), -+ PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x50, 0x10, 19, 1), -+ PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x50, 0x10, 23, 1), -+ PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x50, 0x10, 22, 1), -+ PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x50, 0x10, 21, 1), -+ PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x40, 0x10, 4, 1), -+ PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x40, 0x10, 8, 1), -+ PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x40, 0x10, 7, 1), -+ PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x40, 0x10, 5, 1), -+ PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x40, 0x10, 9, 1), -+ PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x70, 0x10, 18, 1), -+ PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x70, 0x10, 12, 1), -+ PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x70, 0x10, 23, 1), -+ PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x70, 0x10, 21, 1), -+ PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x70, 0x10, 27, 1), -+ PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x70, 0x10, 25, 1), -+ PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x50, 0x10, 2, 1), -+ PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x50, 0x10, 1, 1), -+ PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x50, 0x10, 10, 1), -+ PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x70, 0x10, 15, 1), -+ PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x70, 0x10, 14, 1), -+ PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x70, 0x10, 13, 1), -+ PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x70, 0x10, 16, 1), -+ PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x50, 0x10, 2, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7986_pin_r1_range[] = { -+ PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x80, 0x10, 17, 1), -+ PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x50, 0x10, 10, 1), -+ PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x60, 0x10, 0, 1), -+ PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x80, 0x10, 0, 1), -+ PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x80, 0x10, 8, 1), -+ PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x80, 0x10, 2, 1), -+ PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x60, 0x10, 12, 1), -+ PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x60, 0x10, 18, 1), -+ PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x60, 0x10, 17, 1), -+ PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x60, 0x10, 15, 1), -+ PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x60, 0x10, 19, 1), -+ PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x60, 0x10, 23, 1), -+ PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x60, 0x10, 22, 1), -+ PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x60, 0x10, 21, 1), -+ PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x50, 0x10, 4, 1), -+ PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x50, 0x10, 8, 1), -+ PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x50, 0x10, 7, 1), -+ PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x50, 0x10, 5, 1), -+ PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x50, 0x10, 9, 1), -+ PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x80, 0x10, 18, 1), -+ PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x80, 0x10, 12, 1), -+ PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x80, 0x10, 23, 1), -+ PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x80, 0x10, 21, 1), -+ PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x80, 0x10, 27, 1), -+ PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x80, 0x10, 25, 1), -+ PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x60, 0x10, 2, 1), -+ PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x60, 0x10, 1, 1), -+ PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x60, 0x10, 0, 1), -+ PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x60, 0x10, 10, 1), -+ PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x80, 0x10, 15, 1), -+ PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x80, 0x10, 14, 1), -+ PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x80, 0x10, 13, 1), -+ PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x80, 0x10, 16, 1), -+ PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x60, 0x10, 2, 1), -+}; -+ -+static const struct mtk_pin_reg_calc mt7986_reg_cals[] = { -+ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7986_pin_mode_range), -+ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7986_pin_dir_range), -+ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7986_pin_di_range), -+ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7986_pin_do_range), -+ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7986_pin_smt_range), -+ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7986_pin_ies_range), -+ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7986_pin_drv_range), -+ [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7986_pin_pu_range), -+ [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7986_pin_pd_range), -+ [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7986_pin_pupd_range), -+ [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7986_pin_r0_range), -+ [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7986_pin_r1_range), -+}; -+ -+static const struct mtk_pin_desc mt7986_pins[] = { -+ MT7986_TYPE0_PIN(0, "SYS_WATCHDOG"), -+ MT7986_TYPE0_PIN(1, "WF2G_LED"), -+ MT7986_TYPE0_PIN(2, "WF5G_LED"), -+ MT7986_TYPE0_PIN(3, "I2C_SCL"), -+ MT7986_TYPE0_PIN(4, "I2C_SDA"), -+ MT7986_TYPE0_PIN(5, "GPIO_0"), -+ MT7986_TYPE0_PIN(6, "GPIO_1"), -+ MT7986_TYPE0_PIN(7, "GPIO_2"), -+ MT7986_TYPE0_PIN(8, "GPIO_3"), -+ MT7986_TYPE0_PIN(9, "GPIO_4"), -+ MT7986_TYPE0_PIN(10, "GPIO_5"), -+ MT7986_TYPE0_PIN(11, "GPIO_6"), -+ MT7986_TYPE0_PIN(12, "GPIO_7"), -+ MT7986_TYPE0_PIN(13, "GPIO_8"), -+ MT7986_TYPE0_PIN(14, "GPIO_9"), -+ MT7986_TYPE0_PIN(15, "GPIO_10"), -+ MT7986_TYPE0_PIN(16, "GPIO_11"), -+ MT7986_TYPE0_PIN(17, "GPIO_12"), -+ MT7986_TYPE0_PIN(18, "GPIO_13"), -+ MT7986_TYPE0_PIN(19, "GPIO_14"), -+ MT7986_TYPE0_PIN(20, "GPIO_15"), -+ MT7986_TYPE0_PIN(21, "PWM0"), -+ MT7986_TYPE0_PIN(22, "PWM1"), -+ MT7986_TYPE0_PIN(23, "SPI0_CLK"), -+ MT7986_TYPE0_PIN(24, "SPI0_MOSI"), -+ MT7986_TYPE0_PIN(25, "SPI0_MISO"), -+ MT7986_TYPE0_PIN(26, "SPI0_CS"), -+ MT7986_TYPE0_PIN(27, "SPI0_HOLD"), -+ MT7986_TYPE0_PIN(28, "SPI0_WP"), -+ MT7986_TYPE0_PIN(29, "SPI1_CLK"), -+ MT7986_TYPE0_PIN(30, "SPI1_MOSI"), -+ MT7986_TYPE0_PIN(31, "SPI1_MISO"), -+ MT7986_TYPE0_PIN(32, "SPI1_CS"), -+ MT7986_TYPE0_PIN(33, "SPI2_CLK"), -+ MT7986_TYPE0_PIN(34, "SPI2_MOSI"), -+ MT7986_TYPE0_PIN(35, "SPI2_MISO"), -+ MT7986_TYPE0_PIN(36, "SPI2_CS"), -+ MT7986_TYPE0_PIN(37, "SPI2_HOLD"), -+ MT7986_TYPE0_PIN(38, "SPI2_WP"), -+ MT7986_TYPE0_PIN(39, "UART0_RXD"), -+ MT7986_TYPE0_PIN(40, "UART0_TXD"), -+ MT7986_TYPE0_PIN(41, "PCIE_PERESET_N"), -+ MT7986_TYPE0_PIN(42, "UART1_RXD"), -+ MT7986_TYPE0_PIN(43, "UART1_TXD"), -+ MT7986_TYPE0_PIN(44, "UART1_CTS"), -+ MT7986_TYPE0_PIN(45, "UART1_RTS"), -+ MT7986_TYPE0_PIN(46, "UART2_RXD"), -+ MT7986_TYPE0_PIN(47, "UART2_TXD"), -+ MT7986_TYPE0_PIN(48, "UART2_CTS"), -+ MT7986_TYPE0_PIN(49, "UART2_RTS"), -+ MT7986_TYPE0_PIN(50, "EMMC_DATA_0"), -+ MT7986_TYPE0_PIN(51, "EMMC_DATA_1"), -+ MT7986_TYPE0_PIN(52, "EMMC_DATA_2"), -+ MT7986_TYPE0_PIN(53, "EMMC_DATA_3"), -+ MT7986_TYPE0_PIN(54, "EMMC_DATA_4"), -+ MT7986_TYPE0_PIN(55, "EMMC_DATA_5"), -+ MT7986_TYPE0_PIN(56, "EMMC_DATA_6"), -+ MT7986_TYPE0_PIN(57, "EMMC_DATA_7"), -+ MT7986_TYPE0_PIN(58, "EMMC_CMD"), -+ MT7986_TYPE0_PIN(59, "EMMC_CK"), -+ MT7986_TYPE0_PIN(60, "EMMC_DSL"), -+ MT7986_TYPE0_PIN(61, "EMMC_RSTB"), -+ MT7986_TYPE0_PIN(62, "PCM_DTX"), -+ MT7986_TYPE0_PIN(63, "PCM_DRX"), -+ MT7986_TYPE0_PIN(64, "PCM_CLK"), -+ MT7986_TYPE0_PIN(65, "PCM_FS"), -+ MT7986_TYPE0_PIN(66, "MT7531_INT"), -+ MT7986_TYPE0_PIN(67, "SMI_MDC"), -+ MT7986_TYPE0_PIN(68, "SMI_MDIO"), -+ MT7986_TYPE1_PIN(69, "WF0_DIG_RESETB"), -+ MT7986_TYPE1_PIN(70, "WF0_CBA_RESETB"), -+ MT7986_TYPE1_PIN(71, "WF0_XO_REQ"), -+ MT7986_TYPE1_PIN(72, "WF0_TOP_CLK"), -+ MT7986_TYPE1_PIN(73, "WF0_TOP_DATA"), -+ MT7986_TYPE1_PIN(74, "WF0_HB1"), -+ MT7986_TYPE1_PIN(75, "WF0_HB2"), -+ MT7986_TYPE1_PIN(76, "WF0_HB3"), -+ MT7986_TYPE1_PIN(77, "WF0_HB4"), -+ MT7986_TYPE1_PIN(78, "WF0_HB0"), -+ MT7986_TYPE1_PIN(79, "WF0_HB0_B"), -+ MT7986_TYPE1_PIN(80, "WF0_HB5"), -+ MT7986_TYPE1_PIN(81, "WF0_HB6"), -+ MT7986_TYPE1_PIN(82, "WF0_HB7"), -+ MT7986_TYPE1_PIN(83, "WF0_HB8"), -+ MT7986_TYPE1_PIN(84, "WF0_HB9"), -+ MT7986_TYPE1_PIN(85, "WF0_HB10"), -+ MT7986_TYPE1_PIN(86, "WF1_DIG_RESETB"), -+ MT7986_TYPE1_PIN(87, "WF1_CBA_RESETB"), -+ MT7986_TYPE1_PIN(88, "WF1_XO_REQ"), -+ MT7986_TYPE1_PIN(89, "WF1_TOP_CLK"), -+ MT7986_TYPE1_PIN(90, "WF1_TOP_DATA"), -+ MT7986_TYPE1_PIN(91, "WF1_HB1"), -+ MT7986_TYPE1_PIN(92, "WF1_HB2"), -+ MT7986_TYPE1_PIN(93, "WF1_HB3"), -+ MT7986_TYPE1_PIN(94, "WF1_HB4"), -+ MT7986_TYPE1_PIN(95, "WF1_HB0"), -+ MT7986_TYPE1_PIN(96, "WF1_HB0_B"), -+ MT7986_TYPE1_PIN(97, "WF1_HB5"), -+ MT7986_TYPE1_PIN(98, "WF1_HB6"), -+ MT7986_TYPE1_PIN(99, "WF1_HB7"), -+ MT7986_TYPE1_PIN(100, "WF1_HB8"), -+}; -+ -+static const struct mtk_io_type_desc mt7986_io_type_desc[] = { -+ [IO_TYPE_GRP0] = { -+ .name = "18OD33", -+ .bias_set = mtk_pinconf_bias_set_pupd_r1_r0, -+ .drive_set = mtk_pinconf_drive_set_v1, -+ .input_enable = mtk_pinconf_input_enable_v1, -+ }, -+ [IO_TYPE_GRP1] = { -+ .name = "18A01", -+ .bias_set = mtk_pinconf_bias_set_pu_pd, -+ .drive_set = mtk_pinconf_drive_set_v1, -+ .input_enable = mtk_pinconf_input_enable_v1, -+ }, -+}; -+ -+/* List all groups consisting of these pins dedicated to the enablement of -+ * certain hardware block and the corresponding mode for all of the pins. -+ * The hardware probably has multiple combinations of these pinouts. -+ */ -+ -+static int mt7986_watchdog_pins[] = { 0, }; -+static int mt7986_watchdog_funcs[] = { 1, }; -+ -+static int mt7986_wifi_led_pins[] = { 1, 2, }; -+static int mt7986_wifi_led_funcs[] = { 1, 1, }; -+ -+static int mt7986_i2c_pins[] = { 3, 4, }; -+static int mt7986_i2c_funcs[] = { 1, 1, }; -+ -+static int mt7986_uart1_0_pins[] = { 7, 8, 9, 10, }; -+static int mt7986_uart1_0_funcs[] = { 3, 3, 3, 3, }; -+ -+static int mt7986_spi1_0_pins[] = { 11, 12, 13, 14, }; -+static int mt7986_spi1_0_funcs[] = { 3, 3, 3, 3, }; -+ -+static int mt7986_pwm1_1_pins[] = { 20, }; -+static int mt7986_pwm1_1_funcs[] = { 2, }; -+ -+static int mt7986_pwm0_pins[] = { 21, }; -+static int mt7986_pwm0_funcs[] = { 1, }; -+ -+static int mt7986_pwm1_0_pins[] = { 22, }; -+static int mt7986_pwm1_0_funcs[] = { 1, }; -+ -+static int mt7986_emmc_45_pins[] = { -+ 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, }; -+static int mt7986_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; -+ -+static int mt7986_snfi_pins[] = { 23, 24, 25, 26, 27, 28, }; -+static int mt7986_snfi_funcs[] = { 1, 1, 1, 1, 1, 1, }; -+ -+static int mt7986_spi1_1_pins[] = { 23, 24, 25, 26, }; -+static int mt7986_spi1_1_funcs[] = { 3, 3, 3, 3, }; -+ -+static int mt7986_uart1_1_pins[] = { 23, 24, 25, 26, }; -+static int mt7986_uart1_1_funcs[] = { 4, 4, 4, 4, }; -+ -+static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, }; -+static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, }; -+ -+static int mt7986_uart1_2_pins[] = { 29, 30, 31, 32, }; -+static int mt7986_uart1_2_funcs[] = { 3, 3, 3, 3, }; -+ -+static int mt7986_uart2_0_pins[] = { 29, 30, 31, 32, }; -+static int mt7986_uart2_0_funcs[] = { 4, 4, 4, 4, }; -+ -+static int mt7986_spi0_pins[] = { 33, 34, 35, 36, }; -+static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, }; -+ -+static int mt7986_spi0_wp_hold_pins[] = { 37, 38, }; -+static int mt7986_spi0_wp_hold_funcs[] = { 1, 1, }; -+ -+static int mt7986_uart2_1_pins[] = { 33, 34, 35, 36, }; -+static int mt7986_uart2_1_funcs[] = { 3, 3, 3, 3, }; -+ -+static int mt7986_uart1_3_rx_tx_pins[] = { 35, 36, }; -+static int mt7986_uart1_3_rx_tx_funcs[] = { 2, 2, }; -+ -+static int mt7986_uart1_3_cts_rts_pins[] = { 37, 38, }; -+static int mt7986_uart1_3_cts_rts_funcs[] = { 2, 2, }; -+ -+static int mt7986_spi1_3_pins[] = { 33, 34, 35, 36, }; -+static int mt7986_spi1_3_funcs[] = { 4, 4, 4, 4, }; -+ -+static int mt7986_uart0_pins[] = { 39, 40, }; -+static int mt7986_uart0_funcs[] = { 1, 1, }; -+ -+static int mt7986_pcie_reset_pins[] = { 41, }; -+static int mt7986_pcie_reset_funcs[] = { 1, }; -+ -+static int mt7986_uart1_pins[] = { 42, 43, 44, 45, }; -+static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, }; -+ -+static int mt7986_uart2_pins[] = { 46, 47, 48, 49, }; -+static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, }; -+ -+static int mt7986_emmc_51_pins[] = { -+ 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, }; -+static int mt7986_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; -+ -+static int mt7986_pcm_pins[] = { 62, 63, 64, 65, }; -+static int mt7986_pcm_funcs[] = { 1, 1, 1, 1, }; -+ -+static int mt7986_i2s_pins[] = { 62, 63, 64, 65, }; -+static int mt7986_i2s_funcs[] = { 1, 1, 1, 1, }; -+ -+static int mt7986_switch_int_pins[] = { 66, }; -+static int mt7986_switch_int_funcs[] = { 1, }; -+ -+static int mt7986_mdc_mdio_pins[] = { 67, 68, }; -+static int mt7986_mdc_mdio_funcs[] = { 1, 1, }; -+ -+static int mt7986_wf_2g_pins[] = {74, 75, 76, 77, 78, 79, 80, 81, 82, 83, }; -+static int mt7986_wf_2g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; -+ -+static int mt7986_wf_5g_pins[] = {91, 92, 93, 94, 95, 96, 97, 98, 99, 100, }; -+static int mt7986_wf_5g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; -+ -+static int mt7986_wf_dbdc_pins[] = { -+ 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, }; -+static int mt7986_wf_dbdc_funcs[] = { -+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; -+ -+static int mt7986_pcie_clk_pins[] = { 9, }; -+static int mt7986_pcie_clk_funcs[] = { 1, }; -+ -+static int mt7986_pcie_wake_pins[] = { 10, }; -+static int mt7986_pcie_wake_funcs[] = { 1, }; -+ -+static const struct mtk_group_desc mt7986_groups[] = { -+ PINCTRL_PIN_GROUP("watchdog", mt7986_watchdog), -+ PINCTRL_PIN_GROUP("wifi_led", mt7986_wifi_led), -+ PINCTRL_PIN_GROUP("i2c", mt7986_i2c), -+ PINCTRL_PIN_GROUP("uart1_0", mt7986_uart1_0), -+ PINCTRL_PIN_GROUP("pcie_clk", mt7986_pcie_clk), -+ PINCTRL_PIN_GROUP("pcie_wake", mt7986_pcie_wake), -+ PINCTRL_PIN_GROUP("spi1_0", mt7986_spi1_0), -+ PINCTRL_PIN_GROUP("pwm1_1", mt7986_pwm1_1), -+ PINCTRL_PIN_GROUP("pwm0", mt7986_pwm0), -+ PINCTRL_PIN_GROUP("pwm1_0", mt7986_pwm1_0), -+ PINCTRL_PIN_GROUP("emmc_45", mt7986_emmc_45), -+ PINCTRL_PIN_GROUP("snfi", mt7986_snfi), -+ PINCTRL_PIN_GROUP("spi1_1", mt7986_spi1_1), -+ PINCTRL_PIN_GROUP("uart1_1", mt7986_uart1_1), -+ PINCTRL_PIN_GROUP("spi1_2", mt7986_spi1_2), -+ PINCTRL_PIN_GROUP("uart1_2", mt7986_uart1_2), -+ PINCTRL_PIN_GROUP("uart2_0", mt7986_uart2_0), -+ PINCTRL_PIN_GROUP("spi0", mt7986_spi0), -+ PINCTRL_PIN_GROUP("spi0_wp_hold", mt7986_spi0_wp_hold), -+ PINCTRL_PIN_GROUP("uart2_1", mt7986_uart2_1), -+ PINCTRL_PIN_GROUP("uart1_3_rx_tx", mt7986_uart1_3_rx_tx), -+ PINCTRL_PIN_GROUP("uart1_3_cts_rts", mt7986_uart1_3_cts_rts), -+ PINCTRL_PIN_GROUP("spi1_3", mt7986_spi1_3), -+ PINCTRL_PIN_GROUP("uart0", mt7986_uart0), -+ PINCTRL_PIN_GROUP("switch_int", mt7986_switch_int), -+ PINCTRL_PIN_GROUP("mdc_mdio", mt7986_mdc_mdio), -+ PINCTRL_PIN_GROUP("pcie_pereset", mt7986_pcie_reset), -+ PINCTRL_PIN_GROUP("uart1", mt7986_uart1), -+ PINCTRL_PIN_GROUP("uart2", mt7986_uart2), -+ PINCTRL_PIN_GROUP("emmc_51", mt7986_emmc_51), -+ PINCTRL_PIN_GROUP("pcm", mt7986_pcm), -+ PINCTRL_PIN_GROUP("i2s", mt7986_i2s), -+ PINCTRL_PIN_GROUP("wf_2g", mt7986_wf_2g), -+ PINCTRL_PIN_GROUP("wf_5g", mt7986_wf_5g), -+ PINCTRL_PIN_GROUP("wf_dbdc", mt7986_wf_dbdc), -+}; -+ -+/* Joint those groups owning the same capability in user point of view which -+ * allows that people tend to use through the device tree. -+ */ -+ -+static const char *const mt7986_audio_groups[] = { "pcm", "i2s" }; -+static const char *const mt7986_emmc_groups[] = { "emmc_45", "emmc_51", }; -+static const char *const mt7986_ethernet_groups[] = { "switch_int", -+ "mdc_mdio", }; -+static const char *const mt7986_i2c_groups[] = { "i2c", }; -+static const char *const mt7986_led_groups[] = { "wifi_led", }; -+static const char *const mt7986_flash_groups[] = { "snfi", }; -+static const char *const mt7986_pcie_groups[] = { "pcie_clk", "pcie_wake", -+ "pcie_pereset" }; -+static const char *const mt7986_pwm_groups[] = { "pwm0", "pwm1_0", "pwm1_1", }; -+static const char *const mt7986_spi_groups[] = { "spi0", "spi0_wp_hold", -+ "spi1_0", "spi1_1", "spi1_2", "spi1_3", }; -+static const char *const mt7986_uart_groups[] = { "uart1_0", "uart1_1", -+ "uart1_2", "uart1_3_rx_tx", "uart1_3_cts_rts", "uart2_0", "uart2_1", -+ "uart0", "uart1", "uart2", }; -+static const char *const mt7986_wdt_groups[] = { "watchdog", }; -+static const char *const mt7986_wf_groups[] = { "wf_2g", "wf_5g", "wf_dbdc", }; -+ -+static const struct mtk_function_desc mt7986_functions[] = { -+ {"audio", mt7986_audio_groups, ARRAY_SIZE(mt7986_audio_groups)}, -+ {"emmc", mt7986_emmc_groups, ARRAY_SIZE(mt7986_emmc_groups)}, -+ {"eth", mt7986_ethernet_groups, ARRAY_SIZE(mt7986_ethernet_groups)}, -+ {"i2c", mt7986_i2c_groups, ARRAY_SIZE(mt7986_i2c_groups)}, -+ {"led", mt7986_led_groups, ARRAY_SIZE(mt7986_led_groups)}, -+ {"flash", mt7986_flash_groups, ARRAY_SIZE(mt7986_flash_groups)}, -+ {"pcie", mt7986_pcie_groups, ARRAY_SIZE(mt7986_pcie_groups)}, -+ {"pwm", mt7986_pwm_groups, ARRAY_SIZE(mt7986_pwm_groups)}, -+ {"spi", mt7986_spi_groups, ARRAY_SIZE(mt7986_spi_groups)}, -+ {"uart", mt7986_uart_groups, ARRAY_SIZE(mt7986_uart_groups)}, -+ {"watchdog", mt7986_wdt_groups, ARRAY_SIZE(mt7986_wdt_groups)}, -+ {"wifi", mt7986_wf_groups, ARRAY_SIZE(mt7986_wf_groups)}, -+}; -+ -+static struct mtk_pinctrl_soc mt7986_data = { -+ .name = "mt7986_pinctrl", -+ .reg_cal = mt7986_reg_cals, -+ .pins = mt7986_pins, -+ .npins = ARRAY_SIZE(mt7986_pins), -+ .grps = mt7986_groups, -+ .ngrps = ARRAY_SIZE(mt7986_groups), -+ .funcs = mt7986_functions, -+ .nfuncs = ARRAY_SIZE(mt7986_functions), -+ .io_type = mt7986_io_type_desc, -+ .ntype = ARRAY_SIZE(mt7986_io_type_desc), -+ .gpio_mode = 0, -+ .base_names = mt7986_pinctrl_register_base_names, -+ .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), -+ .base_calc = 1, -+}; -+ -+static int mtk_pinctrl_mt7986_probe(struct udevice *dev) -+{ -+ return mtk_pinctrl_common_probe(dev, &mt7986_data); -+} -+ -+static const struct udevice_id mt7986_pctrl_match[] = { -+ {.compatible = "mediatek,mt7986-pinctrl"}, -+ { /* sentinel */ } -+}; -+ -+U_BOOT_DRIVER(mt7986_pinctrl) = { -+ .name = "mt7986_pinctrl", -+ .id = UCLASS_PINCTRL, -+ .of_match = mt7986_pctrl_match, -+ .ops = &mtk_pinctrl_ops, -+ .probe = mtk_pinctrl_mt7986_probe, -+ .priv_auto = sizeof(struct mtk_pinctrl_priv), -+}; diff --git a/package/boot/uboot-mediatek/patches/002-0022-clk-mediatek-add-CLK_BYPASS_XTAL-flag-to-allow-bypas.patch b/package/boot/uboot-mediatek/patches/002-0022-clk-mediatek-add-CLK_BYPASS_XTAL-flag-to-allow-bypas.patch deleted file mode 100644 index b9f0954401e..00000000000 --- a/package/boot/uboot-mediatek/patches/002-0022-clk-mediatek-add-CLK_BYPASS_XTAL-flag-to-allow-bypas.patch +++ /dev/null @@ -1,63 +0,0 @@ -From 907d65c5020fefc9944ec57a9e0bd66dc648823e Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 31 Aug 2022 19:04:59 +0800 -Subject: [PATCH 22/32] clk: mediatek: add CLK_BYPASS_XTAL flag to allow - bypassing searching clock parent of xtal clock - -The mtk clock framework in u-boot uses array index for searching clock -parent (kernel uses strings for search), so we need to specify a special -clock with ID=0 for CLK_XTAL in u-boot. - -In the mt7622/mt7629 clock tree, the clocks with ID=0 never call -mtk_topckgen_get_mux_rate, adn return xtal clock directly. This what we -expected. - -However for newer chips, they may have some clocks with ID=0 not -representing the xtal clock and still needs mtk_topckgen_get_mux_rate be -called. Current logic will make entire clock driver not working. - -This patch adds a flag to indicate that whether a clock driver needs clocks -with ID=0 to call mtk_topckgen_get_mux_rate. - -Reviewed-by: Simon Glass -Signed-off-by: Weijie Gao ---- - drivers/clk/mediatek/clk-mtk.c | 4 +++- - drivers/clk/mediatek/clk-mtk.h | 6 ++++++ - 2 files changed, 9 insertions(+), 1 deletion(-) - ---- a/drivers/clk/mediatek/clk-mtk.c -+++ b/drivers/clk/mediatek/clk-mtk.c -@@ -319,7 +319,9 @@ static ulong mtk_topckgen_get_mux_rate(s - index &= mux->mux_mask << mux->mux_shift; - index = index >> mux->mux_shift; - -- if (mux->parent[index]) -+ if (mux->parent[index] > 0 || -+ (mux->parent[index] == CLK_XTAL && -+ priv->tree->flags & CLK_BYPASS_XTAL)) - return mtk_clk_find_parent_rate(clk, mux->parent[index], - NULL); - ---- a/drivers/clk/mediatek/clk-mtk.h -+++ b/drivers/clk/mediatek/clk-mtk.h -@@ -11,6 +11,11 @@ - #define CLK_XTAL 0 - #define MHZ (1000 * 1000) - -+/* flags in struct mtk_clk_tree */ -+ -+/* clk id == 0 doesn't mean it's xtal clk */ -+#define CLK_BYPASS_XTAL BIT(0) -+ - #define HAVE_RST_BAR BIT(0) - #define CLK_DOMAIN_SCPSYS BIT(0) - #define CLK_MUX_SETCLR_UPD BIT(1) -@@ -197,6 +202,7 @@ struct mtk_clk_tree { - const struct mtk_fixed_clk *fclks; - const struct mtk_fixed_factor *fdivs; - const struct mtk_composite *muxes; -+ u32 flags; - }; - - struct mtk_clk_priv { diff --git a/package/boot/uboot-mediatek/patches/002-0023-clk-mediatek-add-support-to-configure-clock-driver-p.patch b/package/boot/uboot-mediatek/patches/002-0023-clk-mediatek-add-support-to-configure-clock-driver-p.patch deleted file mode 100644 index c8af7e31918..00000000000 --- a/package/boot/uboot-mediatek/patches/002-0023-clk-mediatek-add-support-to-configure-clock-driver-p.patch +++ /dev/null @@ -1,198 +0,0 @@ -From 50859bea6a3334834b8250e7e5406507f0d0918a Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 31 Aug 2022 19:05:06 +0800 -Subject: [PATCH 23/32] clk: mediatek: add support to configure clock driver - parent - -This patch adds support for a clock node to configure its parent clock -where possible. - -Reviewed-by: Simon Glass -Signed-off-by: Weijie Gao ---- - drivers/clk/mediatek/clk-mtk.c | 79 ++++++++++++++++++++-------------- - drivers/clk/mediatek/clk-mtk.h | 2 + - 2 files changed, 48 insertions(+), 33 deletions(-) - ---- a/drivers/clk/mediatek/clk-mtk.c -+++ b/drivers/clk/mediatek/clk-mtk.c -@@ -42,20 +42,14 @@ - * the accurate frequency. - */ - static ulong mtk_clk_find_parent_rate(struct clk *clk, int id, -- const struct driver *drv) -+ struct udevice *pdev) - { - struct clk parent = { .id = id, }; - -- if (drv) { -- struct udevice *dev; -- -- if (uclass_get_device_by_driver(UCLASS_CLK, drv, &dev)) -- return -ENODEV; -- -- parent.dev = dev; -- } else { -+ if (pdev) -+ parent.dev = pdev; -+ else - parent.dev = clk->dev; -- } - - return clk_get_rate(&parent); - } -@@ -296,7 +290,7 @@ static ulong mtk_topckgen_get_factor_rat - switch (fdiv->flags & CLK_PARENT_MASK) { - case CLK_PARENT_APMIXED: - rate = mtk_clk_find_parent_rate(clk, fdiv->parent, -- DM_DRIVER_GET(mtk_clk_apmixedsys)); -+ priv->parent); - break; - case CLK_PARENT_TOPCKGEN: - rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL); -@@ -321,9 +315,18 @@ static ulong mtk_topckgen_get_mux_rate(s - - if (mux->parent[index] > 0 || - (mux->parent[index] == CLK_XTAL && -- priv->tree->flags & CLK_BYPASS_XTAL)) -- return mtk_clk_find_parent_rate(clk, mux->parent[index], -- NULL); -+ priv->tree->flags & CLK_BYPASS_XTAL)) { -+ switch (mux->flags & CLK_PARENT_MASK) { -+ case CLK_PARENT_APMIXED: -+ return mtk_clk_find_parent_rate(clk, mux->parent[index], -+ priv->parent); -+ break; -+ default: -+ return mtk_clk_find_parent_rate(clk, mux->parent[index], -+ NULL); -+ break; -+ } -+ } - - return priv->tree->xtal_rate; - } -@@ -342,7 +345,7 @@ static ulong mtk_topckgen_get_rate(struc - priv->tree->muxes_offs); - } - --static int mtk_topckgen_enable(struct clk *clk) -+static int mtk_clk_mux_enable(struct clk *clk) - { - struct mtk_clk_priv *priv = dev_get_priv(clk->dev); - const struct mtk_composite *mux; -@@ -375,7 +378,7 @@ static int mtk_topckgen_enable(struct cl - return 0; - } - --static int mtk_topckgen_disable(struct clk *clk) -+static int mtk_clk_mux_disable(struct clk *clk) - { - struct mtk_clk_priv *priv = dev_get_priv(clk->dev); - const struct mtk_composite *mux; -@@ -401,7 +404,7 @@ static int mtk_topckgen_disable(struct c - return 0; - } - --static int mtk_topckgen_set_parent(struct clk *clk, struct clk *parent) -+static int mtk_common_clk_set_parent(struct clk *clk, struct clk *parent) - { - struct mtk_clk_priv *priv = dev_get_priv(clk->dev); - -@@ -473,19 +476,7 @@ static ulong mtk_clk_gate_get_rate(struc - struct mtk_cg_priv *priv = dev_get_priv(clk->dev); - const struct mtk_gate *gate = &priv->gates[clk->id]; - -- switch (gate->flags & CLK_PARENT_MASK) { -- case CLK_PARENT_APMIXED: -- return mtk_clk_find_parent_rate(clk, gate->parent, -- DM_DRIVER_GET(mtk_clk_apmixedsys)); -- break; -- case CLK_PARENT_TOPCKGEN: -- return mtk_clk_find_parent_rate(clk, gate->parent, -- DM_DRIVER_GET(mtk_clk_topckgen)); -- break; -- -- default: -- return priv->tree->xtal_rate; -- } -+ return mtk_clk_find_parent_rate(clk, gate->parent, priv->parent); - } - - const struct clk_ops mtk_clk_apmixedsys_ops = { -@@ -496,10 +487,10 @@ const struct clk_ops mtk_clk_apmixedsys_ - }; - - const struct clk_ops mtk_clk_topckgen_ops = { -- .enable = mtk_topckgen_enable, -- .disable = mtk_topckgen_disable, -+ .enable = mtk_clk_mux_enable, -+ .disable = mtk_clk_mux_disable, - .get_rate = mtk_topckgen_get_rate, -- .set_parent = mtk_topckgen_set_parent, -+ .set_parent = mtk_common_clk_set_parent, - }; - - const struct clk_ops mtk_clk_gate_ops = { -@@ -512,11 +503,22 @@ int mtk_common_clk_init(struct udevice * - const struct mtk_clk_tree *tree) - { - struct mtk_clk_priv *priv = dev_get_priv(dev); -+ struct udevice *parent; -+ int ret; - - priv->base = dev_read_addr_ptr(dev); - if (!priv->base) - return -ENOENT; - -+ ret = uclass_get_device_by_phandle(UCLASS_CLK, dev, "clock-parent", &parent); -+ if (ret || !parent) { -+ ret = uclass_get_device_by_driver(UCLASS_CLK, -+ DM_DRIVER_GET(mtk_clk_apmixedsys), &parent); -+ if (ret || !parent) -+ return -ENOENT; -+ } -+ -+ priv->parent = parent; - priv->tree = tree; - - return 0; -@@ -527,11 +529,22 @@ int mtk_common_clk_gate_init(struct udev - const struct mtk_gate *gates) - { - struct mtk_cg_priv *priv = dev_get_priv(dev); -+ struct udevice *parent; -+ int ret; - - priv->base = dev_read_addr_ptr(dev); - if (!priv->base) - return -ENOENT; - -+ ret = uclass_get_device_by_phandle(UCLASS_CLK, dev, "clock-parent", &parent); -+ if (ret || !parent) { -+ ret = uclass_get_device_by_driver(UCLASS_CLK, -+ DM_DRIVER_GET(mtk_clk_topckgen), &parent); -+ if (ret || !parent) -+ return -ENOENT; -+ } -+ -+ priv->parent = parent; - priv->tree = tree; - priv->gates = gates; - ---- a/drivers/clk/mediatek/clk-mtk.h -+++ b/drivers/clk/mediatek/clk-mtk.h -@@ -206,11 +206,13 @@ struct mtk_clk_tree { - }; - - struct mtk_clk_priv { -+ struct udevice *parent; - void __iomem *base; - const struct mtk_clk_tree *tree; - }; - - struct mtk_cg_priv { -+ struct udevice *parent; - void __iomem *base; - const struct mtk_clk_tree *tree; - const struct mtk_gate *gates; diff --git a/package/boot/uboot-mediatek/patches/002-0024-clk-mediatek-add-infrasys-clock-mux-support.patch b/package/boot/uboot-mediatek/patches/002-0024-clk-mediatek-add-infrasys-clock-mux-support.patch deleted file mode 100644 index 6475dde3886..00000000000 --- a/package/boot/uboot-mediatek/patches/002-0024-clk-mediatek-add-infrasys-clock-mux-support.patch +++ /dev/null @@ -1,135 +0,0 @@ -From c53d249df9a75f77f5d0abb986a8913bc13070d0 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 31 Aug 2022 19:05:09 +0800 -Subject: [PATCH 24/32] clk: mediatek: add infrasys clock mux support - -This patch adds infrasys clock mux support for mediatek clock drivers. - -Reviewed-by: Simon Glass -Signed-off-by: Weijie Gao ---- - drivers/clk/mediatek/clk-mtk.c | 71 ++++++++++++++++++++++++++++++++++ - drivers/clk/mediatek/clk-mtk.h | 4 +- - 2 files changed, 74 insertions(+), 1 deletion(-) - ---- a/drivers/clk/mediatek/clk-mtk.c -+++ b/drivers/clk/mediatek/clk-mtk.c -@@ -303,6 +303,24 @@ static ulong mtk_topckgen_get_factor_rat - return mtk_factor_recalc_rate(fdiv, rate); - } - -+static ulong mtk_infrasys_get_factor_rate(struct clk *clk, u32 off) -+{ -+ struct mtk_clk_priv *priv = dev_get_priv(clk->dev); -+ const struct mtk_fixed_factor *fdiv = &priv->tree->fdivs[off]; -+ ulong rate; -+ -+ switch (fdiv->flags & CLK_PARENT_MASK) { -+ case CLK_PARENT_TOPCKGEN: -+ rate = mtk_clk_find_parent_rate(clk, fdiv->parent, -+ priv->parent); -+ break; -+ default: -+ rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL); -+ } -+ -+ return mtk_factor_recalc_rate(fdiv, rate); -+} -+ - static ulong mtk_topckgen_get_mux_rate(struct clk *clk, u32 off) - { - struct mtk_clk_priv *priv = dev_get_priv(clk->dev); -@@ -331,6 +349,33 @@ static ulong mtk_topckgen_get_mux_rate(s - return priv->tree->xtal_rate; - } - -+static ulong mtk_infrasys_get_mux_rate(struct clk *clk, u32 off) -+{ -+ struct mtk_clk_priv *priv = dev_get_priv(clk->dev); -+ const struct mtk_composite *mux = &priv->tree->muxes[off]; -+ u32 index; -+ -+ index = readl(priv->base + mux->mux_reg); -+ index &= mux->mux_mask << mux->mux_shift; -+ index = index >> mux->mux_shift; -+ -+ if (mux->parent[index] > 0 || -+ (mux->parent[index] == CLK_XTAL && -+ priv->tree->flags & CLK_BYPASS_XTAL)) { -+ switch (mux->flags & CLK_PARENT_MASK) { -+ case CLK_PARENT_TOPCKGEN: -+ return mtk_clk_find_parent_rate(clk, mux->parent[index], -+ priv->parent); -+ break; -+ default: -+ return mtk_clk_find_parent_rate(clk, mux->parent[index], -+ NULL); -+ break; -+ } -+ } -+ return 0; -+} -+ - static ulong mtk_topckgen_get_rate(struct clk *clk) - { - struct mtk_clk_priv *priv = dev_get_priv(clk->dev); -@@ -345,6 +390,25 @@ static ulong mtk_topckgen_get_rate(struc - priv->tree->muxes_offs); - } - -+static ulong mtk_infrasys_get_rate(struct clk *clk) -+{ -+ struct mtk_clk_priv *priv = dev_get_priv(clk->dev); -+ -+ ulong rate; -+ -+ if (clk->id < priv->tree->fdivs_offs) { -+ rate = priv->tree->fclks[clk->id].rate; -+ } else if (clk->id < priv->tree->muxes_offs) { -+ rate = mtk_infrasys_get_factor_rate(clk, clk->id - -+ priv->tree->fdivs_offs); -+ } else { -+ rate = mtk_infrasys_get_mux_rate(clk, clk->id - -+ priv->tree->muxes_offs); -+ } -+ -+ return rate; -+} -+ - static int mtk_clk_mux_enable(struct clk *clk) - { - struct mtk_clk_priv *priv = dev_get_priv(clk->dev); -@@ -493,6 +557,13 @@ const struct clk_ops mtk_clk_topckgen_op - .set_parent = mtk_common_clk_set_parent, - }; - -+const struct clk_ops mtk_clk_infrasys_ops = { -+ .enable = mtk_clk_mux_enable, -+ .disable = mtk_clk_mux_disable, -+ .get_rate = mtk_infrasys_get_rate, -+ .set_parent = mtk_common_clk_set_parent, -+}; -+ - const struct clk_ops mtk_clk_gate_ops = { - .enable = mtk_clk_gate_enable, - .disable = mtk_clk_gate_disable, ---- a/drivers/clk/mediatek/clk-mtk.h -+++ b/drivers/clk/mediatek/clk-mtk.h -@@ -28,7 +28,8 @@ - - #define CLK_PARENT_APMIXED BIT(4) - #define CLK_PARENT_TOPCKGEN BIT(5) --#define CLK_PARENT_MASK GENMASK(5, 4) -+#define CLK_PARENT_INFRASYS BIT(6) -+#define CLK_PARENT_MASK GENMASK(6, 4) - - #define ETHSYS_HIFSYS_RST_CTRL_OFS 0x34 - -@@ -220,6 +221,7 @@ struct mtk_cg_priv { - - extern const struct clk_ops mtk_clk_apmixedsys_ops; - extern const struct clk_ops mtk_clk_topckgen_ops; -+extern const struct clk_ops mtk_clk_infrasys_ops; - extern const struct clk_ops mtk_clk_gate_ops; - - int mtk_common_clk_init(struct udevice *dev, diff --git a/package/boot/uboot-mediatek/patches/002-0025-clk-mediatek-add-CLK_XTAL-support-for-clock-driver.patch b/package/boot/uboot-mediatek/patches/002-0025-clk-mediatek-add-CLK_XTAL-support-for-clock-driver.patch deleted file mode 100644 index b03ca7384fa..00000000000 --- a/package/boot/uboot-mediatek/patches/002-0025-clk-mediatek-add-CLK_XTAL-support-for-clock-driver.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 0a2cd71e3b16eaa8797b5eec78356970186e552e Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 31 Aug 2022 19:05:11 +0800 -Subject: [PATCH 25/32] clk: mediatek: add CLK_XTAL support for clock driver - -This adds the CLK_XTAL macro/flag to allow modeling clocks which are -directly connected to the xtal clock. - -Signed-off-by: Weijie Gao ---- - drivers/clk/mediatek/clk-mtk.c | 4 ++++ - drivers/clk/mediatek/clk-mtk.h | 3 ++- - 2 files changed, 6 insertions(+), 1 deletion(-) - ---- a/drivers/clk/mediatek/clk-mtk.c -+++ b/drivers/clk/mediatek/clk-mtk.c -@@ -296,6 +296,7 @@ static ulong mtk_topckgen_get_factor_rat - rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL); - break; - -+ case CLK_PARENT_XTAL: - default: - rate = priv->tree->xtal_rate; - } -@@ -314,6 +315,9 @@ static ulong mtk_infrasys_get_factor_rat - rate = mtk_clk_find_parent_rate(clk, fdiv->parent, - priv->parent); - break; -+ case CLK_PARENT_XTAL: -+ rate = priv->tree->xtal_rate; -+ break; - default: - rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL); - } ---- a/drivers/clk/mediatek/clk-mtk.h -+++ b/drivers/clk/mediatek/clk-mtk.h -@@ -29,7 +29,8 @@ - #define CLK_PARENT_APMIXED BIT(4) - #define CLK_PARENT_TOPCKGEN BIT(5) - #define CLK_PARENT_INFRASYS BIT(6) --#define CLK_PARENT_MASK GENMASK(6, 4) -+#define CLK_PARENT_XTAL BIT(7) -+#define CLK_PARENT_MASK GENMASK(7, 4) - - #define ETHSYS_HIFSYS_RST_CTRL_OFS 0x34 - diff --git a/package/boot/uboot-mediatek/patches/002-0026-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch b/package/boot/uboot-mediatek/patches/002-0026-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch deleted file mode 100644 index da2506d93e6..00000000000 --- a/package/boot/uboot-mediatek/patches/002-0026-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch +++ /dev/null @@ -1,956 +0,0 @@ -From 54b66dd24310dba4798caa6e4c02b8571f522602 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 31 Aug 2022 19:05:13 +0800 -Subject: [PATCH 26/32] clk: mediatek: add clock driver support for MediaTek - MT7986 SoC - -This patch adds clock driver support for MediaTek MT7986 SoC - -Reviewed-by: Sean Anderson -Reviewed-by: Simon Glass -Signed-off-by: Weijie Gao ---- - drivers/clk/mediatek/Makefile | 1 + - drivers/clk/mediatek/clk-mt7986.c | 672 +++++++++++++++++++++++++ - include/dt-bindings/clock/mt7986-clk.h | 249 +++++++++ - 3 files changed, 922 insertions(+) - create mode 100644 drivers/clk/mediatek/clk-mt7986.c - create mode 100644 include/dt-bindings/clock/mt7986-clk.h - ---- a/drivers/clk/mediatek/Makefile -+++ b/drivers/clk/mediatek/Makefile -@@ -7,6 +7,7 @@ obj-$(CONFIG_MT8512) += clk-mt8512.o - obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o - obj-$(CONFIG_TARGET_MT7622) += clk-mt7622.o - obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o -+obj-$(CONFIG_TARGET_MT7986) += clk-mt7986.o - obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o - obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o - obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o ---- /dev/null -+++ b/drivers/clk/mediatek/clk-mt7986.c -@@ -0,0 +1,672 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * MediaTek clock driver for MT7986 SoC -+ * -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Sam Shih -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "clk-mtk.h" -+ -+#define MT7986_CLK_PDN 0x250 -+#define MT7986_CLK_PDN_EN_WRITE BIT(31) -+ -+#define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ -+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) -+ -+#define TOP_FACTOR(_id, _name, _parent, _mult, _div) \ -+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) -+ -+#define INFRA_FACTOR(_id, _name, _parent, _mult, _div) \ -+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_INFRASYS) -+ -+/* FIXED PLLS */ -+static const struct mtk_fixed_clk fixed_pll_clks[] = { -+ FIXED_CLK(CK_APMIXED_ARMPLL, CLK_XTAL, 2000000000), -+ FIXED_CLK(CK_APMIXED_NET2PLL, CLK_XTAL, 800000000), -+ FIXED_CLK(CK_APMIXED_MMPLL, CLK_XTAL, 1440000000), -+ FIXED_CLK(CK_APMIXED_SGMPLL, CLK_XTAL, 325000000), -+ FIXED_CLK(CK_APMIXED_WEDMCUPLL, CLK_XTAL, 760000000), -+ FIXED_CLK(CK_APMIXED_NET1PLL, CLK_XTAL, 2500000000), -+ FIXED_CLK(CK_APMIXED_MPLL, CLK_XTAL, 416000000), -+ FIXED_CLK(CK_APMIXED_APLL2, CLK_XTAL, 196608000), -+}; -+ -+/* TOPCKGEN FIXED CLK */ -+static const struct mtk_fixed_clk top_fixed_clks[] = { -+ FIXED_CLK(CK_TOP_CB_CKSQ_40M, CLK_XTAL, 40000000), -+}; -+ -+/* TOPCKGEN FIXED DIV */ -+static const struct mtk_fixed_factor top_fixed_divs[] = { -+ PLL_FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", CK_APMIXED_MPLL, 1, 1), -+ PLL_FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", CK_APMIXED_MPLL, 1, 2), -+ PLL_FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", CK_APMIXED_MPLL, 1, 4), -+ PLL_FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", CK_APMIXED_MPLL, 1, 8), -+ PLL_FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", CK_APMIXED_MPLL, 1, 16), -+ PLL_FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", CK_APMIXED_MPLL, 1, 2), -+ PLL_FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", CK_APMIXED_MMPLL, 1, 2), -+ PLL_FACTOR(CK_TOP_CB_MM_D4, "cb_mm_d4", CK_APMIXED_MMPLL, 1, 4), -+ PLL_FACTOR(CK_TOP_CB_MM_D8, "cb_mm_d8", CK_APMIXED_MMPLL, 1, 8), -+ PLL_FACTOR(CK_TOP_MM_D8_D2, "mm_d8_d2", CK_APMIXED_MMPLL, 1, 16), -+ PLL_FACTOR(CK_TOP_MM_D3_D8, "mm_d3_d8", CK_APMIXED_MMPLL, 1, 8), -+ PLL_FACTOR(CK_TOP_CB_U2_PHYD_CK, "cb_u2_phyd", CK_APMIXED_MMPLL, 1, 30), -+ PLL_FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", CK_APMIXED_APLL2, 1, -+ 1), -+ PLL_FACTOR(CK_TOP_APLL2_D4, "apll2_d4", CK_APMIXED_APLL2, 1, 4), -+ PLL_FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", CK_APMIXED_NET1PLL, 1, 4), -+ PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5), -+ PLL_FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", CK_APMIXED_NET1PLL, 1, 10), -+ PLL_FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", CK_APMIXED_NET1PLL, 1, 20), -+ PLL_FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", CK_APMIXED_NET1PLL, 1, 16), -+ PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32), -+ PLL_FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", CK_APMIXED_NET2PLL, 1, -+ 1), -+ PLL_FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", CK_APMIXED_NET2PLL, 1, 4), -+ PLL_FACTOR(CK_TOP_NET2_D4_D2, "net2_d4_d2", CK_APMIXED_NET2PLL, 1, 8), -+ PLL_FACTOR(CK_TOP_NET2_D3_D2, "net2_d3_d2", CK_APMIXED_NET2PLL, 1, 2), -+ PLL_FACTOR(CK_TOP_CB_WEDMCU_760M, "cb_wedmcu_760m", -+ CK_APMIXED_WEDMCUPLL, 1, 1), -+ PLL_FACTOR(CK_TOP_WEDMCU_D5_D2, "wedmcu_d5_d2", CK_APMIXED_WEDMCUPLL, 1, -+ 10), -+ PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1), -+ TOP_FACTOR(CK_TOP_CB_CKSQ_40M_D2, "cb_cksq_40m_d2", CK_TOP_CB_CKSQ_40M, -+ 1, 2), -+ TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_CB_CKSQ_40M, 1, -+ 1250), -+ TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_CB_CKSQ_40M, 1, -+ 1220), -+ TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", CK_TOP_CB_CKSQ_40M, 1, -+ 1), -+ TOP_FACTOR(CK_TOP_USB_TX250M, "usb_tx250m", CK_TOP_CB_CKSQ_40M, 1, 1), -+ TOP_FACTOR(CK_TOP_USB_LN0_CK, "usb_ln0", CK_TOP_CB_CKSQ_40M, 1, 1), -+ TOP_FACTOR(CK_TOP_USB_CDR_CK, "usb_cdr", CK_TOP_CB_CKSQ_40M, 1, 1), -+ TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_PEXTP_TL, "pextp_tl", CK_TOP_PEXTP_TL_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_EMMC_250M, "emmc_250m", CK_TOP_EMMC_250M_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_EMMC_416M, "emmc_416m", CK_TOP_EMMC_416M_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_F_26M_ADC_CK, "f_26m_adc", CK_TOP_F_26M_ADC_SEL, 1, -+ 1), -+ TOP_FACTOR(CK_TOP_SYSAXI, "sysaxi", CK_TOP_SYSAXI_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", -+ CK_TOP_NETSYS_MCU_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_SGM_325M, "sgm_325m", CK_TOP_SGM_325M_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_A1SYS, "a1sys", CK_TOP_A1SYS_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_EIP_B, "eip_b", CK_TOP_EIP_B_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_F26M, "csw_f26m", CK_TOP_F26M_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_AUD_L, "aud_l", CK_TOP_AUD_L_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 2, 1), -+ TOP_FACTOR(CK_TOP_U2U3_REF, "u2u3_ref", CK_TOP_U2U3_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_U2U3_SYS, "u2u3_sys", CK_TOP_U2U3_SYS_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_U2U3_XHCI, "u2u3_xhci", CK_TOP_U2U3_XHCI_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_AP2CNN_HOST, "ap2cnn_host", CK_TOP_AP2CNN_HOST_SEL, 1, -+ 1), -+}; -+ -+/* TOPCKGEN MUX PARENTS */ -+static const int nfi1x_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D8, -+ CK_TOP_NET1_D8_D2, CK_TOP_NET2_D3_D2, -+ CK_TOP_CB_M_D4, CK_TOP_MM_D8_D2, -+ CK_TOP_WEDMCU_D5_D2, CK_TOP_CB_M_D8 }; -+ -+static const int spinfi_parents[] = { -+ CK_TOP_CB_CKSQ_40M_D2, CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4, -+ CK_TOP_CB_M_D4, CK_TOP_MM_D8_D2, CK_TOP_WEDMCU_D5_D2, -+ CK_TOP_MM_D3_D8, CK_TOP_CB_M_D8 -+}; -+ -+static const int spi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2, -+ CK_TOP_CB_MM_D8, CK_TOP_NET1_D8_D2, -+ CK_TOP_NET2_D3_D2, CK_TOP_NET1_D5_D4, -+ CK_TOP_CB_M_D4, CK_TOP_WEDMCU_D5_D2 }; -+ -+static const int uart_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D8, -+ CK_TOP_M_D8_D2 }; -+ -+static const int pwm_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2, -+ CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4 }; -+ -+static const int i2c_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4, -+ CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 }; -+ -+static const int pextp_tl_ck_parents[] = { CK_TOP_CB_CKSQ_40M, -+ CK_TOP_NET1_D5_D4, CK_TOP_NET2_D4_D2, -+ CK_TOP_CB_RTC_32K }; -+ -+static const int emmc_250m_parents[] = { CK_TOP_CB_CKSQ_40M, -+ CK_TOP_NET1_D5_D2 }; -+ -+static const int emmc_416m_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_416M }; -+ -+static const int f_26m_adc_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D8_D2 }; -+ -+static const int dramc_md32_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2 }; -+ -+static const int sysaxi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2, -+ CK_TOP_CB_NET2_D4 }; -+ -+static const int sysapb_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D3_D2, -+ CK_TOP_NET2_D4_D2 }; -+ -+static const int arm_db_main_parents[] = { CK_TOP_CB_CKSQ_40M, -+ CK_TOP_NET2_D3_D2 }; -+ -+static const int arm_db_jtsel_parents[] = { -1, CK_TOP_CB_CKSQ_40M }; -+ -+static const int netsys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D4 }; -+ -+static const int netsys_500m_parents[] = { CK_TOP_CB_CKSQ_40M, -+ CK_TOP_CB_NET1_D5 }; -+ -+static const int netsys_mcu_parents[] = { CK_TOP_CB_CKSQ_40M, -+ CK_TOP_CB_WEDMCU_760M, -+ CK_TOP_CB_MM_D2, CK_TOP_CB_NET1_D4, -+ CK_TOP_CB_NET1_D5 }; -+ -+static const int netsys_2x_parents[] = { CK_TOP_CB_CKSQ_40M, -+ CK_TOP_CB_NET2_800M, -+ CK_TOP_CB_WEDMCU_760M, -+ CK_TOP_CB_MM_D2 }; -+ -+static const int sgm_325m_parents[] = { CK_TOP_CB_CKSQ_40M, -+ CK_TOP_CB_SGM_325M }; -+ -+static const int sgm_reg_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D4 }; -+ -+static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4 }; -+ -+static const int conn_mcusys_parents[] = { CK_TOP_CB_CKSQ_40M, -+ CK_TOP_CB_MM_D2 }; -+ -+static const int eip_b_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_800M }; -+ -+static const int aud_l_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M, -+ CK_TOP_M_D8_D2 }; -+ -+static const int a_tuner_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4, -+ CK_TOP_M_D8_D2 }; -+ -+static const int u2u3_sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4 }; -+ -+static const int da_u2_refsel_parents[] = { CK_TOP_CB_CKSQ_40M, -+ CK_TOP_CB_U2_PHYD_CK }; -+ -+#define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ -+ _shift, _width, _gate, _upd_ofs, _upd) \ -+ { \ -+ .id = _id, .mux_reg = _mux_ofs, .mux_set_reg = _mux_set_ofs, \ -+ .mux_clr_reg = _mux_clr_ofs, .upd_reg = _upd_ofs, \ -+ .upd_shift = _upd, .mux_shift = _shift, \ -+ .mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs, \ -+ .gate_shift = _gate, .parent = _parents, \ -+ .num_parents = ARRAY_SIZE(_parents), \ -+ .flags = CLK_MUX_SETCLR_UPD, \ -+ } -+ -+/* TOPCKGEN MUX_GATE */ -+static const struct mtk_composite top_muxes[] = { -+ /* CLK_CFG_0 */ -+ TOP_MUX(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x000, 0x004, -+ 0x008, 0, 3, 7, 0x1C0, 0), -+ TOP_MUX(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x000, 0x004, -+ 0x008, 8, 3, 15, 0x1C0, 1), -+ TOP_MUX(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000, 0x004, 0x008, 16, -+ 3, 23, 0x1C0, 2), -+ TOP_MUX(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x000, 0x004, -+ 0x008, 24, 3, 31, 0x1C0, 3), -+ /* CLK_CFG_1 */ -+ TOP_MUX(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010, 0x014, 0x018, -+ 0, 2, 7, 0x1C0, 4), -+ TOP_MUX(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010, 0x014, 0x018, 8, -+ 2, 15, 0x1C0, 5), -+ TOP_MUX(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010, 0x014, 0x018, 16, -+ 2, 23, 0x1C0, 6), -+ TOP_MUX(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents, -+ 0x010, 0x014, 0x018, 24, 2, 31, 0x1C0, 7), -+ /* CLK_CFG_2 */ -+ TOP_MUX(CK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x020, -+ 0x024, 0x028, 0, 1, 7, 0x1C0, 8), -+ TOP_MUX(CK_TOP_EMMC_416M_SEL, "emmc_416m_sel", emmc_416m_parents, 0x020, -+ 0x024, 0x028, 8, 1, 15, 0x1C0, 9), -+ TOP_MUX(CK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel", f_26m_adc_parents, 0x020, -+ 0x024, 0x028, 16, 1, 23, 0x1C0, 10), -+ TOP_MUX(CK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents, 0x020, 0x024, -+ 0x028, 24, 1, 31, 0x1C0, 11), -+ /* CLK_CFG_3 */ -+ TOP_MUX(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents, -+ 0x030, 0x034, 0x038, 0, 1, 7, 0x1C0, 12), -+ TOP_MUX(CK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, 0x030, 0x034, -+ 0x038, 8, 2, 15, 0x1C0, 13), -+ TOP_MUX(CK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x030, 0x034, -+ 0x038, 16, 2, 23, 0x1C0, 14), -+ TOP_MUX(CK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", arm_db_main_parents, -+ 0x030, 0x034, 0x038, 24, 1, 31, 0x1C0, 15), -+ /* CLK_CFG_4 */ -+ TOP_MUX(CK_TOP_ARM_DB_JTSEL, "arm_db_jtsel", arm_db_jtsel_parents, -+ 0x040, 0x044, 0x048, 0, 1, 7, 0x1C0, 16), -+ TOP_MUX(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x040, 0x044, -+ 0x048, 8, 1, 15, 0x1C0, 17), -+ TOP_MUX(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents, -+ 0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18), -+ TOP_MUX(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents, -+ 0x040, 0x044, 0x048, 24, 3, 31, 0x1C0, 19), -+ /* CLK_CFG_5 */ -+ TOP_MUX(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x050, -+ 0x054, 0x058, 0, 2, 7, 0x1C0, 20), -+ TOP_MUX(CK_TOP_SGM_325M_SEL, "sgm_325m_sel", sgm_325m_parents, 0x050, -+ 0x054, 0x058, 8, 1, 15, 0x1C0, 21), -+ TOP_MUX(CK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, 0x050, -+ 0x054, 0x058, 16, 1, 23, 0x1C0, 22), -+ TOP_MUX(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x050, 0x054, -+ 0x058, 24, 1, 31, 0x1C0, 23), -+ /* CLK_CFG_6 */ -+ TOP_MUX(CK_TOP_CONN_MCUSYS_SEL, "conn_mcusys_sel", conn_mcusys_parents, -+ 0x060, 0x064, 0x068, 0, 1, 7, 0x1C0, 24), -+ TOP_MUX(CK_TOP_EIP_B_SEL, "eip_b_sel", eip_b_parents, 0x060, 0x064, -+ 0x068, 8, 1, 15, 0x1C0, 25), -+ TOP_MUX(CK_TOP_PCIE_PHY_SEL, "pcie_phy_sel", f_26m_adc_parents, 0x060, -+ 0x064, 0x068, 16, 1, 23, 0x1C0, 26), -+ TOP_MUX(CK_TOP_USB3_PHY_SEL, "usb3_phy_sel", f_26m_adc_parents, 0x060, -+ 0x064, 0x068, 24, 1, 31, 0x1C0, 27), -+ /* CLK_CFG_7 */ -+ TOP_MUX(CK_TOP_F26M_SEL, "csw_f26m_sel", f_26m_adc_parents, 0x070, -+ 0x074, 0x078, 0, 1, 7, 0x1C0, 28), -+ TOP_MUX(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x070, 0x074, -+ 0x078, 8, 2, 15, 0x1C0, 29), -+ TOP_MUX(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a_tuner_parents, 0x070, -+ 0x074, 0x078, 16, 2, 23, 0x1C0, 30), -+ TOP_MUX(CK_TOP_U2U3_SEL, "u2u3_sel", f_26m_adc_parents, 0x070, 0x074, -+ 0x078, 24, 1, 31, 0x1C4, 0), -+ /* CLK_CFG_8 */ -+ TOP_MUX(CK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", u2u3_sys_parents, 0x080, -+ 0x084, 0x088, 0, 1, 7, 0x1C4, 1), -+ TOP_MUX(CK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", u2u3_sys_parents, 0x080, -+ 0x084, 0x088, 8, 1, 15, 0x1C4, 2), -+ TOP_MUX(CK_TOP_DA_U2_REFSEL, "da_u2_refsel", da_u2_refsel_parents, -+ 0x080, 0x084, 0x088, 16, 1, 23, 0x1C4, 3), -+ TOP_MUX(CK_TOP_DA_U2_CK_1P_SEL, "da_u2_ck_1p_sel", da_u2_refsel_parents, -+ 0x080, 0x084, 0x088, 24, 1, 31, 0x1C4, 4), -+ /* CLK_CFG_9 */ -+ TOP_MUX(CK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", sgm_reg_parents, -+ 0x090, 0x094, 0x098, 0, 1, 7, 0x1C4, 5), -+}; -+ -+/* INFRA FIXED DIV */ -+static const struct mtk_fixed_factor infra_fixed_divs[] = { -+ TOP_FACTOR(CK_INFRA_CK_F26M, "infra_ck_f26m", CK_TOP_F26M_SEL, 1, 1), -+ TOP_FACTOR(CK_INFRA_UART, "infra_uart", CK_TOP_UART_SEL, 1, 1), -+ TOP_FACTOR(CK_INFRA_ISPI0, "infra_ispi0", CK_TOP_SPI_SEL, 1, 1), -+ TOP_FACTOR(CK_INFRA_I2C, "infra_i2c", CK_TOP_I2C_SEL, 1, 1), -+ TOP_FACTOR(CK_INFRA_ISPI1, "infra_ispi1", CK_TOP_SPINFI_SEL, 1, 1), -+ TOP_FACTOR(CK_INFRA_PWM, "infra_pwm", CK_TOP_PWM_SEL, 1, 1), -+ TOP_FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", CK_TOP_SYSAXI_SEL, 1, 2), -+ TOP_FACTOR(CK_INFRA_CK_F32K, "infra_ck_f32k", CK_TOP_CB_RTC_32P7K, 1, -+ 1), -+ TOP_FACTOR(CK_INFRA_PCIE_CK, "infra_pcie", CK_TOP_PEXTP_TL_SEL, 1, 1), -+ INFRA_FACTOR(CK_INFRA_PWM_BCK, "infra_pwm_bck", CK_INFRA_PWM_BSEL, 1, -+ 1), -+ INFRA_FACTOR(CK_INFRA_PWM_CK1, "infra_pwm_ck1", CK_INFRA_PWM1_SEL, 1, -+ 1), -+ INFRA_FACTOR(CK_INFRA_PWM_CK2, "infra_pwm_ck2", CK_INFRA_PWM2_SEL, 1, -+ 1), -+ TOP_FACTOR(CK_INFRA_133M_HCK, "infra_133m_hck", CK_TOP_SYSAXI, 1, 1), -+ TOP_FACTOR(CK_INFRA_EIP_CK, "infra_eip", CK_TOP_EIP_B, 1, 1), -+ INFRA_FACTOR(CK_INFRA_66M_PHCK, "infra_66m_phck", CK_INFRA_133M_HCK, 1, -+ 1), -+ TOP_FACTOR(CK_INFRA_FAUD_L_CK, "infra_faud_l", CK_TOP_AUD_L, 1, 1), -+ TOP_FACTOR(CK_INFRA_FAUD_AUD_CK, "infra_faud_aud", CK_TOP_A1SYS, 1, 1), -+ TOP_FACTOR(CK_INFRA_FAUD_EG2_CK, "infra_faud_eg2", CK_TOP_A_TUNER, 1, -+ 1), -+ TOP_FACTOR(CK_INFRA_I2CS_CK, "infra_i2cs", CK_TOP_I2C_BCK, 1, 1), -+ INFRA_FACTOR(CK_INFRA_MUX_UART0, "infra_mux_uart0", CK_INFRA_UART0_SEL, -+ 1, 1), -+ INFRA_FACTOR(CK_INFRA_MUX_UART1, "infra_mux_uart1", CK_INFRA_UART1_SEL, -+ 1, 1), -+ INFRA_FACTOR(CK_INFRA_MUX_UART2, "infra_mux_uart2", CK_INFRA_UART2_SEL, -+ 1, 1), -+ TOP_FACTOR(CK_INFRA_NFI_CK, "infra_nfi", CK_TOP_NFI1X, 1, 1), -+ TOP_FACTOR(CK_INFRA_SPINFI_CK, "infra_spinfi", CK_TOP_SPINFI_BCK, 1, 1), -+ INFRA_FACTOR(CK_INFRA_MUX_SPI0, "infra_mux_spi0", CK_INFRA_SPI0_SEL, 1, -+ 1), -+ INFRA_FACTOR(CK_INFRA_MUX_SPI1, "infra_mux_spi1", CK_INFRA_SPI1_SEL, 1, -+ 1), -+ TOP_FACTOR(CK_INFRA_RTC_32K, "infra_rtc_32k", CK_TOP_CB_RTC_32K, 1, 1), -+ TOP_FACTOR(CK_INFRA_FMSDC_CK, "infra_fmsdc", CK_TOP_EMMC_416M, 1, 1), -+ TOP_FACTOR(CK_INFRA_FMSDC_HCK_CK, "infra_fmsdc_hck", CK_TOP_EMMC_250M, -+ 1, 1), -+ TOP_FACTOR(CK_INFRA_PERI_133M, "infra_peri_133m", CK_TOP_SYSAXI, 1, 1), -+ TOP_FACTOR(CK_INFRA_133M_PHCK, "infra_133m_phck", CK_TOP_SYSAXI, 1, 1), -+ TOP_FACTOR(CK_INFRA_USB_SYS_CK, "infra_usb_sys", CK_TOP_U2U3_SYS, 1, 1), -+ TOP_FACTOR(CK_INFRA_USB_CK, "infra_usb", CK_TOP_U2U3_REF, 1, 1), -+ TOP_FACTOR(CK_INFRA_USB_XHCI_CK, "infra_usb_xhci", CK_TOP_U2U3_XHCI, 1, -+ 1), -+ TOP_FACTOR(CK_INFRA_PCIE_GFMUX_TL_O_PRE, "infra_pcie_mux", -+ CK_TOP_PEXTP_TL, 1, 1), -+ TOP_FACTOR(CK_INFRA_F26M_CK0, "infra_f26m_ck0", CK_TOP_F26M, 1, 1), -+ TOP_FACTOR(CK_INFRA_HD_133M, "infra_hd_133m", CK_TOP_SYSAXI, 1, 1), -+}; -+ -+/* INFRASYS MUX PARENTS */ -+static const int infra_uart0_parents[] = { CK_INFRA_CK_F26M, CK_INFRA_UART }; -+ -+static const int infra_spi0_parents[] = { CK_INFRA_I2C, CK_INFRA_ISPI0 }; -+ -+static const int infra_spi1_parents[] = { CK_INFRA_I2C, CK_INFRA_ISPI1 }; -+ -+static const int infra_pwm_bsel_parents[] = { CK_INFRA_CK_F32K, -+ CK_INFRA_CK_F26M, -+ CK_INFRA_66M_MCK, CK_INFRA_PWM }; -+ -+static const int infra_pcie_parents[] = { CK_INFRA_CK_F32K, CK_INFRA_CK_F26M, -+ -1, CK_INFRA_PCIE_CK }; -+ -+#define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \ -+ { \ -+ .id = _id, .mux_reg = (_reg) + 0x8, \ -+ .mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \ -+ .mux_shift = _shift, .mux_mask = BIT(_width) - 1, \ -+ .parent = _parents, .num_parents = ARRAY_SIZE(_parents), \ -+ .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_INFRASYS, \ -+ } -+ -+/* INFRA MUX */ -+ -+static const struct mtk_composite infra_muxes[] = { -+ /* MODULE_CLK_SEL_0 */ -+ INFRA_MUX(CK_INFRA_UART0_SEL, "infra_uart0_sel", infra_uart0_parents, -+ 0x10, 0, 1), -+ INFRA_MUX(CK_INFRA_UART1_SEL, "infra_uart1_sel", infra_uart0_parents, -+ 0x10, 1, 1), -+ INFRA_MUX(CK_INFRA_UART2_SEL, "infra_uart2_sel", infra_uart0_parents, -+ 0x10, 2, 1), -+ INFRA_MUX(CK_INFRA_SPI0_SEL, "infra_spi0_sel", infra_spi0_parents, 0x10, -+ 4, 1), -+ INFRA_MUX(CK_INFRA_SPI1_SEL, "infra_spi1_sel", infra_spi1_parents, 0x10, -+ 5, 1), -+ INFRA_MUX(CK_INFRA_PWM1_SEL, "infra_pwm1_sel", infra_pwm_bsel_parents, -+ 0x10, 9, 2), -+ INFRA_MUX(CK_INFRA_PWM2_SEL, "infra_pwm2_sel", infra_pwm_bsel_parents, -+ 0x10, 11, 2), -+ INFRA_MUX(CK_INFRA_PWM_BSEL, "infra_pwm_bsel", infra_pwm_bsel_parents, -+ 0x10, 13, 2), -+ /* MODULE_CLK_SEL_1 */ -+ INFRA_MUX(CK_INFRA_PCIE_SEL, "infra_pcie_sel", infra_pcie_parents, 0x20, -+ 0, 2), -+}; -+ -+static const struct mtk_gate_regs infra_0_cg_regs = { -+ .set_ofs = 0x40, -+ .clr_ofs = 0x44, -+ .sta_ofs = 0x48, -+}; -+ -+static const struct mtk_gate_regs infra_1_cg_regs = { -+ .set_ofs = 0x50, -+ .clr_ofs = 0x54, -+ .sta_ofs = 0x58, -+}; -+ -+static const struct mtk_gate_regs infra_2_cg_regs = { -+ .set_ofs = 0x60, -+ .clr_ofs = 0x64, -+ .sta_ofs = 0x68, -+}; -+ -+#define GATE_INFRA0(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, .parent = _parent, .regs = &infra_0_cg_regs, \ -+ .shift = _shift, \ -+ .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \ -+ } -+ -+#define GATE_INFRA1(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, .parent = _parent, .regs = &infra_1_cg_regs, \ -+ .shift = _shift, \ -+ .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \ -+ } -+ -+#define GATE_INFRA2(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, .parent = _parent, .regs = &infra_2_cg_regs, \ -+ .shift = _shift, \ -+ .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \ -+ } -+ -+/* INFRA GATE */ -+ -+static const struct mtk_gate infracfg_ao_gates[] = { -+ /* INFRA0 */ -+ GATE_INFRA0(CK_INFRA_GPT_STA, "infra_gpt_sta", CK_INFRA_66M_MCK, 0), -+ GATE_INFRA0(CK_INFRA_PWM_HCK, "infra_pwm_hck", CK_INFRA_66M_MCK, 1), -+ GATE_INFRA0(CK_INFRA_PWM_STA, "infra_pwm_sta", CK_INFRA_PWM_BCK, 2), -+ GATE_INFRA0(CK_INFRA_PWM1_CK, "infra_pwm1", CK_INFRA_PWM_CK1, 3), -+ GATE_INFRA0(CK_INFRA_PWM2_CK, "infra_pwm2", CK_INFRA_PWM_CK2, 4), -+ GATE_INFRA0(CK_INFRA_CQ_DMA_CK, "infra_cq_dma", CK_INFRA_133M_HCK, 6), -+ GATE_INFRA0(CK_INFRA_EIP97_CK, "infra_eip97", CK_INFRA_EIP_CK, 7), -+ GATE_INFRA0(CK_INFRA_AUD_BUS_CK, "infra_aud_bus", CK_INFRA_66M_PHCK, 8), -+ GATE_INFRA0(CK_INFRA_AUD_26M_CK, "infra_aud_26m", CK_INFRA_CK_F26M, 9), -+ GATE_INFRA0(CK_INFRA_AUD_L_CK, "infra_aud_l", CK_INFRA_FAUD_L_CK, 10), -+ GATE_INFRA0(CK_INFRA_AUD_AUD_CK, "infra_aud_aud", CK_INFRA_FAUD_AUD_CK, -+ 11), -+ GATE_INFRA0(CK_INFRA_AUD_EG2_CK, "infra_aud_eg2", CK_INFRA_FAUD_EG2_CK, -+ 13), -+ GATE_INFRA0(CK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", CK_INFRA_CK_F26M, -+ 14), -+ GATE_INFRA0(CK_INFRA_DBG_CK, "infra_dbg", CK_INFRA_66M_MCK, 15), -+ GATE_INFRA0(CK_INFRA_AP_DMA_CK, "infra_ap_dma", CK_INFRA_66M_MCK, 16), -+ GATE_INFRA0(CK_INFRA_SEJ_CK, "infra_sej", CK_INFRA_66M_MCK, 24), -+ GATE_INFRA0(CK_INFRA_SEJ_13M_CK, "infra_sej_13m", CK_INFRA_CK_F26M, 25), -+ GATE_INFRA0(CK_INFRA_TRNG_CK, "infra_trng", CK_INFRA_HD_133M, 26), -+ /* INFRA1 */ -+ GATE_INFRA1(CK_INFRA_THERM_CK, "infra_therm", CK_INFRA_CK_F26M, 0), -+ GATE_INFRA1(CK_INFRA_I2CO_CK, "infra_i2co", CK_INFRA_I2CS_CK, 1), -+ GATE_INFRA1(CK_INFRA_UART0_CK, "infra_uart0", CK_INFRA_MUX_UART0, 2), -+ GATE_INFRA1(CK_INFRA_UART1_CK, "infra_uart1", CK_INFRA_MUX_UART1, 3), -+ GATE_INFRA1(CK_INFRA_UART2_CK, "infra_uart2", CK_INFRA_MUX_UART2, 4), -+ GATE_INFRA1(CK_INFRA_NFI1_CK, "infra_nfi1", CK_INFRA_NFI_CK, 8), -+ GATE_INFRA1(CK_INFRA_SPINFI1_CK, "infra_spinfi1", CK_INFRA_SPINFI_CK, -+ 9), -+ GATE_INFRA1(CK_INFRA_NFI_HCK_CK, "infra_nfi_hck", CK_INFRA_66M_MCK, 10), -+ GATE_INFRA1(CK_INFRA_SPI0_CK, "infra_spi0", CK_INFRA_MUX_SPI0, 11), -+ GATE_INFRA1(CK_INFRA_SPI1_CK, "infra_spi1", CK_INFRA_MUX_SPI1, 12), -+ GATE_INFRA1(CK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", CK_INFRA_66M_MCK, -+ 13), -+ GATE_INFRA1(CK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", CK_INFRA_66M_MCK, -+ 14), -+ GATE_INFRA1(CK_INFRA_FRTC_CK, "infra_frtc", CK_INFRA_RTC_32K, 15), -+ GATE_INFRA1(CK_INFRA_MSDC_CK, "infra_msdc", CK_INFRA_FMSDC_CK, 16), -+ GATE_INFRA1(CK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", -+ CK_INFRA_FMSDC_HCK_CK, 17), -+ GATE_INFRA1(CK_INFRA_MSDC_133M_CK, "infra_msdc_133m", -+ CK_INFRA_PERI_133M, 18), -+ GATE_INFRA1(CK_INFRA_MSDC_66M_CK, "infra_msdc_66m", CK_INFRA_66M_PHCK, -+ 19), -+ GATE_INFRA1(CK_INFRA_ADC_26M_CK, "infra_adc_26m", CK_INFRA_CK_F26M, 20), -+ GATE_INFRA1(CK_INFRA_ADC_FRC_CK, "infra_adc_frc", CK_INFRA_CK_F26M, 21), -+ GATE_INFRA1(CK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", CK_INFRA_NFI_CK, -+ 23), -+ /* INFRA2 */ -+ GATE_INFRA2(CK_INFRA_IUSB_133_CK, "infra_iusb_133", CK_INFRA_133M_PHCK, -+ 0), -+ GATE_INFRA2(CK_INFRA_IUSB_66M_CK, "infra_iusb_66m", CK_INFRA_66M_PHCK, -+ 1), -+ GATE_INFRA2(CK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", CK_INFRA_USB_SYS_CK, -+ 2), -+ GATE_INFRA2(CK_INFRA_IUSB_CK, "infra_iusb", CK_INFRA_USB_CK, 3), -+ GATE_INFRA2(CK_INFRA_IPCIE_CK, "infra_ipcie", CK_INFRA_PCIE_CK, 13), -+ GATE_INFRA2(CK_INFRA_IPCIER_CK, "infra_ipcier", CK_INFRA_F26M_CK0, 15), -+ GATE_INFRA2(CK_INFRA_IPCIEB_CK, "infra_ipcieb", CK_INFRA_133M_PHCK, 15), -+}; -+ -+static const struct mtk_clk_tree mt7986_fixed_pll_clk_tree = { -+ .fdivs_offs = CLK_APMIXED_NR_CLK, -+ .xtal_rate = 40 * MHZ, -+ .fclks = fixed_pll_clks, -+}; -+ -+static const struct mtk_clk_tree mt7986_topckgen_clk_tree = { -+ .fdivs_offs = CK_TOP_CB_M_416M, -+ .muxes_offs = CK_TOP_NFI1X_SEL, -+ .fclks = top_fixed_clks, -+ .fdivs = top_fixed_divs, -+ .muxes = top_muxes, -+ .flags = CLK_BYPASS_XTAL, -+}; -+ -+static const struct mtk_clk_tree mt7986_infracfg_clk_tree = { -+ .fdivs_offs = CK_INFRA_CK_F26M, -+ .muxes_offs = CK_INFRA_UART0_SEL, -+ .fdivs = infra_fixed_divs, -+ .muxes = infra_muxes, -+}; -+ -+static const struct udevice_id mt7986_fixed_pll_compat[] = { -+ { .compatible = "mediatek,mt7986-fixed-plls" }, -+ {} -+}; -+ -+static const struct udevice_id mt7986_topckgen_compat[] = { -+ { .compatible = "mediatek,mt7986-topckgen" }, -+ {} -+}; -+ -+static int mt7986_fixed_pll_probe(struct udevice *dev) -+{ -+ return mtk_common_clk_init(dev, &mt7986_fixed_pll_clk_tree); -+} -+ -+static int mt7986_topckgen_probe(struct udevice *dev) -+{ -+ struct mtk_clk_priv *priv = dev_get_priv(dev); -+ -+ priv->base = dev_read_addr_ptr(dev); -+ writel(MT7986_CLK_PDN_EN_WRITE, priv->base + MT7986_CLK_PDN); -+ -+ return mtk_common_clk_init(dev, &mt7986_topckgen_clk_tree); -+} -+ -+U_BOOT_DRIVER(mtk_clk_apmixedsys) = { -+ .name = "mt7986-clock-fixed-pll", -+ .id = UCLASS_CLK, -+ .of_match = mt7986_fixed_pll_compat, -+ .probe = mt7986_fixed_pll_probe, -+ .priv_auto = sizeof(struct mtk_clk_priv), -+ .ops = &mtk_clk_topckgen_ops, -+ .flags = DM_FLAG_PRE_RELOC, -+}; -+ -+U_BOOT_DRIVER(mtk_clk_topckgen) = { -+ .name = "mt7986-clock-topckgen", -+ .id = UCLASS_CLK, -+ .of_match = mt7986_topckgen_compat, -+ .probe = mt7986_topckgen_probe, -+ .priv_auto = sizeof(struct mtk_clk_priv), -+ .ops = &mtk_clk_topckgen_ops, -+ .flags = DM_FLAG_PRE_RELOC, -+}; -+ -+static const struct udevice_id mt7986_infracfg_compat[] = { -+ { .compatible = "mediatek,mt7986-infracfg" }, -+ {} -+}; -+ -+static const struct udevice_id mt7986_infracfg_ao_compat[] = { -+ { .compatible = "mediatek,mt7986-infracfg_ao" }, -+ {} -+}; -+ -+static int mt7986_infracfg_probe(struct udevice *dev) -+{ -+ return mtk_common_clk_init(dev, &mt7986_infracfg_clk_tree); -+} -+ -+static int mt7986_infracfg_ao_probe(struct udevice *dev) -+{ -+ return mtk_common_clk_gate_init(dev, &mt7986_infracfg_clk_tree, -+ infracfg_ao_gates); -+} -+ -+U_BOOT_DRIVER(mtk_clk_infracfg) = { -+ .name = "mt7986-clock-infracfg", -+ .id = UCLASS_CLK, -+ .of_match = mt7986_infracfg_compat, -+ .probe = mt7986_infracfg_probe, -+ .priv_auto = sizeof(struct mtk_clk_priv), -+ .ops = &mtk_clk_infrasys_ops, -+ .flags = DM_FLAG_PRE_RELOC, -+}; -+ -+U_BOOT_DRIVER(mtk_clk_infracfg_ao) = { -+ .name = "mt7986-clock-infracfg-ao", -+ .id = UCLASS_CLK, -+ .of_match = mt7986_infracfg_ao_compat, -+ .probe = mt7986_infracfg_ao_probe, -+ .priv_auto = sizeof(struct mtk_cg_priv), -+ .ops = &mtk_clk_gate_ops, -+ .flags = DM_FLAG_PRE_RELOC, -+}; -+ -+/* ethsys */ -+static const struct mtk_gate_regs eth_cg_regs = { -+ .sta_ofs = 0x30, -+}; -+ -+#define GATE_ETH(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, .parent = _parent, .regs = ð_cg_regs, \ -+ .shift = _shift, \ -+ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ -+ } -+ -+static const struct mtk_gate eth_cgs[] = { -+ GATE_ETH(CK_ETH_FE_EN, "eth_fe_en", CK_TOP_NETSYS_2X, 7), -+ GATE_ETH(CK_ETH_GP2_EN, "eth_gp2_en", CK_TOP_SGM_325M, 8), -+ GATE_ETH(CK_ETH_GP1_EN, "eth_gp1_en", CK_TOP_SGM_325M, 8), -+ GATE_ETH(CK_ETH_WOCPU1_EN, "eth_wocpu1_en", CK_TOP_NETSYS_WED_MCU, 14), -+ GATE_ETH(CK_ETH_WOCPU0_EN, "eth_wocpu0_en", CK_TOP_NETSYS_WED_MCU, 15), -+}; -+ -+static int mt7986_ethsys_probe(struct udevice *dev) -+{ -+ return mtk_common_clk_gate_init(dev, &mt7986_topckgen_clk_tree, -+ eth_cgs); -+} -+ -+static int mt7986_ethsys_bind(struct udevice *dev) -+{ -+ int ret = 0; -+ -+ if (CONFIG_IS_ENABLED(RESET_MEDIATEK)) { -+ ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1); -+ if (ret) -+ debug("Warning: failed to bind reset controller\n"); -+ } -+ -+ return ret; -+} -+ -+static const struct udevice_id mt7986_ethsys_compat[] = { -+ { .compatible = "mediatek,mt7986-ethsys" }, -+ { } -+}; -+ -+U_BOOT_DRIVER(mtk_clk_ethsys) = { -+ .name = "mt7986-clock-ethsys", -+ .id = UCLASS_CLK, -+ .of_match = mt7986_ethsys_compat, -+ .probe = mt7986_ethsys_probe, -+ .bind = mt7986_ethsys_bind, -+ .priv_auto = sizeof(struct mtk_cg_priv), -+ .ops = &mtk_clk_gate_ops, -+}; ---- /dev/null -+++ b/include/dt-bindings/clock/mt7986-clk.h -@@ -0,0 +1,249 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Copyright (C) 2022 MediaTek Inc. All rights reserved. -+ * -+ * Author: Sam Shih -+ */ -+ -+#ifndef _DT_BINDINGS_CLK_MT7986_H -+#define _DT_BINDINGS_CLK_MT7986_H -+ -+/* INFRACFG */ -+ -+#define CK_INFRA_CK_F26M 0 -+#define CK_INFRA_UART 1 -+#define CK_INFRA_ISPI0 2 -+#define CK_INFRA_I2C 3 -+#define CK_INFRA_ISPI1 4 -+#define CK_INFRA_PWM 5 -+#define CK_INFRA_66M_MCK 6 -+#define CK_INFRA_CK_F32K 7 -+#define CK_INFRA_PCIE_CK 8 -+#define CK_INFRA_PWM_BCK 9 -+#define CK_INFRA_PWM_CK1 10 -+#define CK_INFRA_PWM_CK2 11 -+#define CK_INFRA_133M_HCK 12 -+#define CK_INFRA_EIP_CK 13 -+#define CK_INFRA_66M_PHCK 14 -+#define CK_INFRA_FAUD_L_CK 15 -+#define CK_INFRA_FAUD_AUD_CK 17 -+#define CK_INFRA_FAUD_EG2_CK 17 -+#define CK_INFRA_I2CS_CK 18 -+#define CK_INFRA_MUX_UART0 19 -+#define CK_INFRA_MUX_UART1 20 -+#define CK_INFRA_MUX_UART2 21 -+#define CK_INFRA_NFI_CK 22 -+#define CK_INFRA_SPINFI_CK 23 -+#define CK_INFRA_MUX_SPI0 24 -+#define CK_INFRA_MUX_SPI1 25 -+#define CK_INFRA_RTC_32K 26 -+#define CK_INFRA_FMSDC_CK 27 -+#define CK_INFRA_FMSDC_HCK_CK 28 -+#define CK_INFRA_PERI_133M 29 -+#define CK_INFRA_133M_PHCK 30 -+#define CK_INFRA_USB_SYS_CK 31 -+#define CK_INFRA_USB_CK 32 -+#define CK_INFRA_USB_XHCI_CK 33 -+#define CK_INFRA_PCIE_GFMUX_TL_O_PRE 34 -+#define CK_INFRA_F26M_CK0 35 -+#define CK_INFRA_HD_133M 36 -+#define CLK_INFRA_NR_CLK 37 -+ -+/* TOPCKGEN */ -+ -+#define CK_TOP_CB_CKSQ_40M 0 -+#define CK_TOP_CB_M_416M 1 -+#define CK_TOP_CB_M_D2 2 -+#define CK_TOP_CB_M_D4 3 -+#define CK_TOP_CB_M_D8 4 -+#define CK_TOP_M_D8_D2 5 -+#define CK_TOP_M_D3_D2 6 -+#define CK_TOP_CB_MM_D2 7 -+#define CK_TOP_CB_MM_D4 8 -+#define CK_TOP_CB_MM_D8 9 -+#define CK_TOP_MM_D8_D2 10 -+#define CK_TOP_MM_D3_D8 11 -+#define CK_TOP_CB_U2_PHYD_CK 12 -+#define CK_TOP_CB_APLL2_196M 13 -+#define CK_TOP_APLL2_D4 14 -+#define CK_TOP_CB_NET1_D4 15 -+#define CK_TOP_CB_NET1_D5 16 -+#define CK_TOP_NET1_D5_D2 17 -+#define CK_TOP_NET1_D5_D4 18 -+#define CK_TOP_NET1_D8_D2 19 -+#define CK_TOP_NET1_D8_D4 20 -+#define CK_TOP_CB_NET2_800M 21 -+#define CK_TOP_CB_NET2_D4 22 -+#define CK_TOP_NET2_D4_D2 23 -+#define CK_TOP_NET2_D3_D2 24 -+#define CK_TOP_CB_WEDMCU_760M 25 -+#define CK_TOP_WEDMCU_D5_D2 26 -+#define CK_TOP_CB_SGM_325M 27 -+#define CK_TOP_CB_CKSQ_40M_D2 28 -+#define CK_TOP_CB_RTC_32K 29 -+#define CK_TOP_CB_RTC_32P7K 30 -+#define CK_TOP_NFI1X 31 -+#define CK_TOP_USB_EQ_RX250M 32 -+#define CK_TOP_USB_TX250M 33 -+#define CK_TOP_USB_LN0_CK 34 -+#define CK_TOP_USB_CDR_CK 35 -+#define CK_TOP_SPINFI_BCK 36 -+#define CK_TOP_I2C_BCK 37 -+#define CK_TOP_PEXTP_TL 38 -+#define CK_TOP_EMMC_250M 39 -+#define CK_TOP_EMMC_416M 40 -+#define CK_TOP_F_26M_ADC_CK 41 -+#define CK_TOP_SYSAXI 42 -+#define CK_TOP_NETSYS_WED_MCU 43 -+#define CK_TOP_NETSYS_2X 44 -+#define CK_TOP_SGM_325M 45 -+#define CK_TOP_A1SYS 46 -+#define CK_TOP_EIP_B 47 -+#define CK_TOP_F26M 48 -+#define CK_TOP_AUD_L 49 -+#define CK_TOP_A_TUNER 50 -+#define CK_TOP_U2U3_REF 51 -+#define CK_TOP_U2U3_SYS 52 -+#define CK_TOP_U2U3_XHCI 53 -+#define CK_TOP_AP2CNN_HOST 54 -+#define CK_TOP_NFI1X_SEL 55 -+#define CK_TOP_SPINFI_SEL 56 -+#define CK_TOP_SPI_SEL 57 -+#define CK_TOP_SPIM_MST_SEL 58 -+#define CK_TOP_UART_SEL 59 -+#define CK_TOP_PWM_SEL 60 -+#define CK_TOP_I2C_SEL 61 -+#define CK_TOP_PEXTP_TL_SEL 62 -+#define CK_TOP_EMMC_250M_SEL 63 -+#define CK_TOP_EMMC_416M_SEL 64 -+#define CK_TOP_F_26M_ADC_SEL 65 -+#define CK_TOP_DRAMC_SEL 66 -+#define CK_TOP_DRAMC_MD32_SEL 67 -+#define CK_TOP_SYSAXI_SEL 68 -+#define CK_TOP_SYSAPB_SEL 69 -+#define CK_TOP_ARM_DB_MAIN_SEL 70 -+#define CK_TOP_ARM_DB_JTSEL 71 -+#define CK_TOP_NETSYS_SEL 72 -+#define CK_TOP_NETSYS_500M_SEL 73 -+#define CK_TOP_NETSYS_MCU_SEL 74 -+#define CK_TOP_NETSYS_2X_SEL 75 -+#define CK_TOP_SGM_325M_SEL 76 -+#define CK_TOP_SGM_REG_SEL 77 -+#define CK_TOP_A1SYS_SEL 78 -+#define CK_TOP_CONN_MCUSYS_SEL 79 -+#define CK_TOP_EIP_B_SEL 80 -+#define CK_TOP_PCIE_PHY_SEL 81 -+#define CK_TOP_USB3_PHY_SEL 82 -+#define CK_TOP_F26M_SEL 83 -+#define CK_TOP_AUD_L_SEL 84 -+#define CK_TOP_A_TUNER_SEL 85 -+#define CK_TOP_U2U3_SEL 86 -+#define CK_TOP_U2U3_SYS_SEL 87 -+#define CK_TOP_U2U3_XHCI_SEL 88 -+#define CK_TOP_DA_U2_REFSEL 89 -+#define CK_TOP_DA_U2_CK_1P_SEL 90 -+#define CK_TOP_AP2CNN_HOST_SEL 91 -+#define CLK_TOP_NR_CLK 92 -+ -+/* -+ * INFRACFG_AO -+ * clock muxes need to be append to infracfg domain, and clock gates -+ * need to be keep in infracgh_ao domain -+ */ -+ -+#define CK_INFRA_UART0_SEL (0 + CLK_INFRA_NR_CLK) -+#define CK_INFRA_UART1_SEL (1 + CLK_INFRA_NR_CLK) -+#define CK_INFRA_UART2_SEL (2 + CLK_INFRA_NR_CLK) -+#define CK_INFRA_SPI0_SEL (3 + CLK_INFRA_NR_CLK) -+#define CK_INFRA_SPI1_SEL (4 + CLK_INFRA_NR_CLK) -+#define CK_INFRA_PWM1_SEL (5 + CLK_INFRA_NR_CLK) -+#define CK_INFRA_PWM2_SEL (6 + CLK_INFRA_NR_CLK) -+#define CK_INFRA_PWM_BSEL (7 + CLK_INFRA_NR_CLK) -+#define CK_INFRA_PCIE_SEL (8 + CLK_INFRA_NR_CLK) -+#define CK_INFRA_GPT_STA 0 -+#define CK_INFRA_PWM_HCK 1 -+#define CK_INFRA_PWM_STA 2 -+#define CK_INFRA_PWM1_CK 3 -+#define CK_INFRA_PWM2_CK 4 -+#define CK_INFRA_CQ_DMA_CK 5 -+#define CK_INFRA_EIP97_CK 6 -+#define CK_INFRA_AUD_BUS_CK 7 -+#define CK_INFRA_AUD_26M_CK 8 -+#define CK_INFRA_AUD_L_CK 9 -+#define CK_INFRA_AUD_AUD_CK 10 -+#define CK_INFRA_AUD_EG2_CK 11 -+#define CK_INFRA_DRAMC_26M_CK 12 -+#define CK_INFRA_DBG_CK 13 -+#define CK_INFRA_AP_DMA_CK 14 -+#define CK_INFRA_SEJ_CK 15 -+#define CK_INFRA_SEJ_13M_CK 16 -+#define CK_INFRA_THERM_CK 17 -+#define CK_INFRA_I2CO_CK 18 -+#define CK_INFRA_TRNG_CK 19 -+#define CK_INFRA_UART0_CK 20 -+#define CK_INFRA_UART1_CK 21 -+#define CK_INFRA_UART2_CK 22 -+#define CK_INFRA_NFI1_CK 23 -+#define CK_INFRA_SPINFI1_CK 24 -+#define CK_INFRA_NFI_HCK_CK 25 -+#define CK_INFRA_SPI0_CK 26 -+#define CK_INFRA_SPI1_CK 27 -+#define CK_INFRA_SPI0_HCK_CK 28 -+#define CK_INFRA_SPI1_HCK_CK 29 -+#define CK_INFRA_FRTC_CK 30 -+#define CK_INFRA_MSDC_CK 31 -+#define CK_INFRA_MSDC_HCK_CK 32 -+#define CK_INFRA_MSDC_133M_CK 33 -+#define CK_INFRA_MSDC_66M_CK 34 -+#define CK_INFRA_ADC_26M_CK 35 -+#define CK_INFRA_ADC_FRC_CK 36 -+#define CK_INFRA_FBIST2FPC_CK 37 -+#define CK_INFRA_IUSB_133_CK 38 -+#define CK_INFRA_IUSB_66M_CK 39 -+#define CK_INFRA_IUSB_SYS_CK 40 -+#define CK_INFRA_IUSB_CK 41 -+#define CK_INFRA_IPCIE_CK 42 -+#define CK_INFRA_IPCIER_CK 43 -+#define CK_INFRA_IPCIEB_CK 44 -+#define CLK_INFRA_AO_NR_CLK 45 -+ -+/* APMIXEDSYS */ -+ -+#define CK_APMIXED_ARMPLL 0 -+#define CK_APMIXED_NET2PLL 1 -+#define CK_APMIXED_MMPLL 2 -+#define CK_APMIXED_SGMPLL 3 -+#define CK_APMIXED_WEDMCUPLL 4 -+#define CK_APMIXED_NET1PLL 5 -+#define CK_APMIXED_MPLL 6 -+#define CK_APMIXED_APLL2 7 -+#define CLK_APMIXED_NR_CLK 8 -+ -+/* SGMIISYS_0 */ -+ -+#define CK_SGM0_TX_EN 0 -+#define CK_SGM0_RX_EN 1 -+#define CK_SGM0_CK0_EN 2 -+#define CK_SGM0_CDR_CK0_EN 3 -+#define CLK_SGMII0_NR_CLK 4 -+ -+/* SGMIISYS_1 */ -+ -+#define CK_SGM1_TX_EN 0 -+#define CK_SGM1_RX_EN 1 -+#define CK_SGM1_CK1_EN 2 -+#define CK_SGM1_CDR_CK1_EN 3 -+#define CLK_SGMII1_NR_CLK 4 -+ -+/* ETHSYS */ -+ -+#define CK_ETH_FE_EN 0 -+#define CK_ETH_GP2_EN 1 -+#define CK_ETH_GP1_EN 2 -+#define CK_ETH_WOCPU1_EN 3 -+#define CK_ETH_WOCPU0_EN 4 -+#define CLK_ETH_NR_CLK 5 -+ -+#endif -+ -+/* _DT_BINDINGS_CLK_MT7986_H */ diff --git a/package/boot/uboot-mediatek/patches/002-0027-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch b/package/boot/uboot-mediatek/patches/002-0027-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch deleted file mode 100644 index cc90fa1944c..00000000000 --- a/package/boot/uboot-mediatek/patches/002-0027-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch +++ /dev/null @@ -1,985 +0,0 @@ -From d525836896235c4678f6144cc4608d5b15e02660 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 31 Aug 2022 19:05:16 +0800 -Subject: [PATCH 27/32] clk: mediatek: add clock driver support for MediaTek - MT7981 SoC - -This patch adds clock driver support for MediaTek MT7981 SoC - -Reviewed-by: Sean Anderson -Reviewed-by: Simon Glass -Signed-off-by: Weijie Gao ---- - drivers/clk/mediatek/Makefile | 1 + - drivers/clk/mediatek/clk-mt7981.c | 683 +++++++++++++++++++++++++ - include/dt-bindings/clock/mt7981-clk.h | 267 ++++++++++ - 3 files changed, 951 insertions(+) - create mode 100644 drivers/clk/mediatek/clk-mt7981.c - create mode 100644 include/dt-bindings/clock/mt7981-clk.h - ---- a/drivers/clk/mediatek/Makefile -+++ b/drivers/clk/mediatek/Makefile -@@ -8,6 +8,7 @@ obj-$(CONFIG_TARGET_MT7623) += clk-mt762 - obj-$(CONFIG_TARGET_MT7622) += clk-mt7622.o - obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o - obj-$(CONFIG_TARGET_MT7986) += clk-mt7986.o -+obj-$(CONFIG_TARGET_MT7981) += clk-mt7981.o - obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o - obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o - obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o ---- /dev/null -+++ b/drivers/clk/mediatek/clk-mt7981.c -@@ -0,0 +1,683 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * MediaTek clock driver for MT7981 SoC -+ * -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Sam Shih -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "clk-mtk.h" -+ -+#define MT7981_CLK_PDN 0x250 -+#define MT7981_CLK_PDN_EN_WRITE BIT(31) -+ -+#define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ -+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) -+ -+#define TOP_FACTOR(_id, _name, _parent, _mult, _div) \ -+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) -+ -+#define INFRA_FACTOR(_id, _name, _parent, _mult, _div) \ -+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_INFRASYS) -+ -+/* FIXED PLLS */ -+static const struct mtk_fixed_clk fixed_pll_clks[] = { -+ FIXED_CLK(CK_APMIXED_ARMPLL, CLK_XTAL, 1300000000), -+ FIXED_CLK(CK_APMIXED_NET2PLL, CLK_XTAL, 800000000), -+ FIXED_CLK(CK_APMIXED_MMPLL, CLK_XTAL, 720000000), -+ FIXED_CLK(CK_APMIXED_SGMPLL, CLK_XTAL, 325000000), -+ FIXED_CLK(CK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000), -+ FIXED_CLK(CK_APMIXED_NET1PLL, CLK_XTAL, 2500000000), -+ FIXED_CLK(CK_APMIXED_MPLL, CLK_XTAL, 416000000), -+ FIXED_CLK(CK_APMIXED_APLL2, CLK_XTAL, 196608000), -+}; -+ -+/* TOPCKGEN FIXED CLK */ -+static const struct mtk_fixed_clk top_fixed_clks[] = { -+ FIXED_CLK(CK_TOP_CB_CKSQ_40M, CLK_XTAL, 40000000), -+}; -+ -+/* TOPCKGEN FIXED DIV */ -+static const struct mtk_fixed_factor top_fixed_divs[] = { -+ PLL_FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", CK_APMIXED_MPLL, 1, 1), -+ PLL_FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", CK_APMIXED_MPLL, 1, 2), -+ PLL_FACTOR(CK_TOP_CB_M_D3, "cb_m_d3", CK_APMIXED_MPLL, 1, 3), -+ PLL_FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", CK_APMIXED_MPLL, 1, 2), -+ PLL_FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", CK_APMIXED_MPLL, 1, 4), -+ PLL_FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", CK_APMIXED_MPLL, 1, 8), -+ PLL_FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", CK_APMIXED_MPLL, 1, 16), -+ PLL_FACTOR(CK_TOP_CB_MM_720M, "cb_mm_720m", CK_APMIXED_MMPLL, 1, 1), -+ PLL_FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", CK_APMIXED_MMPLL, 1, 2), -+ PLL_FACTOR(CK_TOP_CB_MM_D3, "cb_mm_d3", CK_APMIXED_MMPLL, 1, 3), -+ PLL_FACTOR(CK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", CK_APMIXED_MMPLL, 1, 15), -+ PLL_FACTOR(CK_TOP_CB_MM_D4, "cb_mm_d4", CK_APMIXED_MMPLL, 1, 4), -+ PLL_FACTOR(CK_TOP_CB_MM_D6, "cb_mm_d6", CK_APMIXED_MMPLL, 1, 6), -+ PLL_FACTOR(CK_TOP_MM_D6_D2, "mm_d6_d2", CK_APMIXED_MMPLL, 1, 12), -+ PLL_FACTOR(CK_TOP_CB_MM_D8, "cb_mm_d8", CK_APMIXED_MMPLL, 1, 8), -+ PLL_FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", CK_APMIXED_APLL2, 1, -+ 1), -+ PLL_FACTOR(CK_TOP_APLL2_D2, "apll2_d2", CK_APMIXED_APLL2, 1, 2), -+ PLL_FACTOR(CK_TOP_APLL2_D4, "apll2_d4", CK_APMIXED_APLL2, 1, 4), -+ PLL_FACTOR(CK_TOP_NET1_2500M, "net1_2500m", CK_APMIXED_NET1PLL, 1, 1), -+ PLL_FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", CK_APMIXED_NET1PLL, 1, 4), -+ PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5), -+ PLL_FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", CK_APMIXED_NET1PLL, 1, 10), -+ PLL_FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", CK_APMIXED_NET1PLL, 1, 20), -+ PLL_FACTOR(CK_TOP_CB_NET1_D8, "cb_net1_d8", CK_APMIXED_NET1PLL, 1, 8), -+ PLL_FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", CK_APMIXED_NET1PLL, 1, 16), -+ PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32), -+ PLL_FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", CK_APMIXED_NET2PLL, 1, -+ 1), -+ PLL_FACTOR(CK_TOP_CB_NET2_D2, "cb_net2_d2", CK_APMIXED_NET2PLL, 1, 2), -+ PLL_FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", CK_APMIXED_NET2PLL, 1, 4), -+ PLL_FACTOR(CK_TOP_NET2_D4_D2, "net2_d4_d2", CK_APMIXED_NET2PLL, 1, 8), -+ PLL_FACTOR(CK_TOP_NET2_D4_D4, "net2_d4_d4", CK_APMIXED_NET2PLL, 1, 16), -+ PLL_FACTOR(CK_TOP_CB_NET2_D6, "cb_net2_d6", CK_APMIXED_NET2PLL, 1, 6), -+ PLL_FACTOR(CK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", -+ CK_APMIXED_WEDMCUPLL, 1, 1), -+ PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1), -+ TOP_FACTOR(CK_TOP_CKSQ_40M_D2, "cksq_40m_d2", CK_TOP_CB_CKSQ_40M, 1, 2), -+ TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_CB_CKSQ_40M, 1, -+ 1250), -+ TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_CB_CKSQ_40M, 1, -+ 1220), -+ TOP_FACTOR(CK_TOP_USB_TX250M, "usb_tx250m", CK_TOP_CB_CKSQ_40M, 1, 1), -+ TOP_FACTOR(CK_TOP_FAUD, "faud", CK_TOP_CB_CKSQ_40M, 1, 1), -+ TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", CK_TOP_CB_CKSQ_40M, 1, -+ 1), -+ TOP_FACTOR(CK_TOP_USB_CDR_CK, "usb_cdr", CK_TOP_CB_CKSQ_40M, 1, 1), -+ TOP_FACTOR(CK_TOP_USB_LN0_CK, "usb_ln0", CK_TOP_CB_CKSQ_40M, 1, 1), -+ TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_SPI, "spi", CK_TOP_SPI_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_SPIM_MST, "spim_mst", CK_TOP_SPIM_MST_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_UART_BCK, "uart_bck", CK_TOP_UART_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_PWM_BCK, "pwm_bck", CK_TOP_PWM_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_PEXTP_TL, "pextp_tl", CK_TOP_PEXTP_TL_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_EMMC_208M, "emmc_208m", CK_TOP_EMMC_208M_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_EMMC_400M, "emmc_400m", CK_TOP_EMMC_400M_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_DRAMC_REF, "dramc_ref", CK_TOP_DRAMC_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_DRAMC_MD32, "dramc_md32", CK_TOP_DRAMC_MD32_SEL, 1, -+ 1), -+ TOP_FACTOR(CK_TOP_SYSAXI, "sysaxi", CK_TOP_SYSAXI_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_SYSAPB, "sysapb", CK_TOP_SYSAPB_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_ARM_DB_MAIN, "arm_db_main", CK_TOP_ARM_DB_MAIN_SEL, 1, -+ 1), -+ TOP_FACTOR(CK_TOP_AP2CNN_HOST, "ap2cnn_host", CK_TOP_AP2CNN_HOST_SEL, 1, -+ 1), -+ TOP_FACTOR(CK_TOP_NETSYS, "netsys", CK_TOP_NETSYS_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_NETSYS_500M, "netsys_500m", CK_TOP_NETSYS_500M_SEL, 1, -+ 1), -+ TOP_FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", -+ CK_TOP_NETSYS_MCU_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_SGM_325M, "sgm_325m", CK_TOP_SGM_325M_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_SGM_REG, "sgm_reg", CK_TOP_SGM_REG_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_F26M, "csw_f26m", CK_TOP_F26M_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_EIP97B, "eip97b", CK_TOP_EIP97B_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_USB3_PHY, "usb3_phy", CK_TOP_USB3_PHY_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_AUD, "aud", CK_TOP_FAUD, 1, 1), -+ TOP_FACTOR(CK_TOP_A1SYS, "a1sys", CK_TOP_A1SYS_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_AUD_L, "aud_l", CK_TOP_AUD_L_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_U2U3_REF, "u2u3_ref", CK_TOP_U2U3_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_U2U3_SYS, "u2u3_sys", CK_TOP_U2U3_SYS_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_U2U3_XHCI, "u2u3_xhci", CK_TOP_U2U3_XHCI_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_USB_FRMCNT, "usb_frmcnt", CK_TOP_USB_FRMCNT_SEL, 1, -+ 1), -+}; -+ -+/* TOPCKGEN MUX PARENTS */ -+static const int nfi1x_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D4, -+ CK_TOP_NET1_D8_D2, CK_TOP_CB_NET2_D6, -+ CK_TOP_CB_M_D4, CK_TOP_CB_MM_D8, -+ CK_TOP_NET1_D8_D4, CK_TOP_CB_M_D8 }; -+ -+static const int spinfi_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_CB_CKSQ_40M, -+ CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4, -+ CK_TOP_CB_MM_D8, CK_TOP_NET1_D8_D4, -+ CK_TOP_MM_D6_D2, CK_TOP_CB_M_D8 }; -+ -+static const int spi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2, -+ CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2, -+ CK_TOP_CB_NET2_D6, CK_TOP_NET1_D5_D4, -+ CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 }; -+ -+static const int uart_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D8, -+ CK_TOP_M_D8_D2 }; -+ -+static const int pwm_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2, -+ CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4, -+ CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K }; -+ -+static const int i2c_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4, -+ CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 }; -+ -+static const int pextp_tl_ck_parents[] = { CK_TOP_CB_CKSQ_40M, -+ CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4, -+ CK_TOP_CB_RTC_32K }; -+ -+static const int emmc_208m_parents[] = { -+ CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2, CK_TOP_CB_NET2_D4, -+ CK_TOP_CB_APLL2_196M, CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2, -+ CK_TOP_CB_MM_D6 -+}; -+ -+static const int emmc_400m_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_D2, -+ CK_TOP_CB_MM_D2, CK_TOP_CB_NET2_D2 }; -+ -+static const int csw_f26m_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_M_D8_D2 }; -+ -+static const int dramc_md32_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2, -+ CK_TOP_CB_WEDMCU_208M }; -+ -+static const int sysaxi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2 }; -+ -+static const int sysapb_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D3_D2 }; -+ -+static const int arm_db_main_parents[] = { CK_TOP_CB_CKSQ_40M, -+ CK_TOP_CB_NET2_D6 }; -+ -+static const int ap2cnn_host_parents[] = { CK_TOP_CB_CKSQ_40M, -+ CK_TOP_NET1_D8_D4 }; -+ -+static const int netsys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D2 }; -+ -+static const int netsys_500m_parents[] = { CK_TOP_CB_CKSQ_40M, -+ CK_TOP_CB_NET1_D5 }; -+ -+static const int netsys_mcu_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_720M, -+ CK_TOP_CB_NET1_D4, CK_TOP_CB_NET1_D5, -+ CK_TOP_CB_M_416M }; -+ -+static const int netsys_2x_parents[] = { CK_TOP_CB_CKSQ_40M, -+ CK_TOP_CB_NET2_800M, -+ CK_TOP_CB_MM_720M }; -+ -+static const int sgm_325m_parents[] = { CK_TOP_CB_CKSQ_40M, -+ CK_TOP_CB_SGM_325M }; -+ -+static const int sgm_reg_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_D4 }; -+ -+static const int eip97b_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D5, -+ CK_TOP_CB_M_416M, CK_TOP_CB_MM_D2, -+ CK_TOP_NET1_D5_D2 }; -+ -+static const int aud_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M }; -+ -+static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4 }; -+ -+static const int aud_l_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M, -+ CK_TOP_M_D8_D2 }; -+ -+static const int a_tuner_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4, -+ CK_TOP_M_D8_D2 }; -+ -+static const int u2u3_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D8_D2 }; -+ -+static const int u2u3_sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4 }; -+ -+static const int usb_frmcnt_parents[] = { CK_TOP_CB_CKSQ_40M, -+ CK_TOP_CB_MM_D3_D5 }; -+ -+#define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ -+ _shift, _width, _gate, _upd_ofs, _upd) \ -+ { \ -+ .id = _id, .mux_reg = _mux_ofs, .mux_set_reg = _mux_set_ofs, \ -+ .mux_clr_reg = _mux_clr_ofs, .upd_reg = _upd_ofs, \ -+ .upd_shift = _upd, .mux_shift = _shift, \ -+ .mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs, \ -+ .gate_shift = _gate, .parent = _parents, \ -+ .num_parents = ARRAY_SIZE(_parents), \ -+ .flags = CLK_MUX_SETCLR_UPD, \ -+ } -+ -+/* TOPCKGEN MUX_GATE */ -+static const struct mtk_composite top_muxes[] = { -+ TOP_MUX(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x0, 0x4, 0x8, 0, -+ 3, 7, 0x1c0, 0), -+ TOP_MUX(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x0, 0x4, 0x8, -+ 8, 3, 15, 0x1c0, 1), -+ TOP_MUX(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0, 0x4, 0x8, 16, 3, -+ 23, 0x1c0, 2), -+ TOP_MUX(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x0, 0x4, 0x8, -+ 24, 3, 31, 0x1c0, 3), -+ TOP_MUX(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x10, 0x14, 0x18, 0, -+ 2, 7, 0x1c0, 4), -+ TOP_MUX(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x10, 0x14, 0x18, 8, 3, -+ 15, 0x1c0, 5), -+ TOP_MUX(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x10, 0x14, 0x18, 16, 2, -+ 23, 0x1c0, 6), -+ TOP_MUX(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents, -+ 0x10, 0x14, 0x18, 24, 2, 31, 0x1c0, 7), -+ TOP_MUX(CK_TOP_EMMC_208M_SEL, "emmc_208m_sel", emmc_208m_parents, 0x20, -+ 0x24, 0x28, 0, 3, 7, 0x1c0, 8), -+ TOP_MUX(CK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x20, -+ 0x24, 0x28, 8, 2, 15, 0x1c0, 9), -+ TOP_MUX(CK_TOP_F26M_SEL, "csw_f26m_sel", csw_f26m_parents, 0x20, 0x24, -+ 0x28, 16, 1, 23, 0x1c0, 10), -+ TOP_MUX(CK_TOP_DRAMC_SEL, "dramc_sel", csw_f26m_parents, 0x20, 0x24, -+ 0x28, 24, 1, 31, 0x1c0, 11), -+ TOP_MUX(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents, -+ 0x30, 0x34, 0x38, 0, 2, 7, 0x1c0, 12), -+ TOP_MUX(CK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, 0x30, 0x34, -+ 0x38, 8, 1, 15, 0x1c0, 13), -+ TOP_MUX(CK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x30, 0x34, -+ 0x38, 16, 1, 23, 0x1c0, 14), -+ TOP_MUX(CK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", arm_db_main_parents, -+ 0x30, 0x34, 0x38, 24, 1, 31, 0x1c0, 15), -+ TOP_MUX(CK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", ap2cnn_host_parents, -+ 0x40, 0x44, 0x48, 0, 1, 7, 0x1c0, 16), -+ TOP_MUX(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x40, 0x44, -+ 0x48, 8, 1, 15, 0x1c0, 17), -+ TOP_MUX(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents, -+ 0x40, 0x44, 0x48, 16, 1, 23, 0x1c0, 18), -+ TOP_MUX(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents, -+ 0x40, 0x44, 0x48, 24, 3, 31, 0x1c0, 19), -+ TOP_MUX(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x50, -+ 0x54, 0x58, 0, 2, 7, 0x1c0, 20), -+ TOP_MUX(CK_TOP_SGM_325M_SEL, "sgm_325m_sel", sgm_325m_parents, 0x50, -+ 0x54, 0x58, 8, 1, 15, 0x1c0, 21), -+ TOP_MUX(CK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, 0x50, 0x54, -+ 0x58, 16, 1, 23, 0x1c0, 22), -+ TOP_MUX(CK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents, 0x50, 0x54, -+ 0x58, 24, 3, 31, 0x1c0, 23), -+ TOP_MUX(CK_TOP_USB3_PHY_SEL, "usb3_phy_sel", csw_f26m_parents, 0x60, -+ 0x64, 0x68, 0, 1, 7, 0x1c0, 24), -+ TOP_MUX(CK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x60, 0x64, 0x68, 8, 1, -+ 15, 0x1c0, 25), -+ TOP_MUX(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x60, 0x64, 0x68, -+ 16, 1, 23, 0x1c0, 26), -+ TOP_MUX(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x60, 0x64, 0x68, -+ 24, 2, 31, 0x1c0, 27), -+ TOP_MUX(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a_tuner_parents, 0x70, 0x74, -+ 0x78, 0, 2, 7, 0x1c0, 28), -+ TOP_MUX(CK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x70, 0x74, 0x78, 8, -+ 1, 15, 0x1c0, 29), -+ TOP_MUX(CK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", u2u3_sys_parents, 0x70, -+ 0x74, 0x78, 16, 1, 23, 0x1c0, 30), -+ TOP_MUX(CK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", u2u3_sys_parents, 0x70, -+ 0x74, 0x78, 24, 1, 31, 0x1c4, 0), -+ TOP_MUX(CK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents, -+ 0x80, 0x84, 0x88, 0, 1, 7, 0x1c4, 1), -+}; -+ -+/* INFRA FIXED DIV */ -+static const struct mtk_fixed_factor infra_fixed_divs[] = { -+ TOP_FACTOR(CK_INFRA_CK_F26M, "infra_ck_f26m", CK_TOP_F26M_SEL, 1, 1), -+ TOP_FACTOR(CK_INFRA_UART, "infra_uart", CK_TOP_UART_SEL, 1, 1), -+ TOP_FACTOR(CK_INFRA_ISPI0, "infra_ispi0", CK_TOP_SPI_SEL, 1, 1), -+ TOP_FACTOR(CK_INFRA_I2C, "infra_i2c", CK_TOP_I2C_SEL, 1, 1), -+ TOP_FACTOR(CK_INFRA_ISPI1, "infra_ispi1", CK_TOP_SPIM_MST_SEL, 1, 1), -+ TOP_FACTOR(CK_INFRA_PWM, "infra_pwm", CK_TOP_PWM_SEL, 1, 1), -+ TOP_FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", CK_TOP_SYSAXI_SEL, 1, 2), -+ TOP_FACTOR(CK_INFRA_CK_F32K, "infra_ck_f32k", CK_TOP_CB_RTC_32P7K, 1, -+ 1), -+ TOP_FACTOR(CK_INFRA_PCIE_CK, "infra_pcie", CK_TOP_PEXTP_TL_SEL, 1, 1), -+ INFRA_FACTOR(CK_INFRA_PWM_BCK, "infra_pwm_bck", CK_INFRA_PWM_BSEL, 1, -+ 1), -+ INFRA_FACTOR(CK_INFRA_PWM_CK1, "infra_pwm_ck1", CK_INFRA_PWM1_SEL, 1, -+ 1), -+ INFRA_FACTOR(CK_INFRA_PWM_CK2, "infra_pwm_ck2", CK_INFRA_PWM2_SEL, 1, -+ 1), -+ TOP_FACTOR(CK_INFRA_133M_HCK, "infra_133m_hck", CK_TOP_SYSAXI, 1, 1), -+ INFRA_FACTOR(CK_INFRA_66M_PHCK, "infra_66m_phck", CK_INFRA_133M_HCK, 1, -+ 1), -+ TOP_FACTOR(CK_INFRA_FAUD_L_CK, "infra_faud_l", CK_TOP_AUD_L, 1, 1), -+ TOP_FACTOR(CK_INFRA_FAUD_AUD_CK, "infra_faud_aud", CK_TOP_A1SYS, 1, 1), -+ TOP_FACTOR(CK_INFRA_FAUD_EG2_CK, "infra_faud_eg2", CK_TOP_A_TUNER, 1, -+ 1), -+ TOP_FACTOR(CK_INFRA_I2CS_CK, "infra_i2cs", CK_TOP_I2C_BCK, 1, 1), -+ INFRA_FACTOR(CK_INFRA_MUX_UART0, "infra_mux_uart0", CK_INFRA_UART0_SEL, -+ 1, 1), -+ INFRA_FACTOR(CK_INFRA_MUX_UART1, "infra_mux_uart1", CK_INFRA_UART1_SEL, -+ 1, 1), -+ INFRA_FACTOR(CK_INFRA_MUX_UART2, "infra_mux_uart2", CK_INFRA_UART2_SEL, -+ 1, 1), -+ TOP_FACTOR(CK_INFRA_NFI_CK, "infra_nfi", CK_TOP_NFI1X, 1, 1), -+ TOP_FACTOR(CK_INFRA_SPINFI_CK, "infra_spinfi", CK_TOP_SPINFI_BCK, 1, 1), -+ INFRA_FACTOR(CK_INFRA_MUX_SPI0, "infra_mux_spi0", CK_INFRA_SPI0_SEL, 1, -+ 1), -+ INFRA_FACTOR(CK_INFRA_MUX_SPI1, "infra_mux_spi1", CK_INFRA_SPI1_SEL, 1, -+ 1), -+ INFRA_FACTOR(CK_INFRA_MUX_SPI2, "infra_mux_spi2", CK_INFRA_SPI2_SEL, 1, -+ 1), -+ TOP_FACTOR(CK_INFRA_RTC_32K, "infra_rtc_32k", CK_TOP_CB_RTC_32K, 1, 1), -+ TOP_FACTOR(CK_INFRA_FMSDC_CK, "infra_fmsdc", CK_TOP_EMMC_400M, 1, 1), -+ TOP_FACTOR(CK_INFRA_FMSDC_HCK_CK, "infra_fmsdc_hck", CK_TOP_EMMC_208M, -+ 1, 1), -+ TOP_FACTOR(CK_INFRA_PERI_133M, "infra_peri_133m", CK_TOP_SYSAXI, 1, 1), -+ TOP_FACTOR(CK_INFRA_133M_PHCK, "infra_133m_phck", CK_TOP_SYSAXI, 1, 1), -+ TOP_FACTOR(CK_INFRA_USB_SYS_CK, "infra_usb_sys", CK_TOP_U2U3_SYS, 1, 1), -+ TOP_FACTOR(CK_INFRA_USB_CK, "infra_usb", CK_TOP_U2U3_REF, 1, 1), -+ TOP_FACTOR(CK_INFRA_USB_XHCI_CK, "infra_usb_xhci", CK_TOP_U2U3_XHCI, 1, -+ 1), -+ TOP_FACTOR(CK_INFRA_PCIE_GFMUX_TL_O_PRE, "infra_pcie_mux", -+ CK_TOP_PEXTP_TL, 1, 1), -+ TOP_FACTOR(CK_INFRA_F26M_CK0, "infra_f26m_ck0", CK_TOP_F26M, 1, 1), -+ TOP_FACTOR(CK_INFRA_133M_MCK, "infra_133m_mck", CK_TOP_SYSAXI, 1, 1), -+}; -+ -+/* INFRASYS MUX PARENTS */ -+static const int infra_uart0_parents[] = { CK_INFRA_CK_F26M, CK_INFRA_UART }; -+ -+static const int infra_spi0_parents[] = { CK_INFRA_I2C, CK_INFRA_ISPI0 }; -+ -+static const int infra_spi1_parents[] = { CK_INFRA_I2C, CK_INFRA_ISPI1 }; -+ -+static const int infra_pwm1_parents[] = { -1, -1, -1, CK_INFRA_PWM }; -+ -+static const int infra_pwm_bsel_parents[] = { -1, -1, -1, CK_INFRA_PWM }; -+ -+static const int infra_pcie_parents[] = { CK_INFRA_CK_F32K, CK_INFRA_CK_F26M, -+ CK_TOP_CB_CKSQ_40M, CK_INFRA_PCIE_CK}; -+ -+#define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \ -+ { \ -+ .id = _id, .mux_reg = (_reg) + 0x8, \ -+ .mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \ -+ .mux_shift = _shift, .mux_mask = BIT(_width) - 1, \ -+ .parent = _parents, .num_parents = ARRAY_SIZE(_parents), \ -+ .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_INFRASYS, \ -+ } -+ -+/* INFRA MUX */ -+static const struct mtk_composite infra_muxes[] = { -+ INFRA_MUX(CK_INFRA_UART0_SEL, "infra_uart0_sel", infra_uart0_parents, -+ 0x10, 0, 1), -+ INFRA_MUX(CK_INFRA_UART1_SEL, "infra_uart1_sel", infra_uart0_parents, -+ 0x10, 1, 1), -+ INFRA_MUX(CK_INFRA_UART2_SEL, "infra_uart2_sel", infra_uart0_parents, -+ 0x10, 2, 1), -+ INFRA_MUX(CK_INFRA_SPI0_SEL, "infra_spi0_sel", infra_spi0_parents, 0x10, -+ 4, 1), -+ INFRA_MUX(CK_INFRA_SPI1_SEL, "infra_spi1_sel", infra_spi1_parents, 0x10, -+ 5, 1), -+ INFRA_MUX(CK_INFRA_SPI2_SEL, "infra_spi2_sel", infra_spi0_parents, 0x10, -+ 6, 1), -+ INFRA_MUX(CK_INFRA_PWM1_SEL, "infra_pwm1_sel", infra_pwm1_parents, 0x10, -+ 9, 2), -+ INFRA_MUX(CK_INFRA_PWM2_SEL, "infra_pwm2_sel", infra_pwm1_parents, 0x10, -+ 11, 2), -+ INFRA_MUX(CK_INFRA_PWM_BSEL, "infra_pwm_bsel", infra_pwm_bsel_parents, -+ 0x10, 13, 2), -+ INFRA_MUX(CK_INFRA_PCIE_SEL, "infra_pcie_sel", infra_pcie_parents, 0x20, -+ 0, 2), -+}; -+ -+static const struct mtk_gate_regs infra_0_cg_regs = { -+ .set_ofs = 0x40, -+ .clr_ofs = 0x44, -+ .sta_ofs = 0x48, -+}; -+ -+static const struct mtk_gate_regs infra_1_cg_regs = { -+ .set_ofs = 0x50, -+ .clr_ofs = 0x54, -+ .sta_ofs = 0x58, -+}; -+ -+static const struct mtk_gate_regs infra_2_cg_regs = { -+ .set_ofs = 0x60, -+ .clr_ofs = 0x64, -+ .sta_ofs = 0x68, -+}; -+ -+#define GATE_INFRA0(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, .parent = _parent, .regs = &infra_0_cg_regs, \ -+ .shift = _shift, \ -+ .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \ -+ } -+ -+#define GATE_INFRA1(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, .parent = _parent, .regs = &infra_1_cg_regs, \ -+ .shift = _shift, \ -+ .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \ -+ } -+ -+#define GATE_INFRA2(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, .parent = _parent, .regs = &infra_2_cg_regs, \ -+ .shift = _shift, \ -+ .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \ -+ } -+ -+/* INFRA GATE */ -+static const struct mtk_gate infracfg_ao_gates[] = { -+ GATE_INFRA0(CK_INFRA_GPT_STA, "infra_gpt_sta", CK_INFRA_66M_MCK, 0), -+ GATE_INFRA0(CK_INFRA_PWM_HCK, "infra_pwm_hck", CK_INFRA_66M_MCK, 1), -+ GATE_INFRA0(CK_INFRA_PWM_STA, "infra_pwm_sta", CK_INFRA_PWM_BCK, 2), -+ GATE_INFRA0(CK_INFRA_PWM1_CK, "infra_pwm1", CK_INFRA_PWM_CK1, 3), -+ GATE_INFRA0(CK_INFRA_PWM2_CK, "infra_pwm2", CK_INFRA_PWM_CK2, 4), -+ GATE_INFRA0(CK_INFRA_CQ_DMA_CK, "infra_cq_dma", CK_INFRA_133M_HCK, 6), -+ GATE_INFRA0(CK_INFRA_AUD_BUS_CK, "infra_aud_bus", CK_INFRA_66M_PHCK, 8), -+ GATE_INFRA0(CK_INFRA_AUD_26M_CK, "infra_aud_26m", CK_INFRA_CK_F26M, 9), -+ GATE_INFRA0(CK_INFRA_AUD_L_CK, "infra_aud_l", CK_INFRA_FAUD_L_CK, 10), -+ GATE_INFRA0(CK_INFRA_AUD_AUD_CK, "infra_aud_aud", CK_INFRA_FAUD_AUD_CK, -+ 11), -+ GATE_INFRA0(CK_INFRA_AUD_EG2_CK, "infra_aud_eg2", CK_INFRA_FAUD_EG2_CK, -+ 13), -+ GATE_INFRA0(CK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", CK_INFRA_CK_F26M, -+ 14), -+ GATE_INFRA0(CK_INFRA_DBG_CK, "infra_dbg", CK_INFRA_66M_MCK, 15), -+ GATE_INFRA0(CK_INFRA_AP_DMA_CK, "infra_ap_dma", CK_INFRA_66M_MCK, 16), -+ GATE_INFRA0(CK_INFRA_SEJ_CK, "infra_sej", CK_INFRA_66M_MCK, 24), -+ GATE_INFRA0(CK_INFRA_SEJ_13M_CK, "infra_sej_13m", CK_INFRA_CK_F26M, 25), -+ GATE_INFRA1(CK_INFRA_THERM_CK, "infra_therm", CK_INFRA_CK_F26M, 0), -+ GATE_INFRA1(CK_INFRA_I2CO_CK, "infra_i2co", CK_INFRA_I2CS_CK, 1), -+ GATE_INFRA1(CK_INFRA_UART0_CK, "infra_uart0", CK_INFRA_MUX_UART0, 2), -+ GATE_INFRA1(CK_INFRA_UART1_CK, "infra_uart1", CK_INFRA_MUX_UART1, 3), -+ GATE_INFRA1(CK_INFRA_UART2_CK, "infra_uart2", CK_INFRA_MUX_UART2, 4), -+ GATE_INFRA1(CK_INFRA_SPI2_CK, "infra_spi2", CK_INFRA_MUX_SPI2, 6), -+ GATE_INFRA1(CK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", CK_INFRA_66M_MCK, -+ 7), -+ GATE_INFRA1(CK_INFRA_NFI1_CK, "infra_nfi1", CK_INFRA_NFI_CK, 8), -+ GATE_INFRA1(CK_INFRA_SPINFI1_CK, "infra_spinfi1", CK_INFRA_SPINFI_CK, -+ 9), -+ GATE_INFRA1(CK_INFRA_NFI_HCK_CK, "infra_nfi_hck", CK_INFRA_66M_MCK, 10), -+ GATE_INFRA1(CK_INFRA_SPI0_CK, "infra_spi0", CK_INFRA_MUX_SPI0, 11), -+ GATE_INFRA1(CK_INFRA_SPI1_CK, "infra_spi1", CK_INFRA_MUX_SPI1, 12), -+ GATE_INFRA1(CK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", CK_INFRA_66M_MCK, -+ 13), -+ GATE_INFRA1(CK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", CK_INFRA_66M_MCK, -+ 14), -+ GATE_INFRA1(CK_INFRA_FRTC_CK, "infra_frtc", CK_INFRA_RTC_32K, 15), -+ GATE_INFRA1(CK_INFRA_MSDC_CK, "infra_msdc", CK_INFRA_FMSDC_CK, 16), -+ GATE_INFRA1(CK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", -+ CK_INFRA_FMSDC_HCK_CK, 17), -+ GATE_INFRA1(CK_INFRA_MSDC_133M_CK, "infra_msdc_133m", -+ CK_INFRA_PERI_133M, 18), -+ GATE_INFRA1(CK_INFRA_MSDC_66M_CK, "infra_msdc_66m", CK_INFRA_66M_PHCK, -+ 19), -+ GATE_INFRA1(CK_INFRA_ADC_26M_CK, "infra_adc_26m", CK_TOP_F26M, 20), -+ GATE_INFRA1(CK_INFRA_ADC_FRC_CK, "infra_adc_frc", CK_TOP_F26M, 21), -+ GATE_INFRA1(CK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", CK_INFRA_NFI_CK, -+ 23), -+ GATE_INFRA1(CK_INFRA_I2C_MCK_CK, "infra_i2c_mck", CK_INFRA_133M_MCK, -+ 25), -+ GATE_INFRA1(CK_INFRA_I2C_PCK_CK, "infra_i2c_pck", CK_INFRA_66M_MCK, 26), -+ GATE_INFRA2(CK_INFRA_IUSB_133_CK, "infra_iusb_133", CK_INFRA_133M_PHCK, -+ 0), -+ GATE_INFRA2(CK_INFRA_IUSB_66M_CK, "infra_iusb_66m", CK_INFRA_66M_PHCK, -+ 1), -+ GATE_INFRA2(CK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", CK_INFRA_USB_SYS_CK, -+ 2), -+ GATE_INFRA2(CK_INFRA_IUSB_CK, "infra_iusb", CK_INFRA_USB_CK, 3), -+ GATE_INFRA2(CK_INFRA_IPCIE_CK, "infra_ipcie", -+ CK_INFRA_PCIE_GFMUX_TL_O_PRE, 12), -+ GATE_INFRA2(CK_INFRA_IPCIER_CK, "infra_ipcier", CK_INFRA_F26M_CK0, 14), -+ GATE_INFRA2(CK_INFRA_IPCIEB_CK, "infra_ipcieb", CK_INFRA_133M_PHCK, 15), -+}; -+ -+static const struct mtk_clk_tree mt7981_fixed_pll_clk_tree = { -+ .fdivs_offs = CLK_APMIXED_NR_CLK, -+ .xtal_rate = 40 * MHZ, -+ .fclks = fixed_pll_clks, -+}; -+ -+static const struct mtk_clk_tree mt7981_topckgen_clk_tree = { -+ .fdivs_offs = CK_TOP_CB_M_416M, -+ .muxes_offs = CK_TOP_NFI1X_SEL, -+ .fclks = top_fixed_clks, -+ .fdivs = top_fixed_divs, -+ .muxes = top_muxes, -+ .flags = CLK_BYPASS_XTAL, -+}; -+ -+static const struct mtk_clk_tree mt7981_infracfg_clk_tree = { -+ .fdivs_offs = CK_INFRA_CK_F26M, -+ .muxes_offs = CK_INFRA_UART0_SEL, -+ .fdivs = infra_fixed_divs, -+ .muxes = infra_muxes, -+}; -+ -+static const struct udevice_id mt7981_fixed_pll_compat[] = { -+ { .compatible = "mediatek,mt7981-fixed-plls" }, -+ {} -+}; -+ -+static const struct udevice_id mt7981_topckgen_compat[] = { -+ { .compatible = "mediatek,mt7981-topckgen" }, -+ {} -+}; -+ -+static int mt7981_fixed_pll_probe(struct udevice *dev) -+{ -+ return mtk_common_clk_init(dev, &mt7981_fixed_pll_clk_tree); -+} -+ -+static int mt7981_topckgen_probe(struct udevice *dev) -+{ -+ struct mtk_clk_priv *priv = dev_get_priv(dev); -+ -+ priv->base = dev_read_addr_ptr(dev); -+ writel(MT7981_CLK_PDN_EN_WRITE, priv->base + MT7981_CLK_PDN); -+ -+ return mtk_common_clk_init(dev, &mt7981_topckgen_clk_tree); -+} -+ -+U_BOOT_DRIVER(mtk_clk_apmixedsys) = { -+ .name = "mt7981-clock-fixed-pll", -+ .id = UCLASS_CLK, -+ .of_match = mt7981_fixed_pll_compat, -+ .probe = mt7981_fixed_pll_probe, -+ .priv_auto = sizeof(struct mtk_clk_priv), -+ .ops = &mtk_clk_topckgen_ops, -+ .flags = DM_FLAG_PRE_RELOC, -+}; -+ -+U_BOOT_DRIVER(mtk_clk_topckgen) = { -+ .name = "mt7981-clock-topckgen", -+ .id = UCLASS_CLK, -+ .of_match = mt7981_topckgen_compat, -+ .probe = mt7981_topckgen_probe, -+ .priv_auto = sizeof(struct mtk_clk_priv), -+ .ops = &mtk_clk_topckgen_ops, -+ .flags = DM_FLAG_PRE_RELOC, -+}; -+ -+static const struct udevice_id mt7981_infracfg_compat[] = { -+ { .compatible = "mediatek,mt7981-infracfg" }, -+ {} -+}; -+ -+static const struct udevice_id mt7981_infracfg_ao_compat[] = { -+ { .compatible = "mediatek,mt7981-infracfg_ao" }, -+ {} -+}; -+ -+static int mt7981_infracfg_probe(struct udevice *dev) -+{ -+ return mtk_common_clk_init(dev, &mt7981_infracfg_clk_tree); -+} -+ -+static int mt7981_infracfg_ao_probe(struct udevice *dev) -+{ -+ return mtk_common_clk_gate_init(dev, &mt7981_infracfg_clk_tree, -+ infracfg_ao_gates); -+} -+ -+U_BOOT_DRIVER(mtk_clk_infracfg) = { -+ .name = "mt7981-clock-infracfg", -+ .id = UCLASS_CLK, -+ .of_match = mt7981_infracfg_compat, -+ .probe = mt7981_infracfg_probe, -+ .priv_auto = sizeof(struct mtk_clk_priv), -+ .ops = &mtk_clk_infrasys_ops, -+ .flags = DM_FLAG_PRE_RELOC, -+}; -+ -+U_BOOT_DRIVER(mtk_clk_infracfg_ao) = { -+ .name = "mt7981-clock-infracfg-ao", -+ .id = UCLASS_CLK, -+ .of_match = mt7981_infracfg_ao_compat, -+ .probe = mt7981_infracfg_ao_probe, -+ .priv_auto = sizeof(struct mtk_cg_priv), -+ .ops = &mtk_clk_gate_ops, -+ .flags = DM_FLAG_PRE_RELOC, -+}; -+ -+/* ethsys */ -+static const struct mtk_gate_regs eth_cg_regs = { -+ .set_ofs = 0x30, -+ .clr_ofs = 0x30, -+ .sta_ofs = 0x30, -+}; -+ -+#define GATE_ETH(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, .parent = _parent, .regs = ð_cg_regs, \ -+ .shift = _shift, \ -+ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ -+ } -+ -+static const struct mtk_gate eth_cgs[] = { -+ GATE_ETH(CK_ETH_FE_EN, "eth_fe_en", CK_TOP_NETSYS_2X, 6), -+ GATE_ETH(CK_ETH_GP2_EN, "eth_gp2_en", CK_TOP_SGM_325M, 7), -+ GATE_ETH(CK_ETH_GP1_EN, "eth_gp1_en", CK_TOP_SGM_325M, 8), -+ GATE_ETH(CK_ETH_WOCPU0_EN, "eth_wocpu0_en", CK_TOP_NETSYS_WED_MCU, 15), -+}; -+ -+static int mt7981_ethsys_probe(struct udevice *dev) -+{ -+ return mtk_common_clk_gate_init(dev, &mt7981_topckgen_clk_tree, -+ eth_cgs); -+} -+ -+static int mt7981_ethsys_bind(struct udevice *dev) -+{ -+ int ret = 0; -+ -+ if (CONFIG_IS_ENABLED(RESET_MEDIATEK)) { -+ ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1); -+ if (ret) -+ debug("Warning: failed to bind reset controller\n"); -+ } -+ -+ return ret; -+} -+ -+static const struct udevice_id mt7981_ethsys_compat[] = { -+ { .compatible = "mediatek,mt7981-ethsys", }, -+ {} -+}; -+ -+U_BOOT_DRIVER(mtk_clk_ethsys) = { -+ .name = "mt7981-clock-ethsys", -+ .id = UCLASS_CLK, -+ .of_match = mt7981_ethsys_compat, -+ .probe = mt7981_ethsys_probe, -+ .bind = mt7981_ethsys_bind, -+ .priv_auto = sizeof(struct mtk_cg_priv), -+ .ops = &mtk_clk_gate_ops, -+}; ---- /dev/null -+++ b/include/dt-bindings/clock/mt7981-clk.h -@@ -0,0 +1,267 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Copyright (C) 2022 MediaTek Inc. All rights reserved. -+ * -+ * Author: Sam Shih -+ */ -+ -+#ifndef _DT_BINDINGS_CLK_MT7981_H -+#define _DT_BINDINGS_CLK_MT7981_H -+ -+/* INFRACFG */ -+ -+#define CK_INFRA_CK_F26M 0 -+#define CK_INFRA_UART 1 -+#define CK_INFRA_ISPI0 2 -+#define CK_INFRA_I2C 3 -+#define CK_INFRA_ISPI1 4 -+#define CK_INFRA_PWM 5 -+#define CK_INFRA_66M_MCK 6 -+#define CK_INFRA_CK_F32K 7 -+#define CK_INFRA_PCIE_CK 8 -+#define CK_INFRA_PWM_BCK 9 -+#define CK_INFRA_PWM_CK1 10 -+#define CK_INFRA_PWM_CK2 11 -+#define CK_INFRA_133M_HCK 12 -+#define CK_INFRA_66M_PHCK 13 -+#define CK_INFRA_FAUD_L_CK 14 -+#define CK_INFRA_FAUD_AUD_CK 15 -+#define CK_INFRA_FAUD_EG2_CK 16 -+#define CK_INFRA_I2CS_CK 17 -+#define CK_INFRA_MUX_UART0 18 -+#define CK_INFRA_MUX_UART1 19 -+#define CK_INFRA_MUX_UART2 20 -+#define CK_INFRA_NFI_CK 21 -+#define CK_INFRA_SPINFI_CK 22 -+#define CK_INFRA_MUX_SPI0 23 -+#define CK_INFRA_MUX_SPI1 24 -+#define CK_INFRA_MUX_SPI2 25 -+#define CK_INFRA_RTC_32K 26 -+#define CK_INFRA_FMSDC_CK 27 -+#define CK_INFRA_FMSDC_HCK_CK 28 -+#define CK_INFRA_PERI_133M 29 -+#define CK_INFRA_133M_PHCK 30 -+#define CK_INFRA_USB_SYS_CK 31 -+#define CK_INFRA_USB_CK 32 -+#define CK_INFRA_USB_XHCI_CK 33 -+#define CK_INFRA_PCIE_GFMUX_TL_O_PRE 34 -+#define CK_INFRA_F26M_CK0 35 -+#define CK_INFRA_133M_MCK 36 -+#define CLK_INFRA_NR_CLK 37 -+ -+/* TOPCKGEN */ -+ -+#define CK_TOP_CB_CKSQ_40M 0 -+#define CK_TOP_CB_M_416M 1 -+#define CK_TOP_CB_M_D2 2 -+#define CK_TOP_CB_M_D3 3 -+#define CK_TOP_M_D3_D2 4 -+#define CK_TOP_CB_M_D4 5 -+#define CK_TOP_CB_M_D8 6 -+#define CK_TOP_M_D8_D2 7 -+#define CK_TOP_CB_MM_720M 8 -+#define CK_TOP_CB_MM_D2 9 -+#define CK_TOP_CB_MM_D3 10 -+#define CK_TOP_CB_MM_D3_D5 11 -+#define CK_TOP_CB_MM_D4 12 -+#define CK_TOP_CB_MM_D6 13 -+#define CK_TOP_MM_D6_D2 14 -+#define CK_TOP_CB_MM_D8 15 -+#define CK_TOP_CB_APLL2_196M 16 -+#define CK_TOP_APLL2_D2 17 -+#define CK_TOP_APLL2_D4 18 -+#define CK_TOP_NET1_2500M 19 -+#define CK_TOP_CB_NET1_D4 20 -+#define CK_TOP_CB_NET1_D5 21 -+#define CK_TOP_NET1_D5_D2 22 -+#define CK_TOP_NET1_D5_D4 23 -+#define CK_TOP_CB_NET1_D8 24 -+#define CK_TOP_NET1_D8_D2 25 -+#define CK_TOP_NET1_D8_D4 26 -+#define CK_TOP_CB_NET2_800M 27 -+#define CK_TOP_CB_NET2_D2 28 -+#define CK_TOP_CB_NET2_D4 29 -+#define CK_TOP_NET2_D4_D2 30 -+#define CK_TOP_NET2_D4_D4 31 -+#define CK_TOP_CB_NET2_D6 32 -+#define CK_TOP_CB_WEDMCU_208M 33 -+#define CK_TOP_CB_SGM_325M 34 -+#define CK_TOP_CKSQ_40M_D2 35 -+#define CK_TOP_CB_RTC_32K 36 -+#define CK_TOP_CB_RTC_32P7K 37 -+#define CK_TOP_USB_TX250M 38 -+#define CK_TOP_FAUD 39 -+#define CK_TOP_NFI1X 40 -+#define CK_TOP_USB_EQ_RX250M 41 -+#define CK_TOP_USB_CDR_CK 42 -+#define CK_TOP_USB_LN0_CK 43 -+#define CK_TOP_SPINFI_BCK 44 -+#define CK_TOP_SPI 45 -+#define CK_TOP_SPIM_MST 46 -+#define CK_TOP_UART_BCK 47 -+#define CK_TOP_PWM_BCK 48 -+#define CK_TOP_I2C_BCK 49 -+#define CK_TOP_PEXTP_TL 50 -+#define CK_TOP_EMMC_208M 51 -+#define CK_TOP_EMMC_400M 52 -+#define CK_TOP_DRAMC_REF 53 -+#define CK_TOP_DRAMC_MD32 54 -+#define CK_TOP_SYSAXI 55 -+#define CK_TOP_SYSAPB 56 -+#define CK_TOP_ARM_DB_MAIN 57 -+#define CK_TOP_AP2CNN_HOST 58 -+#define CK_TOP_NETSYS 59 -+#define CK_TOP_NETSYS_500M 60 -+#define CK_TOP_NETSYS_WED_MCU 61 -+#define CK_TOP_NETSYS_2X 62 -+#define CK_TOP_SGM_325M 63 -+#define CK_TOP_SGM_REG 64 -+#define CK_TOP_F26M 65 -+#define CK_TOP_EIP97B 66 -+#define CK_TOP_USB3_PHY 67 -+#define CK_TOP_AUD 68 -+#define CK_TOP_A1SYS 69 -+#define CK_TOP_AUD_L 70 -+#define CK_TOP_A_TUNER 71 -+#define CK_TOP_U2U3_REF 72 -+#define CK_TOP_U2U3_SYS 73 -+#define CK_TOP_U2U3_XHCI 74 -+#define CK_TOP_USB_FRMCNT 75 -+#define CK_TOP_NFI1X_SEL 76 -+#define CK_TOP_SPINFI_SEL 77 -+#define CK_TOP_SPI_SEL 78 -+#define CK_TOP_SPIM_MST_SEL 79 -+#define CK_TOP_UART_SEL 80 -+#define CK_TOP_PWM_SEL 81 -+#define CK_TOP_I2C_SEL 82 -+#define CK_TOP_PEXTP_TL_SEL 83 -+#define CK_TOP_EMMC_208M_SEL 84 -+#define CK_TOP_EMMC_400M_SEL 85 -+#define CK_TOP_F26M_SEL 86 -+#define CK_TOP_DRAMC_SEL 87 -+#define CK_TOP_DRAMC_MD32_SEL 88 -+#define CK_TOP_SYSAXI_SEL 89 -+#define CK_TOP_SYSAPB_SEL 90 -+#define CK_TOP_ARM_DB_MAIN_SEL 91 -+#define CK_TOP_AP2CNN_HOST_SEL 92 -+#define CK_TOP_NETSYS_SEL 93 -+#define CK_TOP_NETSYS_500M_SEL 94 -+#define CK_TOP_NETSYS_MCU_SEL 95 -+#define CK_TOP_NETSYS_2X_SEL 96 -+#define CK_TOP_SGM_325M_SEL 97 -+#define CK_TOP_SGM_REG_SEL 98 -+#define CK_TOP_EIP97B_SEL 99 -+#define CK_TOP_USB3_PHY_SEL 100 -+#define CK_TOP_AUD_SEL 101 -+#define CK_TOP_A1SYS_SEL 102 -+#define CK_TOP_AUD_L_SEL 103 -+#define CK_TOP_A_TUNER_SEL 104 -+#define CK_TOP_U2U3_SEL 105 -+#define CK_TOP_U2U3_SYS_SEL 106 -+#define CK_TOP_U2U3_XHCI_SEL 107 -+#define CK_TOP_USB_FRMCNT_SEL 108 -+#define CLK_TOP_NR_CLK 109 -+ -+/* -+ * INFRACFG_AO -+ * clock muxes need to be append to infracfg domain, and clock gates -+ * need to be keep in infracgh_ao domain -+ */ -+#define INFRACFG_AO_OFFSET 10 -+ -+#define CK_INFRA_UART0_SEL (0 + CLK_INFRA_NR_CLK) -+#define CK_INFRA_UART1_SEL (1 + CLK_INFRA_NR_CLK) -+#define CK_INFRA_UART2_SEL (2 + CLK_INFRA_NR_CLK) -+#define CK_INFRA_SPI0_SEL (3 + CLK_INFRA_NR_CLK) -+#define CK_INFRA_SPI1_SEL (4 + CLK_INFRA_NR_CLK) -+#define CK_INFRA_SPI2_SEL (5 + CLK_INFRA_NR_CLK) -+#define CK_INFRA_PWM1_SEL (6 + CLK_INFRA_NR_CLK) -+#define CK_INFRA_PWM2_SEL (7 + CLK_INFRA_NR_CLK) -+#define CK_INFRA_PWM_BSEL (8 + CLK_INFRA_NR_CLK) -+#define CK_INFRA_PCIE_SEL (9 + CLK_INFRA_NR_CLK) -+#define CK_INFRA_GPT_STA (10 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_PWM_HCK (11 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_PWM_STA (12 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_PWM1_CK (13 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_PWM2_CK (14 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_CQ_DMA_CK (15 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_AUD_BUS_CK (16 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_AUD_26M_CK (17 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_AUD_L_CK (18 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_AUD_AUD_CK (19 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_AUD_EG2_CK (20 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_DRAMC_26M_CK (21 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_DBG_CK (22 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_AP_DMA_CK (23 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_SEJ_CK (24 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_SEJ_13M_CK (25 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_THERM_CK (26 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_I2CO_CK (27 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_UART0_CK (28 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_UART1_CK (29 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_UART2_CK (30 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_SPI2_CK (31 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_SPI2_HCK_CK (32 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_NFI1_CK (33 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_SPINFI1_CK (34 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_NFI_HCK_CK (35 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_SPI0_CK (36 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_SPI1_CK (37 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_SPI0_HCK_CK (38 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_SPI1_HCK_CK (39 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_FRTC_CK (40 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_MSDC_CK (41 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_MSDC_HCK_CK (42 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_MSDC_133M_CK (43 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_MSDC_66M_CK (44 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_ADC_26M_CK (45 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_ADC_FRC_CK (46 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_FBIST2FPC_CK (47 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_I2C_MCK_CK (48 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_I2C_PCK_CK (49 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_IUSB_133_CK (50 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_IUSB_66M_CK (51 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_IUSB_SYS_CK (52 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_IUSB_CK (53 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_IPCIE_CK (54 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_IPCIER_CK (55 - INFRACFG_AO_OFFSET) -+#define CK_INFRA_IPCIEB_CK (56 - INFRACFG_AO_OFFSET) -+#define CLK_INFRA_AO_NR_CLK (57 - INFRACFG_AO_OFFSET) -+ -+/* APMIXEDSYS */ -+ -+#define CK_APMIXED_ARMPLL 0 -+#define CK_APMIXED_NET2PLL 1 -+#define CK_APMIXED_MMPLL 2 -+#define CK_APMIXED_SGMPLL 3 -+#define CK_APMIXED_WEDMCUPLL 4 -+#define CK_APMIXED_NET1PLL 5 -+#define CK_APMIXED_MPLL 6 -+#define CK_APMIXED_APLL2 7 -+#define CLK_APMIXED_NR_CLK 8 -+ -+/* SGMIISYS_0 */ -+ -+#define CK_SGM0_TX_EN 0 -+#define CK_SGM0_RX_EN 1 -+#define CK_SGM0_CK0_EN 2 -+#define CK_SGM0_CDR_CK0_EN 3 -+#define CLK_SGMII0_NR_CLK 4 -+ -+/* SGMIISYS_1 */ -+ -+#define CK_SGM1_TX_EN 0 -+#define CK_SGM1_RX_EN 1 -+#define CK_SGM1_CK1_EN 2 -+#define CK_SGM1_CDR_CK1_EN 3 -+#define CLK_SGMII1_NR_CLK 4 -+ -+/* ETHSYS */ -+ -+#define CK_ETH_FE_EN 0 -+#define CK_ETH_GP2_EN 1 -+#define CK_ETH_GP1_EN 2 -+#define CK_ETH_WOCPU0_EN 3 -+#define CLK_ETH_NR_CLK 4 -+ -+#endif /* _DT_BINDINGS_CLK_MT7981_H */ diff --git a/package/boot/uboot-mediatek/patches/002-0028-cpu-add-basic-cpu-driver-for-MediaTek-ARM-chips.patch b/package/boot/uboot-mediatek/patches/002-0028-cpu-add-basic-cpu-driver-for-MediaTek-ARM-chips.patch deleted file mode 100644 index 1f4d486d389..00000000000 --- a/package/boot/uboot-mediatek/patches/002-0028-cpu-add-basic-cpu-driver-for-MediaTek-ARM-chips.patch +++ /dev/null @@ -1,133 +0,0 @@ -From e3c707d23a3a5bc1ba9b8c03731a32c3714ae56a Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 31 Aug 2022 19:05:20 +0800 -Subject: [PATCH 28/32] cpu: add basic cpu driver for MediaTek ARM chips - -Add basic CPU driver used to retrieve CPU model information. - -Signed-off-by: Weijie Gao ---- - drivers/cpu/Makefile | 1 + - drivers/cpu/mtk_cpu.c | 106 ++++++++++++++++++++++++++++++++++++++++++ - 2 files changed, 107 insertions(+) - create mode 100644 drivers/cpu/mtk_cpu.c - ---- a/drivers/cpu/Makefile -+++ b/drivers/cpu/Makefile -@@ -9,6 +9,7 @@ obj-$(CONFIG_CPU) += cpu-uclass.o - obj-$(CONFIG_ARCH_BMIPS) += bmips_cpu.o - obj-$(CONFIG_ARCH_IMX8) += imx8_cpu.o - obj-$(CONFIG_ARCH_AT91) += at91_cpu.o -+obj-$(CONFIG_ARCH_MEDIATEK) += mtk_cpu.o - obj-$(CONFIG_CPU_MPC83XX) += mpc83xx_cpu.o - obj-$(CONFIG_CPU_RISCV) += riscv_cpu.o - obj-$(CONFIG_CPU_MICROBLAZE) += microblaze_cpu.o ---- /dev/null -+++ b/drivers/cpu/mtk_cpu.c -@@ -0,0 +1,106 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (C) 2022 MediaTek Inc. All rights reserved. -+ * -+ * Author: Weijie Gao -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+DECLARE_GLOBAL_DATA_PTR; -+ -+struct mtk_cpu_plat { -+ void __iomem *hwver_base; -+}; -+ -+static int mtk_cpu_get_desc(const struct udevice *dev, char *buf, int size) -+{ -+ struct mtk_cpu_plat *plat = dev_get_plat(dev); -+ -+ snprintf(buf, size, "MediaTek MT%04X", readl(plat->hwver_base)); -+ -+ return 0; -+} -+ -+static int mtk_cpu_get_count(const struct udevice *dev) -+{ -+ return 1; -+} -+ -+static int mtk_cpu_get_vendor(const struct udevice *dev, char *buf, int size) -+{ -+ snprintf(buf, size, "MediaTek"); -+ -+ return 0; -+} -+ -+static int mtk_cpu_probe(struct udevice *dev) -+{ -+ struct mtk_cpu_plat *plat = dev_get_plat(dev); -+ const void *fdt = gd->fdt_blob, *reg; -+ int offset, parent, len, na, ns; -+ u64 addr; -+ -+ if (!fdt) -+ return -ENODEV; -+ -+ offset = fdt_path_offset(fdt, "/hwver"); -+ if (offset < 0) -+ return -ENODEV; -+ -+ parent = fdt_parent_offset(fdt, offset); -+ if (parent < 0) -+ return -ENODEV; -+ -+ na = fdt_address_cells(fdt, parent); -+ if (na < 1) -+ return -ENODEV; -+ -+ ns = fdt_size_cells(gd->fdt_blob, parent); -+ if (ns < 0) -+ return -ENODEV; -+ -+ reg = fdt_getprop(gd->fdt_blob, offset, "reg", &len); -+ if (!reg) -+ return -ENODEV; -+ -+ if (ns) -+ addr = fdt_translate_address(fdt, offset, reg); -+ else -+ addr = fdt_read_number(reg, na); -+ -+ plat->hwver_base = map_sysmem(addr, 0); -+ if (!plat->hwver_base) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static const struct cpu_ops mtk_cpu_ops = { -+ .get_desc = mtk_cpu_get_desc, -+ .get_count = mtk_cpu_get_count, -+ .get_vendor = mtk_cpu_get_vendor, -+}; -+ -+static const struct udevice_id mtk_cpu_ids[] = { -+ { .compatible = "arm,cortex-a7" }, -+ { .compatible = "arm,cortex-a53" }, -+ { .compatible = "arm,cortex-a73" }, -+ { /* sentinel */ } -+}; -+ -+U_BOOT_DRIVER(cpu_mtk) = { -+ .name = "mtk-cpu", -+ .id = UCLASS_CPU, -+ .of_match = mtk_cpu_ids, -+ .ops = &mtk_cpu_ops, -+ .probe = mtk_cpu_probe, -+ .plat_auto = sizeof(struct mtk_cpu_plat), -+ .flags = DM_FLAG_PRE_RELOC, -+}; diff --git a/package/boot/uboot-mediatek/patches/002-0029-tools-mtk_image-split-gfh-header-verification-into-a.patch b/package/boot/uboot-mediatek/patches/002-0029-tools-mtk_image-split-gfh-header-verification-into-a.patch deleted file mode 100644 index 54c92eaaf77..00000000000 --- a/package/boot/uboot-mediatek/patches/002-0029-tools-mtk_image-split-gfh-header-verification-into-a.patch +++ /dev/null @@ -1,89 +0,0 @@ -From 1c9174cbf57ddc75bb5a25b2563333d974fd1a55 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 31 Aug 2022 19:05:22 +0800 -Subject: [PATCH 29/32] tools: mtk_image: split gfh header verification into a - new function - -The verification code of gfh header for NAND and non-NAND are identical. -It's better to define a individual function to reduce redundancy. - -Reviewed-by: Simon Glass -Signed-off-by: Weijie Gao ---- - tools/mtk_image.c | 51 +++++++++++++++++++---------------------------- - 1 file changed, 21 insertions(+), 30 deletions(-) - ---- a/tools/mtk_image.c -+++ b/tools/mtk_image.c -@@ -480,6 +480,25 @@ static int mtk_image_vrec_header(struct - return SHA256_SUM_LEN; - } - -+static int mtk_image_verify_gfh(struct gfh_header *gfh, uint32_t type, int print) -+{ -+ if (strcmp(gfh->file_info.name, GFH_FILE_INFO_NAME)) -+ return -1; -+ -+ if (le32_to_cpu(gfh->file_info.flash_type) != type) -+ return -1; -+ -+ if (print) -+ printf("Load Address: %08x\n", -+ le32_to_cpu(gfh->file_info.load_addr) + -+ le32_to_cpu(gfh->file_info.jump_offset)); -+ -+ if (print) -+ printf("Architecture: %s\n", is_arm64_image ? "ARM64" : "ARM"); -+ -+ return 0; -+} -+ - static int mtk_image_verify_gen_header(const uint8_t *ptr, int print) - { - union gen_boot_header *gbh = (union gen_boot_header *)ptr; -@@ -542,21 +561,7 @@ static int mtk_image_verify_gen_header(c - - gfh = (struct gfh_header *)(ptr + gfh_offset); - -- if (strcmp(gfh->file_info.name, GFH_FILE_INFO_NAME)) -- return -1; -- -- if (le32_to_cpu(gfh->file_info.flash_type) != GFH_FLASH_TYPE_GEN) -- return -1; -- -- if (print) -- printf("Load Address: %08x\n", -- le32_to_cpu(gfh->file_info.load_addr) + -- le32_to_cpu(gfh->file_info.jump_offset)); -- -- if (print) -- printf("Architecture: %s\n", is_arm64_image ? "ARM64" : "ARM"); -- -- return 0; -+ return mtk_image_verify_gfh(gfh, GFH_FLASH_TYPE_GEN, print); - } - - static int mtk_image_verify_nand_header(const uint8_t *ptr, int print) -@@ -610,21 +615,7 @@ static int mtk_image_verify_nand_header( - - gfh = (struct gfh_header *)(ptr + 2 * le16_to_cpu(nh->pagesize)); - -- if (strcmp(gfh->file_info.name, GFH_FILE_INFO_NAME)) -- return -1; -- -- if (le32_to_cpu(gfh->file_info.flash_type) != GFH_FLASH_TYPE_NAND) -- return -1; -- -- if (print) -- printf("Load Address: %08x\n", -- le32_to_cpu(gfh->file_info.load_addr) + -- le32_to_cpu(gfh->file_info.jump_offset)); -- -- if (print) -- printf("Architecture: %s\n", is_arm64_image ? "ARM64" : "ARM"); -- -- return 0; -+ return mtk_image_verify_gfh(gfh, GFH_FLASH_TYPE_NAND, print); - } - - static uint32_t crc32be_cal(const void *data, size_t length) diff --git a/package/boot/uboot-mediatek/patches/002-0030-tools-mtk_image-split-the-code-of-generating-NAND-he.patch b/package/boot/uboot-mediatek/patches/002-0030-tools-mtk_image-split-the-code-of-generating-NAND-he.patch deleted file mode 100644 index 2f5c9353563..00000000000 --- a/package/boot/uboot-mediatek/patches/002-0030-tools-mtk_image-split-the-code-of-generating-NAND-he.patch +++ /dev/null @@ -1,821 +0,0 @@ -From 8867a5e66369d4a7da667e0f505597e1ac91209e Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 31 Aug 2022 19:05:24 +0800 -Subject: [PATCH 30/32] tools: mtk_image: split the code of generating NAND - header into a new file - -The predefined NAND headers take too much spaces in the mtk_image.c. -Moving them into a new file can significantly improve the readability of -both mtk_image.c and the new mtk_nand_headers.c. - -This is a preparation for adding more NAND headers. - -Reviewed-by: Simon Glass -Signed-off-by: Weijie Gao ---- - tools/Makefile | 1 + - tools/mtk_image.c | 305 ++++++--------------------------------- - tools/mtk_image.h | 25 ---- - tools/mtk_nand_headers.c | 286 ++++++++++++++++++++++++++++++++++++ - tools/mtk_nand_headers.h | 61 ++++++++ - 5 files changed, 389 insertions(+), 289 deletions(-) - create mode 100644 tools/mtk_nand_headers.c - create mode 100644 tools/mtk_nand_headers.h - ---- a/tools/Makefile -+++ b/tools/Makefile -@@ -147,6 +147,7 @@ dumpimage-mkimage-objs := aisimage.o \ - gpimage.o \ - gpimage-common.o \ - mtk_image.o \ -+ mtk_nand_headers.o \ - $(ECDSA_OBJS-y) \ - $(RSA_OBJS-y) \ - $(AES_OBJS-y) ---- a/tools/mtk_image.c -+++ b/tools/mtk_image.c -@@ -12,216 +12,7 @@ - #include - #include "imagetool.h" - #include "mtk_image.h" -- --/* NAND header for SPI-NAND with 2KB page + 64B spare */ --static const union nand_boot_header snand_hdr_2k_64_data = { -- .data = { -- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -- 0x00, 0x00, 0x00, 0x08, 0x03, 0x00, 0x40, 0x00, -- 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x7B, 0xC4, 0x17, 0x9D, -- 0xCA, 0x42, 0x90, 0xD0, 0x98, 0xD0, 0xE0, 0xF7, -- 0xDB, 0xCD, 0x16, 0xF6, 0x03, 0x73, 0xD2, 0xB8, -- 0x93, 0xB2, 0x56, 0x5A, 0x84, 0x6E, 0x00, 0x00 -- } --}; -- --/* NAND header for SPI-NAND with 2KB page + 120B/128B spare */ --static const union nand_boot_header snand_hdr_2k_128_data = { -- .data = { -- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, -- 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x90, 0x28, 0xED, 0x13, -- 0x7F, 0x12, 0x22, 0xCD, 0x3D, 0x06, 0xF1, 0xB3, -- 0x6F, 0x2E, 0xD9, 0xA0, 0x9D, 0x7A, 0xBD, 0xD7, -- 0xB3, 0x28, 0x3C, 0x13, 0xDB, 0x4E, 0x00, 0x00 -- } --}; -- --/* NAND header for SPI-NAND with 4KB page + 256B spare */ --static const union nand_boot_header snand_hdr_4k_256_data = { -- .data = { -- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -- 0x00, 0x00, 0x00, 0x10, 0x05, 0x00, 0xE0, 0x00, -- 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x47, 0xED, 0x0E, 0xC3, -- 0x83, 0xBF, 0x41, 0xD2, 0x85, 0x21, 0x97, 0x57, -- 0xC4, 0x2E, 0x6B, 0x7A, 0x40, 0xE0, 0xCF, 0x8F, -- 0x37, 0xBD, 0x17, 0xB6, 0xC7, 0xFE, 0x00, 0x00 -- } --}; -- --/* NAND header for Parallel NAND 1Gb with 2KB page + 64B spare */ --static const union nand_boot_header nand_hdr_1gb_2k_64_data = { -- .data = { -- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, -- 0x40, 0x00, 0x00, 0x04, 0x0B, 0x00, 0x11, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x12, 0x28, 0x1C, 0x12, -- 0x8F, 0xFD, 0xF8, 0x32, 0x6F, 0x6D, 0xCF, 0x6C, -- 0xDA, 0x21, 0x70, 0x8C, 0xDA, 0x0A, 0x22, 0x82, -- 0xAA, 0x59, 0xFA, 0x7C, 0x42, 0x2D, 0x00, 0x00 -- } --}; -- --/* NAND header for Parallel NAND 2Gb with 2KB page + 64B spare */ --static const union nand_boot_header nand_hdr_2gb_2k_64_data = { -- .data = { -- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, -- 0x40, 0x00, 0x00, 0x08, 0x0B, 0x00, 0x11, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x20, 0x9C, 0x3D, 0x2D, -- 0x7B, 0x68, 0x63, 0x52, 0x2E, 0x04, 0x63, 0xF1, -- 0x35, 0x4E, 0x44, 0x3E, 0xF8, 0xAC, 0x9B, 0x95, -- 0xAB, 0xFE, 0xE4, 0xE1, 0xD5, 0xF9, 0x00, 0x00 -- } --}; -- --/* NAND header for Parallel NAND 4Gb with 2KB page + 64B spare */ --static const union nand_boot_header nand_hdr_4gb_2k_64_data = { -- .data = { -- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, -- 0x40, 0x00, 0x00, 0x10, 0x0B, 0x00, 0x11, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0xE3, 0x0F, 0x86, 0x32, -- 0x68, 0x05, 0xD9, 0xC8, 0x13, 0xDF, 0xC5, 0x0B, -- 0x35, 0x3A, 0x68, 0xA5, 0x3C, 0x0C, 0x73, 0x87, -- 0x63, 0xB0, 0xBE, 0xCC, 0x84, 0x47, 0x00, 0x00 -- } --}; -- --/* NAND header for Parallel NAND 2Gb with 2KB page + 128B spare */ --static const union nand_boot_header nand_hdr_2gb_2k_128_data = { -- .data = { -- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, -- 0x40, 0x00, 0x00, 0x08, 0x0B, 0x00, 0x11, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x01, 0xA5, 0xE9, 0x5A, -- 0xDF, 0x58, 0x62, 0x41, 0xD6, 0x26, 0x77, 0xBC, -- 0x76, 0x1F, 0x27, 0x4E, 0x4F, 0x6C, 0xC3, 0xF0, -- 0x36, 0xDE, 0xD9, 0xB3, 0xFF, 0x93, 0x00, 0x00 -- } --}; -- --/* NAND header for Parallel NAND 4Gb with 2KB page + 128B spare */ --static const union nand_boot_header nand_hdr_4gb_2k_128_data = { -- .data = { -- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, -- 0x40, 0x00, 0x00, 0x10, 0x0B, 0x00, 0x11, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0xC2, 0x36, 0x52, 0x45, -- 0xCC, 0x35, 0xD8, 0xDB, 0xEB, 0xFD, 0xD1, 0x46, -- 0x76, 0x6B, 0x0B, 0xD5, 0x8B, 0xCC, 0x2B, 0xE2, -- 0xFE, 0x90, 0x83, 0x9E, 0xAE, 0x2D, 0x00, 0x00 -- } --}; -- --static const struct nand_header_type { -- const char *name; -- const union nand_boot_header *data; --} nand_headers[] = { -- { -- .name = "2k+64", -- .data = &snand_hdr_2k_64_data -- }, { -- .name = "2k+120", -- .data = &snand_hdr_2k_128_data -- }, { -- .name = "2k+128", -- .data = &snand_hdr_2k_128_data -- }, { -- .name = "4k+256", -- .data = &snand_hdr_4k_256_data -- }, { -- .name = "1g:2k+64", -- .data = &nand_hdr_1gb_2k_64_data -- }, { -- .name = "2g:2k+64", -- .data = &nand_hdr_2gb_2k_64_data -- }, { -- .name = "4g:2k+64", -- .data = &nand_hdr_4gb_2k_64_data -- }, { -- .name = "2g:2k+128", -- .data = &nand_hdr_2gb_2k_128_data -- }, { -- .name = "4g:2k+128", -- .data = &nand_hdr_4gb_2k_128_data -- } --}; -+#include "mtk_nand_headers.h" - - static const struct brom_img_type { - const char *name; -@@ -264,6 +55,7 @@ static uint32_t crc32tbl[256]; - - /* NAND header selected by user */ - static const union nand_boot_header *hdr_nand; -+static uint32_t hdr_nand_size; - - /* GFH header + 2 * 4KB pages of NAND */ - static char hdr_tmp[sizeof(struct gfh_header) + 0x2000]; -@@ -402,12 +194,7 @@ static int mtk_brom_parse_imagename(cons - } - - /* parse nand header type */ -- for (i = 0; i < ARRAY_SIZE(nand_headers); i++) { -- if (!strcmp(nand_headers[i].name, nandinfo)) { -- hdr_nand = nand_headers[i].data; -- break; -- } -- } -+ hdr_nand = mtk_nand_header_find(nandinfo); - - /* parse device header offset */ - if (hdr_offs && hdr_offs[0]) -@@ -432,6 +219,9 @@ static int mtk_brom_parse_imagename(cons - return -EINVAL; - } - -+ if (hdr_media == BRLYT_TYPE_NAND || hdr_media == BRLYT_TYPE_SNAND) -+ hdr_nand_size = mtk_nand_header_size(hdr_nand); -+ - return 0; - } - -@@ -468,7 +258,7 @@ static int mtk_image_vrec_header(struct - } - - if (hdr_media == BRLYT_TYPE_NAND || hdr_media == BRLYT_TYPE_SNAND) -- tparams->header_size = 2 * le16_to_cpu(hdr_nand->pagesize); -+ tparams->header_size = hdr_nand_size; - else - tparams->header_size = sizeof(struct gen_device_header); - -@@ -566,16 +356,17 @@ static int mtk_image_verify_gen_header(c - - static int mtk_image_verify_nand_header(const uint8_t *ptr, int print) - { -- union nand_boot_header *nh = (union nand_boot_header *)ptr; - struct brom_layout_header *bh; -+ struct nand_header_info info; - struct gfh_header *gfh; - const char *bootmedia; -+ int ret; - -- if (strncmp(nh->version, NAND_BOOT_VERSION, sizeof(nh->version)) || -- strcmp(nh->id, NAND_BOOT_ID)) -- return -1; -+ ret = mtk_nand_header_info(ptr, &info); -+ if (ret < 0) -+ return ret; - -- bh = (struct brom_layout_header *)(ptr + le16_to_cpu(nh->pagesize)); -+ bh = (struct brom_layout_header *)(ptr + info.page_size); - - if (strcmp(bh->name, BRLYT_NAME)) - return -1; -@@ -586,34 +377,23 @@ static int mtk_image_verify_nand_header( - if (le32_to_cpu(bh->type) == BRLYT_TYPE_NAND) - bootmedia = "Parallel NAND"; - else if (le32_to_cpu(bh->type) == BRLYT_TYPE_SNAND) -- bootmedia = "Serial NAND"; -+ bootmedia = "Serial NAND (SNFI/AP)"; - else - return -1; - } - - if (print) { -- printf("Boot Media: %s\n", bootmedia); -- -- if (le32_to_cpu(bh->type) == BRLYT_TYPE_NAND) { -- uint64_t capacity = -- (uint64_t)le16_to_cpu(nh->numblocks) * -- (uint64_t)le16_to_cpu(nh->pages_of_block) * -- (uint64_t)le16_to_cpu(nh->pagesize) * 8; -- printf("Capacity: %dGb\n", -- (uint32_t)(capacity >> 30)); -- } -+ printf("Boot Media: %s\n", bootmedia); - -- if (le16_to_cpu(nh->pagesize) >= 1024) -- printf("Page Size: %dKB\n", -- le16_to_cpu(nh->pagesize) >> 10); -+ if (info.page_size >= 1024) -+ printf("Page Size: %dKB\n", info.page_size >> 10); - else -- printf("Page Size: %dB\n", -- le16_to_cpu(nh->pagesize)); -+ printf("Page Size: %dB\n", info.page_size); - -- printf("Spare Size: %dB\n", le16_to_cpu(nh->oobsize)); -+ printf("Spare Size: %dB\n", info.spare_size); - } - -- gfh = (struct gfh_header *)(ptr + 2 * le16_to_cpu(nh->pagesize)); -+ gfh = (struct gfh_header *)(ptr + info.gfh_offset); - - return mtk_image_verify_gfh(gfh, GFH_FLASH_TYPE_NAND, print); - } -@@ -713,7 +493,7 @@ static int mtk_image_verify_header(unsig - if (image_get_magic(hdr) == IH_MAGIC) - return mtk_image_verify_mt7621_header(ptr, 0); - -- if (!strcmp((char *)ptr, NAND_BOOT_NAME)) -+ if (is_mtk_nand_header(ptr)) - return mtk_image_verify_nand_header(ptr, 0); - else - return mtk_image_verify_gen_header(ptr, 0); -@@ -739,7 +519,7 @@ static void mtk_image_print_header(const - return; - } - -- if (!strcmp((char *)ptr, NAND_BOOT_NAME)) -+ if (is_mtk_nand_header(ptr)) - mtk_image_verify_nand_header(ptr, 1); - else - mtk_image_verify_gen_header(ptr, 1); -@@ -870,36 +650,33 @@ static void mtk_image_set_gen_header(voi - static void mtk_image_set_nand_header(void *ptr, off_t filesize, - uint32_t loadaddr) - { -- union nand_boot_header *nh = (union nand_boot_header *)ptr; - struct brom_layout_header *brlyt; - struct gfh_header *gfh; -- uint32_t payload_pages; -- int i; -+ uint32_t payload_pages, nand_page_size; - -- /* NAND device header, repeat 4 times */ -- for (i = 0; i < 4; i++) -- memcpy(nh + i, hdr_nand, sizeof(union nand_boot_header)); -+ /* NAND header */ -+ nand_page_size = mtk_nand_header_put(hdr_nand, ptr); - -- /* BRLYT header */ -- payload_pages = (filesize + le16_to_cpu(hdr_nand->pagesize) - 1) / -- le16_to_cpu(hdr_nand->pagesize); -- brlyt = (struct brom_layout_header *) -- (ptr + le16_to_cpu(hdr_nand->pagesize)); -- put_brom_layout_header(brlyt, hdr_media); -- brlyt->header_size = cpu_to_le32(2); -- brlyt->total_size = cpu_to_le32(payload_pages); -- brlyt->header_size_2 = brlyt->header_size; -- brlyt->total_size_2 = brlyt->total_size; -- brlyt->unused = cpu_to_le32(1); -+ if (nand_page_size) { -+ /* BRLYT header */ -+ payload_pages = (filesize + nand_page_size - 1) / -+ nand_page_size; -+ brlyt = (struct brom_layout_header *)(ptr + nand_page_size); -+ put_brom_layout_header(brlyt, hdr_media); -+ brlyt->header_size = cpu_to_le32(2); -+ brlyt->total_size = cpu_to_le32(payload_pages); -+ brlyt->header_size_2 = brlyt->header_size; -+ brlyt->total_size_2 = brlyt->total_size; -+ brlyt->unused = cpu_to_le32(1); -+ } - - /* GFH header */ -- gfh = (struct gfh_header *)(ptr + 2 * le16_to_cpu(hdr_nand->pagesize)); -- put_ghf_header(gfh, filesize, 2 * le16_to_cpu(hdr_nand->pagesize), -- loadaddr, GFH_FLASH_TYPE_NAND); -+ gfh = (struct gfh_header *)(ptr + hdr_nand_size); -+ put_ghf_header(gfh, filesize, hdr_nand_size, loadaddr, -+ GFH_FLASH_TYPE_NAND); - - /* Generate SHA256 hash */ -- put_hash((uint8_t *)gfh, -- filesize - 2 * le16_to_cpu(hdr_nand->pagesize) - SHA256_SUM_LEN); -+ put_hash((uint8_t *)gfh, filesize - hdr_nand_size - SHA256_SUM_LEN); - } - - static void mtk_image_set_mt7621_header(void *ptr, off_t filesize, ---- a/tools/mtk_image.h -+++ b/tools/mtk_image.h -@@ -26,31 +26,6 @@ union gen_boot_header { - #define SF_BOOT_NAME "SF_BOOT" - #define SDMMC_BOOT_NAME "SDMMC_BOOT" - --/* Header for NAND */ --union nand_boot_header { -- struct { -- char name[12]; -- char version[4]; -- char id[8]; -- uint16_t ioif; -- uint16_t pagesize; -- uint16_t addrcycles; -- uint16_t oobsize; -- uint16_t pages_of_block; -- uint16_t numblocks; -- uint16_t writesize_shift; -- uint16_t erasesize_shift; -- uint8_t dummy[60]; -- uint8_t ecc_parity[28]; -- }; -- -- uint8_t data[0x80]; --}; -- --#define NAND_BOOT_NAME "BOOTLOADER!" --#define NAND_BOOT_VERSION "V006" --#define NAND_BOOT_ID "NFIINFO" -- - /* BootROM layout header */ - struct brom_layout_header { - char name[8]; ---- /dev/null -+++ b/tools/mtk_nand_headers.c -@@ -0,0 +1,286 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * MediaTek BootROM NAND header definitions -+ * -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Weijie Gao -+ */ -+ -+#include -+#include -+#include "imagetool.h" -+#include "mtk_image.h" -+#include "mtk_nand_headers.h" -+ -+/* NAND header for SPI-NAND with 2KB page + 64B spare */ -+static const union nand_boot_header snand_hdr_2k_64_data = { -+ .data = { -+ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -+ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -+ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -+ 0x00, 0x00, 0x00, 0x08, 0x03, 0x00, 0x40, 0x00, -+ 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x7B, 0xC4, 0x17, 0x9D, -+ 0xCA, 0x42, 0x90, 0xD0, 0x98, 0xD0, 0xE0, 0xF7, -+ 0xDB, 0xCD, 0x16, 0xF6, 0x03, 0x73, 0xD2, 0xB8, -+ 0x93, 0xB2, 0x56, 0x5A, 0x84, 0x6E, 0x00, 0x00 -+ } -+}; -+ -+/* NAND header for SPI-NAND with 2KB page + 120B/128B spare */ -+static const union nand_boot_header snand_hdr_2k_128_data = { -+ .data = { -+ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -+ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -+ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -+ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, -+ 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x90, 0x28, 0xED, 0x13, -+ 0x7F, 0x12, 0x22, 0xCD, 0x3D, 0x06, 0xF1, 0xB3, -+ 0x6F, 0x2E, 0xD9, 0xA0, 0x9D, 0x7A, 0xBD, 0xD7, -+ 0xB3, 0x28, 0x3C, 0x13, 0xDB, 0x4E, 0x00, 0x00 -+ } -+}; -+ -+/* NAND header for SPI-NAND with 4KB page + 256B spare */ -+static const union nand_boot_header snand_hdr_4k_256_data = { -+ .data = { -+ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -+ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -+ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -+ 0x00, 0x00, 0x00, 0x10, 0x05, 0x00, 0xE0, 0x00, -+ 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x47, 0xED, 0x0E, 0xC3, -+ 0x83, 0xBF, 0x41, 0xD2, 0x85, 0x21, 0x97, 0x57, -+ 0xC4, 0x2E, 0x6B, 0x7A, 0x40, 0xE0, 0xCF, 0x8F, -+ 0x37, 0xBD, 0x17, 0xB6, 0xC7, 0xFE, 0x00, 0x00 -+ } -+}; -+ -+/* NAND header for Parallel NAND 1Gb with 2KB page + 64B spare */ -+static const union nand_boot_header nand_hdr_1gb_2k_64_data = { -+ .data = { -+ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -+ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -+ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -+ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, -+ 0x40, 0x00, 0x00, 0x04, 0x0B, 0x00, 0x11, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x12, 0x28, 0x1C, 0x12, -+ 0x8F, 0xFD, 0xF8, 0x32, 0x6F, 0x6D, 0xCF, 0x6C, -+ 0xDA, 0x21, 0x70, 0x8C, 0xDA, 0x0A, 0x22, 0x82, -+ 0xAA, 0x59, 0xFA, 0x7C, 0x42, 0x2D, 0x00, 0x00 -+ } -+}; -+ -+/* NAND header for Parallel NAND 2Gb with 2KB page + 64B spare */ -+static const union nand_boot_header nand_hdr_2gb_2k_64_data = { -+ .data = { -+ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -+ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -+ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -+ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, -+ 0x40, 0x00, 0x00, 0x08, 0x0B, 0x00, 0x11, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x20, 0x9C, 0x3D, 0x2D, -+ 0x7B, 0x68, 0x63, 0x52, 0x2E, 0x04, 0x63, 0xF1, -+ 0x35, 0x4E, 0x44, 0x3E, 0xF8, 0xAC, 0x9B, 0x95, -+ 0xAB, 0xFE, 0xE4, 0xE1, 0xD5, 0xF9, 0x00, 0x00 -+ } -+}; -+ -+/* NAND header for Parallel NAND 4Gb with 2KB page + 64B spare */ -+static const union nand_boot_header nand_hdr_4gb_2k_64_data = { -+ .data = { -+ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -+ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -+ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -+ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, -+ 0x40, 0x00, 0x00, 0x10, 0x0B, 0x00, 0x11, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xE3, 0x0F, 0x86, 0x32, -+ 0x68, 0x05, 0xD9, 0xC8, 0x13, 0xDF, 0xC5, 0x0B, -+ 0x35, 0x3A, 0x68, 0xA5, 0x3C, 0x0C, 0x73, 0x87, -+ 0x63, 0xB0, 0xBE, 0xCC, 0x84, 0x47, 0x00, 0x00 -+ } -+}; -+ -+/* NAND header for Parallel NAND 2Gb with 2KB page + 128B spare */ -+static const union nand_boot_header nand_hdr_2gb_2k_128_data = { -+ .data = { -+ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -+ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -+ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -+ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, -+ 0x40, 0x00, 0x00, 0x08, 0x0B, 0x00, 0x11, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x01, 0xA5, 0xE9, 0x5A, -+ 0xDF, 0x58, 0x62, 0x41, 0xD6, 0x26, 0x77, 0xBC, -+ 0x76, 0x1F, 0x27, 0x4E, 0x4F, 0x6C, 0xC3, 0xF0, -+ 0x36, 0xDE, 0xD9, 0xB3, 0xFF, 0x93, 0x00, 0x00 -+ } -+}; -+ -+/* NAND header for Parallel NAND 4Gb with 2KB page + 128B spare */ -+static const union nand_boot_header nand_hdr_4gb_2k_128_data = { -+ .data = { -+ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -+ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -+ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -+ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, -+ 0x40, 0x00, 0x00, 0x10, 0x0B, 0x00, 0x11, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xC2, 0x36, 0x52, 0x45, -+ 0xCC, 0x35, 0xD8, 0xDB, 0xEB, 0xFD, 0xD1, 0x46, -+ 0x76, 0x6B, 0x0B, 0xD5, 0x8B, 0xCC, 0x2B, 0xE2, -+ 0xFE, 0x90, 0x83, 0x9E, 0xAE, 0x2D, 0x00, 0x00 -+ } -+}; -+ -+static const struct nand_header_type { -+ const char *name; -+ const union nand_boot_header *data; -+} nand_headers[] = { -+ { -+ .name = "2k+64", -+ .data = &snand_hdr_2k_64_data -+ }, { -+ .name = "2k+120", -+ .data = &snand_hdr_2k_128_data -+ }, { -+ .name = "2k+128", -+ .data = &snand_hdr_2k_128_data -+ }, { -+ .name = "4k+256", -+ .data = &snand_hdr_4k_256_data -+ }, { -+ .name = "1g:2k+64", -+ .data = &nand_hdr_1gb_2k_64_data -+ }, { -+ .name = "2g:2k+64", -+ .data = &nand_hdr_2gb_2k_64_data -+ }, { -+ .name = "4g:2k+64", -+ .data = &nand_hdr_4gb_2k_64_data -+ }, { -+ .name = "2g:2k+128", -+ .data = &nand_hdr_2gb_2k_128_data -+ }, { -+ .name = "4g:2k+128", -+ .data = &nand_hdr_4gb_2k_128_data -+ } -+}; -+ -+const union nand_boot_header *mtk_nand_header_find(const char *name) -+{ -+ uint32_t i; -+ -+ for (i = 0; i < ARRAY_SIZE(nand_headers); i++) { -+ if (!strcmp(nand_headers[i].name, name)) -+ return nand_headers[i].data; -+ } -+ -+ return NULL; -+} -+ -+uint32_t mtk_nand_header_size(const union nand_boot_header *hdr_nand) -+{ -+ return 2 * le16_to_cpu(hdr_nand->pagesize); -+} -+ -+static int mtk_nand_header_ap_info(const void *ptr, -+ struct nand_header_info *info) -+{ -+ union nand_boot_header *nh = (union nand_boot_header *)ptr; -+ -+ if (strncmp(nh->version, NAND_BOOT_VERSION, sizeof(nh->version)) || -+ strcmp(nh->id, NAND_BOOT_ID)) -+ return -1; -+ -+ info->page_size = le16_to_cpu(nh->pagesize); -+ info->spare_size = le16_to_cpu(nh->oobsize); -+ info->gfh_offset = 2 * info->page_size; -+ -+ return 0; -+} -+ -+int mtk_nand_header_info(const void *ptr, struct nand_header_info *info) -+{ -+ if (!strcmp((char *)ptr, NAND_BOOT_NAME)) -+ return mtk_nand_header_ap_info(ptr, info); -+ -+ return -1; -+} -+ -+bool is_mtk_nand_header(const void *ptr) -+{ -+ struct nand_header_info info; -+ -+ if (mtk_nand_header_info(ptr, &info) >= 0) -+ return true; -+ -+ return false; -+} -+ -+uint32_t mtk_nand_header_put(const union nand_boot_header *hdr_nand, void *ptr) -+{ -+ union nand_boot_header *nh = (union nand_boot_header *)ptr; -+ int i; -+ -+ /* NAND device header, repeat 4 times */ -+ for (i = 0; i < 4; i++) -+ memcpy(nh + i, hdr_nand, sizeof(union nand_boot_header)); -+ -+ return le16_to_cpu(hdr_nand->pagesize); -+} ---- /dev/null -+++ b/tools/mtk_nand_headers.h -@@ -0,0 +1,61 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * MediaTek BootROM NAND header definitions -+ * -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Weijie Gao -+ */ -+ -+#ifndef _MTK_NAND_HEADERS_H -+#define _MTK_NAND_HEADERS_H -+ -+#include -+#include -+ -+struct nand_header_info { -+ uint32_t page_size; -+ uint32_t spare_size; -+ uint32_t gfh_offset; -+}; -+ -+/* AP BROM Header for NAND */ -+union nand_boot_header { -+ struct { -+ char name[12]; -+ char version[4]; -+ char id[8]; -+ uint16_t ioif; /* I/O interface */ -+ uint16_t pagesize; /* NAND page size */ -+ uint16_t addrcycles; /* Address cycles */ -+ uint16_t oobsize; /* NAND page spare size */ -+ uint16_t pages_of_block; /* Pages of one block */ -+ uint16_t numblocks; /* Total blocks of NAND chip */ -+ uint16_t writesize_shift; -+ uint16_t erasesize_shift; -+ uint8_t dummy[60]; -+ uint8_t ecc_parity[28]; /* ECC parity of this header */ -+ }; -+ -+ uint8_t data[0x80]; -+}; -+ -+#define NAND_BOOT_NAME "BOOTLOADER!" -+#define NAND_BOOT_VERSION "V006" -+#define NAND_BOOT_ID "NFIINFO" -+ -+/* Find nand header data by name */ -+const union nand_boot_header *mtk_nand_header_find(const char *name); -+ -+/* Device header size using this nand header */ -+uint32_t mtk_nand_header_size(const union nand_boot_header *hdr_nand); -+ -+/* Get nand info from nand header (page size, spare size, ...) */ -+int mtk_nand_header_info(const void *ptr, struct nand_header_info *info); -+ -+/* Whether given header data is valid */ -+bool is_mtk_nand_header(const void *ptr); -+ -+/* Generate Device header using give nand header */ -+uint32_t mtk_nand_header_put(const union nand_boot_header *hdr_nand, void *ptr); -+ -+#endif /* _MTK_NAND_HEADERS_H */ diff --git a/package/boot/uboot-mediatek/patches/002-0031-tools-mtk_image-add-support-for-nand-headers-used-by.patch b/package/boot/uboot-mediatek/patches/002-0031-tools-mtk_image-add-support-for-nand-headers-used-by.patch deleted file mode 100644 index c20dffdb36d..00000000000 --- a/package/boot/uboot-mediatek/patches/002-0031-tools-mtk_image-add-support-for-nand-headers-used-by.patch +++ /dev/null @@ -1,702 +0,0 @@ -From d459092aca25e081401606e18b7097f33b575188 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 31 Aug 2022 19:05:26 +0800 -Subject: [PATCH 31/32] tools: mtk_image: add support for nand headers used by - newer chips - -This patch adds more nand headers in two new types: -1. HSM header, used for spi-nand thru SNFI interface -2. SPIM header, used for spi-nand thru spi-mem interface - -The original nand header is renamed to AP header. - -Signed-off-by: Weijie Gao ---- - tools/mtk_image.c | 23 ++- - tools/mtk_nand_headers.c | 422 +++++++++++++++++++++++++++++++++++++-- - tools/mtk_nand_headers.h | 110 +++++++++- - 3 files changed, 525 insertions(+), 30 deletions(-) - ---- a/tools/mtk_image.c -+++ b/tools/mtk_image.c -@@ -33,6 +33,9 @@ static const struct brom_img_type { - }, { - .name = "snand", - .type = BRLYT_TYPE_SNAND -+ }, { -+ .name = "spim-nand", -+ .type = BRLYT_TYPE_SNAND - } - }; - -@@ -54,7 +57,7 @@ static char lk_name[32] = "U-Boot"; - static uint32_t crc32tbl[256]; - - /* NAND header selected by user */ --static const union nand_boot_header *hdr_nand; -+static const struct nand_header_type *hdr_nand; - static uint32_t hdr_nand_size; - - /* GFH header + 2 * 4KB pages of NAND */ -@@ -366,20 +369,26 @@ static int mtk_image_verify_nand_header( - if (ret < 0) - return ret; - -- bh = (struct brom_layout_header *)(ptr + info.page_size); -+ if (!ret) { -+ bh = (struct brom_layout_header *)(ptr + info.page_size); - -- if (strcmp(bh->name, BRLYT_NAME)) -- return -1; -+ if (strcmp(bh->name, BRLYT_NAME)) -+ return -1; -+ -+ if (le32_to_cpu(bh->magic) != BRLYT_MAGIC) -+ return -1; - -- if (le32_to_cpu(bh->magic) != BRLYT_MAGIC) { -- return -1; -- } else { - if (le32_to_cpu(bh->type) == BRLYT_TYPE_NAND) - bootmedia = "Parallel NAND"; - else if (le32_to_cpu(bh->type) == BRLYT_TYPE_SNAND) - bootmedia = "Serial NAND (SNFI/AP)"; - else - return -1; -+ } else { -+ if (info.snfi) -+ bootmedia = "Serial NAND (SNFI/HSM)"; -+ else -+ bootmedia = "Serial NAND (SPIM)"; - } - - if (print) { ---- a/tools/mtk_nand_headers.c -+++ b/tools/mtk_nand_headers.c -@@ -188,55 +188,346 @@ static const union nand_boot_header nand - } - }; - --static const struct nand_header_type { -+/* HSM BROM NAND header for SPI NAND with 2KB page + 64B spare */ -+static const union hsm_nand_boot_header hsm_nand_hdr_2k_64_data = { -+ .data = { -+ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x08, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, -+ 0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, -+ 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, -+ 0xFF, 0x00, 0x00, 0x00, 0x21, 0xD2, 0xEE, 0xF6, -+ 0xAE, 0xDD, 0x5E, 0xC2, 0x82, 0x8E, 0x9A, 0x62, -+ 0x09, 0x8E, 0x80, 0xE2, 0x37, 0x0D, 0xC9, 0xFA, -+ 0xA9, 0xDD, 0xFC, 0x92, 0x34, 0x2A, 0xED, 0x51, -+ 0xA4, 0x1B, 0xF7, 0x63, 0xCC, 0x5A, 0xC7, 0xFB, -+ 0xED, 0x21, 0x02, 0x23, 0x51, 0x31 -+ } -+}; -+ -+/* HSM BROM NAND header for SPI NAND with 2KB page + 128B spare */ -+static const union hsm_nand_boot_header hsm_nand_hdr_2k_128_data = { -+ .data = { -+ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x08, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, -+ 0x40, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, -+ 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, -+ 0xFF, 0x00, 0x00, 0x00, 0x71, 0x7f, 0x71, 0xAC, -+ 0x42, 0xD0, 0x5B, 0xD2, 0x12, 0x81, 0x15, 0x0A, -+ 0x0C, 0xD4, 0xF6, 0x32, 0x1E, 0x63, 0xE7, 0x81, -+ 0x8A, 0x7F, 0xDE, 0xF9, 0x4B, 0x91, 0xEC, 0xC2, -+ 0x70, 0x00, 0x7F, 0x57, 0xAF, 0xDC, 0xE4, 0x24, -+ 0x57, 0x09, 0xBC, 0xC5, 0x35, 0xDC -+ } -+}; -+ -+/* HSM BROM NAND header for SPI NAND with 4KB page + 256B spare */ -+static const union hsm_nand_boot_header hsm_nand_hdr_4k_256_data = { -+ .data = { -+ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, -+ 0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, -+ 0x0C, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, -+ 0xFF, 0x00, 0x00, 0x00, 0x62, 0x04, 0xD6, 0x1F, -+ 0x2B, 0x57, 0x7A, 0x2D, 0xFE, 0xBB, 0x4A, 0x50, -+ 0xEC, 0xF8, 0x70, 0x1A, 0x44, 0x15, 0xF6, 0xA2, -+ 0x8E, 0xB0, 0xFD, 0xFA, 0xDC, 0xAA, 0x5A, 0x4E, -+ 0xCB, 0x8E, 0xC9, 0x72, 0x08, 0xDC, 0x20, 0xB9, -+ 0x98, 0xC8, 0x82, 0xD8, 0xBE, 0x44 -+ } -+}; -+ -+/* HSM2.0 BROM NAND header for SPI NAND with 2KB page + 64B spare */ -+static const union hsm20_nand_boot_header hsm20_nand_hdr_2k_64_data = { -+ .data = { -+ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, -+ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x08, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, -+ 0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, -+ 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0x01, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x5F, 0x4B, 0xB2, 0x5B, 0x8B, 0x1C, 0x35, 0xDA, -+ 0x83, 0xE6, 0x6C, 0xC3, 0xFB, 0x8C, 0x78, 0x23, -+ 0xD0, 0x89, 0x24, 0xD9, 0x6C, 0x35, 0x2C, 0x5D, -+ 0x8F, 0xBB, 0xFC, 0x10, 0xD0, 0xE2, 0x22, 0x7D, -+ 0xC8, 0x97, 0x9A, 0xEF, 0xC6, 0xB5, 0xA7, 0x4E, -+ 0x4E, 0x0E -+ } -+}; -+ -+/* HSM2.0 BROM NAND header for SPI NAND with 2KB page + 128B spare */ -+static const union hsm20_nand_boot_header hsm20_nand_hdr_2k_128_data = { -+ .data = { -+ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, -+ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x08, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, -+ 0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, -+ 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0x01, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0xF8, 0x7E, 0xC1, 0x5D, 0x61, 0x54, 0xEA, 0x9F, -+ 0x5E, 0x66, 0x39, 0x66, 0x21, 0xFF, 0x8C, 0x3B, -+ 0xBE, 0xA7, 0x5A, 0x9E, 0xD7, 0xBD, 0x9E, 0x89, -+ 0xEE, 0x7E, 0x10, 0x31, 0x9A, 0x1D, 0x82, 0x49, -+ 0xA3, 0x4E, 0xD8, 0x47, 0xD7, 0x19, 0xF4, 0x2D, -+ 0x8E, 0x53 -+ } -+}; -+ -+/* HSM2.0 BROM NAND header for SPI NAND with 4KB page + 256B spare */ -+static const union hsm20_nand_boot_header hsm20_nand_hdr_4k_256_data = { -+ .data = { -+ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, -+ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, -+ 0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, -+ 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0x01, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x79, 0x01, 0x1F, 0x86, 0x62, 0x6A, 0x43, 0xAE, -+ 0xE6, 0xF8, 0xDD, 0x5B, 0x29, 0xB7, 0xA2, 0x7F, -+ 0x29, 0x72, 0x54, 0x37, 0xBE, 0x50, 0xD4, 0x24, -+ 0xAB, 0x60, 0xF4, 0x44, 0x97, 0x3B, 0x65, 0x21, -+ 0x73, 0x24, 0x1F, 0x93, 0x0E, 0x9E, 0x96, 0x88, -+ 0x78, 0x6C -+ } -+}; -+ -+/* SPIM-NAND header for SPI NAND with 2KB page + 64B spare */ -+static const union spim_nand_boot_header spim_nand_hdr_2k_64_data = { -+ .data = { -+ 0x53, 0x50, 0x49, 0x4e, 0x41, 0x4e, 0x44, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, -+ 0x00, 0x08, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, -+ 0x40, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x20, 0x30, -+ 0x01, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -+ } -+}; -+ -+/* SPIM-NAND header for SPI NAND with 2KB page + 128B spare */ -+static const union spim_nand_boot_header spim_nand_hdr_2k_128_data = { -+ .data = { -+ 0x53, 0x50, 0x49, 0x4e, 0x41, 0x4e, 0x44, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, -+ 0x00, 0x08, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, -+ 0x40, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x20, 0x30, -+ 0x01, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -+ } -+}; -+ -+/* SPIM-NAND header for SPI NAND with 4KB page + 256B spare */ -+static const union spim_nand_boot_header spim_nand_hdr_4k_256_data = { -+ .data = { -+ 0x53, 0x50, 0x49, 0x4e, 0x41, 0x4e, 0x44, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, -+ 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, -+ 0x40, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x20, 0x30, -+ 0x01, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -+ } -+}; -+ -+struct nand_header_type { - const char *name; -- const union nand_boot_header *data; -+ enum nand_boot_header_type type; -+ union { -+ const union nand_boot_header *ap; -+ const union hsm_nand_boot_header *hsm; -+ const union hsm20_nand_boot_header *hsm20; -+ const union spim_nand_boot_header *spim; -+ }; - } nand_headers[] = { - { - .name = "2k+64", -- .data = &snand_hdr_2k_64_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &snand_hdr_2k_64_data, - }, { - .name = "2k+120", -- .data = &snand_hdr_2k_128_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &snand_hdr_2k_128_data, - }, { - .name = "2k+128", -- .data = &snand_hdr_2k_128_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &snand_hdr_2k_128_data, - }, { - .name = "4k+256", -- .data = &snand_hdr_4k_256_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &snand_hdr_4k_256_data, - }, { - .name = "1g:2k+64", -- .data = &nand_hdr_1gb_2k_64_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &nand_hdr_1gb_2k_64_data, - }, { - .name = "2g:2k+64", -- .data = &nand_hdr_2gb_2k_64_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &nand_hdr_2gb_2k_64_data, - }, { - .name = "4g:2k+64", -- .data = &nand_hdr_4gb_2k_64_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &nand_hdr_4gb_2k_64_data, - }, { - .name = "2g:2k+128", -- .data = &nand_hdr_2gb_2k_128_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &nand_hdr_2gb_2k_128_data, - }, { - .name = "4g:2k+128", -- .data = &nand_hdr_4gb_2k_128_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &nand_hdr_4gb_2k_128_data, -+ }, { -+ .name = "hsm:2k+64", -+ .type = NAND_BOOT_HSM_HEADER, -+ .hsm = &hsm_nand_hdr_2k_64_data, -+ }, { -+ .name = "hsm:2k+128", -+ .type = NAND_BOOT_HSM_HEADER, -+ .hsm = &hsm_nand_hdr_2k_128_data, -+ }, { -+ .name = "hsm:4k+256", -+ .type = NAND_BOOT_HSM_HEADER, -+ .hsm = &hsm_nand_hdr_4k_256_data, -+ }, { -+ .name = "hsm20:2k+64", -+ .type = NAND_BOOT_HSM20_HEADER, -+ .hsm20 = &hsm20_nand_hdr_2k_64_data, -+ }, { -+ .name = "hsm20:2k+128", -+ .type = NAND_BOOT_HSM20_HEADER, -+ .hsm20 = &hsm20_nand_hdr_2k_128_data, -+ }, { -+ .name = "hsm20:4k+256", -+ .type = NAND_BOOT_HSM20_HEADER, -+ .hsm20 = &hsm20_nand_hdr_4k_256_data, -+ }, { -+ .name = "spim:2k+64", -+ .type = NAND_BOOT_SPIM_HEADER, -+ .spim = &spim_nand_hdr_2k_64_data, -+ }, { -+ .name = "spim:2k+128", -+ .type = NAND_BOOT_SPIM_HEADER, -+ .spim = &spim_nand_hdr_2k_128_data, -+ }, { -+ .name = "spim:4k+256", -+ .type = NAND_BOOT_SPIM_HEADER, -+ .spim = &spim_nand_hdr_4k_256_data, - } - }; - --const union nand_boot_header *mtk_nand_header_find(const char *name) -+const struct nand_header_type *mtk_nand_header_find(const char *name) - { - uint32_t i; - - for (i = 0; i < ARRAY_SIZE(nand_headers); i++) { - if (!strcmp(nand_headers[i].name, name)) -- return nand_headers[i].data; -+ return &nand_headers[i]; - } - - return NULL; - } - --uint32_t mtk_nand_header_size(const union nand_boot_header *hdr_nand) -+uint32_t mtk_nand_header_size(const struct nand_header_type *hdr_nand) - { -- return 2 * le16_to_cpu(hdr_nand->pagesize); -+ switch (hdr_nand->type) { -+ case NAND_BOOT_HSM_HEADER: -+ return le32_to_cpu(hdr_nand->hsm->page_size); -+ -+ case NAND_BOOT_HSM20_HEADER: -+ return le32_to_cpu(hdr_nand->hsm20->page_size); -+ -+ case NAND_BOOT_SPIM_HEADER: -+ return le32_to_cpu(hdr_nand->spim->page_size); -+ -+ default: -+ return 2 * le16_to_cpu(hdr_nand->ap->pagesize); -+ } - } - - static int mtk_nand_header_ap_info(const void *ptr, -@@ -251,14 +542,45 @@ static int mtk_nand_header_ap_info(const - info->page_size = le16_to_cpu(nh->pagesize); - info->spare_size = le16_to_cpu(nh->oobsize); - info->gfh_offset = 2 * info->page_size; -+ info->snfi = true; - - return 0; - } - -+static int mtk_nand_header_hsm_info(const void *ptr, -+ struct nand_header_info *info) -+{ -+ union hsm_nand_boot_header *nh = (union hsm_nand_boot_header *)ptr; -+ -+ info->page_size = le16_to_cpu(nh->page_size); -+ info->spare_size = le16_to_cpu(nh->spare_size); -+ info->gfh_offset = info->page_size; -+ info->snfi = true; -+ -+ return 1; -+} -+ -+static int mtk_nand_header_spim_info(const void *ptr, -+ struct nand_header_info *info) -+{ -+ union spim_nand_boot_header *nh = (union spim_nand_boot_header *)ptr; -+ -+ info->page_size = le16_to_cpu(nh->page_size); -+ info->spare_size = le16_to_cpu(nh->spare_size); -+ info->gfh_offset = info->page_size; -+ info->snfi = false; -+ -+ return 1; -+} -+ - int mtk_nand_header_info(const void *ptr, struct nand_header_info *info) - { - if (!strcmp((char *)ptr, NAND_BOOT_NAME)) - return mtk_nand_header_ap_info(ptr, info); -+ else if (!strncmp((char *)ptr, HSM_NAND_BOOT_NAME, 8)) -+ return mtk_nand_header_hsm_info(ptr, info); -+ else if (!strncmp((char *)ptr, SPIM_NAND_BOOT_NAME, 8)) -+ return mtk_nand_header_spim_info(ptr, info); - - return -1; - } -@@ -273,14 +595,74 @@ bool is_mtk_nand_header(const void *ptr) - return false; - } - --uint32_t mtk_nand_header_put(const union nand_boot_header *hdr_nand, void *ptr) -+static uint16_t crc16(const uint8_t *p, uint32_t len) -+{ -+ uint16_t crc = 0x4f4e; -+ uint32_t i; -+ -+ while (len--) { -+ crc ^= *p++ << 8; -+ for (i = 0; i < 8; i++) -+ crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0); -+ } -+ -+ return crc; -+} -+ -+static uint32_t mtk_nand_header_put_ap(const struct nand_header_type *hdr_nand, -+ void *ptr) - { -- union nand_boot_header *nh = (union nand_boot_header *)ptr; - int i; - - /* NAND device header, repeat 4 times */ -- for (i = 0; i < 4; i++) -- memcpy(nh + i, hdr_nand, sizeof(union nand_boot_header)); -+ for (i = 0; i < 4; i++) { -+ memcpy(ptr, hdr_nand->ap, sizeof(*hdr_nand->ap)); -+ ptr += sizeof(*hdr_nand->ap); -+ } -+ -+ return le16_to_cpu(hdr_nand->ap->pagesize); -+} - -- return le16_to_cpu(hdr_nand->pagesize); -+static uint32_t mtk_nand_header_put_hsm(const struct nand_header_type *hdr_nand, -+ void *ptr) -+{ -+ memcpy(ptr, hdr_nand->hsm, sizeof(*hdr_nand->hsm)); -+ return 0; -+} -+ -+static uint32_t mtk_nand_header_put_hsm20(const struct nand_header_type *hdr_nand, -+ void *ptr) -+{ -+ memcpy(ptr, hdr_nand->hsm20, sizeof(*hdr_nand->hsm20)); -+ return 0; -+} -+ -+static uint32_t mtk_nand_header_put_spim(const struct nand_header_type *hdr_nand, -+ void *ptr) -+{ -+ uint16_t crc; -+ -+ memcpy(ptr, hdr_nand->spim, sizeof(*hdr_nand->spim)); -+ -+ crc = crc16(ptr, 0x4e); -+ memcpy(ptr + 0x4e, &crc, sizeof(uint16_t)); -+ -+ return 0; -+} -+ -+uint32_t mtk_nand_header_put(const struct nand_header_type *hdr_nand, void *ptr) -+{ -+ switch (hdr_nand->type) { -+ case NAND_BOOT_HSM_HEADER: -+ return mtk_nand_header_put_hsm(hdr_nand, ptr); -+ -+ case NAND_BOOT_HSM20_HEADER: -+ return mtk_nand_header_put_hsm20(hdr_nand, ptr); -+ -+ case NAND_BOOT_SPIM_HEADER: -+ return mtk_nand_header_put_spim(hdr_nand, ptr); -+ -+ default: -+ return mtk_nand_header_put_ap(hdr_nand, ptr); -+ } - } ---- a/tools/mtk_nand_headers.h -+++ b/tools/mtk_nand_headers.h -@@ -16,6 +16,7 @@ struct nand_header_info { - uint32_t page_size; - uint32_t spare_size; - uint32_t gfh_offset; -+ bool snfi; - }; - - /* AP BROM Header for NAND */ -@@ -39,15 +40,117 @@ union nand_boot_header { - uint8_t data[0x80]; - }; - -+/* HSM BROM Header for NAND */ -+union hsm_nand_boot_header { -+ struct { -+ char id[8]; -+ uint32_t version; /* Header version */ -+ uint32_t config; /* Header config */ -+ uint32_t sector_size; /* ECC step size */ -+ uint32_t fdm_size; /* User OOB size of a step */ -+ uint32_t fdm_ecc_size; /* ECC parity size of a step */ -+ uint32_t lbs; -+ uint32_t page_size; /* NAND page size */ -+ uint32_t spare_size; /* NAND page spare size */ -+ uint32_t page_per_block; /* Pages of one block */ -+ uint32_t blocks; /* Total blocks of NAND chip */ -+ uint32_t plane_sel_position; /* Plane bit position */ -+ uint32_t pll; /* Value of pll reg */ -+ uint32_t acccon; /* Value of access timing reg */ -+ uint32_t strobe_sel; /* Value of DQS selection reg*/ -+ uint32_t acccon1; /* Value of access timing reg */ -+ uint32_t dqs_mux; /* Value of DQS mux reg */ -+ uint32_t dqs_ctrl; /* Value of DQS control reg */ -+ uint32_t delay_ctrl; /* Value of delay ctrl reg */ -+ uint32_t latch_lat; /* Value of latch latency reg */ -+ uint32_t sample_delay; /* Value of sample delay reg */ -+ uint32_t driving; /* Value of driving reg */ -+ uint32_t bl_start; /* Bootloader start addr */ -+ uint32_t bl_end; /* Bootloader end addr */ -+ uint8_t ecc_parity[42]; /* ECC parity of this header */ -+ }; -+ -+ uint8_t data[0x8E]; -+}; -+ -+/* HSM2.0 BROM Header for NAND */ -+union hsm20_nand_boot_header { -+ struct { -+ char id[8]; -+ uint32_t version; /* Header version */ -+ uint32_t config; /* Header config */ -+ uint32_t sector_size; /* ECC step size */ -+ uint32_t fdm_size; /* User OOB size of a step */ -+ uint32_t fdm_ecc_size; /* ECC parity size of a step */ -+ uint32_t lbs; -+ uint32_t page_size; /* NAND page size */ -+ uint32_t spare_size; /* NAND page spare size */ -+ uint32_t page_per_block; /* Pages of one block */ -+ uint32_t blocks; /* Total blocks of NAND chip */ -+ uint32_t plane_sel_position; /* Plane bit position */ -+ uint32_t pll; /* Value of pll reg */ -+ uint32_t acccon; /* Value of access timing reg */ -+ uint32_t strobe_sel; /* Value of DQS selection reg*/ -+ uint32_t acccon1; /* Value of access timing reg */ -+ uint32_t dqs_mux; /* Value of DQS mux reg */ -+ uint32_t dqs_ctrl; /* Value of DQS control reg */ -+ uint32_t delay_ctrl; /* Value of delay ctrl reg */ -+ uint32_t latch_lat; /* Value of latch latency reg */ -+ uint32_t sample_delay; /* Value of sample delay reg */ -+ uint32_t driving; /* Value of driving reg */ -+ uint32_t reserved; -+ uint32_t bl0_start; /* Bootloader start addr */ -+ uint32_t bl0_end; /* Bootloader end addr */ -+ uint32_t bl0_type; /* Bootloader type */ -+ uint8_t bl_reserve[84]; -+ uint8_t ecc_parity[42]; /* ECC parity of this header */ -+ }; -+ -+ uint8_t data[0xEA]; -+}; -+ -+/* SPIM BROM Header for SPI-NAND */ -+union spim_nand_boot_header { -+ struct { -+ char id[8]; -+ uint32_t version; /* Header version */ -+ uint32_t config; /* Header config */ -+ uint32_t page_size; /* NAND page size */ -+ uint32_t spare_size; /* NAND page spare size */ -+ uint16_t page_per_block; /* Pages of one block */ -+ uint16_t plane_sel_position; /* Plane bit position */ -+ uint16_t reserve_reg; -+ uint16_t reserve_val; -+ uint16_t ecc_error; /* ECC error reg addr */ -+ uint16_t ecc_mask; /* ECC error bit mask */ -+ uint32_t bl_start; /* Bootloader start addr */ -+ uint32_t bl_end; /* Bootloader end addr */ -+ uint8_t ecc_parity[32]; /* ECC parity of this header */ -+ uint32_t integrity_crc; /* CRC of this header */ -+ }; -+ -+ uint8_t data[0x50]; -+}; -+ -+enum nand_boot_header_type { -+ NAND_BOOT_AP_HEADER, -+ NAND_BOOT_HSM_HEADER, -+ NAND_BOOT_HSM20_HEADER, -+ NAND_BOOT_SPIM_HEADER -+}; -+ - #define NAND_BOOT_NAME "BOOTLOADER!" - #define NAND_BOOT_VERSION "V006" - #define NAND_BOOT_ID "NFIINFO" - -+#define HSM_NAND_BOOT_NAME "NANDCFG!" -+#define SPIM_NAND_BOOT_NAME "SPINAND!" -+ - /* Find nand header data by name */ --const union nand_boot_header *mtk_nand_header_find(const char *name); -+const struct nand_header_type *mtk_nand_header_find(const char *name); - - /* Device header size using this nand header */ --uint32_t mtk_nand_header_size(const union nand_boot_header *hdr_nand); -+uint32_t mtk_nand_header_size(const struct nand_header_type *hdr_nand); - - /* Get nand info from nand header (page size, spare size, ...) */ - int mtk_nand_header_info(const void *ptr, struct nand_header_info *info); -@@ -56,6 +159,7 @@ int mtk_nand_header_info(const void *ptr - bool is_mtk_nand_header(const void *ptr); - - /* Generate Device header using give nand header */ --uint32_t mtk_nand_header_put(const union nand_boot_header *hdr_nand, void *ptr); -+uint32_t mtk_nand_header_put(const struct nand_header_type *hdr_nand, -+ void *ptr); - - #endif /* _MTK_NAND_HEADERS_H */ diff --git a/package/boot/uboot-mediatek/patches/002-0032-MAINTAINERS-update-maintainer-for-MediaTek-ARM-platf.patch b/package/boot/uboot-mediatek/patches/002-0032-MAINTAINERS-update-maintainer-for-MediaTek-ARM-platf.patch deleted file mode 100644 index eacec0a8f7f..00000000000 --- a/package/boot/uboot-mediatek/patches/002-0032-MAINTAINERS-update-maintainer-for-MediaTek-ARM-platf.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 180f8ce7cac9277406ee702ea9390a6f78981bda Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 31 Aug 2022 19:05:28 +0800 -Subject: [PATCH 32/32] MAINTAINERS: update maintainer for MediaTek ARM - platform - -Add new files for MediaTek ARM platform - -Reviewed-by: Simon Glass -Signed-off-by: Weijie Gao ---- - MAINTAINERS | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -356,20 +356,26 @@ F: doc/device-tree-bindings/phy/phy-mtk- - F: doc/device-tree-bindings/usb/mediatek,* - F: doc/README.mediatek - F: drivers/clk/mediatek/ -+F: drivers/cpu/mtk_cpu.c -+F: drivers/i2c/mtk_i2c.c - F: drivers/mmc/mtk-sd.c - F: drivers/phy/phy-mtk-* - F: drivers/pinctrl/mediatek/ - F: drivers/power/domain/mtk-power-domain.c - F: drivers/ram/mediatek/ - F: drivers/spi/mtk_snfi_spi.c -+F: drivers/spi/mtk_spim.c - F: drivers/timer/mtk_timer.c - F: drivers/usb/host/xhci-mtk.c - F: drivers/usb/mtu3/ - F: drivers/watchdog/mtk_wdt.c - F: drivers/net/mtk_eth.c -+F: drivers/net/mtk_eth.h - F: drivers/reset/reset-mediatek.c - F: tools/mtk_image.c - F: tools/mtk_image.h -+F: tools/mtk_nand_headers.c -+F: tools/mtk_nand_headers.h - N: mediatek - - ARM METHODE SUPPORT diff --git a/package/boot/uboot-mediatek/patches/051-mt7986-enable-pstore.patch b/package/boot/uboot-mediatek/patches/051-mt7986-enable-pstore.patch index 15484bef559..d6ae7f0f139 100644 --- a/package/boot/uboot-mediatek/patches/051-mt7986-enable-pstore.patch +++ b/package/boot/uboot-mediatek/patches/051-mt7986-enable-pstore.patch @@ -1,6 +1,6 @@ --- a/arch/arm/dts/mt7986.dtsi +++ b/arch/arm/dts/mt7986.dtsi -@@ -46,6 +46,35 @@ +@@ -50,6 +50,35 @@ }; }; diff --git a/package/boot/uboot-mediatek/patches/100-01-board-mediatek-add-more-network-configurations.patch b/package/boot/uboot-mediatek/patches/100-01-board-mediatek-add-more-network-configurations.patch index 0ee01b227bc..f0486bdc47a 100644 --- a/package/boot/uboot-mediatek/patches/100-01-board-mediatek-add-more-network-configurations.patch +++ b/package/boot/uboot-mediatek/patches/100-01-board-mediatek-add-more-network-configurations.patch @@ -16,7 +16,7 @@ Signed-off-by: Weijie Gao --- a/include/configs/mt7622.h +++ b/include/configs/mt7622.h -@@ -23,6 +23,7 @@ +@@ -19,6 +19,7 @@ /* Ethernet */ #define CONFIG_IPADDR 192.168.1.1 @@ -27,7 +27,7 @@ Signed-off-by: Weijie Gao #endif --- a/include/configs/mt7623.h +++ b/include/configs/mt7623.h -@@ -37,6 +37,7 @@ +@@ -35,6 +35,7 @@ /* Ethernet */ #define CONFIG_IPADDR 192.168.1.1 #define CONFIG_SERVERIP 192.168.1.2 @@ -37,7 +37,7 @@ Signed-off-by: Weijie Gao --- a/include/configs/mt7629.h +++ b/include/configs/mt7629.h -@@ -32,5 +32,6 @@ +@@ -30,5 +30,6 @@ /* Ethernet */ #define CONFIG_IPADDR 192.168.1.1 #define CONFIG_SERVERIP 192.168.1.2 @@ -46,7 +46,7 @@ Signed-off-by: Weijie Gao #endif --- a/include/configs/mt7981.h +++ b/include/configs/mt7981.h -@@ -23,4 +23,9 @@ +@@ -18,4 +18,9 @@ /* DRAM */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 @@ -58,7 +58,7 @@ Signed-off-by: Weijie Gao #endif --- a/include/configs/mt7986.h +++ b/include/configs/mt7986.h -@@ -23,4 +23,9 @@ +@@ -18,4 +18,9 @@ /* DRAM */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 diff --git a/package/boot/uboot-mediatek/patches/100-02-drivers-mtd-add-support-for-MediaTek-SPI-NAND-flash-.patch b/package/boot/uboot-mediatek/patches/100-02-drivers-mtd-add-support-for-MediaTek-SPI-NAND-flash-.patch index 89cc0aa71eb..41d6950170b 100644 --- a/package/boot/uboot-mediatek/patches/100-02-drivers-mtd-add-support-for-MediaTek-SPI-NAND-flash-.patch +++ b/package/boot/uboot-mediatek/patches/100-02-drivers-mtd-add-support-for-MediaTek-SPI-NAND-flash-.patch @@ -1337,7 +1337,7 @@ Signed-off-by: Weijie Gao + instr->state = MTD_ERASING; + + while (start_addr < end_addr) { -+ WATCHDOG_RESET(); ++ schedule(); + + if (mtk_snand_block_isbad(msm->snf, start_addr)) { + if (!instr->scrub) { @@ -1390,7 +1390,7 @@ Signed-off-by: Weijie Gao + ops->retlen = 0; + + while (len || ooblen) { -+ WATCHDOG_RESET(); ++ schedule(); + + if (ops->mode == MTD_OPS_AUTO_OOB) + ret = mtk_snand_read_page_auto_oob(msm->snf, addr, @@ -1518,7 +1518,7 @@ Signed-off-by: Weijie Gao + ops->retlen = 0; + + while (len || ooblen) { -+ WATCHDOG_RESET(); ++ schedule(); + + if (len) { + /* Move data */ diff --git a/package/boot/uboot-mediatek/patches/100-03-mtd-mtk-snand-add-support-for-SPL.patch b/package/boot/uboot-mediatek/patches/100-03-mtd-mtk-snand-add-support-for-SPL.patch index ac56638ff74..3d7c4a9bf60 100644 --- a/package/boot/uboot-mediatek/patches/100-03-mtd-mtk-snand-add-support-for-SPL.patch +++ b/package/boot/uboot-mediatek/patches/100-03-mtd-mtk-snand-add-support-for-SPL.patch @@ -74,7 +74,7 @@ Signed-off-by: Weijie Gao + return -ENODEV; + + while (sizeremain) { -+ WATCHDOG_RESET(); ++ schedule(); + + leading = off & writesize_mask; + chunksize = cinfo.pagesize - leading; diff --git a/package/boot/uboot-mediatek/patches/100-04-env-add-support-for-generic-MTD-device.patch b/package/boot/uboot-mediatek/patches/100-04-env-add-support-for-generic-MTD-device.patch index 9bc5f58919f..7f3d497e457 100644 --- a/package/boot/uboot-mediatek/patches/100-04-env-add-support-for-generic-MTD-device.patch +++ b/package/boot/uboot-mediatek/patches/100-04-env-add-support-for-generic-MTD-device.patch @@ -93,7 +93,7 @@ Signed-off-by: Weijie Gao default 0x3f8000 if ARCH_ROCKCHIP && ENV_IS_IN_MMC default 0x140000 if ARCH_ROCKCHIP && ENV_IS_IN_SPI_FLASH default 0xF0000 if ARCH_SUNXI -@@ -599,6 +626,12 @@ config ENV_SECT_SIZE +@@ -600,6 +627,12 @@ config ENV_SECT_SIZE help Size of the sector containing the environment. @@ -399,7 +399,7 @@ Signed-off-by: Weijie Gao ENVL_ONENAND, --- a/tools/Makefile +++ b/tools/Makefile -@@ -41,6 +41,7 @@ ENVCRC-$(CONFIG_ENV_IS_EMBEDDED) = y +@@ -40,6 +40,7 @@ ENVCRC-$(CONFIG_ENV_IS_EMBEDDED) = y ENVCRC-$(CONFIG_ENV_IS_IN_EEPROM) = y ENVCRC-$(CONFIG_ENV_IS_IN_FLASH) = y ENVCRC-$(CONFIG_ENV_IS_IN_ONENAND) = y diff --git a/package/boot/uboot-mediatek/patches/100-06-mtd-add-core-facility-code-of-NMBM.patch b/package/boot/uboot-mediatek/patches/100-06-mtd-add-core-facility-code-of-NMBM.patch index 92a578a4857..7cc85e0718a 100644 --- a/package/boot/uboot-mediatek/patches/100-06-mtd-add-core-facility-code-of-NMBM.patch +++ b/package/boot/uboot-mediatek/patches/100-06-mtd-add-core-facility-code-of-NMBM.patch @@ -750,7 +750,7 @@ Signed-off-by: Weijie Gao + addr = ba2addr(ni, ba); + + for (off = 0; off < ni->lower.erasesize; off += ni->lower.writesize) { -+ WATCHDOG_RESET(); ++ schedule(); + + ret = nmbm_read_phys_page(ni, addr + off, ni->page_cache, NULL, + NMBM_MODE_PLACE_OOB); @@ -789,7 +789,7 @@ Signed-off-by: Weijie Gao + bool success; + + while (ba < limit) { -+ WATCHDOG_RESET(); ++ schedule(); + + if (nmbm_get_block_state(ni, ba) != BLOCK_ST_GOOD) + goto next_block; @@ -840,7 +840,7 @@ Signed-off-by: Weijie Gao + addr = ba2addr(ni, ba); + + for (off = 0; off < ni->lower.erasesize; off += ni->lower.writesize) { -+ WATCHDOG_RESET(); ++ schedule(); + + /* Prepare page data. fill 0xff to unused region */ + memcpy(ni->page_cache, data, size); @@ -884,7 +884,7 @@ Signed-off-by: Weijie Gao + bool success; + + while (ba > limit) { -+ WATCHDOG_RESET(); ++ schedule(); + + if (nmbm_get_block_state(ni, ba) != BLOCK_ST_GOOD) + goto next_block; @@ -939,7 +939,7 @@ Signed-off-by: Weijie Gao + int ret; + + while (sizeremain) { -+ WATCHDOG_RESET(); ++ schedule(); + + leading = off & ni->writesize_mask; + chunksize = ni->lower.writesize - leading; @@ -989,7 +989,7 @@ Signed-off-by: Weijie Gao + int ret; + + while (sizeremain) { -+ WATCHDOG_RESET(); ++ schedule(); + + leading = off & ni->writesize_mask; + chunksize = ni->lower.writesize - leading; @@ -1045,7 +1045,7 @@ Signed-off-by: Weijie Gao + bool success; + + while (sizeremain && ba < limit) { -+ WATCHDOG_RESET(); ++ schedule(); + + chunksize = sizeremain; + if (chunksize > ni->lower.erasesize) @@ -1307,7 +1307,7 @@ Signed-off-by: Weijie Gao + + /* Try to write new info table next to the existing table */ + while (write_ba >= ni->mapping_blocks_ba) { -+ WATCHDOG_RESET(); ++ schedule(); + + success = nmbm_write_info_table(ni, write_ba, + ni->mapping_blocks_top_ba, @@ -1426,7 +1426,7 @@ Signed-off-by: Weijie Gao + + /* Try to write temporary info table into spare unmapped blocks */ + while (write_ba >= ni->mapping_blocks_ba) { -+ WATCHDOG_RESET(); ++ schedule(); + + success = nmbm_write_info_table(ni, write_ba, + ni->mapping_blocks_top_ba, @@ -1512,7 +1512,7 @@ Signed-off-by: Weijie Gao + + /* Write new backup info table. */ + while (write_ba >= main_table_end_ba) { -+ WATCHDOG_RESET(); ++ schedule(); + + success = nmbm_write_info_table(ni, write_ba, + ni->mapping_blocks_top_ba, @@ -1901,7 +1901,7 @@ Signed-off-by: Weijie Gao + int ret; + + while (sizeremain && ba < limit) { -+ WATCHDOG_RESET(); ++ schedule(); + + if (nmbm_get_block_state(ni, ba) != BLOCK_ST_GOOD) + goto next_block; @@ -1994,7 +1994,7 @@ Signed-off-by: Weijie Gao + bool success; + + while (ba < limit - size2blk(ni, ni->info_table_size)) { -+ WATCHDOG_RESET(); ++ schedule(); + + success = nmbm_try_load_info_table(ni, ba, table_end_ba, + write_count, @@ -2206,7 +2206,7 @@ Signed-off-by: Weijie Gao + limit = block_count - ni->lower.max_reserved_blocks; + + while (ba >= limit) { -+ WATCHDOG_RESET(); ++ schedule(); + + ba--; + addr = ba2addr(ni, ba); @@ -2220,7 +2220,7 @@ Signed-off-by: Weijie Gao + */ + for (off = 0; off < ni->lower.erasesize; + off += ni->lower.writesize) { -+ WATCHDOG_RESET(); ++ schedule(); + + ret = nmbn_read_data(ni, addr + off, &sig, + sizeof(sig)); @@ -2592,7 +2592,7 @@ Signed-off-by: Weijie Gao + end_ba = addr2ba(ni, addr + size - 1); + + while (start_ba <= end_ba) { -+ WATCHDOG_RESET(); ++ schedule(); + + ret = nmbm_erase_logic_block(ni, start_ba); + if (ret) { @@ -2724,7 +2724,7 @@ Signed-off-by: Weijie Gao + } + + while (sizeremain) { -+ WATCHDOG_RESET(); ++ schedule(); + + leading = off & ni->writesize_mask; + chunksize = ni->lower.writesize - leading; @@ -2891,7 +2891,7 @@ Signed-off-by: Weijie Gao + } + + while (sizeremain) { -+ WATCHDOG_RESET(); ++ schedule(); + + leading = off & ni->writesize_mask; + chunksize = ni->lower.writesize - leading; diff --git a/package/boot/uboot-mediatek/patches/100-07-mtd-nmbm-add-support-for-mtd.patch b/package/boot/uboot-mediatek/patches/100-07-mtd-nmbm-add-support-for-mtd.patch index 644ac8f105c..718f00e7641 100644 --- a/package/boot/uboot-mediatek/patches/100-07-mtd-nmbm-add-support-for-mtd.patch +++ b/package/boot/uboot-mediatek/patches/100-07-mtd-nmbm-add-support-for-mtd.patch @@ -280,7 +280,7 @@ Signed-off-by: Weijie Gao + ops->retlen = 0; + + while (len || ooblen) { -+ WATCHDOG_RESET(); ++ schedule(); + + ret = nmbm_read_single_page(nm->ni, addr, datcache, oobcache, + mode); @@ -413,7 +413,7 @@ Signed-off-by: Weijie Gao + ops->retlen = 0; + + while (len || ooblen) { -+ WATCHDOG_RESET(); ++ schedule(); + + if (len) { + /* Move data */ diff --git a/package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch b/package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch index c49dd442f4a..1d8139e6726 100644 --- a/package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch +++ b/package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch @@ -13,7 +13,7 @@ Signed-off-by: Weijie Gao --- a/common/board_r.c +++ b/common/board_r.c -@@ -385,6 +385,20 @@ static int initr_nand(void) +@@ -388,6 +388,20 @@ static int initr_nand(void) } #endif @@ -34,7 +34,7 @@ Signed-off-by: Weijie Gao #if defined(CONFIG_CMD_ONENAND) /* go init the NAND */ static int initr_onenand(void) -@@ -697,6 +711,9 @@ static init_fnc_t init_sequence_r[] = { +@@ -703,6 +717,9 @@ static init_fnc_t init_sequence_r[] = { #ifdef CONFIG_CMD_ONENAND initr_onenand, #endif diff --git a/package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch b/package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch index 185414a884f..91c7a5b04fc 100644 --- a/package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch +++ b/package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch @@ -15,7 +15,7 @@ Signed-off-by: Weijie Gao --- a/cmd/Kconfig +++ b/cmd/Kconfig -@@ -1305,6 +1305,12 @@ config CMD_NAND_TORTURE +@@ -1342,6 +1342,12 @@ config CMD_NAND_TORTURE endif # CMD_NAND @@ -30,7 +30,7 @@ Signed-off-by: Weijie Gao depends on NVME --- a/cmd/Makefile +++ b/cmd/Makefile -@@ -114,6 +114,7 @@ obj-y += legacy-mtd-utils.o +@@ -125,6 +125,7 @@ obj-y += legacy-mtd-utils.o endif obj-$(CONFIG_CMD_MUX) += mux.o obj-$(CONFIG_CMD_NAND) += nand.o diff --git a/package/boot/uboot-mediatek/patches/100-10-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch b/package/boot/uboot-mediatek/patches/100-10-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch index 6e38ec4ac90..6336fb33f57 100644 --- a/package/boot/uboot-mediatek/patches/100-10-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch +++ b/package/boot/uboot-mediatek/patches/100-10-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch @@ -20,7 +20,7 @@ Signed-off-by: SkyLake.Huang --- a/cmd/mtd.c +++ b/cmd/mtd.c -@@ -492,6 +492,42 @@ out_put_mtd: +@@ -504,6 +504,42 @@ out_put_mtd: return CMD_RET_SUCCESS; } @@ -63,7 +63,7 @@ Signed-off-by: SkyLake.Huang #ifdef CONFIG_AUTO_COMPLETE static int mtd_name_complete(int argc, char *const argv[], char last_char, int maxv, char *cmdv[]) -@@ -540,6 +576,7 @@ static char mtd_help_text[] = +@@ -552,6 +588,7 @@ static char mtd_help_text[] = "\n" "Specific functions:\n" "mtd bad \n" @@ -71,7 +71,7 @@ Signed-off-by: SkyLake.Huang "\n" "With:\n" "\t: NAND partition/chip name (or corresponding DM device name or OF path)\n" -@@ -565,4 +602,6 @@ U_BOOT_CMD_WITH_SUBCMDS(mtd, "MTD utils" +@@ -577,4 +614,6 @@ U_BOOT_CMD_WITH_SUBCMDS(mtd, "MTD utils" U_BOOT_SUBCMD_MKENT_COMPLETE(erase, 4, 0, do_mtd_erase, mtd_name_complete), U_BOOT_SUBCMD_MKENT_COMPLETE(bad, 2, 1, do_mtd_bad, diff --git a/package/boot/uboot-mediatek/patches/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch b/package/boot/uboot-mediatek/patches/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch index 6af47f6eda2..2e07a583292 100644 --- a/package/boot/uboot-mediatek/patches/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch +++ b/package/boot/uboot-mediatek/patches/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch @@ -270,7 +270,7 @@ Signed-off-by: Weijie Gao ENVL_REMOTE, --- a/tools/Makefile +++ b/tools/Makefile -@@ -43,6 +43,7 @@ ENVCRC-$(CONFIG_ENV_IS_IN_FLASH) = y +@@ -42,6 +42,7 @@ ENVCRC-$(CONFIG_ENV_IS_IN_FLASH) = y ENVCRC-$(CONFIG_ENV_IS_IN_ONENAND) = y ENVCRC-$(CONFIG_ENV_IS_IN_MTD) = y ENVCRC-$(CONFIG_ENV_IS_IN_NAND) = y diff --git a/package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch b/package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch index 6aa57017634..86d1d774195 100644 --- a/package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch +++ b/package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch @@ -26,7 +26,7 @@ Signed-off-by: Weijie Gao --- a/cmd/Kconfig +++ b/cmd/Kconfig -@@ -1305,6 +1305,14 @@ config CMD_NAND_TORTURE +@@ -1342,6 +1342,14 @@ config CMD_NAND_TORTURE endif # CMD_NAND @@ -43,7 +43,7 @@ Signed-off-by: Weijie Gao bool "nmbm" --- a/cmd/Makefile +++ b/cmd/Makefile -@@ -114,6 +114,7 @@ obj-y += legacy-mtd-utils.o +@@ -125,6 +125,7 @@ obj-y += legacy-mtd-utils.o endif obj-$(CONFIG_CMD_MUX) += mux.o obj-$(CONFIG_CMD_NAND) += nand.o diff --git a/package/boot/uboot-mediatek/patches/100-14-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch b/package/boot/uboot-mediatek/patches/100-14-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch index 8696fc1f168..6be54b49474 100644 --- a/package/boot/uboot-mediatek/patches/100-14-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch +++ b/package/boot/uboot-mediatek/patches/100-14-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch @@ -13,7 +13,7 @@ Signed-off-by: Weijie Gao --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c -@@ -2791,6 +2791,100 @@ static int spi_nor_init_params(struct sp +@@ -2818,6 +2818,100 @@ static int spi_nor_init_params(struct sp return 0; } @@ -114,7 +114,7 @@ Signed-off-by: Weijie Gao static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size) { size_t i; -@@ -3858,6 +3952,7 @@ int spi_nor_scan(struct spi_nor *nor) +@@ -3901,6 +3995,7 @@ int spi_nor_scan(struct spi_nor *nor) nor->write = spi_nor_write_data; nor->read_reg = spi_nor_read_reg; nor->write_reg = spi_nor_write_reg; @@ -124,7 +124,7 @@ Signed-off-by: Weijie Gao --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h -@@ -28,6 +28,7 @@ +@@ -29,6 +29,7 @@ #define SNOR_MFR_SPANSION CFI_MFR_AMD #define SNOR_MFR_SST CFI_MFR_SST #define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */ @@ -132,7 +132,7 @@ Signed-off-by: Weijie Gao #define SNOR_MFR_CYPRESS 0x34 /* -@@ -558,6 +559,7 @@ struct spi_nor { +@@ -565,6 +566,7 @@ struct spi_nor { void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops); int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len); int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len); diff --git a/package/boot/uboot-mediatek/patches/100-15-cmd-sf-add-support-to-read-flash-unique-ID.patch b/package/boot/uboot-mediatek/patches/100-15-cmd-sf-add-support-to-read-flash-unique-ID.patch index e372944383a..6a4e6c3ca6e 100644 --- a/package/boot/uboot-mediatek/patches/100-15-cmd-sf-add-support-to-read-flash-unique-ID.patch +++ b/package/boot/uboot-mediatek/patches/100-15-cmd-sf-add-support-to-read-flash-unique-ID.patch @@ -12,7 +12,7 @@ Signed-off-by: Weijie Gao --- a/cmd/sf.c +++ b/cmd/sf.c -@@ -403,6 +403,14 @@ static int do_spi_protect(int argc, char +@@ -407,6 +407,14 @@ static int do_spi_protect(int argc, char return ret == 0 ? 0 : 1; } @@ -27,7 +27,7 @@ Signed-off-by: Weijie Gao enum { STAGE_ERASE, STAGE_CHECK, -@@ -599,6 +607,8 @@ static int do_spi_flash(struct cmd_tbl * +@@ -603,6 +611,8 @@ static int do_spi_flash(struct cmd_tbl * ret = do_spi_flash_erase(argc, argv); else if (strcmp(cmd, "protect") == 0) ret = do_spi_protect(argc, argv); @@ -36,7 +36,7 @@ Signed-off-by: Weijie Gao else if (IS_ENABLED(CONFIG_CMD_SF_TEST) && !strcmp(cmd, "test")) ret = do_spi_flash_test(argc, argv); else -@@ -629,7 +639,8 @@ static const char long_help[] = +@@ -633,7 +643,8 @@ static const char long_help[] = " at `addr' to flash at `offset'\n" " or to start of mtd `partition'\n" "sf protect lock/unlock sector len - protect/unprotect 'len' bytes starting\n" diff --git a/package/boot/uboot-mediatek/patches/100-16-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch b/package/boot/uboot-mediatek/patches/100-16-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch index ee45ff0de63..e0571671bcc 100644 --- a/package/boot/uboot-mediatek/patches/100-16-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch +++ b/package/boot/uboot-mediatek/patches/100-16-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch @@ -91,7 +91,7 @@ Signed-off-by: Weijie Gao default_str = env_get("bootmenu_default"); if (default_str) -@@ -356,9 +380,9 @@ static struct bootmenu_data *bootmenu_cr +@@ -366,9 +390,9 @@ static struct bootmenu_data *bootmenu_cr /* Add Quit entry if entering U-Boot console is disabled */ if (!IS_ENABLED(CONFIG_BOOTMENU_DISABLE_UBOOT_CONSOLE)) @@ -203,11 +203,7 @@ Signed-off-by: Weijie Gao case 1: --- a/include/menu.h +++ b/include/menu.h -@@ -2,10 +2,11 @@ - /* - * Copyright 2010-2011 Calxeda, Inc. - */ -- +@@ -6,6 +6,8 @@ #ifndef __MENU_H__ #define __MENU_H__ @@ -216,7 +212,7 @@ Signed-off-by: Weijie Gao struct menu; struct menu *menu_create(char *title, int timeout, int prompt, -@@ -18,6 +19,8 @@ int menu_get_choice(struct menu *m, void +@@ -18,6 +20,8 @@ int menu_get_choice(struct menu *m, void int menu_item_add(struct menu *m, char *item_key, void *item_data); int menu_destroy(struct menu *m); int menu_default_choice(struct menu *m, void **choice); @@ -225,7 +221,7 @@ Signed-off-by: Weijie Gao /** * menu_show() Show a boot menu -@@ -40,6 +43,7 @@ struct bootmenu_data { +@@ -40,6 +44,7 @@ struct bootmenu_data { int active; /* active menu entry */ int count; /* total count of menu entries */ struct bootmenu_entry *first; /* first menu entry */ @@ -233,10 +229,10 @@ Signed-off-by: Weijie Gao }; enum bootmenu_key { -@@ -48,11 +52,11 @@ enum bootmenu_key { - KEY_DOWN, - KEY_SELECT, - KEY_QUIT, +@@ -51,11 +56,12 @@ enum bootmenu_key { + KEY_PLUS, + KEY_MINUS, + KEY_SPACE, + KEY_CHOICE, }; @@ -245,6 +241,6 @@ Signed-off-by: Weijie Gao + enum bootmenu_key *key, int *esc, int *choice); void bootmenu_loop(struct bootmenu_data *menu, - enum bootmenu_key *key, int *esc); -- + enum bootmenu_key *key, int *esc, int *choice); + #endif /* __MENU_H__ */ diff --git a/package/boot/uboot-mediatek/patches/100-19-board-mt7622-use-new-spi-nand-driver.patch b/package/boot/uboot-mediatek/patches/100-19-board-mt7622-use-new-spi-nand-driver.patch index bb455d0b2bd..624da59d253 100644 --- a/package/boot/uboot-mediatek/patches/100-19-board-mt7622-use-new-spi-nand-driver.patch +++ b/package/boot/uboot-mediatek/patches/100-19-board-mt7622-use-new-spi-nand-driver.patch @@ -55,7 +55,7 @@ Signed-off-by: Weijie Gao reg = <0x11014000 0x1000>; --- a/configs/mt7622_rfb_defconfig +++ b/configs/mt7622_rfb_defconfig -@@ -20,6 +20,7 @@ CONFIG_SYS_MAXARGS=8 +@@ -21,6 +21,7 @@ CONFIG_SYS_MAXARGS=8 CONFIG_SYS_PBSIZE=1049 CONFIG_CMD_BOOTMENU=y CONFIG_CMD_MMC=y @@ -63,7 +63,7 @@ Signed-off-by: Weijie Gao CONFIG_CMD_PCI=y CONFIG_CMD_SF_TEST=y CONFIG_CMD_PING=y -@@ -35,6 +36,10 @@ CONFIG_SYSCON=y +@@ -36,6 +37,10 @@ CONFIG_SYSCON=y CONFIG_CLK=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_MMC_MTK=y diff --git a/package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch b/package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch index 2d10cd0ea95..ff327dd3b82 100644 --- a/package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch +++ b/package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch @@ -18,7 +18,7 @@ Signed-off-by: Weijie Gao --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -1234,6 +1234,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ +@@ -1266,6 +1266,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7623n-bananapi-bpi-r2.dtb \ mt7629-rfb.dtb \ mt7981-rfb.dtb \ diff --git a/package/boot/uboot-mediatek/patches/100-21-mtd-spi-nor-add-more-flash-ids.patch b/package/boot/uboot-mediatek/patches/100-21-mtd-spi-nor-add-more-flash-ids.patch index d30b051ec05..20a827141d1 100644 --- a/package/boot/uboot-mediatek/patches/100-21-mtd-spi-nor-add-more-flash-ids.patch +++ b/package/boot/uboot-mediatek/patches/100-21-mtd-spi-nor-add-more-flash-ids.patch @@ -13,7 +13,7 @@ Signed-off-by: Weijie Gao --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c -@@ -648,6 +648,7 @@ static int set_4byte(struct spi_nor *nor +@@ -672,6 +672,7 @@ static int set_4byte(struct spi_nor *nor case SNOR_MFR_ISSI: case SNOR_MFR_MACRONIX: case SNOR_MFR_WINBOND: @@ -45,7 +45,7 @@ Signed-off-by: Weijie Gao INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) -@@ -395,6 +401,16 @@ const struct flash_info spi_nor_ids[] = +@@ -398,6 +404,16 @@ const struct flash_info spi_nor_ids[] = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, { @@ -62,7 +62,7 @@ Signed-off-by: Weijie Gao INFO("w25q128jw", 0xef8018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) -@@ -439,6 +455,11 @@ const struct flash_info spi_nor_ids[] = +@@ -447,6 +463,11 @@ const struct flash_info spi_nor_ids[] = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, { INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, diff --git a/package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch b/package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch index 8f6e1c79cf5..5f1f2681504 100644 --- a/package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch +++ b/package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch @@ -15,7 +15,7 @@ Signed-off-by: Weijie Gao --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig -@@ -812,6 +812,14 @@ config MMC_MTK +@@ -818,6 +818,14 @@ config MMC_MTK This is needed if support for any SD/SDIO/MMC devices is required. If unsure, say N. diff --git a/package/boot/uboot-mediatek/patches/100-24-cmd-ubi-make-volume-find-create-remove-APIs-public.patch b/package/boot/uboot-mediatek/patches/100-24-cmd-ubi-make-volume-find-create-remove-APIs-public.patch index ba32fa869df..bfe27a482cd 100644 --- a/package/boot/uboot-mediatek/patches/100-24-cmd-ubi-make-volume-find-create-remove-APIs-public.patch +++ b/package/boot/uboot-mediatek/patches/100-24-cmd-ubi-make-volume-find-create-remove-APIs-public.patch @@ -14,7 +14,7 @@ Signed-off-by: Weijie Gao --- a/cmd/ubi.c +++ b/cmd/ubi.c -@@ -148,8 +148,8 @@ bad: +@@ -213,8 +213,8 @@ bad: return err; } @@ -25,7 +25,7 @@ Signed-off-by: Weijie Gao { struct ubi_mkvol_req req; int err; -@@ -182,7 +182,7 @@ static int ubi_create_vol(char *volume, +@@ -247,7 +247,7 @@ static int ubi_create_vol(char *volume, return ubi_create_volume(ubi, &req); } @@ -34,7 +34,7 @@ Signed-off-by: Weijie Gao { struct ubi_volume *vol = NULL; int i; -@@ -197,7 +197,7 @@ static struct ubi_volume *ubi_find_volum +@@ -262,7 +262,7 @@ static struct ubi_volume *ubi_find_volum return NULL; } diff --git a/package/boot/uboot-mediatek/patches/100-25-cmd-ubi-allow-creating-volume-with-all-free-spaces.patch b/package/boot/uboot-mediatek/patches/100-25-cmd-ubi-allow-creating-volume-with-all-free-spaces.patch index 1d62c05e40a..d023b004f76 100644 --- a/package/boot/uboot-mediatek/patches/100-25-cmd-ubi-allow-creating-volume-with-all-free-spaces.patch +++ b/package/boot/uboot-mediatek/patches/100-25-cmd-ubi-allow-creating-volume-with-all-free-spaces.patch @@ -12,7 +12,7 @@ Signed-off-by: Weijie Gao --- a/cmd/ubi.c +++ b/cmd/ubi.c -@@ -161,7 +161,11 @@ int ubi_create_vol(char *volume, int64_t +@@ -226,7 +226,11 @@ int ubi_create_vol(char *volume, int64_t req.vol_id = vol_id; req.alignment = 1; diff --git a/package/boot/uboot-mediatek/patches/100-26-env-ubi-add-support-to-create-environment-volume-if-.patch b/package/boot/uboot-mediatek/patches/100-26-env-ubi-add-support-to-create-environment-volume-if-.patch index bc164f4dd5d..4f47a01661c 100644 --- a/package/boot/uboot-mediatek/patches/100-26-env-ubi-add-support-to-create-environment-volume-if-.patch +++ b/package/boot/uboot-mediatek/patches/100-26-env-ubi-add-support-to-create-environment-volume-if-.patch @@ -14,7 +14,7 @@ Signed-off-by: Weijie Gao --- a/env/Kconfig +++ b/env/Kconfig -@@ -665,6 +665,12 @@ config ENV_UBI_VOLUME_REDUND +@@ -666,6 +666,12 @@ config ENV_UBI_VOLUME_REDUND help Name of the redundant volume that you want to store the environment in. diff --git a/package/boot/uboot-mediatek/patches/120-use-xz-instead-of-lzma.patch b/package/boot/uboot-mediatek/patches/120-use-xz-instead-of-lzma.patch index 9dca900fcf9..9f46fed4c9c 100644 --- a/package/boot/uboot-mediatek/patches/120-use-xz-instead-of-lzma.patch +++ b/package/boot/uboot-mediatek/patches/120-use-xz-instead-of-lzma.patch @@ -1,6 +1,6 @@ --- a/Makefile +++ b/Makefile -@@ -1062,7 +1062,7 @@ quiet_cmd_pad_cat = CAT $@ +@@ -1069,7 +1069,7 @@ quiet_cmd_pad_cat = CAT $@ cmd_pad_cat = $(cmd_objcopy) && $(append) || { rm -f $@; false; } quiet_cmd_lzma = LZMA $@ diff --git a/package/boot/uboot-mediatek/patches/130-fix-mkimage-host-build.patch b/package/boot/uboot-mediatek/patches/130-fix-mkimage-host-build.patch index 8b110a880f1..cd65c1321fc 100644 --- a/package/boot/uboot-mediatek/patches/130-fix-mkimage-host-build.patch +++ b/package/boot/uboot-mediatek/patches/130-fix-mkimage-host-build.patch @@ -1,6 +1,6 @@ --- a/tools/image-host.c +++ b/tools/image-host.c -@@ -1122,6 +1122,7 @@ static int fit_config_add_verification_d +@@ -1125,6 +1125,7 @@ static int fit_config_add_verification_d * 2) get public key (X509_get_pubkey) * 3) provide der format (d2i_RSAPublicKey) */ @@ -8,7 +8,7 @@ static int read_pub_key(const char *keydir, const void *name, unsigned char **pubkey, int *pubkey_len) { -@@ -1175,6 +1176,13 @@ err_cert: +@@ -1178,6 +1179,13 @@ err_cert: fclose(f); return ret; } diff --git a/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch b/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch index d725920aff4..3990f7df37b 100644 --- a/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch +++ b/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch @@ -1,6 +1,6 @@ --- a/cmd/bootm.c +++ b/cmd/bootm.c -@@ -256,6 +256,67 @@ U_BOOT_CMD( +@@ -259,6 +259,67 @@ U_BOOT_CMD( /* iminfo - print header info for a requested image */ /*******************************************************************/ #if defined(CONFIG_CMD_IMI) @@ -70,7 +70,7 @@ { --- a/boot/image-fit.c +++ b/boot/image-fit.c -@@ -2031,6 +2031,51 @@ static const char *fit_get_image_type_pr +@@ -2051,6 +2051,50 @@ static const char *fit_get_image_type_pr return "unknown"; } @@ -118,13 +118,12 @@ + return max_size; +} + -+ - int fit_image_load(bootm_headers_t *images, ulong addr, + int fit_image_load(struct bootm_headers *images, ulong addr, const char **fit_unamep, const char **fit_uname_configp, - int arch, int image_type, int bootstage_id, + int arch, int ph_type, int bootstage_id, --- a/include/image.h +++ b/include/image.h -@@ -955,6 +955,7 @@ int fit_parse_subimage(const char *spec, +@@ -1042,6 +1042,7 @@ int fit_parse_subimage(const char *spec, ulong *addr, const char **image_name); int fit_get_subimage_count(const void *fit, int images_noffset); diff --git a/package/boot/uboot-mediatek/patches/211-cmd-bootmenu-custom-title.patch b/package/boot/uboot-mediatek/patches/211-cmd-bootmenu-custom-title.patch index 72926ea2e7f..69a3a07b901 100644 --- a/package/boot/uboot-mediatek/patches/211-cmd-bootmenu-custom-title.patch +++ b/package/boot/uboot-mediatek/patches/211-cmd-bootmenu-custom-title.patch @@ -1,6 +1,6 @@ --- a/cmd/bootmenu.c +++ b/cmd/bootmenu.c -@@ -439,7 +439,11 @@ static void menu_display_statusline(stru +@@ -449,7 +449,11 @@ static void menu_display_statusline(stru printf(ANSI_CURSOR_POSITION, 1, 1); puts(ANSI_CLEAR_LINE); printf(ANSI_CURSOR_POSITION, 2, 3); @@ -13,7 +13,7 @@ puts(ANSI_CLEAR_LINE_TO_END); printf(ANSI_CURSOR_POSITION, 3, 1); puts(ANSI_CLEAR_LINE); -@@ -524,6 +528,7 @@ static enum bootmenu_ret bootmenu_show(i +@@ -534,6 +538,7 @@ static enum bootmenu_ret bootmenu_show(i return BOOTMENU_RET_FAIL; } @@ -23,7 +23,7 @@ goto cleanup; --- a/include/menu.h +++ b/include/menu.h -@@ -43,6 +43,7 @@ struct bootmenu_data { +@@ -44,6 +44,7 @@ struct bootmenu_data { int active; /* active menu entry */ int count; /* total count of menu entries */ struct bootmenu_entry *first; /* first menu entry */ diff --git a/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch b/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch index 171c9862f3a..f79d1376a3a 100644 --- a/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch +++ b/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch @@ -1,6 +1,6 @@ --- a/cmd/Kconfig +++ b/cmd/Kconfig -@@ -579,6 +579,12 @@ config CMD_ENV_EXISTS +@@ -591,6 +591,12 @@ config CMD_ENV_EXISTS Check if a variable is defined in the environment for use in shell scripting. diff --git a/package/boot/uboot-mediatek/patches/280-image-fdt-save-name-of-FIT-configuration-in-chosen-node.patch b/package/boot/uboot-mediatek/patches/280-image-fdt-save-name-of-FIT-configuration-in-chosen-node.patch index d3e6bc983d6..5a84598f901 100644 --- a/package/boot/uboot-mediatek/patches/280-image-fdt-save-name-of-FIT-configuration-in-chosen-node.patch +++ b/package/boot/uboot-mediatek/patches/280-image-fdt-save-name-of-FIT-configuration-in-chosen-node.patch @@ -16,7 +16,7 @@ Reviewed-by: Tom Rini --- a/boot/image-fdt.c +++ b/boot/image-fdt.c -@@ -636,6 +636,12 @@ int image_setup_libfdt(bootm_headers_t * +@@ -636,6 +636,12 @@ int image_setup_libfdt(struct bootm_head images->fit_uname_cfg, strlen(images->fit_uname_cfg) + 1, 1); diff --git a/package/boot/uboot-mediatek/patches/300-force-pylibfdt-build.patch b/package/boot/uboot-mediatek/patches/300-force-pylibfdt-build.patch index e84ba7c4edf..4abf13eda86 100644 --- a/package/boot/uboot-mediatek/patches/300-force-pylibfdt-build.patch +++ b/package/boot/uboot-mediatek/patches/300-force-pylibfdt-build.patch @@ -1,6 +1,6 @@ --- a/Makefile +++ b/Makefile -@@ -2032,26 +2032,7 @@ endif +@@ -2028,26 +2028,7 @@ endif # Check dtc and pylibfdt, if DTC is provided, else build them PHONY += scripts_dtc scripts_dtc: scripts_basic diff --git a/package/boot/uboot-mediatek/patches/400-update-bpir2-defconfig.patch b/package/boot/uboot-mediatek/patches/400-update-bpir2-defconfig.patch index 599c882c0bf..d064fe4363d 100644 --- a/package/boot/uboot-mediatek/patches/400-update-bpir2-defconfig.patch +++ b/package/boot/uboot-mediatek/patches/400-update-bpir2-defconfig.patch @@ -1,7 +1,7 @@ --- a/configs/mt7623n_bpir2_defconfig +++ b/configs/mt7623n_bpir2_defconfig -@@ -4,57 +4,142 @@ CONFIG_ARCH_MEDIATEK=y - CONFIG_SYS_TEXT_BASE=0x81e00000 +@@ -5,57 +5,142 @@ CONFIG_ARCH_MEDIATEK=y + CONFIG_TEXT_BASE=0x81e00000 CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x1000 diff --git a/package/boot/uboot-mediatek/patches/401-update-u7623-defconfig.patch b/package/boot/uboot-mediatek/patches/401-update-u7623-defconfig.patch index ff2c3af41f4..791be300503 100644 --- a/package/boot/uboot-mediatek/patches/401-update-u7623-defconfig.patch +++ b/package/boot/uboot-mediatek/patches/401-update-u7623-defconfig.patch @@ -1,7 +1,7 @@ --- a/configs/mt7623a_unielec_u7623_02_defconfig +++ b/configs/mt7623a_unielec_u7623_02_defconfig -@@ -4,55 +4,140 @@ CONFIG_ARCH_MEDIATEK=y - CONFIG_SYS_TEXT_BASE=0x81e00000 +@@ -5,55 +5,140 @@ CONFIG_ARCH_MEDIATEK=y + CONFIG_TEXT_BASE=0x81e00000 CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x1000 diff --git a/package/boot/uboot-mediatek/patches/404-add-bananapi_bpi-r64_defconfigs.patch b/package/boot/uboot-mediatek/patches/404-add-bananapi_bpi-r64_defconfigs.patch index 5bb444a18e5..8627b2ebafb 100644 --- a/package/boot/uboot-mediatek/patches/404-add-bananapi_bpi-r64_defconfigs.patch +++ b/package/boot/uboot-mediatek/patches/404-add-bananapi_bpi-r64_defconfigs.patch @@ -1,6 +1,6 @@ --- /dev/null +++ b/configs/mt7622_bananapi_bpi-r64-sdmmc_defconfig -@@ -0,0 +1,159 @@ +@@ -0,0 +1,160 @@ +CONFIG_ARM=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y @@ -8,6 +8,7 @@ +CONFIG_SYS_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_SYS_LOAD_ADDR=0x40080000 ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_USE_DEFAULT_ENV_FILE=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOOTP_SEND_HOSTNAME=y @@ -247,7 +248,7 @@ +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title $ver" --- /dev/null +++ b/configs/mt7622_bananapi_bpi-r64-emmc_defconfig -@@ -0,0 +1,146 @@ +@@ -0,0 +1,147 @@ +CONFIG_ARM=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y @@ -255,6 +256,7 @@ +CONFIG_SYS_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_SYS_LOAD_ADDR=0x40080000 ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_USE_DEFAULT_ENV_FILE=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOOTP_SEND_HOSTNAME=y @@ -455,13 +457,14 @@ +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title $ver" --- /dev/null +++ b/configs/mt7622_bananapi_bpi-r64-snand_defconfig -@@ -0,0 +1,140 @@ +@@ -0,0 +1,141 @@ +CONFIG_ARM=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_SYS_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_SYS_LOAD_ADDR=0x40080000 ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_USE_DEFAULT_ENV_FILE=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOOTP_SEND_HOSTNAME=y diff --git a/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch b/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch index fd302bd0853..13d9a3c7505 100644 --- a/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch +++ b/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch @@ -1,6 +1,6 @@ --- /dev/null +++ b/configs/mt7622_linksys_e8450_defconfig -@@ -0,0 +1,136 @@ +@@ -0,0 +1,137 @@ +CONFIG_ARM=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y @@ -126,6 +126,7 @@ +CONFIG_MTK_SPI_NAND=y +CONFIG_MTK_SPI_NAND_MTD=y +CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_WDT_MTK=y +CONFIG_LZO=y +CONFIG_ZSTD=y @@ -335,7 +336,7 @@ +}; --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -1231,6 +1231,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ +@@ -1263,6 +1263,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7622-rfb.dtb \ mt7623a-unielec-u7623-02-emmc.dtb \ mt7622-bananapi-bpi-r64.dtb \ diff --git a/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch b/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch index 3e7dacc3b38..6c35e078702 100644 --- a/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch +++ b/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch @@ -1,6 +1,6 @@ --- /dev/null +++ b/configs/mt7622_ubnt_unifi-6-lr_defconfig -@@ -0,0 +1,142 @@ +@@ -0,0 +1,143 @@ +CONFIG_ARM=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y @@ -143,6 +143,7 @@ +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_USE_4K_SECTORS=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y --- /dev/null +++ b/arch/arm/dts/mt7622-ubnt-unifi-6-lr.dts @@ -0,0 +1,187 @@ @@ -335,7 +336,7 @@ +}; --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -1232,6 +1232,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ +@@ -1264,6 +1264,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7623a-unielec-u7623-02-emmc.dtb \ mt7622-bananapi-bpi-r64.dtb \ mt7622-linksys-e8450-ubi.dtb \ @@ -398,7 +399,7 @@ +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title $ver" --- a/common/board_r.c +++ b/common/board_r.c -@@ -65,6 +65,7 @@ +@@ -66,6 +66,7 @@ #include #include #include @@ -406,7 +407,7 @@ DECLARE_GLOBAL_DATA_PTR; -@@ -409,6 +410,20 @@ static int initr_onenand(void) +@@ -412,6 +413,20 @@ static int initr_onenand(void) } #endif @@ -427,7 +428,7 @@ #ifdef CONFIG_MMC static int initr_mmc(void) { -@@ -714,6 +729,9 @@ static init_fnc_t init_sequence_r[] = { +@@ -720,6 +735,9 @@ static init_fnc_t init_sequence_r[] = { #ifdef CONFIG_NMBM_MTD initr_nmbm, #endif diff --git a/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch b/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch index cad24409b20..7bde3f17c3b 100644 --- a/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch +++ b/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch @@ -1,6 +1,6 @@ --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -1239,6 +1239,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ +@@ -1271,6 +1271,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7981-snfi-nand-rfb.dtb \ mt7981-emmc-rfb.dtb \ mt7981-sd-rfb.dtb \ @@ -11,13 +11,14 @@ mt7986a-sd-rfb.dtb \ --- /dev/null +++ b/configs/mt7986a_bpi-r3-emmc_defconfig -@@ -0,0 +1,193 @@ +@@ -0,0 +1,194 @@ +CONFIG_ARM=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_TARGET_MT7986=y +CONFIG_SYS_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="mt7986a-bpi-r3-emmc" +CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3_emmc_env" @@ -207,13 +208,14 @@ +CONFIG_LMB_MAX_REGIONS=64 --- /dev/null +++ b/configs/mt7986a_bpi-r3-nor_defconfig -@@ -0,0 +1,192 @@ +@@ -0,0 +1,193 @@ +CONFIG_ARM=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_TARGET_MT7986=y +CONFIG_SYS_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="mt7986a-bpi-r3-emmc" +CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3_nor_env" @@ -402,13 +404,14 @@ +CONFIG_LMB_MAX_REGIONS=64 --- /dev/null +++ b/configs/mt7986a_bpi-r3-sd_defconfig -@@ -0,0 +1,193 @@ +@@ -0,0 +1,194 @@ +CONFIG_ARM=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_TARGET_MT7986=y +CONFIG_SYS_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="mt7986a-bpi-r3-sd" +CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3_sdmmc_env" @@ -598,13 +601,14 @@ +CONFIG_LMB_MAX_REGIONS=64 --- /dev/null +++ b/configs/mt7986a_bpi-r3-snand_defconfig -@@ -0,0 +1,194 @@ +@@ -0,0 +1,195 @@ +CONFIG_ARM=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_TARGET_MT7986=y +CONFIG_SYS_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="mt7986a-bpi-r3-emmc" +CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3_snand_env" diff --git a/package/boot/uboot-mediatek/patches/431-add-xiaomi_redmi-ax6000.patch b/package/boot/uboot-mediatek/patches/431-add-xiaomi_redmi-ax6000.patch index 7628c6637c8..26c4e146612 100644 --- a/package/boot/uboot-mediatek/patches/431-add-xiaomi_redmi-ax6000.patch +++ b/package/boot/uboot-mediatek/patches/431-add-xiaomi_redmi-ax6000.patch @@ -1,12 +1,13 @@ --- /dev/null +++ b/configs/mt7986_xiaomi_redmi-ax6000_defconfig -@@ -0,0 +1,175 @@ +@@ -0,0 +1,176 @@ +CONFIG_ARM=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_TARGET_MT7986=y +CONFIG_SYS_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="mt7986a-xiaomi_redmi-ax6000" +CONFIG_DEFAULT_ENV_FILE="xiaomi_redmi-ax6000_env"