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Merge branch 'openwrt:master' into master

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Hayzam Sherif 2023-11-28 16:48:22 +05:30 committed by GitHub
commit 49d1621eb2
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GPG key ID: 4AEE18F83AFDEB23
981 changed files with 17615 additions and 14197 deletions
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25
include/image-commands.mk
View file

@ -133,6 +133,8 @@ define Build/append-md5sum-ascii-salted
rm $@.salted
endef
UBI_NAND_SIZE_LIMIT = $(IMAGE_SIZE) - ($(NAND_SIZE)*20/1024 + 4*$(BLOCKSIZE))
define Build/append-ubi
sh $(TOPDIR)/scripts/ubinize-image.sh \
$(if $(UBOOTENV_IN_UBI),--uboot-env) \
@ -146,6 +148,8 @@ define Build/append-ubi
$(UBINIZE_OPTS)
cat $@.tmp >> $@
rm $@.tmp
$(if $(and $(IMAGE_SIZE),$(NAND_SIZE)),\
$(call Build/check-size,$(UBI_NAND_SIZE_LIMIT)))
endef
define Build/ubinize-kernel
@ -215,7 +219,7 @@ endef
define Build/check-size
@imagesize="$$(stat -c%s $@)"; \
limitsize="$$(($(subst k,* 1024,$(subst m, * 1024k,$(if $(1),$(1),$(IMAGE_SIZE))))))"; \
limitsize="$$(($(call exp_units,$(if $(1),$(1),$(IMAGE_SIZE)))))"; \
[ $$limitsize -ge $$imagesize ] || { \
$(call ERROR_MESSAGE, WARNING: Image file $@ is too big: $$imagesize > $$limitsize); \
rm -f $@; \
@ -389,10 +393,17 @@ define Build/kernel-bin
endef
define Build/linksys-image
$(TOPDIR)/scripts/linksys-image.sh \
let \
size="$$(stat -c%s $@)" \
pad="$(call exp_units,$(PAGESIZE))" \
offset="256" \
pad="(pad - ((size + offset) % pad)) % pad"; \
dd if=/dev/zero bs=$$pad count=1 | tr '\000' '\377' >> $@
printf ".LINKSYS.01000409%-15s%08X%-8s%-16s" \
"$(call param_get_default,type,$(1),$(DEVICE_NAME))" \
$@ $@.new
mv $@.new $@
"$$(cksum $@ | cut -d ' ' -f1)" \
"0" "K0000000F0246434" >> $@
dd if=/dev/zero bs=192 count=1 >> $@
endef
define Build/lzma
@ -466,8 +477,8 @@ endef
define Build/pad-offset
let \
size="$$(stat -c%s $@)" \
pad="$(subst k,* 1024,$(word 1, $(1)))" \
offset="$(subst k,* 1024,$(word 2, $(1)))" \
pad="$(call exp_units,$(word 1, $(1)))" \
offset="$(call exp_units,$(word 2, $(1)))" \
pad="(pad - ((size + offset) % pad)) % pad" \
newsize='size + pad'; \
dd if=$@ of=$@.new bs=$$newsize count=1 conv=sync
@ -629,7 +640,7 @@ endef
define Build/zyxel-ras-image
let \
newsize="$(subst k,* 1024,$(RAS_ROOTFS_SIZE))"; \
newsize="$(call exp_units,$(RAS_ROOTFS_SIZE))"; \
$(STAGING_DIR_HOST)/bin/mkrasimage \
-b $(RAS_BOARD) \
-v $(RAS_VERSION) \

5
include/image.mk
View file

@ -20,6 +20,8 @@ include $(INCLUDE_DIR)/rootfs.mk
override MAKE:=$(_SINGLE)$(SUBMAKE)
override NO_TRACE_MAKE:=$(_SINGLE)$(NO_TRACE_MAKE)
exp_units = $(subst k, * 1024,$(subst m, * 1024k,$(subst g, * 1024m,$(1))))
target_params = $(subst +,$(space),$*)
param_get = $(patsubst $(1)=%,%,$(filter $(1)=%,$(2)))
param_get_default = $(firstword $(call param_get,$(1),$(2)) $(3))
@ -395,6 +397,7 @@ define Device/Init
DEVICE_IMG_NAME = $$(DEVICE_IMG_PREFIX)-$$(1)-$$(2)
FACTORY_IMG_NAME :=
IMAGE_SIZE :=
NAND_SIZE :=
KERNEL_PREFIX = $$(DEVICE_IMG_PREFIX)
KERNEL_SUFFIX := -kernel.bin
KERNEL_INITRAMFS_SUFFIX = $$(KERNEL_SUFFIX)
@ -455,7 +458,7 @@ DEFAULT_DEVICE_VARS := \
DEVICE_DTS_DIR DEVICE_DTS_OVERLAY DEVICE_DTS_LOADADDR \
DEVICE_FDT_NUM DEVICE_IMG_PREFIX SOC BOARD_NAME UIMAGE_MAGIC UIMAGE_NAME \
UIMAGE_TIME SUPPORTED_DEVICES IMAGE_METADATA KERNEL_ENTRY KERNEL_LOADADDR \
UBOOT_PATH IMAGE_SIZE \
UBOOT_PATH IMAGE_SIZE NAND_SIZE \
FACTORY_IMG_NAME FACTORY_SIZE \
DEVICE_PACKAGES DEVICE_COMPAT_VERSION DEVICE_COMPAT_MESSAGE \
DEVICE_VENDOR DEVICE_MODEL DEVICE_VARIANT \

31
include/u-boot.mk
View file

@ -1,3 +1,5 @@
include $(INCLUDE_DIR)/prereq.mk
PKG_NAME ?= u-boot
ifndef PKG_SOURCE_PROTO
@ -18,6 +20,31 @@ PKG_LICENSE_FILES:=Licenses/README
PKG_BUILD_PARALLEL ?= 1
ifdef UBOOT_USE_BINMAN
$(eval $(call TestHostCommand,python3-pyelftools, \
Please install the Python3 elftools module, \
$(STAGING_DIR_HOST)/bin/python3 -c 'import elftools'))
endif
ifdef UBOOT_USE_INTREE_DTC
$(eval $(call TestHostCommand,python3-dev, \
Please install the python3-dev package, \
python3.11-config --includes 2>&1 | grep 'python3', \
python3.10-config --includes 2>&1 | grep 'python3', \
python3.9-config --includes 2>&1 | grep 'python3', \
python3.8-config --includes 2>&1 | grep 'python3', \
python3.7-config --includes 2>&1 | grep 'python3', \
python3-config --includes 2>&1 | grep -E 'python3\.([7-9]|[0-9][0-9])\.?'))
$(eval $(call TestHostCommand,python3-setuptools, \
Please install the Python3 setuptools module, \
$(STAGING_DIR_HOST)/bin/python3 -c 'import setuptools'))
$(eval $(call TestHostCommand,swig, \
Please install the swig package, \
swig -version))
endif
export GCC_HONOUR_COPTS=s
define Package/u-boot/install/default
@ -88,7 +115,9 @@ define Build/Configure/U-Boot
+$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) $(UBOOT_CONFIGURE_VARS) oldconfig)
endef
DTC=$(wildcard $(LINUX_DIR)/scripts/dtc/dtc)
ifndef UBOOT_USE_INTREE_DTC
DTC=$(wildcard $(LINUX_DIR)/scripts/dtc/dtc)
endif
define Build/Compile/U-Boot
+$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) \

10
package/boot/arm-trusted-firmware-mediatek/Makefile
View file

@ -191,6 +191,15 @@ define Trusted-Firmware-A/mt7986-spim-nand-ddr4
NAND_TYPE:=spim:2k+64
endef
define Trusted-Firmware-A/mt7986-spim-nand-4k-ddr4
NAME:=MediaTek MT7986 (SPI-NAND via SPIM, DDR4)
BOOT_DEVICE:=spim-nand
BUILD_SUBTARGET:=filogic
PLAT:=mt7986
DDR_TYPE:=ddr4
NAND_TYPE:=spim:4k+256
endef
define Trusted-Firmware-A/mt7986-nor-ddr3
NAME:=MediaTek MT7986 (SPI-NOR, DDR3)
BOOT_DEVICE:=nor
@ -377,6 +386,7 @@ TFA_TARGETS:= \
mt7986-sdmmc-ddr4 \
mt7986-snand-ddr4 \
mt7986-spim-nand-ddr4 \
mt7986-spim-nand-4k-ddr4 \
mt7988-emmc-ddr3 \
mt7988-nor-ddr3 \
mt7988-sdmmc-ddr3 \

47
package/boot/rkbin/Makefile Normal file
View file

@ -0,0 +1,47 @@
# SPDX-License-Identifier: GPL-2.0-only
#
# Copyright (C) 2021-2023 ImmortalWrt.org
include $(TOPDIR)/rules.mk
PKG_NAME:=rkbin
PKG_RELEASE:=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=https://github.com/rockchip-linux/rkbin.git
PKG_SOURCE_DATE:=2023-07-26
PKG_SOURCE_VERSION:=b4558da0860ca48bf1a571dd33ccba580b9abe23
PKG_MIRROR_HASH:=5842fbcb7e217c336235573e431e427f2f745390d989f6765a6c258a5bdf1b6e
PKG_LICENSE_FILES:=LICENSE
PKG_MAINTAINER:=Tianling Shen <cnsztl@immortalwrt.org>
include $(INCLUDE_DIR)/kernel.mk
include $(INCLUDE_DIR)/trusted-firmware-a.mk
include $(INCLUDE_DIR)/package.mk
define Trusted-Firmware-A/Default
NAME:=Rockchip $(1) SoCs
BUILD_TARGET:=rockchip
endef
define Trusted-Firmware-A/rk3568
BUILD_SUBTARGET:=armv8
ATF:=rk35/rk3568_bl31_v1.43.elf
TPL:=rk35/rk3568_ddr_1560MHz_v1.18.bin
endef
TFA_TARGETS:= \
rk3568
define Build/Compile
endef
define Package/trusted-firmware-a/install
$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
$(CP) $(PKG_BUILD_DIR)/bin/$(ATF) $(STAGING_DIR_IMAGE)/
$(CP) $(PKG_BUILD_DIR)/bin/$(TPL) $(STAGING_DIR_IMAGE)/
endef
$(eval $(call BuildPackage/Trusted-Firmware-A))

1
package/boot/uboot-envtools/files/ath79
View file

@ -31,6 +31,7 @@ asus,zenwifi-cd6n|\
asus,zenwifi-cd6r|\
buffalo,bhr-4grv2|\
devolo,magic-2-wifi|\
dlink,dap-1720-a1|\
dlink,dir-859-a1|\
dlink,dir-859-a3|\
dlink,dir-869-a1|\

52
package/boot/uboot-envtools/files/mediatek_filogic
View file

@ -54,31 +54,11 @@ cmcc,rax3000m)
;;
esac
;;
glinet,gl-mt3000)
ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x80000" "0x20000"
;;
glinet,gl-mt6000)
local envdev=$(find_mmc_part "u-boot-env")
ubootenv_add_uci_config "$envdev" "0x0" "0x80000"
;;
mercusys,mr90x-v1)
local envdev=/dev/mtd$(find_mtd_index "u-boot-env")
ubootenv_add_uci_config "$envdev" "0x0" "0x20000" "0x20000" "1"
;;
cetron,ct3003|\
netgear,wax220|\
zbtlink,zbt-z8102ax)
ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x20000" "0x20000"
;;
ubnt,unifi-6-plus)
ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x80000" "0x10000"
;;
xiaomi,mi-router-wr30u-112m-nmbm|\
xiaomi,mi-router-wr30u-stock|\
xiaomi,redmi-router-ax6000-stock)
ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x10000" "0x20000"
ubootenv_add_uci_sys_config "/dev/mtd2" "0x0" "0x10000" "0x20000"
;;
h3c,magic-nx30-pro|\
jcg,q30-pro|\
qihoo,360t7|\
@ -94,10 +74,42 @@ xiaomi,redmi-router-ax6000-ubootmod)
ubootenv_add_uci_config "$envdev" "0x0" "0x1f000" "0x20000" "1"
ubootenv_add_uci_config "$envdev2" "0x0" "0x1f000" "0x20000" "1"
;;
glinet,gl-mt2500)
local envdev=$(find_mmc_part "u-boot-env")
ubootenv_add_uci_config "$envdev" "0x400000" "0x80000"
;;
glinet,gl-mt3000)
ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x80000" "0x20000"
;;
glinet,gl-mt6000)
local envdev=$(find_mmc_part "u-boot-env")
ubootenv_add_uci_config "$envdev" "0x0" "0x80000"
;;
mercusys,mr90x-v1)
local envdev=/dev/mtd$(find_mtd_index "u-boot-env")
ubootenv_add_uci_config "$envdev" "0x0" "0x20000" "0x20000" "1"
;;
ubnt,unifi-6-plus)
ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x80000" "0x10000"
;;
xiaomi,mi-router-wr30u-112m-nmbm|\
xiaomi,mi-router-wr30u-stock|\
xiaomi,redmi-router-ax6000-stock)
ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x10000" "0x20000"
ubootenv_add_uci_sys_config "/dev/mtd2" "0x0" "0x10000" "0x20000"
;;
zyxel,ex5601-t0)
local envdev=/dev/mtd$(find_mtd_index "u-boot-env")
ubootenv_add_uci_config "$envdev" "0x0" "0x20000" "0x40000" "2"
;;
zyxel,ex5601-t0-ubootmod)
. /lib/upgrade/nand.sh
local envubi=$(nand_find_ubi ubi)
local envdev=/dev/$(nand_find_volume $envubi ubootenv)
local envdev2=/dev/$(nand_find_volume $envubi ubootenv2)
ubootenv_add_uci_config "$envdev" "0x0" "0x1f000" "0x20000" "1"
ubootenv_add_uci_config "$envdev2" "0x0" "0x1f000" "0x20000" "1"
;;
zyxel,ex5700-telenor)
ubootenv_add_uci_config "/dev/ubootenv" "0x0" "0x4000" "0x4000" "1"
;;

15
package/boot/uboot-mediatek/Makefile
View file

@ -5,6 +5,8 @@ PKG_VERSION:=2023.07.02
PKG_HASH:=6b6a48581c14abb0f95bd87c1af4d740922406d7b801002a9f94727fdde021d5
PKG_BUILD_DEPENDS:=!(TARGET_ramips||TARGET_mediatek_mt7623):arm-trusted-firmware-tools/host
UBOOT_USE_INTREE_DTC:=1
include $(INCLUDE_DIR)/u-boot.mk
include $(INCLUDE_DIR)/package.mk
include $(INCLUDE_DIR)/host-build.mk
@ -453,6 +455,18 @@ define U-Boot/mt7986_xiaomi_redmi-router-ax6000
DEPENDS:=+trusted-firmware-a-mt7986-spim-nand-ddr4
endef
define U-Boot/mt7986_zyxel_ex5601-t0
NAME:=Zyxel EX5601-T0
BUILD_SUBTARGET:=filogic
BUILD_DEVICES:=zyxel_ex5601-t0-ubootmod
UBOOT_CONFIG:=mt7986_zyxel_ex5601-t0
UBOOT_IMAGE:=u-boot.fip
BL2_BOOTDEV:=spim-nand-4k
BL2_SOC:=mt7986
BL2_DDRTYPE:=ddr4
DEPENDS:=+trusted-firmware-a-mt7986-spim-nand-4k-ddr4
endef
define U-Boot/mt7988_rfb-spim-nand
NAME:=MT7988 Reference Board
BUILD_SUBTARGET:=filogic
@ -552,6 +566,7 @@ UBOOT_TARGETS := \
mt7986_tplink_tl-xdr6086 \
mt7986_tplink_tl-xdr6088 \
mt7986_xiaomi_redmi-router-ax6000 \
mt7986_zyxel_ex5601-t0 \
mt7986_rfb \
mt7988_rfb-spim-nand \
mt7988_rfb-snand \

30
package/boot/uboot-mediatek/patches/300-force-pylibfdt-build.patch
View file

@ -1,30 +0,0 @@
--- a/Makefile
+++ b/Makefile
@@ -2006,26 +2006,7 @@ endif
# Check dtc and pylibfdt, if DTC is provided, else build them
PHONY += scripts_dtc
scripts_dtc: scripts_basic
- $(Q)if test "$(DTC)" = "$(DTC_INTREE)"; then \
- $(MAKE) $(build)=scripts/dtc; \
- else \
- if ! $(DTC) -v >/dev/null; then \
- echo '*** Failed to check dtc version: $(DTC)'; \
- false; \
- else \
- if test "$(call dtc-version)" -lt $(DTC_MIN_VERSION); then \
- echo '*** Your dtc is too old, please upgrade to dtc $(DTC_MIN_VERSION) or newer'; \
- false; \
- else \
- if [ -n "$(CONFIG_PYLIBFDT)" ]; then \
- if ! echo "import libfdt" | $(PYTHON3) 2>/dev/null; then \
- echo '*** pylibfdt does not seem to be available with $(PYTHON3)'; \
- false; \
- fi; \
- fi; \
- fi; \
- fi; \
- fi
+ $(MAKE) $(build)=scripts/dtc
# ---------------------------------------------------------------------------
quiet_cmd_cpp_lds = LDS $@

431
package/boot/uboot-mediatek/patches/439-add-zyxel_ex5601-t0.patch Normal file
View file

@ -0,0 +1,431 @@
--- /dev/null
+++ b/configs/mt7986_zyxel_ex5601-t0_defconfig
@@ -0,0 +1,186 @@
+CONFIG_ARM=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_TARGET_MT7986=y
+CONFIG_TEXT_BASE=0x41e00000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="mt7986a-zyxel_ex5601-t0"
+CONFIG_DEFAULT_ENV_FILE="zyxel_ex5601-t0_env"
+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-zyxel_ex5601-t0.dtb"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DEBUG_UART_BASE=0x11002000
+CONFIG_DEBUG_UART_CLOCK=40000000
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x46000000
+CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_BOOTDELAY=30
+CONFIG_AUTOBOOT_MENU_SHOW=y
+CONFIG_CFB_CONSOLE_ANSI=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_GPIO=y
+CONFIG_GPIO_HOG=y
+CONFIG_CMD_ENV_FLAGS=y
+CONFIG_FIT=y
+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
+CONFIG_LED=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
+CONFIG_LOGLEVEL=7
+CONFIG_LOG=y
+CONFIG_SYS_PROMPT="EX5601> "
+CONFIG_CMD_BOOTMENU=y
+CONFIG_CMD_BOOTP=y
+CONFIG_CMD_BUTTON=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_CPU=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_ECHO=y
+CONFIG_CMD_ENV_READMEM=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FDT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_FS_UUID=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_ITEST=y
+CONFIG_CMD_LED=y
+CONFIG_CMD_LICENSE=y
+CONFIG_CMD_LINK_LOCAL=y
+# CONFIG_CMD_MBR is not set
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_PSTORE=y
+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_PXE=y
+CONFIG_CMD_PWM=y
+CONFIG_CMD_SMC=y
+CONFIG_CMD_TFTPBOOT=y
+CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_UBI=y
+CONFIG_CMD_UBI_RENAME=y
+CONFIG_CMD_UBIFS=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_SETEXPR=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_SOURCE=y
+CONFIG_CMD_STRINGS=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_UUID=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DM_MTD=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_USB=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MTK=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_PARTITION_UUIDS=y
+CONFIG_NETCONSOLE=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_SCSI=y
+CONFIG_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SCSI=y
+CONFIG_CMD_SCSI=y
+CONFIG_PHY=y
+CONFIG_PHY_MTK_TPHY=y
+CONFIG_PHY_FIXED=y
+CONFIG_MTK_AHCI=y
+CONFIG_DM_ETH=y
+CONFIG_MEDIATEK_ETH=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCIE_MEDIATEK=y
+# CONFIG_MMC is not set
+# CONFIG_DM_MMC is not set
+CONFIG_MTD=y
+CONFIG_MTD_UBI_FASTMAP=y
+# CONFIG_DM_PCI is not set
+# CONFIG_PCIE_MEDIATEK is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MT7622=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_PRE_CONSOLE_BUFFER=y
+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
+CONFIG_MTK_POWER_DOMAIN=y
+CONFIG_RAM=y
+CONFIG_DM_SERIAL=y
+CONFIG_MTK_SERIAL=y
+CONFIG_SPI=y
+# CONFIG_I2C is not set
+CONFIG_DM_SPI=y
+CONFIG_MTK_SPI_NAND=y
+CONFIG_MTK_SPI_NAND_MTD=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_WDT_MTK=y
+CONFIG_LZO=y
+CONFIG_ZSTD=y
+CONFIG_HEXDUMP=y
+CONFIG_RANDOM_UUID=y
+CONFIG_REGEX=y
+CONFIG_USB=y
+CONFIG_USB_HOST=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_MTK=y
+CONFIG_USB_STORAGE=y
+CONFIG_OF_EMBED=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_UBI=y
+CONFIG_ENV_UBI_PART="ubi"
+CONFIG_ENV_SIZE=0x1f000
+CONFIG_ENV_SIZE_REDUND=0x1f000
+CONFIG_ENV_UBI_VOLUME="ubootenv"
+CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_PHY_FIXED=y
+CONFIG_DM_ETH=y
+CONFIG_MEDIATEK_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MT7986=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MTK_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_MTK_SERIAL=y
+CONFIG_HEXDUMP=y
+CONFIG_USE_DEFAULT_ENV_FILE=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_MTK_SPIM=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_LMB_MAX_REGIONS=64
+CONFIG_USE_IPADDR=y
+CONFIG_IPADDR="192.168.1.1"
+CONFIG_USE_SERVERIP=y
+CONFIG_SERVERIP="192.168.1.254"
--- /dev/null
+++ b/arch/arm/dts/mt7986a-zyxel_ex5601-t0.dts
@@ -0,0 +1,181 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Author: Valerio 'ftp21' Mancini <ftp21@ftp21.eu>
+ * Author: Nicolò Veronese <nicveronese@gmail.com>
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/linux-event-codes.h>
+#include "mt7986.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "Zyxel EX5601-T0 ubootmod";
+ compatible = "mediatek,mt7986", "mediatek,mt7986-sd-rfb";
+
+ chosen {
+ stdout-path = &uart0;
+ tick-timer = &timer0;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0x20000000>;
+ };
+
+ keys {
+ compatible = "gpio-keys";
+ factory {
+ label = "reset";
+ gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+
+ wps {
+ label = "wps";
+ gpios = <&gpio 56 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_status_green: pwr {
+ label = "green:status";
+ gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led_sfp_green: sfp {
+ label = "green:sfp";
+ gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+};
+
+&uart0 {
+ mediatek,force-highspeed;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "disabled";
+};
+
+&eth {
+ status = "okay";
+ mediatek,gmac-id = <0>;
+ phy-mode = "2500base-x";
+ mediatek,switch = "mt7531";
+ reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ };
+};
+
+&pinctrl {
+ spic_pins: spi1-pins-func-1 {
+ mux {
+ function = "spi";
+ groups = "spi1_2";
+ };
+ };
+
+ uart1_pins: spi1-pins-func-3 {
+ mux {
+ function = "uart";
+ groups = "uart1_2";
+ };
+ };
+
+ spi_flash_pins: spi0-pins-func-1 {
+ mux {
+ function = "flash";
+ groups = "spi0", "spi0_wp_hold";
+ };
+
+ conf-pu {
+ pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_00>;
+ };
+
+ conf-pd {
+ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
+ };
+ };
+};
+
+&spi0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_flash_pins>;
+ status = "okay";
+ must_tx;
+ enhance_timing;
+ dma_ext;
+ ipm_design;
+ support_quad;
+ tick_dly = <1>;
+ sample_sel = <0>;
+
+ spi_nand@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ spi-tx-buswidth = <4>;
+ spi-rx-buswidth = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "bl2";
+ reg = <0x0 0x100000>;
+ };
+
+ partition@100000 {
+ label = "u-boot-env";
+ reg = <0x0100000 0x0080000>;
+ };
+
+ partition@180000 {
+ label = "Factory";
+ reg = <0x180000 0x0200000>;
+ };
+
+ partition@380000 {
+ label = "fip";
+ reg = <0x380000 0x0200000>;
+ };
+
+ partition@540000 {
+ label = "zloader";
+ reg = <0x540000 0x0040000>;
+ read-only;
+ };
+ partition@580000 {
+ label = "ubi";
+ reg = <0x580000 0x1da80000>;
+ };
+ };
+ };
+};
+
+&watchdog {
+ status = "disabled";
+};
+
--- /dev/null
+++ b/zyxel_ex5601-t0_env
@@ -0,0 +1,55 @@
+ethaddr_factory=mtd read Factory 0x40080000 0x0 0x20000 && env readmem -b ethaddr 0x4008002A 0x6 ; setenv ethaddr_factory
+ipaddr=192.168.1.1
+serverip=192.168.1.254
+loadaddr=0x46000000
+console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0
+bootargs=console=ttyS0,115200n8 console_msg_format=syslog
+bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi
+bootconf=config-1
+bootdelay=0
+bootfile=openwrt-mediatek-filogic-zyxel_ex5601-t0-ubootmod-initramfs-recovery.itb
+bootfile_bl2=openwrt-mediatek-filogic-zyxel_ex5601-t0-ubootmod-preloader.bin
+bootfile_fip=openwrt-mediatek-filogic-zyxel_ex5601-t0-ubootmod-bl31-uboot.fip
+bootfile_upg=openwrt-mediatek-filogic-zyxel_ex5601-t0-ubootmod-squashfs-sysupgrade.itb
+bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60
+bootmenu_default=0
+bootmenu_delay=0
+bootmenu_title= ( ( ( OpenWrt ) ) )
+bootmenu_0=Initialize environment.=run _firstboot
+bootmenu_0d=Run default boot command.=run boot_default
+bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return
+bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return
+bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return
+bootmenu_4=Load production system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
+bootmenu_5=Load recovery system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
+bootmenu_6=Load BL31+U-Boot FIP via TFTP then write to NAND.=run boot_tftp_write_fip ; run bootmenu_confirm_return
+bootmenu_7=Load BL2 preloader via TFTP then write to NAND.=run boot_tftp_write_bl2 ; run bootmenu_confirm_return
+bootmenu_8=Reboot.=reset
+bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset
+boot_first=if button reset ; then run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu
+boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever
+boot_production=run ubi_read_production && bootm $loadaddr#$bootconf
+boot_recovery=run ubi_read_recovery && bootm $loadaddr#$bootconf
+boot_ubi=run boot_production ; run boot_recovery ; run boot_tftp_forever
+boot_tftp_forever=while true ; do run boot_tftp_recovery ; sleep 1 ; done
+boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
+boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
+boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf
+boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run mtd_write_fip && run reset_factory
+boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run mtd_write_bl2
+part_fit=fit
+reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800
+mtd_write_fip=mtd erase fip && mtd write fip $loadaddr
+mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr
+ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 0 ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 1
+ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset
+ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi
+ubi_read_production=ubi read $loadaddr $part_fit && iminfo $loadaddr && run ubi_prepare_rootfs
+ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery
+ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data
+ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize
+ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize
+_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv
+_firstboot=setenv _firstboot ; run ethaddr_factory ; run _switch_to_menu ; run _init_env ; run boot_first
+_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
+_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title $ver"

63
package/boot/uboot-rockchip/Makefile
View file

@ -5,13 +5,15 @@
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_VERSION:=2021.07
PKG_RELEASE:=5
PKG_HASH:=312b7eeae44581d1362c3a3f02c28d806647756c82ba8c72241c7cdbe68ba77e
PKG_VERSION:=2023.07.02
PKG_RELEASE:=1
PKG_HASH:=6b6a48581c14abb0f95bd87c1af4d740922406d7b801002a9f94727fdde021d5
PKG_MAINTAINER:=Tobias Maedel <openwrt@tbspace.de>
UBOOT_USE_BINMAN:=1
UBOOT_USE_INTREE_DTC:=1
include $(INCLUDE_DIR)/u-boot.mk
include $(INCLUDE_DIR)/package.mk
@ -28,7 +30,6 @@ define U-Boot/rk3328/Default
BUILD_SUBTARGET:=armv8
DEPENDS:=+PACKAGE_u-boot-$(1):trusted-firmware-a-rk3328
ATF:=rk3328_bl31.elf
OF_PLATDATA:=$(1)
endef
define U-Boot/nanopi-r2c-rk3328
@ -116,6 +117,30 @@ define U-Boot/rockpro64-rk3399
pine64_rockpro64
endef
# RK3568 boards
define U-Boot/rk3568/Default
BUILD_SUBTARGET:=armv8
DEPENDS:=+PACKAGE_u-boot-$(1):trusted-firmware-a-rk3568
ATF:=rk3568_bl31_v1.43.elf
TPL:=rk3568_ddr_1560MHz_v1.18.bin
endef
define U-Boot/nanopi-r5c-rk3568
$(U-Boot/rk3568/Default)
NAME:=NanoPi R5C
BUILD_DEVICES:= \
friendlyarm_nanopi-r5c
endef
define U-Boot/nanopi-r5s-rk3568
$(U-Boot/rk3568/Default)
NAME:=NanoPi R5S
BUILD_DEVICES:= \
friendlyarm_nanopi-r5s
endef
UBOOT_TARGETS := \
nanopc-t4-rk3399 \
nanopi-r4s-rk3399 \
@ -127,27 +152,21 @@ UBOOT_TARGETS := \
orangepi-r1-plus-lts-rk3328 \
roc-cc-rk3328 \
rock64-rk3328 \
rock-pi-e-rk3328
rock-pi-e-rk3328 \
nanopi-r5c-rk3568 \
nanopi-r5s-rk3568
UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes
UBOOT_CUSTOMIZE_CONFIG := \
--disable SPL_FIT_SIGNATURE \
--disable TOOLS_MKEFICAPSULE \
--set-str MKIMAGE_DTC_PATH $(PKG_BUILD_DIR)/scripts/dtc/dtc
UBOOT_MAKE_FLAGS += \
BL31=$(STAGING_DIR_IMAGE)/$(ATF)
define Build/Configure
$(call Build/Configure/U-Boot)
ifneq ($(OF_PLATDATA),)
mkdir -p $(PKG_BUILD_DIR)/tpl/dts
mkdir -p $(PKG_BUILD_DIR)/include/generated
$(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-plat.c $(PKG_BUILD_DIR)/tpl/dts/dt-plat.c
$(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-structs-gen.h $(PKG_BUILD_DIR)/include/generated/dt-structs-gen.h
$(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-decl.h $(PKG_BUILD_DIR)/include/generated/dt-decl.h
endif
$(SED) 's#CONFIG_MKIMAGE_DTC_PATH=.*#CONFIG_MKIMAGE_DTC_PATH="$(PKG_BUILD_DIR)/scripts/dtc/dtc"#g' $(PKG_BUILD_DIR)/.config
endef
PATH=$(STAGING_DIR_HOST)/bin:$(PATH) \
BL31=$(STAGING_DIR_IMAGE)/$(ATF) \
$(if $(TPL),ROCKCHIP_TPL=$(STAGING_DIR_IMAGE)/$(TPL))
define Build/InstallDev
$(INSTALL_DIR) $(STAGING_DIR_IMAGE)

24
package/boot/uboot-rockchip/patches/001-scripts-remove-dependency-on-swig.patch
View file

@ -1,24 +0,0 @@
From b137ca16b54c67d76714ea5a0138741959b0dc29 Mon Sep 17 00:00:00 2001
From: David Bauer <mail@david-bauer.net>
Date: Mon, 13 Jul 2020 23:37:37 +0200
Subject: [PATCH] scripts: remove dependency on swig
Don't build the libfdt tool, as it has a dependency on swig (which
OpenWrt does not ship).
This requires more hacks, as of-platdata generation does not work
without it.
Signed-off-by: David Bauer <mail@david-bauer.net>
---
scripts/dtc/Makefile | 2 --
1 file changed, 2 deletions(-)
--- a/scripts/dtc/Makefile
+++ b/scripts/dtc/Makefile
@@ -18,5 +18,3 @@ HOSTCFLAGS_dtc-parser.tab.o := -I$(src)
# dependencies on generated files need to be listed explicitly
$(obj)/dtc-lexer.lex.o: $(obj)/dtc-parser.tab.h
-# Added for U-Boot
-subdir-$(CONFIG_PYLIBFDT) += pylibfdt

28
package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch
View file

@ -1,28 +0,0 @@
From 55273cf6079ddd3b006da69f0113c2c66c03f17e Mon Sep 17 00:00:00 2001
From: David Bauer <mail@david-bauer.net>
Date: Tue, 14 Jul 2020 22:44:22 +0200
Subject: [PATCH] spl: remove dtoc of-pdata generation
Remove the dtoc of-pdata generation. This generation is dependant on
libpython-dev. As OpenWrt does not ship with this dependency, use
pre-generated pdata files and remove the generation from the
build-process.
This only affects RK3328 boards.
Signed-off-by: David Bauer <mail@david-bauer.net>
---
scripts/Makefile.spl | 6 ------
1 file changed, 6 deletions(-)
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -354,8 +354,6 @@ $(platdata-hdr) $(u-boot-spl-platdata_c)
@# of OF_PLATDATA_INST and this might change between builds. Leaving old
@# ones around is confusing and it is possible that switching the
@# setting again will use the old one instead of regenerating it.
- @rm -f $(u-boot-spl-all-platdata_c) $(u-boot-spl-all-platdata)
- $(call if_changed,dtoc)
ifdef CONFIG_SAMSUNG
ifdef CONFIG_VAR_SIZE_SPL

80
package/boot/uboot-rockchip/patches/103-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus.patch → package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus.patch
View file

@ -1,4 +1,4 @@
From ff312af37d5f263f181468639aab83f645d331f1 Mon Sep 17 00:00:00 2001
From 89afb631d965292aaf433806d8224b53d9e74036 Mon Sep 17 00:00:00 2001
From: Tianling Shen <cnsztl@gmail.com>
Date: Sat, 20 May 2023 18:50:38 +0800
Subject: [PATCH] rockchip: rk3328: Add support for Orange Pi R1 Plus
@ -27,7 +27,7 @@ Signed-off-by: Tianling Shen <cnsztl@gmail.com>
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -110,6 +110,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
@@ -125,6 +125,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-evb.dtb \
rk3328-nanopi-r2c.dtb \
rk3328-nanopi-r2s.dtb \
@ -53,24 +53,24 @@ Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+};
+
+&gpio0 {
+ u-boot,dm-spl;
+ bootph-pre-ram;
+};
+
+&pinctrl {
+ u-boot,dm-spl;
+ bootph-pre-ram;
+};
+
+&sdmmc0m1_gpio {
+ u-boot,dm-spl;
+&sdmmc0m1_pin {
+ bootph-pre-ram;
+};
+
+&pcfg_pull_up_4ma {
+ u-boot,dm-spl;
+ bootph-pre-ram;
+};
+
+/* Need this and all the pinctrl/gpio stuff above to set pinmux */
+&vcc_sd {
+ u-boot,dm-spl;
+ bootph-pre-ram;
+};
+
+&gmac2io {
@ -81,12 +81,12 @@ Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+
+&spi0 {
+ spi_flash: spiflash@0 {
+ u-boot,dm-pre-reloc;
+ bootph-all;
+ };
+};
--- /dev/null
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus.dts
@@ -0,0 +1,359 @@
@@ -0,0 +1,373 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Based on rk3328-nanopi-r2s.dts, which is:
@ -104,6 +104,7 @@ Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+ compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
+
+ aliases {
+ ethernet1 = &rtl8153;
+ mmc0 = &sdmmc;
+ };
+
@ -146,7 +147,7 @@ Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+ vcc_sd: sdmmc-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&sdmmc0m1_gpio>;
+ pinctrl-0 = <&sdmmc0m1_pin>;
+ pinctrl-names = "default";
+ regulator-name = "vcc_sd";
+ regulator-boot-on;
@ -439,6 +440,19 @@ Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+ status = "okay";
+};
+
+&usbdrd3 {
+ dr_mode = "host";
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Second port is for USB 3.0 */
+ rtl8153: device@2 {
+ compatible = "usbbda,8153";
+ reg = <2>;
+ };
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
@ -463,39 +477,52 @@ Signed-off-by: Tianling Shen <cnsztl@gmail.com>
M: Chen-Yu Tsai <wens@csie.org>
--- /dev/null
+++ b/configs/orangepi-r1-plus-rk3328_defconfig
@@ -0,0 +1,98 @@
@@ -0,0 +1,114 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_TEXT_BASE=0x00200000
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus"
+CONFIG_DM_RESET=y
+CONFIG_ROCKCHIP_RK3328=y
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL_STACK=0x400000
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
+CONFIG_DEBUG_UART_BASE=0xFF130000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYSINFO=y
+CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus.dtb"
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_MISC_INIT_R=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x2000000
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
@ -504,11 +531,11 @@ Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_TPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_TPL_OF_PLATDATA=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TPL_DM=y
+CONFIG_REGMAP=y
@ -526,13 +553,14 @@ Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_DM_ETH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_PMIC_RK8XX=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
@ -542,9 +570,11 @@ Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SPI=y
+CONFIG_SYSINFO=y
+CONFIG_SYSRESET=y
+# CONFIG_TPL_SYSRESET is not set
+CONFIG_USB=y

27
package/boot/uboot-rockchip/patches/101-rock64pro-disable-CONFIG_USE_PREBOOT.patch
View file

@ -1,27 +0,0 @@
From 2114d68b3c755ec8043ae9e43ac8e9753e0cec84 Mon Sep 17 00:00:00 2001
From: Marty Jones <mj8263788@gmail.com>
Date: Sun, 17 Jan 2021 15:26:09 -0500
Subject: [PATCH] rockpro64: disable CONFIG_USE_PREBOOT
On commit https://github.com/u-boot/u-boot/commit/f81f9f0ebac596bae7f27db095f4f0272b606cc3
CONFIG_USE_PREBOOT was enabled on the RockPro64.
When the board is booting, U-Boot hangs as soon as it disables the USB
controller. This is a workaround until a final solution is deployed
upstream.
Signed-off-by: Marty Jones <mj8263788@gmail.com>
---
configs/rockpro64-rk3399_defconfig | 1 -
1 file changed, 1 deletion(-)
--- a/configs/rockpro64-rk3399_defconfig
+++ b/configs/rockpro64-rk3399_defconfig
@@ -12,7 +12,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
-CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y

63
package/boot/uboot-rockchip/patches/104-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus-LT.patch → package/boot/uboot-rockchip/patches/101-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus-LT.patch
View file

@ -1,4 +1,4 @@
From 7a9326a96098bc63d2b60538f657c3a533415276 Mon Sep 17 00:00:00 2001
From 408fd4570c0f1e6b1fe3722998394651144f2a29 Mon Sep 17 00:00:00 2001
From: Tianling Shen <cnsztl@gmail.com>
Date: Sat, 20 May 2023 18:52:14 +0800
Subject: [PATCH] rockchip: rk3328: Add support for Orange Pi R1 Plus LTS
@ -10,7 +10,6 @@ changed from DDR4 to LPDDR3.
The device tree is taken from kernel v6.4-rc1.
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
---
arch/arm/dts/Makefile | 1 +
.../rk3328-orangepi-r1-plus-lts-u-boot.dtsi | 46 +++++++
@ -24,7 +23,7 @@ Signed-off-by: Tianling Shen <cnsztl@gmail.com>
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -111,6 +111,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
@@ -126,6 +126,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-nanopi-r2c.dtb \
rk3328-nanopi-r2s.dtb \
rk3328-orangepi-r1-plus.dtb \
@ -50,24 +49,24 @@ Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+};
+
+&gpio0 {
+ u-boot,dm-spl;
+ bootph-pre-ram;
+};
+
+&pinctrl {
+ u-boot,dm-spl;
+ bootph-pre-ram;
+};
+
+&sdmmc0m1_gpio {
+ u-boot,dm-spl;
+&sdmmc0m1_pin {
+ bootph-pre-ram;
+};
+
+&pcfg_pull_up_4ma {
+ u-boot,dm-spl;
+ bootph-pre-ram;
+};
+
+/* Need this and all the pinctrl/gpio stuff above to set pinmux */
+&vcc_sd {
+ u-boot,dm-spl;
+ bootph-pre-ram;
+};
+
+&gmac2io {
@ -78,7 +77,7 @@ Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+
+&spi0 {
+ spi_flash: spiflash@0 {
+ u-boot,dm-pre-reloc;
+ bootph-all;
+ };
+};
--- /dev/null
@ -141,39 +140,52 @@ Signed-off-by: Tianling Shen <cnsztl@gmail.com>
M: Chen-Yu Tsai <wens@csie.org>
--- /dev/null
+++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig
@@ -0,0 +1,98 @@
@@ -0,0 +1,114 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_TEXT_BASE=0x00200000
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts"
+CONFIG_DM_RESET=y
+CONFIG_ROCKCHIP_RK3328=y
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL_STACK=0x400000
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
+CONFIG_DEBUG_UART_BASE=0xFF130000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYSINFO=y
+CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb"
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_MISC_INIT_R=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x2000000
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
@ -182,11 +194,11 @@ Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_TPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_TPL_OF_PLATDATA=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TPL_DM=y
+CONFIG_REGMAP=y
@ -204,13 +216,14 @@ Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_DM_ETH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_PMIC_RK8XX=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
@ -220,9 +233,11 @@ Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SPI=y
+CONFIG_SYSINFO=y
+CONFIG_SYSRESET=y
+# CONFIG_TPL_SYSRESET is not set
+CONFIG_USB=y

199
package/boot/uboot-rockchip/patches/102-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R2C.patch
View file

@ -1,199 +0,0 @@
From 7000a609473ffe14d32c656cdd0ff3ca0d3ecbd7 Mon Sep 17 00:00:00 2001
From: Tianling Shen <cnsztl@gmail.com>
Date: Tue, 11 Apr 2023 18:14:49 +0800
Subject: [PATCH] rockchip: rk3328: Add support for FriendlyARM NanoPi R2C
The NanoPi R2C is a minor variant of NanoPi R2S with the on-board NIC
chip changed from rtl8211e to yt8521s, and otherwise identical to R2S.
The device tree is taken from the kernel linux-next branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=004589ff9df5b75672a78b6c3c4cba93202b14c9
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi | 3 +
arch/arm/dts/rk3328-nanopi-r2c.dts | 40 ++++++++
board/rockchip/evb_rk3328/MAINTAINERS | 6 ++
configs/nanopi-r2c-rk3328_defconfig | 112 +++++++++++++++++++++
5 files changed, 162 insertions(+)
create mode 100644 arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3328-nanopi-r2c.dts
create mode 100644 configs/nanopi-r2c-rk3328_defconfig
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -108,6 +108,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-evb.dtb \
+ rk3328-nanopi-r2c.dtb \
rk3328-nanopi-r2s.dtb \
rk3328-roc-cc.dtb \
rk3328-rock64.dtb \
--- /dev/null
+++ b/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rk3328-nanopi-r2s-u-boot.dtsi"
--- /dev/null
+++ b/arch/arm/dts/rk3328-nanopi-r2c.dts
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
+ */
+
+/dts-v1/;
+#include "rk3328-nanopi-r2s.dts"
+
+/ {
+ model = "FriendlyElec NanoPi R2C";
+ compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
+};
+
+&gmac2io {
+ phy-handle = <&yt8521s>;
+ tx_delay = <0x22>;
+ rx_delay = <0x12>;
+
+ mdio {
+ /delete-node/ ethernet-phy@1;
+
+ yt8521s: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <3>;
+
+ motorcomm,clk-out-frequency-hz = <125000000>;
+ motorcomm,keep-pll-enabled;
+ motorcomm,auto-sleep-disabled;
+
+ pinctrl-0 = <&eth_phy_reset_pin>;
+ pinctrl-names = "default";
+ reset-assert-us = <10000>;
+ reset-deassert-us = <50000>;
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
--- a/board/rockchip/evb_rk3328/MAINTAINERS
+++ b/board/rockchip/evb_rk3328/MAINTAINERS
@@ -5,6 +5,12 @@ F: board/rockchip/evb_rk3328
F: include/configs/evb_rk3328.h
F: configs/evb-rk3328_defconfig
+NANOPI-R2C-RK3328
+M: Tianling Shen <cnsztl@gmail.com>
+S: Maintained
+F: configs/nanopi-r2c-rk3328_defconfig
+F: arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi
+
NANOPI-R2S-RK3328
M: David Bauer <mail@david-bauer.net>
S: Maintained
--- /dev/null
+++ b/configs/nanopi-r2c-rk3328_defconfig
@@ -0,0 +1,98 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c"
+CONFIG_ROCKCHIP_RK3328=y
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_DEBUG_UART_BASE=0xFF130000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_MISC_INIT_R=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_TPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_TPL_OF_PLATDATA=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_TPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_TPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_FASTBOOT_BUF_ADDR=0x800800
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSINFO=y
+CONFIG_SYSRESET=y
+# CONFIG_TPL_SYSRESET is not set
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y

917
package/boot/uboot-rockchip/patches/103-rockchip-rk3568-Add-support-for-FriendlyARM-NanoPi-R.patch Normal file
View file

@ -0,0 +1,917 @@
From c84214aab0e4c5b2f619dd89655f27b3ae40e82b Mon Sep 17 00:00:00 2001
From: Tianling Shen <cnsztl@gmail.com>
Date: Tue, 30 May 2023 15:00:33 +0800
Subject: [PATCH] rockchip: rk3568: Add support for FriendlyARM NanoPi R5S
FriendlyARM NanoPi R5S is an open-sourced mini IoT gateway device.
Board Specifications
- Rockchip RK3568
- 2 or 4GB LPDDR4X
- 8GB or 16GB eMMC, SD card slot
- GbE LAN (Native)
- 2x 2.5G LAN (PCIe)
- M.2 Connector
- HDMI 2.0, MIPI DSI/CSI
- 2xUSB 3.0 Host
- USB Type C PD, 5V/9V/12V
- GPIO: 12-pin 0.5mm FPC connector
The device tree is taken from kernel v6.4-rc1.
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi | 31 ++
arch/arm/dts/rk3568-nanopi-r5s.dts | 136 +++++
arch/arm/dts/rk3568-nanopi-r5s.dtsi | 590 +++++++++++++++++++++
board/rockchip/evb_rk3568/MAINTAINERS | 8 +
configs/nanopi-r5s-rk3568_defconfig | 85 +++
6 files changed, 851 insertions(+)
create mode 100644 arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dts
create mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dtsi
create mode 100644 configs/nanopi-r5s-rk3568_defconfig
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3566-anbernic-rgxx3.dtb \
rk3566-radxa-cm3-io.dtb \
rk3568-evb.dtb \
+ rk3568-nanopi-r5s.dtb \
rk3568-rock-3a.dtb
dtb-$(CONFIG_ROCKCHIP_RK3588) += \
--- /dev/null
+++ b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyelec.com)
+ *
+ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
+ */
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart2;
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
+ };
+};
+
+&sdhci {
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+};
+
+&uart2 {
+ clock-frequency = <24000000>;
+ bootph-all;
+ status = "okay";
+};
--- /dev/null
+++ b/arch/arm/dts/rk3568-nanopi-r5s.dts
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyelec.com)
+ *
+ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
+ */
+
+/dts-v1/;
+#include "rk3568-nanopi-r5s.dtsi"
+
+/ {
+ model = "FriendlyElec NanoPi R5S";
+ compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568";
+
+ aliases {
+ ethernet0 = &gmac0;
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>;
+
+ led-lan1 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <1>;
+ gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-lan2 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <2>;
+ gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>;
+ };
+
+ power_led: led-power {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_POWER;
+ linux,default-trigger = "heartbeat";
+ gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-wan {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WAN;
+ gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&gmac0 {
+ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
+ assigned-clock-rates = <0>, <125000000>;
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy0>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac0_miim
+ &gmac0_tx_bus2
+ &gmac0_rx_bus2
+ &gmac0_rgmii_clk
+ &gmac0_rgmii_bus>;
+ snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ /* Reset time is 15ms, 50ms for rtl8211f */
+ snps,reset-delays-us = <0 15000 50000>;
+ tx_delay = <0x3c>;
+ rx_delay = <0x2f>;
+ status = "okay";
+};
+
+&mdio0 {
+ rgmii_phy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ pinctrl-0 = <&eth_phy0_reset_pin>;
+ pinctrl-names = "default";
+ };
+};
+
+&pcie2x1 {
+ num-lanes = <1>;
+ reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&pcie30phy {
+ data-lanes = <1 2>;
+ status = "okay";
+};
+
+&pcie3x1 {
+ num-lanes = <1>;
+ reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie>;
+ status = "okay";
+};
+
+&pcie3x2 {
+ num-lanes = <1>;
+ num-ib-windows = <8>;
+ num-ob-windows = <8>;
+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie>;
+ status = "okay";
+};
+
+&pinctrl {
+ gmac0 {
+ eth_phy0_reset_pin: eth-phy0-reset-pin {
+ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ gpio-leds {
+ lan1_led_pin: lan1-led-pin {
+ rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ lan2_led_pin: lan2-led-pin {
+ rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ power_led_pin: power-led-pin {
+ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ wan_led_pin: wan-led-pin {
+ rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
--- /dev/null
+++ b/arch/arm/dts/rk3568-nanopi-r5s.dtsi
@@ -0,0 +1,590 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyelec.com)
+ *
+ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3568.dtsi"
+
+/ {
+ aliases {
+ mmc0 = &sdmmc0;
+ mmc1 = &sdhci;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ hdmi-con {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ vdd_usbc: vdd-usbc-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_usbc";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vdd_usbc>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vdd_usbc>;
+ };
+
+ vcc3v3_pcie: vcc3v3-pcie-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <200000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_usb: vcc5v0-usb-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vdd_usbc>;
+ };
+
+ vcc5v0_usb_host: vcc5v0-usb-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb_host_en>;
+ regulator-name = "vcc5v0_usb_host";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usb>;
+ };
+
+ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb_otg_en>;
+ regulator-name = "vcc5v0_usb_otg";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usb>;
+ };
+
+ pcie30_avdd0v9: pcie30-avdd0v9-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ pcie30_avdd1v8: pcie30-avdd1v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+};
+
+&combphy0 {
+ status = "okay";
+};
+
+&combphy1 {
+ status = "okay";
+};
+
+&combphy2 {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&hdmi {
+ avdd-0v9-supply = <&vdda0v9_image>;
+ avdd-1v8-supply = <&vcca1v8_image>;
+ status = "okay";
+};
+
+&hdmi_in {
+ hdmi_in_vp0: endpoint {
+ remote-endpoint = <&vp0_out_hdmi>;
+ };
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&hdmi_sound {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>;
+ rockchip,system-power-controller;
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+ wakeup-source;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
+ regulator-always-on;
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_npu: DCDC_REG4 {
+ regulator-name = "vdd_npu";
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG5 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-name = "vdda0v9_image";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <950000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-name = "vdda_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-name = "vdda0v9_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-name = "vccio_acodec";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-name = "vcc3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca_1v8: LDO_REG7 {
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG8 {
+ regulator-name = "vcca1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-name = "vcca1v8_image";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3: SWITCH_REG1 {
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd: SWITCH_REG2 {
+ regulator-name = "vcc3v3_sd";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+
+ };
+};
+
+&i2c5 {
+ status = "okay";
+
+ hym8563: rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <0>;
+ clock-output-names = "rtcic_32kout";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hym8563_int>;
+ wakeup-source;
+ };
+};
+
+&i2s0_8ch {
+ status = "okay";
+};
+
+&pcie30phy {
+ data-lanes = <1 2>;
+ status = "okay";
+};
+
+&pinctrl {
+ hym8563 {
+ hym8563_int: hym8563-int {
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ pmic {
+ pmic_int: pmic-int {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ usb {
+ vcc5v0_usb_host_en: vcc5v0-usb-host-en {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcc3v3_pmu>;
+ vccio1-supply = <&vccio_acodec>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcc_1v8>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_1v8>;
+ vccio7-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcca_1v8>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
+ status = "okay";
+};
+
+&sdmmc0 {
+ max-frequency = <150000000>;
+ no-sdio;
+ no-mmc;
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ vmmc-supply = <&vcc3v3_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ status = "okay";
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ extcon = <&usb2phy0>;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usb_host1_xhci {
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy0_host {
+ phy-supply = <&vcc5v0_usb_host>;
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ status = "okay";
+};
+
+&usb2phy1 {
+ status = "okay";
+};
+
+&usb2phy1_host {
+ phy-supply = <&vcc5v0_usb_otg>;
+ status = "okay";
+};
+
+&usb2phy1_otg {
+ status = "okay";
+};
+
+&vop {
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+ remote-endpoint = <&hdmi_in_vp0>;
+ };
+};
--- a/board/rockchip/evb_rk3568/MAINTAINERS
+++ b/board/rockchip/evb_rk3568/MAINTAINERS
@@ -7,6 +7,14 @@ F: configs/evb-rk3568_defconfig
F: arch/arm/dts/rk3568-evb-boot.dtsi
F: arch/arm/dts/rk3568-evb.dts
+NANOPI-R5S
+M: Tianling Shen <cnsztl@gmail.com>
+S: Maintained
+F: configs/nanopi-r5s-rk3568_defconfig
+F: arch/arm/dts/rk3568-nanopi-r5s.dts
+F: arch/arm/dts/rk3568-nanopi-r5s.dtsi
+F: arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
+
RADXA-CM3
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
--- /dev/null
+++ b/configs/nanopi-r5s-rk3568_defconfig
@@ -0,0 +1,85 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_EVB_RK3568=y
+CONFIG_SPL_STACK=0x400000
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5s.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x4000000
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_WARN=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_ERRNO_STR=y

269
package/boot/uboot-rockchip/patches/104-rockchip-rk3568-Add-support-for-FriendlyARM-NanoPi-R.patch Normal file
View file

@ -0,0 +1,269 @@
From 41538742491c46100f570680c02fbdd0d2b6b880 Mon Sep 17 00:00:00 2001
From: Tianling Shen <cnsztl@gmail.com>
Date: Tue, 30 May 2023 15:00:33 +0800
Subject: [PATCH] rockchip: rk3568: Add support for FriendlyARM NanoPi R5C
FriendlyARM NanoPi R5C is an open-sourced mini IoT gateway device.
Specification:
- Rockchip RK3568
- 1/4GB LPDDR4X RAM
- 8/32GB eMMC
- SD card slot
- M.2 Connector
- 2x USB 3.0 Port
- 2x 2500 Base-T (PCIe, r8125)
- HDMI 2.0
- MIPI DSI/CSI
- USB Type C 5V
The device tree is taken from kernel v6.4-rc1.
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi | 3 +
arch/arm/dts/rk3568-nanopi-r5c.dts | 112 +++++++++++++++++++++
board/rockchip/evb_rk3568/MAINTAINERS | 7 ++
configs/nanopi-r5c-rk3568_defconfig | 85 ++++++++++++++++
5 files changed, 208 insertions(+)
create mode 100644 arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3568-nanopi-r5c.dts
create mode 100644 configs/nanopi-r5c-rk3568_defconfig
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3566-anbernic-rgxx3.dtb \
rk3566-radxa-cm3-io.dtb \
rk3568-evb.dtb \
+ rk3568-nanopi-r5c.dtb \
rk3568-nanopi-r5s.dtb \
rk3568-rock-3a.dtb
--- /dev/null
+++ b/arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rk3568-nanopi-r5s-u-boot.dtsi"
--- /dev/null
+++ b/arch/arm/dts/rk3568-nanopi-r5c.dts
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyelec.com)
+ *
+ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
+ */
+
+/dts-v1/;
+#include "rk3568-nanopi-r5s.dtsi"
+
+/ {
+ model = "FriendlyElec NanoPi R5C";
+ compatible = "friendlyarm,nanopi-r5c", "rockchip,rk3568";
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&reset_button_pin>;
+
+ button-reset {
+ debounce-interval = <50>;
+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&lan_led_pin>, <&power_led_pin>, <&wan_led_pin>, <&wlan_led_pin>;
+
+ led-lan {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>;
+ };
+
+ power_led: led-power {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_POWER;
+ linux,default-trigger = "heartbeat";
+ gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-wan {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WAN;
+ gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-wlan {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WLAN;
+ gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&pcie2x1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie20_reset_pin>;
+ reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&pcie3x1 {
+ num-lanes = <1>;
+ reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie>;
+ status = "okay";
+};
+
+&pcie3x2 {
+ num-lanes = <1>;
+ reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie>;
+ status = "okay";
+};
+
+&pinctrl {
+ gpio-leds {
+ lan_led_pin: lan-led-pin {
+ rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ power_led_pin: power-led-pin {
+ rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ wan_led_pin: wan-led-pin {
+ rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ wlan_led_pin: wlan-led-pin {
+ rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pcie {
+ pcie20_reset_pin: pcie20-reset-pin {
+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ rockchip-key {
+ reset_button_pin: reset-button-pin {
+ rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
--- a/board/rockchip/evb_rk3568/MAINTAINERS
+++ b/board/rockchip/evb_rk3568/MAINTAINERS
@@ -7,6 +7,13 @@ F: configs/evb-rk3568_defconfig
F: arch/arm/dts/rk3568-evb-boot.dtsi
F: arch/arm/dts/rk3568-evb.dts
+NANOPI-R5C
+M: Tianling Shen <cnsztl@gmail.com>
+S: Maintained
+F: configs/nanopi-r5c-rk3568_defconfig
+F: arch/arm/dts/rk3568-nanopi-r5c.dts
+F: arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi
+
NANOPI-R5S
M: Tianling Shen <cnsztl@gmail.com>
S: Maintained
--- /dev/null
+++ b/configs/nanopi-r5c-rk3568_defconfig
@@ -0,0 +1,85 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5c"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_EVB_RK3568=y
+CONFIG_SPL_STACK=0x400000
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5c.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x4000000
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_WARN=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_ERRNO_STR=y

23
package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-decl.h
View file

@ -1,23 +0,0 @@
/*
* DO NOT MODIFY
*
* Declares externs for all device/uclass instances.
* This was generated by dtoc from a .dtb (device tree binary) file.
*/
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
/* driver declarations - these allow DM_DRIVER_GET() to be used */
extern U_BOOT_DRIVER(rockchip_rk3328_cru);
extern U_BOOT_DRIVER(rockchip_rk3328_dmc);
extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
extern U_BOOT_DRIVER(ns16550_serial);
extern U_BOOT_DRIVER(rockchip_rk3328_grf);
/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */
extern UCLASS_DRIVER(clk);
extern UCLASS_DRIVER(mmc);
extern UCLASS_DRIVER(ram);
extern UCLASS_DRIVER(serial);
extern UCLASS_DRIVER(syscon);

155
package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-plat.c
View file

@ -1,155 +0,0 @@
/*
* DO NOT MODIFY
*
* Declares the U_BOOT_DRIVER() records and platform data.
* This was generated by dtoc from a .dtb (device tree binary) file.
*/
/* Allow use of U_BOOT_DRVINFO() in this file */
#define DT_PLAT_C
#include <common.h>
#include <dm.h>
#include <dt-structs.h>
/*
* driver_info declarations, ordered by 'struct driver_info' linker_list idx:
*
* idx driver_info driver
* --- -------------------- --------------------
* 0: clock_controller_at_ff440000 rockchip_rk3328_cru
* 1: dmc rockchip_rk3328_dmc
* 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc
* 3: serial_at_ff130000 ns16550_serial
* 4: syscon_at_ff100000 rockchip_rk3328_grf
* --- -------------------- --------------------
*/
/*
* Node /clock-controller@ff440000 index 0
* driver rockchip_rk3328_cru parent None
*/
static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
.reg = {0xff440000, 0x1000},
.rockchip_grf = 0x3a,
};
U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
.name = "rockchip_rk3328_cru",
.plat = &dtv_clock_controller_at_ff440000,
.plat_size = sizeof(dtv_clock_controller_at_ff440000),
.parent_idx = -1,
};
/*
* Node /dmc index 1
* driver rockchip_rk3328_dmc parent None
*/
static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
.reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
0xff720000, 0x1000, 0xff798000, 0x1000},
.rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0,
0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15,
0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0,
0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8,
0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8,
0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104,
0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114,
0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184,
0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240,
0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff,
0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c,
0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
0x77, 0x77, 0x79, 0x9},
};
U_BOOT_DRVINFO(dmc) = {
.name = "rockchip_rk3328_dmc",
.plat = &dtv_dmc,
.plat_size = sizeof(dtv_dmc),
.parent_idx = -1,
};
/*
* Node /mmc@ff500000 index 2
* driver rockchip_rk3288_dw_mshc parent None
*/
static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
.bus_width = 0x4,
.cap_sd_highspeed = true,
.clocks = {
{0, {317}},
{0, {33}},
{0, {74}},
{0, {78}},},
.disable_wp = true,
.fifo_depth = 0x100,
.interrupts = {0x0, 0xc, 0x4},
.max_frequency = 0x8f0d180,
.pinctrl_0 = {0x47, 0x48, 0x49, 0x4a},
.pinctrl_names = "default",
.reg = {0xff500000, 0x4000},
.sd_uhs_sdr104 = true,
.sd_uhs_sdr12 = true,
.sd_uhs_sdr25 = true,
.sd_uhs_sdr50 = true,
.u_boot_spl_fifo_mode = true,
.vmmc_supply = 0x4b,
.vqmmc_supply = 0x1e,
};
U_BOOT_DRVINFO(mmc_at_ff500000) = {
.name = "rockchip_rk3288_dw_mshc",
.plat = &dtv_mmc_at_ff500000,
.plat_size = sizeof(dtv_mmc_at_ff500000),
.parent_idx = -1,
};
/*
* Node /serial@ff130000 index 3
* driver ns16550_serial parent None
*/
static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
.clock_frequency = 0x16e3600,
.clocks = {
{0, {40}},
{0, {212}},},
.dma_names = {"tx", "rx"},
.dmas = {0x10, 0x6, 0x10, 0x7},
.interrupts = {0x0, 0x39, 0x4},
.pinctrl_0 = 0x26,
.pinctrl_names = "default",
.reg = {0xff130000, 0x100},
.reg_io_width = 0x4,
.reg_shift = 0x2,
};
U_BOOT_DRVINFO(serial_at_ff130000) = {
.name = "ns16550_serial",
.plat = &dtv_serial_at_ff130000,
.plat_size = sizeof(dtv_serial_at_ff130000),
.parent_idx = -1,
};
/*
* Node /syscon@ff100000 index 4
* driver rockchip_rk3328_grf parent None
*/
static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
.reg = {0xff100000, 0x1000},
};
U_BOOT_DRVINFO(syscon_at_ff100000) = {
.name = "rockchip_rk3328_grf",
.plat = &dtv_syscon_at_ff100000,
.plat_size = sizeof(dtv_syscon_at_ff100000),
.parent_idx = -1,
};

51
package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-structs-gen.h
View file

@ -1,51 +0,0 @@
/*
* DO NOT MODIFY
*
* Defines the structs used to hold devicetree data.
* This was generated by dtoc from a .dtb (device tree binary) file.
*/
#include <stdbool.h>
#include <linux/libfdt.h>
struct dtd_ns16550_serial {
fdt32_t clock_frequency;
struct phandle_1_arg clocks[2];
const char * dma_names[2];
fdt32_t dmas[4];
fdt32_t interrupts[3];
fdt32_t pinctrl_0;
const char * pinctrl_names;
fdt64_t reg[2];
fdt32_t reg_io_width;
fdt32_t reg_shift;
};
struct dtd_rockchip_rk3288_dw_mshc {
fdt32_t bus_width;
bool cap_sd_highspeed;
struct phandle_1_arg clocks[4];
bool disable_wp;
fdt32_t fifo_depth;
fdt32_t interrupts[3];
fdt32_t max_frequency;
fdt32_t pinctrl_0[4];
const char * pinctrl_names;
fdt64_t reg[2];
bool sd_uhs_sdr104;
bool sd_uhs_sdr12;
bool sd_uhs_sdr25;
bool sd_uhs_sdr50;
bool u_boot_spl_fifo_mode;
fdt32_t vmmc_supply;
fdt32_t vqmmc_supply;
};
struct dtd_rockchip_rk3328_cru {
fdt64_t reg[2];
fdt32_t rockchip_grf;
};
struct dtd_rockchip_rk3328_dmc {
fdt64_t reg[12];
fdt32_t rockchip_sdram_params[196];
};
struct dtd_rockchip_rk3328_grf {
fdt64_t reg[2];
};

23
package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-decl.h
View file

@ -1,23 +0,0 @@
/*
* DO NOT MODIFY
*
* Declares externs for all device/uclass instances.
* This was generated by dtoc from a .dtb (device tree binary) file.
*/
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
/* driver declarations - these allow DM_DRIVER_GET() to be used */
extern U_BOOT_DRIVER(rockchip_rk3328_cru);
extern U_BOOT_DRIVER(rockchip_rk3328_dmc);
extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
extern U_BOOT_DRIVER(ns16550_serial);
extern U_BOOT_DRIVER(rockchip_rk3328_grf);
/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */
extern UCLASS_DRIVER(clk);
extern UCLASS_DRIVER(mmc);
extern UCLASS_DRIVER(ram);
extern UCLASS_DRIVER(serial);
extern UCLASS_DRIVER(syscon);

155
package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-plat.c
View file

@ -1,155 +0,0 @@
/*
* DO NOT MODIFY
*
* Declares the U_BOOT_DRIVER() records and platform data.
* This was generated by dtoc from a .dtb (device tree binary) file.
*/
/* Allow use of U_BOOT_DRVINFO() in this file */
#define DT_PLAT_C
#include <common.h>
#include <dm.h>
#include <dt-structs.h>
/*
* driver_info declarations, ordered by 'struct driver_info' linker_list idx:
*
* idx driver_info driver
* --- -------------------- --------------------
* 0: clock_controller_at_ff440000 rockchip_rk3328_cru
* 1: dmc rockchip_rk3328_dmc
* 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc
* 3: serial_at_ff130000 ns16550_serial
* 4: syscon_at_ff100000 rockchip_rk3328_grf
* --- -------------------- --------------------
*/
/*
* Node /clock-controller@ff440000 index 0
* driver rockchip_rk3328_cru parent None
*/
static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
.reg = {0xff440000, 0x1000},
.rockchip_grf = 0x3a,
};
U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
.name = "rockchip_rk3328_cru",
.plat = &dtv_clock_controller_at_ff440000,
.plat_size = sizeof(dtv_clock_controller_at_ff440000),
.parent_idx = -1,
};
/*
* Node /dmc index 1
* driver rockchip_rk3328_dmc parent None
*/
static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
.reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
0xff720000, 0x1000, 0xff798000, 0x1000},
.rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0,
0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15,
0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0,
0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8,
0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8,
0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104,
0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114,
0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184,
0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240,
0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff,
0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c,
0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
0x77, 0x77, 0x79, 0x9},
};
U_BOOT_DRVINFO(dmc) = {
.name = "rockchip_rk3328_dmc",
.plat = &dtv_dmc,
.plat_size = sizeof(dtv_dmc),
.parent_idx = -1,
};
/*
* Node /mmc@ff500000 index 2
* driver rockchip_rk3288_dw_mshc parent None
*/
static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
.bus_width = 0x4,
.cap_sd_highspeed = true,
.clocks = {
{0, {317}},
{0, {33}},
{0, {74}},
{0, {78}},},
.disable_wp = true,
.fifo_depth = 0x100,
.interrupts = {0x0, 0xc, 0x4},
.max_frequency = 0x8f0d180,
.pinctrl_0 = {0x47, 0x48, 0x49, 0x4a},
.pinctrl_names = "default",
.reg = {0xff500000, 0x4000},
.sd_uhs_sdr104 = true,
.sd_uhs_sdr12 = true,
.sd_uhs_sdr25 = true,
.sd_uhs_sdr50 = true,
.u_boot_spl_fifo_mode = true,
.vmmc_supply = 0x4b,
.vqmmc_supply = 0x1e,
};
U_BOOT_DRVINFO(mmc_at_ff500000) = {
.name = "rockchip_rk3288_dw_mshc",
.plat = &dtv_mmc_at_ff500000,
.plat_size = sizeof(dtv_mmc_at_ff500000),
.parent_idx = -1,
};
/*
* Node /serial@ff130000 index 3
* driver ns16550_serial parent None
*/
static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
.clock_frequency = 0x16e3600,
.clocks = {
{0, {40}},
{0, {212}},},
.dma_names = {"tx", "rx"},
.dmas = {0x10, 0x6, 0x10, 0x7},
.interrupts = {0x0, 0x39, 0x4},
.pinctrl_0 = 0x26,
.pinctrl_names = "default",
.reg = {0xff130000, 0x100},
.reg_io_width = 0x4,
.reg_shift = 0x2,
};
U_BOOT_DRVINFO(serial_at_ff130000) = {
.name = "ns16550_serial",
.plat = &dtv_serial_at_ff130000,
.plat_size = sizeof(dtv_serial_at_ff130000),
.parent_idx = -1,
};
/*
* Node /syscon@ff100000 index 4
* driver rockchip_rk3328_grf parent None
*/
static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
.reg = {0xff100000, 0x1000},
};
U_BOOT_DRVINFO(syscon_at_ff100000) = {
.name = "rockchip_rk3328_grf",
.plat = &dtv_syscon_at_ff100000,
.plat_size = sizeof(dtv_syscon_at_ff100000),
.parent_idx = -1,
};

51
package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h
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@ -1,51 +0,0 @@
/*
* DO NOT MODIFY
*
* Defines the structs used to hold devicetree data.
* This was generated by dtoc from a .dtb (device tree binary) file.
*/
#include <stdbool.h>
#include <linux/libfdt.h>
struct dtd_ns16550_serial {
fdt32_t clock_frequency;
struct phandle_1_arg clocks[2];
const char * dma_names[2];
fdt32_t dmas[4];
fdt32_t interrupts[3];
fdt32_t pinctrl_0;
const char * pinctrl_names;
fdt64_t reg[2];
fdt32_t reg_io_width;
fdt32_t reg_shift;
};
struct dtd_rockchip_rk3288_dw_mshc {
fdt32_t bus_width;
bool cap_sd_highspeed;
struct phandle_1_arg clocks[4];
bool disable_wp;
fdt32_t fifo_depth;
fdt32_t interrupts[3];
fdt32_t max_frequency;
fdt32_t pinctrl_0[4];
const char * pinctrl_names;
fdt64_t reg[2];
bool sd_uhs_sdr104;
bool sd_uhs_sdr12;
bool sd_uhs_sdr25;
bool sd_uhs_sdr50;
bool u_boot_spl_fifo_mode;
fdt32_t vmmc_supply;
fdt32_t vqmmc_supply;
};
struct dtd_rockchip_rk3328_cru {
fdt64_t reg[2];
fdt32_t rockchip_grf;
};
struct dtd_rockchip_rk3328_dmc {
fdt64_t reg[12];
fdt32_t rockchip_sdram_params[196];
};
struct dtd_rockchip_rk3328_grf {
fdt64_t reg[2];
};

24
package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-decl.h
View file

@ -1,24 +0,0 @@
/*
* DO NOT MODIFY
*
* Declares externs for all device/uclass instances.
* This was generated by dtoc from a .dtb (device tree binary) file.
*/
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
/* driver declarations - these allow DM_DRIVER_GET() to be used */
extern U_BOOT_DRIVER(rockchip_rk3328_cru);
extern U_BOOT_DRIVER(rockchip_rk3328_dmc);
extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
extern U_BOOT_DRIVER(ns16550_serial);
extern U_BOOT_DRIVER(rockchip_rk3328_spi);
extern U_BOOT_DRIVER(rockchip_rk3328_grf);
/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */
extern UCLASS_DRIVER(clk);
extern UCLASS_DRIVER(mmc);
extern UCLASS_DRIVER(ram);
extern UCLASS_DRIVER(serial);
extern UCLASS_DRIVER(syscon);

170
package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-plat.c
View file

@ -1,170 +0,0 @@
/*
* DO NOT MODIFY
*
* Declares the U_BOOT_DRIVER() records and platform data.
* This was generated by dtoc from a .dtb (device tree binary) file.
*/
/* Allow use of U_BOOT_DRVINFO() in this file */
#define DT_PLAT_C
#include <common.h>
#include <dm.h>
#include <dt-structs.h>
/*
* driver_info declarations, ordered by 'struct driver_info' linker_list idx:
*
* idx driver_info driver
* --- -------------------- --------------------
* 0: clock_controller_at_ff440000 rockchip_rk3328_cru
* 1: dmc rockchip_rk3328_dmc
* 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc
* 3: serial_at_ff130000 ns16550_serial
* 4: spi_at_ff190000 rockchip_rk3328_spi
* 5: syscon_at_ff100000 rockchip_rk3328_grf
* --- -------------------- --------------------
*/
/*
* Node /clock-controller@ff440000 index 0
* driver rockchip_rk3328_cru parent None
*/
static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
.reg = {0xff440000, 0x1000},
.rockchip_grf = 0x38,
};
U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
.name = "rockchip_rk3328_cru",
.plat = &dtv_clock_controller_at_ff440000,
.plat_size = sizeof(dtv_clock_controller_at_ff440000),
.parent_idx = -1,
};
/*
* Node /dmc index 1
* driver rockchip_rk3328_dmc parent None
*/
static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
.reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
0xff720000, 0x1000, 0xff798000, 0x1000},
.rockchip_sdram_params = {0x1, 0xc, 0x3, 0x1, 0x0, 0x0, 0x10, 0x10,
0x10, 0x10, 0x0, 0x8c48a18a, 0x0, 0x21, 0x482, 0x15,
0x21a, 0xff, 0x14d, 0x6, 0x1, 0x0, 0x0, 0x0,
0x43041008, 0x64, 0x140023, 0xd0, 0x220002, 0xd4, 0x10000, 0xd8,
0x703, 0xdc, 0x830004, 0xe0, 0x10000, 0xe4, 0x70003, 0xf4,
0xf011f, 0x100, 0x6090b07, 0x104, 0x2020b, 0x108, 0x2030506, 0x10c,
0x505000, 0x110, 0x3020204, 0x114, 0x1010303, 0x118, 0x2020003, 0x120,
0x303, 0x138, 0x25, 0x180, 0x3c000f, 0x184, 0x900000, 0x190,
0x7020000, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240, 0x900090c, 0x244,
0x101, 0x250, 0xf00, 0x490, 0x1, 0xffffffff, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xb, 0x28, 0x6, 0x2c,
0x0, 0x30, 0x3, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
0x77, 0x77, 0x79, 0x9},
};
U_BOOT_DRVINFO(dmc) = {
.name = "rockchip_rk3328_dmc",
.plat = &dtv_dmc,
.plat_size = sizeof(dtv_dmc),
.parent_idx = -1,
};
/*
* Node /mmc@ff500000 index 2
* driver rockchip_rk3288_dw_mshc parent None
*/
static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
.bus_width = 0x4,
.cap_sd_highspeed = true,
.clocks = {
{0, {317}},
{0, {33}},
{0, {74}},
{0, {78}},},
.disable_wp = true,
.fifo_depth = 0x100,
.interrupts = {0x0, 0xc, 0x4},
.max_frequency = 0x8f0d180,
.pinctrl_0 = {0x45, 0x46, 0x47, 0x48},
.pinctrl_names = "default",
.reg = {0xff500000, 0x4000},
.u_boot_spl_fifo_mode = true,
.vmmc_supply = 0x49,
};
U_BOOT_DRVINFO(mmc_at_ff500000) = {
.name = "rockchip_rk3288_dw_mshc",
.plat = &dtv_mmc_at_ff500000,
.plat_size = sizeof(dtv_mmc_at_ff500000),
.parent_idx = -1,
};
/*
* Node /serial@ff130000 index 3
* driver ns16550_serial parent None
*/
static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
.clock_frequency = 0x16e3600,
.clocks = {
{0, {40}},
{0, {212}},},
.dma_names = {"tx", "rx"},
.dmas = {0x10, 0x6, 0x10, 0x7},
.interrupts = {0x0, 0x39, 0x4},
.pinctrl_0 = 0x24,
.pinctrl_names = "default",
.reg = {0xff130000, 0x100},
.reg_io_width = 0x4,
.reg_shift = 0x2,
};
U_BOOT_DRVINFO(serial_at_ff130000) = {
.name = "ns16550_serial",
.plat = &dtv_serial_at_ff130000,
.plat_size = sizeof(dtv_serial_at_ff130000),
.parent_idx = -1,
};
/* Node /spi@ff190000 index 4 */
static struct dtd_rockchip_rk3328_spi dtv_spi_at_ff190000 = {
.clocks = {
{0, {32}},
{0, {209}},},
.dma_names = {"tx", "rx"},
.dmas = {0x10, 0x8, 0x10, 0x9},
.interrupts = {0x0, 0x31, 0x4},
.pinctrl_0 = {0x2c, 0x2d, 0x2e, 0x2f},
.pinctrl_names = "default",
.reg = {0xff190000, 0x1000},
};
U_BOOT_DRVINFO(spi_at_ff190000) = {
.name = "rockchip_rk3328_spi",
.plat = &dtv_spi_at_ff190000,
.plat_size = sizeof(dtv_spi_at_ff190000),
.parent_idx = -1,
};
/*
* Node /syscon@ff100000 index 5
* driver rockchip_rk3328_grf parent None
*/
static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
.reg = {0xff100000, 0x1000},
};
U_BOOT_DRVINFO(syscon_at_ff100000) = {
.name = "rockchip_rk3328_grf",
.plat = &dtv_syscon_at_ff100000,
.plat_size = sizeof(dtv_syscon_at_ff100000),
.parent_idx = -1,
};

55
package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-structs-gen.h
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@ -1,55 +0,0 @@
/*
* DO NOT MODIFY
*
* Defines the structs used to hold devicetree data.
* This was generated by dtoc from a .dtb (device tree binary) file.
*/
#include <stdbool.h>
#include <linux/libfdt.h>
struct dtd_ns16550_serial {
fdt32_t clock_frequency;
struct phandle_1_arg clocks[2];
const char * dma_names[2];
fdt32_t dmas[4];
fdt32_t interrupts[3];
fdt32_t pinctrl_0;
const char * pinctrl_names;
fdt64_t reg[2];
fdt32_t reg_io_width;
fdt32_t reg_shift;
};
struct dtd_rockchip_rk3288_dw_mshc {
fdt32_t bus_width;
bool cap_sd_highspeed;
struct phandle_1_arg clocks[4];
bool disable_wp;
fdt32_t fifo_depth;
fdt32_t interrupts[3];
fdt32_t max_frequency;
fdt32_t pinctrl_0[4];
const char * pinctrl_names;
fdt64_t reg[2];
bool u_boot_spl_fifo_mode;
fdt32_t vmmc_supply;
};
struct dtd_rockchip_rk3328_cru {
fdt64_t reg[2];
fdt32_t rockchip_grf;
};
struct dtd_rockchip_rk3328_dmc {
fdt64_t reg[12];
fdt32_t rockchip_sdram_params[196];
};
struct dtd_rockchip_rk3328_grf {
fdt64_t reg[2];
};
struct dtd_rockchip_rk3328_spi {
struct phandle_1_arg clocks[2];
const char * dma_names[2];
fdt32_t dmas[4];
fdt32_t interrupts[3];
fdt32_t pinctrl_0[4];
const char * pinctrl_names;
fdt64_t reg[2];
};

24
package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-decl.h
View file

@ -1,24 +0,0 @@
/*
* DO NOT MODIFY
*
* Declares externs for all device/uclass instances.
* This was generated by dtoc from a .dtb (device tree binary) file.
*/
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
/* driver declarations - these allow DM_DRIVER_GET() to be used */
extern U_BOOT_DRIVER(rockchip_rk3328_cru);
extern U_BOOT_DRIVER(rockchip_rk3328_dmc);
extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
extern U_BOOT_DRIVER(ns16550_serial);
extern U_BOOT_DRIVER(rockchip_rk3328_spi);
extern U_BOOT_DRIVER(rockchip_rk3328_grf);
/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */
extern UCLASS_DRIVER(clk);
extern UCLASS_DRIVER(mmc);
extern UCLASS_DRIVER(ram);
extern UCLASS_DRIVER(serial);
extern UCLASS_DRIVER(syscon);

170
package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-plat.c
View file

@ -1,170 +0,0 @@
/*
* DO NOT MODIFY
*
* Declares the U_BOOT_DRIVER() records and platform data.
* This was generated by dtoc from a .dtb (device tree binary) file.
*/
/* Allow use of U_BOOT_DRVINFO() in this file */
#define DT_PLAT_C
#include <common.h>
#include <dm.h>
#include <dt-structs.h>
/*
* driver_info declarations, ordered by 'struct driver_info' linker_list idx:
*
* idx driver_info driver
* --- -------------------- --------------------
* 0: clock_controller_at_ff440000 rockchip_rk3328_cru
* 1: dmc rockchip_rk3328_dmc
* 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc
* 3: serial_at_ff130000 ns16550_serial
* 4: spi_at_ff190000 rockchip_rk3328_spi
* 5: syscon_at_ff100000 rockchip_rk3328_grf
* --- -------------------- --------------------
*/
/*
* Node /clock-controller@ff440000 index 0
* driver rockchip_rk3328_cru parent None
*/
static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
.reg = {0xff440000, 0x1000},
.rockchip_grf = 0x38,
};
U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
.name = "rockchip_rk3328_cru",
.plat = &dtv_clock_controller_at_ff440000,
.plat_size = sizeof(dtv_clock_controller_at_ff440000),
.parent_idx = -1,
};
/*
* Node /dmc index 1
* driver rockchip_rk3328_dmc parent None
*/
static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
.reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
0xff720000, 0x1000, 0xff798000, 0x1000},
.rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0,
0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15,
0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0,
0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8,
0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8,
0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104,
0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114,
0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184,
0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240,
0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff,
0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c,
0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
0x77, 0x77, 0x79, 0x9},
};
U_BOOT_DRVINFO(dmc) = {
.name = "rockchip_rk3328_dmc",
.plat = &dtv_dmc,
.plat_size = sizeof(dtv_dmc),
.parent_idx = -1,
};
/*
* Node /mmc@ff500000 index 2
* driver rockchip_rk3288_dw_mshc parent None
*/
static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
.bus_width = 0x4,
.cap_sd_highspeed = true,
.clocks = {
{0, {317}},
{0, {33}},
{0, {74}},
{0, {78}},},
.disable_wp = true,
.fifo_depth = 0x100,
.interrupts = {0x0, 0xc, 0x4},
.max_frequency = 0x8f0d180,
.pinctrl_0 = {0x45, 0x46, 0x47, 0x48},
.pinctrl_names = "default",
.reg = {0xff500000, 0x4000},
.u_boot_spl_fifo_mode = true,
.vmmc_supply = 0x49,
};
U_BOOT_DRVINFO(mmc_at_ff500000) = {
.name = "rockchip_rk3288_dw_mshc",
.plat = &dtv_mmc_at_ff500000,
.plat_size = sizeof(dtv_mmc_at_ff500000),
.parent_idx = -1,
};
/*
* Node /serial@ff130000 index 3
* driver ns16550_serial parent None
*/
static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
.clock_frequency = 0x16e3600,
.clocks = {
{0, {40}},
{0, {212}},},
.dma_names = {"tx", "rx"},
.dmas = {0x10, 0x6, 0x10, 0x7},
.interrupts = {0x0, 0x39, 0x4},
.pinctrl_0 = 0x24,
.pinctrl_names = "default",
.reg = {0xff130000, 0x100},
.reg_io_width = 0x4,
.reg_shift = 0x2,
};
U_BOOT_DRVINFO(serial_at_ff130000) = {
.name = "ns16550_serial",
.plat = &dtv_serial_at_ff130000,
.plat_size = sizeof(dtv_serial_at_ff130000),
.parent_idx = -1,
};
/* Node /spi@ff190000 index 4 */
static struct dtd_rockchip_rk3328_spi dtv_spi_at_ff190000 = {
.clocks = {
{0, {32}},
{0, {209}},},
.dma_names = {"tx", "rx"},
.dmas = {0x10, 0x8, 0x10, 0x9},
.interrupts = {0x0, 0x31, 0x4},
.pinctrl_0 = {0x2c, 0x2d, 0x2e, 0x2f},
.pinctrl_names = "default",
.reg = {0xff190000, 0x1000},
};
U_BOOT_DRVINFO(spi_at_ff190000) = {
.name = "rockchip_rk3328_spi",
.plat = &dtv_spi_at_ff190000,
.plat_size = sizeof(dtv_spi_at_ff190000),
.parent_idx = -1,
};
/*
* Node /syscon@ff100000 index 5
* driver rockchip_rk3328_grf parent None
*/
static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
.reg = {0xff100000, 0x1000},
};
U_BOOT_DRVINFO(syscon_at_ff100000) = {
.name = "rockchip_rk3328_grf",
.plat = &dtv_syscon_at_ff100000,
.plat_size = sizeof(dtv_syscon_at_ff100000),
.parent_idx = -1,
};

55
package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-structs-gen.h
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@ -1,55 +0,0 @@
/*
* DO NOT MODIFY
*
* Defines the structs used to hold devicetree data.
* This was generated by dtoc from a .dtb (device tree binary) file.
*/
#include <stdbool.h>
#include <linux/libfdt.h>
struct dtd_ns16550_serial {
fdt32_t clock_frequency;
struct phandle_1_arg clocks[2];
const char * dma_names[2];
fdt32_t dmas[4];
fdt32_t interrupts[3];
fdt32_t pinctrl_0;
const char * pinctrl_names;
fdt64_t reg[2];
fdt32_t reg_io_width;
fdt32_t reg_shift;
};
struct dtd_rockchip_rk3288_dw_mshc {
fdt32_t bus_width;
bool cap_sd_highspeed;
struct phandle_1_arg clocks[4];
bool disable_wp;
fdt32_t fifo_depth;
fdt32_t interrupts[3];
fdt32_t max_frequency;
fdt32_t pinctrl_0[4];
const char * pinctrl_names;
fdt64_t reg[2];
bool u_boot_spl_fifo_mode;
fdt32_t vmmc_supply;
};
struct dtd_rockchip_rk3328_cru {
fdt64_t reg[2];
fdt32_t rockchip_grf;
};
struct dtd_rockchip_rk3328_dmc {
fdt64_t reg[12];
fdt32_t rockchip_sdram_params[196];
};
struct dtd_rockchip_rk3328_grf {
fdt64_t reg[2];
};
struct dtd_rockchip_rk3328_spi {
struct phandle_1_arg clocks[2];
const char * dma_names[2];
fdt32_t dmas[4];
fdt32_t interrupts[3];
fdt32_t pinctrl_0[4];
const char * pinctrl_names;
fdt64_t reg[2];
};

24
package/boot/uboot-rockchip/src/of-platdata/roc-cc-rk3328/dt-decl.h
View file

@ -1,24 +0,0 @@
/*
* DO NOT MODIFY
*
* Declares externs for all device/uclass instances.
* This was generated by dtoc from a .dtb (device tree binary) file.
*/
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
/* driver declarations - these allow DM_DRIVER_GET() to be used */
extern U_BOOT_DRIVER(rockchip_rk3328_cru);
extern U_BOOT_DRIVER(rockchip_rk3328_dmc);
extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
extern U_BOOT_DRIVER(ns16550_serial);
extern U_BOOT_DRIVER(rockchip_rk3328_grf);
/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */
extern UCLASS_DRIVER(clk);
extern UCLASS_DRIVER(mmc);
extern UCLASS_DRIVER(ram);
extern UCLASS_DRIVER(serial);
extern UCLASS_DRIVER(syscon);

189
package/boot/uboot-rockchip/src/of-platdata/roc-cc-rk3328/dt-plat.c
View file

@ -1,189 +0,0 @@
/*
* DO NOT MODIFY
*
* Declares the U_BOOT_DRIVER() records and platform data.
* This was generated by dtoc from a .dtb (device tree binary) file.
*/
/* Allow use of U_BOOT_DRVINFO() in this file */
#define DT_PLAT_C
#include <common.h>
#include <dm.h>
#include <dt-structs.h>
/*
* driver_info declarations, ordered by 'struct driver_info' linker_list idx:
*
* idx driver_info driver
* --- -------------------- --------------------
* 0: clock_controller_at_ff440000 rockchip_rk3328_cru
* 1: dmc rockchip_rk3328_dmc
* 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc
* 3: mmc_at_ff520000 rockchip_rk3288_dw_mshc
* 4: serial_at_ff130000 ns16550_serial
* 5: syscon_at_ff100000 rockchip_rk3328_grf
* --- -------------------- --------------------
*/
/*
* Node /clock-controller@ff440000 index 0
* driver rockchip_rk3328_cru parent None
*/
static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
.reg = {0xff440000, 0x1000},
.rockchip_grf = 0x3a,
};
U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
.name = "rockchip_rk3328_cru",
.plat = &dtv_clock_controller_at_ff440000,
.plat_size = sizeof(dtv_clock_controller_at_ff440000),
.parent_idx = -1,
};
/*
* Node /dmc index 1
* driver rockchip_rk3328_dmc parent None
*/
static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
.reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
0xff720000, 0x1000, 0xff798000, 0x1000},
.rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0,
0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15,
0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0,
0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8,
0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8,
0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104,
0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114,
0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184,
0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240,
0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff,
0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c,
0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
0x77, 0x77, 0x79, 0x9},
};
U_BOOT_DRVINFO(dmc) = {
.name = "rockchip_rk3328_dmc",
.plat = &dtv_dmc,
.plat_size = sizeof(dtv_dmc),
.parent_idx = -1,
};
/*
* Node /mmc@ff500000 index 2
* driver rockchip_rk3288_dw_mshc parent None
*/
static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
.bus_width = 0x4,
.cap_mmc_highspeed = true,
.cap_sd_highspeed = true,
.clocks = {
{0, {317}},
{0, {33}},
{0, {74}},
{0, {78}},},
.disable_wp = true,
.fifo_depth = 0x100,
.interrupts = {0x0, 0xc, 0x4},
.max_frequency = 0x8f0d180,
.pinctrl_0 = {0x47, 0x48, 0x49, 0x4a},
.pinctrl_names = "default",
.reg = {0xff500000, 0x4000},
.sd_uhs_sdr104 = true,
.sd_uhs_sdr12 = true,
.sd_uhs_sdr25 = true,
.sd_uhs_sdr50 = true,
.u_boot_spl_fifo_mode = true,
.vmmc_supply = 0x4b,
.vqmmc_supply = 0x1e,
};
U_BOOT_DRVINFO(mmc_at_ff500000) = {
.name = "rockchip_rk3288_dw_mshc",
.plat = &dtv_mmc_at_ff500000,
.plat_size = sizeof(dtv_mmc_at_ff500000),
.parent_idx = -1,
};
/*
* Node /mmc@ff520000 index 3
* driver rockchip_rk3288_dw_mshc parent None
*/
static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff520000 = {
.bus_width = 0x8,
.cap_mmc_highspeed = true,
.clocks = {
{0, {319}},
{0, {35}},
{0, {76}},
{0, {80}},},
.fifo_depth = 0x100,
.interrupts = {0x0, 0xe, 0x4},
.max_frequency = 0x8f0d180,
.mmc_ddr_1_8v = true,
.mmc_hs200_1_8v = true,
.non_removable = true,
.pinctrl_0 = {0x4c, 0x4d, 0x4e, 0x0},
.pinctrl_names = "default",
.reg = {0xff520000, 0x4000},
.u_boot_spl_fifo_mode = true,
.vmmc_supply = 0x1c,
.vqmmc_supply = 0x1d,
};
U_BOOT_DRVINFO(mmc_at_ff520000) = {
.name = "rockchip_rk3288_dw_mshc",
.plat = &dtv_mmc_at_ff520000,
.plat_size = sizeof(dtv_mmc_at_ff520000),
.parent_idx = -1,
};
/*
* Node /serial@ff130000 index 4
* driver ns16550_serial parent None
*/
static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
.clock_frequency = 0x16e3600,
.clocks = {
{0, {40}},
{0, {212}},},
.dma_names = {"tx", "rx"},
.dmas = {0x10, 0x6, 0x10, 0x7},
.interrupts = {0x0, 0x39, 0x4},
.pinctrl_0 = 0x26,
.pinctrl_names = "default",
.reg = {0xff130000, 0x100},
.reg_io_width = 0x4,
.reg_shift = 0x2,
};
U_BOOT_DRVINFO(serial_at_ff130000) = {
.name = "ns16550_serial",
.plat = &dtv_serial_at_ff130000,
.plat_size = sizeof(dtv_serial_at_ff130000),
.parent_idx = -1,
};
/*
* Node /syscon@ff100000 index 5
* driver rockchip_rk3328_grf parent None
*/
static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
.reg = {0xff100000, 0x1000},
};
U_BOOT_DRVINFO(syscon_at_ff100000) = {
.name = "rockchip_rk3328_grf",
.plat = &dtv_syscon_at_ff100000,
.plat_size = sizeof(dtv_syscon_at_ff100000),
.parent_idx = -1,
};

55
package/boot/uboot-rockchip/src/of-platdata/roc-cc-rk3328/dt-structs-gen.h
View file

@ -1,55 +0,0 @@
/*
* DO NOT MODIFY
*
* Defines the structs used to hold devicetree data.
* This was generated by dtoc from a .dtb (device tree binary) file.
*/
#include <stdbool.h>
#include <linux/libfdt.h>
struct dtd_ns16550_serial {
fdt32_t clock_frequency;
struct phandle_1_arg clocks[2];
const char * dma_names[2];
fdt32_t dmas[4];
fdt32_t interrupts[3];
fdt32_t pinctrl_0;
const char * pinctrl_names;
fdt64_t reg[2];
fdt32_t reg_io_width;
fdt32_t reg_shift;
};
struct dtd_rockchip_rk3288_dw_mshc {
fdt32_t bus_width;
bool cap_mmc_highspeed;
bool cap_sd_highspeed;
struct phandle_1_arg clocks[4];
bool disable_wp;
fdt32_t fifo_depth;
fdt32_t interrupts[3];
fdt32_t max_frequency;
bool mmc_ddr_1_8v;
bool mmc_hs200_1_8v;
bool non_removable;
fdt32_t pinctrl_0[4];
const char * pinctrl_names;
fdt64_t reg[2];
bool sd_uhs_sdr104;
bool sd_uhs_sdr12;
bool sd_uhs_sdr25;
bool sd_uhs_sdr50;
bool u_boot_spl_fifo_mode;
fdt32_t vmmc_supply;
fdt32_t vqmmc_supply;
};
struct dtd_rockchip_rk3328_cru {
fdt64_t reg[2];
fdt32_t rockchip_grf;
};
struct dtd_rockchip_rk3328_dmc {
fdt64_t reg[12];
fdt32_t rockchip_sdram_params[196];
};
struct dtd_rockchip_rk3328_grf {
fdt64_t reg[2];
};

24
package/boot/uboot-rockchip/src/of-platdata/rock-pi-e-rk3328/dt-decl.h
View file

@ -1,24 +0,0 @@
/*
* DO NOT MODIFY
*
* Declares externs for all device/uclass instances.
* This was generated by dtoc from a .dtb (device tree binary) file.
*/
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
/* driver declarations - these allow DM_DRIVER_GET() to be used */
extern U_BOOT_DRIVER(rockchip_rk3328_cru);
extern U_BOOT_DRIVER(rockchip_rk3328_dmc);
extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
extern U_BOOT_DRIVER(ns16550_serial);
extern U_BOOT_DRIVER(rockchip_rk3328_grf);
/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */
extern UCLASS_DRIVER(clk);
extern UCLASS_DRIVER(mmc);
extern UCLASS_DRIVER(ram);
extern UCLASS_DRIVER(serial);
extern UCLASS_DRIVER(syscon);

189
package/boot/uboot-rockchip/src/of-platdata/rock-pi-e-rk3328/dt-plat.c
View file

@ -1,189 +0,0 @@
/*
* DO NOT MODIFY
*
* Declares the U_BOOT_DRIVER() records and platform data.
* This was generated by dtoc from a .dtb (device tree binary) file.
*/
/* Allow use of U_BOOT_DRVINFO() in this file */
#define DT_PLAT_C
#include <common.h>
#include <dm.h>
#include <dt-structs.h>
/*
* driver_info declarations, ordered by 'struct driver_info' linker_list idx:
*
* idx driver_info driver
* --- -------------------- --------------------
* 0: clock_controller_at_ff440000 rockchip_rk3328_cru
* 1: dmc rockchip_rk3328_dmc
* 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc
* 3: mmc_at_ff520000 rockchip_rk3288_dw_mshc
* 4: serial_at_ff130000 ns16550_serial
* 5: syscon_at_ff100000 rockchip_rk3328_grf
* --- -------------------- --------------------
*/
/*
* Node /clock-controller@ff440000 index 0
* driver rockchip_rk3328_cru parent None
*/
static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
.reg = {0xff440000, 0x1000},
.rockchip_grf = 0x38,
};
U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
.name = "rockchip_rk3328_cru",
.plat = &dtv_clock_controller_at_ff440000,
.plat_size = sizeof(dtv_clock_controller_at_ff440000),
.parent_idx = -1,
};
/*
* Node /dmc index 1
* driver rockchip_rk3328_dmc parent None
*/
static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
.reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
0xff720000, 0x1000, 0xff798000, 0x1000},
.rockchip_sdram_params = {0x1, 0xc, 0x3, 0x1, 0x0, 0x0, 0x10, 0x10,
0x10, 0x10, 0x0, 0x9028b189, 0x0, 0x21, 0x482, 0x15,
0x222, 0xff, 0x14d, 0x3, 0x1, 0x0, 0x0, 0x0,
0x43041001, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x20000, 0xd8,
0x100, 0xdc, 0x3200000, 0xe0, 0x0, 0xe4, 0x90000, 0xf4,
0xf011f, 0x100, 0x7090b06, 0x104, 0x50209, 0x108, 0x3030407, 0x10c,
0x202006, 0x110, 0x3020204, 0x114, 0x3030202, 0x120, 0x903, 0x180,
0x800020, 0x184, 0x0, 0x190, 0x7010001, 0x198, 0x5001100, 0x1a0,
0xc0400003, 0x240, 0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490,
0x1, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xa, 0x28, 0x6, 0x2c,
0x0, 0x30, 0x5, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
0x77, 0x77, 0x79, 0x9},
};
U_BOOT_DRVINFO(dmc) = {
.name = "rockchip_rk3328_dmc",
.plat = &dtv_dmc,
.plat_size = sizeof(dtv_dmc),
.parent_idx = -1,
};
/*
* Node /mmc@ff500000 index 2
* driver rockchip_rk3288_dw_mshc parent None
*/
static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
.bus_width = 0x4,
.cap_mmc_highspeed = true,
.cap_sd_highspeed = true,
.card_detect_delay = 0xc8,
.clocks = {
{0, {317}},
{0, {33}},
{0, {74}},
{0, {78}},},
.disable_wp = true,
.fifo_depth = 0x100,
.interrupts = {0x0, 0xc, 0x4},
.max_frequency = 0x8f0d180,
.num_slots = 0x1,
.pinctrl_0 = {0x45, 0x46, 0x47, 0x48},
.pinctrl_names = "default",
.reg = {0xff500000, 0x4000},
.supports_sd = true,
.u_boot_spl_fifo_mode = true,
.vmmc_supply = 0x49,
};
U_BOOT_DRVINFO(mmc_at_ff500000) = {
.name = "rockchip_rk3288_dw_mshc",
.plat = &dtv_mmc_at_ff500000,
.plat_size = sizeof(dtv_mmc_at_ff500000),
.parent_idx = -1,
};
/*
* Node /mmc@ff520000 index 3
* driver rockchip_rk3288_dw_mshc parent None
*/
static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff520000 = {
.bus_width = 0x8,
.cap_mmc_highspeed = true,
.clocks = {
{0, {319}},
{0, {35}},
{0, {76}},
{0, {80}},},
.disable_wp = true,
.fifo_depth = 0x100,
.interrupts = {0x0, 0xe, 0x4},
.max_frequency = 0x8f0d180,
.mmc_hs200_1_8v = true,
.non_removable = true,
.num_slots = 0x1,
.pinctrl_0 = {0x4a, 0x4b, 0x4c, 0x0},
.pinctrl_names = "default",
.reg = {0xff520000, 0x4000},
.supports_emmc = true,
.u_boot_spl_fifo_mode = true,
.vmmc_supply = 0x1c,
.vqmmc_supply = 0x1d,
};
U_BOOT_DRVINFO(mmc_at_ff520000) = {
.name = "rockchip_rk3288_dw_mshc",
.plat = &dtv_mmc_at_ff520000,
.plat_size = sizeof(dtv_mmc_at_ff520000),
.parent_idx = -1,
};
/*
* Node /serial@ff130000 index 4
* driver ns16550_serial parent None
*/
static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
.clock_frequency = 0x16e3600,
.clocks = {
{0, {40}},
{0, {212}},},
.dma_names = {"tx", "rx"},
.dmas = {0x10, 0x6, 0x10, 0x7},
.interrupts = {0x0, 0x39, 0x4},
.pinctrl_0 = 0x24,
.pinctrl_names = "default",
.reg = {0xff130000, 0x100},
.reg_io_width = 0x4,
.reg_shift = 0x2,
};
U_BOOT_DRVINFO(serial_at_ff130000) = {
.name = "ns16550_serial",
.plat = &dtv_serial_at_ff130000,
.plat_size = sizeof(dtv_serial_at_ff130000),
.parent_idx = -1,
};
/*
* Node /syscon@ff100000 index 5
* driver rockchip_rk3328_grf parent None
*/
static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
.reg = {0xff100000, 0x1000},
};
U_BOOT_DRVINFO(syscon_at_ff100000) = {
.name = "rockchip_rk3328_grf",
.plat = &dtv_syscon_at_ff100000,
.plat_size = sizeof(dtv_syscon_at_ff100000),
.parent_idx = -1,
};

54
package/boot/uboot-rockchip/src/of-platdata/rock-pi-e-rk3328/dt-structs-gen.h
View file

@ -1,54 +0,0 @@
/*
* DO NOT MODIFY
*
* Defines the structs used to hold devicetree data.
* This was generated by dtoc from a .dtb (device tree binary) file.
*/
#include <stdbool.h>
#include <linux/libfdt.h>
struct dtd_ns16550_serial {
fdt32_t clock_frequency;
struct phandle_1_arg clocks[2];
const char * dma_names[2];
fdt32_t dmas[4];
fdt32_t interrupts[3];
fdt32_t pinctrl_0;
const char * pinctrl_names;
fdt64_t reg[2];
fdt32_t reg_io_width;
fdt32_t reg_shift;
};
struct dtd_rockchip_rk3288_dw_mshc {
fdt32_t bus_width;
bool cap_mmc_highspeed;
bool cap_sd_highspeed;
fdt32_t card_detect_delay;
struct phandle_1_arg clocks[4];
bool disable_wp;
fdt32_t fifo_depth;
fdt32_t interrupts[3];
fdt32_t max_frequency;
bool mmc_hs200_1_8v;
bool non_removable;
fdt32_t num_slots;
fdt32_t pinctrl_0[4];
const char * pinctrl_names;
fdt64_t reg[2];
bool supports_emmc;
bool supports_sd;
bool u_boot_spl_fifo_mode;
fdt32_t vmmc_supply;
fdt32_t vqmmc_supply;
};
struct dtd_rockchip_rk3328_cru {
fdt64_t reg[2];
fdt32_t rockchip_grf;
};
struct dtd_rockchip_rk3328_dmc {
fdt64_t reg[12];
fdt32_t rockchip_sdram_params[196];
};
struct dtd_rockchip_rk3328_grf {
fdt64_t reg[2];
};

27
package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-decl.h
View file

@ -1,27 +0,0 @@
/*
* DO NOT MODIFY
*
* Declares externs for all device/uclass instances.
* This was generated by dtoc from a .dtb (device tree binary) file.
*/
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
/* driver declarations - these allow DM_DRIVER_GET() to be used */
extern U_BOOT_DRIVER(rockchip_rk3328_cru);
extern U_BOOT_DRIVER(rockchip_rk3328_dmc);
extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
extern U_BOOT_DRIVER(ns16550_serial);
extern U_BOOT_DRIVER(rockchip_rk3328_spi);
extern U_BOOT_DRIVER(jedec_spi_nor);
extern U_BOOT_DRIVER(rockchip_rk3328_grf);
/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */
extern UCLASS_DRIVER(clk);
extern UCLASS_DRIVER(mmc);
extern UCLASS_DRIVER(ram);
extern UCLASS_DRIVER(serial);
extern UCLASS_DRIVER(spi_flash);
extern UCLASS_DRIVER(syscon);

219
package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-plat.c
View file

@ -1,219 +0,0 @@
/*
* DO NOT MODIFY
*
* Declares the U_BOOT_DRIVER() records and platform data.
* This was generated by dtoc from a .dtb (device tree binary) file.
*/
/* Allow use of U_BOOT_DRVINFO() in this file */
#define DT_PLAT_C
#include <common.h>
#include <dm.h>
#include <dt-structs.h>
/*
* driver_info declarations, ordered by 'struct driver_info' linker_list idx:
*
* idx driver_info driver
* --- -------------------- --------------------
* 0: clock_controller_at_ff440000 rockchip_rk3328_cru
* 1: dmc rockchip_rk3328_dmc
* 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc
* 3: mmc_at_ff520000 rockchip_rk3288_dw_mshc
* 4: serial_at_ff130000 ns16550_serial
* 5: spi_at_ff190000 rockchip_rk3328_spi
* 6: spiflash_at_0 jedec_spi_nor
* 7: syscon_at_ff100000 rockchip_rk3328_grf
* --- -------------------- --------------------
*/
/*
* Node /clock-controller@ff440000 index 0
* driver rockchip_rk3328_cru parent None
*/
static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
.reg = {0xff440000, 0x1000},
.rockchip_grf = 0x3b,
};
U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
.name = "rockchip_rk3328_cru",
.plat = &dtv_clock_controller_at_ff440000,
.plat_size = sizeof(dtv_clock_controller_at_ff440000),
.parent_idx = -1,
};
/*
* Node /dmc index 1
* driver rockchip_rk3328_dmc parent None
*/
static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
.reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
0xff720000, 0x1000, 0xff798000, 0x1000},
.rockchip_sdram_params = {0x1, 0xc, 0x3, 0x1, 0x0, 0x0, 0x10, 0x10,
0x10, 0x10, 0x0, 0x98899459, 0x0, 0x2e, 0x544, 0x15,
0x432, 0xff, 0x320, 0x6, 0x1, 0x0, 0x1, 0x0,
0x43041008, 0x64, 0x300054, 0xd0, 0x500002, 0xd4, 0x10000, 0xd8,
0xe03, 0xdc, 0x43001a, 0xe0, 0x10000, 0xe4, 0xe0005, 0xf4,
0xf011f, 0x100, 0xb141b11, 0x104, 0x3031a, 0x108, 0x3060809, 0x10c,
0x606000, 0x110, 0x8020409, 0x114, 0x1010606, 0x118, 0x2020004, 0x120,
0x404, 0x138, 0x58, 0x180, 0x900024, 0x184, 0x1400000, 0x190,
0x7050002, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240, 0xa020b28, 0x244,
0x101, 0x250, 0xf00, 0x490, 0x1, 0xffffffff, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xb, 0x28, 0xc, 0x2c,
0x0, 0x30, 0x6, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
0x77, 0x77, 0x79, 0x9},
};
U_BOOT_DRVINFO(dmc) = {
.name = "rockchip_rk3328_dmc",
.plat = &dtv_dmc,
.plat_size = sizeof(dtv_dmc),
.parent_idx = -1,
};
/*
* Node /mmc@ff500000 index 2
* driver rockchip_rk3288_dw_mshc parent None
*/
static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
.bus_width = 0x4,
.cap_mmc_highspeed = true,
.cap_sd_highspeed = true,
.clocks = {
{0, {317}},
{0, {33}},
{0, {74}},
{0, {78}},},
.disable_wp = true,
.fifo_depth = 0x100,
.interrupts = {0x0, 0xc, 0x4},
.max_frequency = 0x8f0d180,
.pinctrl_0 = {0x4a, 0x4b, 0x4c, 0x4d},
.pinctrl_names = "default",
.reg = {0xff500000, 0x4000},
.u_boot_spl_fifo_mode = true,
.vmmc_supply = 0x4e,
};
U_BOOT_DRVINFO(mmc_at_ff500000) = {
.name = "rockchip_rk3288_dw_mshc",
.plat = &dtv_mmc_at_ff500000,
.plat_size = sizeof(dtv_mmc_at_ff500000),
.parent_idx = -1,
};
/*
* Node /mmc@ff520000 index 3
* driver rockchip_rk3288_dw_mshc parent None
*/
static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff520000 = {
.bus_width = 0x8,
.cap_mmc_highspeed = true,
.clocks = {
{0, {319}},
{0, {35}},
{0, {76}},
{0, {80}},},
.fifo_depth = 0x100,
.interrupts = {0x0, 0xe, 0x4},
.max_frequency = 0x8f0d180,
.mmc_hs200_1_8v = true,
.non_removable = true,
.pinctrl_0 = {0x4f, 0x50, 0x51, 0x0},
.pinctrl_names = "default",
.reg = {0xff520000, 0x4000},
.u_boot_spl_fifo_mode = true,
.vmmc_supply = 0x1e,
.vqmmc_supply = 0x1f,
};
U_BOOT_DRVINFO(mmc_at_ff520000) = {
.name = "rockchip_rk3288_dw_mshc",
.plat = &dtv_mmc_at_ff520000,
.plat_size = sizeof(dtv_mmc_at_ff520000),
.parent_idx = -1,
};
/*
* Node /serial@ff130000 index 4
* driver ns16550_serial parent None
*/
static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
.clock_frequency = 0x16e3600,
.clocks = {
{0, {40}},
{0, {212}},},
.dma_names = {"tx", "rx"},
.dmas = {0x10, 0x6, 0x10, 0x7},
.interrupts = {0x0, 0x39, 0x4},
.pinctrl_0 = 0x27,
.pinctrl_names = "default",
.reg = {0xff130000, 0x100},
.reg_io_width = 0x4,
.reg_shift = 0x2,
};
U_BOOT_DRVINFO(serial_at_ff130000) = {
.name = "ns16550_serial",
.plat = &dtv_serial_at_ff130000,
.plat_size = sizeof(dtv_serial_at_ff130000),
.parent_idx = -1,
};
/* Node /spi@ff190000 index 5 */
static struct dtd_rockchip_rk3328_spi dtv_spi_at_ff190000 = {
.clocks = {
{0, {32}},
{0, {209}},},
.dma_names = {"tx", "rx"},
.dmas = {0x10, 0x8, 0x10, 0x9},
.interrupts = {0x0, 0x31, 0x4},
.pinctrl_0 = {0x2f, 0x30, 0x31, 0x32},
.pinctrl_names = "default",
.reg = {0xff190000, 0x1000},
};
U_BOOT_DRVINFO(spi_at_ff190000) = {
.name = "rockchip_rk3328_spi",
.plat = &dtv_spi_at_ff190000,
.plat_size = sizeof(dtv_spi_at_ff190000),
.parent_idx = -1,
};
/*
* Node /spi@ff190000/spiflash@0 index 6
* driver jedec_spi_nor parent None
*/
static struct dtd_jedec_spi_nor dtv_spiflash_at_0 = {
.reg = {0x0},
.spi_max_frequency = 0x2faf080,
};
U_BOOT_DRVINFO(spiflash_at_0) = {
.name = "jedec_spi_nor",
.plat = &dtv_spiflash_at_0,
.plat_size = sizeof(dtv_spiflash_at_0),
.parent_idx = 5,
};
/*
* Node /syscon@ff100000 index 7
* driver rockchip_rk3328_grf parent None
*/
static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
.reg = {0xff100000, 0x1000},
};
U_BOOT_DRVINFO(syscon_at_ff100000) = {
.name = "rockchip_rk3328_grf",
.plat = &dtv_syscon_at_ff100000,
.plat_size = sizeof(dtv_syscon_at_ff100000),
.parent_idx = -1,
};

63
package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-structs-gen.h
View file

@ -1,63 +0,0 @@
/*
* DO NOT MODIFY
*
* Defines the structs used to hold devicetree data.
* This was generated by dtoc from a .dtb (device tree binary) file.
*/
#include <stdbool.h>
#include <linux/libfdt.h>
struct dtd_jedec_spi_nor {
fdt32_t reg[1];
fdt32_t spi_max_frequency;
};
struct dtd_ns16550_serial {
fdt32_t clock_frequency;
struct phandle_1_arg clocks[2];
const char * dma_names[2];
fdt32_t dmas[4];
fdt32_t interrupts[3];
fdt32_t pinctrl_0;
const char * pinctrl_names;
fdt64_t reg[2];
fdt32_t reg_io_width;
fdt32_t reg_shift;
};
struct dtd_rockchip_rk3288_dw_mshc {
fdt32_t bus_width;
bool cap_mmc_highspeed;
bool cap_sd_highspeed;
struct phandle_1_arg clocks[4];
bool disable_wp;
fdt32_t fifo_depth;
fdt32_t interrupts[3];
fdt32_t max_frequency;
bool mmc_hs200_1_8v;
bool non_removable;
fdt32_t pinctrl_0[4];
const char * pinctrl_names;
fdt64_t reg[2];
bool u_boot_spl_fifo_mode;
fdt32_t vmmc_supply;
fdt32_t vqmmc_supply;
};
struct dtd_rockchip_rk3328_cru {
fdt64_t reg[2];
fdt32_t rockchip_grf;
};
struct dtd_rockchip_rk3328_dmc {
fdt64_t reg[12];
fdt32_t rockchip_sdram_params[196];
};
struct dtd_rockchip_rk3328_grf {
fdt64_t reg[2];
};
struct dtd_rockchip_rk3328_spi {
struct phandle_1_arg clocks[2];
const char * dma_names[2];
fdt32_t dmas[4];
fdt32_t interrupts[3];
fdt32_t pinctrl_0[4];
const char * pinctrl_names;
fdt64_t reg[2];
};

2
package/boot/uboot-sifiveu/Makefile
View file

@ -10,6 +10,8 @@ PKG_RELEASE:=1
PKG_VERSION:=2022.10
PKG_HASH:=50b4482a505bc281ba8470c399a3c26e145e29b23500bc35c50debd7fa46bdf8
UBOOT_USE_INTREE_DTC:=1
include $(INCLUDE_DIR)/u-boot.mk
include $(INCLUDE_DIR)/package.mk

30
package/boot/uboot-sifiveu/patches/300-force-pylibfdt-build.patch
View file

@ -1,30 +0,0 @@
--- a/Makefile
+++ b/Makefile
@@ -2028,26 +2028,7 @@ endif
# Check dtc and pylibfdt, if DTC is provided, else build them
PHONY += scripts_dtc
scripts_dtc: scripts_basic
- $(Q)if test "$(DTC)" = "$(DTC_INTREE)"; then \
- $(MAKE) $(build)=scripts/dtc; \
- else \
- if ! $(DTC) -v >/dev/null; then \
- echo '*** Failed to check dtc version: $(DTC)'; \
- false; \
- else \
- if test "$(call dtc-version)" -lt $(DTC_MIN_VERSION); then \
- echo '*** Your dtc is too old, please upgrade to dtc $(DTC_MIN_VERSION) or newer'; \
- false; \
- else \
- if [ -n "$(CONFIG_PYLIBFDT)" ]; then \
- if ! echo "import libfdt" | $(PYTHON3) 2>/dev/null; then \
- echo '*** pylibfdt does not seem to be available with $(PYTHON3)'; \
- false; \
- fi; \
- fi; \
- fi; \
- fi; \
- fi
+ $(MAKE) $(build)=scripts/dtc
# ---------------------------------------------------------------------------
quiet_cmd_cpp_lds = LDS $@

2
package/boot/uboot-sunxi/Makefile
View file

@ -15,6 +15,8 @@ PKG_HASH:=e31cac91545ff41b71cec5d8c22afd695645cd6e2a442ccdacacd60534069341
PKG_MAINTAINER:=Zoltan HERPAI <wigyori@uid0.hu>
UBOOT_USE_INTREE_DTC:=1
include $(INCLUDE_DIR)/u-boot.mk
include $(INCLUDE_DIR)/package.mk

30
package/boot/uboot-sunxi/patches/300-force-pylibfdt-build.patch
View file

@ -1,30 +0,0 @@
--- a/Makefile
+++ b/Makefile
@@ -2000,26 +2000,7 @@ endif
# Check dtc and pylibfdt, if DTC is provided, else build them
PHONY += scripts_dtc
scripts_dtc: scripts_basic
- $(Q)if test "$(DTC)" = "$(DTC_INTREE)"; then \
- $(MAKE) $(build)=scripts/dtc; \
- else \
- if ! $(DTC) -v >/dev/null; then \
- echo '*** Failed to check dtc version: $(DTC)'; \
- false; \
- else \
- if test "$(call dtc-version)" -lt $(DTC_MIN_VERSION); then \
- echo '*** Your dtc is too old, please upgrade to dtc $(DTC_MIN_VERSION) or newer'; \
- false; \
- else \
- if [ -n "$(CONFIG_PYLIBFDT)" ]; then \
- if ! echo "import libfdt" | $(PYTHON3) 2>/dev/null; then \
- echo '*** pylibfdt does not seem to be available with $(PYTHON3)'; \
- false; \
- fi; \
- fi; \
- fi; \
- fi; \
- fi
+ $(MAKE) $(build)=scripts/dtc
# ---------------------------------------------------------------------------
quiet_cmd_cpp_lds = LDS $@

8
package/kernel/mwlwifi/Makefile
View file

@ -8,16 +8,16 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=mwlwifi
PKG_RELEASE=2
PKG_RELEASE=1
PKG_LICENSE:=ISC
PKG_LICENSE_FILES:=
PKG_SOURCE_URL:=https://github.com/kaloz/mwlwifi
PKG_SOURCE_PROTO:=git
PKG_SOURCE_DATE:=2023-04-29
PKG_SOURCE_VERSION:=6a436714d2ea0d0adf39fc4d7d45e6a17fcc9371
PKG_MIRROR_HASH:=dcc320a8f859b732ff65c7ded0b5199a625bfba05a775a6bed15ed3c10cb2748
PKG_SOURCE_DATE:=2023-11-20
PKG_SOURCE_VERSION:=2a5a4ae31a2ad1b432a1dcb6ef6c3298e3330b2c
PKG_MIRROR_HASH:=b1151051ed6eba063c05916d8dbc4f03f804772d217e8c65b7baa263ded7a961
PKG_MAINTAINER:=Imre Kaloz <kaloz@openwrt.org>
PKG_BUILD_PARALLEL:=1

39
package/kernel/mwlwifi/patches/001-Fix-compilation-warning-with-64-bit-system.patch
View file

@ -117,11 +117,9 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
hif/pcie/tx_ndp.c | 2 +-
4 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/debugfs.c b/debugfs.c
index 39b09fd..42efd28 100644
--- a/debugfs.c
+++ b/debugfs.c
@@ -1332,7 +1332,7 @@ done:
@@ -1342,7 +1342,7 @@ done:
priv->reg_value);
else
len += scnprintf(p + len, size - len,
@ -130,11 +128,9 @@ index 39b09fd..42efd28 100644
ret, priv->reg_type, priv->reg_offset,
priv->reg_value);
diff --git a/hif/fwcmd.c b/hif/fwcmd.c
index 376b58f..582c8d2 100644
--- a/hif/fwcmd.c
+++ b/hif/fwcmd.c
@@ -3604,7 +3604,7 @@ int mwl_fwcmd_get_fw_core_dump(struct ieee80211_hw *hw,
@@ -3623,7 +3623,7 @@ int mwl_fwcmd_get_fw_core_dump(struct ie
core_dump->size_kb = pcmd->cmd_data.coredump.size_kb;
core_dump->flags = pcmd->cmd_data.coredump.flags;
memcpy(buff,
@ -143,11 +139,20 @@ index 376b58f..582c8d2 100644
sizeof(struct hostcmd_cmd_get_fw_core_dump) -
sizeof(struct hostcmd_cmd_get_fw_core_dump_)),
MAX_CORE_DUMP_BUFFER);
diff --git a/hif/pcie/pcie.c b/hif/pcie/pcie.c
index 24453b6..5b6c633 100644
--- a/hif/pcie/8964/tx_ndp.c
+++ b/hif/pcie/8964/tx_ndp.c
@@ -336,7 +336,7 @@ int pcie_tx_init_ndp(struct ieee80211_hw
if (sizeof(struct pcie_tx_ctrl_ndp) >
sizeof(tx_info->driver_data)) {
- wiphy_err(hw->wiphy, "driver data is not enough: %d (%d)\n",
+ wiphy_err(hw->wiphy, "driver data is not enough: %zu (%zu)\n",
sizeof(struct pcie_tx_ctrl_ndp),
sizeof(tx_info->driver_data));
return -ENOMEM;
--- a/hif/pcie/pcie.c
+++ b/hif/pcie/pcie.c
@@ -1320,8 +1320,8 @@ static void pcie_bf_mimo_ctrl_decode(struct mwl_priv *priv,
@@ -1464,8 +1464,8 @@ static void pcie_bf_mimo_ctrl_decode(str
&fp_data->f_pos);
filp_close(fp_data, current->files);
} else {
@ -158,19 +163,3 @@ index 24453b6..5b6c633 100644
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(5,10,0)
diff --git a/hif/pcie/tx_ndp.c b/hif/pcie/tx_ndp.c
index 6758cde..3140a2e 100644
--- a/hif/pcie/tx_ndp.c
+++ b/hif/pcie/tx_ndp.c
@@ -335,7 +335,7 @@ int pcie_tx_init_ndp(struct ieee80211_hw *hw)
if (sizeof(struct pcie_tx_ctrl_ndp) >
sizeof(tx_info->status.status_driver_data)) {
- wiphy_err(hw->wiphy, "driver data is not enough: %d (%d)\n",
+ wiphy_err(hw->wiphy, "driver data is not enough: %zu (%zu)\n",
sizeof(struct pcie_tx_ctrl_ndp),
sizeof(tx_info->status.status_driver_data));
return -ENOMEM;
--
2.39.2

2
package/kernel/mwlwifi/patches/004-mwlwifi-fix-PCIe-DT-node-null-pointer-dereference.patch
View file

@ -19,7 +19,7 @@ Signed-off-by: Robert Marko <robert.marko@sartura.hr>
--- a/hif/pcie/pcie.c
+++ b/hif/pcie/pcie.c
@@ -573,7 +573,8 @@ static struct device_node *pcie_get_devi
@@ -685,7 +685,8 @@ static struct device_node *pcie_get_devi
struct device_node *dev_node;
dev_node = pci_bus_to_OF_node(pcie_priv->pdev->bus);

201
package/kernel/mwlwifi/patches/005-mac80211_update.patch
View file

@ -1,6 +1,6 @@
--- a/core.c
+++ b/core.c
@@ -706,7 +706,7 @@ static void mwl_chnl_switch_event(struct
@@ -718,7 +718,7 @@ static void mwl_chnl_switch_event(struct
vif = container_of((void *)mwl_vif, struct ieee80211_vif,
drv_priv);
@ -11,7 +11,7 @@
spin_unlock_bh(&priv->vif_lock);
--- a/debugfs.c
+++ b/debugfs.c
@@ -455,9 +455,9 @@ static ssize_t mwl_debugfs_vif_read(stru
@@ -498,9 +498,9 @@ static ssize_t mwl_debugfs_vif_read(stru
switch (vif->type) {
case NL80211_IFTYPE_AP:
len += scnprintf(p + len, size - len, "type: ap\n");
@ -24,7 +24,7 @@
len += scnprintf(p + len, size - len,
"ssid: %s\n", ssid);
len += scnprintf(p + len, size - len,
@@ -479,8 +479,8 @@ static ssize_t mwl_debugfs_vif_read(stru
@@ -522,8 +522,8 @@ static ssize_t mwl_debugfs_vif_read(stru
"type: unknown\n");
break;
}
@ -35,62 +35,58 @@
len += scnprintf(p + len, size - len,
"channel: %d: width: %d\n",
chan_def->chan->hw_value,
@@ -564,28 +564,28 @@ static ssize_t mwl_debugfs_sta_read(stru
"amsdu cap: 0x%02x\n",
sta_info->amsdu_ctrl.cap);
}
- if (sta->ht_cap.ht_supported) {
+ if (sta->deflink.ht_cap.ht_supported) {
len += scnprintf(p + len, size - len,
"ht_cap: 0x%04x, ampdu: %02x, %02x\n",
- sta->ht_cap.cap,
- sta->ht_cap.ampdu_factor,
- sta->ht_cap.ampdu_density);
+ sta->deflink.ht_cap.cap,
+ sta->deflink.ht_cap.ampdu_factor,
+ sta->deflink.ht_cap.ampdu_density);
len += scnprintf(p + len, size - len,
"rx_mask: 0x%02x, %02x, %02x, %02x\n",
- sta->ht_cap.mcs.rx_mask[0],
- sta->ht_cap.mcs.rx_mask[1],
- sta->ht_cap.mcs.rx_mask[2],
- sta->ht_cap.mcs.rx_mask[3]);
+ sta->deflink.ht_cap.mcs.rx_mask[0],
+ sta->deflink.ht_cap.mcs.rx_mask[1],
+ sta->deflink.ht_cap.mcs.rx_mask[2],
+ sta->deflink.ht_cap.mcs.rx_mask[3]);
}
- if (sta->vht_cap.vht_supported) {
+ if (sta->deflink.vht_cap.vht_supported) {
len += scnprintf(p + len, size - len,
"vht_cap: 0x%08x, mcs: %02x, %02x\n",
- sta->vht_cap.cap,
- sta->vht_cap.vht_mcs.rx_mcs_map,
- sta->vht_cap.vht_mcs.tx_mcs_map);
+ sta->deflink.vht_cap.cap,
+ sta->deflink.vht_cap.vht_mcs.rx_mcs_map,
+ sta->deflink.vht_cap.vht_mcs.tx_mcs_map);
}
len += scnprintf(p + len, size - len, "rx_bw: %d, rx_nss: %d\n",
- sta->bandwidth, sta->rx_nss);
+ sta->deflink.bandwidth, sta->deflink.rx_nss);
len += scnprintf(p + len, size - len,
"tdls: %d, tdls_init: %d\n",
sta->tdls, sta->tdls_initiator);
@@ -596,18 +596,18 @@ static ssize_t mwl_debugfs_sta_read(stru
sta_info->wds ? "true" : "false",
sta_info->ba_hist.enable ? "enable" : "disable",
sta_info->is_amsdu_allowed ? sta_info->amsdu_ctrl.cap : 0 ,
- sta->ht_cap.ht_supported ? sta->ht_cap.cap : 0,
- sta->ht_cap.ht_supported ? sta->ht_cap.ampdu_factor : 0,
- sta->ht_cap.ht_supported ? sta->ht_cap.ampdu_density : 0,
- sta->ht_cap.ht_supported ? sta->ht_cap.mcs.rx_mask[0] : 0,
- sta->ht_cap.ht_supported ? sta->ht_cap.mcs.rx_mask[1] : 0,
- sta->ht_cap.ht_supported ? sta->ht_cap.mcs.rx_mask[2] : 0,
- sta->ht_cap.ht_supported ? sta->ht_cap.mcs.rx_mask[3] : 0,
- sta->vht_cap.vht_supported ? sta->vht_cap.cap : 0,
- sta->vht_cap.vht_supported ? sta->vht_cap.vht_mcs.rx_mcs_map : 0,
- sta->vht_cap.vht_supported ? sta->vht_cap.vht_mcs.tx_mcs_map : 0,
- sta->bandwidth,
- sta->rx_nss,
+ sta->deflink.ht_cap.ht_supported ? sta->deflink.ht_cap.cap : 0,
+ sta->deflink.ht_cap.ht_supported ? sta->deflink.ht_cap.ampdu_factor : 0,
+ sta->deflink.ht_cap.ht_supported ? sta->deflink.ht_cap.ampdu_density : 0,
+ sta->deflink.ht_cap.ht_supported ? sta->deflink.ht_cap.mcs.rx_mask[0] : 0,
+ sta->deflink.ht_cap.ht_supported ? sta->deflink.ht_cap.mcs.rx_mask[1] : 0,
+ sta->deflink.ht_cap.ht_supported ? sta->deflink.ht_cap.mcs.rx_mask[2] : 0,
+ sta->deflink.ht_cap.ht_supported ? sta->deflink.ht_cap.mcs.rx_mask[3] : 0,
+ sta->deflink.vht_cap.vht_supported ? sta->deflink.vht_cap.cap : 0,
+ sta->deflink.vht_cap.vht_supported ? sta->deflink.vht_cap.vht_mcs.rx_mcs_map : 0,
+ sta->deflink.vht_cap.vht_supported ? sta->deflink.vht_cap.vht_mcs.tx_mcs_map : 0,
+ sta->deflink.bandwidth,
+ sta->deflink.rx_nss,
sta->tdls,
sta->tdls_initiator,
sta->wme,
--- a/hif/fwcmd.c
+++ b/hif/fwcmd.c
@@ -634,8 +634,9 @@ einval:
@@ -633,11 +633,15 @@ einval:
}
static int mwl_fwcmd_set_ap_beacon(struct mwl_priv *priv,
struct mwl_vif *mwl_vif,
- struct mwl_vif *mwl_vif,
- struct ieee80211_bss_conf *bss_conf)
+ struct ieee80211_vif *vif)
{
+ struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
struct hostcmd_cmd_ap_beacon *pcmd;
struct ds_params *phy_ds_param_set;
+ struct mwl_vif *mwl_vif;
+ struct ieee80211_bss_conf *bss_conf;
+
+ mwl_vif = mwl_dev_get_vif(vif);
+ bss_conf = &vif->bss_conf;
@@ -664,7 +665,7 @@ static int mwl_fwcmd_set_ap_beacon(struc
/* wmm structure of start command is defined less one byte,
* due to following field country is not used, add byte one
@@ -664,7 +668,7 @@ static int mwl_fwcmd_set_ap_beacon(struc
pcmd->cmd_hdr.macid = mwl_vif->macid;
ether_addr_copy(pcmd->start_cmd.sta_mac_addr, mwl_vif->bssid);
@ -99,16 +95,16 @@
if (priv->chip_type == MWL8997)
ether_addr_copy(pcmd->start_cmd.bssid, mwl_vif->bssid);
pcmd->start_cmd.bss_type = 1;
@@ -2091,7 +2092,7 @@ int mwl_fwcmd_set_beacon(struct ieee8021
@@ -2090,7 +2094,7 @@ int mwl_fwcmd_set_beacon(struct ieee8021
if (mwl_fwcmd_set_wsc_ie(hw, b_inf->ie_wsc_len, b_inf->ie_wsc_ptr))
goto err;
- if (mwl_fwcmd_set_ap_beacon(priv, mwl_vif, &vif->bss_conf))
+ if (mwl_fwcmd_set_ap_beacon(priv, mwl_vif, vif))
+ if (mwl_fwcmd_set_ap_beacon(priv, vif))
goto err;
if (b_inf->cap_info & WLAN_CAPABILITY_SPECTRUM_MGMT)
@@ -2153,38 +2154,38 @@ int mwl_fwcmd_set_new_stn_add(struct iee
@@ -2152,38 +2156,38 @@ int mwl_fwcmd_set_new_stn_add(struct iee
ether_addr_copy(pcmd->mac_addr, sta->addr);
if (hw->conf.chandef.chan->band == NL80211_BAND_2GHZ)
@ -161,7 +157,7 @@
}
pcmd->is_qos_sta = sta->wme;
@@ -2240,38 +2241,38 @@ int mwl_fwcmd_set_new_stn_add_sc4(struct
@@ -2239,38 +2243,38 @@ int mwl_fwcmd_set_new_stn_add_sc4(struct
ether_addr_copy(pcmd->mac_addr, sta->addr);
if (hw->conf.chandef.chan->band == NL80211_BAND_2GHZ)
@ -214,7 +210,7 @@
}
pcmd->is_qos_sta = sta->wme;
@@ -2788,9 +2789,9 @@ int mwl_fwcmd_create_ba(struct ieee80211
@@ -2787,9 +2791,9 @@ int mwl_fwcmd_create_ba(struct ieee80211
pcmd->ba_info.create_params.flags = cpu_to_le32(ba_flags);
pcmd->ba_info.create_params.queue_id = stream->idx;
pcmd->ba_info.create_params.param_info =
@ -226,7 +222,7 @@
IEEE80211_HT_AMPDU_PARM_DENSITY);
if (direction == BA_FLAG_DIRECTION_UP) {
pcmd->ba_info.create_params.reset_seq_no = 0;
@@ -2800,9 +2801,9 @@ int mwl_fwcmd_create_ba(struct ieee80211
@@ -2799,9 +2803,9 @@ int mwl_fwcmd_create_ba(struct ieee80211
pcmd->ba_info.create_params.current_seq = cpu_to_le16(0);
}
if (priv->chip_type == MWL8964 &&
@ -238,9 +234,51 @@
IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK) >>
IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT);
}
--- a/hif/pcie/8864/tx.c
+++ b/hif/pcie/8864/tx.c
@@ -743,7 +743,7 @@ void pcie_8864_tx_xmit(struct ieee80211_
index = SYSADPT_TX_WMM_QUEUES - index - 1;
txpriority = index;
- if (sta && sta->ht_cap.ht_supported &&
+ if (sta && sta->deflink.ht_cap.ht_supported &&
!(xmitcontrol & EAGLE_TXD_XMITCTRL_USE_MC_RATE) &&
ieee80211_is_data_qos(wh->frame_control)) {
tid = qos & 0xf;
--- a/hif/pcie/8964/tx_ndp.c
+++ b/hif/pcie/8964/tx_ndp.c
@@ -607,7 +607,7 @@ void pcie_tx_xmit_ndp(struct ieee80211_h
pcie_tx_encapsulate_frame(priv, skb, k_conf);
} else {
tid = qos & 0x7;
- if (sta && sta->ht_cap.ht_supported && !eapol_frame &&
+ if (sta && sta->deflink.ht_cap.ht_supported && !eapol_frame &&
qos != 0xFFFF) {
pcie_tx_count_packet(sta, tid);
spin_lock_bh(&priv->stream_lock);
--- a/hif/pcie/8997/tx.c
+++ b/hif/pcie/8997/tx.c
@@ -81,7 +81,7 @@ static int pcie_txbd_ring_create(struct
wiphy_info(priv->hw->wiphy,
"TX ring: - base: %p, pbase: 0x%x, len: %d\n",
pcie_priv->txbd_ring_vbase,
- pcie_priv->txbd_ring_pbase,
+ (u32)pcie_priv->txbd_ring_pbase,
pcie_priv->txbd_ring_size);
for (num = 0; num < PCIE_MAX_TXRX_BD; num++) {
@@ -694,7 +694,7 @@ void pcie_8997_tx_xmit(struct ieee80211_
index = SYSADPT_TX_WMM_QUEUES - index - 1;
txpriority = index;
- if (sta && sta->ht_cap.ht_supported &&
+ if (sta && sta->deflink.ht_cap.ht_supported &&
!(xmitcontrol & EAGLE_TXD_XMITCTRL_USE_MC_RATE) &&
ieee80211_is_data_qos(wh->frame_control)) {
tid = qos & 0xf;
--- a/mac80211.c
+++ b/mac80211.c
@@ -371,15 +371,15 @@ static void mwl_mac80211_bss_info_change
@@ -368,15 +368,15 @@ static void mwl_mac80211_bss_info_change
}
}
@ -259,7 +297,7 @@
{
struct mwl_priv *priv = hw->priv;
struct mwl_vif *mwl_vif;
@@ -429,8 +429,8 @@ static void mwl_mac80211_bss_info_change
@@ -426,8 +426,8 @@ static void mwl_mac80211_bss_info_change
if (changed & (BSS_CHANGED_BEACON_INT | BSS_CHANGED_BEACON)) {
struct sk_buff *skb;
@ -270,7 +308,7 @@
(!info->hidden_ssid)) {
if (mwl_vif->broadcast_ssid != true) {
mwl_fwcmd_broadcast_ssid_enable(hw, vif, true);
@@ -444,7 +444,7 @@ static void mwl_mac80211_bss_info_change
@@ -441,7 +441,7 @@ static void mwl_mac80211_bss_info_change
}
if (!mwl_vif->set_beacon) {
@ -279,7 +317,7 @@
if (skb) {
mwl_fwcmd_set_beacon(hw, vif, skb->data, skb->len);
@@ -461,7 +461,7 @@ static void mwl_mac80211_bss_info_change
@@ -458,7 +458,7 @@ static void mwl_mac80211_bss_info_change
static void mwl_mac80211_bss_info_changed(struct ieee80211_hw *hw,
struct ieee80211_vif *vif,
struct ieee80211_bss_conf *info,
@ -288,7 +326,7 @@
{
switch (vif->type) {
case NL80211_IFTYPE_AP:
@@ -584,10 +584,10 @@ static int mwl_mac80211_sta_add(struct i
@@ -583,10 +583,10 @@ static int mwl_mac80211_sta_add(struct i
if (vif->type == NL80211_IFTYPE_MESH_POINT)
sta_info->is_mesh_node = true;
@ -296,12 +334,12 @@
+ if (sta->deflink.ht_cap.ht_supported) {
sta_info->is_ampdu_allowed = true;
sta_info->is_amsdu_allowed = false;
- if (sta->ht_cap.cap & IEEE80211_HT_CAP_MAX_AMSDU)
+ if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_MAX_AMSDU)
- if (sta->ht_cap.cap & IEEE80211_HT_CAP_MAX_AMSDU) {
+ if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_MAX_AMSDU) {
sta_info->amsdu_ctrl.cap = MWL_AMSDU_SIZE_8K;
else
sta_info->amsdu_ctrl.cap = MWL_AMSDU_SIZE_4K;
@@ -669,7 +669,7 @@ static int mwl_mac80211_sta_remove(struc
sta_info->amsdu_ctrl.amsdu_allow_size = SYSADPT_AMSDU_8K_MAX_SIZE;
}
@@ -670,7 +670,7 @@ static int mwl_mac80211_sta_remove(struc
static int mwl_mac80211_conf_tx(struct ieee80211_hw *hw,
struct ieee80211_vif *vif,
@ -310,7 +348,7 @@
const struct ieee80211_tx_queue_params *params)
{
struct mwl_priv *priv = hw->priv;
@@ -928,4 +928,5 @@ const struct ieee80211_ops mwl_mac80211_
@@ -934,4 +934,5 @@ const struct ieee80211_ops mwl_mac80211_
.pre_channel_switch = mwl_mac80211_chnl_switch,
.sw_scan_start = mwl_mac80211_sw_scan_start,
.sw_scan_complete = mwl_mac80211_sw_scan_complete,
@ -360,34 +398,3 @@
switch (format) {
case TX_RATE_FORMAT_LEGACY:
--- a/hif/pcie/tx.c
+++ b/hif/pcie/tx.c
@@ -153,7 +153,7 @@ static int pcie_txbd_ring_create(struct
wiphy_info(priv->hw->wiphy,
"TX ring: - base: %p, pbase: 0x%x, len: %d\n",
pcie_priv->txbd_ring_vbase,
- pcie_priv->txbd_ring_pbase,
+ (u32)pcie_priv->txbd_ring_pbase,
pcie_priv->txbd_ring_size);
for (num = 0; num < PCIE_MAX_TXRX_BD; num++) {
@@ -1091,7 +1091,7 @@ void pcie_tx_xmit(struct ieee80211_hw *h
index = SYSADPT_TX_WMM_QUEUES - index - 1;
txpriority = index;
- if (sta && sta->ht_cap.ht_supported && !eapol_frame &&
+ if (sta && sta->deflink.ht_cap.ht_supported && !eapol_frame &&
ieee80211_is_data_qos(wh->frame_control)) {
tid = qos & 0xf;
pcie_tx_count_packet(sta, tid);
--- a/hif/pcie/tx_ndp.c
+++ b/hif/pcie/tx_ndp.c
@@ -602,7 +602,7 @@ void pcie_tx_xmit_ndp(struct ieee80211_h
pcie_tx_encapsulate_frame(priv, skb, k_conf, NULL);
} else {
tid = qos & 0x7;
- if (sta && sta->ht_cap.ht_supported && !eapol_frame &&
+ if (sta && sta->deflink.ht_cap.ht_supported && !eapol_frame &&
qos != 0xFFFF) {
pcie_tx_count_packet(sta, tid);
spin_lock_bh(&priv->stream_lock);

8
package/kernel/mwlwifi/patches/006-remove-uaccess-and-get_fs-calls-from-PCIe-for-Kenel-.patch
View file

@ -19,11 +19,9 @@ Signed-off-by: Stefan Kalscheuer <stefan@stklcode.de>
hif/pcie/pcie.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hif/pcie/pcie.c b/hif/pcie/pcie.c
index 24453b6..bee1cc5 100644
--- a/hif/pcie/pcie.c
+++ b/hif/pcie/pcie.c
@@ -1294,7 +1294,9 @@ static void pcie_bf_mimo_ctrl_decode(struct mwl_priv *priv,
@@ -1439,7 +1439,9 @@ static void pcie_bf_mimo_ctrl_decode(str
const char filename[] = "/tmp/BF_MIMO_Ctrl_Field_Output.txt";
char str_buf[256];
char *buf = &str_buf[0];
@ -33,7 +31,7 @@ index 24453b6..bee1cc5 100644
#if LINUX_VERSION_CODE < KERNEL_VERSION(5,0,0)
oldfs = get_fs();
@@ -1302,7 +1304,7 @@ static void pcie_bf_mimo_ctrl_decode(struct mwl_priv *priv,
@@ -1447,7 +1449,7 @@ static void pcie_bf_mimo_ctrl_decode(str
#elif LINUX_VERSION_CODE < KERNEL_VERSION(5,10,0)
oldfs = get_fs();
set_fs(KERNEL_DS);
@ -42,7 +40,7 @@ index 24453b6..bee1cc5 100644
oldfs = force_uaccess_begin();
#endif
@@ -1326,7 +1328,7 @@ static void pcie_bf_mimo_ctrl_decode(struct mwl_priv *priv,
@@ -1471,7 +1473,7 @@ static void pcie_bf_mimo_ctrl_decode(str
#if LINUX_VERSION_CODE < KERNEL_VERSION(5,10,0)
set_fs(oldfs);

273
package/kernel/mwlwifi/patches/007-replace-usage-of-the-deprecated-pci-dma-compat.h-API.patch
View file

@ -24,11 +24,9 @@ Signed-off-by: Stefan Kalscheuer <stefan@stklcode.de>
hif/pcie/tx_ndp.c | 14 +++++++-------
5 files changed, 39 insertions(+), 39 deletions(-)
diff --git a/hif/pcie/pcie.c b/hif/pcie/pcie.c
index bee1cc5..d85c29e 100644
--- a/hif/pcie/pcie.c
+++ b/hif/pcie/pcie.c
@@ -1556,7 +1556,7 @@ static int pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
@@ -1701,7 +1701,7 @@ static int pcie_probe(struct pci_dev *pd
return rc;
}
@ -37,11 +35,9 @@ index bee1cc5..d85c29e 100644
if (rc) {
pr_err("%s: 32-bit PCI DMA not supported\n",
PCIE_DRV_NAME);
diff --git a/hif/pcie/rx.c b/hif/pcie/rx.c
index 91eb984..2857c0f 100644
--- a/hif/pcie/rx.c
+++ b/hif/pcie/rx.c
@@ -107,11 +107,11 @@ static int pcie_rx_ring_init(struct mwl_priv *priv)
--- a/hif/pcie/8864/rx.c
+++ b/hif/pcie/8864/rx.c
@@ -107,11 +107,11 @@ static int pcie_rx_ring_init(struct mwl_
desc->prx_ring[i].rssi = 0x00;
desc->prx_ring[i].pkt_len =
cpu_to_le16(SYSADPT_MAX_AGGR_SIZE);
@ -56,7 +52,7 @@ index 91eb984..2857c0f 100644
wiphy_err(priv->hw->wiphy,
"failed to map pci memory!\n");
return -ENOMEM;
@@ -153,11 +153,11 @@ static void pcie_rx_ring_cleanup(struct mwl_priv *priv)
@@ -153,11 +153,11 @@ static void pcie_rx_ring_cleanup(struct
if (!rx_hndl->psk_buff)
continue;
@ -70,12 +66,12 @@ index 91eb984..2857c0f 100644
dev_kfree_skb_any(rx_hndl->psk_buff);
@@ -335,11 +335,11 @@ static inline int pcie_rx_refill(struct mwl_priv *priv,
@@ -332,11 +332,11 @@ static inline int pcie_rx_refill(struct
rx_hndl->pdesc->rssi = 0x00;
rx_hndl->pdesc->pkt_len = cpu_to_le16(desc->rx_buf_size);
- dma = pci_map_single(pcie_priv->pdev,
+ dma = dma_map_single(&(pcie_priv->pdev)->dev,
+ dma = dma_map_single(&pcie_priv->pdev->dev,
rx_hndl->psk_buff->data,
desc->rx_buf_size,
- PCI_DMA_FROMDEVICE);
@ -85,7 +81,7 @@ index 91eb984..2857c0f 100644
dev_kfree_skb_any(rx_hndl->psk_buff);
wiphy_err(priv->hw->wiphy,
"failed to map pci memory!\n");
@@ -413,10 +413,10 @@ void pcie_rx_recv(unsigned long data)
@@ -410,10 +410,10 @@ void pcie_8864_rx_recv(unsigned long dat
prx_skb = curr_hndl->psk_buff;
if (!prx_skb)
goto out;
@ -98,11 +94,58 @@ index 91eb984..2857c0f 100644
pkt_len = le16_to_cpu(curr_hndl->pdesc->pkt_len);
if (skb_tailroom(prx_skb) < pkt_len) {
diff --git a/hif/pcie/rx_ndp.c b/hif/pcie/rx_ndp.c
index 228075d..106d559 100644
--- a/hif/pcie/rx_ndp.c
+++ b/hif/pcie/rx_ndp.c
@@ -86,11 +86,11 @@ static int pcie_rx_ring_init_ndp(struct mwl_priv *priv)
--- a/hif/pcie/8864/tx.c
+++ b/hif/pcie/8864/tx.c
@@ -171,11 +171,11 @@ static void pcie_tx_ring_cleanup(struct
desc->tx_hndl[i].psk_buff->data,
le32_to_cpu(
desc->ptx_ring[i].pkt_ptr));
- pci_unmap_single(pcie_priv->pdev,
+ dma_unmap_single(&(pcie_priv->pdev)->dev,
le32_to_cpu(
desc->ptx_ring[i].pkt_ptr),
desc->tx_hndl[i].psk_buff->len,
- PCI_DMA_TODEVICE);
+ DMA_TO_DEVICE);
dev_kfree_skb_any(desc->tx_hndl[i].psk_buff);
desc->ptx_ring[i].status =
cpu_to_le32(EAGLE_TXD_STATUS_IDLE);
@@ -291,9 +291,9 @@ static inline void pcie_tx_skb(struct mw
tx_desc->type = tx_ctrl->type;
tx_desc->xmit_control = tx_ctrl->xmit_control;
tx_desc->sap_pkt_info = 0;
- dma = pci_map_single(pcie_priv->pdev, tx_skb->data,
- tx_skb->len, PCI_DMA_TODEVICE);
- if (pci_dma_mapping_error(pcie_priv->pdev, dma)) {
+ dma = dma_map_single(&(pcie_priv->pdev)->dev, tx_skb->data,
+ tx_skb->len, DMA_TO_DEVICE);
+ if (dma_mapping_error(&(pcie_priv->pdev)->dev, dma)) {
dev_kfree_skb_any(tx_skb);
wiphy_err(priv->hw->wiphy,
"failed to map pci memory!\n");
@@ -447,10 +447,10 @@ static void pcie_non_pfu_tx_done(struct
(tx_desc->status & cpu_to_le32(EAGLE_TXD_STATUS_OK)) &&
(!(tx_desc->status &
cpu_to_le32(EAGLE_TXD_STATUS_FW_OWNED)))) {
- pci_unmap_single(pcie_priv->pdev,
+ dma_unmap_single(&(pcie_priv->pdev)->dev,
le32_to_cpu(tx_desc->pkt_ptr),
le16_to_cpu(tx_desc->pkt_len),
- PCI_DMA_TODEVICE);
+ DMA_TO_DEVICE);
done_skb = tx_hndl->psk_buff;
rate = le32_to_cpu(tx_desc->rate_info);
tx_desc->pkt_ptr = 0;
@@ -925,4 +925,4 @@ void pcie_8864_tx_del_sta_amsdu_pkts(str
}
}
spin_unlock_bh(&sta_info->amsdu_lock);
-}
\ No newline at end of file
+}
--- a/hif/pcie/8964/rx_ndp.c
+++ b/hif/pcie/8964/rx_ndp.c
@@ -86,11 +86,11 @@ static int pcie_rx_ring_init_ndp(struct
}
skb_reserve(psk_buff, MIN_BYTES_RX_HEADROOM);
@ -117,7 +160,7 @@ index 228075d..106d559 100644
wiphy_err(priv->hw->wiphy,
"failed to map pci memory!\n");
return -ENOMEM;
@@ -120,11 +120,11 @@ static void pcie_rx_ring_cleanup_ndp(struct mwl_priv *priv)
@@ -120,11 +120,11 @@ static void pcie_rx_ring_cleanup_ndp(str
if (desc->prx_ring) {
for (i = 0; i < MAX_NUM_RX_DESC; i++) {
if (desc->rx_vbuflist[i]) {
@ -131,7 +174,7 @@ index 228075d..106d559 100644
desc->rx_vbuflist[i] = NULL;
}
}
@@ -400,11 +400,11 @@ static inline int pcie_rx_refill_ndp(struct mwl_priv *priv, u32 buf_idx)
@@ -411,11 +411,11 @@ static inline int pcie_rx_refill_ndp(str
return -ENOMEM;
skb_reserve(psk_buff, MIN_BYTES_RX_HEADROOM);
@ -146,7 +189,7 @@ index 228075d..106d559 100644
wiphy_err(priv->hw->wiphy,
"refill: failed to map pci memory!\n");
return -ENOMEM;
@@ -509,10 +509,10 @@ recheck:
@@ -520,10 +520,10 @@ recheck:
break;
}
@ -159,81 +202,9 @@ index 228075d..106d559 100644
bad_mic = false;
ctrl = le32_to_cpu(prx_ring_done->ctrl);
diff --git a/hif/pcie/tx.c b/hif/pcie/tx.c
index 62a34a8..8f3c828 100644
--- a/hif/pcie/tx.c
+++ b/hif/pcie/tx.c
@@ -243,11 +243,11 @@ static void pcie_tx_ring_cleanup(struct mwl_priv *priv)
desc->tx_hndl[i].psk_buff->data,
le32_to_cpu(
desc->ptx_ring[i].pkt_ptr));
- pci_unmap_single(pcie_priv->pdev,
+ dma_unmap_single(&(pcie_priv->pdev)->dev,
le32_to_cpu(
desc->ptx_ring[i].pkt_ptr),
desc->tx_hndl[i].psk_buff->len,
- PCI_DMA_TODEVICE);
+ DMA_TO_DEVICE);
dev_kfree_skb_any(desc->tx_hndl[i].psk_buff);
desc->ptx_ring[i].status =
cpu_to_le32(EAGLE_TXD_STATUS_IDLE);
@@ -305,10 +305,10 @@ static void pcie_txbd_ring_delete(struct mwl_priv *priv)
skb = pcie_priv->tx_buf_list[num];
tx_desc = (struct pcie_tx_desc *)skb->data;
- pci_unmap_single(pcie_priv->pdev,
+ dma_unmap_single(&(pcie_priv->pdev)->dev,
le32_to_cpu(tx_desc->pkt_ptr),
skb->len,
- PCI_DMA_TODEVICE);
+ DMA_TO_DEVICE);
dev_kfree_skb_any(skb);
}
pcie_priv->tx_buf_list[num] = NULL;
@@ -453,9 +453,9 @@ static inline void pcie_tx_skb(struct mwl_priv *priv, int desc_num,
tx_desc->type = tx_ctrl->type;
tx_desc->xmit_control = tx_ctrl->xmit_control;
tx_desc->sap_pkt_info = 0;
- dma = pci_map_single(pcie_priv->pdev, tx_skb->data,
- tx_skb->len, PCI_DMA_TODEVICE);
- if (pci_dma_mapping_error(pcie_priv->pdev, dma)) {
+ dma = dma_map_single(&(pcie_priv->pdev)->dev, tx_skb->data,
+ tx_skb->len, DMA_TO_DEVICE);
+ if (dma_mapping_error(&(pcie_priv->pdev)->dev, dma)) {
dev_kfree_skb_any(tx_skb);
wiphy_err(priv->hw->wiphy,
"failed to map pci memory!\n");
@@ -676,10 +676,10 @@ static void pcie_pfu_tx_done(struct mwl_priv *priv)
pfu_dma = (struct pcie_pfu_dma_data *)done_skb->data;
tx_desc = &pfu_dma->tx_desc;
dma_data = &pfu_dma->dma_data;
- pci_unmap_single(pcie_priv->pdev,
+ dma_unmap_single(&(pcie_priv->pdev)->dev,
le32_to_cpu(data_buf->paddr),
le16_to_cpu(data_buf->len),
- PCI_DMA_TODEVICE);
+ DMA_TO_DEVICE);
tx_desc->pkt_ptr = 0;
tx_desc->pkt_len = 0;
tx_desc->status = cpu_to_le32(EAGLE_TXD_STATUS_IDLE);
@@ -768,10 +768,10 @@ static void pcie_non_pfu_tx_done(struct mwl_priv *priv)
(tx_desc->status & cpu_to_le32(EAGLE_TXD_STATUS_OK)) &&
(!(tx_desc->status &
cpu_to_le32(EAGLE_TXD_STATUS_FW_OWNED)))) {
- pci_unmap_single(pcie_priv->pdev,
+ dma_unmap_single(&(pcie_priv->pdev)->dev,
le32_to_cpu(tx_desc->pkt_ptr),
le16_to_cpu(tx_desc->pkt_len),
- PCI_DMA_TODEVICE);
+ DMA_TO_DEVICE);
done_skb = tx_hndl->psk_buff;
rate = le32_to_cpu(tx_desc->rate_info);
tx_desc->pkt_ptr = 0;
diff --git a/hif/pcie/tx_ndp.c b/hif/pcie/tx_ndp.c
index 6758cde..f4256c2 100644
--- a/hif/pcie/tx_ndp.c
+++ b/hif/pcie/tx_ndp.c
@@ -131,10 +131,10 @@ static void pcie_tx_ring_cleanup_ndp(struct mwl_priv *priv)
--- a/hif/pcie/8964/tx_ndp.c
+++ b/hif/pcie/8964/tx_ndp.c
@@ -132,10 +132,10 @@ static void pcie_tx_ring_cleanup_ndp(str
for (i = 0; i < MAX_TX_RING_SEND_SIZE; i++) {
tx_skb = desc->tx_vbuflist[i];
if (tx_skb) {
@ -246,7 +217,7 @@ index 6758cde..f4256c2 100644
dev_kfree_skb_any(tx_skb);
desc->pphys_tx_buflist[i] = 0;
desc->tx_vbuflist[i] = NULL;
@@ -266,9 +266,9 @@ static inline int pcie_tx_skb_ndp(struct mwl_priv *priv,
@@ -267,9 +267,9 @@ static inline int pcie_tx_skb_ndp(struct
(TXRING_CTRL_TAG_MGMT << TXRING_CTRL_TAG_SHIFT));
}
@ -259,7 +230,7 @@ index 6758cde..f4256c2 100644
dev_kfree_skb_any(tx_skb);
wiphy_err(priv->hw->wiphy,
"failed to map pci memory!\n");
@@ -450,10 +450,10 @@ void pcie_tx_done_ndp(struct ieee80211_hw *hw)
@@ -451,10 +451,10 @@ void pcie_tx_done_ndp(struct ieee80211_h
"buffer is NULL for tx done ring\n");
break;
}
@ -272,4 +243,110 @@ index 6758cde..f4256c2 100644
desc->pphys_tx_buflist[index] = 0;
desc->tx_vbuflist[index] = NULL;
--- a/hif/pcie/8997/rx.c
+++ b/hif/pcie/8997/rx.c
@@ -107,11 +107,11 @@ static int pcie_rx_ring_init(struct mwl_
desc->prx_ring[i].rssi = 0x00;
desc->prx_ring[i].pkt_len =
cpu_to_le16(SYSADPT_MAX_AGGR_SIZE);
- dma = pci_map_single(pcie_priv->pdev,
+ dma = dma_map_single(&(pcie_priv->pdev)->dev,
rx_hndl->psk_buff->data,
desc->rx_buf_size,
- PCI_DMA_FROMDEVICE);
- if (pci_dma_mapping_error(pcie_priv->pdev, dma)) {
+ DMA_FROM_DEVICE);
+ if (dma_mapping_error(&(pcie_priv->pdev)->dev, dma)) {
wiphy_err(priv->hw->wiphy,
"failed to map pci memory!\n");
return -ENOMEM;
@@ -153,11 +153,11 @@ static void pcie_rx_ring_cleanup(struct
if (!rx_hndl->psk_buff)
continue;
- pci_unmap_single(pcie_priv->pdev,
+ dma_unmap_single(&(pcie_priv->pdev)->dev,
le32_to_cpu
(rx_hndl->pdesc->pphys_buff_data),
desc->rx_buf_size,
- PCI_DMA_FROMDEVICE);
+ DMA_FROM_DEVICE);
dev_kfree_skb_any(rx_hndl->psk_buff);
@@ -332,11 +332,11 @@ static inline int pcie_rx_refill(struct
rx_hndl->pdesc->rssi = 0x00;
rx_hndl->pdesc->pkt_len = cpu_to_le16(desc->rx_buf_size);
- dma = pci_map_single(pcie_priv->pdev,
+ dma = dma_map_single(&pcie_priv->pdev->dev,
rx_hndl->psk_buff->data,
desc->rx_buf_size,
- PCI_DMA_FROMDEVICE);
- if (pci_dma_mapping_error(pcie_priv->pdev, dma)) {
+ DMA_FROM_DEVICE);
+ if (dma_mapping_error(&(pcie_priv->pdev)->dev, dma)) {
dev_kfree_skb_any(rx_hndl->psk_buff);
wiphy_err(priv->hw->wiphy,
"failed to map pci memory!\n");
@@ -410,10 +410,10 @@ void pcie_8997_rx_recv(unsigned long dat
prx_skb = curr_hndl->psk_buff;
if (!prx_skb)
goto out;
- pci_unmap_single(pcie_priv->pdev,
+ dma_unmap_single(&(pcie_priv->pdev)->dev,
le32_to_cpu(curr_hndl->pdesc->pphys_buff_data),
desc->rx_buf_size,
- PCI_DMA_FROMDEVICE);
+ DMA_FROM_DEVICE);
pkt_len = le16_to_cpu(curr_hndl->pdesc->pkt_len);
if (skb_tailroom(prx_skb) < pkt_len) {
--- a/hif/pcie/8997/tx.c
+++ b/hif/pcie/8997/tx.c
@@ -139,10 +139,10 @@ static void pcie_txbd_ring_delete(struct
skb = pcie_priv->tx_buf_list[num];
tx_desc = (struct pcie_tx_desc *)skb->data;
- pci_unmap_single(pcie_priv->pdev,
+ dma_unmap_single(&(pcie_priv->pdev)->dev,
le32_to_cpu(tx_desc->pkt_ptr),
skb->len,
- PCI_DMA_TODEVICE);
+ DMA_TO_DEVICE);
dev_kfree_skb_any(skb);
}
pcie_priv->tx_buf_list[num] = NULL;
@@ -222,9 +222,9 @@ static inline void pcie_tx_skb(struct mw
tx_desc->type = tx_ctrl->type;
tx_desc->xmit_control = tx_ctrl->xmit_control;
tx_desc->sap_pkt_info = 0;
- dma = pci_map_single(pcie_priv->pdev, tx_skb->data,
- tx_skb->len, PCI_DMA_TODEVICE);
- if (pci_dma_mapping_error(pcie_priv->pdev, dma)) {
+ dma = dma_map_single(&(pcie_priv->pdev)->dev, tx_skb->data,
+ tx_skb->len, DMA_TO_DEVICE);
+ if (dma_mapping_error(&(pcie_priv->pdev)->dev, dma)) {
dev_kfree_skb_any(tx_skb);
wiphy_err(priv->hw->wiphy,
"failed to map pci memory!\n");
@@ -401,10 +401,10 @@ static void pcie_pfu_tx_done(struct mwl_
pfu_dma = (struct pcie_pfu_dma_data *)done_skb->data;
tx_desc = &pfu_dma->tx_desc;
dma_data = &pfu_dma->dma_data;
- pci_unmap_single(pcie_priv->pdev,
+ dma_unmap_single(&(pcie_priv->pdev)->dev,
le32_to_cpu(data_buf->paddr),
le16_to_cpu(data_buf->len),
- PCI_DMA_TODEVICE);
+ DMA_TO_DEVICE);
tx_desc->pkt_ptr = 0;
tx_desc->pkt_len = 0;
tx_desc->status = cpu_to_le32(EAGLE_TXD_STATUS_IDLE);
@@ -875,4 +875,4 @@ void pcie_8997_tx_del_sta_amsdu_pkts(str
}
}
spin_unlock_bh(&sta_info->amsdu_lock);
-}
\ No newline at end of file
+}

6
package/libs/libubox/Makefile
View file

@ -5,9 +5,9 @@ PKG_RELEASE=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=$(PROJECT_GIT)/project/libubox.git
PKG_MIRROR_HASH:=f22de22a784a0135cc2869fe81ff30e52136dca36863ee713503b4be5be01869
PKG_SOURCE_DATE:=2023-05-23
PKG_SOURCE_VERSION:=75a3b870cace1171faf57bd55e5a9a2f1564f757
PKG_MIRROR_HASH:=e0881d8c61a953c2e0e721f3063e4a3d53de81fe74dee972074c839b5027a75f
PKG_SOURCE_DATE:=2023-11-27
PKG_SOURCE_VERSION:=d4c3066e7c5efa5f395c21db77609516d386cbf8
PKG_ABI_VERSION:=$(call abi_version_str,$(PKG_SOURCE_DATE))
CMAKE_INSTALL:=1

10
package/libs/udebug/Makefile
View file

@ -11,9 +11,9 @@ PKG_NAME:=udebug
CMAKE_INSTALL:=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=$(PROJECT_GIT)/project/udebug.git
PKG_MIRROR_HASH:=baf437fb12b1faaf6c7eea3fea253c6d87c31b85f768b48d3984fe398e5b20b8
PKG_SOURCE_DATE:=2023-11-20
PKG_SOURCE_VERSION:=759d9404034b7da97b3950c806ace7296a0f7a12
PKG_MIRROR_HASH:=c0d3701516dcbe0fe2badbeda50076e4f07ec054c4a80621c7aaf4e83ea75d0c
PKG_SOURCE_DATE:=2023-11-27
PKG_SOURCE_VERSION:=d4b99820afd03a726ea50687d4393007da0fd0df
PKG_ABI_VERSION:=$(call abi_version_str,$(PKG_SOURCE_DATE))
PKG_LICENSE:=GPL-2.0
@ -26,14 +26,14 @@ define Package/libudebug
SECTION:=libs
CATEGORY:=Libraries
TITLE:=udebug client library
DEPENDS:=+libubox
DEPENDS:=+libubox +libubus
endef
define Package/udebugd
SECTION:=utils
CATEGORY:=Utilities
TITLE:=OpenWrt debug service
DEPENDS:=+libudebug +libubus
DEPENDS:=+libudebug
endef
define Package/udebugd/conffiles

6
package/libs/ustream-ssl/Makefile
View file

@ -5,9 +5,9 @@ PKG_RELEASE:=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=$(PROJECT_GIT)/project/ustream-ssl.git
PKG_SOURCE_DATE:=2023-02-25
PKG_SOURCE_VERSION:=498f6e268d4d2b0ad33b430f4ba1abe397d31496
PKG_MIRROR_HASH:=a201d065dd613e30886c9f13a0851cec79538192cfe591b6f8ecd88724d55fb1
PKG_SOURCE_DATE:=2023-11-26
PKG_SOURCE_VERSION:=263b9a97cf7e1e2467319c23832b705fc01190b5
PKG_MIRROR_HASH:=1c01d633f21c6cb578a785826d1983284b28f49b20d608d82179842dcdbeed6e
CMAKE_INSTALL:=1
PKG_LICENSE:=ISC

2
package/network/services/dnsmasq/patches/200-ubus_dns.patch
View file

@ -210,7 +210,7 @@
+ return;
+
+ ubus_free(ubus);
+ ubus = NULL;
+ daemon->ubus = NULL;
+}
+
static int ubus_handle_metrics(struct ubus_context *ctx, struct ubus_object *obj,

10
package/utils/f2fs-tools/Makefile
View file

@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk
PKG_NAME:=f2fs-tools
PKG_VERSION:=1.16.0
PKG_RELEASE:=1
PKG_RELEASE:=2
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
PKG_SOURCE_URL:=https://git.kernel.org/pub/scm/linux/kernel/git/jaegeuk/f2fs-tools.git/snapshot/
@ -133,10 +133,10 @@ Package/mkf2fs-selinux/install = $(Package/mkf2fs/install)
define Package/f2fsck/install
$(INSTALL_DIR) $(1)/usr/sbin
$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/fsck.f2fs $(1)/usr/sbin
ln -s /usr/sbin/fsck.f2fs $(1)/usr/sbin/defrag.f2fs
ln -s /usr/sbin/fsck.f2fs $(1)/usr/sbin/dump.f2fs
ln -s /usr/sbin/fsck.f2fs $(1)/usr/sbin/sload.f2fs
ln -s /usr/sbin/fsck.f2fs $(1)/usr/sbin/resize.f2fs
$(LN) ../sbin/fsck.f2fs $(1)/usr/sbin/defrag.f2fs
$(LN) ../sbin/fsck.f2fs $(1)/usr/sbin/dump.f2fs
$(LN) ../sbin/fsck.f2fs $(1)/usr/sbin/sload.f2fs
$(LN) ../sbin/fsck.f2fs $(1)/usr/sbin/resize.f2fs
endef
Package/f2fsck-selinux/install = $(Package/f2fsck/install)

64
scripts/linksys-image.sh
View file

@ -1,64 +0,0 @@
#!/bin/sh
#
# Copyright (C) 2018 Oceanic Systems (UK) Ltd
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
# Maintained by: Ryan Pannell <ryan [at] o s u k l .com> <github.com/Escalion>
#
# Write Linksys signature for factory image
# This is appended to the factory image and is tested by the Linksys Upgrader - as observed in civic.
# The footer is 256 bytes. The format is:
# .LINKSYS. This is detected by the Linksys upgrader before continuing with upgrade. (9 bytes)
# <VERSION> The version number of upgrade. Not checked so use arbitrary value (8 bytes)
# <TYPE> Model of target device, padded (0x20) to (15 bytes)
# <CRC> CRC checksum of the image to flash (8 byte)
# <padding> Padding ('0' + 0x20 *7) (8 bytes)
# <signature> Signature of signer. Not checked so use arbitrary value (16 bytes)
# <padding> Padding (0x00) (192 bytes)
## version history
# * version 1: initial commit
set -e
ME="${0##*/}"
usage() {
echo "Usage: $ME <type> <in filename>"
[ "$IMG_OUT" ] && rm -f "$IMG_OUT"
exit 1
}
[ "$#" -lt 3 ] && usage
TYPE=$1
tmpdir="$( mktemp -d 2> /dev/null )"
if [ -z "$tmpdir" ]; then
# try OSX signature
tmpdir="$( mktemp -t 'ubitmp' -d )"
fi
if [ -z "$tmpdir" ]; then
exit 1
fi
trap "rm -rf $tmpdir" EXIT
IMG_TMP_OUT="${tmpdir}/out"
IMG_IN=$2
IMG_OUT="${IMG_IN}.new"
[ ! -f "$IMG_IN" ] && echo "$ME: Not a valid image: $IMG_IN" && usage
dd if="${IMG_IN}" of="${IMG_TMP_OUT}"
CRC=$(printf "%08X" $(dd if="${IMG_IN}" bs=$(stat -c%s "${IMG_IN}") count=1|cksum| cut -d ' ' -f1))
printf ".LINKSYS.01000409%-15s%-8s%-8s%-16s" "${TYPE}" "${CRC}" "0" "K0000000F0246434" >> "${IMG_TMP_OUT}"
dd if=/dev/zero bs=1 count=192 conv=notrunc >> "${IMG_TMP_OUT}"
cp "${IMG_TMP_OUT}" "${IMG_OUT}"

30
target/linux/apm821xx/dts/netgear-wndr4700.dts
View file

@ -267,23 +267,25 @@
reg = <0x07fc0000 0x00040000>;
read-only;
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_wifi_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_wifi_c: macaddr@c {
reg = <0xc 0x6>;
};
macaddr_wifi_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_wifi_c: macaddr@c {
reg = <0xc 0x6>;
};
calibration_wifi_1000: calibration@1000 {
reg = <0x1000 0x440>;
};
calibration_wifi_1000: calibration@1000 {
reg = <0x1000 0x440>;
};
calibration_wifi_5000: calibration@5000 {
reg = <0x5000 0x440>;
calibration_wifi_5000: calibration@5000 {
reg = <0x5000 0x440>;
};
};
};
};

1
target/linux/ath79/dts/ar7161_aruba_ap-105.dts
View file

@ -159,7 +159,6 @@
hwinfo: partition@fe0000 {
reg = <0xfe0000 0x10000>;
compatible = "nvmem-cells";
label = "hwinfo";
read-only;

30
target/linux/ath79/dts/ar7161_aruba_ap-175.dts
View file

@ -122,9 +122,8 @@
ath9k0: wifi@0,11 {
compatible = "pci168c,0029";
nvmem-cells = <&macaddr_hwinfo_1c>;
nvmem-cells = <&macaddr_hwinfo_1c 1>;
nvmem-cell-names = "mac-address";
mac-address-increment = <1>;
reg = <0x8800 0 0 0 0>;
#gpio-cells = <2>;
gpio-controller;
@ -132,9 +131,8 @@
ath9k1: wifi@0,12 {
compatible = "pci168c,0029";
nvmem-cells = <&macaddr_hwinfo_1c>;
nvmem-cells = <&macaddr_hwinfo_1c 2>;
nvmem-cell-names = "mac-address";
mac-address-increment = <2>;
reg = <0x9000 0 0 0 0>;
#gpio-cells = <2>;
gpio-controller;
@ -151,7 +149,7 @@
&eth0 {
status = "okay";
nvmem-cells = <&macaddr_hwinfo_1c>;
nvmem-cells = <&macaddr_hwinfo_1c 0>;
nvmem-cell-names = "mac-address";
phy-mode = "rgmii";
@ -187,6 +185,18 @@
label = "hwinfo";
reg = <0xfe0000 0x10000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_hwinfo_1c: macaddr@1c {
compatible = "mac-base";
reg = <0x1c 0x6>;
#nvmem-cell-cells = <1>;
};
};
};
partition@ff0000 {
@ -198,16 +208,6 @@
};
};
&hwinfo {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_hwinfo_1c: macaddr@1c {
reg = <0x1c 0x6>;
};
};
&i2c0 {
gpio_ext: gpio@21 {
status = "okay";

33
target/linux/ath79/dts/ar7161_buffalo_wzr-hp-ag300h.dtsi
View file

@ -148,6 +148,22 @@
label = "art";
reg = <0x0050000 0x0010000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_120c: macaddr@120c {
reg = <0x120c 0x6>;
};
macaddr_art_520c: macaddr@520c {
compatible = "mac-base";
reg = <0x520c 0x6>;
#nvmem-cell-cells = <1>;
};
};
};
partition@60000 {
@ -240,23 +256,8 @@
&eth1 {
status = "okay";
nvmem-cells = <&macaddr_art_520c>;
nvmem-cells = <&macaddr_art_520c 1>;
nvmem-cell-names = "mac-address";
mac-address-increment = <1>;
phy-handle = <&phy4>;
};
&art {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_120c: macaddr@120c {
reg = <0x120c 0x6>;
};
macaddr_art_520c: macaddr@520c {
reg = <0x520c 0x6>;
};
};

1
target/linux/ath79/dts/ar7161_dlink_dir-825-b1.dts
View file

@ -186,7 +186,6 @@
};
partition@660000 {
compatible = "nvmem-cells";
label = "caldata";
reg = <0x660000 0x010000>;
read-only;

45
target/linux/ath79/dts/ar7161_fortinet_fap-220-b.dts
View file

@ -99,9 +99,8 @@
compatible = "pci168c,0029";
reg = <0x8800 0 0 0 0>;
ieee80211-freq-limit = <2402000 2482000>;
nvmem-cells = <&macaddr_art_120c>, <&cal_art_1000>;
nvmem-cells = <&macaddr_uboot_3ff80 9>, <&cal_art_1000>;
nvmem-cell-names = "mac-address", "calibration";
mac-address-increment = <1>;
#gpio-cells = <2>;
gpio-controller;
};
@ -110,9 +109,8 @@
compatible = "pci168c,0029";
reg = <0x9000 0 0 0 0>;
ieee80211-freq-limit = <2402000 2482000 4900000 5990000>;
nvmem-cells = <&macaddr_art_520c>, <&cal_art_5000>;
nvmem-cells = <&macaddr_uboot_3ff80 2>, <&cal_art_5000>;
nvmem-cell-names = "mac-address", "calibration";
mac-address-increment = <9>;
#gpio-cells = <2>;
gpio-controller;
};
@ -133,7 +131,7 @@
&eth1 {
status = "okay";
nvmem-cells = <&macaddr_art_120c>;
nvmem-cells = <&macaddr_uboot_3ff80 0>;
nvmem-cell-names = "mac-address";
pll-data = <0x00110000 0x00001099 0x00991099>;
@ -149,35 +147,18 @@
status = "okay";
};
&uboot {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
/* Currently doesn't work, because this one lacks colons as delimiters */
macaddr_uboot_3ff80: mac-address-ascii@3ff80 {
reg = <0x3ff80 0xc>;
};
};
&art {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
cal_art_1000: calibration@1000 {
reg = <0x1000 0xeb8>;
};
cal_art_1000: calibration@1000 {
reg = <0x1000 0xeb8>;
};
macaddr_art_120c: mac-address@120c {
reg = <0x120c 0x6>;
};
cal_art_5000: calibration@5000 {
reg = <0x5000 0xeb8>;
};
macaddr_art_520c: mac-address@520c {
reg = <0x520c 0x6>;
cal_art_5000: calibration@5000 {
reg = <0x5000 0xeb8>;
};
};
};

19
target/linux/ath79/dts/ar7161_jjplus_ja76pf2.dts
View file

@ -158,16 +158,19 @@
label = "Atheros Board Data";
reg = <0xff0000 0x10000>;
read-only;
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_wan: macaddr@1000 {
reg = <0x1000 0x6>;
};
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_lan: macaddr@1006 {
reg = <0x1006 0x6>;
macaddr_wan: macaddr@1000 {
reg = <0x1000 0x6>;
};
macaddr_lan: macaddr@1006 {
reg = <0x1006 0x6>;
};
};
};
};

30
target/linux/ath79/dts/ar7161_meraki_mr16.dts
View file

@ -74,9 +74,8 @@
compatible = "pci168c,0029";
reg = <0x8800 0 0 0 0>;
qca,no-eeprom;
nvmem-cells = <&macaddr_config_66>;
nvmem-cells = <&macaddr_config_66 1>;
nvmem-cell-names = "mac-address";
mac-address-increment = <1>;
#gpio-cells = <2>;
gpio-controller;
};
@ -85,9 +84,8 @@
compatible = "pci168c,0029";
reg = <0x9000 0 0 0 0>;
qca,no-eeprom;
nvmem-cells = <&macaddr_config_66>;
nvmem-cells = <&macaddr_config_66 2>;
nvmem-cell-names = "mac-address";
mac-address-increment = <2>;
#gpio-cells = <2>;
gpio-controller;
};
@ -103,7 +101,7 @@
&eth0 {
status = "okay";
nvmem-cells = <&macaddr_config_66>;
nvmem-cells = <&macaddr_config_66 0>;
nvmem-cell-names = "mac-address";
pll-data = <0x00110000 0x00001099 0x00991099>;
@ -141,6 +139,18 @@
label = "config";
reg = <0x80000 0x20000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_config_66: macaddr@66 {
compatible = "mac-base";
reg = <0x66 0x6>;
#nvmem-cell-cells = <1>;
};
};
};
partition@a0000 {
@ -157,13 +167,3 @@
};
};
};
&config {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_config_66: macaddr@66 {
reg = <0x66 0x6>;
};
};

41
target/linux/ath79/dts/ar7161_netgear_wndap360.dts
View file

@ -112,28 +112,32 @@
reg = <0x7f0000 0x010000>;
read-only;
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_120c: macaddr@120c {
reg = <0x120c 0x6>;
};
macaddr_art_120c: macaddr@120c {
reg = <0x120c 0x6>;
};
macaddr_art_520c: macaddr@520c {
reg = <0x520c 0x6>;
};
macaddr_art_520c: macaddr@520c {
compatible = "mac-base";
reg = <0x520c 0x6>;
#nvmem-cell-cells = <1>;
};
calibration_art_1000: calibration@1000 {
reg = <0x1000 0xeb8>;
};
calibration_art_1000: calibration@1000 {
reg = <0x1000 0xeb8>;
};
calibration_art_5000: calibration@5000 {
reg = <0x5000 0xeb8>;
calibration_art_5000: calibration@5000 {
reg = <0x5000 0xeb8>;
};
};
};
};
@ -155,9 +159,8 @@
ath9k1: wifi@0,12 {
compatible = "pci168c,0029";
reg = <0x9000 0 0 0 0>;
nvmem-cells = <&macaddr_art_520c>, <&calibration_art_5000>;
nvmem-cells = <&macaddr_art_520c 1>, <&calibration_art_5000>;
nvmem-cell-names = "mac-address", "calibration";
mac-address-increment = <1>;
#gpio-cells = <2>;
gpio-controller;
};

52
target/linux/ath79/dts/ar7161_netgear_wndr3700-v2.dts
View file

@ -35,6 +35,32 @@
label = "art";
reg = <0xff0000 0x010000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
macaddr_art_c: macaddr@c {
reg = <0xc 0x6>;
};
cal_art_1000: cal@1000 {
reg = <0x1000 0xeb8>;
};
cal_art_5000: cal@5000 {
reg = <0x5000 0xeb8>;
};
};
};
};
@ -57,29 +83,3 @@
nvmem-cells = <&macaddr_art_6>;
nvmem-cell-names = "mac-address";
};
&art {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
macaddr_art_c: macaddr@c {
reg = <0xc 0x6>;
};
cal_art_1000: cal@1000 {
reg = <0x1000 0xeb8>;
};
cal_art_5000: cal@5000 {
reg = <0x5000 0xeb8>;
};
};

52
target/linux/ath79/dts/ar7161_netgear_wndr3700.dts
View file

@ -35,6 +35,32 @@
label = "art";
reg = <0x7f0000 0x010000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
macaddr_art_c: macaddr@c {
reg = <0xc 0x6>;
};
cal_art_1000: cal@1000 {
reg = <0x1000 0xeb8>;
};
cal_art_5000: cal@5000 {
reg = <0x5000 0xeb8>;
};
};
};
};
@ -76,29 +102,3 @@
nvmem-cells = <&macaddr_art_6>;
nvmem-cell-names = "mac-address";
};
&art {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
macaddr_art_c: macaddr@c {
reg = <0xc 0x6>;
};
cal_art_1000: cal@1000 {
reg = <0x1000 0xeb8>;
};
cal_art_5000: cal@5000 {
reg = <0x5000 0xeb8>;
};
};

52
target/linux/ath79/dts/ar7161_netgear_wndr3800.dts
View file

@ -36,6 +36,32 @@
label = "art";
reg = <0xff0000 0x010000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
macaddr_art_c: macaddr@c {
reg = <0xc 0x6>;
};
cal_art_1000: cal@1000 {
reg = <0x1000 0xeb8>;
};
cal_art_5000: cal@5000 {
reg = <0x5000 0xeb8>;
};
};
};
};
@ -58,29 +84,3 @@
nvmem-cells = <&macaddr_art_6>;
nvmem-cell-names = "mac-address";
};
&art {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
macaddr_art_c: macaddr@c {
reg = <0xc 0x6>;
};
cal_art_1000: cal@1000 {
reg = <0x1000 0xeb8>;
};
cal_art_5000: cal@5000 {
reg = <0x5000 0xeb8>;
};
};

52
target/linux/ath79/dts/ar7161_netgear_wndr3800ch.dts
View file

@ -36,6 +36,32 @@
label = "art";
reg = <0xff0000 0x010000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
macaddr_art_c: macaddr@c {
reg = <0xc 0x6>;
};
cal_art_1000: cal@1000 {
reg = <0x1000 0xeb8>;
};
cal_art_5000: cal@5000 {
reg = <0x5000 0xeb8>;
};
};
};
};
@ -58,29 +84,3 @@
nvmem-cells = <&macaddr_art_6>;
nvmem-cell-names = "mac-address";
};
&art {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
macaddr_art_c: macaddr@c {
reg = <0xc 0x6>;
};
cal_art_1000: cal@1000 {
reg = <0x1000 0xeb8>;
};
cal_art_5000: cal@5000 {
reg = <0x5000 0xeb8>;
};
};

52
target/linux/ath79/dts/ar7161_netgear_wndrmac-v1.dts
View file

@ -35,6 +35,32 @@
label = "art";
reg = <0xff0000 0x010000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
macaddr_art_c: macaddr@c {
reg = <0xc 0x6>;
};
cal_art_1000: cal@1000 {
reg = <0x1000 0xeb8>;
};
cal_art_5000: cal@5000 {
reg = <0x5000 0xeb8>;
};
};
};
};
@ -57,29 +83,3 @@
nvmem-cells = <&macaddr_art_6>;
nvmem-cell-names = "mac-address";
};
&art {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
macaddr_art_c: macaddr@c {
reg = <0xc 0x6>;
};
cal_art_1000: cal@1000 {
reg = <0x1000 0xeb8>;
};
cal_art_5000: cal@5000 {
reg = <0x5000 0xeb8>;
};
};

52
target/linux/ath79/dts/ar7161_netgear_wndrmac-v2.dts
View file

@ -36,6 +36,32 @@
label = "art";
reg = <0xff0000 0x010000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
macaddr_art_c: macaddr@c {
reg = <0xc 0x6>;
};
cal_art_1000: cal@1000 {
reg = <0x1000 0xeb8>;
};
cal_art_5000: cal@5000 {
reg = <0x5000 0xeb8>;
};
};
};
};
@ -58,29 +84,3 @@
nvmem-cells = <&macaddr_art_6>;
nvmem-cell-names = "mac-address";
};
&art {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
macaddr_art_c: macaddr@c {
reg = <0xc 0x6>;
};
cal_art_1000: cal@1000 {
reg = <0x1000 0xeb8>;
};
cal_art_5000: cal@5000 {
reg = <0x5000 0xeb8>;
};
};

18
target/linux/ath79/dts/ar7161_ruckus_gd11.dtsi
View file

@ -223,21 +223,3 @@
&usb_phy {
status = "okay";
};
&board_data {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_bdata_60: macaddr@60 {
reg = <0x60 0x6>;
};
macaddr_bdata_66: macaddr@66 {
reg = <0x66 0x6>;
};
macaddr_bdata_76: macaddr@76 {
reg = <0x76 0x6>;
};
};

20
target/linux/ath79/dts/ar7161_ruckus_zf7341.dts
View file

@ -6,3 +6,23 @@
model = "Ruckus ZoneFlex 7341[-U]";
compatible = "ruckus,zf7341", "qca,ar7161";
};
&board_data {
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_bdata_60: macaddr@60 {
reg = <0x60 0x6>;
};
macaddr_bdata_66: macaddr@66 {
reg = <0x66 0x6>;
};
macaddr_bdata_76: macaddr@76 {
reg = <0x76 0x6>;
};
};
};

20
target/linux/ath79/dts/ar7161_ruckus_zf7351.dts
View file

@ -113,3 +113,23 @@
gpio-hog;
};
};
&board_data {
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_bdata_60: macaddr@60 {
reg = <0x60 0x6>;
};
macaddr_bdata_66: macaddr@66 {
reg = <0x66 0x6>;
};
macaddr_bdata_76: macaddr@76 {
reg = <0x76 0x6>;
};
};
};

22
target/linux/ath79/dts/ar7161_ruckus_zf7363.dts
View file

@ -33,7 +33,25 @@
};
&board_data {
macaddr_bdata_6c: macaddr@6c {
reg = <0x6c 0x6>;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_bdata_60: macaddr@60 {
reg = <0x60 0x6>;
};
macaddr_bdata_66: macaddr@66 {
reg = <0x66 0x6>;
};
macaddr_bdata_6c: macaddr@6c {
reg = <0x6c 0x6>;
};
macaddr_bdata_76: macaddr@76 {
reg = <0x76 0x6>;
};
};
};

29
target/linux/ath79/dts/ar7240_buffalo_whr-g301n.dts
View file

@ -147,22 +147,33 @@
reg = <0x3f0000 0x10000>;
label = "art";
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_120c: macaddr@120c {
compatible = "mac-base";
reg = <0x120c 0x6>;
#nvmem-cell-cells = <1>;
};
};
};
};
};
};
&eth0 {
nvmem-cells = <&macaddr_art_120c>;
nvmem-cells = <&macaddr_art_120c 0>;
nvmem-cell-names = "mac-address";
};
&eth1 {
status = "okay";
nvmem-cells = <&macaddr_art_120c>;
nvmem-cells = <&macaddr_art_120c 1>;
nvmem-cell-names = "mac-address";
mac-address-increment = <1>;
};
&pcie {
@ -172,7 +183,7 @@
compatible = "pci168c,002a";
reg = <0x0000 0 0 0 0>;
qca,no-eeprom;
nvmem-cells = <&macaddr_art_120c>;
nvmem-cells = <&macaddr_art_120c 0>;
nvmem-cell-names = "mac-address";
#gpio-cells = <2>;
gpio-controller;
@ -184,13 +195,3 @@
pinctrl-single,bits = <0x0 0x0 0xf8>;
};
};
&art {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_120c: macaddr@120c {
reg = <0x120c 0x6>;
};
};

12
target/linux/ath79/dts/ar7240_engenius_enh202-v1.dts
View file

@ -96,11 +96,13 @@
};
&art {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
};
};

35
target/linux/ath79/dts/ar7240_netgear_wnr1000-v2.dts
View file

@ -168,13 +168,29 @@
label = "art";
reg = <0x3f0000 0x10000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
compatible = "mac-base";
reg = <0x0 0x6>;
#nvmem-cell-cells = <1>;
};
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
};
};
};
};
};
&eth0 {
nvmem-cells = <&macaddr_art_0>;
nvmem-cells = <&macaddr_art_0 0>;
nvmem-cell-names = "mac-address";
};
@ -191,25 +207,10 @@
ath9k: wifi@0,0 {
compatible = "pci168c,002b";
reg = <0x0000 0 0 0 0>;
nvmem-cells = <&macaddr_art_0>;
nvmem-cells = <&macaddr_art_0 1>;
nvmem-cell-names = "mac-address";
mac-address-increment = <1>;
qca,no-eeprom;
#gpio-cells = <2>;
gpio-controller;
};
};
&art {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
};

35
target/linux/ath79/dts/ar7240_netgear_wnr612-v2.dtsi
View file

@ -101,13 +101,29 @@
reg = <0x3f0000 0x10000>;
label = "art";
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
compatible = "mac-base";
reg = <0x0 0x6>;
#nvmem-cell-cells = <1>;
};
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
};
};
};
};
};
&eth0 {
nvmem-cells = <&macaddr_art_0>;
nvmem-cells = <&macaddr_art_0 0>;
nvmem-cell-names = "mac-address";
};
@ -124,25 +140,10 @@
ath9k: wifi@0,0 {
compatible = "pci168c,002b";
reg = <0x0000 0 0 0 0>;
nvmem-cells = <&macaddr_art_0>;
nvmem-cells = <&macaddr_art_0 1>;
nvmem-cell-names = "mac-address";
mac-address-increment = <1>;
qca,no-eeprom;
#gpio-cells = <2>;
gpio-controller;
};
};
&art {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
};

24
target/linux/ath79/dts/ar7240_openmesh_om2p-v1.dts
View file

@ -127,20 +127,22 @@
reg = <0xfc0000 0x040000>;
read-only;
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
calibration_art_1000: calibration@1000 {
reg = <0x1000 0x440>;
calibration_art_1000: calibration@1000 {
reg = <0x1000 0x440>;
};
};
};
};

36
target/linux/ath79/dts/ar7240_ruckus_zf7025.dts
View file

@ -150,6 +150,24 @@
reg = <0xfc0000 0x40000>;
label = "board-data";
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_board_data_60: macaddr@60 {
reg = <0x60 0x6>;
};
macaddr_board_data_66: macaddr@66 {
reg = <0x66 0x6>;
};
macaddr_board_data_6c: macaddr@6c {
reg = <0x6c 0x6>;
};
};
};
};
};
@ -176,21 +194,3 @@
nvmem-cell-names = "mac-address";
};
};
&board_data {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_board_data_60: macaddr@60 {
reg = <0x60 0x6>;
};
macaddr_board_data_66: macaddr@66 {
reg = <0x66 0x6>;
};
macaddr_board_data_6c: macaddr@6c {
reg = <0x6c 0x6>;
};
};

24
target/linux/ath79/dts/ar7240_tplink.dtsi
View file

@ -77,6 +77,18 @@
reg = <0x0 0x20000>;
label = "u-boot";
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_uboot_1fc00: macaddr@1fc00 {
compatible = "mac-base";
reg = <0x1fc00 0x6>;
#nvmem-cell-cells = <1>;
};
};
};
partition@20000 {
@ -104,7 +116,7 @@
ath9k: wifi@0,0 {
reg = <0x0000 0 0 0 0>;
qca,no-eeprom;
nvmem-cells = <&macaddr_uboot_1fc00>;
nvmem-cells = <&macaddr_uboot_1fc00 0>;
nvmem-cell-names = "mac-address";
#gpio-cells = <2>;
gpio-controller;
@ -116,13 +128,3 @@
pinctrl-single,bits = <0x0 0x0 0xf8>;
};
};
&uboot {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_uboot_1fc00: macaddr@1fc00 {
reg = <0x1fc00 0x6>;
};
};

6
target/linux/ath79/dts/ar7240_tplink_tl-wr.dtsi
View file

@ -30,15 +30,13 @@
};
&eth0 {
nvmem-cells = <&macaddr_uboot_1fc00>;
nvmem-cells = <&macaddr_uboot_1fc00 (-1)>;
nvmem-cell-names = "mac-address";
mac-address-increment = <(-1)>;
};
&eth1 {
nvmem-cells = <&macaddr_uboot_1fc00>;
nvmem-cells = <&macaddr_uboot_1fc00 1>;
nvmem-cell-names = "mac-address";
mac-address-increment = <1>;
};
&ath9k {

35
target/linux/ath79/dts/ar7241_netgear_wnr2000-v3.dts
View file

@ -171,6 +171,22 @@
label = "art";
reg = <0x3f0000 0x10000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
compatible = "mac-base";
reg = <0x0 0x6>;
#nvmem-cell-cells = <1>;
};
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
};
};
};
};
@ -179,7 +195,7 @@
&eth0 {
status = "okay";
nvmem-cells = <&macaddr_art_0>;
nvmem-cells = <&macaddr_art_0 0>;
nvmem-cell-names = "mac-address";
};
@ -196,25 +212,10 @@
ath9k: wifi@0,0 {
compatible = "pci168c,002e";
reg = <0x0000 0 0 0 0>;
nvmem-cells = <&macaddr_art_0>;
nvmem-cells = <&macaddr_art_0 1>;
nvmem-cell-names = "mac-address";
mac-address-increment = <1>;
qca,no-eeprom;
#gpio-cells = <2>;
gpio-controller;
};
};
&art {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
};

35
target/linux/ath79/dts/ar7241_netgear_wnr2200-16m.dts
View file

@ -35,11 +35,27 @@
label = "art";
reg = <0xff0000 0x10000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
compatible = "mac-base";
reg = <0x0 0x6>;
#nvmem-cell-cells = <1>;
};
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
};
};
};
&eth0 {
nvmem-cells = <&macaddr_art_0>;
nvmem-cells = <&macaddr_art_0 0>;
nvmem-cell-names = "mac-address";
};
@ -49,21 +65,6 @@
};
&ath9k {
nvmem-cells = <&macaddr_art_0>;
nvmem-cells = <&macaddr_art_0 1>;
nvmem-cell-names = "mac-address";
mac-address-increment = <1>;
};
&art {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
};

35
target/linux/ath79/dts/ar7241_netgear_wnr2200-8m.dts
View file

@ -35,11 +35,27 @@
label = "art";
reg = <0x7f0000 0x10000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
compatible = "mac-base";
reg = <0x0 0x6>;
#nvmem-cell-cells = <1>;
};
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
};
};
};
&eth0 {
nvmem-cells = <&macaddr_art_0>;
nvmem-cells = <&macaddr_art_0 0>;
nvmem-cell-names = "mac-address";
};
@ -49,21 +65,6 @@
};
&ath9k {
nvmem-cells = <&macaddr_art_0>;
nvmem-cells = <&macaddr_art_0 1>;
nvmem-cell-names = "mac-address";
mac-address-increment = <1>;
};
&art {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
};

29
target/linux/ath79/dts/ar7241_tplink.dtsi
View file

@ -64,6 +64,18 @@
reg = <0x0 0x20000>;
label = "u-boot";
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_uboot_1fc00: macaddr@1fc00 {
compatible = "mac-base";
reg = <0x1fc00 0x6>;
#nvmem-cell-cells = <1>;
};
};
};
partition@20000 {
@ -89,7 +101,7 @@
#gpio-cells = <2>;
gpio-controller;
qca,no-eeprom;
nvmem-cells = <&macaddr_uboot_1fc00>;
nvmem-cells = <&macaddr_uboot_1fc00 0>;
nvmem-cell-names = "mac-address";
};
};
@ -97,22 +109,11 @@
&eth0 { /* WAN interface, initialized last as eth1 */
status = "okay";
nvmem-cells = <&macaddr_uboot_1fc00>;
nvmem-cells = <&macaddr_uboot_1fc00 1>;
nvmem-cell-names = "mac-address";
mac-address-increment = <1>;
};
&eth1 { /* LAN interface, initialized first as eth0 */
nvmem-cells = <&macaddr_uboot_1fc00>;
nvmem-cells = <&macaddr_uboot_1fc00 0>;
nvmem-cell-names = "mac-address";
};
&uboot {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_uboot_1fc00: macaddr@1fc00 {
reg = <0x1fc00 0x6>;
};
};

30
target/linux/ath79/dts/ar7241_tplink_tl-wr842n-v1.dts
View file

@ -102,6 +102,18 @@
reg = <0x0 0x20000>;
label = "u-boot";
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_uboot_1fc00: macaddr@1fc00 {
compatible = "mac-base";
reg = <0x1fc00 0x6>;
#nvmem-cell-cells = <1>;
};
};
};
partition@20000 {
@ -128,7 +140,7 @@
#gpio-cells = <2>;
gpio-controller;
qca,no-eeprom;
nvmem-cells = <&macaddr_uboot_1fc00>;
nvmem-cells = <&macaddr_uboot_1fc00 0>;
nvmem-cell-names = "mac-address";
};
};
@ -136,23 +148,11 @@
&eth0 {
status = "okay";
nvmem-cells = <&macaddr_uboot_1fc00>;
nvmem-cells = <&macaddr_uboot_1fc00 (-1)>;
nvmem-cell-names = "mac-address";
mac-address-increment = <(-1)>;
};
&eth1 {
nvmem-cells = <&macaddr_uboot_1fc00>;
nvmem-cells = <&macaddr_uboot_1fc00 1>;
nvmem-cell-names = "mac-address";
mac-address-increment = <1>;
};
&uboot {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_uboot_1fc00: macaddr@1fc00 {
reg = <0x1fc00 0x6>;
};
};

24
target/linux/ath79/dts/ar7241_ubnt_unifi-ap-outdoor-plus.dts
View file

@ -87,20 +87,22 @@
reg = <0xff0000 0x10000>;
read-only;
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
calibration_art_1000: calibration@1000 {
reg = <0x1000 0xeb8>;
calibration_art_1000: calibration@1000 {
reg = <0x1000 0xeb8>;
};
};
};
};

18
target/linux/ath79/dts/ar7241_ubnt_unifi-ap.dtsi
View file

@ -73,16 +73,18 @@
reg = <0x7f0000 0x010000>;
read-only;
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
calibration_art_1000: calibration@1000 {
reg = <0x1000 0x440>;
calibration_art_1000: calibration@1000 {
reg = <0x1000 0x440>;
};
};
};
};

12
target/linux/ath79/dts/ar7242_buffalo_bhr-4grv.dts
View file

@ -20,11 +20,13 @@
};
&art {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
};
};

18
target/linux/ath79/dts/ar7242_buffalo_wzr-hp-g302h-a1a0.dts
View file

@ -138,16 +138,18 @@
label = "art";
read-only;
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_120c: macaddr@120c {
reg = <0x120c 0x6>;
};
macaddr_art_120c: macaddr@120c {
reg = <0x120c 0x6>;
};
calibration_art_1000: calibration@1000 {
reg = <0x1000 0xeb8>;
calibration_art_1000: calibration@1000 {
reg = <0x1000 0xeb8>;
};
};
};

12
target/linux/ath79/dts/ar7242_buffalo_wzr-hp-g450h.dts
View file

@ -83,11 +83,13 @@
};
&art {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_1002: macaddr@1002 {
reg = <0x1002 0x6>;
macaddr_art_1002: macaddr@1002 {
reg = <0x1002 0x6>;
};
};
};

19
target/linux/ath79/dts/ar7242_engenius_eap350-v1.dts
View file

@ -63,7 +63,7 @@
&eth0 {
status = "okay";
nvmem-cells = <&macaddr_art_0>;
nvmem-cells = <&macaddr_art_0 0>;
nvmem-cell-names = "mac-address";
phy-handle = <&phy4>;
@ -78,9 +78,8 @@
ath9k: wifi@0,0,0 {
compatible = "pci168c,002a";
reg = <0x0 0 0 0 0>;
nvmem-cells = <&macaddr_art_0>;
nvmem-cells = <&macaddr_art_0 1>;
nvmem-cell-names = "mac-address";
mac-address-increment = <1>;
qca,no-eeprom;
#gpio-cells = <2>;
gpio-controller;
@ -88,11 +87,15 @@
};
&art {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
macaddr_art_0: macaddr@0 {
compatible = "mac-base";
reg = <0x0 0x6>;
#nvmem-cell-cells = <1>;
};
};
};

19
target/linux/ath79/dts/ar7242_engenius_ecb350-v1.dts
View file

@ -63,7 +63,7 @@
&eth0 {
status = "okay";
nvmem-cells = <&macaddr_art_0>;
nvmem-cells = <&macaddr_art_0 0>;
nvmem-cell-names = "mac-address";
phy-handle = <&phy4>;
@ -78,9 +78,8 @@
ath9k: wifi@0,0,0 {
compatible = "pci168c,002a";
reg = <0x0 0 0 0 0>;
nvmem-cells = <&macaddr_art_0>;
nvmem-cells = <&macaddr_art_0 (-1)>;
nvmem-cell-names = "mac-address";
mac-address-increment = <(-1)>;
qca,no-eeprom;
#gpio-cells = <2>;
gpio-controller;
@ -88,11 +87,15 @@
};
&art {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
macaddr_art_0: macaddr@0 {
compatible = "mac-base";
reg = <0x0 0x6>;
#nvmem-cell-cells = <1>;
};
};
};

29
target/linux/ath79/dts/ar7242_meraki_mr12.dts
View file

@ -74,9 +74,8 @@
compatible = "pci168c,002a";
reg = <0x0000 0 0 0 0>;
qca,no-eeprom;
nvmem-cells = <&macaddr_config_66>;
nvmem-cells = <&macaddr_config_66 1>;
nvmem-cell-names = "mac-address";
mac-address-increment = <1>;
};
};
@ -91,7 +90,7 @@
&eth0 {
status = "okay";
nvmem-cells = <&macaddr_config_66>;
nvmem-cells = <&macaddr_config_66 0>;
nvmem-cell-names = "mac-address";
pll-data = <0x02000000 0x00000101 0x00001313>;
@ -107,7 +106,7 @@
&eth1 {
status = "okay";
nvmem-cells = <&macaddr_config_66>;
nvmem-cells = <&macaddr_config_66 0>;
nvmem-cell-names = "mac-address";
};
@ -140,6 +139,18 @@
label = "config";
reg = <0x80000 0x20000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_config_66: macaddr@66 {
compatible = "mac-base";
reg = <0x66 0x6>;
#nvmem-cell-cells = <1>;
};
};
};
partition@a0000 {
@ -156,13 +167,3 @@
};
};
};
&config {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_config_66: macaddr@66 {
reg = <0x66 0x6>;
};
};

40
target/linux/ath79/dts/ar7242_tplink_tl-wr2543-v1.dts
View file

@ -107,6 +107,16 @@
label = "u-boot";
reg = <0x000000 0x020000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_uboot_1fc00: macaddr@1fc00 {
reg = <0x1fc00 0x6>;
};
};
};
partition@20000 {
@ -119,6 +129,16 @@
label = "art";
reg = <0x7f0000 0x010000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
cal_art_1000: cal@1000 {
reg = <0x1000 0x440>;
};
};
};
};
};
@ -157,23 +177,3 @@
full-duplex;
};
};
&uboot {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_uboot_1fc00: macaddr@1fc00 {
reg = <0x1fc00 0x6>;
};
};
&art {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
cal_art_1000: cal@1000 {
reg = <0x1000 0x440>;
};
};

10
target/linux/ath79/dts/ar7242_ubnt_edgeswitch-5xp.dts
View file

@ -75,13 +75,3 @@
full-duplex;
};
};
&art {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
};

10
target/linux/ath79/dts/ar7242_ubnt_edgeswitch-8xp.dts
View file

@ -186,13 +186,3 @@
full-duplex;
};
};
&art {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
};

24
target/linux/ath79/dts/ar7242_ubnt_sw.dtsi
View file

@ -104,6 +104,20 @@
reg = <0x7f0000 0x010000>;
label = "art";
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
};
};
};
};
@ -127,13 +141,3 @@
nvmem-cells = <&macaddr_art_6>;
nvmem-cell-names = "mac-address";
};
&art {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
};

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