qualcommax: remove PCIe bridge nodes

PCIe bridge nodes are now present in the SoC DTSI, so drop our downstream
ones as otherwise ath1*k BDF matching will fail.

Link: https://github.com/openwrt/openwrt/pull/18789
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Robert Marko 2025-05-12 20:11:22 +02:00
parent 5e0bbd3670
commit 487fc2ec96
11 changed files with 12 additions and 87 deletions

View file

@ -307,12 +307,7 @@
perst-gpios = <&tlmm 15 GPIO_ACTIVE_LOW>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
pcie@0 {
wifi@1,0 {
status = "okay";

View file

@ -154,12 +154,7 @@
perst-gpios = <&tlmm 15 GPIO_ACTIVE_LOW>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
pcie@0 {
wifi@1,0 {
status = "okay";

View file

@ -165,12 +165,7 @@
perst-gpios = <&tlmm 15 GPIO_ACTIVE_LOW>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
pcie@0 {
wifi@1,0 {
status = "okay";

View file

@ -155,12 +155,7 @@
status = "okay";
perst-gpio = <&tlmm 60 GPIO_ACTIVE_LOW>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
pcie@0 {
wifi@1,0 {
status = "okay";

View file

@ -521,12 +521,8 @@
&pcie0 {
status = "okay";
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
pcie@0 {
wifi@1,0 {
status = "okay";
/* ath11k has no DT compatible for PCI cards */

View file

@ -50,12 +50,7 @@
perst-gpio = <&tlmm 52 GPIO_ACTIVE_HIGH>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
pcie@0 {
wifi0: wifi@1,0 {
status = "okay";

View file

@ -535,12 +535,7 @@
perst-gpio = <&tlmm 58 GPIO_ACTIVE_LOW>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
pcie@0 {
wifi@1,0 {
status = "okay";
@ -562,12 +557,7 @@
perst-gpio = <&tlmm 62 GPIO_ACTIVE_HIGH>;
bridge@1,0 {
reg = <0x00010000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
pcie@0 {
wifi@1,0 {
status = "okay";

View file

@ -281,13 +281,6 @@
status = "okay";
perst-gpio = <&tlmm 58 GPIO_ACTIVE_LOW>;
bridge@0,0 {
reg = <0x00020000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
&pcie_qmp1 {
@ -299,12 +292,7 @@
perst-gpio = <&tlmm 61 GPIO_ACTIVE_LOW>;
bridge@1,0 {
reg = <0x00010000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
pcie@0 {
wifi@1,0 {
status = "okay";

View file

@ -522,12 +522,7 @@
perst-gpio = <&tlmm 58 GPIO_ACTIVE_LOW>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
pcie@0 {
wifi0: wifi@1,0 {
status = "okay";

View file

@ -498,12 +498,7 @@
perst-gpio = <&tlmm 61 GPIO_ACTIVE_LOW>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
pcie@0 {
wifi@1,0 {
status = "okay";

View file

@ -451,13 +451,6 @@
status = "okay";
perst-gpio = <&tlmm 58 GPIO_ACTIVE_LOW>;
bridge@0,0 {
reg = <0x00020000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
&pcie_qmp1 {
@ -468,13 +461,6 @@
status = "okay";
perst-gpio = <&tlmm 62 GPIO_ACTIVE_HIGH>;
bridge@1,0 {
reg = <0x00010000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
&wifi {