From bf06a7c865531cf20735cbdfac46d4947fcc18a6 Mon Sep 17 00:00:00 2001 From: Jan-Niklas Burfeind Date: Tue, 20 Dec 2022 16:43:23 +0100 Subject: [PATCH 01/72] uboot-sunxi: use UUID of bootdev and bootpart Several sunxi devices come with multiple mmc devices. On such devices, the mmc device order is unpredictable, so using /dev/mmcblk0p2 as root device doesn't always work, which results in unbootable devices. For the Banana Pi BPI-R3 in the mediatek target, this has been solved by defining aliases for the mmc devices in the DTS. Ideally we would do the same here, but for sunxi-a64 we already use UUID probing, so let's start with that (5f2ff607e286 ("uboot-sunxi: a64: allow booting directly from eMMC")). Since we're building and including u-boot in each supported device image, and this method has been proven to work fine for a64, let's just change the default u-boot env file to do the same. Fixes: #10080 Fixes: e6d9f6fdff ("sunxi: add support for FriendlyARM NanoPi R1") Co-authored-by: Karl Palsson Signed-off-by: Jan-Niklas Burfeind [use UUID in default u-boot env, rewrite commit message] Signed-off-by: Stijn Tintel --- package/boot/uboot-sunxi/uEnv-default.txt | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/package/boot/uboot-sunxi/uEnv-default.txt b/package/boot/uboot-sunxi/uEnv-default.txt index e024954516c..36e41c59b12 100644 --- a/package/boot/uboot-sunxi/uEnv-default.txt +++ b/package/boot/uboot-sunxi/uEnv-default.txt @@ -1,6 +1,8 @@ setenv fdt_high ffffffff -setenv loadkernel fatload mmc 0 \$kernel_addr_r uImage -setenv loaddtb fatload mmc 0 \$fdt_addr_r dtb -setenv bootargs console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rootwait +setenv mmc_rootpart 2 +part uuid mmc ${mmc_bootdev}:${mmc_rootpart} uuid +setenv loadkernel fatload mmc \$mmc_bootdev \$kernel_addr_r uImage +setenv loaddtb fatload mmc \$mmc_bootdev \$fdt_addr_r dtb +setenv bootargs console=ttyS0,115200 earlyprintk root=PARTUUID=${uuid} rootwait setenv uenvcmd run loadkernel \&\& run loaddtb \&\& bootm \$kernel_addr_r - \$fdt_addr_r run uenvcmd From 274dfcb19e0aabff3f0437c71f7743d677b938c4 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Thu, 22 Dec 2022 16:19:28 +0100 Subject: [PATCH 02/72] mt76: update to the latest version a03ef0aab93e wifi: mt76: mt7921: fix deadlock in mt7921_abort_roc 5b509e80384a wifi: mt76: dma: fix a regression in adding rx buffers Signed-off-by: Felix Fietkau --- package/kernel/mt76/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/kernel/mt76/Makefile b/package/kernel/mt76/Makefile index c71c7c52ded..d6f53a1d509 100644 --- a/package/kernel/mt76/Makefile +++ b/package/kernel/mt76/Makefile @@ -8,9 +8,9 @@ PKG_LICENSE_FILES:= PKG_SOURCE_URL:=https://github.com/openwrt/mt76 PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2022-12-09 -PKG_SOURCE_VERSION:=7fae1de12ae7832a6095fd2df198f41fabd5223d -PKG_MIRROR_HASH:=c2bf2f23265d5e181c275a62a64f487b190f19b43fc4c584b62b9e6c16e992ef +PKG_SOURCE_DATE:=2022-12-22 +PKG_SOURCE_VERSION:=5b509e80384ab019ac11aa90c81ec0dbb5b0d7f2 +PKG_MIRROR_HASH:=6fc25df4d28becd010ff4971b23731c08b53e69381a9e4c868091899712f78a9 PKG_MAINTAINER:=Felix Fietkau PKG_USE_NINJA:=0 From 259c014555d689e0d2e54e7b82ddd3e00e11fd3a Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Fri, 23 Dec 2022 00:14:03 +0100 Subject: [PATCH 03/72] kernel: Move CONFIG_DRM_XEN_FRONTEND to generic configuration The CONFIG_DRM_XEN_FRONTEND configuration symbol is also used by the layerscape target, move it to the generic kernel configuration. Signed-off-by: Hauke Mehrtens --- target/linux/generic/config-5.15 | 1 + target/linux/x86/64/config-5.15 | 1 - target/linux/x86/generic/config-5.15 | 1 - 3 files changed, 1 insertion(+), 2 deletions(-) diff --git a/target/linux/generic/config-5.15 b/target/linux/generic/config-5.15 index c3f8f9e9b8d..df8c942b62f 100644 --- a/target/linux/generic/config-5.15 +++ b/target/linux/generic/config-5.15 @@ -1666,6 +1666,7 @@ CONFIG_DQL=y # CONFIG_DRM_VKMS is not set # CONFIG_DRM_VMWGFX is not set # CONFIG_DRM_XEN is not set +# CONFIG_DRM_XEN_FRONTEND is not set # CONFIG_DS1682 is not set # CONFIG_DS1803 is not set # CONFIG_DS4424 is not set diff --git a/target/linux/x86/64/config-5.15 b/target/linux/x86/64/config-5.15 index 46c6f55f8d1..a20891ea55f 100644 --- a/target/linux/x86/64/config-5.15 +++ b/target/linux/x86/64/config-5.15 @@ -150,7 +150,6 @@ CONFIG_DRM_TTM=y CONFIG_DRM_TTM_HELPER=y CONFIG_DRM_VIRTIO_GPU=y CONFIG_DRM_VRAM_HELPER=y -# CONFIG_DRM_XEN_FRONTEND is not set CONFIG_EFI=y CONFIG_EFIVAR_FS=m # CONFIG_EFI_BOOTLOADER_CONTROL is not set diff --git a/target/linux/x86/generic/config-5.15 b/target/linux/x86/generic/config-5.15 index f573732eb31..1da6ad555da 100644 --- a/target/linux/x86/generic/config-5.15 +++ b/target/linux/x86/generic/config-5.15 @@ -106,7 +106,6 @@ CONFIG_DRM_TTM=y CONFIG_DRM_TTM_HELPER=y CONFIG_DRM_VIRTIO_GPU=y CONFIG_DRM_VRAM_HELPER=y -# CONFIG_DRM_XEN_FRONTEND is not set CONFIG_EFI=y CONFIG_EFIVAR_FS=m # CONFIG_EFI_BOOTLOADER_CONTROL is not set From 92eb787d08be3fc8cfdf314f99a5b1dd91b439b2 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Fri, 23 Dec 2022 00:28:51 +0100 Subject: [PATCH 04/72] kernel: Move CONFIG_PWM_IMG and CONFIG_PWM_MEDIATEK to generic configuration In the build of the ramips/mt76x8 target the user gets asked about these two configuration options, add them to the generic kernel configuration. Signed-off-by: Hauke Mehrtens --- target/linux/generic/config-5.10 | 2 ++ target/linux/generic/config-5.15 | 2 ++ target/linux/ramips/mt76x8/config-5.10 | 1 - 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/target/linux/generic/config-5.10 b/target/linux/generic/config-5.10 index 44fe4511a43..a2dc9b90b1f 100644 --- a/target/linux/generic/config-5.10 +++ b/target/linux/generic/config-5.10 @@ -4641,7 +4641,9 @@ CONFIG_PROC_SYSCTL=y # CONFIG_PWM is not set # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_IMG is not set # CONFIG_PWM_JZ4740 is not set +# CONFIG_PWM_MEDIATEK is not set # CONFIG_PWM_PCA9685 is not set CONFIG_PWRSEQ_EMMC=y # CONFIG_PWRSEQ_SD8787 is not set diff --git a/target/linux/generic/config-5.15 b/target/linux/generic/config-5.15 index df8c942b62f..df9755b19e6 100644 --- a/target/linux/generic/config-5.15 +++ b/target/linux/generic/config-5.15 @@ -4861,7 +4861,9 @@ CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_DWC is not set # CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_IMG is not set # CONFIG_PWM_JZ4740 is not set +# CONFIG_PWM_MEDIATEK is not set # CONFIG_PWM_PCA9685 is not set # CONFIG_PWM_RASPBERRYPI_POE is not set CONFIG_PWRSEQ_EMMC=y diff --git a/target/linux/ramips/mt76x8/config-5.10 b/target/linux/ramips/mt76x8/config-5.10 index 36922354a94..b6687f8949c 100644 --- a/target/linux/ramips/mt76x8/config-5.10 +++ b/target/linux/ramips/mt76x8/config-5.10 @@ -149,7 +149,6 @@ CONFIG_PINCTRL=y # CONFIG_PINCTRL_AW9523 is not set CONFIG_PINCTRL_RT2880=y # CONFIG_PINCTRL_SINGLE is not set -# CONFIG_PWM_MEDIATEK is not set CONFIG_RALINK=y # CONFIG_RALINK_WDT is not set CONFIG_REGMAP=y From 376eb2d9240520e793d8f62996693152d136b465 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Fri, 23 Dec 2022 00:33:44 +0100 Subject: [PATCH 05/72] ramips: Fix drivers/pwm/pwm-mediatek-ramips.c compile The pwmchip_remove() function returns void now. Fix a compile problem in the drivers/pwm/pwm-mediatek-ramips.c driver. Signed-off-by: Hauke Mehrtens --- .../ramips/patches-5.15/845-pwm-add-mediatek-support.patch | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/linux/ramips/patches-5.15/845-pwm-add-mediatek-support.patch b/target/linux/ramips/patches-5.15/845-pwm-add-mediatek-support.patch index 7792b7d63cf..06074d60310 100644 --- a/target/linux/ramips/patches-5.15/845-pwm-add-mediatek-support.patch +++ b/target/linux/ramips/patches-5.15/845-pwm-add-mediatek-support.patch @@ -41,7 +41,7 @@ Signed-off-by: John Crispin obj-$(CONFIG_PWM_NTXEC) += pwm-ntxec.o --- /dev/null +++ b/drivers/pwm/pwm-mediatek-ramips.c -@@ -0,0 +1,173 @@ +@@ -0,0 +1,175 @@ +/* + * Mediatek Pulse Width Modulator driver + * @@ -190,7 +190,9 @@ Signed-off-by: John Crispin + for (i = 0; i < NUM_PWM; i++) + pwm_disable(&pc->chip.pwms[i]); + -+ return pwmchip_remove(&pc->chip); ++ pwmchip_remove(&pc->chip); ++ ++ return 0; +} + +static const struct of_device_id mtk_pwm_of_match[] = { From 13d6048e0600273af1fa4fca7b29d4f5b4852000 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Mon, 19 Dec 2022 16:44:29 +0100 Subject: [PATCH 06/72] ath25: add generic subtarget Same game as for 853e4dd3062df7cb5704b15d6af6730e3194b571. Add generic to the filenames. Signed-off-by: Christian Marangi --- target/linux/ath25/Makefile | 1 + target/linux/ath25/generic/target.mk | 1 + 2 files changed, 2 insertions(+) create mode 100644 target/linux/ath25/generic/target.mk diff --git a/target/linux/ath25/Makefile b/target/linux/ath25/Makefile index ebbc9141d9f..4675962e6f1 100644 --- a/target/linux/ath25/Makefile +++ b/target/linux/ath25/Makefile @@ -8,6 +8,7 @@ ARCH:=mips BOARD:=ath25 BOARDNAME:=Atheros AR231x/AR5312 FEATURES:=squashfs low_mem small_flash +SUBTARGETS:=generic KERNEL_PATCHVER:=5.10 KERNEL_TESTING_PATCHVER:=5.10 diff --git a/target/linux/ath25/generic/target.mk b/target/linux/ath25/generic/target.mk new file mode 100644 index 00000000000..f5cb1fb19b9 --- /dev/null +++ b/target/linux/ath25/generic/target.mk @@ -0,0 +1 @@ +BOARDNAME:=Generic From cf49c7d5225364d11b3e10f0c94c55e90afa9c62 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Mon, 19 Dec 2022 16:45:11 +0100 Subject: [PATCH 07/72] gemini: add generic subtarget Same game as for 853e4dd3062df7cb5704b15d6af6730e3194b571. Add generic to the filenames. Signed-off-by: Christian Marangi --- target/linux/gemini/Makefile | 1 + target/linux/gemini/generic/target.mk | 1 + 2 files changed, 2 insertions(+) create mode 100644 target/linux/gemini/generic/target.mk diff --git a/target/linux/gemini/Makefile b/target/linux/gemini/Makefile index d5c9bbad13d..4266db16cd3 100644 --- a/target/linux/gemini/Makefile +++ b/target/linux/gemini/Makefile @@ -9,6 +9,7 @@ BOARD:=gemini BOARDNAME:=Cortina Systems CS351x FEATURES:=squashfs pci rtc usb dt gpio display ext4 rootfs-part boot-part CPU_TYPE:=fa526 +SUBTARGETS:=generic KERNEL_PATCHVER:=5.15 diff --git a/target/linux/gemini/generic/target.mk b/target/linux/gemini/generic/target.mk new file mode 100644 index 00000000000..f5cb1fb19b9 --- /dev/null +++ b/target/linux/gemini/generic/target.mk @@ -0,0 +1 @@ +BOARDNAME:=Generic From cada395a5075e30ec28ee95a2255801de13f2cc4 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Mon, 19 Dec 2022 16:45:39 +0100 Subject: [PATCH 08/72] kirkwood: add generic subtarget Same game as for 853e4dd3062df7cb5704b15d6af6730e3194b571. Add generic to the filenames. Signed-off-by: Christian Marangi --- target/linux/kirkwood/Makefile | 1 + target/linux/kirkwood/generic/target.mk | 1 + 2 files changed, 2 insertions(+) create mode 100644 target/linux/kirkwood/generic/target.mk diff --git a/target/linux/kirkwood/Makefile b/target/linux/kirkwood/Makefile index c7a25451c9c..4827d90ee2d 100644 --- a/target/linux/kirkwood/Makefile +++ b/target/linux/kirkwood/Makefile @@ -9,6 +9,7 @@ BOARD:=kirkwood BOARDNAME:=Marvell Kirkwood FEATURES:=usb nand squashfs ramdisk CPU_TYPE:=xscale +SUBTARGETS:=generic KERNEL_PATCHVER:=5.10 KERNEL_TESTING_PATCHVER:=5.15 diff --git a/target/linux/kirkwood/generic/target.mk b/target/linux/kirkwood/generic/target.mk new file mode 100644 index 00000000000..f5cb1fb19b9 --- /dev/null +++ b/target/linux/kirkwood/generic/target.mk @@ -0,0 +1 @@ +BOARDNAME:=Generic From 64ef920bb742fbb7a09ca6a588eb6da1aab9bf60 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Mon, 19 Dec 2022 16:46:10 +0100 Subject: [PATCH 09/72] mxs: add generic subtarget Same game as for 853e4dd3062df7cb5704b15d6af6730e3194b571. Add generic to the filenames. Signed-off-by: Christian Marangi --- target/linux/mxs/Makefile | 1 + target/linux/mxs/generic/target.mk | 1 + 2 files changed, 2 insertions(+) create mode 100644 target/linux/mxs/generic/target.mk diff --git a/target/linux/mxs/Makefile b/target/linux/mxs/Makefile index 7b6c6ee3f15..998983090ec 100644 --- a/target/linux/mxs/Makefile +++ b/target/linux/mxs/Makefile @@ -9,6 +9,7 @@ BOARD:=mxs BOARDNAME:=Freescale i.MX23/i.MX28 FEATURES:=ext4 rtc usb gpio CPU_TYPE:=arm926ej-s +SUBTARGETS:=generic KERNEL_PATCHVER:=5.10 KERNEL_TESTING_PATCHVER:=5.15 diff --git a/target/linux/mxs/generic/target.mk b/target/linux/mxs/generic/target.mk new file mode 100644 index 00000000000..f5cb1fb19b9 --- /dev/null +++ b/target/linux/mxs/generic/target.mk @@ -0,0 +1 @@ +BOARDNAME:=Generic From 6d7129ef044d4ee8c26943bb4aa68ecbb59034c9 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Mon, 19 Dec 2022 16:46:24 +0100 Subject: [PATCH 10/72] zynq: add generic subtarget Same game as for 853e4dd3062df7cb5704b15d6af6730e3194b571. Add generic to the filenames. Signed-off-by: Christian Marangi --- target/linux/zynq/Makefile | 1 + target/linux/zynq/generic/target.mk | 1 + 2 files changed, 2 insertions(+) create mode 100644 target/linux/zynq/generic/target.mk diff --git a/target/linux/zynq/Makefile b/target/linux/zynq/Makefile index 83807913e41..770cbf99dd0 100644 --- a/target/linux/zynq/Makefile +++ b/target/linux/zynq/Makefile @@ -10,6 +10,7 @@ BOARDNAME:=Xilinx Zynq 7000 SoCs FEATURES:=fpu gpio rtc usb usbgadget boot-part rootfs-part squashfs CPU_TYPE:=cortex-a9 CPU_SUBTYPE:=neon +SUBTARGETS:=generic # future support SUBTARGETS: for both zynq and zynqmp diff --git a/target/linux/zynq/generic/target.mk b/target/linux/zynq/generic/target.mk new file mode 100644 index 00000000000..f5cb1fb19b9 --- /dev/null +++ b/target/linux/zynq/generic/target.mk @@ -0,0 +1 @@ +BOARDNAME:=Generic From c028e1b1a0ad1e2105f3d13e7dd25a72e8d405fd Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Mon, 19 Dec 2022 16:46:44 +0100 Subject: [PATCH 11/72] tegra: add generic subtarget Same game as for 853e4dd3062df7cb5704b15d6af6730e3194b571. Add generic to the filenames. Signed-off-by: Christian Marangi --- target/linux/tegra/Makefile | 1 + target/linux/tegra/generic/target.mk | 1 + 2 files changed, 2 insertions(+) create mode 100644 target/linux/tegra/generic/target.mk diff --git a/target/linux/tegra/Makefile b/target/linux/tegra/Makefile index 51019607f25..81db1ac5fc6 100644 --- a/target/linux/tegra/Makefile +++ b/target/linux/tegra/Makefile @@ -10,6 +10,7 @@ BOARDNAME := NVIDIA Tegra FEATURES := audio boot-part display ext4 fpu gpio pci pcie rootfs-part rtc squashfs usb CPU_TYPE := cortex-a9 CPU_SUBTYPE := vfpv3-d16 +SUBTARGETS := generic KERNEL_PATCHVER := 5.10 KERNEL_TESTING_PATCHVER := 5.15 diff --git a/target/linux/tegra/generic/target.mk b/target/linux/tegra/generic/target.mk new file mode 100644 index 00000000000..f5cb1fb19b9 --- /dev/null +++ b/target/linux/tegra/generic/target.mk @@ -0,0 +1 @@ +BOARDNAME:=Generic From 8e2e67d117c6c957443b42b08a010e6c0defae42 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Mon, 19 Dec 2022 16:46:56 +0100 Subject: [PATCH 12/72] octeontx: add generic subtarget Same game as for 853e4dd3062df7cb5704b15d6af6730e3194b571. Add generic to the filenames. Signed-off-by: Christian Marangi --- target/linux/octeontx/Makefile | 1 + target/linux/octeontx/generic/target.mk | 1 + 2 files changed, 2 insertions(+) create mode 100644 target/linux/octeontx/generic/target.mk diff --git a/target/linux/octeontx/Makefile b/target/linux/octeontx/Makefile index eb90529740e..68a8259b76e 100644 --- a/target/linux/octeontx/Makefile +++ b/target/linux/octeontx/Makefile @@ -8,6 +8,7 @@ ARCH:=aarch64 BOARD:=octeontx BOARDNAME:=Octeon-TX FEATURES:=targz pcie gpio rtc usb fpu +SUBTARGETS:=generic KERNEL_PATCHVER:=5.10 diff --git a/target/linux/octeontx/generic/target.mk b/target/linux/octeontx/generic/target.mk new file mode 100644 index 00000000000..f5cb1fb19b9 --- /dev/null +++ b/target/linux/octeontx/generic/target.mk @@ -0,0 +1 @@ +BOARDNAME:=Generic From 314d997e26184718713ba5a14514367edcb2661f Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Mon, 19 Dec 2022 16:47:16 +0100 Subject: [PATCH 13/72] pistachio: add generic subtarget Same game as for 853e4dd3062df7cb5704b15d6af6730e3194b571. Add generic to the filenames. Signed-off-by: Christian Marangi --- target/linux/pistachio/Makefile | 1 + target/linux/pistachio/generic/target.mk | 1 + 2 files changed, 2 insertions(+) create mode 100644 target/linux/pistachio/generic/target.mk diff --git a/target/linux/pistachio/Makefile b/target/linux/pistachio/Makefile index 8bafaa0b217..cec8614a139 100644 --- a/target/linux/pistachio/Makefile +++ b/target/linux/pistachio/Makefile @@ -10,6 +10,7 @@ BOARDNAME:=MIPS pistachio FEATURES:=fpu usb usbgadget squashfs targz nand CPU_TYPE:=24kc CPU_SUBTYPE:=24kf +SUBTARGETS:=generic KERNEL_PATCHVER:=5.10 diff --git a/target/linux/pistachio/generic/target.mk b/target/linux/pistachio/generic/target.mk new file mode 100644 index 00000000000..f5cb1fb19b9 --- /dev/null +++ b/target/linux/pistachio/generic/target.mk @@ -0,0 +1 @@ +BOARDNAME:=Generic From b2bfea481e8030561346a49f92818e07518c08c2 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Mon, 19 Dec 2022 16:47:35 +0100 Subject: [PATCH 14/72] omap: add generic subtarget Same game as for 853e4dd3062df7cb5704b15d6af6730e3194b571. Add generic to the filenames. Signed-off-by: Christian Marangi --- target/linux/omap/Makefile | 1 + target/linux/omap/generic/target.mk | 1 + 2 files changed, 2 insertions(+) create mode 100644 target/linux/omap/generic/target.mk diff --git a/target/linux/omap/Makefile b/target/linux/omap/Makefile index 51f19862d67..364fa07e8e1 100644 --- a/target/linux/omap/Makefile +++ b/target/linux/omap/Makefile @@ -10,6 +10,7 @@ BOARDNAME:=TI OMAP3/4/AM33xx FEATURES:=usb usbgadget ext4 targz fpu audio display nand rootfs-part squashfs CPU_TYPE:=cortex-a8 CPU_SUBTYPE:=vfpv3 +SUBTARGETS:=generic KERNEL_PATCHVER:=5.10 KERNEL_TESTING_PATCHVER:=5.15 diff --git a/target/linux/omap/generic/target.mk b/target/linux/omap/generic/target.mk new file mode 100644 index 00000000000..f5cb1fb19b9 --- /dev/null +++ b/target/linux/omap/generic/target.mk @@ -0,0 +1 @@ +BOARDNAME:=Generic From ae614fb397c2754e2b6dab896b58ec30b11af526 Mon Sep 17 00:00:00 2001 From: Olliver Schinagl Date: Wed, 14 Dec 2022 11:33:01 +0100 Subject: [PATCH 15/72] tools: Improve diffability/maintainability There's no purpose to squish multiple tools into a single line (and spread those out over multiple lines). It might look 'nice' in certain conditions, but it's annoying to maintain. For example, but not limited to: * adding/removing tools, causes hard to read diffs * Duplicates are harder to spot * Sorting can not be (easily?) automated With this proposed change, the above annoyances go away. Inserting a new tool can be done with a single line-change-diff, sorting can be done by any editor (in vi, select, :sort for example) and dupes are much easier to spot. Signed-off-by: Olliver Schinagl --- tools/Makefile | 42 +++++++++++++++++++++++++++++++++++++----- 1 file changed, 37 insertions(+), 5 deletions(-) diff --git a/tools/Makefile b/tools/Makefile index 5ba15c641b4..6300180d3f4 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -21,11 +21,43 @@ ifneq ($(CONFIG_SDK)$(CONFIG_PACKAGE_kmod-b43)$(CONFIG_BRCMSMAC_USE_FW_FROM_WL), BUILD_B43_TOOLS = y endif -tools-y += autoconf autoconf-archive automake bc bison cmake cpio dosfstools -tools-y += e2fsprogs expat fakeroot findutils firmware-utils flex gengetopt -tools-y += libressl libtool lzma m4 make-ext4fs meson missing-macros mkimage -tools-y += mklibs mtd-utils mtools ninja padjffs2 patch-image -tools-y += patchelf pkgconf quilt squashfskit4 sstrip zip zlib zstd +tools-y += autoconf +tools-y += autoconf-archive +tools-y += automake +tools-y += bc +tools-y += bison +tools-y += cmake +tools-y += cpio +tools-y += dosfstools +tools-y += e2fsprogs +tools-y += expat +tools-y += fakeroot +tools-y += findutils +tools-y += firmware-utils +tools-y += flex +tools-y += gengetopt +tools-y += libressl +tools-y += libtool +tools-y += lzma +tools-y += m4 +tools-y += make-ext4fs +tools-y += meson +tools-y += missing-macros +tools-y += mkimage +tools-y += mklibs +tools-y += mtd-utils +tools-y += mtools +tools-y += ninja +tools-y += padjffs2 +tools-y += patch-image +tools-y += patchelf +tools-y += pkgconf +tools-y += quilt +tools-y += squashfskit4 +tools-y += sstrip +tools-y += zip +tools-y += zlib +tools-y += zstd tools-$(if $(CONFIG_BUILD_ALL_HOST_TOOLS)$(BUILD_B43_TOOLS),y) += b43-tools tools-$(if $(CONFIG_BUILD_ALL_HOST_TOOLS)$(BUILD_ISL),y) += isl tools-$(if $(CONFIG_BUILD_ALL_HOST_TOOLS)$(BUILD_TOOLCHAIN),y) += gmp mpc mpfr From 113fd5b93be02cb47008744aa5640107344a3963 Mon Sep 17 00:00:00 2001 From: Olliver Schinagl Date: Mon, 3 Oct 2022 14:45:21 +0200 Subject: [PATCH 16/72] realtek: 5.10: Fix incorrect switch patches Add correct header to patche(s) to be correctly used by git am and have better tracking of it. See commit f1f97db627b2 ("realtek: Convert incorrect v5.10 patches"). Signed-off-by: Olliver Schinagl --- .../302-clocksource-add-otto-driver.patch | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/target/linux/realtek/patches-5.10/302-clocksource-add-otto-driver.patch b/target/linux/realtek/patches-5.10/302-clocksource-add-otto-driver.patch index 8b17ddaef00..81dff89f82f 100644 --- a/target/linux/realtek/patches-5.10/302-clocksource-add-otto-driver.patch +++ b/target/linux/realtek/patches-5.10/302-clocksource-add-otto-driver.patch @@ -1,3 +1,56 @@ +From 3cc8011171186d906c547bc6f0c1f8e350edc7cf Mon Sep 17 00:00:00 2001 +From: Markus Stockhausen +Date: Mon, 3 Oct 2022 14:45:21 +0200 +Subject: [PATCH] realtek: resurrect timer driver + +Now that we provide a clock driver for the Reltek SOCs the CPU frequency might +change on demand. This has direct visible effects during operation + +- the CEVT 4K timer is no longer a stable clocksource +- after CPU frequencies changes time calculation works wrong +- sched_clock falls back to kernel default interval (100 Hz) +- timestamps in dmesg have only 2 digits left + +[ 0.000000] sched_clock: 32 bits at 100 Hz, resolution 10000000ns, wraps ... +[ 0.060000] pid_max: default: 32768 minimum: 301 +[ 0.070000] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) +[ 0.070000] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) +[ 0.080000] dyndbg: Ignore empty _ddebug table in a CONFIG_DYNAMIC_DEBUG_CORE build +[ 0.090000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, ... + +Looking around where we can start the CEVT timer for RTL930X is a good basis. +Initially it was developed as a clocksource driver for the broken timer in that +specific SOC series. Afterwards it was shifted around to the CEVT location, +got SMP enablement and lost its clocksource feature. So we at least have +something to copy from. As the timers on these devices are well understood +the implementation follows this way: + +- leave the RTL930X implementation as is +- provide a new driver for RTL83XX devices only +- swap RTL930X driver at a later time + +Like the clock driver this patch contains a self contained module that is SOC +independet and already provides full support for the RTL838X, RTL839X and +RTL930X devices. Some of the new (or reestablished) features are: + +- simplified initialization routines +- SMP setup with CPU hotplug framework +- derived from LXB clock speed +- supplied clocksource +- dedicated register functions for better readability +- documentation about some caveats + +Signed-off-by: Markus Stockhausen +[remove unused header includes, remove old CONFIG_MIPS dependency, add +REALTEK_ prefix to driver symbol] +Signed-off-by: Sander Vanheule + +--- + drivers/clocksource/Kconfig | 12 +++ + drivers/clocksource/Makefile | 1 + + include/linux/cpuhotplug.h | 1 + + 3 files changed, 14 insertions(+) + --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -127,6 +127,17 @@ config RDA_TIMER From f649a7b5f337f1b2a69879b45ebafffec1380011 Mon Sep 17 00:00:00 2001 From: Olliver Schinagl Date: Mon, 3 Oct 2022 14:45:21 +0200 Subject: [PATCH 17/72] realtek: 5.15: Fix incorrect switch patches Add correct header to patche(s) to be correctly used by git am and have better tracking of it. See commit f1f97db627b2 ("realtek: Convert incorrect v5.10 patches"). Signed-off-by: Olliver Schinagl --- .../302-clocksource-add-otto-driver.patch | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/target/linux/realtek/patches-5.15/302-clocksource-add-otto-driver.patch b/target/linux/realtek/patches-5.15/302-clocksource-add-otto-driver.patch index fb1f4643561..8f2f4c0c4aa 100644 --- a/target/linux/realtek/patches-5.15/302-clocksource-add-otto-driver.patch +++ b/target/linux/realtek/patches-5.15/302-clocksource-add-otto-driver.patch @@ -1,3 +1,56 @@ +From 3cc8011171186d906c547bc6f0c1f8e350edc7cf Mon Sep 17 00:00:00 2001 +From: Markus Stockhausen +Date: Mon, 3 Oct 2022 14:45:21 +0200 +Subject: [PATCH] realtek: resurrect timer driver + +Now that we provide a clock driver for the Reltek SOCs the CPU frequency might +change on demand. This has direct visible effects during operation + +- the CEVT 4K timer is no longer a stable clocksource +- after CPU frequencies changes time calculation works wrong +- sched_clock falls back to kernel default interval (100 Hz) +- timestamps in dmesg have only 2 digits left + +[ 0.000000] sched_clock: 32 bits at 100 Hz, resolution 10000000ns, wraps ... +[ 0.060000] pid_max: default: 32768 minimum: 301 +[ 0.070000] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) +[ 0.070000] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) +[ 0.080000] dyndbg: Ignore empty _ddebug table in a CONFIG_DYNAMIC_DEBUG_CORE build +[ 0.090000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, ... + +Looking around where we can start the CEVT timer for RTL930X is a good basis. +Initially it was developed as a clocksource driver for the broken timer in that +specific SOC series. Afterwards it was shifted around to the CEVT location, +got SMP enablement and lost its clocksource feature. So we at least have +something to copy from. As the timers on these devices are well understood +the implementation follows this way: + +- leave the RTL930X implementation as is +- provide a new driver for RTL83XX devices only +- swap RTL930X driver at a later time + +Like the clock driver this patch contains a self contained module that is SOC +independet and already provides full support for the RTL838X, RTL839X and +RTL930X devices. Some of the new (or reestablished) features are: + +- simplified initialization routines +- SMP setup with CPU hotplug framework +- derived from LXB clock speed +- supplied clocksource +- dedicated register functions for better readability +- documentation about some caveats + +Signed-off-by: Markus Stockhausen +[remove unused header includes, remove old CONFIG_MIPS dependency, add +REALTEK_ prefix to driver symbol] +Signed-off-by: Sander Vanheule + +--- + drivers/clocksource/Kconfig | 12 +++ + drivers/clocksource/Makefile | 1 + + include/linux/cpuhotplug.h | 1 + + 3 files changed, 14 insertions(+) + --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -127,6 +127,17 @@ config RDA_TIMER From af4417418749b9233c5a205affbcdea659cc685b Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Fri, 9 Dec 2022 18:09:32 +0100 Subject: [PATCH 18/72] CI: tools: reogranize and split workflow Generilize tools workflow for future usage in shared workflow for tools build. Split tools workflow to tools and push-containers: - tools just execute build test - push-containers build and push prebuilt containers Signed-off-by: Christian Marangi --- .github/workflows/build-tools.yml | 72 ++++++++++++++ .github/workflows/push-containers.yml | 86 +++++++++++++++++ .github/workflows/tools.yml | 133 +------------------------- 3 files changed, 163 insertions(+), 128 deletions(-) create mode 100644 .github/workflows/build-tools.yml create mode 100644 .github/workflows/push-containers.yml diff --git a/.github/workflows/build-tools.yml b/.github/workflows/build-tools.yml new file mode 100644 index 00000000000..ca415489c5a --- /dev/null +++ b/.github/workflows/build-tools.yml @@ -0,0 +1,72 @@ +name: Build host tools + +on: + workflow_call: + inputs: + generate_prebuilt_artifacts: + type: boolean + +permissions: + contents: read + +jobs: + build: + name: Build tools + runs-on: ubuntu-latest + container: registry.gitlab.com/openwrt/buildbot/buildworker-3.4.1 + + steps: + - name: Checkout + uses: actions/checkout@v3 + with: + path: openwrt + + - name: Fix permission + run: chown -R buildbot:buildbot openwrt + + - name: Set configs for tools container + shell: su buildbot -c "sh -e {0}" + working-directory: openwrt + run: | + touch .config + echo CONFIG_DEVEL=y >> .config + echo CONFIG_AUTOREMOVE=y >> .config + echo CONFIG_CCACHE=y >> .config + + - name: Make prereq + shell: su buildbot -c "sh -e {0}" + working-directory: openwrt + run: make defconfig + + - name: Build tools + shell: su buildbot -c "sh -e {0}" + working-directory: openwrt + run: make tools/install -j$(nproc) BUILD_LOG=1 || ret=$? .github/workflows/scripts/show_build_failures.sh + + - name: Upload logs + if: always() + uses: actions/upload-artifact@v3 + with: + name: linux-buildbot-logs + path: openwrt/logs + + - name: Upload config + if: always() + uses: actions/upload-artifact@v3 + with: + name: linux-buildbot-config + path: openwrt/.config + + - name: Archive prebuilt tools + if: inputs.generate_prebuilt_artifacts == true + shell: su buildbot -c "sh -e {0}" + working-directory: openwrt + run: tar --mtime=now -cf tools.tar staging_dir/host build_dir/host dl + + - name: Upload prebuilt tools + if: inputs.generate_prebuilt_artifacts == true + uses: actions/upload-artifact@v3 + with: + name: linux-buildbot-prebuilt-tools + path: openwrt/tools.tar + retention-days: 1 diff --git a/.github/workflows/push-containers.yml b/.github/workflows/push-containers.yml new file mode 100644 index 00000000000..56e0daa611b --- /dev/null +++ b/.github/workflows/push-containers.yml @@ -0,0 +1,86 @@ +name: Build and Push prebuilt tools container + +on: + push: + paths: + - 'tools/**' + - '.github/workflows/build-tools.yml' + - '.github/workflows/push-containers.yml' + - '.github/workflows/Dockerfile.tools' + +permissions: + contents: read + +jobs: + build-linux-buildbot: + name: Build tools with buildbot container + uses: ./.github/workflows/build-tools.yml + with: + generate_prebuilt_artifacts: true + + push-tools-container: + needs: build-linux-buildbot + name: Push prebuilt tools container + runs-on: ubuntu-latest + + permissions: + contents: read + packages: write + + steps: + - name: Set lower case owner name + env: + OWNER: ${{ github.repository_owner }} + run: | + echo "OWNER_LC=${OWNER,,}" >> "$GITHUB_ENV" + + # Per branch tools container tag + # By default stick to latest + # For official test targetting openwrt stable branch + # Get the branch or parse the tag and push dedicated tools containers + # Any branch that will match this pattern openwrt-[0-9][0-9].[0-9][0-9] + # will refresh the tools container with the matching tag. + # (example branch openwrt-22.03 -> tools:openwrt-22.03) + # (example branch openwrt-22.03-test -> tools:openwrt-22.03) + - name: Determine tools container tag + run: | + CONTAINER_TAG=latest + + if [ ${{ github.ref_type }} == "branch" ]; then + if echo "${{ github.ref_name }}" | grep -q -E 'openwrt-[0-9][0-9]\.[0-9][0-9]'; then + CONTAINER_TAG="$(echo ${{ github.ref_name }} | sed 's/^\(openwrt-[0-9][0-9]\.[0-9][0-9]\).*/\1/')" + fi + elif [ ${{ github.ref_type }} == "tag" ]; then + if echo "${{ github.ref_name }}" | grep -q -E 'v[0-9][0-9]\.[0-9][0-9]\..+'; then + CONTAINER_TAG=openwrt-"$(echo ${{ github.ref_name }} | sed 's/v\([0-9][0-9]\.[0-9][0-9]\)\..\+/\1/')" + fi + fi + + echo "Tools container to push tools:$CONTAINER_TAG" + echo "CONTAINER_TAG=$CONTAINER_TAG" >> "$GITHUB_ENV" + + - name: Checkout + uses: actions/checkout@v3 + with: + path: 'openwrt' + + - name: Download prebuilt tools from build job + uses: actions/download-artifact@v3 + with: + name: linux-buildbot-prebuilt-tools + path: openwrt + + - name: Login to GitHub Container Registry + uses: docker/login-action@v2 + with: + registry: ghcr.io + username: ${{ github.actor }} + password: ${{ secrets.GITHUB_TOKEN }} + + - name: Build and push + uses: docker/build-push-action@v3 + with: + context: openwrt + push: true + tags: ghcr.io/${{ env.OWNER_LC }}/tools:${{ env.CONTAINER_TAG }} + file: openwrt/.github/workflows/Dockerfile.tools diff --git a/.github/workflows/tools.yml b/.github/workflows/tools.yml index 304b5f7d62a..69ee456bce9 100644 --- a/.github/workflows/tools.yml +++ b/.github/workflows/tools.yml @@ -4,10 +4,12 @@ on: pull_request: paths: - 'tools/**' + - '.github/workflows/build-tools.yml' - '.github/workflows/tools.yml' push: paths: - 'tools/**' + - '.github/workflows/build-tools.yml' - '.github/workflows/tools.yml' permissions: @@ -15,7 +17,7 @@ permissions: jobs: build-macos-latest: - if: github.event_name != 'push' + name: Build tools with macos latest runs-on: macos-latest steps: @@ -97,130 +99,5 @@ jobs: path: ${{ env.WORKPATH }}/openwrt/.config build-linux-buildbot: - runs-on: ubuntu-latest - container: registry.gitlab.com/openwrt/buildbot/buildworker-3.4.1 - - steps: - - name: Checkout - uses: actions/checkout@v3 - with: - path: 'openwrt' - - - name: Fix permission - run: | - chown -R buildbot:buildbot openwrt - - - name: Set configs for tools container - if: github.event_name == 'push' - shell: su buildbot -c "sh -e {0}" - working-directory: openwrt - run: | - touch .config - echo CONFIG_DEVEL=y >> .config - echo CONFIG_AUTOREMOVE=y >> .config - echo CONFIG_CCACHE=y >> .config - - - name: Make prereq - shell: su buildbot -c "sh -e {0}" - working-directory: openwrt - run: make defconfig - - - name: Build tools BuildBot Container - shell: su buildbot -c "sh -e {0}" - working-directory: openwrt - run: make tools/install -j$(nproc) BUILD_LOG=1 || ret=$? .github/workflows/scripts/show_build_failures.sh - - - name: Upload logs - if: always() - uses: actions/upload-artifact@v3 - with: - name: linux-buildbot-logs - path: openwrt/logs - - - name: Upload config - if: always() - uses: actions/upload-artifact@v3 - with: - name: linux-buildbot-config - path: openwrt/.config - - - name: Archive prebuilt tools - if: github.event_name == 'push' - shell: su buildbot -c "sh -e {0}" - working-directory: openwrt - run: tar --mtime=now -cf tools.tar staging_dir/host build_dir/host dl - - - name: Upload prebuilt tools - if: github.event_name == 'push' - uses: actions/upload-artifact@v3 - with: - name: linux-buildbot-prebuilt-tools - path: openwrt/tools.tar - retention-days: 1 - - push-tools-container: - needs: build-linux-buildbot - runs-on: ubuntu-latest - if: github.event_name == 'push' - - permissions: - contents: read - packages: write - - steps: - - name: Set lower case owner name - env: - OWNER: ${{ github.repository_owner }} - run: | - echo "OWNER_LC=${OWNER,,}" >> "$GITHUB_ENV" - - # Per branch tools container tag - # By default stick to latest - # For official test targetting openwrt stable branch - # Get the branch or parse the tag and push dedicated tools containers - # Any branch that will match this pattern openwrt-[0-9][0-9].[0-9][0-9] - # will refresh the tools container with the matching tag. - # (example branch openwrt-22.03 -> tools:openwrt-22.03) - # (example branch openwrt-22.03-test -> tools:openwrt-22.03) - - name: Determine tools container tag - run: | - CONTAINER_TAG=latest - - if [ ${{ github.ref_type }} == "branch" ]; then - if echo "${{ github.ref_name }}" | grep -q -E 'openwrt-[0-9][0-9]\.[0-9][0-9]'; then - CONTAINER_TAG="$(echo ${{ github.ref_name }} | sed 's/^\(openwrt-[0-9][0-9]\.[0-9][0-9]\).*/\1/')" - fi - elif [ ${{ github.ref_type }} == "tag" ]; then - if echo "${{ github.ref_name }}" | grep -q -E 'v[0-9][0-9]\.[0-9][0-9]\..+'; then - CONTAINER_TAG=openwrt-"$(echo ${{ github.ref_name }} | sed 's/v\([0-9][0-9]\.[0-9][0-9]\)\..\+/\1/')" - fi - fi - - echo "Tools container to push tools:$CONTAINER_TAG" - echo "CONTAINER_TAG=$CONTAINER_TAG" >> "$GITHUB_ENV" - - - name: Checkout - uses: actions/checkout@v3 - with: - path: 'openwrt' - - - name: Download prebuilt tools from build job - uses: actions/download-artifact@v3 - with: - name: linux-buildbot-prebuilt-tools - path: openwrt - - - name: Login to GitHub Container Registry - uses: docker/login-action@v2 - with: - registry: ghcr.io - username: ${{ github.actor }} - password: ${{ secrets.GITHUB_TOKEN }} - - - name: Build and push - uses: docker/build-push-action@v3 - with: - context: openwrt - push: true - tags: ghcr.io/${{ env.OWNER_LC }}/tools:${{ env.CONTAINER_TAG }} - file: openwrt/.github/workflows/Dockerfile.tools + name: Build tools with buildbot container + uses: ./.github/workflows/build-tools.yml From b4da12c2a0609975cf5ae03d3deb92012bf9e784 Mon Sep 17 00:00:00 2001 From: Josef Schlehofer Date: Thu, 22 Dec 2022 19:37:36 +0100 Subject: [PATCH 19/72] mpc85xx: drop empty patch as it backported to LTS kernel 5.15.70 This patch is part of Linux kernel 5.15.70, the content was removed, but the empty file is still being carried over the repository, so remove it once for all Fixes: e1b009c ("kernel: bump 5.15 to 5.15.70") Signed-off-by: Josef Schlehofer --- ...110-gpio-mpc8xxx-Fix-support-for-IRQ_TYPE_LEVEL_LOW-flow.patch | 0 1 file changed, 0 insertions(+), 0 deletions(-) delete mode 100644 target/linux/mpc85xx/patches-5.15/110-gpio-mpc8xxx-Fix-support-for-IRQ_TYPE_LEVEL_LOW-flow.patch diff --git a/target/linux/mpc85xx/patches-5.15/110-gpio-mpc8xxx-Fix-support-for-IRQ_TYPE_LEVEL_LOW-flow.patch b/target/linux/mpc85xx/patches-5.15/110-gpio-mpc8xxx-Fix-support-for-IRQ_TYPE_LEVEL_LOW-flow.patch deleted file mode 100644 index e69de29bb2d..00000000000 From cb7d662dac897dd7df6ba6ba60417db822bd68f2 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sat, 24 Dec 2022 14:39:17 +0100 Subject: [PATCH 20/72] mac80211: Do not build brcmsmac on bcm47xx_legacy brcmsmac needs bcma. bcma is build into the kernel for the other bcm47xx subtargets, but not for the legacy target because it only uses ssb. We could build bcma as a module for bcm47xx_legacy, but none of these old devices uses a wifi card supported by brcsmac. Signed-off-by: Hauke Mehrtens --- package/kernel/mac80211/broadcom.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/package/kernel/mac80211/broadcom.mk b/package/kernel/mac80211/broadcom.mk index 67599acbade..90167941c4e 100644 --- a/package/kernel/mac80211/broadcom.mk +++ b/package/kernel/mac80211/broadcom.mk @@ -381,7 +381,7 @@ define KernelPackage/brcmsmac $(call KernelPackage/mac80211/Default) TITLE:=Broadcom IEEE802.11n PCIe SoftMAC WLAN driver URL:=https://wireless.wiki.kernel.org/en/users/drivers/brcm80211 - DEPENDS+= +kmod-mac80211 +!TARGET_bcm47xx:kmod-bcma +kmod-lib-cordic +kmod-lib-crc8 +kmod-brcmutil +!BRCMSMAC_USE_FW_FROM_WL:brcmsmac-firmware + DEPENDS+=@!TARGET_bcm47xx_legacy +kmod-mac80211 +!TARGET_bcm47xx:kmod-bcma +kmod-lib-cordic +kmod-lib-crc8 +kmod-brcmutil +!BRCMSMAC_USE_FW_FROM_WL:brcmsmac-firmware FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/broadcom/brcm80211/brcmsmac/brcmsmac.ko AUTOLOAD:=$(call AutoProbe,brcmsmac) MENU:=1 From 0c405bceba11574b3d11c5612adfe5f70e2817fd Mon Sep 17 00:00:00 2001 From: John Audia Date: Wed, 21 Dec 2022 14:13:53 -0500 Subject: [PATCH 21/72] kernel: bump 5.15 to 5.15.85 All patches automatically rebased. Build system: x86_64 Build-tested: bcm2711/RPi4B Run-tested: bcm2711/RPi4B Signed-off-by: John Audia --- include/kernel-5.15 | 4 ++-- .../950-0600-xhci-quirks-add-link-TRB-quirk-for-VL805.patch | 2 +- .../950-0606-usb-xhci-add-VLI_TRB_CACHE_BUG-quirk.patch | 2 +- ...usb-xhci-add-a-quirk-for-Superspeed-bulk-OUT-transfe.patch | 2 +- .../hack-5.15/780-usb-net-MeigLink_modem_support.patch | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/include/kernel-5.15 b/include/kernel-5.15 index 5013ce44e23..c32d5f6d23a 100644 --- a/include/kernel-5.15 +++ b/include/kernel-5.15 @@ -1,2 +1,2 @@ -LINUX_VERSION-5.15 = .84 -LINUX_KERNEL_HASH-5.15.84 = 318dc30cb059c2e35b59652b166b39804bb3a941f11878aae6119019a04b8217 +LINUX_VERSION-5.15 = .85 +LINUX_KERNEL_HASH-5.15.85 = 2c0bae29fac98e0a9408914a4551b2971365ac0000351cb255d6bd9aa0849808 diff --git a/target/linux/bcm27xx/patches-5.15/950-0600-xhci-quirks-add-link-TRB-quirk-for-VL805.patch b/target/linux/bcm27xx/patches-5.15/950-0600-xhci-quirks-add-link-TRB-quirk-for-VL805.patch index dc946b1c634..10820c6708a 100644 --- a/target/linux/bcm27xx/patches-5.15/950-0600-xhci-quirks-add-link-TRB-quirk-for-VL805.patch +++ b/target/linux/bcm27xx/patches-5.15/950-0600-xhci-quirks-add-link-TRB-quirk-for-VL805.patch @@ -22,7 +22,7 @@ Signed-off-by: Jonathan Bell --- a/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c -@@ -291,6 +291,7 @@ static void xhci_pci_quirks(struct devic +@@ -293,6 +293,7 @@ static void xhci_pci_quirks(struct devic if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) { xhci->quirks |= XHCI_LPM_SUPPORT; xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS; diff --git a/target/linux/bcm27xx/patches-5.15/950-0606-usb-xhci-add-VLI_TRB_CACHE_BUG-quirk.patch b/target/linux/bcm27xx/patches-5.15/950-0606-usb-xhci-add-VLI_TRB_CACHE_BUG-quirk.patch index 4d477eb4e1e..f3bb6384c65 100644 --- a/target/linux/bcm27xx/patches-5.15/950-0606-usb-xhci-add-VLI_TRB_CACHE_BUG-quirk.patch +++ b/target/linux/bcm27xx/patches-5.15/950-0606-usb-xhci-add-VLI_TRB_CACHE_BUG-quirk.patch @@ -53,7 +53,7 @@ Signed-off-by: Jonathan Bell cycle_state, type, max_packet, flags); --- a/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c -@@ -292,6 +292,7 @@ static void xhci_pci_quirks(struct devic +@@ -294,6 +294,7 @@ static void xhci_pci_quirks(struct devic xhci->quirks |= XHCI_LPM_SUPPORT; xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS; xhci->quirks |= XHCI_AVOID_DQ_ON_LINK; diff --git a/target/linux/bcm27xx/patches-5.15/950-0717-usb-xhci-add-a-quirk-for-Superspeed-bulk-OUT-transfe.patch b/target/linux/bcm27xx/patches-5.15/950-0717-usb-xhci-add-a-quirk-for-Superspeed-bulk-OUT-transfe.patch index 372ec6f8e7c..34562507c29 100644 --- a/target/linux/bcm27xx/patches-5.15/950-0717-usb-xhci-add-a-quirk-for-Superspeed-bulk-OUT-transfe.patch +++ b/target/linux/bcm27xx/patches-5.15/950-0717-usb-xhci-add-a-quirk-for-Superspeed-bulk-OUT-transfe.patch @@ -26,7 +26,7 @@ Signed-off-by: Jonathan Bell --- a/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c -@@ -293,6 +293,7 @@ static void xhci_pci_quirks(struct devic +@@ -295,6 +295,7 @@ static void xhci_pci_quirks(struct devic xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS; xhci->quirks |= XHCI_AVOID_DQ_ON_LINK; xhci->quirks |= XHCI_VLI_TRB_CACHE_BUG; diff --git a/target/linux/generic/hack-5.15/780-usb-net-MeigLink_modem_support.patch b/target/linux/generic/hack-5.15/780-usb-net-MeigLink_modem_support.patch index eb11d9b700b..60c5f6b7625 100644 --- a/target/linux/generic/hack-5.15/780-usb-net-MeigLink_modem_support.patch +++ b/target/linux/generic/hack-5.15/780-usb-net-MeigLink_modem_support.patch @@ -29,7 +29,7 @@ Subject: [PATCH] net/usb/qmi_wwan: add MeigLink modem support #define QUECTEL_VENDOR_ID 0x2c7c /* These Quectel products use Quectel's vendor ID */ -@@ -1155,6 +1157,11 @@ static const struct usb_device_id option +@@ -1156,6 +1158,11 @@ static const struct usb_device_id option .driver_info = ZLP }, { USB_DEVICE(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_BG96), .driver_info = RSVD(4) }, From 59254010077c9086afee8a8b4c490943d6749065 Mon Sep 17 00:00:00 2001 From: John Audia Date: Wed, 21 Dec 2022 14:19:12 -0500 Subject: [PATCH 22/72] kernel: bump 5.10 to 5.10.161 All patches automatically rebased. Build system: x86_64 Build-tested: ramips/tplink_archer-a6-v3 Run-tested: ramips/tplink_archer-a6-v3 Signed-off-by: John Audia --- include/kernel-5.10 | 4 ++-- .../patches-5.10/802-usb-xhci-force-msi-renesas-xhci.patch | 2 +- .../hack-5.10/780-usb-net-MeigLink_modem_support.patch | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/kernel-5.10 b/include/kernel-5.10 index abfb0422d12..da007fc72dd 100644 --- a/include/kernel-5.10 +++ b/include/kernel-5.10 @@ -1,2 +1,2 @@ -LINUX_VERSION-5.10 = .160 -LINUX_KERNEL_HASH-5.10.160 = 30d5076acae863941045880c4c5c5109d26a54a932168fa1324237e8aeaa840b +LINUX_VERSION-5.10 = .161 +LINUX_KERNEL_HASH-5.10.161 = 7aaaf6d0bcd8a2cfa14ad75f02ca62bb2de08aad3bee3eff198de49ea5254079 diff --git a/target/linux/apm821xx/patches-5.10/802-usb-xhci-force-msi-renesas-xhci.patch b/target/linux/apm821xx/patches-5.10/802-usb-xhci-force-msi-renesas-xhci.patch index 4ca2946481f..00ca3fbade7 100644 --- a/target/linux/apm821xx/patches-5.10/802-usb-xhci-force-msi-renesas-xhci.patch +++ b/target/linux/apm821xx/patches-5.10/802-usb-xhci-force-msi-renesas-xhci.patch @@ -13,7 +13,7 @@ produce a noisy warning. --- a/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c -@@ -274,6 +274,7 @@ static void xhci_pci_quirks(struct devic +@@ -276,6 +276,7 @@ static void xhci_pci_quirks(struct devic pdev->device == 0x0015) { xhci->quirks |= XHCI_RESET_ON_RESUME; xhci->quirks |= XHCI_ZERO_64B_REGS; diff --git a/target/linux/generic/hack-5.10/780-usb-net-MeigLink_modem_support.patch b/target/linux/generic/hack-5.10/780-usb-net-MeigLink_modem_support.patch index 8718aedfa35..6d499b88fe8 100644 --- a/target/linux/generic/hack-5.10/780-usb-net-MeigLink_modem_support.patch +++ b/target/linux/generic/hack-5.10/780-usb-net-MeigLink_modem_support.patch @@ -33,7 +33,7 @@ Submitted-by: Daniel Golle #define QUECTEL_VENDOR_ID 0x2c7c /* These Quectel products use Quectel's vendor ID */ -@@ -1155,6 +1157,11 @@ static const struct usb_device_id option +@@ -1156,6 +1158,11 @@ static const struct usb_device_id option .driver_info = ZLP }, { USB_DEVICE(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_BG96), .driver_info = RSVD(4) }, From c7d3bbb909bdcccd4f26f18b18cc1cb00500a874 Mon Sep 17 00:00:00 2001 From: Jan-Niklas Burfeind Date: Fri, 23 Dec 2022 22:03:14 +0100 Subject: [PATCH 23/72] sunxi: ensure NanoPi R1 has unique MAC address Ensure the MAC address for all NanoPi R1 boards is assigned uniquely for each board. The vendor ships the device in two variants; one with and one without eMMC; but both without static mac-addresses. In order to assign both board types unique MAC addresses, fall back on the same method used for the NanoPi R2S and R4S in case the EEPROM chip is not present by generating the board MAC from the SD card CID. [0] https://wiki.friendlyelec.com/wiki/index.php/NanoPi_R1#Hardware_Spec Similar too and based on: commit b5675f500daf ("rockchip: ensure NanoPi R4S has unique MAC address") Co-authored-by: David Bauer Signed-off-by: Jan-Niklas Burfeind --- .../base-files/files/lib/functions/system.sh | 8 ++++++ .../armv8/base-files/etc/board.d/02_network | 13 ++-------- .../sunxi/base-files/etc/board.d/02_network | 25 +++++++++++++++++++ 3 files changed, 35 insertions(+), 11 deletions(-) diff --git a/package/base-files/files/lib/functions/system.sh b/package/base-files/files/lib/functions/system.sh index 29de2e5dd69..176c10d0655 100644 --- a/package/base-files/files/lib/functions/system.sh +++ b/package/base-files/files/lib/functions/system.sh @@ -204,6 +204,14 @@ macaddr_add() { echo $oui:$nic } +macaddr_generate_from_mmc_cid() { + local mmc_dev=$1 + + local sd_hash=$(sha256sum /sys/class/block/$mmc_dev/device/cid) + local mac_base=$(macaddr_canonicalize "$(echo "${sd_hash}" | dd bs=1 count=12 2>/dev/null)") + echo "$(macaddr_unsetbit_mc "$(macaddr_setbit_la "${mac_base}")")" +} + macaddr_geteui() { local mac=$1 local sep=$2 diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network index b0e64799471..816045a4803 100644 --- a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network +++ b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network @@ -17,15 +17,6 @@ rockchip_setup_interfaces() esac } -generate_mac_from_mmc_cid() -{ - local mmc_dev=$1 - - local sd_hash=$(sha256sum /sys/class/block/$mmc_dev/device/cid) - local mac_base=$(macaddr_canonicalize "$(echo "${sd_hash}" | dd bs=1 count=12 2>/dev/null)") - echo "$(macaddr_unsetbit_mc "$(macaddr_setbit_la "${mac_base}")")" -} - nanopi_r4s_get_mac() { local interface=$1 @@ -38,7 +29,7 @@ nanopi_r4s_get_mac() address=$(macaddr_setbit_la "$address") fi else - address=$(generate_mac_from_mmc_cid mmcblk1) + address=$(macaddr_generate_from_mmc_cid mmcblk1) if [ "$interface" = "lan" ]; then address=$(macaddr_add "$address" 1) fi @@ -56,7 +47,7 @@ rockchip_setup_macs() case "$board" in friendlyarm,nanopi-r2s) - wan_mac=$(generate_mac_from_mmc_cid mmcblk0) + wan_mac=$(macaddr_generate_from_mmc_cid mmcblk0) lan_mac=$(macaddr_add "$wan_mac" 1) ;; friendlyarm,nanopi-r4s) diff --git a/target/linux/sunxi/base-files/etc/board.d/02_network b/target/linux/sunxi/base-files/etc/board.d/02_network index 46ace1f67c5..b295dc7daa4 100644 --- a/target/linux/sunxi/base-files/etc/board.d/02_network +++ b/target/linux/sunxi/base-files/etc/board.d/02_network @@ -29,6 +29,27 @@ sunxi_setup_interfaces() esac } +nanopi_r1_get_mac() +{ + local interface=$1 + local eeprom_path="/sys/bus/i2c/devices/2-0051/eeprom" + local address + + if [ -f "$eeprom_path" ]; then + address=$(get_mac_binary "$eeprom_path" 0xfa) + if [ "$interface" = "lan" ]; then + address=$(macaddr_setbit_la "$address") + fi + else + address=$(macaddr_generate_from_mmc_cid mmcblk1) + if [ "$interface" = "lan" ]; then + address=$(macaddr_add "$address" 1) + fi + fi + + echo "$address" +} + sunxi_setup_macs() { local board="$1" @@ -37,6 +58,10 @@ sunxi_setup_macs() local label_mac="" case "$board" in + friendlyarm,nanopi-r1) + wan_mac=$(nanopi_r1_get_mac wan) + lan_mac=$(nanopi_r1_get_mac lan) + ;; friendlyarm,nanopi-r1s-h5) lan_mac=$(get_mac_binary "/sys/bus/i2c/devices/0-0051/eeprom" 0xfa) ;; From 5c85c1f344c649c7dbd11046b6a412b88e0db5d9 Mon Sep 17 00:00:00 2001 From: Kuan-Yi Li Date: Sun, 25 Dec 2022 04:05:03 +0800 Subject: [PATCH 24/72] uboot-kirkwood: build with kirkwood generic subtarget Fix image build fail by using the generic subtarget. Fixes: cada395a ("kirkwood: add generic subtarget") Ref: 40e3f660 ("uboot-fritz4040: build with ipq40xx generic subtarget") Signed-off-by: Kuan-Yi Li [ add commit description ] Signed-off-by: Christian Marangi --- package/boot/uboot-kirkwood/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/package/boot/uboot-kirkwood/Makefile b/package/boot/uboot-kirkwood/Makefile index d9cb10ce13a..320d14bfa86 100644 --- a/package/boot/uboot-kirkwood/Makefile +++ b/package/boot/uboot-kirkwood/Makefile @@ -17,6 +17,7 @@ include $(INCLUDE_DIR)/package.mk define U-Boot/Default BUILD_TARGET:=kirkwood + BUILD_SUBTARGET:=generic endef define U-Boot/dockstar From 1c35dc26f12fae6aa7e2f3e7cf5481508a0e6c61 Mon Sep 17 00:00:00 2001 From: Kuan-Yi Li Date: Sun, 25 Dec 2022 04:06:03 +0800 Subject: [PATCH 25/72] uboot-mxs: build with mxs generic subtarget Fix image build fail by using the generic subtarget. Fixes: 64ef920b ("mxs: add generic subtarget") Ref: 40e3f660 ("uboot-fritz4040: build with ipq40xx generic subtarget") Signed-off-by: Kuan-Yi Li [ add commit description ] Signed-off-by: Christian Marangi --- package/boot/uboot-mxs/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/package/boot/uboot-mxs/Makefile b/package/boot/uboot-mxs/Makefile index 3c908874faa..ae1c027a0a8 100644 --- a/package/boot/uboot-mxs/Makefile +++ b/package/boot/uboot-mxs/Makefile @@ -19,6 +19,7 @@ include $(INCLUDE_DIR)/host-build.mk define U-Boot/Default BUILD_TARGET:=mxs + BUILD_SUBTARGET:=generic UBOOT_IMAGE:=u-boot.sb DEFAULT:=y HIDDEN:=1 From 64bfb8b7d64708e3da7d245783ca79de2db6cbff Mon Sep 17 00:00:00 2001 From: Kuan-Yi Li Date: Sun, 25 Dec 2022 04:06:14 +0800 Subject: [PATCH 26/72] uboot-zynq: build with zynq generic subtarget Fix image build fail by using the generic subtarget. Fixes: 6d7129ef ("zynq: add generic subtarget") Ref: 40e3f660 ("uboot-fritz4040: build with ipq40xx generic subtarget") Signed-off-by: Kuan-Yi Li [ add commit description ] Signed-off-by: Christian Marangi --- package/boot/uboot-zynq/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/package/boot/uboot-zynq/Makefile b/package/boot/uboot-zynq/Makefile index c605cfaeb2a..0f93c4f4535 100644 --- a/package/boot/uboot-zynq/Makefile +++ b/package/boot/uboot-zynq/Makefile @@ -18,6 +18,7 @@ include $(INCLUDE_DIR)/host-build.mk define U-Boot/Default BUILD_TARGET:=zynq + BUILD_SUBTARGET:=generic UBOOT_IMAGE:=spl/boot.bin u-boot.img UBOOT_CONFIG:=zynq_$(1) UENV:=default From 808046b2ee9e6cba3d1b4aa8c64c34087b245bfe Mon Sep 17 00:00:00 2001 From: Kuan-Yi Li Date: Sun, 25 Dec 2022 04:06:26 +0800 Subject: [PATCH 27/72] uboot-tegra: build with tegra generic subtarget Fix image build fail by using the generic subtarget. Fixes: c028e1b1 ("tegra: add generic subtarget") Ref: 40e3f660 ("uboot-fritz4040: build with ipq40xx generic subtarget") Signed-off-by: Kuan-Yi Li [ add commit description ] Signed-off-by: Christian Marangi --- package/boot/uboot-tegra/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/package/boot/uboot-tegra/Makefile b/package/boot/uboot-tegra/Makefile index 582f7be9471..876682fabc4 100644 --- a/package/boot/uboot-tegra/Makefile +++ b/package/boot/uboot-tegra/Makefile @@ -18,6 +18,7 @@ include $(INCLUDE_DIR)/package.mk define U-Boot/Default BUILD_TARGET := tegra + BUILD_SUBTARGET := generic HIDDEN := y endef From a5f16b4f4fa36dede65c70de1464971052a0dcbd Mon Sep 17 00:00:00 2001 From: Kuan-Yi Li Date: Sun, 25 Dec 2022 04:06:38 +0800 Subject: [PATCH 28/72] uboot-omap: build with omap generic subtarget Fix image build fail by using the generic subtarget. Fixes: b2bfea48 ("omap: add generic subtarget") Ref: 40e3f660 ("uboot-fritz4040: build with ipq40xx generic subtarget") Signed-off-by: Kuan-Yi Li [ add commit description ] Signed-off-by: Christian Marangi --- package/boot/uboot-omap/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/package/boot/uboot-omap/Makefile b/package/boot/uboot-omap/Makefile index 4c12eec29dc..4ee0bde7add 100644 --- a/package/boot/uboot-omap/Makefile +++ b/package/boot/uboot-omap/Makefile @@ -18,6 +18,7 @@ include $(INCLUDE_DIR)/package.mk define U-Boot/Default BUILD_TARGET:=omap + BUILD_SUBTARGET:=generic UBOOT_IMAGE:=u-boot.img MLO endef From 5c7e4a9d2e25d5ecc33c3c2650e4f954936c9c69 Mon Sep 17 00:00:00 2001 From: Kevin Darbyshire-Bryant Date: Mon, 17 Oct 2022 19:28:07 +0100 Subject: [PATCH 29/72] dnsmasq: bump to v2.88 Most relevant feature for openwrt in this release, supports dynamically removing hosts from 'hostsdir' supplied host files. Signed-off-by: Kevin Darbyshire-Bryant --- package/network/services/dnsmasq/Makefile | 4 ++-- .../patches/100-remove-old-runtime-kernel-support.patch | 6 +++--- package/network/services/dnsmasq/patches/200-ubus_dns.patch | 6 +++--- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/package/network/services/dnsmasq/Makefile b/package/network/services/dnsmasq/Makefile index d4aa2984501..65ef9da3a9a 100644 --- a/package/network/services/dnsmasq/Makefile +++ b/package/network/services/dnsmasq/Makefile @@ -8,13 +8,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=dnsmasq -PKG_UPSTREAM_VERSION:=2.87 +PKG_UPSTREAM_VERSION:=2.88 PKG_VERSION:=$(subst test,~~test,$(subst rc,~rc,$(PKG_UPSTREAM_VERSION))) PKG_RELEASE:=$(AUTORELEASE) PKG_SOURCE:=$(PKG_NAME)-$(PKG_UPSTREAM_VERSION).tar.xz PKG_SOURCE_URL:=https://thekelleys.org.uk/dnsmasq/ -PKG_HASH:=0228c0364a7f2356fd7e7f1549937cbf3099a78d3b2eb1ba5bb0c31e2b89de7a +PKG_HASH:=23544deda10340c053bea6f15a93fed6ea7f5aaa85316bfc671ffa6d22fbc1b3 PKG_LICENSE:=GPL-2.0 PKG_LICENSE_FILES:=COPYING diff --git a/package/network/services/dnsmasq/patches/100-remove-old-runtime-kernel-support.patch b/package/network/services/dnsmasq/patches/100-remove-old-runtime-kernel-support.patch index b1b134a98c2..76065375bde 100644 --- a/package/network/services/dnsmasq/patches/100-remove-old-runtime-kernel-support.patch +++ b/package/network/services/dnsmasq/patches/100-remove-old-runtime-kernel-support.patch @@ -26,7 +26,7 @@ Signed-off-by: Kevin Darbyshire-Bryant --- a/src/dnsmasq.h +++ b/src/dnsmasq.h -@@ -1229,7 +1229,7 @@ extern struct daemon { +@@ -1247,7 +1247,7 @@ extern struct daemon { int inotifyfd; #endif #if defined(HAVE_LINUX_NETWORK) @@ -35,7 +35,7 @@ Signed-off-by: Kevin Darbyshire-Bryant #elif defined(HAVE_BSD_NETWORK) int dhcp_raw_fd, dhcp_icmp_fd, routefd; #endif -@@ -1422,9 +1422,6 @@ int read_write(int fd, unsigned char *pa +@@ -1452,9 +1452,6 @@ int read_write(int fd, unsigned char *pa void close_fds(long max_fd, int spare1, int spare2, int spare3); int wildcard_match(const char* wildcard, const char* match); int wildcard_matchn(const char* wildcard, const char* match, int num); @@ -140,7 +140,7 @@ Signed-off-by: Kevin Darbyshire-Bryant my_syslog(LOG_ERR, _("failed to update ipset %s: %s"), setname, strerror(errno)); --- a/src/util.c +++ b/src/util.c -@@ -833,22 +833,3 @@ int wildcard_matchn(const char* wildcard +@@ -855,22 +855,3 @@ int wildcard_matchn(const char* wildcard return (!num) || (*wildcard == *match); } diff --git a/package/network/services/dnsmasq/patches/200-ubus_dns.patch b/package/network/services/dnsmasq/patches/200-ubus_dns.patch index c4cc1df207f..f88763f94a0 100644 --- a/package/network/services/dnsmasq/patches/200-ubus_dns.patch +++ b/package/network/services/dnsmasq/patches/200-ubus_dns.patch @@ -1,6 +1,6 @@ --- a/src/dnsmasq.h +++ b/src/dnsmasq.h -@@ -1598,14 +1598,26 @@ void emit_dbus_signal(int action, struct +@@ -1630,14 +1630,26 @@ void emit_dbus_signal(int action, struct /* ubus.c */ #ifdef HAVE_UBUS @@ -151,7 +151,7 @@ if (!ADD_RDLEN(header, p, qlen, rdlen)) return 0; /* bad packet */ } -@@ -568,7 +637,7 @@ int extract_addresses(struct dns_header +@@ -570,7 +639,7 @@ int extract_addresses(struct dns_header cache_start_insert(); /* find_soa is needed for dns_doctor side effects, so don't call it lazily if there are any. */ @@ -269,7 +269,7 @@ struct ubus_context *ubus = (struct ubus_context *)daemon->ubus; --- a/src/dnsmasq.c +++ b/src/dnsmasq.c -@@ -1998,6 +1998,10 @@ static void check_dns_listeners(time_t n +@@ -2003,6 +2003,10 @@ static void check_dns_listeners(time_t n daemon->pipe_to_parent = pipefd[1]; } From ab31547df06430798e6adb853a7faab13eb1754c Mon Sep 17 00:00:00 2001 From: Xuefer H Date: Sat, 24 Dec 2022 20:16:11 +0800 Subject: [PATCH 30/72] libbsd: fix libpath to not use host path libpath.so uses host path in ld script causing other packages fail to cross compile, e.g. perl: "ld: cannot find /usr/lib/libbsd.so.0.11.6: No such file or directory" Fixes: openwrt/packages#19390 Signed-off-by: Xuefer H --- package/libs/libbsd/Makefile | 1 + package/libs/libbsd/patches/001-fix-libpath.patch | 13 +++++++++++++ 2 files changed, 14 insertions(+) create mode 100644 package/libs/libbsd/patches/001-fix-libpath.patch diff --git a/package/libs/libbsd/Makefile b/package/libs/libbsd/Makefile index 789126cb829..92c7054e3bd 100644 --- a/package/libs/libbsd/Makefile +++ b/package/libs/libbsd/Makefile @@ -14,6 +14,7 @@ PKG_LICENSE_FILES:=COPYING PKG_INSTALL:=1 PKG_BUILD_PARALLEL:=1 PKG_BUILD_DEPENDS := libmd +PKG_FIXUP:=autoreconf include $(INCLUDE_DIR)/package.mk diff --git a/package/libs/libbsd/patches/001-fix-libpath.patch b/package/libs/libbsd/patches/001-fix-libpath.patch new file mode 100644 index 00000000000..ca240702496 --- /dev/null +++ b/package/libs/libbsd/patches/001-fix-libpath.patch @@ -0,0 +1,13 @@ +do not use host path to fix cross compiling + +--- a/src/Makefile.am ++++ b/src/Makefile.am +@@ -160,7 +160,7 @@ + (echo '/* GNU ld script'; \ + echo ' * The MD5 functions are provided by the libmd library. */'; \ + cat format.ld; \ +- echo "GROUP($(runtimelibdir)/$$soname AS_NEEDED($(MD5_LIBS)))"; \ ++ echo "GROUP($$soname AS_NEEDED($(MD5_LIBS)))"; \ + )>$(DESTDIR)$(libdir)/libbsd.so + else + if [ "$(libdir)" != "$(runtimelibdir)" ]; then \ From 5db4fbad4f55acf1a1bcc8b9685e2581789226a5 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Sun, 17 Jul 2022 13:26:14 +0200 Subject: [PATCH 31/72] rules: drop -Wno-error additional flags from default TARGET_CFLAGS We currently enable -Wno-error=unused-but-set-variable and -Wno-error=unused-result by default on every compile package. While this is (relatively) unharmful, we should follow other project direction and starts enforcing good code quality. For example the linux kernel recently started to enforce Wall by default and clean code is mandatory for inclusion. Drop for good these flags and and make it mandatory to correctly handle return values at least with a warning log if they are not strictly error condition. Signed-off-by: Christian Marangi --- rules.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rules.mk b/rules.mk index e17852e0217..d53f673d425 100644 --- a/rules.mk +++ b/rules.mk @@ -184,7 +184,7 @@ ifndef DUMP -include $(TOOLCHAIN_DIR)/info.mk export GCC_HONOUR_COPTS:=0 TARGET_CROSS:=$(if $(TARGET_CROSS),$(TARGET_CROSS),$(OPTIMIZE_FOR_CPU)-openwrt-linux$(if $(TARGET_SUFFIX),-$(TARGET_SUFFIX))-) - TARGET_CFLAGS+= -fhonour-copts -Wno-error=unused-but-set-variable -Wno-error=unused-result + TARGET_CFLAGS+= -fhonour-copts TARGET_CPPFLAGS+= -I$(TOOLCHAIN_DIR)/usr/include ifeq ($(CONFIG_USE_MUSL),y) TARGET_CPPFLAGS+= -I$(TOOLCHAIN_DIR)/include/fortify From 73dca49f355fe10d1d5e629b0df584b03a1849b3 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Mon, 26 Dec 2022 13:58:47 +0100 Subject: [PATCH 32/72] uhttpd: update to latest Git HEAD 2397755 client: fix incorrectly emitting HTTP 413 for certain content lengths Signed-off-by: Hauke Mehrtens --- package/network/services/uhttpd/Makefile | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/package/network/services/uhttpd/Makefile b/package/network/services/uhttpd/Makefile index d6a5a271819..55ca3f68189 100644 --- a/package/network/services/uhttpd/Makefile +++ b/package/network/services/uhttpd/Makefile @@ -8,13 +8,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=uhttpd -PKG_RELEASE:=3 +PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/uhttpd.git -PKG_SOURCE_DATE:=2022-08-12 -PKG_SOURCE_VERSION:=e3395cd90bed9b7b9fc319e79528fedcc0d947fe -PKG_MIRROR_HASH:=14e9df9f85c406b8abbb14427e5f678383782500c549d842c0481cd954fc4ea3 +PKG_SOURCE_DATE:=2022-10-31 +PKG_SOURCE_VERSION:=23977554d9694d025eada50a5547e99ee1be7838 +PKG_MIRROR_HASH:=e546fd57d0d0be6a51e2aeb5797febe8c89d2bba61b26c930ecb0616d5f6ace9 PKG_MAINTAINER:=Felix Fietkau PKG_LICENSE:=ISC From fb15cb4ce9559021d463b5cb3816d8a9eeb8f3f9 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Wed, 21 Dec 2022 23:32:23 +0100 Subject: [PATCH 33/72] iproute2: Fix build with GCC 12 and glibc 2.36 This fixes the detection of name_to_handle_at() when GCC 12 and glibc 2.36 are used. Signed-off-by: Hauke Mehrtens --- ...-configure-Remove-include-sys-stat.h.patch | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 package/network/utils/iproute2/patches/320-configure-Remove-include-sys-stat.h.patch diff --git a/package/network/utils/iproute2/patches/320-configure-Remove-include-sys-stat.h.patch b/package/network/utils/iproute2/patches/320-configure-Remove-include-sys-stat.h.patch new file mode 100644 index 00000000000..02bb20297d3 --- /dev/null +++ b/package/network/utils/iproute2/patches/320-configure-Remove-include-sys-stat.h.patch @@ -0,0 +1,43 @@ +From 3a3a2f6be704c970938eb8dac4eb0118f1c2fb06 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Wed, 21 Dec 2022 23:26:28 +0100 +Subject: [PATCH iproute2 v2] configure: Remove include + +The check_name_to_handle_at() function in the configure script is +including sys/stat.h. This include fails with glibc 2.36 like this: +```` +In file included from /linux-5.15.84/include/uapi/linux/stat.h:5, + from /toolchain-x86_64_gcc-12.2.0_glibc/include/bits/statx.h:31, + from /toolchain-x86_64_gcc-12.2.0_glibc/include/sys/stat.h:465, + from config.YExfMc/name_to_handle_at_test.c:3: +/linux-5.15.84/include/uapi/linux/types.h:10:2: warning: #warning "Attempt to use kernel headers from user space, see https://kernelnewbies.org/KernelHeaders" [-Wcpp] + 10 | #warning "Attempt to use kernel headers from user space, see https://kernelnewbies.org/KernelHeaders" + | ^~~~~~~ +In file included from /linux-5.15.84/include/uapi/linux/posix_types.h:5, + from /linux-5.15.84/include/uapi/linux/types.h:14: +/linux-5.15.84/include/uapi/linux/stddef.h:5:10: fatal error: linux/compiler_types.h: No such file or directory + 5 | #include + | ^~~~~~~~~~~~~~~~~~~~~~~~ +compilation terminated. +```` + +Just removing the include works, the manpage of name_to_handle_at() says +only fcntl.h is needed. + +Fixes: c5b72cc56bf8 ("lib/fs: fix issue when {name,open}_to_handle_at() is not implemented") +Tested-by: Heiko Thiery +Signed-off-by: Hauke Mehrtens +--- + configure | 1 - + 1 file changed, 1 deletion(-) + +--- a/configure ++++ b/configure +@@ -215,7 +215,6 @@ check_name_to_handle_at() + cat >$TMPDIR/name_to_handle_at_test.c < +-#include + #include + int main(int argc, char **argv) + { From c94ca63ed4eed9aa92dc2fa4d61235b6845b42d3 Mon Sep 17 00:00:00 2001 From: Jan Hoffmann Date: Sat, 17 Dec 2022 21:39:40 +0100 Subject: [PATCH 34/72] realtek: don't set L2LEARNING flag in rtl83xx TX header As learning for the CPU port is now disabled globally, the bit in the TX header doesn't have any effect anymore. Remove it to make the header consistent with the global configuration. Originally, this change was intended to be applied before commit eb456aedfe24 ("realtek: use assisted learning on CPU port"), which is why the commit message incorrectly mentions that the TX header already disables learning. The reason for disabling learning on the CPU port in the first place is that it doesn't work correctly when packets are trapped to the CPU and then forwarded by the CPU to other ports. In that case, the switch would incorrectly learn the CPU port as source. An example that triggered this issue are Multicast Listener Reports and IGMP membership reports. Signed-off-by: Jan Hoffmann --- .../realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c | 4 ++-- .../realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c index 166e49e139d..32de5cc5549 100644 --- a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c +++ b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c @@ -96,7 +96,7 @@ struct notify_b { static void rtl838x_create_tx_header(struct p_hdr *h, unsigned int dest_port, int prio) { // cpu_tag[0] is reserved on the RTL83XX SoCs - h->cpu_tag[1] = 0x0401; // BIT 10: RTL8380_CPU_TAG, BIT0: L2LEARNING on + h->cpu_tag[1] = 0x0400; // BIT 10: RTL8380_CPU_TAG h->cpu_tag[2] = 0x0200; // Set only AS_DPM, to enable DPM settings below h->cpu_tag[3] = 0x0000; h->cpu_tag[4] = BIT(dest_port) >> 16; @@ -111,7 +111,7 @@ static void rtl839x_create_tx_header(struct p_hdr *h, unsigned int dest_port, in { // cpu_tag[0] is reserved on the RTL83XX SoCs h->cpu_tag[1] = 0x0100; // RTL8390_CPU_TAG marker - h->cpu_tag[2] = BIT(4) | BIT(7); /* AS_DPM (4) and L2LEARNING (7) flags */ + h->cpu_tag[2] = BIT(4); /* AS_DPM flag */ h->cpu_tag[3] = h->cpu_tag[4] = h->cpu_tag[5] = 0; // h->cpu_tag[1] |= BIT(1) | BIT(0); // Bypass filter 1/2 if (dest_port >= 32) { diff --git a/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.c b/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.c index 166e49e139d..32de5cc5549 100644 --- a/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.c +++ b/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.c @@ -96,7 +96,7 @@ struct notify_b { static void rtl838x_create_tx_header(struct p_hdr *h, unsigned int dest_port, int prio) { // cpu_tag[0] is reserved on the RTL83XX SoCs - h->cpu_tag[1] = 0x0401; // BIT 10: RTL8380_CPU_TAG, BIT0: L2LEARNING on + h->cpu_tag[1] = 0x0400; // BIT 10: RTL8380_CPU_TAG h->cpu_tag[2] = 0x0200; // Set only AS_DPM, to enable DPM settings below h->cpu_tag[3] = 0x0000; h->cpu_tag[4] = BIT(dest_port) >> 16; @@ -111,7 +111,7 @@ static void rtl839x_create_tx_header(struct p_hdr *h, unsigned int dest_port, in { // cpu_tag[0] is reserved on the RTL83XX SoCs h->cpu_tag[1] = 0x0100; // RTL8390_CPU_TAG marker - h->cpu_tag[2] = BIT(4) | BIT(7); /* AS_DPM (4) and L2LEARNING (7) flags */ + h->cpu_tag[2] = BIT(4); /* AS_DPM flag */ h->cpu_tag[3] = h->cpu_tag[4] = h->cpu_tag[5] = 0; // h->cpu_tag[1] |= BIT(1) | BIT(0); // Bypass filter 1/2 if (dest_port >= 32) { From 9aa123d778e2631c2698a60ceeec610a14e1343b Mon Sep 17 00:00:00 2001 From: Jan Hoffmann Date: Sat, 17 Dec 2022 21:45:41 +0100 Subject: [PATCH 35/72] realtek: simplify log messages in rtl83xx_mdio_probe This function currently prints three messages for every switch port at KERN_INFO level. This takes a considerable amount of time during bootup and can even trigger an external watchdog. Replace these log messages by a single one at KERN_DEBUG level. Signed-off-by: Jan Hoffmann --- .../realtek/files-5.10/drivers/net/dsa/rtl83xx/common.c | 8 +------- .../realtek/files-5.15/drivers/net/dsa/rtl83xx/common.c | 8 +------- 2 files changed, 2 insertions(+), 14 deletions(-) diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/common.c b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/common.c index e86ff9ccdfe..63c024c81e8 100644 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/common.c +++ b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/common.c @@ -323,7 +323,6 @@ static int __init rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv) if (of_property_read_u32(dn, "reg", &pn)) continue; - pr_info("%s found port %d\n", __func__, pn); phy_node = of_parse_phandle(dn, "phy-handle", 0); if (!phy_node) { if (pn != priv->cpu_port) @@ -331,14 +330,9 @@ static int __init rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv) continue; } - pr_info("%s port %d has phandle\n", __func__, pn); if (of_property_read_u32(phy_node, "sds", &priv->ports[pn].sds_num)) priv->ports[pn].sds_num = -1; - else { - pr_info("%s sds port %d is %d\n", __func__, pn, - priv->ports[pn].sds_num); - } - pr_info("%s port %d has SDS\n", __func__, priv->ports[pn].sds_num); + pr_debug("%s port %d has SDS %d\n", __func__, pn, priv->ports[pn].sds_num); if (of_get_phy_mode(dn, &interface)) interface = PHY_INTERFACE_MODE_NA; diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/common.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/common.c index b5afed0ef55..8b0b55d8919 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/common.c +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/common.c @@ -323,7 +323,6 @@ static int __init rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv) if (of_property_read_u32(dn, "reg", &pn)) continue; - pr_info("%s found port %d\n", __func__, pn); phy_node = of_parse_phandle(dn, "phy-handle", 0); if (!phy_node) { if (pn != priv->cpu_port) @@ -331,14 +330,9 @@ static int __init rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv) continue; } - pr_info("%s port %d has phandle\n", __func__, pn); if (of_property_read_u32(phy_node, "sds", &priv->ports[pn].sds_num)) priv->ports[pn].sds_num = -1; - else { - pr_info("%s sds port %d is %d\n", __func__, pn, - priv->ports[pn].sds_num); - } - pr_info("%s port %d has SDS\n", __func__, priv->ports[pn].sds_num); + pr_debug("%s port %d has SDS %d\n", __func__, pn, priv->ports[pn].sds_num); if (of_get_phy_mode(dn, &interface)) interface = PHY_INTERFACE_MODE_NA; From ae0a3f88ac335801f17035504ba572d14205787a Mon Sep 17 00:00:00 2001 From: Jan Hoffmann Date: Sat, 17 Dec 2022 21:45:42 +0100 Subject: [PATCH 36/72] realtek: restructure rtl_table_read/write These two functions are identical apart from writing different values to the read/write bit. Create a new function rtl_table_exec to reduce code duplication. Also replace the unbounded busy-waiting loop. The new implementation may sleep, but as the hardware typically responds before the first poll, any callers doing many table accesses still need to make sure not to block other kernel tasks themselves. So far, polling timeout errors are only handled by logging an error, but a return value is added to allow proper handling in the future. Signed-off-by: Jan Hoffmann --- .../drivers/net/dsa/rtl83xx/common.c | 41 +++++++++++++------ .../drivers/net/dsa/rtl83xx/rtl83xx.h | 4 +- .../drivers/net/dsa/rtl83xx/common.c | 41 +++++++++++++------ .../drivers/net/dsa/rtl83xx/rtl83xx.h | 4 +- 4 files changed, 62 insertions(+), 28 deletions(-) diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/common.c b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/common.c index 63c024c81e8..15e6ed09269 100644 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/common.c +++ b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/common.c @@ -121,28 +121,45 @@ void rtl_table_release(struct table_reg *r) // pr_info("Unlock done\n"); } +static int rtl_table_exec(struct table_reg *r, bool is_write, int idx) +{ + int ret = 0; + u32 cmd, val; + + /* Read/write bit has inverted meaning on RTL838x */ + if (r->rmode) + cmd = is_write ? 0 : BIT(r->c_bit); + else + cmd = is_write ? BIT(r->c_bit) : 0; + + cmd |= BIT(r->c_bit + 1); /* Execute bit */ + cmd |= r->tbl << r->t_bit; /* Table type */ + cmd |= idx & (BIT(r->t_bit) - 1); /* Index */ + + sw_w32(cmd, r->addr); + + ret = readx_poll_timeout(sw_r32, r->addr, val, + !(val & BIT(r->c_bit + 1)), 20, 10000); + if (ret) + pr_err("%s: timeout\n", __func__); + + return ret; +} + /* * Reads table index idx into the data registers of the table */ -void rtl_table_read(struct table_reg *r, int idx) +int rtl_table_read(struct table_reg *r, int idx) { - u32 cmd = r->rmode ? BIT(r->c_bit) : 0; - - cmd |= BIT(r->c_bit + 1) | (r->tbl << r->t_bit) | (idx & (BIT(r->t_bit) - 1)); - sw_w32(cmd, r->addr); - do { } while (sw_r32(r->addr) & BIT(r->c_bit + 1)); + return rtl_table_exec(r, false, idx); } /* * Writes the content of the table data registers into the table at index idx */ -void rtl_table_write(struct table_reg *r, int idx) +int rtl_table_write(struct table_reg *r, int idx) { - u32 cmd = r->rmode ? 0 : BIT(r->c_bit); - - cmd |= BIT(r->c_bit + 1) | (r->tbl << r->t_bit) | (idx & (BIT(r->t_bit) - 1)); - sw_w32(cmd, r->addr); - do { } while (sw_r32(r->addr) & BIT(r->c_bit + 1)); + return rtl_table_exec(r, true, idx); } /* diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl83xx.h b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl83xx.h index 107016469c6..485d0e8a7e9 100644 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl83xx.h +++ b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl83xx.h @@ -67,8 +67,8 @@ typedef enum { void rtl_table_init(void); struct table_reg *rtl_table_get(rtl838x_tbl_reg_t r, int t); void rtl_table_release(struct table_reg *r); -void rtl_table_read(struct table_reg *r, int idx); -void rtl_table_write(struct table_reg *r, int idx); +int rtl_table_read(struct table_reg *r, int idx); +int rtl_table_write(struct table_reg *r, int idx); inline u16 rtl_table_data(struct table_reg *r, int i); inline u32 rtl_table_data_r(struct table_reg *r, int i); inline void rtl_table_data_w(struct table_reg *r, u32 v, int i); diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/common.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/common.c index 8b0b55d8919..fb359dc4faa 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/common.c +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/common.c @@ -121,28 +121,45 @@ void rtl_table_release(struct table_reg *r) // pr_info("Unlock done\n"); } +static int rtl_table_exec(struct table_reg *r, bool is_write, int idx) +{ + int ret = 0; + u32 cmd, val; + + /* Read/write bit has inverted meaning on RTL838x */ + if (r->rmode) + cmd = is_write ? 0 : BIT(r->c_bit); + else + cmd = is_write ? BIT(r->c_bit) : 0; + + cmd |= BIT(r->c_bit + 1); /* Execute bit */ + cmd |= r->tbl << r->t_bit; /* Table type */ + cmd |= idx & (BIT(r->t_bit) - 1); /* Index */ + + sw_w32(cmd, r->addr); + + ret = readx_poll_timeout(sw_r32, r->addr, val, + !(val & BIT(r->c_bit + 1)), 20, 10000); + if (ret) + pr_err("%s: timeout\n", __func__); + + return ret; +} + /* * Reads table index idx into the data registers of the table */ -void rtl_table_read(struct table_reg *r, int idx) +int rtl_table_read(struct table_reg *r, int idx) { - u32 cmd = r->rmode ? BIT(r->c_bit) : 0; - - cmd |= BIT(r->c_bit + 1) | (r->tbl << r->t_bit) | (idx & (BIT(r->t_bit) - 1)); - sw_w32(cmd, r->addr); - do { } while (sw_r32(r->addr) & BIT(r->c_bit + 1)); + return rtl_table_exec(r, false, idx); } /* * Writes the content of the table data registers into the table at index idx */ -void rtl_table_write(struct table_reg *r, int idx) +int rtl_table_write(struct table_reg *r, int idx) { - u32 cmd = r->rmode ? 0 : BIT(r->c_bit); - - cmd |= BIT(r->c_bit + 1) | (r->tbl << r->t_bit) | (idx & (BIT(r->t_bit) - 1)); - sw_w32(cmd, r->addr); - do { } while (sw_r32(r->addr) & BIT(r->c_bit + 1)); + return rtl_table_exec(r, true, idx); } /* diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl83xx.h b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl83xx.h index 107016469c6..485d0e8a7e9 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl83xx.h +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl83xx.h @@ -67,8 +67,8 @@ typedef enum { void rtl_table_init(void); struct table_reg *rtl_table_get(rtl838x_tbl_reg_t r, int t); void rtl_table_release(struct table_reg *r); -void rtl_table_read(struct table_reg *r, int idx); -void rtl_table_write(struct table_reg *r, int idx); +int rtl_table_read(struct table_reg *r, int idx); +int rtl_table_write(struct table_reg *r, int idx); inline u16 rtl_table_data(struct table_reg *r, int i); inline u32 rtl_table_data_r(struct table_reg *r, int i); inline void rtl_table_data_w(struct table_reg *r, u32 v, int i); From 2c40359c5c12621fa386efca3139ea523db6d39f Mon Sep 17 00:00:00 2001 From: Jan Hoffmann Date: Sat, 17 Dec 2022 21:45:43 +0100 Subject: [PATCH 37/72] realtek: add cond_resched to loops accessing the FDB table A full loop accessing all FDB entries can take several milliseconds (on RTL839x about 20 ms), so give other kernel tasks a chance to run. This is especially important for rtl83xx_port_fdb_dump which is itself called in a loop for all ports by the kernel. Signed-off-by: Jan Hoffmann --- .../linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/debugfs.c | 3 +++ target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c | 3 +++ .../linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/debugfs.c | 3 +++ target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/dsa.c | 3 +++ 4 files changed, 12 insertions(+) diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/debugfs.c b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/debugfs.c index 9a7c7714c64..3c935f629af 100644 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/debugfs.c +++ b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/debugfs.c @@ -343,6 +343,9 @@ static int l2_table_show(struct seq_file *m, void *v) seq_printf(m, "Hash table bucket %d index %d ", bucket, index); l2_table_print_entry(m, priv, &e); + + if (!((i + 1) % 64)) + cond_resched(); } for (i = 0; i < 64; i++) { diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c index 6eea0dc9367..63461ff5734 100644 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c +++ b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c @@ -1728,6 +1728,9 @@ static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port, if (e.port == port || e.port == RTL930X_PORT_IGNORE) cb(e.mac, e.vid, e.is_static, data); + + if (!((i + 1) % 64)) + cond_resched(); } for (i = 0; i < 64; i++) { diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/debugfs.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/debugfs.c index 9a7c7714c64..3c935f629af 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/debugfs.c +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/debugfs.c @@ -343,6 +343,9 @@ static int l2_table_show(struct seq_file *m, void *v) seq_printf(m, "Hash table bucket %d index %d ", bucket, index); l2_table_print_entry(m, priv, &e); + + if (!((i + 1) % 64)) + cond_resched(); } for (i = 0; i < 64; i++) { diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/dsa.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/dsa.c index 9281e08d33e..3e71813112b 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/dsa.c +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/dsa.c @@ -1725,6 +1725,9 @@ static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port, if (e.port == port || e.port == RTL930X_PORT_IGNORE) cb(e.mac, e.vid, e.is_static, data); + + if (!((i + 1) % 64)) + cond_resched(); } for (i = 0; i < 64; i++) { From 758c88b969639d0e6b684669d2e54dd1be3102f4 Mon Sep 17 00:00:00 2001 From: Olliver Schinagl Date: Tue, 30 Aug 2022 21:25:25 +0200 Subject: [PATCH 38/72] realtek: Whitespace and codestyle cleanup Fix some ugly whitepsaces and codestyle issues around the realtek sources. While this is by no means perfect, it catches what it caught. Signed-off-by: Olliver Schinagl --- .../bindings/realtek,otto-timer.yaml | 2 +- .../include/asm/mach-rtl838x/mach-rtl83xx.h | 4 +- .../arch/mips/kernel/cevt-rtl9300.c | 6 +- .../drivers/clk/realtek/clk-rtl838x-sram.S | 1 - .../drivers/clk/realtek/clk-rtl839x-sram.S | 1 - .../drivers/clk/realtek/clk-rtl83xx.c | 6 +- .../files-5.15/drivers/gpio/gpio-rtl8231.c | 15 +- .../drivers/i2c/busses/i2c-rtl9300.c | 8 +- .../drivers/i2c/muxes/i2c-mux-rtl9300.c | 8 +- .../drivers/net/dsa/rtl83xx/Kconfig | 1 - .../drivers/net/dsa/rtl83xx/common.c | 102 +++-- .../drivers/net/dsa/rtl83xx/debugfs.c | 2 +- .../files-5.15/drivers/net/dsa/rtl83xx/dsa.c | 75 ++-- .../files-5.15/drivers/net/dsa/rtl83xx/qos.c | 50 +-- .../drivers/net/dsa/rtl83xx/rtl838x.c | 153 +++---- .../drivers/net/dsa/rtl83xx/rtl838x.h | 34 +- .../drivers/net/dsa/rtl83xx/rtl839x.c | 133 +++--- .../drivers/net/dsa/rtl83xx/rtl83xx.h | 1 - .../drivers/net/dsa/rtl83xx/rtl930x.c | 259 ++++++----- .../drivers/net/dsa/rtl83xx/rtl931x.c | 133 +++--- .../files-5.15/drivers/net/dsa/rtl83xx/tc.c | 16 +- .../drivers/net/ethernet/rtl838x_eth.c | 156 +++---- .../drivers/net/ethernet/rtl838x_eth.h | 4 +- .../files-5.15/drivers/net/phy/rtl83xx-phy.c | 405 +++++++++--------- .../files-5.15/drivers/net/phy/rtl83xx-phy.h | 2 +- 25 files changed, 767 insertions(+), 810 deletions(-) diff --git a/target/linux/realtek/files-5.15/Documentation/devicetree/bindings/realtek,otto-timer.yaml b/target/linux/realtek/files-5.15/Documentation/devicetree/bindings/realtek,otto-timer.yaml index b508362a728..40e834e3775 100644 --- a/target/linux/realtek/files-5.15/Documentation/devicetree/bindings/realtek,otto-timer.yaml +++ b/target/linux/realtek/files-5.15/Documentation/devicetree/bindings/realtek,otto-timer.yaml @@ -17,7 +17,7 @@ description: | RTL83XX: 0x3100, 0x3110, 0x3120, 0x3130, 0x3140 RTL93XX: 0x3200, 0x3210, 0x3220, 0x3230, 0x3240 - + properties: compatible: items: diff --git a/target/linux/realtek/files-5.15/arch/mips/include/asm/mach-rtl838x/mach-rtl83xx.h b/target/linux/realtek/files-5.15/arch/mips/include/asm/mach-rtl838x/mach-rtl83xx.h index d95e5fb0987..aa2d918efbc 100644 --- a/target/linux/realtek/files-5.15/arch/mips/include/asm/mach-rtl838x/mach-rtl83xx.h +++ b/target/linux/realtek/files-5.15/arch/mips/include/asm/mach-rtl838x/mach-rtl83xx.h @@ -350,9 +350,7 @@ #define RTL931X_MAC_L2_GLOBAL_CTRL2 (0x1358) #define RTL931X_MAC_L2_GLOBAL_CTRL1 (0x5548) -/* - * Switch interrupts - */ +/* Switch interrupts */ #define RTL838X_IMR_GLB (0x1100) #define RTL838X_IMR_PORT_LINK_STS_CHG (0x1104) #define RTL838X_ISR_GLB_SRC (0x1148) diff --git a/target/linux/realtek/files-5.15/arch/mips/kernel/cevt-rtl9300.c b/target/linux/realtek/files-5.15/arch/mips/kernel/cevt-rtl9300.c index 1c8c30de5d5..447e754f203 100644 --- a/target/linux/realtek/files-5.15/arch/mips/kernel/cevt-rtl9300.c +++ b/target/linux/realtek/files-5.15/arch/mips/kernel/cevt-rtl9300.c @@ -11,7 +11,7 @@ #include -/* +/* * Timer registers * the RTL9300/9310 SoCs have 6 timers, each register block 0x10 apart */ @@ -59,6 +59,7 @@ static irqreturn_t rtl9300_timer_interrupt(int irq, void *dev_id) writel(v, rtl_clk->base + RTL9300_TC_INT); clk->event_handler(clk); + return IRQ_HANDLED; } @@ -101,6 +102,7 @@ static int rtl9300_state_periodic(struct clock_event_device *clk) rtl9300_clock_stop(base); writel(RTL9300_CLOCK_RATE / HZ, base + RTL9300_TC_DATA); rtl9300_timer_start(base, TIMER_MODE_REPEAT); + return 0; } @@ -112,6 +114,7 @@ static int rtl9300_state_oneshot(struct clock_event_device *clk) rtl9300_clock_stop(base); writel(RTL9300_CLOCK_RATE / HZ, base + RTL9300_TC_DATA); rtl9300_timer_start(base, TIMER_MODE_ONCE); + return 0; } @@ -121,6 +124,7 @@ static int rtl9300_shutdown(struct clock_event_device *clk) pr_debug("------------- rtl9300_shutdown %08x\n", (u32)base); rtl9300_clock_stop(base); + return 0; } diff --git a/target/linux/realtek/files-5.15/drivers/clk/realtek/clk-rtl838x-sram.S b/target/linux/realtek/files-5.15/drivers/clk/realtek/clk-rtl838x-sram.S index 527436bbab4..24317231330 100644 --- a/target/linux/realtek/files-5.15/drivers/clk/realtek/clk-rtl838x-sram.S +++ b/target/linux/realtek/files-5.15/drivers/clk/realtek/clk-rtl838x-sram.S @@ -147,4 +147,3 @@ wait_cpu: .globl rtcl_838x_dram_size rtcl_838x_dram_size: .word .-rtcl_838x_dram_start - diff --git a/target/linux/realtek/files-5.15/drivers/clk/realtek/clk-rtl839x-sram.S b/target/linux/realtek/files-5.15/drivers/clk/realtek/clk-rtl839x-sram.S index cd43dfaabd0..eb44cd90f14 100644 --- a/target/linux/realtek/files-5.15/drivers/clk/realtek/clk-rtl839x-sram.S +++ b/target/linux/realtek/files-5.15/drivers/clk/realtek/clk-rtl839x-sram.S @@ -139,4 +139,3 @@ wait_pllclock: .globl rtcl_839x_dram_size rtcl_839x_dram_size: .word .-rtcl_839x_dram_start - diff --git a/target/linux/realtek/files-5.15/drivers/clk/realtek/clk-rtl83xx.c b/target/linux/realtek/files-5.15/drivers/clk/realtek/clk-rtl83xx.c index 9b8183fbebd..ce5c166bcad 100644 --- a/target/linux/realtek/files-5.15/drivers/clk/realtek/clk-rtl83xx.c +++ b/target/linux/realtek/files-5.15/drivers/clk/realtek/clk-rtl83xx.c @@ -467,9 +467,9 @@ static long rtcl_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long */ #define RTCL_SRAM_FUNC(SOC, PBASE, FN) ({ \ - rtcl_##SOC##_sram_##FN = ((void *)&rtcl_##SOC##_dram_##FN \ - - (void *)&rtcl_##SOC##_dram_start) \ - + (void *)PBASE; }) + rtcl_##SOC##_sram_##FN = ((void *)&rtcl_##SOC##_dram_##FN - \ + (void *)&rtcl_##SOC##_dram_start) + \ + (void *)PBASE; }) static const struct clk_ops rtcl_clk_ops = { .set_rate = rtcl_set_rate, diff --git a/target/linux/realtek/files-5.15/drivers/gpio/gpio-rtl8231.c b/target/linux/realtek/files-5.15/drivers/gpio/gpio-rtl8231.c index 368c4fa60fb..0b0d0390593 100644 --- a/target/linux/realtek/files-5.15/drivers/gpio/gpio-rtl8231.c +++ b/target/linux/realtek/files-5.15/drivers/gpio/gpio-rtl8231.c @@ -55,7 +55,7 @@ static u32 rtl8231_read(struct rtl8231_gpios *gpios, u32 reg) if (n >= USEC_TIMEOUT) return 0x80000000; - + pr_debug("%s: %x, %x, %x\n", __func__, gpios->smi_bus_id, reg, (t & 0xffff0000) >> 16); @@ -127,6 +127,7 @@ static int rtl8231_pin_dir(struct rtl8231_gpios *gpios, u32 gpio, u32 dir) rtl8231_write(gpios, pin_dir_addr, v); gpios->reg_shadow[pin_dir_addr] = v; gpios->reg_cached |= 1 << pin_dir_addr; + return 0; } @@ -150,6 +151,7 @@ static int rtl8231_pin_dir_get(struct rtl8231_gpios *gpios, u32 gpio, u32 *dir) *dir = 1; else *dir = 0; + return 0; } @@ -166,6 +168,7 @@ static int rtl8231_pin_set(struct rtl8231_gpios *gpios, u32 gpio, u32 data) rtl8231_write(gpios, RTL8231_GPIO_DATA(gpio), v); gpios->reg_shadow[RTL8231_GPIO_DATA(gpio)] = v; gpios->reg_cached |= 1 << RTL8231_GPIO_DATA(gpio); + return 0; } @@ -179,6 +182,7 @@ static int rtl8231_pin_get(struct rtl8231_gpios *gpios, u32 gpio, u16 *state) } *state = v & 0xffff; + return 0; } @@ -191,6 +195,7 @@ static int rtl8231_direction_input(struct gpio_chip *gc, unsigned int offset) mutex_lock(&miim_lock); err = rtl8231_pin_dir(gpios, offset, 1); mutex_unlock(&miim_lock); + return err; } @@ -203,8 +208,10 @@ static int rtl8231_direction_output(struct gpio_chip *gc, unsigned int offset, i mutex_lock(&miim_lock); err = rtl8231_pin_dir(gpios, offset, 0); mutex_unlock(&miim_lock); + if (!err) err = rtl8231_pin_set(gpios, offset, value); + return err; } @@ -217,6 +224,7 @@ static int rtl8231_get_direction(struct gpio_chip *gc, unsigned int offset) mutex_lock(&miim_lock); rtl8231_pin_dir_get(gpios, offset, &v); mutex_unlock(&miim_lock); + return v; } @@ -228,8 +236,10 @@ static int rtl8231_gpio_get(struct gpio_chip *gc, unsigned int offset) mutex_lock(&miim_lock); rtl8231_pin_get(gpios, offset, &state); mutex_unlock(&miim_lock); + if (state & (1 << (offset % 16))) return 1; + return 0; } @@ -337,8 +347,7 @@ static int rtl8231_gpio_probe(struct platform_device *pdev) gpios->gc.get = rtl8231_gpio_get; gpios->gc.get_direction = rtl8231_get_direction; - err = devm_gpiochip_add_data(dev, &gpios->gc, gpios); - return err; + return devm_gpiochip_add_data(dev, &gpios->gc, gpios); } static struct platform_driver rtl8231_gpio_driver = { diff --git a/target/linux/realtek/files-5.15/drivers/i2c/busses/i2c-rtl9300.c b/target/linux/realtek/files-5.15/drivers/i2c/busses/i2c-rtl9300.c index 382dfd40109..a1b5f669ba7 100644 --- a/target/linux/realtek/files-5.15/drivers/i2c/busses/i2c-rtl9300.c +++ b/target/linux/realtek/files-5.15/drivers/i2c/busses/i2c-rtl9300.c @@ -23,7 +23,7 @@ struct i2c_drv_data { void (*config_io)(struct rtl9300_i2c *i2c, int scl_num, int sda_num); u32 mst2_offset; }; - + DEFINE_MUTEX(i2c_lock); static void rtl9300_i2c_reg_addr_set(struct rtl9300_i2c *i2c, u32 reg, u16 len) @@ -347,7 +347,7 @@ static int rtl9300_i2c_probe(struct platform_device *pdev) int ret = 0; pr_info("%s probing I2C adapter\n", __func__); - + if (!node) { dev_err(i2c->dev, "No DT found\n"); return -EINVAL; @@ -376,7 +376,7 @@ static int rtl9300_i2c_probe(struct platform_device *pdev) case I2C_MAX_STANDARD_MODE_FREQ: i2c->bus_freq = RTL9300_I2C_STD_FREQ; break; - + case I2C_MAX_FAST_MODE_FREQ: i2c->bus_freq = RTL9300_I2C_FAST_FREQ; break; @@ -451,7 +451,7 @@ struct i2c_drv_data rtl9300_i2c_drv_data = { }; struct i2c_drv_data rtl9310_i2c_drv_data = { - .scl0_pin = 13, + .scl0_pin = 13, .scl1_pin = 14, .sda0_pin = 0, .read = rtl9310_i2c_read, diff --git a/target/linux/realtek/files-5.15/drivers/i2c/muxes/i2c-mux-rtl9300.c b/target/linux/realtek/files-5.15/drivers/i2c/muxes/i2c-mux-rtl9300.c index 2f45b0a3ccb..b277c125e9c 100644 --- a/target/linux/realtek/files-5.15/drivers/i2c/muxes/i2c-mux-rtl9300.c +++ b/target/linux/realtek/files-5.15/drivers/i2c/muxes/i2c-mux-rtl9300.c @@ -123,8 +123,8 @@ static struct device_node *mux_parent_adapter(struct device *dev, struct rtl9300 if (!parent) return ERR_PTR(-EPROBE_DEFER); - if (!(of_device_is_compatible(parent_np, "realtek,rtl9300-i2c") - || of_device_is_compatible(parent_np, "realtek,rtl9310-i2c"))){ + if (!(of_device_is_compatible(parent_np, "realtek,rtl9300-i2c") || + of_device_is_compatible(parent_np, "realtek,rtl9310-i2c"))){ dev_err(dev, "I2C parent not an RTL9300 I2C controller\n"); return ERR_PTR(-ENODEV); } @@ -147,7 +147,7 @@ struct i2c_mux_data rtl9300_i2c_mux_data = { }; struct i2c_mux_data rtl9310_i2c_mux_data = { - .scl0_pin = 13, + .scl0_pin = 13, .scl1_pin = 14, .sda0_pin = 0, .sda_pins = 16, @@ -177,7 +177,7 @@ static int rtl9300_i2c_mux_probe(struct platform_device *pdev) int ret; pr_info("%s probing I2C adapter\n", __func__); - + if (!node) { dev_err(dev, "No DT found\n"); return -EINVAL; diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/Kconfig b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/Kconfig index 281f08054fa..3124ee8d20c 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/Kconfig +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/Kconfig @@ -5,4 +5,3 @@ config NET_DSA_RTL83XX select NET_DSA_TAG_TRAILER help This driver adds support for Realtek RTL83xx series switching. - diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/common.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/common.c index fb359dc4faa..de75b83e2de 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/common.c +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/common.c @@ -9,8 +9,8 @@ #include #include #include - #include + #include "rtl83xx.h" extern struct rtl83xx_soc_info soc_info; @@ -90,8 +90,7 @@ void rtl_table_init(void) mutex_init(&rtl838x_tbl_regs[i].lock); } -/* - * Request access to table t in table access register r +/* Request access to table t in table access register r * Returns a handle to a lock for that table */ struct table_reg *rtl_table_get(rtl838x_tbl_reg_t r, int t) @@ -108,9 +107,7 @@ struct table_reg *rtl_table_get(rtl838x_tbl_reg_t r, int t) return &rtl838x_tbl_regs[r]; } -/* - * Release a table r, unlock the corresponding lock - */ +/* Release a table r, unlock the corresponding lock */ void rtl_table_release(struct table_reg *r) { if (!r) @@ -146,24 +143,19 @@ static int rtl_table_exec(struct table_reg *r, bool is_write, int idx) return ret; } -/* - * Reads table index idx into the data registers of the table - */ +/* Reads table index idx into the data registers of the table */ int rtl_table_read(struct table_reg *r, int idx) { return rtl_table_exec(r, false, idx); } -/* - * Writes the content of the table data registers into the table at index idx - */ +/* Writes the content of the table data registers into the table at index idx */ int rtl_table_write(struct table_reg *r, int idx) { return rtl_table_exec(r, true, idx); } -/* - * Returns the address of the ith data register of table register r +/* Returns the address of the ith data register of table register r * the address is relative to the beginning of the Switch-IO block at 0xbb000000 */ inline u16 rtl_table_data(struct table_reg *r, int i) @@ -196,7 +188,7 @@ void rtl838x_set_port_reg(u64 set, int reg) u64 rtl838x_get_port_reg(int reg) { - return ((u64) sw_r32(reg)); + return ((u64)sw_r32(reg)); } /* Port register accessor functions for the RTL839x and RTL931X SoCs */ @@ -212,6 +204,7 @@ u64 rtl839x_get_port_reg_be(int reg) v <<= 32; v |= sw_r32(reg + 4); + return v; } @@ -239,6 +232,7 @@ u64 rtl839x_get_port_reg_le(int reg) v <<= 32; v |= sw_r32(reg); + return v; } @@ -254,6 +248,7 @@ int read_phy(u32 port, u32 page, u32 reg, u32 *val) case RTL9310_FAMILY_ID: return rtl931x_read_phy(port, page, reg, val); } + return -1; } @@ -269,6 +264,7 @@ int write_phy(u32 port, u32 page, u32 reg, u32 val) case RTL9310_FAMILY_ID: return rtl931x_write_phy(port, page, reg, val); } + return -1; } @@ -303,8 +299,7 @@ static int __init rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv) bus->name = "rtl838x slave mii"; - /* - * Since the NIC driver is loaded first, we can use the mdio rw functions + /* Since the NIC driver is loaded first, we can use the mdio rw functions * assigned there. */ bus->read = priv->mii_bus->read; @@ -379,21 +374,21 @@ static int __init rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv) priv->ports[pn].phy = PHY_RTL930X_SDS; } } else { - if (of_property_read_bool(phy_node, "phy-is-integrated") - && !of_property_read_bool(phy_node, "sfp")) { + if (of_property_read_bool(phy_node, "phy-is-integrated") && + !of_property_read_bool(phy_node, "sfp")) { priv->ports[pn].phy = PHY_RTL8218B_INT; continue; } } - if (!of_property_read_bool(phy_node, "phy-is-integrated") - && of_property_read_bool(phy_node, "sfp")) { + if (!of_property_read_bool(phy_node, "phy-is-integrated") && + of_property_read_bool(phy_node, "sfp")) { priv->ports[pn].phy = PHY_RTL8214FC; continue; } - if (!of_property_read_bool(phy_node, "phy-is-integrated") - && !of_property_read_bool(phy_node, "sfp")) { + if (!of_property_read_bool(phy_node, "phy-is-integrated") && + !of_property_read_bool(phy_node, "sfp")) { priv->ports[pn].phy = PHY_RTL8218B_EXT; continue; } @@ -419,6 +414,7 @@ static int __init rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv) } pr_debug("%s done\n", __func__); + return 0; } @@ -435,6 +431,7 @@ static int __init rtl83xx_get_l2aging(struct rtl838x_switch_priv *priv) pr_debug("L2 AGING time: %d sec\n", t); pr_debug("Dynamic aging for ports: %x\n", sw_r32(priv->r->l2_port_aging_out)); + return t; } @@ -469,6 +466,7 @@ int rtl83xx_lag_add(struct dsa_switch *ds, int group, int port, struct netdev_la pr_err("%s: Port %d already member of LAG %d.\n", __func__, port, i); return -ENOSPC; } + switch(info->hash_type) { case NETDEV_LAG_HASH_L2: algomsk |= TRUNK_DISTRIBUTION_ALGO_DMAC_BIT; @@ -497,6 +495,7 @@ int rtl83xx_lag_add(struct dsa_switch *ds, int group, int port, struct netdev_la pr_info("%s: Added port %d to LAG %d. Members now %016llx.\n", __func__, port, group, priv->lags_port_members[group]); + return 0; } @@ -526,12 +525,11 @@ int rtl83xx_lag_del(struct dsa_switch *ds, int group, int port) pr_info("%s: Removed port %d from LAG %d. Members now %016llx.\n", __func__, port, group, priv->lags_port_members[group]); + return 0; } -/* - * Allocate a 64 bit octet counter located in the LOG HW table - */ +/* Allocate a 64 bit octet counter located in the LOG HW table */ static int rtl83xx_octet_cntr_alloc(struct rtl838x_switch_priv *priv) { int idx; @@ -550,8 +548,7 @@ static int rtl83xx_octet_cntr_alloc(struct rtl838x_switch_priv *priv) return idx; } -/* - * Allocate a 32-bit packet counter +/* Allocate a 32-bit packet counter * 2 32-bit packet counters share the location of a 64-bit octet counter * Initially there are no free packet counters and 2 new ones need to be freed * by allocating the corresponding octet counter @@ -585,8 +582,7 @@ int rtl83xx_packet_cntr_alloc(struct rtl838x_switch_priv *priv) return idx; } -/* - * Add an L2 nexthop entry for the L3 routing system / PIE forwarding in the SoC +/* Add an L2 nexthop entry for the L3 routing system / PIE forwarding in the SoC * Use VID and MAC in rtl838x_l2_entry to identify either a free slot in the L2 hash table * or mark an existing entry as a nexthop by setting it's nexthop bit * Called from the L3 layer @@ -655,8 +651,7 @@ int rtl83xx_l2_nexthop_add(struct rtl838x_switch_priv *priv, struct rtl83xx_next return 0; } -/* - * Removes a Layer 2 next hop entry in the forwarding database +/* Removes a Layer 2 next hop entry in the forwarding database * If it was static, the entire entry is removed, otherwise the nexthop bit is cleared * and we wait until the entry ages out */ @@ -733,11 +728,11 @@ static int rtl83xx_handle_changeupper(struct rtl838x_switch_priv *priv, out: mutex_unlock(&priv->reg_mutex); + return 0; } -/* - * Is the lower network device a DSA slave network device of our RTL930X-switch? +/* Is the lower network device a DSA slave network device of our RTL930X-switch? * Unfortunately we cannot just follow dev->dsa_prt as this is only set for the * DSA master device. */ @@ -757,6 +752,7 @@ int rtl83xx_port_is_under(const struct net_device * dev, struct rtl838x_switch_p if (priv->ports[i].dp->slave == dev) return i; } + return -EINVAL; } @@ -791,9 +787,7 @@ const static struct rhashtable_params route_ht_params = { .head_offset = offsetof(struct rtl83xx_route, linkage), }; -/* - * Updates an L3 next hop entry in the ROUTING table - */ +/* Updates an L3 next hop entry in the ROUTING table */ static int rtl83xx_l3_nexthop_update(struct rtl838x_switch_priv *priv, __be32 ip_addr, u64 mac) { struct rtl83xx_route *r; @@ -865,6 +859,7 @@ static int rtl83xx_l3_nexthop_update(struct rtl838x_switch_priv *priv, __be32 i } } rcu_read_unlock(); + return 0; } @@ -895,6 +890,7 @@ static int rtl83xx_port_ipv4_resolve(struct rtl838x_switch_priv *priv, } neigh_release(n); + return err; } @@ -970,6 +966,7 @@ static struct rtl83xx_route *rtl83xx_route_alloc(struct rtl838x_switch_priv *pri out_free: kfree(r); + return NULL; } @@ -991,7 +988,8 @@ static struct rtl83xx_route *rtl83xx_host_route_alloc(struct rtl838x_switch_priv } /* We require a unique route ID irrespective of whether it is a prefix or host - * route (on RTL93xx) as we use this ID to associate a DMAC and next-hop entry */ + * route (on RTL93xx) as we use this ID to associate a DMAC and next-hop entry + */ r->id = idx + MAX_ROUTES; r->gw_ip = ip; @@ -1013,6 +1011,7 @@ static struct rtl83xx_route *rtl83xx_host_route_alloc(struct rtl838x_switch_priv out_free: kfree(r); + return NULL; } @@ -1082,8 +1081,7 @@ static int rtl83xx_fib4_del(struct rtl838x_switch_priv *priv, return 0; } -/* - * On the RTL93xx, an L3 termination endpoint MAC address on which the router waits +/* On the RTL93xx, an L3 termination endpoint MAC address on which the router waits * for packets to be routed needs to be allocated. */ static int rtl83xx_alloc_router_mac(struct rtl838x_switch_priv *priv, u64 mac) @@ -1269,6 +1267,7 @@ static int rtl83xx_fib6_add(struct rtl838x_switch_priv *priv, { pr_debug("In %s\n", __func__); // nh->fib_nh_flags |= RTNH_F_OFFLOAD; + return 0; } @@ -1557,14 +1556,14 @@ static int __init rtl83xx_sw_probe(struct platform_device *pdev) */ return err; } + err = dsa_register_switch(priv->ds); if (err) { dev_err(dev, "Error registering switch: %d\n", err); return err; } - /* - * dsa_to_port returns dsa_port from the port list in + /* dsa_to_port returns dsa_port from the port list in * dsa_switch_tree, the tree is built when the switch * is registered by dsa_register_switch */ @@ -1582,19 +1581,19 @@ static int __init rtl83xx_sw_probe(struct platform_device *pdev) switch (priv->family_id) { case RTL8380_FAMILY_ID: err = request_irq(priv->link_state_irq, rtl838x_switch_irq, - IRQF_SHARED, "rtl838x-link-state", priv->ds); + IRQF_SHARED, "rtl838x-link-state", priv->ds); break; case RTL8390_FAMILY_ID: err = request_irq(priv->link_state_irq, rtl839x_switch_irq, - IRQF_SHARED, "rtl839x-link-state", priv->ds); + IRQF_SHARED, "rtl839x-link-state", priv->ds); break; case RTL9300_FAMILY_ID: err = request_irq(priv->link_state_irq, rtl930x_switch_irq, - IRQF_SHARED, "rtl930x-link-state", priv->ds); + IRQF_SHARED, "rtl930x-link-state", priv->ds); break; case RTL9310_FAMILY_ID: err = request_irq(priv->link_state_irq, rtl931x_switch_irq, - IRQF_SHARED, "rtl931x-link-state", priv->ds); + IRQF_SHARED, "rtl931x-link-state", priv->ds); break; } if (err) { @@ -1616,9 +1615,7 @@ static int __init rtl83xx_sw_probe(struct platform_device *pdev) for (i = 0; i < 4; i++) priv->mirror_group_ports[i] = -1; - /* - * Register netdevice event callback to catch changes in link aggregation groups - */ + /* Register netdevice event callback to catch changes in link aggregation groups */ priv->nb.notifier_call = rtl83xx_netdevice_event; if (register_netdevice_notifier(&priv->nb)) { priv->nb.notifier_call = NULL; @@ -1629,8 +1626,7 @@ static int __init rtl83xx_sw_probe(struct platform_device *pdev) // Initialize hash table for L3 routing rhltable_init(&priv->routes, &route_ht_params); - /* - * Register netevent notifier callback to catch notifications about neighboring + /* Register netevent notifier callback to catch notifications about neighboring * changes to update nexthop entries for L3 routing. */ priv->ne_nb.notifier_call = rtl83xx_netevent_event; @@ -1642,8 +1638,7 @@ static int __init rtl83xx_sw_probe(struct platform_device *pdev) priv->fib_nb.notifier_call = rtl83xx_fib_event; - /* - * Register Forwarding Information Base notifier to offload routes where + /* Register Forwarding Information Base notifier to offload routes where * where possible * Only FIBs pointing to our own netdevs are programmed into * the device, so no need to pass a callback. @@ -1680,6 +1675,7 @@ static int rtl83xx_sw_remove(struct platform_device *pdev) { // TODO: pr_debug("Removing platform driver for rtl83xx-sw\n"); + return 0; } diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/debugfs.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/debugfs.c index 3c935f629af..bc7b3f1461d 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/debugfs.c +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/debugfs.c @@ -2,8 +2,8 @@ #include #include - #include + #include "rtl83xx.h" #define RTL838X_DRIVER_NAME "rtl838x" diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/dsa.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/dsa.c index 3e71813112b..f6e1f55a206 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/dsa.c +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/dsa.c @@ -2,14 +2,12 @@ #include #include - #include + #include "rtl83xx.h" - extern struct rtl83xx_soc_info soc_info; - static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv) { mutex_lock(&priv->reg_mutex); @@ -111,9 +109,7 @@ static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds, return DSA_TAG_PROTO_TRAILER; } -/* - * Initialize all VLANS - */ +/* Initialize all VLANS */ static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv) { struct rtl838x_vlan_info info; @@ -218,8 +214,7 @@ static int rtl83xx_setup(struct dsa_switch *ds) rtl83xx_port_set_salrn(priv, priv->cpu_port, false); ds->assisted_learning_on_cpu_port = true; - /* - * Make sure all frames sent to the switch's MAC are trapped to the CPU-port + /* Make sure all frames sent to the switch's MAC are trapped to the CPU-port * 0: FWD, 1: DROP, 2: TRAP2CPU */ if (priv->family_id == RTL8380_FAMILY_ID) @@ -414,8 +409,8 @@ static void rtl93xx_phylink_validate(struct dsa_switch *ds, int port, } // Internal phys of the RTL93xx family provide 10G - if (priv->ports[port].phy_is_integrated - && state->interface == PHY_INTERFACE_MODE_1000BASEX) { + if (priv->ports[port].phy_is_integrated && + state->interface == PHY_INTERFACE_MODE_1000BASEX) { phylink_set(mask, 1000baseX_Full); } else if (priv->ports[port].phy_is_integrated) { phylink_set(mask, 1000baseX_Full); @@ -492,6 +487,7 @@ static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port, state->pause |= MLO_PAUSE_RX; if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port)) state->pause |= MLO_PAUSE_TX; + return 1; } @@ -506,8 +502,7 @@ static int rtl93xx_phylink_mac_link_state(struct dsa_switch *ds, int port, if (port < 0 || port > priv->cpu_port) return -EINVAL; - /* - * On the RTL9300 for at least the RTL8226B PHY, the MAC-side link + /* On the RTL9300 for at least the RTL8226B PHY, the MAC-side link * state needs to be read twice in order to read a correct result. * This would not be necessary for ports connected e.g. to RTL8218D * PHYs. @@ -574,6 +569,7 @@ static int rtl93xx_phylink_mac_link_state(struct dsa_switch *ds, int port, state->pause |= MLO_PAUSE_RX; if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port)) state->pause |= MLO_PAUSE_TX; + return 1; } @@ -988,7 +984,7 @@ static int rtl83xx_mc_group_alloc(struct rtl838x_switch_priv *priv, int port) set_bit(mc_group, priv->mc_group_bm); mc_group++; // We cannot use group 0, as this is used for lookup miss flooding - portmask = BIT_ULL(port) | BIT_ULL(priv->cpu_port); + portmask = BIT_ULL(port) | BIT_ULL(priv->cpu_port); priv->r->write_mcast_pmask(mc_group, portmask); return mc_group; @@ -1134,6 +1130,7 @@ static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port, pr_info("Enabled EEE for port %d\n", port); else pr_info("Disabled EEE for port %d\n", port); + return 0; } @@ -1158,8 +1155,9 @@ static int rtl93xx_get_mac_eee(struct dsa_switch *ds, int port, { struct rtl838x_switch_priv *priv = ds->priv; - e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full - | SUPPORTED_2500baseX_Full; + e->supported = SUPPORTED_100baseT_Full | + SUPPORTED_1000baseT_Full | + SUPPORTED_2500baseX_Full; priv->r->eee_port_ability(priv, e, port); @@ -1175,6 +1173,7 @@ static int rtl83xx_set_ageing_time(struct dsa_switch *ds, unsigned int msec) struct rtl838x_switch_priv *priv = ds->priv; priv->r->set_ageing_time(msec); + return 0; } @@ -1306,7 +1305,7 @@ void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) case BR_STATE_LEARNING: /* 2 */ port_state[index] |= (2 << bit); break; - case BR_STATE_FORWARDING: /* 3*/ + case BR_STATE_FORWARDING: /* 3 */ port_state[index] |= (3 << bit); default: break; @@ -1463,9 +1462,9 @@ static int rtl83xx_vlan_add(struct dsa_switch *ds, int port, priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, vlan->vid); priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, vlan->vid); priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER, - PBVLAN_MODE_UNTAG_AND_PRITAG); + PBVLAN_MODE_UNTAG_AND_PRITAG); priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER, - PBVLAN_MODE_UNTAG_AND_PRITAG); + PBVLAN_MODE_UNTAG_AND_PRITAG); priv->ports[port].pvid = vlan->vid; } @@ -1523,9 +1522,9 @@ static int rtl83xx_vlan_del(struct dsa_switch *ds, int port, priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, 0); priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, 0); priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER, - PBVLAN_MODE_UNTAG_AND_PRITAG); + PBVLAN_MODE_UNTAG_AND_PRITAG); priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER, - PBVLAN_MODE_UNTAG_AND_PRITAG); + PBVLAN_MODE_UNTAG_AND_PRITAG); } /* Get port memberships of this vlan */ priv->r->vlan_tables_read(vlan->vid, &info); @@ -1576,8 +1575,7 @@ static void rtl83xx_setup_l2_mc_entry(struct rtl838x_l2_entry *e, int vid, u64 m u64_to_ether_addr(mac, e->mac); } -/* - * Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops +/* Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops * over the entries in the bucket until either a matching entry is found or an empty slot * Returns the filled in rtl838x_l2_entry and the index in the bucket when an entry was found * when an empty slot was found and must exist is false, the index of the slot is returned @@ -1606,8 +1604,7 @@ static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv *priv, u64 seed return idx; } -/* - * Uses the seed to identify an entry in the CAM by looping over all its entries +/* Uses the seed to identify an entry in the CAM by looping over all its entries * Returns the filled in rtl838x_l2_entry and the index in the CAM when an entry was found * when an empty slot was found the index of the slot is returned * when no slots are available returns -1 @@ -1630,6 +1627,7 @@ static int rtl83xx_find_l2_cam_entry(struct rtl838x_switch_priv *priv, u64 seed, break; } } + return idx; } @@ -1668,8 +1666,10 @@ static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port, } err = -ENOTSUPP; + out: mutex_unlock(&priv->reg_mutex); + return err; } @@ -1703,8 +1703,10 @@ static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port, goto out; } err = -ENOENT; + out: mutex_unlock(&priv->reg_mutex); + return err; } @@ -1741,6 +1743,7 @@ static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port, } mutex_unlock(&priv->reg_mutex); + return 0; } @@ -1810,6 +1813,7 @@ static int rtl83xx_port_mdb_add(struct dsa_switch *ds, int port, } err = -ENOTSUPP; + out: mutex_unlock(&priv->reg_mutex); if (err) @@ -1862,8 +1866,10 @@ int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port, goto out; } // TODO: Re-enable with a newer kernel: err = -ENOENT; + out: mutex_unlock(&priv->reg_mutex); + return err; } @@ -1874,7 +1880,7 @@ static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port, /* We support 4 mirror groups, one destination port per group */ int group; struct rtl838x_switch_priv *priv = ds->priv; - int ctrl_reg, dpm_reg, spm_reg; + int ctrl_reg, dpm_reg, spm_reg; pr_debug("In %s\n", __func__); @@ -1923,6 +1929,7 @@ static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port, priv->mirror_group_ports[group] = mirror->to_local_port; mutex_unlock(&priv->reg_mutex); + return 0; } @@ -2054,8 +2061,8 @@ static int rtl83xx_port_lag_join(struct dsa_switch *ds, int port, if (!priv->lag_devs[i]) priv->lag_devs[i] = lag; - if (priv->lag_primary[i]==-1) { - priv->lag_primary[i]=port; + if (priv->lag_primary[i] == -1) { + priv->lag_primary[i] = port; } else priv->is_lagmember[port] = 1; @@ -2070,8 +2077,8 @@ static int rtl83xx_port_lag_join(struct dsa_switch *ds, int port, out: mutex_unlock(&priv->reg_mutex); - return err; + return err; } static int rtl83xx_port_lag_leave(struct dsa_switch *ds, int port, @@ -2081,7 +2088,7 @@ static int rtl83xx_port_lag_leave(struct dsa_switch *ds, int port, struct rtl838x_switch_priv *priv = ds->priv; mutex_lock(&priv->reg_mutex); - for (i=0;in_lags;i++) { + for (i = 0; i < priv->n_lags; i++) { if (priv->lags_port_members[i] & BIT_ULL(port)) { group = i; break; @@ -2122,8 +2129,9 @@ int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg) u32 offset = 0; struct rtl838x_switch_priv *priv = ds->priv; - if (phy_addr >= 24 && phy_addr <= 27 - && priv->ports[24].phy == PHY_RTL838X_SDS) { + if ((phy_addr >= 24) && + (phy_addr <= 27) && + (priv->ports[24].phy == PHY_RTL838X_SDS)) { if (phy_addr == 26) offset = 0x100; val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff; @@ -2139,8 +2147,9 @@ int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val) u32 offset = 0; struct rtl838x_switch_priv *priv = ds->priv; - if (phy_addr >= 24 && phy_addr <= 27 - && priv->ports[24].phy == PHY_RTL838X_SDS) { + if ((phy_addr >= 24) && + (phy_addr <= 27) && + (priv->ports[24].phy == PHY_RTL838X_SDS)) { if (phy_addr == 26) offset = 0x100; sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)); diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/qos.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/qos.c index 2fc8d37f3e4..8a2621fb28b 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/qos.c +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/qos.c @@ -2,8 +2,8 @@ #include #include - #include + #include "rtl83xx.h" static struct rtl838x_switch_priv *switch_priv; @@ -20,28 +20,28 @@ int dot1p_priority_remapping[] = {0, 1, 2, 3, 4, 5, 6, 7}; static void rtl839x_read_scheduling_table(int port) { - u32 cmd = 1 << 9 /* Execute cmd */ - | 0 << 8 /* Read */ - | 0 << 6 /* Table type 0b00 */ - | (port & 0x3f); + u32 cmd = 1 << 9 | /* Execute cmd */ + 0 << 8 | /* Read */ + 0 << 6 | /* Table type 0b00 */ + (port & 0x3f); rtl839x_exec_tbl2_cmd(cmd); } static void rtl839x_write_scheduling_table(int port) { - u32 cmd = 1 << 9 /* Execute cmd */ - | 1 << 8 /* Write */ - | 0 << 6 /* Table type 0b00 */ - | (port & 0x3f); + u32 cmd = 1 << 9 | /* Execute cmd */ + 1 << 8 | /* Write */ + 0 << 6 | /* Table type 0b00 */ + (port & 0x3f); rtl839x_exec_tbl2_cmd(cmd); } static void rtl839x_read_out_q_table(int port) { - u32 cmd = 1 << 9 /* Execute cmd */ - | 0 << 8 /* Read */ - | 2 << 6 /* Table type 0b10 */ - | (port & 0x3f); + u32 cmd = 1 << 9 | /* Execute cmd */ + 0 << 8 | /* Read */ + 2 << 6 | /* Table type 0b10 */ + (port & 0x3f); rtl839x_exec_tbl2_cmd(cmd); } @@ -56,12 +56,10 @@ static void rtl838x_storm_enable(struct rtl838x_switch_priv *priv, int port, boo u32 rtl838x_get_egress_rate(struct rtl838x_switch_priv *priv, int port) { - u32 rate; - if (port > priv->cpu_port) return 0; - rate = sw_r32(RTL838X_SCHED_P_EGR_RATE_CTRL(port)) & 0x3fff; - return rate; + + return sw_r32(RTL838X_SCHED_P_EGR_RATE_CTRL(port)) & 0x3fff; } /* Sets the rate limit, 10MBit/s is equal to a rate value of 625 */ @@ -86,8 +84,10 @@ void rtl838x_egress_rate_queue_limit(struct rtl838x_switch_priv *priv, int port, { if (port > priv->cpu_port) return; + if (queue > 7) return; + sw_w32(rate, RTL838X_SCHED_Q_EGR_RATE_CTRL(port, queue)); } @@ -118,7 +118,8 @@ static void rtl838x_rate_control_init(struct rtl838x_switch_priv *priv) sw_w32_mask(0xffff, 0x800, RTL838X_SCHED_LB_THR); /* Enable storm control on all ports with a PHY and limit rates, - * for UC and MC for both known and unknown addresses */ + * for UC and MC for both known and unknown addresses + */ for (i = 0; i < priv->cpu_port; i++) { if (priv->ports[i].phy) { sw_w32((1 << 18) | 0x8000, RTL838X_STORM_CTRL_PORT_UC(i)); @@ -180,7 +181,7 @@ int rtl839x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate sw_w32_mask(0xfff << 20, rate << 20, RTL839X_TBL_ACCESS_DATA_2(8)); rtl839x_write_scheduling_table(port); - + mutex_unlock(&priv->reg_mutex); return old_rate; @@ -317,7 +318,7 @@ void rtl839x_setup_prio2queue_matrix(int *min_queues) /* Sets the CPU queue depending on the internal priority of a packet */ void rtl83xx_setup_prio2queue_cpu_matrix(int *max_queues) { - int reg = soc_info.family == RTL8380_FAMILY_ID ? RTL838X_QM_PKT2CPU_INTPRI_MAP + int reg = soc_info.family == RTL8380_FAMILY_ID ? RTL838X_QM_PKT2CPU_INTPRI_MAP : RTL839X_QM_PKT2CPU_INTPRI_MAP; int i; u32 v; @@ -351,7 +352,6 @@ void rtl83xx_set_ingress_priority(int port, int priority) sw_w32(priority << ((port % 10) *3), RTL838X_PRI_SEL_PORT_PRI(port)); else sw_w32(priority << ((port % 10) *3), RTL839X_PRI_SEL_PORT_PRI(port)); - } int rtl839x_get_scheduling_algorithm(struct rtl838x_switch_priv *priv, int port) @@ -367,6 +367,7 @@ int rtl839x_get_scheduling_algorithm(struct rtl838x_switch_priv *priv, int port) if (v & BIT(19)) return WEIGHTED_ROUND_ROBIN; + return WEIGHTED_FAIR_QUEUE; } @@ -386,7 +387,7 @@ void rtl839x_set_scheduling_algorithm(struct rtl838x_switch_priv *priv, int port // Get current OAM state oam_port_state = sw_r32(RTL839X_OAM_PORT_ACT_CTRL(port)); - + // Disable OAM to block traffice v = sw_r32(RTL839X_OAM_CTRL); sw_w32_mask(0, 1, RTL839X_OAM_CTRL); @@ -397,7 +398,7 @@ void rtl839x_set_scheduling_algorithm(struct rtl838x_switch_priv *priv, int port // Set port egress rate to unlimited egress_rate = rtl839x_set_egress_rate(priv, port, 0xFFFFF); - + // Wait until the egress used page count of that port is 0 i = 0; do { @@ -528,7 +529,7 @@ void rtl839x_config_qos(void) for (p = 0; p < 8; p++) v |= (dot1p_priority_remapping[p] & 0x7) << (p * 3); sw_w32(v, RTL839X_PRI_SEL_IPRI_REMAP); - + /* Configure Drop Precedence for Drop Eligible Indicator (DEI) * Index 0: 0 * Index 1: 2 @@ -572,5 +573,4 @@ void __init rtl83xx_setup_qos(struct rtl838x_switch_priv *priv) rtl838x_rate_control_init(priv); else if (priv->family_id == RTL8390_FAMILY_ID) rtl839x_rate_control_init(priv); - } diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.c index 9ce50989790..bd24b4e0ac2 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.c +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.c @@ -75,8 +75,7 @@ enum template_field_id { TEMPLATE_FIELD_FLOW_LABEL = 41, }; -/* - * The RTL838X SoCs use 5 fixed templates with definitions for which data fields are to +/* The RTL838X SoCs use 5 fixed templates with definitions for which data fields are to * be copied from the Ethernet Frame header into the 12 User-definable fields of the Packet * Inspection Engine's buffer. The following defines the field contents for each of the fixed * templates. Additionally, 3 user-definable templates can be set up via the definitions @@ -216,8 +215,7 @@ static u64 rtl838x_l2_hash_seed(u64 mac, u32 vid) return mac << 12 | vid; } -/* - * Applies the same hash algorithm as the one used currently by the ASIC to the seed +/* Applies the same hash algorithm as the one used currently by the ASIC to the seed * and returns a key into the L2 hash table */ static u32 rtl838x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed) @@ -237,9 +235,9 @@ static u32 rtl838x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed) h = h1 ^ h2 ^ h3 ^ ((seed >> 55) & 0x1ff); h ^= ((seed >> 22) & 0x7ff) ^ (seed & 0x7ff); } else { - h = ((seed >> 55) & 0x1ff) ^ ((seed >> 44) & 0x7ff) - ^ ((seed >> 33) & 0x7ff) ^ ((seed >> 22) & 0x7ff) - ^ ((seed >> 11) & 0x7ff) ^ (seed & 0x7ff); + h = ((seed >> 55) & 0x1ff) ^ ((seed >> 44) & 0x7ff) ^ + ((seed >> 33) & 0x7ff) ^ ((seed >> 22) & 0x7ff) ^ + ((seed >> 11) & 0x7ff) ^ (seed & 0x7ff); } return h; @@ -275,9 +273,7 @@ inline static int rtl838x_trk_mbr_ctr(int group) return RTL838X_TRK_MBR_CTR + (group << 2); } -/* - * Fills an L2 entry structure from the SoC registers - */ +/* Fills an L2 entry structure from the SoC registers */ static void rtl838x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e) { /* Table contains different entry types, we need to identify the right one: @@ -316,9 +312,10 @@ static void rtl838x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e) } e->age = (r[0] >> 17) & 0x3; e->valid = true; - + /* A valid entry has one of mutli-cast, aging, sa/da-blocking, - * next-hop or static entry bit set */ + * next-hop or static entry bit set + */ if (!(r[0] & 0x007c0000) && !(r[1] & 0xd0000000)) e->valid = false; else @@ -341,9 +338,7 @@ static void rtl838x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e) e->type = IP6_MULTICAST; } -/* - * Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry - */ +/* Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry */ static void rtl838x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e) { u64 mac = ether_addr_to_u64(e->mac); @@ -389,21 +384,19 @@ static void rtl838x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e) } } -/* - * Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table +/* Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table * hash is the id of the bucket and pos is the position of the entry in that bucket * The data read from the SoC is filled into rtl838x_l2_entry */ static u64 rtl838x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e) { - u64 entry; u32 r[3]; struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 0); // Access L2 Table 0 u32 idx = (0 << 14) | (hash << 2) | pos; // Search SRAM, with hash and at pos in bucket int i; rtl_table_read(q, idx); - for (i= 0; i < 3; i++) + for (i = 0; i < 3; i++) r[i] = sw_r32(rtl_table_data(q, i)); rtl_table_release(q); @@ -412,8 +405,7 @@ static u64 rtl838x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2 if (!e->valid) return 0; - entry = (((u64) r[1]) << 32) | (r[2]); // mac and vid concatenated as hash seed - return entry; + return (((u64) r[1]) << 32) | (r[2]); // mac and vid concatenated as hash seed } static void rtl838x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e) @@ -426,7 +418,7 @@ static void rtl838x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_ rtl838x_fill_l2_row(r, e); - for (i= 0; i < 3; i++) + for (i = 0; i < 3; i++) sw_w32(r[i], rtl_table_data(q, i)); rtl_table_write(q, idx); @@ -435,13 +427,12 @@ static void rtl838x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_ static u64 rtl838x_read_cam(int idx, struct rtl838x_l2_entry *e) { - u64 entry; u32 r[3]; struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 1); // Access L2 Table 1 int i; rtl_table_read(q, idx); - for (i= 0; i < 3; i++) + for (i = 0; i < 3; i++) r[i] = sw_r32(rtl_table_data(q, i)); rtl_table_release(q); @@ -453,8 +444,7 @@ static u64 rtl838x_read_cam(int idx, struct rtl838x_l2_entry *e) pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]); // Return MAC with concatenated VID ac concatenated ID - entry = (((u64) r[1]) << 32) | r[2]; - return entry; + return (((u64) r[1]) << 32) | r[2]; } static void rtl838x_write_cam(int idx, struct rtl838x_l2_entry *e) @@ -465,7 +455,7 @@ static void rtl838x_write_cam(int idx, struct rtl838x_l2_entry *e) rtl838x_fill_l2_row(r, e); - for (i= 0; i < 3; i++) + for (i = 0; i < 3; i++) sw_w32(r[i], rtl_table_data(q, i)); rtl_table_write(q, idx); @@ -539,8 +529,7 @@ static void rtl838x_enable_learning(int port, bool enable) static void rtl838x_enable_flood(int port, bool enable) { - /* - * 0: Forward + /* 0: Forward * 1: Disable * 2: to CPU * 3: Copy to CPU @@ -562,10 +551,10 @@ static void rtl838x_enable_bcast_flood(int port, bool enable) static void rtl838x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]) { int i; - u32 cmd = 1 << 15 /* Execute cmd */ - | 1 << 14 /* Read */ - | 2 << 12 /* Table type 0b10 */ - | (msti & 0xfff); + u32 cmd = 1 << 15 | /* Execute cmd */ + 1 << 14 | /* Read */ + 2 << 12 | /* Table type 0b10 */ + (msti & 0xfff); priv->r->exec_tbl0_cmd(cmd); for (i = 0; i < 2; i++) @@ -575,10 +564,10 @@ static void rtl838x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port static void rtl838x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]) { int i; - u32 cmd = 1 << 15 /* Execute cmd */ - | 0 << 14 /* Write */ - | 2 << 12 /* Table type 0b10 */ - | (msti & 0xfff); + u32 cmd = 1 << 15 | /* Execute cmd */ + 0 << 14 | /* Write */ + 2 << 12 | /* Table type 0b10 */ + (msti & 0xfff); for (i = 0; i < 2; i++) sw_w32(port_state[i], priv->r->tbl_access_data_0(i)); @@ -605,9 +594,7 @@ void rtl838x_traffic_disable(int source, int dest) rtl838x_mask_port_reg(BIT(dest), 0, rtl838x_port_iso_ctrl(source)); } -/* - * Enables or disables the EEE/EEEP capability of a port - */ +/* Enables or disables the EEE/EEEP capability of a port */ static void rtl838x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable) { u32 v; @@ -634,9 +621,7 @@ static void rtl838x_port_eee_set(struct rtl838x_switch_priv *priv, int port, boo } -/* - * Get EEE own capabilities and negotiation result - */ +/* Get EEE own capabilities and negotiation result */ static int rtl838x_eee_port_ability(struct rtl838x_switch_priv *priv, struct ethtool_eee *e, int port) { @@ -729,8 +714,7 @@ static void rtl838x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_fro mutex_unlock(&priv->reg_mutex); } -/* - * Reads the intermediate representation of the templated match-fields of the +/* Reads the intermediate representation of the templated match-fields of the * PIE rule in the pie_rule structure and fills in the raw data fields in the * raw register space r[]. * The register space configuration size is identical for the RTL8380/90 and RTL9300, @@ -826,7 +810,6 @@ static void rtl838x_write_pie_templated(u32 r[], struct pie_rule *pr, enum templ data_m = pr->sip_m >> 16; } break; - case TEMPLATE_FIELD_SIP2: case TEMPLATE_FIELD_SIP3: case TEMPLATE_FIELD_SIP4: @@ -836,7 +819,6 @@ static void rtl838x_write_pie_templated(u32 r[], struct pie_rule *pr, enum templ data = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)]; data_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)]; break; - case TEMPLATE_FIELD_DIP0: if (pr->is_ipv6) { data = pr->dip6.s6_addr16[7]; @@ -846,7 +828,6 @@ static void rtl838x_write_pie_templated(u32 r[], struct pie_rule *pr, enum templ data_m = pr->dip_m; } break; - case TEMPLATE_FIELD_DIP1: if (pr->is_ipv6) { data = pr->dip6.s6_addr16[6]; @@ -856,7 +837,6 @@ static void rtl838x_write_pie_templated(u32 r[], struct pie_rule *pr, enum templ data_m = pr->dip_m >> 16; } break; - case TEMPLATE_FIELD_DIP2: case TEMPLATE_FIELD_DIP3: case TEMPLATE_FIELD_DIP4: @@ -866,7 +846,6 @@ static void rtl838x_write_pie_templated(u32 r[], struct pie_rule *pr, enum templ data = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)]; data_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)]; break; - case TEMPLATE_FIELD_IP_TOS_PROTO: data = pr->tos_proto; data_m = pr->tos_proto_m; @@ -897,8 +876,7 @@ static void rtl838x_write_pie_templated(u32 r[], struct pie_rule *pr, enum templ } } -/* - * Creates the intermediate representation of the templated match-fields of the +/* Creates the intermediate representation of the templated match-fields of the * PIE rule in the pie_rule structure by reading the raw data fields in the * raw register space r[]. * The register space configuration size is identical for the RTL8380/90 and RTL9300, @@ -1002,7 +980,6 @@ static void rtl838x_read_pie_templated(u32 r[], struct pie_rule *pr, enum templa case TEMPLATE_FIELD_SIP6: case TEMPLATE_FIELD_SIP7: break; - case TEMPLATE_FIELD_DIP0: pr->dip = data; pr->dip_m = data_m; @@ -1434,13 +1411,17 @@ static int rtl838x_pie_verify_template(struct rtl838x_switch_priv *priv, return -1; if (pr->is_ipv6) { - if ((pr->sip6_m.s6_addr32[0] || pr->sip6_m.s6_addr32[1] - || pr->sip6_m.s6_addr32[2] || pr->sip6_m.s6_addr32[3]) - && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_SIP2)) + if ((pr->sip6_m.s6_addr32[0] || + pr->sip6_m.s6_addr32[1] || + pr->sip6_m.s6_addr32[2] || + pr->sip6_m.s6_addr32[3]) && + !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_SIP2)) return -1; - if ((pr->dip6_m.s6_addr32[0] || pr->dip6_m.s6_addr32[1] - || pr->dip6_m.s6_addr32[2] || pr->dip6_m.s6_addr32[3]) - && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_DIP2)) + if ((pr->dip6_m.s6_addr32[0] || + pr->dip6_m.s6_addr32[1] || + pr->dip6_m.s6_addr32[2] || + pr->dip6_m.s6_addr32[3]) && + !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_DIP2)) return -1; } @@ -1497,6 +1478,7 @@ static int rtl838x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rul rtl838x_pie_rule_write(priv, idx, pr); mutex_unlock(&priv->pie_mutex); + return 0; } @@ -1508,8 +1490,7 @@ static void rtl838x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rul clear_bit(idx, priv->pie_use_bm); } -/* - * Initializes the Packet Inspection Engine: +/* Initializes the Packet Inspection Engine: * powers it up, enables default matching templates for all blocks * and clears all rules possibly installed by u-boot */ @@ -1695,17 +1676,17 @@ void rtl838x_set_receive_management_action(int port, rma_ctrl_t type, action_typ case BPDU: sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1), RTL838X_RMA_BPDU_CTRL + ((port >> 4) << 2)); - break; + break; case PTP: sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1), RTL838X_RMA_PTP_CTRL + ((port >> 4) << 2)); - break; + break; case LLTP: sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1), RTL838X_RMA_LLTP_CTRL + ((port >> 4) << 2)); - break; + break; default: - break; + break; } } @@ -1776,7 +1757,7 @@ const struct rtl838x_reg rtl838x_reg = { .init_eee = rtl838x_init_eee, .port_eee_set = rtl838x_port_eee_set, .eee_port_ability = rtl838x_eee_port_ability, - .l2_hash_seed = rtl838x_l2_hash_seed, + .l2_hash_seed = rtl838x_l2_hash_seed, .l2_hash_key = rtl838x_l2_hash_key, .read_mcast_pmask = rtl838x_read_mcast_pmask, .write_mcast_pmask = rtl838x_write_mcast_pmask, @@ -1816,6 +1797,7 @@ irqreturn_t rtl838x_switch_irq(int irq, void *dev_id) dsa_port_phylink_mac_change(ds, i, false); } } + return IRQ_HANDLED; } @@ -1832,11 +1814,10 @@ int rtl838x_smi_wait_op(int timeout) return ret; } -/* - * Reads a register in a page from the PHY - */ +/* Reads a register in a page from the PHY */ int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val) { + int err = -ETIMEDOUT; u32 v; u32 park_page; @@ -1865,19 +1846,18 @@ int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val) *val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff; - mutex_unlock(&smi_lock); - return 0; + err = 0; timeout: mutex_unlock(&smi_lock); + return -ETIMEDOUT; } -/* - * Write to a register in a page of the PHY - */ +/* Write to a register in a page of the PHY */ int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val) { + int err = -ETIMEDOUT; u32 v; u32 park_page; @@ -1902,19 +1882,18 @@ int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val) if (rtl838x_smi_wait_op(100000)) goto timeout; - mutex_unlock(&smi_lock); - return 0; + err = 0; timeout: mutex_unlock(&smi_lock); + return -ETIMEDOUT; } -/* - * Read an mmd register of a PHY - */ +/* Read an mmd register of a PHY */ int rtl838x_read_mmd_phy(u32 port, u32 addr, u32 reg, u32 *val) { + int err = -ETIMEDOUT; u32 v; mutex_lock(&smi_lock); @@ -1939,19 +1918,18 @@ int rtl838x_read_mmd_phy(u32 port, u32 addr, u32 reg, u32 *val) *val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff; - mutex_unlock(&smi_lock); - return 0; + err = 0; timeout: mutex_unlock(&smi_lock); - return -ETIMEDOUT; + + return err; } -/* - * Write to an mmd register of a PHY - */ +/* Write to an mmd register of a PHY */ int rtl838x_write_mmd_phy(u32 port, u32 addr, u32 reg, u32 val) { + int err = -ETIMEDOUT; u32 v; pr_debug("MMD write: port %d, dev %d, reg %d, val %x\n", port, addr, reg, val); @@ -1975,12 +1953,11 @@ int rtl838x_write_mmd_phy(u32 port, u32 addr, u32 reg, u32 val) if (rtl838x_smi_wait_op(100000)) goto timeout; - mutex_unlock(&smi_lock); - return 0; + err = 0; timeout: mutex_unlock(&smi_lock); - return -ETIMEDOUT; + return err; } void rtl8380_get_version(struct rtl838x_switch_priv *priv) diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.h b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.h index 19049e4c957..68a4675e111 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.h +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.h @@ -5,9 +5,7 @@ #include -/* - * Register definition - */ +/* Register definition */ #define RTL838X_MAC_PORT_CTRL(port) (0xd560 + (((port) << 7))) #define RTL839X_MAC_PORT_CTRL(port) (0x8004 + (((port) << 7))) #define RTL930X_MAC_PORT_CTRL(port) (0x3260 + (((port) << 6))) @@ -398,17 +396,16 @@ #define RTL839X_SPCL_TRAP_SWITCH_IPV4_ADDR_CTRL (0x106C) #define RTL839X_SPCL_TRAP_CRC_CTRL (0x1070) /* special port action controls */ -/* - values: - 0 = FORWARD (default) - 1 = DROP - 2 = TRAP2CPU - 3 = FLOOD IN ALL PORT - - Register encoding. - offset = CTRL + (port >> 4) << 2 - value/mask = 3 << ((port&0xF) << 1) -*/ +/* values: + * 0 = FORWARD (default) + * 1 = DROP + * 2 = TRAP2CPU + * 3 = FLOOD IN ALL PORT + * + * Register encoding. + * offset = CTRL + (port >> 4) << 2 + * value/mask = 3 << ((port & 0xF) << 1) + */ typedef enum { BPDU = 0, @@ -429,17 +426,17 @@ typedef enum { COPY2CPU, } action_type_t; -#define RTL838X_RMA_BPDU_CTRL (0x4330) +#define RTL838X_RMA_BPDU_CTRL (0x4330) #define RTL839X_RMA_BPDU_CTRL (0x122C) #define RTL930X_RMA_BPDU_CTRL (0x9E7C) #define RTL931X_RMA_BPDU_CTRL (0x881C) -#define RTL838X_RMA_PTP_CTRL (0x4338) +#define RTL838X_RMA_PTP_CTRL (0x4338) #define RTL839X_RMA_PTP_CTRL (0x123C) #define RTL930X_RMA_PTP_CTRL (0x9E88) #define RTL931X_RMA_PTP_CTRL (0x8834) -#define RTL838X_RMA_LLTP_CTRL (0x4340) +#define RTL838X_RMA_LLTP_CTRL (0x4340) #define RTL839X_RMA_LLTP_CTRL (0x124C) #define RTL930X_RMA_LLTP_CTRL (0x9EFC) #define RTL931X_RMA_LLTP_CTRL (0x8918) @@ -871,8 +868,7 @@ struct rtl838x_l3_intf { u8 ip6_pbr_icmp_redirect; }; -/* - * An entry in the RTL93XX SoC's ROUTER_MAC tables setting up a termination point +/* An entry in the RTL93XX SoC's ROUTER_MAC tables setting up a termination point * for the L3 routing system. Packets arriving and matching an entry in this table * will be considered for routing. * Mask fields state whether the corresponding data fields matter for matching diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl839x.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl839x.c index 986a4b5f45c..6fac8bd6741 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl839x.c +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl839x.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only #include + #include "rtl83xx.h" #define RTL839X_VLAN_PORT_TAG_STS_UNTAG 0x0 @@ -228,8 +229,7 @@ static void rtl839x_vlan_set_untagged(u32 vlan, u64 portmask) rtl_table_release(r); } -/* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer - */ +/* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer */ static void rtl839x_vlan_fwd_on_inner(int port, bool is_set) { if (is_set) @@ -238,9 +238,7 @@ static void rtl839x_vlan_fwd_on_inner(int port, bool is_set) rtl839x_mask_port_reg_be(0ULL, BIT_ULL(port), RTL839X_VLAN_PORT_FWD); } -/* - * Hash seed is vid (actually rvid) concatenated with the MAC address - */ +/* Hash seed is vid (actually rvid) concatenated with the MAC address */ static u64 rtl839x_l2_hash_seed(u64 mac, u32 vid) { u64 v = vid; @@ -251,8 +249,7 @@ static u64 rtl839x_l2_hash_seed(u64 mac, u32 vid) return v; } -/* - * Applies the same hash algorithm as the one used currently by the ASIC to the seed +/* Applies the same hash algorithm as the one used currently by the ASIC to the seed * and returns a key into the L2 hash table */ static u32 rtl839x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed) @@ -260,18 +257,18 @@ static u32 rtl839x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed) u32 h1, h2, h; if (sw_r32(priv->r->l2_ctrl_0) & 1) { - h1 = (u32) (((seed >> 60) & 0x3f) ^ ((seed >> 54) & 0x3f) - ^ ((seed >> 36) & 0x3f) ^ ((seed >> 30) & 0x3f) - ^ ((seed >> 12) & 0x3f) ^ ((seed >> 6) & 0x3f)); - h2 = (u32) (((seed >> 48) & 0x3f) ^ ((seed >> 42) & 0x3f) - ^ ((seed >> 24) & 0x3f) ^ ((seed >> 18) & 0x3f) - ^ (seed & 0x3f)); + h1 = (u32) (((seed >> 60) & 0x3f) ^ ((seed >> 54) & 0x3f) ^ + ((seed >> 36) & 0x3f) ^ ((seed >> 30) & 0x3f) ^ + ((seed >> 12) & 0x3f) ^ ((seed >> 6) & 0x3f)); + h2 = (u32) (((seed >> 48) & 0x3f) ^ ((seed >> 42) & 0x3f) ^ + ((seed >> 24) & 0x3f) ^ ((seed >> 18) & 0x3f) ^ + (seed & 0x3f)); h = (h1 << 6) | h2; } else { - h = (seed >> 60) - ^ ((((seed >> 48) & 0x3f) << 6) | ((seed >> 54) & 0x3f)) - ^ ((seed >> 36) & 0xfff) ^ ((seed >> 24) & 0xfff) - ^ ((seed >> 12) & 0xfff) ^ (seed & 0xfff); + h = (seed >> 60) ^ + ((((seed >> 48) & 0x3f) << 6) | ((seed >> 54) & 0x3f)) ^ + ((seed >> 36) & 0xfff) ^ ((seed >> 24) & 0xfff) ^ + ((seed >> 12) & 0xfff) ^ (seed & 0xfff); } return h; @@ -368,9 +365,7 @@ static void rtl839x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e) // pr_info("%s: vid %d, rvid: %d\n", __func__, e->vid, e->rvid); } -/* - * Fills the 3 SoC table registers r[] with the information in the rtl838x_l2_entry - */ +/* Fills the 3 SoC table registers r[] with the information in the rtl838x_l2_entry */ static void rtl839x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e) { if (!e->valid) { @@ -417,8 +412,7 @@ static void rtl839x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e) } } -/* - * Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table +/* Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table * hash is the id of the bucket and pos is the position of the entry in that bucket * The data read from the SoC is filled into rtl838x_l2_entry */ @@ -430,7 +424,7 @@ static u64 rtl839x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2 int i; rtl_table_read(q, idx); - for (i= 0; i < 3; i++) + for (i = 0; i < 3; i++) r[i] = sw_r32(rtl_table_data(q, i)); rtl_table_release(q); @@ -452,7 +446,7 @@ static void rtl839x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_ rtl839x_fill_l2_row(r, e); - for (i= 0; i < 3; i++) + for (i = 0; i < 3; i++) sw_w32(r[i], rtl_table_data(q, i)); rtl_table_write(q, idx); @@ -466,7 +460,7 @@ static u64 rtl839x_read_cam(int idx, struct rtl838x_l2_entry *e) int i; rtl_table_read(q, idx); - for (i= 0; i < 3; i++) + for (i = 0; i < 3; i++) r[i] = sw_r32(rtl_table_data(q, i)); rtl_table_release(q); @@ -489,7 +483,7 @@ static void rtl839x_write_cam(int idx, struct rtl838x_l2_entry *e) rtl839x_fill_l2_row(r, e); - for (i= 0; i < 3; i++) + for (i = 0; i < 3; i++) sw_w32(r[i], rtl_table_data(q, i)); rtl_table_write(q, idx); @@ -583,8 +577,7 @@ static void rtl839x_enable_learning(int port, bool enable) static void rtl839x_enable_flood(int port, bool enable) { - /* - * 0: Forward + /* 0: Forward * 1: Disable * 2: to CPU * 3: Copy to CPU @@ -623,6 +616,7 @@ irqreturn_t rtl839x_switch_irq(int irq, void *dev_id) dsa_port_phylink_mac_change(ds, i, false); } } + return IRQ_HANDLED; } @@ -689,6 +683,7 @@ int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val) errout: mutex_unlock(&smi_lock); + return err; } @@ -729,12 +724,11 @@ int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val) errout: mutex_unlock(&smi_lock); + return err; } -/* - * Read an mmd register of the PHY - */ +/* Read an mmd register of the PHY */ int rtl839x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val) { int err = 0; @@ -765,12 +759,11 @@ int rtl839x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val) errout: mutex_unlock(&smi_lock); + return err; } -/* - * Write to an mmd register of the PHY - */ +/* Write to an mmd register of the PHY */ int rtl839x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val) { int err = 0; @@ -802,6 +795,7 @@ int rtl839x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val) errout: mutex_unlock(&smi_lock); + return err; } @@ -838,10 +832,10 @@ void rtl839x_vlan_profile_dump(int profile) static void rtl839x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]) { int i; - u32 cmd = 1 << 16 /* Execute cmd */ - | 0 << 15 /* Read */ - | 5 << 12 /* Table type 0b101 */ - | (msti & 0xfff); + u32 cmd = 1 << 16 | /* Execute cmd */ + 0 << 15 | /* Read */ + 5 << 12 | /* Table type 0b101 */ + (msti & 0xfff); priv->r->exec_tbl0_cmd(cmd); for (i = 0; i < 4; i++) @@ -851,18 +845,16 @@ static void rtl839x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port static void rtl839x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]) { int i; - u32 cmd = 1 << 16 /* Execute cmd */ - | 1 << 15 /* Write */ - | 5 << 12 /* Table type 0b101 */ - | (msti & 0xfff); + u32 cmd = 1 << 16 | /* Execute cmd */ + 1 << 15 | /* Write */ + 5 << 12 | /* Table type 0b101 */ + (msti & 0xfff); for (i = 0; i < 4; i++) sw_w32(port_state[i], priv->r->tbl_access_data_0(i)); priv->r->exec_tbl0_cmd(cmd); } -/* - * Enables or disables the EEE/EEEP capability of a port - */ +/* Enables or disables the EEE/EEEP capability of a port */ void rtl839x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable) { u32 v; @@ -885,9 +877,7 @@ void rtl839x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enabl priv->ports[port].eee_enabled = enable; } -/* - * Get EEE own capabilities and negotiation result - */ +/* Get EEE own capabilities and negotiation result */ int rtl839x_eee_port_ability(struct rtl838x_switch_priv *priv, struct ethtool_eee *e, int port) { u64 link, a; @@ -944,9 +934,7 @@ static void rtl839x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int inde sw_w32_mask(0, BIT(block), RTL839X_ACL_BLK_LOOKUP_CTRL); } -/* - * Delete a range of Packet Inspection Engine rules - */ +/* Delete a range of Packet Inspection Engine rules */ static int rtl839x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to) { u32 v = (index_from << 1)| (index_to << 13 ) | BIT(0); @@ -962,11 +950,11 @@ static int rtl839x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from } while (sw_r32(RTL839X_ACL_CLR_CTRL) & BIT(0)); mutex_unlock(&priv->reg_mutex); + return 0; } -/* - * Reads the intermediate representation of the templated match-fields of the +/* Reads the intermediate representation of the templated match-fields of the * PIE rule in the pie_rule structure and fills in the raw data fields in the * raw register space r[]. * The register space configuration size is identical for the RTL8380/90 and RTL9300, @@ -1067,7 +1055,6 @@ static void rtl839x_write_pie_templated(u32 r[], struct pie_rule *pr, enum templ data_m = pr->sip_m >> 16; } break; - case TEMPLATE_FIELD_SIP2: case TEMPLATE_FIELD_SIP3: case TEMPLATE_FIELD_SIP4: @@ -1077,7 +1064,6 @@ static void rtl839x_write_pie_templated(u32 r[], struct pie_rule *pr, enum templ data = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)]; data_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)]; break; - case TEMPLATE_FIELD_DIP0: if (pr->is_ipv6) { data = pr->dip6.s6_addr16[7]; @@ -1087,7 +1073,6 @@ static void rtl839x_write_pie_templated(u32 r[], struct pie_rule *pr, enum templ data_m = pr->dip_m; } break; - case TEMPLATE_FIELD_DIP1: if (pr->is_ipv6) { data = pr->dip6.s6_addr16[6]; @@ -1097,7 +1082,6 @@ static void rtl839x_write_pie_templated(u32 r[], struct pie_rule *pr, enum templ data_m = pr->dip_m >> 16; } break; - case TEMPLATE_FIELD_DIP2: case TEMPLATE_FIELD_DIP3: case TEMPLATE_FIELD_DIP4: @@ -1107,7 +1091,6 @@ static void rtl839x_write_pie_templated(u32 r[], struct pie_rule *pr, enum templ data = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)]; data_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)]; break; - case TEMPLATE_FIELD_IP_TOS_PROTO: data = pr->tos_proto; data_m = pr->tos_proto_m; @@ -1140,8 +1123,7 @@ static void rtl839x_write_pie_templated(u32 r[], struct pie_rule *pr, enum templ } } -/* - * Creates the intermediate representation of the templated match-fields of the +/* Creates the intermediate representation of the templated match-fields of the * PIE rule in the pie_rule structure by reading the raw data fields in the * raw register space r[]. * The register space configuration size is identical for the RTL8380/90 and RTL9300, @@ -1541,13 +1523,17 @@ static int rtl839x_pie_verify_template(struct rtl838x_switch_priv *priv, return -1; if (pr->is_ipv6) { - if ((pr->sip6_m.s6_addr32[0] || pr->sip6_m.s6_addr32[1] - || pr->sip6_m.s6_addr32[2] || pr->sip6_m.s6_addr32[3]) - && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_SIP2)) + if ((pr->sip6_m.s6_addr32[0] || + pr->sip6_m.s6_addr32[1] || + pr->sip6_m.s6_addr32[2] || + pr->sip6_m.s6_addr32[3]) && + !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_SIP2)) return -1; - if ((pr->dip6_m.s6_addr32[0] || pr->dip6_m.s6_addr32[1] - || pr->dip6_m.s6_addr32[2] || pr->dip6_m.s6_addr32[3]) - && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_DIP2)) + if ((pr->dip6_m.s6_addr32[0] || + pr->dip6_m.s6_addr32[1] || + pr->dip6_m.s6_addr32[2] || + pr->dip6_m.s6_addr32[3]) && + !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_DIP2)) return -1; } @@ -1607,6 +1593,7 @@ static int rtl839x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rul rtl839x_pie_rule_write(priv, idx, pr); mutex_unlock(&priv->pie_mutex); + return 0; } @@ -1743,9 +1730,7 @@ static void rtl839x_route_write(int idx, struct rtl83xx_route *rt) rtl_table_release(r); } -/* - * Configure the switch's own MAC addresses used when routing packets - */ +/* Configure the switch's own MAC addresses used when routing packets */ static void rtl839x_setup_port_macs(struct rtl838x_switch_priv *priv) { int i; @@ -1836,17 +1821,17 @@ void rtl839x_set_receive_management_action(int port, rma_ctrl_t type, action_typ case BPDU: sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1), RTL839X_RMA_BPDU_CTRL + ((port >> 4) << 2)); - break; + break; case PTP: sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1), RTL839X_RMA_PTP_CTRL + ((port >> 4) << 2)); - break; + break; case LLTP: sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1), RTL839X_RMA_LLTP_CTRL + ((port >> 4) << 2)); - break; + break; default: - break; + break; } } @@ -1917,7 +1902,7 @@ const struct rtl838x_reg rtl839x_reg = { .init_eee = rtl839x_init_eee, .port_eee_set = rtl839x_port_eee_set, .eee_port_ability = rtl839x_eee_port_ability, - .l2_hash_seed = rtl839x_l2_hash_seed, + .l2_hash_seed = rtl839x_l2_hash_seed, .l2_hash_key = rtl839x_l2_hash_key, .read_mcast_pmask = rtl839x_read_mcast_pmask, .write_mcast_pmask = rtl839x_write_mcast_pmask, diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl83xx.h b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl83xx.h index 485d0e8a7e9..679f0533b4f 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl83xx.h +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl83xx.h @@ -134,4 +134,3 @@ int rtl83xx_lag_add(struct dsa_switch *ds, int group, int port, struct netdev_la int rtl83xx_lag_del(struct dsa_switch *ds, int group, int port); #endif /* _NET_DSA_RTL83XX_H */ - diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl930x.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl930x.c index 5dde8353e2d..6cd0c6b8144 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl930x.c +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl930x.c @@ -242,8 +242,7 @@ static void rtl930x_vlan_set_untagged(u32 vlan, u64 portmask) rtl_table_release(r); } -/* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer - */ +/* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer */ static void rtl930x_vlan_fwd_on_inner(int port, bool is_set) { // Always set all tag modes to fwd based on either inner or outer tag @@ -289,10 +288,10 @@ static void rtl930x_l2_learning_setup(void) static void rtl930x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]) { int i; - u32 cmd = 1 << 17 /* Execute cmd */ - | 0 << 16 /* Read */ - | 4 << 12 /* Table type 0b10 */ - | (msti & 0xfff); + u32 cmd = 1 << 17 | /* Execute cmd */ + 0 << 16 | /* Read */ + 4 << 12 | /* Table type 0b10 */ + (msti & 0xfff); priv->r->exec_tbl0_cmd(cmd); for (i = 0; i < 2; i++) @@ -303,10 +302,10 @@ static void rtl930x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port static void rtl930x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]) { int i; - u32 cmd = 1 << 17 /* Execute cmd */ - | 1 << 16 /* Write */ - | 4 << 12 /* Table type 4 */ - | (msti & 0xfff); + u32 cmd = 1 << 17 | /* Execute cmd */ + 1 << 16 | /* Write */ + 4 << 12 | /* Table type 4 */ + (msti & 0xfff); for (i = 0; i < 2; i++) sw_w32(port_state[i], RTL930X_TBL_ACCESS_DATA_0(i)); @@ -338,8 +337,7 @@ static u64 rtl930x_l2_hash_seed(u64 mac, u32 vid) return v; } -/* - * Calculate both the block 0 and the block 1 hash by applyingthe same hash +/* Calculate both the block 0 and the block 1 hash by applyingthe same hash * algorithm as the one used currently by the ASIC to the seed, and return * both hashes in the lower and higher word of the return value since only 12 bit of * the hash are significant @@ -348,9 +346,12 @@ static u32 rtl930x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed) { u32 k0, k1, h1, h2, h; - k0 = (u32) (((seed >> 55) & 0x1f) ^ ((seed >> 44) & 0x7ff) - ^ ((seed >> 33) & 0x7ff) ^ ((seed >> 22) & 0x7ff) - ^ ((seed >> 11) & 0x7ff) ^ (seed & 0x7ff)); + k0 = (u32) (((seed >> 55) & 0x1f) ^ + ((seed >> 44) & 0x7ff) ^ + ((seed >> 33) & 0x7ff) ^ + ((seed >> 22) & 0x7ff) ^ + ((seed >> 11) & 0x7ff) ^ + (seed & 0x7ff)); h1 = (seed >> 11) & 0x7ff; h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f); @@ -358,9 +359,12 @@ static u32 rtl930x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed) h2 = (seed >> 33) & 0x7ff; h2 = ((h2 & 0x3f) << 5)| ((h2 >> 6) & 0x3f); - k1 = (u32) (((seed << 55) & 0x1f) ^ ((seed >> 44) & 0x7ff) ^ h2 - ^ ((seed >> 22) & 0x7ff) ^ h1 - ^ (seed & 0x7ff)); + k1 = (u32) (((seed << 55) & 0x1f) ^ + ((seed >> 44) & 0x7ff) ^ + h2 ^ + ((seed >> 22) & 0x7ff) ^ + h1 ^ + (seed & 0x7ff)); // Algorithm choice for block 0 if (sw_r32(RTL930X_L2_CTRL) & BIT(0)) @@ -382,9 +386,7 @@ static u32 rtl930x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed) return h; } -/* - * Fills an L2 entry structure from the SoC registers - */ +/* Fills an L2 entry structure from the SoC registers */ static void rtl930x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e) { pr_debug("In %s valid?\n", __func__); @@ -443,9 +445,7 @@ static void rtl930x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e) } } -/* - * Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry - */ +/* Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry */ static void rtl930x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e) { u32 port; @@ -457,9 +457,12 @@ static void rtl930x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e) r[2] = BIT(31); // Set valid bit - r[0] = ((u32)e->mac[0]) << 24 | ((u32)e->mac[1]) << 16 - | ((u32)e->mac[2]) << 8 | ((u32)e->mac[3]); - r[1] = ((u32)e->mac[4]) << 24 | ((u32)e->mac[5]) << 16; + r[0] = ((u32)e->mac[0]) << 24 | + ((u32)e->mac[1]) << 16 | + ((u32)e->mac[2]) << 8 | + ((u32)e->mac[3]); + r[1] = ((u32)e->mac[4]) << 24 | + ((u32)e->mac[5]) << 16; r[2] |= e->next_hop ? BIT(12) : 0; @@ -490,8 +493,7 @@ static void rtl930x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e) } } -/* - * Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table +/* Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table * hash is the id of the bucket and pos is the position of the entry in that bucket * The data read from the SoC is filled into rtl838x_l2_entry */ @@ -506,9 +508,10 @@ static u64 rtl930x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2 pr_debug("%s: hash %08x, pos: %d\n", __func__, hash, pos); - /* On the RTL93xx, 2 different hash algorithms are used making it a total of - * 8 buckets that need to be searched, 4 for each hash-half - * Use second hash space when bucket is between 4 and 8 */ + /* On the RTL93xx, 2 different hash algorithms are used making it a + * total of 8 buckets that need to be searched, 4 for each hash-half + * Use second hash space when bucket is between 4 and 8 + */ if (pos >= 4) { pos -= 4; hash >>= 16; @@ -531,11 +534,16 @@ static u64 rtl930x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2 if (!e->valid) return 0; - mac = ((u64)e->mac[0]) << 40 | ((u64)e->mac[1]) << 32 | ((u64)e->mac[2]) << 24 - | ((u64)e->mac[3]) << 16 | ((u64)e->mac[4]) << 8 | ((u64)e->mac[5]); + mac = ((u64)e->mac[0]) << 40 | + ((u64)e->mac[1]) << 32 | + ((u64)e->mac[2]) << 24 | + ((u64)e->mac[3]) << 16 | + ((u64)e->mac[4]) << 8 | + ((u64)e->mac[5]); seed = rtl930x_l2_hash_seed(mac, e->rvid); pr_debug("%s: mac %016llx, seed %016llx\n", __func__, mac, seed); + // return vid with concatenated mac as unique id return seed; } @@ -553,7 +561,7 @@ static void rtl930x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_ rtl930x_fill_l2_row(r, e); - for (i= 0; i < 3; i++) + for (i = 0; i < 3; i++) sw_w32(r[i], rtl_table_data(q, i)); rtl_table_write(q, idx); @@ -567,7 +575,7 @@ static u64 rtl930x_read_cam(int idx, struct rtl838x_l2_entry *e) int i; rtl_table_read(q, idx); - for (i= 0; i < 3; i++) + for (i = 0; i < 3; i++) r[i] = sw_r32(rtl_table_data(q, i)); rtl_table_release(q); @@ -588,7 +596,7 @@ static void rtl930x_write_cam(int idx, struct rtl838x_l2_entry *e) rtl930x_fill_l2_row(r, e); - for (i= 0; i < 3; i++) + for (i = 0; i < 3; i++) sw_w32(r[i], rtl_table_data(q, i)); rtl_table_write(q, idx); @@ -607,6 +615,7 @@ static u64 rtl930x_read_mcast_pmask(int idx) rtl_table_release(q); pr_debug("%s: Index idx %d has portmask %08x\n", __func__, idx, portmask); + return portmask; } @@ -632,12 +641,12 @@ u64 rtl930x_traffic_get(int source) rtl_table_read(r, source); v = sw_r32(rtl_table_data(r, 0)); rtl_table_release(r); - return v >> 3; + v = v >> 3; + + return v; } -/* - * Enable traffic between a source port and a destination port matrix - */ +/* Enable traffic between a source port and a destination port matrix */ void rtl930x_traffic_set(int source, u64 dest_matrix) { struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6); @@ -698,7 +707,8 @@ irqreturn_t rtl930x_switch_irq(int irq, void *dev_id) for (i = 0; i < 28; i++) { if (ports & BIT(i)) { /* Read the register twice because of issues with latency at least - * with the external RTL8226 PHY on the XGS1210 */ + * with the external RTL8226 PHY on the XGS1210 + */ link = sw_r32(RTL930X_MAC_LINK_STS); link = sw_r32(RTL930X_MAC_LINK_STS); if (link & BIT(i)) @@ -772,9 +782,7 @@ int rtl930x_read_phy(u32 port, u32 page, u32 reg, u32 *val) return err; } -/* - * Write to an mmd register of the PHY - */ +/* Write to an mmd register of the PHY */ int rtl930x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val) { int err = 0; @@ -803,9 +811,7 @@ int rtl930x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val) return err; } -/* - * Read an mmd register of the PHY - */ +/* Read an mmd register of the PHY */ int rtl930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val) { int err = 0; @@ -834,8 +840,7 @@ int rtl930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val) return err; } -/* - * Calculate both the block 0 and the block 1 hash, and return in +/* Calculate both the block 0 and the block 1 hash, and return in * lower and higher word of the return value since only 12 bit of * the hash are significant */ @@ -843,19 +848,25 @@ u32 rtl930x_hash(struct rtl838x_switch_priv *priv, u64 seed) { u32 k0, k1, h1, h2, h; - k0 = (u32) (((seed >> 55) & 0x1f) ^ ((seed >> 44) & 0x7ff) - ^ ((seed >> 33) & 0x7ff) ^ ((seed >> 22) & 0x7ff) - ^ ((seed >> 11) & 0x7ff) ^ (seed & 0x7ff)); + k0 = (u32) (((seed >> 55) & 0x1f) ^ + ((seed >> 44) & 0x7ff) ^ + ((seed >> 33) & 0x7ff) ^ + ((seed >> 22) & 0x7ff) ^ + ((seed >> 11) & 0x7ff) ^ + (seed & 0x7ff)); h1 = (seed >> 11) & 0x7ff; h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f); h2 = (seed >> 33) & 0x7ff; - h2 = ((h2 & 0x3f) << 5)| ((h2 >> 6) & 0x3f); + h2 = ((h2 & 0x3f) << 5) | ((h2 >> 6) & 0x3f); - k1 = (u32) (((seed << 55) & 0x1f) ^ ((seed >> 44) & 0x7ff) ^ h2 - ^ ((seed >> 22) & 0x7ff) ^ h1 - ^ (seed & 0x7ff)); + k1 = (u32) (((seed << 55) & 0x1f) ^ + ((seed >> 44) & 0x7ff) ^ + h2 ^ + ((seed >> 22) & 0x7ff) ^ + h1 ^ + (seed & 0x7ff)); // Algorithm choice for block 0 if (sw_r32(RTL930X_L2_CTRL) & BIT(0)) @@ -877,9 +888,7 @@ u32 rtl930x_hash(struct rtl838x_switch_priv *priv, u64 seed) return h; } -/* - * Enables or disables the EEE/EEEP capability of a port - */ +/* Enables or disables the EEE/EEEP capability of a port */ void rtl930x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable) { u32 v; @@ -901,9 +910,7 @@ void rtl930x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enabl priv->ports[port].eee_enabled = enable; } -/* - * Get EEE own capabilities and negotiation result - */ +/* Get EEE own capabilities and negotiation result */ int rtl930x_eee_port_ability(struct rtl838x_switch_priv *priv, struct ethtool_eee *e, int port) { u32 link, a; @@ -1012,41 +1019,41 @@ static u32 rtl930x_l3_hash6(struct in6_addr *ip6, int algorithm, bool move_dip) rows[9] = (HASH_PICK(ip6->s6_addr[9], 0, 6) << 3) | HASH_PICK(ip6->s6_addr[10], 5, 3); rows[10] = (HASH_PICK(ip6->s6_addr[10], 0, 5) << 4) | HASH_PICK(ip6->s6_addr[11], 4, 4); if (!algorithm) { - rows[11] = (HASH_PICK(ip6->s6_addr[11], 0, 4) << 5) - | (HASH_PICK(ip6->s6_addr[12], 3, 5) << 0); - rows[12] = (HASH_PICK(ip6->s6_addr[12], 0, 3) << 6) - | (HASH_PICK(ip6->s6_addr[13], 2, 6) << 0); - rows[13] = (HASH_PICK(ip6->s6_addr[13], 0, 2) << 7) - | (HASH_PICK(ip6->s6_addr[14], 1, 7) << 0); + rows[11] = (HASH_PICK(ip6->s6_addr[11], 0, 4) << 5) | + (HASH_PICK(ip6->s6_addr[12], 3, 5) << 0); + rows[12] = (HASH_PICK(ip6->s6_addr[12], 0, 3) << 6) | + (HASH_PICK(ip6->s6_addr[13], 2, 6) << 0); + rows[13] = (HASH_PICK(ip6->s6_addr[13], 0, 2) << 7) | + (HASH_PICK(ip6->s6_addr[14], 1, 7) << 0); if (!move_dip) { - rows[14] = (HASH_PICK(ip6->s6_addr[14], 0, 1) << 8) - | (HASH_PICK(ip6->s6_addr[15], 0, 8) << 0); + rows[14] = (HASH_PICK(ip6->s6_addr[14], 0, 1) << 8) | + (HASH_PICK(ip6->s6_addr[15], 0, 8) << 0); } - hash = rows[0] ^ rows[1] ^ rows[2] ^ rows[3] ^ rows[4] ^ rows[5] ^ rows[6] - ^ rows[7] ^ rows[8] ^ rows[9] ^ rows[10] ^ rows[11] ^ rows[12] - ^ rows[13] ^ rows[14]; + hash = rows[0] ^ rows[1] ^ rows[2] ^ rows[3] ^ rows[4] ^ + rows[5] ^ rows[6] ^ rows[7] ^ rows[8] ^ rows[9] ^ + rows[10] ^ rows[11] ^ rows[12] ^ rows[13] ^ rows[14]; } else { rows[11] = (HASH_PICK(ip6->s6_addr[11], 0, 4) << 5); rows[12] = (HASH_PICK(ip6->s6_addr[12], 3, 5) << 0); - rows[13] = (HASH_PICK(ip6->s6_addr[12], 0, 3) << 6) - | HASH_PICK(ip6->s6_addr[13], 2, 6); - rows[14] = (HASH_PICK(ip6->s6_addr[13], 0, 2) << 7) - | HASH_PICK(ip6->s6_addr[14], 1, 7); + rows[13] = (HASH_PICK(ip6->s6_addr[12], 0, 3) << 6) | + HASH_PICK(ip6->s6_addr[13], 2, 6); + rows[14] = (HASH_PICK(ip6->s6_addr[13], 0, 2) << 7) | + HASH_PICK(ip6->s6_addr[14], 1, 7); if (!move_dip) { - rows[15] = (HASH_PICK(ip6->s6_addr[14], 0, 1) << 8) - | (HASH_PICK(ip6->s6_addr[15], 0, 8) << 0); + rows[15] = (HASH_PICK(ip6->s6_addr[14], 0, 1) << 8) | + (HASH_PICK(ip6->s6_addr[15], 0, 8) << 0); } s0 = rows[12] + rows[13] + rows[14]; s1 = (s0 & 0x1ff) + ((s0 & (0x1ff << 9)) >> 9); pH = (s1 & 0x1ff) + ((s1 & (0x1ff << 9)) >> 9); - hash = rows[0] ^ rows[1] ^ rows[2] ^ rows[3] ^ rows[4] ^ rows[5] ^ rows[6] - ^ rows[7] ^ rows[8] ^ rows[9] ^ rows[10] ^ rows[11] ^ pH ^ rows[15]; + hash = rows[0] ^ rows[1] ^ rows[2] ^ rows[3] ^ rows[4] ^ + rows[5] ^ rows[6] ^ rows[7] ^ rows[8] ^ rows[9] ^ + rows[10] ^ rows[11] ^ pH ^ rows[15]; } return hash; } -/* - * Read a prefix route entry from the L3_PREFIX_ROUTE_IPUC table +/* Read a prefix route entry from the L3_PREFIX_ROUTE_IPUC table * We currently only support IPv4 and IPv6 unicast route */ static void rtl930x_route_read(int idx, struct rtl83xx_route *rt) @@ -1128,8 +1135,7 @@ static void rtl930x_net6_mask(int prefix_len, struct in6_addr *ip6_m) ip6_m->s6_addr[o] |= b ? 0xff00 >> b : 0x00; } -/* - * Read a host route entry from the table using its index +/* Read a host route entry from the table using its index * We currently only support IPv4 and IPv6 unicast route */ static void rtl930x_host_route_read(int idx, struct rtl83xx_route *rt) @@ -1181,8 +1187,7 @@ out: rtl_table_release(r); } -/* - * Write a host route entry from the table using its index +/* Write a host route entry from the table using its index * We currently only support IPv4 and IPv6 unicast route */ static void rtl930x_host_route_write(int idx, struct rtl83xx_route *rt) @@ -1237,8 +1242,7 @@ out: rtl_table_release(r); } -/* - * Look up the index of a prefix route in the routing table CAM for unicast IPv4/6 routes +/* Look up the index of a prefix route in the routing table CAM for unicast IPv4/6 routes * using hardware offload. */ static int rtl930x_route_lookup_hw(struct rtl83xx_route *rt) @@ -1317,8 +1321,7 @@ static int rtl930x_find_l3_slot(struct rtl83xx_route *rt, bool must_exist) return -1; } -/* - * Write a prefix route into the routing table CAM at position idx +/* Write a prefix route into the routing table CAM at position idx * Currently only IPv4 and IPv6 unicast routes are supported */ static void rtl930x_route_write(int idx, struct rtl83xx_route *rt) @@ -1400,8 +1403,7 @@ static void rtl930x_route_write(int idx, struct rtl83xx_route *rt) } -/* - * Get the destination MAC and L3 egress interface ID of a nexthop entry from +/* Get the destination MAC and L3 egress interface ID of a nexthop entry from * the SoC's L3_NEXTHOP table */ static void rtl930x_get_l3_nexthop(int idx, u16 *dmac_id, u16 *interface) @@ -1467,9 +1469,7 @@ static int rtl930x_l3_mtu_add(struct rtl838x_switch_priv *priv, int mtu) return mtu_id; } -/* - * Creates an interface for a route by setting up the HW tables in the SoC - */ +/* Creates an interface for a route by setting up the HW tables in the SoC */ static int rtl930x_l3_intf_add(struct rtl838x_switch_priv *priv, struct rtl838x_l3_intf *intf) { int i, intf_id, mtu_id; @@ -1501,8 +1501,7 @@ static int rtl930x_l3_intf_add(struct rtl838x_switch_priv *priv, struct rtl838x_ } } -/* - * Set the destination MAC and L3 egress interface ID for a nexthop entry in the SoC's +/* Set the destination MAC and L3 egress interface ID for a nexthop entry in the SoC's * L3_NEXTHOP table. The nexthop entry is identified by idx. * dmac_id is the reference to the L2 entry in the L2 forwarding table, special values are * 0x7ffe: TRAP2CPU @@ -1530,8 +1529,7 @@ static void rtl930x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int inde sw_w32_mask(0, BIT(block), RTL930X_PIE_BLK_LOOKUP_CTRL); } -/* - * Reads the intermediate representation of the templated match-fields of the +/* Reads the intermediate representation of the templated match-fields of the * PIE rule in the pie_rule structure and fills in the raw data fields in the * raw register space r[]. * The register space configuration size is identical for the RTL8380/90 and RTL9300, @@ -1624,7 +1622,6 @@ static void rtl930x_write_pie_templated(u32 r[], struct pie_rule *pr, enum templ data_m = pr->sip_m >> 16; } break; - case TEMPLATE_FIELD_SIP2: case TEMPLATE_FIELD_SIP3: case TEMPLATE_FIELD_SIP4: @@ -1634,7 +1631,6 @@ static void rtl930x_write_pie_templated(u32 r[], struct pie_rule *pr, enum templ data = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)]; data_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)]; break; - case TEMPLATE_FIELD_DIP0: if (pr->is_ipv6) { data = pr->dip6.s6_addr16[7]; @@ -1644,7 +1640,6 @@ static void rtl930x_write_pie_templated(u32 r[], struct pie_rule *pr, enum templ data_m = pr->dip_m; } break; - case TEMPLATE_FIELD_DIP1: if (pr->is_ipv6) { data = pr->dip6.s6_addr16[6]; @@ -1654,7 +1649,6 @@ static void rtl930x_write_pie_templated(u32 r[], struct pie_rule *pr, enum templ data_m = pr->dip_m >> 16; } break; - case TEMPLATE_FIELD_DIP2: case TEMPLATE_FIELD_DIP3: case TEMPLATE_FIELD_DIP4: @@ -1664,7 +1658,6 @@ static void rtl930x_write_pie_templated(u32 r[], struct pie_rule *pr, enum templ data = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)]; data_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)]; break; - case TEMPLATE_FIELD_IP_TOS_PROTO: data = pr->tos_proto; data_m = pr->tos_proto_m; @@ -1900,8 +1893,7 @@ static bool rtl930x_pie_templ_has(int t, enum template_field_id field_type) return false; } -/* - * Verify that the rule pr is compatible with a given template t in block block +/* Verify that the rule pr is compatible with a given template t in block block * Note that this function is SoC specific since the values of e.g. TEMPLATE_FIELD_SIP0 * depend on the SoC */ @@ -1917,13 +1909,17 @@ static int rtl930x_pie_verify_template(struct rtl838x_switch_priv *priv, return -1; if (pr->is_ipv6) { - if ((pr->sip6_m.s6_addr32[0] || pr->sip6_m.s6_addr32[1] - || pr->sip6_m.s6_addr32[2] || pr->sip6_m.s6_addr32[3]) - && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_SIP2)) + if ((pr->sip6_m.s6_addr32[0] || + pr->sip6_m.s6_addr32[1] || + pr->sip6_m.s6_addr32[2] || + pr->sip6_m.s6_addr32[3]) && + !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_SIP2)) return -1; - if ((pr->dip6_m.s6_addr32[0] || pr->dip6_m.s6_addr32[1] - || pr->dip6_m.s6_addr32[2] || pr->dip6_m.s6_addr32[3]) - && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_DIP2)) + if ((pr->dip6_m.s6_addr32[0] || + pr->dip6_m.s6_addr32[1] || + pr->dip6_m.s6_addr32[2] || + pr->dip6_m.s6_addr32[3]) && + !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_DIP2)) return -1; } @@ -1991,9 +1987,7 @@ static int rtl930x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rul return 0; } -/* - * Delete a range of Packet Inspection Engine rules - */ +/* Delete a range of Packet Inspection Engine rules */ static int rtl930x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to) { u32 v = (index_from << 1)| (index_to << 12 ) | BIT(0); @@ -2040,7 +2034,7 @@ static void rtl930x_pie_init(struct rtl838x_switch_priv *priv) // Assign blocks 0-7 to VACL phase (bit = 0), blocks 8-15 to IACL (bit = 1) sw_w32(0xff00, RTL930X_PIE_BLK_PHASE_CTRL); - + // Enable predefined templates 0, 1 for first quarter of all blocks template_selectors = 0 | (1 << 4); for (i = 0; i < priv->n_pie_blocks / 4; i++) @@ -2063,8 +2057,7 @@ static void rtl930x_pie_init(struct rtl838x_switch_priv *priv) } -/* - * Sets up an egress interface for L3 actions +/* Sets up an egress interface for L3 actions * Actions for ip4/6_icmp_redirect, ip4/6_pbr_icmp_redirect are: * 0: FORWARD, 1: DROP, 2: TRAP2CPU, 3: COPY2CPU, 4: TRAP2MASTERCPU 5: COPY2MASTERCPU * 6: HARDDROP @@ -2097,8 +2090,7 @@ static void rtl930x_set_l3_egress_intf(int idx, struct rtl838x_l3_intf *intf) rtl_table_release(r); } -/* - * Reads a MAC entry for L3 termination as entry point for routing +/* Reads a MAC entry for L3 termination as entry point for routing * from the hardware table * idx is the index into the L3_ROUTER_MAC table */ @@ -2121,18 +2113,17 @@ static void rtl930x_get_l3_router_mac(u32 idx, struct rtl93xx_rt_mac *m) m->vid = v & 0xfff; m->vid_mask = w & 0xfff; m->action = sw_r32(rtl_table_data(r, 6)) & 0x7; - m->mac_mask = ((((u64)sw_r32(rtl_table_data(r, 5))) << 32) & 0xffffffffffffULL) - | (sw_r32(rtl_table_data(r, 4))); - m->mac = ((((u64)sw_r32(rtl_table_data(r, 1))) << 32) & 0xffffffffffffULL) - | (sw_r32(rtl_table_data(r, 2))); + m->mac_mask = ((((u64)sw_r32(rtl_table_data(r, 5))) << 32) & 0xffffffffffffULL) | + (sw_r32(rtl_table_data(r, 4))); + m->mac = ((((u64)sw_r32(rtl_table_data(r, 1))) << 32) & 0xffffffffffffULL) | + (sw_r32(rtl_table_data(r, 2))); // Bits L3_INTF and BMSK_L3_INTF are 0 out: rtl_table_release(r); } -/* - * Writes a MAC entry for L3 termination as entry point for routing +/* Writes a MAC entry for L3 termination as entry point for routing * into the hardware table * idx is the index into the L3_ROUTER_MAC table */ @@ -2172,8 +2163,7 @@ static void rtl930x_set_l3_router_mac(u32 idx, struct rtl93xx_rt_mac *m) rtl_table_release(r); } -/* - * Get the Destination-MAC of an L3 egress interface or the Source MAC for routed packets +/* Get the Destination-MAC of an L3 egress interface or the Source MAC for routed packets * from the SoC's L3_EGR_INTF_MAC table * Indexes 0-2047 are DMACs, 2048+ are SMACs */ @@ -2192,8 +2182,8 @@ static u64 rtl930x_get_l3_egress_mac(u32 idx) return mac; } -/* - * Set the Destination-MAC of a route or the Source MAC of an L3 egress interface + +/* Set the Destination-MAC of a route or the Source MAC of an L3 egress interface * in the SoC's L3_EGR_INTF_MAC table * Indexes 0-2047 are DMACs, 2048+ are SMACs */ @@ -2211,8 +2201,7 @@ static void rtl930x_set_l3_egress_mac(u32 idx, u64 mac) rtl_table_release(r); } -/* - * Configure L3 routing settings of the device: +/* Configure L3 routing settings of the device: * - MTUs * - Egress interface * - The router's MAC address on which routed packets are expected @@ -2425,7 +2414,7 @@ static void rtl930x_led_init(struct rtl838x_switch_priv *priv) return; } - for (i= 0; i < priv->cpu_port; i++) { + for (i = 0; i < priv->cpu_port; i++) { pos = (i << 1) % 32; sw_w32_mask(0x3 << pos, 0, RTL930X_LED_PORT_FIB_SET_SEL_CTRL(i)); sw_w32_mask(0x3 << pos, 0, RTL930X_LED_PORT_COPR_SET_SEL_CTRL(i)); diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl931x.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl931x.c index ee8d6c2c737..802eecccd87 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl931x.c +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl931x.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only #include + #include "rtl83xx.h" #define RTL931X_VLAN_PORT_TAG_STS_INTERNAL 0x0 @@ -142,12 +143,12 @@ void rtl931x_vlan_profile_dump(int index) return; profile[0] = sw_r32(RTL931X_VLAN_PROFILE_SET(index)); - profile[1] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 4) & 0x1FFFFFFFULL) << 32 - | (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 8) & 0xFFFFFFFF); - profile[2] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 16) & 0x1FFFFFFFULL) << 32 - | (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 12) & 0xFFFFFFFF); - profile[3] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 20) & 0x1FFFFFFFULL) << 32 - | (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 24) & 0xFFFFFFFF); + profile[1] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 4) & 0x1FFFFFFFULL) << 32 | + (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 8) & 0xFFFFFFFF); + profile[2] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 16) & 0x1FFFFFFFULL) << 32 | + (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 12) & 0xFFFFFFFF); + profile[3] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 20) & 0x1FFFFFFFULL) << 32 | + (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 24) & 0xFFFFFFFF); pr_info("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %llx, \ IPv4 Unknown MultiCast Field %llx, IPv6 Unknown MultiCast Field: %llx", @@ -157,10 +158,10 @@ void rtl931x_vlan_profile_dump(int index) static void rtl931x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]) { int i; - u32 cmd = 1 << 20 /* Execute cmd */ - | 0 << 19 /* Read */ - | 5 << 15 /* Table type 0b101 */ - | (msti & 0x3fff); + u32 cmd = 1 << 20 | /* Execute cmd */ + 0 << 19 | /* Read */ + 5 << 15 | /* Table type 0b101 */ + (msti & 0x3fff); priv->r->exec_tbl0_cmd(cmd); for (i = 0; i < 4; i++) @@ -170,10 +171,10 @@ static void rtl931x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port static void rtl931x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]) { int i; - u32 cmd = 1 << 20 /* Execute cmd */ - | 1 << 19 /* Write */ - | 5 << 15 /* Table type 0b101 */ - | (msti & 0x3fff); + u32 cmd = 1 << 20 | /* Execute cmd */ + 1 << 19 | /* Write */ + 5 << 15 | /* Table type 0b101 */ + (msti & 0x3fff); for (i = 0; i < 4; i++) sw_w32(port_state[i], priv->r->tbl_access_data_0(i)); priv->r->exec_tbl0_cmd(cmd); @@ -316,6 +317,7 @@ irqreturn_t rtl931x_switch_irq(int irq, void *dev_id) } } } + return IRQ_HANDLED; } @@ -352,6 +354,7 @@ int rtl931x_write_phy(u32 port, u32 page, u32 reg, u32 val) err = -EIO; mutex_unlock(&smi_lock); + return err; } @@ -380,12 +383,11 @@ int rtl931x_read_phy(u32 port, u32 page, u32 reg, u32 *val) __func__, port, page, reg, *val, v); mutex_unlock(&smi_lock); + return 0; } -/* - * Read an mmd register of the PHY - */ +/* Read an mmd register of the PHY */ int rtl931x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val) { int err = 0; @@ -427,9 +429,7 @@ int rtl931x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val) return err; } -/* - * Write to an mmd register of the PHY - */ +/* Write to an mmd register of the PHY */ int rtl931x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val) { int err = 0; @@ -460,6 +460,7 @@ int rtl931x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val) pr_debug("%s: port %d, dev: %x, regnum: %x, val: %x (err %d)\n", __func__, port, devnum, mdiobus_c45_regad(regnum), val, err); mutex_unlock(&smi_lock); + return err; } @@ -538,12 +539,12 @@ u64 rtl931x_traffic_get(int source) rtl_table_read(r, source); v = sw_r32(rtl_table_data(r, 0)); rtl_table_release(r); - return v >> 3; + v = v >> 3; + + return v; } -/* - * Enable traffic between a source port and a destination port matrix - */ +/* Enable traffic between a source port and a destination port matrix */ void rtl931x_traffic_set(int source, u64 dest_matrix) { struct table_reg *r = rtl_table_get(RTL9310_TBL_0, 6); @@ -581,8 +582,7 @@ static u64 rtl931x_l2_hash_seed(u64 mac, u32 vid) return v; } -/* - * Calculate both the block 0 and the block 1 hash by applyingthe same hash +/* Calculate both the block 0 and the block 1 hash by applyingthe same hash * algorithm as the one used currently by the ASIC to the seed, and return * both hashes in the lower and higher word of the return value since only 12 bit of * the hash are significant. @@ -629,9 +629,7 @@ static u32 rtl931x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed) return h; } -/* - * Fills an L2 entry structure from the SoC registers - */ +/* Fills an L2 entry structure from the SoC registers */ static void rtl931x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e) { pr_debug("In %s valid?\n", __func__); @@ -697,9 +695,7 @@ static void rtl931x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e) } } -/* - * Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry - */ +/* Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry */ static void rtl931x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e) { u32 port; @@ -711,9 +707,12 @@ static void rtl931x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e) r[2] = BIT(31); // Set valid bit - r[0] = ((u32)e->mac[0]) << 24 | ((u32)e->mac[1]) << 16 - | ((u32)e->mac[2]) << 8 | ((u32)e->mac[3]); - r[1] = ((u32)e->mac[4]) << 24 | ((u32)e->mac[5]) << 16; + r[0] = ((u32)e->mac[0]) << 24 | + ((u32)e->mac[1]) << 16 | + ((u32)e->mac[2]) << 8 | + ((u32)e->mac[3]); + r[1] = ((u32)e->mac[4]) << 24 | + ((u32)e->mac[5]) << 16; r[2] |= e->next_hop ? BIT(12) : 0; @@ -744,8 +743,7 @@ static void rtl931x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e) } } -/* - * Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table +/* Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table * hash is the id of the bucket and pos is the position of the entry in that bucket * The data read from the SoC is filled into rtl838x_l2_entry */ @@ -762,7 +760,8 @@ static u64 rtl931x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2 /* On the RTL93xx, 2 different hash algorithms are used making it a total of * 8 buckets that need to be searched, 4 for each hash-half - * Use second hash space when bucket is between 4 and 8 */ + * Use second hash space when bucket is between 4 and 8 + */ if (pos >= 4) { pos -= 4; hash >>= 16; @@ -785,18 +784,23 @@ static u64 rtl931x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2 if (!e->valid) return 0; - mac = ((u64)e->mac[0]) << 40 | ((u64)e->mac[1]) << 32 | ((u64)e->mac[2]) << 24 - | ((u64)e->mac[3]) << 16 | ((u64)e->mac[4]) << 8 | ((u64)e->mac[5]); + mac = ((u64)e->mac[0]) << 40 | + ((u64)e->mac[1]) << 32 | + ((u64)e->mac[2]) << 24 | + ((u64)e->mac[3]) << 16 | + ((u64)e->mac[4]) << 8 | + ((u64)e->mac[5]); seed = rtl931x_l2_hash_seed(mac, e->rvid); pr_debug("%s: mac %016llx, seed %016llx\n", __func__, mac, seed); + // return vid with concatenated mac as unique id return seed; } static u64 rtl931x_read_cam(int idx, struct rtl838x_l2_entry *e) { - return 0; + return 0; } static void rtl931x_write_cam(int idx, struct rtl838x_l2_entry *e) @@ -817,12 +821,11 @@ static void rtl931x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_ rtl931x_fill_l2_row(r, e); pr_info("%s: %d: %08x %08x %08x\n", __func__, idx, r[0], r[1], r[2]); - for (i= 0; i < 4; i++) + for (i = 0; i < 4; i++) sw_w32(r[i], rtl_table_data(q, i)); rtl_table_write(q, idx); rtl_table_release(q); - } static void rtl931x_vlan_fwd_on_inner(int port, bool is_set) @@ -857,7 +860,7 @@ static void rtl931x_vlan_profile_setup(int profile) p[5] = 0x1FFFFFF; // IPv6 unknwon MC flooding portmask p[6] = 0xFFFFFFFF; - for (i = 0; i < 7; i++) + for (int i = 0; i < 7; i++) sw_w32(p[i], RTL931X_VLAN_PROFILE_SET(profile) + i * 4); pr_info("Leaving %s\n", __func__); } @@ -888,6 +891,7 @@ static u64 rtl931x_read_mcast_pmask(int idx) rtl_table_release(q); pr_debug("%s: Index idx %d has portmask %016llx\n", __func__, idx, portmask); + return portmask; } @@ -919,6 +923,7 @@ static int rtl931x_set_ageing_time(unsigned long msec) t = t > 0x1FFFFF ? 0x1FFFFF : t; sw_w32_mask(0x1FFFFF, t, RTL931X_L2_AGE_CTRL); pr_debug("Dynamic aging for ports: %x\n", sw_r32(RTL931X_L2_PORT_AGE_CTRL)); + return 0; } void rtl931x_sw_init(struct rtl838x_switch_priv *priv) @@ -933,8 +938,7 @@ static void rtl931x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int inde sw_w32_mask(0, BIT(block), RTL931X_PIE_BLK_LOOKUP_CTRL); } -/* - * Fills the data in the intermediate representation in the pie_rule structure +/* Fills the data in the intermediate representation in the pie_rule structure * into a data field for a given template field field_type * TODO: This function looks very similar to the function of the rtl9300, but * since it uses the physical template_field_id, which are different for each @@ -1031,7 +1035,6 @@ int rtl931x_pie_data_fill(enum template_field_id field_type, struct pie_rule *pr *data = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)]; *data_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)]; break; - case TEMPLATE_FIELD_DIP0: if (pr->is_ipv6) { *data = pr->dip6.s6_addr16[7]; @@ -1050,7 +1053,6 @@ int rtl931x_pie_data_fill(enum template_field_id field_type, struct pie_rule *pr *data_m = pr->dip_m >> 16; } break; - case TEMPLATE_FIELD_DIP2: case TEMPLATE_FIELD_DIP3: case TEMPLATE_FIELD_DIP4: @@ -1060,7 +1062,6 @@ int rtl931x_pie_data_fill(enum template_field_id field_type, struct pie_rule *pr *data = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)]; *data_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)]; break; - case TEMPLATE_FIELD_IP_TOS_PROTO: *data = pr->tos_proto; *data_m = pr->tos_proto_m; @@ -1092,8 +1093,7 @@ int rtl931x_pie_data_fill(enum template_field_id field_type, struct pie_rule *pr return 0; } -/* - * Reads the intermediate representation of the templated match-fields of the +/* Reads the intermediate representation of the templated match-fields of the * PIE rule in the pie_rule structure and fills in the raw data fields in the * raw register space r[]. * The register space configuration size is identical for the RTL8380/90 and RTL9300, @@ -1310,8 +1310,7 @@ static bool rtl931x_pie_templ_has(int t, enum template_field_id field_type) return false; } -/* - * Verify that the rule pr is compatible with a given template t in block block +/* Verify that the rule pr is compatible with a given template t in block block * Note that this function is SoC specific since the values of e.g. TEMPLATE_FIELD_SIP0 * depend on the SoC */ @@ -1327,13 +1326,17 @@ static int rtl931x_pie_verify_template(struct rtl838x_switch_priv *priv, return -1; if (pr->is_ipv6) { - if ((pr->sip6_m.s6_addr32[0] || pr->sip6_m.s6_addr32[1] - || pr->sip6_m.s6_addr32[2] || pr->sip6_m.s6_addr32[3]) - && !rtl931x_pie_templ_has(t, TEMPLATE_FIELD_SIP2)) + if ((pr->sip6_m.s6_addr32[0] || + pr->sip6_m.s6_addr32[1] || + pr->sip6_m.s6_addr32[2] || + pr->sip6_m.s6_addr32[3]) && + !rtl931x_pie_templ_has(t, TEMPLATE_FIELD_SIP2)) return -1; - if ((pr->dip6_m.s6_addr32[0] || pr->dip6_m.s6_addr32[1] - || pr->dip6_m.s6_addr32[2] || pr->dip6_m.s6_addr32[3]) - && !rtl931x_pie_templ_has(t, TEMPLATE_FIELD_DIP2)) + if ((pr->dip6_m.s6_addr32[0] || + pr->dip6_m.s6_addr32[1] || + pr->dip6_m.s6_addr32[2] || + pr->dip6_m.s6_addr32[3]) && + !rtl931x_pie_templ_has(t, TEMPLATE_FIELD_DIP2)) return -1; } @@ -1398,12 +1401,11 @@ static int rtl931x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rul rtl931x_pie_rule_write(priv, idx, pr); mutex_unlock(&priv->pie_mutex); + return 0; } -/* - * Delete a range of Packet Inspection Engine rules - */ +/* Delete a range of Packet Inspection Engine rules */ static int rtl931x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to) { u32 v = (index_from << 1)| (index_to << 13 ) | BIT(0); @@ -1419,6 +1421,7 @@ static int rtl931x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from } while (sw_r32(RTL931X_PIE_CLR_CTRL) & BIT(0)); mutex_unlock(&priv->reg_mutex); + return 0; } @@ -1533,7 +1536,7 @@ void rtl931x_set_distribution_algorithm(int group, int algoidx, u32 algomsk) u32 newmask = 0; /* TODO: for now we set algoidx to 0 */ - algoidx=0; + algoidx = 0; if (algomsk & TRUNK_DISTRIBUTION_ALGO_SIP_BIT) { l3shift = 4; @@ -1584,7 +1587,7 @@ static void rtl931x_led_init(struct rtl838x_switch_priv *priv) return; } - for (i= 0; i < priv->cpu_port; i++) { + for (i = 0; i < priv->cpu_port; i++) { pos = (i << 1) % 32; sw_w32_mask(0x3 << pos, 0, RTL931X_LED_PORT_FIB_SET_SEL_CTRL(i)); sw_w32_mask(0x3 << pos, 0, RTL931X_LED_PORT_COPR_SET_SEL_CTRL(i)); @@ -1626,7 +1629,6 @@ static void rtl931x_led_init(struct rtl838x_switch_priv *priv) for (i = 0; i < 32; i++) pr_info("%s %08x: %08x\n",__func__, 0xbb000600 + i * 4, sw_r32(0x0600 + i * 4)); - } const struct rtl838x_reg rtl931x_reg = { @@ -1698,4 +1700,3 @@ const struct rtl838x_reg rtl931x_reg = { .l3_setup = rtl931x_l3_setup, .led_init = rtl931x_led_init, }; - diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/tc.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/tc.c index d0a8ee8cfe4..401fb4553c5 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/tc.c +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/tc.c @@ -5,14 +5,12 @@ #include #include #include - #include + #include "rtl83xx.h" #include "rtl838x.h" -/* - * Parse the flow rule for the matching conditions - */ +/* Parse the flow rule for the matching conditions */ static int rtl83xx_parse_flow_rule(struct rtl838x_switch_priv *priv, struct flow_rule *rule, struct rtl83xx_flow *flow) { @@ -44,8 +42,7 @@ static int rtl83xx_parse_flow_rule(struct rtl838x_switch_priv *priv, flow->rule.frame_type_l4 = 0; if (match.key->ip_proto == IPPROTO_TCP) flow->rule.frame_type_l4 = 1; - if (match.key->ip_proto == IPPROTO_ICMP - || match.key->ip_proto ==IPPROTO_ICMPV6) + if (match.key->ip_proto == IPPROTO_ICMP || match.key->ip_proto == IPPROTO_ICMPV6) flow->rule.frame_type_l4 = 2; if (match.key->ip_proto == IPPROTO_TCP) flow->rule.frame_type_l4 = 3; @@ -150,7 +147,7 @@ static int rtl83xx_add_flow(struct rtl838x_switch_priv *priv, struct flow_cls_of pr_debug("%s\n", __func__); rtl83xx_parse_flow_rule(priv, rule, flow); - + flow_action_for_each(i, act, &rule->action) { switch (act->id) { case FLOW_ACTION_DROP: @@ -288,6 +285,7 @@ out_free: kfree(flow); out: pr_err("%s: error %d\n", __func__, err); + return err; } @@ -311,6 +309,7 @@ static int rtl83xx_delete_flower(struct rtl838x_switch_priv *priv, kfree_rcu(flow, rcu_head); rcu_read_unlock(); + return 0; } @@ -335,7 +334,8 @@ static int rtl83xx_stats_flower(struct rtl838x_switch_priv *priv, // TODO: We need a second PIE rule to count the bytes flow_stats_update(&cls_flower->stats, 100 * new_packets, new_packets, 0, lastused, - FLOW_ACTION_HW_STATS_IMMEDIATE); + FLOW_ACTION_HW_STATS_IMMEDIATE); + return 0; } diff --git a/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.c b/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.c index 32de5cc5549..6cd649db541 100644 --- a/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.c +++ b/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* - * linux/drivers/net/ethernet/rtl838x_eth.c +/* linux/drivers/net/ethernet/rtl838x_eth.c * Copyright (C) 2020 B. Koblitz */ @@ -26,8 +25,7 @@ extern struct rtl83xx_soc_info soc_info; -/* - * Maximum number of RX rings is 8 on RTL83XX and 32 on the 93XX +/* Maximum number of RX rings is 8 on RTL83XX and 32 on the 93XX * The ring is assigned by switch based on packet/port priortity * Maximum number of TX rings is 2, Ring 2 being the high priority * ring on the RTL93xx SoCs. MAX_RXLEN gives the maximum length @@ -179,9 +177,9 @@ struct rtl838x_rx_q { struct rtl838x_eth_priv { struct net_device *netdev; struct platform_device *pdev; - void *membase; - spinlock_t lock; - struct mii_bus *mii_bus; + void *membase; + spinlock_t lock; + struct mii_bus *mii_bus; struct rtl838x_rx_q rx_qs[MAX_RXRINGS]; struct phylink *phylink; struct phylink_config phylink_config; @@ -213,8 +211,7 @@ extern int rtl930x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val); extern int rtl931x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val); extern int rtl931x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val); -/* - * On the RTL93XX, the RTL93XX_DMA_IF_RX_RING_CNTR track the fill level of +/* On the RTL93XX, the RTL93XX_DMA_IF_RX_RING_CNTR track the fill level of * the rings. Writing x into these registers substracts x from its content. * When the content reaches the ring size, the ASIC no longer adds * packets to this receive queue. @@ -329,8 +326,7 @@ bool rtl931x_decode_tag(struct p_hdr *h, struct dsa_tag *t) return t->l2_offloaded; } -/* - * Discard the RX ring-buffers, called as part of the net-ISR +/* Discard the RX ring-buffers, called as part of the net-ISR * when the buffer runs over */ static void rtl838x_rb_cleanup(struct rtl838x_eth_priv *priv, int status) @@ -349,15 +345,16 @@ static void rtl838x_rb_cleanup(struct rtl838x_eth_priv *priv, int status) pr_debug("Got something: %d\n", ring->c_rx[r]); h = &ring->rx_header[r][ring->c_rx[r]]; memset(h, 0, sizeof(struct p_hdr)); - h->buf = (u8 *)KSEG1ADDR(ring->rx_space - + r * priv->rxringlen * RING_BUFFER - + ring->c_rx[r] * RING_BUFFER); + h->buf = (u8 *)KSEG1ADDR(ring->rx_space + + r * priv->rxringlen * RING_BUFFER + + ring->c_rx[r] * RING_BUFFER); h->size = RING_BUFFER; /* make sure the header is visible to the ASIC */ mb(); - ring->rx_r[r][ring->c_rx[r]] = KSEG1ADDR(h) | 0x1 - | (ring->c_rx[r] == (priv->rxringlen - 1) ? WRAP : 0x1); + ring->rx_r[r][ring->c_rx[r]] = KSEG1ADDR(h) | 0x1 | (ring->c_rx[r] == (priv->rxringlen - 1) ? + WRAP : + 0x1); ring->c_rx[r] = (ring->c_rx[r] + 1) % priv->rxringlen; } while (&ring->rx_r[r][ring->c_rx[r]] != last); } @@ -520,7 +517,7 @@ static irqreturn_t rtl93xx_net_irq(int irq, void *dev_id) /* RX buffer overrun */ if (status_rx_r) { pr_debug("RX buffer overrun: status %x, mask: %x\n", - status_rx_r, sw_r32(priv->r->dma_if_intr_rx_runout_msk)); + status_rx_r, sw_r32(priv->r->dma_if_intr_rx_runout_msk)); sw_w32(status_rx_r, priv->r->dma_if_intr_rx_runout_sts); rtl838x_rb_cleanup(priv, status_rx_r); } @@ -645,7 +642,7 @@ static void rtl838x_hw_reset(struct rtl838x_eth_priv *priv) u32 int_saved, nbuf; u32 reset_mask; int i, pos; - + pr_info("RESETTING %x, CPU_PORT %d\n", priv->family_id, priv->cpu_port); sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(priv->cpu_port)); mdelay(100); @@ -699,7 +696,7 @@ static void rtl838x_hw_reset(struct rtl838x_eth_priv *priv) pos = (i % 3) * 10; sw_w32_mask(0x3ff << pos, 0, priv->r->dma_if_rx_ring_size(i)); sw_w32_mask(0x3ff << pos, priv->rxringlen, - priv->r->dma_if_rx_ring_cntr(i)); + priv->r->dma_if_rx_ring_cntr(i)); } } @@ -821,20 +818,20 @@ static void rtl93xx_hw_en_rxtx(struct rtl838x_eth_priv *priv) static void rtl838x_setup_ring_buffer(struct rtl838x_eth_priv *priv, struct ring_b *ring) { int i, j; - struct p_hdr *h; for (i = 0; i < priv->rxrings; i++) { for (j = 0; j < priv->rxringlen; j++) { h = &ring->rx_header[i][j]; memset(h, 0, sizeof(struct p_hdr)); - h->buf = (u8 *)KSEG1ADDR(ring->rx_space - + i * priv->rxringlen * RING_BUFFER - + j * RING_BUFFER); + h->buf = (u8 *)KSEG1ADDR(ring->rx_space + + i * priv->rxringlen * RING_BUFFER + + j * RING_BUFFER); h->size = RING_BUFFER; /* All rings owned by switch, last one wraps */ - ring->rx_r[i][j] = KSEG1ADDR(h) | 1 - | (j == (priv->rxringlen - 1) ? WRAP : 0); + ring->rx_r[i][j] = KSEG1ADDR(h) | 1 | (j == (priv->rxringlen - 1) ? + WRAP : + 0); } ring->c_rx[i] = 0; } @@ -843,14 +840,14 @@ static void rtl838x_setup_ring_buffer(struct rtl838x_eth_priv *priv, struct ring for (j = 0; j < TXRINGLEN; j++) { h = &ring->tx_header[i][j]; memset(h, 0, sizeof(struct p_hdr)); - h->buf = (u8 *)KSEG1ADDR(ring->tx_space - + i * TXRINGLEN * RING_BUFFER - + j * RING_BUFFER); + h->buf = (u8 *)KSEG1ADDR(ring->tx_space + + i * TXRINGLEN * RING_BUFFER + + j * RING_BUFFER); h->size = RING_BUFFER; ring->tx_r[i][j] = KSEG1ADDR(&ring->tx_header[i][j]); } /* Last header is wrapping around */ - ring->tx_r[i][j-1] |= WRAP; + ring->tx_r[i][j - 1] |= WRAP; ring->c_tx[i] = 0; } } @@ -1032,8 +1029,7 @@ static int rtl838x_eth_stop(struct net_device *ndev) static void rtl838x_eth_set_multicast_list(struct net_device *ndev) { - /* - * Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F}) + /* Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F}) * CTRL_0_FULL = GENMASK(21, 0) = 0x3FFFFF */ if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) { @@ -1050,8 +1046,7 @@ static void rtl838x_eth_set_multicast_list(struct net_device *ndev) static void rtl839x_eth_set_multicast_list(struct net_device *ndev) { - /* - * Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F}) + /* Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F}) * CTRL_0_FULL = GENMASK(31, 2) = 0xFFFFFFFC * Lower two bits are reserved, corresponding to RMA 01-80-C2-00-00-00 * CTRL_1_FULL = CTRL_2_FULL = GENMASK(31, 0) @@ -1077,8 +1072,7 @@ static void rtl839x_eth_set_multicast_list(struct net_device *ndev) static void rtl930x_eth_set_multicast_list(struct net_device *ndev) { - /* - * Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F}) + /* Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F}) * CTRL_0_FULL = GENMASK(31, 2) = 0xFFFFFFFC * Lower two bits are reserved, corresponding to RMA 01-80-C2-00-00-00 * CTRL_1_FULL = CTRL_2_FULL = GENMASK(31, 0) @@ -1096,8 +1090,7 @@ static void rtl930x_eth_set_multicast_list(struct net_device *ndev) static void rtl931x_eth_set_multicast_list(struct net_device *ndev) { - /* - * Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F}) + /* Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F}) * CTRL_0_FULL = GENMASK(31, 2) = 0xFFFFFFFC * Lower two bits are reserved, corresponding to RMA 01-80-C2-00-00-00. * CTRL_1_FULL = CTRL_2_FULL = GENMASK(31, 0) @@ -1147,13 +1140,14 @@ static int rtl838x_eth_tx(struct sk_buff *skb, struct net_device *dev) len = skb->len; /* Check for DSA tagging at the end of the buffer */ - if (netdev_uses_dsa(dev) && skb->data[len-4] == 0x80 - && skb->data[len-3] < priv->cpu_port - && skb->data[len-2] == 0x10 - && skb->data[len-1] == 0x00) { + if (netdev_uses_dsa(dev) && + skb->data[len - 4] == 0x80 && + skb->data[len - 3] < priv->cpu_port && + skb->data[len - 2] == 0x10 && + skb->data[len - 1] == 0x00) { /* Reuse tag space for CRC if possible */ - dest_port = skb->data[len-3]; - skb->data[len-4] = skb->data[len-3] = skb->data[len-2] = skb->data[len-1] = 0x00; + dest_port = skb->data[len - 3]; + skb->data[len - 4] = skb->data[len - 3] = skb->data[len - 2] = skb->data[len - 1] = 0x00; len -= 4; } @@ -1198,8 +1192,7 @@ static int rtl838x_eth_tx(struct sk_buff *skb, struct net_device *dev) } /* Tell switch to send data */ - if (priv->family_id == RTL9310_FAMILY_ID - || priv->family_id == RTL9300_FAMILY_ID) { + if (priv->family_id == RTL9310_FAMILY_ID || priv->family_id == RTL9300_FAMILY_ID) { // Ring ID q == 0: Low priority, Ring ID = 1: High prio queue if (!q) sw_w32_mask(0, BIT(2), priv->r->dma_if_ctrl); @@ -1218,13 +1211,14 @@ static int rtl838x_eth_tx(struct sk_buff *skb, struct net_device *dev) dev_warn(&priv->pdev->dev, "Data is owned by switch\n"); ret = NETDEV_TX_BUSY; } + txdone: spin_unlock_irqrestore(&priv->lock, flags); + return ret; } -/* - * Return queue number for TX. On the RTL83XX, these queues have equal priority +/* Return queue number for TX. On the RTL83XX, these queues have equal priority * so we do round-robin */ u16 rtl83xx_pick_tx_queue(struct net_device *dev, struct sk_buff *skb, @@ -1236,14 +1230,14 @@ u16 rtl83xx_pick_tx_queue(struct net_device *dev, struct sk_buff *skb, return last % TXRINGS; } -/* - * Return queue number for TX. On the RTL93XX, queue 1 is the high priority queue +/* Return queue number for TX. On the RTL93XX, queue 1 is the high priority queue */ u16 rtl93xx_pick_tx_queue(struct net_device *dev, struct sk_buff *skb, struct net_device *sb_dev) { if (skb->priority >= TC_PRIO_CONTROL) return 1; + return 0; } @@ -1291,7 +1285,7 @@ static int rtl838x_hw_receive(struct net_device *dev, int r, int budget) skb_reserve(skb, NET_IP_ALIGN); if (likely(skb)) { - /* BUG: Prevent bug on RTL838x SoCs*/ + /* BUG: Prevent bug on RTL838x SoCs */ if (priv->family_id == RTL8380_FAMILY_ID) { sw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0)); for (i = 0; i < priv->rxrings; i++) { @@ -1308,12 +1302,12 @@ static int rtl838x_hw_receive(struct net_device *dev, int r, int budget) /* Overwrite CRC with cpu_tag */ if (dsa) { priv->r->decode_tag(h, &tag); - skb->data[len-4] = 0x80; - skb->data[len-3] = tag.port; - skb->data[len-2] = 0x10; - skb->data[len-1] = 0x00; + skb->data[len - 4] = 0x80; + skb->data[len - 3] = tag.port; + skb->data[len - 2] = 0x10; + skb->data[len - 1] = 0x00; if (tag.l2_offloaded) - skb->data[len-3] |= 0x40; + skb->data[len - 3] |= 0x40; } if (tag.queue >= 0) @@ -1342,8 +1336,9 @@ static int rtl838x_hw_receive(struct net_device *dev, int r, int budget) h->buf = data; h->size = RING_BUFFER; - ring->rx_r[r][ring->c_rx[r]] = KSEG1ADDR(h) | 0x1 - | (ring->c_rx[r] == (priv->rxringlen - 1) ? WRAP : 0x1); + ring->rx_r[r][ring->c_rx[r]] = KSEG1ADDR(h) | 0x1 | (ring->c_rx[r] == (priv->rxringlen - 1) ? + WRAP : + 0x1); ring->c_rx[r] = (ring->c_rx[r] + 1) % priv->rxringlen; last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4)); } while (&ring->rx_r[r][ring->c_rx[r]] != last && work_done < budget); @@ -1382,6 +1377,7 @@ static int rtl838x_poll_rx(struct napi_struct *napi, int budget) else sw_w32_mask(0, 0xf00ff | BIT(r + 8), priv->r->dma_if_intr_msk); } + return work_done; } @@ -1568,6 +1564,7 @@ static int rtl838x_set_mac_address(struct net_device *dev, void *p) rtl838x_set_mac_hw(dev, mac); pr_info("Using MAC %08x%08x\n", sw_r32(priv->r->mac), sw_r32(priv->r->mac + 4)); + return 0; } @@ -1584,7 +1581,7 @@ static int rtl8380_init_mac(struct rtl838x_eth_priv *priv) if (priv->family_id == 0x8390) return rtl8390_init_mac(priv); - // At present we do not know how to set up EEE on any other SoC than RTL8380 + /* At present we do not know how to set up EEE on any other SoC than RTL8380 */ if (priv->family_id != 0x8380) return 0; @@ -1602,6 +1599,7 @@ static int rtl8380_init_mac(struct rtl838x_eth_priv *priv) for (i = 8; i <= 28; i++) sw_w32(0, 0xd57c + i * 0x80); } + return 0; } @@ -1611,6 +1609,7 @@ static int rtl838x_get_link_ksettings(struct net_device *ndev, struct rtl838x_eth_priv *priv = netdev_priv(ndev); pr_debug("%s called\n", __func__); + return phylink_ethtool_ksettings_get(priv->phylink, cmd); } @@ -1620,6 +1619,7 @@ static int rtl838x_set_link_ksettings(struct net_device *ndev, struct rtl838x_eth_priv *priv = netdev_priv(ndev); pr_debug("%s called\n", __func__); + return phylink_ethtool_ksettings_set(priv->phylink, cmd); } @@ -1645,6 +1645,7 @@ static int rtl838x_mdio_read_paged(struct mii_bus *bus, int mii_id, u16 page, in } if (err) return err; + return val; } @@ -1673,8 +1674,10 @@ static int rtl839x_mdio_read_paged(struct mii_bus *bus, int mii_id, u16 page, in err = rtl839x_read_phy(mii_id, page, regnum, &val); pr_debug("PHY: %d register %x read %x, err %d\n", mii_id, regnum, val, err); } - if (err) + + if (err) return err; + return val; } @@ -1703,8 +1706,10 @@ static int rtl930x_mdio_read_paged(struct mii_bus *bus, int mii_id, u16 page, in err = rtl930x_read_phy(mii_id, page, regnum, &val); pr_debug("PHY: %d register %x read %x, err %d\n", mii_id, regnum, val, err); } + if (err) return err; + return val; } @@ -1744,6 +1749,7 @@ static int rtl931x_mdio_read_paged(struct mii_bus *bus, int mii_id, u16 page, in if (err) return err; + return val; } @@ -1777,6 +1783,7 @@ static int rtl838x_mdio_write_paged(struct mii_bus *bus, int mii_id, u16 page, } err = rtl838x_write_phy(mii_id, page, regnum, value); pr_debug("PHY: %d register %x write %x, err %d\n", mii_id, regnum, value, err); + return err; } @@ -1807,6 +1814,7 @@ static int rtl839x_mdio_write_paged(struct mii_bus *bus, int mii_id, u16 page, err = rtl839x_write_phy(mii_id, page, regnum, value); pr_debug("PHY: %d register %x write %x, err %d\n", mii_id, regnum, value, err); + return err; } @@ -1831,6 +1839,7 @@ static int rtl930x_mdio_write_paged(struct mii_bus *bus, int mii_id, u16 page, err = rtl930x_write_phy(mii_id, page, regnum, value); pr_debug("PHY: %d register %x write %x, err %d\n", mii_id, regnum, value, err); + return err; } @@ -1861,6 +1870,7 @@ static int rtl931x_mdio_write_paged(struct mii_bus *bus, int mii_id, u16 page, err = rtl931x_write_phy(mii_id, page, regnum, value); pr_debug("PHY: %d register %x write %x, err %d\n", mii_id, regnum, value, err); + return err; } @@ -1951,7 +1961,6 @@ static int rtl930x_mdio_reset(struct mii_bus *bus) switch (priv->interfaces[i]) { case PHY_INTERFACE_MODE_10GBASER: break; // Serdes: Value = 0 - case PHY_INTERFACE_MODE_HSGMII: private_poll_mask |= BIT(i); // fallthrough @@ -1959,12 +1968,10 @@ static int rtl930x_mdio_reset(struct mii_bus *bus) v |= BIT(mac_type_bit[i]); uses_usxgmii = true; break; - case PHY_INTERFACE_MODE_QSGMII: private_poll_mask |= BIT(i); v |= 3 << mac_type_bit[i]; break; - default: break; } @@ -1976,7 +1983,8 @@ static int rtl930x_mdio_reset(struct mii_bus *bus) /* The following magic values are found in the port configuration, they seem to * define different ways of polling a PHY. The below is for the Aquantia PHYs of - * the XGS1250 and the RTL8226 of the XGS1210 */ + * the XGS1250 and the RTL8226 of the XGS1210 + */ if (uses_usxgmii) { sw_w32(0x01010000, RTL930X_SMI_10GPHY_POLLING_REG0_CFG); sw_w32(0x01E7C400, RTL930X_SMI_10GPHY_POLLING_REG9_CFG); @@ -2004,6 +2012,7 @@ static int rtl930x_mdio_reset(struct mii_bus *bus) sw_r32(RTL930X_SMI_10GPHY_POLLING_REG10_CFG)); pr_debug("%s: RTL930X_SMI_PRVTE_POLLING_CTRL %08x\n", __func__, sw_r32(RTL930X_SMI_PRVTE_POLLING_CTRL)); + return 0; } @@ -2057,10 +2066,10 @@ static int rtl931x_mdio_reset(struct mii_bus *bus) pr_info("c45_mask: %08x, RTL931X_SMI_GLB_CTRL0 was %X", c45_mask, sw_r32(RTL931X_SMI_GLB_CTRL0)); /* We have a 10G PHY enable polling - sw_w32(0x01010000, RTL931X_SMI_10GPHY_POLLING_SEL2); - sw_w32(0x01E7C400, RTL931X_SMI_10GPHY_POLLING_SEL3); - sw_w32(0x01E7E820, RTL931X_SMI_10GPHY_POLLING_SEL4); -*/ + * sw_w32(0x01010000, RTL931X_SMI_10GPHY_POLLING_SEL2); + * sw_w32(0x01E7C400, RTL931X_SMI_10GPHY_POLLING_SEL3); + * sw_w32(0x01E7E820, RTL931X_SMI_10GPHY_POLLING_SEL4); + */ sw_w32_mask(0xff, c45_mask, RTL931X_SMI_GLB_CTRL1); return 0; @@ -2221,6 +2230,7 @@ static int rtl838x_mdio_init(struct rtl838x_eth_priv *priv) err_put_node: of_node_put(mii_np); + return ret; } @@ -2358,7 +2368,7 @@ static int __init rtl838x_eth_probe(struct platform_device *pdev) return -EINVAL; } - rxrings = (soc_info.family == RTL8380_FAMILY_ID + rxrings = (soc_info.family == RTL8380_FAMILY_ID || soc_info.family == RTL8390_FAMILY_ID) ? 8 : 32; rxrings = rxrings > MAX_RXRINGS ? MAX_RXRINGS : rxrings; rxringlen = MAX_ENTRIES / rxrings; @@ -2392,9 +2402,9 @@ static int __init rtl838x_eth_probe(struct platform_device *pdev) } /* Allocate buffer memory */ - priv->membase = dmam_alloc_coherent(&pdev->dev, rxrings * rxringlen * RING_BUFFER - + sizeof(struct ring_b) + sizeof(struct notify_b), - (void *)&dev->mem_start, GFP_KERNEL); + priv->membase = dmam_alloc_coherent(&pdev->dev, rxrings * rxringlen * RING_BUFFER + + sizeof(struct ring_b) + sizeof(struct notify_b), + (void *)&dev->mem_start, GFP_KERNEL); if (!priv->membase) { dev_err(&pdev->dev, "cannot allocate DMA buffer\n"); err = -ENOMEM; @@ -2469,7 +2479,7 @@ static int __init rtl838x_eth_probe(struct platform_device *pdev) rtl8380_init_mac(priv); - /* try to get mac address in the following order: + /* Try to get mac address in the following order: * 1) from device tree data * 2) from internal registers set by bootloader */ @@ -2540,6 +2550,7 @@ static int __init rtl838x_eth_probe(struct platform_device *pdev) err_free: pr_err("Error setting up netdev, freeing it again.\n"); free_netdev(dev); + return err; } @@ -2562,6 +2573,7 @@ static int rtl838x_eth_remove(struct platform_device *pdev) unregister_netdev(dev); free_netdev(dev); } + return 0; } diff --git a/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.h b/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.h index d00d11d0c82..fbd2bcadd6d 100644 --- a/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.h +++ b/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.h @@ -3,9 +3,7 @@ #ifndef _RTL838X_ETH_H #define _RTL838X_ETH_H -/* - * Register definition - */ +/* Register definition */ /* Per port MAC control */ #define RTL838X_MAC_PORT_CTRL (0xd560) diff --git a/target/linux/realtek/files-5.15/drivers/net/phy/rtl83xx-phy.c b/target/linux/realtek/files-5.15/drivers/net/phy/rtl83xx-phy.c index 491ceb48b6a..38012d75d0e 100644 --- a/target/linux/realtek/files-5.15/drivers/net/phy/rtl83xx-phy.c +++ b/target/linux/realtek/files-5.15/drivers/net/phy/rtl83xx-phy.c @@ -36,8 +36,7 @@ extern struct mutex smi_lock; #define RTL821X_PAGE_STATE 0x0b80 #define RTL821X_PAGE_PATCH 0x0b82 -/* - * Using the special page 0xfff with the MDIO controller found in +/* Using the special page 0xfff with the MDIO controller found in * RealTek SoCs allows to access the PHY in RAW mode, ie. bypassing * the cache and paging engine of the MDIO controller. */ @@ -55,8 +54,7 @@ extern struct mutex smi_lock; #define RTL9300_PHY_ID_MASK 0xf0ffffff -/* - * This lock protects the state of the SoC automatically polling the PHYs over the SMI +/* This lock protects the state of the SoC automatically polling the PHYs over the SMI * bus to detect e.g. link and media changes. For operations on the PHYs such as * patching or other configuration changes such as EEE, polling needs to be disabled * since otherwise these operations may fails or lead to unpredictable results. @@ -83,7 +81,7 @@ static u64 disable_polling(int port) saved_state <<= 32; saved_state |= sw_r32(RTL839X_SMI_PORT_POLLING_CTRL); sw_w32_mask(BIT(port % 32), 0, - RTL839X_SMI_PORT_POLLING_CTRL + ((port >> 5) << 2)); + RTL839X_SMI_PORT_POLLING_CTRL + ((port >> 5) << 2)); break; case RTL9300_FAMILY_ID: saved_state = sw_r32(RTL930X_SMI_POLL_CTRL); @@ -150,8 +148,7 @@ u16 rtl9300_sds_regs[] = { 0x0194, 0x0194, 0x0194, 0x0194, 0x02a0, 0x02a0, 0x02a 0x02A4, 0x02A4, 0x0198, 0x0198 }; u8 rtl9300_sds_lsb[] = { 0, 6, 12, 18, 0, 6, 12, 18, 0, 6, 0, 6}; -/* - * Reset the SerDes by powering it off and set a new operations mode +/* Reset the SerDes by powering it off and set a new operations mode * of the SerDes. 0x1f is off. Other modes are * 0x02: SGMII 0x04: 1000BX_FIBER 0x05: FIBER100 * 0x06: QSGMII 0x09: RSGMII 0x0d: USXGMII @@ -176,7 +173,7 @@ void rtl9300_sds_rst(int sds_num, u32 mode) mdelay(10); pr_debug("%s: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n", __func__, - sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4)); + sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4)); } void rtl9300_sds_set(int sds_num, u32 mode) @@ -192,7 +189,7 @@ void rtl9300_sds_set(int sds_num, u32 mode) mdelay(10); pr_debug("%s: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n", __func__, - sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4)); + sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4)); } u32 rtl9300_sds_mode_get(int sds_num) @@ -210,8 +207,7 @@ u32 rtl9300_sds_mode_get(int sds_num) return v & 0x1f; } -/* - * On the RTL839x family of SoCs with inbuilt SerDes, these SerDes are accessed through +/* On the RTL839x family of SoCs with inbuilt SerDes, these SerDes are accessed through * a 2048 bit register that holds the contents of the PHY being simulated by the SoC. */ int rtl839x_read_sds_phy(int phy_addr, int phy_reg) @@ -223,8 +219,7 @@ int rtl839x_read_sds_phy(int phy_addr, int phy_reg) if (phy_addr == 49) offset = 0x100; - /* - * For the RTL8393 internal SerDes, we simulate a PHY ID in registers 2/3 + /* For the RTL8393 internal SerDes, we simulate a PHY ID in registers 2/3 * which would otherwise read as 0. */ if (soc_info.id == 0x8393) { @@ -234,8 +229,7 @@ int rtl839x_read_sds_phy(int phy_addr, int phy_reg) return 0x8393; } - /* - * Register RTL839X_SDS12_13_XSG0 is 2048 bit broad, the MSB (bit 15) of the + /* Register RTL839X_SDS12_13_XSG0 is 2048 bit broad, the MSB (bit 15) of the * 0th PHY register is bit 1023 (in byte 0x80). Because PHY-registers are 16 * bit broad, we offset by reg << 1. In the SoC 2 registers are stored in * one 32 bit register. @@ -247,11 +241,11 @@ int rtl839x_read_sds_phy(int phy_addr, int phy_reg) val = (val >> 16) & 0xffff; else val &= 0xffff; + return val; } -/* - * On the RTL930x family of SoCs, the internal SerDes are accessed through an IO +/* On the RTL930x family of SoCs, the internal SerDes are accessed through an IO * register which simulates commands to an internal MDIO bus. */ int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg) @@ -314,6 +308,7 @@ int rtl931x_read_sds_phy(int phy_addr, int page, int phy_reg) return -EIO; pr_debug("%s: returning %04x\n", __func__, sw_r32(RTL931X_SERDES_INDRT_DATA_CTRL) & 0xffff); + return sw_r32(RTL931X_SERDES_INDRT_DATA_CTRL) & 0xffff; } @@ -326,7 +321,7 @@ int rtl931x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v) sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL); sw_w32(v, RTL931X_SERDES_INDRT_DATA_CTRL); - + cmd = sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) | 0x3; sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL); @@ -342,8 +337,7 @@ int rtl931x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v) return 0; } -/* - * On the RTL838x SoCs, the internal SerDes is accessed through direct access to +/* On the RTL838x SoCs, the internal SerDes is accessed through direct access to * standard PHY registers, where a 32 bit register holds a 16 bit word as found * in a standard page 0 of a PHY */ @@ -449,9 +443,9 @@ static int rtl8226_read_status(struct phy_device *phydev) // } // Link status must be read twice - for (i = 0; i < 2; i++) { + for (i = 0; i < 2; i++) val = phy_read_mmd(phydev, MMD_VEND2, 0xA402); - } + phydev->link = val & BIT(2) ? 1 : 0; if (!phydev->link) goto out; @@ -486,6 +480,7 @@ static int rtl8226_read_status(struct phy_device *phydev) default: break; } + out: return ret; } @@ -566,7 +561,7 @@ out: } static int rtl8226_get_eee(struct phy_device *phydev, - struct ethtool_eee *e) + struct ethtool_eee *e) { u32 val; int addr = phydev->mdio.addr; @@ -706,6 +701,7 @@ static int rtl8390_configure_generic(struct phy_device *phydev) /* Internal RTL8218B, version 2 */ phydev_info(phydev, "Detected unknown %x\n", val); + return 0; } @@ -744,11 +740,8 @@ static int rtl8380_configure_int_rtl8218b(struct phy_device *phydev) return -1; } - rtl838x_6275B_intPhy_perport = (void *)h + sizeof(struct fw_header) - + h->parts[8].start; - - rtl8218b_6276B_hwEsd_perport = (void *)h + sizeof(struct fw_header) - + h->parts[9].start; + rtl838x_6275B_intPhy_perport = (void *)h + sizeof(struct fw_header) + h->parts[8].start; + rtl8218b_6276B_hwEsd_perport = (void *)h + sizeof(struct fw_header) + h->parts[9].start; if (sw_r32(RTL838X_DMY_REG31) == 0x1) ipd_flag = 1; @@ -774,8 +767,8 @@ static int rtl8380_configure_int_rtl8218b(struct phy_device *phydev) } if (i >= 100) { phydev_err(phydev, - "ERROR: Port %d not ready for patch.\n", - mac + p); + "ERROR: Port %d not ready for patch.\n", + mac + p); return -1; } } @@ -783,18 +776,19 @@ static int rtl8380_configure_int_rtl8218b(struct phy_device *phydev) i = 0; while (rtl838x_6275B_intPhy_perport[i * 2]) { phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW, - rtl838x_6275B_intPhy_perport[i * 2], - rtl838x_6275B_intPhy_perport[i * 2 + 1]); + rtl838x_6275B_intPhy_perport[i * 2], + rtl838x_6275B_intPhy_perport[i * 2 + 1]); i++; } i = 0; while (rtl8218b_6276B_hwEsd_perport[i * 2]) { phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW, - rtl8218b_6276B_hwEsd_perport[i * 2], - rtl8218b_6276B_hwEsd_perport[i * 2 + 1]); + rtl8218b_6276B_hwEsd_perport[i * 2], + rtl8218b_6276B_hwEsd_perport[i * 2 + 1]); i++; } } + return 0; } @@ -836,14 +830,9 @@ static int rtl8380_configure_ext_rtl8218b(struct phy_device *phydev) return -1; } - rtl8380_rtl8218b_perchip = (void *)h + sizeof(struct fw_header) - + h->parts[0].start; - - rtl8218B_6276B_rtl8380_perport = (void *)h + sizeof(struct fw_header) - + h->parts[1].start; - - rtl8380_rtl8218b_perport = (void *)h + sizeof(struct fw_header) - + h->parts[2].start; + rtl8380_rtl8218b_perchip = (void *)h + sizeof(struct fw_header) + h->parts[0].start; + rtl8218B_6276B_rtl8380_perport = (void *)h + sizeof(struct fw_header) + h->parts[1].start; + rtl8380_rtl8218b_perport = (void *)h + sizeof(struct fw_header) + h->parts[2].start; val = phy_read(phydev, 0); if (val & (1 << 11)) @@ -861,11 +850,11 @@ static int rtl8380_configure_ext_rtl8218b(struct phy_device *phydev) phydev_info(phydev, "Detected chip revision %04x\n", val); i = 0; - while (rtl8380_rtl8218b_perchip[i * 3] - && rtl8380_rtl8218b_perchip[i * 3 + 1]) { - phy_package_port_write_paged(phydev, rtl8380_rtl8218b_perchip[i * 3], - RTL83XX_PAGE_RAW, rtl8380_rtl8218b_perchip[i * 3 + 1], - rtl8380_rtl8218b_perchip[i * 3 + 2]); + while (rtl8380_rtl8218b_perchip[i * 3] && + rtl8380_rtl8218b_perchip[i * 3 + 1]) { + phy_package_port_write_paged(phydev, rtl8380_rtl8218b_perchip[i * 3], + RTL83XX_PAGE_RAW, rtl8380_rtl8218b_perchip[i * 3 + 1], + rtl8380_rtl8218b_perchip[i * 3 + 2]); i++; } @@ -911,11 +900,11 @@ static int rtl8380_configure_ext_rtl8218b(struct phy_device *phydev) i = 0; while (rtl8218B_6276B_rtl8380_perport[i * 2]) { phy_write_paged(phydev, RTL83XX_PAGE_RAW, rtl8218B_6276B_rtl8380_perport[i * 2], - rtl8218B_6276B_rtl8380_perport[i * 2 + 1]); + rtl8218B_6276B_rtl8380_perport[i * 2 + 1]); i++; } - /*Disable broadcast ID*/ + /* Disable broadcast ID */ rtl821x_phy_setup_package_broadcast(phydev, false); return 0; @@ -1036,6 +1025,7 @@ static int rtl8214fc_set_port(struct phy_device *phydev, int port) pr_debug("%s port %d to %d\n", __func__, addr, port); rtl8214fc_media_set(phydev, is_fibre); + return 0; } @@ -1046,11 +1036,11 @@ static int rtl8214fc_get_port(struct phy_device *phydev) pr_debug("%s: port %d\n", __func__, addr); if (rtl8214fc_media_is_fibre(phydev)) return PORT_FIBRE; + return PORT_MII; } -/* - * Enable EEE on the RTL8218B PHYs +/* Enable EEE on the RTL8218B PHYs * The method used is not the preferred way (which would be based on the MAC-EEE state, * but the only way that works since the kernel first enables EEE in the MAC * and then sets up the PHY. The MAC-based approach would require the oppsite. @@ -1087,12 +1077,12 @@ void rtl8218d_eee_set(struct phy_device *phydev, bool enable) phy_write(phydev, 0, val); } - /* GPHY page back to auto*/ + /* GPHY page back to auto */ phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO); } static int rtl8218b_get_eee(struct phy_device *phydev, - struct ethtool_eee *e) + struct ethtool_eee *e) { u32 val; int addr = phydev->mdio.addr; @@ -1120,7 +1110,7 @@ static int rtl8218b_get_eee(struct phy_device *phydev, } static int rtl8218d_get_eee(struct phy_device *phydev, - struct ethtool_eee *e) + struct ethtool_eee *e) { u32 val; int addr = phydev->mdio.addr; @@ -1142,7 +1132,7 @@ static int rtl8218d_get_eee(struct phy_device *phydev, } static int rtl8214fc_set_eee(struct phy_device *phydev, - struct ethtool_eee *e) + struct ethtool_eee *e) { u32 poll_state; int port = phydev->mdio.addr; @@ -1190,7 +1180,7 @@ static int rtl8214fc_set_eee(struct phy_device *phydev, phy_write(phydev, 0, val); } - /* GPHY page back to auto*/ + /* GPHY page back to auto */ phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO); resume_polling(poll_state); @@ -1199,7 +1189,7 @@ static int rtl8214fc_set_eee(struct phy_device *phydev, } static int rtl8214fc_get_eee(struct phy_device *phydev, - struct ethtool_eee *e) + struct ethtool_eee *e) { int addr = phydev->mdio.addr; @@ -1257,7 +1247,7 @@ static int rtl8218b_set_eee(struct phy_device *phydev, struct ethtool_eee *e) phy_write(phydev, 0, val); } - /* GPHY page back to auto*/ + /* GPHY page back to auto */ phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO); pr_info("%s done\n", __func__); @@ -1302,6 +1292,7 @@ static int rtl8380_configure_rtl8214c(struct phy_device *phydev) /* GPHY auto conf */ phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO); + return 0; } @@ -1339,11 +1330,9 @@ static int rtl8380_configure_rtl8214fc(struct phy_device *phydev) return -1; } - rtl8380_rtl8214fc_perchip = (void *)h + sizeof(struct fw_header) - + h->parts[0].start; + rtl8380_rtl8214fc_perchip = (void *)h + sizeof(struct fw_header) + h->parts[0].start; - rtl8380_rtl8214fc_perport = (void *)h + sizeof(struct fw_header) - + h->parts[1].start; + rtl8380_rtl8214fc_perport = (void *)h + sizeof(struct fw_header) + h->parts[1].start; /* detect phy version */ phy_write_paged(phydev, RTL83XX_PAGE_RAW, 27, 0x0004); @@ -1359,14 +1348,13 @@ static int rtl8380_configure_rtl8214fc(struct phy_device *phydev) phy_write_paged(phydev, 0, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER); i = 0; - while (rtl8380_rtl8214fc_perchip[i * 3] - && rtl8380_rtl8214fc_perchip[i * 3 + 1]) { + while (rtl8380_rtl8214fc_perchip[i * 3] && + rtl8380_rtl8214fc_perchip[i * 3 + 1]) { if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x1f) page = rtl8380_rtl8214fc_perchip[i * 3 + 2]; if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x13 && page == 0x260) { val = phy_read_paged(phydev, 0x260, 13); - val = (val & 0x1f00) | (rtl8380_rtl8214fc_perchip[i * 3 + 2] - & 0xe0ff); + val = (val & 0x1f00) | (rtl8380_rtl8214fc_perchip[i * 3 + 2] & 0xe0ff); phy_write_paged(phydev, RTL83XX_PAGE_RAW, rtl8380_rtl8214fc_perchip[i * 3 + 1], val); } else { @@ -1428,11 +1416,11 @@ static int rtl8380_configure_rtl8214fc(struct phy_device *phydev) i = 0; while (rtl8380_rtl8214fc_perport[i * 2]) { phy_write_paged(phydev, RTL83XX_PAGE_RAW, rtl8380_rtl8214fc_perport[i * 2], - rtl8380_rtl8214fc_perport[i * 2 + 1]); + rtl8380_rtl8214fc_perport[i * 2 + 1]); i++; } - /*Disable broadcast ID*/ + /* Disable broadcast ID */ rtl821x_phy_setup_package_broadcast(phydev, false); /* Auto medium selection */ @@ -1477,29 +1465,21 @@ static int rtl8380_configure_serdes(struct phy_device *phydev) return -1; } - rtl8380_sds_take_reset = (void *)h + sizeof(struct fw_header) - + h->parts[0].start; + rtl8380_sds_take_reset = (void *)h + sizeof(struct fw_header) + h->parts[0].start; - rtl8380_sds_common = (void *)h + sizeof(struct fw_header) - + h->parts[1].start; + rtl8380_sds_common = (void *)h + sizeof(struct fw_header) + h->parts[1].start; - rtl8380_sds01_qsgmii_6275b = (void *)h + sizeof(struct fw_header) - + h->parts[2].start; + rtl8380_sds01_qsgmii_6275b = (void *)h + sizeof(struct fw_header) + h->parts[2].start; - rtl8380_sds23_qsgmii_6275b = (void *)h + sizeof(struct fw_header) - + h->parts[3].start; + rtl8380_sds23_qsgmii_6275b = (void *)h + sizeof(struct fw_header) + h->parts[3].start; - rtl8380_sds4_fiber_6275b = (void *)h + sizeof(struct fw_header) - + h->parts[4].start; + rtl8380_sds4_fiber_6275b = (void *)h + sizeof(struct fw_header) + h->parts[4].start; - rtl8380_sds5_fiber_6275b = (void *)h + sizeof(struct fw_header) - + h->parts[5].start; + rtl8380_sds5_fiber_6275b = (void *)h + sizeof(struct fw_header) + h->parts[5].start; - rtl8380_sds_reset = (void *)h + sizeof(struct fw_header) - + h->parts[6].start; + rtl8380_sds_reset = (void *)h + sizeof(struct fw_header) + h->parts[6].start; - rtl8380_sds_release_reset = (void *)h + sizeof(struct fw_header) - + h->parts[7].start; + rtl8380_sds_release_reset = (void *)h + sizeof(struct fw_header) + h->parts[7].start; /* Back up serdes power off value */ sds_conf_value = sw_r32(RTL838X_SDS_CFG_REG); @@ -1538,7 +1518,7 @@ static int rtl8380_configure_serdes(struct phy_device *phydev) i = 0; while (rtl8380_sds01_qsgmii_6275b[2 * i]) { sw_w32(rtl8380_sds01_qsgmii_6275b[2 * i + 1], - rtl8380_sds01_qsgmii_6275b[2 * i]); + rtl8380_sds01_qsgmii_6275b[2 * i]); i++; } @@ -1576,6 +1556,7 @@ static int rtl8380_configure_serdes(struct phy_device *phydev) sw_w32(sds_conf_value, RTL838X_SDS_CFG_REG); pr_info("Configuration of SERDES done\n"); + return 0; } @@ -1647,7 +1628,7 @@ static int rtl9300_read_status(struct phy_device *phydev) mode = rtl9300_sds_mode_get(sds_num); pr_info("%s got SDS mode %02x\n", __func__, mode); - if (mode == 0x1a) { // 10GR mode + if (mode == 0x1a) { // 10GR mode status = rtl9300_sds_field_r(sds_num, 0x5, 0, 12, 12); latch_status = rtl9300_sds_field_r(sds_num, 0x4, 1, 2, 2); status |= rtl9300_sds_field_r(sds_num, 0x5, 0, 12, 12); @@ -1686,8 +1667,7 @@ void rtl930x_sds_rx_rst(int sds_num, phy_interface_t phy_if) rtl9300_sds_field_w(sds_num, page, 0x15, 4, 4, 0x0); } -/* - * Force PHY modes on 10GBit Serdes +/* Force PHY modes on 10GBit Serdes */ void rtl9300_force_sds_mode(int sds, phy_interface_t phy_if) { @@ -1803,6 +1783,7 @@ void rtl9300_force_sds_mode(int sds, phy_interface_t phy_if) if (cr_0 && cr_1 && cr_2) { u32 t; + if (phy_if != PHY_INTERFACE_MODE_10GBASER) break; @@ -1874,16 +1855,15 @@ void rtl9300_sds_tx_config(int sds, phy_interface_t phy_if) return; } - rtl9300_sds_field_w(sds, page, 0x1, 15, 11, pre_amp); - rtl9300_sds_field_w(sds, page, 0x7, 0, 0, pre_en); - rtl9300_sds_field_w(sds, page, 0x7, 8, 4, main_amp); - rtl9300_sds_field_w(sds, page, 0x6, 4, 0, post_amp); - rtl9300_sds_field_w(sds, page, 0x7, 3, 3, post_en); + rtl9300_sds_field_w(sds, page, 0x01, 15, 11, pre_amp); + rtl9300_sds_field_w(sds, page, 0x06, 4, 0, post_amp); + rtl9300_sds_field_w(sds, page, 0x07, 0, 0, pre_en); + rtl9300_sds_field_w(sds, page, 0x07, 3, 3, post_en); + rtl9300_sds_field_w(sds, page, 0x07, 8, 4, main_amp); rtl9300_sds_field_w(sds, page, 0x18, 15, 12, impedance); } -/* - * Wait for clock ready, this assumes the SerDes is in XGMII mode +/* Wait for clock ready, this assumes the SerDes is in XGMII mode * timeout is in ms */ int rtl9300_sds_clock_wait(int timeout) @@ -1932,8 +1912,8 @@ void rtl9300_sds_rxcal_dcvs_manual(u32 sds_num, u32 dcvs_id, bool manual, u32 dv switch(dcvs_id) { case 0: rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 14, 14, 0x1); - rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 5, 5, dvcs_list[0]); - rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 4, 0, dvcs_list[1]); + rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 5, 5, dvcs_list[0]); + rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 4, 0, dvcs_list[1]); break; case 1: rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 13, 13, 0x1); @@ -1943,22 +1923,22 @@ void rtl9300_sds_rxcal_dcvs_manual(u32 sds_num, u32 dcvs_id, bool manual, u32 dv case 2: rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 12, 12, 0x1); rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 10, 10, dvcs_list[0]); - rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 9, 6, dvcs_list[1]); + rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 9, 6, dvcs_list[1]); break; case 3: rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 11, 11, 0x1); - rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 5, 5, dvcs_list[0]); - rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 4, 1, dvcs_list[1]); + rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 5, 5, dvcs_list[0]); + rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 4, 1, dvcs_list[1]); break; case 4: rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 15, 15, 0x1); rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 10, 10, dvcs_list[0]); - rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 9, 6, dvcs_list[1]); + rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 9, 6, dvcs_list[1]); break; case 5: rtl9300_sds_field_w(sds_num, 0x2e, 0x02, 11, 11, 0x1); - rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 4, 4, dvcs_list[0]); - rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 3, 0, dvcs_list[1]); + rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 4, 4, dvcs_list[0]); + rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 3, 0, dvcs_list[1]); break; default: break; @@ -2012,8 +1992,8 @@ void rtl9300_sds_rxcal_dcvs_get(u32 sds_num, u32 dcvs_id, u32 dcvs_list[]) mdelay(1); // ##DCVS0 Read Out - dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4); - dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0); + dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4); + dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0); dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 14, 14); break; @@ -2022,8 +2002,8 @@ void rtl9300_sds_rxcal_dcvs_get(u32 sds_num, u32 dcvs_id, u32 dcvs_list[]) mdelay(1); // ##DCVS0 Read Out - dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4); - dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0); + dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4); + dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0); dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 13, 13); break; @@ -2032,8 +2012,8 @@ void rtl9300_sds_rxcal_dcvs_get(u32 sds_num, u32 dcvs_id, u32 dcvs_list[]) mdelay(1); // ##DCVS0 Read Out - dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4); - dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0); + dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4); + dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0); dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 12, 12); break; case 3: @@ -2041,9 +2021,9 @@ void rtl9300_sds_rxcal_dcvs_get(u32 sds_num, u32 dcvs_id, u32 dcvs_list[]) mdelay(1); // ##DCVS0 Read Out - dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4); - dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0); - dcvs_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 11, 11); + dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4); + dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0); + dcvs_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 11, 11); break; case 4: @@ -2051,8 +2031,8 @@ void rtl9300_sds_rxcal_dcvs_get(u32 sds_num, u32 dcvs_id, u32 dcvs_list[]) mdelay(1); // ##DCVS0 Read Out - dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4); - dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0); + dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4); + dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0); dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x01, 15, 15); break; @@ -2061,9 +2041,9 @@ void rtl9300_sds_rxcal_dcvs_get(u32 sds_num, u32 dcvs_id, u32 dcvs_list[]) mdelay(1); // ##DCVS0 Read Out - dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4); - dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0); - dcvs_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x02, 11, 11); + dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4); + dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0); + dcvs_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x02, 11, 11); break; default: @@ -2162,8 +2142,8 @@ void rtl9300_sds_rxcal_vth_manual(u32 sds_num, bool manual, u32 vth_list[]) { if (manual) { rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, 13, 13, 0x1); - rtl9300_sds_field_w(sds_num, 0x2e, 0x13, 5, 3, vth_list[0]); - rtl9300_sds_field_w(sds_num, 0x2e, 0x13, 2, 0, vth_list[1]); + rtl9300_sds_field_w(sds_num, 0x2e, 0x13, 5, 3, vth_list[0]); + rtl9300_sds_field_w(sds_num, 0x2e, 0x13, 2, 0, vth_list[1]); } else { rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, 13, 13, 0x0); mdelay(10); @@ -2329,72 +2309,72 @@ void rtl9300_sds_rxcal_tap_get(u32 sds_num, u32 tap_id, u32 tap_list[]) void rtl9300_do_rx_calibration_1(int sds, phy_interface_t phy_mode) { // From both rtl9300_rxCaliConf_serdes_myParam and rtl9300_rxCaliConf_phy_myParam - int tap0_init_val = 0x1f; // Initial Decision Fed Equalizer 0 tap - int vth_min = 0x0; + int tap0_init_val = 0x1f; // Initial Decision Fed Equalizer 0 tap + int vth_min = 0x0; pr_info("start_1.1.1 initial value for sds %d\n", sds); rtl930x_write_sds_phy(sds, 6, 0, 0); // FGCAL - rtl9300_sds_field_w(sds, 0x2e, 0x01, 14, 14, 0x0); - rtl9300_sds_field_w(sds, 0x2e, 0x1c, 10, 5, 0x20); - rtl9300_sds_field_w(sds, 0x2f, 0x02, 0, 0, 0x1); + rtl9300_sds_field_w(sds, 0x2e, 0x01, 14, 14, 0x00); + rtl9300_sds_field_w(sds, 0x2e, 0x1c, 10, 5, 0x20); + rtl9300_sds_field_w(sds, 0x2f, 0x02, 0, 0, 0x01); // DCVS - rtl9300_sds_field_w(sds, 0x2e, 0x1e, 14, 11, 0x0); - rtl9300_sds_field_w(sds, 0x2e, 0x01, 15, 15, 0x0); - rtl9300_sds_field_w(sds, 0x2e, 0x02, 11, 11, 0x0); - rtl9300_sds_field_w(sds, 0x2e, 0x1c, 4, 0, 0x0); - rtl9300_sds_field_w(sds, 0x2e, 0x1d, 15, 11, 0x0); - rtl9300_sds_field_w(sds, 0x2e, 0x1d, 10, 6, 0x0); - rtl9300_sds_field_w(sds, 0x2e, 0x1d, 5, 1, 0x0); - rtl9300_sds_field_w(sds, 0x2e, 0x02, 10, 6, 0x0); - rtl9300_sds_field_w(sds, 0x2e, 0x11, 4, 0, 0x0); - rtl9300_sds_field_w(sds, 0x2f, 0x00, 3, 0, 0xf); - rtl9300_sds_field_w(sds, 0x2e, 0x04, 6, 6, 0x1); - rtl9300_sds_field_w(sds, 0x2e, 0x04, 7, 7, 0x1); + rtl9300_sds_field_w(sds, 0x2e, 0x1e, 14, 11, 0x00); + rtl9300_sds_field_w(sds, 0x2e, 0x01, 15, 15, 0x00); + rtl9300_sds_field_w(sds, 0x2e, 0x02, 11, 11, 0x00); + rtl9300_sds_field_w(sds, 0x2e, 0x1c, 4, 0, 0x00); + rtl9300_sds_field_w(sds, 0x2e, 0x1d, 15, 11, 0x00); + rtl9300_sds_field_w(sds, 0x2e, 0x1d, 10, 6, 0x00); + rtl9300_sds_field_w(sds, 0x2e, 0x1d, 5, 1, 0x00); + rtl9300_sds_field_w(sds, 0x2e, 0x02, 10, 6, 0x00); + rtl9300_sds_field_w(sds, 0x2e, 0x11, 4, 0, 0x00); + rtl9300_sds_field_w(sds, 0x2f, 0x00, 3, 0, 0x0f); + rtl9300_sds_field_w(sds, 0x2e, 0x04, 6, 6, 0x01); + rtl9300_sds_field_w(sds, 0x2e, 0x04, 7, 7, 0x01); // LEQ (Long Term Equivalent signal level) - rtl9300_sds_field_w(sds, 0x2e, 0x16, 14, 8, 0x0); + rtl9300_sds_field_w(sds, 0x2e, 0x16, 14, 8, 0x00); // DFE (Decision Fed Equalizer) - rtl9300_sds_field_w(sds, 0x2f, 0x03, 5, 0, tap0_init_val); - rtl9300_sds_field_w(sds, 0x2e, 0x09, 11, 6, 0x0); - rtl9300_sds_field_w(sds, 0x2e, 0x09, 5, 0, 0x0); - rtl9300_sds_field_w(sds, 0x2e, 0x0a, 5, 0, 0x0); - rtl9300_sds_field_w(sds, 0x2f, 0x01, 5, 0, 0x0); - rtl9300_sds_field_w(sds, 0x2f, 0x12, 5, 0, 0x0); - rtl9300_sds_field_w(sds, 0x2e, 0x0a, 11, 6, 0x0); - rtl9300_sds_field_w(sds, 0x2e, 0x06, 5, 0, 0x0); - rtl9300_sds_field_w(sds, 0x2f, 0x01, 5, 0, 0x0); + rtl9300_sds_field_w(sds, 0x2f, 0x03, 5, 0, tap0_init_val); + rtl9300_sds_field_w(sds, 0x2e, 0x09, 11, 6, 0x00); + rtl9300_sds_field_w(sds, 0x2e, 0x09, 5, 0, 0x00); + rtl9300_sds_field_w(sds, 0x2e, 0x0a, 5, 0, 0x00); + rtl9300_sds_field_w(sds, 0x2f, 0x01, 5, 0, 0x00); + rtl9300_sds_field_w(sds, 0x2f, 0x12, 5, 0, 0x00); + rtl9300_sds_field_w(sds, 0x2e, 0x0a, 11, 6, 0x00); + rtl9300_sds_field_w(sds, 0x2e, 0x06, 5, 0, 0x00); + rtl9300_sds_field_w(sds, 0x2f, 0x01, 5, 0, 0x00); // Vth - rtl9300_sds_field_w(sds, 0x2e, 0x13, 5, 3, 0x7); - rtl9300_sds_field_w(sds, 0x2e, 0x13, 2, 0, 0x7); - rtl9300_sds_field_w(sds, 0x2f, 0x0b, 5, 3, vth_min); + rtl9300_sds_field_w(sds, 0x2e, 0x13, 5, 3, 0x07); + rtl9300_sds_field_w(sds, 0x2e, 0x13, 2, 0, 0x07); + rtl9300_sds_field_w(sds, 0x2f, 0x0b, 5, 3, vth_min); pr_info("end_1.1.1 --\n"); pr_info("start_1.1.2 Load DFE init. value\n"); - rtl9300_sds_field_w(sds, 0x2e, 0x0f, 13, 7, 0x7f); + rtl9300_sds_field_w(sds, 0x2e, 0x0f, 13, 7, 0x7f); pr_info("end_1.1.2\n"); pr_info("start_1.1.3 disable LEQ training,enable DFE clock\n"); - rtl9300_sds_field_w(sds, 0x2e, 0x17, 7, 7, 0x0); - rtl9300_sds_field_w(sds, 0x2e, 0x17, 6, 2, 0x0); - rtl9300_sds_field_w(sds, 0x2e, 0x0c, 8, 8, 0x0); - rtl9300_sds_field_w(sds, 0x2e, 0x0b, 4, 4, 0x1); - rtl9300_sds_field_w(sds, 0x2e, 0x12, 14, 14, 0x0); - rtl9300_sds_field_w(sds, 0x2f, 0x02, 15, 15, 0x0); + rtl9300_sds_field_w(sds, 0x2e, 0x17, 7, 7, 0x00); + rtl9300_sds_field_w(sds, 0x2e, 0x17, 6, 2, 0x00); + rtl9300_sds_field_w(sds, 0x2e, 0x0c, 8, 8, 0x00); + rtl9300_sds_field_w(sds, 0x2e, 0x0b, 4, 4, 0x01); + rtl9300_sds_field_w(sds, 0x2e, 0x12, 14, 14, 0x00); + rtl9300_sds_field_w(sds, 0x2f, 0x02, 15, 15, 0x00); pr_info("end_1.1.3 --\n"); pr_info("start_1.1.4 offset cali setting\n"); - rtl9300_sds_field_w(sds, 0x2e, 0x0f, 15, 14, 0x3); + rtl9300_sds_field_w(sds, 0x2e, 0x0f, 15, 14, 0x03); pr_info("end_1.1.4\n"); @@ -2403,18 +2383,18 @@ void rtl9300_do_rx_calibration_1(int sds, phy_interface_t phy_mode) // TODO: make this work for DAC cables of different lengths // For a 10GBit serdes wit Fibre, SDS 8 or 9 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || PHY_INTERFACE_MODE_1000BASEX) - rtl9300_sds_field_w(sds, 0x2e, 0x16, 3, 2, 0x2); + rtl9300_sds_field_w(sds, 0x2e, 0x16, 3, 2, 0x02); else pr_err("%s not PHY-based or SerDes, implement DAC!\n", __func__); // No serdes, check for Aquantia PHYs - rtl9300_sds_field_w(sds, 0x2e, 0x16, 3, 2, 0x2); + rtl9300_sds_field_w(sds, 0x2e, 0x16, 3, 2, 0x02); - rtl9300_sds_field_w(sds, 0x2e, 0x0f, 6, 0, 0x5f); - rtl9300_sds_field_w(sds, 0x2f, 0x05, 7, 2, 0x1f); - rtl9300_sds_field_w(sds, 0x2e, 0x19, 9, 5, 0x1f); - rtl9300_sds_field_w(sds, 0x2f, 0x0b, 15, 9, 0x3c); - rtl9300_sds_field_w(sds, 0x2e, 0x0b, 1, 0, 0x3); + rtl9300_sds_field_w(sds, 0x2e, 0x0f, 6, 0, 0x5f); + rtl9300_sds_field_w(sds, 0x2f, 0x05, 7, 2, 0x1f); + rtl9300_sds_field_w(sds, 0x2e, 0x19, 9, 5, 0x1f); + rtl9300_sds_field_w(sds, 0x2f, 0x0b, 15, 9, 0x3c); + rtl9300_sds_field_w(sds, 0x2e, 0x0b, 1, 0, 0x03); pr_info("end_1.1.5\n"); } @@ -2424,10 +2404,10 @@ void rtl9300_do_rx_calibration_2_1(u32 sds_num) pr_info("start_1.2.1 ForegroundOffsetCal_Manual\n"); // Gray config endis to 1 - rtl9300_sds_field_w(sds_num, 0x2f, 0x02, 2, 2, 0x1); + rtl9300_sds_field_w(sds_num, 0x2f, 0x02, 2, 2, 0x01); // ForegroundOffsetCal_Manual(auto mode) - rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 14, 14, 0x0); + rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 14, 14, 0x00); pr_info("end_1.2.1"); } @@ -2467,7 +2447,7 @@ void rtl9300_do_rx_calibration_2_3(int sds_num) fgcal_binary = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 0); pr_info("%s: fgcal_gray: %d, fgcal_binary %d\n", - __func__, fgcal_gray, fgcal_binary); + __func__, fgcal_gray, fgcal_binary); offset_range = rtl9300_sds_field_r(sds_num, 0x2e, 0x15, 15, 14); @@ -2739,8 +2719,8 @@ int rtl9300_sds_check_calibration(int sds_num, phy_interface_t phy_mode) switch (phy_mode) { case PHY_INTERFACE_MODE_XGMII: - if ((errors2 - errors1 > 100) - || (errors1 >= 0xffff00) || (errors2 >= 0xffff00)) { + if ((errors2 - errors1 > 100) || + (errors1 >= 0xffff00) || (errors2 >= 0xffff00)) { pr_info("%s XSGMII error rate too high\n", __func__); return 1; } @@ -2754,6 +2734,7 @@ int rtl9300_sds_check_calibration(int sds_num, phy_interface_t phy_mode) default: return 1; } + return 0; } @@ -2813,11 +2794,11 @@ int rtl9300_serdes_setup(int sds_num, phy_interface_t phy_mode) // Maybe use dal_longan_sds_init - // dal_longan_construct_serdesConfig_init // Serdes Construct + // dal_longan_construct_serdesConfig_init // Serdes Construct rtl9300_phy_enable_10g_1g(sds_num); // Set Serdes Mode - rtl9300_sds_set(sds_num, 0x1a); // 0x1b: RTK_MII_10GR1000BX_AUTO + rtl9300_sds_set(sds_num, 0x1a); // 0x1b: RTK_MII_10GR1000BX_AUTO // Do RX calibration do { @@ -2838,7 +2819,7 @@ typedef struct { sds_config rtl9300_a_sds_10gr_lane0[] = { - /*1G*/ + /* 1G */ {0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000}, @@ -2855,7 +2836,7 @@ sds_config rtl9300_a_sds_10gr_lane0[] = {0x2D, 0x18, 0x8E88}, {0x2D, 0x19, 0x4902}, {0x2D, 0x1D, 0x2641}, {0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88}, {0x2F, 0x19, 0x4902}, {0x2F, 0x1D, 0x66E1}, - /*3.125G*/ + /* 3.125G */ {0x28, 0x00, 0x0668}, {0x28, 0x02, 0xD020}, {0x28, 0x06, 0xC000}, {0x28, 0x0B, 0x1892}, {0x28, 0x0F, 0xFFDF}, {0x28, 0x12, 0x01C4}, {0x28, 0x13, 0x027F}, {0x28, 0x14, 0x1311}, {0x28, 0x16, 0x00C9}, @@ -2864,7 +2845,7 @@ sds_config rtl9300_a_sds_10gr_lane0[] = {0x29, 0x05, 0x7F7C}, {0x29, 0x07, 0x8100}, {0x29, 0x08, 0x0001}, {0x29, 0x09, 0xFFD4}, {0x29, 0x0A, 0x7C2F}, {0x29, 0x0E, 0x003F}, {0x29, 0x0F, 0x0121}, {0x29, 0x10, 0x0020}, {0x29, 0x11, 0x8840}, - /*10G*/ + /* 10G */ {0x06, 0x0D, 0x0F00}, {0x06, 0x00, 0x0000}, {0x06, 0x01, 0xC800}, {0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, @@ -2886,7 +2867,7 @@ sds_config rtl9300_a_sds_10gr_lane0[] = sds_config rtl9300_a_sds_10gr_lane1[] = { - /*1G*/ + /* 1G */ {0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206}, {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003}, {0x21, 0x0B, 0x0005}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, @@ -2901,7 +2882,7 @@ sds_config rtl9300_a_sds_10gr_lane1[] = {0x25, 0x0F, 0x0121}, {0x25, 0x10, 0x0020}, {0x25, 0x11, 0x8840}, {0x2B, 0x13, 0x3D87}, {0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87}, {0x2D, 0x14, 0x1808}, - /*3.125G*/ + /* 3.125G */ {0x28, 0x00, 0x0668}, {0x28, 0x02, 0xD020}, {0x28, 0x06, 0xC000}, {0x28, 0x0B, 0x1892}, {0x28, 0x0F, 0xFFDF}, {0x28, 0x12, 0x01C4}, {0x28, 0x13, 0x027F}, {0x28, 0x14, 0x1311}, {0x28, 0x16, 0x00C9}, @@ -2910,7 +2891,7 @@ sds_config rtl9300_a_sds_10gr_lane1[] = {0x29, 0x03, 0xFFDF}, {0x29, 0x05, 0x7F7C}, {0x29, 0x07, 0x8100}, {0x29, 0x08, 0x0001}, {0x29, 0x0A, 0x7C2F}, {0x29, 0x0E, 0x003F}, {0x29, 0x0F, 0x0121}, {0x29, 0x10, 0x0020}, {0x29, 0x11, 0x8840}, - /*10G*/ + /* 10G */ {0x06, 0x0D, 0x0F00}, {0x06, 0x00, 0x0000}, {0x06, 0x01, 0xC800}, {0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003}, {0x21, 0x0B, 0x0005}, @@ -2962,7 +2943,7 @@ int rtl9300_configure_serdes(struct phy_device *phydev) if (dev->of_node) { dn = dev->of_node; - + if (of_property_read_u32(dn, "sds", &sds_num)) sds_num = -1; pr_info("%s: Port %d, SerDes is %d\n", __func__, phy_addr, sds_num); @@ -3007,14 +2988,14 @@ int rtl9300_configure_serdes(struct phy_device *phydev) if (sds_num % 2) { for (i = 0; i < sizeof(rtl9300_a_sds_10gr_lane1) / sizeof(sds_config); ++i) { rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane1[i].page, - rtl9300_a_sds_10gr_lane1[i].reg, - rtl9300_a_sds_10gr_lane1[i].data); + rtl9300_a_sds_10gr_lane1[i].reg, + rtl9300_a_sds_10gr_lane1[i].data); } } else { for (i = 0; i < sizeof(rtl9300_a_sds_10gr_lane0) / sizeof(sds_config); ++i) { rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane0[i].page, - rtl9300_a_sds_10gr_lane0[i].reg, - rtl9300_a_sds_10gr_lane0[i].data); + rtl9300_a_sds_10gr_lane0[i].reg, + rtl9300_a_sds_10gr_lane0[i].data); } } @@ -3074,7 +3055,6 @@ void rtl9310_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int start_bit, rtl931x_write_sds_phy(sds, page, reg, data); } - u32 rtl9310_sds_field_r(int sds, u32 page, u32 reg, int end_bit, int start_bit) { int l = end_bit - start_bit + 1; @@ -3092,7 +3072,7 @@ static void rtl931x_sds_rst(u32 sds) int shift = ((sds & 0x3) << 3); // TODO: We need to lock this! - + o = sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR); v = o | BIT(sds); sw_w32(v, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR); @@ -3121,15 +3101,15 @@ static void rtl931x_symerr_clear(u32 sds, phy_interface_t mode) xsg_sdsid_1 = xsg_sdsid_0 + 1; for (i = 0; i < 4; ++i) { - rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 24, 2, 0, i); - rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 3, 15, 8, 0x0); - rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 2, 15, 0, 0x0); + rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 24, 2, 0, i); + rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 3, 15, 8, 0x0); + rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 2, 15, 0, 0x0); } for (i = 0; i < 4; ++i) { - rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 24, 2, 0, i); - rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 3, 15, 8, 0x0); - rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 2, 15, 0, 0x0); + rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 24, 2, 0, i); + rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 3, 15, 8, 0x0); + rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 2, 15, 0, 0x0); } rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 0, 15, 0, 0x0); @@ -3150,6 +3130,7 @@ static u32 rtl931x_get_analog_sds(u32 sds) if (sds < 14) return sds_map[sds]; + return sds; } @@ -3225,6 +3206,7 @@ static int rtl931x_sds_cmu_page_get(phy_interface_t mode) default: return -1; } + return -1; } @@ -3300,7 +3282,7 @@ static void rtl931x_cmu_type_set(u32 asds, phy_interface_t mode, int chiptype) evenSds = asds - lane; pr_info("%s: cmu_type %0d cmu_page %x frc_cmu_spd %d lane %d asds %d\n", - __func__, cmu_type, cmu_page, frc_cmu_spd, lane, asds); + __func__, cmu_type, cmu_page, frc_cmu_spd, lane, asds); if (cmu_type == 1) { pr_info("%s A CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7)); @@ -3405,19 +3387,18 @@ static sds_config sds_config_10p3125g_cmu_type1[] = { void rtl931x_sds_init(u32 sds, phy_interface_t mode) { - - u32 board_sds_tx_type1[] = { 0x1C3, 0x1C3, 0x1C3, 0x1A3, 0x1A3, - 0x1A3, 0x143, 0x143, 0x143, 0x143, 0x163, 0x163 + u32 board_sds_tx_type1[] = { + 0x01c3, 0x01c3, 0x01c3, 0x01a3, 0x01a3, 0x01a3, + 0x0143, 0x0143, 0x0143, 0x0143, 0x0163, 0x0163, }; - - u32 board_sds_tx[] = { 0x1A00, 0x1A00, 0x200, 0x200, 0x200, - 0x200, 0x1A3, 0x1A3, 0x1A3, 0x1A3, 0x1E3, 0x1E3 + u32 board_sds_tx[] = { + 0x1a00, 0x1a00, 0x0200, 0x0200, 0x0200, 0x0200, + 0x01a3, 0x01a3, 0x01a3, 0x01a3, 0x01e3, 0x01e3 }; - - u32 board_sds_tx2[] = { 0xDC0, 0x1C0, 0x200, 0x180, 0x160, - 0x123, 0x123, 0x163, 0x1A3, 0x1A0, 0x1C3, 0x9C3 + u32 board_sds_tx2[] = { + 0x0dc0, 0x01c0, 0x0200, 0x0180, 0x0160, 0x0123, + 0x0123, 0x0163, 0x01a3, 0x01a0, 0x01c3, 0x09c3, }; - u32 asds, dSds, ori, model_info, val; int chiptype = 0; @@ -3456,7 +3437,7 @@ void rtl931x_sds_init(u32 sds, phy_interface_t mode) dSds = (sds - 1) * 2; pr_info("%s: 2.5gbit %08X dsds %d", __func__, - rtl931x_read_sds_phy(dSds, 0x1, 0x14), dSds); + rtl931x_read_sds_phy(dSds, 0x1, 0x14), dSds); pr_info("%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\n", __func__, sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR)); ori = sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR); @@ -3500,7 +3481,7 @@ void rtl931x_sds_init(u32 sds, phy_interface_t mode) for (i = 0; i < sizeof(sds_config_10p3125g_cmu_type1) / sizeof(sds_config); ++i) { rtl931x_write_sds_phy(evenSds, - sds_config_10p3125g_cmu_type1[i].page - 0x4, sds_config_10p3125g_cmu_type1[i].reg, sds_config_10p3125g_cmu_type1[i].data); + sds_config_10p3125g_cmu_type1[i].page - 0x4, sds_config_10p3125g_cmu_type1[i].reg, sds_config_10p3125g_cmu_type1[i].data); } rtl9310_sds_field_w(asds, 0x6, 0x2, 12, 12, 0); @@ -3527,7 +3508,7 @@ void rtl931x_sds_init(u32 sds, phy_interface_t mode) break; case PHY_INTERFACE_MODE_10GBASER: // MII_10GR / MII_10GR1000BX_AUTO: - // configure 10GR fiber mode=1 + // configure 10GR fiber mode=1 rtl9310_sds_field_w(asds, 0x1f, 0xb, 1, 1, 1); // init fiber_1g @@ -3566,7 +3547,7 @@ void rtl931x_sds_init(u32 sds, phy_interface_t mode) case PHY_INTERFACE_MODE_QSGMII: default: pr_info("%s: PHY mode %s not supported by SerDes %d\n", - __func__, phy_modes(mode), sds); + __func__, phy_modes(mode), sds); return; } @@ -3594,9 +3575,11 @@ void rtl931x_sds_init(u32 sds, phy_interface_t mode) sw_w32(val, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR); pr_debug("%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\n", __func__, sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR)); - if (mode == PHY_INTERFACE_MODE_XGMII || mode == PHY_INTERFACE_MODE_QSGMII - || mode == PHY_INTERFACE_MODE_HSGMII || mode == PHY_INTERFACE_MODE_SGMII - || mode == PHY_INTERFACE_MODE_USXGMII) { + if (mode == PHY_INTERFACE_MODE_XGMII || + mode == PHY_INTERFACE_MODE_QSGMII || + mode == PHY_INTERFACE_MODE_HSGMII || + mode == PHY_INTERFACE_MODE_SGMII || + mode == PHY_INTERFACE_MODE_USXGMII) { if (mode == PHY_INTERFACE_MODE_XGMII) rtl931x_sds_mii_mode_set(sds, mode); else @@ -3621,7 +3604,7 @@ int rtl931x_sds_cmu_band_set(int sds, bool enable, u32 band, phy_interface_t mod rtl9310_sds_field_w(asds, page, 0x7, 13, 13, 0); rtl9310_sds_field_w(asds, page, 0x7, 11, 11, 0); } - + rtl9310_sds_field_w(asds, page, 0x7, 4, 0, band); rtl931x_sds_rst(sds); @@ -3674,6 +3657,7 @@ int rtl931x_link_sts_get(u32 sds) pr_info("%s: serdes %d sts %d, sts1 %d, latch_sts %d, latch_sts1 %d\n", __func__, sds, sts, sts1, latch_sts, latch_sts1); + return sts1; } @@ -3741,6 +3725,7 @@ static int rtl8214c_phy_probe(struct phy_device *phydev) /* Configuration must be done whil patching still possible */ return rtl8380_configure_rtl8214c(phydev); } + return 0; } @@ -3807,6 +3792,7 @@ static int rtl8218d_phy_probe(struct phy_device *phydev) /* Configuration must be done while patching still possible */ // TODO: return configure_rtl8218d(phydev); } + return 0; } @@ -3825,6 +3811,7 @@ static int rtl838x_serdes_probe(struct phy_device *phydev) return rtl8380_configure_serdes(phydev); return 0; } + return -ENODEV; } diff --git a/target/linux/realtek/files-5.15/drivers/net/phy/rtl83xx-phy.h b/target/linux/realtek/files-5.15/drivers/net/phy/rtl83xx-phy.h index 553d9a1575e..4addfe1442f 100644 --- a/target/linux/realtek/files-5.15/drivers/net/phy/rtl83xx-phy.h +++ b/target/linux/realtek/files-5.15/drivers/net/phy/rtl83xx-phy.h @@ -60,7 +60,7 @@ struct __attribute__ ((__packed__)) fw_header { #define RTL930X_SDS_INDACS_DATA (0x03B4) #define RTL930X_MAC_FORCE_MODE_CTRL (0xCA1C) -/*Registers of the internal SerDes of the 9310 */ +/* Registers of the internal SerDes of the 9310 */ #define RTL931X_SERDES_INDRT_ACCESS_CTRL (0x5638) #define RTL931X_SERDES_INDRT_DATA_CTRL (0x563C) #define RTL931X_SERDES_MODE_CTRL (0x13cc) From 0a931767cf2a4c2592bb37c1109299a56fb0ee89 Mon Sep 17 00:00:00 2001 From: Olliver Schinagl Date: Thu, 22 Dec 2022 11:27:59 +0100 Subject: [PATCH 39/72] realtek: Replace C++ style comments The only exception to C++ style comments are SPDX license identifier markers at the start of C files (even headers have C style markers). Signed-off-by: Olliver Schinagl --- .../include/asm/mach-rtl838x/mach-rtl83xx.h | 2 +- .../arch/mips/kernel/cevt-rtl9300.c | 14 +- .../files-5.15/drivers/gpio/gpio-rtl8231.c | 8 +- .../drivers/i2c/busses/i2c-rtl9300.c | 36 +-- .../drivers/i2c/busses/i2c-rtl9300.h | 4 +- .../drivers/i2c/muxes/i2c-mux-rtl9300.c | 12 +- .../drivers/net/dsa/rtl83xx/common.c | 151 ++++----- .../drivers/net/dsa/rtl83xx/debugfs.c | 18 +- .../files-5.15/drivers/net/dsa/rtl83xx/dsa.c | 66 ++-- .../files-5.15/drivers/net/dsa/rtl83xx/qos.c | 100 +++--- .../drivers/net/dsa/rtl83xx/rtl838x.c | 244 +++++++-------- .../drivers/net/dsa/rtl83xx/rtl838x.h | 224 ++++++------- .../drivers/net/dsa/rtl83xx/rtl839x.c | 178 +++++------ .../drivers/net/dsa/rtl83xx/rtl930x.c | 294 +++++++++--------- .../drivers/net/dsa/rtl83xx/rtl931x.c | 138 ++++---- .../files-5.15/drivers/net/dsa/rtl83xx/tc.c | 12 +- .../drivers/net/ethernet/rtl838x_eth.c | 126 ++++---- .../drivers/net/ethernet/rtl838x_eth.h | 2 +- .../files-5.15/drivers/net/phy/rtl83xx-phy.c | 287 ++++++++--------- .../files-5.15/drivers/net/phy/rtl83xx-phy.h | 4 +- 20 files changed, 961 insertions(+), 959 deletions(-) diff --git a/target/linux/realtek/files-5.15/arch/mips/include/asm/mach-rtl838x/mach-rtl83xx.h b/target/linux/realtek/files-5.15/arch/mips/include/asm/mach-rtl838x/mach-rtl83xx.h index aa2d918efbc..d9c0b311aea 100644 --- a/target/linux/realtek/files-5.15/arch/mips/include/asm/mach-rtl838x/mach-rtl83xx.h +++ b/target/linux/realtek/files-5.15/arch/mips/include/asm/mach-rtl838x/mach-rtl83xx.h @@ -366,7 +366,7 @@ #define RTL930X_ISR_GLB (0xC658) #define RTL930X_ISR_PORT_LINK_STS_CHG (0xC660) -// IMR_GLB does not exit on RTL931X +/* IMR_GLB does not exit on RTL931X */ #define RTL931X_IMR_PORT_LINK_STS_CHG (0x126C) #define RTL931X_ISR_GLB_SRC (0x12B4) #define RTL931X_ISR_PORT_LINK_STS_CHG (0x12B8) diff --git a/target/linux/realtek/files-5.15/arch/mips/kernel/cevt-rtl9300.c b/target/linux/realtek/files-5.15/arch/mips/kernel/cevt-rtl9300.c index 447e754f203..1f7698d3144 100644 --- a/target/linux/realtek/files-5.15/arch/mips/kernel/cevt-rtl9300.c +++ b/target/linux/realtek/files-5.15/arch/mips/kernel/cevt-rtl9300.c @@ -24,11 +24,11 @@ #define RTL9300_TC_INT_IP BIT(16) #define RTL9300_TC_INT_IE BIT(20) -// Timer modes +/* Timer modes */ #define TIMER_MODE_REPEAT 1 #define TIMER_MODE_ONCE 0 -// Minimum divider is 2 +/* Minimum divider is 2 */ #define DIVISOR_RTL9300 2 #define N_BITS 28 @@ -54,7 +54,7 @@ static irqreturn_t rtl9300_timer_interrupt(int irq, void *dev_id) u32 v = readl(rtl_clk->base + RTL9300_TC_INT); - // Acknowledge the IRQ + /* Acknowledge the IRQ */ v |= RTL9300_TC_INT_IP; writel(v, rtl_clk->base + RTL9300_TC_INT); @@ -69,7 +69,7 @@ static void rtl9300_clock_stop(void __iomem *base) writel(0, base + RTL9300_TC_CTRL); - // Acknowledge possibly pending IRQ + /* Acknowledge possibly pending IRQ */ v = readl(base + RTL9300_TC_INT); writel(v | RTL9300_TC_INT_IP, base + RTL9300_TC_INT); } @@ -132,14 +132,14 @@ static void rtl9300_clock_setup(void __iomem *base) { u32 v; - // Disable timer + /* Disable timer */ writel(0, base + RTL9300_TC_CTRL); - // Acknowledge possibly pending IRQ + /* Acknowledge possibly pending IRQ */ v = readl(base + RTL9300_TC_INT); writel(v | RTL9300_TC_INT_IP, base + RTL9300_TC_INT); - // Setup maximum period (for use as clock-source) + /* Setup maximum period (for use as clock-source) */ writel(0x0fffffff, base + RTL9300_TC_DATA); } diff --git a/target/linux/realtek/files-5.15/drivers/gpio/gpio-rtl8231.c b/target/linux/realtek/files-5.15/drivers/gpio/gpio-rtl8231.c index 0b0d0390593..2821591a97e 100644 --- a/target/linux/realtek/files-5.15/drivers/gpio/gpio-rtl8231.c +++ b/target/linux/realtek/files-5.15/drivers/gpio/gpio-rtl8231.c @@ -45,7 +45,7 @@ static u32 rtl8231_read(struct rtl8231_gpios *gpios, u32 reg) /* Set execution bit: cleared when operation completed */ t |= 1; - // Start execution + /* Start execution */ sw_w32(t, gpios->ext_gpio_indrt_access); do { udelay(1); @@ -76,7 +76,7 @@ static int rtl8231_write(struct rtl8231_gpios *gpios, u32 reg, u32 data) /* Set execution bit: cleared when operation completed */ t |= 1; - // Start execution + /* Start execution */ sw_w32(t, gpios->ext_gpio_indrt_access); do { udelay(1); @@ -259,10 +259,10 @@ int rtl8231_init(struct rtl8231_gpios *gpios) gpios->reg_cached = 0; if (soc_info.family == RTL8390_FAMILY_ID) { - // RTL8390: Enable external gpio in global led control register + /* RTL8390: Enable external gpio in global led control register */ sw_w32_mask(0x7 << 18, 0x4 << 18, RTL839X_LED_GLB_CTRL); } else if (soc_info.family == RTL8380_FAMILY_ID) { - // RTL8380: Enable RTL8231 indirect access mode + /* RTL8380: Enable RTL8231 indirect access mode */ sw_w32_mask(0, 1, RTL838X_EXTRA_GPIO_CTRL); sw_w32_mask(3, 1, RTL838X_DMY_REG5); } diff --git a/target/linux/realtek/files-5.15/drivers/i2c/busses/i2c-rtl9300.c b/target/linux/realtek/files-5.15/drivers/i2c/busses/i2c-rtl9300.c index a1b5f669ba7..9afd2f823ea 100644 --- a/target/linux/realtek/files-5.15/drivers/i2c/busses/i2c-rtl9300.c +++ b/target/linux/realtek/files-5.15/drivers/i2c/busses/i2c-rtl9300.c @@ -28,22 +28,22 @@ DEFINE_MUTEX(i2c_lock); static void rtl9300_i2c_reg_addr_set(struct rtl9300_i2c *i2c, u32 reg, u16 len) { - // Set register address width + /* Set register address width */ REG_MASK(i2c, 0x3 << RTL9300_I2C_CTRL2_MADDR_WIDTH, len << RTL9300_I2C_CTRL2_MADDR_WIDTH, RTL9300_I2C_CTRL2); - // Set register address + /* Set register address */ REG_MASK(i2c, 0xffffff << RTL9300_I2C_CTRL1_MEM_ADDR, reg << RTL9300_I2C_CTRL1_MEM_ADDR, RTL9300_I2C_CTRL1); } static void rtl9310_i2c_reg_addr_set(struct rtl9300_i2c *i2c, u32 reg, u16 len) { - // Set register address width + /* Set register address width */ REG_MASK(i2c, 0x3 << RTL9310_I2C_CTRL_MADDR_WIDTH, len << RTL9310_I2C_CTRL_MADDR_WIDTH, RTL9310_I2C_CTRL); - // Set register address + /* Set register address */ writel(reg, REG(i2c, RTL9310_I2C_MEMADDR)); } @@ -51,14 +51,14 @@ static void rtl9300_i2c_config_io(struct rtl9300_i2c *i2c, int scl_num, int sda_ { u32 v; - // Set SCL pin + /* Set SCL pin */ REG_MASK(i2c, 0, BIT(RTL9300_I2C_CTRL1_GPIO8_SCL_SEL), RTL9300_I2C_CTRL1); - // Set SDA pin + /* Set SDA pin */ REG_MASK(i2c, 0x7 << RTL9300_I2C_CTRL1_SDA_OUT_SEL, i2c->sda_num << RTL9300_I2C_CTRL1_SDA_OUT_SEL, RTL9300_I2C_CTRL1); - // Set SDA pin to I2C functionality + /* Set SDA pin to I2C functionality */ v = readl(i2c->base + RTL9300_I2C_MST_GLB_CTRL); v |= BIT(i2c->sda_num); writel(v, i2c->base + RTL9300_I2C_MST_GLB_CTRL); @@ -68,14 +68,14 @@ static void rtl9310_i2c_config_io(struct rtl9300_i2c *i2c, int scl_num, int sda_ { u32 v; - // Set SCL pin + /* Set SCL pin */ REG_MASK(i2c, 0, BIT(RTL9310_I2C_MST_IF_SEL_GPIO_SCL_SEL + scl_num), RTL9310_I2C_MST_IF_SEL); - // Set SDA pin + /* Set SDA pin */ REG_MASK(i2c, 0x7 << RTL9310_I2C_CTRL_SDA_OUT_SEL, i2c->sda_num << RTL9310_I2C_CTRL_SDA_OUT_SEL, RTL9310_I2C_CTRL); - // Set SDA pin to I2C functionality + /* Set SDA pin to I2C functionality */ v = readl(i2c->base + RTL9310_I2C_MST_IF_SEL); v |= BIT(i2c->sda_num); writel(v, i2c->base + RTL9310_I2C_MST_IF_SEL); @@ -83,19 +83,19 @@ static void rtl9310_i2c_config_io(struct rtl9300_i2c *i2c, int scl_num, int sda_ static int rtl9300_i2c_config_xfer(struct rtl9300_i2c *i2c, u16 addr, u16 len) { - // Set bus frequency + /* Set bus frequency */ REG_MASK(i2c, 0x3 << RTL9300_I2C_CTRL2_SCL_FREQ, i2c->bus_freq << RTL9300_I2C_CTRL2_SCL_FREQ, RTL9300_I2C_CTRL2); - // Set slave device address + /* Set slave device address */ REG_MASK(i2c, 0x7f << RTL9300_I2C_CTRL2_DEV_ADDR, addr << RTL9300_I2C_CTRL2_DEV_ADDR, RTL9300_I2C_CTRL2); - // Set data length + /* Set data length */ REG_MASK(i2c, 0xf << RTL9300_I2C_CTRL2_DATA_WIDTH, ((len - 1) & 0xf) << RTL9300_I2C_CTRL2_DATA_WIDTH, RTL9300_I2C_CTRL2); - // Set read mode to random + /* Set read mode to random */ REG_MASK(i2c, 0x1 << RTL9300_I2C_CTRL2_READ_MODE, 0, RTL9300_I2C_CTRL2); return 0; @@ -103,19 +103,19 @@ static int rtl9300_i2c_config_xfer(struct rtl9300_i2c *i2c, u16 addr, u16 len) static int rtl9310_i2c_config_xfer(struct rtl9300_i2c *i2c, u16 addr, u16 len) { - // Set bus frequency + /* Set bus frequency */ REG_MASK(i2c, 0x3 << RTL9310_I2C_CTRL_SCL_FREQ, i2c->bus_freq << RTL9310_I2C_CTRL_SCL_FREQ, RTL9310_I2C_CTRL); - // Set slave device address + /* Set slave device address */ REG_MASK(i2c, 0x7f << RTL9310_I2C_CTRL_DEV_ADDR, addr << RTL9310_I2C_CTRL_DEV_ADDR, RTL9310_I2C_CTRL); - // Set data length + /* Set data length */ REG_MASK(i2c, 0xf << RTL9310_I2C_CTRL_DATA_WIDTH, ((len - 1) & 0xf) << RTL9310_I2C_CTRL_DATA_WIDTH, RTL9310_I2C_CTRL); - // Set read mode to random + /* Set read mode to random */ REG_MASK(i2c, 0x1 << RTL9310_I2C_CTRL_READ_MODE, 0, RTL9310_I2C_CTRL); return 0; diff --git a/target/linux/realtek/files-5.15/drivers/i2c/busses/i2c-rtl9300.h b/target/linux/realtek/files-5.15/drivers/i2c/busses/i2c-rtl9300.h index b10c38c91ca..617a1b6632c 100644 --- a/target/linux/realtek/files-5.15/drivers/i2c/busses/i2c-rtl9300.h +++ b/target/linux/realtek/files-5.15/drivers/i2c/busses/i2c-rtl9300.h @@ -55,8 +55,8 @@ struct rtl9300_i2c { struct device *dev; struct i2c_adapter adap; u8 bus_freq; - u8 sda_num; // SDA channel number - u8 scl_num; // SCL channel, mapping to master 1 or 2 + u8 sda_num; /* SDA channel number */ + u8 scl_num; /* SCL channel, mapping to master 1 or 2 */ }; #endif diff --git a/target/linux/realtek/files-5.15/drivers/i2c/muxes/i2c-mux-rtl9300.c b/target/linux/realtek/files-5.15/drivers/i2c/muxes/i2c-mux-rtl9300.c index b277c125e9c..57036d9d566 100644 --- a/target/linux/realtek/files-5.15/drivers/i2c/muxes/i2c-mux-rtl9300.c +++ b/target/linux/realtek/files-5.15/drivers/i2c/muxes/i2c-mux-rtl9300.c @@ -48,11 +48,11 @@ static int rtl9300_i2c_mux_select(struct i2c_mux_core *muxc, u32 chan) { struct rtl9300_mux *mux = i2c_mux_priv(muxc); - // Set SCL pin + /* Set SCL pin */ REG_MASK(channels[chan].scl_num, 0, BIT(RTL9300_I2C_CTRL1_GPIO8_SCL_SEL), RTL9300_I2C_CTRL1); - // Set SDA pin + /* Set SDA pin */ REG_MASK(channels[chan].scl_num, 0x7 << RTL9300_I2C_CTRL1_SDA_OUT_SEL, channels[chan].sda_num << RTL9300_I2C_CTRL1_SDA_OUT_SEL, RTL9300_I2C_CTRL1); @@ -66,11 +66,11 @@ static int rtl9310_i2c_mux_select(struct i2c_mux_core *muxc, u32 chan) { struct rtl9300_mux *mux = i2c_mux_priv(muxc); - // Set SCL pin + /* Set SCL pin */ REG_MASK(0, 0, BIT(RTL9310_I2C_MST_IF_SEL_GPIO_SCL_SEL + channels[chan].scl_num), RTL9310_I2C_MST_IF_SEL); - // Set SDA pin + /* Set SDA pin */ REG_MASK(channels[chan].scl_num, 0xf << RTL9310_I2C_CTRL_SDA_OUT_SEL, channels[chan].sda_num << RTL9310_I2C_CTRL_SDA_OUT_SEL, RTL9310_I2C_CTRL); @@ -90,7 +90,7 @@ static void rtl9300_sda_sel(struct i2c_mux_core *muxc, int pin) struct rtl9300_mux *mux = i2c_mux_priv(muxc); u32 v; - // Set SDA pin to I2C functionality + /* Set SDA pin to I2C functionality */ v = readl(REG(0, RTL9300_I2C_MST_GLB_CTRL)); v |= BIT(pin); writel(v, REG(0, RTL9300_I2C_MST_GLB_CTRL)); @@ -101,7 +101,7 @@ static void rtl9310_sda_sel(struct i2c_mux_core *muxc, int pin) struct rtl9300_mux *mux = i2c_mux_priv(muxc); u32 v; - // Set SDA pin to I2C functionality + /* Set SDA pin to I2C functionality */ v = readl(REG(0, RTL9310_I2C_MST_IF_SEL)); v |= BIT(pin); writel(v, REG(0, RTL9310_I2C_MST_IF_SEL)); diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/common.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/common.c index de75b83e2de..2f68a0a1cef 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/common.c +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/common.c @@ -58,28 +58,28 @@ int rtl83xx_port_get_stp_state(struct rtl838x_switch_priv *priv, int port) } static struct table_reg rtl838x_tbl_regs[] = { - TBL_DESC(0x6900, 0x6908, 3, 15, 13, 1), // RTL8380_TBL_L2 - TBL_DESC(0x6914, 0x6918, 18, 14, 12, 1), // RTL8380_TBL_0 - TBL_DESC(0xA4C8, 0xA4CC, 6, 14, 12, 1), // RTL8380_TBL_1 + TBL_DESC(0x6900, 0x6908, 3, 15, 13, 1), /* RTL8380_TBL_L2 */ + TBL_DESC(0x6914, 0x6918, 18, 14, 12, 1), /* RTL8380_TBL_0 */ + TBL_DESC(0xA4C8, 0xA4CC, 6, 14, 12, 1), /* RTL8380_TBL_1 */ - TBL_DESC(0x1180, 0x1184, 3, 16, 14, 0), // RTL8390_TBL_L2 - TBL_DESC(0x1190, 0x1194, 17, 15, 12, 0), // RTL8390_TBL_0 - TBL_DESC(0x6B80, 0x6B84, 4, 14, 12, 0), // RTL8390_TBL_1 - TBL_DESC(0x611C, 0x6120, 9, 8, 6, 0), // RTL8390_TBL_2 + TBL_DESC(0x1180, 0x1184, 3, 16, 14, 0), /* RTL8390_TBL_L2 */ + TBL_DESC(0x1190, 0x1194, 17, 15, 12, 0), /* RTL8390_TBL_0 */ + TBL_DESC(0x6B80, 0x6B84, 4, 14, 12, 0), /* RTL8390_TBL_1 */ + TBL_DESC(0x611C, 0x6120, 9, 8, 6, 0), /* RTL8390_TBL_2 */ - TBL_DESC(0xB320, 0xB334, 3, 18, 16, 0), // RTL9300_TBL_L2 - TBL_DESC(0xB340, 0xB344, 19, 16, 12, 0), // RTL9300_TBL_0 - TBL_DESC(0xB3A0, 0xB3A4, 20, 16, 13, 0), // RTL9300_TBL_1 - TBL_DESC(0xCE04, 0xCE08, 6, 14, 12, 0), // RTL9300_TBL_2 - TBL_DESC(0xD600, 0xD604, 30, 7, 6, 0), // RTL9300_TBL_HSB - TBL_DESC(0x7880, 0x7884, 22, 9, 8, 0), // RTL9300_TBL_HSA + TBL_DESC(0xB320, 0xB334, 3, 18, 16, 0), /* RTL9300_TBL_L2 */ + TBL_DESC(0xB340, 0xB344, 19, 16, 12, 0), /* RTL9300_TBL_0 */ + TBL_DESC(0xB3A0, 0xB3A4, 20, 16, 13, 0), /* RTL9300_TBL_1 */ + TBL_DESC(0xCE04, 0xCE08, 6, 14, 12, 0), /* RTL9300_TBL_2 */ + TBL_DESC(0xD600, 0xD604, 30, 7, 6, 0), /* RTL9300_TBL_HSB */ + TBL_DESC(0x7880, 0x7884, 22, 9, 8, 0), /* RTL9300_TBL_HSA */ - TBL_DESC(0x8500, 0x8508, 8, 19, 15, 0), // RTL9310_TBL_0 - TBL_DESC(0x40C0, 0x40C4, 22, 16, 14, 0), // RTL9310_TBL_1 - TBL_DESC(0x8528, 0x852C, 6, 18, 14, 0), // RTL9310_TBL_2 - TBL_DESC(0x0200, 0x0204, 9, 15, 12, 0), // RTL9310_TBL_3 - TBL_DESC(0x20dc, 0x20e0, 29, 7, 6, 0), // RTL9310_TBL_4 - TBL_DESC(0x7e1c, 0x7e20, 53, 8, 6, 0), // RTL9310_TBL_5 + TBL_DESC(0x8500, 0x8508, 8, 19, 15, 0), /* RTL9310_TBL_0 */ + TBL_DESC(0x40C0, 0x40C4, 22, 16, 14, 0), /* RTL9310_TBL_1 */ + TBL_DESC(0x8528, 0x852C, 6, 18, 14, 0), /* RTL9310_TBL_2 */ + TBL_DESC(0x0200, 0x0204, 9, 15, 12, 0), /* RTL9310_TBL_3 */ + TBL_DESC(0x20dc, 0x20e0, 29, 7, 6, 0), /* RTL9310_TBL_4 */ + TBL_DESC(0x7e1c, 0x7e20, 53, 8, 6, 0), /* RTL9310_TBL_5 */ }; void rtl_table_init(void) @@ -113,9 +113,9 @@ void rtl_table_release(struct table_reg *r) if (!r) return; -// pr_info("Unlocking %08x\n", (u32)r); +/* pr_info("Unlocking %08x\n", (u32)r); */ mutex_unlock(&r->lock); -// pr_info("Unlock done\n"); +/* pr_info("Unlock done\n"); */ } static int rtl_table_exec(struct table_reg *r, bool is_write, int idx) @@ -359,7 +359,7 @@ static int __init rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv) led_set = 0; priv->ports[pn].led_set = led_set; - // Check for the integrated SerDes of the RTL8380M first + /* Check for the integrated SerDes of the RTL8380M first */ if (of_property_read_bool(phy_node, "phy-is-integrated") && priv->id == 0x8380 && pn >= 24) { pr_debug("----> FÓUND A SERDES\n"); @@ -475,15 +475,15 @@ int rtl83xx_lag_add(struct dsa_switch *ds, int group, int port, struct netdev_la case NETDEV_LAG_HASH_L23: algomsk |= TRUNK_DISTRIBUTION_ALGO_DMAC_BIT; algomsk |= TRUNK_DISTRIBUTION_ALGO_SMAC_BIT; - algomsk |= TRUNK_DISTRIBUTION_ALGO_SIP_BIT; //source ip - algomsk |= TRUNK_DISTRIBUTION_ALGO_DIP_BIT; //dest ip + algomsk |= TRUNK_DISTRIBUTION_ALGO_SIP_BIT; /* source ip */ + algomsk |= TRUNK_DISTRIBUTION_ALGO_DIP_BIT; /* dest ip */ algoidx = 1; break; case NETDEV_LAG_HASH_L34: - algomsk |= TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT; //sport - algomsk |= TRUNK_DISTRIBUTION_ALGO_DST_L4PORT_BIT; //dport - algomsk |= TRUNK_DISTRIBUTION_ALGO_SIP_BIT; //source ip - algomsk |= TRUNK_DISTRIBUTION_ALGO_DIP_BIT; //dest ip + algomsk |= TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT; /* sport */ + algomsk |= TRUNK_DISTRIBUTION_ALGO_DST_L4PORT_BIT; /* dport */ + algomsk |= TRUNK_DISTRIBUTION_ALGO_SIP_BIT; /* source ip */ + algomsk |= TRUNK_DISTRIBUTION_ALGO_DIP_BIT; /* dest ip */ algoidx = 2; break; default: @@ -519,7 +519,7 @@ int rtl83xx_lag_del(struct dsa_switch *ds, int group, int port) return -ENOSPC; } - // 0x7f algo mask all + /* 0x7f algo mask all */ priv->r->mask_port_reg_be(BIT_ULL(port), 0, priv->r->trk_mbr_ctr(group)); priv->lags_port_members[group] &= ~BIT_ULL(port); @@ -603,7 +603,7 @@ int rtl83xx_l2_nexthop_add(struct rtl838x_switch_priv *priv, struct rtl83xx_next u64_to_ether_addr(nh->mac, &e.mac[0]); e.port = nh->port; - // Loop over all entries in the hash-bucket and over the second block on 93xx SoCs + /* Loop over all entries in the hash-bucket and over the second block on 93xx SoCs */ for (i = 0; i < priv->l2_bucket_size; i++) { entry = priv->r->read_l2_entry_using_hash(key, i, &e); @@ -619,14 +619,14 @@ int rtl83xx_l2_nexthop_add(struct rtl838x_switch_priv *priv, struct rtl83xx_next return -1; } - // Found an existing (e->valid is true) or empty entry, make it a nexthop entry + /* Found an existing (e->valid is true) or empty entry, make it a nexthop entry */ nh->l2_id = idx; if (e.valid) { nh->port = e.port; - nh->vid = e.vid; // Save VID + nh->vid = e.vid; /* Save VID */ nh->rvid = e.rvid; nh->dev_id = e.stack_dev; - // If the entry is already a valid next hop entry, don't change it + /* If the entry is already a valid next hop entry, don't change it */ if (e.next_hop) return 0; } else { @@ -638,12 +638,12 @@ int rtl83xx_l2_nexthop_add(struct rtl838x_switch_priv *priv, struct rtl83xx_next e.block_da = false; e.block_sa = false; e.suspended = false; - e.age = 0; // With port-ignore + e.age = 0; /* With port-ignore */ e.port = priv->port_ignore; u64_to_ether_addr(nh->mac, &e.mac[0]); } e.next_hop = true; - e.nh_route_id = nh->id; // NH route ID takes place of VID + e.nh_route_id = nh->id; /* NH route ID takes place of VID */ e.nh_vlan_target = false; priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e); @@ -671,7 +671,7 @@ int rtl83xx_l2_nexthop_rm(struct rtl838x_switch_priv *priv, struct rtl83xx_nexth if (e.is_static) e.valid = false; e.next_hop = false; - e.vid = nh->vid; // Restore VID + e.vid = nh->vid; /* Restore VID */ e.rvid = nh->rvid; priv->r->write_l2_entry_using_hash(key, i, &e); @@ -740,11 +740,12 @@ int rtl83xx_port_is_under(const struct net_device * dev, struct rtl838x_switch_p { int i; -// TODO: On 5.12: -// if(!dsa_slave_dev_check(dev)) { -// netdev_info(dev, "%s: not a DSA device.\n", __func__); -// return -EINVAL; -// } +/* TODO: On 5.12: + * if(!dsa_slave_dev_check(dev)) { + * netdev_info(dev, "%s: not a DSA device.\n", __func__); + * return -EINVAL; + * } + */ for (i = 0; i < priv->cpu_port; i++) { if (!priv->ports[i].dp) @@ -804,7 +805,7 @@ static int rtl83xx_l3_nexthop_update(struct rtl838x_switch_priv *priv, __be32 i pr_info("%s: Setting up fwding: ip %pI4, GW mac %016llx\n", __func__, &ip_addr, mac); - // Reads the ROUTING table entry associated with the route + /* Reads the ROUTING table entry associated with the route */ priv->r->route_read(r->id, r); pr_info("Route with id %d to %pI4 / %d\n", r->id, &r->dst_ip, r->prefix_len); @@ -812,19 +813,19 @@ static int rtl83xx_l3_nexthop_update(struct rtl838x_switch_priv *priv, __be32 i r->nh.port = priv->port_ignore; r->nh.id = r->id; - // Do we need to explicitly add a DMAC entry with the route's nh index? + /* Do we need to explicitly add a DMAC entry with the route's nh index? */ if (priv->r->set_l3_egress_mac) priv->r->set_l3_egress_mac(r->id, mac); - // Update ROUTING table: map gateway-mac and switch-mac id to route id + /* Update ROUTING table: map gateway-mac and switch-mac id to route id */ rtl83xx_l2_nexthop_add(priv, &r->nh); r->attr.valid = true; r->attr.action = ROUTE_ACT_FORWARD; r->attr.type = 0; - r->attr.hit = false; // Reset route-used indicator + r->attr.hit = false; /* Reset route-used indicator */ - // Add PIE entry with dst_ip and prefix_len + /* Add PIE entry with dst_ip and prefix_len */ r->pr.dip = r->dst_ip; r->pr.dip_m = inet_make_mask(r->prefix_len); @@ -948,7 +949,7 @@ static struct rtl83xx_route *rtl83xx_route_alloc(struct rtl838x_switch_priv *pri r->id = idx; r->gw_ip = ip; - r->pr.id = -1; // We still need to allocate a rule in HW + r->pr.id = -1; /* We still need to allocate a rule in HW */ r->is_host_route = false; err = rhltable_insert(&priv->routes, &r->linkage, route_ht_params); @@ -993,7 +994,7 @@ static struct rtl83xx_route *rtl83xx_host_route_alloc(struct rtl838x_switch_priv r->id = idx + MAX_ROUTES; r->gw_ip = ip; - r->pr.id = -1; // We still need to allocate a rule in HW + r->pr.id = -1; /* We still need to allocate a rule in HW */ r->is_host_route = true; err = rhltable_insert(&priv->routes, &r->linkage, route_ht_params); @@ -1031,7 +1032,7 @@ static void rtl83xx_route_rm(struct rtl838x_switch_priv *priv, struct rtl83xx_ro priv->r->host_route_write(id, r); clear_bit(r->id - MAX_ROUTES, priv->host_route_use_bm); } else { - // If there is a HW representation of the route, delete it + /* If there is a HW representation of the route, delete it */ if (priv->r->route_lookup_hw) { id = priv->r->route_lookup_hw(r); pr_info("%s: Got id for prefix route: %d\n", __func__, id); @@ -1110,13 +1111,13 @@ static int rtl83xx_alloc_router_mac(struct rtl838x_switch_priv *priv, u64 mac) m.valid = true; m.mac = mac; - m.p_type = 0; // An individual port, not a trunk port - m.p_id = 0x3f; // Listen on any port + m.p_type = 0; /* An individual port, not a trunk port */ + m.p_id = 0x3f; /* Listen on any port */ m.p_id_mask = 0; - m.vid = 0; // Listen on any VLAN... - m.vid_mask = 0; // ... so mask needs to be 0 - m.mac_mask = 0xffffffffffffULL; // We want an exact match of the interface MAC - m.action = L3_FORWARD; // Route the packet + m.vid = 0; /* Listen on any VLAN... */ + m.vid_mask = 0; /* ... so mask needs to be 0 */ + m.mac_mask = 0xffffffffffffULL; /* We want an exact match of the interface MAC */ + m.action = L3_FORWARD; /* Route the packet */ priv->r->set_l3_router_mac(free_mac, &m); mutex_unlock(&priv->reg_mutex); @@ -1148,15 +1149,15 @@ static int rtl83xx_alloc_egress_intf(struct rtl838x_switch_priv *priv, u64 mac, return -1; } - // Set up default egress interface 1 + /* Set up default egress interface 1 */ intf.vid = vlan; intf.smac_idx = free_mac; intf.ip4_mtu_id = 1; intf.ip6_mtu_id = 1; - intf.ttl_scope = 1; // TTL - intf.hl_scope = 1; // Hop Limit - intf.ip4_icmp_redirect = intf.ip6_icmp_redirect = 2; // FORWARD - intf.ip4_pbr_icmp_redirect = intf.ip6_pbr_icmp_redirect = 2; // FORWARD; + intf.ttl_scope = 1; /* TTL */ + intf.hl_scope = 1; /* Hop Limit */ + intf.ip4_icmp_redirect = intf.ip6_icmp_redirect = 2; /* FORWARD */ + intf.ip4_pbr_icmp_redirect = intf.ip6_pbr_icmp_redirect = 2; /* FORWARD; */ priv->r->set_l3_egress_intf(free_mac, &intf); priv->r->set_l3_egress_mac(L3_EGRESS_DMACS + free_mac, mac); @@ -1190,22 +1191,22 @@ static int rtl83xx_fib4_add(struct rtl838x_switch_priv *priv, if (port < 0) return -1; - // For now we only work with routes that have a gateway and are not ourself -// if ((!nh->fib_nh_gw4) && (info->dst_len != 32)) -// return 0; + /* For now we only work with routes that have a gateway and are not ourself */ +/* if ((!nh->fib_nh_gw4) && (info->dst_len != 32)) */ +/* return 0; */ if ((info->dst & 0xff) == 0xff) return 0; - // Do not offload routes to 192.168.100.x + /* Do not offload routes to 192.168.100.x */ if ((info->dst & 0xffffff00) == 0xc0a86400) return 0; - // Do not offload routes to 127.x.x.x + /* Do not offload routes to 127.x.x.x */ if ((info->dst & 0xff000000) == 0x7f000000) return 0; - // Allocate route or host-route (entry if hardware supports this) + /* Allocate route or host-route (entry if hardware supports this) */ if (info->dst_len == 32 && priv->r->host_route_write) r = rtl83xx_host_route_alloc(priv, nh->fib_nh_gw4); else @@ -1229,7 +1230,7 @@ static int rtl83xx_fib4_add(struct rtl838x_switch_priv *priv, if (rtl83xx_alloc_router_mac(priv, mac)) goto out_free_rt; - // vid = 0: Do not care about VID + /* vid = 0: Do not care about VID */ r->nh.if_id = rtl83xx_alloc_egress_intf(priv, mac, vlan); if (r->nh.if_id < 0) goto out_free_rmac; @@ -1249,7 +1250,7 @@ static int rtl83xx_fib4_add(struct rtl838x_switch_priv *priv, } } - // We need to resolve the mac address of the GW + /* We need to resolve the mac address of the GW */ if (!to_localhost) rtl83xx_port_ipv4_resolve(priv, dev, nh->fib_nh_gw4); @@ -1266,7 +1267,7 @@ static int rtl83xx_fib6_add(struct rtl838x_switch_priv *priv, struct fib6_entry_notifier_info *info) { pr_debug("In %s\n", __func__); -// nh->fib_nh_flags |= RTNH_F_OFFLOAD; +/* nh->fib_nh_flags |= RTNH_F_OFFLOAD; */ return 0; } @@ -1462,7 +1463,7 @@ static int __init rtl83xx_sw_probe(struct platform_device *pdev) return -EINVAL; } - // Initialize access to RTL switch tables + /* Initialize access to RTL switch tables */ rtl_table_init(); priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); @@ -1623,7 +1624,7 @@ static int __init rtl83xx_sw_probe(struct platform_device *pdev) goto err_register_nb; } - // Initialize hash table for L3 routing + /* Initialize hash table for L3 routing */ rhltable_init(&priv->routes, &route_ht_params); /* Register netevent notifier callback to catch notifications about neighboring @@ -1647,13 +1648,13 @@ static int __init rtl83xx_sw_probe(struct platform_device *pdev) if (err) goto err_register_fib_nb; - // TODO: put this into l2_setup() - // Flood BPDUs to all ports including cpu-port + /* TODO: put this into l2_setup() */ + /* Flood BPDUs to all ports including cpu-port */ if (soc_info.family != RTL9300_FAMILY_ID) { bpdu_mask = soc_info.family == RTL8380_FAMILY_ID ? 0x1FFFFFFF : 0x1FFFFFFFFFFFFF; priv->r->set_port_reg_be(bpdu_mask, priv->r->rma_bpdu_fld_pmask); - // TRAP 802.1X frames (EAPOL) to the CPU-Port, bypass STP and VLANs + /* TRAP 802.1X frames (EAPOL) to the CPU-Port, bypass STP and VLANs */ sw_w32(7, priv->r->spcl_trap_eapol_ctrl); rtl838x_dbgfs_init(priv); @@ -1673,7 +1674,7 @@ err_register_nb: static int rtl83xx_sw_remove(struct platform_device *pdev) { - // TODO: + /* TODO: */ pr_debug("Removing platform driver for rtl83xx-sw\n"); return 0; diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/debugfs.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/debugfs.c index bc7b3f1461d..0ad4872c387 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/debugfs.c +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/debugfs.c @@ -109,21 +109,21 @@ const char *rtl930x_drop_cntr[] = { const char *rtl931x_drop_cntr[] = { "ALE_RX_GOOD_PKTS", "RX_MAX_FRAME_SIZE", "MAC_RX_DROP", "OPENFLOW_IP_MPLS_TTL", "OPENFLOW_TBL_MISS", - "IGR_BW", "SPECIAL_CONGEST", "EGR_QUEUE", "RESERVED", "EGR_LINK_STATUS", "STACK_UCAST_NONUCAST_TTL", // 10 + "IGR_BW", "SPECIAL_CONGEST", "EGR_QUEUE", "RESERVED", "EGR_LINK_STATUS", "STACK_UCAST_NONUCAST_TTL", /* 10 */ "STACK_NONUC_BLOCKING_PMSK", "L2_CRC", "SRC_PORT_FILTER", "PARSER_PACKET_TOO_LONG", "PARSER_MALFORM_PACKET", - "MPLS_OVER_2_LBL", "EACL_METER", "IACL_METER", "PROTO_STORM", "INVALID_CAPWAP_HEADER", // 20 + "MPLS_OVER_2_LBL", "EACL_METER", "IACL_METER", "PROTO_STORM", "INVALID_CAPWAP_HEADER", /* 20 */ "MAC_IP_SUBNET_BASED_VLAN", "OAM_PARSER", "UC_MC_RPF", "IP_MAC_BINDING_MATCH_MISMATCH", "SA_BLOCK", - "TUNNEL_IP_ADDRESS_CHECK", "EACL_DROP", "IACL_DROP", "ATTACK_PREVENT", "SYSTEM_PORT_LIMIT_LEARN", // 30, + "TUNNEL_IP_ADDRESS_CHECK", "EACL_DROP", "IACL_DROP", "ATTACK_PREVENT", "SYSTEM_PORT_LIMIT_LEARN", /* 30 */ "OAMPDU", "CCM_RX", "CFM_UNKNOWN_TYPE", "LBM_LBR_LTM_LTR", "Y_1731", "VLAN_LIMIT_LEARN", - "VLAN_ACCEPT_FRAME_TYPE", "CFI_1", "STATIC_DYNAMIC_PORT_MOVING", "PORT_MOVE_FORBID", // 40 + "VLAN_ACCEPT_FRAME_TYPE", "CFI_1", "STATIC_DYNAMIC_PORT_MOVING", "PORT_MOVE_FORBID", /* 40 */ "L3_CRC", "BPDU_PTP_LLDP_EAPOL_RMA", "MSTP_SRC_DROP_DISABLED_BLOCKING", "INVALID_SA", "NEW_SA", - "VLAN_IGR_FILTER", "IGR_VLAN_CONVERT", "GRATUITOUS_ARP", "MSTP_SRC_DROP", "L2_HASH_FULL", // 50 + "VLAN_IGR_FILTER", "IGR_VLAN_CONVERT", "GRATUITOUS_ARP", "MSTP_SRC_DROP", "L2_HASH_FULL", /* 50 */ "MPLS_UNKNOWN_LBL", "L3_IPUC_NON_IP", "TTL", "MTU", "ICMP_REDIRECT", "STORM_CONTROL", "L3_DIP_DMAC_MISMATCH", - "IP4_IP_OPTION", "IP6_HBH_EXT_HEADER", "IP4_IP6_HEADER_ERROR", // 60 + "IP4_IP_OPTION", "IP6_HBH_EXT_HEADER", "IP4_IP6_HEADER_ERROR", /* 60 */ "ROUTING_IP_ADDR_CHECK", "ROUTING_EXCEPTION", "DA_BLOCK", "OAM_MUX", "PORT_ISOLATION", "VLAN_EGR_FILTER", - "MIRROR_ISOLATE", "MSTP_DESTINATION_DROP", "L2_MC_BRIDGE", "IP_UC_MC_ROUTING_LOOK_UP_MISS", // 70 + "MIRROR_ISOLATE", "MSTP_DESTINATION_DROP", "L2_MC_BRIDGE", "IP_UC_MC_ROUTING_LOOK_UP_MISS", /* 70 */ "L2_UC", "L2_MC", "IP4_MC", "IP6_MC", "L3_UC_MC_ROUTE", "UNKNOWN_L2_UC_FLPM", "BC_FLPM", - "VLAN_PRO_UNKNOWN_L2_MC_FLPM", "VLAN_PRO_UNKNOWN_IP4_MC_FLPM", "VLAN_PROFILE_UNKNOWN_IP6_MC_FLPM" // 80, + "VLAN_PRO_UNKNOWN_L2_MC_FLPM", "VLAN_PRO_UNKNOWN_IP4_MC_FLPM", "VLAN_PROFILE_UNKNOWN_IP6_MC_FLPM", /* 80 */ }; static ssize_t rtl838x_common_read(char __user *buffer, size_t count, @@ -465,7 +465,7 @@ void rtl838x_dbgfs_cleanup(struct rtl838x_switch_priv *priv) { debugfs_remove_recursive(priv->dbgfs_dir); -// kfree(priv->dbgfs_entries); +/* kfree(priv->dbgfs_entries); */ } static int rtl838x_dbgfs_port_init(struct dentry *parent, struct rtl838x_switch_priv *priv, diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/dsa.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/dsa.c index f6e1f55a206..c940ffb9b97 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/dsa.c +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/dsa.c @@ -122,22 +122,22 @@ static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv) pr_info("UNKNOWN_MC_PMASK: %016llx\n", priv->r->read_mcast_pmask(UNKNOWN_MC_PMASK)); priv->r->vlan_profile_dump(0); - info.fid = 0; // Default Forwarding ID / MSTI - info.hash_uc_fid = false; // Do not build the L2 lookup hash with FID, but VID - info.hash_mc_fid = false; // Do the same for Multicast packets - info.profile_id = 0; // Use default Vlan Profile 0 - info.tagged_ports = 0; // Initially no port members + info.fid = 0; /* Default Forwarding ID / MSTI */ + info.hash_uc_fid = false; /* Do not build the L2 lookup hash with FID, but VID */ + info.hash_mc_fid = false; /* Do the same for Multicast packets */ + info.profile_id = 0; /* Use default Vlan Profile 0 */ + info.tagged_ports = 0; /* Initially no port members */ if (priv->family_id == RTL9310_FAMILY_ID) { info.if_id = 0; info.multicast_grp_mask = 0; info.l2_tunnel_list_id = -1; } - // Initialize all vlans 0-4095 + /* Initialize all vlans 0-4095 */ for (i = 0; i < MAX_VLANS; i ++) priv->r->vlan_set_tagged(i, &info); - // reset PVIDs; defaults to 1 on reset + /* reset PVIDs; defaults to 1 on reset */ for (i = 0; i <= priv->ds->num_ports; i++) { priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_INNER, 0); priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_OUTER, 0); @@ -145,7 +145,7 @@ static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv) priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_OUTER, PBVLAN_MODE_UNTAG_AND_PRITAG); } - // Set forwarding action based on inner VLAN tag + /* Set forwarding action based on inner VLAN tag */ for (i = 0; i < priv->cpu_port; i++) priv->r->vlan_fwd_on_inner(i, true); } @@ -248,7 +248,7 @@ static int rtl93xx_setup(struct dsa_switch *ds) sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4); } - // Disable all ports except CPU port + /* Disable all ports except CPU port */ for (i = 0; i < ds->num_ports; i++) priv->ports[i].enable = false; priv->ports[priv->cpu_port].enable = true; @@ -263,7 +263,7 @@ static int rtl93xx_setup(struct dsa_switch *ds) rtl930x_print_matrix(); - // TODO: Initialize statistics + /* TODO: Initialize statistics */ rtl83xx_vlan_setup(priv); @@ -408,7 +408,7 @@ static void rtl93xx_phylink_validate(struct dsa_switch *ds, int port, phylink_set(mask, 1000baseT_Half); } - // Internal phys of the RTL93xx family provide 10G + /* Internal phys of the RTL93xx family provide 10G */ if (priv->ports[port].phy_is_integrated && state->interface == PHY_INTERFACE_MODE_1000BASEX) { phylink_set(mask, 1000baseX_Full); @@ -679,7 +679,7 @@ static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port, reg |= 1 << speed_bit; break; default: - break; // Ignore, including 10MBit which has a speed value of 0 + break; /* Ignore, including 10MBit which has a speed value of 0 */ } if (priv->family_id == RTL8380_FAMILY_ID) { @@ -696,7 +696,7 @@ static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port, reg |= RTL839X_DUPLEX_MODE; } - // LAG members must use DUPLEX and we need to enable the link + /* LAG members must use DUPLEX and we need to enable the link */ if (priv->lagmembers & BIT_ULL(port)) { switch(priv->family_id) { case RTL8380_FAMILY_ID: @@ -708,7 +708,7 @@ static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port, } } - // Disable AN + /* Disable AN */ if (priv->family_id == RTL8380_FAMILY_ID) reg &= ~RTL838X_NWAY_EN; sw_w32(reg, priv->r->mac_force_mode_ctrl(port)); @@ -746,7 +746,7 @@ static void rtl931x_phylink_mac_config(struct dsa_switch *ds, int port, rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_10GBASER); break; case PHY_INTERFACE_MODE_USXGMII: - // Translates to MII_USXGMII_10GSXGMII + /* Translates to MII_USXGMII_10GSXGMII */ band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_USXGMII); rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_USXGMII); break; @@ -772,7 +772,7 @@ static void rtl931x_phylink_mac_config(struct dsa_switch *ds, int port, reg &= ~(RTL931X_DUPLEX_MODE | RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN); reg &= ~(0xf << 12); - reg |= 0x2 << 12; // Set SMI speed to 0x2 + reg |= 0x2 << 12; /* Set SMI speed to 0x2 */ reg |= RTL931X_TX_PAUSE_EN | RTL931X_RX_PAUSE_EN; @@ -797,7 +797,7 @@ static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port, pr_info("%s port %d, mode %x, phy-mode: %s, speed %d, link %d\n", __func__, port, mode, phy_modes(state->interface), state->speed, state->link); - // Nothing to be done for the CPU-port + /* Nothing to be done for the CPU-port */ if (port == priv->cpu_port) return; @@ -819,7 +819,7 @@ static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port, break; case PHY_INTERFACE_MODE_10GBASER: case PHY_INTERFACE_MODE_10GKR: - sds_mode = 0x1b; // 10G 1000X Auto + sds_mode = 0x1b; /* 10G 1000X Auto */ break; case PHY_INTERFACE_MODE_USXGMII: sds_mode = 0x0d; @@ -864,7 +864,7 @@ static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port, reg |= RTL930X_DUPLEX_MODE; if (priv->ports[port].phy_is_integrated) - reg &= ~RTL930X_FORCE_EN; // Clear MAC_FORCE_EN to allow SDS-MAC link + reg &= ~RTL930X_FORCE_EN; /* Clear MAC_FORCE_EN to allow SDS-MAC link */ else reg |= RTL930X_FORCE_EN; @@ -880,7 +880,7 @@ static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port, /* Stop TX/RX to port */ sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port)); - // No longer force link + /* No longer force link */ sw_w32_mask(0x3, 0, priv->r->mac_force_mode_ctrl(port)); } @@ -894,7 +894,7 @@ static void rtl93xx_phylink_mac_link_down(struct dsa_switch *ds, int port, /* Stop TX/RX to port */ sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port)); - // No longer force link + /* No longer force link */ if (priv->family_id == RTL9300_FAMILY_ID) v = RTL930X_FORCE_EN | RTL930X_FORCE_LINK_EN; else if (priv->family_id == RTL9310_FAMILY_ID) @@ -912,7 +912,7 @@ static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port, struct rtl838x_switch_priv *priv = ds->priv; /* Restart TX/RX to port */ sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port)); - // TODO: Set speed/duplex/pauses + /* TODO: Set speed/duplex/pauses */ } static void rtl93xx_phylink_mac_link_up(struct dsa_switch *ds, int port, @@ -926,7 +926,7 @@ static void rtl93xx_phylink_mac_link_up(struct dsa_switch *ds, int port, /* Restart TX/RX to port */ sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port)); - // TODO: Set speed/duplex/pauses + /* TODO: Set speed/duplex/pauses */ } static void rtl83xx_get_strings(struct dsa_switch *ds, @@ -983,7 +983,7 @@ static int rtl83xx_mc_group_alloc(struct rtl838x_switch_priv *priv, int port) } set_bit(mc_group, priv->mc_group_bm); - mc_group++; // We cannot use group 0, as this is used for lookup miss flooding + mc_group++; /* We cannot use group 0, as this is used for lookup miss flooding */ portmask = BIT_ULL(port) | BIT_ULL(priv->cpu_port); priv->r->write_mcast_pmask(mc_group, portmask); @@ -1079,7 +1079,7 @@ static int rtl83xx_port_enable(struct dsa_switch *ds, int port, v |= priv->ports[port].pm; priv->r->traffic_set(port, v); - // TODO: Figure out if this is necessary + /* TODO: Figure out if this is necessary */ if (priv->family_id == RTL9300_FAMILY_ID) { sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL); sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL); @@ -1101,7 +1101,7 @@ static void rtl83xx_port_disable(struct dsa_switch *ds, int port) if (!dsa_is_user_port(ds, port)) return; - // BUG: This does not work on RTL931X + /* BUG: This does not work on RTL931X */ /* remove port from switch mask of CPU_PORT */ priv->r->traffic_disable(priv->cpu_port, port); store_mcgroups(priv, port); @@ -1589,7 +1589,7 @@ static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv *priv, u64 seed u64 entry; pr_debug("%s: using key %x, for seed %016llx\n", __func__, key, seed); - // Loop over all entries in the hash-bucket and over the second block on 93xx SoCs + /* Loop over all entries in the hash-bucket and over the second block on 93xx SoCs */ for (i = 0; i < priv->l2_bucket_size; i++) { entry = priv->r->read_l2_entry_using_hash(key, i, e); pr_debug("valid %d, mac %016llx\n", e->valid, ether_addr_to_u64(&e->mac[0])); @@ -1649,14 +1649,14 @@ static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port, idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e); - // Found an existing or empty entry + /* Found an existing or empty entry */ if (idx >= 0) { rtl83xx_setup_l2_uc_entry(&e, port, vid, mac); priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e); goto out; } - // Hash buckets full, try CAM + /* Hash buckets full, try CAM */ rtl83xx_find_l2_cam_entry(priv, seed, false, &e); if (idx >= 0) { @@ -1772,7 +1772,7 @@ static int rtl83xx_port_mdb_add(struct dsa_switch *ds, int port, idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e); - // Found an existing or empty entry + /* Found an existing or empty entry */ if (idx >= 0) { if (e.valid) { pr_debug("Found an existing entry %016llx, mc_group %d\n", @@ -1791,7 +1791,7 @@ static int rtl83xx_port_mdb_add(struct dsa_switch *ds, int port, goto out; } - // Hash buckets full, try CAM + /* Hash buckets full, try CAM */ rtl83xx_find_l2_cam_entry(priv, seed, false, &e); if (idx >= 0) { @@ -1865,7 +1865,7 @@ int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port, } goto out; } - // TODO: Re-enable with a newer kernel: err = -ENOENT; + /* TODO: Re-enable with a newer kernel: err = -ENOENT; */ out: mutex_unlock(&priv->reg_mutex); @@ -2032,7 +2032,7 @@ static int rtl83xx_port_lag_change(struct dsa_switch *ds, int port) struct rtl838x_switch_priv *priv = ds->priv; pr_debug("%s: %d\n", __func__, port); - // Nothing to be done... + /* Nothing to be done... */ return 0; } diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/qos.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/qos.c index 8a2621fb28b..59d043581b1 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/qos.c +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/qos.c @@ -47,7 +47,7 @@ static void rtl839x_read_out_q_table(int port) static void rtl838x_storm_enable(struct rtl838x_switch_priv *priv, int port, bool enable) { - // Enable Storm control for that port for UC, MC, and BC + /* Enable Storm control for that port for UC, MC, and BC */ if (enable) sw_w32(0x7, RTL838X_STORM_CTRL_LB_CTRL(port)); else @@ -96,24 +96,24 @@ static void rtl838x_rate_control_init(struct rtl838x_switch_priv *priv) int i; pr_info("Enabling Storm control\n"); - // TICK_PERIOD_PPS + /* TICK_PERIOD_PPS */ if (priv->id == 0x8380) sw_w32_mask(0x3ff << 20, 434 << 20, RTL838X_SCHED_LB_TICK_TKN_CTRL_0); - // Set burst rate - sw_w32(0x00008000, RTL838X_STORM_CTRL_BURST_0); // UC - sw_w32(0x80008000, RTL838X_STORM_CTRL_BURST_1); // MC and BC + /* Set burst rate */ + sw_w32(0x00008000, RTL838X_STORM_CTRL_BURST_0); /* UC */ + sw_w32(0x80008000, RTL838X_STORM_CTRL_BURST_1); /* MC and BC */ - // Set burst Packets per Second to 32 - sw_w32(0x00000020, RTL838X_STORM_CTRL_BURST_PPS_0); // UC - sw_w32(0x00200020, RTL838X_STORM_CTRL_BURST_PPS_1); // MC and BC + /* Set burst Packets per Second to 32 */ + sw_w32(0x00000020, RTL838X_STORM_CTRL_BURST_PPS_0); /* UC */ + sw_w32(0x00200020, RTL838X_STORM_CTRL_BURST_PPS_1); /* MC and BC */ - // Include IFG in storm control, rate based on bytes/s (0 = packets) + /* Include IFG in storm control, rate based on bytes/s (0 = packets) */ sw_w32_mask(0, 1 << 6 | 1 << 5, RTL838X_STORM_CTRL); - // Bandwidth control includes preamble and IFG (10 Bytes) + /* Bandwidth control includes preamble and IFG (10 Bytes) */ sw_w32_mask(0, 1, RTL838X_SCHED_CTRL); - // On SoCs except RTL8382M, set burst size of port egress + /* On SoCs except RTL8382M, set burst size of port egress */ if (priv->id != 0x8382) sw_w32_mask(0xffff, 0x800, RTL838X_SCHED_LB_THR); @@ -129,14 +129,14 @@ static void rtl838x_rate_control_init(struct rtl838x_switch_priv *priv) } } - // Attack prevention, enable all attack prevention measures - //sw_w32(0x1ffff, RTL838X_ATK_PRVNT_CTRL); + /* Attack prevention, enable all attack prevention measures */ + /* sw_w32(0x1ffff, RTL838X_ATK_PRVNT_CTRL); */ /* Attack prevention, drop (bit = 0) problematic packets on all ports. * Setting bit = 1 means: trap to CPU */ - //sw_w32(0, RTL838X_ATK_PRVNT_ACT); - // Enable attack prevention on all ports - //sw_w32(0x0fffffff, RTL838X_ATK_PRVNT_PORT_EN); + /* sw_w32(0, RTL838X_ATK_PRVNT_ACT); */ + /* Enable attack prevention on all ports */ + /* sw_w32(0x0fffffff, RTL838X_ATK_PRVNT_PORT_EN); */ } /* Sets the rate limit, 10MBit/s is equal to a rate value of 625 */ @@ -228,21 +228,21 @@ static void rtl839x_rate_control_init(struct rtl838x_switch_priv *priv) /* Tick length and token size settings for SoC with 250MHz, * RTL8350 family would use 50MHz */ - // Set the special tick period + /* Set the special tick period */ sw_w32(976563, RTL839X_STORM_CTRL_SPCL_LB_TICK_TKN_CTRL); - // Ingress tick period and token length 10G + /* Ingress tick period and token length 10G */ sw_w32(18 << 11 | 151, RTL839X_IGR_BWCTRL_LB_TICK_TKN_CTRL_0); - // Ingress tick period and token length 1G + /* Ingress tick period and token length 1G */ sw_w32(245 << 11 | 129, RTL839X_IGR_BWCTRL_LB_TICK_TKN_CTRL_1); - // Egress tick period 10G, bytes/token 10G and tick period 1G, bytes/token 1G + /* Egress tick period 10G, bytes/token 10G and tick period 1G, bytes/token 1G */ sw_w32(18 << 24 | 151 << 16 | 185 << 8 | 97, RTL839X_SCHED_LB_TICK_TKN_CTRL); - // Set the tick period of the CPU and the Token Len + /* Set the tick period of the CPU and the Token Len */ sw_w32(3815 << 8 | 1, RTL839X_SCHED_LB_TICK_TKN_PPS_CTRL); - // Set the Weighted Fair Queueing burst size + /* Set the Weighted Fair Queueing burst size */ sw_w32_mask(0xffff, 4500, RTL839X_SCHED_LB_THR); - // Storm-rate calculation is based on bytes/sec (bit 5), include IFG (bit 6) + /* Storm-rate calculation is based on bytes/sec (bit 5), include IFG (bit 6) */ sw_w32_mask(0, 1 << 5 | 1 << 6, RTL839X_STORM_CTRL); /* Based on the rate control mode being bytes/s @@ -270,24 +270,24 @@ static void rtl839x_rate_control_init(struct rtl838x_switch_priv *priv) continue; if (priv->ports[p].is10G) - rtl839x_set_egress_rate(priv, p, 625000); // 10GB/s + rtl839x_set_egress_rate(priv, p, 625000); /* 10GB/s */ else - rtl839x_set_egress_rate(priv, p, 62500); // 1GB/s + rtl839x_set_egress_rate(priv, p, 62500); /* 1GB/s */ - // Setup queues: all RTL83XX SoCs have 8 queues, maximum rate + /* Setup queues: all RTL83XX SoCs have 8 queues, maximum rate */ for (q = 0; q < 8; q++) rtl839x_egress_rate_queue_limit(priv, p, q, 0xfffff); if (priv->ports[p].is10G) { - // Set high threshold to maximum + /* Set high threshold to maximum */ sw_w32_mask(0xffff, 0xffff, RTL839X_IGR_BWCTRL_PORT_CTRL_10G_0(p)); } else { - // Set high threshold to maximum + /* Set high threshold to maximum */ sw_w32_mask(0xffff, 0xffff, RTL839X_IGR_BWCTRL_PORT_CTRL_1(p)); } } - // Set global ingress low watermark rate + /* Set global ingress low watermark rate */ sw_w32(65532, RTL839X_IGR_BWCTRL_CTRL_LB_THR); } @@ -382,24 +382,24 @@ void rtl839x_set_scheduling_algorithm(struct rtl838x_switch_priv *priv, int port mutex_lock(&priv->reg_mutex); /* Check whether we need to empty the egress queue of that port due to Errata E0014503 */ if (sched == WEIGHTED_FAIR_QUEUE && t == WEIGHTED_ROUND_ROBIN && port != priv->cpu_port) { - // Read Operations, Adminstatrion and Management control register + /* Read Operations, Adminstatrion and Management control register */ oam_state = sw_r32(RTL839X_OAM_CTRL); - // Get current OAM state + /* Get current OAM state */ oam_port_state = sw_r32(RTL839X_OAM_PORT_ACT_CTRL(port)); - // Disable OAM to block traffice + /* Disable OAM to block traffice */ v = sw_r32(RTL839X_OAM_CTRL); sw_w32_mask(0, 1, RTL839X_OAM_CTRL); v = sw_r32(RTL839X_OAM_CTRL); - // Set to trap action OAM forward (bits 1, 2) and OAM Mux Action Drop (bit 0) + /* Set to trap action OAM forward (bits 1, 2) and OAM Mux Action Drop (bit 0) */ sw_w32(0x2, RTL839X_OAM_PORT_ACT_CTRL(port)); - // Set port egress rate to unlimited + /* Set port egress rate to unlimited */ egress_rate = rtl839x_set_egress_rate(priv, port, 0xFFFFF); - // Wait until the egress used page count of that port is 0 + /* Wait until the egress used page count of that port is 0 */ i = 0; do { usleep_range(100, 200); @@ -410,19 +410,19 @@ void rtl839x_set_scheduling_algorithm(struct rtl838x_switch_priv *priv, int port } while (i < 3500 && count > 0); } - // Actually set the scheduling algorithm + /* Actually set the scheduling algorithm */ rtl839x_read_scheduling_table(port); sw_w32_mask(BIT(19), sched ? BIT(19) : 0, RTL839X_TBL_ACCESS_DATA_2(8)); rtl839x_write_scheduling_table(port); if (sched == WEIGHTED_FAIR_QUEUE && t == WEIGHTED_ROUND_ROBIN && port != priv->cpu_port) { - // Restore OAM state to control register + /* Restore OAM state to control register */ sw_w32(oam_state, RTL839X_OAM_CTRL); - // Restore trap action state + /* Restore trap action state */ sw_w32(oam_port_state, RTL839X_OAM_PORT_ACT_CTRL(port)); - // Restore port egress rate + /* Restore port egress rate */ rtl839x_set_egress_rate(priv, port, egress_rate); } @@ -463,7 +463,7 @@ void rtl838x_config_qos(void) pr_info("RTL838X_PRI_SEL_TBL_CTRL(i): %08x\n", sw_r32(RTL838X_PRI_SEL_TBL_CTRL(0))); rtl83xx_setup_default_prio2queue(); - // Enable inner (bit 12) and outer (bit 13) priority remapping from DSCP + /* Enable inner (bit 12) and outer (bit 13) priority remapping from DSCP */ sw_w32_mask(0, BIT(12) | BIT(13), RTL838X_PRI_DSCP_INVLD_CTRL0); /* Set default weight for calculating internal priority, in prio selection group 0 @@ -472,7 +472,7 @@ void rtl838x_config_qos(void) v = 3 | (4 << 3) | (5 << 6) | (6 << 9) | (7 << 12); sw_w32(v, RTL838X_PRI_SEL_TBL_CTRL(0)); - // Set the inner and outer priority one-to-one to re-marked outer dot1p priority + /* Set the inner and outer priority one-to-one to re-marked outer dot1p priority */ v = 0; for (p = 0; p < 8; p++) v |= p << (3 * p); @@ -484,19 +484,19 @@ void rtl838x_config_qos(void) v |= (dot1p_priority_remapping[p] & 0x7) << (p * 3); sw_w32(v, RTL838X_PRI_SEL_IPRI_REMAP); - // On all ports set scheduler type to WFQ + /* On all ports set scheduler type to WFQ */ for (i = 0; i <= soc_info.cpu_port; i++) sw_w32(0, RTL838X_SCHED_P_TYPE_CTRL(i)); - // Enable egress scheduler for CPU-Port + /* Enable egress scheduler for CPU-Port */ sw_w32_mask(0, BIT(8), RTL838X_SCHED_LB_CTRL(soc_info.cpu_port)); - // Enable egress drop allways on + /* Enable egress drop allways on */ sw_w32_mask(0, BIT(11), RTL838X_FC_P_EGR_DROP_CTRL(soc_info.cpu_port)); - // Give special trap frames priority 7 (BPDUs) and routing exceptions: + /* Give special trap frames priority 7 (BPDUs) and routing exceptions: */ sw_w32_mask(0, 7 << 3 | 7, RTL838X_QM_PKT2CPU_INTPRI_2); - // Give RMA frames priority 7: + /* Give RMA frames priority 7: */ sw_w32_mask(0, 7, RTL838X_QM_PKT2CPU_INTPRI_1); } @@ -513,18 +513,18 @@ void rtl839x_config_qos(void) for (port = 0; port < soc_info.cpu_port; port++) sw_w32(7, RTL839X_QM_PORT_QNUM(port)); - // CPU-port gets queue number 7 + /* CPU-port gets queue number 7 */ sw_w32(7, RTL839X_QM_PORT_QNUM(soc_info.cpu_port)); for (port = 0; port <= soc_info.cpu_port; port++) { rtl83xx_set_ingress_priority(port, 0); rtl839x_set_scheduling_algorithm(priv, port, WEIGHTED_FAIR_QUEUE); rtl839x_set_scheduling_queue_weights(priv, port, default_queue_weights); - // Do re-marking based on outer tag + /* Do re-marking based on outer tag */ sw_w32_mask(0, BIT(port % 32), RTL839X_RMK_PORT_DEI_TAG_CTRL(port)); } - // Remap dot1p priorities to internal priority, for this the outer tag needs be re-marked + /* Remap dot1p priorities to internal priority, for this the outer tag needs be re-marked */ v = 0; for (p = 0; p < 8; p++) v |= (dot1p_priority_remapping[p] & 0x7) << (p * 3); @@ -537,7 +537,7 @@ void rtl839x_config_qos(void) */ sw_w32(2 << 2, RTL839X_PRI_SEL_DEI2DP_REMAP); - // Re-mark DEI: 4 bit-fields of 2 bits each, field 0 is bits 0-1, ... + /* Re-mark DEI: 4 bit-fields of 2 bits each, field 0 is bits 0-1, ... */ sw_w32((0x1 << 2) | (0x1 << 4), RTL839X_RMK_DEI_CTRL); /* Set Congestion avoidance drop probability to 0 for drop precedences 0-2 (bits 24-31) diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.c index bd24b4e0ac2..124cd564785 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.c +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.c @@ -24,54 +24,54 @@ extern struct mutex smi_lock; -// see_dal_maple_acl_log2PhyTmplteField and src/app/diag_v2/src/diag_acl.c +/* see_dal_maple_acl_log2PhyTmplteField and src/app/diag_v2/src/diag_acl.c */ /* Definition of the RTL838X-specific template field IDs as used in the PIE */ enum template_field_id { TEMPLATE_FIELD_SPMMASK = 0, - TEMPLATE_FIELD_SPM0 = 1, // Source portmask ports 0-15 - TEMPLATE_FIELD_SPM1 = 2, // Source portmask ports 16-28 + TEMPLATE_FIELD_SPM0 = 1, /* Source portmask ports 0-15 */ + TEMPLATE_FIELD_SPM1 = 2, /* Source portmask ports 16-28 */ TEMPLATE_FIELD_RANGE_CHK = 3, - TEMPLATE_FIELD_DMAC0 = 4, // Destination MAC [15:0] - TEMPLATE_FIELD_DMAC1 = 5, // Destination MAC [31:16] - TEMPLATE_FIELD_DMAC2 = 6, // Destination MAC [47:32] - TEMPLATE_FIELD_SMAC0 = 7, // Source MAC [15:0] - TEMPLATE_FIELD_SMAC1 = 8, // Source MAC [31:16] - TEMPLATE_FIELD_SMAC2 = 9, // Source MAC [47:32] - TEMPLATE_FIELD_ETHERTYPE = 10, // Ethernet typ - TEMPLATE_FIELD_OTAG = 11, // Outer VLAN tag - TEMPLATE_FIELD_ITAG = 12, // Inner VLAN tag - TEMPLATE_FIELD_SIP0 = 13, // IPv4 or IPv6 source IP[15:0] or ARP/RARP - // source protocol address in header - TEMPLATE_FIELD_SIP1 = 14, // IPv4 or IPv6 source IP[31:16] or ARP/RARP - TEMPLATE_FIELD_DIP0 = 15, // IPv4 or IPv6 destination IP[15:0] - TEMPLATE_FIELD_DIP1 = 16, // IPv4 or IPv6 destination IP[31:16] - TEMPLATE_FIELD_IP_TOS_PROTO = 17, // IPv4 TOS/IPv6 traffic class and - // IPv4 proto/IPv6 next header fields - TEMPLATE_FIELD_L34_HEADER = 18, // packet with extra tag and IPv6 with auth, dest, - // frag, route, hop-by-hop option header, - // IGMP type, TCP flag - TEMPLATE_FIELD_L4_SPORT = 19, // TCP/UDP source port - TEMPLATE_FIELD_L4_DPORT = 20, // TCP/UDP destination port + TEMPLATE_FIELD_DMAC0 = 4, /* Destination MAC [15:0] */ + TEMPLATE_FIELD_DMAC1 = 5, /* Destination MAC [31:16] */ + TEMPLATE_FIELD_DMAC2 = 6, /* Destination MAC [47:32] */ + TEMPLATE_FIELD_SMAC0 = 7, /* Source MAC [15:0] */ + TEMPLATE_FIELD_SMAC1 = 8, /* Source MAC [31:16] */ + TEMPLATE_FIELD_SMAC2 = 9, /* Source MAC [47:32] */ + TEMPLATE_FIELD_ETHERTYPE = 10, /* Ethernet typ */ + TEMPLATE_FIELD_OTAG = 11, /* Outer VLAN tag */ + TEMPLATE_FIELD_ITAG = 12, /* Inner VLAN tag */ + TEMPLATE_FIELD_SIP0 = 13, /* IPv4 or IPv6 source IP[15:0] or ARP/RARP */ + /* source protocol address in header */ + TEMPLATE_FIELD_SIP1 = 14, /* IPv4 or IPv6 source IP[31:16] or ARP/RARP */ + TEMPLATE_FIELD_DIP0 = 15, /* IPv4 or IPv6 destination IP[15:0] */ + TEMPLATE_FIELD_DIP1 = 16, /* IPv4 or IPv6 destination IP[31:16] */ + TEMPLATE_FIELD_IP_TOS_PROTO = 17, /* IPv4 TOS/IPv6 traffic class and */ + /* IPv4 proto/IPv6 next header fields */ + TEMPLATE_FIELD_L34_HEADER = 18, /* packet with extra tag and IPv6 with auth, dest, */ + /* frag, route, hop-by-hop option header, */ + /* IGMP type, TCP flag */ + TEMPLATE_FIELD_L4_SPORT = 19, /* TCP/UDP source port */ + TEMPLATE_FIELD_L4_DPORT = 20, /* TCP/UDP destination port */ TEMPLATE_FIELD_ICMP_IGMP = 21, TEMPLATE_FIELD_IP_RANGE = 22, - TEMPLATE_FIELD_FIELD_SELECTOR_VALID = 23, // Field selector mask + TEMPLATE_FIELD_FIELD_SELECTOR_VALID = 23, /* Field selector mask */ TEMPLATE_FIELD_FIELD_SELECTOR_0 = 24, TEMPLATE_FIELD_FIELD_SELECTOR_1 = 25, TEMPLATE_FIELD_FIELD_SELECTOR_2 = 26, TEMPLATE_FIELD_FIELD_SELECTOR_3 = 27, - TEMPLATE_FIELD_SIP2 = 28, // IPv6 source IP[47:32] - TEMPLATE_FIELD_SIP3 = 29, // IPv6 source IP[63:48] - TEMPLATE_FIELD_SIP4 = 30, // IPv6 source IP[79:64] - TEMPLATE_FIELD_SIP5 = 31, // IPv6 source IP[95:80] - TEMPLATE_FIELD_SIP6 = 32, // IPv6 source IP[111:96] - TEMPLATE_FIELD_SIP7 = 33, // IPv6 source IP[127:112] - TEMPLATE_FIELD_DIP2 = 34, // IPv6 destination IP[47:32] - TEMPLATE_FIELD_DIP3 = 35, // IPv6 destination IP[63:48] - TEMPLATE_FIELD_DIP4 = 36, // IPv6 destination IP[79:64] - TEMPLATE_FIELD_DIP5 = 37, // IPv6 destination IP[95:80] - TEMPLATE_FIELD_DIP6 = 38, // IPv6 destination IP[111:96] - TEMPLATE_FIELD_DIP7 = 39, // IPv6 destination IP[127:112] - TEMPLATE_FIELD_FWD_VID = 40, // Forwarding VLAN-ID + TEMPLATE_FIELD_SIP2 = 28, /* IPv6 source IP[47:32] */ + TEMPLATE_FIELD_SIP3 = 29, /* IPv6 source IP[63:48] */ + TEMPLATE_FIELD_SIP4 = 30, /* IPv6 source IP[79:64] */ + TEMPLATE_FIELD_SIP5 = 31, /* IPv6 source IP[95:80] */ + TEMPLATE_FIELD_SIP6 = 32, /* IPv6 source IP[111:96] */ + TEMPLATE_FIELD_SIP7 = 33, /* IPv6 source IP[127:112] */ + TEMPLATE_FIELD_DIP2 = 34, /* IPv6 destination IP[47:32] */ + TEMPLATE_FIELD_DIP3 = 35, /* IPv6 destination IP[63:48] */ + TEMPLATE_FIELD_DIP4 = 36, /* IPv6 destination IP[79:64] */ + TEMPLATE_FIELD_DIP5 = 37, /* IPv6 destination IP[95:80] */ + TEMPLATE_FIELD_DIP6 = 38, /* IPv6 destination IP[111:96] */ + TEMPLATE_FIELD_DIP7 = 39, /* IPv6 destination IP[127:112] */ + TEMPLATE_FIELD_FWD_VID = 40, /* Forwarding VLAN-ID */ TEMPLATE_FIELD_FLOW_LABEL = 41, }; @@ -151,7 +151,7 @@ static inline int rtl838x_tbl_access_data_0(int i) static void rtl838x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info) { u32 v; - // Read VLAN table (0) via register 0 + /* Read VLAN table (0) via register 0 */ struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 0); rtl_table_read(r, vlan); @@ -165,7 +165,7 @@ static void rtl838x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info) info->hash_uc_fid = !!(v & 0x10); info->fid = (v >> 5) & 0x3f; - // Read UNTAG table (0) via table register 1 + /* Read UNTAG table (0) via table register 1 */ r = rtl_table_get(RTL8380_TBL_1, 0); rtl_table_read(r, vlan); info->untagged_ports = sw_r32(rtl_table_data(r, 0)); @@ -175,7 +175,7 @@ static void rtl838x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info) static void rtl838x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info) { u32 v; - // Access VLAN table (0) via register 0 + /* Access VLAN table (0) via register 0 */ struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 0); sw_w32(info->tagged_ports, rtl_table_data(r, 0)); @@ -192,7 +192,7 @@ static void rtl838x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info) static void rtl838x_vlan_set_untagged(u32 vlan, u64 portmask) { - // Access UNTAG table (0) via register 1 + /* Access UNTAG table (0) via register 1 */ struct table_reg *r = rtl_table_get(RTL8380_TBL_1, 0); sw_w32(portmask & 0x1fffffff, rtl_table_data(r, 0)); @@ -320,13 +320,13 @@ static void rtl838x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e) e->valid = false; else e->type = L2_UNICAST; - } else { // L2 multicast + } else { /* L2 multicast */ pr_debug("Got L2 MC entry: %08x %08x %08x\n", r[0], r[1], r[2]); e->valid = true; e->type = L2_MULTICAST; e->mc_portmask_index = (r[0] >> 12) & 0x1ff; } - } else { // IPv4 and IPv6 multicast + } else { /* IPv4 and IPv6 multicast */ e->valid = true; e->mc_portmask_index = (r[0] >> 12) & 0x1ff; e->mc_gip = (r[1] << 20) | (r[2] >> 12); @@ -370,13 +370,13 @@ static void rtl838x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e) r[0] |= e->nh_route_id & 0x1ff; } r[0] |= (e->age & 0x3) << 17; - } else { // L2 Multicast + } else { /* L2 Multicast */ r[0] |= (e->mc_portmask_index & 0x1ff) << 12; r[2] |= e->rvid & 0xfff; r[0] |= e->vid & 0xfff; pr_debug("FILL MC: %08x %08x %08x\n", r[0], r[1], r[2]); } - } else { // IPv4 and IPv6 multicast + } else { /* IPv4 and IPv6 multicast */ r[0] |= (e->mc_portmask_index & 0x1ff) << 12; r[1] = e->mc_gip >> 20; r[2] = e->mc_gip << 12; @@ -391,8 +391,8 @@ static void rtl838x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e) static u64 rtl838x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e) { u32 r[3]; - struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 0); // Access L2 Table 0 - u32 idx = (0 << 14) | (hash << 2) | pos; // Search SRAM, with hash and at pos in bucket + struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 0); /* Access L2 Table 0 */ + u32 idx = (0 << 14) | (hash << 2) | pos; /* Search SRAM, with hash and at pos in bucket */ int i; rtl_table_read(q, idx); @@ -405,7 +405,7 @@ static u64 rtl838x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2 if (!e->valid) return 0; - return (((u64) r[1]) << 32) | (r[2]); // mac and vid concatenated as hash seed + return (((u64) r[1]) << 32) | (r[2]); /* mac and vid concatenated as hash seed */ } static void rtl838x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e) @@ -414,7 +414,7 @@ static void rtl838x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_ struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 0); int i; - u32 idx = (0 << 14) | (hash << 2) | pos; // Access SRAM, with hash and at pos in bucket + u32 idx = (0 << 14) | (hash << 2) | pos; /* Access SRAM, with hash and at pos in bucket */ rtl838x_fill_l2_row(r, e); @@ -428,7 +428,7 @@ static void rtl838x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_ static u64 rtl838x_read_cam(int idx, struct rtl838x_l2_entry *e) { u32 r[3]; - struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 1); // Access L2 Table 1 + struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 1); /* Access L2 Table 1 */ int i; rtl_table_read(q, idx); @@ -443,14 +443,14 @@ static u64 rtl838x_read_cam(int idx, struct rtl838x_l2_entry *e) pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]); - // Return MAC with concatenated VID ac concatenated ID + /* Return MAC with concatenated VID ac concatenated ID */ return (((u64) r[1]) << 32) | r[2]; } static void rtl838x_write_cam(int idx, struct rtl838x_l2_entry *e) { u32 r[3]; - struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 1); // Access L2 Table 1 + struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 1); /* Access L2 Table 1 */ int i; rtl838x_fill_l2_row(r, e); @@ -465,7 +465,7 @@ static void rtl838x_write_cam(int idx, struct rtl838x_l2_entry *e) static u64 rtl838x_read_mcast_pmask(int idx) { u32 portmask; - // Read MC_PMSK (2) via register RTL8380_TBL_L2 + /* Read MC_PMSK (2) via register RTL8380_TBL_L2 */ struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 2); rtl_table_read(q, idx); @@ -477,7 +477,7 @@ static u64 rtl838x_read_mcast_pmask(int idx) static void rtl838x_write_mcast_pmask(int idx, u64 portmask) { - // Access MC_PMSK (2) via register RTL8380_TBL_L2 + /* Access MC_PMSK (2) via register RTL8380_TBL_L2 */ struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 2); sw_w32(((u32)portmask) & 0x1fffffff, rtl_table_data(q, 0)); @@ -488,7 +488,7 @@ static void rtl838x_write_mcast_pmask(int idx, u64 portmask) static void rtl838x_vlan_profile_setup(int profile) { u32 pmask_id = UNKNOWN_MC_PMASK; - // Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for unknown MC traffic flooding + /* Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for unknown MC traffic flooding */ u32 p = 1 | pmask_id << 1 | pmask_id << 10 | pmask_id << 19; sw_w32(p, RTL838X_VLAN_PROFILE(profile)); @@ -512,16 +512,16 @@ static void rtl838x_l2_learning_setup(void) * and per vlan (bit 2) */ sw_w32(0x7, RTL838X_L2_LRN_CONSTRT_EN); - // Limit learning to maximum: 16k entries, after that just flood (bits 0-1) + /* Limit learning to maximum: 16k entries, after that just flood (bits 0-1) */ sw_w32((0x3fff << 2) | 0, RTL838X_L2_LRN_CONSTRT); - // Do not trap ARP packets to CPU_PORT + /* Do not trap ARP packets to CPU_PORT */ sw_w32(0, RTL838X_SPCL_TRAP_ARP_CTRL); } static void rtl838x_enable_learning(int port, bool enable) { - // Limit learning to maximum: 16k entries + /* Limit learning to maximum: 16k entries */ sw_w32_mask(0x3fff << 2, enable ? (0x3fff << 2) : 0, RTL838X_L2_PORT_LRN_CONSTRT + (port << 2)); @@ -599,17 +599,17 @@ static void rtl838x_port_eee_set(struct rtl838x_switch_priv *priv, int port, boo { u32 v; - // This works only for Ethernet ports, and on the RTL838X, ports from 24 are SFP + /* This works only for Ethernet ports, and on the RTL838X, ports from 24 are SFP */ if (port >= 24) return; pr_debug("In %s: setting port %d to %d\n", __func__, port, enable); v = enable ? 0x3 : 0x0; - // Set EEE state for 100 (bit 9) & 1000MBit (bit 10) + /* Set EEE state for 100 (bit 9) & 1000MBit (bit 10) */ sw_w32_mask(0x3 << 9, v << 9, priv->r->mac_force_mode_ctrl(port)); - // Set TX/RX EEE state + /* Set TX/RX EEE state */ if (enable) { sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_TX_EN); sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_RX_EN); @@ -660,7 +660,7 @@ static void rtl838x_init_eee(struct rtl838x_switch_priv *priv, bool enable) sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL); sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL); - // Enable EEE MAC support on ports + /* Enable EEE MAC support on ports */ for (i = 0; i < priv->cpu_port; i++) { if (priv->ports[i].phy) rtl838x_port_eee_set(priv, i, enable); @@ -673,7 +673,7 @@ static void rtl838x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int inde int block = index / PIE_BLOCK_SIZE; u32 block_state = sw_r32(RTL838X_ACL_BLK_LOOKUP_CTRL); - // Make sure rule-lookup is enabled in the block + /* Make sure rule-lookup is enabled in the block */ if (!(block_state & BIT(block))) sw_w32(block_state | BIT(block), RTL838X_ACL_BLK_LOOKUP_CTRL); } @@ -689,23 +689,23 @@ static void rtl838x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_fro pr_debug("%s: from %d to %d\n", __func__, index_from, index_to); mutex_lock(&priv->reg_mutex); - // Remember currently active blocks + /* Remember currently active blocks */ block_state = sw_r32(RTL838X_ACL_BLK_LOOKUP_CTRL); - // Make sure rule-lookup is disabled in the relevant blocks + /* Make sure rule-lookup is disabled in the relevant blocks */ for (block = block_from; block <= block_to; block++) { if (block_state & BIT(block)) sw_w32(block_state & (~BIT(block)), RTL838X_ACL_BLK_LOOKUP_CTRL); } - // Write from-to and execute bit into control register + /* Write from-to and execute bit into control register */ sw_w32(v, RTL838X_ACL_CLR_CTRL); - // Wait until command has completed + /* Wait until command has completed */ do { } while (sw_r32(RTL838X_ACL_CLR_CTRL) & BIT(0)); - // Re-enable rule lookup + /* Re-enable rule lookup */ for (block = block_from; block <= block_to; block++) { if (!(block_state & BIT(block))) sw_w32(block_state | BIT(block), RTL838X_ACL_BLK_LOOKUP_CTRL); @@ -969,7 +969,7 @@ static void rtl838x_read_pie_templated(u32 r[], struct pie_rule *pr, enum templa break; case TEMPLATE_FIELD_SIP2: pr->is_ipv6 = true; - // Make use of limitiations on the position of the match values + /* Make use of limitiations on the position of the match values */ ipv6_addr_set(&pr->sip6, pr->sip, r[5 - i / 2], r[4 - i / 2], r[3 - i / 2]); ipv6_addr_set(&pr->sip6_m, pr->sip_m, r[5 - i / 2], @@ -1112,7 +1112,7 @@ static void rtl838x_write_pie_fixed_fields(u32 r[], struct pie_rule *pr) r[14] |= pr->ivalid ? BIT(27) : 0; if (pr->drop) - r[17] = 0x1 << 14; // Standard drop action + r[17] = 0x1 << 14; /* Standard drop action */ else r[17] = 0; r[17] |= pr->fwd_sel ? BIT(13) : 0; @@ -1145,8 +1145,8 @@ static int rtl838x_write_pie_action(u32 r[], struct pie_rule *pr) * defines which Action Information Field (0-4) in the IACL table stores * the additional data of the action (like e.g. the port number a packet is * forwarded to) */ - // TODO: count bits in selectors to limit to a maximum number of actions - if (pr->fwd_sel) { // Forwarding action + /* TODO: count bits in selectors to limit to a maximum number of actions */ + if (pr->fwd_sel) { /* Forwarding action */ data = pr->fwd_act << 13; data |= pr->fwd_data; data |= pr->bypass_all ? BIT(12) : 0; @@ -1156,89 +1156,89 @@ static int rtl838x_write_pie_action(u32 r[], struct pie_rule *pr) fields_used++; } - if (pr->ovid_sel) { // Outer VID action + if (pr->ovid_sel) { /* Outer VID action */ data = (pr->ovid_act & 0x3) << 12; data |= pr->ovid_data; *aif-- = data; fields_used++; } - if (pr->ivid_sel) { // Inner VID action + if (pr->ivid_sel) { /* Inner VID action */ data = (pr->ivid_act & 0x3) << 12; data |= pr->ivid_data; *aif-- = data; fields_used++; } - if (pr->flt_sel) { // Filter action + if (pr->flt_sel) { /* Filter action */ *aif-- = pr->flt_data; fields_used++; } - if (pr->log_sel) { // Log action + if (pr->log_sel) { /* Log action */ if (fields_used >= 4) return -1; *aif-- = pr->log_data; fields_used++; } - if (pr->rmk_sel) { // Remark action + if (pr->rmk_sel) { /* Remark action */ if (fields_used >= 4) return -1; *aif-- = pr->rmk_data; fields_used++; } - if (pr->meter_sel) { // Meter action + if (pr->meter_sel) { /* Meter action */ if (fields_used >= 4) return -1; *aif-- = pr->meter_data; fields_used++; } - if (pr->tagst_sel) { // Egress Tag Status action + if (pr->tagst_sel) { /* Egress Tag Status action */ if (fields_used >= 4) return -1; *aif-- = pr->tagst_data; fields_used++; } - if (pr->mir_sel) { // Mirror action + if (pr->mir_sel) { /* Mirror action */ if (fields_used >= 4) return -1; *aif-- = pr->mir_data; fields_used++; } - if (pr->nopri_sel) { // Normal Priority action + if (pr->nopri_sel) { /* Normal Priority action */ if (fields_used >= 4) return -1; *aif-- = pr->nopri_data; fields_used++; } - if (pr->cpupri_sel) { // CPU Priority action + if (pr->cpupri_sel) { /* CPU Priority action */ if (fields_used >= 4) return -1; *aif-- = pr->nopri_data; fields_used++; } - if (pr->otpid_sel) { // OTPID action + if (pr->otpid_sel) { /* OTPID action */ if (fields_used >= 4) return -1; *aif-- = pr->otpid_data; fields_used++; } - if (pr->itpid_sel) { // ITPID action + if (pr->itpid_sel) { /* ITPID action */ if (fields_used >= 4) return -1; *aif-- = pr->itpid_data; fields_used++; } - if (pr->shaper_sel) { // Traffic shaper action + if (pr->shaper_sel) { /* Traffic shaper action */ if (fields_used >= 4) return -1; *aif-- = pr->shaper_data; @@ -1258,7 +1258,7 @@ static void rtl838x_read_pie_action(u32 r[], struct pie_rule *pr) if (pr->drop) pr_debug("%s: Action Drop: %d", __func__, pr->drop); - if (pr->fwd_sel){ // Forwarding action + if (pr->fwd_sel){ /* Forwarding action */ pr->fwd_act = *aif >> 13; pr->fwd_data = *aif--; pr->bypass_all = pr->fwd_data & BIT(12); @@ -1267,31 +1267,31 @@ static void rtl838x_read_pie_action(u32 r[], struct pie_rule *pr) if (pr->bypass_all || pr->bypass_ibc_sc || pr->bypass_igr_stp) pr->bypass_sel = true; } - if (pr->ovid_sel) // Outer VID action + if (pr->ovid_sel) /* Outer VID action */ pr->ovid_data = *aif--; - if (pr->ivid_sel) // Inner VID action + if (pr->ivid_sel) /* Inner VID action */ pr->ivid_data = *aif--; - if (pr->flt_sel) // Filter action + if (pr->flt_sel) /* Filter action */ pr->flt_data = *aif--; - if (pr->log_sel) // Log action + if (pr->log_sel) /* Log action */ pr->log_data = *aif--; - if (pr->rmk_sel) // Remark action + if (pr->rmk_sel) /* Remark action */ pr->rmk_data = *aif--; - if (pr->meter_sel) // Meter action + if (pr->meter_sel) /* Meter action */ pr->meter_data = *aif--; - if (pr->tagst_sel) // Egress Tag Status action + if (pr->tagst_sel) /* Egress Tag Status action */ pr->tagst_data = *aif--; - if (pr->mir_sel) // Mirror action + if (pr->mir_sel) /* Mirror action */ pr->mir_data = *aif--; - if (pr->nopri_sel) // Normal Priority action + if (pr->nopri_sel) /* Normal Priority action */ pr->nopri_data = *aif--; - if (pr->cpupri_sel) // CPU Priority action + if (pr->cpupri_sel) /* CPU Priority action */ pr->nopri_data = *aif--; - if (pr->otpid_sel) // OTPID action + if (pr->otpid_sel) /* OTPID action */ pr->otpid_data = *aif--; - if (pr->itpid_sel) // ITPID action + if (pr->itpid_sel) /* ITPID action */ pr->itpid_data = *aif--; - if (pr->shaper_sel) // Traffic shaper action + if (pr->shaper_sel) /* Traffic shaper action */ pr->shaper_data = *aif--; } @@ -1318,7 +1318,7 @@ static void rtl838x_pie_rule_dump(struct pie_rule *pr) static int rtl838x_pie_rule_read(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr) { - // Read IACL table (1) via register 0 + /* Read IACL table (1) via register 0 */ struct table_reg *q = rtl_table_get(RTL8380_TBL_0, 1); u32 r[18]; int i; @@ -1348,7 +1348,7 @@ static int rtl838x_pie_rule_read(struct rtl838x_switch_priv *priv, int idx, stru static int rtl838x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr) { - // Access IACL table (1) via register 0 + /* Access IACL table (1) via register 0 */ struct table_reg *q = rtl_table_get(RTL8380_TBL_0, 1); u32 r[18]; int i, err = 0; @@ -1373,7 +1373,7 @@ static int rtl838x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, str goto err_out; } -// rtl838x_pie_rule_dump_raw(r); +/* rtl838x_pie_rule_dump_raw(r); */ for (i = 0; i < 18; i++) sw_w32(r[i], rtl_table_data(q, i)); @@ -1431,7 +1431,7 @@ static int rtl838x_pie_verify_template(struct rtl838x_switch_priv *priv, if (ether_addr_to_u64(pr->dmac) && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0)) return -1; - // TODO: Check more + /* TODO: Check more */ i = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE); @@ -1470,7 +1470,7 @@ static int rtl838x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rul set_bit(idx, priv->pie_use_bm); pr->valid = true; - pr->tid = j; // Mapped to template number + pr->tid = j; /* Mapped to template number */ pr->tid_m = 0x3; pr->id = idx; @@ -1501,36 +1501,36 @@ static void rtl838x_pie_init(struct rtl838x_switch_priv *priv) mutex_init(&priv->pie_mutex); - // Enable ACL lookup on all ports, including CPU_PORT + /* Enable ACL lookup on all ports, including CPU_PORT */ for (i = 0; i <= priv->cpu_port; i++) sw_w32(1, RTL838X_ACL_PORT_LOOKUP_CTRL(i)); - // Power on all PIE blocks + /* Power on all PIE blocks */ for (i = 0; i < priv->n_pie_blocks; i++) sw_w32_mask(0, BIT(i), RTL838X_ACL_BLK_PWR_CTRL); - // Include IPG in metering + /* Include IPG in metering */ sw_w32(1, RTL838X_METER_GLB_CTRL); - // Delete all present rules + /* Delete all present rules */ rtl838x_pie_rule_del(priv, 0, priv->n_pie_blocks * PIE_BLOCK_SIZE - 1); - // Routing bypasses source port filter: disable write-protection, first + /* Routing bypasses source port filter: disable write-protection, first */ sw_w32_mask(0, 3, RTL838X_INT_RW_CTRL); sw_w32_mask(0, 1, RTL838X_DMY_REG27); sw_w32_mask(3, 0, RTL838X_INT_RW_CTRL); - // Enable predefined templates 0, 1 and 2 for even blocks + /* Enable predefined templates 0, 1 and 2 for even blocks */ template_selectors = 0 | (1 << 3) | (2 << 6); for (i = 0; i < 6; i += 2) sw_w32(template_selectors, RTL838X_ACL_BLK_TMPLTE_CTRL(i)); - // Enable predefined templates 0, 3 and 4 (IPv6 support) for odd blocks + /* Enable predefined templates 0, 3 and 4 (IPv6 support) for odd blocks */ template_selectors = 0 | (3 << 3) | (4 << 6); for (i = 1; i < priv->n_pie_blocks; i += 2) sw_w32(template_selectors, RTL838X_ACL_BLK_TMPLTE_CTRL(i)); - // Group each pair of physical blocks together to a logical block + /* Group each pair of physical blocks together to a logical block */ sw_w32(0b10101010101, RTL838X_ACL_BLK_GROUP_CTRL); } @@ -1538,7 +1538,7 @@ static u32 rtl838x_packet_cntr_read(int counter) { u32 v; - // Read LOG table (3) via register RTL8380_TBL_0 + /* Read LOG table (3) via register RTL8380_TBL_0 */ struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 3); pr_debug("In %s, id %d\n", __func__, counter); @@ -1546,7 +1546,7 @@ static u32 rtl838x_packet_cntr_read(int counter) pr_debug("Registers: %08x %08x\n", sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1))); - // The table has a size of 2 registers + /* The table has a size of 2 registers */ if (counter % 2) v = sw_r32(rtl_table_data(r, 0)); else @@ -1559,11 +1559,11 @@ static u32 rtl838x_packet_cntr_read(int counter) static void rtl838x_packet_cntr_clear(int counter) { - // Access LOG table (3) via register RTL8380_TBL_0 + /* Access LOG table (3) via register RTL8380_TBL_0 */ struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 3); pr_debug("In %s, id %d\n", __func__, counter); - // The table has a size of 2 registers + /* The table has a size of 2 registers */ if (counter % 2) sw_w32(0, rtl_table_data(r, 0)); else @@ -1576,13 +1576,13 @@ static void rtl838x_packet_cntr_clear(int counter) static void rtl838x_route_read(int idx, struct rtl83xx_route *rt) { - // Read ROUTING table (2) via register RTL8380_TBL_1 + /* Read ROUTING table (2) via register RTL8380_TBL_1 */ struct table_reg *r = rtl_table_get(RTL8380_TBL_1, 2); pr_debug("In %s, id %d\n", __func__, idx); rtl_table_read(r, idx); - // The table has a size of 2 registers + /* The table has a size of 2 registers */ rt->nh.gw = sw_r32(rtl_table_data(r, 0)); rt->nh.gw <<= 32; rt->nh.gw |= sw_r32(rtl_table_data(r, 1)); @@ -1592,7 +1592,7 @@ static void rtl838x_route_read(int idx, struct rtl83xx_route *rt) static void rtl838x_route_write(int idx, struct rtl83xx_route *rt) { - // Access ROUTING table (2) via register RTL8380_TBL_1 + /* Access ROUTING table (2) via register RTL8380_TBL_1 */ struct table_reg *r = rtl_table_get(RTL8380_TBL_1, 2); pr_debug("In %s, id %d, gw: %016llx\n", __func__, idx, rt->nh.gw); @@ -1605,7 +1605,7 @@ static void rtl838x_route_write(int idx, struct rtl83xx_route *rt) static int rtl838x_l3_setup(struct rtl838x_switch_priv *priv) { - // Nothing to be done + /* Nothing to be done */ return 0; } @@ -1664,7 +1664,7 @@ static void rtl838x_set_egr_filter(int port, enum egr_filter state) void rtl838x_set_distribution_algorithm(int group, int algoidx, u32 algomsk) { - algoidx &= 1; // RTL838X only supports 2 concurrent algorithms + algoidx &= 1; /* RTL838X only supports 2 concurrent algorithms */ sw_w32_mask(1 << (group % 8), algoidx << (group % 8), RTL838X_TRK_HASH_IDX_CTRL + ((group >> 3) << 2)); sw_w32(algomsk, RTL838X_TRK_HASH_CTRL + (algoidx << 2)); diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.h b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.h index 68a4675e111..a4bfc285a60 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.h +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.h @@ -518,13 +518,13 @@ typedef enum { #define RTL930X_PIE_BLK_PHASE_CTRL (0xA5A4) #define RTL931X_PIE_BLK_PHASE_CTRL (0x4184) -// PIE actions +/* PIE actions */ #define PIE_ACT_COPY_TO_PORT 2 #define PIE_ACT_REDIRECT_TO_PORT 4 #define PIE_ACT_ROUTE_UC 6 #define PIE_ACT_VID_ASSIGN 0 -// L3 actions +/* L3 actions */ #define L3_FORWARD 0 #define L3_DROP 1 #define L3_TRAP2CPU 2 @@ -533,7 +533,7 @@ typedef enum { #define L3_COPY2MASTERCPU 5 #define L3_HARDDROP 6 -// Route actions +/* Route actions */ #define ROUTE_ACT_FORWARD 0 #define ROUTE_ACT_TRAP2CPU 1 #define ROUTE_ACT_COPY2CPU 2 @@ -631,10 +631,10 @@ struct rtl838x_vlan_info { u8 profile_id; bool hash_mc_fid; bool hash_uc_fid; - u8 fid; // AKA MSTI + u8 fid; /* AKA MSTI */ - // The following fields are used only by the RTL931X - int if_id; // Interface (index in L3_EGR_INTF_IDX) + /* The following fields are used only by the RTL931X */ + int if_id; /* Interface (index in L3_EGR_INTF_IDX) */ u16 multicast_grp_mask; int l2_tunnel_list_id; }; @@ -670,9 +670,9 @@ struct rtl838x_l2_entry { u32 mc_sip; u16 mc_mac_index; u16 nh_route_id; - bool nh_vlan_target; // Only RTL83xx: VLAN used for next hop + bool nh_vlan_target; /* Only RTL83xx: VLAN used for next hop */ - // The following is only valid on RTL931x + /* The following is only valid on RTL931x */ bool is_open_flow; bool is_pe_forward; bool is_local_forward; @@ -709,35 +709,35 @@ enum egr_filter { * to SoC family (e.g. because of different port ranges) */ struct pie_rule { int id; - enum pie_phase phase; // Phase in which this template is applied - int packet_cntr; // ID of a packet counter assigned to this rule - int octet_cntr; // ID of a byte counter assigned to this rule + enum pie_phase phase; /* Phase in which this template is applied */ + int packet_cntr; /* ID of a packet counter assigned to this rule */ + int octet_cntr; /* ID of a byte counter assigned to this rule */ u32 last_packet_cnt; u64 last_octet_cnt; - // The following are requirements for the pie template + /* The following are requirements for the pie template */ bool is_egress; - bool is_ipv6; // This is a rule with IPv6 fields + bool is_ipv6; /* This is a rule with IPv6 fields */ - // Fixed fields that are always matched against on RTL8380 + /* Fixed fields that are always matched against on RTL8380 */ u8 spmmask_fix; - u8 spn; // Source port number - bool stacking_port; // Source port is stacking port - bool mgnt_vlan; // Packet arrived on management VLAN - bool dmac_hit_sw; // The packet's destination MAC matches one of the device's - bool content_too_deep; // The content of the packet cannot be parsed: too many layers - bool not_first_frag; // Not the first IP fragment - u8 frame_type_l4; // 0: UDP, 1: TCP, 2: ICMP/ICMPv6, 3: IGMP - u8 frame_type; // 0: ARP, 1: L2 only, 2: IPv4, 3: IPv6 - bool otag_fmt; // 0: outer tag packet, 1: outer priority tag or untagged - bool itag_fmt; // 0: inner tag packet, 1: inner priority tag or untagged - bool otag_exist; // packet with outer tag - bool itag_exist; // packet with inner tag - bool frame_type_l2; // 0: Ethernet, 1: LLC_SNAP, 2: LLC_Other, 3: Reserved - bool igr_normal_port; // Ingress port is not cpu or stacking port - u8 tid; // The template ID defining the what the templated fields mean + u8 spn; /* Source port number */ + bool stacking_port; /* Source port is stacking port */ + bool mgnt_vlan; /* Packet arrived on management VLAN */ + bool dmac_hit_sw; /* The packet's destination MAC matches one of the device's */ + bool content_too_deep; /* The content of the packet cannot be parsed: too many layers */ + bool not_first_frag; /* Not the first IP fragment */ + u8 frame_type_l4; /* 0: UDP, 1: TCP, 2: ICMP/ICMPv6, 3: IGMP */ + u8 frame_type; /* 0: ARP, 1: L2 only, 2: IPv4, 3: IPv6 */ + bool otag_fmt; /* 0: outer tag packet, 1: outer priority tag or untagged */ + bool itag_fmt; /* 0: inner tag packet, 1: inner priority tag or untagged */ + bool otag_exist; /* packet with outer tag */ + bool itag_exist; /* packet with inner tag */ + bool frame_type_l2; /* 0: Ethernet, 1: LLC_SNAP, 2: LLC_Other, 3: Reserved */ + bool igr_normal_port; /* Ingress port is not cpu or stacking port */ + u8 tid; /* The template ID defining the what the templated fields mean */ - // Masks for the fields that are always matched against on RTL8380 + /* Masks for the fields that are always matched against on RTL8380 */ u8 spmmask_fix_m; u8 spn_m; bool stacking_port_m; @@ -755,52 +755,52 @@ struct pie_rule { bool igr_normal_port_m; u8 tid_m; - // Logical operations between rules, special rules for rule numbers apply + /* Logical operations between rules, special rules for rule numbers apply */ bool valid; - bool cond_not; // Matches when conditions not match - bool cond_and1; // And this rule 2n with the next rule 2n+1 in same block - bool cond_and2; // And this rule m in block 2n with rule m in block 2n+1 + bool cond_not; /* Matches when conditions not match */ + bool cond_and1; /* And this rule 2n with the next rule 2n+1 in same block */ + bool cond_and2; /* And this rule m in block 2n with rule m in block 2n+1 */ bool ivalid; - // Actions to be performed - bool drop; // Drop the packet - bool fwd_sel; // Forward packet: to port, portmask, dest route, next rule, drop - bool ovid_sel; // So something to outer vlan-id: shift, re-assign - bool ivid_sel; // Do something to inner vlan-id: shift, re-assign - bool flt_sel; // Filter the packet when sending to certain ports - bool log_sel; // Log the packet in one of the LOG-table counters - bool rmk_sel; // Re-mark the packet, i.e. change the priority-tag - bool meter_sel; // Meter the packet, i.e. limit rate of this type of packet - bool tagst_sel; // Change the ergress tag - bool mir_sel; // Mirror the packet to a Link Aggregation Group - bool nopri_sel; // Change the normal priority - bool cpupri_sel; // Change the CPU priority - bool otpid_sel; // Change Outer Tag Protocol Identifier (802.1q) - bool itpid_sel; // Change Inner Tag Protocol Identifier (802.1q) - bool shaper_sel; // Apply traffic shaper - bool mpls_sel; // MPLS actions - bool bypass_sel; // Bypass actions - bool fwd_sa_lrn; // Learn the source address when forwarding - bool fwd_mod_to_cpu; // Forward the modified VLAN tag format to CPU-port + /* Actions to be performed */ + bool drop; /* Drop the packet */ + bool fwd_sel; /* Forward packet: to port, portmask, dest route, next rule, drop */ + bool ovid_sel; /* So something to outer vlan-id: shift, re-assign */ + bool ivid_sel; /* Do something to inner vlan-id: shift, re-assign */ + bool flt_sel; /* Filter the packet when sending to certain ports */ + bool log_sel; /* Log the packet in one of the LOG-table counters */ + bool rmk_sel; /* Re-mark the packet, i.e. change the priority-tag */ + bool meter_sel; /* Meter the packet, i.e. limit rate of this type of packet */ + bool tagst_sel; /* Change the ergress tag */ + bool mir_sel; /* Mirror the packet to a Link Aggregation Group */ + bool nopri_sel; /* Change the normal priority */ + bool cpupri_sel; /* Change the CPU priority */ + bool otpid_sel; /* Change Outer Tag Protocol Identifier (802.1q) */ + bool itpid_sel; /* Change Inner Tag Protocol Identifier (802.1q) */ + bool shaper_sel; /* Apply traffic shaper */ + bool mpls_sel; /* MPLS actions */ + bool bypass_sel; /* Bypass actions */ + bool fwd_sa_lrn; /* Learn the source address when forwarding */ + bool fwd_mod_to_cpu; /* Forward the modified VLAN tag format to CPU-port */ - // Fields used in predefined templates 0-2 on RTL8380 / 90 / 9300 - u64 spm; // Source Port Matrix - u16 otag; // Outer VLAN-ID - u8 smac[ETH_ALEN]; // Source MAC address - u8 dmac[ETH_ALEN]; // Destination MAC address - u16 ethertype; // Ethernet frame type field in ethernet header - u16 itag; // Inner VLAN-ID + /* Fields used in predefined templates 0-2 on RTL8380 / 90 / 9300 */ + u64 spm; /* Source Port Matrix */ + u16 otag; /* Outer VLAN-ID */ + u8 smac[ETH_ALEN]; /* Source MAC address */ + u8 dmac[ETH_ALEN]; /* Destination MAC address */ + u16 ethertype; /* Ethernet frame type field in ethernet header */ + u16 itag; /* Inner VLAN-ID */ u16 field_range_check; - u32 sip; // Source IP - struct in6_addr sip6; // IPv6 Source IP - u32 dip; // Destination IP - struct in6_addr dip6; // IPv6 Destination IP - u16 tos_proto; // IPv4: TOS + Protocol fields, IPv6: Traffic class + next header - u16 sport; // TCP/UDP source port - u16 dport; // TCP/UDP destination port + u32 sip; /* Source IP */ + struct in6_addr sip6; /* IPv6 Source IP */ + u32 dip; /* Destination IP */ + struct in6_addr dip6; /* IPv6 Destination IP */ + u16 tos_proto; /* IPv4: TOS + Protocol fields, IPv6: Traffic class + next header */ + u16 sport; /* TCP/UDP source port */ + u16 dport; /* TCP/UDP destination port */ u16 icmp_igmp; u16 tcp_info; - u16 dsap_ssap; // Destination / Source Service Access Point bytes (802.3) + u16 dsap_ssap; /* Destination / Source Service Access Point bytes (802.3) */ u64 spm_m; u16 otag_m; @@ -810,9 +810,9 @@ struct pie_rule { u16 itag_m; u16 field_range_check_m; u32 sip_m; - struct in6_addr sip6_m; // IPv6 Source IP mask + struct in6_addr sip6_m; /* IPv6 Source IP mask */ u32 dip_m; - struct in6_addr dip6_m; // IPv6 Destination IP mask + struct in6_addr dip6_m; /* IPv6 Destination IP mask */ u16 tos_proto_m; u16 sport_m; u16 dport_m; @@ -820,25 +820,25 @@ struct pie_rule { u16 tcp_info_m; u16 dsap_ssap_m; - // Data associated with actions - u8 fwd_act; // Type of forwarding action - // 0: permit, 1: drop, 2: copy to port id, 4: copy to portmask - // 4: redirect to portid, 5: redirect to portmask - // 6: route, 7: vlan leaky (only 8380) - u16 fwd_data; // Additional data for forwarding action, e.g. destination port + /* Data associated with actions */ + u8 fwd_act; /* Type of forwarding action */ + /* 0: permit, 1: drop, 2: copy to port id, 4: copy to portmask */ + /* 4: redirect to portid, 5: redirect to portmask */ + /* 6: route, 7: vlan leaky (only 8380) */ + u16 fwd_data; /* Additional data for forwarding action, e.g. destination port */ u8 ovid_act; - u16 ovid_data; // Outer VLAN ID + u16 ovid_data; /* Outer VLAN ID */ u8 ivid_act; - u16 ivid_data; // Inner VLAN ID - u16 flt_data; // Filtering data - u16 log_data; // ID of packet or octet counter in LOG table, on RTL93xx - // unnecessary since PIE-Rule-ID == LOG-counter-ID + u16 ivid_data; /* Inner VLAN ID */ + u16 flt_data; /* Filtering data */ + u16 log_data; /* ID of packet or octet counter in LOG table, on RTL93xx */ + /* unnecessary since PIE-Rule-ID == LOG-counter-ID */ bool log_octets; - u8 mpls_act; // MPLS action type - u16 mpls_lib_idx; // MPLS action data + u8 mpls_act; /* MPLS action type */ + u16 mpls_lib_idx; /* MPLS action data */ - u16 rmk_data; // Data for remarking - u16 meter_data; // ID of meter for bandwidth control + u16 rmk_data; /* Data for remarking */ + u16 meter_data; /* ID of meter for bandwidth control */ u16 tagst_data; u16 mir_data; u16 nopri_data; @@ -847,10 +847,10 @@ struct pie_rule { u16 itpid_data; u16 shaper_data; - // Bypass actions, ignored on RTL8380 - bool bypass_all; // Not clear - bool bypass_igr_stp; // Bypass Ingress STP state - bool bypass_ibc_sc; // Bypass Ingress Bandwidth Control and Storm Control + /* Bypass actions, ignored on RTL8380 */ + bool bypass_all; /* Not clear */ + bool bypass_igr_stp; /* Bypass Ingress STP state */ + bool bypass_ibc_sc; /* Bypass Ingress Bandwidth Control and Storm Control */ }; struct rtl838x_l3_intf { @@ -874,30 +874,30 @@ struct rtl838x_l3_intf { * Mask fields state whether the corresponding data fields matter for matching */ struct rtl93xx_rt_mac { - bool valid; // Valid or not - bool p_type; // Individual (0) or trunk (1) port - bool p_mask; // Whether the port type is used + bool valid; /* Valid or not */ + bool p_type; /* Individual (0) or trunk (1) port */ + bool p_mask; /* Whether the port type is used */ u8 p_id; - u8 p_id_mask; // Mask for the port - u8 action; // Routing action performed: 0: FORWARD, 1: DROP, 2: TRAP2CPU - // 3: COPY2CPU, 4: TRAP2MASTERCPU, 5: COPY2MASTERCPU, 6: HARDDROP + u8 p_id_mask; /* Mask for the port */ + u8 action; /* Routing action performed: 0: FORWARD, 1: DROP, 2: TRAP2CPU */ + /* 3: COPY2CPU, 4: TRAP2MASTERCPU, 5: COPY2MASTERCPU, 6: HARDDROP */ u16 vid; u16 vid_mask; - u64 mac; // MAC address used as source MAC in the routed packet + u64 mac; /* MAC address used as source MAC in the routed packet */ u64 mac_mask; }; struct rtl83xx_nexthop { - u16 id; // ID: L3_NEXT_HOP table-index or route-index set in L2_NEXT_HOP + u16 id; /* ID: L3_NEXT_HOP table-index or route-index set in L2_NEXT_HOP */ u32 dev_id; u16 port; - u16 vid; // VLAN-ID for L2 table entry (saved from L2-UC entry) - u16 rvid; // Relay VID/FID for the L2 table entry - u64 mac; // The MAC address of the entry in the L2_NEXT_HOP table + u16 vid; /* VLAN-ID for L2 table entry (saved from L2-UC entry) */ + u16 rvid; /* Relay VID/FID for the L2 table entry */ + u64 mac; /* The MAC address of the entry in the L2_NEXT_HOP table */ u16 mac_id; - u16 l2_id; // Index of this next hop forwarding entry in L2 FIB table - u64 gw; // The gateway MAC address packets are forwarded to - int if_id; // Interface (into L3_EGR_INTF_IDX) + u16 l2_id; /* Index of this next hop forwarding entry in L2 FIB table */ + u64 gw; /* The gateway MAC address packets are forwarded to */ + int if_id; /* Interface (into L3_EGR_INTF_IDX) */ }; struct rtl838x_switch_priv; @@ -924,14 +924,14 @@ struct rtl93xx_route_attr { }; struct rtl83xx_route { - u32 gw_ip; // IP of the route's gateway - u32 dst_ip; // IP of the destination net + u32 gw_ip; /* IP of the route's gateway */ + u32 dst_ip; /* IP of the destination net */ struct in6_addr dst_ip6; - int prefix_len; // Network prefix len of the destination net + int prefix_len; /* Network prefix len of the destination net */ bool is_host_route; - int id; // ID number of this route + int id; /* ID number of this route */ struct rhlist_head linkage; - u16 switch_mac_id; // Index into switch's own MACs, RTL839X only + u16 switch_mac_id; /* Index into switch's own MACs, RTL839X only */ struct rtl83xx_nexthop nh; struct pie_rule pr; struct rtl93xx_route_attr attr; @@ -1043,8 +1043,8 @@ struct rtl838x_switch_priv { u16 family_id; char version; struct rtl838x_port ports[57]; - struct mutex reg_mutex; // Mutex for individual register manipulations - struct mutex pie_mutex; // Mutex for Packet Inspection Engine + struct mutex reg_mutex; /* Mutex for individual register manipulations */ + struct mutex pie_mutex; /* Mutex for Packet Inspection Engine */ int link_state_irq; int mirror_group_ports[4]; struct mii_bus *mii_bus; @@ -1063,7 +1063,7 @@ struct rtl838x_switch_priv { u32 lag_primary[MAX_LAGS]; u32 is_lagmember[57]; u64 lagmembers; - struct notifier_block nb; // TODO: change to different name + struct notifier_block nb; /* TODO: change to different name */ struct notifier_block ne_nb; struct notifier_block fib_nb; bool eee_enabled; diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl839x.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl839x.c index 6fac8bd6741..01461edc4b6 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl839x.c +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl839x.c @@ -25,18 +25,18 @@ extern struct rtl83xx_soc_info soc_info; /* Definition of the RTL839X-specific template field IDs as used in the PIE */ enum template_field_id { TEMPLATE_FIELD_SPMMASK = 0, - TEMPLATE_FIELD_SPM0 = 1, // Source portmask ports 0-15 - TEMPLATE_FIELD_SPM1 = 2, // Source portmask ports 16-31 - TEMPLATE_FIELD_SPM2 = 3, // Source portmask ports 32-47 - TEMPLATE_FIELD_SPM3 = 4, // Source portmask ports 48-56 - TEMPLATE_FIELD_DMAC0 = 5, // Destination MAC [15:0] - TEMPLATE_FIELD_DMAC1 = 6, // Destination MAC [31:16] - TEMPLATE_FIELD_DMAC2 = 7, // Destination MAC [47:32] - TEMPLATE_FIELD_SMAC0 = 8, // Source MAC [15:0] - TEMPLATE_FIELD_SMAC1 = 9, // Source MAC [31:16] - TEMPLATE_FIELD_SMAC2 = 10, // Source MAC [47:32] - TEMPLATE_FIELD_ETHERTYPE = 11, // Ethernet frame type field - // Field-ID 12 is not used + TEMPLATE_FIELD_SPM0 = 1, /* Source portmask ports 0-15 */ + TEMPLATE_FIELD_SPM1 = 2, /* Source portmask ports 16-31 */ + TEMPLATE_FIELD_SPM2 = 3, /* Source portmask ports 32-47 */ + TEMPLATE_FIELD_SPM3 = 4, /* Source portmask ports 48-56 */ + TEMPLATE_FIELD_DMAC0 = 5, /* Destination MAC [15:0] */ + TEMPLATE_FIELD_DMAC1 = 6, /* Destination MAC [31:16] */ + TEMPLATE_FIELD_DMAC2 = 7, /* Destination MAC [47:32] */ + TEMPLATE_FIELD_SMAC0 = 8, /* Source MAC [15:0] */ + TEMPLATE_FIELD_SMAC1 = 9, /* Source MAC [31:16] */ + TEMPLATE_FIELD_SMAC2 = 10, /* Source MAC [47:32] */ + TEMPLATE_FIELD_ETHERTYPE = 11, /* Ethernet frame type field */ + /* Field-ID 12 is not used */ TEMPLATE_FIELD_OTAG = 13, TEMPLATE_FIELD_ITAG = 14, TEMPLATE_FIELD_SIP0 = 15, @@ -88,7 +88,7 @@ enum template_field_id { TEMPLATE_FIELD_DIP7 = 61, }; -// Number of fixed templates predefined in the SoC +/* Number of fixed templates predefined in the SoC */ #define N_FIXED_TEMPLATES 5 static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] = { @@ -163,7 +163,7 @@ static inline int rtl839x_tbl_access_data_0(int i) static void rtl839x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info) { u32 u, v, w; - // Read VLAN table (0) via register 0 + /* Read VLAN table (0) via register 0 */ struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 0); rtl_table_read(r, vlan); @@ -179,7 +179,7 @@ static void rtl839x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info) info->hash_uc_fid = !!(w & BIT(3)); info->fid = (v >> 3) & 0xff; - // Read UNTAG table (0) via table register 1 + /* Read UNTAG table (0) via table register 1 */ r = rtl_table_get(RTL8390_TBL_1, 0); rtl_table_read(r, vlan); u = sw_r32(rtl_table_data(r, 0)); @@ -193,7 +193,7 @@ static void rtl839x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info) static void rtl839x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info) { u32 u, v, w; - // Access VLAN table (0) via register 0 + /* Access VLAN table (0) via register 0 */ struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 0); u = info->tagged_ports >> 21; @@ -216,7 +216,7 @@ static void rtl839x_vlan_set_untagged(u32 vlan, u64 portmask) { u32 u, v; - // Access UNTAG table (0) via table register 1 + /* Access UNTAG table (0) via table register 1 */ struct table_reg *r = rtl_table_get(RTL8390_TBL_1, 0); u = portmask >> 21; @@ -349,7 +349,7 @@ static void rtl839x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e) e->mc_portmask_index = (r[2] >> 6) & 0xfff; e->vid = e->rvid; } - } else { // IPv4 and IPv6 multicast + } else { /* IPv4 and IPv6 multicast */ e->vid = e->rvid = (r[0] << 20) & 0xfff; e->mc_gip = r[1]; e->mc_portmask_index = (r[2] >> 6) & 0xfff; @@ -362,7 +362,7 @@ static void rtl839x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e) e->valid = true; e->type = IP6_MULTICAST; } - // pr_info("%s: vid %d, rvid: %d\n", __func__, e->vid, e->rvid); + /* pr_info("%s: vid %d, rvid: %d\n", __func__, e->vid, e->rvid); */ } /* Fills the 3 SoC table registers r[] with the information in the rtl838x_l2_entry */ @@ -385,7 +385,7 @@ static void rtl839x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e) r[1] |= ((u32)e->mac[4]) << 12; r[1] |= ((u32)e->mac[5]) << 4; - if (!(e->mac[0] & 1)) { // Not multicast + if (!(e->mac[0] & 1)) { /* Not multicast */ r[2] |= e->is_static ? BIT(18) : 0; r[0] |= ((u32)e->rvid) << 20; r[2] |= e->port << 24; @@ -401,11 +401,11 @@ static void rtl839x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e) r[2] |= e->vid << 4; } pr_debug("Write L2 NH: %08x %08x %08x\n", r[0], r[1], r[2]); - } else { // L2 Multicast + } else { /* L2 Multicast */ r[0] |= ((u32)e->rvid) << 20; r[2] |= ((u32)e->mc_portmask_index) << 6; } - } else { // IPv4 or IPv6 MC entry + } else { /* IPv4 or IPv6 MC entry */ r[0] = ((u32)e->rvid) << 20; r[1] = e->mc_gip; r[2] |= ((u32)e->mc_portmask_index) << 6; @@ -420,7 +420,7 @@ static u64 rtl839x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2 { u32 r[3]; struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 0); - u32 idx = (0 << 14) | (hash << 2) | pos; // Search SRAM, with hash and at pos in bucket + u32 idx = (0 << 14) | (hash << 2) | pos; /* Search SRAM, with hash and at pos in bucket */ int i; rtl_table_read(q, idx); @@ -442,7 +442,7 @@ static void rtl839x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_ struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 0); int i; - u32 idx = (0 << 14) | (hash << 2) | pos; // Access SRAM, with hash and at pos in bucket + u32 idx = (0 << 14) | (hash << 2) | pos; /* Access SRAM, with hash and at pos in bucket */ rtl839x_fill_l2_row(r, e); @@ -456,7 +456,7 @@ static void rtl839x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_ static u64 rtl839x_read_cam(int idx, struct rtl838x_l2_entry *e) { u32 r[3]; - struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 1); // Access L2 Table 1 + struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 1); /* Access L2 Table 1 */ int i; rtl_table_read(q, idx); @@ -471,14 +471,14 @@ static u64 rtl839x_read_cam(int idx, struct rtl838x_l2_entry *e) pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]); - // Return MAC with concatenated VID ac concatenated ID + /* Return MAC with concatenated VID ac concatenated ID */ return rtl839x_l2_hash_seed(ether_addr_to_u64(&e->mac[0]), e->rvid); } static void rtl839x_write_cam(int idx, struct rtl838x_l2_entry *e) { u32 r[3]; - struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 1); // Access L2 Table 1 + struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 1); /* Access L2 Table 1 */ int i; rtl839x_fill_l2_row(r, e); @@ -493,14 +493,14 @@ static void rtl839x_write_cam(int idx, struct rtl838x_l2_entry *e) static u64 rtl839x_read_mcast_pmask(int idx) { u64 portmask; - // Read MC_PMSK (2) via register RTL8390_TBL_L2 + /* Read MC_PMSK (2) via register RTL8390_TBL_L2 */ struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 2); rtl_table_read(q, idx); portmask = sw_r32(rtl_table_data(q, 0)); portmask <<= 32; portmask |= sw_r32(rtl_table_data(q, 1)); - portmask >>= 11; // LSB is bit 11 in data registers + portmask >>= 11; /* LSB is bit 11 in data registers */ rtl_table_release(q); return portmask; @@ -508,10 +508,10 @@ static u64 rtl839x_read_mcast_pmask(int idx) static void rtl839x_write_mcast_pmask(int idx, u64 portmask) { - // Access MC_PMSK (2) via register RTL8380_TBL_L2 + /* Access MC_PMSK (2) via register RTL8380_TBL_L2 */ struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 2); - portmask <<= 11; // LSB is bit 11 in data registers + portmask <<= 11; /* LSB is bit 11 in data registers */ sw_w32((u32)(portmask >> 32), rtl_table_data(q, 0)); sw_w32((u32)((portmask & 0xfffff800)), rtl_table_data(q, 1)); rtl_table_write(q, idx); @@ -523,8 +523,8 @@ static void rtl839x_vlan_profile_setup(int profile) u32 p[2]; u32 pmask_id = UNKNOWN_MC_PMASK; - p[0] = pmask_id; // Use portmaks 0xfff for unknown IPv6 MC flooding - // Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for IP/L2-MC traffic flooding + p[0] = pmask_id; /* Use portmaks 0xfff for unknown IPv6 MC flooding */ + /* Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for IP/L2-MC traffic flooding */ p[1] = 1 | pmask_id << 1 | pmask_id << 13; sw_w32(p[0], RTL839X_VLAN_PROFILE(profile)); @@ -560,16 +560,16 @@ static void rtl839x_l2_learning_setup(void) * also for multicast flooding */ sw_w32(UNKNOWN_MC_PMASK << 12 | UNKNOWN_MC_PMASK, RTL839X_L2_FLD_PMSK); - // Limit learning to maximum: 32k entries, after that just flood (bits 0-1) + /* Limit learning to maximum: 32k entries, after that just flood (bits 0-1) */ sw_w32((0x7fff << 2) | 0, RTL839X_L2_LRN_CONSTRT); - // Do not trap ARP packets to CPU_PORT + /* Do not trap ARP packets to CPU_PORT */ sw_w32(0, RTL839X_SPCL_TRAP_ARP_CTRL); } static void rtl839x_enable_learning(int port, bool enable) { - // Limit learning to maximum: 32k entries + /* Limit learning to maximum: 32k entries */ sw_w32_mask(0x7fff << 2, enable ? (0x7fff << 2) : 0, RTL839X_L2_PORT_LRN_CONSTRT + (port << 2)); @@ -620,7 +620,7 @@ irqreturn_t rtl839x_switch_irq(int irq, void *dev_id) return IRQ_HANDLED; } -// TODO: unused +/* TODO: unused */ int rtl8390_sds_power(int mac, int val) { u32 offset = (mac == 48) ? 0x0 : 0x100; @@ -633,7 +633,7 @@ int rtl8390_sds_power(int mac, int val) return -1; } - // Set bit 1003. 1000 starts at 7c + /* Set bit 1003. 1000 starts at 7c */ sw_w32_mask(BIT(11), mode << 11, RTL839X_SDS12_13_PWR0 + offset); return 0; @@ -660,7 +660,7 @@ int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val) if (port > 63 || page > 4095 || reg > 31) return -ENOTSUPP; - // Take bug on RTL839x Rev <= C into account + /* Take bug on RTL839x Rev <= C into account */ if (port >= RTL839X_CPU_PORT) return -EIO; @@ -696,13 +696,13 @@ int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val) if (port > 63 || page > 4095 || reg > 31) return -ENOTSUPP; - // Take bug on RTL839x Rev <= C into account + /* Take bug on RTL839x Rev <= C into account */ if (port >= RTL839X_CPU_PORT) return -EIO; mutex_lock(&smi_lock); - // Set PHY to access + /* Set PHY to access */ rtl839x_set_port_reg_le(BIT_ULL(port), RTL839X_PHYREG_PORT_CTRL); sw_w32_mask(0xffff0000, val << 16, RTL839X_PHYREG_DATA_CTRL); @@ -734,26 +734,26 @@ int rtl839x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val) int err = 0; u32 v; - // Take bug on RTL839x Rev <= C into account + /* Take bug on RTL839x Rev <= C into account */ if (port >= RTL839X_CPU_PORT) return -EIO; mutex_lock(&smi_lock); - // Set PHY to access + /* Set PHY to access */ sw_w32_mask(0xffff << 16, port << 16, RTL839X_PHYREG_DATA_CTRL); - // Set MMD device number and register to write to + /* Set MMD device number and register to write to */ sw_w32(devnum << 16 | (regnum & 0xffff), RTL839X_PHYREG_MMD_CTRL); - v = BIT(2) | BIT(0); // MMD-access | EXEC + v = BIT(2) | BIT(0); /* MMD-access | EXEC */ sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL); err = rtl839x_smi_wait_op(100000); if (err) goto errout; - // There is no error-checking via BIT 1 of v, as it does not seem to be set correctly + /* There is no error-checking via BIT 1 of v, as it does not seem to be set correctly */ *val = (sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff); pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, *val, err); @@ -769,22 +769,22 @@ int rtl839x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val) int err = 0; u32 v; - // Take bug on RTL839x Rev <= C into account + /* Take bug on RTL839x Rev <= C into account */ if (port >= RTL839X_CPU_PORT) return -EIO; mutex_lock(&smi_lock); - // Set PHY to access + /* Set PHY to access */ rtl839x_set_port_reg_le(BIT_ULL(port), RTL839X_PHYREG_PORT_CTRL); - // Set data to write + /* Set data to write */ sw_w32_mask(0xffff << 16, val << 16, RTL839X_PHYREG_DATA_CTRL); - // Set MMD device number and register to write to + /* Set MMD device number and register to write to */ sw_w32(devnum << 16 | (regnum & 0xffff), RTL839X_PHYREG_MMD_CTRL); - v = BIT(3) | BIT(2) | BIT(0); // WRITE | MMD-access | EXEC + v = BIT(3) | BIT(2) | BIT(0); /* WRITE | MMD-access | EXEC */ sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL); err = rtl839x_smi_wait_op(100000); @@ -859,7 +859,7 @@ void rtl839x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enabl { u32 v; - // This works only for Ethernet ports, and on the RTL839X, ports above 47 are SFP + /* This works only for Ethernet ports, and on the RTL839X, ports above 47 are SFP */ if (port >= 48) return; @@ -867,10 +867,10 @@ void rtl839x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enabl pr_debug("In %s: setting port %d to %d\n", __func__, port, enable); v = enable ? 0xf : 0x0; - // Set EEE for 100, 500, 1000MBit and 10GBit + /* Set EEE for 100, 500, 1000MBit and 10GBit */ sw_w32_mask(0xf << 8, v << 8, rtl839x_mac_force_mode_ctrl(port)); - // Set TX/RX EEE state + /* Set TX/RX EEE state */ v = enable ? 0x3 : 0x0; sw_w32(v, RTL839X_EEE_CTRL(port)); @@ -912,14 +912,14 @@ static void rtl839x_init_eee(struct rtl838x_switch_priv *priv, bool enable) pr_info("Setting up EEE, state: %d\n", enable); - // Set wake timer for TX and pause timer both to 0x21 + /* Set wake timer for TX and pause timer both to 0x21 */ sw_w32_mask(0xff << 20| 0xff, 0x21 << 20| 0x21, RTL839X_EEE_TX_TIMER_GELITE_CTRL); - // Set pause wake timer for GIGA-EEE to 0x11 + /* Set pause wake timer for GIGA-EEE to 0x11 */ sw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_GIGA_CTRL); - // Set pause wake timer for 10GBit ports to 0x11 + /* Set pause wake timer for 10GBit ports to 0x11 */ sw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_10G_CTRL); - // Setup EEE on all ports + /* Setup EEE on all ports */ for (i = 0; i < priv->cpu_port; i++) { if (priv->ports[i].phy) rtl839x_port_eee_set(priv, i, enable); @@ -942,10 +942,10 @@ static int rtl839x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from pr_debug("%s: from %d to %d\n", __func__, index_from, index_to); mutex_lock(&priv->reg_mutex); - // Write from-to and execute bit into control register + /* Write from-to and execute bit into control register */ sw_w32(v, RTL839X_ACL_CLR_CTRL); - // Wait until command has completed + /* Wait until command has completed */ do { } while (sw_r32(RTL839X_ACL_CLR_CTRL) & BIT(0)); @@ -1111,7 +1111,7 @@ static void rtl839x_write_pie_templated(u32 r[], struct pie_rule *pr, enum templ pr_info("%s: unknown field %d\n", __func__, field_type); } - // On the RTL8390, the mask fields are not word aligned! + /* On the RTL8390, the mask fields are not word aligned! */ if (!(i % 2)) { r[5 - i / 2] = data; r[12 - i / 2] |= ((u32)data_m << 8); @@ -1213,7 +1213,7 @@ void rtl839x_read_pie_templated(u32 r[], struct pie_rule *pr, enum template_fiel break; case TEMPLATE_FIELD_SIP2: pr->is_ipv6 = true; - // Make use of limitiations on the position of the match values + /* Make use of limitiations on the position of the match values */ ipv6_addr_set(&pr->sip6, pr->sip, r[5 - i / 2], r[4 - i / 2], r[3 - i / 2]); ipv6_addr_set(&pr->sip6_m, pr->sip_m, r[5 - i / 2], @@ -1344,7 +1344,7 @@ static void rtl839x_write_pie_fixed_fields(u32 r[], struct pie_rule *pr) static void rtl839x_write_pie_action(u32 r[], struct pie_rule *pr) { if (pr->drop) { - r[13] |= 0x9; // Set ACT_MASK_FWD & FWD_ACT = DROP + r[13] |= 0x9; /* Set ACT_MASK_FWD & FWD_ACT = DROP */ r[13] |= BIT(3); } else { r[13] |= pr->fwd_sel ? BIT(3) : 0; @@ -1380,7 +1380,7 @@ static void rtl839x_write_pie_action(u32 r[], struct pie_rule *pr) static void rtl839x_read_pie_action(u32 r[], struct pie_rule *pr) { - if (r[13] & BIT(3)) { // ACT_MASK_FWD set, is it a drop? + if (r[13] & BIT(3)) { /* ACT_MASK_FWD set, is it a drop? */ if ((r[14] & 0x7) == 1) { pr->drop = true; } else { @@ -1398,7 +1398,7 @@ static void rtl839x_read_pie_action(u32 r[], struct pie_rule *pr) pr->mir_sel = r[13] & BIT(5); pr->log_sel = r[13] & BIT(4); - // TODO: Read in data fields + /* TODO: Read in data fields */ pr->bypass_all = r[16] & BIT(9); pr->bypass_igr_stp = r[16] & BIT(8); @@ -1432,7 +1432,7 @@ void rtl839x_pie_rule_dump(struct pie_rule *pr) static int rtl839x_pie_rule_read(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr) { - // Read IACL table (2) via register 0 + /* Read IACL table (2) via register 0 */ struct table_reg *q = rtl_table_get(RTL8380_TBL_0, 2); u32 r[17]; int i; @@ -1462,7 +1462,7 @@ static int rtl839x_pie_rule_read(struct rtl838x_switch_priv *priv, int idx, stru static int rtl839x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr) { - // Access IACL table (2) via register 0 + /* Access IACL table (2) via register 0 */ struct table_reg *q = rtl_table_get(RTL8390_TBL_0, 2); u32 r[17]; int i; @@ -1486,7 +1486,7 @@ static int rtl839x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, str rtl839x_write_pie_action(r, pr); -// rtl839x_pie_rule_dump_raw(r); +/* rtl839x_pie_rule_dump_raw(r); */ for (i = 0; i < 17; i++) sw_w32(r[i], rtl_table_data(q, i)); @@ -1543,7 +1543,7 @@ static int rtl839x_pie_verify_template(struct rtl838x_switch_priv *priv, if (ether_addr_to_u64(pr->dmac) && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0)) return -1; - // TODO: Check more + /* TODO: Check more */ i = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE); @@ -1585,7 +1585,7 @@ static int rtl839x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rul set_bit(idx, priv->pie_use_bm); pr->valid = true; - pr->tid = j; // Mapped to template number + pr->tid = j; /* Mapped to template number */ pr->tid_m = 0x3; pr->id = idx; @@ -1612,45 +1612,45 @@ static void rtl839x_pie_init(struct rtl838x_switch_priv *priv) mutex_init(&priv->pie_mutex); - // Power on all PIE blocks + /* Power on all PIE blocks */ for (i = 0; i < priv->n_pie_blocks; i++) sw_w32_mask(0, BIT(i), RTL839X_PS_ACL_PWR_CTRL); - // Set ingress and egress ACL blocks to 50/50: first Egress block is 9 - sw_w32_mask(0x1f, 9, RTL839X_ACL_CTRL); // Writes 9 to cutline field + /* Set ingress and egress ACL blocks to 50/50: first Egress block is 9 */ + sw_w32_mask(0x1f, 9, RTL839X_ACL_CTRL); /* Writes 9 to cutline field */ - // Include IPG in metering + /* Include IPG in metering */ sw_w32(1, RTL839X_METER_GLB_CTRL); - // Delete all present rules + /* Delete all present rules */ rtl839x_pie_rule_del(priv, 0, priv->n_pie_blocks * PIE_BLOCK_SIZE - 1); - // Enable predefined templates 0, 1 for blocks 0-2 + /* Enable predefined templates 0, 1 for blocks 0-2 */ template_selectors = 0 | (1 << 3); for (i = 0; i < 3; i++) sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i)); - // Enable predefined templates 2, 3 for blocks 3-5 + /* Enable predefined templates 2, 3 for blocks 3-5 */ template_selectors = 2 | (3 << 3); for (i = 3; i < 6; i++) sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i)); - // Enable predefined templates 1, 4 for blocks 6-8 + /* Enable predefined templates 1, 4 for blocks 6-8 */ template_selectors = 2 | (3 << 3); for (i = 6; i < 9; i++) sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i)); - // Enable predefined templates 0, 1 for blocks 9-11 + /* Enable predefined templates 0, 1 for blocks 9-11 */ template_selectors = 0 | (1 << 3); for (i = 9; i < 12; i++) sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i)); - // Enable predefined templates 2, 3 for blocks 12-14 + /* Enable predefined templates 2, 3 for blocks 12-14 */ template_selectors = 2 | (3 << 3); for (i = 12; i < 15; i++) sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i)); - // Enable predefined templates 1, 4 for blocks 15-17 + /* Enable predefined templates 1, 4 for blocks 15-17 */ template_selectors = 2 | (3 << 3); for (i = 15; i < 18; i++) sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i)); @@ -1660,13 +1660,13 @@ static u32 rtl839x_packet_cntr_read(int counter) { u32 v; - // Read LOG table (4) via register RTL8390_TBL_0 + /* Read LOG table (4) via register RTL8390_TBL_0 */ struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 4); pr_debug("In %s, id %d\n", __func__, counter); rtl_table_read(r, counter / 2); - // The table has a size of 2 registers + /* The table has a size of 2 registers */ if (counter % 2) v = sw_r32(rtl_table_data(r, 0)); else @@ -1679,11 +1679,11 @@ static u32 rtl839x_packet_cntr_read(int counter) static void rtl839x_packet_cntr_clear(int counter) { - // Access LOG table (4) via register RTL8390_TBL_0 + /* Access LOG table (4) via register RTL8390_TBL_0 */ struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 4); pr_debug("In %s, id %d\n", __func__, counter); - // The table has a size of 2 registers + /* The table has a size of 2 registers */ if (counter % 2) sw_w32(0, rtl_table_data(r, 0)); else @@ -1697,13 +1697,13 @@ static void rtl839x_packet_cntr_clear(int counter) static void rtl839x_route_read(int idx, struct rtl83xx_route *rt) { u64 v; - // Read ROUTING table (2) via register RTL8390_TBL_1 + /* Read ROUTING table (2) via register RTL8390_TBL_1 */ struct table_reg *r = rtl_table_get(RTL8390_TBL_1, 2); pr_debug("In %s\n", __func__); rtl_table_read(r, idx); - // The table has a size of 2 registers + /* The table has a size of 2 registers */ v = sw_r32(rtl_table_data(r, 0)); v <<= 32; v |= sw_r32(rtl_table_data(r, 1)); @@ -1717,7 +1717,7 @@ static void rtl839x_route_write(int idx, struct rtl83xx_route *rt) { u32 v; - // Read ROUTING table (2) via register RTL8390_TBL_1 + /* Read ROUTING table (2) via register RTL8390_TBL_1 */ struct table_reg *r = rtl_table_get(RTL8390_TBL_1, 2); pr_debug("In %s\n", __func__); @@ -1742,7 +1742,7 @@ static void rtl839x_setup_port_macs(struct rtl838x_switch_priv *priv) mac = ether_addr_to_u64(dev->dev_addr); for (i = 0; i < 15; i++) { - mac++; // BUG: VRRP for testing + mac++; /* BUG: VRRP for testing */ sw_w32(mac >> 32, RTL839X_ROUTING_SA_CTRL + i * 8); sw_w32(mac, RTL839X_ROUTING_SA_CTRL + i * 8 + 4); } diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl930x.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl930x.c index 6cd0c6b8144..384b33b0ba5 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl930x.c +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl930x.c @@ -26,15 +26,15 @@ extern struct rtl83xx_soc_info soc_info; /* Definition of the RTL930X-specific template field IDs as used in the PIE */ enum template_field_id { - TEMPLATE_FIELD_SPM0 = 0, // Source portmask ports 0-15 - TEMPLATE_FIELD_SPM1 = 1, // Source portmask ports 16-31 - TEMPLATE_FIELD_DMAC0 = 2, // Destination MAC [15:0] - TEMPLATE_FIELD_DMAC1 = 3, // Destination MAC [31:16] - TEMPLATE_FIELD_DMAC2 = 4, // Destination MAC [47:32] - TEMPLATE_FIELD_SMAC0 = 5, // Source MAC [15:0] - TEMPLATE_FIELD_SMAC1 = 6, // Source MAC [31:16] - TEMPLATE_FIELD_SMAC2 = 7, // Source MAC [47:32] - TEMPLATE_FIELD_ETHERTYPE = 8, // Ethernet frame type field + TEMPLATE_FIELD_SPM0 = 0, /* Source portmask ports 0-15 */ + TEMPLATE_FIELD_SPM1 = 1, /* Source portmask ports 16-31 */ + TEMPLATE_FIELD_DMAC0 = 2, /* Destination MAC [15:0] */ + TEMPLATE_FIELD_DMAC1 = 3, /* Destination MAC [31:16] */ + TEMPLATE_FIELD_DMAC2 = 4, /* Destination MAC [47:32] */ + TEMPLATE_FIELD_SMAC0 = 5, /* Source MAC [15:0] */ + TEMPLATE_FIELD_SMAC1 = 6, /* Source MAC [31:16] */ + TEMPLATE_FIELD_SMAC2 = 7, /* Source MAC [47:32] */ + TEMPLATE_FIELD_ETHERTYPE = 8, /* Ethernet frame type field */ TEMPLATE_FIELD_OTAG = 9, TEMPLATE_FIELD_ITAG = 10, TEMPLATE_FIELD_SIP0 = 11, @@ -71,7 +71,7 @@ enum template_field_id { TEMPLATE_FIELD_SNAP_OUI = 42, TEMPLATE_FIELD_FWD_VID = 43, TEMPLATE_FIELD_RANGE_CHK = 44, - TEMPLATE_FIELD_VLAN_GMSK = 45, // VLAN Group Mask/IP range check + TEMPLATE_FIELD_VLAN_GMSK = 45, /* VLAN Group Mask/IP range check */ TEMPLATE_FIELD_DLP = 46, TEMPLATE_FIELD_META_DATA = 47, TEMPLATE_FIELD_SRC_FWD_VID = 48, @@ -83,9 +83,9 @@ enum template_field_id { */ #define TEMPLATE_FIELD_VLAN TEMPLATE_FIELD_ITAG -// Number of fixed templates predefined in the RTL9300 SoC +/* Number of fixed templates predefined in the RTL9300 SoC */ #define N_FIXED_TEMPLATES 5 -// RTL9300 specific predefined templates +/* RTL9300 specific predefined templates */ static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] = { { @@ -152,7 +152,7 @@ static inline int rtl930x_l2_port_new_salrn(int p) static inline int rtl930x_l2_port_new_sa_fwd(int p) { - // TODO: The definition of the fields changed, because of the master-cpu in a stack + /* TODO: The definition of the fields changed, because of the master-cpu in a stack */ return RTL930X_L2_PORT_NEW_SA_FWD(p); } @@ -164,7 +164,7 @@ inline static int rtl930x_trk_mbr_ctr(int group) static void rtl930x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info) { u32 v, w; - // Read VLAN table (1) via register 0 + /* Read VLAN table (1) via register 0 */ struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 1); rtl_table_read(r, vlan); @@ -179,7 +179,7 @@ static void rtl930x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info) info->hash_uc_fid = !!(w & BIT(28)); info->fid = ((v & 0x7) << 3) | ((w >> 29) & 0x7); - // Read UNTAG table via table register 2 + /* Read UNTAG table via table register 2 */ r = rtl_table_get(RTL9300_TBL_2, 0); rtl_table_read(r, vlan); v = sw_r32(rtl_table_data(r, 0)); @@ -191,7 +191,7 @@ static void rtl930x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info) static void rtl930x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info) { u32 v, w; - // Access VLAN table (1) via register 0 + /* Access VLAN table (1) via register 0 */ struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 1); v = info->tagged_ports << 3; @@ -245,7 +245,7 @@ static void rtl930x_vlan_set_untagged(u32 vlan, u64 portmask) /* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer */ static void rtl930x_vlan_fwd_on_inner(int port, bool is_set) { - // Always set all tag modes to fwd based on either inner or outer tag + /* Always set all tag modes to fwd based on either inner or outer tag */ if (is_set) sw_w32_mask(0, 0xf, RTL930X_VLAN_PORT_FWD + (port << 2)); else @@ -260,11 +260,11 @@ static void rtl930x_vlan_profile_setup(int profile) p[0] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile)); p[1] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 4); - // Enable routing of Ipv4/6 Unicast and IPv4/6 Multicast traffic + /* Enable routing of Ipv4/6 Unicast and IPv4/6 Multicast traffic */ p[0] |= BIT(17) | BIT(16) | BIT(13) | BIT(12); - p[2] = 0x1fffffff; // L2 unknown MC flooding portmask all ports, including the CPU-port - p[3] = 0x1fffffff; // IPv4 unknown MC flooding portmask - p[4] = 0x1fffffff; // IPv6 unknown MC flooding portmask + p[2] = 0x1fffffff; /* L2 unknown MC flooding portmask all ports, including the CPU-port */ + p[3] = 0x1fffffff; /* IPv4 unknown MC flooding portmask */ + p[4] = 0x1fffffff; /* IPv6 unknown MC flooding portmask */ sw_w32(p[0], RTL930X_VLAN_PROFILE_SET(profile)); sw_w32(p[1], RTL930X_VLAN_PROFILE_SET(profile) + 4); @@ -275,13 +275,13 @@ static void rtl930x_vlan_profile_setup(int profile) static void rtl930x_l2_learning_setup(void) { - // Portmask for flooding broadcast traffic + /* Portmask for flooding broadcast traffic */ sw_w32(0x1fffffff, RTL930X_L2_BC_FLD_PMSK); - // Portmask for flooding unicast traffic with unknown destination + /* Portmask for flooding unicast traffic with unknown destination */ sw_w32(0x1fffffff, RTL930X_L2_UNKN_UC_FLD_PMSK); - // Limit learning to maximum: 32k entries, after that just flood (bits 0-1) + /* Limit learning to maximum: 32k entries, after that just flood (bits 0-1) */ sw_w32((0x7fff << 2) | 0, RTL930X_L2_LRN_CONSTRT_CTRL); } @@ -366,7 +366,7 @@ static u32 rtl930x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed) h1 ^ (seed & 0x7ff)); - // Algorithm choice for block 0 + /* Algorithm choice for block 0 */ if (sw_r32(RTL930X_L2_CTRL) & BIT(0)) h = k1; else @@ -398,7 +398,7 @@ static void rtl930x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e) e->is_ip_mc = false; e->is_ipv6_mc = false; - // TODO: Is there not a function to copy directly MAC memory? + /* TODO: Is there not a function to copy directly MAC memory? */ e->mac[0] = (r[0] >> 24); e->mac[1] = (r[0] >> 16); e->mac[2] = (r[0] >> 8); @@ -414,7 +414,7 @@ static void rtl930x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e) e->type = L2_UNICAST; e->is_static = !!(r[2] & BIT(14)); e->port = (r[2] >> 20) & 0x3ff; - // Check for trunk port + /* Check for trunk port */ if (r[2] & BIT(30)) { e->is_trunk = true; e->stack_dev = (e->port >> 9) & 1; @@ -430,7 +430,7 @@ static void rtl930x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e) e->suspended = !!(r[2] & BIT(13)); e->age = (r[2] >> 17) & 3; e->valid = true; - // the UC_VID field in hardware is used for the VID or for the route id + /* the UC_VID field in hardware is used for the VID or for the route id */ if (e->next_hop) { e->nh_route_id = r[2] & 0x7ff; e->vid = 0; @@ -455,7 +455,7 @@ static void rtl930x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e) return; } - r[2] = BIT(31); // Set valid bit + r[2] = BIT(31); /* Set valid bit */ r[0] = ((u32)e->mac[0]) << 24 | ((u32)e->mac[1]) << 16 | @@ -482,12 +482,12 @@ static void rtl930x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e) r[2] |= e->block_sa ? BIT(17) : 0; r[2] |= e->suspended ? BIT(13) : 0; r[2] |= (e->age & 0x3) << 17; - // the UC_VID field in hardware is used for the VID or for the route id + /* the UC_VID field in hardware is used for the VID or for the route id */ if (e->next_hop) r[2] |= e->nh_route_id & 0x7ff; else r[2] |= e->vid & 0xfff; - } else { // L2_MULTICAST + } else { /* L2_MULTICAST */ r[2] |= (e->mc_portmask_index & 0x3ff) << 16; r[2] |= e->mc_mac_index & 0x7ff; } @@ -519,7 +519,7 @@ static u64 rtl930x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2 hash &= 0xffff; } - idx = (0 << 14) | (hash << 2) | pos; // Search SRAM, with hash and at pos in bucket + idx = (0 << 14) | (hash << 2) | pos; /* Search SRAM, with hash and at pos in bucket */ pr_debug("%s: NOW hash %08x, pos: %d\n", __func__, hash, pos); rtl_table_read(q, idx); @@ -544,7 +544,7 @@ static u64 rtl930x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2 seed = rtl930x_l2_hash_seed(mac, e->rvid); pr_debug("%s: mac %016llx, seed %016llx\n", __func__, mac, seed); - // return vid with concatenated mac as unique id + /* return vid with concatenated mac as unique id */ return seed; } @@ -552,7 +552,7 @@ static void rtl930x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_ { u32 r[3]; struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 0); - u32 idx = (0 << 14) | (hash << 2) | pos; // Access SRAM, with hash and at pos in bucket + u32 idx = (0 << 14) | (hash << 2) | pos; /* Access SRAM, with hash and at pos in bucket */ int i; pr_debug("%s: hash %d, pos %d\n", __func__, hash, pos); @@ -584,14 +584,14 @@ static u64 rtl930x_read_cam(int idx, struct rtl838x_l2_entry *e) if (!e->valid) return 0; - // return mac with concatenated vid as unique id + /* return mac with concatenated vid as unique id */ return ((u64)r[0] << 28) | ((r[1] & 0xffff0000) >> 4) | e->vid; } static void rtl930x_write_cam(int idx, struct rtl838x_l2_entry *e) { u32 r[3]; - struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 1); // Access L2 Table 1 + struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 1); /* Access L2 Table 1 */ int i; rtl930x_fill_l2_row(r, e); @@ -606,7 +606,7 @@ static void rtl930x_write_cam(int idx, struct rtl838x_l2_entry *e) static u64 rtl930x_read_mcast_pmask(int idx) { u32 portmask; - // Read MC_PORTMASK (2) via register RTL9300_TBL_L2 + /* Read MC_PORTMASK (2) via register RTL9300_TBL_L2 */ struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 2); rtl_table_read(q, idx); @@ -623,7 +623,7 @@ static void rtl930x_write_mcast_pmask(int idx, u64 portmask) { u32 pm = portmask; - // Access MC_PORTMASK (2) via register RTL9300_TBL_L2 + /* Access MC_PORTMASK (2) via register RTL9300_TBL_L2 */ struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 2); pr_debug("%s: Index idx %d has portmask %08x\n", __func__, idx, pm); @@ -790,16 +790,16 @@ int rtl930x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val) mutex_lock(&smi_lock); - // Set PHY to access + /* Set PHY to access */ sw_w32(BIT(port), RTL930X_SMI_ACCESS_PHY_CTRL_0); - // Set data to write + /* Set data to write */ sw_w32_mask(0xffff << 16, val << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2); - // Set MMD device number and register to write to + /* Set MMD device number and register to write to */ sw_w32(devnum << 16 | (regnum & 0xffff), RTL930X_SMI_ACCESS_PHY_CTRL_3); - v = BIT(2) | BIT(1) | BIT(0); // WRITE | MMD-access | EXEC + v = BIT(2) | BIT(1) | BIT(0); /* WRITE | MMD-access | EXEC */ sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1); do { @@ -819,19 +819,19 @@ int rtl930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val) mutex_lock(&smi_lock); - // Set PHY to access + /* Set PHY to access */ sw_w32_mask(0xffff << 16, port << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2); - // Set MMD device number and register to write to + /* Set MMD device number and register to write to */ sw_w32(devnum << 16 | (regnum & 0xffff), RTL930X_SMI_ACCESS_PHY_CTRL_3); - v = BIT(1) | BIT(0); // MMD-access | EXEC + v = BIT(1) | BIT(0); /* MMD-access | EXEC */ sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1); do { v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1); } while (v & BIT(0)); - // There is no error-checking via BIT 25 of v, as it does not seem to be set correctly + /* There is no error-checking via BIT 25 of v, as it does not seem to be set correctly */ *val = (sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_2) & 0xffff); pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, *val, err); @@ -868,7 +868,7 @@ u32 rtl930x_hash(struct rtl838x_switch_priv *priv, u64 seed) h1 ^ (seed & 0x7ff)); - // Algorithm choice for block 0 + /* Algorithm choice for block 0 */ if (sw_r32(RTL930X_L2_CTRL) & BIT(0)) h = k1; else @@ -893,17 +893,17 @@ void rtl930x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enabl { u32 v; - // This works only for Ethernet ports, and on the RTL930X, ports from 26 are SFP + /* This works only for Ethernet ports, and on the RTL930X, ports from 26 are SFP */ if (port >= 26) return; pr_debug("In %s: setting port %d to %d\n", __func__, port, enable); v = enable ? 0x3f : 0x0; - // Set EEE/EEEP state for 100, 500, 1000MBit and 2.5, 5 and 10GBit + /* Set EEE/EEEP state for 100, 500, 1000MBit and 2.5, 5 and 10GBit */ sw_w32_mask(0, v << 10, rtl930x_mac_force_mode_ctrl(port)); - // Set TX/RX EEE state + /* Set TX/RX EEE state */ v = enable ? 0x3 : 0x0; sw_w32(v, RTL930X_EEE_CTRL(port)); @@ -951,7 +951,7 @@ int rtl930x_eee_port_ability(struct rtl838x_switch_priv *priv, struct ethtool_ee e->lp_advertised |= ADVERTISED_10000baseT_Full; } - // Read 2x to clear latched state + /* Read 2x to clear latched state */ a = sw_r32(RTL930X_EEEP_PORT_CTRL(port)); a = sw_r32(RTL930X_EEEP_PORT_CTRL(port)); pr_info("%s RTL930X_EEEP_PORT_CTRL: %08x\n", __func__, a); @@ -965,7 +965,7 @@ static void rtl930x_init_eee(struct rtl838x_switch_priv *priv, bool enable) pr_info("Setting up EEE, state: %d\n", enable); - // Setup EEE on all ports + /* Setup EEE on all ports */ for (i = 0; i < priv->cpu_port; i++) { if (priv->ports[i].phy) rtl930x_port_eee_set(priv, i, enable); @@ -1062,11 +1062,11 @@ static void rtl930x_route_read(int idx, struct rtl83xx_route *rt) bool host_route, default_route; struct in6_addr ip6_m; - // Read L3_PREFIX_ROUTE_IPUC table (2) via register RTL9300_TBL_1 + /* Read L3_PREFIX_ROUTE_IPUC table (2) via register RTL9300_TBL_1 */ struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 2); rtl_table_read(r, idx); - // The table has a size of 11 registers + /* The table has a size of 11 registers */ rt->attr.valid = !!(sw_r32(rtl_table_data(r, 0)) & BIT(31)); if (!rt->attr.valid) goto out; @@ -1080,7 +1080,7 @@ static void rtl930x_route_read(int idx, struct rtl83xx_route *rt) pr_info("%s: host route %d, default_route %d\n", __func__, host_route, default_route); switch (rt->attr.type) { - case 0: // IPv4 Unicast route + case 0: /* IPv4 Unicast route */ rt->dst_ip = sw_r32(rtl_table_data(r, 4)); ip4_m = sw_r32(rtl_table_data(r, 9)); pr_info("%s: Read ip4 mask: %08x\n", __func__, ip4_m); @@ -1089,7 +1089,7 @@ static void rtl930x_route_read(int idx, struct rtl83xx_route *rt) if (rt->prefix_len < 0) rt->prefix_len = inet_mask_len(ip4_m); break; - case 2: // IPv6 Unicast route + case 2: /* IPv6 Unicast route */ ipv6_addr_set(&rt->dst_ip6, sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 2)), sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 4))); @@ -1102,8 +1102,8 @@ static void rtl930x_route_read(int idx, struct rtl83xx_route *rt) rt->prefix_len = find_last_bit((unsigned long int *)&ip6_m.s6_addr32, 128); break; - case 1: // IPv4 Multicast route - case 3: // IPv6 Multicast route + case 1: /* IPv4 Multicast route */ + case 3: /* IPv6 Multicast route */ pr_warn("%s: route type not supported\n", __func__); goto out; } @@ -1128,7 +1128,7 @@ out: static void rtl930x_net6_mask(int prefix_len, struct in6_addr *ip6_m) { int o, b; - // Define network mask + /* Define network mask */ o = prefix_len >> 3; b = prefix_len & 0x7; memset(ip6_m->s6_addr, 0xff, o); @@ -1141,30 +1141,30 @@ static void rtl930x_net6_mask(int prefix_len, struct in6_addr *ip6_m) static void rtl930x_host_route_read(int idx, struct rtl83xx_route *rt) { u32 v; - // Read L3_HOST_ROUTE_IPUC table (1) via register RTL9300_TBL_1 + /* Read L3_HOST_ROUTE_IPUC table (1) via register RTL9300_TBL_1 */ struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 1); idx = ((idx / 6) * 8) + (idx % 6); pr_debug("In %s, physical index %d\n", __func__, idx); rtl_table_read(r, idx); - // The table has a size of 5 (for UC, 11 for MC) registers + /* The table has a size of 5 (for UC, 11 for MC) registers */ v = sw_r32(rtl_table_data(r, 0)); rt->attr.valid = !!(v & BIT(31)); if (!rt->attr.valid) goto out; rt->attr.type = (v >> 29) & 0x3; switch (rt->attr.type) { - case 0: // IPv4 Unicast route + case 0: /* IPv4 Unicast route */ rt->dst_ip = sw_r32(rtl_table_data(r, 4)); break; - case 2: // IPv6 Unicast route + case 2: /* IPv6 Unicast route */ ipv6_addr_set(&rt->dst_ip6, sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 2)), sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 0))); break; - case 1: // IPv4 Multicast route - case 3: // IPv6 Multicast route + case 1: /* IPv4 Multicast route */ + case 3: /* IPv6 Multicast route */ pr_warn("%s: route type not supported\n", __func__); goto out; } @@ -1193,9 +1193,9 @@ out: static void rtl930x_host_route_write(int idx, struct rtl83xx_route *rt) { u32 v; - // Access L3_HOST_ROUTE_IPUC table (1) via register RTL9300_TBL_1 + /* Access L3_HOST_ROUTE_IPUC table (1) via register RTL9300_TBL_1 */ struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 1); - // The table has a size of 5 (for UC, 11 for MC) registers + /* The table has a size of 5 (for UC, 11 for MC) registers */ idx = ((idx / 6) * 8) + (idx % 6); @@ -1205,7 +1205,7 @@ static void rtl930x_host_route_write(int idx, struct rtl83xx_route *rt) rt->attr.dst_null); pr_debug("%s: GW: %pI4, prefix_len: %d\n", __func__, &rt->dst_ip, rt->prefix_len); - v = BIT(31); // Entry is valid + v = BIT(31); /* Entry is valid */ v |= (rt->attr.type & 0x3) << 29; v |= rt->attr.hit ? BIT(20) : 0; v |= rt->attr.dst_null ? BIT(19) : 0; @@ -1218,20 +1218,20 @@ static void rtl930x_host_route_write(int idx, struct rtl83xx_route *rt) sw_w32(v, rtl_table_data(r, 0)); switch (rt->attr.type) { - case 0: // IPv4 Unicast route + case 0: /* IPv4 Unicast route */ sw_w32(0, rtl_table_data(r, 1)); sw_w32(0, rtl_table_data(r, 2)); sw_w32(0, rtl_table_data(r, 3)); sw_w32(rt->dst_ip, rtl_table_data(r, 4)); break; - case 2: // IPv6 Unicast route + case 2: /* IPv6 Unicast route */ sw_w32(rt->dst_ip6.s6_addr32[0], rtl_table_data(r, 1)); sw_w32(rt->dst_ip6.s6_addr32[1], rtl_table_data(r, 2)); sw_w32(rt->dst_ip6.s6_addr32[2], rtl_table_data(r, 3)); sw_w32(rt->dst_ip6.s6_addr32[3], rtl_table_data(r, 4)); break; - case 1: // IPv4 Multicast route - case 3: // IPv6 Multicast route + case 1: /* IPv4 Multicast route */ + case 3: /* IPv6 Multicast route */ pr_warn("%s: route type not supported\n", __func__); goto out; } @@ -1251,16 +1251,16 @@ static int rtl930x_route_lookup_hw(struct rtl83xx_route *rt) struct in6_addr ip6_m; int i; - if (rt->attr.type == 1 || rt->attr.type == 3) // Hardware only supports UC routes + if (rt->attr.type == 1 || rt->attr.type == 3) /* Hardware only supports UC routes */ return -1; sw_w32_mask(0x3 << 19, rt->attr.type, RTL930X_L3_HW_LU_KEY_CTRL); - if (rt->attr.type) { // IPv6 + if (rt->attr.type) { /* IPv6 */ rtl930x_net6_mask(rt->prefix_len, &ip6_m); for (i = 0; i < 4; i++) sw_w32(rt->dst_ip6.s6_addr32[0] & ip6_m.s6_addr32[0], RTL930X_L3_HW_LU_KEY_IP_CTRL + (i << 2)); - } else { // IPv4 + } else { /* IPv4 */ ip4_m = inet_make_mask(rt->prefix_len); sw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL); sw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL + 4); @@ -1270,17 +1270,17 @@ static int rtl930x_route_lookup_hw(struct rtl83xx_route *rt) sw_w32(v, RTL930X_L3_HW_LU_KEY_IP_CTRL + 12); } - // Execute CAM lookup in SoC + /* Execute CAM lookup in SoC */ sw_w32(BIT(15), RTL930X_L3_HW_LU_CTRL); - // Wait until execute bit clears and result is ready + /* Wait until execute bit clears and result is ready */ do { v = sw_r32(RTL930X_L3_HW_LU_CTRL); } while (v & BIT(15)); pr_info("%s: found: %d, index: %d\n", __func__, !!(v & BIT(14)), v & 0x1ff); - // Test if search successful (BIT 14 set) + /* Test if search successful (BIT 14 set) */ if (v & BIT(14)) return v & 0x1ff; @@ -1293,7 +1293,7 @@ static int rtl930x_find_l3_slot(struct rtl83xx_route *rt, bool must_exist) u32 hash; struct rtl83xx_route route_entry; - // IPv6 entries take up 3 slots + /* IPv6 entries take up 3 slots */ slot_width = (rt->attr.type == 0) || (rt->attr.type == 2) ? 1 : 3; for (t = 0; t < 2; t++) { @@ -1328,8 +1328,8 @@ static void rtl930x_route_write(int idx, struct rtl83xx_route *rt) { u32 v, ip4_m; struct in6_addr ip6_m; - // Access L3_PREFIX_ROUTE_IPUC table (2) via register RTL9300_TBL_1 - // The table has a size of 11 registers (20 for MC) + /* Access L3_PREFIX_ROUTE_IPUC table (2) via register RTL9300_TBL_1 */ + /* The table has a size of 11 registers (20 for MC) */ struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 2); pr_debug("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid); @@ -1350,32 +1350,32 @@ static void rtl930x_route_write(int idx, struct rtl83xx_route *rt) v |= rt->attr.dst_null ? BIT(6) : 0; v |= rt->attr.qos_as ? BIT(6) : 0; v |= rt->attr.qos_prio & 0x7; - v |= rt->prefix_len == 0 ? BIT(20) : 0; // set default route bit + v |= rt->prefix_len == 0 ? BIT(20) : 0; /* set default route bit */ - // set bit mask for entry type always to 0x3 + /* set bit mask for entry type always to 0x3 */ sw_w32(0x3 << 29, rtl_table_data(r, 5)); switch (rt->attr.type) { - case 0: // IPv4 Unicast route + case 0: /* IPv4 Unicast route */ sw_w32(0, rtl_table_data(r, 1)); sw_w32(0, rtl_table_data(r, 2)); sw_w32(0, rtl_table_data(r, 3)); sw_w32(rt->dst_ip, rtl_table_data(r, 4)); - v |= rt->prefix_len == 32 ? BIT(21) : 0; // set host-route bit + v |= rt->prefix_len == 32 ? BIT(21) : 0; /* set host-route bit */ ip4_m = inet_make_mask(rt->prefix_len); sw_w32(0, rtl_table_data(r, 6)); sw_w32(0, rtl_table_data(r, 7)); sw_w32(0, rtl_table_data(r, 8)); sw_w32(ip4_m, rtl_table_data(r, 9)); break; - case 2: // IPv6 Unicast route + case 2: /* IPv6 Unicast route */ sw_w32(rt->dst_ip6.s6_addr32[0], rtl_table_data(r, 1)); sw_w32(rt->dst_ip6.s6_addr32[1], rtl_table_data(r, 2)); sw_w32(rt->dst_ip6.s6_addr32[2], rtl_table_data(r, 3)); sw_w32(rt->dst_ip6.s6_addr32[3], rtl_table_data(r, 4)); - v |= rt->prefix_len == 128 ? BIT(21) : 0; // set host-route bit + v |= rt->prefix_len == 128 ? BIT(21) : 0; /* set host-route bit */ rtl930x_net6_mask(rt->prefix_len, &ip6_m); @@ -1384,8 +1384,8 @@ static void rtl930x_route_write(int idx, struct rtl83xx_route *rt) sw_w32(ip6_m.s6_addr32[2], rtl_table_data(r, 8)); sw_w32(ip6_m.s6_addr32[3], rtl_table_data(r, 9)); break; - case 1: // IPv4 Multicast route - case 3: // IPv6 Multicast route + case 1: /* IPv4 Multicast route */ + case 3: /* IPv6 Multicast route */ pr_warn("%s: route type not supported\n", __func__); rtl_table_release(r); return; @@ -1409,11 +1409,11 @@ static void rtl930x_route_write(int idx, struct rtl83xx_route *rt) static void rtl930x_get_l3_nexthop(int idx, u16 *dmac_id, u16 *interface) { u32 v; - // Read L3_NEXTHOP table (3) via register RTL9300_TBL_1 + /* Read L3_NEXTHOP table (3) via register RTL9300_TBL_1 */ struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 3); rtl_table_read(r, idx); - // The table has a size of 1 register + /* The table has a size of 1 register */ v = sw_r32(rtl_table_data(r, 0)); rtl_table_release(r); @@ -1442,7 +1442,7 @@ static int rtl930x_l3_mtu_add(struct rtl838x_switch_priv *priv, int mtu) int i, free_mtu; int mtu_id; - // Try to find an existing mtu-value or a free slot + /* Try to find an existing mtu-value or a free slot */ free_mtu = MAX_INTF_MTUS; for (i = 0; i < MAX_INTF_MTUS && priv->intf_mtus[i] != mtu; i++) { if ((!priv->intf_mtu_count[i]) && (free_mtu == MAX_INTF_MTUS)) @@ -1458,7 +1458,7 @@ static int rtl930x_l3_mtu_add(struct rtl838x_switch_priv *priv, int mtu) priv->intf_mtus[i] = mtu; pr_info("Writing MTU %d to slot %d\n", priv->intf_mtus[i], i); - // Set MTU-value of the slot TODO: distinguish between IPv4/IPv6 routes / slots + /* Set MTU-value of the slot TODO: distinguish between IPv4/IPv6 routes / slots */ sw_w32_mask(0xffff << ((i % 2) * 16), priv->intf_mtus[i] << ((i % 2) * 16), RTL930X_L3_IP_MTU_CTRL(i)); sw_w32_mask(0xffff << ((i % 2) * 16), priv->intf_mtus[i] << ((i % 2) * 16), @@ -1473,9 +1473,9 @@ static int rtl930x_l3_mtu_add(struct rtl838x_switch_priv *priv, int mtu) static int rtl930x_l3_intf_add(struct rtl838x_switch_priv *priv, struct rtl838x_l3_intf *intf) { int i, intf_id, mtu_id; - // number of MTU-values < 16384 + /* number of MTU-values < 16384 */ - // Use the same IPv6 mtu as the ip4 mtu for this route if unset + /* Use the same IPv6 mtu as the ip4 mtu for this route if unset */ intf->ip6_mtu = intf->ip6_mtu ? intf->ip6_mtu : intf->ip4_mtu; mtu_id = rtl930x_l3_mtu_add(priv, intf->ip4_mtu); @@ -1510,7 +1510,7 @@ static int rtl930x_l3_intf_add(struct rtl838x_switch_priv *priv, struct rtl838x_ */ static void rtl930x_set_l3_nexthop(int idx, u16 dmac_id, u16 interface) { - // Access L3_NEXTHOP table (3) via register RTL9300_TBL_1 + /* Access L3_NEXTHOP table (3) via register RTL9300_TBL_1 */ struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 3); pr_info("%s: Writing to L3_NEXTHOP table, index %d, dmac_id %d, interface %d\n", @@ -1685,7 +1685,7 @@ static void rtl930x_write_pie_templated(u32 r[], struct pie_rule *pr, enum templ pr_info("%s: unknown field %d\n", __func__, field_type); } - // On the RTL9300, the mask fields are not word aligned! + /* On the RTL9300, the mask fields are not word aligned! */ if (!(i % 2)) { r[5 - i / 2] = data; r[12 - i / 2] |= ((u32)data_m << 8); @@ -1787,15 +1787,15 @@ static void rtl930x_write_pie_fixed_fields(u32 r[], struct pie_rule *pr) static void rtl930x_write_pie_action(u32 r[], struct pie_rule *pr) { - // Either drop or forward + /* Either drop or forward */ if (pr->drop) { - r[14] |= BIT(24) | BIT(25) | BIT(26); // Do Green, Yellow and Red drops - // Actually DROP, not PERMIT in Green / Yellow / Red + r[14] |= BIT(24) | BIT(25) | BIT(26); /* Do Green, Yellow and Red drops */ + /* Actually DROP, not PERMIT in Green / Yellow / Red */ r[14] |= BIT(23) | BIT(22) | BIT(20); } else { r[14] |= pr->fwd_sel ? BIT(27) : 0; r[14] |= pr->fwd_act << 18; - r[14] |= BIT(14); // We overwrite any drop + r[14] |= BIT(14); /* We overwrite any drop */ } if (pr->phase == PHASE_VACL) r[14] |= pr->fwd_sa_lrn ? BIT(15) : 0; @@ -1844,7 +1844,7 @@ void rtl930x_pie_rule_dump_raw(u32 r[]) static int rtl930x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr) { - // Access IACL table (2) via register 0 + /* Access IACL table (2) via register 0 */ struct table_reg *q = rtl_table_get(RTL9300_TBL_0, 2); u32 r[19]; int i; @@ -1868,7 +1868,7 @@ static int rtl930x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, str rtl930x_write_pie_action(r, pr); -// rtl930x_pie_rule_dump_raw(r); +/* rtl930x_pie_rule_dump_raw(r); */ for (i = 0; i < 19; i++) sw_w32(r[i], rtl_table_data(q, i)); @@ -1929,7 +1929,7 @@ static int rtl930x_pie_verify_template(struct rtl838x_switch_priv *priv, if (ether_addr_to_u64(pr->dmac) && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0)) return -1; - // TODO: Check more + /* TODO: Check more */ i = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE); @@ -1976,7 +1976,7 @@ static int rtl930x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rul set_bit(idx, priv->pie_use_bm); pr->valid = true; - pr->tid = j; // Mapped to template number + pr->tid = j; /* Mapped to template number */ pr->tid_m = 0x1; pr->id = idx; @@ -1995,10 +1995,10 @@ static int rtl930x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from pr_debug("%s: from %d to %d\n", __func__, index_from, index_to); mutex_lock(&priv->reg_mutex); - // Write from-to and execute bit into control register + /* Write from-to and execute bit into control register */ sw_w32(v, RTL930X_PIE_CLR_CTRL); - // Wait until command has completed + /* Wait until command has completed */ do { } while (sw_r32(RTL930X_PIE_CLR_CTRL) & BIT(0)); @@ -2022,35 +2022,35 @@ static void rtl930x_pie_init(struct rtl838x_switch_priv *priv) mutex_init(&priv->pie_mutex); pr_info("%s\n", __func__); - // Enable ACL lookup on all ports, including CPU_PORT + /* Enable ACL lookup on all ports, including CPU_PORT */ for (i = 0; i <= priv->cpu_port; i++) sw_w32(1, RTL930X_ACL_PORT_LOOKUP_CTRL(i)); - // Include IPG in metering + /* Include IPG in metering */ sw_w32_mask(0, 1, RTL930X_METER_GLB_CTRL); - // Delete all present rules, block size is 128 on all SoC families + /* Delete all present rules, block size is 128 on all SoC families */ rtl930x_pie_rule_del(priv, 0, priv->n_pie_blocks * 128 - 1); - // Assign blocks 0-7 to VACL phase (bit = 0), blocks 8-15 to IACL (bit = 1) + /* Assign blocks 0-7 to VACL phase (bit = 0), blocks 8-15 to IACL (bit = 1) */ sw_w32(0xff00, RTL930X_PIE_BLK_PHASE_CTRL); - // Enable predefined templates 0, 1 for first quarter of all blocks + /* Enable predefined templates 0, 1 for first quarter of all blocks */ template_selectors = 0 | (1 << 4); for (i = 0; i < priv->n_pie_blocks / 4; i++) sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i)); - // Enable predefined templates 2, 3 for second quarter of all blocks + /* Enable predefined templates 2, 3 for second quarter of all blocks */ template_selectors = 2 | (3 << 4); for (i = priv->n_pie_blocks / 4; i < priv->n_pie_blocks / 2; i++) sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i)); - // Enable predefined templates 0, 1 for third half of all blocks + /* Enable predefined templates 0, 1 for third half of all blocks */ template_selectors = 0 | (1 << 4); for (i = priv->n_pie_blocks / 2; i < priv->n_pie_blocks * 3 / 4; i++) sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i)); - // Enable predefined templates 2, 3 for fourth quater of all blocks + /* Enable predefined templates 2, 3 for fourth quater of all blocks */ template_selectors = 2 | (3 << 4); for (i = priv->n_pie_blocks * 3 / 4; i < priv->n_pie_blocks; i++) sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i)); @@ -2066,10 +2066,10 @@ static void rtl930x_pie_init(struct rtl838x_switch_priv *priv) static void rtl930x_set_l3_egress_intf(int idx, struct rtl838x_l3_intf *intf) { u32 u, v; - // Read L3_EGR_INTF table (4) via register RTL9300_TBL_1 + /* Read L3_EGR_INTF table (4) via register RTL9300_TBL_1 */ struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 4); - // The table has 2 registers + /* The table has 2 registers */ u = (intf->vid & 0xfff) << 9; u |= (intf->smac_idx & 0x3f) << 3; u |= (intf->ip4_mtu_id & 0x7); @@ -2097,11 +2097,11 @@ static void rtl930x_set_l3_egress_intf(int idx, struct rtl838x_l3_intf *intf) static void rtl930x_get_l3_router_mac(u32 idx, struct rtl93xx_rt_mac *m) { u32 v, w; - // Read L3_ROUTER_MAC table (0) via register RTL9300_TBL_1 + /* Read L3_ROUTER_MAC table (0) via register RTL9300_TBL_1 */ struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 0); rtl_table_read(r, idx); - // The table has a size of 7 registers, 64 entries + /* The table has a size of 7 registers, 64 entries */ v = sw_r32(rtl_table_data(r, 0)); w = sw_r32(rtl_table_data(r, 3)); m->valid = !!(v & BIT(20)); @@ -2109,7 +2109,7 @@ static void rtl930x_get_l3_router_mac(u32 idx, struct rtl93xx_rt_mac *m) goto out; m->p_type = !!(v & BIT(19)); - m->p_id = (v >> 13) & 0x3f; // trunk id of port + m->p_id = (v >> 13) & 0x3f; /* trunk id of port */ m->vid = v & 0xfff; m->vid_mask = w & 0xfff; m->action = sw_r32(rtl_table_data(r, 6)) & 0x7; @@ -2117,7 +2117,7 @@ static void rtl930x_get_l3_router_mac(u32 idx, struct rtl93xx_rt_mac *m) (sw_r32(rtl_table_data(r, 4))); m->mac = ((((u64)sw_r32(rtl_table_data(r, 1))) << 32) & 0xffffffffffffULL) | (sw_r32(rtl_table_data(r, 2))); - // Bits L3_INTF and BMSK_L3_INTF are 0 + /* Bits L3_INTF and BMSK_L3_INTF are 0 */ out: rtl_table_release(r); @@ -2130,13 +2130,13 @@ out: static void rtl930x_set_l3_router_mac(u32 idx, struct rtl93xx_rt_mac *m) { u32 v, w; - // Read L3_ROUTER_MAC table (0) via register RTL9300_TBL_1 + /* Read L3_ROUTER_MAC table (0) via register RTL9300_TBL_1 */ struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 0); - // The table has a size of 7 registers, 64 entries - v = BIT(20); // mac entry valid, port type is 0: individual + /* The table has a size of 7 registers, 64 entries */ + v = BIT(20); /* mac entry valid, port type is 0: individual */ v |= (m->p_id & 0x3f) << 13; - v |= (m->vid & 0xfff); // Set the interface_id to the vlan id + v |= (m->vid & 0xfff); /* Set the interface_id to the vlan id */ w = m->vid_mask; w |= (m->p_id_mask & 0x3f) << 13; @@ -2144,11 +2144,11 @@ static void rtl930x_set_l3_router_mac(u32 idx, struct rtl93xx_rt_mac *m) sw_w32(v, rtl_table_data(r, 0)); sw_w32(w, rtl_table_data(r, 3)); - // Set MAC address, L3_INTF (bit 12 in register 1) needs to be 0 + /* Set MAC address, L3_INTF (bit 12 in register 1) needs to be 0 */ sw_w32((u32)(m->mac), rtl_table_data(r, 2)); sw_w32(m->mac >> 32, rtl_table_data(r, 1)); - // Set MAC address mask, BMSK_L3_INTF (bit 12 in register 5) needs to be 0 + /* Set MAC address mask, BMSK_L3_INTF (bit 12 in register 5) needs to be 0 */ sw_w32((u32)(m->mac_mask >> 32), rtl_table_data(r, 4)); sw_w32((u32)m->mac_mask, rtl_table_data(r, 5)); @@ -2170,11 +2170,11 @@ static void rtl930x_set_l3_router_mac(u32 idx, struct rtl93xx_rt_mac *m) static u64 rtl930x_get_l3_egress_mac(u32 idx) { u64 mac; - // Read L3_EGR_INTF_MAC table (2) via register RTL9300_TBL_2 + /* Read L3_EGR_INTF_MAC table (2) via register RTL9300_TBL_2 */ struct table_reg *r = rtl_table_get(RTL9300_TBL_2, 2); rtl_table_read(r, idx); - // The table has a size of 2 registers + /* The table has a size of 2 registers */ mac = sw_r32(rtl_table_data(r, 0)); mac <<= 32; mac |= sw_r32(rtl_table_data(r, 1)); @@ -2189,10 +2189,10 @@ static u64 rtl930x_get_l3_egress_mac(u32 idx) */ static void rtl930x_set_l3_egress_mac(u32 idx, u64 mac) { - // Access L3_EGR_INTF_MAC table (2) via register RTL9300_TBL_2 + /* Access L3_EGR_INTF_MAC table (2) via register RTL9300_TBL_2 */ struct table_reg *r = rtl_table_get(RTL9300_TBL_2, 2); - // The table has a size of 2 registers + /* The table has a size of 2 registers */ sw_w32(mac >> 32, rtl_table_data(r, 0)); sw_w32(mac, rtl_table_data(r, 1)); @@ -2211,11 +2211,11 @@ int rtl930x_l3_setup(struct rtl838x_switch_priv *priv) { int i; - // Setup MTU with id 0 for default interface + /* Setup MTU with id 0 for default interface */ for (i = 0; i < MAX_INTF_MTUS; i++) priv->intf_mtu_count[i] = priv->intf_mtus[i] = 0; - priv->intf_mtu_count[0] = 0; // Needs to stay forever + priv->intf_mtu_count[0] = 0; /* Needs to stay forever */ priv->intf_mtus[0] = DEFAULT_MTU; sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP_MTU_CTRL(0)); sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP6_MTU_CTRL(0)); @@ -2228,13 +2228,13 @@ int rtl930x_l3_setup(struct rtl838x_switch_priv *priv) sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP_MTU_CTRL(1)); sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP6_MTU_CTRL(1)); - // Clear all source port MACs + /* Clear all source port MACs */ for (i = 0; i < MAX_SMACS; i++) rtl930x_set_l3_egress_mac(L3_EGRESS_DMACS + i, 0ULL); - // Configure the default L3 hash algorithm - sw_w32_mask(BIT(2), 0, RTL930X_L3_HOST_TBL_CTRL); // Algorithm selection 0 = 0 - sw_w32_mask(0, BIT(3), RTL930X_L3_HOST_TBL_CTRL); // Algorithm selection 1 = 1 + /* Configure the default L3 hash algorithm */ + sw_w32_mask(BIT(2), 0, RTL930X_L3_HOST_TBL_CTRL); /* Algorithm selection 0 = 0 */ + sw_w32_mask(0, BIT(3), RTL930X_L3_HOST_TBL_CTRL); /* Algorithm selection 1 = 1 */ pr_info("L3_IPUC_ROUTE_CTRL %08x, IPMC_ROUTE %08x, IP6UC_ROUTE %08x, IP6MC_ROUTE %08x\n", sw_r32(RTL930X_L3_IPUC_ROUTE_CTRL), sw_r32(RTL930X_L3_IPMC_ROUTE_CTRL), @@ -2253,13 +2253,13 @@ int rtl930x_l3_setup(struct rtl838x_switch_priv *priv) sw_r32(RTL930X_L3_IPUC_ROUTE_CTRL), sw_r32(RTL930X_L3_IPMC_ROUTE_CTRL), sw_r32(RTL930X_L3_IP6UC_ROUTE_CTRL), sw_r32(RTL930X_L3_IP6MC_ROUTE_CTRL)); - // Trap non-ip traffic to the CPU-port (e.g. ARP so we stay reachable) + /* Trap non-ip traffic to the CPU-port (e.g. ARP so we stay reachable) */ sw_w32_mask(0x3 << 8, 0x1 << 8, RTL930X_L3_IP_ROUTE_CTRL); pr_info("L3_IP_ROUTE_CTRL %08x\n", sw_r32(RTL930X_L3_IP_ROUTE_CTRL)); - // PORT_ISO_RESTRICT_ROUTE_CTRL ? + /* PORT_ISO_RESTRICT_ROUTE_CTRL? */ - // Do not use prefix route 0 because of HW limitations + /* Do not use prefix route 0 because of HW limitations */ set_bit(0, priv->route_use_bm); return 0; @@ -2269,7 +2269,7 @@ static u32 rtl930x_packet_cntr_read(int counter) { u32 v; - // Read LOG table (3) via register RTL9300_TBL_0 + /* Read LOG table (3) via register RTL9300_TBL_0 */ struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 3); pr_debug("In %s, id %d\n", __func__, counter); @@ -2277,7 +2277,7 @@ static u32 rtl930x_packet_cntr_read(int counter) pr_debug("Registers: %08x %08x\n", sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1))); - // The table has a size of 2 registers + /* The table has a size of 2 registers */ if (counter % 2) v = sw_r32(rtl_table_data(r, 0)); else @@ -2290,11 +2290,11 @@ static u32 rtl930x_packet_cntr_read(int counter) static void rtl930x_packet_cntr_clear(int counter) { - // Access LOG table (3) via register RTL9300_TBL_0 + /* Access LOG table (3) via register RTL9300_TBL_0 */ struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 3); pr_info("In %s, id %d\n", __func__, counter); - // The table has a size of 2 registers + /* The table has a size of 2 registers */ if (counter % 2) sw_w32(0, rtl_table_data(r, 0)); else @@ -2447,10 +2447,10 @@ static void rtl930x_led_init(struct rtl838x_switch_priv *priv) sw_w32(v, RTL930X_LED_SET0_0_CTRL - i * 8); } - // Set LED mode to serial (0x1) + /* Set LED mode to serial (0x1) */ sw_w32_mask(0x3, 0x1, RTL930X_LED_GLB_CTRL); - // Set port type masks + /* Set port type masks */ sw_w32(pm, RTL930X_LED_PORT_COPR_MASK_CTRL); sw_w32(pm, RTL930X_LED_PORT_FIB_MASK_CTRL); sw_w32(pm, RTL930X_LED_PORT_COMBO_MASK_CTRL); @@ -2477,7 +2477,7 @@ const struct rtl838x_reg rtl930x_reg = { .l2_ctrl_1 = RTL930X_L2_AGE_CTRL, .l2_port_aging_out = RTL930X_L2_PORT_AGE_CTRL, .set_ageing_time = rtl930x_set_ageing_time, - .smi_poll_ctrl = RTL930X_SMI_POLL_CTRL, // TODO: Difference to RTL9300_SMI_PRVTE_POLLING_CTRL + .smi_poll_ctrl = RTL930X_SMI_POLL_CTRL, /* TODO: Difference to RTL9300_SMI_PRVTE_POLLING_CTRL */ .l2_tbl_flush_ctrl = RTL930X_L2_TBL_FLUSH_CTRL, .exec_tbl0_cmd = rtl930x_exec_tbl0_cmd, .exec_tbl1_cmd = rtl930x_exec_tbl1_cmd, diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl931x.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl931x.c index 802eecccd87..cd7c5edf51b 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl931x.c +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl931x.c @@ -80,9 +80,9 @@ enum template_field_id { */ #define TEMPLATE_FIELD_VLAN TEMPLATE_FIELD_ITAG -// Number of fixed templates predefined in the RTL9300 SoC +/* Number of fixed templates predefined in the RTL9300 SoC */ #define N_FIXED_TEMPLATES 5 -// RTL931x specific predefined templates +/* RTL931x specific predefined templates */ static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS_RTL931X] = { { @@ -188,7 +188,7 @@ inline static int rtl931x_trk_mbr_ctr(int group) static void rtl931x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info) { u32 v, w, x, y; - // Read VLAN table (3) via register 0 + /* Read VLAN table (3) via register 0 */ struct table_reg *r = rtl_table_get(RTL9310_TBL_0, 3); rtl_table_read(r, vlan); @@ -201,7 +201,7 @@ static void rtl931x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info) pr_debug("VLAN_READ %d: %08x %08x %08x %08x\n", vlan, v, w, x, y); info->tagged_ports = ((u64) v) << 25 | (w >> 7); info->profile_id = (x >> 16) & 0xf; - info->fid = w & 0x7f; // AKA MSTI depending on context + info->fid = w & 0x7f; /* AKA MSTI depending on context */ info->hash_uc_fid = !!(x & BIT(31)); info->hash_mc_fid = !!(x & BIT(30)); info->if_id = (x >> 20) & 0x3ff; @@ -215,7 +215,7 @@ static void rtl931x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info) info->tagged_ports, info->profile_id, info->hash_uc_fid, info->hash_mc_fid, info->if_id); - // Read UNTAG table via table register 3 + /* Read UNTAG table via table register 3 */ r = rtl_table_get(RTL9310_TBL_3, 0); rtl_table_read(r, vlan); v = ((u64)sw_r32(rtl_table_data(r, 0))) << 25; @@ -228,7 +228,7 @@ static void rtl931x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info) static void rtl931x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info) { u32 v, w, x, y; - // Access VLAN table (1) via register 0 + /* Access VLAN table (1) via register 0 */ struct table_reg *r = rtl_table_get(RTL9310_TBL_0, 3); v = info->tagged_ports >> 25; @@ -302,7 +302,7 @@ irqreturn_t rtl931x_switch_irq(int irq, void *dev_id) pr_debug("RTL931X Link change: status: %x, ports %016llx\n", status, ports); link = rtl839x_get_port_reg_le(RTL931X_MAC_LINK_STS); - // Must re-read this to get correct status + /* Must re-read this to get correct status */ link = rtl839x_get_port_reg_le(RTL931X_MAC_LINK_STS); pr_debug("RTL931X Link change: status: %x, link status %016llx\n", status, link); @@ -402,20 +402,20 @@ int rtl931x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val) mutex_lock(&smi_lock); - // Set PHY to access via port-number + /* Set PHY to access via port-number */ sw_w32(port << 5, RTL931X_SMI_INDRT_ACCESS_BC_PHYID_CTRL); - // Set MMD device number and register to write to + /* Set MMD device number and register to write to */ sw_w32(devnum << 16 | mdiobus_c45_regad(regnum), RTL931X_SMI_INDRT_ACCESS_MMD_CTRL); - v = type << 2 | BIT(0); // MMD-access-type | EXEC + v = type << 2 | BIT(0); /* MMD-access-type | EXEC */ sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0); do { v = sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0); } while (v & BIT(0)); - // Check for error condition + /* Check for error condition */ if (v & BIT(1)) err = -EIO; @@ -439,18 +439,18 @@ int rtl931x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val) mutex_lock(&smi_lock); - // Set PHY to access via port-mask + /* Set PHY to access via port-mask */ pm = (u64)1 << port; sw_w32((u32)pm, RTL931X_SMI_INDRT_ACCESS_CTRL_2); sw_w32((u32)(pm >> 32), RTL931X_SMI_INDRT_ACCESS_CTRL_2 + 4); - // Set data to write + /* Set data to write */ sw_w32_mask(0xffff, val, RTL931X_SMI_INDRT_ACCESS_CTRL_3); - // Set MMD device number and register to write to + /* Set MMD device number and register to write to */ sw_w32(devnum << 16 | mdiobus_c45_regad(regnum), RTL931X_SMI_INDRT_ACCESS_MMD_CTRL); - v = BIT(4) | type << 2 | BIT(0); // WRITE | MMD-access-type | EXEC + v = BIT(4) | type << 2 | BIT(0); /* WRITE | MMD-access-type | EXEC */ sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0); do { @@ -508,9 +508,9 @@ void rtl931x_set_receive_management_action(int port, rma_ctrl_t type, action_typ sw_w32_mask(7 << ((port % 10) * 3), value << ((port % 10) * 3), RTL931X_RMA_BPDU_CTRL + ((port / 10) << 2)); break; case PTP: - //udp + /* udp */ sw_w32_mask(3 << 2, value << 2, RTL931X_RMA_PTP_CTRL + (port << 2)); - //eth2 + /* eth2 */ sw_w32_mask(3, value, RTL931X_RMA_PTP_CTRL + (port << 2)); break; case PTP_UDP: @@ -609,7 +609,7 @@ static u32 rtl931x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed) h4 = (seed >> 48) & 0xfff; k1 = h0 ^ h1 ^ h2 ^ h3 ^ h4; - // Algorithm choice for block 0 + /* Algorithm choice for block 0 */ if (sw_r32(RTL931X_L2_CTRL) & BIT(0)) h = k1; else @@ -659,7 +659,7 @@ static void rtl931x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e) e->is_l2_tunnel = !!(r[2] & BIT(31)); e->is_static = !!(r[2] & BIT(13)); e->port = (r[2] >> 19) & 0x3ff; - // Check for trunk port + /* Check for trunk port */ if (r[2] & BIT(29)) { e->is_trunk = true; e->stack_dev = (e->port >> 9) & 1; @@ -675,7 +675,7 @@ static void rtl931x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e) e->suspended = !!(r[2] & BIT(12)); e->age = (r[2] >> 16) & 3; - // the UC_VID field in hardware is used for the VID or for the route id + /* the UC_VID field in hardware is used for the VID or for the route id */ if (e->next_hop) { e->nh_route_id = r[2] & 0x7ff; e->vid = 0; @@ -685,7 +685,7 @@ static void rtl931x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e) } if (e->is_l2_tunnel) e->l2_tunnel_id = ((r[2] & 0xff) << 4) | (r[3] >> 28); - // TODO: Implement VLAN conversion + /* TODO: Implement VLAN conversion */ } else { e->type = L2_MULTICAST; e->is_local_forward = !!(r[2] & BIT(31)); @@ -705,7 +705,7 @@ static void rtl931x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e) return; } - r[2] = BIT(31); // Set valid bit + r[2] = BIT(31); /* Set valid bit */ r[0] = ((u32)e->mac[0]) << 24 | ((u32)e->mac[1]) << 16 | @@ -732,12 +732,12 @@ static void rtl931x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e) r[2] |= e->block_sa ? BIT(17) : 0; r[2] |= e->suspended ? BIT(13) : 0; r[2] |= (e->age & 0x3) << 17; - // the UC_VID field in hardware is used for the VID or for the route id + /* the UC_VID field in hardware is used for the VID or for the route id */ if (e->next_hop) r[2] |= e->nh_route_id & 0x7ff; else r[2] |= e->vid & 0xfff; - } else { // L2_MULTICAST + } else { /* L2_MULTICAST */ r[2] |= (e->mc_portmask_index & 0x3ff) << 16; r[2] |= e->mc_mac_index & 0x7ff; } @@ -769,7 +769,7 @@ static u64 rtl931x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2 hash &= 0xffff; } - idx = (0 << 14) | (hash << 2) | pos; // Search SRAM, with hash and at pos in bucket + idx = (0 << 14) | (hash << 2) | pos; /* Search SRAM, with hash and at pos in bucket */ pr_debug("%s: NOW hash %08x, pos: %d\n", __func__, hash, pos); rtl_table_read(q, idx); @@ -794,7 +794,7 @@ static u64 rtl931x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2 seed = rtl931x_l2_hash_seed(mac, e->rvid); pr_debug("%s: mac %016llx, seed %016llx\n", __func__, mac, seed); - // return vid with concatenated mac as unique id + /* return vid with concatenated mac as unique id */ return seed; } @@ -811,7 +811,7 @@ static void rtl931x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_ { u32 r[4]; struct table_reg *q = rtl_table_get(RTL9310_TBL_0, 0); - u32 idx = (0 << 14) | (hash << 2) | pos; // Access SRAM, with hash and at pos in bucket + u32 idx = (0 << 14) | (hash << 2) | pos; /* Access SRAM, with hash and at pos in bucket */ int i; pr_info("%s: hash %d, pos %d\n", __func__, hash, pos); @@ -830,7 +830,7 @@ static void rtl931x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_ static void rtl931x_vlan_fwd_on_inner(int port, bool is_set) { - // Always set all tag modes to fwd based on either inner or outer tag + /* Always set all tag modes to fwd based on either inner or outer tag */ if (is_set) sw_w32_mask(0, 0xf, RTL931X_VLAN_PORT_FWD + (port << 2)); else @@ -849,15 +849,15 @@ static void rtl931x_vlan_profile_setup(int profile) p[0] = sw_r32(RTL931X_VLAN_PROFILE_SET(profile)); - // Enable routing of Ipv4/6 Unicast and IPv4/6 Multicast traffic - //p[0] |= BIT(17) | BIT(16) | BIT(13) | BIT(12); - p[0] |= 0x3 << 11; // COPY2CPU + /* Enable routing of Ipv4/6 Unicast and IPv4/6 Multicast traffic */ + /* p[0] |= BIT(17) | BIT(16) | BIT(13) | BIT(12); */ + p[0] |= 0x3 << 11; /* COPY2CPU */ - p[1] = 0x1FFFFFF; // L2 unknwon MC flooding portmask all ports, including the CPU-port + p[1] = 0x1FFFFFF; /* L2 unknwon MC flooding portmask all ports, including the CPU-port */ p[2] = 0xFFFFFFFF; - p[3] = 0x1FFFFFF; // IPv4 unknwon MC flooding portmask + p[3] = 0x1FFFFFF; /* IPv4 unknwon MC flooding portmask */ p[4] = 0xFFFFFFFF; - p[5] = 0x1FFFFFF; // IPv6 unknwon MC flooding portmask + p[5] = 0x1FFFFFF; /* IPv6 unknwon MC flooding portmask */ p[6] = 0xFFFFFFFF; for (int i = 0; i < 7; i++) @@ -867,20 +867,20 @@ static void rtl931x_vlan_profile_setup(int profile) static void rtl931x_l2_learning_setup(void) { - // Portmask for flooding broadcast traffic + /* Portmask for flooding broadcast traffic */ rtl839x_set_port_reg_be(0x1FFFFFFFFFFFFFF, RTL931X_L2_BC_FLD_PMSK); - // Portmask for flooding unicast traffic with unknown destination + /* Portmask for flooding unicast traffic with unknown destination */ rtl839x_set_port_reg_be(0x1FFFFFFFFFFFFFF, RTL931X_L2_UNKN_UC_FLD_PMSK); - // Limit learning to maximum: 64k entries, after that just flood (bits 0-2) + /* Limit learning to maximum: 64k entries, after that just flood (bits 0-2) */ sw_w32((0xffff << 3) | FORWARD, RTL931X_L2_LRN_CONSTRT_CTRL); } static u64 rtl931x_read_mcast_pmask(int idx) { u64 portmask; - // Read MC_PMSK (2) via register RTL9310_TBL_0 + /* Read MC_PMSK (2) via register RTL9310_TBL_0 */ struct table_reg *q = rtl_table_get(RTL9310_TBL_0, 2); rtl_table_read(q, idx); @@ -899,7 +899,7 @@ static void rtl931x_write_mcast_pmask(int idx, u64 portmask) { u64 pm = portmask; - // Access MC_PMSK (2) via register RTL9310_TBL_0 + /* Access MC_PMSK (2) via register RTL9310_TBL_0 */ struct table_reg *q = rtl_table_get(RTL9310_TBL_0, 2); pr_debug("%s: Index idx %d has portmask %016llx\n", __func__, idx, pm); @@ -928,7 +928,7 @@ static int rtl931x_set_ageing_time(unsigned long msec) } void rtl931x_sw_init(struct rtl838x_switch_priv *priv) { -// rtl931x_sds_init(priv); +/* rtl931x_sds_init(priv); */ } static void rtl931x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int index) @@ -1109,7 +1109,7 @@ static void rtl931x_write_pie_templated(u32 r[], struct pie_rule *pr, enum templ for (i = 0; i < N_FIXED_FIELDS; i++) { rtl931x_pie_data_fill(t[i], pr, &data, &data_m); - // On the RTL9300, the mask fields are not word aligned! + /* On the RTL9300, the mask fields are not word aligned! */ if (!(i % 2)) { r[5 - i / 2] = data; r[12 - i / 2] |= ((u32)data_m << 8); @@ -1126,7 +1126,7 @@ static void rtl931x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr) pr->mgnt_vlan = r[7] & BIT(31); if (pr->phase == PHASE_IACL) pr->dmac_hit_sw = r[7] & BIT(30); - else // TODO: EACL/VACL phase handling + else /* TODO: EACL/VACL phase handling */ pr->content_too_deep = r[7] & BIT(30); pr->not_first_frag = r[7] & BIT(29); pr->frame_type_l4 = (r[7] >> 26) & 7; @@ -1203,15 +1203,15 @@ static void rtl931x_write_pie_fixed_fields(u32 r[], struct pie_rule *pr) static void rtl931x_write_pie_action(u32 r[], struct pie_rule *pr) { - // Either drop or forward + /* Either drop or forward */ if (pr->drop) { - r[15] |= BIT(11) | BIT(12) | BIT(13); // Do Green, Yellow and Red drops - // Actually DROP, not PERMIT in Green / Yellow / Red + r[15] |= BIT(11) | BIT(12) | BIT(13); /* Do Green, Yellow and Red drops */ + /* Actually DROP, not PERMIT in Green / Yellow / Red */ r[16] |= BIT(27) | BIT(28) | BIT(29); } else { r[15] |= pr->fwd_sel ? BIT(14) : 0; r[16] |= pr->fwd_act << 24; - r[16] |= BIT(21); // We overwrite any drop + r[16] |= BIT(21); /* We overwrite any drop */ } if (pr->phase == PHASE_VACL) r[16] |= pr->fwd_sa_lrn ? BIT(22) : 0; @@ -1225,7 +1225,7 @@ static void rtl931x_write_pie_action(u32 r[], struct pie_rule *pr) r[15] |= pr->log_sel ? BIT(26) : 0; r[16] |= ((u32)(pr->fwd_data & 0xfff)) << 9; -// r[15] |= pr->log_octets ? BIT(31) : 0; +/* r[15] |= pr->log_octets ? BIT(31) : 0; */ r[15] |= (u32)(pr->meter_data) >> 2; r[16] |= (((u32)(pr->meter_data) >> 7) & 0x3) << 29; @@ -1261,7 +1261,7 @@ void rtl931x_pie_rule_dump_raw(u32 r[]) static int rtl931x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr) { - // Access IACL table (0) via register 1, the table size is 4096 + /* Access IACL table (0) via register 1, the table size is 4096 */ struct table_reg *q = rtl_table_get(RTL9310_TBL_1, 0); u32 r[22]; int i; @@ -1346,7 +1346,7 @@ static int rtl931x_pie_verify_template(struct rtl838x_switch_priv *priv, if (ether_addr_to_u64(pr->dmac) && !rtl931x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0)) return -1; - // TODO: Check more + /* TODO: Check more */ i = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE); @@ -1393,7 +1393,7 @@ static int rtl931x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rul set_bit(idx, priv->pie_use_bm); pr->valid = true; - pr->tid = j; // Mapped to template number + pr->tid = j; /* Mapped to template number */ pr->tid_m = 0x1; pr->id = idx; @@ -1413,10 +1413,10 @@ static int rtl931x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from pr_info("%s: from %d to %d\n", __func__, index_from, index_to); mutex_lock(&priv->reg_mutex); - // Write from-to and execute bit into control register + /* Write from-to and execute bit into control register */ sw_w32(v, RTL931X_PIE_CLR_CTRL); - // Wait until command has completed + /* Wait until command has completed */ do { } while (sw_r32(RTL931X_PIE_CLR_CTRL) & BIT(0)); @@ -1441,21 +1441,21 @@ static void rtl931x_pie_init(struct rtl838x_switch_priv *priv) mutex_init(&priv->pie_mutex); pr_info("%s\n", __func__); - // Enable ACL lookup on all ports, including CPU_PORT + /* Enable ACL lookup on all ports, including CPU_PORT */ for (i = 0; i <= priv->cpu_port; i++) sw_w32(1, RTL931X_ACL_PORT_LOOKUP_CTRL(i)); - // Include IPG in metering + /* Include IPG in metering */ sw_w32_mask(0, 1, RTL931X_METER_GLB_CTRL); - // Delete all present rules, block size is 128 on all SoC families + /* Delete all present rules, block size is 128 on all SoC families */ rtl931x_pie_rule_del(priv, 0, priv->n_pie_blocks * 128 - 1); - // Assign first half blocks 0-7 to VACL phase, second half to IACL - // 3 bits are used for each block, values for PIE blocks are - // 6: Disabled, 0: VACL, 1: IACL, 2: EACL - // And for OpenFlow Flow blocks: 3: Ingress Flow table 0, - // 4: Ingress Flow Table 3, 5: Egress flow table 0 + /* Assign first half blocks 0-7 to VACL phase, second half to IACL */ + /* 3 bits are used for each block, values for PIE blocks are */ + /* 6: Disabled, 0: VACL, 1: IACL, 2: EACL */ + /* And for OpenFlow Flow blocks: 3: Ingress Flow table 0, */ + /* 4: Ingress Flow Table 3, 5: Egress flow table 0 */ for (i = 0; i < priv->n_pie_blocks; i++) { int pos = (i % 10) * 3; u32 r = RTL931X_PIE_BLK_PHASE_CTRL + 4 * (i / 10); @@ -1466,22 +1466,22 @@ static void rtl931x_pie_init(struct rtl838x_switch_priv *priv) sw_w32_mask(0x7 << pos, 1 << pos, r); } - // Enable predefined templates 0, 1 for first quarter of all blocks + /* Enable predefined templates 0, 1 for first quarter of all blocks */ template_selectors = 0 | (1 << 4); for (i = 0; i < priv->n_pie_blocks / 4; i++) sw_w32(template_selectors, RTL931X_PIE_BLK_TMPLTE_CTRL(i)); - // Enable predefined templates 2, 3 for second quarter of all blocks + /* Enable predefined templates 2, 3 for second quarter of all blocks */ template_selectors = 2 | (3 << 4); for (i = priv->n_pie_blocks / 4; i < priv->n_pie_blocks / 2; i++) sw_w32(template_selectors, RTL931X_PIE_BLK_TMPLTE_CTRL(i)); - // Enable predefined templates 0, 1 for third quater of all blocks + /* Enable predefined templates 0, 1 for third quater of all blocks */ template_selectors = 0 | (1 << 4); for (i = priv->n_pie_blocks / 2; i < priv->n_pie_blocks * 3 / 4; i++) sw_w32(template_selectors, RTL931X_PIE_BLK_TMPLTE_CTRL(i)); - // Enable predefined templates 2, 3 for fourth quater of all blocks + /* Enable predefined templates 2, 3 for fourth quater of all blocks */ template_selectors = 2 | (3 << 4); for (i = priv->n_pie_blocks * 3 / 4; i < priv->n_pie_blocks; i++) sw_w32(template_selectors, RTL931X_PIE_BLK_TMPLTE_CTRL(i)); @@ -1595,7 +1595,7 @@ static void rtl931x_led_init(struct rtl838x_switch_priv *priv) if (!priv->ports[i].phy) continue; - v = 0x1; // Found on the EdgeCore, but we do not have any HW description + v = 0x1; /* Found on the EdgeCore, but we do not have any HW description */ sw_w32_mask(0x3 << pos, v << pos, RTL931X_LED_PORT_NUM_CTRL(i)); if (priv->ports[i].phy_is_integrated) @@ -1620,7 +1620,7 @@ static void rtl931x_led_init(struct rtl838x_switch_priv *priv) sw_w32(v, RTL931X_LED_SET0_0_CTRL - i * 8); } - // Set LED mode to serial (0x1) + /* Set LED mode to serial (0x1) */ sw_w32_mask(0x3, 0x1, RTL931X_LED_GLB_CTRL); rtl839x_set_port_reg_le(pm_copper, RTL931X_LED_PORT_COPR_MASK_CTRL); @@ -1640,7 +1640,7 @@ const struct rtl838x_reg rtl931x_reg = { .get_port_reg_le = rtl839x_get_port_reg_le, .stat_port_rst = RTL931X_STAT_PORT_RST, .stat_rst = RTL931X_STAT_RST, - .stat_port_std_mib = 0, // Not defined + .stat_port_std_mib = 0, /* Not defined */ .traffic_enable = rtl931x_traffic_enable, .traffic_disable = rtl931x_traffic_disable, .traffic_get = rtl931x_traffic_get, @@ -1649,7 +1649,7 @@ const struct rtl838x_reg rtl931x_reg = { .l2_ctrl_1 = RTL931X_L2_AGE_CTRL, .l2_port_aging_out = RTL931X_L2_PORT_AGE_CTRL, .set_ageing_time = rtl931x_set_ageing_time, - // .smi_poll_ctrl does not exist + /* .smi_poll_ctrl does not exist */ .l2_tbl_flush_ctrl = RTL931X_L2_TBL_FLUSH_CTRL, .exec_tbl0_cmd = rtl931x_exec_tbl0_cmd, .exec_tbl1_cmd = rtl931x_exec_tbl1_cmd, @@ -1657,7 +1657,7 @@ const struct rtl838x_reg rtl931x_reg = { .isr_glb_src = RTL931X_ISR_GLB_SRC, .isr_port_link_sts_chg = RTL931X_ISR_PORT_LINK_STS_CHG, .imr_port_link_sts_chg = RTL931X_IMR_PORT_LINK_STS_CHG, - // imr_glb does not exist on RTL931X + /* imr_glb does not exist on RTL931X */ .vlan_tables_read = rtl931x_vlan_tables_read, .vlan_set_tagged = rtl931x_vlan_set_tagged, .vlan_set_untagged = rtl931x_vlan_set_untagged, diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/tc.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/tc.c index 401fb4553c5..2c2175922c2 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/tc.c +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/tc.c @@ -69,7 +69,7 @@ static int rtl83xx_parse_flow_rule(struct rtl838x_switch_priv *priv, flow_rule_match_vlan(rule, &match); flow->rule.itag = match.key->vlan_id; flow->rule.itag_m = match.mask->vlan_id; - // TODO: What about match.key->vlan_priority ? + /* TODO: What about match.key->vlan_priority? */ } if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IPV4_ADDRS)) { @@ -105,7 +105,7 @@ static int rtl83xx_parse_flow_rule(struct rtl838x_switch_priv *priv, flow->rule.sport_m = match.mask->src; } - // TODO: ICMP + /* TODO: ICMP */ return 0; } @@ -173,7 +173,7 @@ static int rtl83xx_add_flow(struct rtl838x_switch_priv *priv, struct flow_cls_of case FLOW_ACTION_VLAN_PUSH: pr_debug("%s: VLAN_PUSH\n", __func__); -// TODO: act->vlan.proto +/* TODO: act->vlan.proto */ flow->rule.ivid_act = PIE_ACT_VID_ASSIGN; flow->rule.ivid_sel = true; flow->rule.ivid_data = htons(act->vlan.vid); @@ -268,9 +268,9 @@ rcu_unlock: goto out_free; } - rtl83xx_add_flow(priv, f, flow); // TODO: check error + rtl83xx_add_flow(priv, f, flow); /* TODO: check error */ - // Add log action to flow + /* Add log action to flow */ flow->rule.packet_cntr = rtl83xx_packet_cntr_alloc(priv); if (flow->rule.packet_cntr >= 0) { pr_debug("Using packet counter %d\n", flow->rule.packet_cntr); @@ -332,7 +332,7 @@ static int rtl83xx_stats_flower(struct rtl838x_switch_priv *priv, flow->rule.last_packet_cnt = total_packets; } - // TODO: We need a second PIE rule to count the bytes + /* TODO: We need a second PIE rule to count the bytes */ flow_stats_update(&cls_flower->stats, 100 * new_packets, new_packets, 0, lastused, FLOW_ACTION_HW_STATS_IMMEDIATE); diff --git a/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.c b/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.c index 6cd649db541..af4a54cf89e 100644 --- a/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.c +++ b/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.c @@ -93,9 +93,9 @@ struct notify_b { static void rtl838x_create_tx_header(struct p_hdr *h, unsigned int dest_port, int prio) { - // cpu_tag[0] is reserved on the RTL83XX SoCs - h->cpu_tag[1] = 0x0400; // BIT 10: RTL8380_CPU_TAG - h->cpu_tag[2] = 0x0200; // Set only AS_DPM, to enable DPM settings below + /* cpu_tag[0] is reserved on the RTL83XX SoCs */ + h->cpu_tag[1] = 0x0400; /* BIT 10: RTL8380_CPU_TAG */ + h->cpu_tag[2] = 0x0200; /* Set only AS_DPM, to enable DPM settings below */ h->cpu_tag[3] = 0x0000; h->cpu_tag[4] = BIT(dest_port) >> 16; h->cpu_tag[5] = BIT(dest_port) & 0xffff; @@ -107,11 +107,11 @@ static void rtl838x_create_tx_header(struct p_hdr *h, unsigned int dest_port, in static void rtl839x_create_tx_header(struct p_hdr *h, unsigned int dest_port, int prio) { - // cpu_tag[0] is reserved on the RTL83XX SoCs - h->cpu_tag[1] = 0x0100; // RTL8390_CPU_TAG marker + /* cpu_tag[0] is reserved on the RTL83XX SoCs */ + h->cpu_tag[1] = 0x0100; /* RTL8390_CPU_TAG marker */ h->cpu_tag[2] = BIT(4); /* AS_DPM flag */ h->cpu_tag[3] = h->cpu_tag[4] = h->cpu_tag[5] = 0; - // h->cpu_tag[1] |= BIT(1) | BIT(0); // Bypass filter 1/2 + /* h->cpu_tag[1] |= BIT(1) | BIT(0); */ /* Bypass filter 1/2 */ if (dest_port >= 32) { dest_port -= 32; h->cpu_tag[2] |= (BIT(dest_port) >> 16) & 0xf; @@ -128,7 +128,7 @@ static void rtl839x_create_tx_header(struct p_hdr *h, unsigned int dest_port, in static void rtl930x_create_tx_header(struct p_hdr *h, unsigned int dest_port, int prio) { - h->cpu_tag[0] = 0x8000; // CPU tag marker + h->cpu_tag[0] = 0x8000; /* CPU tag marker */ h->cpu_tag[1] = h->cpu_tag[2] = 0; h->cpu_tag[3] = 0; h->cpu_tag[4] = 0; @@ -143,7 +143,7 @@ static void rtl930x_create_tx_header(struct p_hdr *h, unsigned int dest_port, in static void rtl931x_create_tx_header(struct p_hdr *h, unsigned int dest_port, int prio) { - h->cpu_tag[0] = 0x8000; // CPU tag marker + h->cpu_tag[0] = 0x8000; /* CPU tag marker */ h->cpu_tag[1] = h->cpu_tag[2] = 0; h->cpu_tag[3] = 0; h->cpu_tag[4] = h->cpu_tag[5] = h->cpu_tag[6] = h->cpu_tag[7] = 0; @@ -163,7 +163,7 @@ static void rtl931x_create_tx_header(struct p_hdr *h, unsigned int dest_port, in static void rtl93xx_header_vlan_set(struct p_hdr *h, int vlan) { - h->cpu_tag[2] |= BIT(4); // Enable VLAN forwarding offload + h->cpu_tag[2] |= BIT(4); /* Enable VLAN forwarding offload */ h->cpu_tag[2] |= (vlan >> 8) & 0xf; h->cpu_tag[3] |= (vlan & 0xff) << 8; } @@ -218,12 +218,12 @@ extern int rtl931x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val); */ void rtl838x_update_cntr(int r, int released) { - // This feature is not available on RTL838x SoCs + /* This feature is not available on RTL838x SoCs */ } void rtl839x_update_cntr(int r, int released) { - // This feature is not available on RTL839x SoCs + /* This feature is not available on RTL839x SoCs */ } void rtl930x_update_cntr(int r, int released) @@ -267,7 +267,7 @@ bool rtl838x_decode_tag(struct p_hdr *h, struct dsa_tag *t) t->crc_error = t->reason == 13; pr_debug("Reason: %d\n", t->reason); - if (t->reason != 6) // NIC_RX_REASON_SPECIAL_TRAP + if (t->reason != 6) /* NIC_RX_REASON_SPECIAL_TRAP */ t->l2_offloaded = 1; else t->l2_offloaded = 0; @@ -284,8 +284,8 @@ bool rtl839x_decode_tag(struct p_hdr *h, struct dsa_tag *t) t->crc_error = h->cpu_tag[4] & BIT(6); pr_debug("Reason: %d\n", t->reason); - if ((t->reason >= 7 && t->reason <= 13) || // NIC_RX_REASON_RMA - (t->reason >= 23 && t->reason <= 25)) // NIC_RX_REASON_SPECIAL_TRAP + if ((t->reason >= 7 && t->reason <= 13) || /* NIC_RX_REASON_RMA */ + (t->reason >= 23 && t->reason <= 25)) /* NIC_RX_REASON_SPECIAL_TRAP */ t->l2_offloaded = 0; else t->l2_offloaded = 1; @@ -318,7 +318,7 @@ bool rtl931x_decode_tag(struct p_hdr *h, struct dsa_tag *t) if (t->reason != 63) pr_info("%s: Reason %d, port %d, queue %d\n", __func__, t->reason, t->port, t->queue); - if (t->reason >= 19 && t->reason <= 27) // NIC_RX_REASON_RMA + if (t->reason >= 19 && t->reason <= 27) /* NIC_RX_REASON_RMA */ t->l2_offloaded = 0; else t->l2_offloaded = 1; @@ -688,7 +688,7 @@ static void rtl838x_hw_reset(struct rtl838x_eth_priv *priv) /* Setup Head of Line */ if (priv->family_id == RTL8380_FAMILY_ID) - sw_w32(0, RTL838X_DMA_IF_RX_RING_SIZE); // Disabled on RTL8380 + sw_w32(0, RTL838X_DMA_IF_RX_RING_SIZE); /* Disabled on RTL8380 */ if (priv->family_id == RTL8390_FAMILY_ID) sw_w32(0xffffffff, RTL839X_DMA_IF_RX_RING_CNTR); if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) { @@ -758,7 +758,7 @@ static void rtl839x_hw_en_rxtx(struct rtl838x_eth_priv *priv) sw_w32(0x0000c808, priv->r->dma_if_ctrl); /* Enable Notify, RX done, RX overflow and TX done interrupts */ - sw_w32(0x007fffff, priv->r->dma_if_intr_msk); // Notify IRQ! + sw_w32(0x007fffff, priv->r->dma_if_intr_msk); /* Notify IRQ! */ /* Enable DMA */ sw_w32_mask(0, RX_EN | TX_EN, priv->r->dma_if_ctrl); @@ -767,7 +767,7 @@ static void rtl839x_hw_en_rxtx(struct rtl838x_eth_priv *priv) sw_w32_mask(0x0, 0x3 | BIT(3), priv->r->mac_port_ctrl(priv->cpu_port)); /* CPU port joins Lookup Miss Flooding Portmask */ - // TODO: The code below should also work for the RTL838x + /* TODO: The code below should also work for the RTL838x */ sw_w32(0x28000, RTL839X_TBL_ACCESS_L2_CTRL); sw_w32_mask(0, 0x80000000, RTL839X_TBL_ACCESS_L2_DATA(0)); sw_w32(0x38000, RTL839X_TBL_ACCESS_L2_CTRL); @@ -788,7 +788,7 @@ static void rtl93xx_hw_en_rxtx(struct rtl838x_eth_priv *priv) pos = (i % 3) * 10; sw_w32_mask(0x3ff << pos, priv->rxringlen << pos, priv->r->dma_if_rx_ring_size(i)); - // Some SoCs have issues with missing underflow protection + /* Some SoCs have issues with missing underflow protection */ v = (sw_r32(priv->r->dma_if_rx_ring_cntr(i)) >> pos) & 0x3ff; sw_w32_mask(0x3ff << pos, v, priv->r->dma_if_rx_ring_cntr(i)); } @@ -864,8 +864,8 @@ static void rtl839x_setup_notify_ring_buffer(struct rtl838x_eth_priv *priv) sw_w32_mask(0x3ff << 2, 100 << 2, RTL839X_L2_NOTIFICATION_CTRL); /* Setup notification events */ - sw_w32_mask(0, 1 << 14, RTL839X_L2_CTRL_0); // RTL8390_L2_CTRL_0_FLUSH_NOTIFY_EN - sw_w32_mask(0, 1 << 12, RTL839X_L2_NOTIFICATION_CTRL); // SUSPEND_NOTIFICATION_EN + sw_w32_mask(0, 1 << 14, RTL839X_L2_CTRL_0); /* RTL8390_L2_CTRL_0_FLUSH_NOTIFY_EN */ + sw_w32_mask(0, 1 << 12, RTL839X_L2_NOTIFICATION_CTRL); /* SUSPEND_NOTIFICATION_EN /* Enable Notification */ sw_w32_mask(0, 1 << 0, RTL839X_L2_NOTIFICATION_CTRL); @@ -909,7 +909,7 @@ static int rtl838x_eth_open(struct net_device *ndev) case RTL8390_FAMILY_ID: rtl839x_hw_en_rxtx(priv); - // Trap MLD and IGMP messages to CPU_PORT + /* Trap MLD and IGMP messages to CPU_PORT */ sw_w32(0x3, RTL839X_SPCL_TRAP_IGMP_CTRL); /* Flush learned FDB entries on link down of a port */ sw_w32_mask(0, BIT(7), RTL839X_L2_CTRL_0); @@ -919,20 +919,20 @@ static int rtl838x_eth_open(struct net_device *ndev) rtl93xx_hw_en_rxtx(priv); /* Flush learned FDB entries on link down of a port */ sw_w32_mask(0, BIT(7), RTL930X_L2_CTRL); - // Trap MLD and IGMP messages to CPU_PORT + /* Trap MLD and IGMP messages to CPU_PORT */ sw_w32((0x2 << 3) | 0x2, RTL930X_VLAN_APP_PKT_CTRL); break; case RTL9310_FAMILY_ID: rtl93xx_hw_en_rxtx(priv); - // Trap MLD and IGMP messages to CPU_PORT + /* Trap MLD and IGMP messages to CPU_PORT */ sw_w32((0x2 << 3) | 0x2, RTL931X_VLAN_APP_PKT_CTRL); - // Disable External CPU access to switch, clear EXT_CPU_EN + /* Disable External CPU access to switch, clear EXT_CPU_EN */ sw_w32_mask(BIT(2), 0, RTL931X_MAC_L2_GLOBAL_CTRL2); - // Set PCIE_PWR_DOWN + /* Set PCIE_PWR_DOWN */ sw_w32_mask(0, BIT(1), RTL931X_PS_SOC_CTRL); break; } @@ -950,7 +950,7 @@ static void rtl838x_hw_stop(struct rtl838x_eth_priv *priv) u32 clear_irq = priv->family_id == RTL8380_FAMILY_ID ? 0x000fffff : 0x007fffff; int i; - // Disable RX/TX from/to CPU-port + /* Disable RX/TX from/to CPU-port */ sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(priv->cpu_port)); /* Disable traffic */ @@ -958,7 +958,7 @@ static void rtl838x_hw_stop(struct rtl838x_eth_priv *priv) sw_w32_mask(RX_EN_93XX | TX_EN_93XX, 0, priv->r->dma_if_ctrl); else sw_w32_mask(RX_EN | TX_EN, 0, priv->r->dma_if_ctrl); - mdelay(200); // Test, whether this is needed + mdelay(200); /* Test, whether this is needed */ /* Block all ports */ if (priv->family_id == RTL8380_FAMILY_ID) { @@ -979,7 +979,7 @@ static void rtl838x_hw_stop(struct rtl838x_eth_priv *priv) do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 28)); } } - // TODO: L2 flush register is 64 bit on RTL931X and 930X + /* TODO: L2 flush register is 64 bit on RTL931X and 930X */ /* CPU-Port: Link down */ if (priv->family_id == RTL8380_FAMILY_ID || priv->family_id == RTL8390_FAMILY_ID) @@ -1133,7 +1133,7 @@ static int rtl838x_eth_tx(struct sk_buff *skb, struct net_device *dev) int dest_port = -1; int q = skb_get_queue_mapping(skb) % TXRINGS; - if (q) // Check for high prio queue + if (q) /* Check for high prio queue */ pr_debug("SKB priority: %d\n", skb->priority); spin_lock_irqsave(&priv->lock, flags); @@ -1151,7 +1151,7 @@ static int rtl838x_eth_tx(struct sk_buff *skb, struct net_device *dev) len -= 4; } - len += 4; // Add space for CRC + len += 4; /* Add space for CRC */ if (skb_padto(skb, len)) { ret = NETDEV_TX_OK; @@ -1165,7 +1165,7 @@ static int rtl838x_eth_tx(struct sk_buff *skb, struct net_device *dev) h = &ring->tx_header[q][ring->c_tx[q]]; h->size = len; h->len = len; - // On RTL8380 SoCs, small packet lengths being sent need adjustments + /* On RTL8380 SoCs, small packet lengths being sent need adjustments */ if (priv->family_id == RTL8380_FAMILY_ID) { if (len < ETH_ZLEN - 4) h->len -= 4; @@ -1182,7 +1182,7 @@ static int rtl838x_eth_tx(struct sk_buff *skb, struct net_device *dev) /* Hand over to switch */ ring->tx_r[q][ring->c_tx[q]] |= 1; - // Before starting TX, prevent a Lextra bus bug on RTL8380 SoCs + /* Before starting TX, prevent a Lextra bus bug on RTL8380 SoCs */ if (priv->family_id == RTL8380_FAMILY_ID) { for (i = 0; i < 10; i++) { val = sw_r32(priv->r->dma_if_ctrl); @@ -1193,7 +1193,7 @@ static int rtl838x_eth_tx(struct sk_buff *skb, struct net_device *dev) /* Tell switch to send data */ if (priv->family_id == RTL9310_FAMILY_ID || priv->family_id == RTL9300_FAMILY_ID) { - // Ring ID q == 0: Low priority, Ring ID = 1: High prio queue + /* Ring ID q == 0: Low priority, Ring ID = 1: High prio queue */ if (!q) sw_w32_mask(0, BIT(2), priv->r->dma_if_ctrl); else @@ -1345,7 +1345,7 @@ static int rtl838x_hw_receive(struct net_device *dev, int r, int budget) netif_receive_skb_list(&rx_list); - // Update counters + /* Update counters */ priv->r->update_cntr(r, 0); spin_unlock_irqrestore(&priv->lock, flags); @@ -1570,7 +1570,7 @@ static int rtl838x_set_mac_address(struct net_device *dev, void *p) static int rtl8390_init_mac(struct rtl838x_eth_priv *priv) { - // We will need to set-up EEE and the egress-rate limitation + /* We will need to set-up EEE and the egress-rate limitation */ return 0; } @@ -1889,7 +1889,7 @@ static int rtl838x_mdio_reset(struct mii_bus *bus) /* Enable PHY control via SoC */ sw_w32_mask(0, 1 << 15, RTL838X_SMI_GLB_CTRL); - // Probably should reset all PHYs here... + /* Probably should reset all PHYs here... */ return 0; } @@ -1905,7 +1905,7 @@ static int rtl839x_mdio_reset(struct mii_bus *bus) /* Disable PHY polling via SoC */ sw_w32_mask(1 << 7, 0, RTL839X_SMI_GLB_CTRL); - // Probably should reset all PHYs here... + /* Probably should reset all PHYs here... */ return 0; } @@ -1922,10 +1922,10 @@ static int rtl930x_mdio_reset(struct mii_bus *bus) u32 poll_ctrl = 0; u32 private_poll_mask = 0; u32 v; - bool uses_usxgmii = false; // For the Aquantia PHYs - bool uses_hisgmii = false; // For the RTL8221/8226 + bool uses_usxgmii = false; /* For the Aquantia PHYs */ + bool uses_hisgmii = false; /* For the RTL8221/8226 */ - // Mapping of port to phy-addresses on an SMI bus + /* Mapping of port to phy-addresses on an SMI bus */ poll_sel[0] = poll_sel[1] = 0; for (i = 0; i < RTL930X_CPU_PORT; i++) { if (priv->smi_bus[i] > 3) @@ -1939,14 +1939,14 @@ static int rtl930x_mdio_reset(struct mii_bus *bus) poll_ctrl |= BIT(20 + priv->smi_bus[i]); } - // Configure which SMI bus is behind which port number + /* Configure which SMI bus is behind which port number */ sw_w32(poll_sel[0], RTL930X_SMI_PORT0_15_POLLING_SEL); sw_w32(poll_sel[1], RTL930X_SMI_PORT16_27_POLLING_SEL); - // Disable POLL_SEL for any SMI bus with a normal PHY (not RTL8295R for SFP+) + /* Disable POLL_SEL for any SMI bus with a normal PHY (not RTL8295R for SFP+) */ sw_w32_mask(poll_ctrl, 0, RTL930X_SMI_GLB_CTRL); - // Configure which SMI busses are polled in c45 based on a c45 PHY being on that bus + /* Configure which SMI busses are polled in c45 based on a c45 PHY being on that bus */ for (i = 0; i < 4; i++) if (priv->smi_bus_isc45[i]) c45_mask |= BIT(i + 16); @@ -1954,16 +1954,16 @@ static int rtl930x_mdio_reset(struct mii_bus *bus) pr_info("c45_mask: %08x\n", c45_mask); sw_w32_mask(0, c45_mask, RTL930X_SMI_GLB_CTRL); - // Set the MAC type of each port according to the PHY-interface - // Values are FE: 2, GE: 3, XGE/2.5G: 0(SERDES) or 1(otherwise), SXGE: 0 + /* Set the MAC type of each port according to the PHY-interface */ + /* Values are FE: 2, GE: 3, XGE/2.5G: 0(SERDES) or 1(otherwise), SXGE: 0 */ v = 0; for (i = 0; i < RTL930X_CPU_PORT; i++) { switch (priv->interfaces[i]) { case PHY_INTERFACE_MODE_10GBASER: - break; // Serdes: Value = 0 + break; /* Serdes: Value = 0 */ case PHY_INTERFACE_MODE_HSGMII: private_poll_mask |= BIT(i); - // fallthrough + /* fallthrough */ case PHY_INTERFACE_MODE_USXGMII: v |= BIT(mac_type_bit[i]); uses_usxgmii = true; @@ -1978,7 +1978,7 @@ static int rtl930x_mdio_reset(struct mii_bus *bus) } sw_w32(v, RTL930X_SMI_MAC_TYPE_CTRL); - // Set the private polling mask for all Realtek PHYs (i.e. not the 10GBit Aquantia ones) + /* Set the private polling mask for all Realtek PHYs (i.e. not the 10GBit Aquantia ones) */ sw_w32(private_poll_mask, RTL930X_SMI_PRVTE_POLLING_CTRL); /* The following magic values are found in the port configuration, they seem to @@ -2027,13 +2027,13 @@ static int rtl931x_mdio_reset(struct mii_bus *bus) bool mdc_on[4]; pr_info("%s called\n", __func__); - // Disable port polling for configuration purposes + /* Disable port polling for configuration purposes */ sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL); sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4); msleep(100); mdc_on[0] = mdc_on[1] = mdc_on[2] = mdc_on[3] = false; - // Mapping of port to phy-addresses on an SMI bus + /* Mapping of port to phy-addresses on an SMI bus */ poll_sel[0] = poll_sel[1] = poll_sel[2] = poll_sel[3] = 0; for (i = 0; i < 56; i++) { pos = (i % 6) * 5; @@ -2044,20 +2044,20 @@ static int rtl931x_mdio_reset(struct mii_bus *bus) mdc_on[priv->smi_bus[i]] = true; } - // Configure which SMI bus is behind which port number + /* Configure which SMI bus is behind which port number */ for (i = 0; i < 4; i++) { pr_info("poll sel %d, %08x\n", i, poll_sel[i]); sw_w32(poll_sel[i], RTL931X_SMI_PORT_POLLING_SEL + (i * 4)); } - // Configure which SMI busses + /* Configure which SMI busses */ pr_info("%s: WAS RTL931X_MAC_L2_GLOBAL_CTRL2 %08x\n", __func__, sw_r32(RTL931X_MAC_L2_GLOBAL_CTRL2)); pr_info("c45_mask: %08x, RTL931X_SMI_GLB_CTRL0 was %X", c45_mask, sw_r32(RTL931X_SMI_GLB_CTRL0)); for (i = 0; i < 4; i++) { - // bus is polled in c45 + /* bus is polled in c45 */ if (priv->smi_bus_isc45[i]) - c45_mask |= 0x2 << (i * 2); // Std. C45, non-standard is 0x3 - // Enable bus access via MDC + c45_mask |= 0x2 << (i * 2); /* Std. C45, non-standard is 0x3 */ + /* Enable bus access via MDC */ if (mdc_on[i]) sw_w32_mask(0, BIT(9 + i), RTL931X_MAC_L2_GLOBAL_CTRL2); } @@ -2079,22 +2079,22 @@ static int rtl931x_chip_init(struct rtl838x_eth_priv *priv) { pr_info("In %s\n", __func__); - // Initialize Encapsulation memory and wait until finished + /* Initialize Encapsulation memory and wait until finished */ sw_w32(0x1, RTL931X_MEM_ENCAP_INIT); do { } while (sw_r32(RTL931X_MEM_ENCAP_INIT) & 1); pr_info("%s: init ENCAP done\n", __func__); - // Initialize Managemen Information Base memory and wait until finished + /* Initialize Managemen Information Base memory and wait until finished */ sw_w32(0x1, RTL931X_MEM_MIB_INIT); do { } while (sw_r32(RTL931X_MEM_MIB_INIT) & 1); pr_info("%s: init MIB done\n", __func__); - // Initialize ACL (PIE) memory and wait until finished + /* Initialize ACL (PIE) memory and wait until finished */ sw_w32(0x1, RTL931X_MEM_ACL_INIT); do { } while (sw_r32(RTL931X_MEM_ACL_INIT) & 1); pr_info("%s: init ACL done\n", __func__); - // Initialize ALE memory and wait until finished + /* Initialize ALE memory and wait until finished */ sw_w32(0xFFFFFFFF, RTL931X_MEM_ALE_INIT_0); do { } while (sw_r32(RTL931X_MEM_ALE_INIT_0)); sw_w32(0x7F, RTL931X_MEM_ALE_INIT_1); @@ -2102,10 +2102,10 @@ static int rtl931x_chip_init(struct rtl838x_eth_priv *priv) do { } while (sw_r32(RTL931X_MEM_ALE_INIT_2) & 0x7ff); pr_info("%s: init ALE done\n", __func__); - // Enable ESD auto recovery + /* Enable ESD auto recovery */ sw_w32(0x1, RTL931X_MDX_CTRL_RSVD); - // Init SPI, is this for thermal control or what? + /* Init SPI, is this for thermal control or what? */ sw_w32_mask(0x7 << 11, 0x2 << 11, RTL931X_SPI_CTRL0); return 0; @@ -2411,7 +2411,7 @@ static int __init rtl838x_eth_probe(struct platform_device *pdev) goto err_free; } - // Allocate ring-buffer space at the end of the allocated memory + /* Allocate ring-buffer space at the end of the allocated memory */ ring = priv->membase; ring->rx_space = priv->membase + sizeof(struct ring_b) + sizeof(struct notify_b); diff --git a/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.h b/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.h index fbd2bcadd6d..7a5ff678a4c 100644 --- a/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.h +++ b/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.h @@ -116,7 +116,7 @@ #define RTL930X_MAC_LINK_DUP_STS (0xCB28) #define RTL931X_MAC_LINK_DUP_STS (0x0ef0) -// TODO: RTL8390_MAC_LINK_MEDIA_STS_ADDR ??? +/* TODO: RTL8390_MAC_LINK_MEDIA_STS_ADDR??? */ #define RTL838X_MAC_TX_PAUSE_STS (0xa1a0) #define RTL839X_MAC_TX_PAUSE_STS (0x03b8) diff --git a/target/linux/realtek/files-5.15/drivers/net/phy/rtl83xx-phy.c b/target/linux/realtek/files-5.15/drivers/net/phy/rtl83xx-phy.c index 38012d75d0e..ce83847c6dc 100644 --- a/target/linux/realtek/files-5.15/drivers/net/phy/rtl83xx-phy.c +++ b/target/linux/realtek/files-5.15/drivers/net/phy/rtl83xx-phy.c @@ -143,7 +143,7 @@ static void rtl8380_phy_reset(struct phy_device *phydev) phy_modify(phydev, 0, BIT(15), BIT(15)); } -// The access registers for SDS_MODE_SEL and the LSB for each SDS within +/* The access registers for SDS_MODE_SEL and the LSB for each SDS within */ u16 rtl9300_sds_regs[] = { 0x0194, 0x0194, 0x0194, 0x0194, 0x02a0, 0x02a0, 0x02a0, 0x02a0, 0x02A4, 0x02A4, 0x0198, 0x0198 }; u8 rtl9300_sds_lsb[] = { 0, 6, 12, 18, 0, 6, 12, 18, 0, 6, 0, 6}; @@ -436,13 +436,14 @@ static int rtl8226_read_status(struct phy_device *phydev) int ret = 0, i; u32 val; -// TODO: ret = genphy_read_status(phydev); -// if (ret < 0) { -// pr_info("%s: genphy_read_status failed\n", __func__); -// return ret; -// } +/* TODO: ret = genphy_read_status(phydev); + * if (ret < 0) { + * pr_info("%s: genphy_read_status failed\n", __func__); + * return ret; + * } + */ - // Link status must be read twice + /* Link status must be read twice */ for (i = 0; i < 2; i++) val = phy_read_mmd(phydev, MMD_VEND2, 0xA402); @@ -450,13 +451,13 @@ static int rtl8226_read_status(struct phy_device *phydev) if (!phydev->link) goto out; - // Read duplex status + /* Read duplex status */ val = phy_read_mmd(phydev, MMD_VEND2, 0xA434); if (val < 0) goto out; phydev->duplex = !!(val & BIT(3)); - // Read speed + /* Read speed */ val = phy_read_mmd(phydev, MMD_VEND2, 0xA434); switch (val & 0x0630) { case 0x0000: @@ -496,24 +497,24 @@ static int rtl8226_advertise_aneg(struct phy_device *phydev) if (v < 0) goto out; - v |= BIT(5); // HD 10M - v |= BIT(6); // FD 10M - v |= BIT(7); // HD 100M - v |= BIT(8); // FD 100M + v |= BIT(5); /* HD 10M */ + v |= BIT(6); /* FD 10M */ + v |= BIT(7); /* HD 100M */ + v |= BIT(8); /* FD 100M */ ret = phy_write_mmd(phydev, MMD_AN, 16, v); - // Allow 1GBit + /* Allow 1GBit */ v = phy_read_mmd(phydev, MMD_VEND2, 0xA412); if (v < 0) goto out; - v |= BIT(9); // FD 1000M + v |= BIT(9); /* FD 1000M */ ret = phy_write_mmd(phydev, MMD_VEND2, 0xA412, v); if (ret < 0) goto out; - // Allow 2.5G + /* Allow 2.5G */ v = phy_read_mmd(phydev, MMD_AN, 32); if (v < 0) goto out; @@ -535,17 +536,17 @@ static int rtl8226_config_aneg(struct phy_device *phydev) ret = rtl8226_advertise_aneg(phydev); if (ret) goto out; - // AutoNegotiationEnable + /* AutoNegotiationEnable */ v = phy_read_mmd(phydev, MMD_AN, 0); if (v < 0) goto out; - v |= BIT(12); // Enable AN + v |= BIT(12); /* Enable AN */ ret = phy_write_mmd(phydev, MMD_AN, 0, v); if (ret < 0) goto out; - // RestartAutoNegotiation + /* RestartAutoNegotiation */ v = phy_read_mmd(phydev, MMD_VEND2, 0xA400); if (v < 0) goto out; @@ -554,7 +555,7 @@ static int rtl8226_config_aneg(struct phy_device *phydev) ret = phy_write_mmd(phydev, MMD_VEND2, 0xA400, v); } -// TODO: ret = __genphy_config_aneg(phydev, ret); +/* TODO: ret = __genphy_config_aneg(phydev, ret); */ out: return ret; @@ -592,11 +593,11 @@ static int rtl8226_set_eee(struct phy_device *phydev, struct ethtool_eee *e) poll_state = disable_polling(port); - // Remember aneg state + /* Remember aneg state */ val = phy_read_mmd(phydev, MMD_AN, 0); an_enabled = !!(val & BIT(12)); - // Setup 100/1000MBit + /* Setup 100/1000MBit */ val = phy_read_mmd(phydev, MMD_AN, 60); if (e->eee_enabled) val |= 0x6; @@ -604,7 +605,7 @@ static int rtl8226_set_eee(struct phy_device *phydev, struct ethtool_eee *e) val &= 0x6; phy_write_mmd(phydev, MMD_AN, 60, val); - // Setup 2.5GBit + /* Setup 2.5GBit */ val = phy_read_mmd(phydev, MMD_AN, 62); if (e->eee_enabled) val |= 0x1; @@ -612,7 +613,7 @@ static int rtl8226_set_eee(struct phy_device *phydev, struct ethtool_eee *e) val &= 0x1; phy_write_mmd(phydev, MMD_AN, 62, val); - // RestartAutoNegotiation + /* RestartAutoNegotiation */ val = phy_read_mmd(phydev, MMD_VEND2, 0xA400); val |= BIT(9); phy_write_mmd(phydev, MMD_VEND2, 0xA400, val); @@ -1094,7 +1095,7 @@ static int rtl8218b_get_eee(struct phy_device *phydev, val = phy_read_paged(phydev, 7, 60); if (e->eee_enabled) { - // Verify vs MAC-based EEE + /* Verify vs MAC-based EEE */ e->eee_enabled = !!(val & BIT(7)); if (!e->eee_enabled) { val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25); @@ -1151,13 +1152,13 @@ static int rtl8214fc_set_eee(struct phy_device *phydev, /* Set GPHY page to copper */ phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER); - // Get auto-negotiation status + /* Get auto-negotiation status */ val = phy_read(phydev, 0); an_enabled = val & BIT(12); pr_info("%s: aneg: %d\n", __func__, an_enabled); val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25); - val &= ~BIT(5); // Use MAC-based EEE + val &= ~BIT(5); /* Use MAC-based EEE */ phy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val); /* Enable 100M (bit 1) / 1000M (bit 2) EEE */ @@ -1628,7 +1629,7 @@ static int rtl9300_read_status(struct phy_device *phydev) mode = rtl9300_sds_mode_get(sds_num); pr_info("%s got SDS mode %02x\n", __func__, mode); - if (mode == 0x1a) { // 10GR mode + if (mode == 0x1a) { /* 10GR mode */ status = rtl9300_sds_field_r(sds_num, 0x5, 0, 12, 12); latch_status = rtl9300_sds_field_r(sds_num, 0x4, 1, 2, 2); status |= rtl9300_sds_field_r(sds_num, 0x5, 0, 12, 12); @@ -1657,7 +1658,7 @@ static int rtl9300_read_status(struct phy_device *phydev) void rtl930x_sds_rx_rst(int sds_num, phy_interface_t phy_if) { - int page = 0x2e; // 10GR and USXGMII + int page = 0x2e; /* 10GR and USXGMII */ if (phy_if == PHY_INTERFACE_MODE_1000BASEX) page = 0x24; @@ -1689,7 +1690,7 @@ void rtl9300_force_sds_mode(int sds, phy_interface_t phy_if) case PHY_INTERFACE_MODE_HSGMII: sds_mode = 0x12; lc_value = 0x3; - // Configure LC + /* Configure LC */ break; case PHY_INTERFACE_MODE_1000BASEX: @@ -1700,7 +1701,7 @@ void rtl9300_force_sds_mode(int sds, phy_interface_t phy_if) case PHY_INTERFACE_MODE_2500BASEX: sds_mode = 0x16; lc_value = 0x3; - // Configure LC + /* Configure LC */ break; case PHY_INTERFACE_MODE_10GBASER: @@ -1710,7 +1711,7 @@ void rtl9300_force_sds_mode(int sds, phy_interface_t phy_if) break; case PHY_INTERFACE_MODE_NA: - // This will disable SerDes + /* This will disable SerDes */ sds_mode = 0x1f; break; @@ -1721,12 +1722,12 @@ void rtl9300_force_sds_mode(int sds, phy_interface_t phy_if) } pr_info("%s --------------------- serdes %d forcing to %x ...\n", __func__, sds, sds_mode); - // Power down SerDes + /* Power down SerDes */ rtl9300_sds_field_w(sds, 0x20, 0, 7, 6, 0x3); if (sds == 5) pr_info("%s after %x\n", __func__, rtl930x_read_sds_phy(sds, 0x20, 0)); if (sds == 5) pr_info("%s a %x\n", __func__, rtl930x_read_sds_phy(sds, 0x1f, 9)); - // Force mode enable + /* Force mode enable */ rtl9300_sds_field_w(sds, 0x1f, 9, 6, 6, 0x1); if (sds == 5) pr_info("%s b %x\n", __func__, rtl930x_read_sds_phy(sds, 0x1f, 9)); @@ -1737,7 +1738,7 @@ void rtl9300_force_sds_mode(int sds, phy_interface_t phy_if) return; if (sds == 5) pr_info("%s c %x\n", __func__, rtl930x_read_sds_phy(sds, 0x20, 18)); - // Enable LC and ring + /* Enable LC and ring */ rtl9300_sds_field_w(lane_0, 0x20, 18, 3, 0, 0xf); if (sds == lane_0) @@ -1752,7 +1753,7 @@ void rtl9300_force_sds_mode(int sds, phy_interface_t phy_if) else rtl9300_sds_field_w(lane_0, 0x20, 18, 15, 12, lc_value); - // Force analog LC & ring on + /* Force analog LC & ring on */ rtl9300_sds_field_w(lane_0, 0x21, 11, 3, 0, 0xf); v = lc_on ? 0x3 : 0x1; @@ -1762,11 +1763,11 @@ void rtl9300_force_sds_mode(int sds, phy_interface_t phy_if) else rtl9300_sds_field_w(lane_0, 0x20, 18, 7, 6, v); - // Force SerDes mode + /* Force SerDes mode */ rtl9300_sds_field_w(sds, 0x1f, 9, 6, 6, 1); rtl9300_sds_field_w(sds, 0x1f, 9, 11, 7, sds_mode); - // Toggle LC or Ring + /* Toggle LC or Ring */ for (i = 0; i < 20; i++) { mdelay(200); @@ -1790,19 +1791,19 @@ void rtl9300_force_sds_mode(int sds, phy_interface_t phy_if) t = rtl9300_sds_field_r(sds, 0x6, 0x1, 2, 2); rtl9300_sds_field_w(sds, 0x6, 0x1, 2, 2, 0x1); - // Reset FSM + /* Reset FSM */ rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x1); mdelay(10); rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x0); mdelay(10); - // Need to read this twice + /* Need to read this twice */ v = rtl9300_sds_field_r(sds, 0x5, 0, 12, 12); v = rtl9300_sds_field_r(sds, 0x5, 0, 12, 12); rtl9300_sds_field_w(sds, 0x6, 0x1, 2, 2, t); - // Reset FSM again + /* Reset FSM again */ rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x1); mdelay(10); rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x0); @@ -1822,7 +1823,7 @@ void rtl9300_force_sds_mode(int sds, phy_interface_t phy_if) rtl930x_sds_rx_rst(sds, phy_if); - // Re-enable power + /* Re-enable power */ rtl9300_sds_field_w(sds, 0x20, 0, 7, 6, 0); pr_info("%s --------------------- serdes %d forced to %x DONE\n", __func__, sds, sds_mode); @@ -1830,7 +1831,7 @@ void rtl9300_force_sds_mode(int sds, phy_interface_t phy_if) void rtl9300_sds_tx_config(int sds, phy_interface_t phy_if) { - // parameters: rtl9303_80G_txParam_s2 + /* parameters: rtl9303_80G_txParam_s2 */ int impedance = 0x8; int pre_amp = 0x2; int main_amp = 0x9; @@ -1885,8 +1886,8 @@ void rtl9300_serdes_mac_link_config(int sds, bool tx_normal, bool rx_normal) { u32 v10, v1; - v10 = rtl930x_read_sds_phy(sds, 6, 2); // 10GBit, page 6, reg 2 - v1 = rtl930x_read_sds_phy(sds, 0, 0); // 1GBit, page 0, reg 0 + v10 = rtl930x_read_sds_phy(sds, 6, 2); /* 10GBit, page 6, reg 2 */ + v1 = rtl930x_read_sds_phy(sds, 0, 0); /* 1GBit, page 0, reg 0 */ pr_info("%s: registers before %08x %08x\n", __func__, v10, v1); v10 &= ~(BIT(13) | BIT(14)); @@ -1980,10 +1981,10 @@ void rtl9300_sds_rxcal_dcvs_get(u32 sds_num, u32 dcvs_id, u32 dcvs_list[]) else rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31); - // ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] + /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */ rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1); - // ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] + /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] */ rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20); switch(dcvs_id) { @@ -1991,7 +1992,7 @@ void rtl9300_sds_rxcal_dcvs_get(u32 sds_num, u32 dcvs_id, u32 dcvs_list[]) rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x22); mdelay(1); - // ##DCVS0 Read Out + /* ##DCVS0 Read Out */ dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4); dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0); dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 14, 14); @@ -2001,7 +2002,7 @@ void rtl9300_sds_rxcal_dcvs_get(u32 sds_num, u32 dcvs_id, u32 dcvs_list[]) rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x23); mdelay(1); - // ##DCVS0 Read Out + /* ##DCVS0 Read Out */ dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4); dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0); dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 13, 13); @@ -2011,7 +2012,7 @@ void rtl9300_sds_rxcal_dcvs_get(u32 sds_num, u32 dcvs_id, u32 dcvs_list[]) rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x24); mdelay(1); - // ##DCVS0 Read Out + /* ##DCVS0 Read Out */ dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4); dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0); dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 12, 12); @@ -2020,7 +2021,7 @@ void rtl9300_sds_rxcal_dcvs_get(u32 sds_num, u32 dcvs_id, u32 dcvs_list[]) rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x25); mdelay(1); - // ##DCVS0 Read Out + /* ##DCVS0 Read Out */ dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4); dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0); dcvs_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 11, 11); @@ -2030,7 +2031,7 @@ void rtl9300_sds_rxcal_dcvs_get(u32 sds_num, u32 dcvs_id, u32 dcvs_list[]) rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x2c); mdelay(1); - // ##DCVS0 Read Out + /* ##DCVS0 Read Out */ dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4); dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0); dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x01, 15, 15); @@ -2040,7 +2041,7 @@ void rtl9300_sds_rxcal_dcvs_get(u32 sds_num, u32 dcvs_id, u32 dcvs_list[]) rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x2d); mdelay(1); - // ##DCVS0 Read Out + /* ##DCVS0 Read Out */ dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4); dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0); dcvs_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x02, 11, 11); @@ -2120,14 +2121,14 @@ u32 rtl9300_sds_rxcal_leq_read(int sds_num) else rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31); - // ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] + /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */ rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1); - // ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[0 1 x x x x] + /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[0 1 x x x x] */ rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x10); mdelay(1); - // ##LEQ Read Out + /* ##LEQ Read Out */ leq_gray = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 7, 3); leq_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x18, 15, 15); leq_bin = rtl9300_sds_rxcal_gray_to_binary(leq_gray); @@ -2154,25 +2155,25 @@ void rtl9300_sds_rxcal_vth_get(u32 sds_num, u32 vth_list[]) { u32 vth_manual; - //##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x002F]; //Lane0 - //##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x0031]; //Lane1 + /* ##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x002F]; */ /* Lane0 */ + /* ##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x0031]; */ /* Lane1 */ if (!(sds_num % 2)) rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f); else rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31); - //##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] + /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */ rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1); - //##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] + /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] */ rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20); - //##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 0 0] + /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 0 0] */ rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xc); mdelay(1); - //##VthP & VthN Read Out - vth_list[0] = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 2, 0); // v_thp set bin - vth_list[1] = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 3); // v_thn set bin + /* ##VthP & VthN Read Out */ + vth_list[0] = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 2, 0); /* v_thp set bin */ + vth_list[1] = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 3); /* v_thn set bin */ pr_info("vth_set_bin = %d", vth_list[0]); pr_info("vth_set_bin = %d", vth_list[1]); @@ -2186,7 +2187,7 @@ void rtl9300_sds_rxcal_tap_manual(u32 sds_num, int tap_id, bool manual, u32 tap_ if (manual) { switch(tap_id) { case 0: - //##REG0_LOAD_IN_INIT[0]=1; REG0_TAP0_INIT[5:0]=Tap0_Value + /* ##REG0_LOAD_IN_INIT[0]=1; REG0_TAP0_INIT[5:0]=Tap0_Value */ rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1); rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 5, 5, tap_list[0]); rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 4, 0, tap_list[1]); @@ -2243,15 +2244,15 @@ void rtl9300_sds_rxcal_tap_get(u32 sds_num, u32 tap_id, u32 tap_list[]) else rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31); - //##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] + /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */ rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1); - //##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] + /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] */ rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20); if (!tap_id) { - //##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 0 0 1] + /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 0 0 1] */ rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0); - //##Tap1 Even Read Out + /* ##Tap1 Even Read Out */ mdelay(1); tap0_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5); tap0_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0); @@ -2269,16 +2270,16 @@ void rtl9300_sds_rxcal_tap_get(u32 sds_num, u32 tap_id, u32 tap_list[]) tap_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, 7, 7); pr_info("tap0 manual = %u",tap_manual); } else { - //##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 0 0 1] + /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 0 0 1] */ rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, tap_id); mdelay(1); - //##Tap1 Even Read Out + /* ##Tap1 Even Read Out */ tap_sign_out_even = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5); tap_coef_bin_even = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0); - //##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 1 1 0] + /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 1 1 0] */ rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, (tap_id + 5)); - //##Tap1 Odd Read Out + /* ##Tap1 Odd Read Out */ tap_sign_out_odd = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5); tap_coef_bin_odd = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0); @@ -2308,19 +2309,19 @@ void rtl9300_sds_rxcal_tap_get(u32 sds_num, u32 tap_id, u32 tap_list[]) void rtl9300_do_rx_calibration_1(int sds, phy_interface_t phy_mode) { - // From both rtl9300_rxCaliConf_serdes_myParam and rtl9300_rxCaliConf_phy_myParam - int tap0_init_val = 0x1f; // Initial Decision Fed Equalizer 0 tap + /* From both rtl9300_rxCaliConf_serdes_myParam and rtl9300_rxCaliConf_phy_myParam */ + int tap0_init_val = 0x1f; /* Initial Decision Fed Equalizer 0 tap */ int vth_min = 0x0; pr_info("start_1.1.1 initial value for sds %d\n", sds); rtl930x_write_sds_phy(sds, 6, 0, 0); - // FGCAL + /* FGCAL */ rtl9300_sds_field_w(sds, 0x2e, 0x01, 14, 14, 0x00); rtl9300_sds_field_w(sds, 0x2e, 0x1c, 10, 5, 0x20); rtl9300_sds_field_w(sds, 0x2f, 0x02, 0, 0, 0x01); - // DCVS + /* DCVS */ rtl9300_sds_field_w(sds, 0x2e, 0x1e, 14, 11, 0x00); rtl9300_sds_field_w(sds, 0x2e, 0x01, 15, 15, 0x00); rtl9300_sds_field_w(sds, 0x2e, 0x02, 11, 11, 0x00); @@ -2334,10 +2335,10 @@ void rtl9300_do_rx_calibration_1(int sds, phy_interface_t phy_mode) rtl9300_sds_field_w(sds, 0x2e, 0x04, 6, 6, 0x01); rtl9300_sds_field_w(sds, 0x2e, 0x04, 7, 7, 0x01); - // LEQ (Long Term Equivalent signal level) + /* LEQ (Long Term Equivalent signal level) */ rtl9300_sds_field_w(sds, 0x2e, 0x16, 14, 8, 0x00); - // DFE (Decision Fed Equalizer) + /* DFE (Decision Fed Equalizer) */ rtl9300_sds_field_w(sds, 0x2f, 0x03, 5, 0, tap0_init_val); rtl9300_sds_field_w(sds, 0x2e, 0x09, 11, 6, 0x00); rtl9300_sds_field_w(sds, 0x2e, 0x09, 5, 0, 0x00); @@ -2348,7 +2349,7 @@ void rtl9300_do_rx_calibration_1(int sds, phy_interface_t phy_mode) rtl9300_sds_field_w(sds, 0x2e, 0x06, 5, 0, 0x00); rtl9300_sds_field_w(sds, 0x2f, 0x01, 5, 0, 0x00); - // Vth + /* Vth */ rtl9300_sds_field_w(sds, 0x2e, 0x13, 5, 3, 0x07); rtl9300_sds_field_w(sds, 0x2e, 0x13, 2, 0, 0x07); rtl9300_sds_field_w(sds, 0x2f, 0x0b, 5, 3, vth_min); @@ -2380,14 +2381,14 @@ void rtl9300_do_rx_calibration_1(int sds, phy_interface_t phy_mode) pr_info("start_1.1.5 LEQ and DFE setting\n"); - // TODO: make this work for DAC cables of different lengths - // For a 10GBit serdes wit Fibre, SDS 8 or 9 + /* TODO: make this work for DAC cables of different lengths */ + /* For a 10GBit serdes wit Fibre, SDS 8 or 9 */ if (phy_mode == PHY_INTERFACE_MODE_10GBASER || PHY_INTERFACE_MODE_1000BASEX) rtl9300_sds_field_w(sds, 0x2e, 0x16, 3, 2, 0x02); else pr_err("%s not PHY-based or SerDes, implement DAC!\n", __func__); - // No serdes, check for Aquantia PHYs + /* No serdes, check for Aquantia PHYs */ rtl9300_sds_field_w(sds, 0x2e, 0x16, 3, 2, 0x02); rtl9300_sds_field_w(sds, 0x2e, 0x0f, 6, 0, 0x5f); @@ -2403,10 +2404,10 @@ void rtl9300_do_rx_calibration_2_1(u32 sds_num) { pr_info("start_1.2.1 ForegroundOffsetCal_Manual\n"); - // Gray config endis to 1 + /* Gray config endis to 1 */ rtl9300_sds_field_w(sds_num, 0x2f, 0x02, 2, 2, 0x01); - // ForegroundOffsetCal_Manual(auto mode) + /* ForegroundOffsetCal_Manual(auto mode) */ rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 14, 14, 0x00); pr_info("end_1.2.1"); @@ -2414,7 +2415,7 @@ void rtl9300_do_rx_calibration_2_1(u32 sds_num) void rtl9300_do_rx_calibration_2_2(int sds_num) { - //Force Rx-Run = 0 + /* Force Rx-Run = 0 */ rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 8, 8, 0x0); rtl930x_sds_rx_rst(sds_num, PHY_INTERFACE_MODE_10GBASER); @@ -2433,17 +2434,17 @@ void rtl9300_do_rx_calibration_2_3(int sds_num) else rtl930x_write_sds_phy(sds_num -1 , 0x1f, 0x2, 0x31); - // ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] + /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */ rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1); - // ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] + /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] */ rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20); - // ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 1 1] + /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 1 1] */ rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xf); - // ##FGCAL read gray + /* ##FGCAL read gray */ fgcal_gray = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 0); - // ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 1 0] + /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 1 0] */ rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xe); - // ##FGCAL read binary + /* ##FGCAL read binary */ fgcal_binary = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 0); pr_info("%s: fgcal_gray: %d, fgcal_binary %d\n", @@ -2479,7 +2480,7 @@ void rtl9300_sds_rxcal_3_1(int sds_num, phy_interface_t phy_mode) { pr_info("start_1.3.1"); - // ##1.3.1 + /* ##1.3.1 */ if (phy_mode != PHY_INTERFACE_MODE_10GBASER && phy_mode != PHY_INTERFACE_MODE_1000BASEX) rtl9300_sds_field_w(sds_num, 0x2e, 0xc, 8, 8, 0); @@ -2497,11 +2498,11 @@ void rtl9300_sds_rxcal_3_2(int sds_num, phy_interface_t phy_mode) int i; if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX) { - // rtl9300_rxCaliConf_serdes_myParam + /* rtl9300_rxCaliConf_serdes_myParam */ dac_long_cable_offset = 3; eq_hold_enabled = true; } else { - // rtl9300_rxCaliConf_phy_myParam + /* rtl9300_rxCaliConf_phy_myParam */ dac_long_cable_offset = 0; eq_hold_enabled = false; } @@ -2562,7 +2563,7 @@ void rtl9300_do_rx_calibration_4_1(int sds_num) pr_info("start_1.4.1"); - // ##1.4.1 + /* ##1.4.1 */ rtl9300_sds_rxcal_vth_manual(sds_num, false, vth_list); rtl9300_sds_rxcal_tap_manual(sds_num, 0, false, tap0_list); mdelay(200); @@ -2615,7 +2616,7 @@ void rtl9300_do_rx_calibration_5_2(u32 sds_num) void rtl9300_do_rx_calibration_5(u32 sds_num, phy_interface_t phy_mode) { - if (phy_mode == PHY_INTERFACE_MODE_10GBASER) // dfeTap1_4Enable true + if (phy_mode == PHY_INTERFACE_MODE_10GBASER) /* dfeTap1_4Enable true */ rtl9300_do_rx_calibration_5_2(sds_num); } @@ -2645,7 +2646,7 @@ void rtl9300_do_rx_calibration(int sds, phy_interface_t phy_mode) rtl9300_do_rx_calibration_5(sds, phy_mode); mdelay(20); - // Do this only for 10GR mode, SDS active in mode 0x1a + /* Do this only for 10GR mode, SDS active in mode 0x1a */ if (rtl9300_sds_field_r(sds, 0x1f, 9, 11, 7) == 0x1a) { pr_info("%s: SDS enabled\n", __func__); latch_sts = rtl9300_sds_field_r(sds, 0x4, 1, 2, 2); @@ -2666,7 +2667,7 @@ int rtl9300_sds_sym_err_reset(int sds_num, phy_interface_t phy_mode) break; case PHY_INTERFACE_MODE_10GBASER: - // Read twice to clear + /* Read twice to clear */ rtl930x_read_sds_phy(sds_num, 5, 1); rtl930x_read_sds_phy(sds_num, 5, 1); break; @@ -2711,7 +2712,7 @@ int rtl9300_sds_check_calibration(int sds_num, phy_interface_t phy_mode) rtl9300_sds_sym_err_reset(sds_num, phy_mode); rtl9300_sds_sym_err_reset(sds_num, phy_mode); - // Count errors during 1ms + /* Count errors during 1ms */ errors1 = rtl9300_sds_sym_err_get(sds_num, phy_mode); mdelay(1); errors2 = rtl9300_sds_sym_err_get(sds_num, phy_mode); @@ -2742,21 +2743,21 @@ void rtl9300_phy_enable_10g_1g(int sds_num) { u32 v; - // Enable 1GBit PHY + /* Enable 1GBit PHY */ v = rtl930x_read_sds_phy(sds_num, PHY_PAGE_2, PHY_CTRL_REG); pr_info("%s 1gbit phy: %08x\n", __func__, v); v &= ~BIT(PHY_POWER_BIT); rtl930x_write_sds_phy(sds_num, PHY_PAGE_2, PHY_CTRL_REG, v); pr_info("%s 1gbit phy enabled: %08x\n", __func__, v); - // Enable 10GBit PHY + /* Enable 10GBit PHY */ v = rtl930x_read_sds_phy(sds_num, PHY_PAGE_4, PHY_CTRL_REG); pr_info("%s 10gbit phy: %08x\n", __func__, v); v &= ~BIT(PHY_POWER_BIT); rtl930x_write_sds_phy(sds_num, PHY_PAGE_4, PHY_CTRL_REG, v); pr_info("%s 10gbit phy after: %08x\n", __func__, v); - // dal_longan_construct_mac_default_10gmedia_fiber + /* dal_longan_construct_mac_default_10gmedia_fiber */ v = rtl930x_read_sds_phy(sds_num, 0x1f, 11); pr_info("%s set medium: %08x\n", __func__, v); v |= BIT(1); @@ -2765,7 +2766,7 @@ void rtl9300_phy_enable_10g_1g(int sds_num) } #define RTL930X_MAC_FORCE_MODE_CTRL (0xCA1C) -// phy_mode = PHY_INTERFACE_MODE_10GBASER, sds_mode = 0x1a +/* phy_mode = PHY_INTERFACE_MODE_10GBASER, sds_mode = 0x1a */ int rtl9300_serdes_setup(int sds_num, phy_interface_t phy_mode) { int sds_mode; @@ -2792,15 +2793,15 @@ int rtl9300_serdes_setup(int sds_num, phy_interface_t phy_mode) return -EINVAL; } - // Maybe use dal_longan_sds_init + /* Maybe use dal_longan_sds_init */ - // dal_longan_construct_serdesConfig_init // Serdes Construct + /* dal_longan_construct_serdesConfig_init */ /* Serdes Construct */ rtl9300_phy_enable_10g_1g(sds_num); - // Set Serdes Mode - rtl9300_sds_set(sds_num, 0x1a); // 0x1b: RTK_MII_10GR1000BX_AUTO + /* Set Serdes Mode */ + rtl9300_sds_set(sds_num, 0x1a); /* 0x1b: RTK_MII_10GR1000BX_AUTO */ - // Do RX calibration + /* Do RX calibration */ do { rtl9300_do_rx_calibration(sds_num, phy_mode); calib_tries++; @@ -2914,15 +2915,15 @@ int rtl9300_sds_cmu_band_get(int sds) u32 en; u32 cmu_band; -// page = rtl9300_sds_cmu_page_get(sds); - page = 0x25; // 10GR and 1000BX +/* page = rtl9300_sds_cmu_page_get(sds); */ + page = 0x25; /* 10GR and 1000BX */ sds = (sds % 2) ? (sds - 1) : (sds); rtl9300_sds_field_w(sds, page, 0x1c, 15, 15, 1); rtl9300_sds_field_w(sds + 1, page, 0x1c, 15, 15, 1); en = rtl9300_sds_field_r(sds, page, 27, 1, 1); - if(!en) { // Auto mode + if(!en) { /* Auto mode */ rtl930x_write_sds_phy(sds, 0x1f, 0x02, 31); cmu_band = rtl9300_sds_field_r(sds, 0x1f, 0x15, 5, 1); @@ -2955,7 +2956,7 @@ int rtl9300_configure_serdes(struct phy_device *phydev) if (sds_num < 0) return 0; - if (phy_mode != PHY_INTERFACE_MODE_10GBASER) // TODO: for now we only patch 10GR SerDes + if (phy_mode != PHY_INTERFACE_MODE_10GBASER) /* TODO: for now we only patch 10GR SerDes */ return 0; switch (phy_mode) { @@ -2981,7 +2982,7 @@ int rtl9300_configure_serdes(struct phy_device *phydev) pr_info("%s CMU BAND is %d\n", __func__, rtl9300_sds_cmu_band_get(sds_num)); - // Turn Off Serdes + /* Turn Off Serdes */ rtl9300_sds_rst(sds_num, 0x1f); pr_info("%s PATCHING SerDes %d\n", __func__, sds_num); @@ -3001,28 +3002,28 @@ int rtl9300_configure_serdes(struct phy_device *phydev) rtl9300_phy_enable_10g_1g(sds_num); - // Disable MAC + /* Disable MAC */ sw_w32_mask(0, 1, RTL930X_MAC_FORCE_MODE_CTRL); mdelay(20); - // ----> dal_longan_sds_mode_set + /* ----> dal_longan_sds_mode_set */ pr_info("%s: Configuring RTL9300 SERDES %d, mode %02x\n", __func__, sds_num, sds_mode); - // Configure link to MAC - rtl9300_serdes_mac_link_config(sds_num, true, true); // MAC Construct + /* Configure link to MAC */ + rtl9300_serdes_mac_link_config(sds_num, true, true); /* MAC Construct */ - // Disable MAC + /* Disable MAC */ sw_w32_mask(0, 1, RTL930X_MAC_FORCE_MODE_CTRL); mdelay(20); rtl9300_force_sds_mode(sds_num, PHY_INTERFACE_MODE_NA); - // Re-Enable MAC + /* Re-Enable MAC */ sw_w32_mask(1, 0, RTL930X_MAC_FORCE_MODE_CTRL); rtl9300_force_sds_mode(sds_num, phy_mode); - // Do RX calibration + /* Do RX calibration */ do { rtl9300_do_rx_calibration(sds_num, phy_mode); calib_tries++; @@ -3034,7 +3035,7 @@ int rtl9300_configure_serdes(struct phy_device *phydev) rtl9300_sds_tx_config(sds_num, phy_mode); - // The clock needs only to be configured on the FPGA implementation + /* The clock needs only to be configured on the FPGA implementation */ return 0; } @@ -3071,7 +3072,7 @@ static void rtl931x_sds_rst(u32 sds) u32 o, v, o_mode; int shift = ((sds & 0x3) << 3); - // TODO: We need to lock this! + /* TODO: We need to lock this! */ o = sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR); v = o | BIT(sds); @@ -3188,20 +3189,20 @@ static int rtl931x_sds_cmu_page_get(phy_interface_t mode) { switch (mode) { case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_1000BASEX: // MII_1000BX_FIBER / 100BX_FIBER / 1000BX100BX_AUTO + case PHY_INTERFACE_MODE_1000BASEX: /* MII_1000BX_FIBER / 100BX_FIBER / 1000BX100BX_AUTO */ return 0x24; case PHY_INTERFACE_MODE_HSGMII: - case PHY_INTERFACE_MODE_2500BASEX: // MII_2500Base_X: + case PHY_INTERFACE_MODE_2500BASEX: /* MII_2500Base_X: */ return 0x28; -// case MII_HISGMII_5G: -// return 0x2a; +/* case MII_HISGMII_5G: */ +/* return 0x2a; */ case PHY_INTERFACE_MODE_QSGMII: - return 0x2a; // Code also has 0x34 - case PHY_INTERFACE_MODE_XAUI: // MII_RXAUI_LITE: + return 0x2a; /* Code also has 0x34 */ + case PHY_INTERFACE_MODE_XAUI: /* MII_RXAUI_LITE: */ return 0x2c; - case PHY_INTERFACE_MODE_XGMII: // MII_XSGMII + case PHY_INTERFACE_MODE_XGMII: /* MII_XSGMII */ case PHY_INTERFACE_MODE_10GKR: - case PHY_INTERFACE_MODE_10GBASER: // MII_10GR + case PHY_INTERFACE_MODE_10GBASER: /* MII_10GR */ return 0x2e; default: return -1; @@ -3212,7 +3213,7 @@ static int rtl931x_sds_cmu_page_get(phy_interface_t mode) static void rtl931x_cmu_type_set(u32 asds, phy_interface_t mode, int chiptype) { - int cmu_type = 0; // Clock Management Unit + int cmu_type = 0; /* Clock Management Unit */ u32 cmu_page = 0; u32 frc_cmu_spd; u32 evenSds; @@ -3340,7 +3341,7 @@ static void rtl931x_sds_mii_mode_set(u32 sds, phy_interface_t mode) val = 0x6; break; case PHY_INTERFACE_MODE_XGMII: - val = 0x10; // serdes mode XSGMII + val = 0x10; /* serdes mode XSGMII */ break; case PHY_INTERFACE_MODE_USXGMII: case PHY_INTERFACE_MODE_2500BASEX: @@ -3448,12 +3449,12 @@ void rtl931x_sds_init(u32 sds, phy_interface_t mode) case PHY_INTERFACE_MODE_NA: break; - case PHY_INTERFACE_MODE_XGMII: // MII_XSGMII + case PHY_INTERFACE_MODE_XGMII: /* MII_XSGMII */ if (chiptype) { u32 xsg_sdsid_1; xsg_sdsid_1 = dSds + 1; - //fifo inv clk + /* fifo inv clk */ rtl9310_sds_field_w(dSds, 0x1, 0x1, 7, 4, 0xf); rtl9310_sds_field_w(dSds, 0x1, 0x1, 3, 0, 0xf); @@ -3466,7 +3467,7 @@ void rtl931x_sds_init(u32 sds, phy_interface_t mode) rtl9310_sds_field_w(dSds + 1, 0x0, 0xE, 12, 12, 1); break; - case PHY_INTERFACE_MODE_USXGMII: // MII_USXGMII_10GSXGMII/10GDXGMII/10GQXGMII: + case PHY_INTERFACE_MODE_USXGMII: /* MII_USXGMII_10GSXGMII/10GDXGMII/10GQXGMII: */ u32 i, evenSds; u32 op_code = 0x6003; @@ -3507,18 +3508,18 @@ void rtl931x_sds_init(u32 sds, phy_interface_t mode) } break; - case PHY_INTERFACE_MODE_10GBASER: // MII_10GR / MII_10GR1000BX_AUTO: - // configure 10GR fiber mode=1 + case PHY_INTERFACE_MODE_10GBASER: /* MII_10GR / MII_10GR1000BX_AUTO: */ + /* configure 10GR fiber mode=1 */ rtl9310_sds_field_w(asds, 0x1f, 0xb, 1, 1, 1); - // init fiber_1g + /* init fiber_1g */ rtl9310_sds_field_w(dSds, 0x3, 0x13, 15, 14, 0); rtl9310_sds_field_w(dSds, 0x2, 0x0, 12, 12, 1); rtl9310_sds_field_w(dSds, 0x2, 0x0, 6, 6, 1); rtl9310_sds_field_w(dSds, 0x2, 0x0, 13, 13, 0); - // init auto + /* init auto */ rtl9310_sds_field_w(asds, 0x1f, 13, 15, 0, 0x109e); rtl9310_sds_field_w(asds, 0x1f, 0x6, 14, 10, 0x8); rtl9310_sds_field_w(asds, 0x1f, 0x7, 10, 4, 0x7f); @@ -3528,7 +3529,7 @@ void rtl931x_sds_init(u32 sds, phy_interface_t mode) rtl9310_sds_field_w(dSds, 0x1, 0x14, 8, 8, 1); break; - case PHY_INTERFACE_MODE_1000BASEX: // MII_1000BX_FIBER + case PHY_INTERFACE_MODE_1000BASEX: /* MII_1000BX_FIBER */ rtl9310_sds_field_w(dSds, 0x3, 0x13, 15, 14, 0); rtl9310_sds_field_w(dSds, 0x2, 0x0, 12, 12, 1); @@ -3560,7 +3561,7 @@ void rtl931x_sds_init(u32 sds, phy_interface_t mode) val = 0xa0000; sw_w32(val, RTL931X_CHIP_INFO_ADDR); val = sw_r32(RTL931X_CHIP_INFO_ADDR); - if (val & BIT(28)) // consider 9311 etc. RTL9313_CHIP_ID == HWP_CHIP_ID(unit)) + if (val & BIT(28)) /* consider 9311 etc. RTL9313_CHIP_ID == HWP_CHIP_ID(unit)) */ { rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx2[sds - 2]); } else { @@ -3790,7 +3791,7 @@ static int rtl8218d_phy_probe(struct phy_device *phydev) struct rtl83xx_shared_private *shared = phydev->shared->priv; shared->name = "RTL8218D"; /* Configuration must be done while patching still possible */ -// TODO: return configure_rtl8218d(phydev); +/* TODO: return configure_rtl8218d(phydev); */ } return 0; diff --git a/target/linux/realtek/files-5.15/drivers/net/phy/rtl83xx-phy.h b/target/linux/realtek/files-5.15/drivers/net/phy/rtl83xx-phy.h index 4addfe1442f..3b912318291 100644 --- a/target/linux/realtek/files-5.15/drivers/net/phy/rtl83xx-phy.h +++ b/target/linux/realtek/files-5.15/drivers/net/phy/rtl83xx-phy.h @@ -18,7 +18,7 @@ struct __attribute__ ((__packed__)) fw_header { struct part parts[10]; }; -// TODO: fixed path? +/* TODO: fixed path? */ #define FIRMWARE_838X_8380_1 "rtl838x_phy/rtl838x_8380.fw" #define FIRMWARE_838X_8214FC_1 "rtl838x_phy/rtl838x_8214fc.fw" #define FIRMWARE_838X_8218b_1 "rtl838x_phy/rtl838x_8218b.fw" @@ -35,7 +35,7 @@ struct __attribute__ ((__packed__)) fw_header { #define PHY_ID_RTL8393_I 0x001c8393 #define PHY_ID_RTL9300_I 0x70d03106 -// PHY MMD devices +/* PHY MMD devices */ #define MMD_AN 7 #define MMD_VEND2 31 From 94d8b4852b9ff0063cddfda13a96fb5449f3bd6d Mon Sep 17 00:00:00 2001 From: Olliver Schinagl Date: Wed, 21 Dec 2022 23:26:08 +0100 Subject: [PATCH 40/72] realtek: Cleanup Makefiles Our current Makefiles a little bit messy and can be improved somewhat, both in whitespace and in style. Signed-off-by: Olliver Schinagl --- target/linux/realtek/Makefile | 15 +++++++-- target/linux/realtek/image/Makefile | 33 +++++++++++++++----- target/linux/realtek/image/common.mk | 43 +++++++++++++++++++++----- target/linux/realtek/image/rtl838x.mk | 23 +++++++++++--- target/linux/realtek/image/rtl839x.mk | 15 +++++++-- target/linux/realtek/image/rtl930x.mk | 9 ++++-- target/linux/realtek/rtl838x/target.mk | 1 - target/linux/realtek/rtl839x/target.mk | 1 - target/linux/realtek/rtl930x/target.mk | 1 - 9 files changed, 110 insertions(+), 31 deletions(-) diff --git a/target/linux/realtek/Makefile b/target/linux/realtek/Makefile index 797ae60274e..94280f43e56 100644 --- a/target/linux/realtek/Makefile +++ b/target/linux/realtek/Makefile @@ -18,8 +18,17 @@ endef include $(INCLUDE_DIR)/target.mk -DEFAULT_PACKAGES += uboot-envtools ethtool kmod-gpio-button-hotplug \ - firewall4 nftables kmod-nft-offload odhcp6c \ - ip-full ip-bridge tc-bpf +DEFAULT_PACKAGES += \ + ethtool \ + firewall4 \ + ip-bridge \ + ip-full \ + kmod-gpio-button-hotplug \ + kmod-nft-offload \ + nftables \ + odhcp6c \ + tc-bpf \ + uboot-envtools \ + $(eval $(call BuildTarget)) diff --git a/target/linux/realtek/image/Makefile b/target/linux/realtek/image/Makefile index 6c7be4aa90a..e4a3904aa83 100644 --- a/target/linux/realtek/image/Makefile +++ b/target/linux/realtek/image/Makefile @@ -6,9 +6,15 @@ include $(INCLUDE_DIR)/image.mk KERNEL_LOADADDR = 0x80000000 KERNEL_ENTRY = 0x80000400 -DEVICE_VARS += ZYXEL_VERS DLINK_KERNEL_PART_SIZE -DEVICE_VARS += CAMEO_KERNEL_PART CAMEO_ROOTFS_PART CAMEO_CUSTOMER_SIGNATURE CAMEO_BOARD_VERSION -DEVICE_VARS += H3C_PRODUCT_ID H3C_DEVICE_ID +DEVICE_VARS += \ + CAMEO_BOARD_VERSION \ + CAMEO_CUSTOMER_SIGNATURE \ + CAMEO_KERNEL_PART \ + CAMEO_ROOTFS_PART \ + DLINK_KERNEL_PART_SIZE \ + H3C_DEVICE_ID \ + H3C_PRODUCT_ID \ + ZYXEL_VERS define Build/zyxel-vers ( echo VERS;\ @@ -81,13 +87,26 @@ endef define Device/Default PROFILES = Default - KERNEL := kernel-bin | append-dtb | gzip | uImage gzip - KERNEL_INITRAMFS := kernel-bin | append-dtb | gzip | uImage gzip + KERNEL := \ + kernel-bin | \ + append-dtb | \ + gzip | \ + uImage gzip + KERNEL_INITRAMFS := \ + kernel-bin | \ + append-dtb | \ + gzip | \ + uImage gzip DEVICE_DTS_DIR := ../dts-$(KERNEL_PATCHVER) DEVICE_DTS = $$(SOC)_$(1) IMAGES := sysupgrade.bin - IMAGE/sysupgrade.bin := append-kernel | pad-to 64k | append-rootfs | pad-rootfs | \ - check-size | append-metadata + IMAGE/sysupgrade.bin := \ + append-kernel | \ + append-metadata | \ + append-rootfs | \ + check-size | \ + pad-rootfs | \ + pad-to 64k endef include $(SUBTARGET).mk diff --git a/target/linux/realtek/image/common.mk b/target/linux/realtek/image/common.mk index 9d84ec08f52..0c515295696 100644 --- a/target/linux/realtek/image/common.mk +++ b/target/linux/realtek/image/common.mk @@ -4,15 +4,26 @@ define Device/d-link_dgs-1210 IMAGE_SIZE := 13824k DEVICE_VENDOR := D-Link DLINK_KERNEL_PART_SIZE := 1572864 - KERNEL := kernel-bin | append-dtb | gzip | uImage gzip | dlink-cameo + KERNEL := \ + kernel-bin | \ + append-dtb | \ + gzip | \ + uImage gzip | \ + dlink-cameo CAMEO_KERNEL_PART := 2 CAMEO_ROOTFS_PART := 3 CAMEO_CUSTOMER_SIGNATURE := 2 CAMEO_BOARD_VERSION := 32 IMAGES += factory_image1.bin - IMAGE/factory_image1.bin := append-kernel | pad-to 64k | \ - append-rootfs | pad-rootfs | pad-to 16 | check-size | \ - dlink-version | dlink-headers + IMAGE/factory_image1.bin := \ + append-kernel | \ + pad-to 64k | \ + append-rootfs | \ + pad-rootfs | \ + pad-to 16 | \ + check-size | \ + dlink-version | \ + dlink-headers endef define Device/hpe_1920 @@ -20,8 +31,24 @@ define Device/hpe_1920 IMAGE_SIZE := 29632k BLOCKSIZE := 64k H3C_PRODUCT_ID := 0x3c010501 - KERNEL := kernel-bin | append-dtb | relocate-kernel | 7z | h3c-image | h3c-vfs - KERNEL_INITRAMFS := kernel-bin | append-dtb | relocate-kernel | 7z | h3c-image - IMAGE/sysupgrade.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | append-rootfs | \ - pad-rootfs | check-size | append-metadata + KERNEL := \ + kernel-bin | \ + append-dtb | \ + relocate-kernel | \ + 7z | \ + h3c-image | \ + h3c-vfs + KERNEL_INITRAMFS := \ + kernel-bin | \ + append-dtb | \ + relocate-kernel | \ + 7z | \ + h3c-image + IMAGE/sysupgrade.bin := \ + append-kernel | \ + pad-to $$$$(BLOCKSIZE) | \ + append-rootfs | \ + pad-rootfs | \ + check-size | \ + append-metadata endef diff --git a/target/linux/realtek/image/rtl838x.mk b/target/linux/realtek/image/rtl838x.mk index eef66c89ce1..6d670115497 100644 --- a/target/linux/realtek/image/rtl838x.mk +++ b/target/linux/realtek/image/rtl838x.mk @@ -67,7 +67,10 @@ define Device/engenius_ews2910p DEVICE_VENDOR := EnGenius DEVICE_MODEL := EWP2910P UIMAGE_MAGIC := 0x03802910 - KERNEL_INITRAMFS := kernel-bin | append-dtb | gzip | \ + KERNEL_INITRAMFS := \ + kernel-bin | \ + append-dtb | \ + gzip | \ uImage gzip -n 'IMG-0.00.00-c0.0.00' endef TARGET_DEVICES += engenius_ews2910p @@ -116,8 +119,16 @@ TARGET_DEVICES += iodata_bsh-g24mb # "NGE" refers to the uImage magic define Device/netgear_nge - KERNEL := kernel-bin | append-dtb | lzma | uImage lzma - KERNEL_INITRAMFS := kernel-bin | append-dtb | lzma | uImage lzma + KERNEL := \ + kernel-bin | \ + append-dtb | \ + lzma | \ + uImage lzma + KERNEL_INITRAMFS := \ + kernel-bin | \ + append-dtb | \ + lzma | \ + uImage lzma SOC := rtl8380 IMAGE_SIZE := 14848k UIMAGE_MAGIC := 0x4e474520 @@ -212,7 +223,11 @@ define Device/zyxel_gs1900 IMAGE_SIZE := 6976k DEVICE_VENDOR := ZyXEL UIMAGE_MAGIC := 0x83800000 - KERNEL_INITRAMFS := kernel-bin | append-dtb | gzip | zyxel-vers | \ + KERNEL_INITRAMFS := \ + kernel-bin | \ + append-dtb | \ + gzip | \ + zyxel-vers | \ uImage gzip endef diff --git a/target/linux/realtek/image/rtl839x.mk b/target/linux/realtek/image/rtl839x.mk index 74ae95ccd78..081c13ff9b2 100644 --- a/target/linux/realtek/image/rtl839x.mk +++ b/target/linux/realtek/image/rtl839x.mk @@ -15,7 +15,10 @@ define Device/panasonic_m48eg-pn28480k DEVICE_VENDOR := Panasonic DEVICE_MODEL := Switch-M48eG DEVICE_VARIANT := PN28480K - DEVICE_PACKAGES := kmod-hwmon-gpiofan kmod-hwmon-lm75 kmod-i2c-mux-pca954x \ + DEVICE_PACKAGES := \ + kmod-hwmon-gpiofan \ + kmod-hwmon-lm75 \ + kmod-i2c-mux-pca954x \ kmod-thermal endef TARGET_DEVICES += panasonic_m48eg-pn28480k @@ -27,7 +30,9 @@ define Device/tplink_sg2452p-v4 DEVICE_VENDOR := TP-Link DEVICE_MODEL := SG2452P DEVICE_VARIANT := v4 - DEVICE_PACKAGES := kmod-hwmon-gpiofan kmod-hwmon-tps23861 + DEVICE_PACKAGES := \ + kmod-hwmon-gpiofan \ + kmod-hwmon-tps23861 endef TARGET_DEVICES += tplink_sg2452p-v4 @@ -38,7 +43,11 @@ define Device/zyxel_gs1900-48 UIMAGE_MAGIC := 0x83800000 ZYXEL_VERS := AAHO DEVICE_MODEL := GS1900-48 - KERNEL_INITRAMFS := kernel-bin | append-dtb | gzip | zyxel-vers $$$$(ZYXEL_VERS) | \ + KERNEL_INITRAMFS := \ + kernel-bin | \ + append-dtb | \ + gzip | \ + zyxel-vers $$$$(ZYXEL_VERS) | \ uImage gzip endef TARGET_DEVICES += zyxel_gs1900-48 diff --git a/target/linux/realtek/image/rtl930x.mk b/target/linux/realtek/image/rtl930x.mk index 191ea5b2043..f55c5c002bf 100644 --- a/target/linux/realtek/image/rtl930x.mk +++ b/target/linux/realtek/image/rtl930x.mk @@ -6,9 +6,12 @@ define Device/zyxel_xgs1250-12 ZYXEL_VERS := ABWE DEVICE_VENDOR := Zyxel DEVICE_MODEL := XGS1250-12 - IMAGE_SIZE := 13312k - KERNEL_INITRAMFS := kernel-bin | append-dtb | gzip | zyxel-vers $$$$(ZYXEL_VERS) | \ + IMAGE_SIZE := 13312k + KERNEL_INITRAMFS := \ + kernel-bin | \ + append-dtb | \ + gzip | \ + zyxel-vers $$$$(ZYXEL_VERS) | \ uImage gzip endef - TARGET_DEVICES += zyxel_xgs1250-12 diff --git a/target/linux/realtek/rtl838x/target.mk b/target/linux/realtek/rtl838x/target.mk index ee658ea9862..d78b44b717f 100644 --- a/target/linux/realtek/rtl838x/target.mk +++ b/target/linux/realtek/rtl838x/target.mk @@ -12,4 +12,3 @@ define Target/Description endef FEATURES := $(filter-out mips16,$(FEATURES)) - diff --git a/target/linux/realtek/rtl839x/target.mk b/target/linux/realtek/rtl839x/target.mk index 0bbd6a5d4a1..88993fad147 100644 --- a/target/linux/realtek/rtl839x/target.mk +++ b/target/linux/realtek/rtl839x/target.mk @@ -10,4 +10,3 @@ KERNEL_PATCHVER:=5.10 define Target/Description Build firmware images for Realtek RTL839x based boards. endef - diff --git a/target/linux/realtek/rtl930x/target.mk b/target/linux/realtek/rtl930x/target.mk index f6f204d0063..31b06219cab 100644 --- a/target/linux/realtek/rtl930x/target.mk +++ b/target/linux/realtek/rtl930x/target.mk @@ -10,4 +10,3 @@ KERNEL_PATCHVER:=5.10 define Target/Description Build firmware images for Realtek RTL930x based boards. endef - From 0a83889e89b7213ea8f6eac21de50ffa3ae5a606 Mon Sep 17 00:00:00 2001 From: Olliver Schinagl Date: Thu, 22 Dec 2022 11:53:30 +0100 Subject: [PATCH 41/72] realtek: Reduce variable scopes Linus prefers to have loop initializers nice and tightly scoped. In OpenWRT this has been possible since 41a1a652fbd4 ("kernel: backport gnu11 upgrade"). This patch cleans up variable scope while trying to do the above for 'simple for loops'. This cleans up and simplifies some functions and code, and pulls in variables to a smaller scope. Signed-off-by: Olliver Schinagl --- .../drivers/clk/realtek/clk-rtl83xx.c | 6 +- .../drivers/i2c/busses/i2c-rtl9300.c | 14 +- .../drivers/net/dsa/rtl83xx/common.c | 26 ++- .../drivers/net/dsa/rtl83xx/debugfs.c | 35 ++-- .../files-5.15/drivers/net/dsa/rtl83xx/dsa.c | 58 +++---- .../files-5.15/drivers/net/dsa/rtl83xx/qos.c | 53 +++---- .../drivers/net/dsa/rtl83xx/rtl838x.c | 75 ++++----- .../drivers/net/dsa/rtl83xx/rtl839x.c | 79 ++++------ .../drivers/net/dsa/rtl83xx/rtl930x.c | 101 +++++------- .../drivers/net/dsa/rtl83xx/rtl931x.c | 74 ++++----- .../drivers/net/ethernet/rtl838x_eth.c | 149 +++++++++--------- .../files-5.15/drivers/net/phy/rtl83xx-phy.c | 108 +++++++------ 12 files changed, 335 insertions(+), 443 deletions(-) diff --git a/target/linux/realtek/files-5.15/drivers/clk/realtek/clk-rtl83xx.c b/target/linux/realtek/files-5.15/drivers/clk/realtek/clk-rtl83xx.c index ce5c166bcad..2e5a2e5087b 100644 --- a/target/linux/realtek/files-5.15/drivers/clk/realtek/clk-rtl83xx.c +++ b/target/linux/realtek/files-5.15/drivers/clk/realtek/clk-rtl83xx.c @@ -663,11 +663,10 @@ err_put_device: void rtcl_ccu_log_early(void) { - int clk_idx; char meminfo[80], clkinfo[255], msg[255] = "rtl83xx-clk: initialized"; sprintf(meminfo, " (%d Bit DDR%d)", rtcl_ccu->dram.buswidth, rtcl_ccu->dram.type); - for (clk_idx = 0; clk_idx < CLK_COUNT; clk_idx++) { + for (int clk_idx = 0; clk_idx < CLK_COUNT; clk_idx++) { sprintf(clkinfo, ", %s %lu MHz", rtcl_clk_info[clk_idx].display_name, rtcl_ccu->clks[clk_idx].startup / 1000000); if (clk_idx == CLK_MEM) @@ -679,12 +678,11 @@ void rtcl_ccu_log_early(void) void rtcl_ccu_log_late(void) { - int clk_idx; struct rtcl_clk *rclk; bool overclock = false; char clkinfo[80], msg[255] = "rate setting enabled"; - for (clk_idx = 0; clk_idx < CLK_COUNT; clk_idx++) { + for (int clk_idx = 0; clk_idx < CLK_COUNT; clk_idx++) { rclk = &rtcl_ccu->clks[clk_idx]; overclock |= rclk->max > rclk->startup; sprintf(clkinfo, ", %s %lu-%lu MHz", rtcl_clk_info[clk_idx].display_name, diff --git a/target/linux/realtek/files-5.15/drivers/i2c/busses/i2c-rtl9300.c b/target/linux/realtek/files-5.15/drivers/i2c/busses/i2c-rtl9300.c index 9afd2f823ea..54d916d17a9 100644 --- a/target/linux/realtek/files-5.15/drivers/i2c/busses/i2c-rtl9300.c +++ b/target/linux/realtek/files-5.15/drivers/i2c/busses/i2c-rtl9300.c @@ -123,13 +123,12 @@ static int rtl9310_i2c_config_xfer(struct rtl9300_i2c *i2c, u16 addr, u16 len) static int i2c_read(void __iomem *r0, u8 *buf, int len) { - int i; - u32 v; - if (len > 16) return -EIO; - for (i = 0; i < len; i++) { + for (int i = 0; i < len; i++) { + u32 v; + if (i % 4 == 0) v = readl(r0 + i); buf[i] = v; @@ -141,13 +140,12 @@ static int i2c_read(void __iomem *r0, u8 *buf, int len) static int i2c_write(void __iomem *r0, u8 *buf, int len) { - u32 v; - int i; - if (len > 16) return -EIO; - for (i = 0; i < len; i++) { + for (int i = 0; i < len; i++) { + u32 v; + if (! (i % 4)) v = 0; v <<= 8; diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/common.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/common.c index 2f68a0a1cef..1fa92ae220e 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/common.c +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/common.c @@ -84,9 +84,7 @@ static struct table_reg rtl838x_tbl_regs[] = { void rtl_table_init(void) { - int i; - - for (i = 0; i < RTL_TBL_END; i++) + for (int i = 0; i < RTL_TBL_END; i++) mutex_init(&rtl838x_tbl_regs[i].lock); } @@ -593,7 +591,7 @@ int rtl83xx_l2_nexthop_add(struct rtl838x_switch_priv *priv, struct rtl83xx_next struct rtl838x_l2_entry e; u64 seed = priv->r->l2_hash_seed(nh->mac, nh->rvid); u32 key = priv->r->l2_hash_key(priv, seed); - int i, idx = -1; + int idx = -1; u64 entry; pr_debug("%s searching for %08llx vid %d with key %d, seed: %016llx\n", @@ -604,7 +602,7 @@ int rtl83xx_l2_nexthop_add(struct rtl838x_switch_priv *priv, struct rtl83xx_next e.port = nh->port; /* Loop over all entries in the hash-bucket and over the second block on 93xx SoCs */ - for (i = 0; i < priv->l2_bucket_size; i++) { + for (int i = 0; i < priv->l2_bucket_size; i++) { entry = priv->r->read_l2_entry_using_hash(key, i, &e); if (!e.valid || ((entry & 0x0fffffffffffffffULL) == seed)) { @@ -738,8 +736,6 @@ out: */ int rtl83xx_port_is_under(const struct net_device * dev, struct rtl838x_switch_priv *priv) { - int i; - /* TODO: On 5.12: * if(!dsa_slave_dev_check(dev)) { * netdev_info(dev, "%s: not a DSA device.\n", __func__); @@ -747,7 +743,7 @@ int rtl83xx_port_is_under(const struct net_device * dev, struct rtl838x_switch_p * } */ - for (i = 0; i < priv->cpu_port; i++) { + for (int i = 0; i < priv->cpu_port; i++) { if (!priv->ports[i].dp) continue; if (priv->ports[i].dp->slave == dev) @@ -1087,11 +1083,11 @@ static int rtl83xx_fib4_del(struct rtl838x_switch_priv *priv, */ static int rtl83xx_alloc_router_mac(struct rtl838x_switch_priv *priv, u64 mac) { - int i, free_mac = -1; + int free_mac = -1; struct rtl93xx_rt_mac m; mutex_lock(&priv->reg_mutex); - for (i = 0; i < MAX_ROUTER_MACS; i++) { + for (int i = 0; i < MAX_ROUTER_MACS; i++) { priv->r->get_l3_router_mac(i, &m); if (free_mac < 0 && !m.valid) { free_mac = i; @@ -1127,12 +1123,12 @@ static int rtl83xx_alloc_router_mac(struct rtl838x_switch_priv *priv, u64 mac) static int rtl83xx_alloc_egress_intf(struct rtl838x_switch_priv *priv, u64 mac, int vlan) { - int i, free_mac = -1; + int free_mac = -1; struct rtl838x_l3_intf intf; u64 m; mutex_lock(&priv->reg_mutex); - for (i = 0; i < MAX_SMACS; i++) { + for (int i = 0; i < MAX_SMACS; i++) { m = priv->r->get_l3_egress_mac(L3_EGRESS_DMACS + i); if (free_mac < 0 && !m) { free_mac = i; @@ -1452,7 +1448,7 @@ static int rtl83xx_fib_event(struct notifier_block *this, unsigned long event, v static int __init rtl83xx_sw_probe(struct platform_device *pdev) { - int err = 0, i; + int err = 0; struct rtl838x_switch_priv *priv; struct device *dev = &pdev->dev; u64 bpdu_mask; @@ -1568,7 +1564,7 @@ static int __init rtl83xx_sw_probe(struct platform_device *pdev) * dsa_switch_tree, the tree is built when the switch * is registered by dsa_register_switch */ - for (i = 0; i <= priv->cpu_port; i++) + for (int i = 0; i <= priv->cpu_port; i++) priv->ports[i].dp = dsa_to_port(priv->ds, i); /* Enable link and media change interrupts. Are the SERDES masks needed? */ @@ -1613,7 +1609,7 @@ static int __init rtl83xx_sw_probe(struct platform_device *pdev) priv->r->l3_setup(priv); /* Clear all destination ports for mirror groups */ - for (i = 0; i < 4; i++) + for (int i = 0; i < 4; i++) priv->mirror_group_ports[i] = -1; /* Register netdevice event callback to catch changes in link aggregation groups */ diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/debugfs.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/debugfs.c index 0ad4872c387..f46833f6f7b 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/debugfs.c +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/debugfs.c @@ -214,7 +214,6 @@ static ssize_t drop_counter_read(struct file *filp, char __user *buffer, size_t loff_t *ppos) { struct rtl838x_switch_priv *priv = filp->private_data; - int i; const char **d; u32 v; char *buf; @@ -248,7 +247,7 @@ static ssize_t drop_counter_read(struct file *filp, char __user *buffer, size_t if (!buf) return -ENOMEM; - for (i = 0; i < num; i++) { + for (int i = 0; i < num; i++) { v = sw_r32(offset + (i << 2)) & 0xffff; n += sprintf(buf + n, "%s: %d\n", d[i], v); } @@ -274,7 +273,6 @@ static void l2_table_print_entry(struct seq_file *m, struct rtl838x_switch_priv struct rtl838x_l2_entry *e) { u64 portmask; - int i; if (e->type == L2_UNICAST) { seq_puts(m, "L2_UNICAST\n"); @@ -315,7 +313,7 @@ static void l2_table_print_entry(struct seq_file *m, struct rtl838x_switch_priv portmask = priv->r->read_mcast_pmask(e->mc_portmask_index); seq_printf(m, " index %u ports", e->mc_portmask_index); - for (i = 0; i < 64; i++) { + for (int i = 0; i < 64; i++) { if (portmask & BIT_ULL(i)) seq_printf(m, " %d", i); } @@ -329,11 +327,11 @@ static int l2_table_show(struct seq_file *m, void *v) { struct rtl838x_switch_priv *priv = m->private; struct rtl838x_l2_entry e; - int i, bucket, index; + int bucket, index; mutex_lock(&priv->reg_mutex); - for (i = 0; i < priv->fib_entries; i++) { + for (int i = 0; i < priv->fib_entries; i++) { bucket = i >> 2; index = i & 0x3; priv->r->read_l2_entry_using_hash(bucket, index, &e); @@ -348,7 +346,7 @@ static int l2_table_show(struct seq_file *m, void *v) cond_resched(); } - for (i = 0; i < 64; i++) { + for (int i = 0; i < 64; i++) { priv->r->read_cam(i, &e); if (!e.valid) @@ -517,9 +515,6 @@ static int rtl838x_dbgfs_port_init(struct dentry *parent, struct rtl838x_switch_ static int rtl838x_dbgfs_leds(struct dentry *parent, struct rtl838x_switch_priv *priv) { struct dentry *led_dir; - int p; - char led_sw_p_ctrl_name[20]; - char port_led_name[20]; led_dir = debugfs_create_dir("led", parent); @@ -540,20 +535,24 @@ static int rtl838x_dbgfs_leds(struct dentry *parent, struct rtl838x_switch_priv (u32 *)(RTL838X_SW_BASE + RTL8380_LED1_SW_P_EN_CTRL)); debugfs_create_x32("led2_sw_p_en_ctrl", 0644, led_dir, (u32 *)(RTL838X_SW_BASE + RTL8380_LED2_SW_P_EN_CTRL)); - for (p = 0; p < 28; p++) { + for (int p = 0; p < 28; p++) { + char led_sw_p_ctrl_name[20]; + snprintf(led_sw_p_ctrl_name, sizeof(led_sw_p_ctrl_name), "led_sw_p_ctrl.%02d", p); debugfs_create_x32(led_sw_p_ctrl_name, 0644, led_dir, (u32 *)(RTL838X_SW_BASE + RTL8380_LED_SW_P_CTRL(p))); } } else if (priv->family_id == RTL8390_FAMILY_ID) { + char port_led_name[20]; + debugfs_create_x32("led_glb_ctrl", 0644, led_dir, (u32 *)(RTL838X_SW_BASE + RTL8390_LED_GLB_CTRL)); debugfs_create_x32("led_set_2_3", 0644, led_dir, (u32 *)(RTL838X_SW_BASE + RTL8390_LED_SET_2_3_CTRL)); debugfs_create_x32("led_set_0_1", 0644, led_dir, (u32 *)(RTL838X_SW_BASE + RTL8390_LED_SET_0_1_CTRL)); - for (p = 0; p < 4; p++) { + for (int p = 0; p < 4; p++) { snprintf(port_led_name, sizeof(port_led_name), "led_copr_set_sel.%1d", p); debugfs_create_x32(port_led_name, 0644, led_dir, (u32 *)(RTL838X_SW_BASE + RTL8390_LED_COPR_SET_SEL_CTRL(p << 4))); @@ -575,12 +574,12 @@ static int rtl838x_dbgfs_leds(struct dentry *parent, struct rtl838x_switch_priv (u32 *)(RTL838X_SW_BASE + RTL8390_LED_COMBO_CTRL(32))); debugfs_create_x32("led_sw_ctrl", 0644, led_dir, (u32 *)(RTL838X_SW_BASE + RTL8390_LED_SW_CTRL)); - for (p = 0; p < 5; p++) { + for (int p = 0; p < 5; p++) { snprintf(port_led_name, sizeof(port_led_name), "led_sw_p_en_ctrl.%1d", p); debugfs_create_x32(port_led_name, 0644, led_dir, (u32 *)(RTL838X_SW_BASE + RTL8390_LED_SW_P_EN_CTRL(p * 10))); } - for (p = 0; p < 28; p++) { + for (int p = 0; p < 28; p++) { snprintf(port_led_name, sizeof(port_led_name), "led_sw_p_ctrl.%02d", p); debugfs_create_x32(port_led_name, 0644, led_dir, (u32 *)(RTL838X_SW_BASE + RTL8390_LED_SW_P_CTRL(p))); @@ -595,7 +594,7 @@ void rtl838x_dbgfs_init(struct rtl838x_switch_priv *priv) struct dentry *port_dir; struct dentry *mirror_dir; struct debugfs_regset32 *port_ctrl_regset; - int ret, i; + int ret; char lag_name[10]; char mirror_name[10]; @@ -610,7 +609,7 @@ void rtl838x_dbgfs_init(struct rtl838x_switch_priv *priv) (u32 *)(RTL838X_SW_BASE + RTL838X_MODEL_NAME_INFO)); /* Create one directory per port */ - for (i = 0; i < priv->cpu_port; i++) { + for (int i = 0; i < priv->cpu_port; i++) { if (priv->ports[i].phy) { ret = rtl838x_dbgfs_port_init(rtl838x_dir, priv, i); if (ret) @@ -633,7 +632,7 @@ void rtl838x_dbgfs_init(struct rtl838x_switch_priv *priv) debugfs_create_u8("id", 0444, port_dir, &priv->cpu_port); /* Create entries for LAGs */ - for (i = 0; i < priv->n_lags; i++) { + for (int i = 0; i < priv->n_lags; i++) { snprintf(lag_name, sizeof(lag_name), "lag.%02d", i); if (priv->family_id == RTL8380_FAMILY_ID) debugfs_create_x32(lag_name, 0644, rtl838x_dir, @@ -644,7 +643,7 @@ void rtl838x_dbgfs_init(struct rtl838x_switch_priv *priv) } /* Create directories for mirror groups */ - for (i = 0; i < 4; i++) { + for (int i = 0; i < 4; i++) { snprintf(mirror_name, sizeof(mirror_name), "mirror.%1d", i); mirror_dir = debugfs_create_dir(mirror_name, rtl838x_dir); if (priv->family_id == RTL8380_FAMILY_ID) { diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/dsa.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/dsa.c index c940ffb9b97..83a0441ce27 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/dsa.c +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/dsa.c @@ -26,12 +26,11 @@ static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv) static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv) { - int i; u64 v = 0; msleep(1000); /* Enable all ports with a PHY, including the SFP-ports */ - for (i = 0; i < priv->cpu_port; i++) { + for (int i = 0; i < priv->cpu_port; i++) { if (priv->ports[i].phy) v |= BIT_ULL(i); } @@ -113,7 +112,6 @@ static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds, static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv) { struct rtl838x_vlan_info info; - int i; pr_info("In %s\n", __func__); @@ -134,11 +132,11 @@ static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv) } /* Initialize all vlans 0-4095 */ - for (i = 0; i < MAX_VLANS; i ++) + for (int i = 0; i < MAX_VLANS; i ++) priv->r->vlan_set_tagged(i, &info); /* reset PVIDs; defaults to 1 on reset */ - for (i = 0; i <= priv->ds->num_ports; i++) { + for (int i = 0; i <= priv->ds->num_ports; i++) { priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_INNER, 0); priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_OUTER, 0); priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_INNER, PBVLAN_MODE_UNTAG_AND_PRITAG); @@ -146,15 +144,13 @@ static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv) } /* Set forwarding action based on inner VLAN tag */ - for (i = 0; i < priv->cpu_port; i++) + for (int i = 0; i < priv->cpu_port; i++) priv->r->vlan_fwd_on_inner(i, true); } static void rtl83xx_setup_bpdu_traps(struct rtl838x_switch_priv *priv) { - int i; - - for (i = 0; i < priv->cpu_port; i++) + for (int i = 0; i < priv->cpu_port; i++) priv->r->set_receive_management_action(i, BPDU, COPY2CPU); } @@ -170,7 +166,6 @@ static void rtl83xx_port_set_salrn(struct rtl838x_switch_priv *priv, static int rtl83xx_setup(struct dsa_switch *ds) { - int i; struct rtl838x_switch_priv *priv = ds->priv; u64 port_bitmap = BIT_ULL(priv->cpu_port); @@ -179,7 +174,7 @@ static int rtl83xx_setup(struct dsa_switch *ds) /* Disable MAC polling the PHY so that we can start configuration */ priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl); - for (i = 0; i < ds->num_ports; i++) + for (int i = 0; i < ds->num_ports; i++) priv->ports[i].enable = false; priv->ports[priv->cpu_port].enable = true; @@ -187,7 +182,7 @@ static int rtl83xx_setup(struct dsa_switch *ds) /* Setting bit j in register RTL838X_PORT_ISO_CTRL(i) allows * traffic from source port i to destination port j */ - for (i = 0; i < priv->cpu_port; i++) { + for (int i = 0; i < priv->cpu_port; i++) { if (priv->ports[i].phy) { priv->r->set_port_reg_be(BIT_ULL(priv->cpu_port) | BIT_ULL(i), priv->r->port_iso_ctrl(i)); @@ -233,7 +228,6 @@ static int rtl83xx_setup(struct dsa_switch *ds) static int rtl93xx_setup(struct dsa_switch *ds) { - int i; struct rtl838x_switch_priv *priv = ds->priv; u32 port_bitmap = BIT(priv->cpu_port); @@ -249,11 +243,11 @@ static int rtl93xx_setup(struct dsa_switch *ds) } /* Disable all ports except CPU port */ - for (i = 0; i < ds->num_ports; i++) + for (int i = 0; i < ds->num_ports; i++) priv->ports[i].enable = false; priv->ports[priv->cpu_port].enable = true; - for (i = 0; i < priv->cpu_port; i++) { + for (int i = 0; i < priv->cpu_port; i++) { if (priv->ports[i].phy) { priv->r->traffic_set(i, BIT_ULL(priv->cpu_port) | BIT_ULL(i)); port_bitmap |= BIT_ULL(i); @@ -932,12 +926,10 @@ static void rtl93xx_phylink_mac_link_up(struct dsa_switch *ds, int port, static void rtl83xx_get_strings(struct dsa_switch *ds, int port, u32 stringset, u8 *data) { - int i; - if (stringset != ETH_SS_STATS) return; - for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) + for (int i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) strncpy(data + i * ETH_GSTRING_LEN, rtl83xx_mib[i].name, ETH_GSTRING_LEN); } @@ -947,10 +939,9 @@ static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port, { struct rtl838x_switch_priv *priv = ds->priv; const struct rtl83xx_mib_desc *mib; - int i; u64 h; - for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) { + for (int i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) { mib = &rtl83xx_mib[i]; data[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset); @@ -1026,9 +1017,7 @@ static u64 rtl83xx_mc_group_del_port(struct rtl838x_switch_priv *priv, int mc_gr static void store_mcgroups(struct rtl838x_switch_priv *priv, int port) { - int mc_group; - - for (mc_group = 0; mc_group < MAX_MC_GROUPS; mc_group++) { + for (int mc_group = 0; mc_group < MAX_MC_GROUPS; mc_group++) { u64 portmask = priv->r->read_mcast_pmask(mc_group); if (portmask & BIT_ULL(port)) { priv->mc_group_saves[mc_group] = port; @@ -1039,9 +1028,7 @@ static void store_mcgroups(struct rtl838x_switch_priv *priv, int port) static void load_mcgroups(struct rtl838x_switch_priv *priv, int port) { - int mc_group; - - for (mc_group = 0; mc_group < MAX_MC_GROUPS; mc_group++) { + for (int mc_group = 0; mc_group < MAX_MC_GROUPS; mc_group++) { if (priv->mc_group_saves[mc_group] == port) { rtl83xx_mc_group_add_port(priv, mc_group, port); priv->mc_group_saves[mc_group] = -1; @@ -1182,7 +1169,6 @@ static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port, { struct rtl838x_switch_priv *priv = ds->priv; u64 port_bitmap = BIT_ULL(priv->cpu_port), v; - int i; pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap); @@ -1192,7 +1178,7 @@ static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port, } mutex_lock(&priv->reg_mutex); - for (i = 0; i < ds->num_ports; i++) { + for (int i = 0; i < ds->num_ports; i++) { /* Add this port to the port matrix of the other ports in the * same bridge. If the port is disabled, port matrix is kept * and not being setup until the port becomes enabled. @@ -1227,11 +1213,10 @@ static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port, { struct rtl838x_switch_priv *priv = ds->priv; u64 port_bitmap = BIT_ULL(priv->cpu_port), v; - int i; pr_debug("%s %x: %d", __func__, (u32)priv, port); mutex_lock(&priv->reg_mutex); - for (i = 0; i < ds->num_ports; i++) { + for (int i = 0; i < ds->num_ports; i++) { /* Remove this port from the port matrix of the other ports * in the same bridge. If the port is disabled, port matrix * is kept and not being setup until the port becomes enabled. @@ -1584,13 +1569,13 @@ static void rtl83xx_setup_l2_mc_entry(struct rtl838x_l2_entry *e, int vid, u64 m static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv *priv, u64 seed, bool must_exist, struct rtl838x_l2_entry *e) { - int i, idx = -1; + int idx = -1; u32 key = priv->r->l2_hash_key(priv, seed); u64 entry; pr_debug("%s: using key %x, for seed %016llx\n", __func__, key, seed); /* Loop over all entries in the hash-bucket and over the second block on 93xx SoCs */ - for (i = 0; i < priv->l2_bucket_size; i++) { + for (int i = 0; i < priv->l2_bucket_size; i++) { entry = priv->r->read_l2_entry_using_hash(key, i, e); pr_debug("valid %d, mac %016llx\n", e->valid, ether_addr_to_u64(&e->mac[0])); if (must_exist && !e->valid) @@ -1612,10 +1597,10 @@ static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv *priv, u64 seed static int rtl83xx_find_l2_cam_entry(struct rtl838x_switch_priv *priv, u64 seed, bool must_exist, struct rtl838x_l2_entry *e) { - int i, idx = -1; + int idx = -1; u64 entry; - for (i = 0; i < 64; i++) { + for (int i = 0; i < 64; i++) { entry = priv->r->read_cam(i, e); if (!must_exist && !e->valid) { if (idx < 0) /* First empty entry? */ @@ -1715,11 +1700,10 @@ static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port, { struct rtl838x_l2_entry e; struct rtl838x_switch_priv *priv = ds->priv; - int i; mutex_lock(&priv->reg_mutex); - for (i = 0; i < priv->fib_entries; i++) { + for (int i = 0; i < priv->fib_entries; i++) { priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e); if (!e.valid) @@ -1732,7 +1716,7 @@ static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port, cond_resched(); } - for (i = 0; i < 64; i++) { + for (int i = 0; i < 64; i++) { priv->r->read_cam(i, &e); if (!e.valid) diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/qos.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/qos.c index 59d043581b1..28976412aac 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/qos.c +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/qos.c @@ -93,8 +93,6 @@ void rtl838x_egress_rate_queue_limit(struct rtl838x_switch_priv *priv, int port, static void rtl838x_rate_control_init(struct rtl838x_switch_priv *priv) { - int i; - pr_info("Enabling Storm control\n"); /* TICK_PERIOD_PPS */ if (priv->id == 0x8380) @@ -120,7 +118,7 @@ static void rtl838x_rate_control_init(struct rtl838x_switch_priv *priv) /* Enable storm control on all ports with a PHY and limit rates, * for UC and MC for both known and unknown addresses */ - for (i = 0; i < priv->cpu_port; i++) { + for (int i = 0; i < priv->cpu_port; i++) { if (priv->ports[i].phy) { sw_w32((1 << 18) | 0x8000, RTL838X_STORM_CTRL_PORT_UC(i)); sw_w32((1 << 18) | 0x8000, RTL838X_STORM_CTRL_PORT_MC(i)); @@ -222,8 +220,6 @@ void rtl839x_egress_rate_queue_limit(struct rtl838x_switch_priv *priv, int port, static void rtl839x_rate_control_init(struct rtl838x_switch_priv *priv) { - int p, q; - pr_info("%s: enabling rate control\n", __func__); /* Tick length and token size settings for SoC with 250MHz, * RTL8350 family would use 50MHz @@ -256,7 +252,7 @@ static void rtl839x_rate_control_init(struct rtl838x_switch_priv *priv) * for UC, MC and BC * For 1G port, the minimum burst rate is 1700, maximum 65535, * For 10G ports it is 2650 and 1048575 respectively */ - for (p = 0; p < priv->cpu_port; p++) { + for (int p = 0; p < priv->cpu_port; p++) { if (priv->ports[p].phy && !priv->ports[p].is10G) { sw_w32_mask(0xffff, 0x8000, RTL839X_STORM_CTRL_PORT_UC_1(p)); sw_w32_mask(0xffff, 0x8000, RTL839X_STORM_CTRL_PORT_MC_1(p)); @@ -265,7 +261,7 @@ static void rtl839x_rate_control_init(struct rtl838x_switch_priv *priv) } /* Setup ingress/egress per-port rate control */ - for (p = 0; p < priv->cpu_port; p++) { + for (int p = 0; p < priv->cpu_port; p++) { if (!priv->ports[p].phy) continue; @@ -275,7 +271,7 @@ static void rtl839x_rate_control_init(struct rtl838x_switch_priv *priv) rtl839x_set_egress_rate(priv, p, 62500); /* 1GB/s */ /* Setup queues: all RTL83XX SoCs have 8 queues, maximum rate */ - for (q = 0; q < 8; q++) + for (int q = 0; q < 8; q++) rtl839x_egress_rate_queue_limit(priv, p, q, 0xfffff); if (priv->ports[p].is10G) { @@ -295,22 +291,19 @@ static void rtl839x_rate_control_init(struct rtl838x_switch_priv *priv) void rtl838x_setup_prio2queue_matrix(int *min_queues) { - int i; u32 v; pr_info("Current Intprio2queue setting: %08x\n", sw_r32(RTL838X_QM_INTPRI2QID_CTRL)); - for (i = 0; i < MAX_PRIOS; i++) + for (int i = 0; i < MAX_PRIOS; i++) v |= i << (min_queues[i] * 3); sw_w32(v, RTL838X_QM_INTPRI2QID_CTRL); } void rtl839x_setup_prio2queue_matrix(int *min_queues) { - int i, q; - pr_info("Current Intprio2queue setting: %08x\n", sw_r32(RTL839X_QM_INTPRI2QID_CTRL(0))); - for (i = 0; i < MAX_PRIOS; i++) { - q = min_queues[i]; + for (int i = 0; i < MAX_PRIOS; i++) { + int q = min_queues[i]; sw_w32(i << (q * 3), RTL839X_QM_INTPRI2QID_CTRL(q)); } } @@ -320,11 +313,10 @@ void rtl83xx_setup_prio2queue_cpu_matrix(int *max_queues) { int reg = soc_info.family == RTL8380_FAMILY_ID ? RTL838X_QM_PKT2CPU_INTPRI_MAP : RTL839X_QM_PKT2CPU_INTPRI_MAP; - int i; u32 v; pr_info("QM_PKT2CPU_INTPRI_MAP: %08x\n", sw_r32(reg)); - for (i = 0; i < MAX_PRIOS; i++) + for (int i = 0; i < MAX_PRIOS; i++) v |= max_queues[i] << (i * 3); sw_w32(v, reg); } @@ -432,17 +424,16 @@ void rtl839x_set_scheduling_algorithm(struct rtl838x_switch_priv *priv, int port void rtl839x_set_scheduling_queue_weights(struct rtl838x_switch_priv *priv, int port, int *queue_weights) { - int i, lsb, low_byte, start_bit, high_mask; - mutex_lock(&priv->reg_mutex); rtl839x_read_scheduling_table(port); - for (i = 0; i < 8; i++) { - lsb = 48 + i * 8; - low_byte = 8 - (lsb >> 5); - start_bit = lsb - (low_byte << 5); - high_mask = 0x3ff >> (32 - start_bit); + for (int i = 0; i < 8; i++) { + int lsb = 48 + i * 8; + int low_byte = 8 - (lsb >> 5); + int start_bit = lsb - (low_byte << 5); + int high_mask = 0x3ff >> (32 - start_bit); + sw_w32_mask(0x3ff << start_bit, (queue_weights[i] & 0x3ff) << start_bit, RTL839X_TBL_ACCESS_DATA_2(low_byte)); if (high_mask) @@ -456,7 +447,6 @@ void rtl839x_set_scheduling_queue_weights(struct rtl838x_switch_priv *priv, int void rtl838x_config_qos(void) { - int i, p; u32 v; pr_info("Setting up RTL838X QoS\n"); @@ -474,18 +464,18 @@ void rtl838x_config_qos(void) /* Set the inner and outer priority one-to-one to re-marked outer dot1p priority */ v = 0; - for (p = 0; p < 8; p++) + for (int p = 0; p < 8; p++) v |= p << (3 * p); sw_w32(v, RTL838X_RMK_OPRI_CTRL); sw_w32(v, RTL838X_RMK_IPRI_CTRL); v = 0; - for (p = 0; p < 8; p++) + for (int p = 0; p < 8; p++) v |= (dot1p_priority_remapping[p] & 0x7) << (p * 3); sw_w32(v, RTL838X_PRI_SEL_IPRI_REMAP); /* On all ports set scheduler type to WFQ */ - for (i = 0; i <= soc_info.cpu_port; i++) + for (int i = 0; i <= soc_info.cpu_port; i++) sw_w32(0, RTL838X_SCHED_P_TYPE_CTRL(i)); /* Enable egress scheduler for CPU-Port */ @@ -502,7 +492,6 @@ void rtl838x_config_qos(void) void rtl839x_config_qos(void) { - int port, p, q; u32 v; struct rtl838x_switch_priv *priv = switch_priv; @@ -510,13 +499,13 @@ void rtl839x_config_qos(void) pr_info("RTL839X_PRI_SEL_TBL_CTRL(i): %08x\n", sw_r32(RTL839X_PRI_SEL_TBL_CTRL(0))); rtl83xx_setup_default_prio2queue(); - for (port = 0; port < soc_info.cpu_port; port++) + for (int port = 0; port < soc_info.cpu_port; port++) sw_w32(7, RTL839X_QM_PORT_QNUM(port)); /* CPU-port gets queue number 7 */ sw_w32(7, RTL839X_QM_PORT_QNUM(soc_info.cpu_port)); - for (port = 0; port <= soc_info.cpu_port; port++) { + for (int port = 0; port <= soc_info.cpu_port; port++) { rtl83xx_set_ingress_priority(port, 0); rtl839x_set_scheduling_algorithm(priv, port, WEIGHTED_FAIR_QUEUE); rtl839x_set_scheduling_queue_weights(priv, port, default_queue_weights); @@ -526,7 +515,7 @@ void rtl839x_config_qos(void) /* Remap dot1p priorities to internal priority, for this the outer tag needs be re-marked */ v = 0; - for (p = 0; p < 8; p++) + for (int p = 0; p < 8; p++) v |= (dot1p_priority_remapping[p] & 0x7) << (p * 3); sw_w32(v, RTL839X_PRI_SEL_IPRI_REMAP); @@ -551,7 +540,7 @@ void rtl839x_config_qos(void) /* Set queue-based congestion avoidance properties, register fields are as * for forward RTL839X_WRED_PORT_THR_CTRL */ - for (q = 0; q < 8; q++) { + for (int q = 0; q < 8; q++) { sw_w32(255 << 24 | 78 << 12 | 68, RTL839X_WRED_QUEUE_THR_CTRL(q, 0)); sw_w32(255 << 24 | 74 << 12 | 64, RTL839X_WRED_QUEUE_THR_CTRL(q, 0)); sw_w32(255 << 24 | 70 << 12 | 60, RTL839X_WRED_QUEUE_THR_CTRL(q, 0)); diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.c index 124cd564785..c1d6b0c554b 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.c +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.c @@ -116,10 +116,9 @@ static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] void rtl838x_print_matrix(void) { unsigned volatile int *ptr8; - int i; ptr8 = RTL838X_SW_BASE + RTL838X_PORT_ISO_CTRL(0); - for (i = 0; i < 28; i += 8) + for (int i = 0; i < 28; i += 8) pr_debug("> %8x %8x %8x %8x %8x %8x %8x %8x\n", ptr8[i + 0], ptr8[i + 1], ptr8[i + 2], ptr8[i + 3], ptr8[i + 4], ptr8[i + 5], ptr8[i + 6], ptr8[i + 7]); @@ -393,10 +392,9 @@ static u64 rtl838x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2 u32 r[3]; struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 0); /* Access L2 Table 0 */ u32 idx = (0 << 14) | (hash << 2) | pos; /* Search SRAM, with hash and at pos in bucket */ - int i; rtl_table_read(q, idx); - for (i = 0; i < 3; i++) + for (int i = 0; i < 3; i++) r[i] = sw_r32(rtl_table_data(q, i)); rtl_table_release(q); @@ -412,13 +410,12 @@ static void rtl838x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_ { u32 r[3]; struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 0); - int i; u32 idx = (0 << 14) | (hash << 2) | pos; /* Access SRAM, with hash and at pos in bucket */ rtl838x_fill_l2_row(r, e); - for (i = 0; i < 3; i++) + for (int i = 0; i < 3; i++) sw_w32(r[i], rtl_table_data(q, i)); rtl_table_write(q, idx); @@ -429,10 +426,9 @@ static u64 rtl838x_read_cam(int idx, struct rtl838x_l2_entry *e) { u32 r[3]; struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 1); /* Access L2 Table 1 */ - int i; rtl_table_read(q, idx); - for (i = 0; i < 3; i++) + for (int i = 0; i < 3; i++) r[i] = sw_r32(rtl_table_data(q, i)); rtl_table_release(q); @@ -451,11 +447,10 @@ static void rtl838x_write_cam(int idx, struct rtl838x_l2_entry *e) { u32 r[3]; struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 1); /* Access L2 Table 1 */ - int i; rtl838x_fill_l2_row(r, e); - for (i = 0; i < 3; i++) + for (int i = 0; i < 3; i++) sw_w32(r[i], rtl_table_data(q, i)); rtl_table_write(q, idx); @@ -550,26 +545,24 @@ static void rtl838x_enable_bcast_flood(int port, bool enable) static void rtl838x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]) { - int i; u32 cmd = 1 << 15 | /* Execute cmd */ 1 << 14 | /* Read */ 2 << 12 | /* Table type 0b10 */ (msti & 0xfff); priv->r->exec_tbl0_cmd(cmd); - for (i = 0; i < 2; i++) + for (int i = 0; i < 2; i++) port_state[i] = sw_r32(priv->r->tbl_access_data_0(i)); } static void rtl838x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]) { - int i; u32 cmd = 1 << 15 | /* Execute cmd */ 0 << 14 | /* Write */ 2 << 12 | /* Table type 0b10 */ (msti & 0xfff); - for (i = 0; i < 2; i++) + for (int i = 0; i < 2; i++) sw_w32(port_state[i], priv->r->tbl_access_data_0(i)); priv->r->exec_tbl0_cmd(cmd); } @@ -651,8 +644,6 @@ static int rtl838x_eee_port_ability(struct rtl838x_switch_priv *priv, static void rtl838x_init_eee(struct rtl838x_switch_priv *priv, bool enable) { - int i; - pr_info("Setting up EEE, state: %d\n", enable); sw_w32_mask(0x4, 0, RTL838X_SMI_GLB_CTRL); @@ -661,7 +652,7 @@ static void rtl838x_init_eee(struct rtl838x_switch_priv *priv, bool enable) sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL); /* Enable EEE MAC support on ports */ - for (i = 0; i < priv->cpu_port; i++) { + for (int i = 0; i < priv->cpu_port; i++) { if (priv->ports[i].phy) rtl838x_port_eee_set(priv, i, enable); } @@ -683,7 +674,6 @@ static void rtl838x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_fro int block_from = index_from / PIE_BLOCK_SIZE; int block_to = index_to / PIE_BLOCK_SIZE; u32 v = (index_from << 1)| (index_to << 12 ) | BIT(0); - int block; u32 block_state; pr_debug("%s: from %d to %d\n", __func__, index_from, index_to); @@ -693,7 +683,7 @@ static void rtl838x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_fro block_state = sw_r32(RTL838X_ACL_BLK_LOOKUP_CTRL); /* Make sure rule-lookup is disabled in the relevant blocks */ - for (block = block_from; block <= block_to; block++) { + for (int block = block_from; block <= block_to; block++) { if (block_state & BIT(block)) sw_w32(block_state & (~BIT(block)), RTL838X_ACL_BLK_LOOKUP_CTRL); } @@ -706,7 +696,7 @@ static void rtl838x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_fro } while (sw_r32(RTL838X_ACL_CLR_CTRL) & BIT(0)); /* Re-enable rule lookup */ - for (block = block_from; block <= block_to; block++) { + for (int block = block_from; block <= block_to; block++) { if (!(block_state & BIT(block))) sw_w32(block_state | BIT(block), RTL838X_ACL_BLK_LOOKUP_CTRL); } @@ -723,13 +713,9 @@ static void rtl838x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_fro */ static void rtl838x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[]) { - int i; - enum template_field_id field_type; - u16 data, data_m; - - for (i = 0; i < N_FIXED_FIELDS; i++) { - field_type = t[i]; - data = data_m = 0; + for (int i = 0; i < N_FIXED_FIELDS; i++) { + enum template_field_id field_type = t[i]; + u16 data = 0, data_m = 0; switch (field_type) { case TEMPLATE_FIELD_SPM0: @@ -884,11 +870,10 @@ static void rtl838x_write_pie_templated(u32 r[], struct pie_rule *pr, enum templ */ static void rtl838x_read_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[]) { - int i; - enum template_field_id field_type; - u16 data, data_m; + for (int i = 0; i < N_FIXED_FIELDS; i++) { + enum template_field_id field_type = t[i]; + u16 data, data_m; - for (i = 0; i < N_FIXED_FIELDS; i++) { field_type = t[i]; if (!(i % 2)) { data = r[5 - i / 2]; @@ -1321,13 +1306,12 @@ static int rtl838x_pie_rule_read(struct rtl838x_switch_priv *priv, int idx, stru /* Read IACL table (1) via register 0 */ struct table_reg *q = rtl_table_get(RTL8380_TBL_0, 1); u32 r[18]; - int i; int block = idx / PIE_BLOCK_SIZE; u32 t_select = sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block)); memset(pr, 0, sizeof(*pr)); rtl_table_read(q, idx); - for (i = 0; i < 18; i++) + for (int i = 0; i < 18; i++) r[i] = sw_r32(rtl_table_data(q, i)); rtl_table_release(q); @@ -1351,13 +1335,13 @@ static int rtl838x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, str /* Access IACL table (1) via register 0 */ struct table_reg *q = rtl_table_get(RTL8380_TBL_0, 1); u32 r[18]; - int i, err = 0; + int err = 0; int block = idx / PIE_BLOCK_SIZE; u32 t_select = sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block)); pr_debug("%s: %d, t_select: %08x\n", __func__, idx, t_select); - for (i = 0; i < 18; i++) + for (int i = 0; i < 18; i++) r[i] = 0; if (!pr->valid) @@ -1375,7 +1359,7 @@ static int rtl838x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, str /* rtl838x_pie_rule_dump_raw(r); */ - for (i = 0; i < 18; i++) + for (int i = 0; i < 18; i++) sw_w32(r[i], rtl_table_data(q, i)); err_out: @@ -1387,10 +1371,9 @@ err_out: static bool rtl838x_pie_templ_has(int t, enum template_field_id field_type) { - int i; enum template_field_id ft; - for (i = 0; i < N_FIXED_FIELDS; i++) { + for (int i = 0; i < N_FIXED_FIELDS; i++) { ft = fixed_templates[t][i]; if (field_type == ft) return true; @@ -1443,7 +1426,7 @@ static int rtl838x_pie_verify_template(struct rtl838x_switch_priv *priv, static int rtl838x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rule *pr) { - int idx, block, j, t; + int idx, block, j; pr_debug("In %s\n", __func__); @@ -1451,7 +1434,7 @@ static int rtl838x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rul for (block = 0; block < priv->n_pie_blocks; block++) { for (j = 0; j < 3; j++) { - t = (sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block)) >> (j * 3)) & 0x7; + int t = (sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block)) >> (j * 3)) & 0x7; pr_debug("Testing block %d, template %d, template id %d\n", block, j, t); idx = rtl838x_pie_verify_template(priv, pr, t, block); if (idx >= 0) @@ -1496,17 +1479,16 @@ static void rtl838x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rul */ static void rtl838x_pie_init(struct rtl838x_switch_priv *priv) { - int i; u32 template_selectors; mutex_init(&priv->pie_mutex); /* Enable ACL lookup on all ports, including CPU_PORT */ - for (i = 0; i <= priv->cpu_port; i++) + for (int i = 0; i <= priv->cpu_port; i++) sw_w32(1, RTL838X_ACL_PORT_LOOKUP_CTRL(i)); /* Power on all PIE blocks */ - for (i = 0; i < priv->n_pie_blocks; i++) + for (int i = 0; i < priv->n_pie_blocks; i++) sw_w32_mask(0, BIT(i), RTL838X_ACL_BLK_PWR_CTRL); /* Include IPG in metering */ @@ -1522,12 +1504,12 @@ static void rtl838x_pie_init(struct rtl838x_switch_priv *priv) /* Enable predefined templates 0, 1 and 2 for even blocks */ template_selectors = 0 | (1 << 3) | (2 << 6); - for (i = 0; i < 6; i += 2) + for (int i = 0; i < 6; i += 2) sw_w32(template_selectors, RTL838X_ACL_BLK_TMPLTE_CTRL(i)); /* Enable predefined templates 0, 3 and 4 (IPv6 support) for odd blocks */ template_selectors = 0 | (3 << 3) | (4 << 6); - for (i = 1; i < priv->n_pie_blocks; i += 2) + for (int i = 1; i < priv->n_pie_blocks; i += 2) sw_w32(template_selectors, RTL838X_ACL_BLK_TMPLTE_CTRL(i)); /* Group each pair of physical blocks together to a logical block */ @@ -1782,13 +1764,12 @@ irqreturn_t rtl838x_switch_irq(int irq, void *dev_id) u32 status = sw_r32(RTL838X_ISR_GLB_SRC); u32 ports = sw_r32(RTL838X_ISR_PORT_LINK_STS_CHG); u32 link; - int i; /* Clear status */ sw_w32(ports, RTL838X_ISR_PORT_LINK_STS_CHG); pr_info("RTL8380 Link change: status: %x, ports %x\n", status, ports); - for (i = 0; i < 28; i++) { + for (int i = 0; i < 28; i++) { if (ports & BIT(i)) { link = sw_r32(RTL838X_MAC_LINK_STS); if (link & BIT(i)) diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl839x.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl839x.c index 01461edc4b6..06fdbd89361 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl839x.c +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl839x.c @@ -123,10 +123,9 @@ static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] void rtl839x_print_matrix(void) { volatile u64 *ptr9; - int i; ptr9 = RTL838X_SW_BASE + RTL839X_PORT_ISO_CTRL(0); - for (i = 0; i < 52; i += 4) + for (int i = 0; i < 52; i += 4) pr_debug("> %16llx %16llx %16llx %16llx\n", ptr9[i + 0], ptr9[i + 1], ptr9[i + 2], ptr9[i + 3]); pr_debug("CPU_PORT> %16llx\n", ptr9[52]); @@ -421,10 +420,9 @@ static u64 rtl839x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2 u32 r[3]; struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 0); u32 idx = (0 << 14) | (hash << 2) | pos; /* Search SRAM, with hash and at pos in bucket */ - int i; rtl_table_read(q, idx); - for (i = 0; i < 3; i++) + for (int i = 0; i < 3; i++) r[i] = sw_r32(rtl_table_data(q, i)); rtl_table_release(q); @@ -440,13 +438,12 @@ static void rtl839x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_ { u32 r[3]; struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 0); - int i; u32 idx = (0 << 14) | (hash << 2) | pos; /* Access SRAM, with hash and at pos in bucket */ rtl839x_fill_l2_row(r, e); - for (i = 0; i < 3; i++) + for (int i = 0; i < 3; i++) sw_w32(r[i], rtl_table_data(q, i)); rtl_table_write(q, idx); @@ -457,10 +454,9 @@ static u64 rtl839x_read_cam(int idx, struct rtl838x_l2_entry *e) { u32 r[3]; struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 1); /* Access L2 Table 1 */ - int i; rtl_table_read(q, idx); - for (i = 0; i < 3; i++) + for (int i = 0; i < 3; i++) r[i] = sw_r32(rtl_table_data(q, i)); rtl_table_release(q); @@ -479,11 +475,10 @@ static void rtl839x_write_cam(int idx, struct rtl838x_l2_entry *e) { u32 r[3]; struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 1); /* Access L2 Table 1 */ - int i; rtl839x_fill_l2_row(r, e); - for (i = 0; i < 3; i++) + for (int i = 0; i < 3; i++) sw_w32(r[i], rtl_table_data(q, i)); rtl_table_write(q, idx); @@ -601,13 +596,12 @@ irqreturn_t rtl839x_switch_irq(int irq, void *dev_id) u32 status = sw_r32(RTL839X_ISR_GLB_SRC); u64 ports = rtl839x_get_port_reg_le(RTL839X_ISR_PORT_LINK_STS_CHG); u64 link; - int i; /* Clear status */ rtl839x_set_port_reg_le(ports, RTL839X_ISR_PORT_LINK_STS_CHG); pr_debug("RTL8390 Link change: status: %x, ports %llx\n", status, ports); - for (i = 0; i < RTL839X_CPU_PORT; i++) { + for (int i = 0; i < RTL839X_CPU_PORT; i++) { if (ports & BIT_ULL(i)) { link = rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS); if (link & BIT_ULL(i)) @@ -831,25 +825,23 @@ void rtl839x_vlan_profile_dump(int profile) static void rtl839x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]) { - int i; u32 cmd = 1 << 16 | /* Execute cmd */ 0 << 15 | /* Read */ 5 << 12 | /* Table type 0b101 */ (msti & 0xfff); priv->r->exec_tbl0_cmd(cmd); - for (i = 0; i < 4; i++) + for (int i = 0; i < 4; i++) port_state[i] = sw_r32(priv->r->tbl_access_data_0(i)); } static void rtl839x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]) { - int i; u32 cmd = 1 << 16 | /* Execute cmd */ 1 << 15 | /* Write */ 5 << 12 | /* Table type 0b101 */ (msti & 0xfff); - for (i = 0; i < 4; i++) + for (int i = 0; i < 4; i++) sw_w32(port_state[i], priv->r->tbl_access_data_0(i)); priv->r->exec_tbl0_cmd(cmd); } @@ -908,8 +900,6 @@ int rtl839x_eee_port_ability(struct rtl838x_switch_priv *priv, struct ethtool_ee static void rtl839x_init_eee(struct rtl838x_switch_priv *priv, bool enable) { - int i; - pr_info("Setting up EEE, state: %d\n", enable); /* Set wake timer for TX and pause timer both to 0x21 */ @@ -920,7 +910,7 @@ static void rtl839x_init_eee(struct rtl838x_switch_priv *priv, bool enable) sw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_10G_CTRL); /* Setup EEE on all ports */ - for (i = 0; i < priv->cpu_port; i++) { + for (int i = 0; i < priv->cpu_port; i++) { if (priv->ports[i].phy) rtl839x_port_eee_set(priv, i, enable); } @@ -964,13 +954,9 @@ static int rtl839x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from */ static void rtl839x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[]) { - int i; - enum template_field_id field_type; - u16 data, data_m; - - for (i = 0; i < N_FIXED_FIELDS; i++) { - field_type = t[i]; - data = data_m = 0; + for (int i = 0; i < N_FIXED_FIELDS; i++) { + enum template_field_id field_type = t[i]; + u16 data = 0, data_m = 0; switch (field_type) { case TEMPLATE_FIELD_SPM0: @@ -1132,12 +1118,10 @@ static void rtl839x_write_pie_templated(u32 r[], struct pie_rule *pr, enum templ */ void rtl839x_read_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[]) { - int i; - enum template_field_id field_type; - u16 data, data_m; + for (int i = 0; i < N_FIXED_FIELDS; i++) { + enum template_field_id field_type = t[i]; + u16 data, data_m; - for (i = 0; i < N_FIXED_FIELDS; i++) { - field_type = t[i]; if (!(i % 2)) { data = r[5 - i / 2]; data_m = r[12 - i / 2]; @@ -1435,13 +1419,12 @@ static int rtl839x_pie_rule_read(struct rtl838x_switch_priv *priv, int idx, stru /* Read IACL table (2) via register 0 */ struct table_reg *q = rtl_table_get(RTL8380_TBL_0, 2); u32 r[17]; - int i; int block = idx / PIE_BLOCK_SIZE; u32 t_select = sw_r32(RTL839X_ACL_BLK_TMPLTE_CTRL(block)); memset(pr, 0, sizeof(*pr)); rtl_table_read(q, idx); - for (i = 0; i < 17; i++) + for (int i = 0; i < 17; i++) r[i] = sw_r32(rtl_table_data(q, i)); rtl_table_release(q); @@ -1465,13 +1448,12 @@ static int rtl839x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, str /* Access IACL table (2) via register 0 */ struct table_reg *q = rtl_table_get(RTL8390_TBL_0, 2); u32 r[17]; - int i; int block = idx / PIE_BLOCK_SIZE; u32 t_select = sw_r32(RTL839X_ACL_BLK_TMPLTE_CTRL(block)); pr_debug("%s: %d, t_select: %08x\n", __func__, idx, t_select); - for (i = 0; i < 17; i++) + for (int i = 0; i < 17; i++) r[i] = 0; if (!pr->valid) { @@ -1488,7 +1470,7 @@ static int rtl839x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, str /* rtl839x_pie_rule_dump_raw(r); */ - for (i = 0; i < 17; i++) + for (int i = 0; i < 17; i++) sw_w32(r[i], rtl_table_data(q, i)); rtl_table_write(q, idx); @@ -1499,11 +1481,8 @@ static int rtl839x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, str static bool rtl839x_pie_templ_has(int t, enum template_field_id field_type) { - int i; - enum template_field_id ft; - - for (i = 0; i < N_FIXED_FIELDS; i++) { - ft = fixed_templates[t][i]; + for (int i = 0; i < N_FIXED_FIELDS; i++) { + enum template_field_id ft = fixed_templates[t][i]; if (field_type == ft) return true; } @@ -1607,13 +1586,12 @@ static void rtl839x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rul static void rtl839x_pie_init(struct rtl838x_switch_priv *priv) { - int i; u32 template_selectors; mutex_init(&priv->pie_mutex); /* Power on all PIE blocks */ - for (i = 0; i < priv->n_pie_blocks; i++) + for (int i = 0; i < priv->n_pie_blocks; i++) sw_w32_mask(0, BIT(i), RTL839X_PS_ACL_PWR_CTRL); /* Set ingress and egress ACL blocks to 50/50: first Egress block is 9 */ @@ -1627,32 +1605,32 @@ static void rtl839x_pie_init(struct rtl838x_switch_priv *priv) /* Enable predefined templates 0, 1 for blocks 0-2 */ template_selectors = 0 | (1 << 3); - for (i = 0; i < 3; i++) + for (int i = 0; i < 3; i++) sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i)); /* Enable predefined templates 2, 3 for blocks 3-5 */ template_selectors = 2 | (3 << 3); - for (i = 3; i < 6; i++) + for (int i = 3; i < 6; i++) sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i)); /* Enable predefined templates 1, 4 for blocks 6-8 */ template_selectors = 2 | (3 << 3); - for (i = 6; i < 9; i++) + for (int i = 6; i < 9; i++) sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i)); /* Enable predefined templates 0, 1 for blocks 9-11 */ template_selectors = 0 | (1 << 3); - for (i = 9; i < 12; i++) + for (int i = 9; i < 12; i++) sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i)); /* Enable predefined templates 2, 3 for blocks 12-14 */ template_selectors = 2 | (3 << 3); - for (i = 12; i < 15; i++) + for (int i = 12; i < 15; i++) sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i)); /* Enable predefined templates 1, 4 for blocks 15-17 */ template_selectors = 2 | (3 << 3); - for (i = 15; i < 18; i++) + for (int i = 15; i < 18; i++) sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i)); } @@ -1733,7 +1711,6 @@ static void rtl839x_route_write(int idx, struct rtl83xx_route *rt) /* Configure the switch's own MAC addresses used when routing packets */ static void rtl839x_setup_port_macs(struct rtl838x_switch_priv *priv) { - int i; struct net_device *dev; u64 mac; @@ -1741,7 +1718,7 @@ static void rtl839x_setup_port_macs(struct rtl838x_switch_priv *priv) dev = priv->ports[priv->cpu_port].dp->slave; mac = ether_addr_to_u64(dev->dev_addr); - for (i = 0; i < 15; i++) { + for (int i = 0; i < 15; i++) { mac++; /* BUG: VRRP for testing */ sw_w32(mac >> 32, RTL839X_ROUTING_SA_CTRL + i * 8); sw_w32(mac, RTL839X_ROUTING_SA_CTRL + i * 8 + 4); diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl930x.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl930x.c index 384b33b0ba5..7e4f13fbad7 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl930x.c +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl930x.c @@ -118,10 +118,9 @@ static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] void rtl930x_print_matrix(void) { - int i; struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6); - for (i = 0; i < 29; i++) { + for (int i = 0; i < 29; i++) { rtl_table_read(r, i); pr_debug("> %08x\n", sw_r32(rtl_table_data(r, 0))); } @@ -287,27 +286,25 @@ static void rtl930x_l2_learning_setup(void) static void rtl930x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]) { - int i; u32 cmd = 1 << 17 | /* Execute cmd */ 0 << 16 | /* Read */ 4 << 12 | /* Table type 0b10 */ (msti & 0xfff); priv->r->exec_tbl0_cmd(cmd); - for (i = 0; i < 2; i++) + for (int i = 0; i < 2; i++) port_state[i] = sw_r32(RTL930X_TBL_ACCESS_DATA_0(i)); pr_debug("MSTI: %d STATE: %08x, %08x\n", msti, port_state[0], port_state[1]); } static void rtl930x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]) { - int i; u32 cmd = 1 << 17 | /* Execute cmd */ 1 << 16 | /* Write */ 4 << 12 | /* Table type 4 */ (msti & 0xfff); - for (i = 0; i < 2; i++) + for (int i = 0; i < 2; i++) sw_w32(port_state[i], RTL930X_TBL_ACCESS_DATA_0(i)); priv->r->exec_tbl0_cmd(cmd); } @@ -502,7 +499,6 @@ static u64 rtl930x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2 u32 r[3]; struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 0); u32 idx; - int i; u64 mac; u64 seed; @@ -523,7 +519,7 @@ static u64 rtl930x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2 pr_debug("%s: NOW hash %08x, pos: %d\n", __func__, hash, pos); rtl_table_read(q, idx); - for (i = 0; i < 3; i++) + for (int i = 0; i < 3; i++) r[i] = sw_r32(rtl_table_data(q, i)); rtl_table_release(q); @@ -553,7 +549,6 @@ static void rtl930x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_ u32 r[3]; struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 0); u32 idx = (0 << 14) | (hash << 2) | pos; /* Access SRAM, with hash and at pos in bucket */ - int i; pr_debug("%s: hash %d, pos %d\n", __func__, hash, pos); pr_debug("%s: index %d -> mac %02x:%02x:%02x:%02x:%02x:%02x\n", __func__, idx, @@ -561,7 +556,7 @@ static void rtl930x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_ rtl930x_fill_l2_row(r, e); - for (i = 0; i < 3; i++) + for (int i = 0; i < 3; i++) sw_w32(r[i], rtl_table_data(q, i)); rtl_table_write(q, idx); @@ -572,10 +567,9 @@ static u64 rtl930x_read_cam(int idx, struct rtl838x_l2_entry *e) { u32 r[3]; struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 1); - int i; rtl_table_read(q, idx); - for (i = 0; i < 3; i++) + for (int i = 0; i < 3; i++) r[i] = sw_r32(rtl_table_data(q, i)); rtl_table_release(q); @@ -592,11 +586,10 @@ static void rtl930x_write_cam(int idx, struct rtl838x_l2_entry *e) { u32 r[3]; struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 1); /* Access L2 Table 1 */ - int i; rtl930x_fill_l2_row(r, e); - for (i = 0; i < 3; i++) + for (int i = 0; i < 3; i++) sw_w32(r[i], rtl_table_data(q, i)); rtl_table_write(q, idx); @@ -676,10 +669,9 @@ void rtl930x_traffic_disable(int source, int dest) void rtl9300_dump_debug(void) { - int i; u16 r = RTL930X_STAT_PRVTE_DROP_COUNTER0; - for (i = 0; i < 10; i ++) { + for (int i = 0; i < 10; i ++) { pr_info("# %d %08x %08x %08x %08x %08x %08x %08x %08x\n", i * 8, sw_r32(r), sw_r32(r + 4), sw_r32(r + 8), sw_r32(r + 12), sw_r32(r + 16), sw_r32(r + 20), sw_r32(r + 24), sw_r32(r + 28)); @@ -699,12 +691,11 @@ irqreturn_t rtl930x_switch_irq(int irq, void *dev_id) struct dsa_switch *ds = dev_id; u32 ports = sw_r32(RTL930X_ISR_PORT_LINK_STS_CHG); u32 link; - int i; /* Clear status */ sw_w32(ports, RTL930X_ISR_PORT_LINK_STS_CHG); - for (i = 0; i < 28; i++) { + for (int i = 0; i < 28; i++) { if (ports & BIT(i)) { /* Read the register twice because of issues with latency at least * with the external RTL8226 PHY on the XGS1210 @@ -961,12 +952,10 @@ int rtl930x_eee_port_ability(struct rtl838x_switch_priv *priv, struct ethtool_ee static void rtl930x_init_eee(struct rtl838x_switch_priv *priv, bool enable) { - int i; - pr_info("Setting up EEE, state: %d\n", enable); /* Setup EEE on all ports */ - for (i = 0; i < priv->cpu_port; i++) { + for (int i = 0; i < priv->cpu_port; i++) { if (priv->ports[i].phy) rtl930x_port_eee_set(priv, i, enable); } @@ -1249,7 +1238,6 @@ static int rtl930x_route_lookup_hw(struct rtl83xx_route *rt) { u32 ip4_m, v; struct in6_addr ip6_m; - int i; if (rt->attr.type == 1 || rt->attr.type == 3) /* Hardware only supports UC routes */ return -1; @@ -1257,7 +1245,7 @@ static int rtl930x_route_lookup_hw(struct rtl83xx_route *rt) sw_w32_mask(0x3 << 19, rt->attr.type, RTL930X_L3_HW_LU_KEY_CTRL); if (rt->attr.type) { /* IPv6 */ rtl930x_net6_mask(rt->prefix_len, &ip6_m); - for (i = 0; i < 4; i++) + for (int i = 0; i < 4; i++) sw_w32(rt->dst_ip6.s6_addr32[0] & ip6_m.s6_addr32[0], RTL930X_L3_HW_LU_KEY_IP_CTRL + (i << 2)); } else { /* IPv4 */ @@ -1289,20 +1277,20 @@ static int rtl930x_route_lookup_hw(struct rtl83xx_route *rt) static int rtl930x_find_l3_slot(struct rtl83xx_route *rt, bool must_exist) { - int t, s, slot_width, algorithm, addr, idx; + int slot_width, algorithm, addr, idx; u32 hash; struct rtl83xx_route route_entry; /* IPv6 entries take up 3 slots */ slot_width = (rt->attr.type == 0) || (rt->attr.type == 2) ? 1 : 3; - for (t = 0; t < 2; t++) { + for (int t = 0; t < 2; t++) { algorithm = (sw_r32(RTL930X_L3_HOST_TBL_CTRL) >> (2 + t)) & 0x1; hash = rtl930x_l3_hash4(rt->dst_ip, algorithm, false); pr_debug("%s: table %d, algorithm %d, hash %04x\n", __func__, t, algorithm, hash); - for (s = 0; s < 6; s += slot_width) { + for (int s = 0; s < 6; s += slot_width) { addr = (t << 12) | ((hash & 0x1ff) << 3) | s; pr_debug("%s physical address %d\n", __func__, addr); idx = ((addr / 8) * 6) + (addr % 8); @@ -1539,13 +1527,9 @@ static void rtl930x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int inde */ static void rtl930x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[]) { - int i; - enum template_field_id field_type; - u16 data, data_m; - - for (i = 0; i < N_FIXED_FIELDS; i++) { - field_type = t[i]; - data = data_m = 0; + for (int i = 0; i < N_FIXED_FIELDS; i++) { + enum template_field_id field_type = t[i]; + u16 data = 0, data_m = 0; switch (field_type) { case TEMPLATE_FIELD_SPM0: @@ -1847,13 +1831,12 @@ static int rtl930x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, str /* Access IACL table (2) via register 0 */ struct table_reg *q = rtl_table_get(RTL9300_TBL_0, 2); u32 r[19]; - int i; int block = idx / PIE_BLOCK_SIZE; u32 t_select = sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block)); pr_debug("%s: %d, t_select: %08x\n", __func__, idx, t_select); - for (i = 0; i < 19; i++) + for (int i = 0; i < 19; i++) r[i] = 0; if (!pr->valid) { @@ -1870,7 +1853,7 @@ static int rtl930x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, str /* rtl930x_pie_rule_dump_raw(r); */ - for (i = 0; i < 19; i++) + for (int i = 0; i < 19; i++) sw_w32(r[i], rtl_table_data(q, i)); rtl_table_write(q, idx); @@ -1881,11 +1864,8 @@ static int rtl930x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, str static bool rtl930x_pie_templ_has(int t, enum template_field_id field_type) { - int i; - enum template_field_id ft; - - for (i = 0; i < N_FIXED_FIELDS; i++) { - ft = fixed_templates[t][i]; + for (int i = 0; i < N_FIXED_FIELDS; i++) { + enum template_field_id ft = fixed_templates[t][i]; if (field_type == ft) return true; } @@ -2016,14 +1996,13 @@ static void rtl930x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rul static void rtl930x_pie_init(struct rtl838x_switch_priv *priv) { - int i; u32 template_selectors; mutex_init(&priv->pie_mutex); pr_info("%s\n", __func__); /* Enable ACL lookup on all ports, including CPU_PORT */ - for (i = 0; i <= priv->cpu_port; i++) + for (int i = 0; i <= priv->cpu_port; i++) sw_w32(1, RTL930X_ACL_PORT_LOOKUP_CTRL(i)); /* Include IPG in metering */ @@ -2037,22 +2016,22 @@ static void rtl930x_pie_init(struct rtl838x_switch_priv *priv) /* Enable predefined templates 0, 1 for first quarter of all blocks */ template_selectors = 0 | (1 << 4); - for (i = 0; i < priv->n_pie_blocks / 4; i++) + for (int i = 0; i < priv->n_pie_blocks / 4; i++) sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i)); /* Enable predefined templates 2, 3 for second quarter of all blocks */ template_selectors = 2 | (3 << 4); - for (i = priv->n_pie_blocks / 4; i < priv->n_pie_blocks / 2; i++) + for (int i = priv->n_pie_blocks / 4; i < priv->n_pie_blocks / 2; i++) sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i)); /* Enable predefined templates 0, 1 for third half of all blocks */ template_selectors = 0 | (1 << 4); - for (i = priv->n_pie_blocks / 2; i < priv->n_pie_blocks * 3 / 4; i++) + for (int i = priv->n_pie_blocks / 2; i < priv->n_pie_blocks * 3 / 4; i++) sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i)); /* Enable predefined templates 2, 3 for fourth quater of all blocks */ template_selectors = 2 | (3 << 4); - for (i = priv->n_pie_blocks * 3 / 4; i < priv->n_pie_blocks; i++) + for (int i = priv->n_pie_blocks * 3 / 4; i < priv->n_pie_blocks; i++) sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i)); } @@ -2209,10 +2188,8 @@ static void rtl930x_set_l3_egress_mac(u32 idx, u64 mac) */ int rtl930x_l3_setup(struct rtl838x_switch_priv *priv) { - int i; - /* Setup MTU with id 0 for default interface */ - for (i = 0; i < MAX_INTF_MTUS; i++) + for (int i = 0; i < MAX_INTF_MTUS; i++) priv->intf_mtu_count[i] = priv->intf_mtus[i] = 0; priv->intf_mtu_count[0] = 0; /* Needs to stay forever */ @@ -2229,7 +2206,7 @@ int rtl930x_l3_setup(struct rtl838x_switch_priv *priv) sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP6_MTU_CTRL(1)); /* Clear all source port MACs */ - for (i = 0; i < MAX_SMACS; i++) + for (int i = 0; i < MAX_SMACS; i++) rtl930x_set_l3_egress_mac(L3_EGRESS_DMACS + i, 0ULL); /* Configure the default L3 hash algorithm */ @@ -2400,12 +2377,8 @@ void rtl930x_set_distribution_algorithm(int group, int algoidx, u32 algomsk) static void rtl930x_led_init(struct rtl838x_switch_priv *priv) { - int i, pos; - u32 v, pm = 0, set; - u32 setlen; - const __be32 *led_set; - char set_name[9]; struct device_node *node; + u32 pm = 0; pr_info("%s called\n", __func__); node = of_find_compatible_node(NULL, NULL, "realtek,rtl9300-leds"); @@ -2414,8 +2387,11 @@ static void rtl930x_led_init(struct rtl838x_switch_priv *priv) return; } - for (i = 0; i < priv->cpu_port; i++) { - pos = (i << 1) % 32; + for (int i = 0; i < priv->cpu_port; i++) { + int pos = (i << 1) % 32; + u32 set; + u32 v; + sw_w32_mask(0x3 << pos, 0, RTL930X_LED_PORT_FIB_SET_SEL_CTRL(i)); sw_w32_mask(0x3 << pos, 0, RTL930X_LED_PORT_COPR_SET_SEL_CTRL(i)); @@ -2436,7 +2412,12 @@ static void rtl930x_led_init(struct rtl838x_switch_priv *priv) sw_w32_mask(0, set << pos, RTL930X_LED_PORT_FIB_SET_SEL_CTRL(i)); } - for (i = 0; i < 4; i++) { + for (int i = 0; i < 4; i++) { + const __be32 *led_set; + char set_name[9]; + u32 setlen; + u32 v; + sprintf(set_name, "led_set%d", i); led_set = of_get_property(node, set_name, &setlen); if (!led_set || setlen != 16) @@ -2455,7 +2436,7 @@ static void rtl930x_led_init(struct rtl838x_switch_priv *priv) sw_w32(pm, RTL930X_LED_PORT_FIB_MASK_CTRL); sw_w32(pm, RTL930X_LED_PORT_COMBO_MASK_CTRL); - for (i = 0; i < 24; i++) + for (int i = 0; i < 24; i++) pr_info("%s %08x: %08x\n",__func__, 0xbb00cc00 + i * 4, sw_r32(0xcc00 + i * 4)); } diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl931x.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl931x.c index cd7c5edf51b..92f06622233 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl931x.c +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl931x.c @@ -157,25 +157,23 @@ void rtl931x_vlan_profile_dump(int index) static void rtl931x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]) { - int i; u32 cmd = 1 << 20 | /* Execute cmd */ 0 << 19 | /* Read */ 5 << 15 | /* Table type 0b101 */ (msti & 0x3fff); priv->r->exec_tbl0_cmd(cmd); - for (i = 0; i < 4; i++) + for (int i = 0; i < 4; i++) port_state[i] = sw_r32(priv->r->tbl_access_data_0(i)); } static void rtl931x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]) { - int i; u32 cmd = 1 << 20 | /* Execute cmd */ 1 << 19 | /* Write */ 5 << 15 | /* Table type 0b101 */ (msti & 0x3fff); - for (i = 0; i < 4; i++) + for (int i = 0; i < 4; i++) sw_w32(port_state[i], priv->r->tbl_access_data_0(i)); priv->r->exec_tbl0_cmd(cmd); } @@ -295,7 +293,6 @@ irqreturn_t rtl931x_switch_irq(int irq, void *dev_id) u32 status = sw_r32(RTL931X_ISR_GLB_SRC); u64 ports = rtl839x_get_port_reg_le(RTL931X_ISR_PORT_LINK_STS_CHG); u64 link; - int i; /* Clear status */ rtl839x_set_port_reg_le(ports, RTL931X_ISR_PORT_LINK_STS_CHG); @@ -306,7 +303,7 @@ irqreturn_t rtl931x_switch_irq(int irq, void *dev_id) link = rtl839x_get_port_reg_le(RTL931X_MAC_LINK_STS); pr_debug("RTL931X Link change: status: %x, link status %016llx\n", status, link); - for (i = 0; i < 56; i++) { + for (int i = 0; i < 56; i++) { if (ports & BIT_ULL(i)) { if (link & BIT_ULL(i)) { pr_info("%s port %d up\n", __func__, i); @@ -467,9 +464,8 @@ int rtl931x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val) void rtl931x_print_matrix(void) { volatile u64 *ptr = RTL838X_SW_BASE + RTL839X_PORT_ISO_CTRL(0); - int i; - for (i = 0; i < 52; i += 4) + for (int i = 0; i < 52; i += 4) pr_info("> %16llx %16llx %16llx %16llx\n", ptr[i + 0], ptr[i + 1], ptr[i + 2], ptr[i + 3]); pr_info("CPU_PORT> %16llx\n", ptr[52]); @@ -752,7 +748,6 @@ static u64 rtl931x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2 u32 r[4]; struct table_reg *q = rtl_table_get(RTL9310_TBL_0, 0); u32 idx; - int i; u64 mac; u64 seed; @@ -773,7 +768,7 @@ static u64 rtl931x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2 pr_debug("%s: NOW hash %08x, pos: %d\n", __func__, hash, pos); rtl_table_read(q, idx); - for (i = 0; i < 4; i++) + for (int i = 0; i < 4; i++) r[i] = sw_r32(rtl_table_data(q, i)); rtl_table_release(q); @@ -812,7 +807,6 @@ static void rtl931x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_ u32 r[4]; struct table_reg *q = rtl_table_get(RTL9310_TBL_0, 0); u32 idx = (0 << 14) | (hash << 2) | pos; /* Access SRAM, with hash and at pos in bucket */ - int i; pr_info("%s: hash %d, pos %d\n", __func__, hash, pos); pr_info("%s: index %d -> mac %02x:%02x:%02x:%02x:%02x:%02x\n", __func__, idx, @@ -821,7 +815,7 @@ static void rtl931x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_ rtl931x_fill_l2_row(r, e); pr_info("%s: %d: %08x %08x %08x\n", __func__, idx, r[0], r[1], r[2]); - for (i = 0; i < 4; i++) + for (int i = 0; i < 4; i++) sw_w32(r[i], rtl_table_data(q, i)); rtl_table_write(q, idx); @@ -840,7 +834,6 @@ static void rtl931x_vlan_fwd_on_inner(int port, bool is_set) static void rtl931x_vlan_profile_setup(int profile) { u32 p[7]; - int i; pr_info("In %s\n", __func__); @@ -1103,10 +1096,9 @@ int rtl931x_pie_data_fill(enum template_field_id field_type, struct pie_rule *pr */ static void rtl931x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[]) { - int i; - u16 data, data_m; + for (int i = 0; i < N_FIXED_FIELDS; i++) { + u16 data, data_m; - for (i = 0; i < N_FIXED_FIELDS; i++) { rtl931x_pie_data_fill(t[i], pr, &data, &data_m); /* On the RTL9300, the mask fields are not word aligned! */ @@ -1264,13 +1256,12 @@ static int rtl931x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, str /* Access IACL table (0) via register 1, the table size is 4096 */ struct table_reg *q = rtl_table_get(RTL9310_TBL_1, 0); u32 r[22]; - int i; int block = idx / PIE_BLOCK_SIZE; u32 t_select = sw_r32(RTL931X_PIE_BLK_TMPLTE_CTRL(block)); pr_info("%s: %d, t_select: %08x\n", __func__, idx, t_select); - for (i = 0; i < 22; i++) + for (int i = 0; i < 22; i++) r[i] = 0; if (!pr->valid) { @@ -1287,7 +1278,7 @@ static int rtl931x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, str rtl931x_pie_rule_dump_raw(r); - for (i = 0; i < 22; i++) + for (int i = 0; i < 22; i++) sw_w32(r[i], rtl_table_data(q, i)); rtl_table_write(q, idx); @@ -1298,11 +1289,8 @@ static int rtl931x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, str static bool rtl931x_pie_templ_has(int t, enum template_field_id field_type) { - int i; - enum template_field_id ft; - - for (i = 0; i < N_FIXED_FIELDS_RTL931X; i++) { - ft = fixed_templates[t][i]; + for (int i = 0; i < N_FIXED_FIELDS_RTL931X; i++) { + enum template_field_id ft = fixed_templates[t][i]; if (field_type == ft) return true; } @@ -1358,7 +1346,7 @@ static int rtl931x_pie_verify_template(struct rtl838x_switch_priv *priv, static int rtl931x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rule *pr) { - int idx, block, j, t; + int idx, block, j; int min_block = 0; int max_block = priv->n_pie_blocks / 2; @@ -1372,7 +1360,7 @@ static int rtl931x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rul for (block = min_block; block < max_block; block++) { for (j = 0; j < 2; j++) { - t = (sw_r32(RTL931X_PIE_BLK_TMPLTE_CTRL(block)) >> (j * 4)) & 0xf; + int t = (sw_r32(RTL931X_PIE_BLK_TMPLTE_CTRL(block)) >> (j * 4)) & 0xf; pr_info("Testing block %d, template %d, template id %d\n", block, j, t); pr_info("%s: %08x\n", __func__, sw_r32(RTL931X_PIE_BLK_TMPLTE_CTRL(block))); @@ -1435,14 +1423,13 @@ static void rtl931x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rul static void rtl931x_pie_init(struct rtl838x_switch_priv *priv) { - int i; u32 template_selectors; mutex_init(&priv->pie_mutex); pr_info("%s\n", __func__); /* Enable ACL lookup on all ports, including CPU_PORT */ - for (i = 0; i <= priv->cpu_port; i++) + for (int i = 0; i <= priv->cpu_port; i++) sw_w32(1, RTL931X_ACL_PORT_LOOKUP_CTRL(i)); /* Include IPG in metering */ @@ -1456,7 +1443,7 @@ static void rtl931x_pie_init(struct rtl838x_switch_priv *priv) /* 6: Disabled, 0: VACL, 1: IACL, 2: EACL */ /* And for OpenFlow Flow blocks: 3: Ingress Flow table 0, */ /* 4: Ingress Flow Table 3, 5: Egress flow table 0 */ - for (i = 0; i < priv->n_pie_blocks; i++) { + for (int i = 0; i < priv->n_pie_blocks; i++) { int pos = (i % 10) * 3; u32 r = RTL931X_PIE_BLK_PHASE_CTRL + 4 * (i / 10); @@ -1468,22 +1455,22 @@ static void rtl931x_pie_init(struct rtl838x_switch_priv *priv) /* Enable predefined templates 0, 1 for first quarter of all blocks */ template_selectors = 0 | (1 << 4); - for (i = 0; i < priv->n_pie_blocks / 4; i++) + for (int i = 0; i < priv->n_pie_blocks / 4; i++) sw_w32(template_selectors, RTL931X_PIE_BLK_TMPLTE_CTRL(i)); /* Enable predefined templates 2, 3 for second quarter of all blocks */ template_selectors = 2 | (3 << 4); - for (i = priv->n_pie_blocks / 4; i < priv->n_pie_blocks / 2; i++) + for (int i = priv->n_pie_blocks / 4; i < priv->n_pie_blocks / 2; i++) sw_w32(template_selectors, RTL931X_PIE_BLK_TMPLTE_CTRL(i)); /* Enable predefined templates 0, 1 for third quater of all blocks */ template_selectors = 0 | (1 << 4); - for (i = priv->n_pie_blocks / 2; i < priv->n_pie_blocks * 3 / 4; i++) + for (int i = priv->n_pie_blocks / 2; i < priv->n_pie_blocks * 3 / 4; i++) sw_w32(template_selectors, RTL931X_PIE_BLK_TMPLTE_CTRL(i)); /* Enable predefined templates 2, 3 for fourth quater of all blocks */ template_selectors = 2 | (3 << 4); - for (i = priv->n_pie_blocks * 3 / 4; i < priv->n_pie_blocks; i++) + for (int i = priv->n_pie_blocks * 3 / 4; i < priv->n_pie_blocks; i++) sw_w32(template_selectors, RTL931X_PIE_BLK_TMPLTE_CTRL(i)); } @@ -1572,12 +1559,7 @@ void rtl931x_set_distribution_algorithm(int group, int algoidx, u32 algomsk) static void rtl931x_led_init(struct rtl838x_switch_priv *priv) { - int i, pos; - u32 v, set; u64 pm_copper = 0, pm_fiber = 0; - u32 setlen; - const __be32 *led_set; - char set_name[9]; struct device_node *node; pr_info("%s called\n", __func__); @@ -1587,8 +1569,11 @@ static void rtl931x_led_init(struct rtl838x_switch_priv *priv) return; } - for (i = 0; i < priv->cpu_port; i++) { - pos = (i << 1) % 32; + for (int i = 0; i < priv->cpu_port; i++) { + int pos = (i << 1) % 32; + u32 set; + u32 v; + sw_w32_mask(0x3 << pos, 0, RTL931X_LED_PORT_FIB_SET_SEL_CTRL(i)); sw_w32_mask(0x3 << pos, 0, RTL931X_LED_PORT_COPR_SET_SEL_CTRL(i)); @@ -1608,7 +1593,12 @@ static void rtl931x_led_init(struct rtl838x_switch_priv *priv) sw_w32_mask(0, set << pos, RTL931X_LED_PORT_FIB_SET_SEL_CTRL(i)); } - for (i = 0; i < 4; i++) { + for (int i = 0; i < 4; i++) { + const __be32 *led_set; + char set_name[9]; + u32 setlen; + u32 v; + sprintf(set_name, "led_set%d", i); pr_info(">%s<\n", set_name); led_set = of_get_property(node, set_name, &setlen); @@ -1627,7 +1617,7 @@ static void rtl931x_led_init(struct rtl838x_switch_priv *priv) rtl839x_set_port_reg_le(pm_fiber, RTL931X_LED_PORT_FIB_MASK_CTRL); rtl839x_set_port_reg_le(pm_copper | pm_fiber, RTL931X_LED_PORT_COMBO_MASK_CTRL); - for (i = 0; i < 32; i++) + for (int i = 0; i < 32; i++) pr_info("%s %08x: %08x\n",__func__, 0xbb000600 + i * 4, sw_r32(0x0600 + i * 4)); } diff --git a/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.c b/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.c index af4a54cf89e..1c473cc7f3f 100644 --- a/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.c +++ b/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.c @@ -331,12 +331,11 @@ bool rtl931x_decode_tag(struct p_hdr *h, struct dsa_tag *t) */ static void rtl838x_rb_cleanup(struct rtl838x_eth_priv *priv, int status) { - int r; - u32 *last; - struct p_hdr *h; - struct ring_b *ring = priv->membase; + for (int r = 0; r < priv->rxrings; r++) { + struct ring_b *ring = priv->membase; + struct p_hdr *h; + u32 *last; - for (r = 0; r < priv->rxrings; r++) { pr_debug("In %s working on r: %d\n", __func__, r); last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4)); do { @@ -368,23 +367,22 @@ struct fdb_update_work { void rtl838x_fdb_sync(struct work_struct *work) { - const struct fdb_update_work *uw = - container_of(work, struct fdb_update_work, work); - struct switchdev_notifier_fdb_info info; - u8 addr[ETH_ALEN]; - int i = 0; - int action; + const struct fdb_update_work *uw = container_of(work, struct fdb_update_work, work); - while (uw->macs[i]) { - action = (uw->macs[i] & (1ULL << 63)) ? SWITCHDEV_FDB_ADD_TO_BRIDGE - : SWITCHDEV_FDB_DEL_TO_BRIDGE; + for (int i = 0; uw->macs[i]; i++) { + struct switchdev_notifier_fdb_info info; + u8 addr[ETH_ALEN]; + int action; + + action = (uw->macs[i] & (1ULL << 63)) ? + SWITCHDEV_FDB_ADD_TO_BRIDGE : + SWITCHDEV_FDB_DEL_TO_BRIDGE; u64_to_ether_addr(uw->macs[i] & 0xffffffffffffULL, addr); info.addr = &addr[0]; info.vid = 0; info.offloaded = 1; pr_debug("FDB entry %d: %llx, action %d\n", i, uw->macs[0], action); call_switchdev_notifiers(action, uw->ndev, &info.info, NULL); - i++; } kfree(work); } @@ -392,13 +390,14 @@ void rtl838x_fdb_sync(struct work_struct *work) static void rtl839x_l2_notification_handler(struct rtl838x_eth_priv *priv) { struct notify_b *nb = priv->membase + sizeof(struct ring_b); - u32 e = priv->lastEvent; - struct n_event *event; - int i; - u64 mac; - struct fdb_update_work *w; + u32 e = priv->lastEvent; while (!(nb->ring[e] & 1)) { + struct fdb_update_work *w; + struct n_event *event; + u64 mac; + int i; + w = kzalloc(sizeof(*w), GFP_ATOMIC); if (!w) { pr_err("Out of memory: %s", __func__); @@ -432,7 +431,6 @@ static irqreturn_t rtl83xx_net_irq(int irq, void *dev_id) struct net_device *dev = dev_id; struct rtl838x_eth_priv *priv = netdev_priv(dev); u32 status = sw_r32(priv->r->dma_if_intr_sts); - int i; pr_debug("IRQ: %08x\n", status); @@ -447,7 +445,7 @@ static irqreturn_t rtl83xx_net_irq(int irq, void *dev_id) /* ACK and disable RX interrupt for this ring */ sw_w32_mask(0xff00 & status, 0, priv->r->dma_if_intr_msk); sw_w32(0x0000ff00 & status, priv->r->dma_if_intr_sts); - for (i = 0; i < priv->rxrings; i++) { + for (int i = 0; i < priv->rxrings; i++) { if (status & BIT(i + 8)) { pr_debug("Scheduling queue: %d\n", i); napi_schedule(&priv->rx_qs[i].napi); @@ -488,7 +486,6 @@ static irqreturn_t rtl93xx_net_irq(int irq, void *dev_id) u32 status_rx_r = sw_r32(priv->r->dma_if_intr_rx_runout_sts); u32 status_rx = sw_r32(priv->r->dma_if_intr_rx_done_sts); u32 status_tx = sw_r32(priv->r->dma_if_intr_tx_done_sts); - int i; pr_debug("In %s, status_tx: %08x, status_rx: %08x, status_rx_r: %08x\n", __func__, status_tx, status_rx, status_rx_r); @@ -506,7 +503,7 @@ static irqreturn_t rtl93xx_net_irq(int irq, void *dev_id) /* ACK and disable RX interrupt for given rings */ sw_w32(status_rx, priv->r->dma_if_intr_rx_done_sts); sw_w32_mask(status_rx, 0, priv->r->dma_if_intr_rx_done_msk); - for (i = 0; i < priv->rxrings; i++) { + for (int i = 0; i < priv->rxrings; i++) { if (status_rx & BIT(i)) { pr_debug("Scheduling queue: %d\n", i); napi_schedule(&priv->rx_qs[i].napi); @@ -641,7 +638,6 @@ static void rtl838x_hw_reset(struct rtl838x_eth_priv *priv) { u32 int_saved, nbuf; u32 reset_mask; - int i, pos; pr_info("RESETTING %x, CPU_PORT %d\n", priv->family_id, priv->cpu_port); sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(priv->cpu_port)); @@ -692,8 +688,9 @@ static void rtl838x_hw_reset(struct rtl838x_eth_priv *priv) if (priv->family_id == RTL8390_FAMILY_ID) sw_w32(0xffffffff, RTL839X_DMA_IF_RX_RING_CNTR); if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) { - for (i = 0; i < priv->rxrings; i++) { - pos = (i % 3) * 10; + for (int i = 0; i < priv->rxrings; i++) { + int pos = (i % 3) * 10; + sw_w32_mask(0x3ff << pos, 0, priv->r->dma_if_rx_ring_size(i)); sw_w32_mask(0x3ff << pos, priv->rxringlen, priv->r->dma_if_rx_ring_cntr(i)); @@ -715,13 +712,12 @@ static void rtl838x_hw_reset(struct rtl838x_eth_priv *priv) static void rtl838x_hw_ring_setup(struct rtl838x_eth_priv *priv) { - int i; struct ring_b *ring = priv->membase; - for (i = 0; i < priv->rxrings; i++) + for (int i = 0; i < priv->rxrings; i++) sw_w32(KSEG1ADDR(&ring->rx_r[i]), priv->r->dma_rx_base + i * 4); - for (i = 0; i < TXRINGS; i++) + for (int i = 0; i < TXRINGS; i++) sw_w32(KSEG1ADDR(&ring->tx_r[i]), priv->r->dma_tx_base + i * 4); } @@ -778,14 +774,13 @@ static void rtl839x_hw_en_rxtx(struct rtl838x_eth_priv *priv) static void rtl93xx_hw_en_rxtx(struct rtl838x_eth_priv *priv) { - int i, pos; - u32 v; - /* Setup CPU-Port: RX Buffer truncated at 1600 Bytes */ sw_w32(0x06400040, priv->r->dma_if_ctrl); - for (i = 0; i < priv->rxrings; i++) { - pos = (i % 3) * 10; + for (int i = 0; i < priv->rxrings; i++) { + int pos = (i % 3) * 10; + u32 v; + sw_w32_mask(0x3ff << pos, priv->rxringlen << pos, priv->r->dma_if_rx_ring_size(i)); /* Some SoCs have issues with missing underflow protection */ @@ -817,10 +812,10 @@ static void rtl93xx_hw_en_rxtx(struct rtl838x_eth_priv *priv) static void rtl838x_setup_ring_buffer(struct rtl838x_eth_priv *priv, struct ring_b *ring) { - int i, j; - struct p_hdr *h; + for (int i = 0; i < priv->rxrings; i++) { + struct p_hdr *h; + int j; - for (i = 0; i < priv->rxrings; i++) { for (j = 0; j < priv->rxringlen; j++) { h = &ring->rx_header[i][j]; memset(h, 0, sizeof(struct p_hdr)); @@ -836,7 +831,10 @@ static void rtl838x_setup_ring_buffer(struct rtl838x_eth_priv *priv, struct ring ring->c_rx[i] = 0; } - for (i = 0; i < TXRINGS; i++) { + for (int i = 0; i < TXRINGS; i++) { + struct p_hdr *h; + int j; + for (j = 0; j < TXRINGLEN; j++) { h = &ring->tx_header[i][j]; memset(h, 0, sizeof(struct p_hdr)); @@ -854,10 +852,9 @@ static void rtl838x_setup_ring_buffer(struct rtl838x_eth_priv *priv, struct ring static void rtl839x_setup_notify_ring_buffer(struct rtl838x_eth_priv *priv) { - int i; struct notify_b *b = priv->membase + sizeof(struct ring_b); - for (i = 0; i < NOTIFY_BLOCKS; i++) + for (int i = 0; i < NOTIFY_BLOCKS; i++) b->ring[i] = KSEG1ADDR(&b->blocks[i]) | 1 | (i == (NOTIFY_BLOCKS - 1) ? WRAP : 0); sw_w32((u32) b->ring, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL); @@ -877,7 +874,6 @@ static int rtl838x_eth_open(struct net_device *ndev) unsigned long flags; struct rtl838x_eth_priv *priv = netdev_priv(ndev); struct ring_b *ring = priv->membase; - int i; pr_debug("%s called: RX rings %d(length %d), TX rings %d(length %d)\n", __func__, priv->rxrings, priv->rxringlen, TXRINGS, TXRINGLEN); @@ -895,7 +891,7 @@ static int rtl838x_eth_open(struct net_device *ndev) rtl838x_hw_ring_setup(priv); phylink_start(priv->phylink); - for (i = 0; i < priv->rxrings; i++) + for (int i = 0; i < priv->rxrings; i++) napi_enable(&priv->rx_qs[i].napi); switch (priv->family_id) { @@ -948,7 +944,6 @@ static void rtl838x_hw_stop(struct rtl838x_eth_priv *priv) { u32 force_mac = priv->family_id == RTL8380_FAMILY_ID ? 0x6192C : 0x75; u32 clear_irq = priv->family_id == RTL8380_FAMILY_ID ? 0x000fffff : 0x007fffff; - int i; /* Disable RX/TX from/to CPU-port */ sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(priv->cpu_port)); @@ -969,12 +964,12 @@ static void rtl838x_hw_stop(struct rtl838x_eth_priv *priv) /* Flush L2 address cache */ if (priv->family_id == RTL8380_FAMILY_ID) { - for (i = 0; i <= priv->cpu_port; i++) { + for (int i = 0; i <= priv->cpu_port; i++) { sw_w32(1 << 26 | 1 << 23 | i << 5, priv->r->l2_tbl_flush_ctrl); do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 26)); } } else if (priv->family_id == RTL8390_FAMILY_ID) { - for (i = 0; i <= priv->cpu_port; i++) { + for (int i = 0; i <= priv->cpu_port; i++) { sw_w32(1 << 28 | 1 << 25 | i << 5, priv->r->l2_tbl_flush_ctrl); do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 28)); } @@ -1010,8 +1005,6 @@ static void rtl838x_hw_stop(struct rtl838x_eth_priv *priv) static int rtl838x_eth_stop(struct net_device *ndev) { - unsigned long flags; - int i; struct rtl838x_eth_priv *priv = netdev_priv(ndev); pr_info("in %s\n", __func__); @@ -1019,7 +1012,7 @@ static int rtl838x_eth_stop(struct net_device *ndev) phylink_stop(priv->phylink); rtl838x_hw_stop(priv); - for (i = 0; i < priv->rxrings; i++) + for (int i = 0; i < priv->rxrings; i++) napi_disable(&priv->rx_qs[i].napi); netif_tx_stop_all_queues(ndev); @@ -1123,10 +1116,9 @@ static void rtl838x_eth_tx_timeout(struct net_device *ndev, unsigned int txqueue static int rtl838x_eth_tx(struct sk_buff *skb, struct net_device *dev) { - int len, i; + int len; struct rtl838x_eth_priv *priv = netdev_priv(dev); struct ring_b *ring = priv->membase; - uint32_t val; int ret; unsigned long flags; struct p_hdr *h; @@ -1184,8 +1176,8 @@ static int rtl838x_eth_tx(struct sk_buff *skb, struct net_device *dev) /* Before starting TX, prevent a Lextra bus bug on RTL8380 SoCs */ if (priv->family_id == RTL8380_FAMILY_ID) { - for (i = 0; i < 10; i++) { - val = sw_r32(priv->r->dma_if_ctrl); + for (int i = 0; i < 10; i++) { + u32 val = sw_r32(priv->r->dma_if_ctrl); if ((val & 0xc) == 0xc) break; } @@ -1245,22 +1237,24 @@ static int rtl838x_hw_receive(struct net_device *dev, int r, int budget) { struct rtl838x_eth_priv *priv = netdev_priv(dev); struct ring_b *ring = priv->membase; - struct sk_buff *skb; LIST_HEAD(rx_list); unsigned long flags; - int i, len, work_done = 0; - u8 *data, *skb_data; - unsigned int val; + int work_done = 0; u32 *last; - struct p_hdr *h; bool dsa = netdev_uses_dsa(dev); - struct dsa_tag tag; pr_debug("---------------------------------------------------------- RX - %d\n", r); spin_lock_irqsave(&priv->lock, flags); last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4)); do { + struct sk_buff *skb; + struct dsa_tag tag; + struct p_hdr *h; + u8 *skb_data; + u8 *data; + int len; + if ((ring->rx_r[r][ring->c_rx[r]] & 0x1)) { if (&ring->rx_r[r][ring->c_rx[r]] != last) { netdev_warn(dev, "Ring contention: r: %x, last %x, cur %x\n", @@ -1288,7 +1282,9 @@ static int rtl838x_hw_receive(struct net_device *dev, int r, int budget) /* BUG: Prevent bug on RTL838x SoCs */ if (priv->family_id == RTL8380_FAMILY_ID) { sw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0)); - for (i = 0; i < priv->rxrings; i++) { + for (int i = 0; i < priv->rxrings; i++) { + unsigned int val; + /* Update each ring cnt */ val = sw_r32(priv->r->dma_if_rx_ring_cntr(i)); sw_w32(val, priv->r->dma_if_rx_ring_cntr(i)); @@ -1576,8 +1572,6 @@ static int rtl8390_init_mac(struct rtl838x_eth_priv *priv) static int rtl8380_init_mac(struct rtl838x_eth_priv *priv) { - int i; - if (priv->family_id == 0x8390) return rtl8390_init_mac(priv); @@ -1592,11 +1586,11 @@ static int rtl8380_init_mac(struct rtl838x_eth_priv *priv) /* Init VLAN. TODO: Understand what is being done, here */ if (priv->id == 0x8382) { - for (i = 0; i <= 28; i++) + for (int i = 0; i <= 28; i++) sw_w32(0, 0xd57c + i * 0x80); } if (priv->id == 0x8380) { - for (i = 8; i <= 28; i++) + for (int i = 8; i <= 28; i++) sw_w32(0, 0xd57c + i * 0x80); } @@ -1914,8 +1908,6 @@ u8 mac_type_bit[RTL930X_CPU_PORT] = {0, 0, 0, 0, 2, 2, 2, 2, 4, 4, 4, 4, 6, 6, 6 static int rtl930x_mdio_reset(struct mii_bus *bus) { - int i; - int pos; struct rtl838x_eth_priv *priv = bus->priv; u32 c45_mask = 0; u32 poll_sel[2]; @@ -1927,7 +1919,9 @@ static int rtl930x_mdio_reset(struct mii_bus *bus) /* Mapping of port to phy-addresses on an SMI bus */ poll_sel[0] = poll_sel[1] = 0; - for (i = 0; i < RTL930X_CPU_PORT; i++) { + for (int i = 0; i < RTL930X_CPU_PORT; i++) { + int pos; + if (priv->smi_bus[i] > 3) continue; pos = (i % 6) * 5; @@ -1947,7 +1941,7 @@ static int rtl930x_mdio_reset(struct mii_bus *bus) sw_w32_mask(poll_ctrl, 0, RTL930X_SMI_GLB_CTRL); /* Configure which SMI busses are polled in c45 based on a c45 PHY being on that bus */ - for (i = 0; i < 4; i++) + for (int i = 0; i < 4; i++) if (priv->smi_bus_isc45[i]) c45_mask |= BIT(i + 16); @@ -1957,7 +1951,7 @@ static int rtl930x_mdio_reset(struct mii_bus *bus) /* Set the MAC type of each port according to the PHY-interface */ /* Values are FE: 2, GE: 3, XGE/2.5G: 0(SERDES) or 1(otherwise), SXGE: 0 */ v = 0; - for (i = 0; i < RTL930X_CPU_PORT; i++) { + for (int i = 0; i < RTL930X_CPU_PORT; i++) { switch (priv->interfaces[i]) { case PHY_INTERFACE_MODE_10GBASER: break; /* Serdes: Value = 0 */ @@ -2018,8 +2012,6 @@ static int rtl930x_mdio_reset(struct mii_bus *bus) static int rtl931x_mdio_reset(struct mii_bus *bus) { - int i; - int pos; struct rtl838x_eth_priv *priv = bus->priv; u32 c45_mask = 0; u32 poll_sel[4]; @@ -2035,7 +2027,9 @@ static int rtl931x_mdio_reset(struct mii_bus *bus) mdc_on[0] = mdc_on[1] = mdc_on[2] = mdc_on[3] = false; /* Mapping of port to phy-addresses on an SMI bus */ poll_sel[0] = poll_sel[1] = poll_sel[2] = poll_sel[3] = 0; - for (i = 0; i < 56; i++) { + for (int i = 0; i < 56; i++) { + u32 pos; + pos = (i % 6) * 5; sw_w32_mask(0x1f << pos, priv->smi_addr[i] << pos, RTL931X_SMI_PORT_ADDR + (i / 6) * 4); pos = (i * 2) % 32; @@ -2045,7 +2039,7 @@ static int rtl931x_mdio_reset(struct mii_bus *bus) } /* Configure which SMI bus is behind which port number */ - for (i = 0; i < 4; i++) { + for (int i = 0; i < 4; i++) { pr_info("poll sel %d, %08x\n", i, poll_sel[i]); sw_w32(poll_sel[i], RTL931X_SMI_PORT_POLLING_SEL + (i * 4)); } @@ -2053,7 +2047,7 @@ static int rtl931x_mdio_reset(struct mii_bus *bus) /* Configure which SMI busses */ pr_info("%s: WAS RTL931X_MAC_L2_GLOBAL_CTRL2 %08x\n", __func__, sw_r32(RTL931X_MAC_L2_GLOBAL_CTRL2)); pr_info("c45_mask: %08x, RTL931X_SMI_GLB_CTRL0 was %X", c45_mask, sw_r32(RTL931X_SMI_GLB_CTRL0)); - for (i = 0; i < 4; i++) { + for (int i = 0; i < 4; i++) { /* bus is polled in c45 */ if (priv->smi_bus_isc45[i]) c45_mask |= 0x2 << (i * 2); /* Std. C45, non-standard is 0x3 */ @@ -2357,7 +2351,7 @@ static int __init rtl838x_eth_probe(struct platform_device *pdev) struct resource *res, *mem; phy_interface_t phy_mode; struct phylink *phylink; - int err = 0, i, rxrings, rxringlen; + int err = 0, rxrings, rxringlen; struct ring_b *ring; pr_info("Probing RTL838X eth device pdev: %x, dev: %x\n", @@ -2518,7 +2512,7 @@ static int __init rtl838x_eth_probe(struct platform_device *pdev) if (err) goto err_free; - for (i = 0; i < priv->rxrings; i++) { + for (int i = 0; i < priv->rxrings; i++) { priv->rx_qs[i].id = i; priv->rx_qs[i].priv = priv; netif_napi_add(dev, &priv->rx_qs[i].napi, rtl838x_poll_rx, 64); @@ -2558,7 +2552,6 @@ static int rtl838x_eth_remove(struct platform_device *pdev) { struct net_device *dev = platform_get_drvdata(pdev); struct rtl838x_eth_priv *priv = netdev_priv(dev); - int i; if (dev) { pr_info("Removing platform driver for rtl838x-eth\n"); @@ -2567,7 +2560,7 @@ static int rtl838x_eth_remove(struct platform_device *pdev) netif_tx_stop_all_queues(dev); - for (i = 0; i < priv->rxrings; i++) + for (int i = 0; i < priv->rxrings; i++) netif_napi_del(&priv->rx_qs[i].napi); unregister_netdev(dev); diff --git a/target/linux/realtek/files-5.15/drivers/net/phy/rtl83xx-phy.c b/target/linux/realtek/files-5.15/drivers/net/phy/rtl83xx-phy.c index ce83847c6dc..77332527636 100644 --- a/target/linux/realtek/files-5.15/drivers/net/phy/rtl83xx-phy.c +++ b/target/linux/realtek/files-5.15/drivers/net/phy/rtl83xx-phy.c @@ -433,7 +433,7 @@ static int rtl8226_write_page(struct phy_device *phydev, int page) static int rtl8226_read_status(struct phy_device *phydev) { - int ret = 0, i; + int ret = 0; u32 val; /* TODO: ret = genphy_read_status(phydev); @@ -444,7 +444,7 @@ static int rtl8226_read_status(struct phy_device *phydev) */ /* Link status must be read twice */ - for (i = 0; i < 2; i++) + for (int i = 0; i < 2; i++) val = phy_read_mmd(phydev, MMD_VEND2, 0xA402); phydev->link = val & BIT(2) ? 1 : 0; @@ -709,7 +709,6 @@ static int rtl8390_configure_generic(struct phy_device *phydev) static int rtl8380_configure_int_rtl8218b(struct phy_device *phydev) { u32 val, phy_id; - int i, p, ipd_flag; int mac = phydev->mdio.addr; struct fw_header *h; u32 *rtl838x_6275B_intPhy_perport; @@ -744,8 +743,9 @@ static int rtl8380_configure_int_rtl8218b(struct phy_device *phydev) rtl838x_6275B_intPhy_perport = (void *)h + sizeof(struct fw_header) + h->parts[8].start; rtl8218b_6276B_hwEsd_perport = (void *)h + sizeof(struct fw_header) + h->parts[9].start; - if (sw_r32(RTL838X_DMY_REG31) == 0x1) - ipd_flag = 1; + if (sw_r32(RTL838X_DMY_REG31) == 0x1) { + int ipd_flag = 1; + } val = phy_read(phydev, 0); if (val & BIT(11)) @@ -755,12 +755,14 @@ static int rtl8380_configure_int_rtl8218b(struct phy_device *phydev) msleep(100); /* Ready PHY for patch */ - for (p = 0; p < 8; p++) { + for (int p = 0; p < 8; p++) { phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH); phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW, 0x10, 0x0010); } msleep(500); - for (p = 0; p < 8; p++) { + for (int p = 0; p < 8; p++) { + int i; + for (i = 0; i < 100 ; i++) { val = phy_package_port_read_paged(phydev, p, RTL821X_PAGE_STATE, 0x10); if (val & 0x40) @@ -773,7 +775,9 @@ static int rtl8380_configure_int_rtl8218b(struct phy_device *phydev) return -1; } } - for (p = 0; p < 8; p++) { + for (int p = 0; p < 8; p++) { + int i; + i = 0; while (rtl838x_6275B_intPhy_perport[i * 2]) { phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW, @@ -796,7 +800,6 @@ static int rtl8380_configure_int_rtl8218b(struct phy_device *phydev) static int rtl8380_configure_ext_rtl8218b(struct phy_device *phydev) { u32 val, ipd, phy_id; - int i, l; int mac = phydev->mdio.addr; struct fw_header *h; u32 *rtl8380_rtl8218b_perchip; @@ -850,24 +853,22 @@ static int rtl8380_configure_ext_rtl8218b(struct phy_device *phydev) phydev_info(phydev, "Detected chip revision %04x\n", val); - i = 0; - while (rtl8380_rtl8218b_perchip[i * 3] && - rtl8380_rtl8218b_perchip[i * 3 + 1]) { + for (int i = 0; rtl8380_rtl8218b_perchip[i * 3] && + rtl8380_rtl8218b_perchip[i * 3 + 1]; i++) { phy_package_port_write_paged(phydev, rtl8380_rtl8218b_perchip[i * 3], RTL83XX_PAGE_RAW, rtl8380_rtl8218b_perchip[i * 3 + 1], rtl8380_rtl8218b_perchip[i * 3 + 2]); - i++; } /* Enable PHY */ - for (i = 0; i < 8; i++) { + for (int i = 0; i < 8; i++) { phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN); phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x00, 0x1140); } mdelay(100); /* Request patch */ - for (i = 0; i < 8; i++) { + for (int i = 0; i < 8; i++) { phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH); phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x10, 0x0010); } @@ -875,7 +876,9 @@ static int rtl8380_configure_ext_rtl8218b(struct phy_device *phydev) mdelay(300); /* Verify patch readiness */ - for (i = 0; i < 8; i++) { + for (int i = 0; i < 8; i++) { + int l; + for (l = 0; l < 100; l++) { val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_STATE, 0x10); if (val & 0x40) @@ -898,11 +901,9 @@ static int rtl8380_configure_ext_rtl8218b(struct phy_device *phydev) phy_write_paged(phydev, 0, 30, 0); ipd = (ipd >> 4) & 0xf; /* unused ? */ - i = 0; - while (rtl8218B_6276B_rtl8380_perport[i * 2]) { + for (int i = 0; rtl8218B_6276B_rtl8380_perport[i * 2]; i++) { phy_write_paged(phydev, RTL83XX_PAGE_RAW, rtl8218B_6276B_rtl8380_perport[i * 2], rtl8218B_6276B_rtl8380_perport[i * 2 + 1]); - i++; } /* Disable broadcast ID */ @@ -1299,12 +1300,12 @@ static int rtl8380_configure_rtl8214c(struct phy_device *phydev) static int rtl8380_configure_rtl8214fc(struct phy_device *phydev) { - u32 phy_id, val, page = 0; - int i, l; int mac = phydev->mdio.addr; struct fw_header *h; u32 *rtl8380_rtl8214fc_perchip; u32 *rtl8380_rtl8214fc_perport; + u32 phy_id; + u32 val; val = phy_read(phydev, 2); phy_id = val << 16; @@ -1348,9 +1349,10 @@ static int rtl8380_configure_rtl8214fc(struct phy_device *phydev) msleep(100); phy_write_paged(phydev, 0, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER); - i = 0; - while (rtl8380_rtl8214fc_perchip[i * 3] && - rtl8380_rtl8214fc_perchip[i * 3 + 1]) { + for (int i = 0; rtl8380_rtl8214fc_perchip[i * 3] && + rtl8380_rtl8214fc_perchip[i * 3 + 1]; i++) { + u32 page = 0; + if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x1f) page = rtl8380_rtl8214fc_perchip[i * 3 + 2]; if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x13 && page == 0x260) { @@ -1363,24 +1365,25 @@ static int rtl8380_configure_rtl8214fc(struct phy_device *phydev) rtl8380_rtl8214fc_perchip[i * 3 + 1], rtl8380_rtl8214fc_perchip[i * 3 + 2]); } - i++; } /* Force copper medium */ - for (i = 0; i < 4; i++) { + for (int i = 0; i < 4; i++) { phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN); phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER); } /* Enable PHY */ - for (i = 0; i < 4; i++) { + for (int i = 0; i < 4; i++) { phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN); phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x00, 0x1140); } mdelay(100); /* Disable Autosensing */ - for (i = 0; i < 4; i++) { + for (int i = 0; i < 4; i++) { + int l; + for (l = 0; l < 100; l++) { val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_GPHY, 0x10); if ((val & 0x7) >= 3) @@ -1393,14 +1396,16 @@ static int rtl8380_configure_rtl8214fc(struct phy_device *phydev) } /* Request patch */ - for (i = 0; i < 4; i++) { + for (int i = 0; i < 4; i++) { phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH); phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x10, 0x0010); } mdelay(300); /* Verify patch readiness */ - for (i = 0; i < 4; i++) { + for (int i = 0; i < 4; i++) { + int l; + for (l = 0; l < 100; l++) { val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_STATE, 0x10); if (val & 0x40) @@ -1414,18 +1419,16 @@ static int rtl8380_configure_rtl8214fc(struct phy_device *phydev) /* Use Broadcast ID method for patching */ rtl821x_phy_setup_package_broadcast(phydev, true); - i = 0; - while (rtl8380_rtl8214fc_perport[i * 2]) { + for (int i = 0; rtl8380_rtl8214fc_perport[i * 2]; i++) { phy_write_paged(phydev, RTL83XX_PAGE_RAW, rtl8380_rtl8214fc_perport[i * 2], rtl8380_rtl8214fc_perport[i * 2 + 1]); - i++; } /* Disable broadcast ID */ rtl821x_phy_setup_package_broadcast(phydev, false); /* Auto medium selection */ - for (i = 0; i < 4; i++) { + for (int i = 0; i < 4; i++) { phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN); phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO); } @@ -1672,12 +1675,11 @@ void rtl930x_sds_rx_rst(int sds_num, phy_interface_t phy_if) */ void rtl9300_force_sds_mode(int sds, phy_interface_t phy_if) { + int lc_value; int sds_mode; bool lc_on; - int i, lc_value; int lane_0 = (sds % 2) ? sds - 1 : sds; - u32 v, cr_0, cr_1, cr_2; - u32 m_bit, l_bit; + u32 v; pr_info("%s: SDS: %d, mode %d\n", __func__, sds, phy_if); switch (phy_if) { @@ -1768,7 +1770,10 @@ void rtl9300_force_sds_mode(int sds, phy_interface_t phy_if) rtl9300_sds_field_w(sds, 0x1f, 9, 11, 7, sds_mode); /* Toggle LC or Ring */ - for (i = 0; i < 20; i++) { + for (int i = 0; i < 20; i++) { + u32 cr_0, cr_1, cr_2; + u32 m_bit, l_bit; + mdelay(200); rtl930x_write_sds_phy(lane_0, 0x1f, 2, 53); @@ -2936,14 +2941,15 @@ int rtl9300_sds_cmu_band_get(int sds) int rtl9300_configure_serdes(struct phy_device *phydev) { + int phy_mode = PHY_INTERFACE_MODE_10GBASER; struct device *dev = &phydev->mdio.dev; - int phy_addr = phydev->mdio.addr; - struct device_node *dn; + int calib_tries = 0; u32 sds_num = 0; - int sds_mode, calib_tries = 0, phy_mode = PHY_INTERFACE_MODE_10GBASER, i; + int sds_mode; if (dev->of_node) { - dn = dev->of_node; + struct device_node *dn = dev->of_node; + int phy_addr = phydev->mdio.addr; if (of_property_read_u32(dn, "sds", &sds_num)) sds_num = -1; @@ -2987,13 +2993,13 @@ int rtl9300_configure_serdes(struct phy_device *phydev) pr_info("%s PATCHING SerDes %d\n", __func__, sds_num); if (sds_num % 2) { - for (i = 0; i < sizeof(rtl9300_a_sds_10gr_lane1) / sizeof(sds_config); ++i) { + for (int i = 0; i < sizeof(rtl9300_a_sds_10gr_lane1) / sizeof(sds_config); ++i) { rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane1[i].page, rtl9300_a_sds_10gr_lane1[i].reg, rtl9300_a_sds_10gr_lane1[i].data); } } else { - for (i = 0; i < sizeof(rtl9300_a_sds_10gr_lane0) / sizeof(sds_config); ++i) { + for (int i = 0; i < sizeof(rtl9300_a_sds_10gr_lane0) / sizeof(sds_config); ++i) { rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane0[i].page, rtl9300_a_sds_10gr_lane0[i].reg, rtl9300_a_sds_10gr_lane0[i].data); @@ -3088,26 +3094,26 @@ static void rtl931x_sds_rst(u32 sds) static void rtl931x_symerr_clear(u32 sds, phy_interface_t mode) { - u32 i; - u32 xsg_sdsid_0, xsg_sdsid_1; switch (mode) { case PHY_INTERFACE_MODE_NA: break; case PHY_INTERFACE_MODE_XGMII: + u32 xsg_sdsid_0, xsg_sdsid_1; + if (sds < 2) xsg_sdsid_0 = sds; else xsg_sdsid_0 = (sds - 1) * 2; xsg_sdsid_1 = xsg_sdsid_0 + 1; - for (i = 0; i < 4; ++i) { + for (int i = 0; i < 4; ++i) { rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 24, 2, 0, i); rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 3, 15, 8, 0x0); rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 2, 15, 0, 0x0); } - for (i = 0; i < 4; ++i) { + for (int i = 0; i < 4; ++i) { rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 24, 2, 0, i); rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 3, 15, 8, 0x0); rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 2, 15, 0, 0x0); @@ -3468,19 +3474,19 @@ void rtl931x_sds_init(u32 sds, phy_interface_t mode) break; case PHY_INTERFACE_MODE_USXGMII: /* MII_USXGMII_10GSXGMII/10GDXGMII/10GQXGMII: */ - u32 i, evenSds; u32 op_code = 0x6003; + u32 evenSds; if (chiptype) { rtl9310_sds_field_w(asds, 0x6, 0x2, 12, 12, 1); - for (i = 0; i < sizeof(sds_config_10p3125g_type1) / sizeof(sds_config); ++i) { + for (int i = 0; i < sizeof(sds_config_10p3125g_type1) / sizeof(sds_config); ++i) { rtl931x_write_sds_phy(asds, sds_config_10p3125g_type1[i].page - 0x4, sds_config_10p3125g_type1[i].reg, sds_config_10p3125g_type1[i].data); } evenSds = asds - (asds % 2); - for (i = 0; i < sizeof(sds_config_10p3125g_cmu_type1) / sizeof(sds_config); ++i) { + for (int i = 0; i < sizeof(sds_config_10p3125g_cmu_type1) / sizeof(sds_config); ++i) { rtl931x_write_sds_phy(evenSds, sds_config_10p3125g_cmu_type1[i].page - 0x4, sds_config_10p3125g_cmu_type1[i].reg, sds_config_10p3125g_cmu_type1[i].data); } From 090ad0334369cc8c0197cd6bbb66da1eba601559 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Fri, 16 Dec 2022 13:32:48 +0100 Subject: [PATCH 42/72] hostapd: allow sharing the incoming DAS port across multiple interfaces Use the NAS identifier to find the right receiver context on incoming messages Signed-off-by: Felix Fietkau --- .../hostapd/patches/761-shared_das_port.patch | 298 ++++++++++++++++++ 1 file changed, 298 insertions(+) create mode 100644 package/network/services/hostapd/patches/761-shared_das_port.patch diff --git a/package/network/services/hostapd/patches/761-shared_das_port.patch b/package/network/services/hostapd/patches/761-shared_das_port.patch new file mode 100644 index 00000000000..7516b7349ec --- /dev/null +++ b/package/network/services/hostapd/patches/761-shared_das_port.patch @@ -0,0 +1,298 @@ +--- a/src/radius/radius_das.h ++++ b/src/radius/radius_das.h +@@ -44,6 +44,7 @@ struct radius_das_attrs { + struct radius_das_conf { + int port; + const u8 *shared_secret; ++ const u8 *nas_identifier; + size_t shared_secret_len; + const struct hostapd_ip_addr *client_addr; + unsigned int time_window; +--- a/src/ap/hostapd.c ++++ b/src/ap/hostapd.c +@@ -1367,6 +1367,7 @@ static int hostapd_setup_bss(struct host + struct radius_das_conf das_conf; + os_memset(&das_conf, 0, sizeof(das_conf)); + das_conf.port = conf->radius_das_port; ++ das_conf.nas_identifier = conf->nas_identifier; + das_conf.shared_secret = conf->radius_das_shared_secret; + das_conf.shared_secret_len = + conf->radius_das_shared_secret_len; +--- a/src/radius/radius_das.c ++++ b/src/radius/radius_das.c +@@ -12,13 +12,26 @@ + #include "utils/common.h" + #include "utils/eloop.h" + #include "utils/ip_addr.h" ++#include "utils/list.h" + #include "radius.h" + #include "radius_das.h" + + +-struct radius_das_data { ++static struct dl_list das_ports = DL_LIST_HEAD_INIT(das_ports); ++ ++struct radius_das_port { ++ struct dl_list list; ++ struct dl_list das_data; ++ ++ int port; + int sock; ++}; ++ ++struct radius_das_data { ++ struct dl_list list; ++ struct radius_das_port *port; + u8 *shared_secret; ++ u8 *nas_identifier; + size_t shared_secret_len; + struct hostapd_ip_addr client_addr; + unsigned int time_window; +@@ -378,56 +391,17 @@ fail: + } + + +-static void radius_das_receive(int sock, void *eloop_ctx, void *sock_ctx) ++static void ++radius_das_receive_msg(struct radius_das_data *das, struct radius_msg *msg, ++ struct sockaddr *from, socklen_t fromlen, ++ char *abuf, int from_port) + { +- struct radius_das_data *das = eloop_ctx; +- u8 buf[1500]; +- union { +- struct sockaddr_storage ss; +- struct sockaddr_in sin; +-#ifdef CONFIG_IPV6 +- struct sockaddr_in6 sin6; +-#endif /* CONFIG_IPV6 */ +- } from; +- char abuf[50]; +- int from_port = 0; +- socklen_t fromlen; +- int len; +- struct radius_msg *msg, *reply = NULL; ++ struct radius_msg *reply = NULL; + struct radius_hdr *hdr; + struct wpabuf *rbuf; ++ struct os_time now; + u32 val; + int res; +- struct os_time now; +- +- fromlen = sizeof(from); +- len = recvfrom(sock, buf, sizeof(buf), 0, +- (struct sockaddr *) &from.ss, &fromlen); +- if (len < 0) { +- wpa_printf(MSG_ERROR, "DAS: recvfrom: %s", strerror(errno)); +- return; +- } +- +- os_strlcpy(abuf, inet_ntoa(from.sin.sin_addr), sizeof(abuf)); +- from_port = ntohs(from.sin.sin_port); +- +- wpa_printf(MSG_DEBUG, "DAS: Received %d bytes from %s:%d", +- len, abuf, from_port); +- if (das->client_addr.u.v4.s_addr && +- das->client_addr.u.v4.s_addr != from.sin.sin_addr.s_addr) { +- wpa_printf(MSG_DEBUG, "DAS: Drop message from unknown client"); +- return; +- } +- +- msg = radius_msg_parse(buf, len); +- if (msg == NULL) { +- wpa_printf(MSG_DEBUG, "DAS: Parsing incoming RADIUS packet " +- "from %s:%d failed", abuf, from_port); +- return; +- } +- +- if (wpa_debug_level <= MSG_MSGDUMP) +- radius_msg_dump(msg); + + if (radius_msg_verify_das_req(msg, das->shared_secret, + das->shared_secret_len, +@@ -494,9 +468,8 @@ static void radius_das_receive(int sock, + radius_msg_dump(reply); + + rbuf = radius_msg_get_buf(reply); +- res = sendto(das->sock, wpabuf_head(rbuf), +- wpabuf_len(rbuf), 0, +- (struct sockaddr *) &from.ss, fromlen); ++ res = sendto(das->port->sock, wpabuf_head(rbuf), ++ wpabuf_len(rbuf), 0, from, fromlen); + if (res < 0) { + wpa_printf(MSG_ERROR, "DAS: sendto(to %s:%d): %s", + abuf, from_port, strerror(errno)); +@@ -508,6 +481,72 @@ fail: + radius_msg_free(reply); + } + ++static void radius_das_receive(int sock, void *eloop_ctx, void *sock_ctx) ++{ ++ struct radius_das_port *p = eloop_ctx; ++ struct radius_das_data *das; ++ u8 buf[1500]; ++ union { ++ struct sockaddr_storage ss; ++ struct sockaddr_in sin; ++#ifdef CONFIG_IPV6 ++ struct sockaddr_in6 sin6; ++#endif /* CONFIG_IPV6 */ ++ } from; ++ struct radius_msg *msg; ++ size_t nasid_len = 0; ++ u8 *nasid_buf = NULL; ++ char abuf[50]; ++ int from_port = 0; ++ socklen_t fromlen; ++ int found = 0; ++ int len; ++ ++ fromlen = sizeof(from); ++ len = recvfrom(sock, buf, sizeof(buf), 0, ++ (struct sockaddr *) &from.ss, &fromlen); ++ if (len < 0) { ++ wpa_printf(MSG_ERROR, "DAS: recvfrom: %s", strerror(errno)); ++ return; ++ } ++ ++ os_strlcpy(abuf, inet_ntoa(from.sin.sin_addr), sizeof(abuf)); ++ from_port = ntohs(from.sin.sin_port); ++ ++ msg = radius_msg_parse(buf, len); ++ if (msg == NULL) { ++ wpa_printf(MSG_DEBUG, "DAS: Parsing incoming RADIUS packet " ++ "from %s:%d failed", abuf, from_port); ++ return; ++ } ++ ++ wpa_printf(MSG_DEBUG, "DAS: Received %d bytes from %s:%d", ++ len, abuf, from_port); ++ ++ if (wpa_debug_level <= MSG_MSGDUMP) ++ radius_msg_dump(msg); ++ ++ radius_msg_get_attr_ptr(msg, RADIUS_ATTR_NAS_IDENTIFIER, ++ &nasid_buf, &nasid_len, NULL); ++ dl_list_for_each(das, &p->das_data, struct radius_das_data, list) { ++ if (das->client_addr.u.v4.s_addr && ++ das->client_addr.u.v4.s_addr != from.sin.sin_addr.s_addr) ++ continue; ++ ++ if (das->nas_identifier && nasid_buf && ++ (nasid_len != os_strlen(das->nas_identifier) || ++ os_memcmp(das->nas_identifier, nasid_buf, nasid_len) != 0)) ++ continue; ++ ++ found = 1; ++ radius_das_receive_msg(das, msg, (struct sockaddr *)&from.ss, ++ fromlen, abuf, from_port); ++ } ++ ++ if (!found) ++ wpa_printf(MSG_DEBUG, "DAS: Drop message from unknown client"); ++} ++ + + static int radius_das_open_socket(int port) + { +@@ -533,6 +572,49 @@ static int radius_das_open_socket(int po + } + + ++static struct radius_das_port * ++radius_das_open_port(int port) ++{ ++ struct radius_das_port *p; ++ ++ dl_list_for_each(p, &das_ports, struct radius_das_port, list) { ++ if (p->port == port) ++ return p; ++ } ++ ++ p = os_zalloc(sizeof(*p)); ++ if (p == NULL) ++ return NULL; ++ ++ dl_list_init(&p->das_data); ++ p->port = port; ++ p->sock = radius_das_open_socket(port); ++ if (p->sock < 0) ++ goto free_port; ++ ++ if (eloop_register_read_sock(p->sock, radius_das_receive, p, NULL)) ++ goto close_port; ++ ++ dl_list_add(&das_ports, &p->list); ++ ++ return p; ++ ++close_port: ++ close(p->sock); ++free_port: ++ os_free(p); ++ ++ return NULL; ++} ++ ++static void radius_das_close_port(struct radius_das_port *p) ++{ ++ dl_list_del(&p->list); ++ eloop_unregister_read_sock(p->sock); ++ close(p->sock); ++ free(p); ++} ++ + struct radius_das_data * + radius_das_init(struct radius_das_conf *conf) + { +@@ -553,6 +635,8 @@ radius_das_init(struct radius_das_conf * + das->ctx = conf->ctx; + das->disconnect = conf->disconnect; + das->coa = conf->coa; ++ if (conf->nas_identifier) ++ das->nas_identifier = os_strdup(conf->nas_identifier); + + os_memcpy(&das->client_addr, conf->client_addr, + sizeof(das->client_addr)); +@@ -565,19 +649,15 @@ radius_das_init(struct radius_das_conf * + } + das->shared_secret_len = conf->shared_secret_len; + +- das->sock = radius_das_open_socket(conf->port); +- if (das->sock < 0) { ++ das->port = radius_das_open_port(conf->port); ++ if (!das->port) { + wpa_printf(MSG_ERROR, "Failed to open UDP socket for RADIUS " + "DAS"); + radius_das_deinit(das); + return NULL; + } + +- if (eloop_register_read_sock(das->sock, radius_das_receive, das, NULL)) +- { +- radius_das_deinit(das); +- return NULL; +- } ++ dl_list_add(&das->port->das_data, &das->list); + + return das; + } +@@ -588,11 +668,14 @@ void radius_das_deinit(struct radius_das + if (das == NULL) + return; + +- if (das->sock >= 0) { +- eloop_unregister_read_sock(das->sock); +- close(das->sock); ++ if (das->port) { ++ dl_list_del(&das->list); ++ ++ if (dl_list_empty(&das->port->das_data)) ++ radius_das_close_port(das->port); + } + ++ os_free(das->nas_identifier); + os_free(das->shared_secret); + os_free(das); + } From 78c51de847102541795d7c93b05ae8321fcd50e7 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Tue, 27 Dec 2022 19:08:27 +0100 Subject: [PATCH 43/72] kernel: mediatek: improve ethernet fix for dealing with small fragments Replace the workaround on MT7986 with a proper fix. Software workaround is still needed on older chips. Signed-off-by: Felix Fietkau --- ..._eth_soc-work-around-issue-with-send.patch | 46 +++++++++++++------ ..._eth_soc-drop-generic-vlan-rx-offloa.patch | 12 ++--- 2 files changed, 37 insertions(+), 21 deletions(-) diff --git a/target/linux/generic/pending-5.15/732-10-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch b/target/linux/generic/pending-5.15/732-10-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch index ba86686eeb2..86ce481c2ee 100644 --- a/target/linux/generic/pending-5.15/732-10-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch +++ b/target/linux/generic/pending-5.15/732-10-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch @@ -1,12 +1,15 @@ From: Felix Fietkau Date: Thu, 3 Nov 2022 12:38:49 +0100 -Subject: [PATCH] net: ethernet: mtk_eth_soc: work around issue with - sending small fragments +Subject: [PATCH] net: ethernet: mtk_eth_soc: work around issue with sending + small fragments -When frames are sent with very small fragments, the DMA engine appears to -lock up and transmit attempts time out. Fix this by detecting the presence -of small fragments and use skb_gso_segment + skb_linearize to deal with -them +When lots of frames are sent with a number of very small fragments, an +internal FIFO can overflow, causing the DMA engine to lock up lock up and +transmit attempts time out. + +Fix this on MT7986 by increasing the reserved FIFO space. +Fix this on older chips by detecting the presence of small fragments and use +skb_gso_segment + skb_linearize to deal with them. Signed-off-by: Felix Fietkau --- @@ -42,11 +45,12 @@ Signed-off-by: Felix Fietkau bool gso = false; int tx_num; -@@ -1423,6 +1439,17 @@ static netdev_tx_t mtk_start_xmit(struct +@@ -1423,6 +1439,18 @@ static netdev_tx_t mtk_start_xmit(struct return NETDEV_TX_BUSY; } -+ if (skb_is_gso(skb) && mtk_skb_has_small_frag(skb)) { ++ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) && ++ skb_is_gso(skb) && mtk_skb_has_small_frag(skb)) { + segs = skb_gso_segment(skb, dev->features & ~NETIF_F_ALL_TSO); + if (IS_ERR(segs)) + goto drop; @@ -60,19 +64,31 @@ Signed-off-by: Felix Fietkau /* TSO: fill MSS info in tcp checksum field */ if (skb_is_gso(skb)) { if (skb_cow_head(skb, 0)) { -@@ -1438,8 +1465,13 @@ static netdev_tx_t mtk_start_xmit(struct +@@ -1438,8 +1466,14 @@ static netdev_tx_t mtk_start_xmit(struct } } - if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) - goto drop; -+ skb_list_walk_safe(skb, skb, next) { -+ if ((mtk_skb_has_small_frag(skb) && skb_linearize(skb)) || -+ mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) { -+ stats->tx_dropped++; -+ dev_kfree_skb_any(skb); ++ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ skb_list_walk_safe(skb, skb, next) { ++ if ((mtk_skb_has_small_frag(skb) && skb_linearize(skb)) || ++ mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) { ++ stats->tx_dropped++; ++ dev_kfree_skb_any(skb); ++ } + } -+ } if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) netif_tx_stop_all_queues(dev); +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -246,7 +246,7 @@ + #define MTK_CHK_DDONE_EN BIT(28) + #define MTK_DMAD_WR_WDONE BIT(26) + #define MTK_WCOMP_EN BIT(24) +-#define MTK_RESV_BUF (0x40 << 16) ++#define MTK_RESV_BUF (0x80 << 16) + #define MTK_MUTLI_CNT (0x4 << 12) + #define MTK_LEAKY_BUCKET_EN BIT(11) + diff --git a/target/linux/generic/pending-5.15/732-14-net-ethernet-mtk_eth_soc-drop-generic-vlan-rx-offloa.patch b/target/linux/generic/pending-5.15/732-14-net-ethernet-mtk_eth_soc-drop-generic-vlan-rx-offloa.patch index c3a879e5ab9..0d575b84a08 100644 --- a/target/linux/generic/pending-5.15/732-14-net-ethernet-mtk_eth_soc-drop-generic-vlan-rx-offloa.patch +++ b/target/linux/generic/pending-5.15/732-14-net-ethernet-mtk_eth_soc-drop-generic-vlan-rx-offloa.patch @@ -17,7 +17,7 @@ Signed-off-by: Felix Fietkau --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -1993,29 +1993,16 @@ static int mtk_poll_rx(struct napi_struc +@@ -1995,29 +1995,16 @@ static int mtk_poll_rx(struct napi_struc if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) mtk_ppe_check_skb(eth->ppe[0], skb, hash); @@ -50,7 +50,7 @@ Signed-off-by: Felix Fietkau } skb_record_rx_queue(skb, 0); -@@ -2832,29 +2819,11 @@ static netdev_features_t mtk_fix_feature +@@ -2834,29 +2821,11 @@ static netdev_features_t mtk_fix_feature static int mtk_set_features(struct net_device *dev, netdev_features_t features) { @@ -80,7 +80,7 @@ Signed-off-by: Felix Fietkau return 0; } -@@ -3153,30 +3122,6 @@ static int mtk_open(struct net_device *d +@@ -3155,30 +3124,6 @@ static int mtk_open(struct net_device *d struct mtk_eth *eth = mac->hw; int i, err; @@ -111,7 +111,7 @@ Signed-off-by: Felix Fietkau err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0); if (err) { netdev_err(dev, "%s: could not attach PHY: %d\n", __func__, -@@ -3217,6 +3162,35 @@ static int mtk_open(struct net_device *d +@@ -3219,6 +3164,35 @@ static int mtk_open(struct net_device *d phylink_start(mac->phylink); netif_tx_start_all_queues(dev); @@ -147,7 +147,7 @@ Signed-off-by: Felix Fietkau return 0; } -@@ -3510,10 +3484,9 @@ static int mtk_hw_init(struct mtk_eth *e +@@ -3512,10 +3486,9 @@ static int mtk_hw_init(struct mtk_eth *e if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { val = mtk_r32(eth, MTK_CDMP_IG_CTRL); mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL); @@ -160,7 +160,7 @@ Signed-off-by: Felix Fietkau /* set interrupt delays based on current Net DIM sample */ mtk_dim_rx(ð->rx_dim.work); -@@ -4134,7 +4107,7 @@ static int mtk_add_mac(struct mtk_eth *e +@@ -4136,7 +4109,7 @@ static int mtk_add_mac(struct mtk_eth *e eth->netdev[id]->hw_features |= NETIF_F_LRO; eth->netdev[id]->vlan_features = eth->soc->hw_features & From 425945c313b93d54a4bf870d95e85fb4c7c694a6 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Tue, 27 Dec 2022 19:09:38 +0100 Subject: [PATCH 44/72] kernel: mediatek: fix WED offload regression on MT7622 Fix dealing with DSA untagging offload Signed-off-by: Felix Fietkau --- ..._eth_soc-ppe-fix-L2-offloading-with-.patch | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 target/linux/generic/pending-5.15/734-net-ethernet-mtk_eth_soc-ppe-fix-L2-offloading-with-.patch diff --git a/target/linux/generic/pending-5.15/734-net-ethernet-mtk_eth_soc-ppe-fix-L2-offloading-with-.patch b/target/linux/generic/pending-5.15/734-net-ethernet-mtk_eth_soc-ppe-fix-L2-offloading-with-.patch new file mode 100644 index 00000000000..39d6d0c8795 --- /dev/null +++ b/target/linux/generic/pending-5.15/734-net-ethernet-mtk_eth_soc-ppe-fix-L2-offloading-with-.patch @@ -0,0 +1,55 @@ +From: Felix Fietkau +Date: Tue, 27 Dec 2022 15:02:51 +0100 +Subject: [PATCH] net: ethernet: mtk_eth_soc: ppe: fix L2 offloading with DSA + untagging offload enabled + +Check for skb metadata in order to detect the case where the DSA header is not +present. + +Fixes: 2d7605a72906 ("net: ethernet: mtk_eth_soc: enable hardware DSA untagging") +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -1992,9 +1992,6 @@ static int mtk_poll_rx(struct napi_struc + skb_checksum_none_assert(skb); + skb->protocol = eth_type_trans(skb, netdev); + +- if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) +- mtk_ppe_check_skb(eth->ppe[0], skb, hash); +- + /* When using VLAN untagging in combination with DSA, the + * hardware treats the MTK special tag as a VLAN and untags it. + */ +@@ -2007,6 +2004,9 @@ static int mtk_poll_rx(struct napi_struc + skb_dst_set_noref(skb, ð->dsa_meta[port]->dst); + } + ++ if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) ++ mtk_ppe_check_skb(eth->ppe[0], skb, hash); ++ + skb_record_rx_queue(skb, 0); + napi_gro_receive(napi, skb); + +--- a/drivers/net/ethernet/mediatek/mtk_ppe.c ++++ b/drivers/net/ethernet/mediatek/mtk_ppe.c +@@ -8,6 +8,7 @@ + #include + #include + #include ++#include + #include + #include "mtk_eth_soc.h" + #include "mtk_ppe.h" +@@ -756,7 +757,9 @@ void __mtk_ppe_check_skb(struct mtk_ppe + skb->dev->dsa_ptr->tag_ops->proto != DSA_TAG_PROTO_MTK) + goto out; + +- tag += 4; ++ if (!skb_metadata_dst(skb)) ++ tag += 4; ++ + if (get_unaligned_be16(tag) != ETH_P_8021Q) + break; + From 5863363493565f4b651baeb83251769f2b6d8929 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Wed, 28 Dec 2022 13:40:03 +0100 Subject: [PATCH 45/72] bcm27xx: fix BCMGENET kernel config MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Revert backported upstream commits 421f8663b3a7 and 8d820bc9d12b, which have introduced a regression in BCMGENET kconfig that disabled the network driver for the Raspberry Pi. Fixes: 0c405bceba11 ("kernel: bump 5.15 to 5.15.85") Fixes: e9008223268c ("kernel: bump 5.15 to 5.15.84") Signed-off-by: Álvaro Fernández Rojas --- ...com-Add-PTP_1588_CLOCK_OPTIONAL-depe.patch | 31 +++++++++++++++++++ ...rt-net-broadcom-Fix-BCMGENET-Kconfig.patch | 23 ++++++++++++++ 2 files changed, 54 insertions(+) create mode 100644 target/linux/bcm27xx/patches-5.15/200-Revert-net-broadcom-Add-PTP_1588_CLOCK_OPTIONAL-depe.patch create mode 100644 target/linux/bcm27xx/patches-5.15/201-Revert-net-broadcom-Fix-BCMGENET-Kconfig.patch diff --git a/target/linux/bcm27xx/patches-5.15/200-Revert-net-broadcom-Add-PTP_1588_CLOCK_OPTIONAL-depe.patch b/target/linux/bcm27xx/patches-5.15/200-Revert-net-broadcom-Add-PTP_1588_CLOCK_OPTIONAL-depe.patch new file mode 100644 index 00000000000..4357a6ba134 --- /dev/null +++ b/target/linux/bcm27xx/patches-5.15/200-Revert-net-broadcom-Add-PTP_1588_CLOCK_OPTIONAL-depe.patch @@ -0,0 +1,31 @@ +From 882882912cd25a637ba0cf09932ad248f584e680 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= +Date: Wed, 28 Dec 2022 13:19:49 +0100 +Subject: [PATCH 1/2] Revert "net: broadcom: Add PTP_1588_CLOCK_OPTIONAL + dependency for BCMGENET under ARCH_BCM2835" + +[ Upstream commit 421f8663b3a775c32f724f793264097c60028f2e ] + +This reverts commit eb96fd3983b2cca1c90db45eaff1de67b94f9950. +--- + drivers/net/ethernet/broadcom/Kconfig | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +--- a/drivers/net/ethernet/broadcom/Kconfig ++++ b/drivers/net/ethernet/broadcom/Kconfig +@@ -71,14 +71,13 @@ config BCM63XX_ENET + config BCMGENET + tristate "Broadcom GENET internal MAC support" + depends on HAS_IOMEM +- depends on PTP_1588_CLOCK_OPTIONAL || !ARCH_BCM2835 + select MII + select PHYLIB + select FIXED_PHY + select BCM7XXX_PHY + select MDIO_BCM_UNIMAC + select DIMLIB +- select BROADCOM_PHY if ARCH_BCM2835 ++ select BROADCOM_PHY if (ARCH_BCM2835 && PTP_1588_CLOCK_OPTIONAL) + help + This driver supports the built-in Ethernet MACs found in the + Broadcom BCM7xxx Set Top Box family chipset. diff --git a/target/linux/bcm27xx/patches-5.15/201-Revert-net-broadcom-Fix-BCMGENET-Kconfig.patch b/target/linux/bcm27xx/patches-5.15/201-Revert-net-broadcom-Fix-BCMGENET-Kconfig.patch new file mode 100644 index 00000000000..1e29da5c955 --- /dev/null +++ b/target/linux/bcm27xx/patches-5.15/201-Revert-net-broadcom-Fix-BCMGENET-Kconfig.patch @@ -0,0 +1,23 @@ +From f032f801658ce6b47498f3e140f7e4aef0645042 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= +Date: Wed, 28 Dec 2022 13:20:24 +0100 +Subject: [PATCH 2/2] Revert "net: broadcom: Fix BCMGENET Kconfig" + +[ Upstream commit 8d820bc9d12b8beebca836cceaf2bbe68216c2f8 ] + +This reverts commit 6a264203dbdb0d076891d83bf3bb274d6b3863f2. +--- + drivers/net/ethernet/broadcom/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/ethernet/broadcom/Kconfig ++++ b/drivers/net/ethernet/broadcom/Kconfig +@@ -77,7 +77,7 @@ config BCMGENET + select BCM7XXX_PHY + select MDIO_BCM_UNIMAC + select DIMLIB +- select BROADCOM_PHY if (ARCH_BCM2835 && PTP_1588_CLOCK_OPTIONAL) ++ select BROADCOM_PHY if ARCH_BCM2835 + help + This driver supports the built-in Ethernet MACs found in the + Broadcom BCM7xxx Set Top Box family chipset. From e143e27c8ca6b67af24c8bf8f2eb857919c35e48 Mon Sep 17 00:00:00 2001 From: Birger Koblitz Date: Thu, 12 May 2022 20:40:45 +0200 Subject: [PATCH 46/72] realtek: Fix reset register access The reset register on RTL93xx not merely have bits to execute a reset of a hardware component, but also configuration bits for reset procedures. Keep them during executing a reset. Signed-off-by: Birger Koblitz Signed-off-by: Olliver Schinagl [backport to 5.10 kernel] Signed-off-by: Sander Vanheule --- .../linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c | 2 +- .../linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c index 32de5cc5549..16a846c8d7f 100644 --- a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c +++ b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c @@ -682,7 +682,7 @@ static void rtl838x_hw_reset(struct rtl838x_eth_priv *priv) else reset_mask = 0xc; - sw_w32(reset_mask, priv->r->rst_glb_ctrl); + sw_w32_mask(0, reset_mask, priv->r->rst_glb_ctrl); do { /* Wait for reset of NIC and Queues done */ udelay(20); diff --git a/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.c b/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.c index 1c473cc7f3f..857d389f12d 100644 --- a/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.c +++ b/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.c @@ -675,7 +675,7 @@ static void rtl838x_hw_reset(struct rtl838x_eth_priv *priv) else reset_mask = 0xc; - sw_w32(reset_mask, priv->r->rst_glb_ctrl); + sw_w32_mask(0, reset_mask, priv->r->rst_glb_ctrl); do { /* Wait for reset of NIC and Queues done */ udelay(20); From 3f1e9f6f3b14385cab7ca6d1dcc2a4b658475bc3 Mon Sep 17 00:00:00 2001 From: Felix Baumann Date: Mon, 26 Dec 2022 21:40:43 +0100 Subject: [PATCH 47/72] ramips: add support for read/write uboot env to Asus RX-AX53U Add support for read/writing uboot env by renaming the second partition to its stock label "nvram" and remove the deemed unnecessary "read-only". Split the first partition "u-boot" in two, in order to allow `fw_setenv` safe write-access to the uboot environment variables. This implements hauke's request from [1]. Based on the patch provided by Shiji Yang. [1] https://github.com/openwrt/openwrt/pull/10400#discussion_r945153224 Co-Authored-By: Shiji Yang Signed-off-by: Felix Baumann [ improve commit title and description, fix some whitespace problem ] Signed-off-by: Christian Marangi --- target/linux/ramips/dts/mt7621_asus_rt-ax53u.dts | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/target/linux/ramips/dts/mt7621_asus_rt-ax53u.dts b/target/linux/ramips/dts/mt7621_asus_rt-ax53u.dts index aec8a0494d1..6a5cb0d7193 100644 --- a/target/linux/ramips/dts/mt7621_asus_rt-ax53u.dts +++ b/target/linux/ramips/dts/mt7621_asus_rt-ax53u.dts @@ -60,12 +60,21 @@ partition@0 { label = "u-boot"; - reg = <0x0 0xe0000>; + reg = <0x0 0x80000>; read-only; }; - partition@e0000 { + /* + * u-boot gets split here while keeping u-boot read-only, + * which allows safe usage of fw_setenv + */ + partition@80000 { label = "u-boot-env"; + reg = <0x80000 0x60000>; + }; + + partition@e0000 { + label = "nvram"; reg = <0xe0000 0x100000>; read-only; }; From 75451681d03e609ac8a3d1cd7469eefa53e18ca4 Mon Sep 17 00:00:00 2001 From: Felix Baumann Date: Mon, 26 Dec 2022 21:44:45 +0100 Subject: [PATCH 48/72] uboot-envtools: add support for ramips Asus RX-AX53U Adds uboot-envtools support for ramips Asus RX-AX53U now that partition can be correctly read. Signed-off-by: Felix Baumann [ improve commit title and description ] Signed-off-by: Christian Marangi --- package/boot/uboot-envtools/files/ramips | 1 + 1 file changed, 1 insertion(+) diff --git a/package/boot/uboot-envtools/files/ramips b/package/boot/uboot-envtools/files/ramips index 9cb47cd774d..372b8a49e2a 100644 --- a/package/boot/uboot-envtools/files/ramips +++ b/package/boot/uboot-envtools/files/ramips @@ -49,6 +49,7 @@ zbtlink,zbt-wg2626|\ zte,mf283plus) ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x1000" "0x10000" ;; +asus,rt-ax53u|\ belkin,rt1800|\ h3c,tx1800-plus|\ h3c,tx1801-plus|\ From 6c85c343d24d1d2ee1d3a02a2cbb06446f8eb3b6 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Wed, 28 Dec 2022 20:06:04 +0100 Subject: [PATCH 49/72] kernel: fix ethernet regression on mt7986 Signed-off-by: Felix Fietkau --- ...ernet-mtk_eth_soc-work-around-issue-with-send.patch | 10 +++++----- ...ernet-mtk_eth_soc-drop-packets-to-WDMA-if-the.patch | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/linux/generic/pending-5.15/732-10-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch b/target/linux/generic/pending-5.15/732-10-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch index 86ce481c2ee..f19128d809e 100644 --- a/target/linux/generic/pending-5.15/732-10-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch +++ b/target/linux/generic/pending-5.15/732-10-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch @@ -70,14 +70,14 @@ Signed-off-by: Felix Fietkau - if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) - goto drop; -+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) -+ skb_list_walk_safe(skb, skb, next) { -+ if ((mtk_skb_has_small_frag(skb) && skb_linearize(skb)) || -+ mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) { ++ skb_list_walk_safe(skb, skb, next) { ++ if ((!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) && ++ mtk_skb_has_small_frag(skb) && skb_linearize(skb)) || ++ mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) { + stats->tx_dropped++; + dev_kfree_skb_any(skb); -+ } + } ++ } if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) netif_tx_stop_all_queues(dev); diff --git a/target/linux/generic/pending-5.15/732-12-net-ethernet-mtk_eth_soc-drop-packets-to-WDMA-if-the.patch b/target/linux/generic/pending-5.15/732-12-net-ethernet-mtk_eth_soc-drop-packets-to-WDMA-if-the.patch index 6568e890d2e..416dfb6cf70 100644 --- a/target/linux/generic/pending-5.15/732-12-net-ethernet-mtk_eth_soc-drop-packets-to-WDMA-if-the.patch +++ b/target/linux/generic/pending-5.15/732-12-net-ethernet-mtk_eth_soc-drop-packets-to-WDMA-if-the.patch @@ -11,7 +11,7 @@ Signed-off-by: Felix Fietkau --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -3531,9 +3531,12 @@ static int mtk_hw_init(struct mtk_eth *e +@@ -3533,9 +3533,12 @@ static int mtk_hw_init(struct mtk_eth *e mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { From 4f44b4e506195efa37c51fdd99d8174503305265 Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Sun, 25 Dec 2022 00:51:20 +0100 Subject: [PATCH 50/72] linux-firmware: update to 20221214 Changes: f3c283e amdgpu: updated navi10 firmware for amd-5.4 ba115d4 amdgpu: updated yellow carp firmware for amd-5.4 b8aba70 amdgpu: updated raven2 firmware for amd-5.4 2b21c5e amdgpu: updated raven firmware for amd-5.4 fc9a1c9 amdgpu: updated PSP 13.0.8 firmware for amd-5.4 7d43336 amdgpu: updated GC 10.3.7 RLC firmware for amd-5.4 c089dab amdgpu: updated vega20 firmware for amd-5.4 75e3494 amdgpu: updated PSP 13.0.5 firmware for amd-5.4 31c5734 amdgpu: add VCN 4.0.0 firmware for amd-5.4 a735158 amdgpu: add SMU 13.0.0 firmware for amd-5.4 0bef6bb amdgpu: Add SDMA 6.0.0 firmware for amd-5.4 bb56d1a amdgpu: add PSP 13.0.0 firmware for amd-5.4 e32209f amdgpu: add GC 11.0.0 firmware for amd-5.4 613db81 amdgpu: add DCN 3.2.0 firmware for amd-5.4 1fc8f6c amdgpu: updated vega10 firmware for amd-5.4 2257447 amdgpu: updated beige goby firmware for amd-5.4 6aa0023 amdgpu: updated dimgrey cavefish firmware for amd-5.4 dd1225a amdgpu: updated vangogh firmware for amd-5.4 5cb010e amdgpu: updated picasso firmware for amd-5.4 edf9699 amdgpu: updated navy flounder firmware for amd-5.4 b7e83d9 amdgpu: updated green sardine firmware for amd-5.4 f820cc3 amdgpu: updated sienna cichlid firmware for amd-5.4 b77f539 amdgpu: updated arcture firmware for amd-5.4 dccfdf1 amdgpu: updated navi14 firmware for amd-5.4 5d1af6d amdgpu: updated renoir firmware for amd-5.4 13b9c94 amdgpu: updated navi12 firmware for amd-5.4 e9b8357 amdgpu: updated aldebaran firmware for amd-5.4 b4af754 sr150 : Add NXP SR150 UWB firmware 0707b2f brcm: add/update firmware files for brcmfmac driver 16c9630 rtl_bt: Update RTL8821C BT(USB I/F) FW to 0x75b8_f098 80ed874 amdgpu: update sdma_5.2.7 firmware 32d8681 QCA: Add Bluetooth firmware for WCN785x This commit will add required Bluetooth firmware files for QCA WCN785x. The image version is 2.0.0-00515. cdf9499 linux-firmware: update firmware for MT7916 685ea4d linux-firmware: update firmware for MT7915 7f6279b i915: Add DMC v2.08 for DG2 391fb47 amdgpu: update green sardine DMCUB firmware de854c9 i915: Add DMC v2.10 for MTL daff404 linux-firmware: update firmware for MT7986 70494e3 linux-firmware: update firmware for mediatek bluetooth chip (MT7921) 750c0dc linux-firmware: update firmware for MT7921 WiFi device Signed-off-by: Nick Hainke --- package/firmware/linux-firmware/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/firmware/linux-firmware/Makefile b/package/firmware/linux-firmware/Makefile index 69e3a948ad5..29c48086dd5 100644 --- a/package/firmware/linux-firmware/Makefile +++ b/package/firmware/linux-firmware/Makefile @@ -8,12 +8,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=linux-firmware -PKG_VERSION:=20221109 -PKG_RELEASE:=5 +PKG_VERSION:=20221214 +PKG_RELEASE:=1 PKG_SOURCE_URL:=@KERNEL/linux/kernel/firmware PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz -PKG_HASH:=c0ddffbbcf30f2e015bddd5c6d3ce1f13976b906aceabda4a57e3c41a3190701 +PKG_HASH:=e793783e92acbde549965521462d1d1327827360664cf242dbda08f075654331 PKG_MAINTAINER:=Felix Fietkau From 214c230a7919a7d8c833476ac8c63f9f2475b79f Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Wed, 28 Dec 2022 21:42:52 +0100 Subject: [PATCH 51/72] linux-firmware: ath11k: add symlink for WCN6855 hw2.1 WCN6855 exists in 2 HW revisions, but both use the same FW so upstream just has a symlink for hw2.1 to hw2.0 that I forgot to make. Fixes: b4d3694f81f4 ("linux-firmware: package ath11k consumer cards firmware") Signed-off-by: Robert Marko --- package/firmware/linux-firmware/Makefile | 2 +- package/firmware/linux-firmware/qca_ath11k.mk | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/package/firmware/linux-firmware/Makefile b/package/firmware/linux-firmware/Makefile index 29c48086dd5..70c63f172e8 100644 --- a/package/firmware/linux-firmware/Makefile +++ b/package/firmware/linux-firmware/Makefile @@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=linux-firmware PKG_VERSION:=20221214 -PKG_RELEASE:=1 +PKG_RELEASE:=2 PKG_SOURCE_URL:=@KERNEL/linux/kernel/firmware PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz diff --git a/package/firmware/linux-firmware/qca_ath11k.mk b/package/firmware/linux-firmware/qca_ath11k.mk index 3e997bc3f4a..b8f6ab8605d 100644 --- a/package/firmware/linux-firmware/qca_ath11k.mk +++ b/package/firmware/linux-firmware/qca_ath11k.mk @@ -19,5 +19,6 @@ define Package/ath11k-firmware-wcn6855/install $(INSTALL_DIR) $(1)/lib/firmware/ath11k/WCN6855/hw2.0 $(INSTALL_DATA) \ $(PKG_BUILD_DIR)/ath11k/WCN6855/hw2.0/* $(1)/lib/firmware/ath11k/WCN6855/hw2.0/ + $(LN) ./hw2.0 $(1)/lib/firmware/ath11k/WCN6855/hw2.1 endef $(eval $(call BuildPackage,ath11k-firmware-wcn6855)) From a14170b6e9c8bab493c5e0e7689405a8a0675e8a Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Tue, 20 Dec 2022 16:12:48 +0100 Subject: [PATCH 52/72] ath79: fix calibration-art for some boards "0x1000" looks suspicious. By looking at data provided by @DragonBluep I was able to identify the correct size for AR9380, AR9287 WiFis. Furthermore, PowerCloud Systems CAP324 has a AR9344 WiFi. Signed-off-by: Nick Hainke --- .../base-files/etc/hotplug.d/firmware/10-ath9k-eeprom | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom index 4f107bfe881..df7f1fc0cee 100644 --- a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom +++ b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom @@ -86,7 +86,8 @@ case "$FIRMWARE" in avm,fritz300e) caldata_extract_reverse "urloader" 0x1541 0x440 ;; - buffalo,wzr-hp-g450h) + buffalo,wzr-hp-g450h|\ + pcs,cap324) caldata_extract "art" 0x1000 0x440 ;; dlink,dir-825-c1|\ @@ -103,9 +104,8 @@ case "$FIRMWARE" in ;; netgear,wnr2200-8m|\ netgear,wnr2200-16m|\ - pcs,cap324|\ tplink,tl-wr842n-v1) - caldata_extract "art" 0x1000 0x1000 + caldata_extract "art" 0x1000 0x3e0 ;; wd,mynet-n600|\ wd,mynet-n750) @@ -113,7 +113,7 @@ case "$FIRMWARE" in ath9k_patch_mac $(mtd_get_mac_ascii devdata "wlan5mac") ;; wd,mynet-wifi-rangeextender) - caldata_extract "art" 0x1000 0x1000 + caldata_extract "art" 0x1000 0x440 ath9k_patch_mac $(nvram get wl0_hwaddr) ;; *) From ab8a5f2ea0e15e69a1f5e14642034eb75b2317fd Mon Sep 17 00:00:00 2001 From: Sander Vanheule Date: Wed, 28 Dec 2022 21:46:48 +0100 Subject: [PATCH 53/72] realtek: fix default image generation While cleaning up the makefiles for the realtek target, the order of the default image generating commands was accidentally changed. This caused the image signature to end up somewhere in the middle, misaligning the rootfs. As a result, sysupgrade couldn't verify upgrade images anymore, and devices end up in a boot loop due to the unaligned (and not found) rootfs. Fixes: 94d8b4852b9f ("realtek: Cleanup Makefiles") Signed-off-by: Sander Vanheule --- target/linux/realtek/image/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/linux/realtek/image/Makefile b/target/linux/realtek/image/Makefile index e4a3904aa83..66d7ee48954 100644 --- a/target/linux/realtek/image/Makefile +++ b/target/linux/realtek/image/Makefile @@ -102,11 +102,11 @@ define Device/Default IMAGES := sysupgrade.bin IMAGE/sysupgrade.bin := \ append-kernel | \ - append-metadata | \ + pad-to 64k | \ append-rootfs | \ - check-size | \ pad-rootfs | \ - pad-to 64k + check-size | \ + append-metadata endef include $(SUBTARGET).mk From 80be0fea03f19c8c19e8aa01380ef3d64ae353f9 Mon Sep 17 00:00:00 2001 From: Sander Vanheule Date: Tue, 27 Dec 2022 14:27:44 +0100 Subject: [PATCH 54/72] realtek: fix ZYXELS_VERS for GS1900-48 The GS1900-48 firmware image is identified by the 'AAHN' ID, while the GS1900-48HP is identified by 'AAHO' [1]. The latter was used, resulting in the following error message when upgrading via the stock web UI: Device only can support firmware from V1.00(AAHN.0) and later version Fix image generation by using the correct ID. [1] https://download.zyxel.com/GS1900-48/firmware/GS1900-48_2.70(AAHN.3)C0_2.pdf Link: https://forum.openwrt.org/t/146533 Fixes: 47f5a0a3eed5 ("realtek: Add support for ZyXEL GS1900-48 Switch") Suggested-by: Stefan Lippers-Hollmann Signed-off-by: Sander Vanheule --- target/linux/realtek/image/rtl839x.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/realtek/image/rtl839x.mk b/target/linux/realtek/image/rtl839x.mk index 081c13ff9b2..95dae0f8617 100644 --- a/target/linux/realtek/image/rtl839x.mk +++ b/target/linux/realtek/image/rtl839x.mk @@ -41,7 +41,7 @@ define Device/zyxel_gs1900-48 IMAGE_SIZE := 13952k DEVICE_VENDOR := ZyXEL UIMAGE_MAGIC := 0x83800000 - ZYXEL_VERS := AAHO + ZYXEL_VERS := AAHN DEVICE_MODEL := GS1900-48 KERNEL_INITRAMFS := \ kernel-bin | \ From 1e13081064113eb41ed62118bc49283b8c809eb8 Mon Sep 17 00:00:00 2001 From: Sander Vanheule Date: Wed, 28 Dec 2022 12:26:21 +0100 Subject: [PATCH 55/72] realtek: fix GS1900-48 firwmare partition The listed partition size doesn't match the original partition size, and actually overlaps with the following partition. The partition node name for the "firmware" partition also has an extra 'b' compared to the partition offset. Fixes: 47f5a0a3eed5 ("realtek: Add support for ZyXEL GS1900-48 Switch") Signed-off-by: Sander Vanheule --- target/linux/realtek/dts-5.10/rtl8393_zyxel_gs1900-48.dts | 4 ++-- target/linux/realtek/dts-5.15/rtl8393_zyxel_gs1900-48.dts | 4 ++-- target/linux/realtek/image/rtl839x.mk | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/linux/realtek/dts-5.10/rtl8393_zyxel_gs1900-48.dts b/target/linux/realtek/dts-5.10/rtl8393_zyxel_gs1900-48.dts index dd392c5a9be..48cfae67030 100644 --- a/target/linux/realtek/dts-5.10/rtl8393_zyxel_gs1900-48.dts +++ b/target/linux/realtek/dts-5.10/rtl8393_zyxel_gs1900-48.dts @@ -129,9 +129,9 @@ label = "jffs2"; reg = <0x160000 0x100000>; }; - partition@b260000 { + partition@260000 { label = "firmware"; - reg = <0x260000 0xda0000>; + reg = <0x260000 0x6d0000>; compatible = "openwrt,uimage", "denx,uimage"; openwrt,ih-magic = <0x83800000>; }; diff --git a/target/linux/realtek/dts-5.15/rtl8393_zyxel_gs1900-48.dts b/target/linux/realtek/dts-5.15/rtl8393_zyxel_gs1900-48.dts index dd392c5a9be..48cfae67030 100644 --- a/target/linux/realtek/dts-5.15/rtl8393_zyxel_gs1900-48.dts +++ b/target/linux/realtek/dts-5.15/rtl8393_zyxel_gs1900-48.dts @@ -129,9 +129,9 @@ label = "jffs2"; reg = <0x160000 0x100000>; }; - partition@b260000 { + partition@260000 { label = "firmware"; - reg = <0x260000 0xda0000>; + reg = <0x260000 0x6d0000>; compatible = "openwrt,uimage", "denx,uimage"; openwrt,ih-magic = <0x83800000>; }; diff --git a/target/linux/realtek/image/rtl839x.mk b/target/linux/realtek/image/rtl839x.mk index 95dae0f8617..b5e669fce4b 100644 --- a/target/linux/realtek/image/rtl839x.mk +++ b/target/linux/realtek/image/rtl839x.mk @@ -38,7 +38,7 @@ TARGET_DEVICES += tplink_sg2452p-v4 define Device/zyxel_gs1900-48 SOC := rtl8393 - IMAGE_SIZE := 13952k + IMAGE_SIZE := 6976k DEVICE_VENDOR := ZyXEL UIMAGE_MAGIC := 0x83800000 ZYXEL_VERS := AAHN From 045baca10b157fcc57461392cf27838d147ae5bd Mon Sep 17 00:00:00 2001 From: Sander Vanheule Date: Wed, 28 Dec 2022 21:39:46 +0100 Subject: [PATCH 56/72] realtek: deduplicate GS1900 recipes ZyXEL GS1900 devices with SoCs from both the RTL838x and RTL839x families share the same image structure and size of the firmware partition. Additionally, the GS1900-48 recipe provided a parameter for the zyxel-vers command, but this parameter is not used. Deduplicate the recipes by moving it to target/linux/realtek/image/common.mk. Signed-off-by: Sander Vanheule --- target/linux/realtek/image/common.mk | 12 ++++++++++++ target/linux/realtek/image/rtl838x.mk | 17 ++++------------- target/linux/realtek/image/rtl839x.mk | 12 ++---------- 3 files changed, 18 insertions(+), 23 deletions(-) diff --git a/target/linux/realtek/image/common.mk b/target/linux/realtek/image/common.mk index 0c515295696..702158978fa 100644 --- a/target/linux/realtek/image/common.mk +++ b/target/linux/realtek/image/common.mk @@ -52,3 +52,15 @@ define Device/hpe_1920 check-size | \ append-metadata endef + +define Device/zyxel_gs1900 + DEVICE_VENDOR := ZyXEL + IMAGE_SIZE := 6976k + UIMAGE_MAGIC := 0x83800000 + KERNEL_INITRAMFS := \ + kernel-bin | \ + append-dtb | \ + gzip | \ + zyxel-vers | \ + uImage gzip +endef diff --git a/target/linux/realtek/image/rtl838x.mk b/target/linux/realtek/image/rtl838x.mk index 6d670115497..8727bfa6fb1 100644 --- a/target/linux/realtek/image/rtl838x.mk +++ b/target/linux/realtek/image/rtl838x.mk @@ -218,21 +218,9 @@ define Device/tplink_sg2210p-v3 endef TARGET_DEVICES += tplink_sg2210p-v3 -define Device/zyxel_gs1900 - SOC := rtl8380 - IMAGE_SIZE := 6976k - DEVICE_VENDOR := ZyXEL - UIMAGE_MAGIC := 0x83800000 - KERNEL_INITRAMFS := \ - kernel-bin | \ - append-dtb | \ - gzip | \ - zyxel-vers | \ - uImage gzip -endef - define Device/zyxel_gs1900-10hp $(Device/zyxel_gs1900) + SOC := rtl8380 DEVICE_MODEL := GS1900-10HP ZYXEL_VERS := AAZI endef @@ -248,6 +236,7 @@ TARGET_DEVICES += zyxel_gs1900-16 define Device/zyxel_gs1900-8 $(Device/zyxel_gs1900) + SOC := rtl8380 DEVICE_MODEL := GS1900-8 ZYXEL_VERS := AAHH endef @@ -255,6 +244,7 @@ TARGET_DEVICES += zyxel_gs1900-8 define Device/zyxel_gs1900-8hp-v1 $(Device/zyxel_gs1900) + SOC := rtl8380 DEVICE_MODEL := GS1900-8HP DEVICE_VARIANT := v1 ZYXEL_VERS := AAHI @@ -264,6 +254,7 @@ TARGET_DEVICES += zyxel_gs1900-8hp-v1 define Device/zyxel_gs1900-8hp-v2 $(Device/zyxel_gs1900) + SOC := rtl8380 DEVICE_MODEL := GS1900-8HP DEVICE_VARIANT := v2 ZYXEL_VERS := AAHI diff --git a/target/linux/realtek/image/rtl839x.mk b/target/linux/realtek/image/rtl839x.mk index b5e669fce4b..e9f47786dc8 100644 --- a/target/linux/realtek/image/rtl839x.mk +++ b/target/linux/realtek/image/rtl839x.mk @@ -37,17 +37,9 @@ endef TARGET_DEVICES += tplink_sg2452p-v4 define Device/zyxel_gs1900-48 + $(Device/zyxel_gs1900) SOC := rtl8393 - IMAGE_SIZE := 6976k - DEVICE_VENDOR := ZyXEL - UIMAGE_MAGIC := 0x83800000 - ZYXEL_VERS := AAHN DEVICE_MODEL := GS1900-48 - KERNEL_INITRAMFS := \ - kernel-bin | \ - append-dtb | \ - gzip | \ - zyxel-vers $$$$(ZYXEL_VERS) | \ - uImage gzip + ZYXEL_VERS := AAHN endef TARGET_DEVICES += zyxel_gs1900-48 From 8bac5dc18a139e13338956e83d8dc4948824a82f Mon Sep 17 00:00:00 2001 From: Furong Xu Date: Thu, 22 Dec 2022 10:40:26 +0800 Subject: [PATCH 57/72] mediatek: add new layout for Xiaomi Redmi Router AX6000 for OpenWrt U-Boot This new layout is only bootable with OpenWrt U-Boot. It reuses the two crash partions and expands the ubi partion to the end of whole flash. Do not use this layout with stock U-Boot! Signed-off-by: Furong Xu --- ...7986a-xiaomi-redmi-router-ax6000-stock.dts | 18 ++++++++++++ ...6a-xiaomi-redmi-router-ax6000-ubootmod.dts | 16 ++++++++++ .../mt7986a-xiaomi-redmi-router-ax6000.dts | 18 ++++++++++++ .../mt7986a-xiaomi-redmi-router-ax6000.dtsi | 18 +----------- .../filogic/base-files/etc/board.d/01_leds | 3 +- .../filogic/base-files/etc/board.d/02_network | 6 ++-- .../base-files/lib/upgrade/platform.sh | 4 +++ target/linux/mediatek/image/filogic.mk | 29 +++++++++++++++++++ 8 files changed, 92 insertions(+), 20 deletions(-) create mode 100644 target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000-ubootmod.dts diff --git a/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000-stock.dts b/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000-stock.dts index 64342677b38..114076dffcd 100644 --- a/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000-stock.dts +++ b/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000-stock.dts @@ -8,7 +8,25 @@ compatible = "xiaomi,redmi-router-ax6000-stock", "mediatek,mt7986a"; }; +&spi_nand_flash { + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <64>; +}; + &partitions { + partition@580000 { + label = "crash"; + reg = <0x580000 0x40000>; + read-only; + }; + + partition@5c0000 { + label = "crash_log"; + reg = <0x5c0000 0x40000>; + read-only; + }; + partition@600000 { label = "ubi_kernel"; reg = <0x600000 0x1e00000>; diff --git a/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000-ubootmod.dts b/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000-ubootmod.dts new file mode 100644 index 00000000000..152bbd20f8c --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000-ubootmod.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +#include "mt7986a-xiaomi-redmi-router-ax6000.dtsi" + +/ { + model = "Xiaomi Redmi Router AX6000 (OpenWrt U-Boot layout)"; + compatible = "xiaomi,redmi-router-ax6000-ubootmod", "mediatek,mt7986a"; +}; + +&partitions { + partition@580000 { + label = "ubi"; + reg = <0x580000 0x7a80000>; + }; +}; diff --git a/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000.dts b/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000.dts index a8df7866320..62407334cf0 100644 --- a/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000.dts +++ b/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000.dts @@ -8,7 +8,25 @@ compatible = "xiaomi,redmi-router-ax6000", "mediatek,mt7986a"; }; +&spi_nand_flash { + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <64>; +}; + &partitions { + partition@580000 { + label = "crash"; + reg = <0x580000 0x40000>; + read-only; + }; + + partition@5c0000 { + label = "crash_log"; + reg = <0x5c0000 0x40000>; + read-only; + }; + /* ubi partition is the result of squashing * consecutive stock partitions: * - ubi diff --git a/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000.dtsi b/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000.dtsi index 1a80649721c..cd74fbec742 100644 --- a/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000.dtsi +++ b/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000.dtsi @@ -127,16 +127,12 @@ pinctrl-0 = <&spi_flash_pins>; status = "okay"; - flash@0 { + spi_nand_flash: flash@0 { compatible = "spi-nand"; #address-cells = <1>; #size-cells = <1>; reg = <0>; - mediatek,nmbm; - mediatek,bmt-max-ratio = <1>; - mediatek,bmt-max-reserved-blocks = <64>; - spi-max-frequency = <20000000>; spi-tx-buswidth = <4>; spi-rx-buswidth = <4>; @@ -181,18 +177,6 @@ reg = <0x380000 0x200000>; read-only; }; - - partition@580000 { - label = "crash"; - reg = <0x580000 0x40000>; - read-only; - }; - - partition@5c0000 { - label = "crash_log"; - reg = <0x5c0000 0x40000>; - read-only; - }; }; }; }; diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds b/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds index 8cfed15544d..d85b12fb665 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds @@ -7,7 +7,8 @@ board_config_update case $board in xiaomi,redmi-router-ax6000|\ -xiaomi,redmi-router-ax6000-stock) +xiaomi,redmi-router-ax6000-stock|\ +xiaomi,redmi-router-ax6000-ubootmod) ucidef_set_led_netdev "wan" "wan" "rgb:network" "wan" ;; esac diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network index 1c98dcc7cb3..608161f0ad9 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network @@ -17,7 +17,8 @@ mediatek_setup_interfaces() ucidef_set_interface_macaddr "wan" "$(macaddr_add $(cat /sys/class/net/eth0/address) 1)" ;; xiaomi,redmi-router-ax6000|\ - xiaomi,redmi-router-ax6000-stock) + xiaomi,redmi-router-ax6000-stock|\ + xiaomi,redmi-router-ax6000-ubootmod) ucidef_set_interfaces_lan_wan "lan2 lan3 lan4" wan ;; *) @@ -35,7 +36,8 @@ mediatek_setup_macs() case $board in xiaomi,redmi-router-ax6000|\ - xiaomi,redmi-router-ax6000-stock) + xiaomi,redmi-router-ax6000-stock|\ + xiaomi,redmi-router-ax6000-ubootmod) wan_mac=$(mtd_get_mac_ascii Bdata ethaddr_wan) label_mac=$wan_mac ;; diff --git a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh index 29c7a1475ed..c2808bc7368 100755 --- a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh +++ b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh @@ -64,6 +64,10 @@ platform_do_upgrade() { CI_ROOT_UBIPART=ubi nand_do_upgrade "$1" ;; + xiaomi,redmi-router-ax6000-ubootmod) + CI_KERNPART="fit" + nand_do_upgrade "$1" + ;; *) nand_do_upgrade "$1" ;; diff --git a/target/linux/mediatek/image/filogic.mk b/target/linux/mediatek/image/filogic.mk index 4e3399d120b..4b16cff56ef 100644 --- a/target/linux/mediatek/image/filogic.mk +++ b/target/linux/mediatek/image/filogic.mk @@ -157,3 +157,32 @@ endif IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata endef TARGET_DEVICES += xiaomi_redmi-router-ax6000-stock + +define Device/xiaomi_redmi-router-ax6000-ubootmod + DEVICE_VENDOR := Xiaomi + DEVICE_MODEL := Redmi Router AX6000 (OpenWrt U-Boot layout) + DEVICE_DTS := mt7986a-xiaomi-redmi-router-ax6000-ubootmod + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-leds-ws2812b + KERNEL_INITRAMFS_SUFFIX := -recovery.itb + IMAGES := sysupgrade.itb + KERNEL_LOADADDR := 0x48000000 + UBINIZE_OPTS := -E 5 + BLOCKSIZE := 128k + PAGESIZE := 2048 + KERNEL_IN_UBI := 1 + UBOOTENV_IN_UBI := 1 + KERNEL := kernel-bin | gzip + KERNEL_INITRAMFS := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k + IMAGE/sysupgrade.itb := append-kernel | \ + fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata + ARTIFACTS := preloader.bin bl31-uboot.fip + ARTIFACT/preloader.bin := bl2 spim-nand-ddr4 + ARTIFACT/bl31-uboot.fip := bl31-uboot xiaomi_redmi-router-ax6000 +ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + ARTIFACTS += initramfs-factory.ubi + ARTIFACT/initramfs-factory.ubi := append-image-stage initramfs-recovery.itb | ubinize-kernel +endif +endef +TARGET_DEVICES += xiaomi_redmi-router-ax6000-ubootmod From 1613e3340b829ea9aa6da954bf0ff98214b71751 Mon Sep 17 00:00:00 2001 From: Furong Xu Date: Thu, 22 Dec 2022 10:40:50 +0800 Subject: [PATCH 58/72] uboot-mediatek: add support for Xiaomi Redmi Router AX6000 U-Boot flash instructions: 0. OpenWrt U-Boot does not support stock layout, it comes with recovery boot support, automatic tftp recovery and never blocks UART. A new flash layout is introduced, we call it OpenWrt U-Boot layout, stock flash layout and the old OpenWrt layout are not supported. During the whole flash procedure, please do not reboot or power off unless requested explicitly, or you will break your device. 1. Your device should already running OpenWrt. If not, follow the instructions to flash OpenWrt: https://github.com/openwrt/openwrt/pull/11115 2. Backup BL2 Nvram Bdata Factory and FIP in case you break something or in case you want to go back to stock firmware one day. cat /dev/mtdblock0 > /tmp/BL2.bin cat /dev/mtdblock1 > /tmp/Nvram.bin cat /dev/mtdblock2 > /tmp/Bdata.bin cat /dev/mtdblock3 > /tmp/Factory.bin cat /dev/mtdblock4 > /tmp/FIP.bin And save all whose bin files to somewhere safe. Then backup your configurations, since ubiformat for entire mtd device is required to create new ubootenv volume for OpenWrt U-Boot. 3. Run the following cmd to boot into an initramfs with the new OpenWrt U-Boot layout that expand ubi partion to the end of flash: ubiformat /dev/mtd7 -y -f /tmp/ax6000-ubootmod-initramfs-factory.ubi 4. After boot into initramfs, check mtd partion info. The ubi partion should be mtd5 root@OpenWrt:~# cat /proc/mtd dev: size erasesize name mtd0: 00100000 00020000 BL2 mtd1: 00040000 00020000 Nvram mtd2: 00040000 00020000 Bdata mtd3: 00200000 00020000 Factory mtd4: 00200000 00020000 FIP mtd5: 07a80000 00020000 ubi 5. Load kmod-mtd-rw to temporarily make the bootloader partions writable. The kmod-mtd-rw is from the feeds, it is not packed in initramfs-factory by default. To install kmod-mtd-rw via opkg: opkg update && opkg install kmod-mtd-rw Or, download kmod-mtd-rw.ipk from OpenWrt server and install it manually e.g: https://downloads.openwrt.org/snapshots/targets/mediatek/filogic/kmods/ Select your OpenWrt release version and kernel version accordingly. Load kmod-mtd-rw: insmod /lib/modules/$(uname -r)/mtd-rw.ko i_want_a_brick=1 6. Run the following cmd to clean all pending crash dumps in pstore, or OpenWrt U-Boot may boot into NAND recovery or tftp recovery. rm -f /sys/fs/pstore/* 7. Format ubi and create new ubootenv volume: ubidetach -p /dev/mtd5; ubiformat /dev/mtd5 -y; ubiattach -p /dev/mtd5 ubimkvol /dev/ubi0 -n 0 -N ubootenv -s 128KiB ubimkvol /dev/ubi0 -n 1 -N ubootenv2 -s 128KiB 8. This is optional. Skip this if you do not want to have NAND recovery boot feature offered by OpenWrt U-Boot. Don't worry, you always have automatic tftp recovery feature enabled. ubimkvol /dev/ubi0 -n 2 -N recovery -s 10MiB ubiupdatevol /dev/ubi0_2 /tmp/ax6000-ubootmod-initramfs-recovery.itb 9. Now, flash new U-Boot. Bye-bye ugly stock U-Boot. mtd write /tmp/ax6000-ubootmod-preloader.bin BL2 mtd write /tmp/ax6000-ubootmod-bl31-uboot.fip FIP 10. Flash the squashfs-sysupgrade.bin as usual: sysupgrade -n /tmp/ax6000-ubootmod-squashfs-sysupgrade.itb Enjoy! Signed-off-by: Furong Xu --- .../uboot-envtools/files/mediatek_filogic | 8 + package/boot/uboot-mediatek/Makefile | 13 + .../patches/431-add-xiaomi_redmi-ax6000.patch | 391 ++++++++++++++++++ 3 files changed, 412 insertions(+) create mode 100644 package/boot/uboot-mediatek/patches/431-add-xiaomi_redmi-ax6000.patch diff --git a/package/boot/uboot-envtools/files/mediatek_filogic b/package/boot/uboot-envtools/files/mediatek_filogic index f73ea80109a..bdff66a17bc 100644 --- a/package/boot/uboot-envtools/files/mediatek_filogic +++ b/package/boot/uboot-envtools/files/mediatek_filogic @@ -39,6 +39,14 @@ xiaomi,redmi-router-ax6000-stock) ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x10000" "0x20000" ubootenv_add_uci_sys_config "/dev/mtd2" "0x0" "0x10000" "0x20000" ;; +xiaomi,redmi-router-ax6000-ubootmod) + . /lib/upgrade/nand.sh + local envubi=$(nand_find_ubi ubi) + local envdev=/dev/$(nand_find_volume $envubi ubootenv) + local envdev2=/dev/$(nand_find_volume $envubi ubootenv2) + ubootenv_add_uci_config "$envdev" "0x0" "0x1f000" "0x20000" "1" + ubootenv_add_uci_config "$envdev2" "0x0" "0x1f000" "0x20000" "1" + ;; esac config_load ubootenv diff --git a/package/boot/uboot-mediatek/Makefile b/package/boot/uboot-mediatek/Makefile index 9d823ec6981..866f6fa51a6 100644 --- a/package/boot/uboot-mediatek/Makefile +++ b/package/boot/uboot-mediatek/Makefile @@ -236,6 +236,18 @@ define U-Boot/mt7986_bananapi_bpi-r3-nor FIP_COMPRESS:=1 endef +define U-Boot/mt7986_xiaomi_redmi-router-ax6000 + NAME:=Xiaomi Redmi AX6000 + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=xiaomi_redmi-router-ax6000-ubootmod + UBOOT_CONFIG:=mt7986_xiaomi_redmi-ax6000 + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=spim-nand + BL2_SOC:=mt7986 + BL2_DDRTYPE:=ddr4 + DEPENDS:=+trusted-firmware-a-mt7986-spim-nand-ddr4 +endef + UBOOT_TARGETS := \ mt7620_mt7530_rfb \ mt7620_rfb \ @@ -256,6 +268,7 @@ UBOOT_TARGETS := \ mt7986_bananapi_bpi-r3-sdmmc \ mt7986_bananapi_bpi-r3-snand \ mt7986_bananapi_bpi-r3-nor \ + mt7986_xiaomi_redmi-router-ax6000 \ mt7986_rfb ifdef CONFIG_TARGET_mediatek diff --git a/package/boot/uboot-mediatek/patches/431-add-xiaomi_redmi-ax6000.patch b/package/boot/uboot-mediatek/patches/431-add-xiaomi_redmi-ax6000.patch new file mode 100644 index 00000000000..7628c6637c8 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/431-add-xiaomi_redmi-ax6000.patch @@ -0,0 +1,391 @@ +--- /dev/null ++++ b/configs/mt7986_xiaomi_redmi-ax6000_defconfig +@@ -0,0 +1,175 @@ ++CONFIG_ARM=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TARGET_MT7986=y ++CONFIG_SYS_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="mt7986a-xiaomi_redmi-ax6000" ++CONFIG_DEFAULT_ENV_FILE="xiaomi_redmi-ax6000_env" ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-xiaomi_redmi-ax6000.dtb" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++# CONFIG_LED is not set ++# CONFIG_LED_BLINK is not set ++# CONFIG_LED_GPIO is not set ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_SYS_PROMPT="MT7986> " ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++# CONFIG_CMD_EXT4 is not set ++# CONFIG_CMD_FAT is not set ++CONFIG_CMD_FDT=y ++# CONFIG_CMD_FS_GENERIC is not set ++# CONFIG_CMD_FS_UUID is not set ++CONFIG_CMD_GPIO=y ++# CONFIG_CMD_GPT is not set ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++# CONFIG_CMD_LED is not set ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_MTD=y ++# CONFIG_CMD_PCI is not set ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++# CONFIG_CMD_PWM is not set ++CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_CMD_UBIFS=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++# CONFIG_CMD_USB is not set ++# CONFIG_CMD_FLASH is not set ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++# CONFIG_DM_USB is not set ++# CONFIG_DM_PWM is not set ++# CONFIG_PWM_MTK is not set ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_NETCONSOLE=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_DM_GPIO=y ++# CONFIG_DM_SCSI is not set ++# CONFIG_AHCI is not set ++CONFIG_PHY=y ++# CONFIG_PHY_MTK_TPHY is not set ++CONFIG_PHY_FIXED=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++# CONFIG_PCI is not set ++# CONFIG_MMC is not set ++# CONFIG_DM_MMC is not set ++CONFIG_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y ++# CONFIG_DM_PCI is not set ++# CONFIG_PCIE_MEDIATEK is not set ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++# CONFIG_PINCTRL_MT7622 is not set ++CONFIG_POWER_DOMAIN=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++# CONFIG_I2C is not set ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++# CONFIG_USB is not set ++# CONFIG_USB_HOST is not set ++# CONFIG_USB_XHCI_HCD is not set ++# CONFIG_USB_XHCI_MTK is not set ++# CONFIG_USB_STORAGE is not set ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_SIZE=0x1f000 ++CONFIG_ENV_SIZE_REDUND=0x1f000 ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_PHY_FIXED=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7986=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_HEXDUMP=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTK_SPIM=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_NAND=y ++CONFIG_CMD_NAND_TRIMFFS=y ++CONFIG_LMB_MAX_REGIONS=64 +--- /dev/null ++++ b/arch/arm/dts/mt7986a-xiaomi_redmi-ax6000.dts +@@ -0,0 +1,152 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2021 MediaTek Inc. ++ * Author: Sam Shih ++ */ ++ ++/dts-v1/; ++#include "mt7986.dtsi" ++#include ++ ++/ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "Xiaomi Redmi AX6000"; ++ compatible = "mediatek,mt7986", "mediatek,mt7986-sd-rfb"; ++ ++ chosen { ++ stdout-path = &uart0; ++ tick-timer = &timer0; ++ }; ++ ++ keys { ++ compatible = "gpio-keys"; ++ factory { ++ label = "reset"; ++ gpios = <&gpio 9 GPIO_ACTIVE_LOW>; ++ }; ++ mesh { ++ label = "mesh"; ++ gpios = <&gpio 10 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++ status = "disabled"; ++}; ++ ++ð { ++ status = "okay"; ++ mediatek,gmac-id = <0>; ++ phy-mode = "sgmii"; ++ mediatek,switch = "mt7531"; ++ reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++}; ++ ++&pinctrl { ++ spic_pins: spi1-pins-func-1 { ++ mux { ++ function = "spi"; ++ groups = "spi1_2"; ++ }; ++ }; ++ ++ uart1_pins: spi1-pins-func-3 { ++ mux { ++ function = "uart"; ++ groups = "uart1_2"; ++ }; ++ }; ++ ++ spi_flash_pins: spi0-pins-func-1 { ++ mux { ++ function = "flash"; ++ groups = "spi0", "spi0_wp_hold"; ++ }; ++ ++ conf-pu { ++ pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; ++ drive-strength = ; ++ bias-pull-up = ; ++ }; ++ ++ conf-pd { ++ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; ++ drive-strength = ; ++ bias-pull-down = ; ++ }; ++ }; ++}; ++ ++&spi0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi_flash_pins>; ++ status = "okay"; ++ must_tx; ++ enhance_timing; ++ dma_ext; ++ ipm_design; ++ support_quad; ++ tick_dly = <1>; ++ sample_sel = <0>; ++ ++ spi_nand@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <52000000>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "bl2"; ++ reg = <0x0 0x80000>; ++ }; ++ ++ partition@100000 { ++ label = "nvram"; ++ reg = <0x100000 0x40000>; ++ }; ++ ++ partition@140000 { ++ label = "bdata"; ++ reg = <0x140000 0x40000>; ++ }; ++ ++ partition@180000 { ++ label = "factory"; ++ reg = <0x180000 0x200000>; ++ }; ++ ++ partition@380000 { ++ label = "fip"; ++ reg = <0x380000 0x200000>; ++ }; ++ ++ partition@600000 { ++ label = "ubi"; ++ reg = <0x580000 0x7a80000>; ++ }; ++ }; ++ }; ++}; ++ ++&watchdog { ++ status = "disabled"; ++}; +--- /dev/null ++++ b/xiaomi_redmi-ax6000_env +@@ -0,0 +1,55 @@ ++ethaddr_factory=mtd read factory 0x40080000 0x0 0x20000 && env readmem -b ethaddr 0x40080004 0x6 ; setenv ethaddr_factory ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x46000000 ++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0 ++bootargs=console=ttyS0,115200n8 console_msg_format=syslog ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi ++bootconf=config-1 ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-xiaomi_redmi-router-ax6000-ubootmod-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-filogic-xiaomi_redmi-router-ax6000-ubootmod-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-xiaomi_redmi-router-ax6000-ubootmod-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-filogic-xiaomi_redmi-router-ax6000-ubootmod-squashfs-sysupgrade.itb ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= ( ( ( OpenWrt ) ) ) ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=Load BL31+U-Boot FIP via TFTP then write to NAND.=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=Load BL2 preloader via TFTP then write to NAND.=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_8=Reboot.=reset ++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=run ubi_read_production && bootm $loadaddr#$bootconf ++boot_recovery=run ubi_read_recovery && bootm $loadaddr#$bootconf ++boot_ubi=run boot_production ; run boot_recovery ; run boot_tftp_forever ++boot_tftp_forever=while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run mtd_write_fip && run reset_factory ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run mtd_write_bl2 ++part_fit=fit ++reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 ++mtd_write_fip=mtd erase fip && mtd write fip $loadaddr ++mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 0 ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 1 ++ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset ++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi ++ubi_read_production=ubi read $loadaddr $part_fit && iminfo $loadaddr && run ubi_prepare_rootfs ++ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery ++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize ++_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run ethaddr_factory ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title $ver" From 9d8eff6799469e2ed8a5d2e4decd194902c1ec1b Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Wed, 28 Dec 2022 22:57:49 +0100 Subject: [PATCH 59/72] linux-firmware: disable stripping It has been brought to my attention that recently added WCN6855 firmware is broken as it is getting stripped during building due to being 2 ELF binaries. I am sure WCN6750 and any other ELF binaries are having the same issue, so since stripping firmware binaries is clearly unwanted disable it. Fixes: b4d3694f81f4 ("linux-firmware: package ath11k consumer cards firmware") Signed-off-by: Robert Marko --- package/firmware/linux-firmware/Makefile | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/package/firmware/linux-firmware/Makefile b/package/firmware/linux-firmware/Makefile index 70c63f172e8..7ffd8baf884 100644 --- a/package/firmware/linux-firmware/Makefile +++ b/package/firmware/linux-firmware/Makefile @@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=linux-firmware PKG_VERSION:=20221214 -PKG_RELEASE:=2 +PKG_RELEASE:=3 PKG_SOURCE_URL:=@KERNEL/linux/kernel/firmware PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz @@ -21,6 +21,9 @@ SCAN_DEPS = *.mk include $(INCLUDE_DIR)/package.mk +RSTRIP:=: +STRIP:=: + define Package/firmware-default SECTION:=firmware CATEGORY:=Firmware From 5292637feb42bf97fcc3eaa0c9312e804e256fca Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C5=A0imon=20Bo=C5=99ek?= Date: Wed, 15 Jun 2022 17:31:39 +0200 Subject: [PATCH 60/72] mpc85xx: add support for cpu type 8548 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 8540 cpu type corresponds to e500v1 core while 8548 cpu type corresponds to e500v2 core See https://www.nxp.com/products/processors-and-microcontrollers/legacy-mpu-mcus/powerquicc-processors:POWERQUICC_HOME#powerquicc-iii-mpc85xx and https://www.nxp.com/docs/en/application-note/AN2807.pdf . Co-authored-by: Josef Schlehofer Co-authored-by: Pali Rohár Signed-off-by: Šimon Bořek --- include/target.mk | 1 + 1 file changed, 1 insertion(+) diff --git a/include/target.mk b/include/target.mk index 708ba395c61..a62b1eb0527 100644 --- a/include/target.mk +++ b/include/target.mk @@ -235,6 +235,7 @@ ifeq ($(DUMP),1) ifeq ($(ARCH),powerpc) CPU_CFLAGS_603e:=-mcpu=603e CPU_CFLAGS_8540:=-mcpu=8540 + CPU_CFLAGS_8548:=-mcpu=8548 CPU_CFLAGS_405:=-mcpu=405 CPU_CFLAGS_440:=-mcpu=440 CPU_CFLAGS_464fp:=-mcpu=464fp From 2cad88b99fdae9766de84e6c1cb56f111eb53748 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C5=A0imon=20Bo=C5=99ek?= Date: Wed, 15 Jun 2022 17:38:38 +0200 Subject: [PATCH 61/72] mpc85xx: change CPU_TYPE from 8540 to 8548 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All subtargets as p1010, p1020, p2020 uses e500v2 cores [1] [2] [3] [4], so let's force cpu type to 8545 for all mpc85xx target even though there might exist device with e500v1, but there is no such router supported in OpenWrt and because of that it does not make sense to to set CPU_TYPE for each subtarget. All MPC85xx SoC can be found here: https://www.nxp.com/products/processors-and-microcontrollers/legacy-mpu-mcus/powerquicc-processors:POWERQUICC_HOME#powerquicc-iii-mpc85xx [1] https://www.nxp.com/docs/en/application-note/AN2807.pdf [2] https://www.nxp.com/docs/en/fact-sheet/QP1010FS.pdf [3] https://www.nxp.com/docs/en/product-brief/P1020PB.pdf [4] https://www.nxp.com/docs/en/fact-sheet/QP20XXFS.pdf Co-authored-by: Pali Rohár Signed-off-by: Šimon Bořek --- target/linux/mpc85xx/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/mpc85xx/Makefile b/target/linux/mpc85xx/Makefile index f5f5a9c5c18..552b9811047 100644 --- a/target/linux/mpc85xx/Makefile +++ b/target/linux/mpc85xx/Makefile @@ -7,7 +7,7 @@ include $(TOPDIR)/rules.mk ARCH:=powerpc BOARD:=mpc85xx BOARDNAME:=Freescale MPC85xx -CPU_TYPE:=8540 +CPU_TYPE:=8548 FEATURES:=squashfs ramdisk nand SUBTARGETS:=p1010 p1020 p2020 From 3195a992d6f635ad82dbe39ee584571371334450 Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Wed, 21 Dec 2022 10:34:03 +0100 Subject: [PATCH 62/72] ipq40xx: convert Aruba AP-303H to DSA and enable target again The target was disabled since noone did the DSA conversion. Add the conversion and enable it again. Tested-by: John Walshaw Signed-off-by: Bjoern Dobe Signed-off-by: Nick Hainke --- .../ipq40xx/base-files/etc/board.d/02_network | 1 + .../arm/boot/dts/qcom-ipq4029-ap-303h.dts | 32 +++++++++++++++++++ target/linux/ipq40xx/image/generic.mk | 3 +- 3 files changed, 34 insertions(+), 2 deletions(-) diff --git a/target/linux/ipq40xx/base-files/etc/board.d/02_network b/target/linux/ipq40xx/base-files/etc/board.d/02_network index 74f39ef6de9..bceb434bffd 100644 --- a/target/linux/ipq40xx/base-files/etc/board.d/02_network +++ b/target/linux/ipq40xx/base-files/etc/board.d/02_network @@ -69,6 +69,7 @@ ipq40xx_setup_interfaces() mikrotik,wap-r-ac) ucidef_set_interface_lan "sw-eth1 sw-eth2" ;; + aruba,ap-303h|\ netgear,rbr50|\ netgear,rbs50|\ netgear,srr60|\ diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-ap-303h.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-ap-303h.dts index 7978f90eb48..fba6209d993 100644 --- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-ap-303h.dts +++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-ap-303h.dts @@ -420,6 +420,38 @@ status = "okay"; }; +&gmac { + status = "okay"; +}; + +&switch { + status = "okay"; +}; + +&swport2 { + status = "okay"; + + label = "lan1"; +}; + +&swport3 { + status = "okay"; + + label = "lan2"; +}; + +&swport4 { + status = "okay"; + + label = "lan3"; +}; + +&swport5 { + status = "okay"; + + label = "wan"; +}; + &wifi0 { status = "okay"; qcom,ath10k-calibration-variant = "Aruba-AP-303"; diff --git a/target/linux/ipq40xx/image/generic.mk b/target/linux/ipq40xx/image/generic.mk index 290581ac80a..5dae52ff0ea 100644 --- a/target/linux/ipq40xx/image/generic.mk +++ b/target/linux/ipq40xx/image/generic.mk @@ -181,8 +181,7 @@ define Device/aruba_ap-303h $(call Device/aruba_glenmorangie) DEVICE_MODEL := AP-303H endef -# Missing DSA Setup -#TARGET_DEVICES += aruba_ap-303h +TARGET_DEVICES += aruba_ap-303h define Device/aruba_ap-365 $(call Device/aruba_glenmorangie) From f12bad6c19df4ad10b274e0c1e10bcdaaccf96f3 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sun, 18 Dec 2022 17:32:46 +0100 Subject: [PATCH 63/72] tree-wide: Do not use package librt and libpthread The libraries libpthread, libdl, libutil, libanl have been integrated into the libc library in version 2.34. it is not needed to explicitly link them any more. Most of the functions have been moved from the librt.so into libc.so some time ago already. Signed-off-by: Hauke Mehrtens --- include/package-defaults.mk | 2 +- package/network/services/hostapd/Makefile | 5 ----- package/system/fstools/Makefile | 3 +-- package/system/procd/Makefile | 3 +-- package/system/ubox/Makefile | 6 ++---- package/utils/e2fsprogs/Makefile | 1 - package/utils/lua/Makefile | 2 +- 7 files changed, 6 insertions(+), 16 deletions(-) diff --git a/include/package-defaults.mk b/include/package-defaults.mk index 3ee3a965f20..72f88b9bbbd 100644 --- a/include/package-defaults.mk +++ b/include/package-defaults.mk @@ -2,7 +2,7 @@ # # Copyright (C) 2006-2020 OpenWrt.org -PKG_DEFAULT_DEPENDS = +libc +USE_GLIBC:librt +USE_GLIBC:libpthread +PKG_DEFAULT_DEPENDS = +libc ifneq ($(PKG_NAME),toolchain) PKG_FIXUP_DEPENDS = $(if $(filter kmod-%,$(1)),$(2),$(PKG_DEFAULT_DEPENDS) $(filter-out $(PKG_DEFAULT_DEPENDS),$(2))) diff --git a/package/network/services/hostapd/Makefile b/package/network/services/hostapd/Makefile index 829879f7630..7daca315b0a 100644 --- a/package/network/services/hostapd/Makefile +++ b/package/network/services/hostapd/Makefile @@ -139,11 +139,6 @@ ifneq ($(LOCAL_TYPE),hostapd) endif endif -ifdef CONFIG_USE_GLIBC - TARGET_LDFLAGS += -lrt - TARGET_LDFLAGS_C += -lrt -endif - DRV_DEPENDS:=+PACKAGE_kmod-cfg80211:libnl-tiny diff --git a/package/system/fstools/Makefile b/package/system/fstools/Makefile index f7cb17461c2..f716f26c056 100644 --- a/package/system/fstools/Makefile +++ b/package/system/fstools/Makefile @@ -31,7 +31,6 @@ PKG_MAINTAINER:=John Crispin include $(INCLUDE_DIR)/package.mk include $(INCLUDE_DIR)/cmake.mk -TARGET_LDFLAGS += $(if $(CONFIG_USE_GLIBC),-lrt) CMAKE_OPTIONS += $(if $(CONFIG_FSTOOLS_UBIFS_EXTROOT),-DCMAKE_UBIFS_EXTROOT=y) CMAKE_OPTIONS += $(if $(CONFIG_FSTOOLS_OVL_MOUNT_FULL_ACCESS_TIME),-DCMAKE_OVL_MOUNT_FULL_ACCESS_TIME=y) CMAKE_OPTIONS += $(if $(CONFIG_FSTOOLS_OVL_MOUNT_COMPRESS_ZLIB),-DCMAKE_OVL_MOUNT_COMPRESS_ZLIB=y) @@ -39,7 +38,7 @@ CMAKE_OPTIONS += $(if $(CONFIG_FSTOOLS_OVL_MOUNT_COMPRESS_ZLIB),-DCMAKE_OVL_MOUN define Package/fstools SECTION:=base CATEGORY:=Base system - DEPENDS:=+ubox +USE_GLIBC:librt +NAND_SUPPORT:ubi-utils + DEPENDS:=+ubox +NAND_SUPPORT:ubi-utils TITLE:=OpenWrt filesystem tools MENU:=1 endef diff --git a/package/system/procd/Makefile b/package/system/procd/Makefile index 5e9733675a6..2eebe50a4fa 100644 --- a/package/system/procd/Makefile +++ b/package/system/procd/Makefile @@ -35,7 +35,6 @@ ifeq ($(DUMP),) endif CMAKE_OPTIONS += -DEARLY_PATH="$(TARGET_INIT_PATH)" -TARGET_LDFLAGS += $(if $(CONFIG_USE_GLIBC),-lrt) TARGET_CFLAGS += -flto TARGET_LDFLAGS += -flto @@ -43,7 +42,7 @@ TARGET_LDFLAGS += -flto define Package/procd/Default SECTION:=base CATEGORY:=Base system - DEPENDS:=+ubusd +ubus +libjson-script +ubox +USE_GLIBC:librt +libubox \ + DEPENDS:=+ubusd +ubus +libjson-script +ubox +libubox \ +libubus +libblobmsg-json +libjson-c +jshn TITLE:=OpenWrt system process manager USERID:=:dialout=20 :audio=29 diff --git a/package/system/ubox/Makefile b/package/system/ubox/Makefile index ca177b2c494..1030c14bb1a 100644 --- a/package/system/ubox/Makefile +++ b/package/system/ubox/Makefile @@ -18,12 +18,10 @@ PKG_MAINTAINER:=John Crispin include $(INCLUDE_DIR)/package.mk include $(INCLUDE_DIR)/cmake.mk -TARGET_LDFLAGS += $(if $(CONFIG_USE_GLIBC),-lrt) - define Package/ubox SECTION:=base CATEGORY:=Base system - DEPENDS:=+libubox +ubusd +ubus +libubus +libuci +USE_GLIBC:librt + DEPENDS:=+libubox +ubusd +ubus +libubus +libuci TITLE:=OpenWrt system helper toolbox ALTERNATIVES:=\ 100:/sbin/rmmod:/sbin/kmodloader \ @@ -46,7 +44,7 @@ endef define Package/logd SECTION:=base CATEGORY:=Base system - DEPENDS:=+libubox +libubus +libblobmsg-json +USE_GLIBC:librt + DEPENDS:=+libubox +libubus +libblobmsg-json TITLE:=OpenWrt system log implementation USERID:=logd=514:logd=514 endef diff --git a/package/utils/e2fsprogs/Makefile b/package/utils/e2fsprogs/Makefile index 2ece58f3151..94f22a53cc8 100644 --- a/package/utils/e2fsprogs/Makefile +++ b/package/utils/e2fsprogs/Makefile @@ -144,7 +144,6 @@ endef TARGET_CFLAGS += $(FPIC) -ffunction-sections -fdata-sections -flto -TARGET_LDFLAGS += $(if $(CONFIG_USE_GLIBC),-lrt) TARGET_LDFLAGS += -flto CONFIGURE_ARGS += \ diff --git a/package/utils/lua/Makefile b/package/utils/lua/Makefile index 9d7cc406712..e4d2fd1c500 100644 --- a/package/utils/lua/Makefile +++ b/package/utils/lua/Makefile @@ -99,7 +99,7 @@ define Build/Compile RANLIB="$(TARGET_CROSS)ranlib" \ INSTALL_ROOT=/usr \ CFLAGS="$(TARGET_CPPFLAGS) $(TARGET_CFLAGS)" \ - MYLDFLAGS="$(TARGET_LDFLAGS) $(if $(CONFIG_USE_GLIBC),-lm -ldl)" \ + MYLDFLAGS="$(TARGET_LDFLAGS)" \ PKG_VERSION=$(PKG_VERSION) \ linux rm -rf $(PKG_INSTALL_DIR) From 7272203022e38bc125ced9831ae1983fe3a34f45 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Thu, 29 Dec 2022 19:01:15 +0100 Subject: [PATCH 64/72] ramips: Refresh patches The patch was not applying cleanly any more. Signed-off-by: Hauke Mehrtens --- .../700-net-ethernet-mediatek-support-net-labels.patch | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/linux/ramips/patches-5.15/700-net-ethernet-mediatek-support-net-labels.patch b/target/linux/ramips/patches-5.15/700-net-ethernet-mediatek-support-net-labels.patch index cdd81df9d4d..e1335c8ebc5 100644 --- a/target/linux/ramips/patches-5.15/700-net-ethernet-mediatek-support-net-labels.patch +++ b/target/linux/ramips/patches-5.15/700-net-ethernet-mediatek-support-net-labels.patch @@ -14,7 +14,7 @@ Signed-off-by: René van Dorst --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -3996,6 +3996,7 @@ static const struct net_device_ops mtk_n +@@ -3998,6 +3998,7 @@ static const struct net_device_ops mtk_n static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) { @@ -22,7 +22,7 @@ Signed-off-by: René van Dorst const __be32 *_id = of_get_property(np, "reg", NULL); phy_interface_t phy_mode; struct phylink *phylink; -@@ -4124,6 +4125,9 @@ static int mtk_add_mac(struct mtk_eth *e +@@ -4126,6 +4127,9 @@ static int mtk_add_mac(struct mtk_eth *e register_netdevice_notifier(&mac->device_notifier); } From d29dbf052a1d34d7891b67177e1739db5d5af0bb Mon Sep 17 00:00:00 2001 From: Chuanhong Guo Date: Fri, 30 Dec 2022 15:55:56 +0800 Subject: [PATCH 65/72] mediatek: drop redmi-ax6000 variant with modified env This variant uses xiaomi factory u-boot and modified u-boot-env & bootcmd. By modifying uboot-env, the xiaomi firmware recovery provided in the vendor u-boot doesn't work anymore. It's possible to put u-boot into a state where it refuese to take any serial input. If the u-boot is in this state, users can't restore their firmware without taking the flash off the board. We now have a -stock variant where the vendor u-boot is used in a way that xiaomi firmware recovery still works, and a -ubootmod variant where we get rid of all xiaomi components, have more usable space and no uart console lock. These two should cover all use cases and we don't need this variant anymore. Drop this redmi-ax6000 variant. Existing users of this variant should perform a u-boot mod or restore to the -stock layout. Signed-off-by: Chuanhong Guo --- .../uboot-envtools/files/mediatek_filogic | 1 - .../mt7986a-xiaomi-redmi-router-ax6000.dts | 42 ------------------- .../filogic/base-files/etc/board.d/01_leds | 1 - .../filogic/base-files/etc/board.d/02_network | 2 - target/linux/mediatek/image/filogic.mk | 15 ------- 5 files changed, 61 deletions(-) delete mode 100644 target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000.dts diff --git a/package/boot/uboot-envtools/files/mediatek_filogic b/package/boot/uboot-envtools/files/mediatek_filogic index bdff66a17bc..787fac8dd67 100644 --- a/package/boot/uboot-envtools/files/mediatek_filogic +++ b/package/boot/uboot-envtools/files/mediatek_filogic @@ -34,7 +34,6 @@ bananapi,bpi-r3) ;; esac ;; -xiaomi,redmi-router-ax6000|\ xiaomi,redmi-router-ax6000-stock) ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x10000" "0x20000" ubootenv_add_uci_sys_config "/dev/mtd2" "0x0" "0x10000" "0x20000" diff --git a/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000.dts b/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000.dts deleted file mode 100644 index 62407334cf0..00000000000 --- a/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000.dts +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) - -/dts-v1/; -#include "mt7986a-xiaomi-redmi-router-ax6000.dtsi" - -/ { - model = "Xiaomi Redmi Router AX6000"; - compatible = "xiaomi,redmi-router-ax6000", "mediatek,mt7986a"; -}; - -&spi_nand_flash { - mediatek,nmbm; - mediatek,bmt-max-ratio = <1>; - mediatek,bmt-max-reserved-blocks = <64>; -}; - -&partitions { - partition@580000 { - label = "crash"; - reg = <0x580000 0x40000>; - read-only; - }; - - partition@5c0000 { - label = "crash_log"; - reg = <0x5c0000 0x40000>; - read-only; - }; - - /* ubi partition is the result of squashing - * consecutive stock partitions: - * - ubi - * - ubi1 - * - overlay - */ - partition@600000 { - label = "ubi"; - reg = <0x600000 0x6e00000>; - }; - - /* last 12 MiB is reserved for NMBM bad block table */ -}; diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds b/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds index d85b12fb665..6b922de1635 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds @@ -6,7 +6,6 @@ board=$(board_name) board_config_update case $board in -xiaomi,redmi-router-ax6000|\ xiaomi,redmi-router-ax6000-stock|\ xiaomi,redmi-router-ax6000-ubootmod) ucidef_set_led_netdev "wan" "wan" "rgb:network" "wan" diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network index 608161f0ad9..13f52587c35 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network @@ -16,7 +16,6 @@ mediatek_setup_interfaces() ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 sfp2" "eth1 wan" ucidef_set_interface_macaddr "wan" "$(macaddr_add $(cat /sys/class/net/eth0/address) 1)" ;; - xiaomi,redmi-router-ax6000|\ xiaomi,redmi-router-ax6000-stock|\ xiaomi,redmi-router-ax6000-ubootmod) ucidef_set_interfaces_lan_wan "lan2 lan3 lan4" wan @@ -35,7 +34,6 @@ mediatek_setup_macs() local label_mac="" case $board in - xiaomi,redmi-router-ax6000|\ xiaomi,redmi-router-ax6000-stock|\ xiaomi,redmi-router-ax6000-ubootmod) wan_mac=$(mtd_get_mac_ascii Bdata ethaddr_wan) diff --git a/target/linux/mediatek/image/filogic.mk b/target/linux/mediatek/image/filogic.mk index 4b16cff56ef..5c223d04ff1 100644 --- a/target/linux/mediatek/image/filogic.mk +++ b/target/linux/mediatek/image/filogic.mk @@ -125,21 +125,6 @@ define Device/mediatek_mt7986b-rfb endef TARGET_DEVICES += mediatek_mt7986b-rfb -define Device/xiaomi_redmi-router-ax6000 - DEVICE_VENDOR := Xiaomi - DEVICE_MODEL := Redmi Router AX6000 - DEVICE_DTS := mt7986a-xiaomi-redmi-router-ax6000 - DEVICE_DTS_DIR := ../dts - DEVICE_PACKAGES := kmod-leds-ws2812b - KERNEL_LOADADDR := 0x48000000 - UBINIZE_OPTS := -E 5 - BLOCKSIZE := 128k - PAGESIZE := 2048 - KERNEL_IN_UBI := 1 - IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata -endef -TARGET_DEVICES += xiaomi_redmi-router-ax6000 - define Device/xiaomi_redmi-router-ax6000-stock DEVICE_VENDOR := Xiaomi DEVICE_MODEL := Redmi Router AX6000 (stock layout) From ef4e1ae18db2c64c2bd0146913fe1560536f9b26 Mon Sep 17 00:00:00 2001 From: INAGAKI Hiroshi Date: Wed, 23 Nov 2022 17:12:29 +0900 Subject: [PATCH 66/72] ramips: enable BBT on NAND in I-O DATA devices This patch enables MediaTek NAND BBT on I-O DATA devices manufactured by MSTC (MitraStar Technology Corp.). [WN-AX2033GR] Tested-by: Yanase Yuki [WN-AX1167GR2, WN-DX1167R, WN-DX1200GR, WN-DX2033GR] Tested-by: INAGAKI Hiroshi Signed-off-by: INAGAKI Hiroshi --- target/linux/ramips/dts/mt7621_iodata_wn-dx1200gr.dts | 5 +++++ target/linux/ramips/dts/mt7621_iodata_wn-xx-xr.dtsi | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/target/linux/ramips/dts/mt7621_iodata_wn-dx1200gr.dts b/target/linux/ramips/dts/mt7621_iodata_wn-dx1200gr.dts index 4837f29a46c..653132bc619 100644 --- a/target/linux/ramips/dts/mt7621_iodata_wn-dx1200gr.dts +++ b/target/linux/ramips/dts/mt7621_iodata_wn-dx1200gr.dts @@ -58,6 +58,11 @@ &nand { status = "okay"; + mediatek,bbt; + mediatek,bmt-remap-range = + <0x0000000 0x0800000>, + <0x3600000 0x4980000>; + partitions { compatible = "fixed-partitions"; #address-cells = <1>; diff --git a/target/linux/ramips/dts/mt7621_iodata_wn-xx-xr.dtsi b/target/linux/ramips/dts/mt7621_iodata_wn-xx-xr.dtsi index 89e7f4b3e9f..4b42fcb7de7 100644 --- a/target/linux/ramips/dts/mt7621_iodata_wn-xx-xr.dtsi +++ b/target/linux/ramips/dts/mt7621_iodata_wn-xx-xr.dtsi @@ -55,6 +55,11 @@ &nand { status = "okay"; + mediatek,bbt; + mediatek,bmt-remap-range = + <0x0000000 0x0800000>, + <0x3600000 0x4980000>; + partitions: partitions { compatible = "fixed-partitions"; #address-cells = <1>; From b6c7f90b17b32312eb0b151458ace3405c0544dd Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Thu, 29 Dec 2022 17:40:02 +0100 Subject: [PATCH 67/72] CI: labeler: Add target label to target packages This adds the target label also to changes in packages which are target specific like the boot loader of a target or some drivers which are only use on one target. Signed-off-by: Hauke Mehrtens --- .github/labeler.yml | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/.github/labeler.yml b/.github/labeler.yml index 0910d37bd5d..dd6636cf73c 100644 --- a/.github/labeler.yml +++ b/.github/labeler.yml @@ -9,54 +9,77 @@ - "target/linux/armvirt/**" "target/at91": - "target/linux/at91/**" + - "package/boot/at91bootstrap/**" + - "package/boot/uboot-at91/**" "target/ath25": - "target/linux/ath25/**" "target/ath79": - "target/linux/ath79/**" "target/bcm27xx": - "target/linux/bcm27xx/**" + - "package/kernel/bcm27xx-gpu-fw/**" "target/bcm47xx": - "target/linux/bcm47xx/**" "target/bcm4908": - "target/linux/bcm4908/**" + - "package/boot/uboot-bcm4908/**" "target/bcm53xx": - "target/linux/bcm53xx/**" "target/bcm63xx": - "target/linux/bcm63xx/**" + - "package/kernel/bcm63xx-cfe/**" + - "package/boot/arm-trusted-firmware-bcm63xx/**" "target/bmips": - "target/linux/bmips/**" "target/gemini": - "target/linux/gemini/**" "target/imx": - "target/linux/imx/**" + - "package/boot/imx-bootlets/**" + - "package/boot/uboot-imx/**" "target/ipq40xx": - "target/linux/ipq40xx/**" "target/ipq806x": - "target/linux/ipq806x/**" "target/kirkwood": - "target/linux/kirkwood/**" + - "package/boot/uboot-kirkwood/**" "target/lantiq": - "target/linux/lantiq/**" + - "package/kernel/lantiq/**" + - "package/firmware/lantiq/**" + - "package/boot/uboot-lantiq/**" "target/layerscape": - "target/linux/layerscape/**" + - "package/firmware/layerscape/**" + - "package/boot/tfa-layerscape/**" + - "package/boot/uboot-layerscape/**" + - "package/network/utils/layerscape/**" "target/malta": - "target/linux/malta/**" "target/mediatek": - "target/linux/mediatek/**" + - "package/boot/arm-trusted-firmware-mediatek/**" + - "package/boot/uboot-mediatek/**" "target/mpc85xx": - "target/linux/mpc85xx/**" "target/mvebu": - "target/linux/mvebu/**" + - "package/boot/arm-trusted-firmware-mvebu/**" + - "package/boot/uboot-mvebu/**" "target/mxs": - "target/linux/mxs/**" + - "package/boot/uboot-mxs/**" "target/octeon": - "target/linux/octeon/**" "target/octeontx": - "target/linux/octeontx/**" "target/omap": - "target/linux/omap/**" + - "package/boot/uboot-omap/**" "target/oxnas": - "target/linux/oxnas/**" + - "package/boot/uboot-oxnas/**" "target/pistachio": - "target/linux/pistachio/**" "target/qoriq": @@ -67,16 +90,22 @@ - "target/linux/realtek/**" "target/rockchip": - "target/linux/rockchip/**" + - "package/boot/arm-trusted-firmware-rockchip/**" + - "package/boot/uboot-rockchip/**" "target/sunxi": - "target/linux/sunxi/**" + - "package/boot/arm-trusted-firmware-sunxi/**" + - "package/boot/uboot-sunxi/**" "target/tegra": - "target/linux/tegra/**" + - "package/boot/uboot-tegra/**" "target/uml": - "target/linux/uml/**" "target/x86": - "target/linux/x86/**" "target/zynq": - "target/linux/zynq/**" + - "package/boot/uboot-zynq/**" # target/imagebuilder "target/imagebuilder": - "target/imagebuilder/**" From 2e61469a6c200c958bde0b564e435647dfc14c75 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Fri, 30 Dec 2022 16:42:03 +0100 Subject: [PATCH 68/72] netifd: update to the latest version 2cffe0c44e62 treewide: correctly apply IFNAMSIZ limit 96bcbb2e4eb6 wireless: allow set_retry ubus notify command to trigger a wdev restart a2e8cd75dbf6 wireless: add support for disabling multicast-to-unicast per virtual interface e9f44189ade7 system: move netdev types to system-linux.c where they are used a3fab0119ef1 utils: include utils.h last 7ce73fc16765 vlandev: propagate topology changes 81c1fbcba2f2 device: fix vlan device issues with disappearing lower devices Signed-off-by: Felix Fietkau --- package/network/config/netifd/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/network/config/netifd/Makefile b/package/network/config/netifd/Makefile index 488b9db2b0b..500daaa1522 100644 --- a/package/network/config/netifd/Makefile +++ b/package/network/config/netifd/Makefile @@ -5,9 +5,9 @@ PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/netifd.git -PKG_SOURCE_DATE:=2022-08-25 -PKG_SOURCE_VERSION:=76d2d41b7355e02f95fbfa79affbd232fb090595 -PKG_MIRROR_HASH:=cd754decce7d9f9c69e0ad8c6801f306fa37dd6c8a7039aea610c1c71d06b8f9 +PKG_SOURCE_DATE:=2022-12-30 +PKG_SOURCE_VERSION:=81c1fbcba2f27f687c2a471f341502d47679f401 +PKG_MIRROR_HASH:=41d19f2804759aa42708942e27116bec78b169abee639d97c2ec7f0f62fa7739 PKG_MAINTAINER:=Felix Fietkau PKG_LICENSE:=GPL-2.0 From defd016aefb5135e651ecfbffcfa2d5caf1cba7e Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Tue, 27 Dec 2022 11:22:18 +0100 Subject: [PATCH 69/72] bcm47xx: add tags to upstreamed patches All of the mtd patches are upstreamed to 5.18. Add tags indicating this. Signed-off-by: Nick Hainke --- ...18-mtd-rawnand-brcmnand-Assign-soc-as-early-as-possible.patch} | 0 ...td-rawnand-brcmnand-Allow-SoC-to-provide-I-O-operations.patch} | 0 ....18-mtd-rawnand-brcmnand-Avoid-pdev-in-brcmnand_init_cs.patch} | 0 ...and-brcmnand-Move-OF-operations-out-of-brcmnand_init_cs.patch} | 0 ...8-mtd-rawnand-brcmnand-Allow-working-without-interrupts.patch} | 0 ...d-rawnand-brcmnand-Add-platform-data-structure-for-BCMA.patch} | 0 ...8-mtd-rawnand-brcmnand-Allow-platform-data-instantation.patch} | 0 ...awnand-brcmnand-BCMA-controller-uses-command-shift-of-0.patch} | 0 ...m.patch => 108-v5.18-mtd-rawnand-brcmnand-Add-BCMA-shim.patch} | 0 9 files changed, 0 insertions(+), 0 deletions(-) rename target/linux/bcm47xx/patches-5.10/{100-mtd-rawnand-brcmnand-Assign-soc-as-early-as-possible.patch => 100-v5.18-mtd-rawnand-brcmnand-Assign-soc-as-early-as-possible.patch} (100%) rename target/linux/bcm47xx/patches-5.10/{101-mtd-rawnand-brcmnand-Allow-SoC-to-provide-I-O-operations.patch => 101-v5.18-mtd-rawnand-brcmnand-Allow-SoC-to-provide-I-O-operations.patch} (100%) rename target/linux/bcm47xx/patches-5.10/{102-mtd-rawnand-brcmnand-Avoid-pdev-in-brcmnand_init_cs.patch => 102-v5.18-mtd-rawnand-brcmnand-Avoid-pdev-in-brcmnand_init_cs.patch} (100%) rename target/linux/bcm47xx/patches-5.10/{103-mtd-rawnand-brcmnand-Move-OF-operations-out-of-brcmnand_init_cs.patch => 103-v5.18-mtd-rawnand-brcmnand-Move-OF-operations-out-of-brcmnand_init_cs.patch} (100%) rename target/linux/bcm47xx/patches-5.10/{104-mtd-rawnand-brcmnand-Allow-working-without-interrupts.patch => 104-v5.18-mtd-rawnand-brcmnand-Allow-working-without-interrupts.patch} (100%) rename target/linux/bcm47xx/patches-5.10/{105-mtd-rawnand-brcmnand-Add-platform-data-structure-for-BCMA.patch => 105-v5.18-mtd-rawnand-brcmnand-Add-platform-data-structure-for-BCMA.patch} (100%) rename target/linux/bcm47xx/patches-5.10/{106-mtd-rawnand-brcmnand-Allow-platform-data-instantation.patch => 106-v5.18-mtd-rawnand-brcmnand-Allow-platform-data-instantation.patch} (100%) rename target/linux/bcm47xx/patches-5.10/{107-mtd-rawnand-brcmnand-BCMA-controller-uses-command-shift-of-0.patch => 107-v5.18-mtd-rawnand-brcmnand-BCMA-controller-uses-command-shift-of-0.patch} (100%) rename target/linux/bcm47xx/patches-5.10/{108-mtd-rawnand-brcmnand-Add-BCMA-shim.patch => 108-v5.18-mtd-rawnand-brcmnand-Add-BCMA-shim.patch} (100%) diff --git a/target/linux/bcm47xx/patches-5.10/100-mtd-rawnand-brcmnand-Assign-soc-as-early-as-possible.patch b/target/linux/bcm47xx/patches-5.10/100-v5.18-mtd-rawnand-brcmnand-Assign-soc-as-early-as-possible.patch similarity index 100% rename from target/linux/bcm47xx/patches-5.10/100-mtd-rawnand-brcmnand-Assign-soc-as-early-as-possible.patch rename to target/linux/bcm47xx/patches-5.10/100-v5.18-mtd-rawnand-brcmnand-Assign-soc-as-early-as-possible.patch diff --git a/target/linux/bcm47xx/patches-5.10/101-mtd-rawnand-brcmnand-Allow-SoC-to-provide-I-O-operations.patch b/target/linux/bcm47xx/patches-5.10/101-v5.18-mtd-rawnand-brcmnand-Allow-SoC-to-provide-I-O-operations.patch similarity index 100% rename from target/linux/bcm47xx/patches-5.10/101-mtd-rawnand-brcmnand-Allow-SoC-to-provide-I-O-operations.patch rename to target/linux/bcm47xx/patches-5.10/101-v5.18-mtd-rawnand-brcmnand-Allow-SoC-to-provide-I-O-operations.patch diff --git a/target/linux/bcm47xx/patches-5.10/102-mtd-rawnand-brcmnand-Avoid-pdev-in-brcmnand_init_cs.patch b/target/linux/bcm47xx/patches-5.10/102-v5.18-mtd-rawnand-brcmnand-Avoid-pdev-in-brcmnand_init_cs.patch similarity index 100% rename from target/linux/bcm47xx/patches-5.10/102-mtd-rawnand-brcmnand-Avoid-pdev-in-brcmnand_init_cs.patch rename to target/linux/bcm47xx/patches-5.10/102-v5.18-mtd-rawnand-brcmnand-Avoid-pdev-in-brcmnand_init_cs.patch diff --git a/target/linux/bcm47xx/patches-5.10/103-mtd-rawnand-brcmnand-Move-OF-operations-out-of-brcmnand_init_cs.patch b/target/linux/bcm47xx/patches-5.10/103-v5.18-mtd-rawnand-brcmnand-Move-OF-operations-out-of-brcmnand_init_cs.patch similarity index 100% rename from target/linux/bcm47xx/patches-5.10/103-mtd-rawnand-brcmnand-Move-OF-operations-out-of-brcmnand_init_cs.patch rename to target/linux/bcm47xx/patches-5.10/103-v5.18-mtd-rawnand-brcmnand-Move-OF-operations-out-of-brcmnand_init_cs.patch diff --git a/target/linux/bcm47xx/patches-5.10/104-mtd-rawnand-brcmnand-Allow-working-without-interrupts.patch b/target/linux/bcm47xx/patches-5.10/104-v5.18-mtd-rawnand-brcmnand-Allow-working-without-interrupts.patch similarity index 100% rename from target/linux/bcm47xx/patches-5.10/104-mtd-rawnand-brcmnand-Allow-working-without-interrupts.patch rename to target/linux/bcm47xx/patches-5.10/104-v5.18-mtd-rawnand-brcmnand-Allow-working-without-interrupts.patch diff --git a/target/linux/bcm47xx/patches-5.10/105-mtd-rawnand-brcmnand-Add-platform-data-structure-for-BCMA.patch b/target/linux/bcm47xx/patches-5.10/105-v5.18-mtd-rawnand-brcmnand-Add-platform-data-structure-for-BCMA.patch similarity index 100% rename from target/linux/bcm47xx/patches-5.10/105-mtd-rawnand-brcmnand-Add-platform-data-structure-for-BCMA.patch rename to target/linux/bcm47xx/patches-5.10/105-v5.18-mtd-rawnand-brcmnand-Add-platform-data-structure-for-BCMA.patch diff --git a/target/linux/bcm47xx/patches-5.10/106-mtd-rawnand-brcmnand-Allow-platform-data-instantation.patch b/target/linux/bcm47xx/patches-5.10/106-v5.18-mtd-rawnand-brcmnand-Allow-platform-data-instantation.patch similarity index 100% rename from target/linux/bcm47xx/patches-5.10/106-mtd-rawnand-brcmnand-Allow-platform-data-instantation.patch rename to target/linux/bcm47xx/patches-5.10/106-v5.18-mtd-rawnand-brcmnand-Allow-platform-data-instantation.patch diff --git a/target/linux/bcm47xx/patches-5.10/107-mtd-rawnand-brcmnand-BCMA-controller-uses-command-shift-of-0.patch b/target/linux/bcm47xx/patches-5.10/107-v5.18-mtd-rawnand-brcmnand-BCMA-controller-uses-command-shift-of-0.patch similarity index 100% rename from target/linux/bcm47xx/patches-5.10/107-mtd-rawnand-brcmnand-BCMA-controller-uses-command-shift-of-0.patch rename to target/linux/bcm47xx/patches-5.10/107-v5.18-mtd-rawnand-brcmnand-BCMA-controller-uses-command-shift-of-0.patch diff --git a/target/linux/bcm47xx/patches-5.10/108-mtd-rawnand-brcmnand-Add-BCMA-shim.patch b/target/linux/bcm47xx/patches-5.10/108-v5.18-mtd-rawnand-brcmnand-Add-BCMA-shim.patch similarity index 100% rename from target/linux/bcm47xx/patches-5.10/108-mtd-rawnand-brcmnand-Add-BCMA-shim.patch rename to target/linux/bcm47xx/patches-5.10/108-v5.18-mtd-rawnand-brcmnand-Add-BCMA-shim.patch From 00952fb0caed57aa42cd173f1ece8d399993a136 Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Tue, 27 Dec 2022 11:35:42 +0100 Subject: [PATCH 70/72] bcm47xx: replace "Devices-database-update-patch" with upstream patches Replace "320-MIPS-BCM47XX-Devices-database-update-for-4.x.patch" with upstream patches: - 320-v5.17-MIPS-BCM47XX-Add-board-entry-for-Linksys-WRT320N-v1.patch - 321-v5.17-MIPS-BCM47XX-Add-support-for-Netgear-R6300-v1.patch - 322-v5.17-MIPS-BCM47XX-Add-support-for-Netgear-WN2500RP-v1-v2.patch - 323-v6.0-MIPS-BCM47XX-Add-support-for-Netgear-WNR3500L-v2.patch - 324-v5.17-MIPS-BCM47XX-Add-LEDs-and-buttons-for-Asus-RTN-10U.patch - 325-v5.17-MIPS-BCM47XX-Define-Linksys-WRT310N-V2-buttons.patch Signed-off-by: Nick Hainke --- ...47XX-Devices-database-update-for-4.x.patch | 268 ------------------ ...d-board-entry-for-Linksys-WRT320N-v1.patch | 89 ++++++ ...7XX-Add-support-for-Netgear-R6300-v1.patch | 60 ++++ ...d-support-for-Netgear-WN2500RP-v1-v2.patch | 63 ++++ ...-Add-support-for-Netgear-WNR3500L-v2.patch | 109 +++++++ ...dd-LEDs-and-buttons-for-Asus-RTN-10U.patch | 67 +++++ ...XX-Define-Linksys-WRT310N-V2-buttons.patch | 40 +++ 7 files changed, 428 insertions(+), 268 deletions(-) delete mode 100644 target/linux/bcm47xx/patches-5.10/320-MIPS-BCM47XX-Devices-database-update-for-4.x.patch create mode 100644 target/linux/bcm47xx/patches-5.10/320-v5.17-MIPS-BCM47XX-Add-board-entry-for-Linksys-WRT320N-v1.patch create mode 100644 target/linux/bcm47xx/patches-5.10/321-v5.17-MIPS-BCM47XX-Add-support-for-Netgear-R6300-v1.patch create mode 100644 target/linux/bcm47xx/patches-5.10/322-v5.17-MIPS-BCM47XX-Add-support-for-Netgear-WN2500RP-v1-v2.patch create mode 100644 target/linux/bcm47xx/patches-5.10/323-v6.0-MIPS-BCM47XX-Add-support-for-Netgear-WNR3500L-v2.patch create mode 100644 target/linux/bcm47xx/patches-5.10/324-v5.17-MIPS-BCM47XX-Add-LEDs-and-buttons-for-Asus-RTN-10U.patch create mode 100644 target/linux/bcm47xx/patches-5.10/325-v5.17-MIPS-BCM47XX-Define-Linksys-WRT310N-V2-buttons.patch diff --git a/target/linux/bcm47xx/patches-5.10/320-MIPS-BCM47XX-Devices-database-update-for-4.x.patch b/target/linux/bcm47xx/patches-5.10/320-MIPS-BCM47XX-Devices-database-update-for-4.x.patch deleted file mode 100644 index 8126768f72a..00000000000 --- a/target/linux/bcm47xx/patches-5.10/320-MIPS-BCM47XX-Devices-database-update-for-4.x.patch +++ /dev/null @@ -1,268 +0,0 @@ ---- a/arch/mips/bcm47xx/board.c -+++ b/arch/mips/bcm47xx/board.c -@@ -141,6 +141,7 @@ struct bcm47xx_board_type_list2 bcm47xx_ - {{BCM47XX_BOARD_LINKSYS_WRT300NV11, "Linksys WRT300N V1.1"}, "WRT300N", "1.1"}, - {{BCM47XX_BOARD_LINKSYS_WRT310NV1, "Linksys WRT310N V1"}, "WRT310N", "1.0"}, - {{BCM47XX_BOARD_LINKSYS_WRT310NV2, "Linksys WRT310N V2"}, "WRT310N", "2.0"}, -+ {{BCM47XX_BOARD_LINKSYS_WRT320N_V1, "Linksys WRT320N V1"}, "WRT320N", "1.0"}, - {{BCM47XX_BOARD_LINKSYS_WRT54G3GV2, "Linksys WRT54G3GV2-VF"}, "WRT54G3GV2-VF", "1.0"}, - {{BCM47XX_BOARD_LINKSYS_WRT610NV1, "Linksys WRT610N V1"}, "WRT610N", "1.0"}, - {{BCM47XX_BOARD_LINKSYS_WRT610NV2, "Linksys WRT610N V2"}, "WRT610N", "2.0"}, -@@ -161,9 +162,12 @@ struct bcm47xx_board_type_list1 bcm47xx_ - {{BCM47XX_BOARD_LUXUL_XWR_600_V1, "Luxul XWR-600 V1"}, "luxul_xwr600_v1"}, - {{BCM47XX_BOARD_LUXUL_XWR_1750_V1, "Luxul XWR-1750 V1"}, "luxul_xwr1750_v1"}, - {{BCM47XX_BOARD_NETGEAR_R6200_V1, "Netgear R6200 V1"}, "U12H192T00_NETGEAR"}, -+ {{BCM47XX_BOARD_NETGEAR_R6300_V1, "Netgear R6300 V1"}, "U12H218T00_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WGR614V8, "Netgear WGR614 V8"}, "U12H072T00_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WGR614V9, "Netgear WGR614 V9"}, "U12H094T00_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WGR614_V10, "Netgear WGR614 V10"}, "U12H139T01_NETGEAR"}, -+ {{BCM47XX_BOARD_NETGEAR_WN2500RP_V1, "Netgear WN2500RP V1"}, "U12H197T00_NETGEAR"}, -+ {{BCM47XX_BOARD_NETGEAR_WN2500RP_V2, "Netgear WN2500RP V2"}, "U12H294T00_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WNDR3300, "Netgear WNDR3300"}, "U12H093T00_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WNDR3400V1, "Netgear WNDR3400 V1"}, "U12H155T00_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WNDR3400V2, "Netgear WNDR3400 V2"}, "U12H187T00_NETGEAR"}, -@@ -177,6 +181,7 @@ struct bcm47xx_board_type_list1 bcm47xx_ - {{BCM47XX_BOARD_NETGEAR_WNR1000_V3, "Netgear WNR1000 V3"}, "U12H139T50_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WNR2000, "Netgear WNR2000"}, "U12H114T00_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WNR3500L, "Netgear WNR3500L"}, "U12H136T99_NETGEAR"}, -+ {{BCM47XX_BOARD_NETGEAR_WNR3500L_V2, "Netgear WNR3500L V2"}, "U12H172T00_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WNR3500U, "Netgear WNR3500U"}, "U12H136T00_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WNR3500V2, "Netgear WNR3500 V2"}, "U12H127T00_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WNR3500V2VC, "Netgear WNR3500 V2vc"}, "U12H127T70_NETGEAR"}, -@@ -191,6 +196,7 @@ struct bcm47xx_board_type_list3 bcm47xx_ - {{BCM47XX_BOARD_PHICOMM_M1, "Phicomm M1"}, "0x0590", "80", "0x1104"}, - {{BCM47XX_BOARD_ZTE_H218N, "ZTE H218N"}, "0x053d", "1234", "0x1305"}, - {{BCM47XX_BOARD_NETGEAR_WNR3500L, "Netgear WNR3500L"}, "0x04CF", "3500", "02"}, -+ {{BCM47XX_BOARD_NETGEAR_WNR3500L_V2, "Netgear WNR3500L V2"}, "0x052b", "3500L", "02"}, - {{BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0101, "Linksys WRT54G/GS/GL"}, "0x0101", "42", "0x10"}, - {{BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0467, "Linksys WRT54G/GS/GL"}, "0x0467", "42", "0x10"}, - {{BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0708, "Linksys WRT54G/GS/GL"}, "0x0708", "42", "0x10"}, ---- a/arch/mips/bcm47xx/buttons.c -+++ b/arch/mips/bcm47xx/buttons.c -@@ -27,6 +27,12 @@ - /* Asus */ - - static const struct gpio_keys_button -+bcm47xx_buttons_asus_rtn10u[] __initconst = { -+ BCM47XX_GPIO_KEY(20, KEY_WPS_BUTTON), -+ BCM47XX_GPIO_KEY(21, KEY_RESTART), -+}; -+ -+static const struct gpio_keys_button - bcm47xx_buttons_asus_rtn12[] __initconst = { - BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON), - BCM47XX_GPIO_KEY(1, KEY_RESTART), -@@ -277,6 +283,18 @@ bcm47xx_buttons_linksys_wrt310nv1[] __in - }; - - static const struct gpio_keys_button -+bcm47xx_buttons_linksys_wrt310n_v2[] __initconst = { -+ BCM47XX_GPIO_KEY(5, KEY_WPS_BUTTON), -+ BCM47XX_GPIO_KEY(6, KEY_RESTART), -+}; -+ -+static const struct gpio_keys_button -+bcm47xx_buttons_linksys_wrt320n_v1[] __initconst = { -+ BCM47XX_GPIO_KEY(5, KEY_WPS_BUTTON), -+ BCM47XX_GPIO_KEY(8, KEY_RESTART), -+}; -+ -+static const struct gpio_keys_button - bcm47xx_buttons_linksys_wrt54g3gv2[] __initconst = { - BCM47XX_GPIO_KEY(5, KEY_WIMAX), - BCM47XX_GPIO_KEY(6, KEY_RESTART), -@@ -392,6 +410,17 @@ bcm47xx_buttons_netgear_r6200_v1[] __ini - }; - - static const struct gpio_keys_button -+bcm47xx_buttons_netgear_r6300_v1[] __initconst = { -+ BCM47XX_GPIO_KEY(6, KEY_RESTART), -+}; -+ -+static const struct gpio_keys_button -+bcm47xx_buttons_netgear_wn2500rp_v1[] __initconst = { -+ BCM47XX_GPIO_KEY(12, KEY_RESTART), -+ BCM47XX_GPIO_KEY(31, KEY_WPS_BUTTON), -+}; -+ -+static const struct gpio_keys_button - bcm47xx_buttons_netgear_wndr3400v1[] __initconst = { - BCM47XX_GPIO_KEY(4, KEY_RESTART), - BCM47XX_GPIO_KEY(6, KEY_WPS_BUTTON), -@@ -431,6 +460,13 @@ bcm47xx_buttons_netgear_wnr3500lv1[] __i - }; - - static const struct gpio_keys_button -+bcm47xx_buttons_netgear_wnr3500lv2[] __initconst = { -+ BCM47XX_GPIO_KEY(4, KEY_RESTART), -+ BCM47XX_GPIO_KEY(6, KEY_WPS_BUTTON), -+ BCM47XX_GPIO_KEY(8, KEY_RFKILL), -+}; -+ -+static const struct gpio_keys_button - bcm47xx_buttons_netgear_wnr834bv2[] __initconst = { - BCM47XX_GPIO_KEY(6, KEY_RESTART), - }; -@@ -478,6 +514,9 @@ int __init bcm47xx_buttons_register(void - int err; - - switch (board) { -+ case BCM47XX_BOARD_ASUS_RTN10U: -+ err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_rtn10u); -+ break; - case BCM47XX_BOARD_ASUS_RTN12: - err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_rtn12); - break; -@@ -608,6 +647,12 @@ int __init bcm47xx_buttons_register(void - case BCM47XX_BOARD_LINKSYS_WRT310NV1: - err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt310nv1); - break; -+ case BCM47XX_BOARD_LINKSYS_WRT310NV2: -+ err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt310n_v2); -+ break; -+ case BCM47XX_BOARD_LINKSYS_WRT320N_V1: -+ err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt320n_v1); -+ break; - case BCM47XX_BOARD_LINKSYS_WRT54G3GV2: - err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt54g3gv2); - break; -@@ -674,6 +719,12 @@ int __init bcm47xx_buttons_register(void - case BCM47XX_BOARD_NETGEAR_R6200_V1: - err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_r6200_v1); - break; -+ case BCM47XX_BOARD_NETGEAR_R6300_V1: -+ err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_r6300_v1); -+ break; -+ case BCM47XX_BOARD_NETGEAR_WN2500RP_V1: -+ err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wn2500rp_v1); -+ break; - case BCM47XX_BOARD_NETGEAR_WNDR3400V1: - err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr3400v1); - break; -@@ -692,6 +743,9 @@ int __init bcm47xx_buttons_register(void - case BCM47XX_BOARD_NETGEAR_WNR3500L: - err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wnr3500lv1); - break; -+ case BCM47XX_BOARD_NETGEAR_WNR3500L_V2: -+ err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wnr3500lv2); -+ break; - case BCM47XX_BOARD_NETGEAR_WNR834BV2: - err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wnr834bv2); - break; ---- a/arch/mips/bcm47xx/leds.c -+++ b/arch/mips/bcm47xx/leds.c -@@ -30,6 +30,14 @@ - /* Asus */ - - static const struct gpio_led -+bcm47xx_leds_asus_rtn10u[] __initconst = { -+ BCM47XX_GPIO_LED(5, "green", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF), -+ BCM47XX_GPIO_LED(6, "green", "power", 1, LEDS_GPIO_DEFSTATE_ON), -+ BCM47XX_GPIO_LED(7, "green", "wps", 0, LEDS_GPIO_DEFSTATE_OFF), -+ BCM47XX_GPIO_LED(8, "green", "usb", 0, LEDS_GPIO_DEFSTATE_OFF), -+}; -+ -+static const struct gpio_led - bcm47xx_leds_asus_rtn12[] __initconst = { - BCM47XX_GPIO_LED(2, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON), - BCM47XX_GPIO_LED(7, "unk", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF), -@@ -314,6 +322,13 @@ bcm47xx_leds_linksys_wrt310nv1[] __initc - }; - - static const struct gpio_led -+bcm47xx_leds_linksys_wrt320n_v1[] __initconst = { -+ BCM47XX_GPIO_LED(1, "blue", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF), -+ BCM47XX_GPIO_LED(2, "blue", "power", 0, LEDS_GPIO_DEFSTATE_ON), -+ BCM47XX_GPIO_LED(4, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), -+}; -+ -+static const struct gpio_led - bcm47xx_leds_linksys_wrt54g_generic[] __initconst = { - BCM47XX_GPIO_LED(0, "unk", "dmz", 1, LEDS_GPIO_DEFSTATE_OFF), - BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON), -@@ -513,6 +528,14 @@ bcm47xx_leds_netgear_wnr3500lv1[] __init - }; - - static const struct gpio_led -+bcm47xx_leds_netgear_wnr3500lv2[] __initconst = { -+ BCM47XX_GPIO_LED(0, "blue", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF), -+ BCM47XX_GPIO_LED(1, "green", "wps", 0, LEDS_GPIO_DEFSTATE_OFF), -+ BCM47XX_GPIO_LED(3, "green", "power", 0, LEDS_GPIO_DEFSTATE_ON), -+ BCM47XX_GPIO_LED(7, "amber", "power", 0, LEDS_GPIO_DEFSTATE_OFF), -+}; -+ -+static const struct gpio_led - bcm47xx_leds_netgear_wnr834bv2[] __initconst = { - BCM47XX_GPIO_LED(2, "green", "power", 0, LEDS_GPIO_DEFSTATE_ON), - BCM47XX_GPIO_LED(3, "amber", "power", 0, LEDS_GPIO_DEFSTATE_OFF), -@@ -556,6 +579,9 @@ void __init bcm47xx_leds_register(void) - enum bcm47xx_board board = bcm47xx_board_get(); - - switch (board) { -+ case BCM47XX_BOARD_ASUS_RTN10U: -+ bcm47xx_set_pdata(bcm47xx_leds_asus_rtn10u); -+ break; - case BCM47XX_BOARD_ASUS_RTN12: - bcm47xx_set_pdata(bcm47xx_leds_asus_rtn12); - break; -@@ -689,6 +715,9 @@ void __init bcm47xx_leds_register(void) - case BCM47XX_BOARD_LINKSYS_WRT310NV1: - bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt310nv1); - break; -+ case BCM47XX_BOARD_LINKSYS_WRT320N_V1: -+ bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt320n_v1); -+ break; - case BCM47XX_BOARD_LINKSYS_WRT54G3GV2: - bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt54g3gv2); - break; -@@ -770,6 +799,9 @@ void __init bcm47xx_leds_register(void) - case BCM47XX_BOARD_NETGEAR_WNR3500L: - bcm47xx_set_pdata(bcm47xx_leds_netgear_wnr3500lv1); - break; -+ case BCM47XX_BOARD_NETGEAR_WNR3500L_V2: -+ bcm47xx_set_pdata(bcm47xx_leds_netgear_wnr3500lv2); -+ break; - case BCM47XX_BOARD_NETGEAR_WNR834BV2: - bcm47xx_set_pdata(bcm47xx_leds_netgear_wnr834bv2); - break; ---- a/arch/mips/bcm47xx/workarounds.c -+++ b/arch/mips/bcm47xx/workarounds.c -@@ -22,6 +22,7 @@ void __init bcm47xx_workarounds(void) - - switch (board) { - case BCM47XX_BOARD_NETGEAR_WNR3500L: -+ case BCM47XX_BOARD_NETGEAR_WNR3500L_V2: - bcm47xx_workarounds_enable_usb_power(12); - break; - case BCM47XX_BOARD_NETGEAR_WNDR3400V2: ---- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h -+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h -@@ -72,6 +72,7 @@ enum bcm47xx_board { - BCM47XX_BOARD_LINKSYS_WRT300NV11, - BCM47XX_BOARD_LINKSYS_WRT310NV1, - BCM47XX_BOARD_LINKSYS_WRT310NV2, -+ BCM47XX_BOARD_LINKSYS_WRT320N_V1, - BCM47XX_BOARD_LINKSYS_WRT54G3GV2, - BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0101, - BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0467, -@@ -99,9 +100,12 @@ enum bcm47xx_board { - BCM47XX_BOARD_MOTOROLA_WR850GV2V3, - - BCM47XX_BOARD_NETGEAR_R6200_V1, -+ BCM47XX_BOARD_NETGEAR_R6300_V1, - BCM47XX_BOARD_NETGEAR_WGR614V8, - BCM47XX_BOARD_NETGEAR_WGR614V9, - BCM47XX_BOARD_NETGEAR_WGR614_V10, -+ BCM47XX_BOARD_NETGEAR_WN2500RP_V1, -+ BCM47XX_BOARD_NETGEAR_WN2500RP_V2, - BCM47XX_BOARD_NETGEAR_WNDR3300, - BCM47XX_BOARD_NETGEAR_WNDR3400V1, - BCM47XX_BOARD_NETGEAR_WNDR3400V2, -@@ -114,6 +118,7 @@ enum bcm47xx_board { - BCM47XX_BOARD_NETGEAR_WNR1000_V3, - BCM47XX_BOARD_NETGEAR_WNR2000, - BCM47XX_BOARD_NETGEAR_WNR3500L, -+ BCM47XX_BOARD_NETGEAR_WNR3500L_V2, - BCM47XX_BOARD_NETGEAR_WNR3500U, - BCM47XX_BOARD_NETGEAR_WNR3500V2, - BCM47XX_BOARD_NETGEAR_WNR3500V2VC, diff --git a/target/linux/bcm47xx/patches-5.10/320-v5.17-MIPS-BCM47XX-Add-board-entry-for-Linksys-WRT320N-v1.patch b/target/linux/bcm47xx/patches-5.10/320-v5.17-MIPS-BCM47XX-Add-board-entry-for-Linksys-WRT320N-v1.patch new file mode 100644 index 00000000000..f34336edd5b --- /dev/null +++ b/target/linux/bcm47xx/patches-5.10/320-v5.17-MIPS-BCM47XX-Add-board-entry-for-Linksys-WRT320N-v1.patch @@ -0,0 +1,89 @@ +From 3829e4f10a232964cc728c0479c8097922e5e073 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli +Date: Thu, 6 Jan 2022 19:51:38 -0800 +Subject: [PATCH] MIPS: BCM47XX: Add board entry for Linksys WRT320N v1 + +This router is based on a Broadcom BCM4717A1 chipset and supports +802.11n Wi-Fi. Add a board entry for that router and register LEDs and +buttons accordingly. + +Signed-off-by: Florian Fainelli +Signed-off-by: Thomas Bogendoerfer +--- + arch/mips/bcm47xx/board.c | 1 + + arch/mips/bcm47xx/buttons.c | 9 +++++++++ + arch/mips/bcm47xx/leds.c | 10 ++++++++++ + arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h | 1 + + 4 files changed, 21 insertions(+) + +--- a/arch/mips/bcm47xx/board.c ++++ b/arch/mips/bcm47xx/board.c +@@ -141,6 +141,7 @@ struct bcm47xx_board_type_list2 bcm47xx_ + {{BCM47XX_BOARD_LINKSYS_WRT300NV11, "Linksys WRT300N V1.1"}, "WRT300N", "1.1"}, + {{BCM47XX_BOARD_LINKSYS_WRT310NV1, "Linksys WRT310N V1"}, "WRT310N", "1.0"}, + {{BCM47XX_BOARD_LINKSYS_WRT310NV2, "Linksys WRT310N V2"}, "WRT310N", "2.0"}, ++ {{BCM47XX_BOARD_LINKSYS_WRT320N_V1, "Linksys WRT320N V1"}, "WRT320N", "1.0"}, + {{BCM47XX_BOARD_LINKSYS_WRT54G3GV2, "Linksys WRT54G3GV2-VF"}, "WRT54G3GV2-VF", "1.0"}, + {{BCM47XX_BOARD_LINKSYS_WRT610NV1, "Linksys WRT610N V1"}, "WRT610N", "1.0"}, + {{BCM47XX_BOARD_LINKSYS_WRT610NV2, "Linksys WRT610N V2"}, "WRT610N", "2.0"}, +--- a/arch/mips/bcm47xx/buttons.c ++++ b/arch/mips/bcm47xx/buttons.c +@@ -277,6 +277,12 @@ bcm47xx_buttons_linksys_wrt310nv1[] __in + }; + + static const struct gpio_keys_button ++bcm47xx_buttons_linksys_wrt320n_v1[] __initconst = { ++ BCM47XX_GPIO_KEY(5, KEY_WPS_BUTTON), ++ BCM47XX_GPIO_KEY(8, KEY_RESTART), ++}; ++ ++static const struct gpio_keys_button + bcm47xx_buttons_linksys_wrt54g3gv2[] __initconst = { + BCM47XX_GPIO_KEY(5, KEY_WIMAX), + BCM47XX_GPIO_KEY(6, KEY_RESTART), +@@ -608,6 +614,9 @@ int __init bcm47xx_buttons_register(void + case BCM47XX_BOARD_LINKSYS_WRT310NV1: + err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt310nv1); + break; ++ case BCM47XX_BOARD_LINKSYS_WRT320N_V1: ++ err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt320n_v1); ++ break; + case BCM47XX_BOARD_LINKSYS_WRT54G3GV2: + err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt54g3gv2); + break; +--- a/arch/mips/bcm47xx/leds.c ++++ b/arch/mips/bcm47xx/leds.c +@@ -314,6 +314,13 @@ bcm47xx_leds_linksys_wrt310nv1[] __initc + }; + + static const struct gpio_led ++bcm47xx_leds_linksys_wrt320n_v1[] __initconst = { ++ BCM47XX_GPIO_LED(1, "blue", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF), ++ BCM47XX_GPIO_LED(2, "blue", "power", 0, LEDS_GPIO_DEFSTATE_ON), ++ BCM47XX_GPIO_LED(4, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), ++}; ++ ++static const struct gpio_led + bcm47xx_leds_linksys_wrt54g_generic[] __initconst = { + BCM47XX_GPIO_LED(0, "unk", "dmz", 1, LEDS_GPIO_DEFSTATE_OFF), + BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON), +@@ -689,6 +696,9 @@ void __init bcm47xx_leds_register(void) + case BCM47XX_BOARD_LINKSYS_WRT310NV1: + bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt310nv1); + break; ++ case BCM47XX_BOARD_LINKSYS_WRT320N_V1: ++ bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt320n_v1); ++ break; + case BCM47XX_BOARD_LINKSYS_WRT54G3GV2: + bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt54g3gv2); + break; +--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h ++++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h +@@ -72,6 +72,7 @@ enum bcm47xx_board { + BCM47XX_BOARD_LINKSYS_WRT300NV11, + BCM47XX_BOARD_LINKSYS_WRT310NV1, + BCM47XX_BOARD_LINKSYS_WRT310NV2, ++ BCM47XX_BOARD_LINKSYS_WRT320N_V1, + BCM47XX_BOARD_LINKSYS_WRT54G3GV2, + BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0101, + BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0467, diff --git a/target/linux/bcm47xx/patches-5.10/321-v5.17-MIPS-BCM47XX-Add-support-for-Netgear-R6300-v1.patch b/target/linux/bcm47xx/patches-5.10/321-v5.17-MIPS-BCM47XX-Add-support-for-Netgear-R6300-v1.patch new file mode 100644 index 00000000000..6631e79048b --- /dev/null +++ b/target/linux/bcm47xx/patches-5.10/321-v5.17-MIPS-BCM47XX-Add-support-for-Netgear-R6300-v1.patch @@ -0,0 +1,60 @@ +From 15e690af5cc3cd8f5d14ee2aa3a093f80196110e Mon Sep 17 00:00:00 2001 +From: Florian Fainelli +Date: Thu, 6 Jan 2022 19:51:40 -0800 +Subject: [PATCH] MIPS: BCM47XX: Add support for Netgear R6300 v1 + +Add support for the Netgear R6300 v1 Wi-Fi router using a Broadcom +BCM4706 chipset and supporting 802.11n and 802.11ac. + +Signed-off-by: Florian Fainelli +Signed-off-by: Thomas Bogendoerfer +--- + arch/mips/bcm47xx/board.c | 1 + + arch/mips/bcm47xx/buttons.c | 8 ++++++++ + arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h | 1 + + 3 files changed, 10 insertions(+) + +--- a/arch/mips/bcm47xx/board.c ++++ b/arch/mips/bcm47xx/board.c +@@ -162,6 +162,7 @@ struct bcm47xx_board_type_list1 bcm47xx_ + {{BCM47XX_BOARD_LUXUL_XWR_600_V1, "Luxul XWR-600 V1"}, "luxul_xwr600_v1"}, + {{BCM47XX_BOARD_LUXUL_XWR_1750_V1, "Luxul XWR-1750 V1"}, "luxul_xwr1750_v1"}, + {{BCM47XX_BOARD_NETGEAR_R6200_V1, "Netgear R6200 V1"}, "U12H192T00_NETGEAR"}, ++ {{BCM47XX_BOARD_NETGEAR_R6300_V1, "Netgear R6300 V1"}, "U12H218T00_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WGR614V8, "Netgear WGR614 V8"}, "U12H072T00_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WGR614V9, "Netgear WGR614 V9"}, "U12H094T00_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WGR614_V10, "Netgear WGR614 V10"}, "U12H139T01_NETGEAR"}, +--- a/arch/mips/bcm47xx/buttons.c ++++ b/arch/mips/bcm47xx/buttons.c +@@ -398,6 +398,11 @@ bcm47xx_buttons_netgear_r6200_v1[] __ini + }; + + static const struct gpio_keys_button ++bcm47xx_buttons_netgear_r6300_v1[] __initconst = { ++ BCM47XX_GPIO_KEY(6, KEY_RESTART), ++}; ++ ++static const struct gpio_keys_button + bcm47xx_buttons_netgear_wndr3400v1[] __initconst = { + BCM47XX_GPIO_KEY(4, KEY_RESTART), + BCM47XX_GPIO_KEY(6, KEY_WPS_BUTTON), +@@ -683,6 +688,9 @@ int __init bcm47xx_buttons_register(void + case BCM47XX_BOARD_NETGEAR_R6200_V1: + err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_r6200_v1); + break; ++ case BCM47XX_BOARD_NETGEAR_R6300_V1: ++ err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_r6300_v1); ++ break; + case BCM47XX_BOARD_NETGEAR_WNDR3400V1: + err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr3400v1); + break; +--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h ++++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h +@@ -100,6 +100,7 @@ enum bcm47xx_board { + BCM47XX_BOARD_MOTOROLA_WR850GV2V3, + + BCM47XX_BOARD_NETGEAR_R6200_V1, ++ BCM47XX_BOARD_NETGEAR_R6300_V1, + BCM47XX_BOARD_NETGEAR_WGR614V8, + BCM47XX_BOARD_NETGEAR_WGR614V9, + BCM47XX_BOARD_NETGEAR_WGR614_V10, diff --git a/target/linux/bcm47xx/patches-5.10/322-v5.17-MIPS-BCM47XX-Add-support-for-Netgear-WN2500RP-v1-v2.patch b/target/linux/bcm47xx/patches-5.10/322-v5.17-MIPS-BCM47XX-Add-support-for-Netgear-WN2500RP-v1-v2.patch new file mode 100644 index 00000000000..8f66aee1926 --- /dev/null +++ b/target/linux/bcm47xx/patches-5.10/322-v5.17-MIPS-BCM47XX-Add-support-for-Netgear-WN2500RP-v1-v2.patch @@ -0,0 +1,63 @@ +From 4da27b6d550427a0560a15df36de99cb17629216 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli +Date: Thu, 6 Jan 2022 19:51:41 -0800 +Subject: [PATCH] MIPS: BCM47XX: Add support for Netgear WN2500RP v1 & v2 + +Add support for the Netgear WN2500 RP v1 and v2 Wi-Fi range extenders +based on the BCM5357 chipset and supporting 802.11n and 802.11ac. + +Signed-off-by: Florian Fainelli +Signed-off-by: Thomas Bogendoerfer +--- + arch/mips/bcm47xx/board.c | 2 ++ + arch/mips/bcm47xx/buttons.c | 9 +++++++++ + arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h | 2 ++ + 3 files changed, 13 insertions(+) + +--- a/arch/mips/bcm47xx/board.c ++++ b/arch/mips/bcm47xx/board.c +@@ -166,6 +166,8 @@ struct bcm47xx_board_type_list1 bcm47xx_ + {{BCM47XX_BOARD_NETGEAR_WGR614V8, "Netgear WGR614 V8"}, "U12H072T00_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WGR614V9, "Netgear WGR614 V9"}, "U12H094T00_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WGR614_V10, "Netgear WGR614 V10"}, "U12H139T01_NETGEAR"}, ++ {{BCM47XX_BOARD_NETGEAR_WN2500RP_V1, "Netgear WN2500RP V1"}, "U12H197T00_NETGEAR"}, ++ {{BCM47XX_BOARD_NETGEAR_WN2500RP_V2, "Netgear WN2500RP V2"}, "U12H294T00_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WNDR3300, "Netgear WNDR3300"}, "U12H093T00_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WNDR3400V1, "Netgear WNDR3400 V1"}, "U12H155T00_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WNDR3400V2, "Netgear WNDR3400 V2"}, "U12H187T00_NETGEAR"}, +--- a/arch/mips/bcm47xx/buttons.c ++++ b/arch/mips/bcm47xx/buttons.c +@@ -403,6 +403,12 @@ bcm47xx_buttons_netgear_r6300_v1[] __ini + }; + + static const struct gpio_keys_button ++bcm47xx_buttons_netgear_wn2500rp_v1[] __initconst = { ++ BCM47XX_GPIO_KEY(12, KEY_RESTART), ++ BCM47XX_GPIO_KEY(31, KEY_WPS_BUTTON), ++}; ++ ++static const struct gpio_keys_button + bcm47xx_buttons_netgear_wndr3400v1[] __initconst = { + BCM47XX_GPIO_KEY(4, KEY_RESTART), + BCM47XX_GPIO_KEY(6, KEY_WPS_BUTTON), +@@ -691,6 +697,9 @@ int __init bcm47xx_buttons_register(void + case BCM47XX_BOARD_NETGEAR_R6300_V1: + err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_r6300_v1); + break; ++ case BCM47XX_BOARD_NETGEAR_WN2500RP_V1: ++ err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wn2500rp_v1); ++ break; + case BCM47XX_BOARD_NETGEAR_WNDR3400V1: + err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr3400v1); + break; +--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h ++++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h +@@ -104,6 +104,8 @@ enum bcm47xx_board { + BCM47XX_BOARD_NETGEAR_WGR614V8, + BCM47XX_BOARD_NETGEAR_WGR614V9, + BCM47XX_BOARD_NETGEAR_WGR614_V10, ++ BCM47XX_BOARD_NETGEAR_WN2500RP_V1, ++ BCM47XX_BOARD_NETGEAR_WN2500RP_V2, + BCM47XX_BOARD_NETGEAR_WNDR3300, + BCM47XX_BOARD_NETGEAR_WNDR3400V1, + BCM47XX_BOARD_NETGEAR_WNDR3400V2, diff --git a/target/linux/bcm47xx/patches-5.10/323-v6.0-MIPS-BCM47XX-Add-support-for-Netgear-WNR3500L-v2.patch b/target/linux/bcm47xx/patches-5.10/323-v6.0-MIPS-BCM47XX-Add-support-for-Netgear-WNR3500L-v2.patch new file mode 100644 index 00000000000..272a74933be --- /dev/null +++ b/target/linux/bcm47xx/patches-5.10/323-v6.0-MIPS-BCM47XX-Add-support-for-Netgear-WNR3500L-v2.patch @@ -0,0 +1,109 @@ +From c022e87162219d67d687df22c977d1c2fc95fb42 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli +Date: Thu, 14 Jul 2022 14:13:01 -0700 +Subject: [PATCH] MIPS: BCM47XX: Add support for Netgear WNR3500L v2 + +Add support for the Netgear WNR3500L v2 router based on the BCM47186 +chipset and supporting 802.11n Wi-Fi. + +Signed-off-by: Florian Fainelli +Signed-off-by: Thomas Bogendoerfer +--- + arch/mips/bcm47xx/board.c | 2 ++ + arch/mips/bcm47xx/buttons.c | 10 ++++++++++ + arch/mips/bcm47xx/leds.c | 11 +++++++++++ + arch/mips/bcm47xx/workarounds.c | 1 + + arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h | 1 + + 5 files changed, 25 insertions(+) + +--- a/arch/mips/bcm47xx/board.c ++++ b/arch/mips/bcm47xx/board.c +@@ -181,6 +181,7 @@ struct bcm47xx_board_type_list1 bcm47xx_ + {{BCM47XX_BOARD_NETGEAR_WNR1000_V3, "Netgear WNR1000 V3"}, "U12H139T50_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WNR2000, "Netgear WNR2000"}, "U12H114T00_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WNR3500L, "Netgear WNR3500L"}, "U12H136T99_NETGEAR"}, ++ {{BCM47XX_BOARD_NETGEAR_WNR3500L_V2, "Netgear WNR3500L V2"}, "U12H172T00_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WNR3500U, "Netgear WNR3500U"}, "U12H136T00_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WNR3500V2, "Netgear WNR3500 V2"}, "U12H127T00_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WNR3500V2VC, "Netgear WNR3500 V2vc"}, "U12H127T70_NETGEAR"}, +@@ -195,6 +196,7 @@ struct bcm47xx_board_type_list3 bcm47xx_ + {{BCM47XX_BOARD_PHICOMM_M1, "Phicomm M1"}, "0x0590", "80", "0x1104"}, + {{BCM47XX_BOARD_ZTE_H218N, "ZTE H218N"}, "0x053d", "1234", "0x1305"}, + {{BCM47XX_BOARD_NETGEAR_WNR3500L, "Netgear WNR3500L"}, "0x04CF", "3500", "02"}, ++ {{BCM47XX_BOARD_NETGEAR_WNR3500L_V2, "Netgear WNR3500L V2"}, "0x052b", "3500L", "02"}, + {{BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0101, "Linksys WRT54G/GS/GL"}, "0x0101", "42", "0x10"}, + {{BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0467, "Linksys WRT54G/GS/GL"}, "0x0467", "42", "0x10"}, + {{BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0708, "Linksys WRT54G/GS/GL"}, "0x0708", "42", "0x10"}, +--- a/arch/mips/bcm47xx/buttons.c ++++ b/arch/mips/bcm47xx/buttons.c +@@ -448,6 +448,13 @@ bcm47xx_buttons_netgear_wnr3500lv1[] __i + }; + + static const struct gpio_keys_button ++bcm47xx_buttons_netgear_wnr3500lv2[] __initconst = { ++ BCM47XX_GPIO_KEY(4, KEY_RESTART), ++ BCM47XX_GPIO_KEY(6, KEY_WPS_BUTTON), ++ BCM47XX_GPIO_KEY(8, KEY_RFKILL), ++}; ++ ++static const struct gpio_keys_button + bcm47xx_buttons_netgear_wnr834bv2[] __initconst = { + BCM47XX_GPIO_KEY(6, KEY_RESTART), + }; +@@ -718,6 +725,9 @@ int __init bcm47xx_buttons_register(void + case BCM47XX_BOARD_NETGEAR_WNR3500L: + err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wnr3500lv1); + break; ++ case BCM47XX_BOARD_NETGEAR_WNR3500L_V2: ++ err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wnr3500lv2); ++ break; + case BCM47XX_BOARD_NETGEAR_WNR834BV2: + err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wnr834bv2); + break; +--- a/arch/mips/bcm47xx/leds.c ++++ b/arch/mips/bcm47xx/leds.c +@@ -520,6 +520,14 @@ bcm47xx_leds_netgear_wnr3500lv1[] __init + }; + + static const struct gpio_led ++bcm47xx_leds_netgear_wnr3500lv2[] __initconst = { ++ BCM47XX_GPIO_LED(0, "blue", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF), ++ BCM47XX_GPIO_LED(1, "green", "wps", 0, LEDS_GPIO_DEFSTATE_OFF), ++ BCM47XX_GPIO_LED(3, "green", "power", 0, LEDS_GPIO_DEFSTATE_ON), ++ BCM47XX_GPIO_LED(7, "amber", "power", 0, LEDS_GPIO_DEFSTATE_OFF), ++}; ++ ++static const struct gpio_led + bcm47xx_leds_netgear_wnr834bv2[] __initconst = { + BCM47XX_GPIO_LED(2, "green", "power", 0, LEDS_GPIO_DEFSTATE_ON), + BCM47XX_GPIO_LED(3, "amber", "power", 0, LEDS_GPIO_DEFSTATE_OFF), +@@ -780,6 +788,9 @@ void __init bcm47xx_leds_register(void) + case BCM47XX_BOARD_NETGEAR_WNR3500L: + bcm47xx_set_pdata(bcm47xx_leds_netgear_wnr3500lv1); + break; ++ case BCM47XX_BOARD_NETGEAR_WNR3500L_V2: ++ bcm47xx_set_pdata(bcm47xx_leds_netgear_wnr3500lv2); ++ break; + case BCM47XX_BOARD_NETGEAR_WNR834BV2: + bcm47xx_set_pdata(bcm47xx_leds_netgear_wnr834bv2); + break; +--- a/arch/mips/bcm47xx/workarounds.c ++++ b/arch/mips/bcm47xx/workarounds.c +@@ -22,6 +22,7 @@ void __init bcm47xx_workarounds(void) + + switch (board) { + case BCM47XX_BOARD_NETGEAR_WNR3500L: ++ case BCM47XX_BOARD_NETGEAR_WNR3500L_V2: + bcm47xx_workarounds_enable_usb_power(12); + break; + case BCM47XX_BOARD_NETGEAR_WNDR3400V2: +--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h ++++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h +@@ -118,6 +118,7 @@ enum bcm47xx_board { + BCM47XX_BOARD_NETGEAR_WNR1000_V3, + BCM47XX_BOARD_NETGEAR_WNR2000, + BCM47XX_BOARD_NETGEAR_WNR3500L, ++ BCM47XX_BOARD_NETGEAR_WNR3500L_V2, + BCM47XX_BOARD_NETGEAR_WNR3500U, + BCM47XX_BOARD_NETGEAR_WNR3500V2, + BCM47XX_BOARD_NETGEAR_WNR3500V2VC, diff --git a/target/linux/bcm47xx/patches-5.10/324-v5.17-MIPS-BCM47XX-Add-LEDs-and-buttons-for-Asus-RTN-10U.patch b/target/linux/bcm47xx/patches-5.10/324-v5.17-MIPS-BCM47XX-Add-LEDs-and-buttons-for-Asus-RTN-10U.patch new file mode 100644 index 00000000000..23d50ad902c --- /dev/null +++ b/target/linux/bcm47xx/patches-5.10/324-v5.17-MIPS-BCM47XX-Add-LEDs-and-buttons-for-Asus-RTN-10U.patch @@ -0,0 +1,67 @@ +From aecf89f2f8e8a604c33085c230a1f04ea325de64 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli +Date: Thu, 6 Jan 2022 19:51:39 -0800 +Subject: [PATCH] MIPS: BCM47XX: Add LEDs and buttons for Asus RTN-10U + +Add the definitions for the buttons and LEDs used on the Asus RTN-10U +router. + +Signed-off-by: Florian Fainelli +Signed-off-by: Thomas Bogendoerfer +--- + arch/mips/bcm47xx/buttons.c | 9 +++++++++ + arch/mips/bcm47xx/leds.c | 11 +++++++++++ + 2 files changed, 20 insertions(+) + +--- a/arch/mips/bcm47xx/buttons.c ++++ b/arch/mips/bcm47xx/buttons.c +@@ -27,6 +27,12 @@ + /* Asus */ + + static const struct gpio_keys_button ++bcm47xx_buttons_asus_rtn10u[] __initconst = { ++ BCM47XX_GPIO_KEY(20, KEY_WPS_BUTTON), ++ BCM47XX_GPIO_KEY(21, KEY_RESTART), ++}; ++ ++static const struct gpio_keys_button + bcm47xx_buttons_asus_rtn12[] __initconst = { + BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON), + BCM47XX_GPIO_KEY(1, KEY_RESTART), +@@ -502,6 +508,9 @@ int __init bcm47xx_buttons_register(void + int err; + + switch (board) { ++ case BCM47XX_BOARD_ASUS_RTN10U: ++ err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_rtn10u); ++ break; + case BCM47XX_BOARD_ASUS_RTN12: + err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_rtn12); + break; +--- a/arch/mips/bcm47xx/leds.c ++++ b/arch/mips/bcm47xx/leds.c +@@ -30,6 +30,14 @@ + /* Asus */ + + static const struct gpio_led ++bcm47xx_leds_asus_rtn10u[] __initconst = { ++ BCM47XX_GPIO_LED(5, "green", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF), ++ BCM47XX_GPIO_LED(6, "green", "power", 1, LEDS_GPIO_DEFSTATE_ON), ++ BCM47XX_GPIO_LED(7, "green", "wps", 0, LEDS_GPIO_DEFSTATE_OFF), ++ BCM47XX_GPIO_LED(8, "green", "usb", 0, LEDS_GPIO_DEFSTATE_OFF), ++}; ++ ++static const struct gpio_led + bcm47xx_leds_asus_rtn12[] __initconst = { + BCM47XX_GPIO_LED(2, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON), + BCM47XX_GPIO_LED(7, "unk", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF), +@@ -571,6 +579,9 @@ void __init bcm47xx_leds_register(void) + enum bcm47xx_board board = bcm47xx_board_get(); + + switch (board) { ++ case BCM47XX_BOARD_ASUS_RTN10U: ++ bcm47xx_set_pdata(bcm47xx_leds_asus_rtn10u); ++ break; + case BCM47XX_BOARD_ASUS_RTN12: + bcm47xx_set_pdata(bcm47xx_leds_asus_rtn12); + break; diff --git a/target/linux/bcm47xx/patches-5.10/325-v5.17-MIPS-BCM47XX-Define-Linksys-WRT310N-V2-buttons.patch b/target/linux/bcm47xx/patches-5.10/325-v5.17-MIPS-BCM47XX-Define-Linksys-WRT310N-V2-buttons.patch new file mode 100644 index 00000000000..0c23e8aaf5d --- /dev/null +++ b/target/linux/bcm47xx/patches-5.10/325-v5.17-MIPS-BCM47XX-Define-Linksys-WRT310N-V2-buttons.patch @@ -0,0 +1,40 @@ +From eea175eedf3e2f71b9538d21e643e7a1be4923df Mon Sep 17 00:00:00 2001 +From: Florian Fainelli +Date: Thu, 6 Jan 2022 19:51:37 -0800 +Subject: [PATCH] MIPS: BCM47XX: Define Linksys WRT310N V2 buttons + +Update the buttons registration code to register the two buttons (WPS, +system rester) using the existing BCM47XX_BOARD_LINKSYS_WRT310NV2 board +entry. + +Signed-off-by: Florian Fainelli +Signed-off-by: Thomas Bogendoerfer +--- + arch/mips/bcm47xx/buttons.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/arch/mips/bcm47xx/buttons.c ++++ b/arch/mips/bcm47xx/buttons.c +@@ -289,6 +289,12 @@ bcm47xx_buttons_linksys_wrt320n_v1[] __i + }; + + static const struct gpio_keys_button ++bcm47xx_buttons_linksys_wrt310n_v2[] __initconst = { ++ BCM47XX_GPIO_KEY(5, KEY_WPS_BUTTON), ++ BCM47XX_GPIO_KEY(6, KEY_RESTART), ++}; ++ ++static const struct gpio_keys_button + bcm47xx_buttons_linksys_wrt54g3gv2[] __initconst = { + BCM47XX_GPIO_KEY(5, KEY_WIMAX), + BCM47XX_GPIO_KEY(6, KEY_RESTART), +@@ -644,6 +650,9 @@ int __init bcm47xx_buttons_register(void + case BCM47XX_BOARD_LINKSYS_WRT320N_V1: + err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt320n_v1); + break; ++ case BCM47XX_BOARD_LINKSYS_WRT310NV2: ++ err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt310n_v2); ++ break; + case BCM47XX_BOARD_LINKSYS_WRT54G3GV2: + err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt54g3gv2); + break; From 12fdb4c9f41281da7753818ea4ce54d9a4ed8984 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Fri, 30 Dec 2022 21:02:20 +0100 Subject: [PATCH 71/72] mac80211: fix receiving multicast packets on multiple sta interfaces Also fix MLO sta sdata link initialization Signed-off-by: Felix Fietkau --- ...x-initialization-of-rx-link-and-rx-l.patch | 56 ++++++++++--------- 1 file changed, 30 insertions(+), 26 deletions(-) diff --git a/package/kernel/mac80211/patches/subsys/307-wifi-mac80211-fix-initialization-of-rx-link-and-rx-l.patch b/package/kernel/mac80211/patches/subsys/307-wifi-mac80211-fix-initialization-of-rx-link-and-rx-l.patch index 857c1c84470..0201eeadb16 100644 --- a/package/kernel/mac80211/patches/subsys/307-wifi-mac80211-fix-initialization-of-rx-link-and-rx-l.patch +++ b/package/kernel/mac80211/patches/subsys/307-wifi-mac80211-fix-initialization-of-rx-link-and-rx-l.patch @@ -20,7 +20,7 @@ Signed-off-by: Felix Fietkau --- a/net/mac80211/rx.c +++ b/net/mac80211/rx.c -@@ -4067,6 +4067,56 @@ static void ieee80211_invoke_rx_handlers +@@ -4067,6 +4067,58 @@ static void ieee80211_invoke_rx_handlers #undef CALL_RXH } @@ -36,11 +36,15 @@ Signed-off-by: Felix Fietkau +static bool ieee80211_rx_data_set_link(struct ieee80211_rx_data *rx, + u8 link_id) +{ ++ rx->link_id = link_id; ++ rx->link = rcu_dereference(rx->sdata->link[link_id]); ++ ++ if (!rx->sta || !rx->sta->sta.mlo) ++ return rx->link; ++ + if (!ieee80211_rx_is_valid_sta_link_id(&rx->sta->sta, link_id)) + return false; + -+ rx->link_id = link_id; -+ rx->link = rcu_dereference(rx->sdata->link[link_id]); + rx->link_sta = rcu_dereference(rx->sta->link[link_id]); + + return rx->link && rx->link_sta; @@ -62,14 +66,12 @@ Signed-off-by: Felix Fietkau + if (!rx->sdata) + rx->sdata = sta->sdata; + rx->link_sta = &sta->deflink; -+ -+ if (link_id >= 0 && -+ !ieee80211_rx_data_set_link(rx, link_id)) -+ return false; + } + + if (link_id < 0) + rx->link = &rx->sdata->deflink; ++ else if (!ieee80211_rx_data_set_link(rx, link_id)) ++ return false; + + return true; +} @@ -77,7 +79,7 @@ Signed-off-by: Felix Fietkau /* * This function makes calls into the RX path, therefore * it has to be invoked under RCU read lock. -@@ -4075,16 +4125,19 @@ void ieee80211_release_reorder_timeout(s +@@ -4075,16 +4127,19 @@ void ieee80211_release_reorder_timeout(s { struct sk_buff_head frames; struct ieee80211_rx_data rx = { @@ -102,7 +104,7 @@ Signed-off-by: Felix Fietkau tid_agg_rx = rcu_dereference(sta->ampdu_mlme.tid_rx[tid]); if (!tid_agg_rx) -@@ -4104,10 +4157,6 @@ void ieee80211_release_reorder_timeout(s +@@ -4104,10 +4159,6 @@ void ieee80211_release_reorder_timeout(s }; drv_event_callback(rx.local, rx.sdata, &event); } @@ -113,7 +115,7 @@ Signed-off-by: Felix Fietkau ieee80211_rx_handlers(&rx, &frames); } -@@ -4123,7 +4172,6 @@ void ieee80211_mark_rx_ba_filtered_frame +@@ -4123,7 +4174,6 @@ void ieee80211_mark_rx_ba_filtered_frame /* This is OK -- must be QoS data frame */ .security_idx = tid, .seqno_idx = tid, @@ -121,7 +123,7 @@ Signed-off-by: Felix Fietkau }; int i, diff; -@@ -4134,10 +4182,8 @@ void ieee80211_mark_rx_ba_filtered_frame +@@ -4134,10 +4184,8 @@ void ieee80211_mark_rx_ba_filtered_frame sta = container_of(pubsta, struct sta_info, sta); @@ -134,7 +136,7 @@ Signed-off-by: Felix Fietkau rcu_read_lock(); tid_agg_rx = rcu_dereference(sta->ampdu_mlme.tid_rx[tid]); -@@ -4524,15 +4570,6 @@ void ieee80211_check_fast_rx_iface(struc +@@ -4524,15 +4572,6 @@ void ieee80211_check_fast_rx_iface(struc mutex_unlock(&local->sta_mtx); } @@ -150,7 +152,7 @@ Signed-off-by: Felix Fietkau static void ieee80211_rx_8023(struct ieee80211_rx_data *rx, struct ieee80211_fast_rx *fast_rx, int orig_len) -@@ -4643,7 +4680,6 @@ static bool ieee80211_invoke_fast_rx(str +@@ -4643,7 +4682,6 @@ static bool ieee80211_invoke_fast_rx(str struct sk_buff *skb = rx->skb; struct ieee80211_hdr *hdr = (void *)skb->data; struct ieee80211_rx_status *status = IEEE80211_SKB_RXCB(skb); @@ -158,7 +160,7 @@ Signed-off-by: Felix Fietkau int orig_len = skb->len; int hdrlen = ieee80211_hdrlen(hdr->frame_control); int snap_offs = hdrlen; -@@ -4655,7 +4691,6 @@ static bool ieee80211_invoke_fast_rx(str +@@ -4655,7 +4693,6 @@ static bool ieee80211_invoke_fast_rx(str u8 da[ETH_ALEN]; u8 sa[ETH_ALEN]; } addrs __aligned(2); @@ -166,7 +168,7 @@ Signed-off-by: Felix Fietkau struct ieee80211_sta_rx_stats *stats; /* for parallel-rx, we need to have DUP_VALIDATED, otherwise we write -@@ -4758,18 +4793,10 @@ static bool ieee80211_invoke_fast_rx(str +@@ -4758,18 +4795,10 @@ static bool ieee80211_invoke_fast_rx(str drop: dev_kfree_skb(skb); @@ -187,7 +189,7 @@ Signed-off-by: Felix Fietkau stats->dropped++; return true; -@@ -4787,8 +4814,8 @@ static bool ieee80211_prepare_and_rx_han +@@ -4787,8 +4816,8 @@ static bool ieee80211_prepare_and_rx_han struct ieee80211_local *local = rx->local; struct ieee80211_sub_if_data *sdata = rx->sdata; struct ieee80211_hdr *hdr = (void *)skb->data; @@ -198,7 +200,7 @@ Signed-off-by: Felix Fietkau rx->skb = skb; -@@ -4810,35 +4837,6 @@ static bool ieee80211_prepare_and_rx_han +@@ -4810,35 +4839,6 @@ static bool ieee80211_prepare_and_rx_han if (!ieee80211_accept_frame(rx)) return false; @@ -234,7 +236,7 @@ Signed-off-by: Felix Fietkau if (!consume) { struct skb_shared_hwtstamps *shwt; -@@ -4858,7 +4856,7 @@ static bool ieee80211_prepare_and_rx_han +@@ -4858,7 +4858,7 @@ static bool ieee80211_prepare_and_rx_han shwt->hwtstamp = skb_hwtstamps(skb)->hwtstamp; } @@ -243,7 +245,7 @@ Signed-off-by: Felix Fietkau /* translate to MLD addresses */ if (ether_addr_equal(link->conf->addr, hdr->addr1)) ether_addr_copy(hdr->addr1, rx->sdata->vif.addr); -@@ -4888,6 +4886,7 @@ static void __ieee80211_rx_handle_8023(s +@@ -4888,6 +4888,7 @@ static void __ieee80211_rx_handle_8023(s struct ieee80211_rx_status *status = IEEE80211_SKB_RXCB(skb); struct ieee80211_fast_rx *fast_rx; struct ieee80211_rx_data rx; @@ -251,7 +253,7 @@ Signed-off-by: Felix Fietkau memset(&rx, 0, sizeof(rx)); rx.skb = skb; -@@ -4904,12 +4903,8 @@ static void __ieee80211_rx_handle_8023(s +@@ -4904,12 +4905,8 @@ static void __ieee80211_rx_handle_8023(s if (!pubsta) goto drop; @@ -266,7 +268,7 @@ Signed-off-by: Felix Fietkau /* * TODO: Should the frame be dropped if the right link_id is not -@@ -4918,19 +4913,8 @@ static void __ieee80211_rx_handle_8023(s +@@ -4918,19 +4915,8 @@ static void __ieee80211_rx_handle_8023(s * link_id is used only for stats purpose and updating the stats on * the deflink is fine? */ @@ -288,7 +290,7 @@ Signed-off-by: Felix Fietkau fast_rx = rcu_dereference(rx.sta->fast_rx); if (!fast_rx) -@@ -4948,6 +4932,8 @@ static bool ieee80211_rx_for_interface(s +@@ -4948,6 +4934,8 @@ static bool ieee80211_rx_for_interface(s { struct link_sta_info *link_sta; struct ieee80211_hdr *hdr = (void *)skb->data; @@ -297,7 +299,7 @@ Signed-off-by: Felix Fietkau /* * Look up link station first, in case there's a -@@ -4957,24 +4943,19 @@ static bool ieee80211_rx_for_interface(s +@@ -4957,24 +4945,19 @@ static bool ieee80211_rx_for_interface(s */ link_sta = link_sta_info_get_bss(rx->sdata, hdr->addr2); if (link_sta) { @@ -330,7 +332,7 @@ Signed-off-by: Felix Fietkau return ieee80211_prepare_and_rx_handle(rx, skb, consume); } -@@ -5033,19 +5014,15 @@ static void __ieee80211_rx_handle_packet +@@ -5033,19 +5016,15 @@ static void __ieee80211_rx_handle_packet if (ieee80211_is_data(fc)) { struct sta_info *sta, *prev_sta; @@ -355,7 +357,7 @@ Signed-off-by: Felix Fietkau /* * In MLO connection, fetch the link_id using addr2 * when the driver does not pass link_id in status. -@@ -5063,7 +5040,7 @@ static void __ieee80211_rx_handle_packet +@@ -5063,7 +5042,7 @@ static void __ieee80211_rx_handle_packet if (!link_sta) goto out; @@ -364,7 +366,7 @@ Signed-off-by: Felix Fietkau } if (ieee80211_prepare_and_rx_handle(&rx, skb, true)) -@@ -5079,30 +5056,25 @@ static void __ieee80211_rx_handle_packet +@@ -5079,30 +5058,27 @@ static void __ieee80211_rx_handle_packet continue; } @@ -372,6 +374,7 @@ Signed-off-by: Felix Fietkau - !ieee80211_rx_is_valid_sta_link_id(&prev_sta->sta, - link_id)) || - (!status->link_valid && prev_sta->sta.mlo)) ++ rx.sdata = prev_sta->sdata; + if (!ieee80211_rx_data_set_sta(&rx, &prev_sta->sta, + link_id)) + goto out; @@ -392,6 +395,7 @@ Signed-off-by: Felix Fietkau - !ieee80211_rx_is_valid_sta_link_id(&prev_sta->sta, - link_id)) || - (!status->link_valid && prev_sta->sta.mlo)) ++ rx.sdata = prev_sta->sdata; + if (!ieee80211_rx_data_set_sta(&rx, &prev_sta->sta, + link_id)) goto out; From af3c9b74e177019b18055c263099a42c1c6c3453 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Thu, 29 Dec 2022 21:26:28 +0100 Subject: [PATCH 72/72] mbedtls: update to version 2.28.2 Changelog: https://github.com/Mbed-TLS/mbedtls/releases/tag/v2.28.2 This release of Mbed TLS provides bug fixes and minor enhancements. This release includes fixes for security issues. Fixes the following CVEs: * CVE-2022-46393: Fix potential heap buffer overread and overwrite in DTLS if MBEDTLS_SSL_DTLS_CONNECTION_ID is enabled and MBEDTLS_SSL_CID_IN_LEN_MAX > 2 * MBEDTLS_SSL_CID_OUT_LEN_MAX. * CVE-2022-46392: An adversary with access to precise enough information about memory accesses (typically, an untrusted operating system attacking a secure enclave) could recover an RSA private key after observing the victim performing a single private-key operation if the window size used for the exponentiation was 3 or smaller. Signed-off-by: Hauke Mehrtens --- package/libs/mbedtls/Makefile | 6 +++--- package/libs/mbedtls/patches/100-fix-compile.patch | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/package/libs/mbedtls/Makefile b/package/libs/mbedtls/Makefile index fd0f821d858..b07f0477e45 100644 --- a/package/libs/mbedtls/Makefile +++ b/package/libs/mbedtls/Makefile @@ -8,13 +8,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=mbedtls -PKG_VERSION:=2.28.1 -PKG_RELEASE:=$(AUTORELEASE) +PKG_VERSION:=2.28.2 +PKG_RELEASE:=1 PKG_USE_MIPS16:=0 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=https://codeload.github.com/ARMmbed/mbedtls/tar.gz/v$(PKG_VERSION)? -PKG_HASH:=6797a7b6483ef589deeab8d33d401ed235d7be25eeecda1be8ddfed406d40ff4 +PKG_HASH:=bc55232bf71fd66045122ba9050a29ea7cb2e8f99b064a9e6334a82f715881a0 PKG_LICENSE:=GPL-2.0-or-later PKG_LICENSE_FILES:=gpl-2.0.txt diff --git a/package/libs/mbedtls/patches/100-fix-compile.patch b/package/libs/mbedtls/patches/100-fix-compile.patch index c3b26ac9c9b..411d3716994 100644 --- a/package/libs/mbedtls/patches/100-fix-compile.patch +++ b/package/libs/mbedtls/patches/100-fix-compile.patch @@ -4,7 +4,7 @@ Bug report: https://github.com/Mbed-TLS/mbedtls/issues/6243 --- a/programs/ssl/ssl_server2.c +++ b/programs/ssl/ssl_server2.c -@@ -2511,7 +2511,6 @@ int main( int argc, char *argv[] ) +@@ -2529,7 +2529,6 @@ int main( int argc, char *argv[] ) } key_cert_init2 = 2; #endif /* MBEDTLS_ECDSA_C */ @@ -12,11 +12,11 @@ Bug report: https://github.com/Mbed-TLS/mbedtls/issues/6243 #if defined(MBEDTLS_USE_PSA_CRYPTO) if( opt.key_opaque != 0 ) -@@ -2540,6 +2539,7 @@ int main( int argc, char *argv[] ) +@@ -2558,6 +2557,7 @@ int main( int argc, char *argv[] ) } #endif /* MBEDTLS_USE_PSA_CRYPTO */ #endif /* MBEDTLS_CERTS_C */ + } mbedtls_printf( " ok (key types: %s - %s)\n", mbedtls_pk_get_name( &pkey ), mbedtls_pk_get_name( &pkey2 ) ); - #endif /* MBEDTLS_X509_CRT_PARSE_C */ + #endif /* MBEDTLS_KEY_EXCHANGE_WITH_CERT_ENABLED */