ramips: mtk-sd: stability improvements for MIPS mt762x SoCs
* Add tuning parameters to improve the stability of 48~50 MHz High-Speed SD mode. * Fix I/O errors on EMMC mode by disabling unsupported auto CMD23 feature. Signed-off-by: Shiji Yang <yangshiji66@outlook.com> Link: https://github.com/openwrt/openwrt/pull/18896 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Shiji Yang
Hauke Mehrtens
parent
db76fe6a02
commit
3f78e5c918
8 changed files with 496 additions and 148 deletions
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@ -0,0 +1,81 @@
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From: Shiji Yang <yangshiji66@outlook.com>
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Date: Sat, 24 May 2025 15:53:26 +0800
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Subject: [PATCH 1/3] mmc: mtk-sd: add tuning parameters for legacy MIPS MT762x
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SoCs
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The MIPS MT762x SoCs require some specific tuning parameters at
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different clock frequencies. These legacy SoCs only support max
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48~50 MHz High-Speed SD mode. Therefore, the standard tuning step
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is not available. We have to hard code these tuning parameters
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to make them work properly.
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Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
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---
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drivers/mmc/host/mtk-sd.c | 26 +++++++++++++++++++++++++-
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1 file changed, 25 insertions(+), 1 deletion(-)
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--- a/drivers/mmc/host/mtk-sd.c
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+++ b/drivers/mmc/host/mtk-sd.c
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@@ -75,8 +75,13 @@
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#define MSDC_PATCH_BIT 0xb0
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#define MSDC_PATCH_BIT1 0xb4
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#define MSDC_PATCH_BIT2 0xb8
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+#define MSDC_PAD_CTRL0 0xe0
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+#define MSDC_PAD_CTRL1 0xe4
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+#define MSDC_PAD_CTRL2 0xe8
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#define MSDC_PAD_TUNE 0xec
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#define MSDC_PAD_TUNE0 0xf0
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+#define MSDC_DAT_RDDLY0 0xf0
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+#define MSDC_DAT_RDDLY1 0xf4
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#define PAD_DS_TUNE 0x188
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#define PAD_CMD_TUNE 0x18c
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#define EMMC51_CFG0 0x204
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@@ -408,6 +413,7 @@ struct mtk_mmc_compatible {
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bool enhance_rx;
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bool support_64g;
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bool use_internal_cd;
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+ bool mips_mt762x;
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};
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struct msdc_tune_para {
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@@ -547,6 +553,7 @@ static const struct mtk_mmc_compatible m
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.stop_clk_fix = false,
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.enhance_rx = false,
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.use_internal_cd = true,
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+ .mips_mt762x = true,
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};
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static const struct mtk_mmc_compatible mt7622_compat = {
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@@ -969,7 +976,12 @@ static void msdc_set_mclk(struct msdc_ho
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* mmc_select_hs400() will drop to 50Mhz and High speed mode,
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* tune result of hs200/200Mhz is not suitable for 50Mhz
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*/
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- if (mmc->actual_clock <= 52000000) {
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+ if (host->dev_comp->mips_mt762x &&
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+ mmc->actual_clock > 25000000) {
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+ sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
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+ sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
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+ sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
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+ } else if (mmc->actual_clock <= 52000000) {
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writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
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if (host->top_base) {
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writel(host->def_tune_para.emmc_top_control,
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@@ -1839,6 +1851,18 @@ static void msdc_init_hw(struct msdc_hos
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MSDC_PAD_TUNE_RXDLYSEL);
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}
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+ if (host->dev_comp->mips_mt762x) {
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+ /* Set pins drive strength */
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+ writel(0x000d0044, host->base + MSDC_PAD_CTRL0);
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+ writel(0x000e0044, host->base + MSDC_PAD_CTRL1);
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+ writel(0x000e0044, host->base + MSDC_PAD_CTRL2);
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+
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+ /* Set tuning parameters */
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+ writel(0x84101010, host->base + tune_reg);
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+ writel(0x10101010, host->base + MSDC_DAT_RDDLY0);
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+ writel(0x10101010, host->base + MSDC_DAT_RDDLY1);
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+ }
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+
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if (mmc->caps2 & MMC_CAP2_NO_SDIO) {
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sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
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sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
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@ -0,0 +1,137 @@
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From: Shiji Yang <yangshiji66@outlook.com>
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Date: Fri, 13 Jun 2025 20:12:55 +0800
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Subject: [PATCH 2/3] mmc: mtk-sd: disable auto CMD23 support for mt7620
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MT7628 ProgrammingGuide indicates that the host controller version
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3.0 and later support auto CMD23 function. However, it doesn't
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define SD command register BIT[29](Auto CMD23 enable bit). I guess
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the legacy MIPS MT762x series SoCs don't support this feature at
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all. The experiment on JDCloud RE-SP-01B(MT7621 + 128 GiB EMMC)
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shows that disabling auto CMD23 can fix the following IO errors:
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[ 143.344604] mtk-msdc 1e130000.mmc: msdc_track_cmd_data: cmd=6 arg=03B30101; host->error=0x00000002
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[ 143.353661] mtk-msdc 1e130000.mmc: msdc_track_cmd_data: cmd=6 arg=03B30101; host->error=0x00000002
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[ 143.362662] mtk-msdc 1e130000.mmc: msdc_track_cmd_data: cmd=6 arg=03B30101; host->error=0x00000002
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[ 143.371684] mtk-msdc 1e130000.mmc: msdc_track_cmd_data: cmd=6 arg=03B30101; host->error=0x00000002
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[ 143.380684] I/O error, dev mmcblk0boot0, sector 0 op 0x0:(READ) flags 0x80700 phys_seg 4 prio class 0
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[ 143.390414] mtk-msdc 1e130000.mmc: msdc_track_cmd_data: cmd=6 arg=03B30101; host->error=0x00000002
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[ 143.399468] mtk-msdc 1e130000.mmc: msdc_track_cmd_data: cmd=6 arg=03B30101; host->error=0x00000002
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[ 143.408516] mtk-msdc 1e130000.mmc: msdc_track_cmd_data: cmd=6 arg=03B30101; host->error=0x00000002
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[ 143.417556] mtk-msdc 1e130000.mmc: msdc_track_cmd_data: cmd=6 arg=03B30101; host->error=0x00000002
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[ 143.426590] I/O error, dev mmcblk0boot0, sector 0 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
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[ 143.435585] Buffer I/O error on dev mmcblk0boot0, logical block 0, async page read
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Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
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---
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drivers/mmc/host/mtk-sd.c | 16 +++++++++++++++-
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1 file changed, 15 insertions(+), 1 deletion(-)
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--- a/drivers/mmc/host/mtk-sd.c
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+++ b/drivers/mmc/host/mtk-sd.c
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@@ -412,6 +412,7 @@ struct mtk_mmc_compatible {
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bool stop_clk_fix;
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bool enhance_rx;
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bool support_64g;
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+ bool support_cmd23;
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bool use_internal_cd;
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bool mips_mt762x;
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};
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@@ -501,6 +502,7 @@ static const struct mtk_mmc_compatible m
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.stop_clk_fix = false,
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.enhance_rx = false,
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.support_64g = false,
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+ .support_cmd23 = true,
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};
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static const struct mtk_mmc_compatible mt2712_compat = {
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@@ -514,6 +516,7 @@ static const struct mtk_mmc_compatible m
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.stop_clk_fix = true,
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.enhance_rx = true,
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.support_64g = true,
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+ .support_cmd23 = true,
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};
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static const struct mtk_mmc_compatible mt6779_compat = {
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@@ -527,6 +530,7 @@ static const struct mtk_mmc_compatible m
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.stop_clk_fix = true,
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.enhance_rx = true,
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.support_64g = true,
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+ .support_cmd23 = true,
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};
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static const struct mtk_mmc_compatible mt6795_compat = {
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@@ -540,6 +544,7 @@ static const struct mtk_mmc_compatible m
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.stop_clk_fix = false,
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.enhance_rx = false,
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.support_64g = false,
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+ .support_cmd23 = true,
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};
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static const struct mtk_mmc_compatible mt7620_compat = {
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@@ -552,6 +557,7 @@ static const struct mtk_mmc_compatible m
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.busy_check = false,
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.stop_clk_fix = false,
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.enhance_rx = false,
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+ .support_cmd23 = false,
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.use_internal_cd = true,
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.mips_mt762x = true,
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};
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@@ -567,6 +573,7 @@ static const struct mtk_mmc_compatible m
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.stop_clk_fix = true,
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.enhance_rx = true,
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.support_64g = false,
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+ .support_cmd23 = true,
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};
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static const struct mtk_mmc_compatible mt7986_compat = {
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@@ -580,6 +587,7 @@ static const struct mtk_mmc_compatible m
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.stop_clk_fix = true,
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.enhance_rx = true,
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.support_64g = true,
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+ .support_cmd23 = true,
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};
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static const struct mtk_mmc_compatible mt8135_compat = {
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@@ -593,6 +601,7 @@ static const struct mtk_mmc_compatible m
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.stop_clk_fix = false,
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.enhance_rx = false,
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.support_64g = false,
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+ .support_cmd23 = true,
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};
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static const struct mtk_mmc_compatible mt8173_compat = {
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@@ -606,6 +615,7 @@ static const struct mtk_mmc_compatible m
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.stop_clk_fix = false,
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.enhance_rx = false,
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.support_64g = false,
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+ .support_cmd23 = true,
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};
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static const struct mtk_mmc_compatible mt8183_compat = {
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@@ -619,6 +629,7 @@ static const struct mtk_mmc_compatible m
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.stop_clk_fix = true,
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.enhance_rx = true,
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.support_64g = true,
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+ .support_cmd23 = true,
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};
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static const struct mtk_mmc_compatible mt8516_compat = {
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@@ -630,6 +641,7 @@ static const struct mtk_mmc_compatible m
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.data_tune = true,
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.busy_check = true,
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.stop_clk_fix = true,
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+ .support_cmd23 = true,
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};
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static const struct of_device_id msdc_of_ids[] = {
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@@ -2896,7 +2908,9 @@ static int msdc_drv_probe(struct platfor
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if (mmc->caps & MMC_CAP_SDIO_IRQ)
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mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
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- mmc->caps |= MMC_CAP_CMD23;
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+ if (host->dev_comp->support_cmd23)
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+ mmc->caps |= MMC_CAP_CMD23;
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+
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if (host->cqhci)
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mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
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/* MMC core transfer sizes tunable parameters */
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@ -0,0 +1,30 @@
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From: Shiji Yang <yangshiji66@outlook.com>
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Date: Sat, 24 May 2025 15:53:26 +0800
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Subject: [PATCH 3/3] mmc: mtk-sd: use default PATCH_BIT1/2 values for mt7620
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The definitions of these two registers seem to be slightly different
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from other variants. Use their default values to follow the vendor
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SDK driver behaviors.
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Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
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---
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drivers/mmc/host/mtk-sd.c | 8 +++++---
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1 file changed, 5 insertions(+), 3 deletions(-)
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--- a/drivers/mmc/host/mtk-sd.c
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+++ b/drivers/mmc/host/mtk-sd.c
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@@ -1787,9 +1787,11 @@ static void msdc_init_hw(struct msdc_hos
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}
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writel(0, host->base + MSDC_IOCON);
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sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
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- writel(0x403c0046, host->base + MSDC_PATCH_BIT);
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- sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
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- writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
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+ if (!host->dev_comp->mips_mt762x) {
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+ writel(0x403c0046, host->base + MSDC_PATCH_BIT);
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+ sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
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+ writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
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+ }
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sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
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if (host->dev_comp->stop_clk_fix) {
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@ -1,74 +0,0 @@
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From: Shiji Yang <yangshiji66@outlook.com>
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Date: Wed, 10 Jul 2024 12:18:52 +0800
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Subject: [PATCH] mmc: mtk-sd: initialize the pad and tune registers
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Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
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---
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drivers/mmc/host/mtk-sd.c | 26 +++++++++++++++++++++++---
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1 file changed, 23 insertions(+), 3 deletions(-)
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--- a/drivers/mmc/host/mtk-sd.c
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+++ b/drivers/mmc/host/mtk-sd.c
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@@ -75,8 +75,12 @@
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#define MSDC_PATCH_BIT 0xb0
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#define MSDC_PATCH_BIT1 0xb4
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#define MSDC_PATCH_BIT2 0xb8
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+#define MSDC_PAD_CTRL0 0xe0
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+#define MSDC_PAD_CTRL1 0xe4
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+#define MSDC_PAD_CTRL2 0xe8
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#define MSDC_PAD_TUNE 0xec
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#define MSDC_PAD_TUNE0 0xf0
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+#define MSDC_PAD_TUNE1 0xf4
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#define PAD_DS_TUNE 0x188
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#define PAD_CMD_TUNE 0x18c
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#define EMMC51_CFG0 0x204
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@@ -408,6 +412,7 @@ struct mtk_mmc_compatible {
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bool enhance_rx;
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bool support_64g;
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bool use_internal_cd;
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+ bool legacy_mt762x; /* for mt7620, mt7621 and mt76x8 */
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};
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struct msdc_tune_para {
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@@ -547,6 +552,7 @@ static const struct mtk_mmc_compatible m
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.stop_clk_fix = false,
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.enhance_rx = false,
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.use_internal_cd = true,
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+ .legacy_mt762x = true,
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};
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static const struct mtk_mmc_compatible mt7622_compat = {
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@@ -1763,9 +1769,11 @@ static void msdc_init_hw(struct msdc_hos
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}
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writel(0, host->base + MSDC_IOCON);
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sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
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- writel(0x403c0046, host->base + MSDC_PATCH_BIT);
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- sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
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- writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
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+ if(!host->dev_comp->legacy_mt762x) {
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+ writel(0x403c0046, host->base + MSDC_PATCH_BIT);
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+ sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
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+ writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
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+ }
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sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
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if (host->dev_comp->stop_clk_fix) {
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|
||||||
@@ -1839,6 +1847,18 @@ static void msdc_init_hw(struct msdc_hos
|
|
||||||
MSDC_PAD_TUNE_RXDLYSEL);
|
|
||||||
}
|
|
||||||
|
|
||||||
+ if (host->dev_comp->legacy_mt762x) {
|
|
||||||
+ /* Set pins drive strength */
|
|
||||||
+ writel(0x000d0044, host->base + MSDC_PAD_CTRL0);
|
|
||||||
+ writel(0x000e0044, host->base + MSDC_PAD_CTRL1);
|
|
||||||
+ writel(0x000e0044, host->base + MSDC_PAD_CTRL2);
|
|
||||||
+
|
|
||||||
+ /* Set pad delay */
|
|
||||||
+ writel(0x84101010, host->base + MSDC_PAD_TUNE);
|
|
||||||
+ writel(0x10101010, host->base + MSDC_PAD_TUNE0);
|
|
||||||
+ writel(0x10101010, host->base + MSDC_PAD_TUNE1);
|
|
||||||
+ }
|
|
||||||
+
|
|
||||||
if (mmc->caps2 & MMC_CAP2_NO_SDIO) {
|
|
||||||
sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
|
|
||||||
sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
|
|
||||||
|
|
@ -0,0 +1,81 @@
|
||||||
|
From: Shiji Yang <yangshiji66@outlook.com>
|
||||||
|
Date: Sat, 24 May 2025 15:53:26 +0800
|
||||||
|
Subject: [PATCH 1/3] mmc: mtk-sd: add tuning parameters for legacy MIPS MT762x
|
||||||
|
SoCs
|
||||||
|
|
||||||
|
The MIPS MT762x SoCs require some specific tuning parameters at
|
||||||
|
different clock frequencies. These legacy SoCs only support max
|
||||||
|
48~50 MHz High-Speed SD mode. Therefore, the standard tuning step
|
||||||
|
is not available. We have to hard code these tuning parameters
|
||||||
|
to make them work properly.
|
||||||
|
|
||||||
|
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
|
||||||
|
---
|
||||||
|
drivers/mmc/host/mtk-sd.c | 26 +++++++++++++++++++++++++-
|
||||||
|
1 file changed, 25 insertions(+), 1 deletion(-)
|
||||||
|
|
||||||
|
--- a/drivers/mmc/host/mtk-sd.c
|
||||||
|
+++ b/drivers/mmc/host/mtk-sd.c
|
||||||
|
@@ -76,8 +76,13 @@
|
||||||
|
#define MSDC_PATCH_BIT 0xb0
|
||||||
|
#define MSDC_PATCH_BIT1 0xb4
|
||||||
|
#define MSDC_PATCH_BIT2 0xb8
|
||||||
|
+#define MSDC_PAD_CTRL0 0xe0
|
||||||
|
+#define MSDC_PAD_CTRL1 0xe4
|
||||||
|
+#define MSDC_PAD_CTRL2 0xe8
|
||||||
|
#define MSDC_PAD_TUNE 0xec
|
||||||
|
#define MSDC_PAD_TUNE0 0xf0
|
||||||
|
+#define MSDC_DAT_RDDLY0 0xf0
|
||||||
|
+#define MSDC_DAT_RDDLY1 0xf4
|
||||||
|
#define PAD_DS_TUNE 0x188
|
||||||
|
#define PAD_CMD_TUNE 0x18c
|
||||||
|
#define EMMC51_CFG0 0x204
|
||||||
|
@@ -403,6 +408,7 @@ struct mtk_mmc_compatible {
|
||||||
|
bool enhance_rx;
|
||||||
|
bool support_64g;
|
||||||
|
bool use_internal_cd;
|
||||||
|
+ bool mips_mt762x;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct msdc_tune_para {
|
||||||
|
@@ -541,6 +547,7 @@ static const struct mtk_mmc_compatible m
|
||||||
|
.stop_clk_fix = false,
|
||||||
|
.enhance_rx = false,
|
||||||
|
.use_internal_cd = true,
|
||||||
|
+ .mips_mt762x = true,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct mtk_mmc_compatible mt7622_compat = {
|
||||||
|
@@ -964,7 +971,12 @@ static void msdc_set_mclk(struct msdc_ho
|
||||||
|
* mmc_select_hs400() will drop to 50Mhz and High speed mode,
|
||||||
|
* tune result of hs200/200Mhz is not suitable for 50Mhz
|
||||||
|
*/
|
||||||
|
- if (mmc->actual_clock <= 52000000) {
|
||||||
|
+ if (host->dev_comp->mips_mt762x &&
|
||||||
|
+ mmc->actual_clock > 25000000) {
|
||||||
|
+ sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
|
||||||
|
+ sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
|
||||||
|
+ sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
|
||||||
|
+ } else if (mmc->actual_clock <= 52000000) {
|
||||||
|
writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
|
||||||
|
if (host->top_base) {
|
||||||
|
writel(host->def_tune_para.emmc_top_control,
|
||||||
|
@@ -1822,6 +1834,18 @@ static void msdc_init_hw(struct msdc_hos
|
||||||
|
MSDC_PAD_TUNE_RXDLYSEL);
|
||||||
|
}
|
||||||
|
|
||||||
|
+ if (host->dev_comp->mips_mt762x) {
|
||||||
|
+ /* Set pins drive strength */
|
||||||
|
+ writel(0x000d0044, host->base + MSDC_PAD_CTRL0);
|
||||||
|
+ writel(0x000e0044, host->base + MSDC_PAD_CTRL1);
|
||||||
|
+ writel(0x000e0044, host->base + MSDC_PAD_CTRL2);
|
||||||
|
+
|
||||||
|
+ /* Set tuning parameters */
|
||||||
|
+ writel(0x84101010, host->base + tune_reg);
|
||||||
|
+ writel(0x10101010, host->base + MSDC_DAT_RDDLY0);
|
||||||
|
+ writel(0x10101010, host->base + MSDC_DAT_RDDLY1);
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
if (mmc->caps2 & MMC_CAP2_NO_SDIO) {
|
||||||
|
sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
|
||||||
|
sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
|
||||||
|
|
@ -0,0 +1,137 @@
|
||||||
|
From: Shiji Yang <yangshiji66@outlook.com>
|
||||||
|
Date: Fri, 13 Jun 2025 20:12:55 +0800
|
||||||
|
Subject: [PATCH 2/3] mmc: mtk-sd: disable auto CMD23 support for mt7620
|
||||||
|
|
||||||
|
MT7628 ProgrammingGuide indicates that the host controller version
|
||||||
|
3.0 and later support auto CMD23 function. However, it doesn't
|
||||||
|
define SD command register BIT[29](Auto CMD23 enable bit). I guess
|
||||||
|
the legacy MIPS MT762x series SoCs don't support this feature at
|
||||||
|
all. The experiment on JDCloud RE-SP-01B(MT7621 + 128 GiB EMMC)
|
||||||
|
shows that disabling auto CMD23 can fix the following IO errors:
|
||||||
|
|
||||||
|
[ 143.344604] mtk-msdc 1e130000.mmc: msdc_track_cmd_data: cmd=6 arg=03B30101; host->error=0x00000002
|
||||||
|
[ 143.353661] mtk-msdc 1e130000.mmc: msdc_track_cmd_data: cmd=6 arg=03B30101; host->error=0x00000002
|
||||||
|
[ 143.362662] mtk-msdc 1e130000.mmc: msdc_track_cmd_data: cmd=6 arg=03B30101; host->error=0x00000002
|
||||||
|
[ 143.371684] mtk-msdc 1e130000.mmc: msdc_track_cmd_data: cmd=6 arg=03B30101; host->error=0x00000002
|
||||||
|
[ 143.380684] I/O error, dev mmcblk0boot0, sector 0 op 0x0:(READ) flags 0x80700 phys_seg 4 prio class 0
|
||||||
|
[ 143.390414] mtk-msdc 1e130000.mmc: msdc_track_cmd_data: cmd=6 arg=03B30101; host->error=0x00000002
|
||||||
|
[ 143.399468] mtk-msdc 1e130000.mmc: msdc_track_cmd_data: cmd=6 arg=03B30101; host->error=0x00000002
|
||||||
|
[ 143.408516] mtk-msdc 1e130000.mmc: msdc_track_cmd_data: cmd=6 arg=03B30101; host->error=0x00000002
|
||||||
|
[ 143.417556] mtk-msdc 1e130000.mmc: msdc_track_cmd_data: cmd=6 arg=03B30101; host->error=0x00000002
|
||||||
|
[ 143.426590] I/O error, dev mmcblk0boot0, sector 0 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
|
||||||
|
[ 143.435585] Buffer I/O error on dev mmcblk0boot0, logical block 0, async page read
|
||||||
|
|
||||||
|
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
|
||||||
|
---
|
||||||
|
drivers/mmc/host/mtk-sd.c | 16 +++++++++++++++-
|
||||||
|
1 file changed, 15 insertions(+), 1 deletion(-)
|
||||||
|
|
||||||
|
--- a/drivers/mmc/host/mtk-sd.c
|
||||||
|
+++ b/drivers/mmc/host/mtk-sd.c
|
||||||
|
@@ -407,6 +407,7 @@ struct mtk_mmc_compatible {
|
||||||
|
bool stop_clk_fix;
|
||||||
|
bool enhance_rx;
|
||||||
|
bool support_64g;
|
||||||
|
+ bool support_cmd23;
|
||||||
|
bool use_internal_cd;
|
||||||
|
bool mips_mt762x;
|
||||||
|
};
|
||||||
|
@@ -495,6 +496,7 @@ static const struct mtk_mmc_compatible m
|
||||||
|
.stop_clk_fix = false,
|
||||||
|
.enhance_rx = false,
|
||||||
|
.support_64g = false,
|
||||||
|
+ .support_cmd23 = true,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct mtk_mmc_compatible mt2712_compat = {
|
||||||
|
@@ -508,6 +510,7 @@ static const struct mtk_mmc_compatible m
|
||||||
|
.stop_clk_fix = true,
|
||||||
|
.enhance_rx = true,
|
||||||
|
.support_64g = true,
|
||||||
|
+ .support_cmd23 = true,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct mtk_mmc_compatible mt6779_compat = {
|
||||||
|
@@ -521,6 +524,7 @@ static const struct mtk_mmc_compatible m
|
||||||
|
.stop_clk_fix = true,
|
||||||
|
.enhance_rx = true,
|
||||||
|
.support_64g = true,
|
||||||
|
+ .support_cmd23 = true,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct mtk_mmc_compatible mt6795_compat = {
|
||||||
|
@@ -534,6 +538,7 @@ static const struct mtk_mmc_compatible m
|
||||||
|
.stop_clk_fix = false,
|
||||||
|
.enhance_rx = false,
|
||||||
|
.support_64g = false,
|
||||||
|
+ .support_cmd23 = true,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct mtk_mmc_compatible mt7620_compat = {
|
||||||
|
@@ -546,6 +551,7 @@ static const struct mtk_mmc_compatible m
|
||||||
|
.busy_check = false,
|
||||||
|
.stop_clk_fix = false,
|
||||||
|
.enhance_rx = false,
|
||||||
|
+ .support_cmd23 = false,
|
||||||
|
.use_internal_cd = true,
|
||||||
|
.mips_mt762x = true,
|
||||||
|
};
|
||||||
|
@@ -561,6 +567,7 @@ static const struct mtk_mmc_compatible m
|
||||||
|
.stop_clk_fix = true,
|
||||||
|
.enhance_rx = true,
|
||||||
|
.support_64g = false,
|
||||||
|
+ .support_cmd23 = true,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct mtk_mmc_compatible mt7986_compat = {
|
||||||
|
@@ -574,6 +581,7 @@ static const struct mtk_mmc_compatible m
|
||||||
|
.stop_clk_fix = true,
|
||||||
|
.enhance_rx = true,
|
||||||
|
.support_64g = true,
|
||||||
|
+ .support_cmd23 = true,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct mtk_mmc_compatible mt8135_compat = {
|
||||||
|
@@ -587,6 +595,7 @@ static const struct mtk_mmc_compatible m
|
||||||
|
.stop_clk_fix = false,
|
||||||
|
.enhance_rx = false,
|
||||||
|
.support_64g = false,
|
||||||
|
+ .support_cmd23 = true,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct mtk_mmc_compatible mt8173_compat = {
|
||||||
|
@@ -600,6 +609,7 @@ static const struct mtk_mmc_compatible m
|
||||||
|
.stop_clk_fix = false,
|
||||||
|
.enhance_rx = false,
|
||||||
|
.support_64g = false,
|
||||||
|
+ .support_cmd23 = true,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct mtk_mmc_compatible mt8183_compat = {
|
||||||
|
@@ -613,6 +623,7 @@ static const struct mtk_mmc_compatible m
|
||||||
|
.stop_clk_fix = true,
|
||||||
|
.enhance_rx = true,
|
||||||
|
.support_64g = true,
|
||||||
|
+ .support_cmd23 = true,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct mtk_mmc_compatible mt8516_compat = {
|
||||||
|
@@ -624,6 +635,7 @@ static const struct mtk_mmc_compatible m
|
||||||
|
.data_tune = true,
|
||||||
|
.busy_check = true,
|
||||||
|
.stop_clk_fix = true,
|
||||||
|
+ .support_cmd23 = true,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct of_device_id msdc_of_ids[] = {
|
||||||
|
@@ -2834,7 +2846,9 @@ static int msdc_drv_probe(struct platfor
|
||||||
|
if (mmc->caps & MMC_CAP_SDIO_IRQ)
|
||||||
|
mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
|
||||||
|
|
||||||
|
- mmc->caps |= MMC_CAP_CMD23;
|
||||||
|
+ if (host->dev_comp->support_cmd23)
|
||||||
|
+ mmc->caps |= MMC_CAP_CMD23;
|
||||||
|
+
|
||||||
|
if (host->cqhci)
|
||||||
|
mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
|
||||||
|
/* MMC core transfer sizes tunable parameters */
|
||||||
|
|
@ -0,0 +1,30 @@
|
||||||
|
From: Shiji Yang <yangshiji66@outlook.com>
|
||||||
|
Date: Sat, 24 May 2025 15:53:26 +0800
|
||||||
|
Subject: [PATCH 3/3] mmc: mtk-sd: use default PATCH_BIT1/2 values for mt7620
|
||||||
|
|
||||||
|
The definitions of these two registers seem to be slightly different
|
||||||
|
from other variants. Use their default values to follow the vendor
|
||||||
|
SDK driver behaviors.
|
||||||
|
|
||||||
|
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
|
||||||
|
---
|
||||||
|
drivers/mmc/host/mtk-sd.c | 8 +++++---
|
||||||
|
1 file changed, 5 insertions(+), 3 deletions(-)
|
||||||
|
|
||||||
|
--- a/drivers/mmc/host/mtk-sd.c
|
||||||
|
+++ b/drivers/mmc/host/mtk-sd.c
|
||||||
|
@@ -1780,9 +1780,11 @@ static void msdc_init_hw(struct msdc_hos
|
||||||
|
}
|
||||||
|
writel(0, host->base + MSDC_IOCON);
|
||||||
|
sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
|
||||||
|
- writel(0x403c0046, host->base + MSDC_PATCH_BIT);
|
||||||
|
- sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
|
||||||
|
- writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
|
||||||
|
+ if (!host->dev_comp->mips_mt762x) {
|
||||||
|
+ writel(0x403c0046, host->base + MSDC_PATCH_BIT);
|
||||||
|
+ sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
|
||||||
|
+ writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
|
||||||
|
+ }
|
||||||
|
sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
|
||||||
|
|
||||||
|
if (host->dev_comp->stop_clk_fix) {
|
||||||
|
|
@ -1,74 +0,0 @@
|
||||||
From: Shiji Yang <yangshiji66@outlook.com>
|
|
||||||
Date: Wed, 10 Jul 2024 12:18:52 +0800
|
|
||||||
Subject: [PATCH] mmc: mtk-sd: initialize the pad and tune registers
|
|
||||||
|
|
||||||
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
|
|
||||||
---
|
|
||||||
drivers/mmc/host/mtk-sd.c | 26 +++++++++++++++++++++++---
|
|
||||||
1 file changed, 23 insertions(+), 3 deletions(-)
|
|
||||||
|
|
||||||
--- a/drivers/mmc/host/mtk-sd.c
|
|
||||||
+++ b/drivers/mmc/host/mtk-sd.c
|
|
||||||
@@ -76,8 +76,12 @@
|
|
||||||
#define MSDC_PATCH_BIT 0xb0
|
|
||||||
#define MSDC_PATCH_BIT1 0xb4
|
|
||||||
#define MSDC_PATCH_BIT2 0xb8
|
|
||||||
+#define MSDC_PAD_CTRL0 0xe0
|
|
||||||
+#define MSDC_PAD_CTRL1 0xe4
|
|
||||||
+#define MSDC_PAD_CTRL2 0xe8
|
|
||||||
#define MSDC_PAD_TUNE 0xec
|
|
||||||
#define MSDC_PAD_TUNE0 0xf0
|
|
||||||
+#define MSDC_PAD_TUNE1 0xf4
|
|
||||||
#define PAD_DS_TUNE 0x188
|
|
||||||
#define PAD_CMD_TUNE 0x18c
|
|
||||||
#define EMMC51_CFG0 0x204
|
|
||||||
@@ -403,6 +407,7 @@ struct mtk_mmc_compatible {
|
|
||||||
bool enhance_rx;
|
|
||||||
bool support_64g;
|
|
||||||
bool use_internal_cd;
|
|
||||||
+ bool legacy_mt762x; /* for mt7620, mt7621 and mt76x8 */
|
|
||||||
};
|
|
||||||
|
|
||||||
struct msdc_tune_para {
|
|
||||||
@@ -541,6 +546,7 @@ static const struct mtk_mmc_compatible m
|
|
||||||
.stop_clk_fix = false,
|
|
||||||
.enhance_rx = false,
|
|
||||||
.use_internal_cd = true,
|
|
||||||
+ .legacy_mt762x = true,
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct mtk_mmc_compatible mt7622_compat = {
|
|
||||||
@@ -1756,9 +1762,11 @@ static void msdc_init_hw(struct msdc_hos
|
|
||||||
}
|
|
||||||
writel(0, host->base + MSDC_IOCON);
|
|
||||||
sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
|
|
||||||
- writel(0x403c0046, host->base + MSDC_PATCH_BIT);
|
|
||||||
- sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
|
|
||||||
- writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
|
|
||||||
+ if(!host->dev_comp->legacy_mt762x) {
|
|
||||||
+ writel(0x403c0046, host->base + MSDC_PATCH_BIT);
|
|
||||||
+ sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
|
|
||||||
+ writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
|
|
||||||
+ }
|
|
||||||
sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
|
|
||||||
|
|
||||||
if (host->dev_comp->stop_clk_fix) {
|
|
||||||
@@ -1822,6 +1830,18 @@ static void msdc_init_hw(struct msdc_hos
|
|
||||||
MSDC_PAD_TUNE_RXDLYSEL);
|
|
||||||
}
|
|
||||||
|
|
||||||
+ if (host->dev_comp->legacy_mt762x) {
|
|
||||||
+ /* Set pins drive strength */
|
|
||||||
+ writel(0x000d0044, host->base + MSDC_PAD_CTRL0);
|
|
||||||
+ writel(0x000e0044, host->base + MSDC_PAD_CTRL1);
|
|
||||||
+ writel(0x000e0044, host->base + MSDC_PAD_CTRL2);
|
|
||||||
+
|
|
||||||
+ /* Set pad delay */
|
|
||||||
+ writel(0x84101010, host->base + MSDC_PAD_TUNE);
|
|
||||||
+ writel(0x10101010, host->base + MSDC_PAD_TUNE0);
|
|
||||||
+ writel(0x10101010, host->base + MSDC_PAD_TUNE1);
|
|
||||||
+ }
|
|
||||||
+
|
|
||||||
if (mmc->caps2 & MMC_CAP2_NO_SDIO) {
|
|
||||||
sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
|
|
||||||
sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
|
|
||||||
Loading…
Reference in a new issue