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uboot-mediatek: sync with mtk-openwrt/u-boot 20250711

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- Backport upstream Winbond W25N04KV Flash support.
- Backport upstream GigaDevice series Flash support.
- Backport pending Airoha AN8855 switch TPID value fix.
- Backport Mediatek UART baudrate accuracy compensation support.
- Pull mtk patchset from MTK SDK mtksoc-20250711 branch:
    Remove mt7622_rfb changes. The MTK SDK already dropped them.
    Replace Airoha ethernet PHY driver with new version.
    Split downstream snfi changes into independent patches.
    Add new Marvell CUX3410 PHY driver.
    Add new MediaTek built-in 2.5Gbps PHY driver.

Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
This commit is contained in:
Shiji Yang 2025-07-12 09:25:59 +08:00 committed by Daniel Golle
parent bbd3db4c57
commit 332645a610
42 changed files with 55860 additions and 2647 deletions
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56
package/boot/uboot-mediatek/patches/001-mtd-spinand-winbond-add-Winbond-W25N04KV-flash-suppo.patch Normal file
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@ -0,0 +1,56 @@
From fe37fb8214e40ea64cf03453d112527b629fb08a Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Sat, 7 Jun 2025 23:11:21 +0200
Subject: [PATCH] mtd: spinand: winbond: add Winbond W25N04KV flash support
Add Winbond W25N04KV flash support that use a different value to detect
ECC bitflip.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/mtd/nand/spi/winbond.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
--- a/drivers/mtd/nand/spi/winbond.c
+++ b/drivers/mtd/nand/spi/winbond.c
@@ -11,6 +11,7 @@
#include <linux/device.h>
#include <linux/kernel.h>
#endif
+#include <linux/bitfield.h>
#include <linux/bug.h>
#include <linux/mtd/spinand.h>
@@ -18,6 +19,8 @@
#define WINBOND_CFG_BUF_READ BIT(3)
+#define W25N04KV_STATUS_ECC_5_8_BITFLIPS GENMASK(5, 4)
+
static SPINAND_OP_VARIANTS(read_cache_variants,
SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
@@ -121,6 +124,7 @@ static int w25n02kv_ecc_get_status(struc
return -EBADMSG;
case STATUS_ECC_HAS_BITFLIPS:
+ case W25N04KV_STATUS_ECC_5_8_BITFLIPS:
/*
* Let's try to retrieve the real maximum number of bitflips
* in order to avoid forcing the wear-leveling layer to move
@@ -169,6 +173,15 @@ static const struct spinand_info winbond
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
+ &update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)),
+ SPINAND_INFO("W25N04KV",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x23),
+ NAND_MEMORG(1, 2048, 128, 64, 4096, 40, 2, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
&update_cache_variants),
0,
SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)),

245
package/boot/uboot-mediatek/patches/002-mtd-spinand-gigadevice-sync-supported-chips-with-lin.patch Normal file
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@ -0,0 +1,245 @@
From 506ceddffdc40acf709822b678b986e2e22c5056 Mon Sep 17 00:00:00 2001
From: Chuanhong Guo <gch981213@gmail.com>
Date: Wed, 1 May 2024 15:45:23 +0800
Subject: [PATCH] mtd/spinand: gigadevice: sync supported chips with linux 6.9
Adding support for:
GD5F1GQ4RExxG
GD5F2GQ4UExxG
GD5F2GQ4RExxG
GD5F1GQ5RExxG
GD5F2GQ5UExxG
GD5F2GQ5RExxG
GD5F4GQ6UExxG
GD5F4GQ6RExxG
GD5F1GM7UExxG
GD5F1GM7RExxG
GD5F2GM7UExxG
GD5F2GM7RExxG
GD5F4GM8UExxG
GD5F4GM8RExxG
GD5F2GQ5xExxH
GD5F1GQ5RExxH
GD5F1GQ4RExxH
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
---
drivers/mtd/nand/spi/gigadevice.c | 188 +++++++++++++++++++++++++++++-
1 file changed, 187 insertions(+), 1 deletion(-)
--- a/drivers/mtd/nand/spi/gigadevice.c
+++ b/drivers/mtd/nand/spi/gigadevice.c
@@ -43,6 +43,22 @@ static SPINAND_OP_VARIANTS(read_cache_va
SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0));
+static SPINAND_OP_VARIANTS(read_cache_variants_1gq5,
+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+static SPINAND_OP_VARIANTS(read_cache_variants_2gq5,
+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 4, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 2, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
static SPINAND_OP_VARIANTS(write_cache_variants,
SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
SPINAND_PROG_LOAD(true, 0, NULL, 0));
@@ -329,6 +345,36 @@ static const struct spinand_info gigadev
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
gd5fxgq4uexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F1GQ4RExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc1),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4uexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F2GQ4UExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd2),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4uexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F2GQ4RExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc2),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4uexxg_ecc_get_status)),
SPINAND_INFO("GD5F1GQ4UFxxG",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48),
NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
@@ -343,12 +389,152 @@ static const struct spinand_info gigadev
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51),
NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
NAND_ECCREQ(4, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
&write_cache_variants,
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
gd5fxgq5xexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F1GQ5RExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x41),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq5xexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F2GQ5UExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x52),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq5xexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F2GQ5RExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x42),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq5xexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F4GQ6UExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x55),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 2, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq5xexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F4GQ6RExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x45),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 2, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq5xexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F1GM7UExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x91),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4uexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F1GM7RExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x81),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4uexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F2GM7UExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x92),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4uexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F2GM7RExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x82),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4uexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F4GM8UExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x95),
+ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4uexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F4GM8RExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x85),
+ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4uexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F2GQ5xExxH",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x22),
+ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4uexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F1GQ5RExxH",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x21),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4uexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F1GQ4RExxH",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xc9),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4uexxg_ecc_get_status)),
};
static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {

26
package/boot/uboot-mediatek/patches/003-net-mediatek-correct-the-AN8855-TPID-value-in-port-i.patch Normal file
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@ -0,0 +1,26 @@
From dc495442ba610b190775122a31f958ad74229262 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Tue, 8 Jul 2025 17:53:48 +0800
Subject: [PATCH] net: mediatek: correct the AN8855 TPID value in port
isolation settings
The TPID value should be 0x9100 instead of 0x8100 according to the
datasheet.
Fixes: cedafee9ff3 (net: mediatek: add support for Airoha AN8855 ethernet switch)
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/net/mtk_eth/an8855.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/net/mtk_eth/an8855.c
+++ b/drivers/net/mtk_eth/an8855.c
@@ -909,7 +909,7 @@ static void an8855_port_isolation(struct
/* Set port mode to user port */
an8855_reg_write(priv, AN8855_PVC(i),
- (0x8100 << AN8855_STAG_VPID_S) |
+ (0x9100 << AN8855_STAG_VPID_S) |
(VLAN_ATTR_USER << AN8855_VLAN_ATTR_S));
}
}

44
package/boot/uboot-mediatek/patches/004-01-serial-mediatek-fix-register-names-and-offsets.patch Normal file
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@ -0,0 +1,44 @@
From 6e15d3f91aa698798578d39a6d9e292fcc5c577f Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 23 May 2025 17:25:55 +0800
Subject: [PATCH] serial: mediatek: fix register names and offsets
Fix UART register names and offsets according to the programming
guide to allow implementing some enhanced features.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/serial/serial_mtk.c | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
--- a/drivers/serial/serial_mtk.c
+++ b/drivers/serial/serial_mtk.c
@@ -30,16 +30,23 @@ struct mtk_serial_regs {
u32 mcr;
u32 lsr;
u32 msr;
- u32 spr;
- u32 mdr1;
+ u32 scr;
+ u32 autobaud_en;
u32 highspeed;
u32 sample_count;
u32 sample_point;
+ u32 autobaud_reg;
+ u32 ratefix_ad;
+ u32 autobaud_sample;
+ u32 guard;
+ u32 escape_dat;
+ u32 escape_en;
+ u32 sleep_en;
+ u32 dma_en;
+ u32 rxtri_ad;
u32 fracdiv_l;
u32 fracdiv_m;
- u32 escape_en;
- u32 guard;
- u32 rx_sel;
+ u32 fcr_rd;
};
#define thr rbr

81
package/boot/uboot-mediatek/patches/004-02-serial-mediatek-enable-baudrate-accuracy-compensatio.patch Normal file
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@ -0,0 +1,81 @@
From 6952209ef220138189dd261d06441e1b2d50e994 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 23 May 2025 17:26:02 +0800
Subject: [PATCH] serial: mediatek: enable baudrate accuracy compensation
The high-speed UART from MediaTek supports baudrate accuracy
compensation when using high-speed mode 3.
This is done by calculating the first digit of the fraction part of
sample count value. The fraction value will be then used as the
reference to insert 0 to 10 sample cycle(s) to one frame (assume
that frame format is 8n1, i.e. 10 bits per frame).
The fracdiv_[l/m] registers are used to determine whether a bit in one frame
should be inserted with one sample cycle.
With typical 40MHz source clock, the actual baudrates with/without
accuracy compensation are:
Ideal w/o compensation w/ compensation
======== ================ ===============
9600 9603 9600
115200 114942 115207
921600 930232 921659
3000000 3076923 3007519
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/serial/serial_mtk.c | 24 +++++++++++++++++++++---
1 file changed, 21 insertions(+), 3 deletions(-)
--- a/drivers/serial/serial_mtk.c
+++ b/drivers/serial/serial_mtk.c
@@ -99,10 +99,18 @@ struct mtk_serial_priv {
bool upstream_highspeed_logic;
};
+static const unsigned short fraction_l_mapping[] = {
+ 0, 1, 0x5, 0x15, 0x55, 0x57, 0x57, 0x77, 0x7F, 0xFF, 0xFF
+};
+
+static const unsigned short fraction_m_mapping[] = {
+ 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 3
+};
+
static void _mtk_serial_setbrg(struct mtk_serial_priv *priv, int baud,
uint clk_rate)
{
- u32 quot, realbaud, samplecount = 1;
+ u32 quot, realbaud, samplecount = 1, fraction, frac_l = 0, frac_m = 0;
/* Special case for low baud clock */
if (baud <= 115200 && clk_rate == 12000000) {
@@ -147,7 +155,13 @@ use_hs3:
writel(3, &priv->regs->highspeed);
quot = DIV_ROUND_UP(clk_rate, 256 * baud);
- samplecount = DIV_ROUND_CLOSEST(clk_rate, quot * baud);
+ samplecount = clk_rate / (quot * baud);
+
+ fraction = ((clk_rate * 100) / quot / baud) % 100;
+ fraction = DIV_ROUND_CLOSEST(fraction, 10);
+
+ frac_l = fraction_l_mapping[fraction];
+ frac_m = fraction_m_mapping[fraction];
}
set_baud:
@@ -159,7 +173,11 @@ set_baud:
/* set highspeed mode sample count & point */
writel(samplecount - 1, &priv->regs->sample_count);
- writel((samplecount - 2) >> 1, &priv->regs->sample_point);
+ writel((samplecount >> 1) - 1, &priv->regs->sample_point);
+
+ /* set baudrate fraction compensation */
+ writel(frac_l, &priv->regs->fracdiv_l);
+ writel(frac_m, &priv->regs->fracdiv_m);
}
static int _mtk_serial_putc(struct mtk_serial_priv *priv, const char ch)

28
package/boot/uboot-mediatek/patches/100-02-drivers-mtd-add-support-for-MediaTek-SPI-NAND-flash-.patch → package/boot/uboot-mediatek/patches/100-01-drivers-mtd-add-support-for-MediaTek-SPI-NAND-flash-.patch
View file

@ -1,7 +1,7 @@
From f7704275957852cd4c4632d6da126979ef24b83a Mon Sep 17 00:00:00 2001
From 86d7d787e6d9802176cc563a95ac5c1919fbad66 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Tue, 2 Mar 2021 16:58:01 +0800
Subject: [PATCH 36/71] drivers: mtd: add support for MediaTek SPI-NAND flash
Subject: [PATCH 01/30] drivers: mtd: add support for MediaTek SPI-NAND flash
controller
Add mtd driver for MediaTek SPI-NAND flash controller
@ -19,12 +19,12 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
drivers/mtd/mtk-snand/mtk-snand-def.h | 271 ++++
drivers/mtd/mtk-snand/mtk-snand-ecc.c | 411 ++++++
drivers/mtd/mtk-snand/mtk-snand-ids.c | 515 +++++++
drivers/mtd/mtk-snand/mtk-snand-mtd.c | 535 +++++++
drivers/mtd/mtk-snand/mtk-snand-mtd.c | 534 +++++++
drivers/mtd/mtk-snand/mtk-snand-os.c | 39 +
drivers/mtd/mtk-snand/mtk-snand-os.h | 120 ++
drivers/mtd/mtk-snand/mtk-snand-os.h | 119 ++
drivers/mtd/mtk-snand/mtk-snand.c | 1933 +++++++++++++++++++++++++
drivers/mtd/mtk-snand/mtk-snand.h | 77 +
12 files changed, 3937 insertions(+)
12 files changed, 3935 insertions(+)
create mode 100644 drivers/mtd/mtk-snand/Kconfig
create mode 100644 drivers/mtd/mtk-snand/Makefile
create mode 100644 drivers/mtd/mtk-snand/mtk-snand-def.h
@ -514,8 +514,8 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+int mtk_ecc_setup(struct mtk_snand *snf, void *fmdaddr, uint32_t max_ecc_bytes,
+ uint32_t msg_size)
+{
+ uint32_t i, val, ecc_msg_bits, ecc_strength;
+ int ret;
+ uint32_t val, ecc_msg_bits, ecc_strength;
+ int i, ret;
+
+ snf->ecc_soc = &mtk_ecc_socs[snf->soc];
+
@ -783,7 +783,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+}
--- /dev/null
+++ b/drivers/mtd/mtk-snand/mtk-snand-ids.c
@@ -0,0 +1,519 @@
@@ -0,0 +1,515 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
@ -901,10 +901,6 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+ SNAND_MEMORG_1G_2K_64,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("GD5F1GQ5UExxG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0x51),
+ SNAND_MEMORG_1G_2K_128,
+ &snand_cap_read_from_cache_quad,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("GD5F2GQ4UExIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd2),
+ SNAND_MEMORG_2G_2K_128,
+ &snand_cap_read_from_cache_quad_q2d,
@ -1217,7 +1213,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+
+ SNAND_INFO("FM35Q1GA", SNAND_ID(SNAND_ID_DYMMY, 0xe5, 0x71),
+ SNAND_MEMORG_1G_2K_64,
+ &snand_cap_read_from_cache_x4_only,
+ &snand_cap_read_from_cache_x4,
+ &snand_cap_program_load_x4),
+
+ SNAND_INFO("PN26G01A", SNAND_ID(SNAND_ID_DYMMY, 0xa1, 0xe1),
@ -1305,7 +1301,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+}
--- /dev/null
+++ b/drivers/mtd/mtk-snand/mtk-snand-mtd.c
@@ -0,0 +1,535 @@
@@ -0,0 +1,534 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
@ -1313,7 +1309,6 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#include <config.h>
+#include <dm.h>
+#include <malloc.h>
+#include <mapmem.h>
@ -1885,7 +1880,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+}
--- /dev/null
+++ b/drivers/mtd/mtk-snand/mtk-snand-os.h
@@ -0,0 +1,120 @@
@@ -0,0 +1,119 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
@ -1896,7 +1891,6 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+#ifndef _MTK_SNAND_OS_H_
+#define _MTK_SNAND_OS_H_
+
+#include <config.h>
+#include <cpu_func.h>
+#include <errno.h>
+#include <div64.h>

6
package/boot/uboot-mediatek/patches/100-03-mtd-mtk-snand-add-support-for-SPL.patch → package/boot/uboot-mediatek/patches/100-02-mtd-mtk-snand-add-support-for-SPL.patch
View file

@ -1,7 +1,7 @@
From a347e374cb338213632c6dde88dd226d64bd8b27 Mon Sep 17 00:00:00 2001
From 219aa55e830fe7f5b56dc097f544990a032a0bfe Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Wed, 3 Mar 2021 08:57:29 +0800
Subject: [PATCH 37/71] mtd: mtk-snand: add support for SPL
Subject: [PATCH 02/30] mtd: mtk-snand: add support for SPL
Add support to initialize SPI-NAND in SPL.
Add implementation for SPL NAND loader.
@ -47,7 +47,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#include <config.h>
+#include <common.h>
+#include <dm.h>
+#include <dm/uclass.h>
+#include <malloc.h>

4
package/boot/uboot-mediatek/patches/100-05-mtd-add-a-new-mtd-device-type-for-NMBM.patch → package/boot/uboot-mediatek/patches/100-03-mtd-add-a-new-mtd-device-type-for-NMBM.patch
View file

@ -1,7 +1,7 @@
From d26a789c451068caf4bbb4d1ac7bc1f592b5493e Mon Sep 17 00:00:00 2001
From 6571329dbac9f2278b6a5d36999982220b17daf4 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Mon, 25 Jul 2022 10:58:06 +0800
Subject: [PATCH 39/71] mtd: add a new mtd device type for NMBM
Subject: [PATCH 03/30] mtd: add a new mtd device type for NMBM
This patch adds a new mtd device type for NMBM so that mtdparts can be
correctly probed. And this also gives us an opportunity to add NMBM support

4
package/boot/uboot-mediatek/patches/100-06-mtd-add-core-facility-code-of-NMBM.patch → package/boot/uboot-mediatek/patches/100-04-mtd-add-core-facility-code-of-NMBM.patch
View file

@ -1,7 +1,7 @@
From 690479081fb6a0c0f77f10fb457ad69e71390f15 Mon Sep 17 00:00:00 2001
From 9b29603e11e68148f640d602361dcc5e61f431b3 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Mon, 25 Jul 2022 10:26:35 +0800
Subject: [PATCH 40/71] mtd: add core facility code of NMBM
Subject: [PATCH 04/30] mtd: add core facility code of NMBM
This patch adds a NAND bad block management named NMBM (NAND mapping block
management) which supports using a mapping table to deal with bad blocks

4
package/boot/uboot-mediatek/patches/100-07-mtd-nmbm-add-support-for-mtd.patch → package/boot/uboot-mediatek/patches/100-05-mtd-nmbm-add-support-for-mtd.patch
View file

@ -1,7 +1,7 @@
From 0524995f07fcd216a1a7e267fdb5cf2b0ede8489 Mon Sep 17 00:00:00 2001
From 0056bd4ec8ac2cbde6c2a5e07cba9b4eb3b7cfa3 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Mon, 25 Jul 2022 10:42:12 +0800
Subject: [PATCH 41/71] mtd: nmbm: add support for mtd
Subject: [PATCH 05/30] mtd: nmbm: add support for mtd
Add support to create NMBM based on MTD devices

4
package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch → package/boot/uboot-mediatek/patches/100-06-common-board_r-add-support-to-initialize-NMBM-after-.patch
View file

@ -1,7 +1,7 @@
From dcf24c8deeb43a4406ae18136c8700dc2f867415 Mon Sep 17 00:00:00 2001
From 7499c0e030ef5051b2920576a75dfd7c60d5232a Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Mon, 25 Jul 2022 11:18:03 +0800
Subject: [PATCH 42/71] common: board_r: add support to initialize NMBM after
Subject: [PATCH 06/30] common: board_r: add support to initialize NMBM after
nand initialization
This patch add support to initialize NMBM after nand initialized.

11
package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch → package/boot/uboot-mediatek/patches/100-07-cmd-add-nmbm-command.patch
View file

@ -1,7 +1,7 @@
From 0af8d0aac77f4df4bc7dadbcdea5d9a16f5f3e45 Mon Sep 17 00:00:00 2001
From db0424519d3cc24ae94c15de26af12c075a95e6a Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Mon, 25 Jul 2022 10:44:57 +0800
Subject: [PATCH 43/71] cmd: add nmbm command
Subject: [PATCH 07/30] cmd: add nmbm command
Add nmbm command for debugging, data operations and image-booting support
@ -9,8 +9,8 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
cmd/Kconfig | 6 +
cmd/Makefile | 1 +
cmd/nmbm.c | 327 +++++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 334 insertions(+)
cmd/nmbm.c | 328 +++++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 335 insertions(+)
create mode 100644 cmd/nmbm.c
--- a/cmd/Kconfig
@ -40,7 +40,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
else ifdef CONFIG_NET_LWIP
--- /dev/null
+++ b/cmd/nmbm.c
@@ -0,0 +1,327 @@
@@ -0,0 +1,328 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
@ -49,6 +49,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#include <command.h>
+#include <env.h>
+#include <image.h>
+#include <stdbool.h>
+#include <linux/types.h>

4
package/boot/uboot-mediatek/patches/100-10-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch → package/boot/uboot-mediatek/patches/100-08-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch
View file

@ -1,7 +1,7 @@
From 6dbbc8affb6ab22f940d13d0e928d5e881127ca4 Mon Sep 17 00:00:00 2001
From f180eb4beec9b0cf19e8c2418d2b01404797cb26 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Mon, 25 Jul 2022 11:22:57 +0800
Subject: [PATCH 44/71] cmd: mtd: add markbad subcommand for NMBM testing
Subject: [PATCH 08/30] cmd: mtd: add markbad subcommand for NMBM testing
This patch adds:
* Mark bad block on lower mtd device and erase on upper mtd

39
package/boot/uboot-mediatek/patches/100-12-mtd-mtk-snand-add-NMBM-support-for-SPL.patch → package/boot/uboot-mediatek/patches/100-09-mtd-mtk-snand-add-NMBM-support-for-SPL.patch
View file

@ -1,18 +1,38 @@
From 9e8ac4fc7125795ac5e8834aaf454fd45b99c580 Mon Sep 17 00:00:00 2001
From 1c5d96f544cfe2140834cc79dc1335b0e6fc5ce5 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Mon, 25 Jul 2022 10:53:03 +0800
Subject: [PATCH 46/71] mtd: mtk-snand: add NMBM support for SPL
Subject: [PATCH 09/30] mtd: mtk-snand: add NMBM support for SPL
Add NMBM support for mtk-snand SPL loader
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/mtd/mtk-snand/mtk-snand-spl.c | 127 ++++++++++++++++++++++++++
1 file changed, 127 insertions(+)
drivers/mtd/mtk-snand/Makefile | 2 +-
drivers/mtd/mtk-snand/mtk-snand-spl.c | 133 +++++++++++++++++++++++++-
2 files changed, 133 insertions(+), 2 deletions(-)
--- a/drivers/mtd/mtk-snand/Makefile
+++ b/drivers/mtd/mtk-snand/Makefile
@@ -8,7 +8,7 @@
obj-y += mtk-snand.o mtk-snand-ecc.o mtk-snand-ids.o mtk-snand-os.o
obj-$(CONFIG_MTK_SPI_NAND_MTD) += mtk-snand-mtd.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_SPL_MTK_SPI_NAND) += mtk-snand-spl.o
endif
--- a/drivers/mtd/mtk-snand/mtk-snand-spl.c
+++ b/drivers/mtd/mtk-snand/mtk-snand-spl.c
@@ -13,12 +13,134 @@
@@ -5,7 +5,6 @@
* Author: Weijie Gao <weijie.gao@mediatek.com>
*/
-#include <common.h>
#include <dm.h>
#include <dm/uclass.h>
#include <malloc.h>
@@ -13,12 +12,134 @@
#include <mtd.h>
#include <watchdog.h>
@ -147,7 +167,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
static u8 *page_cache;
int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
@@ -60,6 +182,7 @@ int nand_spl_load_image(uint32_t offs, u
@@ -60,6 +181,7 @@ int nand_spl_load_image(uint32_t offs, u
return ret;
}
@ -155,7 +175,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
void nand_init(void)
{
@@ -105,11 +228,15 @@ void nand_init(void)
@@ -105,11 +227,20 @@ void nand_init(void)
printf("SPI-NAND: %s (%uMB)\n", cinfo.model,
(u32)(cinfo.chipsize >> 20));
@ -168,6 +188,11 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
printf("mtk-snand-spl: failed to allocate page cache\n");
}
+#endif
+}
+
+unsigned int nand_page_size(void)
+{
+ return cinfo.pagesize;
}
void nand_deselect(void)

4
package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch → package/boot/uboot-mediatek/patches/100-10-cmd-add-a-new-command-for-NAND-flash-debugging.patch
View file

@ -1,7 +1,7 @@
From 88271cb3ae9c68dc200d627653df96fc557c2a64 Mon Sep 17 00:00:00 2001
From e33ed7c216b6fc7416e205fffccfedf32e26ff8b Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Mon, 25 Jul 2022 10:55:35 +0800
Subject: [PATCH 47/71] cmd: add a new command for NAND flash debugging
Subject: [PATCH 10/30] cmd: add a new command for NAND flash debugging
Add a command 'nand-ext' for NAND flash debugging:
- Dump a page with oob, with optional raw read support

2
package/boot/uboot-mediatek/patches/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch
View file

@ -1,7 +1,7 @@
From 240d98e6ad0aed3c11236aa40a60bbd6fe01fae5 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Mon, 25 Jul 2022 10:50:46 +0800
Subject: [PATCH 45/71] env: add support for NMBM upper MTD layer
Subject: [PATCH 11/30] env: add support for NMBM upper MTD layer
Add an env driver for NMBM upper MTD layer

4
package/boot/uboot-mediatek/patches/100-14-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch → package/boot/uboot-mediatek/patches/100-12-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch
View file

@ -1,7 +1,7 @@
From c4172a95df8a57a66c70a8b9948b9600a01c4cb7 Mon Sep 17 00:00:00 2001
From b4c97d64ab00d74359112b8fc6e329d2fef792e3 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Mon, 25 Jul 2022 11:32:08 +0800
Subject: [PATCH 49/71] mtd: spi-nor: add support to read flash unique ID
Subject: [PATCH 12/30] mtd: spi-nor: add support to read flash unique ID
This patch adds support to read unique ID from spi-nor flashes.

8
package/boot/uboot-mediatek/patches/100-15-cmd-sf-add-support-to-read-flash-unique-ID.patch → package/boot/uboot-mediatek/patches/100-13-cmd-sf-add-support-to-read-flash-unique-ID.patch
View file

@ -1,14 +1,14 @@
From e60939acbebd07161f3978d1c6f13123fdd2ebf2 Mon Sep 17 00:00:00 2001
From 36d2aafec10998735f93b47a96a0f66c52484af7 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Mon, 25 Jul 2022 11:27:02 +0800
Subject: [PATCH 50/71] cmd: sf: add support to read flash unique ID
Subject: [PATCH 13/30] cmd: sf: add support to read flash unique ID
This patch adds support to display unique ID from spi-nor flashes
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
cmd/sf.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
cmd/sf.c | 11 +++++++++++
1 file changed, 11 insertions(+)
--- a/cmd/sf.c
+++ b/cmd/sf.c

4
package/boot/uboot-mediatek/patches/100-17-common-spl-spl_nand-enable-CONFIG_SYS_NAND_U_BOOT_OF.patch → package/boot/uboot-mediatek/patches/100-14-common-spl-spl_nand-enable-CONFIG_SYS_NAND_U_BOOT_OF.patch
View file

@ -1,7 +1,7 @@
From 7ab891faaaf2b6126694352d4503dc40605a6aec Mon Sep 17 00:00:00 2001
From d38f1f94531a792809f660ad5dcc4627eef1b9ec Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Mon, 25 Jul 2022 15:10:02 +0800
Subject: [PATCH 52/71] common: spl: spl_nand: enable
Subject: [PATCH 14/30] common: spl: spl_nand: enable
CONFIG_SYS_NAND_U_BOOT_OFFS undefined
Enable using spl_nand with CONFIG_SYS_NAND_U_BOOT_OFFS undefined since

31
package/boot/uboot-mediatek/patches/100-19-board-mt7622-use-new-spi-nand-driver.patch → package/boot/uboot-mediatek/patches/100-16-board-mt7622-use-new-spi-nand-driver.patch
View file

@ -1,16 +1,15 @@
From 4c1803cc08b1618d935c1386f43f43a4e9c97697 Mon Sep 17 00:00:00 2001
From 3414e92ca55af9e4d0c20d93fcba0024ca35eb10 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Wed, 3 Mar 2021 10:51:43 +0800
Subject: [PATCH 54/71] board: mt7622: use new spi-nand driver
Subject: [PATCH 16/30] board: mt7622: use new spi-nand driver
Enable new spi-nand driver support for mt7622_rfb_defconfig
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
arch/arm/dts/mt7622-rfb.dts | 7 +++++++
arch/arm/dts/mt7622.dtsi | 16 ++++++++++++++++
configs/mt7622_rfb_defconfig | 5 +++++
3 files changed, 28 insertions(+)
arch/arm/dts/mt7622-rfb.dts | 7 +++++++
arch/arm/dts/mt7622.dtsi | 16 ++++++++++++++++
2 files changed, 23 insertions(+)
--- a/arch/arm/dts/mt7622-rfb.dts
+++ b/arch/arm/dts/mt7622-rfb.dts
@ -53,23 +52,3 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
snor: snor@11014000 {
compatible = "mediatek,mtk-snor";
reg = <0x11014000 0x1000>;
--- a/configs/mt7622_rfb_defconfig
+++ b/configs/mt7622_rfb_defconfig
@@ -20,6 +20,7 @@ CONFIG_SYS_PROMPT="MT7622> "
CONFIG_SYS_MAXARGS=8
CONFIG_CMD_BOOTMENU=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
CONFIG_CMD_PCI=y
CONFIG_CMD_SF_TEST=y
CONFIG_CMD_PING=y
@@ -37,6 +38,9 @@ CONFIG_CLK=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_MTK=y
CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTK_SPI_NAND=y
+CONFIG_MTK_SPI_NAND_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_GIGADEVICE=y

8
package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch → package/boot/uboot-mediatek/patches/100-17-board-mt7981-add-reference-board-using-new-spi-nand-.patch
View file

@ -1,7 +1,7 @@
From d5841f8707dcb7a1f73607de67ab45dba93a56a4 Mon Sep 17 00:00:00 2001
From 124ef4a79d8054f84c22a60d79ccd82646b6402a Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 29 Jul 2022 17:04:12 +0800
Subject: [PATCH 55/71] board: mt7981: add reference board using new spi-nand
Subject: [PATCH 17/30] board: mt7981: add reference board using new spi-nand
driver
Add a new reference board using new spi-nand driver for SPI-NAND flash on
@ -165,6 +165,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+++ b/configs/mt7981_snfi_nand_rfb_defconfig
@@ -0,0 +1,57 @@
+CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_TEXT_BASE=0x41e00000
@ -172,6 +173,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x20000
+CONFIG_DEFAULT_DEVICE_TREE="mt7981-snfi-nand-rfb"
+CONFIG_SYS_PROMPT="MT7981> "
+CONFIG_TARGET_MT7981=y
+CONFIG_DEBUG_UART_BASE=0x11002000
+CONFIG_DEBUG_UART_CLOCK=40000000
@ -181,7 +183,6 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+CONFIG_DEFAULT_FDT_FILE="mt7981-snfi-nand-rfb"
+CONFIG_LOGLEVEL=7
+CONFIG_LOG=y
+CONFIG_SYS_PROMPT="MT7981> "
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=1049
+# CONFIG_BOOTM_NETBSD is not set
@ -211,7 +212,6 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+CONFIG_MTK_SPI_NAND=y
+CONFIG_MTK_SPI_NAND_MTD=y
+CONFIG_PHY_FIXED=y
+CONFIG_DM_ETH=y
+CONFIG_MEDIATEK_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y

35
package/boot/uboot-mediatek/patches/100-21-mtd-spi-nor-add-more-flash-ids.patch → package/boot/uboot-mediatek/patches/100-18-mtd-spi-nor-add-more-flash-ids.patch
View file

@ -1,15 +1,15 @@
From a2df2df6fd1aec32572c7b30ccf5a184ec1763fd Mon Sep 17 00:00:00 2001
From 56d3fcf9efe23f8334741d914f33c9351016d231 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Wed, 27 Jul 2022 16:32:17 +0800
Subject: [PATCH 56/71] mtd: spi-nor: add more flash ids
Subject: [PATCH 18/30] mtd: spi-nor: add more flash ids
Add more spi-nor flash ids
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/mtd/spi/spi-nor-core.c | 1 +
drivers/mtd/spi/spi-nor-ids.c | 23 ++++++++++++++++++++++-
2 files changed, 23 insertions(+), 1 deletion(-)
drivers/mtd/spi/spi-nor-ids.c | 27 ++++++++++++++++++++++++++-
2 files changed, 27 insertions(+), 1 deletion(-)
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@ -23,18 +23,19 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -83,7 +83,9 @@ const struct flash_info spi_nor_ids[] =
@@ -83,7 +83,10 @@ const struct flash_info spi_nor_ids[] =
{ INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, 0) },
{ INFO("en25q64", 0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
{ INFO("en25q128b", 0x1c3018, 0, 64 * 1024, 256, 0) },
- { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, 0) },
+ { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("en25qx128", 0x1c7118, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
+ { INFO("en25qx128a", 0x1c7118, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
+ { INFO("en25qh256", 0x1c7019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("en25qx256a", 0x1c7119, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
{ INFO("en25s64", 0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
#endif
#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
@@ -149,6 +151,11 @@ const struct flash_info spi_nor_ids[] =
@@ -149,6 +152,11 @@ const struct flash_info spi_nor_ids[] =
{INFO("gd55x02g", 0xc8481C, 0, 64 * 1024, 4096, SECT_4K |
SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
{
@ -46,7 +47,23 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
@@ -525,6 +532,16 @@ const struct flash_info spi_nor_ids[] =
@@ -257,6 +265,7 @@ const struct flash_info spi_nor_ids[] =
{ INFO("mx25u3235f", 0xc22536, 0, 4 * 1024, 1024, SECT_4K) },
{ INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) },
{ INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, SECT_4K) },
+ { INFO("mx25l12833f", 0xc22018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("mx25u12835f", 0xc22538, 0, 64 * 1024, 256, SECT_4K) },
{ INFO("mx25u51245g", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
@@ -265,6 +274,7 @@ const struct flash_info spi_nor_ids[] =
{ INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
{ INFO("mx25v8035f", 0xc22314, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("mx25r1635f", 0xc22815, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("mx25l25645g", 0xc22019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("mx25l25655e", 0xc22619, 0, 64 * 1024, 512, 0) },
{ INFO("mx66l51235l", 0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx66u51235f", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
@@ -525,6 +535,16 @@ const struct flash_info spi_nor_ids[] =
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
{
@ -63,7 +80,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
INFO("w25q128jw", 0xef8018, 0, 64 * 1024, 256,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
@@ -588,6 +605,11 @@ const struct flash_info spi_nor_ids[] =
@@ -588,6 +608,11 @@ const struct flash_info spi_nor_ids[] =
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
{ INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

296
package/boot/uboot-mediatek/patches/100-19-mtd-spi-nand-add-more-spi-nand-chips.patch Normal file
View file

@ -0,0 +1,296 @@
From 001ce4e53f197a358b4307d36cc6d5048fc59158 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Wed, 27 Jul 2022 16:36:13 +0800
Subject: [PATCH 19/30] mtd: spi-nand: add more spi-nand chips
Support more spi-nand chips
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/mtd/nand/spi/Makefile | 1 +
drivers/mtd/nand/spi/core.c | 1 +
drivers/mtd/nand/spi/etron.c | 181 ++++++++++++++++++++++++++++++
drivers/mtd/nand/spi/gigadevice.c | 38 +++++++
drivers/mtd/nand/spi/winbond.c | 9 ++
include/linux/mtd/spinand.h | 1 +
6 files changed, 231 insertions(+)
create mode 100644 drivers/mtd/nand/spi/etron.c
--- a/drivers/mtd/nand/spi/Makefile
+++ b/drivers/mtd/nand/spi/Makefile
@@ -2,4 +2,5 @@
spinand-objs := core.o esmt.o gigadevice.o macronix.o micron.o paragon.o
spinand-objs += toshiba.o winbond.o xtx.o
+spinand-objs += etron.o
obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -826,6 +826,7 @@ static const struct nand_ops spinand_ops
};
static const struct spinand_manufacturer *spinand_manufacturers[] = {
+ &etron_spinand_manufacturer,
&gigadevice_spinand_manufacturer,
&macronix_spinand_manufacturer,
&micron_spinand_manufacturer,
--- /dev/null
+++ b/drivers/mtd/nand/spi/etron.c
@@ -0,0 +1,181 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 Etron Technology, Inc.
+ *
+ */
+#ifndef __UBOOT__
+#include <malloc.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#endif
+#include <linux/bug.h>
+#include <linux/mtd/spinand.h>
+
+#define SPINAND_MFR_ETRON 0xD5
+
+#define STATUS_ECC_LIMIT_BITFLIPS (3 << 4)
+
+static SPINAND_OP_VARIANTS(read_cache_variants,
+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+static SPINAND_OP_VARIANTS(write_cache_variants,
+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
+
+static SPINAND_OP_VARIANTS(update_cache_variants,
+ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
+ SPINAND_PROG_LOAD(false, 0, NULL, 0));
+
+static int etron_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 3)
+ return -ERANGE;
+
+ region->offset = (14 * section) + 72;
+ region->length = 14;
+
+ return 0;
+}
+
+static int etron_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 3)
+ return -ERANGE;
+
+ if (section) {
+ region->offset = 18 * section;
+ region->length = 18;
+ } else {
+ /* section 0 has one byte reserved for bad block mark */
+ region->offset = 2;
+ region->length = 16;
+ }
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops etron_ooblayout = {
+ .ecc = etron_ooblayout_ecc,
+ .rfree = etron_ooblayout_free,
+};
+
+static int etron_ecc_get_status(struct spinand_device *spinand,
+ u8 status)
+{
+ struct nand_device *nand = spinand_to_nand(spinand);
+
+ switch (status & STATUS_ECC_MASK) {
+ case STATUS_ECC_NO_BITFLIPS:
+ return 0;
+
+ case STATUS_ECC_UNCOR_ERROR:
+ return -EBADMSG;
+
+ case STATUS_ECC_HAS_BITFLIPS:
+ return nand->eccreq.strength >> 1;
+
+ case STATUS_ECC_LIMIT_BITFLIPS:
+ return nand->eccreq.strength;
+
+ default:
+ break;
+ }
+
+ return -EINVAL;
+}
+
+static const struct spinand_info etron_spinand_table[] = {
+ /* EM73C 1Gb 3.3V */
+ SPINAND_INFO("EM73C044VCF",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x25),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+ /* EM7xD 2Gb */
+ SPINAND_INFO("EM73D044VCR",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x41),
+ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+ SPINAND_INFO("EM73D044VCO",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x3A),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+ SPINAND_INFO("EM78D044VCM",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x8E),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+ /* EM7xE 4Gb */
+ SPINAND_INFO("EM73E044VCE",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x3B),
+ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+ SPINAND_INFO("EM78E044VCD",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x8F),
+ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+ /* EM7xF044VCA 8Gb */
+ SPINAND_INFO("EM73F044VCA",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15),
+ NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+ SPINAND_INFO("EM78F044VCA",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x8D),
+ NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+};
+
+static const struct spinand_manufacturer_ops etron_spinand_manuf_ops = {
+};
+
+const struct spinand_manufacturer etron_spinand_manufacturer = {
+ .id = SPINAND_MFR_ETRON,
+ .name = "Etron",
+ .chips = etron_spinand_table,
+ .nchips = ARRAY_SIZE(etron_spinand_table),
+ .ops = &etron_spinand_manuf_ops,
+};
--- a/drivers/mtd/nand/spi/gigadevice.c
+++ b/drivers/mtd/nand/spi/gigadevice.c
@@ -284,7 +284,45 @@ static int gd5fxgq4ufxxg_ecc_get_status(
return -EINVAL;
}
+static int esmt_1_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 3)
+ return -ERANGE;
+
+ region->offset = (16 * section) + 8;
+ region->length = 8;
+
+ return 0;
+}
+
+static int esmt_1_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 3)
+ return -ERANGE;
+
+ region->offset = (16 * section) + 2;
+ region->length = 6;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops esmt_1_ooblayout = {
+ .ecc = esmt_1_ooblayout_ecc,
+ .rfree = esmt_1_ooblayout_free,
+};
+
static const struct spinand_info gigadevice_spinand_table[] = {
+ SPINAND_INFO("F50L1G41LB",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x01),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+ &write_cache_variants,
+ &update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(&esmt_1_ooblayout, NULL)),
SPINAND_INFO("GD5F1GQ4xA",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf1),
NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
--- a/drivers/mtd/nand/spi/winbond.c
+++ b/drivers/mtd/nand/spi/winbond.c
@@ -167,6 +167,15 @@ static const struct spinand_info winbond
&update_cache_variants),
0,
SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
+ SPINAND_INFO("W25N01KV",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xae, 0x21),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)),
SPINAND_INFO("W25N02KV",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x22),
NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
--- a/include/linux/mtd/spinand.h
+++ b/include/linux/mtd/spinand.h
@@ -244,6 +244,7 @@ struct spinand_manufacturer {
};
/* SPI NAND manufacturers */
+extern const struct spinand_manufacturer etron_spinand_manufacturer;
extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
extern const struct spinand_manufacturer macronix_spinand_manufacturer;
extern const struct spinand_manufacturer micron_spinand_manufacturer;

154
package/boot/uboot-mediatek/patches/100-20-mtd-spi-nand-add-support-for-FudanMicro-chips.patch Normal file
View file

@ -0,0 +1,154 @@
From 83cd1b0984bf53da247eb8fca1119668eb0ba7ea Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Wed, 15 Jan 2025 14:41:03 +0800
Subject: [PATCH 20/30] mtd: spi-nand: add support for FudanMicro chips
Sdd support for FudanMicro SPI-NAND flashes
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/mtd/nand/spi/Makefile | 1 +
drivers/mtd/nand/spi/core.c | 1 +
drivers/mtd/nand/spi/fudanmicro.c | 107 ++++++++++++++++++++++++++++++
include/linux/mtd/spinand.h | 1 +
4 files changed, 110 insertions(+)
create mode 100644 drivers/mtd/nand/spi/fudanmicro.c
--- a/drivers/mtd/nand/spi/Makefile
+++ b/drivers/mtd/nand/spi/Makefile
@@ -3,4 +3,5 @@
spinand-objs := core.o esmt.o gigadevice.o macronix.o micron.o paragon.o
spinand-objs += toshiba.o winbond.o xtx.o
spinand-objs += etron.o
+spinand-objs += fudanmicro.o
obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -827,6 +827,7 @@ static const struct nand_ops spinand_ops
static const struct spinand_manufacturer *spinand_manufacturers[] = {
&etron_spinand_manufacturer,
+ &fudan_spinand_manufacturer,
&gigadevice_spinand_manufacturer,
&macronix_spinand_manufacturer,
&micron_spinand_manufacturer,
--- /dev/null
+++ b/drivers/mtd/nand/spi/fudanmicro.c
@@ -0,0 +1,107 @@
+#ifndef __UBOOT__
+#include <malloc.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#endif
+#include <linux/bitops.h>
+#include <linux/mtd/spinand.h>
+
+#define SPINAND_MFR_FUDAN 0xA1
+
+#define FM25S01B_STATUS_ECC_MASK (7 << 4)
+#define STATUS_ECC_1_3_BITFLIPS (1 << 4)
+#define STATUS_ECC_4_6_BITFLIPS (3 << 4)
+#define STATUS_ECC_7_8_BITFLIPS (5 << 4)
+
+static SPINAND_OP_VARIANTS(read_cache_variants,
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+static SPINAND_OP_VARIANTS(write_cache_variants,
+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
+
+static SPINAND_OP_VARIANTS(update_cache_variants,
+ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
+ SPINAND_PROG_LOAD(false, 0, NULL, 0));
+
+static int fm25s01b_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section)
+ return -ERANGE;
+
+ region->offset = 64;
+ region->length = 64;
+
+ return 0;
+}
+
+static int fm25s01b_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 3)
+ return -ERANGE;
+
+ region->offset = (16 * section) + 4;
+ region->length = 12;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops fm25s01b_ooblayout = {
+ .ecc = fm25s01b_ooblayout_ecc,
+ .rfree = fm25s01b_ooblayout_free,
+};
+
+static int fm25s01b_ecc_get_status(struct spinand_device *spinand,
+ u8 status)
+{
+ switch (status & FM25S01B_STATUS_ECC_MASK) {
+ case STATUS_ECC_NO_BITFLIPS:
+ return 0;
+
+ case STATUS_ECC_UNCOR_ERROR:
+ return -EBADMSG;
+
+ case STATUS_ECC_1_3_BITFLIPS:
+ return 3;
+
+ case STATUS_ECC_4_6_BITFLIPS:
+ return 6;
+
+ case STATUS_ECC_7_8_BITFLIPS:
+ return 8;
+
+ default:
+ break;
+ }
+
+ return -EINVAL;
+}
+
+static const struct spinand_info fudan_spinand_table[] = {
+ SPINAND_INFO("FM25s01B",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD4),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&fm25s01b_ooblayout,
+ fm25s01b_ecc_get_status)),
+};
+
+static const struct spinand_manufacturer_ops fudan_spinand_manuf_ops = {
+};
+
+const struct spinand_manufacturer fudan_spinand_manufacturer = {
+ .id = SPINAND_MFR_FUDAN,
+ .name = "FUDAN Micron",
+ .chips = fudan_spinand_table,
+ .nchips = ARRAY_SIZE(fudan_spinand_table),
+ .ops = &fudan_spinand_manuf_ops,
+};
--- a/include/linux/mtd/spinand.h
+++ b/include/linux/mtd/spinand.h
@@ -245,6 +245,7 @@ struct spinand_manufacturer {
/* SPI NAND manufacturers */
extern const struct spinand_manufacturer etron_spinand_manufacturer;
+extern const struct spinand_manufacturer fudan_spinand_manufacturer;
extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
extern const struct spinand_manufacturer macronix_spinand_manufacturer;
extern const struct spinand_manufacturer micron_spinand_manufacturer;

1225
package/boot/uboot-mediatek/patches/100-21-mtd-spi-nand-add-CASN-page-support.patch Normal file
View file

File diff suppressed because it is too large Load diff

4
package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch → package/boot/uboot-mediatek/patches/100-22-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch
View file

@ -1,7 +1,7 @@
From 793bed29e78cc54d989333d756fef51efaca4e56 Mon Sep 17 00:00:00 2001
From deccfea9a0f0aa889933073323764593fc2298f5 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Tue, 26 Jul 2022 09:29:18 +0800
Subject: [PATCH 58/71] mmc: mtk-sd: add support to display verbose error log
Subject: [PATCH 22/30] mmc: mtk-sd: add support to display verbose error log
Add an option to enable debug log, and also display verbose error log for
both command and data.

550
package/boot/uboot-mediatek/patches/100-22-mtd-spi-nand-backport-from-upstream-kernel.patch
View file

@ -1,550 +0,0 @@
From 8d0665327819c41fce2c8d50f19c967b22eae564 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Wed, 27 Jul 2022 16:36:13 +0800
Subject: [PATCH 57/71] mtd: spi-nand: backport from upstream kernel
Backport new features from upstream kernel
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/mtd/nand/spi/Kconfig | 1 +
drivers/mtd/nand/spi/Makefile | 2 +-
drivers/mtd/nand/spi/core.c | 102 ++++++----
drivers/mtd/nand/spi/etron.c | 181 +++++++++++++++++
drivers/mtd/nand/spi/gigadevice.c | 322 ++++++++++++++++++++++++++----
drivers/mtd/nand/spi/macronix.c | 173 +++++++++++++---
drivers/mtd/nand/spi/micron.c | 50 ++---
drivers/mtd/nand/spi/toshiba.c | 66 +++---
drivers/mtd/nand/spi/winbond.c | 164 ++++++++++++---
include/linux/mtd/spinand.h | 87 +++++---
10 files changed, 923 insertions(+), 225 deletions(-)
create mode 100644 drivers/mtd/nand/spi/etron.c
--- a/drivers/mtd/nand/spi/Makefile
+++ b/drivers/mtd/nand/spi/Makefile
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
-spinand-objs := core.o esmt.o gigadevice.o macronix.o micron.o paragon.o
+spinand-objs := core.o esmt.o etron.o gigadevice.o macronix.o micron.o paragon.o
spinand-objs += toshiba.o winbond.o xtx.o
obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -826,6 +826,7 @@ static const struct nand_ops spinand_ops
};
static const struct spinand_manufacturer *spinand_manufacturers[] = {
+ &etron_spinand_manufacturer,
&gigadevice_spinand_manufacturer,
&macronix_spinand_manufacturer,
&micron_spinand_manufacturer,
--- /dev/null
+++ b/drivers/mtd/nand/spi/etron.c
@@ -0,0 +1,181 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 Etron Technology, Inc.
+ *
+ */
+#ifndef __UBOOT__
+#include <malloc.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#endif
+#include <linux/bug.h>
+#include <linux/mtd/spinand.h>
+
+#define SPINAND_MFR_ETRON 0xD5
+
+#define STATUS_ECC_LIMIT_BITFLIPS (3 << 4)
+
+static SPINAND_OP_VARIANTS(read_cache_variants,
+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+static SPINAND_OP_VARIANTS(write_cache_variants,
+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
+
+static SPINAND_OP_VARIANTS(update_cache_variants,
+ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
+ SPINAND_PROG_LOAD(false, 0, NULL, 0));
+
+static int etron_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 3)
+ return -ERANGE;
+
+ region->offset = (14 * section) + 72;
+ region->length = 14;
+
+ return 0;
+}
+
+static int etron_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 3)
+ return -ERANGE;
+
+ if (section) {
+ region->offset = 18 * section;
+ region->length = 18;
+ } else {
+ /* section 0 has one byte reserved for bad block mark */
+ region->offset = 2;
+ region->length = 16;
+ }
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops etron_ooblayout = {
+ .ecc = etron_ooblayout_ecc,
+ .rfree = etron_ooblayout_free,
+};
+
+static int etron_ecc_get_status(struct spinand_device *spinand,
+ u8 status)
+{
+ struct nand_device *nand = spinand_to_nand(spinand);
+
+ switch (status & STATUS_ECC_MASK) {
+ case STATUS_ECC_NO_BITFLIPS:
+ return 0;
+
+ case STATUS_ECC_UNCOR_ERROR:
+ return -EBADMSG;
+
+ case STATUS_ECC_HAS_BITFLIPS:
+ return nand->eccreq.strength >> 1;
+
+ case STATUS_ECC_LIMIT_BITFLIPS:
+ return nand->eccreq.strength;
+
+ default:
+ break;
+ }
+
+ return -EINVAL;
+}
+
+static const struct spinand_info etron_spinand_table[] = {
+ /* EM73C 1Gb 3.3V */
+ SPINAND_INFO("EM73C044VCF",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x25),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+ /* EM7xD 2Gb */
+ SPINAND_INFO("EM73D044VCR",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x41),
+ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+ SPINAND_INFO("EM73D044VCO",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x3A),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+ SPINAND_INFO("EM78D044VCM",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x8E),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+ /* EM7xE 4Gb */
+ SPINAND_INFO("EM73E044VCE",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x3B),
+ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+ SPINAND_INFO("EM78E044VCD",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x8F),
+ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+ /* EM7xF044VCA 8Gb */
+ SPINAND_INFO("EM73F044VCA",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15),
+ NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+ SPINAND_INFO("EM78F044VCA",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x8D),
+ NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+};
+
+static const struct spinand_manufacturer_ops etron_spinand_manuf_ops = {
+};
+
+const struct spinand_manufacturer etron_spinand_manufacturer = {
+ .id = SPINAND_MFR_ETRON,
+ .name = "Etron",
+ .chips = etron_spinand_table,
+ .nchips = ARRAY_SIZE(etron_spinand_table),
+ .ops = &etron_spinand_manuf_ops,
+};
--- a/drivers/mtd/nand/spi/gigadevice.c
+++ b/drivers/mtd/nand/spi/gigadevice.c
@@ -43,6 +43,24 @@ static SPINAND_OP_VARIANTS(read_cache_va
SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0));
+/* Q5 1Gb */
+static SPINAND_OP_VARIANTS(dummy2_read_cache_variants,
+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+/* Q5 2Gb & 4Gb */
+static SPINAND_OP_VARIANTS(dummy4_read_cache_variants,
+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 4, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 2, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
static SPINAND_OP_VARIANTS(write_cache_variants,
SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
SPINAND_PROG_LOAD(true, 0, NULL, 0));
@@ -268,7 +286,45 @@ static int gd5fxgq4ufxxg_ecc_get_status(
return -EINVAL;
}
+static int esmt_1_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 3)
+ return -ERANGE;
+
+ region->offset = (16 * section) + 8;
+ region->length = 8;
+
+ return 0;
+}
+
+static int esmt_1_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 3)
+ return -ERANGE;
+
+ region->offset = (16 * section) + 2;
+ region->length = 6;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops esmt_1_ooblayout = {
+ .ecc = esmt_1_ooblayout_ecc,
+ .rfree = esmt_1_ooblayout_free,
+ };
+
static const struct spinand_info gigadevice_spinand_table[] = {
+ SPINAND_INFO("F50L1G41LB",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x01),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&dummy2_read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(&esmt_1_ooblayout, NULL)),
SPINAND_INFO("GD5F1GQ4xA",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf1),
NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
@@ -349,6 +405,87 @@ static const struct spinand_info gigadev
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
gd5fxgq5xexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F2GQ5UExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x52),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq5xexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F4GQ6UExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x55),
+ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq5xexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F1GM7UExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x91),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4uexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F2GM7UExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x92),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4uexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F4GM8UExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x95),
+ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4uexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F1GQ5UExxH",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x31),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&dummy2_read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq5xexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F2GQ5UExxH",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x32),
+ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq5xexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F4GQ6UExxH",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35),
+ NAND_MEMORG(1, 2048, 64, 64, 4096, 40, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq5xexxg_ecc_get_status)),
+
};
static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {
--- a/drivers/mtd/nand/spi/winbond.c
+++ b/drivers/mtd/nand/spi/winbond.c
@@ -18,6 +18,23 @@
#define WINBOND_CFG_BUF_READ BIT(3)
+#define W25N02_N04KV_STATUS_ECC_MASK (3 << 4)
+#define W25N02_N04KV_STATUS_ECC_NO_BITFLIPS (0 << 4)
+#define W25N02_N04KV_STATUS_ECC_1_4_BITFLIPS (1 << 4)
+#define W25N02_N04KV_STATUS_ECC_5_8_BITFLIPS (3 << 4)
+#define W25N02_N04KV_STATUS_ECC_UNCOR_ERROR (2 << 4)
+
+#define W25N01_M02GV_STATUS_ECC_MASK (3 << 4)
+#define W25N01_M02GV_STATUS_ECC_NO_BITFLIPS (0 << 4)
+#define W25N01_M02GV_STATUS_ECC_1_BITFLIPS (1 << 4)
+#define W25N01_M02GV_STATUS_ECC_UNCOR_ERROR (2 << 4)
+
+#define W25N01KV_STATUS_ECC_MASK (3 << 4)
+#define W25N01KV_STATUS_ECC_NO_BITFLIPS (0 << 4)
+#define W25N01KV_STATUS_ECC_1_3_BITFLIPS (1 << 4)
+#define W25N01KV_STATUS_ECC_4_BITFLIPS (3 << 4)
+#define W25N01KV_STATUS_ECC_UNCOR_ERROR (2 << 4)
+
static SPINAND_OP_VARIANTS(read_cache_variants,
SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
@@ -34,6 +51,35 @@ static SPINAND_OP_VARIANTS(update_cache_
SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
SPINAND_PROG_LOAD(false, 0, NULL, 0));
+static int w25n02kv_n04kv_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 3)
+ return -ERANGE;
+
+ region->offset = (16 * section) + 64;
+ region->length = 16;
+
+ return 0;
+}
+
+static int w25n02kv_n04kv_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 3)
+ return -ERANGE;
+
+ region->offset = (16 * section) + 2;
+ region->length = 14;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops w25n02kv_n04kv_ooblayout = {
+ .ecc = w25n02kv_n04kv_ooblayout_ecc,
+ .rfree = w25n02kv_n04kv_ooblayout_free,
+};
+
static int w25m02gv_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
@@ -106,6 +152,58 @@ static const struct mtd_ooblayout_ops w2
.rfree = w25n02kv_ooblayout_free,
};
+static int w25n01kv_ecc_get_status(struct spinand_device *spinand,
+ u8 status)
+{
+ switch (status & W25N01KV_STATUS_ECC_MASK) {
+ case W25N01KV_STATUS_ECC_NO_BITFLIPS:
+ return 0;
+
+ case W25N01KV_STATUS_ECC_1_3_BITFLIPS:
+ return 3;
+
+ case W25N01KV_STATUS_ECC_4_BITFLIPS:
+ return 4;
+
+ case W25N01KV_STATUS_ECC_UNCOR_ERROR:
+ return -EBADMSG;
+
+ default:
+ break;
+ }
+
+ return -EINVAL;
+}
+
+static int w25n02kv_n04kv_ecc_get_status(struct spinand_device *spinand,
+ u8 status)
+{
+ switch (status & W25N02_N04KV_STATUS_ECC_MASK) {
+ case W25N02_N04KV_STATUS_ECC_NO_BITFLIPS:
+ return 0;
+
+ case W25N02_N04KV_STATUS_ECC_1_4_BITFLIPS:
+ return 3;
+
+ case W25N02_N04KV_STATUS_ECC_5_8_BITFLIPS:
+ return 4;
+
+ /* W25N02_N04KV_use internal 8bit ECC algorithm.
+ * But the ECC strength is 4 bit requried.
+ * Return 3 if the bit bit flip count less than 5.
+ * Return 4 if the bit bit flip count more than 5 to 8.
+ */
+
+ case W25N02_N04KV_STATUS_ECC_UNCOR_ERROR:
+ return -EBADMSG;
+
+ default:
+ break;
+ }
+
+ return -EINVAL;
+}
+
static int w25n02kv_ecc_get_status(struct spinand_device *spinand,
u8 status)
{
@@ -163,6 +261,15 @@ static const struct spinand_info winbond
&update_cache_variants),
0,
SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
+ SPINAND_INFO("W25N01KV",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xae, 0x21),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(&w25n02kv_n04kv_ooblayout, w25n01kv_ecc_get_status)),
SPINAND_INFO("W25N02KV",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x22),
NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
@@ -172,6 +279,16 @@ static const struct spinand_info winbond
&update_cache_variants),
0,
SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)),
+ SPINAND_INFO("W25N04KV",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x23),
+ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 2, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(&w25n02kv_n04kv_ooblayout,
+ w25n02kv_n04kv_ecc_get_status)),
};
static int winbond_spinand_init(struct spinand_device *spinand)
--- a/include/linux/mtd/spinand.h
+++ b/include/linux/mtd/spinand.h
@@ -244,6 +244,7 @@ struct spinand_manufacturer {
};
/* SPI NAND manufacturers */
+extern const struct spinand_manufacturer etron_spinand_manufacturer;
extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
extern const struct spinand_manufacturer macronix_spinand_manufacturer;
extern const struct spinand_manufacturer micron_spinand_manufacturer;

4
package/boot/uboot-mediatek/patches/100-24-cmd-ubi-make-volume-find-create-remove-APIs-public.patch → package/boot/uboot-mediatek/patches/100-23-cmd-ubi-make-volume-find-create-remove-APIs-public.patch
View file

@ -1,7 +1,7 @@
From dd66fc817f7ab7a4fcab9836a9251a8f64f329df Mon Sep 17 00:00:00 2001
From 3873a7f91bdfaa918b1593196df1da2de41662f4 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Mon, 25 Jul 2022 16:58:36 +0800
Subject: [PATCH 59/71] cmd: ubi: make volume find/create/remove APIs public
Subject: [PATCH 23/30] cmd: ubi: make volume find/create/remove APIs public
Export ubi_create_vol/ubi_find_volume/ubi_remove_vol to public so that they
can be used by other programs.

4
package/boot/uboot-mediatek/patches/100-25-cmd-ubi-allow-creating-volume-with-all-free-spaces.patch → package/boot/uboot-mediatek/patches/100-24-cmd-ubi-allow-creating-volume-with-all-free-spaces.patch
View file

@ -1,7 +1,7 @@
From f6a4130959af1e6d13d616203e42ed3c894666ad Mon Sep 17 00:00:00 2001
From 98ac40f08a59a18198a676a5419bdc72d484c150 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Mon, 25 Jul 2022 17:00:00 +0800
Subject: [PATCH 60/71] cmd: ubi: allow creating volume with all free spaces
Subject: [PATCH 24/30] cmd: ubi: allow creating volume with all free spaces
Allow creating volume with all free spaces by giving a negative size value.

9
package/boot/uboot-mediatek/patches/100-26-env-ubi-add-support-to-create-environment-volume-if-.patch → package/boot/uboot-mediatek/patches/100-25-env-ubi-add-support-to-create-environment-volume-if-.patch
View file

@ -1,7 +1,7 @@
From fc0c70a7c6a088072d0c77e5a59d5e9b7754c6db Mon Sep 17 00:00:00 2001
From e1ea321b028c2af81770c55aa5f1f319228e9a39 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Mon, 25 Jul 2022 17:01:20 +0800
Subject: [PATCH 61/71] env: ubi: add support to create environment volume if
Subject: [PATCH 25/30] env: ubi: add support to create environment volume if
it does not exist
Add an option to allow environment volume being auto created if not exist.
@ -48,7 +48,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
static int env_ubi_load(void)
{
@@ -134,6 +146,10 @@ static int env_ubi_load(void)
@@ -134,6 +146,11 @@ static int env_ubi_load(void)
return -EIO;
}
@ -56,10 +56,11 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+ env_ubi_volume_create(CONFIG_ENV_UBI_VOLUME);
+ env_ubi_volume_create(CONFIG_ENV_UBI_VOLUME_REDUND);
+ }
+
read1_fail = ubi_volume_read(CONFIG_ENV_UBI_VOLUME, (void *)tmp_env1, 0,
CONFIG_ENV_SIZE);
if (read1_fail)
@@ -171,6 +187,9 @@ static int env_ubi_load(void)
@@ -171,6 +188,9 @@ static int env_ubi_load(void)
return -EIO;
}

4
package/boot/uboot-mediatek/patches/100-27-mtd-ubi-add-support-for-UBI-end-of-filesystem-marker.patch → package/boot/uboot-mediatek/patches/100-26-mtd-ubi-add-support-for-UBI-end-of-filesystem-marker.patch
View file

@ -1,7 +1,7 @@
From 189a2fe96931ef3ea0e187c8e9bfa589c2a0ae10 Mon Sep 17 00:00:00 2001
From 501b4d1a43ce6bce4e8fa07ba164af1eec05c8be Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Mon, 25 Jul 2022 17:24:56 +0800
Subject: [PATCH 62/71] mtd: ubi: add support for UBI end-of-filesystem marker
Subject: [PATCH 26/30] mtd: ubi: add support for UBI end-of-filesystem marker
used by OpenWrt
Add support for UBI end-of-filesystem marker used by OpenWrt to allow

24662
package/boot/uboot-mediatek/patches/100-27-net-phy-aquantia-add-support-to-use-embedded-firmwar.patch Normal file
View file

File diff suppressed because it is too large Load diff

11917
package/boot/uboot-mediatek/patches/100-28-net-phy-add-support-for-Airoha-ethernet-PHY-driver.patch Normal file
View file

File diff suppressed because it is too large Load diff

32
package/boot/uboot-mediatek/patches/100-29-net-phy-add-Marvell-CUX3410.patch Normal file
View file

@ -0,0 +1,32 @@
From cedc08e33bf608765464dd80ce3cc170a636a3dd Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Thu, 16 Jan 2025 09:13:10 +0800
Subject: [PATCH 29/30] net: phy: add Marvell CUX3410
Add support for Marvell CUX3410 ethernet PHY
Signed-off-by: Bo-Cun Chen <bc-bocun.chen@mediatek.com>
---
drivers/net/phy/aquantia.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
--- a/drivers/net/phy/aquantia.c
+++ b/drivers/net/phy/aquantia.c
@@ -744,3 +744,17 @@ U_BOOT_PHY_DRIVER(aqr412) = {
.shutdown = &gen10g_shutdown,
.data = AQUANTIA_GEN3,
};
+
+U_BOOT_PHY_DRIVER(cux3410) = {
+ .name = "Marvell CUX3410",
+ .uid = 0x31c31dd3,
+ .mask = 0xfffffff0,
+ .features = PHY_10G_FEATURES,
+ .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS |
+ MDIO_MMD_PHYXS | MDIO_MMD_AN |
+ MDIO_MMD_VEND1),
+ .config = &aquantia_config,
+ .startup = &aquantia_startup,
+ .shutdown = &gen10g_shutdown,
+ .data = AQUANTIA_GEN3,
+};

16941
package/boot/uboot-mediatek/patches/100-30-net-phy-add-support-for-MediaTek-built-in-2.5Gbps-PH.patch Normal file
View file

File diff suppressed because it is too large Load diff

13
package/boot/uboot-mediatek/patches/101-01-mtd-spinand-add-support-for-FORESEE-F35SQA002G.patch
View file

@ -20,16 +20,17 @@ Link: https://lore.kernel.org/linux-mtd/20231002140458.147605-1-mmkurbanov@salut
--- a/drivers/mtd/nand/spi/Makefile
+++ b/drivers/mtd/nand/spi/Makefile
@@ -1,5 +1,5 @@
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
-spinand-objs := core.o esmt.o etron.o gigadevice.o macronix.o micron.o paragon.o
+spinand-objs := core.o esmt.o foresee.o etron.o gigadevice.o macronix.o micron.o paragon.o
-spinand-objs := core.o esmt.o gigadevice.o macronix.o micron.o paragon.o
+spinand-objs := core.o esmt.o foresee.o gigadevice.o macronix.o micron.o paragon.o
spinand-objs += toshiba.o winbond.o xtx.o
obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
spinand-objs += etron.o
spinand-objs += fudanmicro.o
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -834,6 +834,7 @@ static const struct spinand_manufacturer
@@ -895,6 +895,7 @@ static const struct spinand_manufacturer
&toshiba_spinand_manufacturer,
&winbond_spinand_manufacturer,
&esmt_c8_spinand_manufacturer,
@ -139,7 +140,7 @@ Link: https://lore.kernel.org/linux-mtd/20231002140458.147605-1-mmkurbanov@salut
+};
--- a/include/linux/mtd/spinand.h
+++ b/include/linux/mtd/spinand.h
@@ -252,6 +252,7 @@ extern const struct spinand_manufacturer
@@ -306,6 +306,7 @@ extern const struct spinand_manufacturer
extern const struct spinand_manufacturer toshiba_spinand_manufacturer;
extern const struct spinand_manufacturer winbond_spinand_manufacturer;
extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer;

26
package/boot/uboot-mediatek/patches/104-snfi-add-support-for-GD5F1GQ5UE.patch Normal file
View file

@ -0,0 +1,26 @@
From ec8c3dc701cfd53e1ddc9817041e710fb4bbb0f3 Mon Sep 17 00:00:00 2001
From: Chuanhong Guo <gch981213@gmail.com>
Date: Sat, 9 Mar 2024 12:06:31 +0800
Subject: [PATCH] snfi: add support for GD5F1GQ5UE
This patch adds support for GigaDevice GD5F1GQ5UExxG to the
mtk-snfi driver in u-boot.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
---
drivers/mtd/mtk-snand/mtk-snand-ids.c | 4 ++++
1 file changed, 4 insertions(+)
--- a/drivers/mtd/mtk-snand/mtk-snand-ids.c
+++ b/drivers/mtd/mtk-snand/mtk-snand-ids.c
@@ -115,6 +115,10 @@ static const struct snand_flash_info sna
SNAND_MEMORG_1G_2K_64,
&snand_cap_read_from_cache_quad_q2d,
&snand_cap_program_load_x4),
+ SNAND_INFO("GD5F1GQ5UExxG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0x51),
+ SNAND_MEMORG_1G_2K_128,
+ &snand_cap_read_from_cache_quad,
+ &snand_cap_program_load_x4),
SNAND_INFO("GD5F2GQ4UExIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd2),
SNAND_MEMORG_2G_2K_128,
&snand_cap_read_from_cache_quad_q2d,

28
package/boot/uboot-mediatek/patches/106-configs-sync-mt7981-rfb-storage.patch
View file

@ -12,29 +12,15 @@
CONFIG_REGMAP=y
--- a/configs/mt7981_snfi_nand_rfb_defconfig
+++ b/configs/mt7981_snfi_nand_rfb_defconfig
@@ -1,11 +1,12 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_POSITION_INDEPENDENT=y
CONFIG_ARCH_MEDIATEK=y
@@ -5,7 +5,6 @@ CONFIG_ARCH_MEDIATEK=y
CONFIG_TEXT_BASE=0x41e00000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
-CONFIG_ENV_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="mt7981-snfi-nand-rfb"
+CONFIG_SYS_PROMPT="MT7981> "
CONFIG_SYS_PROMPT="MT7981> "
CONFIG_TARGET_MT7981=y
CONFIG_DEBUG_UART_BASE=0x11002000
CONFIG_DEBUG_UART_CLOCK=40000000
@@ -15,7 +16,6 @@ CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="mt7981-snfi-nand-rfb"
CONFIG_LOGLEVEL=7
CONFIG_LOG=y
-CONFIG_SYS_PROMPT="MT7981> "
CONFIG_SYS_CBSIZE=512
CONFIG_SYS_PBSIZE=1049
# CONFIG_BOOTM_NETBSD is not set
@@ -29,8 +29,6 @@ CONFIG_CMD_GPIO=y
@@ -30,8 +29,6 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_MTD=y
CONFIG_CMD_PING=y
CONFIG_CMD_SMC=y
@ -43,14 +29,6 @@
CONFIG_CMD_UBI=y
CONFIG_CMD_UBI_RENAME=y
CONFIG_ENV_OVERWRITE=y
@@ -45,7 +43,6 @@ CONFIG_DM_MTD=y
CONFIG_MTK_SPI_NAND=y
CONFIG_MTK_SPI_NAND_MTD=y
CONFIG_PHY_FIXED=y
-CONFIG_DM_ETH=y
CONFIG_MEDIATEK_ETH=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
@@ -55,3 +52,4 @@ CONFIG_MTK_POWER_DOMAIN=y
CONFIG_DM_SERIAL=y
CONFIG_MTK_SERIAL=y

24
package/boot/uboot-mediatek/patches/109-snfi-FM35Q1GA-is-x4-only.patch Normal file
View file

@ -0,0 +1,24 @@
From a6487e393b1b073ba0895e10f00d0fbb2a5e88d9 Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Mon, 8 Apr 2024 19:35:27 +0100
Subject: [PATCH 2/2] snfi: FM35Q1GA is x4-only
Dont allow x2 read and cache read operations on FM35Q1GA as they seem
to be unstable. Also the Linux drivers does not allow x2 ops.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
drivers/mtd/mtk-snand/mtk-snand-ids.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/mtd/mtk-snand/mtk-snand-ids.c
+++ b/drivers/mtd/mtk-snand/mtk-snand-ids.c
@@ -431,7 +431,7 @@ static const struct snand_flash_info sna
SNAND_INFO("FM35Q1GA", SNAND_ID(SNAND_ID_DYMMY, 0xe5, 0x71),
SNAND_MEMORG_1G_2K_64,
- &snand_cap_read_from_cache_x4,
+ &snand_cap_read_from_cache_x4_only,
&snand_cap_program_load_x4),
SNAND_INFO("PN26G01A", SNAND_ID(SNAND_ID_DYMMY, 0xa1, 0xe1),

0
package/boot/uboot-mediatek/patches/100-29-board-mediatek-wire-up-NMBM-support.patch → package/boot/uboot-mediatek/patches/129-board-mediatek-wire-up-NMBM-support.patch
View file

1929
package/boot/uboot-mediatek/patches/160-net-phy-add-support-for-Airoha-ethernet-PHY-driver.patch
View file

File diff suppressed because it is too large Load diff

33
package/boot/uboot-mediatek/patches/407-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch
View file

@ -1,33 +0,0 @@
From 93d7086edb0db4b05149dfea21a2a82d8f160944 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Sat, 6 Mar 2021 16:29:33 +0800
Subject: [PATCH 10/12] configs: mt7622: enable environment for mt7622_rfb
Enable environment vairables for mt7622_rfb
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
configs/mt7622_rfb_defconfig | 5 +++++
1 file changed, 5 insertions(+)
--- a/configs/mt7622_rfb_defconfig
+++ b/configs/mt7622_rfb_defconfig
@@ -5,6 +5,8 @@ CONFIG_ARCH_MEDIATEK=y
CONFIG_TEXT_BASE=0x41e00000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0x280000
CONFIG_DEFAULT_DEVICE_TREE="mt7622-rfb"
CONFIG_SYS_LOAD_ADDR=0x4007ff28
CONFIG_DEBUG_UART_BASE=0x11002000
@@ -26,6 +28,9 @@ CONFIG_CMD_SF_TEST=y
CONFIG_CMD_PING=y
CONFIG_CMD_SMC=y
CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MTD=y
+CONFIG_ENV_MTD_NAME="spi-nand0"
+CONFIG_ENV_SIZE_REDUND=0x40000
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_USE_IPADDR=y
CONFIG_IPADDR="192.168.1.1"