ramips: mmc: Sync with staging drivers
Mostly whitespace cleanups. Some unneeded code was removed.
MMC init was also moved to the probe function as in
6069bdd087
The cleanup commits are over 100, making it hard to do them individually.
Tested on GnuBee PC1 with an SD card being used as swap.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
This commit is contained in:
Rosen Penev
John Crispin
parent
50913b77e4
commit
2d401925b9
5 changed files with 2559 additions and 3284 deletions
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@ -36,27 +36,10 @@
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#ifndef __ARCH_ARM_MACH_BOARD_H
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#define __ARCH_ARM_MACH_BOARD_H
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#include <generated/autoconf.h>
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#include <linux/pm.h>
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/* --- chhung */
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// #include <mach/mt6575.h>
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// #include <board-custom.h>
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/* end of chhung */
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typedef void (*sdio_irq_handler_t)(void*); /* external irq handler */
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typedef void (*pm_callback_t)(pm_message_t state, void *data);
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#define MSDC_CD_PIN_EN (1 << 0) /* card detection pin is wired */
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#define MSDC_WP_PIN_EN (1 << 1) /* write protection pin is wired */
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#define MSDC_RST_PIN_EN (1 << 2) /* emmc reset pin is wired */
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#define MSDC_SDIO_IRQ (1 << 3) /* use internal sdio irq (bus) */
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#define MSDC_EXT_SDIO_IRQ (1 << 4) /* use external sdio irq */
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#define MSDC_REMOVABLE (1 << 5) /* removable slot */
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#define MSDC_SYS_SUSPEND (1 << 6) /* suspended by system */
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#define MSDC_HIGHSPEED (1 << 7) /* high-speed mode support */
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#define MSDC_UHS1 (1 << 8) /* uhs-1 mode support */
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#define MSDC_DDR (1 << 9) /* ddr mode support */
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#define MSDC_SMPL_RISING (0)
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#define MSDC_SMPL_FALLING (1)
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@ -67,71 +50,14 @@ typedef void (*pm_callback_t)(pm_message_t state, void *data);
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#define MSDC_WP_PIN (3)
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#define MSDC_RST_PIN (4)
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enum {
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MSDC_CLKSRC_48MHZ = 0,
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// MSDC_CLKSRC_26MHZ = 0,
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// MSDC_CLKSRC_197MHZ = 1,
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// MSDC_CLKSRC_208MHZ = 2
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};
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struct msdc_hw {
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unsigned char clk_src; /* host clock source */
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unsigned char cmd_edge; /* command latch edge */
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unsigned char data_edge; /* data latch edge */
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unsigned char clk_drv; /* clock pad driving */
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unsigned char cmd_drv; /* command pad driving */
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unsigned char dat_drv; /* data pad driving */
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unsigned long flags; /* hardware capability flags */
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unsigned long data_pins; /* data pins */
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unsigned long data_offset; /* data address offset */
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/* config gpio pull mode */
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void (*config_gpio_pin)(int type, int pull);
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/* external power control for card */
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void (*ext_power_on)(void);
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void (*ext_power_off)(void);
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/* external sdio irq operations */
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void (*request_sdio_eirq)(sdio_irq_handler_t sdio_irq_handler, void *data);
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void (*enable_sdio_eirq)(void);
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void (*disable_sdio_eirq)(void);
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/* external cd irq operations */
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void (*request_cd_eirq)(sdio_irq_handler_t cd_irq_handler, void *data);
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void (*enable_cd_eirq)(void);
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void (*disable_cd_eirq)(void);
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int (*get_cd_status)(void);
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/* power management callback for external module */
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void (*register_pm)(pm_callback_t pm_cb, void *data);
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};
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extern struct msdc_hw msdc0_hw;
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extern struct msdc_hw msdc1_hw;
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extern struct msdc_hw msdc2_hw;
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extern struct msdc_hw msdc3_hw;
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/*GPS driver*/
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#define GPS_FLAG_FORCE_OFF 0x0001
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struct mt3326_gps_hardware {
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int (*ext_power_on)(int);
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int (*ext_power_off)(int);
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};
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extern struct mt3326_gps_hardware mt3326_gps_hw;
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/* NAND driver */
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struct mt6575_nand_host_hw {
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unsigned int nfi_bus_width; /* NFI_BUS_WIDTH */
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unsigned int nfi_access_timing; /* NFI_ACCESS_TIMING */
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unsigned int nfi_cs_num; /* NFI_CS_NUM */
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unsigned int nand_sec_size; /* NAND_SECTOR_SIZE */
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unsigned int nand_sec_shift; /* NAND_SECTOR_SHIFT */
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unsigned int nand_ecc_size;
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unsigned int nand_ecc_bytes;
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unsigned int nand_ecc_mode;
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};
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extern struct mt6575_nand_host_hw mt6575_nand_hw;
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#endif /* __ARCH_ARM_MACH_BOARD_H */
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@ -48,37 +48,22 @@
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#include "mt6575_sd.h"
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#include <linux/seq_file.h>
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/* mode select */
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u32 dma_size[4]={
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512,
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512,
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512,
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512
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};
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msdc_mode drv_mode[4]={
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MODE_SIZE_DEP, /* using DMA or not depend on the size */
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MODE_SIZE_DEP,
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MODE_SIZE_DEP,
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MODE_SIZE_DEP
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};
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#if defined (MT6575_SD_DEBUG)
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static char cmd_buf[256];
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/* for debug zone */
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static unsigned int sd_debug_zone[4]={
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unsigned int sd_debug_zone[4] = {
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0,
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0,
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0,
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0
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};
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#if defined(MT6575_SD_DEBUG)
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/* for driver profile */
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#define TICKS_ONE_MS (13000)
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u32 gpt_enable = 0;
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u32 sdio_pro_enable = 0; /* make sure gpt is enabled */
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u32 sdio_pro_time = 0; /* no more than 30s */
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u32 gpt_enable;
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u32 sdio_pro_enable; /* make sure gpt is enabled */
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u32 sdio_pro_time; /* no more than 30s */
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struct sdio_profile sdio_perfomance = {0};
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#if 0 /* --- chhung */
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@ -91,7 +76,7 @@ void msdc_init_gpt(void)
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config.clkSrc = GPT_CLK_SRC_SYS;
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config.clkDiv = GPT_CLK_DIV_1; /* 13MHz GPT6 */
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if (GPT_Config(config) == FALSE )
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if (GPT_Config(config) == FALSE)
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return;
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GPT_Start(GPT6);
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@ -104,10 +89,9 @@ u32 msdc_time_calc(u32 old_L32, u32 old_H32, u32 new_L32, u32 new_H32)
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if (new_H32 == old_H32) {
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ret = new_L32 - old_L32;
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} else if(new_H32 == (old_H32 + 1)) {
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if (new_L32 > old_L32) {
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} else if (new_H32 == (old_H32 + 1)) {
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if (new_L32 > old_L32)
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printk("msdc old_L<0x%x> new_L<0x%x>\n", old_L32, new_L32);
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}
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ret = (0xffffffff - old_L32);
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ret += new_L32;
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} else {
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@ -117,9 +101,9 @@ u32 msdc_time_calc(u32 old_L32, u32 old_H32, u32 new_L32, u32 new_H32)
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return ret;
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}
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void msdc_sdio_profile(struct sdio_profile* result)
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void msdc_sdio_profile(struct sdio_profile *result)
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{
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struct cmd_profile* cmd;
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struct cmd_profile *cmd;
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u32 i;
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printk("sdio === performance dump ===\n");
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@ -130,44 +114,44 @@ void msdc_sdio_profile(struct sdio_profile* result)
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/* CMD52 Dump */
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cmd = &result->cmd52_rx;
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printk("sdio === CMD52 Rx <%d>times tick<%d> Max<%d> Min<%d> Aver<%d>\n", cmd->count, cmd->tot_tc,
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cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count);
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cmd->max_tc, cmd->min_tc, cmd->tot_tc / cmd->count);
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cmd = &result->cmd52_tx;
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printk("sdio === CMD52 Tx <%d>times tick<%d> Max<%d> Min<%d> Aver<%d>\n", cmd->count, cmd->tot_tc,
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cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count);
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cmd->max_tc, cmd->min_tc, cmd->tot_tc / cmd->count);
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/* CMD53 Rx bytes + block mode */
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for (i=0; i<512; i++) {
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for (i = 0; i < 512; i++) {
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cmd = &result->cmd53_rx_byte[i];
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if (cmd->count) {
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printk("sdio<%6d><%3dB>_Rx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
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cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
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cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));
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cmd->max_tc, cmd->min_tc, cmd->tot_tc / cmd->count,
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cmd->tot_bytes, (cmd->tot_bytes / 10) * 13 / (cmd->tot_tc / 10));
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}
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}
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for (i=0; i<100; i++) {
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for (i = 0; i < 100; i++) {
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cmd = &result->cmd53_rx_blk[i];
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if (cmd->count) {
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printk("sdio<%6d><%3d>B_Rx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
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cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
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cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));
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cmd->max_tc, cmd->min_tc, cmd->tot_tc / cmd->count,
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cmd->tot_bytes, (cmd->tot_bytes / 10) * 13 / (cmd->tot_tc / 10));
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}
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}
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/* CMD53 Tx bytes + block mode */
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for (i=0; i<512; i++) {
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for (i = 0; i < 512; i++) {
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cmd = &result->cmd53_tx_byte[i];
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if (cmd->count) {
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printk("sdio<%6d><%3dB>_Tx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
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cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
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cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));
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cmd->max_tc, cmd->min_tc, cmd->tot_tc / cmd->count,
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cmd->tot_bytes, (cmd->tot_bytes / 10) * 13 / (cmd->tot_tc / 10));
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}
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}
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for (i=0; i<100; i++) {
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for (i = 0; i < 100; i++) {
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cmd = &result->cmd53_tx_blk[i];
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if (cmd->count) {
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printk("sdio<%6d><%3d>B_Tx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
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cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
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cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));
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cmd->max_tc, cmd->min_tc, cmd->tot_tc / cmd->count,
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cmd->tot_bytes, (cmd->tot_bytes / 10) * 13 / (cmd->tot_tc / 10));
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}
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}
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@ -177,13 +161,12 @@ void msdc_sdio_profile(struct sdio_profile* result)
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//========= sdio command table ===========
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void msdc_performance(u32 opcode, u32 sizes, u32 bRx, u32 ticks)
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{
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struct sdio_profile* result = &sdio_perfomance;
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struct cmd_profile* cmd;
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struct sdio_profile *result = &sdio_perfomance;
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struct cmd_profile *cmd;
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u32 block;
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if (sdio_pro_enable == 0) {
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if (sdio_pro_enable == 0)
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return;
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}
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if (opcode == 52) {
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cmd = bRx ? &result->cmd52_rx : &result->cmd52_tx;
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@ -194,7 +177,8 @@ void msdc_performance(u32 opcode, u32 sizes, u32 bRx, u32 ticks)
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block = sizes / 512;
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if (block >= 99) {
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printk("cmd53 error blocks\n");
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while(1);
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while (1)
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;
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}
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cmd = bRx ? &result->cmd53_rx_blk[block] : &result->cmd53_tx_blk[block];
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}
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@ -203,54 +187,43 @@ void msdc_performance(u32 opcode, u32 sizes, u32 bRx, u32 ticks)
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}
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/* update the members */
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if (ticks > cmd->max_tc){
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if (ticks > cmd->max_tc)
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cmd->max_tc = ticks;
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}
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if (cmd->min_tc == 0 || ticks < cmd->min_tc) {
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if (cmd->min_tc == 0 || ticks < cmd->min_tc)
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cmd->min_tc = ticks;
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}
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cmd->tot_tc += ticks;
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cmd->tot_bytes += sizes;
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cmd->count ++;
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cmd->count++;
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if (bRx) {
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if (bRx)
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result->total_rx_bytes += sizes;
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} else {
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else
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result->total_tx_bytes += sizes;
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}
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result->total_tc += ticks;
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/* dump when total_tc > 30s */
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if (result->total_tc >= sdio_pro_time * TICKS_ONE_MS * 1000) {
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msdc_sdio_profile(result);
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memset(result, 0 , sizeof(struct sdio_profile));
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memset(result, 0, sizeof(struct sdio_profile));
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}
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}
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//========== driver proc interface ===========
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static int msdc_debug_proc_read(struct seq_file *s, void *p)
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{
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seq_printf(s, "\n=========================================\n");
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seq_printf(s, "Index<0> + Id + Zone\n");
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seq_printf(s, "-> PWR<9> WRN<8> | FIO<7> OPS<6> FUN<5> CFG<4> | INT<3> RSP<2> CMD<1> DMA<0>\n");
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seq_printf(s, "-> echo 0 3 0x3ff >msdc_bebug -> host[3] debug zone set to 0x3ff\n");
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seq_puts(s, "\n=========================================\n");
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seq_puts(s, "Index<0> + Id + Zone\n");
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seq_puts(s, "-> PWR<9> WRN<8> | FIO<7> OPS<6> FUN<5> CFG<4> | INT<3> RSP<2> CMD<1> DMA<0>\n");
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seq_puts(s, "-> echo 0 3 0x3ff >msdc_bebug -> host[3] debug zone set to 0x3ff\n");
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seq_printf(s, "-> MSDC[0] Zone: 0x%.8x\n", sd_debug_zone[0]);
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seq_printf(s, "-> MSDC[1] Zone: 0x%.8x\n", sd_debug_zone[1]);
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seq_printf(s, "-> MSDC[2] Zone: 0x%.8x\n", sd_debug_zone[2]);
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seq_printf(s, "-> MSDC[3] Zone: 0x%.8x\n", sd_debug_zone[3]);
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seq_printf(s, "Index<1> + ID:4|Mode:4 + DMA_SIZE\n");
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seq_printf(s, "-> 0)PIO 1)DMA 2)SIZE\n");
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seq_printf(s, "-> echo 1 22 0x200 >msdc_bebug -> host[2] size mode, dma when >= 512\n");
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seq_printf(s, "-> MSDC[0] mode<%d> size<%d>\n", drv_mode[0], dma_size[0]);
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seq_printf(s, "-> MSDC[1] mode<%d> size<%d>\n", drv_mode[1], dma_size[1]);
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seq_printf(s, "-> MSDC[2] mode<%d> size<%d>\n", drv_mode[2], dma_size[2]);
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seq_printf(s, "-> MSDC[3] mode<%d> size<%d>\n", drv_mode[3], dma_size[3]);
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seq_printf(s, "Index<3> + SDIO_PROFILE + TIME\n");
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seq_printf(s, "-> echo 3 1 0x1E >msdc_bebug -> enable sdio_profile, 30s\n");
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seq_puts(s, "Index<3> + SDIO_PROFILE + TIME\n");
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seq_puts(s, "-> echo 3 1 0x1E >msdc_bebug -> enable sdio_profile, 30s\n");
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seq_printf(s, "-> SDIO_PROFILE<%d> TIME<%ds>\n", sdio_pro_enable, sdio_pro_time);
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seq_printf(s, "=========================================\n\n");
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seq_puts(s, "=========================================\n\n");
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return 0;
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}
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@ -264,45 +237,32 @@ static ssize_t msdc_debug_proc_write(struct file *file,
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int id, zone;
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int mode, size;
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if (count == 0)return -1;
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if(count > 255)count = 255;
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if (count == 0)
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return -1;
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if (count > 255)
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count = 255;
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ret = copy_from_user(cmd_buf, buf, count);
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if (ret < 0)return -1;
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if (copy_from_user(cmd_buf, buf, count))
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return -EFAULT;
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cmd_buf[count] = '\0';
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printk("msdc Write %s\n", cmd_buf);
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sscanf(cmd_buf, "%x %x %x", &cmd, &p1, &p2);
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if(cmd == SD_TOOL_ZONE) {
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id = p1; zone = p2; zone &= 0x3ff;
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if (cmd == SD_TOOL_ZONE) {
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id = p1;
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zone = p2;
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zone &= 0x3ff;
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printk("msdc host_id<%d> zone<0x%.8x>\n", id, zone);
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if(id >=0 && id<=3){
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if (id >= 0 && id <= 3) {
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sd_debug_zone[id] = zone;
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}
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else if(id == 4){
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} else if (id == 4) {
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sd_debug_zone[0] = sd_debug_zone[1] = zone;
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sd_debug_zone[2] = sd_debug_zone[3] = zone;
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}
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else{
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} else {
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printk("msdc host_id error when set debug zone\n");
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}
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} else if (cmd == SD_TOOL_DMA_SIZE) {
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id = p1>>4; mode = (p1&0xf); size = p2;
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if(id >=0 && id<=3){
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drv_mode[id] = mode;
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dma_size[id] = p2;
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}
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else if(id == 4){
|
||||
drv_mode[0] = drv_mode[1] = mode;
|
||||
drv_mode[2] = drv_mode[3] = mode;
|
||||
dma_size[0] = dma_size[1] = p2;
|
||||
dma_size[2] = dma_size[3] = p2;
|
||||
}
|
||||
else{
|
||||
printk("msdc host_id error when select mode\n");
|
||||
}
|
||||
} else if (cmd == SD_TOOL_SDIO_PROFILE) {
|
||||
if (p1 == 1) { /* enable profile */
|
||||
if (gpt_enable == 0) {
|
||||
|
|
@ -310,8 +270,11 @@ static ssize_t msdc_debug_proc_write(struct file *file,
|
|||
gpt_enable = 1;
|
||||
}
|
||||
sdio_pro_enable = 1;
|
||||
if (p2 == 0) p2 = 1; if (p2 >= 30) p2 = 30;
|
||||
sdio_pro_time = p2 ;
|
||||
if (p2 == 0)
|
||||
p2 = 1;
|
||||
if (p2 >= 30)
|
||||
p2 = 30;
|
||||
sdio_pro_time = p2;
|
||||
} else if (p1 == 0) {
|
||||
/* todo */
|
||||
sdio_pro_enable = 0;
|
||||
|
|
@ -335,14 +298,9 @@ static const struct file_operations msdc_debug_fops = {
|
|||
.release = single_release,
|
||||
};
|
||||
|
||||
int msdc_debug_proc_init(void)
|
||||
void msdc_debug_proc_init(void)
|
||||
{
|
||||
struct proc_dir_entry *de = proc_create("msdc_debug", 0667, NULL, &msdc_debug_fops);
|
||||
|
||||
if (!de || IS_ERR(de))
|
||||
printk("!! Create MSDC debug PROC fail !!\n");
|
||||
|
||||
return 0 ;
|
||||
proc_create("msdc_debug", 0660, NULL, &msdc_debug_fops);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(msdc_debug_proc_init);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -66,20 +66,18 @@ struct sdio_profile {
|
|||
};
|
||||
|
||||
//==========================
|
||||
typedef enum {
|
||||
enum msdc_dbg {
|
||||
SD_TOOL_ZONE = 0,
|
||||
SD_TOOL_DMA_SIZE = 1,
|
||||
SD_TOOL_PM_ENABLE = 2,
|
||||
SD_TOOL_SDIO_PROFILE = 3,
|
||||
} msdc_dbg;
|
||||
};
|
||||
|
||||
typedef enum {
|
||||
enum msdc_mode {
|
||||
MODE_PIO = 0,
|
||||
MODE_DMA = 1,
|
||||
MODE_SIZE_DEP = 2,
|
||||
} msdc_mode;
|
||||
extern msdc_mode drv_mode[4];
|
||||
extern u32 dma_size[4];
|
||||
};
|
||||
|
||||
/* Debug message event */
|
||||
#define DBG_EVT_NONE (0) /* No event */
|
||||
|
|
@ -104,9 +102,10 @@ extern unsigned int sd_debug_zone[4];
|
|||
do { \
|
||||
if (x) { \
|
||||
printk("[BUG] %s LINE:%d FILE:%s\n", #x, __LINE__, __FILE__); \
|
||||
while(1); \
|
||||
while (1) \
|
||||
; \
|
||||
} \
|
||||
}while(0)
|
||||
} while (0)
|
||||
#endif /* end of +++ */
|
||||
|
||||
#define N_MSG(evt, fmt, args...)
|
||||
|
|
@ -122,8 +121,8 @@ do { \
|
|||
#define ERR_MSG(fmt, args...) \
|
||||
do { \
|
||||
printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d> PID<%s><0x%x>\n", \
|
||||
host->id, ##args , __FUNCTION__, __LINE__, current->comm, current->pid); \
|
||||
} while(0);
|
||||
host->id, ##args, __FUNCTION__, __LINE__, current->comm, current->pid); \
|
||||
} while (0);
|
||||
|
||||
#if 1
|
||||
//defined CONFIG_MTK_MMC_CD_POLL
|
||||
|
|
@ -133,18 +132,18 @@ do { \
|
|||
#define INIT_MSG(fmt, args...) \
|
||||
do { \
|
||||
printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d> PID<%s><0x%x>\n", \
|
||||
host->id, ##args , __FUNCTION__, __LINE__, current->comm, current->pid); \
|
||||
} while(0);
|
||||
host->id, ##args, __FUNCTION__, __LINE__, current->comm, current->pid); \
|
||||
} while (0);
|
||||
|
||||
/* PID in ISR in not corrent */
|
||||
#define IRQ_MSG(fmt, args...) \
|
||||
do { \
|
||||
printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d>\n", \
|
||||
host->id, ##args , __FUNCTION__, __LINE__); \
|
||||
} while(0);
|
||||
host->id, ##args, __FUNCTION__, __LINE__); \
|
||||
} while (0);
|
||||
#endif
|
||||
|
||||
int msdc_debug_proc_init(void);
|
||||
void msdc_debug_proc_init(void);
|
||||
|
||||
#if 0 /* --- chhung */
|
||||
void msdc_init_gpt(void);
|
||||
|
|
|
|||
|
|
@ -37,7 +37,6 @@
|
|||
#define MT6575_SD_H
|
||||
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/mmc/host.h>
|
||||
|
||||
// #include <mach/mt6575_reg_base.h> /* --- by chhung */
|
||||
|
|
@ -45,7 +44,7 @@
|
|||
/*--------------------------------------------------------------------------*/
|
||||
/* Common Macro */
|
||||
/*--------------------------------------------------------------------------*/
|
||||
#define REG_ADDR(x) ((volatile u32*)(base + OFFSET_##x))
|
||||
#define REG_ADDR(x) (base + OFFSET_##x)
|
||||
|
||||
/*--------------------------------------------------------------------------*/
|
||||
/* Common Definition */
|
||||
|
|
@ -254,7 +253,7 @@ enum {
|
|||
#define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
|
||||
#define MSDC_PS_DAT (0xff << 16) /* R */
|
||||
#define MSDC_PS_CMD (0x1 << 24) /* R */
|
||||
#define MSDC_PS_WP (0x1UL<< 31) /* R */
|
||||
#define MSDC_PS_WP (0x1UL << 31) /* R */
|
||||
|
||||
/* MSDC_INT mask */
|
||||
#define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
|
||||
|
|
@ -295,7 +294,7 @@ enum {
|
|||
/* MSDC_FIFOCS mask */
|
||||
#define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */
|
||||
#define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */
|
||||
#define MSDC_FIFOCS_CLR (0x1UL<< 31) /* RW */
|
||||
#define MSDC_FIFOCS_CLR (0x1UL << 31) /* RW */
|
||||
|
||||
/* SDC_CFG mask */
|
||||
#define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
|
||||
|
|
@ -315,7 +314,7 @@ enum {
|
|||
#define SDC_CMD_RW (0x1 << 13) /* RW */
|
||||
#define SDC_CMD_STOP (0x1 << 14) /* RW */
|
||||
#define SDC_CMD_GOIRQ (0x1 << 15) /* RW */
|
||||
#define SDC_CMD_BLKLEN (0xfff<< 16) /* RW */
|
||||
#define SDC_CMD_BLKLEN (0xfff << 16) /* RW */
|
||||
#define SDC_CMD_AUTOCMD (0x3 << 28) /* RW */
|
||||
#define SDC_CMD_VOLSWTH (0x1 << 30) /* RW */
|
||||
|
||||
|
|
@ -397,7 +396,7 @@ enum {
|
|||
#define MSDC_PAD_CTL0_CLKSMT (0x1 << 18) /* RW */
|
||||
#define MSDC_PAD_CTL0_CLKIES (0x1 << 19) /* RW */
|
||||
#define MSDC_PAD_CTL0_CLKTDSEL (0xf << 20) /* RW */
|
||||
#define MSDC_PAD_CTL0_CLKRDSEL (0xffUL<< 24) /* RW */
|
||||
#define MSDC_PAD_CTL0_CLKRDSEL (0xffUL << 24) /* RW */
|
||||
|
||||
/* MSDC_PAD_CTL1 mask */
|
||||
#define MSDC_PAD_CTL1_CMDDRVN (0x7 << 0) /* RW */
|
||||
|
|
@ -408,7 +407,7 @@ enum {
|
|||
#define MSDC_PAD_CTL1_CMDSMT (0x1 << 18) /* RW */
|
||||
#define MSDC_PAD_CTL1_CMDIES (0x1 << 19) /* RW */
|
||||
#define MSDC_PAD_CTL1_CMDTDSEL (0xf << 20) /* RW */
|
||||
#define MSDC_PAD_CTL1_CMDRDSEL (0xffUL<< 24) /* RW */
|
||||
#define MSDC_PAD_CTL1_CMDRDSEL (0xffUL << 24) /* RW */
|
||||
|
||||
/* MSDC_PAD_CTL2 mask */
|
||||
#define MSDC_PAD_CTL2_DATDRVN (0x7 << 0) /* RW */
|
||||
|
|
@ -419,7 +418,7 @@ enum {
|
|||
#define MSDC_PAD_CTL2_DATIES (0x1 << 19) /* RW */
|
||||
#define MSDC_PAD_CTL2_DATSMT (0x1 << 18) /* RW */
|
||||
#define MSDC_PAD_CTL2_DATTDSEL (0xf << 20) /* RW */
|
||||
#define MSDC_PAD_CTL2_DATRDSEL (0xffUL<< 24) /* RW */
|
||||
#define MSDC_PAD_CTL2_DATRDSEL (0xffUL << 24) /* RW */
|
||||
|
||||
/* MSDC_PAD_TUNE mask */
|
||||
#define MSDC_PAD_TUNE_DATWRDLY (0x1F << 0) /* RW */
|
||||
|
|
@ -439,16 +438,16 @@ enum {
|
|||
#define MSDC_DAT_RDDLY1_D6 (0x1F << 16) /* RW */
|
||||
#define MSDC_DAT_RDDLY1_D7 (0x1F << 24) /* RW */
|
||||
|
||||
#define MSDC_CKGEN_MSDC_DLY_SEL (0x1F<<10)
|
||||
#define MSDC_INT_DAT_LATCH_CK_SEL (0x7<<7)
|
||||
#define MSDC_CKGEN_MSDC_CK_SEL (0x1<<6)
|
||||
#define CARD_READY_FOR_DATA (1<<8)
|
||||
#define CARD_CURRENT_STATE(x) ((x&0x00001E00)>>9)
|
||||
#define MSDC_CKGEN_MSDC_DLY_SEL (0x1F << 10)
|
||||
#define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7)
|
||||
#define MSDC_CKGEN_MSDC_CK_SEL (0x1 << 6)
|
||||
#define CARD_READY_FOR_DATA (1 << 8)
|
||||
#define CARD_CURRENT_STATE(x) ((x & 0x00001E00) >> 9)
|
||||
|
||||
/*--------------------------------------------------------------------------*/
|
||||
/* Descriptor Structure */
|
||||
/*--------------------------------------------------------------------------*/
|
||||
typedef struct {
|
||||
struct gpd {
|
||||
u32 hwo:1; /* could be changed by hw */
|
||||
u32 bdp:1;
|
||||
u32 rsv0:6;
|
||||
|
|
@ -463,9 +462,9 @@ typedef struct {
|
|||
u32 arg;
|
||||
u32 blknum;
|
||||
u32 cmd;
|
||||
} gpd_t;
|
||||
};
|
||||
|
||||
typedef struct {
|
||||
struct bd {
|
||||
u32 eol:1;
|
||||
u32 rsv0:7;
|
||||
u32 chksum:8;
|
||||
|
|
@ -477,13 +476,13 @@ typedef struct {
|
|||
void *ptr;
|
||||
u32 buflen:16;
|
||||
u32 rsv3:16;
|
||||
} bd_t;
|
||||
};
|
||||
|
||||
/*--------------------------------------------------------------------------*/
|
||||
/* Register Debugging Structure */
|
||||
/*--------------------------------------------------------------------------*/
|
||||
|
||||
typedef struct {
|
||||
struct msdc_cfg_reg {
|
||||
u32 msdc:1;
|
||||
u32 ckpwn:1;
|
||||
u32 rst:1;
|
||||
|
|
@ -495,8 +494,9 @@ typedef struct {
|
|||
u32 ckdiv:8;
|
||||
u32 ckmod:2;
|
||||
u32 pad:14;
|
||||
} msdc_cfg_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct msdc_iocon_reg {
|
||||
u32 sdr104cksel:1;
|
||||
u32 rsmpl:1;
|
||||
u32 dsmpl:1;
|
||||
|
|
@ -514,8 +514,9 @@ typedef struct {
|
|||
u32 d7spl:1;
|
||||
u32 riscsz:1;
|
||||
u32 pad2:7;
|
||||
} msdc_iocon_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct msdc_ps_reg {
|
||||
u32 cden:1;
|
||||
u32 cdsts:1;
|
||||
u32 pad1:10;
|
||||
|
|
@ -524,8 +525,9 @@ typedef struct {
|
|||
u32 cmd:1;
|
||||
u32 pad2:6;
|
||||
u32 wp:1;
|
||||
} msdc_ps_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct msdc_int_reg {
|
||||
u32 mmcirq:1;
|
||||
u32 cdsc:1;
|
||||
u32 pad1:1;
|
||||
|
|
@ -544,8 +546,9 @@ typedef struct {
|
|||
u32 datcrc:1;
|
||||
u32 atocmd19done:1;
|
||||
u32 pad2:15;
|
||||
} msdc_int_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct msdc_inten_reg {
|
||||
u32 mmcirq:1;
|
||||
u32 cdsc:1;
|
||||
u32 pad1:1;
|
||||
|
|
@ -564,21 +567,25 @@ typedef struct {
|
|||
u32 datcrc:1;
|
||||
u32 atocmd19done:1;
|
||||
u32 pad2:15;
|
||||
} msdc_inten_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct msdc_fifocs_reg {
|
||||
u32 rxcnt:8;
|
||||
u32 pad1:8;
|
||||
u32 txcnt:8;
|
||||
u32 pad2:7;
|
||||
u32 clr:1;
|
||||
} msdc_fifocs_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct msdc_txdat_reg {
|
||||
u32 val;
|
||||
} msdc_txdat_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct msdc_rxdat_reg {
|
||||
u32 val;
|
||||
} msdc_rxdat_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct sdc_cfg_reg {
|
||||
u32 sdiowkup:1;
|
||||
u32 inswkup:1;
|
||||
u32 pad1:14;
|
||||
|
|
@ -589,8 +596,9 @@ typedef struct {
|
|||
u32 intblkgap:1;
|
||||
u32 pad4:2;
|
||||
u32 dtoc:8;
|
||||
} sdc_cfg_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct sdc_cmd_reg {
|
||||
u32 cmd:6;
|
||||
u32 brk:1;
|
||||
u32 rsptyp:3;
|
||||
|
|
@ -603,43 +611,54 @@ typedef struct {
|
|||
u32 atocmd:2;
|
||||
u32 volswth:1;
|
||||
u32 pad2:1;
|
||||
} sdc_cmd_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct sdc_arg_reg {
|
||||
u32 arg;
|
||||
} sdc_arg_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct sdc_sts_reg {
|
||||
u32 sdcbusy:1;
|
||||
u32 cmdbusy:1;
|
||||
u32 pad:29;
|
||||
u32 swrcmpl:1;
|
||||
} sdc_sts_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct sdc_resp0_reg {
|
||||
u32 val;
|
||||
} sdc_resp0_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct sdc_resp1_reg {
|
||||
u32 val;
|
||||
} sdc_resp1_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct sdc_resp2_reg {
|
||||
u32 val;
|
||||
} sdc_resp2_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct sdc_resp3_reg {
|
||||
u32 val;
|
||||
} sdc_resp3_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct sdc_blknum_reg {
|
||||
u32 num;
|
||||
} sdc_blknum_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct sdc_csts_reg {
|
||||
u32 sts;
|
||||
} sdc_csts_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct sdc_cstsen_reg {
|
||||
u32 sts;
|
||||
} sdc_cstsen_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct sdc_datcrcsts_reg {
|
||||
u32 datcrcsts:8;
|
||||
u32 ddrcrcsts:4;
|
||||
u32 pad:20;
|
||||
} sdc_datcrcsts_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct emmc_cfg0_reg {
|
||||
u32 bootstart:1;
|
||||
u32 bootstop:1;
|
||||
u32 bootmode:1;
|
||||
|
|
@ -647,13 +666,15 @@ typedef struct {
|
|||
u32 bootwaidly:3;
|
||||
u32 bootsupp:1;
|
||||
u32 pad2:16;
|
||||
} emmc_cfg0_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct emmc_cfg1_reg {
|
||||
u32 bootcrctmc:16;
|
||||
u32 pad:4;
|
||||
u32 bootacktmc:12;
|
||||
} emmc_cfg1_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct emmc_sts_reg {
|
||||
u32 bootcrcerr:1;
|
||||
u32 bootackerr:1;
|
||||
u32 bootdattmo:1;
|
||||
|
|
@ -662,28 +683,35 @@ typedef struct {
|
|||
u32 bootackrcv:1;
|
||||
u32 bootdatrcv:1;
|
||||
u32 pad:25;
|
||||
} emmc_sts_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct emmc_iocon_reg {
|
||||
u32 bootrst:1;
|
||||
u32 pad:31;
|
||||
} emmc_iocon_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct msdc_acmd_resp_reg {
|
||||
u32 val;
|
||||
} msdc_acmd_resp_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct msdc_acmd19_trg_reg {
|
||||
u32 tunesel:4;
|
||||
u32 pad:28;
|
||||
} msdc_acmd19_trg_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct msdc_acmd19_sts_reg {
|
||||
u32 val;
|
||||
} msdc_acmd19_sts_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct msdc_dma_sa_reg {
|
||||
u32 addr;
|
||||
} msdc_dma_sa_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct msdc_dma_ca_reg {
|
||||
u32 addr;
|
||||
} msdc_dma_ca_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct msdc_dma_ctrl_reg {
|
||||
u32 start:1;
|
||||
u32 stop:1;
|
||||
u32 resume:1;
|
||||
|
|
@ -695,23 +723,27 @@ typedef struct {
|
|||
u32 brustsz:3;
|
||||
u32 pad4:1;
|
||||
u32 xfersz:16;
|
||||
} msdc_dma_ctrl_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct msdc_dma_cfg_reg {
|
||||
u32 status:1;
|
||||
u32 decsen:1;
|
||||
u32 pad1:2;
|
||||
u32 bdcsen:1;
|
||||
u32 gpdcsen:1;
|
||||
u32 pad2:26;
|
||||
} msdc_dma_cfg_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct msdc_dbg_sel_reg {
|
||||
u32 sel:16;
|
||||
u32 pad2:16;
|
||||
} msdc_dbg_sel_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct msdc_dbg_out_reg {
|
||||
u32 val;
|
||||
} msdc_dbg_out_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct msdc_pad_ctl0_reg {
|
||||
u32 clkdrvn:3;
|
||||
u32 rsv0:1;
|
||||
u32 clkdrvp:3;
|
||||
|
|
@ -724,8 +756,9 @@ typedef struct {
|
|||
u32 clkies:1;
|
||||
u32 clktdsel:4;
|
||||
u32 clkrdsel:8;
|
||||
} msdc_pad_ctl0_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct msdc_pad_ctl1_reg {
|
||||
u32 cmddrvn:3;
|
||||
u32 rsv0:1;
|
||||
u32 cmddrvp:3;
|
||||
|
|
@ -738,8 +771,9 @@ typedef struct {
|
|||
u32 cmdies:1;
|
||||
u32 cmdtdsel:4;
|
||||
u32 cmdrdsel:8;
|
||||
} msdc_pad_ctl1_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct msdc_pad_ctl2_reg {
|
||||
u32 datdrvn:3;
|
||||
u32 rsv0:1;
|
||||
u32 datdrvp:3;
|
||||
|
|
@ -752,14 +786,16 @@ typedef struct {
|
|||
u32 daties:1;
|
||||
u32 dattdsel:4;
|
||||
u32 datrdsel:8;
|
||||
} msdc_pad_ctl2_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct msdc_pad_tune_reg {
|
||||
u32 wrrxdly:3;
|
||||
u32 pad1:5;
|
||||
u32 rdrxdly:8;
|
||||
u32 pad2:16;
|
||||
} msdc_pad_tune_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct msdc_dat_rddly0 {
|
||||
u32 dat0:5;
|
||||
u32 rsv0:3;
|
||||
u32 dat1:5;
|
||||
|
|
@ -768,8 +804,9 @@ typedef struct {
|
|||
u32 rsv2:3;
|
||||
u32 dat3:5;
|
||||
u32 rsv3:3;
|
||||
} msdc_dat_rddly0;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct msdc_dat_rddly1 {
|
||||
u32 dat4:5;
|
||||
u32 rsv4:3;
|
||||
u32 dat5:5;
|
||||
|
|
@ -778,8 +815,9 @@ typedef struct {
|
|||
u32 rsv6:3;
|
||||
u32 dat7:5;
|
||||
u32 rsv7:3;
|
||||
} msdc_dat_rddly1;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct msdc_hw_dbg_reg {
|
||||
u32 dbg0sel:8;
|
||||
u32 dbg1sel:6;
|
||||
u32 pad1:2;
|
||||
|
|
@ -787,106 +825,82 @@ typedef struct {
|
|||
u32 pad2:2;
|
||||
u32 dbg3sel:6;
|
||||
u32 pad3:2;
|
||||
} msdc_hw_dbg_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct msdc_version_reg {
|
||||
u32 val;
|
||||
} msdc_version_reg;
|
||||
typedef struct {
|
||||
};
|
||||
|
||||
struct msdc_eco_ver_reg {
|
||||
u32 val;
|
||||
} msdc_eco_ver_reg;
|
||||
};
|
||||
|
||||
struct msdc_regs {
|
||||
msdc_cfg_reg msdc_cfg; /* base+0x00h */
|
||||
msdc_iocon_reg msdc_iocon; /* base+0x04h */
|
||||
msdc_ps_reg msdc_ps; /* base+0x08h */
|
||||
msdc_int_reg msdc_int; /* base+0x0ch */
|
||||
msdc_inten_reg msdc_inten; /* base+0x10h */
|
||||
msdc_fifocs_reg msdc_fifocs; /* base+0x14h */
|
||||
msdc_txdat_reg msdc_txdat; /* base+0x18h */
|
||||
msdc_rxdat_reg msdc_rxdat; /* base+0x1ch */
|
||||
struct msdc_cfg_reg msdc_cfg; /* base+0x00h */
|
||||
struct msdc_iocon_reg msdc_iocon; /* base+0x04h */
|
||||
struct msdc_ps_reg msdc_ps; /* base+0x08h */
|
||||
struct msdc_int_reg msdc_int; /* base+0x0ch */
|
||||
struct msdc_inten_reg msdc_inten; /* base+0x10h */
|
||||
struct msdc_fifocs_reg msdc_fifocs; /* base+0x14h */
|
||||
struct msdc_txdat_reg msdc_txdat; /* base+0x18h */
|
||||
struct msdc_rxdat_reg msdc_rxdat; /* base+0x1ch */
|
||||
u32 rsv1[4];
|
||||
sdc_cfg_reg sdc_cfg; /* base+0x30h */
|
||||
sdc_cmd_reg sdc_cmd; /* base+0x34h */
|
||||
sdc_arg_reg sdc_arg; /* base+0x38h */
|
||||
sdc_sts_reg sdc_sts; /* base+0x3ch */
|
||||
sdc_resp0_reg sdc_resp0; /* base+0x40h */
|
||||
sdc_resp1_reg sdc_resp1; /* base+0x44h */
|
||||
sdc_resp2_reg sdc_resp2; /* base+0x48h */
|
||||
sdc_resp3_reg sdc_resp3; /* base+0x4ch */
|
||||
sdc_blknum_reg sdc_blknum; /* base+0x50h */
|
||||
struct sdc_cfg_reg sdc_cfg; /* base+0x30h */
|
||||
struct sdc_cmd_reg sdc_cmd; /* base+0x34h */
|
||||
struct sdc_arg_reg sdc_arg; /* base+0x38h */
|
||||
struct sdc_sts_reg sdc_sts; /* base+0x3ch */
|
||||
struct sdc_resp0_reg sdc_resp0; /* base+0x40h */
|
||||
struct sdc_resp1_reg sdc_resp1; /* base+0x44h */
|
||||
struct sdc_resp2_reg sdc_resp2; /* base+0x48h */
|
||||
struct sdc_resp3_reg sdc_resp3; /* base+0x4ch */
|
||||
struct sdc_blknum_reg sdc_blknum; /* base+0x50h */
|
||||
u32 rsv2[1];
|
||||
sdc_csts_reg sdc_csts; /* base+0x58h */
|
||||
sdc_cstsen_reg sdc_cstsen; /* base+0x5ch */
|
||||
sdc_datcrcsts_reg sdc_dcrcsta; /* base+0x60h */
|
||||
struct sdc_csts_reg sdc_csts; /* base+0x58h */
|
||||
struct sdc_cstsen_reg sdc_cstsen; /* base+0x5ch */
|
||||
struct sdc_datcrcsts_reg sdc_dcrcsta; /* base+0x60h */
|
||||
u32 rsv3[3];
|
||||
emmc_cfg0_reg emmc_cfg0; /* base+0x70h */
|
||||
emmc_cfg1_reg emmc_cfg1; /* base+0x74h */
|
||||
emmc_sts_reg emmc_sts; /* base+0x78h */
|
||||
emmc_iocon_reg emmc_iocon; /* base+0x7ch */
|
||||
msdc_acmd_resp_reg acmd_resp; /* base+0x80h */
|
||||
msdc_acmd19_trg_reg acmd19_trg; /* base+0x84h */
|
||||
msdc_acmd19_sts_reg acmd19_sts; /* base+0x88h */
|
||||
struct emmc_cfg0_reg emmc_cfg0; /* base+0x70h */
|
||||
struct emmc_cfg1_reg emmc_cfg1; /* base+0x74h */
|
||||
struct emmc_sts_reg emmc_sts; /* base+0x78h */
|
||||
struct emmc_iocon_reg emmc_iocon; /* base+0x7ch */
|
||||
struct msdc_acmd_resp_reg acmd_resp; /* base+0x80h */
|
||||
struct msdc_acmd19_trg_reg acmd19_trg; /* base+0x84h */
|
||||
struct msdc_acmd19_sts_reg acmd19_sts; /* base+0x88h */
|
||||
u32 rsv4[1];
|
||||
msdc_dma_sa_reg dma_sa; /* base+0x90h */
|
||||
msdc_dma_ca_reg dma_ca; /* base+0x94h */
|
||||
msdc_dma_ctrl_reg dma_ctrl; /* base+0x98h */
|
||||
msdc_dma_cfg_reg dma_cfg; /* base+0x9ch */
|
||||
msdc_dbg_sel_reg dbg_sel; /* base+0xa0h */
|
||||
msdc_dbg_out_reg dbg_out; /* base+0xa4h */
|
||||
struct msdc_dma_sa_reg dma_sa; /* base+0x90h */
|
||||
struct msdc_dma_ca_reg dma_ca; /* base+0x94h */
|
||||
struct msdc_dma_ctrl_reg dma_ctrl; /* base+0x98h */
|
||||
struct msdc_dma_cfg_reg dma_cfg; /* base+0x9ch */
|
||||
struct msdc_dbg_sel_reg dbg_sel; /* base+0xa0h */
|
||||
struct msdc_dbg_out_reg dbg_out; /* base+0xa4h */
|
||||
u32 rsv5[2];
|
||||
u32 patch0; /* base+0xb0h */
|
||||
u32 patch1; /* base+0xb4h */
|
||||
u32 rsv6[10];
|
||||
msdc_pad_ctl0_reg pad_ctl0; /* base+0xe0h */
|
||||
msdc_pad_ctl1_reg pad_ctl1; /* base+0xe4h */
|
||||
msdc_pad_ctl2_reg pad_ctl2; /* base+0xe8h */
|
||||
msdc_pad_tune_reg pad_tune; /* base+0xech */
|
||||
msdc_dat_rddly0 dat_rddly0; /* base+0xf0h */
|
||||
msdc_dat_rddly1 dat_rddly1; /* base+0xf4h */
|
||||
msdc_hw_dbg_reg hw_dbg; /* base+0xf8h */
|
||||
struct msdc_pad_ctl0_reg pad_ctl0; /* base+0xe0h */
|
||||
struct msdc_pad_ctl1_reg pad_ctl1; /* base+0xe4h */
|
||||
struct msdc_pad_ctl2_reg pad_ctl2; /* base+0xe8h */
|
||||
struct msdc_pad_tune_reg pad_tune; /* base+0xech */
|
||||
struct msdc_dat_rddly0 dat_rddly0; /* base+0xf0h */
|
||||
struct msdc_dat_rddly1 dat_rddly1; /* base+0xf4h */
|
||||
struct msdc_hw_dbg_reg hw_dbg; /* base+0xf8h */
|
||||
u32 rsv7[1];
|
||||
msdc_version_reg version; /* base+0x100h */
|
||||
msdc_eco_ver_reg eco_ver; /* base+0x104h */
|
||||
struct msdc_version_reg version; /* base+0x100h */
|
||||
struct msdc_eco_ver_reg eco_ver; /* base+0x104h */
|
||||
};
|
||||
|
||||
struct scatterlist_ex {
|
||||
u32 cmd;
|
||||
u32 arg;
|
||||
u32 sglen;
|
||||
struct scatterlist *sg;
|
||||
};
|
||||
|
||||
#define DMA_FLAG_NONE (0x00000000)
|
||||
#define DMA_FLAG_EN_CHKSUM (0x00000001)
|
||||
#define DMA_FLAG_PAD_BLOCK (0x00000002)
|
||||
#define DMA_FLAG_PAD_DWORD (0x00000004)
|
||||
|
||||
struct msdc_dma {
|
||||
u32 flags; /* flags */
|
||||
u32 xfersz; /* xfer size in bytes */
|
||||
u32 sglen; /* size of scatter list */
|
||||
u32 blklen; /* block size */
|
||||
struct scatterlist *sg; /* I/O scatter list */
|
||||
struct scatterlist_ex *esg; /* extended I/O scatter list */
|
||||
u8 mode; /* dma mode */
|
||||
u8 burstsz; /* burst size */
|
||||
u8 intr; /* dma done interrupt */
|
||||
u8 padding; /* padding */
|
||||
u32 cmd; /* enhanced mode command */
|
||||
u32 arg; /* enhanced mode arg */
|
||||
u32 rsp; /* enhanced mode command response */
|
||||
u32 autorsp; /* auto command response */
|
||||
|
||||
gpd_t *gpd; /* pointer to gpd array */
|
||||
bd_t *bd; /* pointer to bd array */
|
||||
struct gpd *gpd; /* pointer to gpd array */
|
||||
struct bd *bd; /* pointer to bd array */
|
||||
dma_addr_t gpd_addr; /* the physical address of gpd array */
|
||||
dma_addr_t bd_addr; /* the physical address of bd array */
|
||||
u32 used_gpd; /* the number of used gpd elements */
|
||||
u32 used_bd; /* the number of used bd elements */
|
||||
};
|
||||
|
||||
struct msdc_host
|
||||
{
|
||||
struct msdc_host {
|
||||
struct msdc_hw *hw;
|
||||
|
||||
struct mmc_host *mmc; /* mmc structure */
|
||||
|
|
@ -894,39 +908,27 @@ struct msdc_host
|
|||
struct mmc_data *data;
|
||||
struct mmc_request *mrq;
|
||||
int cmd_rsp;
|
||||
int cmd_rsp_done;
|
||||
int cmd_r1b_done;
|
||||
|
||||
int error;
|
||||
spinlock_t lock; /* mutex */
|
||||
struct semaphore sem;
|
||||
|
||||
u32 blksz; /* host block size */
|
||||
u32 base; /* host base address */
|
||||
void __iomem *base; /* host base address */
|
||||
int id; /* host id */
|
||||
int pwr_ref; /* core power reference count */
|
||||
|
||||
u32 xfer_size; /* total transferred size */
|
||||
|
||||
struct msdc_dma dma; /* dma channel */
|
||||
u32 dma_addr; /* dma transfer address */
|
||||
u32 dma_left_size; /* dma transfer left size */
|
||||
u32 dma_xfer_size; /* dma transfer size in bytes */
|
||||
int dma_xfer; /* dma transfer mode */
|
||||
|
||||
u32 timeout_ns; /* data timeout ns */
|
||||
u32 timeout_clks; /* data timeout clks */
|
||||
|
||||
atomic_t abort; /* abort transfer */
|
||||
|
||||
int irq; /* host interrupt */
|
||||
|
||||
struct tasklet_struct card_tasklet;
|
||||
#if 0
|
||||
struct work_struct card_workqueue;
|
||||
#else
|
||||
struct delayed_work card_delaywork;
|
||||
#endif
|
||||
|
||||
struct completion cmd_done;
|
||||
struct completion xfer_done;
|
||||
|
|
@ -941,62 +943,44 @@ struct msdc_host
|
|||
u8 power_mode; /* host power mode */
|
||||
u8 card_inserted; /* card inserted ? */
|
||||
u8 suspend; /* host suspended ? */
|
||||
u8 reserved;
|
||||
u8 app_cmd; /* for app command */
|
||||
u32 app_cmd_arg;
|
||||
u64 starttime;
|
||||
};
|
||||
|
||||
static inline unsigned int uffs(unsigned int x)
|
||||
#define sdr_read8(reg) readb(reg)
|
||||
#define sdr_read32(reg) readl(reg)
|
||||
#define sdr_write8(reg, val) writeb(val, reg)
|
||||
#define sdr_write32(reg, val) writel(val, reg)
|
||||
|
||||
static inline void sdr_set_bits(void __iomem *reg, u32 bs)
|
||||
{
|
||||
unsigned int r = 1;
|
||||
u32 val = readl(reg);
|
||||
|
||||
if (!x)
|
||||
return 0;
|
||||
if (!(x & 0xffff)) {
|
||||
x >>= 16;
|
||||
r += 16;
|
||||
}
|
||||
if (!(x & 0xff)) {
|
||||
x >>= 8;
|
||||
r += 8;
|
||||
}
|
||||
if (!(x & 0xf)) {
|
||||
x >>= 4;
|
||||
r += 4;
|
||||
}
|
||||
if (!(x & 3)) {
|
||||
x >>= 2;
|
||||
r += 2;
|
||||
}
|
||||
if (!(x & 1)) {
|
||||
x >>= 1;
|
||||
r += 1;
|
||||
}
|
||||
return r;
|
||||
val |= bs;
|
||||
writel(val, reg);
|
||||
}
|
||||
#define sdr_read8(reg) __raw_readb(reg)
|
||||
#define sdr_read16(reg) __raw_readw(reg)
|
||||
#define sdr_read32(reg) __raw_readl(reg)
|
||||
#define sdr_write8(reg,val) __raw_writeb(val,reg)
|
||||
#define sdr_write16(reg,val) __raw_writew(val,reg)
|
||||
#define sdr_write32(reg,val) __raw_writel(val,reg)
|
||||
|
||||
#define sdr_set_bits(reg,bs) ((*(volatile u32*)(reg)) |= (u32)(bs))
|
||||
#define sdr_clr_bits(reg,bs) ((*(volatile u32*)(reg)) &= ~((u32)(bs)))
|
||||
static inline void sdr_clr_bits(void __iomem *reg, u32 bs)
|
||||
{
|
||||
u32 val = readl(reg);
|
||||
|
||||
#define sdr_set_field(reg,field,val) \
|
||||
do { \
|
||||
volatile unsigned int tv = sdr_read32(reg); \
|
||||
tv &= ~(field); \
|
||||
tv |= ((val) << (uffs((unsigned int)field) - 1)); \
|
||||
sdr_write32(reg,tv); \
|
||||
} while(0)
|
||||
#define sdr_get_field(reg,field,val) \
|
||||
do { \
|
||||
volatile unsigned int tv = sdr_read32(reg); \
|
||||
val = ((tv & (field)) >> (uffs((unsigned int)field) - 1)); \
|
||||
} while(0)
|
||||
val &= ~bs;
|
||||
writel(val, reg);
|
||||
}
|
||||
|
||||
static inline void sdr_set_field(void __iomem *reg, u32 field, u32 val)
|
||||
{
|
||||
unsigned int tv = readl(reg);
|
||||
|
||||
tv &= ~field;
|
||||
tv |= ((val) << (ffs((unsigned int)field) - 1));
|
||||
writel(tv, reg);
|
||||
}
|
||||
|
||||
static inline void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
|
||||
{
|
||||
unsigned int tv = readl(reg);
|
||||
*val = ((tv & field) >> (ffs((unsigned int)field) - 1));
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
Loading…
Reference in a new issue