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uboot-mediatek: bump to v2025.04

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The following upstreamed / superseded patches were dropped:

 060-01-clk-mediatek-mt7629-fix-parent-clock-of-some-top-clo.patch
 060-02-arm-dts-mt7629-fix-sgmii-clock-selection-for-etherne.patch
 060-03-net-mediatek-use-correct-register-field-for-SGMII-sp.patch
 060-04-net-mediatek-correct-register-name-of-ethsys-syscfg1.patch
 060-05-net-mediatek-fix-sgmii-selection-for-mt7622.patch
 060-06-net-mediatek-fix-gmac2-usability-for-mt7629.patch
 060-07-net-mediatek-add-support-for-10GBASE-R.patch
 060-08-net-mediatek-make-sgmii-usxgmii-optional.patch
 060-09-net-mediatek-don-t-enable-GDMA-cpu-bridge-unconditio.patch
 060-10-net-mediatek-fix-usability-with-wget-command.patch
 061-01-net-mediatek-split-ethernet-switch-code-from-mtk_eth.patch
 061-02-net-mediatek-add-support-for-MediaTek-MT7987-SoC.patch
 061-03-net-mediatek-add-support-for-Airoha-AN8855-ethernet-.patch
 070-01-board-mediatek-mt7622-remove-board_late_init.patch
 070-02-clk-mediatek-fix-uninitialized-fields-issue-in-INFRA.patch
 070-03-configs-mt7629-move-image-load-address-to-0x42000000.patch
 070-04-configs-mt7988-move-image-load-address-to-0x44000000.patch
 070-05-spi-mtk_spim-add-support-to-use-DT-live-tree.patch
 070-06-spi-mtk_spim-check-slave-device-mode-in-spi-mem-s-su.patch
 070-07-arm-dts-mediatek-add-quad-mode-capabilities-for-SPI-.patch
 070-08-pwm-mediatek-add-pwm3-support-for-mt7981.patch
 070-09-pci-mediatek-add-support-for-multiple-ports-in-media.patch
 070-10-arm-dts-mediatek-add-pcie-support-for-mt7988.patch
 070-11-arm-dts-medaitek-fix-internal-switch-link-speed-of-m.patch
 070-12-arm-dts-mediatek-add-support-for-all-three-GMACs-for.patch
 070-13-arm-dts-medaitek-add-flash-interface-driving-setting.patch
 070-14-arm-dts-mediatek-update-mt7981-mmc-node.patch
 070-15-MAINTAINERS-update-file-list-for-MediaTek-ARM-platfo.patch
 071-01-pinctrl-mediatek-update-mt7981-pinctrl-driver-based-.patch
 100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch
 290-mt7981-add-USB-nodes.patch

Refreshed all the patches needing it.

Run-tested: GatoNetworks GDSP, Arcadyan Mozart (ynezz),
            Zbt WG3526 (dangowrt)

Signed-off-by: Enrico Mioso <mrkiko.rs@gmail.com>
Signed-off-by: Petr Štetiar <ynezz@true.cz> [patch refresh, Mozart testing]
Signed-off-by: Daniel Golle <daniel@makrotopia.org> [rebased, tested on MT7621]
This commit is contained in:
Enrico Mioso 2025-05-21 17:21:08 +02:00 committed by Daniel Golle
parent c6c29d7b38
commit 2a32d215ba
84 changed files with 265 additions and 9966 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
package/boot/uboot-mediatek/Makefile
View file

@ -1,8 +1,8 @@
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_VERSION:=2025.01
PKG_HASH:=cdef7d507c93f1bbd9f015ea9bc21fa074268481405501945abc6f854d5b686f
PKG_VERSION:=2025.04
PKG_HASH:=439d3bef296effd54130be6a731c5b118be7fddd7fcc663ccbc5fb18294d8718
PKG_BUILD_DEPENDS:=!(TARGET_ramips||TARGET_mediatek_mt7623):arm-trusted-firmware-tools/host
UBOOT_USE_INTREE_DTC:=1

45
package/boot/uboot-mediatek/patches/060-01-clk-mediatek-mt7629-fix-parent-clock-of-some-top-clo.patch
View file

@ -1,45 +0,0 @@
From 6e45549f4dac42748d66462e04f940ef6737289d Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Tue, 17 Dec 2024 16:39:16 +0800
Subject: [PATCH 01/10] clk: mediatek: mt7629: fix parent clock of some top
clock muxes
According to the mt7629 programming guide, the CLK_TOP_F10M_REF_SEL
shares the same parent selection with CLK_TOP_IRRX_SEL, while the
present parent selection for CLK_TOP_F10M_REF_SEL is actually used
for CLK_TOP_SGMII_REF_1_SEL.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/clk/mediatek/clk-mt7629.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
--- a/drivers/clk/mediatek/clk-mt7629.c
+++ b/drivers/clk/mediatek/clk-mt7629.c
@@ -186,7 +186,7 @@ static const int pwm_parents[] = {
CLK_TOP_UNIVPLL2_D4
};
-static const int f10m_ref_parents[] = {
+static const int sgmii_ref_1_parents[] = {
CLK_XTAL,
CLK_TOP_SGMIIPLL_D2
};
@@ -369,7 +369,7 @@ static const struct mtk_composite top_mu
/* CLK_CFG_1 */
MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7),
- MUX_GATE(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15),
+ MUX_GATE(CLK_TOP_F10M_REF_SEL, irrx_parents, 0x50, 8, 1, 15),
MUX_GATE(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23),
MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31),
@@ -412,7 +412,7 @@ static const struct mtk_composite top_mu
/* CLK_CFG_8 */
MUX_GATE(CLK_TOP_CRYPTO_SEL, crypto_parents, 0xC0, 0, 3, 7),
- MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, f10m_ref_parents, 0xC0, 8, 1, 15),
+ MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, sgmii_ref_1_parents, 0xC0, 8, 1, 15),
MUX_GATE(CLK_TOP_10M_SEL, gpt10m_parents, 0xC0, 16, 1, 23),
};

28
package/boot/uboot-mediatek/patches/060-02-arm-dts-mt7629-fix-sgmii-clock-selection-for-etherne.patch
View file

@ -1,28 +0,0 @@
From ba365c3d23411620d86b5baf621c8f5a4000ab33 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Tue, 17 Dec 2024 16:39:20 +0800
Subject: [PATCH 02/10] arm: dts: mt7629: fix sgmii clock selection for
ethernet
Setup correct parent of clock CLK_TOP_SGMII_REF_1_SEL to allow
sgmiisys1 work correctly.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
arch/arm/dts/mt7629.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
--- a/arch/arm/dts/mt7629.dtsi
+++ b/arch/arm/dts/mt7629.dtsi
@@ -314,8 +314,10 @@
"sgmii2_cdr_ref", "sgmii2_cdr_fb",
"sgmii_ck", "eth2pll";
assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
- <&topckgen CLK_TOP_F10M_REF_SEL>;
+ <&topckgen CLK_TOP_F10M_REF_SEL>,
+ <&topckgen CLK_TOP_SGMII_REF_1_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
+ <&topckgen CLK_TOP_SYSPLL4_D16>,
<&topckgen CLK_TOP_SGMIIPLL_D2>;
power-domains = <&scpsys MT7629_POWER_DOMAIN_ETHSYS>;
resets = <&ethsys ETHSYS_FE_RST>;

64
package/boot/uboot-mediatek/patches/060-03-net-mediatek-use-correct-register-field-for-SGMII-sp.patch
View file

@ -1,64 +0,0 @@
From 0d4d8e6f47ef22ea6b3041b4c0cb27b4ed4bf188 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Tue, 17 Dec 2024 16:39:23 +0800
Subject: [PATCH 03/10] net: mediatek: use correct register field for SGMII
speed selection
The register field for SGMII speed selection is a 2-bit field with
value 0 for 1Gbps and 1 for 2.5Gbps (2/3 are reserved).
So it's necessary to set both bits instead of just setting/clearing
only the lower bit.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/net/mtk_eth.c | 12 ++++++------
drivers/net/mtk_eth.h | 3 ++-
2 files changed, 8 insertions(+), 7 deletions(-)
--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
@@ -835,8 +835,8 @@ static int mt7531_port_sgmii_init(struct
}
/* Set SGMII GEN2 speed(2.5G) */
- mt753x_reg_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port),
- SGMSYS_SPEED_2500, SGMSYS_SPEED_2500);
+ mt753x_reg_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), SGMSYS_SPEED_MASK,
+ FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500));
/* Disable SGMII AN */
mt753x_reg_rmw(priv, MT7531_PCS_CONTROL_1(port),
@@ -1281,8 +1281,7 @@ static int mtk_phy_probe(struct udevice
static void mtk_sgmii_an_init(struct mtk_eth_priv *priv)
{
/* Set SGMII GEN1 speed(1G) */
- clrsetbits_le32(priv->sgmii_base + priv->soc->ana_rgc3,
- SGMSYS_SPEED_2500, 0);
+ clrbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, SGMSYS_SPEED_MASK);
/* Enable SGMII AN */
setbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1,
@@ -1305,8 +1304,9 @@ static void mtk_sgmii_an_init(struct mtk
static void mtk_sgmii_force_init(struct mtk_eth_priv *priv)
{
/* Set SGMII GEN2 speed(2.5G) */
- setbits_le32(priv->sgmii_base + priv->soc->ana_rgc3,
- SGMSYS_SPEED_2500);
+ clrsetbits_le32(priv->sgmii_base + priv->soc->ana_rgc3,
+ SGMSYS_SPEED_MASK,
+ FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500));
/* Disable SGMII AN */
clrsetbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1,
--- a/drivers/net/mtk_eth.h
+++ b/drivers/net/mtk_eth.h
@@ -108,7 +108,8 @@ enum mkt_eth_capabilities {
#define SGMSYS_GEN2_SPEED 0x2028
#define SGMSYS_GEN2_SPEED_V2 0x128
-#define SGMSYS_SPEED_2500 BIT(2)
+#define SGMSYS_SPEED_MASK GENMASK(3, 2)
+#define SGMSYS_SPEED_2500 1
/* USXGMII subsystem config registers */
/* Register to control USXGMII XFI PLL digital */

78
package/boot/uboot-mediatek/patches/060-04-net-mediatek-correct-register-name-of-ethsys-syscfg1.patch
View file

@ -1,78 +0,0 @@
From 7562da9454c1a6eff3db3b41c183e03039e855e6 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Tue, 17 Dec 2024 16:39:27 +0800
Subject: [PATCH 04/10] net: mediatek: correct register name of ethsys syscfg1
The SYSCFG0 should be SYSCFG1 according to the programming guide.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/net/mtk_eth.c | 14 +++++++-------
drivers/net/mtk_eth.h | 12 ++++++------
2 files changed, 13 insertions(+), 13 deletions(-)
--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
@@ -1450,8 +1450,8 @@ static void mtk_mac_init(struct mtk_eth_
}
ge_mode = GE_MODE_RGMII;
- mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, SYSCFG0_SGMII_SEL_M,
- SYSCFG0_SGMII_SEL(priv->gmac_id));
+ mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, SYSCFG1_SGMII_SEL_M,
+ SYSCFG1_SGMII_SEL(priv->gmac_id));
if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
mtk_sgmii_an_init(priv);
else
@@ -1469,9 +1469,9 @@ static void mtk_mac_init(struct mtk_eth_
}
/* set the gmac to the right mode */
- mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG,
- SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id),
- ge_mode << SYSCFG0_GE_MODE_S(priv->gmac_id));
+ mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG,
+ SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id),
+ ge_mode << SYSCFG1_GE_MODE_S(priv->gmac_id));
if (priv->force_mode) {
mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
@@ -1527,8 +1527,8 @@ static void mtk_xmac_init(struct mtk_eth
}
/* Set GMAC to the correct mode */
- mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG,
- SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id),
+ mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG,
+ SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id),
0);
if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII &&
--- a/drivers/net/mtk_eth.h
+++ b/drivers/net/mtk_eth.h
@@ -65,11 +65,11 @@ enum mkt_eth_capabilities {
/* Ethernet subsystem registers */
-#define ETHSYS_SYSCFG0_REG 0x14
-#define SYSCFG0_GE_MODE_S(n) (12 + ((n) * 2))
-#define SYSCFG0_GE_MODE_M 0x3
-#define SYSCFG0_SGMII_SEL_M (0x3 << 8)
-#define SYSCFG0_SGMII_SEL(gmac) ((!(gmac)) ? BIT(9) : BIT(8))
+#define ETHSYS_SYSCFG1_REG 0x14
+#define SYSCFG1_GE_MODE_S(n) (12 + ((n) * 2))
+#define SYSCFG1_GE_MODE_M 0x3
+#define SYSCFG1_SGMII_SEL_M (0x3 << 8)
+#define SYSCFG1_SGMII_SEL(gmac) ((!(gmac)) ? BIT(9) : BIT(8))
#define ETHSYS_CLKCFG0_REG 0x2c
#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
@@ -84,7 +84,7 @@ enum mkt_eth_capabilities {
#define QPHY_SEL_MASK 0x3
#define SGMII_QPHY_SEL 0x2
-/* SYSCFG0_GE_MODE: GE Modes */
+/* SYSCFG1_GE_MODE: GE Modes */
#define GE_MODE_RGMII 0
#define GE_MODE_MII 1
#define GE_MODE_MII_PHY 2

90
package/boot/uboot-mediatek/patches/060-05-net-mediatek-fix-sgmii-selection-for-mt7622.patch
View file

@ -1,90 +0,0 @@
From 82f05bc48821f3709f22f3d1f6e45290547f74be Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Tue, 17 Dec 2024 16:39:41 +0800
Subject: [PATCH 05/10] net: mediatek: fix sgmii selection for mt7622
Unlike other platforms, mt7622 has only one SGMII and it can be
attached to either gmac1 or gmac2. So the register field of the
sgmii selection differs from other platforms as newer platforms can
control each sgmii individually.
This patch adds a new capability for mt7622 to handle this case.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/net/mtk_eth.c | 10 ++++++++--
drivers/net/mtk_eth.h | 8 ++++++--
2 files changed, 14 insertions(+), 4 deletions(-)
--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
@@ -1434,7 +1434,7 @@ static void mtk_usxgmii_an_init(struct m
static void mtk_mac_init(struct mtk_eth_priv *priv)
{
- int i, ge_mode = 0;
+ int i, sgmii_sel_mask = 0, ge_mode = 0;
u32 mcr;
switch (priv->phy_interface) {
@@ -1450,8 +1450,13 @@ static void mtk_mac_init(struct mtk_eth_
}
ge_mode = GE_MODE_RGMII;
- mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, SYSCFG1_SGMII_SEL_M,
+
+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_ETH_PATH_MT7622_SGMII))
+ sgmii_sel_mask = SYSCFG1_SGMII_SEL_M;
+
+ mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, sgmii_sel_mask,
SYSCFG1_SGMII_SEL(priv->gmac_id));
+
if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
mtk_sgmii_an_init(priv);
else
@@ -2112,6 +2117,7 @@ static const struct mtk_soc_data mt7623_
};
static const struct mtk_soc_data mt7622_data = {
+ .caps = MT7622_CAPS,
.ana_rgc3 = 0x2028,
.gdma_count = 2,
.pdma_base = PDMA_V1_BASE,
--- a/drivers/net/mtk_eth.h
+++ b/drivers/net/mtk_eth.h
@@ -23,6 +23,7 @@ enum mkt_eth_capabilities {
/* PATH BITS */
MTK_ETH_PATH_GMAC1_TRGMII_BIT,
MTK_ETH_PATH_GMAC2_SGMII_BIT,
+ MTK_ETH_PATH_MT7622_SGMII_BIT,
};
#define MTK_TRGMII BIT(MTK_TRGMII_BIT)
@@ -36,6 +37,7 @@ enum mkt_eth_capabilities {
#define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
#define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT)
+#define MTK_ETH_PATH_MT7622_SGMII BIT(MTK_ETH_PATH_MT7622_SGMII_BIT)
#define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
@@ -45,6 +47,8 @@ enum mkt_eth_capabilities {
#define MT7621_CAPS (MTK_GMAC1_TRGMII | MTK_TRGMII_MT7621_CLK)
+#define MT7622_CAPS (MTK_ETH_PATH_MT7622_SGMII)
+
#define MT7623_CAPS (MTK_GMAC1_TRGMII)
#define MT7981_CAPS (MTK_GMAC2_U3_QPHY | MTK_NETSYS_V2)
@@ -68,8 +72,8 @@ enum mkt_eth_capabilities {
#define ETHSYS_SYSCFG1_REG 0x14
#define SYSCFG1_GE_MODE_S(n) (12 + ((n) * 2))
#define SYSCFG1_GE_MODE_M 0x3
-#define SYSCFG1_SGMII_SEL_M (0x3 << 8)
-#define SYSCFG1_SGMII_SEL(gmac) ((!(gmac)) ? BIT(9) : BIT(8))
+#define SYSCFG1_SGMII_SEL_M GENMASK(9, 8)
+#define SYSCFG1_SGMII_SEL(gmac) BIT(9 - (gmac))
#define ETHSYS_CLKCFG0_REG 0x2c
#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)

73
package/boot/uboot-mediatek/patches/060-06-net-mediatek-fix-gmac2-usability-for-mt7629.patch
View file

@ -1,73 +0,0 @@
From d8d7e566545f836dd49611cafbf44eef56434e08 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Tue, 17 Dec 2024 16:39:46 +0800
Subject: [PATCH 06/10] net: mediatek: fix gmac2 usability for mt7629
MT7629 need extra setting for gmac2 to work. So additional
capability is added for mt7629 to handle this case.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/net/mtk_eth.c | 6 ++++++
drivers/net/mtk_eth.h | 7 +++++++
2 files changed, 13 insertions(+)
--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
@@ -1437,6 +1437,11 @@ static void mtk_mac_init(struct mtk_eth_
int i, sgmii_sel_mask = 0, ge_mode = 0;
u32 mcr;
+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_ETH_PATH_MT7629_GMAC2)) {
+ mtk_infra_rmw(priv, MT7629_INFRA_MISC2_REG,
+ INFRA_MISC2_BONDING_OPTION, priv->gmac_id);
+ }
+
switch (priv->phy_interface) {
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII:
@@ -2101,6 +2106,7 @@ static const struct mtk_soc_data mt7981_
};
static const struct mtk_soc_data mt7629_data = {
+ .caps = MT7629_CAPS,
.ana_rgc3 = 0x128,
.gdma_count = 2,
.pdma_base = PDMA_V1_BASE,
--- a/drivers/net/mtk_eth.h
+++ b/drivers/net/mtk_eth.h
@@ -24,6 +24,7 @@ enum mkt_eth_capabilities {
MTK_ETH_PATH_GMAC1_TRGMII_BIT,
MTK_ETH_PATH_GMAC2_SGMII_BIT,
MTK_ETH_PATH_MT7622_SGMII_BIT,
+ MTK_ETH_PATH_MT7629_GMAC2_BIT,
};
#define MTK_TRGMII BIT(MTK_TRGMII_BIT)
@@ -38,6 +39,7 @@ enum mkt_eth_capabilities {
#define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT)
#define MTK_ETH_PATH_MT7622_SGMII BIT(MTK_ETH_PATH_MT7622_SGMII_BIT)
+#define MTK_ETH_PATH_MT7629_GMAC2 BIT(MTK_ETH_PATH_MT7629_GMAC2_BIT)
#define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
@@ -51,6 +53,8 @@ enum mkt_eth_capabilities {
#define MT7623_CAPS (MTK_GMAC1_TRGMII)
+#define MT7629_CAPS (MTK_ETH_PATH_MT7629_GMAC2 | MTK_INFRA)
+
#define MT7981_CAPS (MTK_GMAC2_U3_QPHY | MTK_NETSYS_V2)
#define MT7986_CAPS (MTK_NETSYS_V2)
@@ -88,6 +92,9 @@ enum mkt_eth_capabilities {
#define QPHY_SEL_MASK 0x3
#define SGMII_QPHY_SEL 0x2
+#define MT7629_INFRA_MISC2_REG 0x70c
+#define INFRA_MISC2_BONDING_OPTION GENMASK(15, 0)
+
/* SYSCFG1_GE_MODE: GE Modes */
#define GE_MODE_RGMII 0
#define GE_MODE_MII 1

147
package/boot/uboot-mediatek/patches/060-07-net-mediatek-add-support-for-10GBASE-R.patch
View file

@ -1,147 +0,0 @@
From ad0c47109e4c9f6297aa247d8bbf7131438bc435 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Tue, 17 Dec 2024 16:39:50 +0800
Subject: [PATCH 07/10] net: mediatek: add support for 10GBASE-R
This patch adds support for 10GBASE-R interface mode
Signed-off-by: Bo-Cun Chen <bc-bocun.chen@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/net/mtk_eth.c | 83 +++++++++++++++++++++++++++++++++++++++++--
1 file changed, 81 insertions(+), 2 deletions(-)
--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
@@ -1246,6 +1246,7 @@ static int mtk_phy_start(struct mtk_eth_
if (!priv->force_mode) {
if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
+ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER ||
priv->phy_interface == PHY_INTERFACE_MODE_XGMII)
mtk_xphy_link_adjust(priv);
else
@@ -1425,6 +1426,71 @@ static void mtk_usxgmii_setup_phya_an_10
udelay(400);
}
+static void mtk_usxgmii_setup_phya_force_10000(struct mtk_eth_priv *priv)
+{
+ regmap_write(priv->usxgmii_regmap, 0x810, 0x000FFE6C);
+ regmap_write(priv->usxgmii_regmap, 0x818, 0x07B1EC7B);
+ regmap_write(priv->usxgmii_regmap, 0x80C, 0xB0000000);
+ ndelay(1020);
+ regmap_write(priv->usxgmii_regmap, 0x80C, 0x90000000);
+ ndelay(1020);
+
+ regmap_write(priv->xfi_pextp_regmap, 0x9024, 0x00C9071C);
+ regmap_write(priv->xfi_pextp_regmap, 0x2020, 0xAA8585AA);
+ regmap_write(priv->xfi_pextp_regmap, 0x2030, 0x0C020707);
+ regmap_write(priv->xfi_pextp_regmap, 0x2034, 0x0E050F0F);
+ regmap_write(priv->xfi_pextp_regmap, 0x2040, 0x00140032);
+ regmap_write(priv->xfi_pextp_regmap, 0x50F0, 0x00C014AA);
+ regmap_write(priv->xfi_pextp_regmap, 0x50E0, 0x3777C12B);
+ regmap_write(priv->xfi_pextp_regmap, 0x506C, 0x005F9CFF);
+ regmap_write(priv->xfi_pextp_regmap, 0x5070, 0x9D9DFAFA);
+ regmap_write(priv->xfi_pextp_regmap, 0x5074, 0x27273F3F);
+ regmap_write(priv->xfi_pextp_regmap, 0x5078, 0xA7883C68);
+ regmap_write(priv->xfi_pextp_regmap, 0x507C, 0x11661166);
+ regmap_write(priv->xfi_pextp_regmap, 0x5080, 0x0E000AAF);
+ regmap_write(priv->xfi_pextp_regmap, 0x5084, 0x08080D0D);
+ regmap_write(priv->xfi_pextp_regmap, 0x5088, 0x02030909);
+ regmap_write(priv->xfi_pextp_regmap, 0x50E4, 0x0C0C0000);
+ regmap_write(priv->xfi_pextp_regmap, 0x50E8, 0x04040000);
+ regmap_write(priv->xfi_pextp_regmap, 0x50EC, 0x0F0F0C06);
+ regmap_write(priv->xfi_pextp_regmap, 0x50A8, 0x506E8C8C);
+ regmap_write(priv->xfi_pextp_regmap, 0x6004, 0x18190000);
+ regmap_write(priv->xfi_pextp_regmap, 0x00F8, 0x01423342);
+ regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F20);
+ regmap_write(priv->xfi_pextp_regmap, 0x0030, 0x00050C00);
+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x02002800);
+ ndelay(1020);
+ regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000020);
+ regmap_write(priv->xfi_pextp_regmap, 0x3028, 0x00008A01);
+ regmap_write(priv->xfi_pextp_regmap, 0x302C, 0x0000A884);
+ regmap_write(priv->xfi_pextp_regmap, 0x3024, 0x00083002);
+ regmap_write(priv->xfi_pextp_regmap, 0x3010, 0x00022220);
+ regmap_write(priv->xfi_pextp_regmap, 0x5064, 0x0F020A01);
+ regmap_write(priv->xfi_pextp_regmap, 0x50B4, 0x06100600);
+ regmap_write(priv->xfi_pextp_regmap, 0x3048, 0x47684100);
+ regmap_write(priv->xfi_pextp_regmap, 0x3050, 0x00000000);
+ regmap_write(priv->xfi_pextp_regmap, 0x3054, 0x00000000);
+ regmap_write(priv->xfi_pextp_regmap, 0x306C, 0x00000F00);
+ if (priv->gmac_id == 2)
+ regmap_write(priv->xfi_pextp_regmap, 0xA008, 0x0007B400);
+ regmap_write(priv->xfi_pextp_regmap, 0xA060, 0x00040000);
+ regmap_write(priv->xfi_pextp_regmap, 0x90D0, 0x00000001);
+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200E800);
+ udelay(150);
+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C111);
+ ndelay(1020);
+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C101);
+ udelay(15);
+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C111);
+ ndelay(1020);
+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C101);
+ udelay(100);
+ regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000030);
+ regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F00);
+ regmap_write(priv->xfi_pextp_regmap, 0x3040, 0x30000000);
+ udelay(400);
+}
+
static void mtk_usxgmii_an_init(struct mtk_eth_priv *priv)
{
mtk_xfi_pll_enable(priv);
@@ -1432,6 +1498,13 @@ static void mtk_usxgmii_an_init(struct m
mtk_usxgmii_setup_phya_an_10000(priv);
}
+static void mtk_10gbaser_init(struct mtk_eth_priv *priv)
+{
+ mtk_xfi_pll_enable(priv);
+ mtk_usxgmii_reset(priv);
+ mtk_usxgmii_setup_phya_force_10000(priv);
+}
+
static void mtk_mac_init(struct mtk_eth_priv *priv)
{
int i, sgmii_sel_mask = 0, ge_mode = 0;
@@ -1532,6 +1605,9 @@ static void mtk_xmac_init(struct mtk_eth
case PHY_INTERFACE_MODE_USXGMII:
mtk_usxgmii_an_init(priv);
break;
+ case PHY_INTERFACE_MODE_10GBASER:
+ mtk_10gbaser_init(priv);
+ break;
default:
break;
}
@@ -1541,7 +1617,8 @@ static void mtk_xmac_init(struct mtk_eth
SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id),
0);
- if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII &&
+ if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
+ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) &&
priv->gmac_id == 1) {
mtk_infra_rmw(priv, TOPMISC_NETSYS_PCS_MUX,
NETSYS_PCS_MUX_MASK, MUX_G2_USXGMII_SEL);
@@ -1843,6 +1920,7 @@ static int mtk_eth_probe(struct udevice
/* Set MAC mode */
if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
+ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER ||
priv->phy_interface == PHY_INTERFACE_MODE_XGMII)
mtk_xmac_init(priv);
else
@@ -1977,7 +2055,8 @@ static int mtk_eth_of_to_plat(struct ude
/* Upstream linux use mediatek,pnswap instead of pn_swap */
priv->pn_swap = ofnode_read_bool(args.node, "pn_swap") ||
ofnode_read_bool(args.node, "mediatek,pnswap");
- } else if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII) {
+ } else if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
+ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) {
/* get corresponding usxgmii phandle */
ret = dev_read_phandle_with_args(dev, "mediatek,usxgmiisys",
NULL, 0, 0, &args);

144
package/boot/uboot-mediatek/patches/060-08-net-mediatek-make-sgmii-usxgmii-optional.patch
View file

@ -1,144 +0,0 @@
From 5ac929fd1ab1d0dc77b9167952aea7cafdb8619f Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Tue, 17 Dec 2024 16:39:55 +0800
Subject: [PATCH 08/10] net: mediatek: make sgmii/usxgmii optional
Not all platforms supports sgmii and/or usxgmii. So we add Kconfig
options for these features and enable them only for supported
platforms.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/net/Kconfig | 12 ++++++++++++
drivers/net/mtk_eth.c | 39 +++++++++++++++++++++++++++++----------
2 files changed, 41 insertions(+), 10 deletions(-)
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -975,6 +975,18 @@ config MEDIATEK_ETH
This Driver support MediaTek Ethernet GMAC
Say Y to enable support for the MediaTek Ethernet GMAC.
+if MEDIATEK_ETH
+
+config MTK_ETH_SGMII
+ bool
+ default y if ARCH_MEDIATEK && !TARGET_MT7623
+
+config MTK_ETH_XGMII
+ bool
+ default y if TARGET_MT7987 || TARGET_MT7988
+
+endif # MEDIATEK_ETH
+
config HIFEMAC_ETH
bool "HiSilicon Fast Ethernet Controller"
select DM_CLK
--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
@@ -1505,7 +1505,7 @@ static void mtk_10gbaser_init(struct mtk
mtk_usxgmii_setup_phya_force_10000(priv);
}
-static void mtk_mac_init(struct mtk_eth_priv *priv)
+static int mtk_mac_init(struct mtk_eth_priv *priv)
{
int i, sgmii_sel_mask = 0, ge_mode = 0;
u32 mcr;
@@ -1522,13 +1522,16 @@ static void mtk_mac_init(struct mtk_eth_
break;
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_2500BASEX:
+ if (!IS_ENABLED(CONFIG_MTK_ETH_SGMII)) {
+ printf("Error: SGMII is not supported on this platform\n");
+ return -ENOTSUPP;
+ }
+
if (MTK_HAS_CAPS(priv->soc->caps, MTK_GMAC2_U3_QPHY)) {
mtk_infra_rmw(priv, USB_PHY_SWITCH_REG, QPHY_SEL_MASK,
SGMII_QPHY_SEL);
}
- ge_mode = GE_MODE_RGMII;
-
if (MTK_HAS_CAPS(priv->soc->caps, MTK_ETH_PATH_MT7622_SGMII))
sgmii_sel_mask = SYSCFG1_SGMII_SEL_M;
@@ -1539,6 +1542,8 @@ static void mtk_mac_init(struct mtk_eth_
mtk_sgmii_an_init(priv);
else
mtk_sgmii_force_init(priv);
+
+ ge_mode = GE_MODE_RGMII;
break;
case PHY_INTERFACE_MODE_MII:
case PHY_INTERFACE_MODE_GMII:
@@ -1595,12 +1600,19 @@ static void mtk_mac_init(struct mtk_eth_
RX_RST | RXC_DQSISEL);
mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, RX_RST, 0);
}
+
+ return 0;
}
-static void mtk_xmac_init(struct mtk_eth_priv *priv)
+static int mtk_xmac_init(struct mtk_eth_priv *priv)
{
u32 force_link = 0;
+ if (!IS_ENABLED(CONFIG_MTK_ETH_XGMII)) {
+ printf("Error: 10Gb interface is not supported on this platform\n");
+ return -ENOTSUPP;
+ }
+
switch (priv->phy_interface) {
case PHY_INTERFACE_MODE_USXGMII:
mtk_usxgmii_an_init(priv);
@@ -1633,6 +1645,8 @@ static void mtk_xmac_init(struct mtk_eth
/* Force GMAC link down */
mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), FORCE_MODE);
+
+ return 0;
}
static void mtk_eth_fifo_init(struct mtk_eth_priv *priv)
@@ -1922,9 +1936,12 @@ static int mtk_eth_probe(struct udevice
if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
priv->phy_interface == PHY_INTERFACE_MODE_10GBASER ||
priv->phy_interface == PHY_INTERFACE_MODE_XGMII)
- mtk_xmac_init(priv);
+ ret = mtk_xmac_init(priv);
else
- mtk_mac_init(priv);
+ ret = mtk_mac_init(priv);
+
+ if (ret)
+ return ret;
/* Probe phy if switch is not specified */
if (priv->sw == SW_NONE)
@@ -2032,8 +2049,9 @@ static int mtk_eth_of_to_plat(struct ude
}
}
- if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII ||
- priv->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
+ if ((priv->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+ priv->phy_interface == PHY_INTERFACE_MODE_2500BASEX) &&
+ IS_ENABLED(CONFIG_MTK_ETH_SGMII)) {
/* get corresponding sgmii phandle */
ret = dev_read_phandle_with_args(dev, "mediatek,sgmiisys",
NULL, 0, 0, &args);
@@ -2055,8 +2073,9 @@ static int mtk_eth_of_to_plat(struct ude
/* Upstream linux use mediatek,pnswap instead of pn_swap */
priv->pn_swap = ofnode_read_bool(args.node, "pn_swap") ||
ofnode_read_bool(args.node, "mediatek,pnswap");
- } else if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
- priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) {
+ } else if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
+ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) &&
+ IS_ENABLED(CONFIG_MTK_ETH_XGMII)) {
/* get corresponding usxgmii phandle */
ret = dev_read_phandle_with_args(dev, "mediatek,usxgmiisys",
NULL, 0, 0, &args);

36
package/boot/uboot-mediatek/patches/060-09-net-mediatek-don-t-enable-GDMA-cpu-bridge-unconditio.patch
View file

@ -1,36 +0,0 @@
From b9dfb5636bc5eb9b783b88b8388dc7d1f41d6498 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Tue, 17 Dec 2024 16:39:59 +0800
Subject: [PATCH 09/10] net: mediatek: don't enable GDMA cpu bridge
unconditionally for NETSYSv3
Enable GDMA cpu bridge only when 10Gb interface is enabled for GMAC other
than GMAC0, or when MT7988 internal switch is used.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/net/mtk_eth.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
@@ -1762,10 +1762,16 @@ static int mtk_eth_start(struct udevice
if (priv->sw == SW_MT7988 && priv->gmac_id == 0) {
mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG,
GDMA_BRIDGE_TO_CPU);
- }
- mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG,
- GDMA_CPU_BRIDGE_EN);
+ mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG,
+ GDMA_CPU_BRIDGE_EN);
+ } else if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
+ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER ||
+ priv->phy_interface == PHY_INTERFACE_MODE_XGMII) &&
+ priv->gmac_id != 0) {
+ mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG,
+ GDMA_CPU_BRIDGE_EN);
+ }
}
udelay(500);

37
package/boot/uboot-mediatek/patches/060-10-net-mediatek-fix-usability-with-wget-command.patch
View file

@ -1,37 +0,0 @@
From c949686e558e00cbb8c38f7c060701006d70cea8 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Tue, 17 Dec 2024 16:40:03 +0800
Subject: [PATCH 10/10] net: mediatek: fix usability with wget command
The wget command currently cannot work correctly with mtk_eth driver.
This patch fixed this by increase DMA ring size and invalidate ring data
after use.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/net/mtk_eth.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
@@ -29,8 +29,8 @@
#include "mtk_eth.h"
-#define NUM_TX_DESC 24
-#define NUM_RX_DESC 24
+#define NUM_TX_DESC 32
+#define NUM_RX_DESC 32
#define TX_TOTAL_BUF_SIZE (NUM_TX_DESC * PKTSIZE_ALIGN)
#define RX_TOTAL_BUF_SIZE (NUM_RX_DESC * PKTSIZE_ALIGN)
#define TOTAL_PKT_BUF_SIZE (TX_TOTAL_BUF_SIZE + RX_TOTAL_BUF_SIZE)
@@ -1897,6 +1897,9 @@ static int mtk_eth_free_pkt(struct udevi
rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size;
+ invalidate_dcache_range((ulong)rxd->rxd1,
+ (ulong)rxd->rxd1 + PKTSIZE_ALIGN);
+
if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN);

6311
package/boot/uboot-mediatek/patches/061-01-net-mediatek-split-ethernet-switch-code-from-mtk_eth.patch
View file

File diff suppressed because it is too large Load diff

63
package/boot/uboot-mediatek/patches/061-02-net-mediatek-add-support-for-MediaTek-MT7987-SoC.patch
View file

@ -1,63 +0,0 @@
From fe106f2093733b8bd61946372945dfea552b4755 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 10 Jan 2025 16:41:20 +0800
Subject: [PATCH 2/3] net: mediatek: add support for MediaTek MT7987 SoC
This patch adds support for MediaTek MT7987.
MT7987 features MediaTek NETSYS v3, similar to MT7988, features three GMACs
which support 2.5Gb HSGMII. One 2.5Gb PHY is also embedded an can be
connected to a dedicated GMAC.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/net/mtk_eth/Kconfig | 4 ++--
drivers/net/mtk_eth/mtk_eth.c | 10 ++++++++++
2 files changed, 12 insertions(+), 2 deletions(-)
--- a/drivers/net/mtk_eth/Kconfig
+++ b/drivers/net/mtk_eth/Kconfig
@@ -16,7 +16,7 @@ config MTK_ETH_SGMII
config MTK_ETH_XGMII
bool
- default y if TARGET_MT7988
+ default y if TARGET_MT7987 || TARGET_MT7988
config MTK_ETH_SWITCH_MT7530
bool "Support for MediaTek MT7530 ethernet switch"
@@ -25,7 +25,7 @@ config MTK_ETH_SWITCH_MT7530
config MTK_ETH_SWITCH_MT7531
bool "Support for MediaTek MT7531 ethernet switch"
default y if TARGET_MT7622 || TARGET_MT7629 || TARGET_MT7981 || \
- TARGET_MT7986
+ TARGET_MT7986 || TARGET_MT7987
config MTK_ETH_SWITCH_MT7988
bool "Support for MediaTek MT7988 built-in ethernet switch"
--- a/drivers/net/mtk_eth/mtk_eth.c
+++ b/drivers/net/mtk_eth/mtk_eth.c
@@ -1477,6 +1477,15 @@ static const struct mtk_soc_data mt7988_
.rxd_size = sizeof(struct mtk_rx_dma_v2),
};
+static const struct mtk_soc_data mt7987_data = {
+ .caps = MT7987_CAPS,
+ .ana_rgc3 = 0x128,
+ .gdma_count = 3,
+ .pdma_base = PDMA_V3_BASE,
+ .txd_size = sizeof(struct mtk_tx_dma_v2),
+ .rxd_size = sizeof(struct mtk_rx_dma_v2),
+};
+
static const struct mtk_soc_data mt7986_data = {
.caps = MT7986_CAPS,
.ana_rgc3 = 0x128,
@@ -1531,6 +1540,7 @@ static const struct mtk_soc_data mt7621_
static const struct udevice_id mtk_eth_ids[] = {
{ .compatible = "mediatek,mt7988-eth", .data = (ulong)&mt7988_data },
+ { .compatible = "mediatek,mt7987-eth", .data = (ulong)&mt7987_data },
{ .compatible = "mediatek,mt7986-eth", .data = (ulong)&mt7986_data },
{ .compatible = "mediatek,mt7981-eth", .data = (ulong)&mt7981_data },
{ .compatible = "mediatek,mt7629-eth", .data = (ulong)&mt7629_data },

1133
package/boot/uboot-mediatek/patches/061-03-net-mediatek-add-support-for-Airoha-AN8855-ethernet-.patch
View file

File diff suppressed because it is too large Load diff

26
package/boot/uboot-mediatek/patches/070-01-board-mediatek-mt7622-remove-board_late_init.patch
View file

@ -1,26 +0,0 @@
From 92090b92fab207250d5b8d5a4a36aa34f5a91f19 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 17 Jan 2025 17:16:33 +0800
Subject: [PATCH 01/15] board: mediatek: mt7622: remove board_late_init
The function board_late_init defined for mt7622 is useless now. Just
remove it.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
board/mediatek/mt7622/mt7622_rfb.c | 7 -------
1 file changed, 7 deletions(-)
--- a/board/mediatek/mt7622/mt7622_rfb.c
+++ b/board/mediatek/mt7622/mt7622_rfb.c
@@ -15,10 +15,3 @@ int board_init(void)
{
return 0;
}
-
-int board_late_init(void)
-{
- gd->env_valid = 1; //to load environment variable from persistent store
- env_relocate();
- return 0;
-}

48
package/boot/uboot-mediatek/patches/070-02-clk-mediatek-fix-uninitialized-fields-issue-in-INFRA.patch
View file

@ -1,48 +0,0 @@
From b033dfb21df8ae876ec69d84bc8c5fafd7aa8ced Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 17 Jan 2025 17:16:38 +0800
Subject: [PATCH 02/15] clk: mediatek: fix uninitialized fields issue in
INFRA_MUX struct
This patch adds missing initialization of fields in INFRA_MUX struct
which caused uart broken after any other infra mux being enabled by
'clk_prepare_enable'
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/clk/mediatek/clk-mt7981.c | 1 +
drivers/clk/mediatek/clk-mt7986.c | 1 +
drivers/clk/mediatek/clk-mt7988.c | 1 +
3 files changed, 3 insertions(+)
--- a/drivers/clk/mediatek/clk-mt7981.c
+++ b/drivers/clk/mediatek/clk-mt7981.c
@@ -359,6 +359,7 @@ static const struct mtk_parent infra_pci
.id = _id, .mux_reg = (_reg) + 0x8, \
.mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \
.mux_shift = _shift, .mux_mask = BIT(_width) - 1, \
+ .gate_shift = -1, .upd_shift = -1, \
.parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \
.flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \
}
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -366,6 +366,7 @@ static const struct mtk_parent infra_pci
.id = _id, .mux_reg = (_reg) + 0x8, \
.mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \
.mux_shift = _shift, .mux_mask = BIT(_width) - 1, \
+ .gate_shift = -1, .upd_shift = -1, \
.parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \
.flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \
}
--- a/drivers/clk/mediatek/clk-mt7988.c
+++ b/drivers/clk/mediatek/clk-mt7988.c
@@ -485,6 +485,7 @@ static const int infra_pcie_gfmux_tl_ck_
.id = _id, .mux_reg = _reg + 0x8, .mux_set_reg = _reg + 0x0, \
.mux_clr_reg = _reg + 0x4, .mux_shift = _shift, \
.mux_mask = BIT(_width) - 1, .parent = _parents, \
+ .gate_shift = -1, .upd_shift = -1, \
.num_parents = ARRAY_SIZE(_parents), \
.flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_TOPCKGEN, \
}

25
package/boot/uboot-mediatek/patches/070-03-configs-mt7629-move-image-load-address-to-0x42000000.patch
View file

@ -1,25 +0,0 @@
From 7958b41b8c6a15c3c993affd2091f8c921b6a8a1 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 17 Jan 2025 17:17:38 +0800
Subject: [PATCH 03/15] configs: mt7629: move image load address to 0x42000000
Update the image load address to ensure it matches the mt7629 NOR
controller's DMA alignment requirements.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
configs/mt7629_rfb_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/configs/mt7629_rfb_defconfig
+++ b/configs/mt7629_rfb_defconfig
@@ -18,7 +18,7 @@ CONFIG_SPL_STACK=0x106000
CONFIG_SPL_TEXT_BASE=0x201000
CONFIG_SPL_STACK_R=y
CONFIG_SYS_BOOTM_LEN=0x4000000
-CONFIG_SYS_LOAD_ADDR=0x42007f1c
+CONFIG_SYS_LOAD_ADDR=0x42000000
CONFIG_SPL_PAYLOAD="u-boot-lzma.img"
CONFIG_BUILD_TARGET="u-boot-mtk.bin"
CONFIG_SPL_IMAGE="spl/u-boot-spl-mtk.bin"

24
package/boot/uboot-mediatek/patches/070-04-configs-mt7988-move-image-load-address-to-0x44000000.patch
View file

@ -1,24 +0,0 @@
From c7a3761ddfce2bd56ad319a254d5269cb26fa18f Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 17 Jan 2025 17:17:44 +0800
Subject: [PATCH 04/15] configs: mt7988: move image load address to 0x44000000
This patch sets mt7988 image load address to 0x44000000 to support loading
larger images.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
configs/mt7988_rfb_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/configs/mt7988_rfb_defconfig
+++ b/configs/mt7988_rfb_defconfig
@@ -7,7 +7,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEFAULT_DEVICE_TREE="mt7988-rfb"
CONFIG_TARGET_MT7988=y
-CONFIG_SYS_LOAD_ADDR=0x46000000
+CONFIG_SYS_LOAD_ADDR=0x44000000
CONFIG_DEBUG_UART_BASE=0x11000000
CONFIG_DEBUG_UART_CLOCK=40000000
CONFIG_DEBUG_UART=y

23
package/boot/uboot-mediatek/patches/070-05-spi-mtk_spim-add-support-to-use-DT-live-tree.patch
View file

@ -1,23 +0,0 @@
From a2c2ac46ca4c4ef5fe043e584cf867a20e93226d Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 17 Jan 2025 17:17:51 +0800
Subject: [PATCH 05/15] spi: mtk_spim: add support to use DT live tree
Change devfdt_get_addr_ptr to dev_read_addr_ptr to support DT live tree.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/spi/mtk_spim.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/spi/mtk_spim.c
+++ b/drivers/spi/mtk_spim.c
@@ -648,7 +648,7 @@ static int mtk_spim_probe(struct udevice
struct mtk_spim_priv *priv = dev_get_priv(dev);
int ret;
- priv->base = devfdt_get_addr_ptr(dev);
+ priv->base = dev_read_addr_ptr(dev);
if (!priv->base)
return -EINVAL;

27
package/boot/uboot-mediatek/patches/070-06-spi-mtk_spim-check-slave-device-mode-in-spi-mem-s-su.patch
View file

@ -1,27 +0,0 @@
From 7725d4ba16577b74567f7cffb2faffa8bdc5ad61 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 17 Jan 2025 17:17:55 +0800
Subject: [PATCH 06/15] spi: mtk_spim: check slave device mode in spi-mem's
supports_op
Call spi_mem_default_supports_op() in supports_op to honor the
slave's supported single/dual/quad mode settings.
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/spi/mtk_spim.c | 3 +++
1 file changed, 3 insertions(+)
--- a/drivers/spi/mtk_spim.c
+++ b/drivers/spi/mtk_spim.c
@@ -359,6 +359,9 @@ static bool mtk_spim_supports_op(struct
struct udevice *bus = dev_get_parent(slave->dev);
struct mtk_spim_priv *priv = dev_get_priv(bus);
+ if (!spi_mem_default_supports_op(slave, op))
+ return false;
+
if (op->cmd.buswidth == 0 || op->cmd.buswidth > 4 ||
op->addr.buswidth > 4 || op->dummy.buswidth > 4 ||
op->data.buswidth > 4)

96
package/boot/uboot-mediatek/patches/070-07-arm-dts-mediatek-add-quad-mode-capabilities-for-SPI-.patch
View file

@ -1,96 +0,0 @@
From c7a602028669f4409538c3ce0a63c4054d0f2b7a Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 17 Jan 2025 17:18:01 +0800
Subject: [PATCH 07/15] arm: dts: mediatek: add quad mode capabilities for SPI
flashes
Explicitly add quad mode capabilities or the SPI controller may
start transfer in single mode.
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
arch/arm/dts/mt7981-rfb.dts | 4 ++++
arch/arm/dts/mt7986a-rfb.dts | 4 ++++
arch/arm/dts/mt7986b-rfb.dts | 4 ++++
arch/arm/dts/mt7988-rfb.dts | 4 ++++
4 files changed, 16 insertions(+)
--- a/arch/arm/dts/mt7981-rfb.dts
+++ b/arch/arm/dts/mt7981-rfb.dts
@@ -143,6 +143,8 @@
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <52000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
};
};
@@ -164,6 +166,8 @@
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <52000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
};
};
--- a/arch/arm/dts/mt7986a-rfb.dts
+++ b/arch/arm/dts/mt7986a-rfb.dts
@@ -190,12 +190,16 @@
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <52000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
};
spi_nand@1 {
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <52000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
};
};
--- a/arch/arm/dts/mt7986b-rfb.dts
+++ b/arch/arm/dts/mt7986b-rfb.dts
@@ -177,12 +177,16 @@
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <52000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
};
spi_nand@1 {
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <52000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
};
};
--- a/arch/arm/dts/mt7988-rfb.dts
+++ b/arch/arm/dts/mt7988-rfb.dts
@@ -144,6 +144,8 @@
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <52000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
};
};
@@ -165,6 +167,8 @@
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <52000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
};
};

98
package/boot/uboot-mediatek/patches/070-08-pwm-mediatek-add-pwm3-support-for-mt7981.patch
View file

@ -1,98 +0,0 @@
From 7071ba2658ef6175183cc5dc85819293811490b3 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 17 Jan 2025 17:18:06 +0800
Subject: [PATCH 08/15] pwm: mediatek: add pwm3 support for mt7981
This patch adds pwm channel 2 (pwm3) support for mt7981
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
arch/arm/dts/mt7981-emmc-rfb.dts | 8 ++++++++
arch/arm/dts/mt7981-rfb.dts | 8 ++++++++
arch/arm/dts/mt7981-sd-rfb.dts | 8 ++++++++
arch/arm/dts/mt7981.dtsi | 10 ++++++++--
drivers/pwm/pwm-mtk.c | 2 +-
5 files changed, 33 insertions(+), 3 deletions(-)
--- a/arch/arm/dts/mt7981-emmc-rfb.dts
+++ b/arch/arm/dts/mt7981-emmc-rfb.dts
@@ -95,6 +95,14 @@
};
};
+ /* pin13 as pwm0, pin15 as pwm1, pin7 as pwm2 */
+ three_pwm_pins_1: three-pwm-pins {
+ mux {
+ function = "pwm";
+ groups = "pwm0_0", "pwm1_1", "pwm2";
+ };
+ };
+
mmc0_pins_default: mmc0default {
mux {
function = "flash";
--- a/arch/arm/dts/mt7981-rfb.dts
+++ b/arch/arm/dts/mt7981-rfb.dts
@@ -123,6 +123,14 @@
groups = "pwm0_1", "pwm1_0", "pwm2";
};
};
+
+ /* pin13 as pwm0, pin15 as pwm1, pin7 as pwm2 */
+ three_pwm_pins_1: three-pwm-pins {
+ mux {
+ function = "pwm";
+ groups = "pwm0_0", "pwm1_1", "pwm2";
+ };
+ };
};
&spi0 {
--- a/arch/arm/dts/mt7981-sd-rfb.dts
+++ b/arch/arm/dts/mt7981-sd-rfb.dts
@@ -95,6 +95,14 @@
};
};
+ /* pin13 as pwm0, pin15 as pwm1, pin7 as pwm2 */
+ three_pwm_pins_1: three-pwm-pins {
+ mux {
+ function = "pwm";
+ groups = "pwm0_0", "pwm1_1", "pwm2";
+ };
+ };
+
mmc0_pins_default: mmc0default {
mux {
function = "flash";
--- a/arch/arm/dts/mt7981.dtsi
+++ b/arch/arm/dts/mt7981.dtsi
@@ -137,8 +137,14 @@
<&infracfg CLK_INFRA_PWM1_CK>,
<&infracfg CLK_INFRA_PWM2_CK>,
<&infracfg CLK_INFRA_PWM3_CK>;
- assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>;
+ assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>,
+ <&infracfg CLK_INFRA_PWM1_SEL>,
+ <&infracfg CLK_INFRA_PWM2_SEL>,
+ <&infracfg CLK_INFRA_PWM3_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
+ <&topckgen CLK_TOP_PWM_SEL>,
+ <&topckgen CLK_TOP_PWM_SEL>,
+ <&topckgen CLK_TOP_PWM_SEL>;
clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
status = "disabled";
};
--- a/drivers/pwm/pwm-mtk.c
+++ b/drivers/pwm/pwm-mtk.c
@@ -192,7 +192,7 @@ static const struct mtk_pwm_soc mt7629_d
};
static const struct mtk_pwm_soc mt7981_data = {
- .num_pwms = 2,
+ .num_pwms = 3,
.pwm45_fixup = false,
.reg_ver = PWM_REG_V2,
};

61
package/boot/uboot-mediatek/patches/070-09-pci-mediatek-add-support-for-multiple-ports-in-media.patch
View file

@ -1,61 +0,0 @@
From dfbadb86b3bc43c004671ab6eb46ee160a192e98 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 17 Jan 2025 17:18:11 +0800
Subject: [PATCH 09/15] pci: mediatek: add support for multiple ports in
mediatek pcie gen3 driver
One MediaTek PCIe Gen3 controller has only one port, where PCI bus 0
on this port represents the controller itself and bus 1 represents
the external PCIe device.
If multiple PCIe controllers are probed in U-Boot, U-Boot will use
bus numbers greater than 2 as input parameters. Therefore, we should
convert the BDF bus number to either 0 or 1 by subtracting the
offset by controller->seq_.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/pci/pcie_mediatek_gen3.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
--- a/drivers/pci/pcie_mediatek_gen3.c
+++ b/drivers/pci/pcie_mediatek_gen3.c
@@ -83,6 +83,28 @@ struct mtk_pcie {
struct phy phy;
};
+static pci_dev_t convert_bdf(const struct udevice *controller, pci_dev_t bdf)
+{
+ int bdfs[3];
+
+ bdfs[0] = PCI_BUS(bdf);
+ bdfs[1] = PCI_DEV(bdf);
+ bdfs[2] = PCI_FUNC(bdf);
+
+ /*
+ * One MediaTek PCIe Gen3 controller has only one port, where PCI bus 0 on
+ * this port represents the controller itself and bus 1 represents the
+ * external PCIe device. If multiple PCIe controllers are probed in U-Boot,
+ * U-Boot will use bus numbers greater than 2 as input parameters. Therefore,
+ * we should convert the BDF bus number to either 0 or 1 by subtracting the
+ * offset by controller->seq_
+ */
+
+ bdfs[0] = bdfs[0] - controller->seq_;
+
+ return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
+}
+
static void mtk_pcie_config_tlp_header(const struct udevice *bus,
pci_dev_t devfn,
int where, int size)
@@ -91,6 +113,8 @@ static void mtk_pcie_config_tlp_header(c
int bytes;
u32 val;
+ devfn = convert_bdf(bus, devfn);
+
size = 1 << size;
bytes = (GENMASK(size - 1, 0) & 0xf) << (where & 0x3);

219
package/boot/uboot-mediatek/patches/070-10-arm-dts-mediatek-add-pcie-support-for-mt7988.patch
View file

@ -1,219 +0,0 @@
From 4064eb22e221ce93fef7f1ec3b13ac670c6b20e2 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 17 Jan 2025 17:18:17 +0800
Subject: [PATCH 10/15] arm: dts: mediatek: add pcie support for mt7988
This patch adds PCIe support for mt7988
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
arch/arm/dts/mt7988-rfb.dts | 18 ++++
arch/arm/dts/mt7988.dtsi | 162 ++++++++++++++++++++++++++++++++++++
2 files changed, 180 insertions(+)
--- a/arch/arm/dts/mt7988-rfb.dts
+++ b/arch/arm/dts/mt7988-rfb.dts
@@ -63,6 +63,24 @@
};
};
+&pcie0 {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};
+
+/* PCIE2 not working in u-boot */
+&pcie2 {
+ status = "disabled";
+};
+
+/* PCIE3 not working in u-boot */
+&pcie3 {
+ status = "disabled";
+};
+
&pinctrl {
i2c1_pins: i2c1-pins {
mux {
--- a/arch/arm/dts/mt7988.dtsi
+++ b/arch/arm/dts/mt7988.dtsi
@@ -188,6 +188,152 @@
status = "okay";
};
+ pcie2: pcie@11280000 {
+ compatible = "mediatek,mt7988-pcie",
+ "mediatek,mt7986-pcie",
+ "mediatek,mt8192-pcie";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ reg = <0 0x11280000 0 0x2000>;
+ reg-names = "pcie-mac";
+ linux,pci-domain = <3>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x20200000 0 0x20200000 0 0x07e00000>;
+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
+ <&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
+ clock-names = "pl_250m", "tl_26m", "peri_26m",
+ "top_133m";
+ phys = <&xphyu3port0 PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+
+ status = "disabled";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &pcie_intc2 0>,
+ <0 0 0 2 &pcie_intc2 1>,
+ <0 0 0 3 &pcie_intc2 2>,
+ <0 0 0 4 &pcie_intc2 3>;
+
+ pcie_intc2: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ pcie3: pcie@11290000 {
+ compatible = "mediatek,mt7988-pcie",
+ "mediatek,mt7986-pcie",
+ "mediatek,mt8192-pcie";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ reg = <0 0x11290000 0 0x2000>;
+ reg-names = "pcie-mac";
+ linux,pci-domain = <2>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x28200000 0 0x28200000 0 0x07e00000>;
+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
+ <&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
+ clock-names = "pl_250m", "tl_26m", "peri_26m",
+ "top_133m";
+ use-dedicated-phy;
+
+ status = "disabled";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &pcie_intc3 0>,
+ <0 0 0 2 &pcie_intc3 1>,
+ <0 0 0 3 &pcie_intc3 2>,
+ <0 0 0 4 &pcie_intc3 3>;
+ pcie_intc3: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ pcie0: pcie@11300000 {
+ compatible = "mediatek,mt7988-pcie",
+ "mediatek,mt7986-pcie",
+ "mediatek,mt8192-pcie";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ reg = <0 0x11300000 0 0x2000>;
+ reg-names = "pcie-mac";
+ linux,pci-domain = <0>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x30200000 0 0x30200000 0 0x07e00000>;
+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
+ <&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
+ clock-names = "pl_250m", "tl_26m", "peri_26m",
+ "top_133m";
+ use-dedicated-phy;
+
+ status = "disabled";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+ <0 0 0 2 &pcie_intc0 1>,
+ <0 0 0 3 &pcie_intc0 2>,
+ <0 0 0 4 &pcie_intc0 3>;
+ pcie_intc0: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ pcie1: pcie@11310000 {
+ compatible = "mediatek,mt7988-pcie",
+ "mediatek,mt7986-pcie",
+ "mediatek,mt8192-pcie";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ reg = <0 0x11310000 0 0x2000>;
+ reg-names = "pcie-mac";
+ linux,pci-domain = <1>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x38200000 0 0x38200000 0 0x07e00000>;
+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
+ <&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
+ clock-names = "pl_250m", "tl_26m", "peri_26m",
+ "top_133m";
+ use-dedicated-phy;
+
+ status = "disabled";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+ <0 0 0 2 &pcie_intc1 1>,
+ <0 0 0 3 &pcie_intc1 2>,
+ <0 0 0 4 &pcie_intc1 3>;
+ pcie_intc1: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
usbtphy: usb-phy@11c50000 {
compatible = "mediatek,mt7988",
"mediatek,generic-tphy-v2";
@@ -214,6 +360,22 @@
status = "okay";
};
};
+
+ xphy: xphy@11e10000 {
+ compatible = "mediatek,mt7988", "mediatek,xsphy";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ xphyu3port0: usb-phy@11e13000 {
+ reg = <0 0x11e13400 0 0x500>;
+ clocks = <&dummy_clk>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
xfi_pextp0: syscon@11f20000 {
compatible = "mediatek,mt7988-xfi_pextp_0", "syscon";

36
package/boot/uboot-mediatek/patches/070-11-arm-dts-medaitek-fix-internal-switch-link-speed-of-m.patch
View file

@ -1,36 +0,0 @@
From 4a85182570200bf5e87e2a9920e9d28e968bc6e0 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 17 Jan 2025 17:18:22 +0800
Subject: [PATCH 11/15] arm: dts: medaitek: fix internal switch link speed of
mt7988
The CPU port of mt7988 internal switch uses 10Gb link speed.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
arch/arm/dts/mt7988-rfb.dts | 2 +-
arch/arm/dts/mt7988-sd-rfb.dts | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
--- a/arch/arm/dts/mt7988-rfb.dts
+++ b/arch/arm/dts/mt7988-rfb.dts
@@ -57,7 +57,7 @@
mediatek,switch = "mt7988";
fixed-link {
- speed = <1000>;
+ speed = <10000>;
full-duplex;
pause;
};
--- a/arch/arm/dts/mt7988-sd-rfb.dts
+++ b/arch/arm/dts/mt7988-sd-rfb.dts
@@ -48,7 +48,7 @@
mediatek,switch = "mt7988";
fixed-link {
- speed = <1000>;
+ speed = <10000>;
full-duplex;
pause;
};

103
package/boot/uboot-mediatek/patches/070-12-arm-dts-mediatek-add-support-for-all-three-GMACs-for.patch
View file

@ -1,103 +0,0 @@
From 64cf3dd0ef520a81a27359d83d58b64939e2aa06 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 17 Jan 2025 17:18:27 +0800
Subject: [PATCH 12/15] arm: dts: mediatek: add support for all three GMACs for
mt7988
This patch add all three GMACs nodes for mt7988. Each GMAC can be
configured to connect to different ethernet switches/PHYs.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
arch/arm/dts/mt7988-rfb.dts | 3 +--
arch/arm/dts/mt7988-sd-rfb.dts | 3 +--
arch/arm/dts/mt7988.dtsi | 42 ++++++++++++++++++++++++++++++++--
3 files changed, 42 insertions(+), 6 deletions(-)
--- a/arch/arm/dts/mt7988-rfb.dts
+++ b/arch/arm/dts/mt7988-rfb.dts
@@ -50,9 +50,8 @@
status = "okay";
};
-&eth {
+&eth0 {
status = "okay";
- mediatek,gmac-id = <0>;
phy-mode = "usxgmii";
mediatek,switch = "mt7988";
--- a/arch/arm/dts/mt7988-sd-rfb.dts
+++ b/arch/arm/dts/mt7988-sd-rfb.dts
@@ -41,9 +41,8 @@
status = "okay";
};
-&eth {
+&eth0 {
status = "okay";
- mediatek,gmac-id = <0>;
phy-mode = "usxgmii";
mediatek,switch = "mt7988";
--- a/arch/arm/dts/mt7988.dtsi
+++ b/arch/arm/dts/mt7988.dtsi
@@ -587,11 +587,11 @@
#reset-cells = <1>;
};
- eth: ethernet@15100000 {
+ eth0: ethernet@15110100 {
compatible = "mediatek,mt7988-eth", "syscon";
reg = <0 0x15100000 0 0x20000>;
+ mediatek,gmac-id = <0>;
mediatek,ethsys = <&ethdma>;
- mediatek,sgmiisys = <&sgmiisys0>;
mediatek,usxgmiisys = <&usxgmiisys0>;
mediatek,xfi_pextp = <&xfi_pextp0>;
mediatek,xfi_pll = <&xfi_pll>;
@@ -602,6 +602,44 @@
#address-cells = <1>;
#size-cells = <0>;
mediatek,mcm;
+ status = "disabled";
+ };
+
+ eth1: ethernet@15110200 {
+ compatible = "mediatek,mt7988-eth", "syscon";
+ reg = <0 0x15100000 0 0x20000>;
+ mediatek,gmac-id = <1>;
+ mediatek,ethsys = <&ethdma>;
+ mediatek,sgmiisys = <&sgmiisys1>;
+ mediatek,usxgmiisys = <&usxgmiisys1>;
+ mediatek,xfi_pextp = <&xfi_pextp1>;
+ mediatek,xfi_pll = <&xfi_pll>;
+ mediatek,infracfg = <&topmisc>;
+ mediatek,toprgu = <&watchdog>;
+ resets = <&ethdma ETHDMA_FE_RST>;
+ reset-names = "fe";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mediatek,mcm;
+ status = "disabled";
+ };
+
+ eth2: ethernet@15110300 {
+ compatible = "mediatek,mt7988-eth", "syscon";
+ reg = <0 0x15100000 0 0x20000>;
+ mediatek,gmac-id = <2>;
+ mediatek,ethsys = <&ethdma>;
+ mediatek,sgmiisys = <&sgmiisys0>;
+ mediatek,usxgmiisys = <&usxgmiisys0>;
+ mediatek,xfi_pextp = <&xfi_pextp0>;
+ mediatek,xfi_pll = <&xfi_pll>;
+ mediatek,infracfg = <&topmisc>;
+ mediatek,toprgu = <&watchdog>;
+ resets = <&ethdma ETHDMA_FE_RST>;
+ reset-names = "fe";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mediatek,mcm;
status = "disabled";
};
};

81
package/boot/uboot-mediatek/patches/070-13-arm-dts-medaitek-add-flash-interface-driving-setting.patch
View file

@ -1,81 +0,0 @@
From 1090c6df3767da2c56d5827ba65ce91af8745420 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 17 Jan 2025 17:18:41 +0800
Subject: [PATCH 13/15] arm: dts: medaitek: add flash interface driving
settings for mt7988
Add driving settings for both SPI and SD/eMMC interfaces to support ensure
flash devices is accessible for ram-booting.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
arch/arm/dts/mt7988-rfb.dts | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
--- a/arch/arm/dts/mt7988-rfb.dts
+++ b/arch/arm/dts/mt7988-rfb.dts
@@ -101,6 +101,19 @@
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
+
+ conf-pu {
+ pins = "SPI0_CSB", "SPI0_HOLD", "SPI0_WP";
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
+ };
+
+ conf-pd {
+ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
+ };
+
};
spi2_pins: spi2-pins {
@@ -108,6 +121,18 @@
function = "spi";
groups = "spi2", "spi2_wp_hold";
};
+
+ conf-pu {
+ pins = "SPI2_CSB", "SPI2_HOLD", "SPI2_WP";
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
+ };
+
+ conf-pd {
+ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
+ };
};
mmc0_pins_default: mmc0default {
@@ -121,18 +146,25 @@
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
input-enable;
+ drive-strength = <MTK_DRIVE_4mA>;
+ mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
conf-clk {
pins = "EMMC_CK";
+ drive-strength = <MTK_DRIVE_6mA>;
+ mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-dsl {
pins = "EMMC_DSL";
+ mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-rst {
pins = "EMMC_RSTB";
+ drive-strength = <MTK_DRIVE_4mA>;
+ mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
};
};

62
package/boot/uboot-mediatek/patches/070-14-arm-dts-mediatek-update-mt7981-mmc-node.patch
View file

@ -1,62 +0,0 @@
From 140303d0308738dfb04059333c9fc25b5159a776 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 17 Jan 2025 17:18:55 +0800
Subject: [PATCH 14/15] arm: dts: mediatek: update mt7981 mmc node
1. Fix mmc clock order of mt7981 to match the clock name
2. Limit the max clock of SD to 50MHz to meet SD Card Spec 2.0
3. Increase the CLK pin driving strength to 8mA
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
arch/arm/dts/mt7981-sd-rfb.dts | 6 ++++--
arch/arm/dts/mt7981.dtsi | 12 ++++++------
2 files changed, 10 insertions(+), 8 deletions(-)
--- a/arch/arm/dts/mt7981-sd-rfb.dts
+++ b/arch/arm/dts/mt7981-sd-rfb.dts
@@ -118,7 +118,7 @@
};
conf-clk {
pins = "SPI1_CS";
- drive-strength = <MTK_DRIVE_6mA>;
+ drive-strength = <MTK_DRIVE_8mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
conf-rst {
@@ -140,10 +140,12 @@
};
&mmc0 {
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_D4>,
+ <&topckgen CLK_TOP_CB_NET2_D2>;
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_default>;
bus-width = <4>;
- max-frequency = <52000000>;
+ max-frequency = <50000000>;
cap-sd-highspeed;
r_smpl = <0>;
vmmc-supply = <&reg_3p3v>;
--- a/arch/arm/dts/mt7981.dtsi
+++ b/arch/arm/dts/mt7981.dtsi
@@ -306,13 +306,13 @@
reg = <0x11230000 0x1000>,
<0x11C20000 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&topckgen CLK_TOP_EMMC_400M>,
- <&topckgen CLK_TOP_EMMC_208M>,
+ clocks = <&topckgen CLK_TOP_EMMC_208M>,
+ <&topckgen CLK_TOP_EMMC_400M>,
<&infracfg CLK_INFRA_MSDC_CK>;
- assigned-clocks = <&topckgen CLK_TOP_EMMC_400M_SEL>,
- <&topckgen CLK_TOP_EMMC_208M_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_D2>,
- <&topckgen CLK_TOP_CB_M_D2>;
+ assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>,
+ <&topckgen CLK_TOP_EMMC_400M_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
+ <&topckgen CLK_TOP_CB_NET2_D2>;
clock-names = "source", "hclk", "source_cg";
status = "disabled";
};

36
package/boot/uboot-mediatek/patches/070-15-MAINTAINERS-update-file-list-for-MediaTek-ARM-platfo.patch
View file

@ -1,36 +0,0 @@
From 8707ea0360046522d0784135b6c9a7c564f9515c Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 17 Jan 2025 17:18:59 +0800
Subject: [PATCH 15/15] MAINTAINERS: update file list for MediaTek ARM platform
Add driver files for MediaTek ARM platform
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
MAINTAINERS | 5 +++++
1 file changed, 5 insertions(+)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -412,9 +412,13 @@ F: drivers/mmc/mtk-sd.c
F: drivers/phy/phy-mtk-*
F: drivers/pinctrl/mediatek/
F: drivers/power/domain/mtk-power-domain.c
+F: drivers/pci/pcie_mediatek_gen3.c
+F: drivers/pci/pcie_mediatek.c
+F: drivers/pwm/pwm-mtk.c
F: drivers/ram/mediatek/
F: drivers/spi/mtk_snfi_spi.c
F: drivers/spi/mtk_spim.c
+F: drivers/spi/mtk_snor.c
F: drivers/timer/mtk_timer.c
F: drivers/usb/host/xhci-mtk.c
F: drivers/usb/mtu3/
@@ -422,6 +426,7 @@ F: drivers/watchdog/mtk_wdt.c
F: drivers/net/mtk_eth.c
F: drivers/net/mtk_eth.h
F: drivers/reset/reset-mediatek.c
+F: drivers/serial/serial_mtk.c
F: include/dt-bindings/clock/mediatek,*
F: include/dt-bindings/power/mediatek,*
F: tools/mtk_image.c

138
package/boot/uboot-mediatek/patches/071-01-pinctrl-mediatek-update-mt7981-pinctrl-driver-based-.patch
View file

@ -1,138 +0,0 @@
From 24e660265f11dad63687c5529cf732538946a197 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 24 Jan 2025 11:39:02 +0800
Subject: [PATCH] pinctrl: mediatek: update mt7981 pinctrl driver based on
upstream kernel
Update mt7981 pinctrl driver based on upstream kernel
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/pinctrl/mediatek/pinctrl-mt7981.c | 51 ++++++++++++++++++++---
1 file changed, 45 insertions(+), 6 deletions(-)
--- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
@@ -569,6 +569,11 @@ static const struct mtk_pin_desc mt7981_
MT7981_TYPE1_PIN(56, "WF_HB10"),
};
+/* List all groups consisting of these pins dedicated to the enablement of
+ * certain hardware block and the corresponding mode for all of the pins.
+ * The hardware probably has multiple combinations of these pinouts.
+ */
+
/* WA_AICE */
static const int mt7981_wa_aice1_pins[] = { 0, 1, };
static const int mt7981_wa_aice1_funcs[] = { 2, 2, };
@@ -632,6 +637,9 @@ static const int mt7981_wo0_jtag_1_funcs
static const int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, };
static const int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, };
+static const int mt7981_uart2_0_tx_rx_pins[] = { 4, 5, };
+static const int mt7981_uart2_0_tx_rx_funcs[] = { 3, 3, };
+
/* GBE_LED0 */
static const int mt7981_gbe_led0_pins[] = { 8, };
static const int mt7981_gbe_led0_funcs[] = { 3, };
@@ -718,6 +726,17 @@ static const int mt7981_drv_vbus_pins[]
static const int mt7981_drv_vbus_funcs[] = { 1, };
/* EMMC */
+static const int mt7981_emmc_reset_pins[] = { 15, };
+static const int mt7981_emmc_reset_funcs[] = { 2, };
+
+static const int mt7981_emmc_4_pins[] = { 16, 17, 18, 19, 24, 25, };
+static const int mt7981_emmc_4_funcs[] = { 2, 2, 2, 2, 2, 2, };
+
+static const int mt7981_emmc_8_pins[] = {
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
+static const int mt7981_emmc_8_funcs[] = {
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
+
static const int mt7981_emmc_45_pins[] = {
15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
static const int mt7981_emmc_45_funcs[] = {
@@ -754,6 +773,12 @@ static const int mt7981_uart1_0_funcs[]
static const int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, };
static const int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, };
+static const int mt7981_uart1_2_pins[] = { 9, 10, };
+static const int mt7981_uart1_2_funcs[] = { 2, 2, };
+
+static const int mt7981_uart1_3_pins[] = { 26, 27, };
+static const int mt7981_uart1_3_funcs[] = { 2, 2, };
+
/* UART2 */
static const int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
static const int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
@@ -832,6 +857,8 @@ static const struct mtk_group_desc mt798
PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0),
/* @GPIO(4,7) WM_JTAG(3) */
PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0),
+ /* @GPIO(4,5) WM_JTAG(4) */
+ PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7981_uart2_0_tx_rx),
/* @GPIO(8) GBE_LED0(3) */
PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0),
/* @GPIO(4,6) PTA_EXT(4) */
@@ -844,7 +871,7 @@ static const struct mtk_group_desc mt798
PINCTRL_PIN_GROUP("spi1_0", mt7981_spi1_0),
/* @GPIO(6,7) I2C(5) */
PINCTRL_PIN_GROUP("i2c0_0", mt7981_i2c0_0),
- /* @GPIO(8): DFD_NTRST(6) */
+ /* @GPIO(0,1,4,5): DFD_NTRST(6) */
PINCTRL_PIN_GROUP("dfd_ntrst", mt7981_dfd_ntrst),
/* @GPIO(9,10): WM_AICE(2) */
PINCTRL_PIN_GROUP("wm_aice1", mt7981_wm_aice1),
@@ -870,6 +897,12 @@ static const struct mtk_group_desc mt798
PINCTRL_PIN_GROUP("udi", mt7981_udi),
/* @GPIO(14) DRV_VBUS(1) */
PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus),
+ /* @GPIO(15): EMMC_RSTB(2) */
+ PINCTRL_PIN_GROUP("emmc_reset", mt7981_emmc_reset),
+ /* @GPIO(16,17,18,19,24,25): EMMC_DATx, EMMC_CLK, EMMC_CMD */
+ PINCTRL_PIN_GROUP("emmc_4", mt7981_emmc_4),
+ /* @GPIO(16,17,18,19,20,21,22,23,24,25): EMMC_DATx, EMMC_CLK, EMMC_CMD */
+ PINCTRL_PIN_GROUP("emmc_8", mt7981_emmc_8),
/* @GPIO(15,25): EMMC(2) */
PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45),
/* @GPIO(16,21): SNFI(3) */
@@ -888,8 +921,12 @@ static const struct mtk_group_desc mt798
PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0),
/* @GPIO(26,29): UART1(2) */
PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1),
+ /* @GPIO(9,10): UART1(2) */
+ PINCTRL_PIN_GROUP("uart1_2", mt7981_uart1_2),
+ /* @GPIO(26,27): UART1(2) */
+ PINCTRL_PIN_GROUP("uart1_3", mt7981_uart1_3),
/* @GPIO(22,25): UART2(3) */
- PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_1),
+ PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1),
/* @GPIO(22,24) PTA_EXT(4) */
PINCTRL_PIN_GROUP("pta_ext_1", mt7981_pta_ext_1),
/* @GPIO(20,21): WM_UART(4) */
@@ -964,9 +1001,10 @@ static const struct mtk_io_type_desc mt7
*/
static const char *const mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2",
"wm_aice1_1", "wa_aice3", "wm_aice1_2", };
-static const char *const mt7981_uart_groups[] = { "wm_uart_0", "uart2_0",
- "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2",
- "uart1_0", "uart1_1", "uart2_0", "wm_aurt_1", "wm_aurt_2", "uart0", };
+static const char *const mt7981_uart_groups[] = { "net_wo0_uart_txd_0",
+ "net_wo0_uart_txd_1", "net_wo0_uart_txd_2", "uart0", "uart1_0",
+ "uart1_1", "uart1_2", "uart1_3", "uart2_0", "uart2_0_tx_rx", "uart2_1",
+ "wm_uart_0", "wm_aurt_1", "wm_aurt_2", };
static const char *const mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", };
static const char *const mt7981_wdt_groups[] = { "watchdog", "watchdog1", };
static const char *const mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk",
@@ -986,7 +1024,8 @@ static const char *const mt7981_i2c_grou
static const char *const mt7981_pcm_groups[] = { "pcm", };
static const char *const mt7981_udi_groups[] = { "udi", };
static const char *const mt7981_usb_groups[] = { "drv_vbus", };
-static const char *const mt7981_flash_groups[] = { "emmc_45", "snfi", };
+static const char *const mt7981_flash_groups[] = { "emmc_reset", "emmc_4",
+ "emmc_8", "emmc_45", "snfi", };
static const char *const mt7981_ethernet_groups[] = { "smi_mdc_mdio",
"gbe_ext_mdc_mdio", "wf0_mode1", "wf0_mode3", "mt7531_int", };
static const char *const mt7981_ant_groups[] = { "ant_sel", };

8
package/boot/uboot-mediatek/patches/100-04-env-add-support-for-generic-MTD-device.patch
View file

@ -19,7 +19,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -61,7 +61,7 @@ config ENV_IS_DEFAULT
@@ -74,7 +74,7 @@ config ENV_IS_DEFAULT
!ENV_IS_IN_MMC && !ENV_IS_IN_NAND && \
!ENV_IS_IN_NVRAM && !ENV_IS_IN_ONENAND && \
!ENV_IS_IN_REMOTE && !ENV_IS_IN_SPI_FLASH && \
@ -28,7 +28,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
select ENV_IS_NOWHERE
config ENV_IS_NOWHERE
@@ -254,6 +254,27 @@ config ENV_IS_IN_MMC
@@ -267,6 +267,27 @@ config ENV_IS_IN_MMC
offset: "u-boot,mmc-env-offset", "u-boot,mmc-env-offset-redundant".
CONFIG_ENV_OFFSET and CONFIG_ENV_OFFSET_REDUND are not used.
@ -56,7 +56,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
config ENV_IS_IN_NAND
bool "Environment in a NAND device"
depends on !CHAIN_OF_TRUST
@@ -561,10 +582,16 @@ config ENV_ADDR_REDUND
@@ -574,10 +595,16 @@ config ENV_ADDR_REDUND
Offset from the start of the device (or partition) of the redundant
environment location.
@ -74,7 +74,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
default 0x3f8000 if ARCH_ROCKCHIP && ENV_IS_IN_MMC
default 0x140000 if ARCH_ROCKCHIP && ENV_IS_IN_SPI_FLASH
default 0xF0000 if ARCH_SUNXI
@@ -622,6 +649,12 @@ config ENV_SECT_SIZE
@@ -635,6 +662,12 @@ config ENV_SECT_SIZE
help
Size of the sector containing the environment.

4
package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch
View file

@ -13,7 +13,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -381,6 +381,20 @@ static int initr_nand(void)
@@ -378,6 +378,20 @@ static int initr_nand(void)
}
#endif
@ -34,7 +34,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
#if defined(CONFIG_CMD_ONENAND)
/* go init the NAND */
static int initr_onenand(void)
@@ -694,6 +708,9 @@ static init_fnc_t init_sequence_r[] = {
@@ -693,6 +707,9 @@ static init_fnc_t init_sequence_r[] = {
#ifdef CONFIG_CMD_ONENAND
initr_onenand,
#endif

4
package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch
View file

@ -15,7 +15,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1492,6 +1492,12 @@ config CMD_NAND_TORTURE
@@ -1525,6 +1525,12 @@ config CMD_NAND_WATCH
endif # CMD_NAND
@ -30,7 +30,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
depends on NVME
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -127,6 +127,7 @@ obj-y += legacy-mtd-utils.o
@@ -130,6 +130,7 @@ obj-y += legacy-mtd-utils.o
endif
obj-$(CONFIG_CMD_MUX) += mux.o
obj-$(CONFIG_CMD_NAND) += nand.o

6
package/boot/uboot-mediatek/patches/100-10-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch
View file

@ -20,7 +20,7 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
--- a/cmd/mtd.c
+++ b/cmd/mtd.c
@@ -730,6 +730,42 @@ out_put_mtd:
@@ -728,6 +728,42 @@ out_put_mtd:
return CMD_RET_SUCCESS;
}
@ -63,7 +63,7 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
#ifdef CONFIG_AUTO_COMPLETE
static int mtd_name_complete(int argc, char *const argv[], char last_char,
int maxv, char *cmdv[])
@@ -777,6 +813,7 @@ U_BOOT_LONGHELP(mtd,
@@ -775,6 +811,7 @@ U_BOOT_LONGHELP(mtd,
"\n"
"Specific functions:\n"
"mtd bad <name>\n"
@ -71,7 +71,7 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
#if CONFIG_IS_ENABLED(CMD_MTD_OTP)
"mtd otpread <name> [u|f] <off> <size>\n"
"mtd otpwrite <name> <off> <hex string>\n"
@@ -817,4 +854,6 @@ U_BOOT_CMD_WITH_SUBCMDS(mtd, "MTD utils"
@@ -815,4 +852,6 @@ U_BOOT_CMD_WITH_SUBCMDS(mtd, "MTD utils"
U_BOOT_SUBCMD_MKENT_COMPLETE(erase, 4, 0, do_mtd_erase,
mtd_name_complete),
U_BOOT_SUBCMD_MKENT_COMPLETE(bad, 2, 1, do_mtd_bad,

6
package/boot/uboot-mediatek/patches/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch
View file

@ -18,7 +18,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -61,7 +61,7 @@ config ENV_IS_DEFAULT
@@ -74,7 +74,7 @@ config ENV_IS_DEFAULT
!ENV_IS_IN_MMC && !ENV_IS_IN_NAND && \
!ENV_IS_IN_NVRAM && !ENV_IS_IN_ONENAND && \
!ENV_IS_IN_REMOTE && !ENV_IS_IN_SPI_FLASH && \
@ -27,7 +27,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
select ENV_IS_NOWHERE
config ENV_IS_NOWHERE
@@ -305,6 +305,21 @@ config ENV_IS_IN_NAND
@@ -318,6 +318,21 @@ config ENV_IS_IN_NAND
Currently, CONFIG_ENV_OFFSET_REDUND is not supported when
using CONFIG_ENV_OFFSET_OOB.
@ -49,7 +49,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
config ENV_RANGE
hex "Length of the region in which the environment can be written"
depends on ENV_IS_IN_NAND
@@ -591,7 +606,7 @@ config ENV_MTD_NAME
@@ -604,7 +619,7 @@ config ENV_MTD_NAME
config ENV_OFFSET
hex "Environment offset"
depends on ENV_IS_IN_EEPROM || ENV_IS_IN_MMC || ENV_IS_IN_NAND || \

4
package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch
View file

@ -26,7 +26,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1492,6 +1492,14 @@ config CMD_NAND_TORTURE
@@ -1525,6 +1525,14 @@ config CMD_NAND_WATCH
endif # CMD_NAND
@ -43,7 +43,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
bool "nmbm"
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -127,6 +127,7 @@ obj-y += legacy-mtd-utils.o
@@ -130,6 +130,7 @@ obj-y += legacy-mtd-utils.o
endif
obj-$(CONFIG_CMD_MUX) += mux.o
obj-$(CONFIG_CMD_NAND) += nand.o

274
package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch
View file

@ -1,274 +0,0 @@
From 452dc98572f8353f77551bcce5a2ca8cd050f498 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Wed, 3 Mar 2021 10:48:53 +0800
Subject: [PATCH 53/71] board: mt7629: add support for booting from SPI-NAND
Add support for mt7629 to boot from SPI-NAND.
Add a new defconfig for mt7629+spi-nand configuration.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
arch/arm/dts/mt7629-rfb-u-boot.dtsi | 8 ++
arch/arm/dts/mt7629-rfb.dts | 10 +++
arch/arm/dts/mt7629.dtsi | 16 ++++
arch/arm/mach-mediatek/Kconfig | 4 +-
board/mediatek/mt7629/Kconfig | 40 ++++++++++
board/mediatek/mt7629/mt7629_rfb.c | 5 ++
configs/mt7629_nand_rfb_defconfig | 113 ++++++++++++++++++++++++++++
7 files changed, 195 insertions(+), 1 deletion(-)
create mode 100644 board/mediatek/mt7629/Kconfig
create mode 100644 configs/mt7629_nand_rfb_defconfig
--- a/arch/arm/dts/mt7629-rfb-u-boot.dtsi
+++ b/arch/arm/dts/mt7629-rfb-u-boot.dtsi
@@ -40,3 +40,11 @@
&snfi {
bootph-all;
};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
+
+&snand {
+ u-boot,dm-pre-reloc;
+};
--- a/arch/arm/dts/mt7629-rfb.dts
+++ b/arch/arm/dts/mt7629-rfb.dts
@@ -47,9 +47,12 @@
};
snfi_pins: snfi-pins {
+ u-boot,dm-pre-reloc;
+
mux {
function = "flash";
groups = "snfi";
+ u-boot,dm-pre-reloc;
};
};
@@ -102,6 +105,13 @@
};
};
+&snand {
+ pinctrl-names = "default";
+ pinctrl-0 = <&snfi_pins>;
+ status = "okay";
+ quad-spi;
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
--- a/arch/arm/dts/mt7629.dtsi
+++ b/arch/arm/dts/mt7629.dtsi
@@ -229,6 +229,22 @@
#size-cells = <0>;
};
+ snand: snand@1100d000 {
+ compatible = "mediatek,mt7629-snand";
+ reg = <0x1100d000 0x1000>,
+ <0x1100e000 0x1000>;
+ reg-names = "nfi", "ecc";
+ clocks = <&pericfg CLK_PERI_NFI_PD>,
+ <&pericfg CLK_PERI_SNFI_PD>,
+ <&pericfg CLK_PERI_NFIECC_PD>;
+ clock-names = "nfi_clk", "pad_clk", "ecc_clk";
+ assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
+ <&topckgen CLK_TOP_NFI_INFRA_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
+ <&topckgen CLK_TOP_UNIVPLL2_D8>;
+ status = "disabled";
+ };
+
snor: snor@11014000 {
compatible = "mediatek,mtk-snor";
reg = <0x11014000 0x1000>;
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -148,9 +148,11 @@ config SYS_CONFIG_NAME
config MTK_BROM_HEADER_INFO
string
- default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622
+ default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7622
default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183
default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 || TARGET_MT7988
default "lk=1" if TARGET_MT7623
+source "board/mediatek/mt7629/Kconfig"
+
endif
--- /dev/null
+++ b/board/mediatek/mt7629/Kconfig
@@ -0,0 +1,40 @@
+if TARGET_MT7629
+
+config MTK_BROM_HEADER_INFO
+ string
+ default "media=nor" if BOOT_FROM_SNOR
+ default "media=snand;nandinfo=2k+64" if BOOT_FROM_SNAND_2K_64
+ default "media=snand;nandinfo=2k+128" if BOOT_FROM_SNAND_2K_128
+ default "media=snand;nandinfo=4k+128" if BOOT_FROM_SNAND_4K_128
+ default "media=snand;nandinfo=4k+256" if BOOT_FROM_SNAND_4K_256
+
+choice
+ prompt "Boot device"
+ default BOOT_FROM_SNOR
+
+config BOOT_FROM_SNOR
+ bool "SPI-NOR"
+
+config BOOT_FROM_SNAND_2K_64
+ bool "SPI-NAND (2K+64)"
+ select MT7629_BOOT_FROM_SNAND
+
+config BOOT_FROM_SNAND_2K_128
+ bool "SPI-NAND (2K+128)"
+ select MT7629_BOOT_FROM_SNAND
+
+config BOOT_FROM_SNAND_4K_128
+ bool "SPI-NAND (4K+128)"
+ select MT7629_BOOT_FROM_SNAND
+
+config BOOT_FROM_SNAND_4K_256
+ bool "SPI-NAND (4K+256)"
+ select MT7629_BOOT_FROM_SNAND
+
+endchoice
+
+config MT7629_BOOT_FROM_SNAND
+ bool
+ default n
+
+endif
--- a/board/mediatek/mt7629/mt7629_rfb.c
+++ b/board/mediatek/mt7629/mt7629_rfb.c
@@ -15,3 +15,8 @@ int board_init(void)
return 0;
}
+
+uint32_t spl_nand_get_uboot_raw_page(void)
+{
+ return CONFIG_SPL_PAD_TO;
+}
--- /dev/null
+++ b/configs/mt7629_nand_rfb_defconfig
@@ -0,0 +1,113 @@
+CONFIG_ARM=y
+CONFIG_SYS_ARCH_TIMER=y
+CONFIG_SYS_THUMB_BUILD=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_TEXT_BASE=0x41e00000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0x0
+CONFIG_DEFAULT_DEVICE_TREE="mt7629-rfb"
+CONFIG_SPL_TEXT_BASE=0x201000
+CONFIG_TARGET_MT7629=y
+CONFIG_BOOT_FROM_SNAND_2K_64=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x40800000
+CONFIG_SYS_LOAD_ADDR=0x42007f1c
+CONFIG_SPL_PAYLOAD="u-boot.img"
+CONFIG_BUILD_TARGET="u-boot-mtk.bin"
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41fffef0
+CONFIG_SPL_IMAGE="spl/u-boot-spl-mtk.bin"
+CONFIG_FIT=y
+# CONFIG_AUTOBOOT is not set
+CONFIG_DEFAULT_FDT_FILE="mt7629-rfb"
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL_MAX_SIZE=0x20000
+CONFIG_SPL_FOOTPRINT_LIMIT=y
+CONFIG_SPL_MAX_FOOTPRINT=0x20000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK=0x106000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="U-Boot> "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_CMD_BOOTMENU=y
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_BIND=y
+CONFIG_CMD_DM=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_LOG=y
+CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-parents"
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MTD=y
+CONFIG_ENV_MTD_NAME="u-boot-env"
+CONFIG_ENV_SIZE_REDUND=0x40000
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTK_SPI_NAND=y
+CONFIG_MTK_SPI_NAND_MTD=y
+CONFIG_SPL_MTK_SPI_NAND=y
+CONFIG_DM_ETH=y
+CONFIG_MEDIATEK_ETH=y
+CONFIG_PHY=y
+CONFIG_PHY_MTK_TPHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_SPL_PINCONF=y
+CONFIG_PINCTRL_MT7629=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MTK_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_DM_SERIAL=y
+CONFIG_MTK_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SPI_MEM=y
+CONFIG_MTK_SNFI_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_MTK=y
+CONFIG_USB_STORAGE=y
+CONFIG_WDT_MTK=y
+# CONFIG_SHA256 is not set
+# CONFIG_SPL_SHA1 is not set
+CONFIG_LZMA=y
+CONFIG_SPL_LZMA=y
+# CONFIG_EFI_LOADER is not set

8
package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch
View file

@ -18,9 +18,9 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1195,6 +1195,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
@@ -1136,6 +1136,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7622-bananapi-bpi-r64.dtb \
mt7623n-bananapi-bpi-r2.dtb \
mt7629-rfb.dtb \
mt7981-rfb.dtb \
+ mt7981-snfi-nand-rfb.dtb \
mt7981-emmc-rfb.dtb \
@ -65,7 +65,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+ mediatek,gmac-id = <0>;
+ phy-mode = "sgmii";
+ mediatek,switch = "mt7531";
+ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
+
+ fixed-link {
+ speed = <1000>;
@ -73,7 +73,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+ };
+};
+
+&pinctrl {
+&pio {
+ snfi_pins: snfi-pins-func-1 {
+ mux {
+ function = "flash";

6
package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch
View file

@ -15,7 +15,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -876,6 +876,14 @@ config MMC_MTK
@@ -868,6 +868,14 @@ config MMC_MTK
This is needed if support for any SD/SDIO/MMC devices is required.
If unsure, say N.
@ -32,7 +32,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
config FSL_SDHC_V2_3
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -84,3 +84,7 @@ obj-$(CONFIG_RENESAS_SDHI) += tmio-comm
@@ -85,3 +85,7 @@ obj-$(CONFIG_RENESAS_SDHI) += tmio-comm
obj-$(CONFIG_MMC_BCM2835) += bcm2835_sdhost.o
obj-$(CONFIG_MMC_MTK) += mtk-sd.o
obj-$(CONFIG_MMC_SDHCI_F_SDH30) += f_sdh30.o
@ -42,7 +42,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+endif
--- a/drivers/mmc/mtk-sd.c
+++ b/drivers/mmc/mtk-sd.c
@@ -783,18 +783,24 @@ static int msdc_ops_send_cmd(struct udev
@@ -784,18 +784,24 @@ static int msdc_ops_send_cmd(struct udev
if (cmd_ret &&
!(cmd_ret == -EIO &&
(cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||

2
package/boot/uboot-mediatek/patches/100-26-env-ubi-add-support-to-create-environment-volume-if-.patch
View file

@ -14,7 +14,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -688,6 +688,12 @@ config ENV_UBI_VOLUME_REDUND
@@ -701,6 +701,12 @@ config ENV_UBI_VOLUME_REDUND
help
Name of the redundant volume that you want to store the environment in.

6
package/boot/uboot-mediatek/patches/100-29-board-mediatek-wire-up-NMBM-support.patch
View file

@ -74,9 +74,9 @@ Subject: [PATCH] board: mediatek: wire-up NMBM support
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
@@ -20,3 +25,36 @@ uint32_t spl_nand_get_uboot_raw_page(voi
{
return CONFIG_SPL_PAD_TO;
@@ -15,3 +20,36 @@ int board_init(void)
return 0;
}
+
+int board_nmbm_init(void)

2
package/boot/uboot-mediatek/patches/103-02-mt7981-enable-pstore.patch
View file

@ -1,6 +1,6 @@
--- a/arch/arm/dts/mt7981.dtsi
+++ b/arch/arm/dts/mt7981.dtsi
@@ -32,6 +32,35 @@
@@ -33,6 +33,35 @@
};
};

2
package/boot/uboot-mediatek/patches/106-configs-sync-mt7981-rfb-storage.patch
View file

@ -1,6 +1,6 @@
--- a/configs/mt7981_rfb_defconfig
+++ b/configs/mt7981_rfb_defconfig
@@ -31,6 +31,9 @@ CONFIG_CMD_MTD=y
@@ -30,6 +30,9 @@ CONFIG_CMD_MTD=y
CONFIG_CMD_SF_TEST=y
CONFIG_CMD_PING=y
CONFIG_CMD_SMC=y

5
package/boot/uboot-mediatek/patches/107-configs-add-useful-options-to-mt7981-rfb.patch
View file

@ -87,7 +87,7 @@
CONFIG_HEXDUMP=y
--- a/configs/mt7981_rfb_defconfig
+++ b/configs/mt7981_rfb_defconfig
@@ -6,39 +6,79 @@ CONFIG_TEXT_BASE=0x41e00000
@@ -6,38 +6,78 @@ CONFIG_TEXT_BASE=0x41e00000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEFAULT_DEVICE_TREE="mt7981-rfb"
@ -97,7 +97,6 @@
CONFIG_DEBUG_UART_BASE=0x11002000
CONFIG_DEBUG_UART_CLOCK=40000000
CONFIG_DEBUG_UART=y
# CONFIG_EFI_LOADER is not set
-# CONFIG_AUTOBOOT is not set
+CONFIG_FIT=y
+CONFIG_SPI_BOOT=y
@ -169,7 +168,7 @@
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_DM_MTD=y
@@ -63,6 +103,7 @@ CONFIG_PINCTRL_MT7981=y
@@ -62,6 +102,7 @@ CONFIG_PINCTRL_MT7981=y
CONFIG_POWER_DOMAIN=y
CONFIG_MTK_POWER_DOMAIN=y
CONFIG_DM_SERIAL=y

4
package/boot/uboot-mediatek/patches/130-fix-mkimage-host-build.patch
View file

@ -1,6 +1,6 @@
--- a/tools/image-host.c
+++ b/tools/image-host.c
@@ -1162,6 +1162,7 @@ static int fit_config_add_verification_d
@@ -1175,6 +1175,7 @@ static int fit_config_add_verification_d
* 2) get public key (X509_get_pubkey)
* 3) provide der format (d2i_RSAPublicKey)
*/
@ -8,7 +8,7 @@
static int read_pub_key(const char *keydir, const void *name,
unsigned char **pubkey, int *pubkey_len)
{
@@ -1215,6 +1216,13 @@ err_cert:
@@ -1228,6 +1229,13 @@ err_cert:
fclose(f);
return ret;
}

2
package/boot/uboot-mediatek/patches/160-net-phy-add-support-for-Airoha-ethernet-PHY-driver.patch
View file

@ -58,7 +58,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -83,6 +83,37 @@ config PHY_ADIN
@@ -79,6 +79,37 @@ config PHY_ADIN
help
Add support for configuring RGMII on Analog Devices ADIN PHYs.

2
package/boot/uboot-mediatek/patches/170-cmd-bootmenu-permit-to-select-bootmenu-entry-with.patch
View file

@ -120,7 +120,7 @@ Changes v2:
entry->command = strdup(sep + 1);
if (!entry->command) {
free(entry->title);
@@ -382,9 +417,9 @@ static struct bootmenu_data *bootmenu_cr
@@ -388,9 +423,9 @@ static struct bootmenu_data *bootmenu_cr
/* Add Quit entry if exiting bootmenu is disabled */
if (!IS_ENABLED(CONFIG_BOOTMENU_DISABLE_UBOOT_CONSOLE))

6
package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch
View file

@ -70,7 +70,7 @@
{
--- a/boot/image-fit.c
+++ b/boot/image-fit.c
@@ -2047,6 +2047,47 @@ static const char *fit_get_image_type_pr
@@ -2054,6 +2054,47 @@ static const char *fit_get_image_type_pr
return "unknown";
}
@ -101,7 +101,7 @@
+ (noffset >= 0) && (ndepth > 0);
+ noffset = fdt_next_node(fit, noffset, &ndepth)) {
+ if (ndepth == 1) {
+ ret = fit_image_get_data_and_size(fit, noffset, &data, &data_size);
+ ret = fit_image_get_data(fit, noffset, &data, &data_size);
+ if (ret)
+ goto out;
+
@ -120,7 +120,7 @@
int arch, int ph_type, int bootstage_id,
--- a/include/image.h
+++ b/include/image.h
@@ -1112,6 +1112,7 @@ int fit_parse_subimage(const char *spec,
@@ -1113,6 +1113,7 @@ int fit_parse_subimage(const char *spec,
ulong *addr, const char **image_name);
int fit_get_subimage_count(const void *fit, int images_noffset);

4
package/boot/uboot-mediatek/patches/211-cmd-bootmenu-custom-title.patch
View file

@ -1,6 +1,6 @@
--- a/cmd/bootmenu.c
+++ b/cmd/bootmenu.c
@@ -476,7 +476,11 @@ static void menu_display_statusline(stru
@@ -482,7 +482,11 @@ static void menu_display_statusline(stru
printf(ANSI_CURSOR_POSITION, 1, 1);
puts(ANSI_CLEAR_LINE);
printf(ANSI_CURSOR_POSITION, 2, 3);
@ -13,7 +13,7 @@
puts(ANSI_CLEAR_LINE_TO_END);
printf(ANSI_CURSOR_POSITION, 3, 1);
puts(ANSI_CLEAR_LINE);
@@ -561,6 +565,7 @@ static enum bootmenu_ret bootmenu_show(i
@@ -573,6 +577,7 @@ static enum bootmenu_ret bootmenu_show(i
return BOOTMENU_RET_FAIL;
}

8
package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch
View file

@ -1,6 +1,6 @@
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -692,6 +692,12 @@ config CMD_ENV_EXISTS
@@ -707,6 +707,12 @@ config CMD_ENV_EXISTS
Check if a variable is defined in the environment for use in
shell scripting.
@ -76,7 +76,7 @@
#if defined(CONFIG_CMD_ENV_CALLBACK)
static int print_static_binding(const char *var_name, const char *callback_name,
void *priv)
@@ -1089,6 +1143,9 @@ static struct cmd_tbl cmd_env_sub[] = {
@@ -1092,6 +1146,9 @@ static struct cmd_tbl cmd_env_sub[] = {
U_BOOT_CMD_MKENT(load, 1, 0, do_env_load, "", ""),
#endif
U_BOOT_CMD_MKENT(print, CONFIG_SYS_MAXARGS, 1, do_env_print, "", ""),
@ -86,7 +86,7 @@
#if defined(CONFIG_CMD_RUN)
U_BOOT_CMD_MKENT(run, CONFIG_SYS_MAXARGS, 1, do_run, "", ""),
#endif
@@ -1172,6 +1229,9 @@ U_BOOT_LONGHELP(env,
@@ -1176,6 +1233,9 @@ U_BOOT_LONGHELP(env,
#if defined(CONFIG_CMD_NVEDIT_EFI)
"env print -e [-guid guid] [-n] [name ...] - print UEFI environment\n"
#endif
@ -96,7 +96,7 @@
#if defined(CONFIG_CMD_RUN)
"env run var [...] - run commands in an environment variable\n"
#endif
@@ -1280,6 +1340,17 @@ U_BOOT_CMD(
@@ -1284,6 +1344,17 @@ U_BOOT_CMD(
);
#endif

2
package/boot/uboot-mediatek/patches/280-image-fdt-save-name-of-FIT-configuration-in-chosen-node.patch
View file

@ -16,7 +16,7 @@ Reviewed-by: Tom Rini <trini@konsulko.com>
--- a/boot/image-fdt.c
+++ b/boot/image-fdt.c
@@ -612,6 +612,12 @@ int image_setup_libfdt(struct bootm_head
@@ -613,6 +613,12 @@ int image_setup_libfdt(struct bootm_head
images->fit_uname_cfg,
strlen(images->fit_uname_cfg) + 1, 1);

71
package/boot/uboot-mediatek/patches/290-mt7981-add-USB-nodes.patch
View file

@ -1,71 +0,0 @@
From cca5775031e4890f195246772e00f7f4ae7438f6 Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Mon, 19 Feb 2024 05:52:24 +0100
Subject: [PATCH 1/2] mt7981.dtsi: add USB nodes
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/arm/dts/mt7981.dtsi | 47 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 47 insertions(+)
--- a/arch/arm/dts/mt7981.dtsi
+++ b/arch/arm/dts/mt7981.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy.h>
#include <dt-bindings/clock/mt7981-clk.h>
#include <dt-bindings/reset/mt7629-reset.h>
#include <dt-bindings/pinctrl/mt65xx.h>
@@ -346,4 +347,50 @@
status = "disabled";
};
+ xhci: xhci@11200000 {
+ compatible = "mediatek,mt7981-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0x11200000 0x2e00>,
+ <0x11203e00 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u3port0 PHY_TYPE_USB3>;
+ clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
+ <&infracfg CLK_INFRA_IUSB_CK>,
+ <&infracfg CLK_INFRA_IUSB_133_CK>,
+ <&infracfg CLK_INFRA_IUSB_66M_CK>,
+ <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
+ clock-names = "sys_ck",
+ "ref_ck",
+ "mcu_ck",
+ "dma_ck",
+ "xhci_ck";
+ mediatek,u3p-dis-msk = <0x1>;
+ status = "okay";
+ };
+
+ usbtphy: usb-phy@11e10000 {
+ compatible = "mediatek,mt7981",
+ "mediatek,generic-tphy-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "okay";
+
+ u2port0: usb-phy@11e10000 {
+ reg = <0x11e10000 0x700>;
+ clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ u3port0: usb-phy@11e10700 {
+ reg = <0x11e10700 0x900>;
+ clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
};

6
package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch
View file

@ -48,9 +48,9 @@
#ifdef CONFIG_ENABLE_NAND_NMBM
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -155,4 +155,11 @@ config MTK_BROM_HEADER_INFO
source "board/mediatek/mt7629/Kconfig"
@@ -170,4 +170,11 @@ config MTK_TZ_MOVABLE
select OF_SYSTEM_SETUP
bool
+config RESET_BUTTON_LABEL
+ string "Button to trigger factory reset"

4
package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch
View file

@ -331,14 +331,14 @@
+};
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1192,6 +1192,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
@@ -1134,6 +1134,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7622-rfb.dtb \
mt7623a-unielec-u7623-02-emmc.dtb \
mt7622-bananapi-bpi-r64.dtb \
+ mt7622-linksys-e8450-ubi.dtb \
mt7623n-bananapi-bpi-r2.dtb \
mt7629-rfb.dtb \
mt7981-rfb.dtb \
mt7981-snfi-nand-rfb.dtb \
--- /dev/null
+++ b/defenvs/linksys_e8450_env
@@ -0,0 +1,55 @@

8
package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch
View file

@ -742,15 +742,15 @@
+};
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1193,6 +1193,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
@@ -1135,6 +1135,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7623a-unielec-u7623-02-emmc.dtb \
mt7622-bananapi-bpi-r64.dtb \
mt7622-linksys-e8450-ubi.dtb \
+ mt7622-ubnt-unifi-6-lr.dtb \
+ mt7622-ubnt-unifi-6-lr-v3.dtb \
mt7623n-bananapi-bpi-r2.dtb \
mt7629-rfb.dtb \
mt7981-rfb.dtb \
mt7981-snfi-nand-rfb.dtb \
--- /dev/null
+++ b/defenvs/ubnt_unifi-6-lr_env
@@ -0,0 +1,50 @@
@ -920,7 +920,7 @@
DECLARE_GLOBAL_DATA_PTR;
@@ -405,6 +406,20 @@ static int initr_onenand(void)
@@ -402,6 +403,20 @@ static int initr_onenand(void)
}
#endif
@ -941,7 +941,7 @@
#ifdef CONFIG_MMC
static int initr_mmc(void)
{
@@ -711,6 +726,9 @@ static init_fnc_t init_sequence_r[] = {
@@ -710,6 +725,9 @@ static init_fnc_t init_sequence_r[] = {
#ifdef CONFIG_NMBM_MTD
initr_nmbm,
#endif

12
package/boot/uboot-mediatek/patches/429-add-netcore-n60.patch
View file

@ -165,13 +165,13 @@
+ factory {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 9 GPIO_ACTIVE_LOW>;
+ };
+
+ wps {
+ label = "wps";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 10 GPIO_ACTIVE_LOW>;
+ };
+ };
+
@ -180,12 +180,12 @@
+
+ status_red {
+ label = "red:status";
+ gpios = <&gpio 29 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 29 GPIO_ACTIVE_LOW>;
+ };
+
+ status_green {
+ label = "green:status";
+ gpios = <&gpio 32 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 32 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
@ -206,7 +206,7 @@
+ mediatek,gmac-id = <0>;
+ phy-mode = "2500base-x";
+ mediatek,switch = "mt7531";
+ reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
+
+ fixed-link {
+ speed = <2500>;
@ -214,7 +214,7 @@
+ };
+};
+
+&pinctrl {
+&pio {
+ spi_flash_pins: spi0-pins-func-1 {
+ mux {
+ function = "flash";

8
package/boot/uboot-mediatek/patches/431-add-xiaomi_redmi-ax6000.patch
View file

@ -139,12 +139,12 @@
+ compatible = "gpio-keys";
+ factory {
+ label = "reset";
+ gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 9 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ mesh {
+ label = "mesh";
+ gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 10 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+ };
@ -166,7 +166,7 @@
+ mediatek,gmac-id = <0>;
+ phy-mode = "2500base-x";
+ mediatek,switch = "mt7531";
+ reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
+
+ fixed-link {
+ speed = <2500>;
@ -174,7 +174,7 @@
+ };
+};
+
+&pinctrl {
+&pio {
+ spic_pins: spi1-pins-func-1 {
+ mux {
+ function = "spi";

16
package/boot/uboot-mediatek/patches/432-add-tplink-xdr608x.patch
View file

@ -427,19 +427,19 @@
+ factory {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 9 GPIO_ACTIVE_LOW>;
+ };
+
+ wps {
+ label = "wps";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 10 GPIO_ACTIVE_LOW>;
+ };
+
+ turbo {
+ label = "turbo";
+ linux,code = <BTN_1>;
+ gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 11 GPIO_ACTIVE_LOW>;
+ };
+ };
+
@ -448,17 +448,17 @@
+
+ status_red {
+ label = "red:status";
+ gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
+ gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
+ };
+
+ status_green {
+ label = "green:status";
+ gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
+ gpios = <&pio 8 GPIO_ACTIVE_HIGH>;
+ };
+
+ turbo {
+ label = "green:turbo";
+ gpios = <&gpio 12 GPIO_ACTIVE_HIGH>;
+ gpios = <&pio 12 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
@ -479,7 +479,7 @@
+ mediatek,gmac-id = <0>;
+ phy-mode = "2500base-x";
+ mediatek,switch = "mt7531";
+ reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
+
+ fixed-link {
+ speed = <2500>;
@ -487,7 +487,7 @@
+ };
+};
+
+&pinctrl {
+&pio {
+ spi_flash_pins: spi0-pins-func-1 {
+ mux {
+ function = "flash";

12
package/boot/uboot-mediatek/patches/433-add-qihoo_360t7.patch
View file

@ -160,13 +160,13 @@
+ factory {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+ };
+
+ wps {
+ label = "wps";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 0 GPIO_ACTIVE_LOW>;
+ };
+ };
+
@ -175,12 +175,12 @@
+
+ status_red {
+ label = "red:status";
+ gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 3 GPIO_ACTIVE_LOW>;
+ };
+
+ status_green {
+ label = "green:status";
+ gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 7 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
@ -201,7 +201,7 @@
+ mediatek,gmac-id = <0>;
+ phy-mode = "2500base-x";
+ mediatek,switch = "mt7531";
+ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
+
+ fixed-link {
+ speed = <2500>;
@ -209,7 +209,7 @@
+ };
+};
+
+&pinctrl {
+&pio {
+ spi_flash_pins: spi0-pins-func-1 {
+ mux {
+ function = "flash";

16
package/boot/uboot-mediatek/patches/434-add-xiaomi_mi-router-wr30u.patch
View file

@ -164,13 +164,13 @@
+
+ reset {
+ label = "reset";
+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+
+ mesh {
+ label = "mesh";
+ gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 0 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_9>;
+ linux,input-type = <EV_SW>;
+ };
@ -181,22 +181,22 @@
+
+ led_system_blue {
+ label = "blue:system";
+ gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 9 GPIO_ACTIVE_LOW>;
+ };
+
+ led_system_yellow {
+ label = "yellow:system";
+ gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 10 GPIO_ACTIVE_LOW>;
+ };
+
+ led_network_blue {
+ label = "blue:network";
+ gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 11 GPIO_ACTIVE_LOW>;
+ };
+
+ led_network_yellow {
+ label = "yellow:network";
+ gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 12 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
@ -217,7 +217,7 @@
+ mediatek,gmac-id = <0>;
+ phy-mode = "sgmii";
+ mediatek,switch = "mt7531";
+ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
+
+ fixed-link {
+ speed = <1000>;
@ -225,7 +225,7 @@
+ };
+};
+
+&pinctrl {
+&pio {
+ spi_flash_pins: spi0-pins-func-1 {
+ mux {
+ function = "flash";

12
package/boot/uboot-mediatek/patches/435-add-h3c_magic-nx30-pro.patch
View file

@ -160,13 +160,13 @@
+ factory {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+ };
+
+ wps {
+ label = "wps";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 0 GPIO_ACTIVE_LOW>;
+ };
+ };
+
@ -175,12 +175,12 @@
+
+ status_red {
+ label = "red:status";
+ gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 4 GPIO_ACTIVE_LOW>;
+ };
+
+ status_green {
+ label = "green:status";
+ gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 5 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
@ -201,7 +201,7 @@
+ mediatek,gmac-id = <0>;
+ phy-mode = "2500base-x";
+ mediatek,switch = "mt7531";
+ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
+
+ fixed-link {
+ speed = <2500>;
@ -209,7 +209,7 @@
+ };
+};
+
+&pinctrl {
+&pio {
+ spi_flash_pins: spi0-pins-func-1 {
+ mux {
+ function = "flash";

10
package/boot/uboot-mediatek/patches/436-add-glinet-mt6000.patch
View file

@ -46,7 +46,7 @@
+
+ wps {
+ label = "reset";
+ gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 9 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
@ -56,12 +56,12 @@
+
+ led_status_blue: green {
+ label = "blue:status";
+ gpios = <&gpio 28 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 28 GPIO_ACTIVE_LOW>;
+ };
+
+ led_status_white: blue {
+ label = "white:status";
+ gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 27 GPIO_ACTIVE_LOW>;
+ };
+ };
+
@ -77,7 +77,7 @@
+ mediatek,gmac-id = <0>;
+ phy-mode = "2500base-x";
+ mediatek,switch = "mt7531";
+ reset-gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 18 GPIO_ACTIVE_HIGH>;
+
+ fixed-link {
+ speed = <2500>;
@ -85,7 +85,7 @@
+ };
+};
+
+&pinctrl {
+&pio {
+ mmc0_pins_default: mmc0default {
+ mux {
+ function = "flash";

16
package/boot/uboot-mediatek/patches/437-add-cmcc_rax3000m.patch
View file

@ -286,14 +286,14 @@
+ button-reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+ };
+
+ button-mesh {
+ label = "mesh";
+ linux,code = <BTN_9>;
+ linux,input-type = <EV_SW>;
+ gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 0 GPIO_ACTIVE_LOW>;
+ };
+ };
+
@ -302,17 +302,17 @@
+
+ led-0 {
+ label = "green:status";
+ gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 9 GPIO_ACTIVE_LOW>;
+ };
+
+ led-1 {
+ label = "blue:status";
+ gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 12 GPIO_ACTIVE_LOW>;
+ };
+
+ led-2 {
+ label = "red:status";
+ gpios = <&gpio 35 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 35 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
@ -322,7 +322,7 @@
+ mediatek,gmac-id = <0>;
+ phy-mode = "2500base-x";
+ mediatek,switch = "mt7531";
+ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
+
+ fixed-link {
+ speed = <2500>;
@ -368,7 +368,7 @@
+ status = "okay";
+};
+
+&pinctrl {
+&pio {
+ mmc0_pins_default: mmc0default {
+ mux {
+ function = "flash";
@ -402,7 +402,7 @@
+/dts-v1/;
+#include "mt7981-cmcc-rax3000m.dtsi"
+
+&pinctrl {
+&pio {
+ spi_flash_pins: spi0-pins-func-1 {
+ mux {
+ function = "flash";

10
package/boot/uboot-mediatek/patches/438-add-jcg_q30-pro.patch
View file

@ -160,7 +160,7 @@
+ factory {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+ };
+ };
+
@ -169,12 +169,12 @@
+
+ status_red {
+ label = "red:status";
+ gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
+ gpios = <&pio 8 GPIO_ACTIVE_HIGH>;
+ };
+
+ status_blue {
+ label = "blue:status";
+ gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 13 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
@ -195,7 +195,7 @@
+ mediatek,gmac-id = <0>;
+ phy-mode = "2500base-x";
+ mediatek,switch = "mt7531";
+ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
+
+ fixed-link {
+ speed = <2500>;
@ -203,7 +203,7 @@
+ };
+};
+
+&pinctrl {
+&pio {
+ spi_flash_pins: spi0-pins-func-1 {
+ mux {
+ function = "flash";

12
package/boot/uboot-mediatek/patches/439-add-zyxel_ex5601-t0.patch
View file

@ -163,13 +163,13 @@
+ compatible = "gpio-keys";
+ factory {
+ label = "reset";
+ gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 21 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+
+ wps {
+ label = "wps";
+ gpios = <&gpio 56 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 56 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+ };
@ -179,13 +179,13 @@
+
+ led_status_green: pwr {
+ label = "green:status";
+ gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
+ gpios = <&pio 13 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led_sfp_green: sfp {
+ label = "green:sfp";
+ gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
+ gpios = <&pio 24 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
@ -207,7 +207,7 @@
+ mediatek,gmac-id = <0>;
+ phy-mode = "2500base-x";
+ mediatek,switch = "mt7531";
+ reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
+
+ fixed-link {
+ speed = <2500>;
@ -215,7 +215,7 @@
+ };
+};
+
+&pinctrl {
+&pio {
+ spic_pins: spi1-pins-func-1 {
+ mux {
+ function = "spi";

12
package/boot/uboot-mediatek/patches/440-add-xiaomi_mi-router-ax3000t.patch
View file

@ -143,13 +143,13 @@
+
+ reset {
+ label = "reset";
+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+
+ mesh {
+ label = "mesh";
+ gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 0 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_9>;
+ linux,input-type = <EV_SW>;
+ };
@ -160,12 +160,12 @@
+
+ led_status_blue {
+ label = "blue:status";
+ gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 9 GPIO_ACTIVE_LOW>;
+ };
+
+ led_status_yellow {
+ label = "yellow:status";
+ gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 10 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
@ -180,7 +180,7 @@
+ mediatek,gmac-id = <0>;
+ phy-mode = "2500base-x";
+ mediatek,switch = "auto";
+ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
+
+ fixed-link {
+ speed = <2500>;
@ -188,7 +188,7 @@
+ };
+};
+
+&pinctrl {
+&pio {
+ spic_pins: spi1-pins-func-1 {
+ mux {
+ function = "spi";

14
package/boot/uboot-mediatek/patches/441-add-jdcloud_re-cp-03.patch
View file

@ -143,13 +143,13 @@
+ button-joylink {
+ label = "joylink";
+ linux,code = <BTN_0>;
+ gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 10 GPIO_ACTIVE_LOW>;
+ };
+
+ button-reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 9 GPIO_ACTIVE_LOW>;
+ };
+ };
+
@ -158,19 +158,19 @@
+
+ led-0 {
+ label = "blue:status";
+ gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
+ gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-1 {
+ label = "red:status";
+ gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
+ gpios = <&pio 11 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ led-2 {
+ label = "green:status";
+ gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 12 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
@ -199,7 +199,7 @@
+ mediatek,gmac-id = <0>;
+ phy-mode = "2500base-x";
+ mediatek,switch = "mt7531";
+ reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
+
+ fixed-link {
+ speed = <2500>;
@ -220,7 +220,7 @@
+ status = "okay";
+};
+
+&pinctrl {
+&pio {
+ mmc0_pins_default: mmc0default {
+ mux {
+ function = "flash";

12
package/boot/uboot-mediatek/patches/442-add-bpi-r3-mini.patch
View file

@ -443,7 +443,7 @@
+ button-reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 7 GPIO_ACTIVE_LOW>;
+ };
+ };
+
@ -452,17 +452,17 @@
+
+ status_led: led-0 {
+ label = "green:status";
+ gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
+ gpios = <&pio 19 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-1 {
+ label = "blue:wlan2g";
+ gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
+ gpios = <&pio 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-2 {
+ label = "blue:wlan5g";
+ gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
+ gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
@ -500,7 +500,7 @@
+
+ airoha,rx-pol-reverse;
+
+ reset-gpios = <&gpio 49 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <20000>;
+ };
@ -519,7 +519,7 @@
+ status = "okay";
+};
+
+&pinctrl {
+&pio {
+ mdio_pins: mdio-pins {
+ mux {
+ function = "eth";

20
package/boot/uboot-mediatek/patches/443-add-nokia_ea0326gmp.patch
View file

@ -141,13 +141,13 @@
+ button-reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+ };
+
+ button-wps {
+ label = "wps";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 0 GPIO_ACTIVE_LOW>;
+ };
+ };
+
@ -156,37 +156,37 @@
+
+ power_led: led-0 {
+ label = "green:power";
+ gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 4 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ };
+
+ led-1 {
+ label = "green:wan";
+ gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 5 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-2 {
+ label = "red:wan";
+ gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 6 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-3 {
+ label = "green:lan";
+ gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 7 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-4 {
+ label = "green:wlan";
+ gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 8 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-5 {
+ label = "green:wps";
+ gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 9 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
@ -197,7 +197,7 @@
+ mediatek,gmac-id = <0>;
+ phy-mode = "2500base-x";
+ mediatek,switch = "mt7531";
+ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
+
+ fixed-link {
+ speed = <2500>;
@ -205,7 +205,7 @@
+ };
+};
+
+&pinctrl {
+&pio {
+ spi_flash_pins: spi0-pins-func-1 {
+ mux {
+ function = "flash";

21
package/boot/uboot-mediatek/patches/444-add-abt_asr3000.patch
View file

@ -110,7 +110,7 @@
+CONFIG_HEXDUMP=y
--- /dev/null
+++ b/arch/arm/dts/mt7981-abt-asr3000.dts
@@ -0,0 +1,176 @@
@@ -0,0 +1,175 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/dts-v1/;
@ -137,18 +137,17 @@
+ gpio-keys {
+ compatible = "gpio-keys";
+
+
+ button-reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+ };
+
+ button-wps {
+ label = "mesh";
+ linux,code = <BTN_9>;
+ linux,input-type = <EV_SW>;
+ gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 0 GPIO_ACTIVE_LOW>;
+ };
+ };
+
@ -157,31 +156,31 @@
+
+ led-0 {
+ label = "red:wan";
+ gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 4 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-1 {
+ label = "green:wan";
+ gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 8 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ mesh_led: led-2 {
+ label = "green:mesh";
+ gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
+ gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ led-3 {
+ label = "green:wlan2g";
+ gpios = <&gpio 34 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 34 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-4 {
+ label = "green:wlan5g";
+ gpios = <&gpio 35 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 35 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
@ -192,7 +191,7 @@
+ mediatek,gmac-id = <0>;
+ phy-mode = "2500base-x";
+ mediatek,switch = "mt7531";
+ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
+
+ fixed-link {
+ speed = <2500>;
@ -200,7 +199,7 @@
+ };
+};
+
+&pinctrl {
+&pio {
+ spi_flash_pins: spi0-pins-func-1 {
+ mux {
+ function = "flash";

16
package/boot/uboot-mediatek/patches/445-add-netis-nx31.patch
View file

@ -143,13 +143,13 @@
+ button-0 {
+ label = "mesh";
+ linux,code = <BTN_0>;
+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+ };
+
+ button-1 {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+ };
+ };
+
@ -158,22 +158,22 @@
+
+ led-0 {
+ label = "blue:wlan2g";
+ gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 5 GPIO_ACTIVE_LOW>;
+ };
+
+ led-1 {
+ label = "blue:status";
+ gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 7 GPIO_ACTIVE_LOW>;
+ };
+
+ led-2 {
+ label = "blue:wan";
+ gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 8 GPIO_ACTIVE_LOW>;
+ };
+
+ led-3 {
+ label = "blue:wlan5g";
+ gpios = <&gpio 34 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 34 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
@ -188,7 +188,7 @@
+ mediatek,gmac-id = <0>;
+ phy-mode = "2500base-x";
+ mediatek,switch = "mt7531";
+ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
+
+ fixed-link {
+ speed = <2500>;
@ -196,7 +196,7 @@
+ };
+};
+
+&pinctrl {
+&pio {
+ spi_flash_pins: spi0-pins-func-1 {
+ mux {
+ function = "flash";

14
package/boot/uboot-mediatek/patches/446-add-cmcc_a10.patch
View file

@ -139,13 +139,13 @@
+ button-reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+ };
+
+ button-wps {
+ label = "wps";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 0 GPIO_ACTIVE_LOW>;
+ };
+ };
+
@ -154,19 +154,19 @@
+
+ led-0 {
+ label = "blue:status";
+ gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 9 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ running_led: led-1 {
+ label = "green:status";
+ gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 10 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ boot_led: led-2 {
+ label = "red:status";
+ gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 11 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ };
+ };
@ -177,7 +177,7 @@
+ mediatek,gmac-id = <0>;
+ phy-mode = "2500base-x";
+ mediatek,switch = "mt7531";
+ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
+
+ fixed-link {
+ speed = <2500>;
@ -185,7 +185,7 @@
+ };
+};
+
+&pinctrl {
+&pio {
+ spi_flash_pins: spi0-pins-func-1 {
+ mux {
+ function = "flash";

8
package/boot/uboot-mediatek/patches/450-add-bpi-r4.patch
View file

@ -671,7 +671,7 @@
+ wps {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 14 GPIO_ACTIVE_LOW>;
+ };
+ };
+
@ -680,12 +680,12 @@
+
+ led_status_green: led-green {
+ label = "green:status";
+ gpios = <&gpio 79 GPIO_ACTIVE_HIGH>;
+ gpios = <&pio 79 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_status_blue: led-blue {
+ label = "blue:status";
+ gpios = <&gpio 63 GPIO_ACTIVE_HIGH>;
+ gpios = <&pio 63 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
@ -713,7 +713,7 @@
+ };
+};
+
+&pinctrl {
+&pio {
+ i2c1_pins: i2c1-pins {
+ mux {
+ function = "i2c";

16
package/boot/uboot-mediatek/patches/451-add-tplink-xtr8488.patch
View file

@ -165,19 +165,19 @@
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 15 GPIO_ACTIVE_LOW>;
+ };
+
+ wps {
+ label = "wps";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 16 GPIO_ACTIVE_LOW>;
+ };
+
+ turbo {
+ label = "turbo";
+ linux,code = <BTN_1>;
+ gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 11 GPIO_ACTIVE_LOW>;
+ };
+ };
+
@ -186,17 +186,17 @@
+
+ status_red {
+ label = "red:status";
+ gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
+ gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
+ };
+
+ status_green {
+ label = "green:status";
+ gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
+ gpios = <&pio 8 GPIO_ACTIVE_HIGH>;
+ };
+
+ turbo {
+ label = "green:turbo";
+ gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 12 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
@ -217,7 +217,7 @@
+ mediatek,gmac-id = <0>;
+ phy-mode = "2500base-x";
+ mediatek,switch = "mt7531";
+ reset-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 6 GPIO_ACTIVE_HIGH>;
+
+ fixed-link {
+ speed = <2500>;
@ -225,7 +225,7 @@
+ };
+};
+
+&pinctrl {
+&pio {
+ spi_flash_pins: spi0-pins-func-1 {
+ mux {
+ function = "flash";

4
package/boot/uboot-mediatek/patches/452-add-xiaomi-redmi-ax6s.patch
View file

@ -15,14 +15,14 @@ Subject: [PATCH] add xiaomi redmi ax6s
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1195,6 +1195,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
@@ -1137,6 +1137,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7622-linksys-e8450-ubi.dtb \
mt7622-ubnt-unifi-6-lr.dtb \
mt7622-ubnt-unifi-6-lr-v3.dtb \
+ mt7622-xiaomi-redmi-router-ax6s.dtb \
mt7623n-bananapi-bpi-r2.dtb \
mt7629-rfb.dtb \
mt7981-rfb.dtb \
mt7981-snfi-nand-rfb.dtb \
--- /dev/null
+++ b/arch/arm/dts/mt7622-xiaomi-redmi-router-ax6s.dts
@@ -0,0 +1,166 @@

12
package/boot/uboot-mediatek/patches/453-add-openwrt-one.patch
View file

@ -31,13 +31,13 @@
+
+ user {
+ label = "front";
+ gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 0 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_0>;
+ };
+
+ reset {
+ label = "back";
+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_1>;
+ };
+ };
@ -47,17 +47,17 @@
+
+ red {
+ label = "red";
+ gpios = <&gpio 9 GPIO_ACTIVE_HIGH>;
+ gpios = <&pio 9 GPIO_ACTIVE_HIGH>;
+ };
+
+ white {
+ label = "white";
+ gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
+ gpios = <&pio 13 GPIO_ACTIVE_HIGH>;
+ };
+
+ green {
+ label = "green";
+ gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
+ gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
@ -78,7 +78,7 @@
+ };
+};
+
+&pinctrl {
+&pio {
+ spi_flash_pins: spi0-pins-func-1 {
+ mux {
+ function = "flash";

20
package/boot/uboot-mediatek/patches/454-add-glinet-x3000.patch
View file

@ -39,7 +39,7 @@
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+ };
+ };
+
@ -48,42 +48,42 @@
+
+ wifi2g {
+ label = "green:wifi2g";
+ gpios = <&gpio 30 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 30 GPIO_ACTIVE_LOW>;
+ };
+
+ wifi5g {
+ label = "green:wifi5g";
+ gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 38 GPIO_ACTIVE_LOW>;
+ };
+
+ 5g_led1 {
+ label = "green:5g:led1";
+ gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 6 GPIO_ACTIVE_LOW>;
+ };
+
+ 5g_led2 {
+ label = "green:5g:led2";
+ gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 7 GPIO_ACTIVE_LOW>;
+ };
+
+ 5g_led3 {
+ label = "green:5g:led3";
+ gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 8 GPIO_ACTIVE_LOW>;
+ };
+
+ 5g_led4 {
+ label = "green:5g:led4";
+ gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;
+ gpios = <&pio 4 GPIO_ACTIVE_HIGH>;
+ };
+
+ power {
+ label = "green:power";
+ gpios = <&gpio 39 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 39 GPIO_ACTIVE_LOW>;
+ };
+
+ wan {
+ label = "green:wan";
+ gpios = <&gpio 31 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 31 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
@ -115,7 +115,7 @@
+ status = "okay";
+};
+
+&pinctrl {
+&pio {
+ mmc0_pins_default: mmc0-pins-default {
+ mux {
+ function = "flash";

10
package/boot/uboot-mediatek/patches/456-add-arcadyan-mozart.patch
View file

@ -224,7 +224,7 @@
+ wps {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio 143 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 143 GPIO_ACTIVE_LOW>;
+ };
+ };
+
@ -233,17 +233,17 @@
+
+ led-red {
+ label = "red:status";
+ gpios = <&gpio 29 GPIO_ACTIVE_HIGH>;
+ gpios = <&pio 29 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-green {
+ label = "blue:status";
+ gpios = <&gpio 30 GPIO_ACTIVE_HIGH>;
+ gpios = <&pio 30 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-blue {
+ label = "blue:status";
+ gpios = <&gpio 31 GPIO_ACTIVE_HIGH>;
+ gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
@ -265,7 +265,7 @@
+ };
+};
+
+&pinctrl {
+&pio {
+ mmc0_pins_default: mmc0default {
+ mux {
+ function = "flash";

6
package/boot/uboot-mediatek/patches/457-initialized-the-watchdog-subsystem-later.patch
View file

@ -13,7 +13,7 @@ Signed-off-by: Enrico Mioso <mrkiko.rs@gmail.com>
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -682,19 +682,13 @@ static init_fnc_t init_sequence_r[] = {
@@ -681,19 +681,13 @@ static init_fnc_t init_sequence_r[] = {
serial_initialize,
initr_announce,
dm_announce,
@ -33,7 +33,7 @@ Signed-off-by: Enrico Mioso <mrkiko.rs@gmail.com>
#if defined(CONFIG_PCI_INIT_R) && defined(CONFIG_SYS_EARLY_PCI_INIT)
/*
* Do early PCI configuration _before_ the flash gets initialised,
@@ -709,7 +703,6 @@ static init_fnc_t init_sequence_r[] = {
@@ -708,7 +702,6 @@ static init_fnc_t init_sequence_r[] = {
#ifdef CONFIG_MTD_NOR_FLASH
initr_flash,
#endif
@ -41,7 +41,7 @@ Signed-off-by: Enrico Mioso <mrkiko.rs@gmail.com>
#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_X86)
/* initialize higher level parts of CPU like time base and timers */
cpu_init_r,
@@ -738,6 +731,10 @@ static init_fnc_t init_sequence_r[] = {
@@ -737,6 +730,10 @@ static init_fnc_t init_sequence_r[] = {
#ifdef CONFIG_PVBLOCK
initr_pvblock,
#endif

24
package/boot/uboot-mediatek/patches/458-add-GatoNetworks-GDSP.patch
View file

@ -44,7 +44,7 @@ Signed-off-by: Enrico Mioso <mrkiko.rs@gmail.com>
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+ };
+ };
+
@ -53,47 +53,47 @@ Signed-off-by: Enrico Mioso <mrkiko.rs@gmail.com>
+
+ sim1 {
+ label = "sim1";
+ gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 13 GPIO_ACTIVE_LOW>;
+ };
+
+ sim2 {
+ label = "sim2";
+ gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 0 GPIO_ACTIVE_LOW>;
+ };
+
+ sg1 {
+ label = "sg1";
+ gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 10 GPIO_ACTIVE_LOW>;
+ };
+
+ sg2 {
+ label = "sg2";
+ gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 11 GPIO_ACTIVE_LOW>;
+ };
+
+ sg3 {
+ label = "sg3";
+ gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 12 GPIO_ACTIVE_LOW>;
+ };
+
+ sg4 {
+ label = "sg4";
+ gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 7 GPIO_ACTIVE_LOW>;
+ };
+
+ sg5 {
+ label = "sg5";
+ gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 8 GPIO_ACTIVE_LOW>;
+ };
+
+ sg6 {
+ label = "sg6";
+ gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 9 GPIO_ACTIVE_LOW>;
+ };
+ };
+ gpio-watchdog {
+ compatible = "linux,wdt-gpio";
+ gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 6 GPIO_ACTIVE_LOW>;
+ hw_algo = "toggle";
+ hw_margin_ms = <25000>;
+ always-running;
@ -106,7 +106,7 @@ Signed-off-by: Enrico Mioso <mrkiko.rs@gmail.com>
+ mediatek,gmac-id = <0>;
+ phy-mode = "2500base-x";
+ mediatek,switch = "mt7531";
+ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
+
+ fixed-link {
+ speed = <2500>;
@ -166,7 +166,7 @@ Signed-off-by: Enrico Mioso <mrkiko.rs@gmail.com>
+ };
+};
+
+&pinctrl {
+&pio {
+ uart1_pins: uart1-pins {
+ mux {
+ function = "uart";

18
package/boot/uboot-mediatek/patches/459-add-mercusys-mr90x-v1.patch
View file

@ -144,7 +144,7 @@
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 10 GPIO_ACTIVE_LOW>;
+ };
+ };
+
@ -153,32 +153,32 @@
+
+ led-0 {
+ label = "green:lan2";
+ gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 7 GPIO_ACTIVE_LOW>;
+ };
+
+ led-1 {
+ label = "green:lan1";
+ gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 9 GPIO_ACTIVE_LOW>;
+ };
+
+ led-2 {
+ label = "green:lan0";
+ gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 12 GPIO_ACTIVE_LOW>;
+ };
+
+ led-3 {
+ label = "green:wan";
+ gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 13 GPIO_ACTIVE_LOW>;
+ };
+
+ led-4 {
+ label = "amber:status";
+ gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
+ gpios = <&pio 16 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_status_green: led-5 {
+ label = "green:status";
+ gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
+ gpios = <&pio 17 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
@ -198,7 +198,7 @@
+ mediatek,gmac-id = <0>;
+ phy-mode = "2500base-x";
+ mediatek,switch = "mt7531";
+ reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
+
+ fixed-link {
+ speed = <2500>;
@ -206,7 +206,7 @@
+ };
+};
+
+&pinctrl {
+&pio {
+ spi_flash_pins: spi0-pins-func-1 {
+ mux {
+ function = "flash";

26
package/boot/uboot-mediatek/patches/460-add-routerich-ax3000.patch
View file

@ -143,13 +143,13 @@
+ button-0 {
+ label = "mesh";
+ linux,code = <BTN_0>;
+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+ };
+
+ button-1 {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+ };
+ };
+
@ -158,47 +158,47 @@
+
+ led-0 {
+ label = "red:wlan5g";
+ gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 5 GPIO_ACTIVE_LOW>;
+ };
+
+ led-1 {
+ label = "red:wan";
+ gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;
+ gpios = <&pio 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-2 {
+ label = "blue:power";
+ gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 7 GPIO_ACTIVE_LOW>;
+ };
+
+ led-3 {
+ label = "blue:lan1";
+ gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 9 GPIO_ACTIVE_LOW>;
+ };
+
+ led-4 {
+ label = "blue:lan2";
+ gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 10 GPIO_ACTIVE_LOW>;
+ };
+
+ led-5 {
+ label = "blue:lan3";
+ gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 11 GPIO_ACTIVE_LOW>;
+ };
+
+ led-6 {
+ label = "blue:wan";
+ gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 12 GPIO_ACTIVE_LOW>;
+ };
+
+ led-7 {
+ label = "blue:wlan2g";
+ gpios = <&gpio 34 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 34 GPIO_ACTIVE_LOW>;
+ };
+
+ led-8 {
+ label = "blue:mesh";
+ gpios = <&gpio 35 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 35 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
@ -213,7 +213,7 @@
+ mediatek,gmac-id = <0>;
+ phy-mode = "2500base-x";
+ mediatek,switch = "mt7531";
+ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
+
+ fixed-link {
+ speed = <2500>;
@ -221,7 +221,7 @@
+ };
+};
+
+&pinctrl {
+&pio {
+ spi_flash_pins: spi0-pins-func-1 {
+ mux {
+ function = "flash";

25
package/boot/uboot-mediatek/patches/461-add-asus-zenwifi-bt8.patch
View file

@ -1,6 +1,6 @@
--- /dev/null
+++ b/configs/mt7988a_asus_zenwifi-bt8_defconfig
@@ -0,0 +1,133 @@
@@ -0,0 +1,130 @@
+CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_POSITION_INDEPENDENT=y
@ -11,10 +11,10 @@
+CONFIG_DEFAULT_DEVICE_TREE="mt7988a-asus-zenwifi-bt8"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_TARGET_MT7988=y
+CONFIG_SYS_LOAD_ADDR=0x50000000
+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
+CONFIG_DEBUG_UART_BASE=0x11000000
+CONFIG_DEBUG_UART_CLOCK=40000000
+CONFIG_SYS_LOAD_ADDR=0x50000000
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
@ -50,14 +50,14 @@
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_PXE=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PSTORE=y
@ -88,8 +88,6 @@
+CONFIG_IPADDR="192.168.1.1"
+CONFIG_USE_SERVERIP=y
+CONFIG_SERVERIP="192.168.1.254"
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_GPIO=y
+CONFIG_CLK=y
@ -133,7 +131,6 @@
+CONFIG_USB_STORAGE=y
+CONFIG_ZSTD=y
+CONFIG_HEXDUMP=y
+CONFIG_LMB_MAX_REGIONS=64
--- /dev/null
+++ b/asus_zenwifi-bt8_env
@@ -0,0 +1,56 @@
@ -244,13 +241,13 @@
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 13 GPIO_ACTIVE_LOW>;
+ };
+
+ wps {
+ label = "wps";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 14 GPIO_ACTIVE_LOW>;
+ };
+ };
+
@ -259,17 +256,17 @@
+
+ led_status_red: led-red {
+ label = "red:status";
+ gpios = <&gpio 57 GPIO_ACTIVE_HIGH>;
+ gpios = <&pio 57 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_status_green: led-green {
+ label = "green:status";
+ gpios = <&gpio 21 GPIO_ACTIVE_HIGH>;
+ gpios = <&pio 21 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_status_blue: led-blue {
+ label = "blue:status";
+ gpios = <&gpio 59 GPIO_ACTIVE_HIGH>;
+ gpios = <&pio 59 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
@ -291,7 +288,7 @@
+ };
+};
+
+&pinctrl {
+&pio {
+ spi0_pins: spi0-pins {
+ mux {
+ function = "spi";

19
package/boot/uboot-mediatek/patches/462-add-netcore-n60-pro.patch
View file

@ -1,3 +1,4 @@
Add test header.
--- /dev/null
+++ b/configs/mt7986_netcore_n60-pro_defconfig
@@ -0,0 +1,128 @@
@ -165,13 +166,13 @@
+ button-reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 9 GPIO_ACTIVE_LOW>;
+ };
+
+ button-mesh {
+ label = "mesh";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 10 GPIO_ACTIVE_LOW>;
+ };
+ };
+
@ -180,27 +181,27 @@
+
+ led-0 {
+ label = "blue:wlan";
+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+ };
+
+ power_led: led-1 {
+ label = "blue:power";
+ gpios = <&gpio 29 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 29 GPIO_ACTIVE_LOW>;
+ };
+
+ led-2 {
+ label = "blue:status";
+ gpios = <&gpio 30 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 30 GPIO_ACTIVE_LOW>;
+ };
+
+ led-3 {
+ label = "blue:mesh";
+ gpios = <&gpio 31 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 31 GPIO_ACTIVE_LOW>;
+ };
+
+ led-4 {
+ label = "blue:wan";
+ gpios = <&gpio 32 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 32 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
@ -221,7 +222,7 @@
+ mediatek,gmac-id = <0>;
+ phy-mode = "2500base-x";
+ mediatek,switch = "mt7531";
+ reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
+
+ fixed-link {
+ speed = <2500>;
@ -229,7 +230,7 @@
+ };
+};
+
+&pinctrl {
+&pio {
+ spi_flash_pins: spi0-pins-func-1 {
+ mux {
+ function = "flash";