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ramips: gpio: always use dynamic GPIO numberspace base

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The new numberspace base starts from 512 instead of 0. The number
base seems come from the kernel symbol CONFIG_GPIOLIB_FASTPATH_LIMIT.

Suppress warning:

gpio gpiochip0: Static allocation of GPIO base is deprecated, use dynamic allocation.

Signed-off-by: Shiji Yang <yangshiji66@qq.com>
This commit is contained in:
Shiji Yang 2024-06-28 15:36:13 +08:00 committed by Hauke Mehrtens
parent 2f1ff5b4ce
commit 24459dc108
11 changed files with 32 additions and 72 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
target/linux/ramips/dts/mt7620a.dtsi
View file

@ -116,7 +116,6 @@
#gpio-cells = <2>;
ngpios = <24>;
ralink,gpio-base = <0>;
ralink,register-map = [ 00 04 08 0c
20 24 28 2c
30 34 ];
@ -133,7 +132,6 @@
#gpio-cells = <2>;
ngpios = <16>;
ralink,gpio-base = <24>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];
@ -152,7 +150,6 @@
#gpio-cells = <2>;
ngpios = <32>;
ralink,gpio-base = <40>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];
@ -171,7 +168,6 @@
#gpio-cells = <2>;
ngpios = <1>;
ralink,gpio-base = <72>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];

4
target/linux/ramips/dts/mt7620n.dtsi
View file

@ -100,7 +100,6 @@
#gpio-cells = <2>;
ngpios = <24>;
ralink,gpio-base = <0>;
ralink,register-map = [ 00 04 08 0c
20 24 28 2c
30 34 ];
@ -117,7 +116,6 @@
#gpio-cells = <2>;
ngpios = <16>;
ralink,gpio-base = <24>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];
@ -136,7 +134,6 @@
#gpio-cells = <2>;
ngpios = <32>;
ralink,gpio-base = <40>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];
@ -155,7 +152,6 @@
#gpio-cells = <2>;
ngpios = <1>;
ralink,gpio-base = <72>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];

3
target/linux/ramips/dts/rt2880.dtsi
View file

@ -88,7 +88,6 @@
#gpio-cells = <2>;
ngpios = <24>;
ralink,gpio-base = <0>;
ralink,register-map = [ 00 04 08 0c
20 24 28 2c
30 34 ];
@ -102,7 +101,6 @@
#gpio-cells = <2>;
ngpios = <16>;
ralink,gpio-base = <24>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];
@ -118,7 +116,6 @@
#gpio-cells = <2>;
ngpios = <32>;
ralink,gpio-base = <40>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];

3
target/linux/ramips/dts/rt3050.dtsi
View file

@ -112,7 +112,6 @@
#gpio-cells = <2>;
ngpios = <24>;
ralink,gpio-base = <0>;
ralink,register-map = [ 00 04 08 0c
20 24 28 2c
30 34 ];
@ -129,7 +128,6 @@
#gpio-cells = <2>;
ngpios = <16>;
ralink,gpio-base = <24>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];
@ -145,7 +143,6 @@
#gpio-cells = <2>;
ngpios = <12>;
ralink,gpio-base = <40>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];

3
target/linux/ramips/dts/rt3352.dtsi
View file

@ -113,7 +113,6 @@
#gpio-cells = <2>;
ngpios = <24>;
ralink,gpio-base = <0>;
ralink,register-map = [ 00 04 08 0c
20 24 28 2c
30 34 ];
@ -130,7 +129,6 @@
#gpio-cells = <2>;
ngpios = <16>;
ralink,gpio-base = <24>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];
@ -146,7 +144,6 @@
#gpio-cells = <2>;
ngpios = <6>;
ralink,gpio-base = <40>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];

4
target/linux/ramips/dts/rt3883.dtsi
View file

@ -116,7 +116,6 @@
#gpio-cells = <2>;
ngpios = <24>;
ralink,gpio-base = <0>;
ralink,register-map = [ 00 04 08 0c
20 24 28 2c
30 34 ];
@ -130,7 +129,6 @@
#gpio-cells = <2>;
ngpios = <16>;
ralink,gpio-base = <24>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];
@ -146,7 +144,6 @@
#gpio-cells = <2>;
ngpios = <32>;
ralink,gpio-base = <40>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];
@ -162,7 +159,6 @@
#gpio-cells = <2>;
ngpios = <24>;
ralink,gpio-base = <72>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];

2
target/linux/ramips/dts/rt5350.dtsi
View file

@ -116,7 +116,6 @@
#gpio-cells = <2>;
ngpios = <22>;
ralink,gpio-base = <0>;
ralink,register-map = [ 00 04 08 0c
20 24 28 2c
30 34 ];
@ -133,7 +132,6 @@
#gpio-cells = <2>;
ngpios = <6>;
ralink,gpio-base = <22>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];

26
target/linux/ramips/mt7620/base-files/etc/board.d/03_gpio_switches
View file

@ -7,30 +7,30 @@ board=$(board_name)
case "$board" in
bolt,bl100)
ucidef_add_gpio_switch "modem_enable" "Enable LTE Modem" "28" "1"
ucidef_add_gpio_switch "modem_enable" "Enable LTE Modem" "540" "1"
;;
dlink,dir-510l)
ucidef_add_gpio_switch "usb_enable1" "USB 1A enable" "12" "0"
ucidef_add_gpio_switch "usb_enable05" "USB 0.5A enable" "13" "1"
ucidef_add_gpio_switch "usb_enable1" "USB 1A enable" "524" "0"
ucidef_add_gpio_switch "usb_enable05" "USB 0.5A enable" "525" "1"
;;
dlink,dwr-960|\
dlink,dwr-961-a1)
ucidef_add_gpio_switch "power_mpcie" "mPCIe power" "0" "1"
ucidef_add_gpio_switch "power_mpcie" "mPCIe power" "512" "1"
;;
head-weblink,hdrm200)
ucidef_add_gpio_switch "sim_switch" "SIM slot switch" "0"
ucidef_add_gpio_switch "io1" "I/O 1" "1"
ucidef_add_gpio_switch "io2" "I/O 2" "2"
ucidef_add_gpio_switch "io3" "I/O 3" "11"
ucidef_add_gpio_switch "io4" "I/O 4" "14"
ucidef_add_gpio_switch "power_mpcie" "mPCIe power" "21" "1"
ucidef_add_gpio_switch "sim_switch" "SIM slot switch" "512"
ucidef_add_gpio_switch "io1" "I/O 1" "513"
ucidef_add_gpio_switch "io2" "I/O 2" "514"
ucidef_add_gpio_switch "io3" "I/O 3" "523"
ucidef_add_gpio_switch "io4" "I/O 4" "526"
ucidef_add_gpio_switch "power_mpcie" "mPCIe power" "533" "1"
;;
lb-link,bl-w1200)
ucidef_add_gpio_switch "eth_leds_enable" "ETH LEDs enable" "10" "1"
ucidef_add_gpio_switch "eth_leds_enable" "ETH LEDs enable" "522" "1"
;;
zbtlink,zbt-we826-e)
ucidef_add_gpio_switch "sim_switch" "SIM slot switch" "13"
ucidef_add_gpio_switch "power_mpcie" "mPCIe power" "14" "1"
ucidef_add_gpio_switch "sim_switch" "SIM slot switch" "525"
ucidef_add_gpio_switch "power_mpcie" "mPCIe power" "526" "1"
;;
esac

16
target/linux/ramips/patches-6.6/801-DT-Add-documentation-for-gpio-ralink.patch
View file

@ -1,22 +1,18 @@
From d410e5478c622c01fcf31427533df5f433df9146 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 28 Jul 2013 19:45:30 +0200
Subject: [PATCH 26/53] DT: Add documentation for gpio-ralink
Subject: [PATCH 1/3] DT: Add documentation for gpio-ralink
Describe gpio-ralink binding.
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-gpio@vger.kernel.org
---
.../devicetree/bindings/gpio/gpio-ralink.txt | 40 ++++++++++++++++++++
1 file changed, 40 insertions(+)
.../devicetree/bindings/gpio/gpio-ralink.txt | 36 +++++++++++++++++++
1 file changed, 36 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpio/gpio-ralink.txt
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-ralink.txt
@@ -0,0 +1,40 @@
@@ -0,0 +1,36 @@
+Ralink SoC GPIO controller bindings
+
+Required properties:
@ -34,9 +30,6 @@ Cc: linux-gpio@vger.kernel.org
+ SoC type. Register offsets need to be in this order.
+ [ INT, EDGE, RENA, FENA, DATA, DIR, POL, SET, RESET, TOGGLE ]
+
+Optional properties:
+- ralink,gpio-base : Specify the GPIO chips base number
+
+Example:
+
+ gpio0: gpio@600 {
@ -51,7 +44,6 @@ Cc: linux-gpio@vger.kernel.org
+ interrupts = <6>;
+
+ ngpios = <24>;
+ ralink,gpio-base = <0>;
+ ralink,register-map = [ 00 04 08 0c
+ 20 24 28 2c
+ 30 34 ];

20
target/linux/ramips/patches-6.6/802-GPIO-MIPS-ralink-add-gpio-driver-for-ralink-SoC.patch
View file

@ -1,20 +1,17 @@
From 69fdd2c4f937796b934e89c33acde9d082e27bfd Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Mon, 4 Aug 2014 20:36:29 +0200
Subject: [PATCH 27/53] GPIO: MIPS: ralink: add gpio driver for ralink SoC
Subject: [PATCH 2/3] GPIO: MIPS: ralink: add gpio driver for ralink SoC
Add gpio driver for Ralink SoC. This driver makes the gpio core on
RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: linux-gpio@vger.kernel.org
---
arch/mips/include/asm/mach-ralink/gpio.h | 24 ++
drivers/gpio/Kconfig | 6 +
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-ralink.c | 355 ++++++++++++++++++++++++++++++
4 files changed, 386 insertions(+)
drivers/gpio/gpio-ralink.c | 336 +++++++++++++++++++++++
4 files changed, 367 insertions(+)
create mode 100644 arch/mips/include/asm/mach-ralink/gpio.h
create mode 100644 drivers/gpio/gpio-ralink.c
@ -72,7 +69,7 @@ Cc: linux-gpio@vger.kernel.org
obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o
--- /dev/null
+++ b/drivers/gpio/gpio-ralink.c
@@ -0,0 +1,341 @@
@@ -0,0 +1,336 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
@ -333,7 +330,7 @@ Cc: linux-gpio@vger.kernel.org
+ struct device_node *np = pdev->dev.of_node;
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ struct ralink_gpio_chip *rg;
+ const __be32 *ngpio, *gpiobase;
+ const __be32 *ngpio;
+
+ if (!res) {
+ dev_err(&pdev->dev, "failed to find resource\n");
@ -363,14 +360,9 @@ Cc: linux-gpio@vger.kernel.org
+ return -EINVAL;
+ }
+
+ gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
+ if (gpiobase)
+ rg->chip.base = be32_to_cpu(*gpiobase);
+ else
+ rg->chip.base = -1;
+
+ spin_lock_init(&rg->lock);
+
+ rg->chip.base = -1;
+ rg->chip.parent = &pdev->dev;
+ rg->chip.label = dev_name(&pdev->dev);
+ rg->chip.fwnode = of_node_to_fwnode(np);

13
target/linux/ramips/patches-6.6/803-gpio-ralink-Add-support-for-GPIO-as-interrupt-contro.patch
View file

@ -1,7 +1,6 @@
From 57fa7f2f4ef6f78ce1d30509c0d111aa3791b524 Mon Sep 17 00:00:00 2001
From: Daniel Santos <daniel.santos@pobox.com>
Date: Sun, 4 Nov 2018 20:24:32 -0600
Subject: gpio-ralink: Add support for GPIO as interrupt-controller
Subject: [PATCH 3/3] gpio-ralink: Add support for GPIO as interrupt-controller
Signed-off-by: Daniel Santos <daniel.santos@pobox.com>
---
@ -11,17 +10,17 @@ Signed-off-by: Daniel Santos <daniel.santos@pobox.com>
--- a/Documentation/devicetree/bindings/gpio/gpio-ralink.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-ralink.txt
@@ -17,6 +17,9 @@ Required properties:
Optional properties:
- ralink,gpio-base : Specify the GPIO chips base number
@@ -14,6 +14,9 @@ Required properties:
- ralink,register-map : The register layout depends on the GPIO bank and actual
SoC type. Register offsets need to be in this order.
[ INT, EDGE, RENA, FENA, DATA, DIR, POL, SET, RESET, TOGGLE ]
+- interrupt-controller : marks this as an interrupt controller
+- #interrupt-cells : a standard two-cell interrupt flag, see
+ interrupt-controller/interrupts.txt
Example:
@@ -28,6 +31,9 @@ Example:
@@ -25,6 +28,9 @@ Example:
reg = <0x600 0x34>;