Revert "qualcommax: ipq50xx: fix GE_PHY and Uniphy resets"
This reverts commit 34e5bc4af54d366147a83904c094d54fec7fb025. While fixing support for 2.5Gbps mode on uniphy in phy to phy link setups, it inadvertently broke fixed link scenario. So let's revert this commit until there's a fix that doesn't impact fixed links. Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://github.com/openwrt/openwrt/pull/18668 Signed-off-by: Robert Marko <robimarko@gmail.com>
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parent
6d4ded04ac
commit
2259807d81
9 changed files with 8 additions and 51 deletions
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@ -13,7 +13,7 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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@@ -202,6 +202,19 @@
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@@ -202,6 +202,21 @@
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clock-names = "gcc_mdio_ahb_clk";
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status = "disabled";
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@ -21,19 +21,21 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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+ ge_phy: ethernet-phy@7 {
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+ compatible = "ethernet-phy-id004d.d0c0";
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+ reg = <7>;
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+
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+ clocks = <&gcc GCC_GEPHY_RX_CLK>,
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+ <&gcc GCC_GEPHY_TX_CLK>;
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+
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+ resets = <&gcc GCC_GEPHY_BCR>,
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+ <&gcc GCC_GEPHY_MISC_ARES>;
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+ <&gcc GCC_GEPHY_MDC_SW_ARES>,
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+ <&gcc GCC_GEPHY_DSP_HW_ARES>,
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+ <&gcc GCC_GEPHY_RX_ARES>,
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+ <&gcc GCC_GEPHY_TX_ARES>;
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+
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+ #clock-cells = <1>;
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+ };
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};
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mdio1: mdio@90000 {
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@@ -398,8 +411,8 @@
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@@ -398,8 +413,8 @@
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<&pcie0_phy>,
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<&pcie1_phy>,
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<0>,
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@ -1,45 +0,0 @@
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From: George Moussalem <george.moussalem@outlook.com>
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Date: Tue, 29 Apr 2025 17:16:31 +0400
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Subject: [PATCH] clk: qcom: gcc-ipq5018: fix GE_PHY and Uniphy resets
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The resets for the GE PHY and Uniphy use bitmasks to assert multiple
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resets simultaneously. These bitmasks are missing and the reset is only
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performed partially against BIT(x) where x is the bit set in the GCC.
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So let's remove the single bit and replace them by the bitmasks as
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intended.
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Link: https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/00743c3e82fa87cba4460e7a2ba32f473a9ce932
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Link: https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/036bdc62aca561e8ff94a29c447fc400de2b7304
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Signed-off-by: zhongjia <zhongjia@codeaurora.org>
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Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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---
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--- a/drivers/clk/qcom/gcc-ipq5018.c
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+++ b/drivers/clk/qcom/gcc-ipq5018.c
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@@ -3566,7 +3566,7 @@ static const struct qcom_reset_map gcc_i
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[GCC_DDRSS_BCR] = { 0x1e000, 0 },
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[GCC_EDPD_BCR] = { 0x3a000, 0 },
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[GCC_GEPHY_BCR] = { 0x56000, 0 },
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- [GCC_GEPHY_MDC_SW_ARES] = { 0x56004, 0 },
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+ [GCC_GEPHY_MDC_SW_ARES] = { 0x56004, .bitmask = 0x3 },
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[GCC_GEPHY_DSP_HW_ARES] = { 0x56004, 1 },
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[GCC_GEPHY_RX_ARES] = { 0x56004, 2 },
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[GCC_GEPHY_TX_ARES] = { 0x56004, 3 },
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@@ -3646,7 +3646,7 @@ static const struct qcom_reset_map gcc_i
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[GCC_UNIPHY_SYS_ARES] = { 0x56104, 1 },
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[GCC_UNIPHY_RX_ARES] = { 0x56104, 4 },
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[GCC_UNIPHY_TX_ARES] = { 0x56104, 5 },
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- [GCC_UNIPHY_SOFT_RESET] = {0x56104, 0 },
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+ [GCC_UNIPHY_SOFT_RESET] = {0x56104, .bitmask = 0x32 },
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[GCC_USB0_BCR] = { 0x3e070, 0 },
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[GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
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[GCC_WCSS_BCR] = { 0x18000, 0 },
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@@ -3659,7 +3659,7 @@ static const struct qcom_reset_map gcc_i
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[GCC_WCSS_AXI_S_ARES] = { 0x59008, 6 },
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[GCC_WCSS_Q6_BCR] = { 0x18004, 0 },
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[GCC_WCSSAON_RESET] = { 0x59010, 0},
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- [GCC_GEPHY_MISC_ARES] = { 0x56004, 0 },
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+ [GCC_GEPHY_MISC_ARES] = { 0x56004, .bitmask = 0xf },
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};
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static const struct of_device_id gcc_ipq5018_match_table[] = {
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@ -1,7 +1,7 @@
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From f71366e0530db2c5cecbbbb6edfbf7344bd6f83b Mon Sep 17 00:00:00 2001
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From: Ziyang Huang <hzyitc@outlook.com>
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Date: Sun, 8 Sep 2024 16:40:12 +0800
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Subject: [PATCH] clk: gcc-ipq5018: remove the unsupported clk
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Subject: [PATCH 1/2] clk: gcc-ipq5018: remove the unsupported clk
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combination for gmac
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Comment out the unsupported clock combination in the frequency table
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@ -13,7 +13,7 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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---
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--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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@@ -697,6 +697,225 @@
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@@ -699,6 +699,225 @@
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};
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};
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