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qca-ssdk: use OpenWrt GIT repo as upstream

Browse source 
Instead of having to deal with patch files, lets use the newly made
OpenWrt GIT repo as the SSDK upstream[1].

All existing patches have been applied to the same source commit, so
there should be no intended changes.

[1] https://github.com/openwrt/qca-ssdk.git

Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Robert Marko 2025-05-09 16:14:16 +02:00
parent 9a3c6df21b
commit 1c4339180a
10 changed files with 5 additions and 653 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
package/kernel/qca-ssdk/Makefile
View file

@ -1,13 +1,13 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=qca-ssdk
PKG_RELEASE:=3
PKG_RELEASE:=1
PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/qca-ssdk.git
PKG_SOURCE_URL:=https://github.com/openwrt/qca-ssdk.git
PKG_SOURCE_PROTO:=git
PKG_SOURCE_DATE:=2024-06-13
PKG_SOURCE_VERSION:=c451136ba69d51d60f770365b6d6d60ff2801998
PKG_MIRROR_HASH:=4c54f2d77b5abeb96bddceb4a9eb58aa2c8fb12b58d5d666196224a35ac107dc
PKG_SOURCE_DATE:=2025-05-09
PKG_SOURCE_VERSION:=4f7dacb232cd2df3e4867c9fcf9e4a08bfa92820
PKG_MIRROR_HASH:=367ac0df54df379f9e8192256f14da3f94fe0797eba768ac671c70c774094804
PKG_FLAGS:=nonshared
PKG_BUILD_PARALLEL:=1

30
package/kernel/qca-ssdk/patches/0003-Revert-qca-ssdk-enable-invoking-fdb-del-function-for.patch
View file

@ -1,30 +0,0 @@
From 73c0992a36bc13e9bb373f98ba246dfc1e29a393 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Tue, 7 Nov 2023 14:21:43 +0100
Subject: [PATCH 3/3] Revert "[qca-ssdk]: enable invoking fdb del function for
kernel6.1"
This reverts commit a86765ee6a87145f64344f4872cfe8c5e629dd62.
Upstream kernel does not have this call present at all, we currently
also dont use it, so revert the commit enabling it.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
src/ref/ref_acl.c | 4 ++++
1 file changed, 4 insertions(+)
--- a/src/ref/ref_acl.c
+++ b/src/ref/ref_acl.c
@@ -229,7 +229,11 @@ _ref_acl_mac_entry_create_rule(a_uint32_
eth_dev = dev_get_by_name(&init_net, entry->ifname);
if (eth_dev)
{
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0))
+ // TODO: replace with corresponding ver
+#else
br_fdb_delete_by_netdev(eth_dev, entry->src_mac.uc, 0);
+#endif
dev_put(eth_dev);
}
}

94
package/kernel/qca-ssdk/patches/0004-SSDK-set-OF-node-for-the-SFP-PHY.patch
View file

@ -1,94 +0,0 @@
From 00d3c54c611143f57b632e4cd3b42b0a94d82307 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Sun, 25 Jun 2023 11:24:09 +0200
Subject: [PATCH 3/3] SSDK: set OF node for the SFP PHY
Currently, SSDK is creating a fake SFP PHY which has no OF node populated,
thus making it impossible to pass it to NSS-DP so port can actually work.
We eliminated QCA-s connecting of the PHY by manually creating a string
and then matching by name and instead only support passing the PHY as
phandle via phy-handle.
So, lets just use the switch port node to which the SFP is connected to
anyway and set it as the PHY device OF node so we can pass it to NSS-DP.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
include/hsl/phy/hsl_phy.h | 6 ++++++
src/hsl/phy/hsl_phy.c | 14 ++++++++++++++
src/hsl/phy/sfp_phy.c | 7 +++++++
src/init/ssdk_dts.c | 7 +++++++
4 files changed, 34 insertions(+)
--- a/include/hsl/phy/hsl_phy.h
+++ b/include/hsl/phy/hsl_phy.h
@@ -584,6 +584,7 @@ typedef struct {
a_bool_t port_link_status[SW_MAX_NR_PORT];
a_uint32_t port_mode[SW_MAX_NR_PORT];
a_uint32_t combo_phy_type[SW_MAX_NR_PORT];
+ struct device_node *port_node[SW_MAX_NR_PORT];
} phy_info_t;
/*qca808x_end*/
#define MALIBU5PORT_PHY 0x004DD0B1
@@ -1038,3 +1039,8 @@ hsl_phydev_eee_update(a_uint32_t dev_id,
#endif /* __cplusplus */
#endif /* _HSL_PHY_H_ */
/*qca808x_end*/
+
+struct device_node*
+hsl_port_node_get(a_uint32_t dev_id, a_uint32_t port_id);
+void
+hsl_port_node_set(a_uint32_t dev_id, a_uint32_t port_id, struct device_node *port_node);
--- a/src/hsl/phy/hsl_phy.c
+++ b/src/hsl/phy/hsl_phy.c
@@ -3433,3 +3433,17 @@ hsl_phy_modify_debug(a_uint32_t dev_id,
return rv;
}
/*qca808x_end*/
+
+struct device_node*
+hsl_port_node_get(a_uint32_t dev_id, a_uint32_t port_id)
+{
+ return phy_info[dev_id]->port_node[port_id];
+}
+
+void
+hsl_port_node_set(a_uint32_t dev_id, a_uint32_t port_id, struct device_node *port_node)
+{
+ phy_info[dev_id]->port_node[port_id] = port_node;
+
+ return;
+}
--- a/src/hsl/phy/sfp_phy.c
+++ b/src/hsl/phy/sfp_phy.c
@@ -335,6 +335,13 @@ int sfp_phy_device_setup(a_uint32_t dev_
phy_device_register(phydev);
phydev->priv = priv;
+ /*
+ * Set the PHY OF node in order to be able to later connect the
+ * fake SFP PHY by passing it as a phandle in phy-handle.
+ */
+ phydev->mdio.dev.of_node = hsl_port_node_get(dev_id, port);
+ if (!phydev->mdio.dev.of_node)
+ return SW_NOT_FOUND;
#if defined(IN_PHY_I2C_MODE)
if (hsl_port_phy_access_type_get(dev_id, port) == PHY_I2C_ACCESS) {
if(phydev->drv)
--- a/src/init/ssdk_dts.c
+++ b/src/init/ssdk_dts.c
@@ -784,6 +784,13 @@ static sw_error_t ssdk_dt_parse_phy_info
}
}
hsl_port_feature_set(dev_id, port_id, phy_features | PHY_F_INIT);
+
+ /*
+ * Save the port node so it can be passed as the
+ * fake SFP PHY OF node in order to be able to
+ * pass the SFP phy via phy-handle
+ */
+ hsl_port_node_set(dev_id, port_id, port_node);
}
return rv;

135
package/kernel/qca-ssdk/patches/102-qca-ssdk-support-selecting-PCS-channel-for-PORT3-on-.patch
View file

@ -1,135 +0,0 @@
From 0116bb7359bd99c09bcad1b2051652cd1a04be3f Mon Sep 17 00:00:00 2001
From: Mantas Pucka <mantas@8devices.com>
Date: Mon, 12 Feb 2024 14:23:04 +0200
Subject: [PATCH] qca-ssdk: support selecting PCS channel for PORT3 on IPQ6018
When QCA8072 is used in PSGMII mode with IPQ6018, PCS used for second
PHY port would overlap with one used by SGMII+ port. SoC has register
to select different PCS in such case.
Original code used PHY_ID for this decision, which also had other
issues, but is no longer viable since we moved to upstream QCA807x
driver.
Introduce DT property port3_pcs_channel to allow describing this in DT.
Default value is <2>, and for some QCA8072 designs <4> would be needed.
Signed-off-by: Mantas Pucka <mantas@8devices.com>
---
include/init/ssdk_dts.h | 2 ++
src/adpt/cppe/adpt_cppe_portctrl.c | 4 ++--
src/adpt/hppe/adpt_hppe_uniphy.c | 7 +------
src/init/ssdk_dts.c | 27 +++++++++++++++++++++++++++
4 files changed, 32 insertions(+), 8 deletions(-)
--- a/include/init/ssdk_dts.h
+++ b/include/init/ssdk_dts.h
@@ -99,6 +99,7 @@ typedef struct
a_uint32_t emu_chip_ver; /*only valid when is_emulation is true*/
a_uint32_t clk_mode;
a_uint32_t pcie_hw_base;
+ a_uint32_t port3_pcs_channel;
led_ctrl_pattern_t source_pattern[SSDK_MAX_PORT_NUM][PORT_LED_SOURCE_MAX];
} ssdk_dt_cfg;
@@ -161,6 +162,7 @@ a_uint32_t ssdk_device_id_get(a_uint32_t
struct device_node *ssdk_dts_node_get(a_uint32_t dev_id);
struct clk *ssdk_dts_essclk_get(a_uint32_t dev_id);
struct clk *ssdk_dts_cmnclk_get(a_uint32_t dev_id);
+a_uint32_t ssdk_dts_port3_pcs_channel_get(a_uint32_t dev_id);
int ssdk_switch_device_num_init(void);
void ssdk_switch_device_num_exit(void);
--- a/src/adpt/cppe/adpt_cppe_portctrl.c
+++ b/src/adpt/cppe/adpt_cppe_portctrl.c
@@ -33,6 +33,7 @@
#include "hsl_phy.h"
#include "hsl_port_prop.h"
#include "hppe_init.h"
+#include "ssdk_dts.h"
#include "adpt.h"
#include "adpt_hppe.h"
#include "adpt_cppe_portctrl.h"
@@ -60,8 +61,7 @@ _adpt_cppe_port_mux_mac_set(a_uint32_t d
case SSDK_PHYSICAL_PORT3:
case SSDK_PHYSICAL_PORT4:
if (mode0 == PORT_WRAPPER_PSGMII) {
- if (hsl_port_phyid_get(dev_id,
- SSDK_PHYSICAL_PORT3) == MALIBU2PORT_PHY) {
+ if (ssdk_dts_port3_pcs_channel_get(dev_id) == 4) {
cppe_port_mux_ctrl.bf.port3_pcs_sel =
CPPE_PORT3_PCS_SEL_PCS0_CHANNEL4;
cppe_port_mux_ctrl.bf.port4_pcs_sel =
--- a/src/adpt/hppe/adpt_hppe_uniphy.c
+++ b/src/adpt/hppe/adpt_hppe_uniphy.c
@@ -1160,9 +1160,6 @@ __adpt_hppe_uniphy_psgmii_mode_set(a_uin
{
a_uint32_t i;
sw_error_t rv = SW_OK;
-#if defined(CPPE)
- a_uint32_t phy_type = 0;
-#endif
union uniphy_mode_ctrl_u uniphy_mode_ctrl;
@@ -1172,9 +1169,7 @@ __adpt_hppe_uniphy_psgmii_mode_set(a_uin
SSDK_DEBUG("uniphy %d is psgmii mode\n", uniphy_index);
#if defined(CPPE)
if (adpt_ppe_type_get(dev_id) == CPPE_TYPE) {
- phy_type = hsl_port_phyid_get(dev_id,
- SSDK_PHYSICAL_PORT3);
- if (phy_type == MALIBU2PORT_PHY) {
+ if (ssdk_dts_port3_pcs_channel_get(dev_id) == 4) {
SSDK_INFO("cypress uniphy %d is qca8072 psgmii mode\n", uniphy_index);
rv = __adpt_cppe_uniphy_mode_set(dev_id, uniphy_index,
PORT_WRAPPER_PSGMII);
--- a/src/init/ssdk_dts.c
+++ b/src/init/ssdk_dts.c
@@ -272,6 +272,13 @@ struct clk *ssdk_dts_cmnclk_get(a_uint32
return cfg->cmnblk_clk;
}
+a_uint32_t ssdk_dts_port3_pcs_channel_get(a_uint32_t dev_id)
+{
+ ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id];
+
+ return cfg->port3_pcs_channel;
+}
+
#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
static void ssdk_dt_parse_mac_mode(a_uint32_t dev_id,
struct device_node *switch_node, ssdk_init_cfg *cfg)
@@ -305,6 +312,25 @@ static void ssdk_dt_parse_mac_mode(a_uin
return;
}
+
+static void ssdk_dt_parse_port3_pcs_channel(a_uint32_t dev_id,
+ struct device_node *switch_node, ssdk_init_cfg *cfg)
+{
+ const __be32 *port3_pcs_channel;
+ a_uint32_t len = 0;
+
+ port3_pcs_channel = of_get_property(switch_node, "port3_pcs_channel", &len);
+ if (!port3_pcs_channel) {
+ ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port3_pcs_channel = 2;
+ }
+ else {
+ ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port3_pcs_channel =
+ be32_to_cpup(port3_pcs_channel);
+ }
+
+ return;
+}
+
#ifdef IN_UNIPHY
static void ssdk_dt_parse_uniphy(a_uint32_t dev_id)
{
@@ -1354,6 +1380,7 @@ sw_error_t ssdk_dt_parse(ssdk_init_cfg *
rv = ssdk_dt_parse_access_mode(switch_node, ssdk_dt_priv);
SW_RTN_ON_ERROR(rv);
ssdk_dt_parse_mac_mode(*dev_id, switch_node, cfg);
+ ssdk_dt_parse_port3_pcs_channel(*dev_id, switch_node, cfg);
ssdk_dt_parse_mdio(*dev_id, switch_node, cfg);
ssdk_dt_parse_port_bmp(*dev_id, switch_node, cfg);
ssdk_dt_parse_interrupt(*dev_id, switch_node);

33
package/kernel/qca-ssdk/patches/103-hsl_phy-add-support-for-AQR114C-B0-PHY.patch
View file

@ -1,33 +0,0 @@
From ab3b663842f66d0ed290696cee9edb9070a36e8f Mon Sep 17 00:00:00 2001
From: Paweł Owoc <frut3k7@gmail.com>
Date: Wed, 7 May 2024 10:37:44 +0100
Subject: [PATCH] hsl_phy: add support for AQR114C-B0 PHY
Add support for AQR114C-B0 PHY.
Signed-off-by: Paweł Owoc <frut3k7@gmail.com>
---
include/hsl/phy/hsl_phy.h | 1 +
src/hsl/phy/hsl_phy.c | 1 +
2 files changed, 2 insertions(+)
--- a/include/hsl/phy/hsl_phy.h
+++ b/include/hsl/phy/hsl_phy.h
@@ -613,6 +613,7 @@ typedef struct {
#define AQUANTIA_PHY_113C_B0 0x31c31C12
#define AQUANTIA_PHY_113C_B1 0x31c31C13
#define AQUANTIA_PHY_112C 0x03a1b792
+#define AQUANTIA_PHY_114C_B0 0x31c31c22
#define MVL_PHY_X3410 0x31c31DD3
#define PHY_805XV2 0x004DD082
--- a/src/hsl/phy/hsl_phy.c
+++ b/src/hsl/phy/hsl_phy.c
@@ -271,6 +271,7 @@ phy_type_t hsl_phytype_get_by_phyid(a_ui
case AQUANTIA_PHY_113C_B0:
case AQUANTIA_PHY_113C_B1:
case AQUANTIA_PHY_112C:
+ case AQUANTIA_PHY_114C_B0:
case MVL_PHY_X3410:
phytype = AQUANTIA_PHY_CHIP;
break;

127
package/kernel/qca-ssdk/patches/111-hsl_phy-split-MP_PHY-config.patch
View file

@ -1,127 +0,0 @@
From 15847e1f56b7f9423095cd96fd9d524a41bee814 Mon Sep 17 00:00:00 2001
From: Ziyang Huang <hzyitc@outlook.com>
Date: Sun, 8 Sep 2024 15:24:07 +0800
Subject: [PATCH] hsl_phy: split MP_PHY config
Compiling the MP_PHY driver for ipq50xx is disabled in the Makefile in
favor of a native driver being upstreamed. As such, conditionally disable
unneeded flags and code associated to initializing the MP GE PHY that
would otherwise conflict with the native driver.
Signed-off-by: Ziyang Huang <hzyitc@outlook.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
config | 1 +
make/linux_opt.mk | 5 +++++
src/adpt/mp/adpt_mp_portctrl.c | 4 ++++
src/hsl/phy/Makefile | 8 +-------
src/hsl/phy/hsl_phy.c | 4 ++--
5 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/config b/config
index 99d99dff..1f74e4f8 100644
--- a/config
+++ b/config
@@ -299,6 +299,7 @@ else ifeq (DESS, $(CHIP_TYPE))
else ifeq (MP, $(CHIP_TYPE))
IN_QCA803X_PHY=TRUE
IN_QCA808X_PHY=TRUE
+ IN_MP_PHY=TRUE
IN_SFP_PHY=TRUE
IN_SFP=TRUE
else ifeq (APPE, $(CHIP_TYPE))
diff --git a/make/linux_opt.mk b/make/linux_opt.mk
index 6936b754..66b08ef5 100644
--- a/make/linux_opt.mk
+++ b/make/linux_opt.mk
@@ -183,6 +183,11 @@ endif
ifeq (TRUE, $(IN_QCA808X_PHY))
MODULE_CFLAG += -DIN_QCA808X_PHY
endif
+
+ifeq (TRUE, $(IN_MP_PHY))
+ MODULE_CFLAG += -DIN_MP_PHY
+endif
+
ifeq (TRUE, $(IN_SFP_PHY))
MODULE_CFLAG += -DIN_SFP_PHY
endif
diff --git a/src/adpt/mp/adpt_mp_portctrl.c b/src/adpt/mp/adpt_mp_portctrl.c
index 2c983fff..db60fc72 100644
--- a/src/adpt/mp/adpt_mp_portctrl.c
+++ b/src/adpt/mp/adpt_mp_portctrl.c
@@ -92,12 +92,15 @@ static sw_error_t
adpt_mp_port_reset_set(a_uint32_t dev_id, a_uint32_t port_id)
{
sw_error_t rv = 0;
+#ifdef IN_MP_PHY
a_uint32_t phy_addr;
hsl_phy_ops_t *phy_drv;
+#endif
ADPT_DEV_ID_CHECK(dev_id);
if (port_id == SSDK_PHYSICAL_PORT1) {
+#ifdef IN_MP_PHY
/*internal gephy reset*/
SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get(dev_id,
port_id));
@@ -107,6 +110,7 @@ adpt_mp_port_reset_set(a_uint32_t dev_id, a_uint32_t port_id)
SW_RTN_ON_ERROR (rv);
rv = phy_drv->phy_function_reset(dev_id, phy_addr, PHY_FIFO_RESET);
SW_RTN_ON_ERROR (rv);
+#endif
} else if (port_id == SSDK_PHYSICAL_PORT2) {
rv = adpt_mp_uniphy_adapter_port_reset(dev_id, port_id);
} else {
diff --git a/src/hsl/phy/Makefile b/src/hsl/phy/Makefile
index 68d0679f..0eae9377 100755
--- a/src/hsl/phy/Makefile
+++ b/src/hsl/phy/Makefile
@@ -23,7 +23,7 @@ ifeq (ISIS, $(CHIP_TYPE))
SRC_LIST = f1_phy.c
endif
-ifeq (MP, $(CHIP_TYPE))
+ifeq (TRUE, $(IN_MP_PHY))
SRC_LIST = mpge_phy.c
ifeq (TRUE, $(IN_LED))
SRC_LIST += mpge_led.c
@@ -40,12 +40,6 @@ endif
ifeq (ALL_CHIP, $(CHIP_TYPE))
SRC_LIST = f1_phy.c f2_phy.c malibu_phy.c
-ifneq (,$(filter MP, $(SUPPORT_CHIP)))
- SRC_LIST += mpge_phy.c
-ifeq (TRUE, $(IN_LED))
- SRC_LIST += mpge_led.c
-endif
-endif
endif
ifeq (NONHK_CHIP, $(CHIP_TYPE))
diff --git a/src/hsl/phy/hsl_phy.c b/src/hsl/phy/hsl_phy.c
index f2cf90e2..efab2343 100644
--- a/src/hsl/phy/hsl_phy.c
+++ b/src/hsl/phy/hsl_phy.c
@@ -28,7 +28,7 @@
#if defined(ATHENA) ||defined(SHIVA) ||defined(HORUS)
#include <f2_phy.h>
#endif
-#ifdef MP
+#ifdef IN_MP_PHY
#include "mpge_phy.h"
#endif
#ifdef IN_MALIBU_PHY
@@ -94,7 +94,7 @@ phy_driver_instance_t ssdk_phy_driver[] =
#else
{SFP_PHY_CHIP, {0}, NULL, NULL, NULL},
#endif
- #ifdef MP
+ #ifdef IN_MP_PHY
{MPGE_PHY_CHIP, {0}, NULL, mpge_phy_init, NULL},
#else
{MPGE_PHY_CHIP, {0}, NULL, NULL, NULL},
--
2.40.1

40
package/kernel/qca-ssdk/patches/112-init-MP-allow-to-ignore-reset-controlls.patch
View file

@ -1,40 +0,0 @@
From 01fb404dbda1872ad99cea88bf43313bed30200a Mon Sep 17 00:00:00 2001
From: Ziyang Huang <hzyitc@outlook.com>
Date: Sun, 8 Sep 2024 15:24:07 +0800
Subject: [PATCH] init: MP: allow to ignore reset controlls
The SSDK is not used anymore to initialize the internal IPQ5018 GE PHY as
there is a separate driver pending upstream review/approval:
https://lore.kernel.org/all/TYZPR01MB5556D5568546D6DA4313209EC9762@ \
TYZPR01MB5556.apcprd01.prod.exchangelabs.com/
As such, change the code to not error out when the reset controls aren't
found in the DTS where the SSDK expects them. These resets are now defined
under the definition based on the new driver mentioned above.
Signed-off-by: Ziyang Huang <hzyitc@outlook.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
src/init/ssdk_clk.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/src/init/ssdk_clk.c b/src/init/ssdk_clk.c
index 71e59452..bc244c6e 100644
--- a/src/init/ssdk_clk.c
+++ b/src/init/ssdk_clk.c
@@ -1282,10 +1282,8 @@ ssdk_mp_reset_init(void)
for (i = 0; i < MP_BCR_RST_MAX; i++) {
rst = of_reset_control_get(rst_node, mp_rst_ids[i]);
- if (IS_ERR(rst)) {
- SSDK_ERROR("%s not exist!\n", mp_rst_ids[i]);
- return;
- }
+ if (IS_ERR(rst))
+ continue;
ssdk_gcc_reset(rst, SSDK_RESET_ASSERT);
msleep(200);
ssdk_gcc_reset(rst, SSDK_RESET_DEASSERT);
--
2.40.1

82
package/kernel/qca-ssdk/patches/121-MP-fix-build-issues.patch
View file

@ -1,82 +0,0 @@
From a4378eb29c7b9dd95601d20f507a2220457f8ede Mon Sep 17 00:00:00 2001
From: Ziyang Huang <hzyitc@outlook.com>
Date: Sun, 8 Sep 2024 15:24:07 +0800
Subject: [PATCH] MP: fix build issues
Enable the IN_VSI make flag which enables macro definitions needed to
successfully compile the SSDK for the ipq50xx target. In addition, fix an
incorrect return type by expanding the macro called and return a boolean
instead of an integer.
Signed-off-by: Ziyang Huang <hzyitc@outlook.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
config | 30 +-----------------------------
src/adpt/mp/adpt_mp_portctrl.c | 3 ++-
2 files changed, 3 insertions(+), 30 deletions(-)
diff --git a/config b/config
index 1f74e4f8..58d67648 100644
--- a/config
+++ b/config
@@ -374,6 +374,7 @@ ifneq (, $(filter MPPE APPE HPPE CPPE ALL_CHIP, $(CHIP_TYPE)))
endif
ifneq (, $(filter MP, $(CHIP_TYPE)))
+ IN_VSI=TRUE
IN_UNIPHY=TRUE
endif
@@ -436,35 +437,6 @@ endif
# SDK Features According To Specfic Switch #
#############################################
ifeq (MP, $(CHIP_TYPE))
- ifeq (disable, $(ISISC_ENABLE))
- IN_ACL=FALSE
- IN_FDB=FALSE
- IN_IGMP=FALSE
- IN_LEAKY=FALSE
- IN_LED=FALSE
- IN_MIRROR=FALSE
- IN_MISC=FALSE
- IN_PORTVLAN=FALSE
- IN_QOS=FALSE
- IN_RATE=FALSE
- IN_STP=FALSE
- IN_VLAN=FALSE
- IN_REDUCED_ACL=FALSE
- IN_COSMAP=FALSE
- IN_IP=FALSE
- IN_NAT=FALSE
- IN_FLOW=FALSE
- IN_TRUNK=FALSE
- IN_RSS_HASH=FALSE
- IN_SEC=FALSE
- IN_QM=FALSE
- IN_PPPOE=FALSE
- IN_VSI=FALSE
- IN_SERVCODE=FALSE
- IN_BM=FALSE
- IN_SHAPER=FALSE
- IN_POLICER=FALSE
- endif
IN_CTRLPKT=TRUE
endif
diff --git a/src/adpt/mp/adpt_mp_portctrl.c b/src/adpt/mp/adpt_mp_portctrl.c
index db60fc72..c230e214 100644
--- a/src/adpt/mp/adpt_mp_portctrl.c
+++ b/src/adpt/mp/adpt_mp_portctrl.c
@@ -45,7 +45,8 @@ _adpt_mp_gcc_mac_clock_set(a_uint32_t dev_id,
static a_bool_t
_adpt_mp_port_phy_connected (a_uint32_t dev_id, fal_port_t port_id)
{
- ADPT_DEV_ID_CHECK(dev_id);
+ if (dev_id >= SW_MAX_NR_DEV)
+ return A_FALSE;
/* force port which connect s17c or other device chip*/
if (hsl_port_feature_get(dev_id, port_id, PHY_F_FORCE | PHY_F_SFP)) {
--
2.40.1

57
package/kernel/qca-ssdk/patches/122-init-replace-ioremap_nocache-with-ioremap.patch
View file

@ -1,57 +0,0 @@
From a90a9f3e2a21cb87c2cbf2ddb999846aa614e88a Mon Sep 17 00:00:00 2001
From: Ziyang Huang <hzyitc@outlook.com>
Date: Sun, 8 Sep 2024 15:24:07 +0800
Subject: [PATCH 2/2] init: replace ioremap_nocache() with ioremap()
As per https://lore.kernel.org/linux-mips/20191209194819.GA28157@lst.de/T/,
ioremap_nocache is deprecated so let's replace all calls by ioremap instead.
Signed-off-by: Ziyang Huang <hzyitc@outlook.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
src/init/ssdk_clk.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/init/ssdk_clk.c b/src/init/ssdk_clk.c
index bc244c6e..dc45691e 100644
--- a/src/init/ssdk_clk.c
+++ b/src/init/ssdk_clk.c
@@ -1183,7 +1183,7 @@ ssdk_mp_tcsr_get(a_uint32_t tcsr_offset, a_uint32_t *tcsr_val)
{
void __iomem *tcsr_base = NULL;
- tcsr_base = ioremap_nocache(TCSR_ETH_ADDR, TCSR_ETH_SIZE);
+ tcsr_base = ioremap(TCSR_ETH_ADDR, TCSR_ETH_SIZE);
if (!tcsr_base)
{
SSDK_ERROR("Failed to map tcsr eth address!\n");
@@ -1200,7 +1200,7 @@ ssdk_mp_tcsr_set(a_uint32_t tcsr_offset, a_uint32_t tcsr_val)
{
void __iomem *tcsr_base = NULL;
- tcsr_base = ioremap_nocache(TCSR_ETH_ADDR, TCSR_ETH_SIZE);
+ tcsr_base = ioremap(TCSR_ETH_ADDR, TCSR_ETH_SIZE);
if (!tcsr_base)
{
SSDK_ERROR("Failed to map tcsr eth address!\n");
@@ -1248,7 +1248,7 @@ ssdk_mp_cmnblk_stable_check(void)
a_uint32_t reg_val;
int i, loops = 20;
- pll_lock = ioremap_nocache(CMN_PLL_LOCKED_ADDR, CMN_PLL_LOCKED_SIZE);
+ pll_lock = ioremap(CMN_PLL_LOCKED_ADDR, CMN_PLL_LOCKED_SIZE);
if (!pll_lock) {
SSDK_ERROR("Failed to map CMN PLL LOCK register!\n");
return A_FALSE;
@@ -1303,7 +1303,7 @@ static void ssdk_cmnblk_pll_src_set(enum cmnblk_pll_src_type pll_source)
void __iomem *cmn_pll_src_base = NULL;
a_uint32_t reg_val;
- cmn_pll_src_base = ioremap_nocache(CMN_BLK_PLL_SRC_ADDR, CMN_BLK_SIZE);
+ cmn_pll_src_base = ioremap(CMN_BLK_PLL_SRC_ADDR, CMN_BLK_SIZE);
if (!cmn_pll_src_base) {
SSDK_ERROR("Failed to map cmn pll source address!\n");
return;
--
2.40.1

50
package/kernel/qca-ssdk/patches/200-allow-parallel-build.patch
View file

@ -1,50 +0,0 @@
--- a/Makefile
+++ b/Makefile
@@ -1,17 +1,19 @@
-include ./config
-
ifndef PRJ_PATH
PRJ_PATH=$(shell pwd)
endif
export PRJ_PATH
-include ./make/config.mk
-include ./make/tools.mk
-include ./make/$(OS)_opt.mk
+include $(PRJ_PATH)/config
+
+include $(PRJ_PATH)/make/config.mk
+include $(PRJ_PATH)/make/tools.mk
+include $(PRJ_PATH)/make/$(OS)_opt.mk
SUB_DIR=$(patsubst %/, %, $(dir $(wildcard src/*/Makefile)))
SUB_LIB=$(subst src/, , $(SUB_DIR))
+include $(PRJ_PATH)/Makefile.modules
+
####################################################################
# SSDK-Style Makefile
####################################################################
@@ -27,11 +29,7 @@ all: $(BIN_DIR) kslib
# LNX Modules-Style Makefile
####################################################################
modules: $(BIN_DIR) kslib_c
- mkdir -p ./temp/;cp * ./temp -a;cd ./temp;cp ../Makefile.modules ./Makefile;
- make -C $(SYS_PATH) M=$(PRJ_PATH)/temp $(LNX_MAKEOPTS) modules
- cp $(PRJ_PATH)/temp/Module.symvers $(PRJ_PATH)/Module.symvers;
- cp temp/*.ko build/bin;
- rm -Rf ./temp/*.o ./temp/*.ko ./temp/*.a
+ @$(MAKE) -C $(SYS_PATH) M=$(PRJ_PATH) $(LNX_MAKEOPTS) modules
@echo "---Build [SSDK-$(VERSION)] at $(BUILD_DATE) finished."
kslib_c:
--- a/make/linux_opt.mk
+++ b/make/linux_opt.mk
@@ -782,6 +782,6 @@ LOCAL_CFLAGS += $(CPU_CFLAG) -D"KBUILD_M
####################################################################
# cflags for LNX Modules-Style Makefile
####################################################################
-LNX_LOCAL_CFLAGS += $(MODULE_INC) $(MODULE_CFLAG) ${EXTRA_INC} -DFALLTHROUGH
+LNX_LOCAL_CFLAGS = $(MODULE_INC) $(MODULE_CFLAG) ${EXTRA_INC} -DFALLTHROUGH
export LNX_LOCAL_CFLAGS