mediatek: filogic: reorder nodes in mt7988a.dtsi
Use order described as preferred in DTS Coding Style: 1. Sort bus nodes by unit address 2. Use alpha-numerical order for the rest Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
This commit is contained in:
Rafał Miłecki
parent
f95eecfb21
commit
061a70d33c
2 changed files with 432 additions and 432 deletions
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@ -19,11 +19,13 @@
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#address-cells = <2>;
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#address-cells = <2>;
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#size-cells = <2>;
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#size-cells = <2>;
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clk40m: oscillator@0 {
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cci: cci {
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compatible = "fixed-clock";
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compatible = "mediatek,mt7988-cci",
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clock-frequency = <40000000>;
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"mediatek,mt8183-cci";
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#clock-cells = <0>;
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clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
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clock-output-names = "clkxtal";
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<&topckgen CLK_TOP_XTAL>;
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clock-names = "cci", "intermediate";
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operating-points-v2 = <&cci_opp>;
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};
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};
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cpus {
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cpus {
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@ -99,15 +101,6 @@
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};
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};
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};
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};
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cci: cci {
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compatible = "mediatek,mt7988-cci",
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"mediatek,mt8183-cci";
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clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
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<&topckgen CLK_TOP_XTAL>;
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clock-names = "cci", "intermediate";
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operating-points-v2 = <&cci_opp>;
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};
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cci_opp: opp_table_cci {
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cci_opp: opp_table_cci {
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compatible = "operating-points-v2";
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compatible = "operating-points-v2";
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opp-shared;
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opp-shared;
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@ -129,6 +122,13 @@
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};
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};
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};
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};
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clk40m: oscillator@0 {
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compatible = "fixed-clock";
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clock-frequency = <40000000>;
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#clock-cells = <0>;
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clock-output-names = "clkxtal";
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};
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pmu {
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pmu {
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compatible = "arm,cortex-a73-pmu";
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compatible = "arm,cortex-a73-pmu";
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interrupt-parent = <&gic>;
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interrupt-parent = <&gic>;
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@ -140,86 +140,6 @@
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method = "smc";
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method = "smc";
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};
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
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secmon_reserved: secmon@43000000 {
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reg = <0 0x43000000 0 0x50000>;
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no-map;
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};
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};
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thermal-zones {
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cpu_thermal: cpu-thermal {
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polling-delay-passive = <1000>;
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polling-delay = <1000>;
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thermal-sensors = <&lvts 0>;
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trips {
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cpu_trip_crit: crit {
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temperature = <125000>;
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hysteresis = <2000>;
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type = "critical";
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};
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cpu_trip_hot: hot {
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temperature = <120000>;
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hysteresis = <2000>;
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type = "hot";
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};
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cpu_trip_active_high: active-high {
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temperature = <115000>;
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hysteresis = <2000>;
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type = "active";
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};
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cpu_trip_active_med: active-med {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "active";
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};
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cpu_trip_active_low: active-low {
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temperature = <40000>;
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hysteresis = <2000>;
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type = "active";
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};
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};
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cooling-maps {
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cpu-active-high {
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/* active: set fan to cooling level 2 */
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cooling-device = <&fan 3 3>;
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trip = <&cpu_trip_active_high>;
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};
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cpu-active-low {
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/* active: set fan to cooling level 1 */
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cooling-device = <&fan 2 2>;
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trip = <&cpu_trip_active_med>;
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};
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cpu-passive {
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/* passive: set fan to cooling level 0 */
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cooling-device = <&fan 1 1>;
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trip = <&cpu_trip_active_low>;
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};
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};
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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reg_1p8v: regulator-1p8v {
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reg_1p8v: regulator-1p8v {
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compatible = "regulator-fixed";
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.8V";
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regulator-name = "fixed-1.8V";
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@ -238,6 +158,18 @@
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regulator-always-on;
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regulator-always-on;
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};
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
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secmon_reserved: secmon@43000000 {
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reg = <0 0x43000000 0 0x50000>;
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no-map;
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};
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};
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soc {
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soc {
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#address-cells = <2>;
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#address-cells = <2>;
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#size-cells = <2>;
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#size-cells = <2>;
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@ -539,6 +471,25 @@
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};
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};
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};
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};
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pwm: pwm@10048000 {
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compatible = "mediatek,mt7988-pwm";
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reg = <0 0x10048000 0 0x1000>;
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#pwm-cells = <2>;
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clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
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<&infracfg CLK_INFRA_66M_PWM_HCK>,
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<&infracfg CLK_INFRA_66M_PWM_CK1>,
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<&infracfg CLK_INFRA_66M_PWM_CK2>,
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<&infracfg CLK_INFRA_66M_PWM_CK3>,
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<&infracfg CLK_INFRA_66M_PWM_CK4>,
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<&infracfg CLK_INFRA_66M_PWM_CK5>,
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<&infracfg CLK_INFRA_66M_PWM_CK6>,
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<&infracfg CLK_INFRA_66M_PWM_CK7>,
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<&infracfg CLK_INFRA_66M_PWM_CK8>;
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clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
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"pwm4","pwm5","pwm6","pwm7","pwm8";
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status = "disabled";
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};
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sgmiisys0: syscon@10060000 {
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sgmiisys0: syscon@10060000 {
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compatible = "mediatek,mt7988-sgmiisys",
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compatible = "mediatek,mt7988-sgmiisys",
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"mediatek,mt7988-sgmiisys_0",
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"mediatek,mt7988-sgmiisys_0",
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@ -571,28 +522,6 @@
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#clock-cells = <1>;
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#clock-cells = <1>;
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};
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};
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xfi_pextp0: xfi-pextp@11f20000 {
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compatible = "mediatek,mt7988-xfi-pextp",
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"mediatek,mt7988-xfi-pextp_0",
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"syscon";
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reg = <0 0x11f20000 0 0x10000>;
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#clock-cells = <1>;
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};
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xfi_pextp1: xfi-pextp@11f30000 {
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compatible = "mediatek,mt7988-xfi-pextp",
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"mediatek,mt7988-xfi-pextp_1",
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"syscon";
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reg = <0 0x11f30000 0 0x10000>;
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#clock-cells = <1>;
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};
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xfi_pll: xfi-pll@11f40000 {
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compatible = "mediatek,mt7988-xfi-pll", "syscon";
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reg = <0 0x11f40000 0 0x1000>;
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#clock-cells = <1>;
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};
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mcusys: mcusys@100e0000 {
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mcusys: mcusys@100e0000 {
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compatible = "mediatek,mt7988-mcusys", "syscon";
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compatible = "mediatek,mt7988-mcusys", "syscon";
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reg = <0 0x100e0000 0 0x1000>;
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reg = <0 0x100e0000 0 0x1000>;
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@ -742,25 +671,6 @@
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status = "disabled";
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status = "disabled";
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};
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};
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pwm: pwm@10048000 {
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compatible = "mediatek,mt7988-pwm";
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reg = <0 0x10048000 0 0x1000>;
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#pwm-cells = <2>;
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clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
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<&infracfg CLK_INFRA_66M_PWM_HCK>,
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<&infracfg CLK_INFRA_66M_PWM_CK1>,
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<&infracfg CLK_INFRA_66M_PWM_CK2>,
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<&infracfg CLK_INFRA_66M_PWM_CK3>,
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<&infracfg CLK_INFRA_66M_PWM_CK4>,
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<&infracfg CLK_INFRA_66M_PWM_CK5>,
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<&infracfg CLK_INFRA_66M_PWM_CK6>,
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<&infracfg CLK_INFRA_66M_PWM_CK7>,
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<&infracfg CLK_INFRA_66M_PWM_CK8>;
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clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
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"pwm4","pwm5","pwm6","pwm7","pwm8";
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status = "disabled";
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};
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fan: pwm-fan {
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fan: pwm-fan {
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compatible = "pwm-fan";
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compatible = "pwm-fan";
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/* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */
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/* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */
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@ -780,15 +690,53 @@
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nvmem-cell-names = "e_data1";
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nvmem-cell-names = "e_data1";
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};
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};
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crypto: crypto@15600000 {
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ssusb0: usb@11190000 {
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compatible = "inside-secure,safexcel-eip197b";
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compatible = "mediatek,mt7988-xhci",
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reg = <0 0x15600000 0 0x180000>;
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"mediatek,mtk-xhci";
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interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
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reg = <0 0x11190000 0 0x2e00>,
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<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
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<0 0x11193e00 0 0x0100>;
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<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
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reg-names = "mac", "ippc";
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<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "ring0", "ring1", "ring2", "ring3";
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phys = <&xphyu2port0 PHY_TYPE_USB2>,
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status = "okay";
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<&xphyu3port0 PHY_TYPE_USB3>;
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clocks = <&infracfg CLK_INFRA_USB_SYS>,
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<&infracfg CLK_INFRA_USB_XHCI>,
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<&infracfg CLK_INFRA_USB_REF>,
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<&infracfg CLK_INFRA_66M_USB_HCK>,
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<&infracfg CLK_INFRA_133M_USB_HCK>;
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clock-names = "sys_ck",
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"xhci_ck",
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"ref_ck",
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"mcu_ck",
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"dma_ck";
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#address-cells = <2>;
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#size-cells = <2>;
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mediatek,p0_speed_fixup;
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status = "disabled";
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};
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ssusb1: usb@11200000 {
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compatible = "mediatek,mt7988-xhci",
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"mediatek,mtk-xhci";
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reg = <0 0x11200000 0 0x2e00>,
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<0 0x11203e00 0 0x0100>;
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reg-names = "mac", "ippc";
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interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&tphyu2port0 PHY_TYPE_USB2>,
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<&tphyu3port0 PHY_TYPE_USB3>;
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clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
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<&infracfg CLK_INFRA_USB_XHCI_CK_P1>,
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<&infracfg CLK_INFRA_USB_CK_P1>,
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<&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
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<&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>;
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clock-names = "sys_ck",
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"xhci_ck",
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"ref_ck",
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"mcu_ck",
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"dma_ck";
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#address-cells = <2>;
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#size-cells = <2>;
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status = "disabled";
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};
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};
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afe: audio-controller@11210000 {
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afe: audio-controller@11210000 {
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@ -820,6 +768,29 @@
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status = "disabled";
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status = "disabled";
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};
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};
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mmc0: mmc@11230000 {
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compatible = "mediatek,mt7986-mmc",
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"mediatek,mt7981-mmc";
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reg = <0 0x11230000 0 0x1000>,
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<0 0x11D60000 0 0x1000>;
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interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CLK_INFRA_MSDC400>,
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<&infracfg CLK_INFRA_MSDC2_HCK>,
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<&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
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<&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
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assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
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<&topckgen CLK_TOP_EMMC_400M_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
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<&apmixedsys CLK_APMIXED_MSDCPLL>;
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clock-names = "source",
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"hclk",
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"axi_cg",
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"ahb_cg";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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pcie2: pcie@11280000 {
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pcie2: pcie@11280000 {
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compatible = "mediatek,mt7988-pcie",
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compatible = "mediatek,mt7988-pcie",
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"mediatek,mt7986-pcie",
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"mediatek,mt7986-pcie",
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@ -979,78 +950,6 @@
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};
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};
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};
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};
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ssusb0: usb@11190000 {
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compatible = "mediatek,mt7988-xhci",
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"mediatek,mtk-xhci";
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reg = <0 0x11190000 0 0x2e00>,
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<0 0x11193e00 0 0x0100>;
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reg-names = "mac", "ippc";
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interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&xphyu2port0 PHY_TYPE_USB2>,
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<&xphyu3port0 PHY_TYPE_USB3>;
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clocks = <&infracfg CLK_INFRA_USB_SYS>,
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<&infracfg CLK_INFRA_USB_XHCI>,
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<&infracfg CLK_INFRA_USB_REF>,
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<&infracfg CLK_INFRA_66M_USB_HCK>,
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|
||||||
<&infracfg CLK_INFRA_133M_USB_HCK>;
|
|
||||||
clock-names = "sys_ck",
|
|
||||||
"xhci_ck",
|
|
||||||
"ref_ck",
|
|
||||||
"mcu_ck",
|
|
||||||
"dma_ck";
|
|
||||||
#address-cells = <2>;
|
|
||||||
#size-cells = <2>;
|
|
||||||
mediatek,p0_speed_fixup;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
ssusb1: usb@11200000 {
|
|
||||||
compatible = "mediatek,mt7988-xhci",
|
|
||||||
"mediatek,mtk-xhci";
|
|
||||||
reg = <0 0x11200000 0 0x2e00>,
|
|
||||||
<0 0x11203e00 0 0x0100>;
|
|
||||||
reg-names = "mac", "ippc";
|
|
||||||
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
phys = <&tphyu2port0 PHY_TYPE_USB2>,
|
|
||||||
<&tphyu3port0 PHY_TYPE_USB3>;
|
|
||||||
clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
|
|
||||||
<&infracfg CLK_INFRA_USB_XHCI_CK_P1>,
|
|
||||||
<&infracfg CLK_INFRA_USB_CK_P1>,
|
|
||||||
<&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
|
|
||||||
<&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>;
|
|
||||||
clock-names = "sys_ck",
|
|
||||||
"xhci_ck",
|
|
||||||
"ref_ck",
|
|
||||||
"mcu_ck",
|
|
||||||
"dma_ck";
|
|
||||||
#address-cells = <2>;
|
|
||||||
#size-cells = <2>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
mmc0: mmc@11230000 {
|
|
||||||
compatible = "mediatek,mt7986-mmc",
|
|
||||||
"mediatek,mt7981-mmc";
|
|
||||||
reg = <0 0x11230000 0 0x1000>,
|
|
||||||
<0 0x11D60000 0 0x1000>;
|
|
||||||
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
clocks = <&infracfg CLK_INFRA_MSDC400>,
|
|
||||||
<&infracfg CLK_INFRA_MSDC2_HCK>,
|
|
||||||
<&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
|
|
||||||
<&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
|
|
||||||
assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
|
|
||||||
<&topckgen CLK_TOP_EMMC_400M_SEL>;
|
|
||||||
assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
|
|
||||||
<&apmixedsys CLK_APMIXED_MSDCPLL>;
|
|
||||||
clock-names = "source",
|
|
||||||
"hclk",
|
|
||||||
"axi_cg",
|
|
||||||
"ahb_cg";
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
tphy: tphy@11c50000 {
|
tphy: tphy@11c50000 {
|
||||||
compatible = "mediatek,mt7988",
|
compatible = "mediatek,mt7988",
|
||||||
"mediatek,generic-tphy-v2";
|
"mediatek,generic-tphy-v2";
|
||||||
|
|
@ -1108,6 +1007,28 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
xfi_pextp0: xfi-pextp@11f20000 {
|
||||||
|
compatible = "mediatek,mt7988-xfi-pextp",
|
||||||
|
"mediatek,mt7988-xfi-pextp_0",
|
||||||
|
"syscon";
|
||||||
|
reg = <0 0x11f20000 0 0x10000>;
|
||||||
|
#clock-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
xfi_pextp1: xfi-pextp@11f30000 {
|
||||||
|
compatible = "mediatek,mt7988-xfi-pextp",
|
||||||
|
"mediatek,mt7988-xfi-pextp_1",
|
||||||
|
"syscon";
|
||||||
|
reg = <0 0x11f30000 0 0x10000>;
|
||||||
|
#clock-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
xfi_pll: xfi-pll@11f40000 {
|
||||||
|
compatible = "mediatek,mt7988-xfi-pll", "syscon";
|
||||||
|
reg = <0 0x11f40000 0 0x1000>;
|
||||||
|
#clock-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
efuse: efuse@11f50000 {
|
efuse: efuse@11f50000 {
|
||||||
compatible = "mediatek,efuse";
|
compatible = "mediatek,efuse";
|
||||||
reg = <0 0x11f50000 0 0x1000>;
|
reg = <0 0x11f50000 0 0x1000>;
|
||||||
|
|
@ -1437,5 +1358,84 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
crypto: crypto@15600000 {
|
||||||
|
compatible = "inside-secure,safexcel-eip197b";
|
||||||
|
reg = <0 0x15600000 0 0x180000>;
|
||||||
|
interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
interrupt-names = "ring0", "ring1", "ring2", "ring3";
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
thermal-zones {
|
||||||
|
cpu_thermal: cpu-thermal {
|
||||||
|
polling-delay-passive = <1000>;
|
||||||
|
polling-delay = <1000>;
|
||||||
|
thermal-sensors = <&lvts 0>;
|
||||||
|
trips {
|
||||||
|
cpu_trip_crit: crit {
|
||||||
|
temperature = <125000>;
|
||||||
|
hysteresis = <2000>;
|
||||||
|
type = "critical";
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu_trip_hot: hot {
|
||||||
|
temperature = <120000>;
|
||||||
|
hysteresis = <2000>;
|
||||||
|
type = "hot";
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu_trip_active_high: active-high {
|
||||||
|
temperature = <115000>;
|
||||||
|
hysteresis = <2000>;
|
||||||
|
type = "active";
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu_trip_active_med: active-med {
|
||||||
|
temperature = <85000>;
|
||||||
|
hysteresis = <2000>;
|
||||||
|
type = "active";
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu_trip_active_low: active-low {
|
||||||
|
temperature = <40000>;
|
||||||
|
hysteresis = <2000>;
|
||||||
|
type = "active";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
cooling-maps {
|
||||||
|
cpu-active-high {
|
||||||
|
/* active: set fan to cooling level 2 */
|
||||||
|
cooling-device = <&fan 3 3>;
|
||||||
|
trip = <&cpu_trip_active_high>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu-active-low {
|
||||||
|
/* active: set fan to cooling level 1 */
|
||||||
|
cooling-device = <&fan 2 2>;
|
||||||
|
trip = <&cpu_trip_active_med>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu-passive {
|
||||||
|
/* passive: set fan to cooling level 0 */
|
||||||
|
cooling-device = <&fan 1 1>;
|
||||||
|
trip = <&cpu_trip_active_low>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
timer {
|
||||||
|
compatible = "arm,armv8-timer";
|
||||||
|
interrupt-parent = <&gic>;
|
||||||
|
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
||||||
|
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
||||||
|
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
||||||
|
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -19,11 +19,13 @@
|
||||||
#address-cells = <2>;
|
#address-cells = <2>;
|
||||||
#size-cells = <2>;
|
#size-cells = <2>;
|
||||||
|
|
||||||
clk40m: oscillator@0 {
|
cci: cci {
|
||||||
compatible = "fixed-clock";
|
compatible = "mediatek,mt7988-cci",
|
||||||
clock-frequency = <40000000>;
|
"mediatek,mt8183-cci";
|
||||||
#clock-cells = <0>;
|
clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
|
||||||
clock-output-names = "clkxtal";
|
<&topckgen CLK_TOP_XTAL>;
|
||||||
|
clock-names = "cci", "intermediate";
|
||||||
|
operating-points-v2 = <&cci_opp>;
|
||||||
};
|
};
|
||||||
|
|
||||||
cpus {
|
cpus {
|
||||||
|
|
@ -99,15 +101,6 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
cci: cci {
|
|
||||||
compatible = "mediatek,mt7988-cci",
|
|
||||||
"mediatek,mt8183-cci";
|
|
||||||
clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
|
|
||||||
<&topckgen CLK_TOP_XTAL>;
|
|
||||||
clock-names = "cci", "intermediate";
|
|
||||||
operating-points-v2 = <&cci_opp>;
|
|
||||||
};
|
|
||||||
|
|
||||||
cci_opp: opp_table_cci {
|
cci_opp: opp_table_cci {
|
||||||
compatible = "operating-points-v2";
|
compatible = "operating-points-v2";
|
||||||
opp-shared;
|
opp-shared;
|
||||||
|
|
@ -129,6 +122,13 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
clk40m: oscillator@0 {
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
clock-frequency = <40000000>;
|
||||||
|
#clock-cells = <0>;
|
||||||
|
clock-output-names = "clkxtal";
|
||||||
|
};
|
||||||
|
|
||||||
pmu {
|
pmu {
|
||||||
compatible = "arm,cortex-a73-pmu";
|
compatible = "arm,cortex-a73-pmu";
|
||||||
interrupt-parent = <&gic>;
|
interrupt-parent = <&gic>;
|
||||||
|
|
@ -140,86 +140,6 @@
|
||||||
method = "smc";
|
method = "smc";
|
||||||
};
|
};
|
||||||
|
|
||||||
reserved-memory {
|
|
||||||
#address-cells = <2>;
|
|
||||||
#size-cells = <2>;
|
|
||||||
ranges;
|
|
||||||
|
|
||||||
/* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
|
|
||||||
secmon_reserved: secmon@43000000 {
|
|
||||||
reg = <0 0x43000000 0 0x50000>;
|
|
||||||
no-map;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
thermal-zones {
|
|
||||||
cpu_thermal: cpu-thermal {
|
|
||||||
polling-delay-passive = <1000>;
|
|
||||||
polling-delay = <1000>;
|
|
||||||
thermal-sensors = <&lvts 0>;
|
|
||||||
trips {
|
|
||||||
cpu_trip_crit: crit {
|
|
||||||
temperature = <125000>;
|
|
||||||
hysteresis = <2000>;
|
|
||||||
type = "critical";
|
|
||||||
};
|
|
||||||
|
|
||||||
cpu_trip_hot: hot {
|
|
||||||
temperature = <120000>;
|
|
||||||
hysteresis = <2000>;
|
|
||||||
type = "hot";
|
|
||||||
};
|
|
||||||
|
|
||||||
cpu_trip_active_high: active-high {
|
|
||||||
temperature = <115000>;
|
|
||||||
hysteresis = <2000>;
|
|
||||||
type = "active";
|
|
||||||
};
|
|
||||||
|
|
||||||
cpu_trip_active_med: active-med {
|
|
||||||
temperature = <85000>;
|
|
||||||
hysteresis = <2000>;
|
|
||||||
type = "active";
|
|
||||||
};
|
|
||||||
|
|
||||||
cpu_trip_active_low: active-low {
|
|
||||||
temperature = <40000>;
|
|
||||||
hysteresis = <2000>;
|
|
||||||
type = "active";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
cooling-maps {
|
|
||||||
cpu-active-high {
|
|
||||||
/* active: set fan to cooling level 2 */
|
|
||||||
cooling-device = <&fan 3 3>;
|
|
||||||
trip = <&cpu_trip_active_high>;
|
|
||||||
};
|
|
||||||
|
|
||||||
cpu-active-low {
|
|
||||||
/* active: set fan to cooling level 1 */
|
|
||||||
cooling-device = <&fan 2 2>;
|
|
||||||
trip = <&cpu_trip_active_med>;
|
|
||||||
};
|
|
||||||
|
|
||||||
cpu-passive {
|
|
||||||
/* passive: set fan to cooling level 0 */
|
|
||||||
cooling-device = <&fan 1 1>;
|
|
||||||
trip = <&cpu_trip_active_low>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
timer {
|
|
||||||
compatible = "arm,armv8-timer";
|
|
||||||
interrupt-parent = <&gic>;
|
|
||||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
|
||||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
|
||||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
|
||||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
|
|
||||||
};
|
|
||||||
|
|
||||||
reg_1p8v: regulator-1p8v {
|
reg_1p8v: regulator-1p8v {
|
||||||
compatible = "regulator-fixed";
|
compatible = "regulator-fixed";
|
||||||
regulator-name = "fixed-1.8V";
|
regulator-name = "fixed-1.8V";
|
||||||
|
|
@ -238,6 +158,18 @@
|
||||||
regulator-always-on;
|
regulator-always-on;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
reserved-memory {
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
ranges;
|
||||||
|
|
||||||
|
/* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
|
||||||
|
secmon_reserved: secmon@43000000 {
|
||||||
|
reg = <0 0x43000000 0 0x50000>;
|
||||||
|
no-map;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
soc {
|
soc {
|
||||||
#address-cells = <2>;
|
#address-cells = <2>;
|
||||||
#size-cells = <2>;
|
#size-cells = <2>;
|
||||||
|
|
@ -539,6 +471,25 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
pwm: pwm@10048000 {
|
||||||
|
compatible = "mediatek,mt7988-pwm";
|
||||||
|
reg = <0 0x10048000 0 0x1000>;
|
||||||
|
#pwm-cells = <2>;
|
||||||
|
clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
|
||||||
|
<&infracfg CLK_INFRA_66M_PWM_HCK>,
|
||||||
|
<&infracfg CLK_INFRA_66M_PWM_CK1>,
|
||||||
|
<&infracfg CLK_INFRA_66M_PWM_CK2>,
|
||||||
|
<&infracfg CLK_INFRA_66M_PWM_CK3>,
|
||||||
|
<&infracfg CLK_INFRA_66M_PWM_CK4>,
|
||||||
|
<&infracfg CLK_INFRA_66M_PWM_CK5>,
|
||||||
|
<&infracfg CLK_INFRA_66M_PWM_CK6>,
|
||||||
|
<&infracfg CLK_INFRA_66M_PWM_CK7>,
|
||||||
|
<&infracfg CLK_INFRA_66M_PWM_CK8>;
|
||||||
|
clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
|
||||||
|
"pwm4","pwm5","pwm6","pwm7","pwm8";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
sgmiisys0: syscon@10060000 {
|
sgmiisys0: syscon@10060000 {
|
||||||
compatible = "mediatek,mt7988-sgmiisys",
|
compatible = "mediatek,mt7988-sgmiisys",
|
||||||
"mediatek,mt7988-sgmiisys_0",
|
"mediatek,mt7988-sgmiisys_0",
|
||||||
|
|
@ -571,28 +522,6 @@
|
||||||
#clock-cells = <1>;
|
#clock-cells = <1>;
|
||||||
};
|
};
|
||||||
|
|
||||||
xfi_pextp0: xfi-pextp@11f20000 {
|
|
||||||
compatible = "mediatek,mt7988-xfi-pextp",
|
|
||||||
"mediatek,mt7988-xfi-pextp_0",
|
|
||||||
"syscon";
|
|
||||||
reg = <0 0x11f20000 0 0x10000>;
|
|
||||||
#clock-cells = <1>;
|
|
||||||
};
|
|
||||||
|
|
||||||
xfi_pextp1: xfi-pextp@11f30000 {
|
|
||||||
compatible = "mediatek,mt7988-xfi-pextp",
|
|
||||||
"mediatek,mt7988-xfi-pextp_1",
|
|
||||||
"syscon";
|
|
||||||
reg = <0 0x11f30000 0 0x10000>;
|
|
||||||
#clock-cells = <1>;
|
|
||||||
};
|
|
||||||
|
|
||||||
xfi_pll: xfi-pll@11f40000 {
|
|
||||||
compatible = "mediatek,mt7988-xfi-pll", "syscon";
|
|
||||||
reg = <0 0x11f40000 0 0x1000>;
|
|
||||||
#clock-cells = <1>;
|
|
||||||
};
|
|
||||||
|
|
||||||
mcusys: mcusys@100e0000 {
|
mcusys: mcusys@100e0000 {
|
||||||
compatible = "mediatek,mt7988-mcusys", "syscon";
|
compatible = "mediatek,mt7988-mcusys", "syscon";
|
||||||
reg = <0 0x100e0000 0 0x1000>;
|
reg = <0 0x100e0000 0 0x1000>;
|
||||||
|
|
@ -742,25 +671,6 @@
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
pwm: pwm@10048000 {
|
|
||||||
compatible = "mediatek,mt7988-pwm";
|
|
||||||
reg = <0 0x10048000 0 0x1000>;
|
|
||||||
#pwm-cells = <2>;
|
|
||||||
clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
|
|
||||||
<&infracfg CLK_INFRA_66M_PWM_HCK>,
|
|
||||||
<&infracfg CLK_INFRA_66M_PWM_CK1>,
|
|
||||||
<&infracfg CLK_INFRA_66M_PWM_CK2>,
|
|
||||||
<&infracfg CLK_INFRA_66M_PWM_CK3>,
|
|
||||||
<&infracfg CLK_INFRA_66M_PWM_CK4>,
|
|
||||||
<&infracfg CLK_INFRA_66M_PWM_CK5>,
|
|
||||||
<&infracfg CLK_INFRA_66M_PWM_CK6>,
|
|
||||||
<&infracfg CLK_INFRA_66M_PWM_CK7>,
|
|
||||||
<&infracfg CLK_INFRA_66M_PWM_CK8>;
|
|
||||||
clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
|
|
||||||
"pwm4","pwm5","pwm6","pwm7","pwm8";
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
fan: pwm-fan {
|
fan: pwm-fan {
|
||||||
compatible = "pwm-fan";
|
compatible = "pwm-fan";
|
||||||
/* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */
|
/* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */
|
||||||
|
|
@ -780,15 +690,53 @@
|
||||||
nvmem-cell-names = "e_data1";
|
nvmem-cell-names = "e_data1";
|
||||||
};
|
};
|
||||||
|
|
||||||
crypto: crypto@15600000 {
|
ssusb0: usb@11190000 {
|
||||||
compatible = "inside-secure,safexcel-eip197b";
|
compatible = "mediatek,mt7988-xhci",
|
||||||
reg = <0 0x15600000 0 0x180000>;
|
"mediatek,mtk-xhci";
|
||||||
interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
|
reg = <0 0x11190000 0 0x2e00>,
|
||||||
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
|
<0 0x11193e00 0 0x0100>;
|
||||||
<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
|
reg-names = "mac", "ippc";
|
||||||
<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
|
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
interrupt-names = "ring0", "ring1", "ring2", "ring3";
|
phys = <&xphyu2port0 PHY_TYPE_USB2>,
|
||||||
status = "okay";
|
<&xphyu3port0 PHY_TYPE_USB3>;
|
||||||
|
clocks = <&infracfg CLK_INFRA_USB_SYS>,
|
||||||
|
<&infracfg CLK_INFRA_USB_XHCI>,
|
||||||
|
<&infracfg CLK_INFRA_USB_REF>,
|
||||||
|
<&infracfg CLK_INFRA_66M_USB_HCK>,
|
||||||
|
<&infracfg CLK_INFRA_133M_USB_HCK>;
|
||||||
|
clock-names = "sys_ck",
|
||||||
|
"xhci_ck",
|
||||||
|
"ref_ck",
|
||||||
|
"mcu_ck",
|
||||||
|
"dma_ck";
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
mediatek,p0_speed_fixup;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
ssusb1: usb@11200000 {
|
||||||
|
compatible = "mediatek,mt7988-xhci",
|
||||||
|
"mediatek,mtk-xhci";
|
||||||
|
reg = <0 0x11200000 0 0x2e00>,
|
||||||
|
<0 0x11203e00 0 0x0100>;
|
||||||
|
reg-names = "mac", "ippc";
|
||||||
|
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
phys = <&tphyu2port0 PHY_TYPE_USB2>,
|
||||||
|
<&tphyu3port0 PHY_TYPE_USB3>;
|
||||||
|
clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
|
||||||
|
<&infracfg CLK_INFRA_USB_XHCI_CK_P1>,
|
||||||
|
<&infracfg CLK_INFRA_USB_CK_P1>,
|
||||||
|
<&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
|
||||||
|
<&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>;
|
||||||
|
clock-names = "sys_ck",
|
||||||
|
"xhci_ck",
|
||||||
|
"ref_ck",
|
||||||
|
"mcu_ck",
|
||||||
|
"dma_ck";
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
afe: audio-controller@11210000 {
|
afe: audio-controller@11210000 {
|
||||||
|
|
@ -820,6 +768,29 @@
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
mmc0: mmc@11230000 {
|
||||||
|
compatible = "mediatek,mt7986-mmc",
|
||||||
|
"mediatek,mt7981-mmc";
|
||||||
|
reg = <0 0x11230000 0 0x1000>,
|
||||||
|
<0 0x11D60000 0 0x1000>;
|
||||||
|
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&infracfg CLK_INFRA_MSDC400>,
|
||||||
|
<&infracfg CLK_INFRA_MSDC2_HCK>,
|
||||||
|
<&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
|
||||||
|
<&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
|
||||||
|
assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
|
||||||
|
<&topckgen CLK_TOP_EMMC_400M_SEL>;
|
||||||
|
assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
|
||||||
|
<&apmixedsys CLK_APMIXED_MSDCPLL>;
|
||||||
|
clock-names = "source",
|
||||||
|
"hclk",
|
||||||
|
"axi_cg",
|
||||||
|
"ahb_cg";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
pcie2: pcie@11280000 {
|
pcie2: pcie@11280000 {
|
||||||
compatible = "mediatek,mt7988-pcie",
|
compatible = "mediatek,mt7988-pcie",
|
||||||
"mediatek,mt7986-pcie",
|
"mediatek,mt7986-pcie",
|
||||||
|
|
@ -979,78 +950,6 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
ssusb0: usb@11190000 {
|
|
||||||
compatible = "mediatek,mt7988-xhci",
|
|
||||||
"mediatek,mtk-xhci";
|
|
||||||
reg = <0 0x11190000 0 0x2e00>,
|
|
||||||
<0 0x11193e00 0 0x0100>;
|
|
||||||
reg-names = "mac", "ippc";
|
|
||||||
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
phys = <&xphyu2port0 PHY_TYPE_USB2>,
|
|
||||||
<&xphyu3port0 PHY_TYPE_USB3>;
|
|
||||||
clocks = <&infracfg CLK_INFRA_USB_SYS>,
|
|
||||||
<&infracfg CLK_INFRA_USB_XHCI>,
|
|
||||||
<&infracfg CLK_INFRA_USB_REF>,
|
|
||||||
<&infracfg CLK_INFRA_66M_USB_HCK>,
|
|
||||||
<&infracfg CLK_INFRA_133M_USB_HCK>;
|
|
||||||
clock-names = "sys_ck",
|
|
||||||
"xhci_ck",
|
|
||||||
"ref_ck",
|
|
||||||
"mcu_ck",
|
|
||||||
"dma_ck";
|
|
||||||
#address-cells = <2>;
|
|
||||||
#size-cells = <2>;
|
|
||||||
mediatek,p0_speed_fixup;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
ssusb1: usb@11200000 {
|
|
||||||
compatible = "mediatek,mt7988-xhci",
|
|
||||||
"mediatek,mtk-xhci";
|
|
||||||
reg = <0 0x11200000 0 0x2e00>,
|
|
||||||
<0 0x11203e00 0 0x0100>;
|
|
||||||
reg-names = "mac", "ippc";
|
|
||||||
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
phys = <&tphyu2port0 PHY_TYPE_USB2>,
|
|
||||||
<&tphyu3port0 PHY_TYPE_USB3>;
|
|
||||||
clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
|
|
||||||
<&infracfg CLK_INFRA_USB_XHCI_CK_P1>,
|
|
||||||
<&infracfg CLK_INFRA_USB_CK_P1>,
|
|
||||||
<&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
|
|
||||||
<&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>;
|
|
||||||
clock-names = "sys_ck",
|
|
||||||
"xhci_ck",
|
|
||||||
"ref_ck",
|
|
||||||
"mcu_ck",
|
|
||||||
"dma_ck";
|
|
||||||
#address-cells = <2>;
|
|
||||||
#size-cells = <2>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
mmc0: mmc@11230000 {
|
|
||||||
compatible = "mediatek,mt7986-mmc",
|
|
||||||
"mediatek,mt7981-mmc";
|
|
||||||
reg = <0 0x11230000 0 0x1000>,
|
|
||||||
<0 0x11D60000 0 0x1000>;
|
|
||||||
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
clocks = <&infracfg CLK_INFRA_MSDC400>,
|
|
||||||
<&infracfg CLK_INFRA_MSDC2_HCK>,
|
|
||||||
<&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
|
|
||||||
<&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
|
|
||||||
assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
|
|
||||||
<&topckgen CLK_TOP_EMMC_400M_SEL>;
|
|
||||||
assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
|
|
||||||
<&apmixedsys CLK_APMIXED_MSDCPLL>;
|
|
||||||
clock-names = "source",
|
|
||||||
"hclk",
|
|
||||||
"axi_cg",
|
|
||||||
"ahb_cg";
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
tphy: tphy@11c50000 {
|
tphy: tphy@11c50000 {
|
||||||
compatible = "mediatek,mt7988",
|
compatible = "mediatek,mt7988",
|
||||||
"mediatek,generic-tphy-v2";
|
"mediatek,generic-tphy-v2";
|
||||||
|
|
@ -1108,6 +1007,28 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
xfi_pextp0: xfi-pextp@11f20000 {
|
||||||
|
compatible = "mediatek,mt7988-xfi-pextp",
|
||||||
|
"mediatek,mt7988-xfi-pextp_0",
|
||||||
|
"syscon";
|
||||||
|
reg = <0 0x11f20000 0 0x10000>;
|
||||||
|
#clock-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
xfi_pextp1: xfi-pextp@11f30000 {
|
||||||
|
compatible = "mediatek,mt7988-xfi-pextp",
|
||||||
|
"mediatek,mt7988-xfi-pextp_1",
|
||||||
|
"syscon";
|
||||||
|
reg = <0 0x11f30000 0 0x10000>;
|
||||||
|
#clock-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
xfi_pll: xfi-pll@11f40000 {
|
||||||
|
compatible = "mediatek,mt7988-xfi-pll", "syscon";
|
||||||
|
reg = <0 0x11f40000 0 0x1000>;
|
||||||
|
#clock-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
efuse: efuse@11f50000 {
|
efuse: efuse@11f50000 {
|
||||||
compatible = "mediatek,efuse";
|
compatible = "mediatek,efuse";
|
||||||
reg = <0 0x11f50000 0 0x1000>;
|
reg = <0 0x11f50000 0 0x1000>;
|
||||||
|
|
@ -1437,5 +1358,84 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
crypto: crypto@15600000 {
|
||||||
|
compatible = "inside-secure,safexcel-eip197b";
|
||||||
|
reg = <0 0x15600000 0 0x180000>;
|
||||||
|
interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
interrupt-names = "ring0", "ring1", "ring2", "ring3";
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
thermal-zones {
|
||||||
|
cpu_thermal: cpu-thermal {
|
||||||
|
polling-delay-passive = <1000>;
|
||||||
|
polling-delay = <1000>;
|
||||||
|
thermal-sensors = <&lvts 0>;
|
||||||
|
trips {
|
||||||
|
cpu_trip_crit: crit {
|
||||||
|
temperature = <125000>;
|
||||||
|
hysteresis = <2000>;
|
||||||
|
type = "critical";
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu_trip_hot: hot {
|
||||||
|
temperature = <120000>;
|
||||||
|
hysteresis = <2000>;
|
||||||
|
type = "hot";
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu_trip_active_high: active-high {
|
||||||
|
temperature = <115000>;
|
||||||
|
hysteresis = <2000>;
|
||||||
|
type = "active";
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu_trip_active_med: active-med {
|
||||||
|
temperature = <85000>;
|
||||||
|
hysteresis = <2000>;
|
||||||
|
type = "active";
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu_trip_active_low: active-low {
|
||||||
|
temperature = <40000>;
|
||||||
|
hysteresis = <2000>;
|
||||||
|
type = "active";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
cooling-maps {
|
||||||
|
cpu-active-high {
|
||||||
|
/* active: set fan to cooling level 2 */
|
||||||
|
cooling-device = <&fan 3 3>;
|
||||||
|
trip = <&cpu_trip_active_high>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu-active-low {
|
||||||
|
/* active: set fan to cooling level 1 */
|
||||||
|
cooling-device = <&fan 2 2>;
|
||||||
|
trip = <&cpu_trip_active_med>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu-passive {
|
||||||
|
/* passive: set fan to cooling level 0 */
|
||||||
|
cooling-device = <&fan 1 1>;
|
||||||
|
trip = <&cpu_trip_active_low>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
timer {
|
||||||
|
compatible = "arm,armv8-timer";
|
||||||
|
interrupt-parent = <&gic>;
|
||||||
|
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
||||||
|
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
||||||
|
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
||||||
|
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue